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Graphics

To: riscy@pyramid.com (Mips 3000)
Subject: Graphics
From: Bill Broadley <broadley@neurocog.lrdc.pitt.edu>
Date: Mon, 28 Jun 1993 03:16:14 -0500 (EDT)
The newest HP xterminals which were by far the fastest when they were announced
are based in i960 chip (I believe 22.5 Mhz).  I can peek inside ours if people 
are interested in the other chips inside.  As a reaction to this tektronics 
dropped the there 68030 at 20 Mhz+ 34020 at 40 Mhz (might of been the 34010) 
and used a mips 3000 + support chips.  I believe ncd dropped whatevery they 
had and went with an 88100(I think).  I think tektronics had problems getting 
both processors to work well together.  There engineers stopped out and tried
to figure out why the HP was winning by such large numbers on our benchmark.

Both the "How to write a fast xserver for a dumb frame buffer" and
"The Design of a Smart frame buffer" are good reading for those who 
are into Hardware+xserver design.

From a previus message I heard that at 40 Mhz you would get about 6 MB 
a second, where do these number come from?  Did somebody also say
that the mips could write through the tiga chip for 16 bit access to
vram?

Couldn't a TIGA chip write from vram memory to vram memory at 16 bytes every 
other cycle right? (16 bit access read, 16 bit access write).  So at 40 mhz 
they would be 20 million * 2 bytes or 40 million pixels a second no?  

Updating screen from the mips ram would be the same right? (16 bit read on
the mips, 16 bit write on tiga) a 1024x768 screen updated more then 40 times 
a second sounds great to me.  Am I missing something??? Or can the mips
not support a 32 bit read from ram every 4 th cycle (with a 16 bit
write to tiga every other cycle?)

With a C compiler for the tiga chip I think we would be able to get the
tiga working as a dumb frame buffer then gradually move more and more
of the server onto the tiga chip which would shrink the mips ram
usage, shrink the usage of mips cpu cycles, shrink the usage of mips/
Tiga memory bandwidth etc.   I'd say we would need a minimum of 512
dram on the tiga chip to make it smarter then a dumb frame buffer.

Without the TIGA chip anyone care to speculate what percentage of the
cpu would be used under different conditions?

I know of no support for any free xserver to run on the TIGA chip, I heard of
a few that were sold, but none free.  The c compiler for a reasonable cost 
seems like a great idea (I'd chip in).  I have heard of $1500 tiga boards
for pc's that run the xserver on the tiga chip.  I have a couple tiga 
boards and none of the have Xservers (if they are free where??)

I've heard bad things about alot of buffered serial chips, and that
the National Semiconductors 16550 afn was reliable.  If the NS16552 (the 2 
port version) gets good review (i.e. has few bugs) it sounds good to put 
one on everybody's motherboard.  I like this much better then a everyone 
stick whatever they have on the ISA bus.  How much more do we want
out of a serial chip then a wide range of speeds and a 12 character
buffer? (well 16 but it generates a interrupt at 12).  The more hardware
in common between mips motherboards the better remember we have a
much smaller number of people writing software in support of the mips
then the linux community has.  Maybe we should donate a motherboard
to linus !! 8-)  (I'll pitch in $40-$50 towards a linus ported linux)

-- 
Bill                                    1st>    Broadley@neurocog.lrdc.pitt.edu
Broadley@schneider3.lrdc.pitt.edu <2nd  3rd>                 Broadley+@pitt.edu
Linux is great.         Bike to live, live to bike.                      PGP-ok


 

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