riscy
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Re: The MIPs design I've been working on

To: riscy@pyramid.com
Subject: Re: The MIPs design I've been working on
From: Steven.D.Ligett@Dartmouth.EDU (Steven D. Ligett)
Date: 25 Jun 93 11:19:32 EDT
Drew Eckhardt asked some questions about the simple explanation of the design
I threw out:

(on memory system design)
1) Since normal humans can't afford the 25ns memory to run 0ws, 
we need to run with wait states (which kill performance) =8^)
Interleaving can cut the number of waitstates, but we can't do it 
if our memory is all on a single 32 bit SIMM. 

My goal is cheap.  The memory is not interleaved.  Both cpus share the ram,
but the 3041 is expected to run its little DMA code out of cache most of the
time.  Also, the Vram is on the same bus.  cheap.

(really Vram?)
2) Are you talking VRAM, or DRAM?  The former is inherently dual 
ported, and keeps the video hardware from eating over half our memory
bandwidth.  If we're using the later, how have you isolated it from the 
main bus? 

Vram SIMMs.  All current Macs use them - giving us low cost, and availability
due to volume, and availability.  cheap.

(on the Philips (signetics) Uart)
3) I'm not familiar with this chip.  How big are the buffers (very important
if it's entirely interrupt driven),  and will it interface with a DMA 
controller?

Quad uart.  52 pin plcc.  8 byte fifos for each channel's receive and xmit
channels.  I mean, 8 for each receive, and 8 for each xmit.  Programmable
fifo interrupt thresholds.  (One instruction on the 3041 will read/write 4
bytes.)  Four pins per channel for modem controls.  Biggest lack - arbitrary
baud rates.  There are six sets of baud rates, and pairs of channels share
sets of rates.  Within a pair, any xmitter or xrcvr can have any rate from
the set.  $24.  cheap.

(on the I/O bus)
4) A propriety 8-bit bus is a neat idea - we get some breathing room for 
second ethernet boards, etc, but don't have to jump through hoops doing
ISA compatability.

Along these lines, another thing that may be worth considering to satisfy
the anti-ethernet/uart/etc minimalists would be including sockets, address
decoding, and glue for these parts but leaving the sockets empty on one 
set of boards.

Aside from the scsi, and one or two quad uarts, I don't see putting much I/O
on the board.  An RTC/eeprom.  I'd have to be convinced that ethernet needs
to be on the motherboard.  The I/O bus is JUST for I/O I don't have my notes
with me, but it's 8 data lines, a small number of address lines, +12, +5,
-12, grounds, clock, and some handshake lines.  Each slot is decoded into a
separate address block.  That is, the handshake lines aren't bussed - they're
decoded.

(on the video)
5) Is the TI 34076 whatever a CRT controller and a RAM DAC (ie pallette
chip)?
If it's the later, what are you driving it with?

It's a ramdac - the NSC timing chip controls - well, it controls the timing! 
:-)  An 80 mhz clock would drive the pixels (1024x768), and provide the
processor clocks as well.  Would have space for other oscillators on the
board.  I'll dig up the NSC chip info.  The 34076 does the ordinary 1, 2, 4,
or 8 to 24 bit table lookups.


 

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