riscy
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Re: The MIPs design I've been working on

To: riscy@pyramid.com, Steven.D.Ligett@dartmouth.edu (Steven D. Ligett)
Subject: Re: The MIPs design I've been working on
From: Drew Eckhardt <drew@caesar.cs.Colorado.EDU>
Date: Fri, 25 Jun 1993 08:48:32 -0600
In-reply-to: Your message of "25 Jun 1993 09:17:15 EDT." <5264379@prancer.Dartmouth.EDU>

    I've been noodling along on a design for a MIPS box based on the IDT chips
    for the past two years.  Some folks ideas here have been along the same
    lines, what with serial I/O processors, etc., so I'll outline where my desi
   gn
    is.  Any details are subject to change, of course.  Let me first draw a
    simple picture.
    
       +-----+     +-----+     +-----+
       | 3081|     | RAM |     |     |     
       | or  |<--->| and |<--->| 3041|     
       | 3051|     | VRAM|     |     |
       +-----+     +-----+     +-----+
                      |           |
                   +-----+     +-----+
                   |RAM- |     | I/O |     
                   | DAC |     | and |     
                   |     |     |EPROM|
                   +-----+     +-----+
    
    The main cpu is a 3051 @ 20 mhz or a 3081 @ 40 mhz.  The main cpu is
    connected ONLY to the RAM and VRAM.  Three 72-pin SIMMs for the RAM (up to 
   96
    MB, if you can afford 32 MB SIMMs).  

Since normal humans can't afford the 25ns memory to run 0ws, 
we need to run with wait states (which kill performance) =8^)
Interleaving can cut the number of waitstates, but we can't do it 
if our memory is all on a single 32 bit SIMM. 

    VRAM composed of Mac compatible SIMMs;
    either 512 KB or 1 MB.

Are you talking VRAM, or DRAM?  The former is inherently dual 
ported, and keeps the video hardware from eating over half our memory
bandwidth.  If we're using the later, how have you isolated it from the 
main bus? 
    
    All the I/O goes through the 3041 @ 20 mhz.  Basically, the 3041 is a smart
    DMA controller for the 3081.  There's a 53c94 SCSI chip on a 16-bit bus, so
   me
    26c94 quad uarts on an 8-bit bus

I'm not familiar with this chip.  How big are the buffers (very important
if it's entirely interrupt driven),  and will it interface with a DMA 
controller?

  one boot eprom on the 8-bit bus, and some
    slots.  The slots are a simple 8-bit bus, 36 pins, giving up to about
    10MB/sec off the 3041.  

A propriety 8-bit bus is a neat idea - we get some breathing room for 
second ethernet boards, etc, but don't have to jump through hoops doing
ISA compatability.

Along these lines, another thing that may be worth considering to satisfy
the anti-ethernet/uart/etc minimalists would be including sockets, address
decoding, and glue for these parts but leaving the sockets empty on one 
set of boards.
    
    The RAMDAC is in the TI 34076 family, which cost from $15 on up, depending 
   on
    speed, features, etc.  Timing is handled by a NSC chip whose number escapes
    me at the moment.

Is the TI 34076 whatever a CRT controller and a RAM DAC (ie pallette chip)?
If it's the later, what are you driving it with?

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