I've been noodling along on a design for a MIPS box based on the IDT chips
for the past two years. Some folks ideas here have been along the same
lines, what with serial I/O processors, etc., so I'll outline where my design
is. Any details are subject to change, of course. Let me first draw a
simple picture.
+-----+ +-----+ +-----+
| 3081| | RAM | | |
| or |<--->| and |<--->| 3041|
| 3051| | VRAM| | |
+-----+ +-----+ +-----+
| |
+-----+ +-----+
|RAM- | | I/O |
| DAC | | and |
| | |EPROM|
+-----+ +-----+
The main cpu is a 3051 @ 20 mhz or a 3081 @ 40 mhz. The main cpu is
connected ONLY to the RAM and VRAM. Three 72-pin SIMMs for the RAM (up to 96
MB, if you can afford 32 MB SIMMs). VRAM composed of Mac compatible SIMMs;
either 512 KB or 1 MB.
All the I/O goes through the 3041 @ 20 mhz. Basically, the 3041 is a smart
DMA controller for the 3081. There's a 53c94 SCSI chip on a 16-bit bus, some
26c94 quad uarts on an 8-bit bus, one boot eprom on the 8-bit bus, and some
slots. The slots are a simple 8-bit bus, 36 pins, giving up to about
10MB/sec off the 3041. The 3041 invisibly (to the software) handles 8, 16,
and 32 bits tranfers.
The RAMDAC is in the TI 34076 family, which cost from $15 on up, depending on
speed, features, etc. Timing is handled by a NSC chip whose number escapes
me at the moment.
|