riscy
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Re: Long ramblings about project design

To: riscy@pyramid.com, Bill Broadley <broadley@neurocog.lrdc.pitt.edu>
Subject: Re: Long ramblings about project design
From: Drew Eckhardt <drew@caesar.cs.Colorado.EDU>
Date: Fri, 25 Jun 1993 04:32:37 -0600
In-reply-to: Your message of "Fri, 25 Jun 1993 04:47:56 CDT." <9306250848.AA21198@gossip.pyramid.com>
    The minimal cost solution would a cpu+ram on a ISA slow, but this seems of 
    little utility and would be quite ISA limited.  I'd guess the cost would 
    be around $150-$200 above the cost of the cpu?

Might not be possible - there isn't a lot of realestate available on an 
ISA board.

    Despite ISA's bad reputation it handles up to 4-5 MB a second which, despit
   e 
    the advertising, is enough for most users bus needs with the possible excep
   tion
    of high resolution video.  

Possible isn't quite strong enough.

    I believe that VESA support is almost free (simple bus) is this true?
    Are non-surface mounted chips available?  A fairly high end VESA local
    bus S3 805 can be had for less then $200 (+ cost of supporting vesa).

Another poster suggested that  TI32010 can be had for $20, add
cost of the RAMDAC + either DRAM (about $20/meg) or VRAM (two-three times 
DRAM price).

    I see VESA as the only possibility for future expansion, because EISA
    is to expensive ??  Vesa nicely  maxes out at 40 Mhz to ;-)

Nasty timing problems acompany any high speed bus, and since we aren't 
Pee-Cee compatable VESA might not be that easy.
    
    Apparently the TI34020 is a fairly powerful chip (used in xterminals from 
    tektronics, and high end (> $1k) video cards.  I know of no free drivers an
   d 
    I suspect that they would be quite involved to write them (I believe I've s
   een 
    entire X11 servers running on them, which would be WAY cool.)  I am suprise
   d 
    they are cheap and would volunter to attempt an X11 driver for that chip.  

    But writing a X11 server for a TMS34020 is beyond me, as oppsed to a driver
    
    which I think I could get to work.  Am I thinking of the correct chip here?

You can allways use just a minimal amount of intelligence, ie treating
it as a dumb frame buffer if possible, or just doing bitblts with it until 
you get arround to doing a "propper" driver..
    
    Apparently a SCSI buss is pretty cheap (Did I hear $5.00?) 

That's where your SCSI chips start at.  

    I'd suggest SCSI-II 5 MB/sec as a minimum

With the exception of arbitration, it's entirely a software 
issue (and most SCSI-I systems implement arbitration).$

 (scsi-II is supposed to be "defined" then
    scsi-I so hopefully less compatibility problems).  No need for more
    speed really (most drives can handle max 1.0-1.5 MB/sec real world).

Most new drives are some what faster than this - if we assume 64 
sectors/track (not atypical), and a rotational speed of 3600RPM - 
that's 1920K/sec.  Better drives will spin at 5400 RPM, which
would be 2880K/sec.  

However, there's nothing stopping you from having multiple 
nexuses established to multiple devices at the same time,
in which case every device needs to be able to burst at 
a speed greater than the combined total of their sustained
transfer rates.  Add in command overhead when data isn't 
being transfered and it adds up quickly..
    
    How many people who want a mips have ethernet?  I don't. Why not 
    standardize on say a WD8013? It has a 32 k cache or so and ethernet is a 
    MAX 10 megabit, or 1.25 MB which the ISA should handle fine (especially sin
   ce 
    we have fast int cpu).  

   Remeber disk, and video are already on a different 
   bus.
    (Either VESA or native) Is it cheaper to do it on board? 

Yes, since this is a non-profit project, and your-not-top-of-the-line
ether, video, etc chips are cheap, your address decoding is on the same 
PAL as something else on the motherboard, and the price of your glue is 
negligible.

I'll call the national semi distributor again and get the pricing on
the 8390 (this is what the 8013 uses, unlike the proposed ~450K/sec 
AMD lance, it is allegedly a 1M/sec chip, and it is available in a 
PLCC package), and 8391 (transciever) (thinnet).

    I know it hurts to have a board without slots, but the ISA is limiting enou
   gh 
    so anything new and hot won't be happy in a ISA slot anyways. 

I'm begining to wonder about the need for the ISA bus - 

Pros : we can put nifty things like ROM burners in the ISA slots, and
        parallel printer/floppy controllers.

Cons :  the ISA slots take up lots of realestate (not just 
        for the connector - we could have clearance problems with 
        heat sinked chipps and SIMMs)

        Interfacing the ISA bus to the MIPs could be complicated,
        since the existing bus interface chips are designed to 
        mate up with x86 CPUs, etc.

How hard would it be to put a floppy controller and parallel port on
the mainboard compared to putting in a full ISA bus?
    
    Oh yeah why so many sim slots?  I have hit the limit at 8 slots
    (with 8 MB) and then upgraded to 16 MB in 4 slots.  I can see 16 slots
    but why more? 16 MB is around $400 anyone planning to spend more then
    $1600/64 MB for a mips machine running a linux derivative without a second
    level cache?

Memory interleaving.  You use more, smaller chips so that you can 
interleave memory accesses to them, cutting wait states by a factor 
of two for two-way for sequential accesses on a cache miss, four 
by four-way.  In order two take advantage of interleaving,
you need to fill two or four banks at a time.  

Hmm - I know our chipset supports 2-way interleave, does it support 
way?  And what about page mode?  
    
    Anyone have any idea how much money/board design is saved by the "integrati
   on"
    of the 3051/3052 and 3081?  I.e. how much hard would it be to put in a chip
    
    that lacks such integration?  I.e. say I call motorolla tomorrow any they s
   ay 
    we will ship some prerelease derated 40 Mhz (from 50 Mhz) powerpc chips for
    $200
    a piece.  What would the cost of using a standard nonintegrated chip over a
    
    integrated/embedded chip?  I believe the price of the powerpc is expected
    to be $320 or so for 50 Mhz (to fast but would probably work at 40), and
    $400 at 66 Mhz.

Wow! a volunteer to do the GNU ports of GCC and GDB to the PowerPC =8^)

We'd also need support chips (availability and cost?), and would have to
work arround hardware bugs in the chip (ie, early 386's that didn't 
run in protected mode, the 68040 with broken transcendental functions,
etc).

Since we have the tools, the SPARC might be worth looking at.
    
    Hmm another bossibiliy is a cheap non fpu processor that has bus snooping,
    I think the 486 sx fits the description.  This probably isn't feaible 
    and besides it's a INTEL chip (yuck)

The solution we're looking at right now would be competitive with a 
486DX2-66 in terms of both price (I can get a 486DX2-66/64K secondary 
cache VESA local bus mainboard for $610 (Of course, this doesn't include 
video (say $150), SCSI (say $200), ethernet ($80), 16550's, etc)) and 
performance (integer performance is very comparable, floating point 
is as much as 5X as much).  

I really like it, especially now that I've quit DOS!
    
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