From miles@cogsci.edinburgh.ac.uk Fri Nov 5 14:15:08 1993 Received: from sun2.nsfnet-relay.ac.uk by SunSITE.unc.edu (SMI4.1/FvK 1.02) id AA24884; Fri, 5 Nov 93 14:15:08 EST Via: uk.ac.edinburgh.cogsci; Fri, 5 Nov 1993 10:24:48 +0000 Date: Thu, 4 Nov 93 14:29:12 GMT Message-Id: <2379.9311041429@oliphant.cogsci.ed.ac.uk> From: Miles Bader To: riscy@sunsite.unc.edu In-Reply-To: <9310200601.AA09278@gossip.pyramid.com> References: <9310200601.AA09278@gossip.pyramid.com> Subject: R4200 price Blat: Foop Bill Broadley writes: > We won't be able to get the 4200 at anywhere near $75 from what I heard, > more like $250. I guess y'all have probably seen this (I was apparently cut off the mailing list when it moved to the new site so I haven't gotten anything for a while), but: machale@royalty.mti.sgi.com (James MacHale) writes in comp.arch: > On October 18th NEC Electronics announced VR4200 samples available > immediately. Samples were priced at approximately $80. Mass > production scheduled for calendar Q.2 94. How this price relates to the eventual price I don't know... [I seem to recall hearing that the target price for the 4200 was something absurd like $12... Connection to reality: unknown] -Miles -- Miles Bader - HCRC, U of Edinburgh - miles@cogsci.ed.ac.uk, +44 31 650-4439 Is it true that nothing can be known? If so how do we know this? --Woody Allen From glowell@crl.com Sat Nov 6 20:10:35 1993 Received: from crl.crl.com (crl.com) by SunSITE.unc.edu (SMI4.1/FvK 1.02) id AA17674; Sat, 6 Nov 93 20:10:35 EST Received: by crl.crl.com id AA22655 (5.65c/IDA-1.5 for riscy@sunsite.unc.edu); Sat, 6 Nov 1993 17:10:10 -0800 From: Gary Lowell Message-Id: <199311070110.AA22655@crl.crl.com> Subject: Re: R4200 price To: riscy@sunsite.unc.edu Date: Sat, 6 Nov 1993 17:10:10 -0800 (PST) In-Reply-To: <2379.9311041429@oliphant.cogsci.ed.ac.uk> from "Miles Bader" at Nov 5, 93 04:55:56 pm X-Mailer: ELM [version 2.4 PL23] Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 472 In the 1 November Computer Reseller News there is a press release from NEC that confirms the $80 price, and mentions that the price is expected to drop to $50 by mid-1994. I belive that this is the chip that is planned for use in the new Nitendo game box which is supposed to retail for around $200. Toshiba has also announced their R4600 processor, which I believe is a varient of the R4200. Cheers, Gary Lowell Home: glowell@crl.com Work: glowell@thorn.wpd.sgi.com From broadley@neurocog.lrdc.pitt.edu Fri Nov 12 11:08:50 1993 Received: from neurocog.lrdc.pitt.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA19194; Fri, 12 Nov 1993 16:08:51 -0500 Received: from localhost (broadley@localhost) by neurocog.lrdc.pitt.edu (8.6.4/8.6.4) id QAA02054 for riscy@sunsite.unc.edu; Fri, 12 Nov 1993 16:08:50 -0500 From: Bill Broadley Message-Id: <199311122108.QAA02054@neurocog.lrdc.pitt.edu> Subject: Dead? Mips info. To: riscy@sunsite.unc.edu Date: Fri, 12 Nov 1993 16:08:50 -0500 (EST) X-Mailer: ELM [version 2.4 PL21] Content-Type: text Content-Length: 1797 Hello there any progress?? Is riscy dead? I certainly hope not! The computer world is moving forward and I'm doing my best not to spend another penny on my x86 system, so I can afford a riscy board. Sunsite apparently has the list misconfigured for awhile after they patched the sendmail bug, hopefully this should be fixed now. Anyways sgigate.sgi.com has opened for ftp a bunch of informative docs on the 4000, 4200, 4400, and TFP chips, all under /pub/docs I believe. I read up on the 4200 seems like an ideal chip for us: 55 specint 30 specfp (about twice 486-66). Pin compatible with 4000 PC 16k/8K (I/D) cache direct mapped (can read both per cycle at 64 bits wide) 5 stage pipeline (vs 4[04]00 8 stage) Lots of neat low power stuff (1.5 watts at 80 Mhz, .4 w at 20Mhz, 0 at 0 Mhz) no L2 support (I wonder if the spec numbers are for a cacheless machine) I hear they are sampling now at under $100. If you want all the nitty gritty details grab the file R4200_Prod_Overview.ps. BTW I've seen VERY few msg's since the list moved to sunsite (like about 5), if thats off please let me know and I'll try to fix things. Nothing official announced (that I know of), but I believe the 4600 will be more expensive and have twice the fp (about the same int), seems like the 4200 is still best for the riscy board. -- Bill 1st> Broadley@neurocog.lrdc.pitt.edu Broadley@schneider3.lrdc.pitt.edu <2nd 3rd> Broadley+@pitt.edu Linux is great. Bike to live, live to bike. PGP-ok --JAA26791.753116189/neurocog.lrdc.pitt.edu-- -- Bill 1st> Broadley@neurocog.lrdc.pitt.edu Broadley@schneider3.lrdc.pitt.edu <2nd 3rd> Broadley+@pitt.edu Linux is great. Bike to live, live to bike. PGP-ok From ses@tipper.oit.unc.edu Fri Nov 12 11:42:49 1993 Received: from tipper.oit.unc.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA23620; Fri, 12 Nov 1993 16:42:51 -0500 Received: from localhost.oit.unc.edu by tipper.oit.unc.edu (SMI4.1/FvK 1.02) id AA10275; Fri, 12 Nov 93 16:42:49 EST Message-Id: <9311122142.AA10275@tipper.oit.unc.edu> To: riscy@sunsite.unc.edu Subject: Re: Dead? Mips info. In-Reply-To: Your message of "Fri, 12 Nov 93 16:15:25 EST." <199311122108.QAA02054@neurocog.lrdc.pitt.edu> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Fri, 12 Nov 93 16:42:49 -0500 From: Simon E Spero Sendmail has been brow-beaten into submission now, and ricy seems to be fine. Do not meddle in the affairs of mailers, for the are subtle, and quick to coredump. From af4@ukc.ac.uk Fri Nov 12 23:25:03 1993 Received: from mercury.ukc.ac.uk by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA05752; Fri, 12 Nov 1993 18:32:47 -0500 Message-Id: <199311122332.AA05752@SunSITE.Unc.EDU> Received: from eagle by mercury.ukc.ac.uk with UKC POP3+ id aa03234; 12 Nov 93 23:28 GMT Date: Fri, 12 Nov 93 23:25:03 +0000 From: Fwuffy To: riscy@sunsite.unc.edu Subject: riscy status? The list has been dead for sometime. Would anybody care to summarise on what chips (if any) we have definitely decided on? Decisions need to be made if we are ever to get out of the vapourware phase... From broadley@neurocog.lrdc.pitt.edu Fri Nov 12 14:26:39 1993 Received: from neurocog.lrdc.pitt.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA09951; Fri, 12 Nov 1993 19:26:40 -0500 Received: from localhost (broadley@localhost) by neurocog.lrdc.pitt.edu (8.6.4/8.6.4) id TAA04577 for riscy@SunSITE.Unc.EDU; Fri, 12 Nov 1993 19:26:39 -0500 From: Bill Broadley Message-Id: <199311130026.TAA04577@neurocog.lrdc.pitt.edu> Subject: Re: riscy status? To: riscy@SunSITE.Unc.EDU Date: Fri, 12 Nov 1993 19:26:39 -0500 (EST) In-Reply-To: <199311122332.AA05752@SunSITE.Unc.EDU> from "Fwuffy" at Nov 12, 93 06:35:14 pm X-Mailer: ELM [version 2.4 PL21] Content-Type: text Content-Length: 506 > > > The list has been dead for sometime. Would anybody care to summarise on > what chips (if any) we have definitely decided on? Decisions need to be > made if we are ever to get out of the vapourware phase... > Basically a mip 4k derivative. Based on the latest info I'd say an mips 4200. -- Bill 1st> Broadley@neurocog.lrdc.pitt.edu Broadley@schneider3.lrdc.pitt.edu <2nd 3rd> Broadley+@pitt.edu Linux is great. Bike to live, live to bike. PGP-ok From ksh@charybdis.prl.ufl.edu Sat Nov 13 09:23:44 1993 Received: from charybdis.prl.ufl.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA07329; Sat, 13 Nov 1993 14:22:29 -0500 Received: by charybdis.prl.ufl.edu (4.1/1.34) id AA12725; Sat, 13 Nov 93 14:23:44 EST Date: Sat, 13 Nov 93 14:23:44 EST From: ksh@charybdis.prl.ufl.edu (Kevin S Ho) Message-Id: <9311131923.AA12725@charybdis.prl.ufl.edu> To: riscy@sunsite.unc.edu Subject: Re: riscy status? I would disagree. I believe that, although the 4600 is more expensive, the CPU is the hardest part to upgrade. The extra FLOPS would make a difference. KsH From broadley@neurocog.lrdc.pitt.edu Sat Nov 13 09:32:42 1993 Received: from neurocog.lrdc.pitt.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA08152; Sat, 13 Nov 1993 14:32:44 -0500 Received: from localhost (broadley@localhost) by neurocog.lrdc.pitt.edu (8.6.4/8.6.4) id OAA17640 for riscy@SunSITE.Unc.EDU; Sat, 13 Nov 1993 14:32:43 -0500 From: Bill Broadley Message-Id: <199311131932.OAA17640@neurocog.lrdc.pitt.edu> Subject: Re: riscy status? To: riscy@SunSITE.Unc.EDU Date: Sat, 13 Nov 1993 14:32:42 -0500 (EST) In-Reply-To: <9311131923.AA12725@charybdis.prl.ufl.edu> from "Kevin S Ho" at Nov 13, 93 02:25:55 pm X-Mailer: ELM [version 2.4 PL21] Content-Type: text Content-Length: 767 > > I would disagree. I believe that, although the 4600 is more expensive, > the CPU is the hardest part to upgrade. The extra FLOPS would make a > difference. > > KsH > >From what I hear the 4600 is 60 specint, and 60 specfp +/-, not pin compatible, and won't be shipping till late next summer. The 4200 is 55 specint 30 specfp, is sampling now, is pin compatible. I think unless we want to design our own mothebroard AND wait till next summer the 4200 is the way to go. If ya want to upgrade the pc get the 4400 or 4000 pin compatible upgrade. -- Bill 1st> Broadley@neurocog.lrdc.pitt.edu Broadley@schneider3.lrdc.pitt.edu <2nd 3rd> Broadley+@pitt.edu Linux is great. Bike to live, live to bike. PGP-ok From andy@waldorf-gmbh.de Mon Nov 15 09:46:07 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA26558; Mon, 15 Nov 1993 02:49:50 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id HH04265; Mon, 15 Nov 1993 08:47:07 +0100 Received: from resi From: Andreas Busse Date: Mon, 15 Nov 93 08:46:07 +0100 Message-Id: <9311150746.AA20914@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA20914; Mon, 15 Nov 93 08:46:07 +0100 To: riscy@sunsite.unc.edu Subject: News Hi there ! After riscy seems to work again, I can post what always bounced for several days: ------------------ Hi Mipsers, I've got some news regarding the NEC/MTI riscWS/EISA design. By accident, someone at SGI/MTI US joined a Waldorf-specific mailing list. What a luck, he has to do with the board designs ! I asked him for detailed information incl. part lists. This is what he wrote: > Hi Andy, > > I received your message and will try to send you some information very > soon. Unfortunately, for the next 2-3 days things are very tight since > we are trying to build machines and demos for Comdex. I will very much > appreciate if you gave me until Mon-Tue next week to pull this together > and send it to you. I hope this is okay with you. > > Thanks a lot and best regards > [name deleted] > > P.S. - very briefly the riscWS/EISA kit is available from NEC (we used > to distribute it but handed over the responsibility to NEC recently) > It includes all board level design information that you mentioned in > your mail plus binaries of all s/w. To get the sources you may have > to another agreement (not a big deal). The cost is nominal - $3500 > or $5000 per kit. > > Magnum PC is basically the same design. > > ..... more later. Go and have a look at the Comdex ! Cheers, Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From ronald@osf.uci.kun.nl Mon Nov 15 11:58:42 1993 Received: from osf.uci.kun.nl by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA01994; Mon, 15 Nov 1993 05:01:53 -0500 Received: by osf.uci.kun.nl (5.65c/1.34) id AA05420; Mon, 15 Nov 1993 10:58:43 +0100 From: ronald@osf.uci.kun.nl (Ronald Schalk) Message-Id: <199311150958.AA05420@osf.uci.kun.nl> Subject: Re: riscy status To: riscy@sunsite.unc.edu (project riscy) Date: Mon, 15 Nov 1993 10:58:42 +0100 (MET) X-Mailer: ELM [version 2.4 PL21] Content-Type: text Content-Length: 1306 > The 4200 is 55 specint 30 specfp, is sampling now, is pin compatible. > > I think unless we want to design our own mothebroard AND wait till > next summer the 4200 is the way to go. I completely agree, the 4200 will be the chip in the next-generation Nintendo games. I heard this from the technical director from MIPS Europe himself. This means that the chip will be dirt-cheap in the future. Well 80 bucks is IMHO already very cheap. > > If ya want to upgrade the pc get the 4400 or 4000 pin compatible upgrade. > On a sideline: how difficult will it be to make some kind of daughtercard? Dec just announced such a beast, it'll work with 486,586 (oh sorry pentium) and (in the future) Alpha. I don't know what's on the daughtercard, but I guess the cache and bios is on it, and of course some glue. Ronald ******************************************************************** * ing. Ronald Schalk, afdeling CS, sectie COOS * * Universitair Centrum Informatievoorziening (UCI) * * University of Nijmegen (KUN) snailmail: Geert Grooteplein 41 * * e-mail : R.Schalk@uci.kun.nl 6525 GA Nijmegen * * tel: +31 80 617997 fax: +31 80 617979 The Netherlands * ******************************************************************** From amoss@cs.huji.ac.il Mon Nov 15 14:20:54 1993 Received: from cs.huji.ac.il by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA02750; Mon, 15 Nov 1993 05:20:59 -0500 Received: from picton.cs.huji.ac.il by cs.huji.ac.il with SMTP id AA27391 (5.65c/HUJI 4.144 for riscy@sunsite.unc.edu); Mon, 15 Nov 1993 12:20:55 +0200 Received: from localhost by picton.cs.huji.ac.il with SMTP id AA05584 (5.65c/HUJI 4.1 for riscy@sunsite.unc.edu); Mon, 15 Nov 1993 12:20:54 +0200 Message-Id: <199311151020.AA05584@picton.cs.huji.ac.il> To: riscy@sunsite.unc.edu Subject: Re: riscy status In-Reply-To: Your message of Mon, 15 Nov 1993 05:03:24 -0500 . <199311150958.AA05420@osf.uci.kun.nl> From: Amos Shapira Date: Mon, 15 Nov 1993 12:20:54 +0200 Sender: amoss@CS.HUJI.AC.IL ronald@osf.uci.kun.nl (Ronald Schalk) writes: |> If ya want to upgrade the pc get the 4400 or 4000 pin compatible upgrade. |> | |On a sideline: how difficult will it be to make some kind of daughtercard? |Dec just announced such a beast, it'll work with 486,586 (oh sorry pentium) |and (in the future) Alpha. I don't know what's on the daughtercard, but I |guess the cache and bios is on it, and of course some glue. If it's relevant - SGI's Indy is coming with doughter cards so you can change between R4000PC/R4000SC or any other card which might come out in the future. Could the technician from SGI/MTI (?) teach us about this option? On a second though, adding a doughter card must be going to rise the cost and time to design significally, isn't it? All in all - the last message from Wuldorf sounds very encouraging. I just hope we won't go again into the R4200 vs. ???? debate again and catch this opporunity while it is valid. Cheers, --Amos --Amos Shapira (Jumper Extraordinaire) | "Of course Australia was marked for C.S. System Group, Hebrew University, | glory, for its people had been chosen Jerusalem 91904, ISRAEL | by the finest judges in England." amoss@cs.huji.ac.il | -- Anonymous From drew@kinglear.cs.Colorado.EDU Mon Nov 15 15:03:19 1993 Received: from kinglear.cs.colorado.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA15861; Tue, 16 Nov 1993 00:03:22 -0500 Received: from localhost (localhost [127.0.0.1]) by kinglear.cs.Colorado.EDU (8.6.4/8.6.4) with SMTP id WAA02352 for ; Mon, 15 Nov 1993 22:03:20 -0700 Message-Id: <199311160503.WAA02352@kinglear.cs.Colorado.EDU> X-Authentication-Warning: kinglear.cs.Colorado.EDU: Host localhost didn't use HELO protocol To: riscy@sunsite.unc.edu Subject: Re: riscy status In-Reply-To: Your message of "Mon, 15 Nov 1993 05:21:13 EST." <199311151020.AA05584@picton.cs.huji.ac.il> Date: Mon, 15 Nov 1993 22:03:19 -0700 From: Drew Eckhardt On a second though, adding a doughter card must be going to rise the cost and time to design significally, isn't it? No. The signals on the SC and PC chips (with the exception of interrupt levels > the first one) are 100% compatable, so you can go with the standard 179 pin PGA on the main board. 4000PC, 4200PC, and 4400PC chips are plug compatable, change them, the crystal, and setup for the serially loaded boot data which determines the clock divisor and access pattern for the memory interface. For the MC/SC series chips or a surface mount 4200, you can go with a daughter card that routes the pins to the right place, just like AMD does with their 386 chips, HP did with the 9000/400's which could take either a 68040 or 68030 + 68882, etc. From atk@agua.colorado.edu Tue Nov 16 00:42:30 1993 Received: from boulder.Colorado.EDU by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA13778; Tue, 16 Nov 1993 09:42:00 -0500 Received: from agua.Colorado.EDU by boulder.Colorado.EDU with SMTP id AA21548 (5.65c/IDA-1.4.4 for ); Tue, 16 Nov 1993 07:41:56 -0700 Received: by agua.colorado.edu (cu.generic.890828) Date: Tue, 16 Nov 93 07:42:30 MST From: Alan Krantz Message-Id: <9311161442.AA00362@agua.colorado.edu> To: riscy@sunsite.unc.edu Subject: Re: riscy status This is not really a topic of this newsgroup but i was talking to a friend and he said netbsd had shared libraries - anyways anyone have any quick comments on pros/cons of linux vs netbsd ? atk From andy@waldorf-gmbh.de Tue Nov 16 17:04:56 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA16081; Tue, 16 Nov 1993 10:11:19 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id JA05284; Tue, 16 Nov 1993 16:08:31 +0100 Received: from resi From: Andreas Busse Date: Tue, 16 Nov 93 16:04:56 +0100 Message-Id: <9311161504.AA23992@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA23992; Tue, 16 Nov 93 16:04:56 +0100 To: riscy@sunsite.unc.edu Subject: Receiving multiple copies Please, can someone check if I am on the list more than once ? I always get two copies of the same message. Thanks, Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From tthorn@daimi.aau.dk Tue Nov 16 17:14:34 1993 Received: from avignon.daimi.aau.dk by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA16334; Tue, 16 Nov 1993 10:14:37 -0500 Received: by avignon.daimi.aau.dk id AA22032 (5.65c8/IDA-1.4.4 for riscy@sunsite.unc.edu); Tue, 16 Nov 1993 16:14:34 +0100 Date: Tue, 16 Nov 1993 16:14:34 +0100 From: Tommy Thorn Message-Id: <199311161514.AA22032@avignon.daimi.aau.dk> To: riscy@sunsite.unc.edu Subject: Re: riscy status References: <9311161442.AA00362@agua.colorado.edu> Reply-To: Tommy.Thorn@daimi.aau.dk Alan Krantz writes: > This is not really a topic of this newsgroup but i was talking to a friend ^^^^^^^^^ This is *NOT*, repeat, *NOT* a newsgroup! This is a mailing list! > and he said netbsd had shared libraries - anyways anyone have any quick ..and so has Linux.. > comments on pros/cons of linux vs netbsd ? > > atk NO NO NO NO NO!! PLEASE, take this discussion elsewhere, like alt.fan.linux or alt.fan.netbsd. We have enough noice here. -- Tommy.Thorn@daimi.aau.dk Staff-programmer Aarhus University, Ny Munkegade 116 Phone: +45 89423223 DK-8000 Aarhus C, Denmark. Fax: +45 86135725 PGP Public Key fingerprint: E7B1175FC30D9E96B67AF61D89A70A1F From amoss@cs.huji.ac.il Tue Nov 16 19:54:17 1993 Received: from cs.huji.ac.il by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA19942; Tue, 16 Nov 1993 10:54:29 -0500 Received: from joker.cs.huji.ac.il by cs.huji.ac.il with SMTP id AA21226 (5.65c/HUJI 4.144 for riscy@sunsite.unc.edu); Tue, 16 Nov 1993 17:54:18 +0200 Received: from localhost by joker.cs.huji.ac.il with SMTP id AA02141 (5.65c/HUJI 4.1 for riscy@sunsite.unc.edu); Tue, 16 Nov 1993 17:54:17 +0200 Message-Id: <199311161554.AA02141@joker.cs.huji.ac.il> To: riscy@sunsite.unc.edu Subject: Re: riscy status In-Reply-To: Your message of Tue, 16 Nov 1993 09:47:57 -0500 . <9311161442.AA00362@agua.colorado.edu> From: Amos Shapira Date: Tue, 16 Nov 1993 17:54:17 +0200 Sender: amoss@CS.HUJI.AC.IL Alan Krantz writes: |This is not really a topic of this newsgroup but i was talking to a friend |and he said netbsd had shared libraries - anyways anyone have any quick |comments on pros/cons of linux vs netbsd ? | |atk I think this IS a topic for this group. It was raised here quite a while ago but I can't remember what was the conclusion. Anyone care to sumrise the previous discussion? Cheers, --Amos --Amos Shapira (Jumper Extraordinaire) | "War does not determine who is right, C.S. System Group, Hebrew University, | but who is left" Jerusalem 91904, ISRAEL | amoss@cs.huji.ac.il | -- Anonymous? From broadley@neurocog.lrdc.pitt.edu Tue Nov 16 07:04:54 1993 Received: from neurocog.lrdc.pitt.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA27284; Tue, 16 Nov 1993 12:04:58 -0500 Received: from localhost (broadley@localhost) by neurocog.lrdc.pitt.edu (8.6.4/8.6.4) id MAA07311 for riscy@SunSITE.Unc.EDU; Tue, 16 Nov 1993 12:04:54 -0500 From: Bill Broadley Message-Id: <199311161704.MAA07311@neurocog.lrdc.pitt.edu> Subject: Re: riscy status To: riscy@SunSITE.Unc.EDU Date: Tue, 16 Nov 1993 12:04:54 -0500 (EST) In-Reply-To: <199311161554.AA02141@joker.cs.huji.ac.il> from "Amos Shapira" at Nov 16, 93 10:58:44 am X-Mailer: ELM [version 2.4 PL21] Content-Type: text Content-Length: 1047 > I think this IS a topic for this group. It was raised here quite a while ago > but I can't remember what was the conclusion. Anyone care to sumrise the > previous discussion? > > Cheers, > I don't see any harm in discussing it, not like anything else is happening except waiting. Keep in mind for the very small userbase involved in riscy that we must have a unified effort to get ANYTHING running. For us to have a reasonable chance of success we must first get whatever is easiest/fastest etc ported. Then worry about alternatives. >From people who have spent much more time inside kernels and device drivers say that linux would be the easiest/fastest and thats good enough for me. I personally find that strange since I believe bsd already runs on a few mips machines, but can accept that, besides linux is a cool unix. -- Bill 1st> Broadley@neurocog.lrdc.pitt.edu Broadley@schneider3.lrdc.pitt.edu <2nd 3rd> Broadley+@pitt.edu Linux is great. Bike to live, live to bike. PGP-ok From miles@cogsci.edinburgh.ac.uk Thu Nov 18 12:35:12 1993 Received: from sun2.nsfnet-relay.ac.uk by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA03181; Thu, 18 Nov 1993 08:26:17 -0500 Via: uk.ac.edinburgh.cogsci; Thu, 18 Nov 1993 12:35:17 +0000 Date: Thu, 18 Nov 93 12:35:12 GMT Message-Id: <6682.9311181235@oliphant.cogsci.ed.ac.uk> From: Miles Bader To: riscy Subject: [...sgi.announce: Low Cost, High Performance Microprocessor Now Shipping; Desktop and Notebook PCs Designs Demonstrated] Blat: Foop ---------------- Forwarded message: ---------------- From: jcwright@rhino.corp.sgi.com (Jill Wright) Newsgroups: comp.sys.sgi.announce Subject: Low Cost, High Performance Microprocessor Now Shipping; Desktop and Notebook PCs Designs Demonstrated Date: 17 Nov 1993 21:47:49 GMT This release was issued today and went over the wire at 12:02p.m. PST. [This press release has been slightly edited to remove any blatant commerical aspects. MJW:moderator] LOW COST, HIGH PERFORMANCE MICROPROCESSOR NOW SHIPPING; DESKTOP AND NOTEBOOK PCs DESIGNS DEMONSTRATED LAS VEGAS, Nevada-November 16, 1993 -MIPS Technologies, Inc. today announced and demonstrated reference designs for systems manufacturers to build high-performance, cost-effective desktop and notebook personal computers based on the MIPS R4200(tm) 64-bit RISC microprocessor for the Microsoft Windows NT operating system. The R4200 provides similar performance to Intel's Pentium for under one-tenth the power dissipation. The R4200 is now shipping in sample quantities. R4200-based notebook and desktop computers are on display at Comdex in the MIPS Technologies booth (L-1492), with an additional notebook in the NEC Electronics booth (L-2636). The R4200 operates at a clock speed of 80 MHz with integer computational performance of 55 SPECint92. The processor supports Windows NT and the Unix operating system. A second version of the processor running at 100 MHz is scheduled for release in early in 1994, providing even higher performance but remaining a low-power consumption, under-$100 processor. The R4200 features advanced power management for use in "green" Energy Star-compliant computers and notebook computers designed for long battery life. At full power, the R4200 runs at only 1.5 watts. To save energy, in periods of low activity, the processor switches to reduced power mode. In this mode, the R4200 operates at one-quarter power. During longer periods of inactivity the processor "powers down." When reactivated, the "Instant-On" capability allows the system to restore the processor to its executing state quickly. The reference designs can enable manufacturers to readily build affordable PCs based on the R4200 which take full advantage of the processor's performance, low cost and low power requirements. There are four R4200 reference designs: a notebook designed for high-performance, a notebook emphasizing long battery life, a desktop designed for high-performance and a low cost desktop. These four reference designs complement the more than five existing reference designs for MIPS-based PCs. In addition to desktop and notebook PCs, the R4200 and derivative core products are ideally suited for use in hand-held and other consumer products as well as other embedded applications such as laser printer controllers, X-terminals and communications devices. "The low cost and high performance of the MIPS R4200 opens up new worlds of computers and consumer devices," said Tom Whiteside, president of MIPS Technologies. "With the R4200, companies can cost effectively deliver the power needed to take advantage of interactive multimedia or Windows NT applications." Windows NT was developed on the MIPS architecture, and MIPS-based PCs are designed to run Windows NT optimally and offer the highest performance at prices comparable to 486-based PCs. MIPS-based PCs smoothly run existing MS-DOS and Microsoft Windows application software, but their power becomes especially apparent with 32-bit Windows NT applications. New 32-bit applications are now becoming available. - end - MIPS is a registered trademark, and R4200 is a trademark of MIPS Technologies, Inc. Pentium is a trademark and Intel is a registered trademark of Intel Corporation. Windows NT is a trademark of Microsoft Corporation. From kent@tifsim.pac.sc.ti.com Thu Nov 18 08:31:31 1993 Received: from lobby.ti.com by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA19093; Thu, 18 Nov 1993 15:34:24 -0500 Received: from tifsim.pac.sc.ti.com ([128.247.112.4]) by lobby.ti.com with SMTP (5.65c/LAI-3.2) id AA13794; Thu, 18 Nov 1993 14:34:25 -0600 Received: by tifsim.pac.sc.ti.com (5.57/Ultrix3.0-C) id AA13627; Thu, 18 Nov 93 14:31:59 -0600 From: kent@tifsim.pac.sc.ti.com (Russell Kent) Received: by juliet.pac.sc.ti.com id ; Thu, 18 Nov 93 14:31:32 CST Message-Id: <9311182031.AA11803@juliet.pac.sc.ti.com> Subject: Texas Inst. Video Interface Palette chip To: riscy@sunsite.unc.edu Date: Thu, 18 Nov 93 14:31:31 CST X-Mailer: ELM [version 2.3 PL11] Stupid @#$!%#!% list processor. Apparently when the list moved from pyramid to sunsite it lost my registration. *sigh* I sent this a few days ago... Hello fellow MIPSers. This came out on the T.I. news service (while I was in Malaysia a few days back). I'm not enough of a video hardware person to pass judgement on it, but I thought I'd let those who are have a gander at it. (Please forgive the hype-speak). According to the T.I. semiconductor product information center, recommended unit pricing in 1,000s is: 135MHz US$31.25 175MHz 56.25 200MHz 83.75 According to them, T.I. is accepting orders now with an 8 week manufacturing lead time. A data manual is available from the T.I. Literature center at 1-800-477-8924 (sorry to those of you overseas). The literature number is SLAS080. I haven't called them so I don't know the cost (if any) of the data manual. Russell Kent -- Texas Instruments rkent@lobby.ti.com -or- PO Box 655012 M/S 3624 kent@tifsim.pac.sc.ti.com Dallas, TX 75265 TI-MSG: RAK9 Voice: (214) 917-2285 FAX: (214) 917-5112 ------8<------8<------8<------8<------8<------8<------8<------8<------8<------ NEW COLOR PALETTE CHIP PROVIDES PHOTO-QUALITY COLOR RENDITION AND 64-BIT PERFORMANCE FOR PC, WORKSTATION GRAPHICS DALLAS (Nov. 11) -- Designers of personal computer and workstation graphics systems can use a new video interface palette (VIP) from TI to implement cost- effective, high-performance graphics for mainstream and high-end applications. The device is the industry's first color palette chip with a 64-bit picture element (pixel) bus designed for the PC graphics accelerator market. Because the device is available in three speeds - 135, 175 and 200 MHz, one design with this device can be used in applications across a wide performance spectrum from mainstream to high-end systems. A design incorporating this device can be easily upgraded by adding more memory and a high-speed VIP. The device's separate VGA port makes it well-suited for PC graphics and windows accelerator applications. The TVP3020 Video Interface Palette (VIP) can display 24-bit true color (16 million colors) at a resolution of 1024 x 768 and 16-bit true color (65,000 colors) at resolutions up to 1600 x 1280. The TVP3020 true color can be gamma corrected to allow for more accurate color rendition. By integrating the functions of a traditional color palette, plus several discrete chips such as buffer logic and multiplexers, the TVP3020 offers a complete graphics back-end system on a chip which can directly interface to 4 mega bytes of video random access memory (VRAM) as well as many industry- standard graphics accelerators. "The TVP3020 VIP is particularly well-suited to windows accelerator products, especially those involving true color at high resolutions," said Richard Nail, TI product marketing manager for color palettes. "With a maximum speed of 200 MHz, this is the fastest PC-optimized color palette device available on the market today." With an internal frequency doubler, the TVP3020 is able to reduce system costs by allowing the use of less expensive, low-frequency synthesizers. System performance is also enhanced by the device's hardware cursor, which eliminates the need for the system's CPU or graphics processor to create the display's cursor in software. The VIP pixel bus can be programmed for 4-, 8-, 16-, 32- or 64-bit widths and many different color depths, allowing a single hardware design to support many resolution/color combinations. In addition, the TVP3020 has a color-key switching capability so that true color images and graphic overlays can be easily combined on-screen. ------8<------8<------8<------8<------8<------8<------8<------8<------8<------ From gt@prosun.first.gmd.de Thu Nov 18 22:53:10 1993 Received: from prosun.first.gmd.de by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA21379; Thu, 18 Nov 1993 15:55:15 -0500 Received: from gs2.gmd.de (gs2.first.gmd.de) by prosun.first.gmd.de (4.1/SMI-4.1) id AA22733; Thu, 18 Nov 93 21:47:25 +0100 From: gt@prosun.first.gmd.de (Gerd Truschinski) Message-Id: <9311182047.AA22733@prosun.first.gmd.de> Subject: Re: Texas Inst. Video Interface Palette chip To: riscy@sunsite.unc.edu Date: Thu, 18 Nov 1993 21:53:10 +0100 (MET) In-Reply-To: <9311182031.AA11803@juliet.pac.sc.ti.com> from "Russell Kent" at Nov 18, 93 03:35:19 pm X-Mailer: ELM [version 2.4 PL22] Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 293 > According to the T.I. semiconductor product information center, recommended > unit pricing in 1,000s is: > > 135MHz US$31.25 > 175MHz 56.25 > 200MHz 83.75 > That is all about the TVP3020, isn't it. What is it good for us? I don't see the point. Please help me. /gT/ From kent@tifsim.pac.sc.ti.com Thu Nov 18 10:28:17 1993 Received: from ti.com by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA00620; Thu, 18 Nov 1993 17:30:44 -0500 Received: from tifsim.pac.sc.ti.com ([128.247.112.4]) by ti.com with SMTP (5.65c/LAI-3.2) id AA10845; Thu, 18 Nov 1993 16:32:01 -0600 Received: by tifsim.pac.sc.ti.com (5.57/Ultrix3.0-C) id AA17776; Thu, 18 Nov 93 16:28:45 -0600 From: kent@tifsim.pac.sc.ti.com (Russell Kent) Received: by juliet.pac.sc.ti.com id ; Thu, 18 Nov 93 16:28:18 CST Message-Id: <9311182228.AA12174@juliet.pac.sc.ti.com> Subject: Re: Texas Inst. Video Interface Palette chip To: riscy@sunsite.unc.edu Date: Thu, 18 Nov 93 16:28:17 CST In-Reply-To: <9311182047.AA22733@prosun.first.gmd.de>; from "Gerd Truschinski" at Nov 18, 93 4:14 pm X-Mailer: ELM [version 2.3 PL11] Gerd Truschinski replies to my posting: > > According to the T.I. semiconductor product information center, recommended > > unit pricing in 1,000s is: > > > > 135MHz US$31.25 > > 175MHz 56.25 > > 200MHz 83.75 > > > That is all about the TVP3020, isn't it. What is it good for us? I don't > see the point. Please help me. > > /gT/ Well, maybe it doesn't. I'm just a software person. Earlier discussions had talked about using a TI 34076 RAMDAC coupled with a NSC LM1882 video sync generator plus VRAM and interface circuitry to generate video. The TVP3020 hype said: By integrating the functions of a traditional color palette, plus several discrete chips such as buffer logic and multiplexers, the TVP3020 offers a complete graphics back-end system on a chip which can directly interface to 4 mega bytes of video random access memory (VRAM) as well as many industry-standard graphics accelerators. I took them at their word (foolish me?). I thought that the TVP3020 would eliminate the all the other gook, plus it has a 64-bit wide interface which I thought the R4200 had also (possibly eliminating bus-width matching circuitry). So, educate me. If this is *not* what the TVP is, then what is it? Russell -- Texas Instruments rkent@lobby.ti.com -or- PO Box 655012 M/S 3624 kent@tifsim.pac.sc.ti.com Dallas, TX 75265 TI-MSG: RAK9 Voice: (214) 917-2285 FAX: (214) 917-5112 From broadley@neurocog.lrdc.pitt.edu Thu Nov 18 14:37:06 1993 Received: from neurocog.lrdc.pitt.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA12580; Thu, 18 Nov 1993 19:37:09 -0500 Received: from localhost (broadley@localhost) by neurocog.lrdc.pitt.edu (8.6.4/8.6.4) id TAA25984 for riscy@sunsite.unc.edu; Thu, 18 Nov 1993 19:37:08 -0500 From: Bill Broadley Message-Id: <199311190037.TAA25984@neurocog.lrdc.pitt.edu> Subject: Comdex: 4200's To: riscy@sunsite.unc.edu Date: Thu, 18 Nov 1993 19:37:06 -0500 (EST) X-Mailer: ELM [version 2.4 PL21] Content-Type: text Content-Length: 573 Apparently mips is talking about 4 new "4200 reference designs" at comdex: notebook designed for high performance notebook designed for long life desktop PC designed for high performance low-cost desktop model I suspect the difference between the last two is second level cache. So lets hope mips is eager to sell us the designs. -- Bill 1st> Broadley@neurocog.lrdc.pitt.edu Broadley@schneider3.lrdc.pitt.edu <2nd 3rd> Broadley+@pitt.edu Linux is great. Bike to live, live to bike. PGP-ok From ksh@charybdis.prl.ufl.edu Thu Nov 18 15:51:38 1993 Received: from charybdis.prl.ufl.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA20641; Thu, 18 Nov 1993 20:50:20 -0500 Received: by charybdis.prl.ufl.edu (4.1/1.34) id AA19013; Thu, 18 Nov 93 20:51:38 EST Date: Thu, 18 Nov 93 20:51:38 EST From: ksh@charybdis.prl.ufl.edu (Kevin S Ho) Message-Id: <9311190151.AA19013@charybdis.prl.ufl.edu> To: riscy@sunsite.unc.edu Subject: Re: Comdex: 4200's Well, these 4200's seem to be quite good, but let's look at expansion potential, as we don't want to pull a "PC". If the 4200 is expected to be a resonable public archietecture with a future, which it seems to be, then we should use it, but we should put more into infrastructure. The spec I have seen of the goal board should imho havve eisa, at least KsH From Steven.D.Ligett@Dartmouth.EDU Mon Nov 18 17:13:28 1993 Received: from coos.dartmouth.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA28347; Thu, 18 Nov 1993 22:13:35 -0500 Received: by coos.dartmouth.edu (5.65/DEC-Ultrix/4.3) id AA19803; Thu, 18 Nov 1993 22:13:29 -0500 Message-Id: <7629005@prancer.Dartmouth.EDU> Date: 18 Nov 93 22:13:28 EST From: Steven.D.Ligett@Dartmouth.EDU (Steven D. Ligett) Subject: Re: Texas Inst. Video Interface Palette chip To: riscy@sunsite.unc.edu --- You wrote: So, educate me. If this is *not* what the TVP is, then what is it? --- end of quoted material --- Sounds like a 34076 w 64-bit vram interface. From drew@kinglear.cs.Colorado.EDU Thu Nov 18 13:48:53 1993 Received: from kinglear.cs.colorado.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA01694; Thu, 18 Nov 1993 22:48:56 -0500 Received: from localhost (localhost [127.0.0.1]) by kinglear.cs.Colorado.EDU (8.6.4/8.6.4) with SMTP id UAA05602 for ; Thu, 18 Nov 1993 20:48:54 -0700 Message-Id: <199311190348.UAA05602@kinglear.cs.Colorado.EDU> X-Authentication-Warning: kinglear.cs.Colorado.EDU: Host localhost didn't use HELO protocol To: riscy@sunsite.unc.edu Subject: Re: Comdex: 4200's In-Reply-To: Your message of "Thu, 18 Nov 1993 20:50:48 EST." <9311190151.AA19013@charybdis.prl.ufl.edu> Date: Thu, 18 Nov 1993 20:48:53 -0700 From: Drew Eckhardt Well, these 4200's seem to be quite good, but let's look at expansion potential, as we don't want to pull a "PC". If the 4200 is expected to be a resonable public archietecture with a future, which it seems to be, then we should use it, but we should put more into infrastructure. The spec I have seen of the goal board should imho havve eisa, at least We've discussed this before : 1. The 4200 is available in a R4000PC compatable 179 pin PGA package as well as a surface mount package. If you go with the 179 pin PGA, you have an immediate, plug-compatable upgrade path to the R4000PC (100Mhz, 8KI, 8KD), or R4400PC (100 or 150Mhz, 16KI, 16KD) (Note : you have to also change the serially downloaded boot information determining memory interface speed and access patterns as well as the clock crystal) 2. There's nothing stopping you from making a daughter card with the 179pin PGA connector on the bottom - AMD does this to get their surface mount 386DX chips into normal 386 PGA sockets, HP did it on some of their 68k workstations to allow for either 68040 or 68030+68882 boxes, etc. With a daughter card like this, you can use 4200 surface mount chips, 4000/4400 MC/SC chips with the 128 bit interface to second level cache, etc. 3. The IDT Orion should ship some time in a 179 pin PGA package. In other words : there is no upgrade problem with a 4200. From drew@kinglear.cs.Colorado.EDU Thu Nov 18 15:54:34 1993 Received: from kinglear.cs.colorado.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA11008; Fri, 19 Nov 1993 00:54:44 -0500 Received: from localhost (localhost [127.0.0.1]) by kinglear.cs.Colorado.EDU (8.6.4/8.6.4) with SMTP id WAA06563; Thu, 18 Nov 1993 22:54:41 -0700 Message-Id: <199311190554.WAA06563@kinglear.cs.Colorado.EDU> X-Authentication-Warning: kinglear.cs.Colorado.EDU: Host localhost didn't use HELO protocol To: "Poorly written mailing list software" , "Poorly written mailing list software administration" Subject: Hideous mailing list software Date: Thu, 18 Nov 1993 22:54:34 -0700 From: Drew Eckhardt Is it just me, or is this sort of crap anoying, especially given the number of sites with shared mail pools on a large number of systems, where users incoming mail addresses don't correspond to where their mail is coming from (ie, drew@colorado.edu doesn't go to a real machine), etc? IMHO, list-serv should be configured like other mailing list servers and allow 'non-subscribers' to post to the list, or it should include an ALIAS facility allowing it to treat mail from drew@*.colorado.edu correctly. ------- Forwarded Message Return-Path: riscy@SunSITE.Unc.EDU Received: from SunSITE.Unc.EDU (SunSite.unc.edu [152.2.22.81]) by nag.cs.Colorado.EDU (8.6.4/8.6.4) with SMTP id AAA11005 for ; Fri, 19 Nov 1993 00:48:47 -0500 Received: from (localhost.oit.unc.edu) by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA10505; Fri, 19 Nov 1993 00:48:40 -0500 Date: Fri, 19 Nov 1993 00:48:40 -0500 Message-Id: <199311190543.WAA00901@hamlet.cs.Colorado.EDU> Errors-To: caret@c-side.com Reply-To: riscy@SunSITE.Unc.EDU Originator: riscy@sunsite.unc.edu Sender: riscy@SunSITE.Unc.EDU Precedence: bulk From: riscy@SunSITE.Unc.EDU To: drew@hamlet.cs.colorado.edu Subject: Error Condition Re: Re: Texas Inst. Video Interface Palette chip X-Listprocessor-Version: 6.0a -- ListProcessor by Anastasios Kotsikonas drew@hamlet.cs.colorado.edu: You are not subscribed to riscy@sunsite.unc.edu. Your message is returned to you unprocessed. If you want to subscribe, send mail to listserv@sunsite.unc.edu with the following request: subscribe RISCY Your Name In addition, the system found the following address(es) that resemble yours. If one of these is you, please resend your message from that one, or use the 'set address' request to change the address you are subscribed with: DREW@KINGLEAR.CS.COLORADO.EDU From drew@kinglear.cs.Colorado.EDU Thu Nov 18 15:55:31 1993 Received: from kinglear.cs.colorado.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA11090; Fri, 19 Nov 1993 00:55:34 -0500 Received: from localhost (localhost [127.0.0.1]) by kinglear.cs.Colorado.EDU (8.6.4/8.6.4) with SMTP id WAA06574 for ; Thu, 18 Nov 1993 22:55:32 -0700 Message-Id: <199311190555.WAA06574@kinglear.cs.Colorado.EDU> X-Authentication-Warning: kinglear.cs.Colorado.EDU: Host localhost didn't use HELO protocol To: riscy@sunsite.unc.edu Subject: Re something, was deleted by listserv Date: Thu, 18 Nov 1993 22:55:31 -0700 From: Drew Eckhardt > According to the T.I. semiconductor product information center, recommend ed > unit pricing in 1,000s is: > > 135MHz US$31.25 > 175MHz 56.25 > 200MHz 83.75 > That is all about the TVP3020, isn't it. What is it good for us? I don't see the point. Please help me. When we feed it with 64 bit VRAM, the net effect is 1. Cheap - the TVP3020 @ $31.25 to $83.75 plus VRAM (up to 4M) @ $60/meg and a clock circuit is our video solution. 2. Fast - a VRAM based dumb frame buffer lets you do graphics operations at about 95% of the speed you'd do them to DRAM, and in this case we have a 64bit wide interface to the VRAM. Read DEC's paper on framebuffers if you'd like an accelerated chip, the gist of it is that the main processor will allways be faster than the coprocessor lagging a generation behind it. In our case (single user workstation), we don't care if our background processes slow down when we blit, scroll, etc, it's the apparant speed that's important. 3. Flexible - you can drive any of our configurations off of this, from VGA resolutions with minimal colors to 1600x1280 with 16 bit true color. It's a more integrated, slightly more expensive version of the TI34076 solution Steven original proposed, looks real nice. From drew@kinglear.cs.Colorado.EDU Thu Nov 18 16:23:11 1993 Received: from kinglear.cs.colorado.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA12885; Fri, 19 Nov 1993 01:23:15 -0500 Received: from localhost (localhost [127.0.0.1]) by kinglear.cs.Colorado.EDU (8.6.4/8.6.4) with SMTP id XAA06660 for ; Thu, 18 Nov 1993 23:23:12 -0700 Message-Id: <199311190623.XAA06660@kinglear.cs.Colorado.EDU> X-Authentication-Warning: kinglear.cs.Colorado.EDU: Host localhost didn't use HELO protocol To: riscy@sunsite.unc.edu Subject: Subject was deleted by lousy list server when it bounced it Date: Thu, 18 Nov 1993 23:23:11 -0700 From: Drew Eckhardt > According to the T.I. semiconductor product information center, recommend ed > unit pricing in 1,000s is: > > 135MHz US$31.25 > 175MHz 56.25 > 200MHz 83.75 > That is all about the TVP3020, isn't it. What is it good for us? I don't see the point. Please help me. When we feed it with 64 bit VRAM, the net effect is 1. Cheap - the TVP3020 @ $31.25 to $83.75 plus VRAM (up to 4M) @ $60/meg and a clock circuit is our video solution. 2. Fast - a VRAM based dumb frame buffer lets you do graphics operations at about 95% of the speed you'd do them to DRAM, and in this case we have a 64bit wide interface to the VRAM. Read DEC's paper on framebuffers if you'd like an accelerated chip, the gist of it is that the main processor will allways be faster than the coprocessor lagging a generation behind it. In our case (single user workstation), we don't care if our background processes slow down when we blit, scroll, etc, it's the apparant speed that's important. 3. Flexible - you can drive any of our configurations off of this, from VGA resolutions with minimal colors to 1600x1280 with 16 bit true color. It's a more integrated, slightly more expensive version of the TI34076 solution Steven original proposed, looks real nice. ------- End of Forwarded Message From drew@kinglear.cs.Colorado.EDU Thu Nov 18 16:26:53 1993 Received: from kinglear.cs.colorado.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA13137; Fri, 19 Nov 1993 01:26:56 -0500 Received: from localhost (localhost [127.0.0.1]) by kinglear.cs.Colorado.EDU (8.6.4/8.6.4) with SMTP id XAA06698 for ; Thu, 18 Nov 1993 23:26:54 -0700 Message-Id: <199311190626.XAA06698@kinglear.cs.Colorado.EDU> X-Authentication-Warning: kinglear.cs.Colorado.EDU: Host localhost didn't use HELO protocol To: riscy@sunsite.unc.edu Subject: Subject was deleted by abysmal mailing list software Date: Thu, 18 Nov 1993 23:26:53 -0700 From: Drew Eckhardt > According to the T.I. semiconductor product information center, recommend ed > unit pricing in 1,000s is: > > 135MHz US$31.25 > 175MHz 56.25 > 200MHz 83.75 > That is all about the TVP3020, isn't it. What is it good for us? I don't see the point. Please help me. When we feed it with 64 bit VRAM, the net effect is 1. Cheap - the TVP3020 @ $31.25 to $83.75 plus VRAM (up to 4M) @ $60/meg and a clock circuit is our video solution. 2. Fast - a VRAM based dumb frame buffer lets you do graphics operations at about 95% of the speed you'd do them to DRAM, and in this case we have a 64bit wide interface to the VRAM. Read DEC's paper on framebuffers if you'd like an accelerated chip, the gist of it is that the main processor will allways be faster than the coprocessor lagging a generation behind it. In our case (single user workstation), we don't care if our background processes slow down when we blit, scroll, etc, it's the apparant speed that's important. 3. Flexible - you can drive any of our configurations off of this, from VGA resolutions with minimal colors to 1600x1280 with 16 bit true color. It's a more integrated, slightly more expensive version of the TI34076 solution Steven original proposed, looks real nice. ------- End of Forwarded Message From drew@kinglear.cs.Colorado.EDU Thu Nov 18 16:33:12 1993 Received: from kinglear.cs.colorado.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA13508; Fri, 19 Nov 1993 01:33:14 -0500 Received: from localhost (localhost [127.0.0.1]) by kinglear.cs.Colorado.EDU (8.6.4/8.6.4) with SMTP id XAA06746 for ; Thu, 18 Nov 1993 23:33:13 -0700 Message-Id: <199311190633.XAA06746@kinglear.cs.Colorado.EDU> X-Authentication-Warning: kinglear.cs.Colorado.EDU: Host localhost didn't use HELO protocol To: riscy@sunsite.unc.edu Subject: Subject was deleted by lousy mailing list software Date: Thu, 18 Nov 1993 23:33:12 -0700 From: Drew Eckhardt > According to the T.I. semiconductor product information center, recommend ed > unit pricing in 1,000s is: > > 135MHz US$31.25 > 175MHz 56.25 > 200MHz 83.75 > That is all about the TVP3020, isn't it. What is it good for us? I don't see the point. Please help me. When we feed it with 64 bit VRAM, the net effect is 1. Cheap - the TVP3020 @ $31.25 to $83.75 plus VRAM (up to 4M) @ $60/meg and a clock circuit is our video solution. 2. Fast - a VRAM based dumb frame buffer lets you do graphics operations at about 95% of the speed you'd do them to DRAM, and in this case we have a 64bit wide interface to the VRAM. Read DEC's paper on framebuffers if you'd like an accelerated chip, the gist of it is that the main processor will allways be faster than the coprocessor lagging a generation behind it. In our case (single user workstation), we don't care if our background processes slow down when we blit, scroll, etc, it's the apparant speed that's important. 3. Flexible - you can drive any of our configurations off of this, from VGA resolutions with minimal colors to 1600x1280 with 16 bit true color. It's a more integrated, slightly more expensive version of the TI34076 solution Steven original proposed, looks real nice. ------- End of Forwarded Message From drew@kinglear.cs.Colorado.EDU Thu Nov 18 17:05:30 1993 Received: from kinglear.cs.colorado.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA15511; Fri, 19 Nov 1993 02:05:37 -0500 Received: from localhost (localhost [127.0.0.1]) by kinglear.cs.Colorado.EDU (8.6.4/8.6.4) with SMTP id AAA07132 for ; Fri, 19 Nov 1993 00:05:35 -0700 Message-Id: <199311190705.AAA07132@kinglear.cs.Colorado.EDU> X-Authentication-Warning: kinglear.cs.Colorado.EDU: Host localhost didn't use HELO protocol To: riscy@sunsite.unc.edu Subject: Re: riscy status? In-Reply-To: Your message of "Fri, 12 Nov 1993 18:35:14 EST." <199311122332.AA05752@SunSITE.Unc.EDU> Date: Fri, 19 Nov 1993 00:05:30 -0700 From: Drew Eckhardt The list has been dead for sometime. Would anybody care to summarise on what chips (if any) we have definitely decided on? Decisions need to be made if we are ever to get out of the vapourware phase... About a month ago, I posted to the list, said that I didn't have very much going on and that if people committed to a NCR53cf94 semi-intelligent, slave mode DMA FAST SCSI-II chip, I'd build an ISA protoboard and get a stable driver. No one would commit to the 53cf94 even though no better alternative had been proposed and the price and complexity difference between it and NCR busmasters is significant (the later is a microcontroller, meaning you have to write an assembler for it and debugging is nastier, the 53c700/800 series are also closer to $60 in the same quantities that the NCR53cf94 is $25, and you won't get any better throughput with the increased costs). And we don't have any commitments on any other chips. Here's a forward of a summary Bill mailed out a little while ago : I/O MISC: SMC FDC37c666 2.88 MB floppy controller, 2 16550's, bi directional parallel, IDE $23.00 qty 26 SCSI: NCR 53cf90/53cf94 fast SCSI II 68 leads 0.910" square for $18.60 in qnty 50-99 VLSI VL82C114 Real time clock, nvram, keyboard, refresh counter, and ISA address buffer. 8 UKP qty 24-99 VIDEO: A dumb frame buffer would probably work out well (given the wide bandwidth, high speed cpu). The arc chipset provides for a 64 bit bus to video. 1 MB vram $60 1 TI tlc34076 RAMDAC $32 1 NSC LM1882 Video sync generator $ 8 From wolff@dutecai.et.tudelft.nl Fri Nov 19 11:22:47 1993 Received: from dutecai.et.tudelft.nl by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA24073; Fri, 19 Nov 1993 04:22:50 -0500 Received: by dutecai.et.tudelft.nl (4.1/1.34JP) id AA19333; Fri, 19 Nov 93 10:22:47 +0100 Date: Fri, 19 Nov 93 10:22:47 +0100 From: wolff@dutecai.et.tudelft.nl (Rogier Wolff) Message-Id: <9311190922.AA19333@dutecai.et.tudelft.nl> To: riscy@sunsite.unc.edu Subject: X-Listprocessor-Version: 6.0a -- ListProcessor by Anastasios Kotsikonas Message 28/28 From riscy@sunsite.unc.edu Nov 19, 93 04:07:42 am -0500 Return-Path: Date: Fri, 19 Nov 1993 04:07:42 -0500 Errors-To: caret@c-side.com Reply-To: riscy@sunsite.unc.edu Originator: riscy@sunsite.unc.edu Sender: riscy@sunsite.unc.edu Precedence: bulk To: wolff@dutecai.et.tudelft.nl Subject: Error Condition Re: Re: Texas Inst. Video Interface Palette chip X-Listprocessor-Version: 6.0a -- ListProcessor by Anastasios Kotsikonas wolff@liberator.et.tudelft.nl: You are not subscribed to riscy@sunsite.unc.edu. Your message is returned to you unprocessed. If you want to subscribe, send mail to listserv@sunsite.unc.edu with the following request: subscribe RISCY Your Name In addition, the system found the following address(es) that resemble yours. If one of these is you, please resend your message from that one, or use the 'set address' request to change the address you are subscribed with: WOLFF@DUTECAI.ET.TUDELFT.NL ------------------------------------------------------------------------------- > > The TVP3020 Video Interface Palette (VIP) can display 24-bit true color (16 > million colors) at a resolution of 1024 x 768 and 16-bit true color (65,000 > colors) at resolutions up to 1600 x 1280. Jeeez. If you want to advertize "High End" then you need to support more than 1024x768 at 24 bits per pixel. To me "High End" is at least 1280x1024, even at 24 bits per pixel. You don't even need more than 4Mb RAM to pull this off.... According to SGS Thompson info I have at 1600x1280@70Hz, you need a video bandwidth of 1.3 * 1600 * 1280 * 70 = 186Mhz. With three bytes per pixel you need 560 Mb per second of video data. At 8 bytes per transfer you get a 70Mhz transfer rate of video data. This is slightly tricky, but not unusual for high end systems. Roger. From andy@waldorf-gmbh.de Fri Nov 19 10:24:43 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA28192; Fri, 19 Nov 1993 05:43:32 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id MR09608; Fri, 19 Nov 1993 09:31:41 +0100 Received: from resi From: Andreas Busse Date: Fri, 19 Nov 93 09:24:43 +0100 Message-Id: <9311190824.AA29266@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA29266; Fri, 19 Nov 93 09:24:43 +0100 To: riscy@sunsite.unc.edu Subject: Re: Hideous mailing list software > Is it just me, or is this sort of crap anoying, especially given the number > of sites with shared mail pools on a large number of systems, where users > incoming mail addresses don't correspond to where their mail is coming > from (ie, drew@colorado.edu doesn't go to a real machine), etc? > > > IMHO, list-serv should be configured like other mailing list servers and > allow 'non-subscribers' to post to the list, or it should include an > ALIAS facility allowing it to treat mail from drew@*.colorado.edu > correctly. No, it's not only you. I had the same trouble. More painful, we had subscribed as riscy@waldorf-gmbh.de, a sublist here at Waldorf (simply an alias for sendmail) to avoid unnessary traffic. With this stupid, over-secure and #$^&*&% listserver I couldn't post anymore (see above). Even more painful, I receive messages now twice (although I *have* removed me from our sublist !). No, it's not funny. Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From andy@waldorf-gmbh.de Fri Nov 19 10:36:32 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA28288; Fri, 19 Nov 1993 05:45:46 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id MR09706; Fri, 19 Nov 1993 09:41:21 +0100 Received: from resi From: Andreas Busse Date: Fri, 19 Nov 93 09:36:32 +0100 Message-Id: <9311190836.AA29346@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA29346; Fri, 19 Nov 93 09:36:32 +0100 To: riscy@sunsite.unc.edu Subject: Re: Subject was deleted by abysmal mailing list software > > According to the T.I. semiconductor product information center, recommend > ed > > unit pricing in 1,000s is: > > > > 135MHz US$31.25 > > 175MHz 56.25 [...] I HAVE RECEIVED THIS MESSAGE 6 (SIX) TIMES ! WHAT'S GOING ON HERE ??????????????????????? I believe it may be cheaper for us to setup the list here at Waldorf... Can someone explain me what kind of brain damaged software this listserver is ? Andy P.S.: Sorry for being so loud... ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From Daniel.Veillard@imag.fr Fri Nov 19 13:36:36 1993 Received: from imag.imag.fr by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA02447; Fri, 19 Nov 1993 07:07:12 -0500 Received: from maupiti.imag.fr by imag.imag.fr with SMTP id AA17823 (5.65c8/IDA-1.4.4 for ); Fri, 19 Nov 1993 13:04:33 +0100 Received: by maupiti.imag.fr (5.65/5.17) id AA05272; Fri, 19 Nov 1993 13:06:59 +0100 From: Daniel.Veillard@imag.fr (Daniel Veillard) Message-Id: <9311191206.AA05272@maupiti.imag.fr> To: riscy@sunsite.unc.edu Cc: Danie.Veillard@imag.fr Subject: L2 Caching and SIMMs format Date: Fri, 19 Nov 93 12:36:36 +0100 just a few remarks concerning The Board design : - maybe we should put the L2 cache memory management even if most of us won't use it (SRAM == $$$), in order to preserve the expandability of the beast. Upgrading to R4400 without L2 cache may not be very interesting. - What format of SIMMs will be needed, 36 or 72 bits? I bet most of us spent much $$$ in 36 bit SIMMs and would be disapointed if these cannot fit onto their Super Board. But there is probably a bandwith problem with 36 bits SIMMs. Maybe the HW specialists here could comment on these points, Daniel ------------------------------------------------------------------ PS : my first posting failed due to a change in the way mail is managed here in Grenoble. I had to re-suscribe to the mailing list but I cannot remove my old adress : >daniel.veillard@imag.fr: You are not subscribed to riscy@sunsite.unc.edu. >Your message is returned to you unprocessed. If you want to subscribe, >send mail to listserv@sunsite.unc.edu with the following request: > > subscribe RISCY Your Name > >In addition, the system found the following address(es) that resemble yours. >If one of these is you, please resend your message from that one, or use the >'set address' request to change the address you are subscribed with: > >DANIEL.VEILLARD@IMAG.IMAG.FR ^^^^^ could someone remove this old adress, please. ------------------------------------------------------------------ Daniel Veillard : | Bull-IMAG Systems E-mail : Daniel.Veillard@imag.fr | Centre Equation Tel : (33) 76 63 48 53 | 2 ave. de Vignates Fax : (33) 76 54 76 15 | 38610 GIERES FRANCE From hp@quasi.vmars.tuwien.ac.at Fri Nov 19 07:13:27 1993 Received: from quasi.vmars.tuwien.ac.at by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA02822; Fri, 19 Nov 1993 07:13:27 -0500 Received: by quasi.vmars.tuwien.ac.at id AA04962 (5.64+/IDA-1.3.4 for riscy@sunsite.unc.edu); Fri, 19 Nov 93 13:12:37 +0100 From: Peter Holzer Message-Id: <9311191212.AA04962@quasi.vmars.tuwien.ac.at> Subject: Re: Subject was deleted by abysmal mailing list software To: riscy@sunsite.unc.edu Date: Fri, 19 Nov 93 13:12:36 MET In-Reply-To: <9311190836.AA29346@resi.waldorf-gmbh.de>; from "Andreas Busse" at Nov 19, 93 5:51 am Reply-To: hp@vmars.vmars.tuwien.ac.at X-Return-Receipt-To: hp@vmars.tuwien.ac.at X-Mailer: ELM [version 2.3 PL5] You (Andreas Busse) wrote: > > > > According to the T.I. semiconductor product information center, recommend > > ed > > > unit pricing in 1,000s is: > > > > > > 135MHz US$31.25 > > > 175MHz 56.25 > [...] > > I HAVE RECEIVED THIS MESSAGE 6 (SIX) TIMES ! > WHAT'S GOING ON HERE ??????????????????????? I only got it 4 times and the subject was different each time, so I guess that Drew remailed it several times. BTW the previous mails in this thread did have a subject when I got them, so there seems to be conspiration between the list-server and Drew's setup to remove subjects :-) I agree that the list-server should allow either aliases for users or postings from unsubscribed users. hp -- _ | hp@vmars.tuwien.ac.at | Peter Holzer | TU Vienna | CS/Real-Time Systems |_|_) |------------------------------------------------------------------------ | | | ...and it's finished! It only has to be written. __/ | -- Karl Lehenbauer From kent@tifsim.pac.sc.ti.com Fri Nov 19 01:00:41 1993 Received: from ti.com by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA06517; Fri, 19 Nov 1993 08:02:11 -0500 Received: from tifsim.pac.sc.ti.com ([128.247.112.4]) by ti.com with SMTP (5.65c/LAI-3.2) id AA13305; Fri, 19 Nov 1993 07:03:42 -0600 Received: by tifsim.pac.sc.ti.com (5.57/Ultrix3.0-C) id AA15209; Fri, 19 Nov 93 07:01:47 -0600 From: kent@tifsim.pac.sc.ti.com (Russell Kent) Received: by juliet.pac.sc.ti.com id ; Fri, 19 Nov 93 07:00:42 CST Message-Id: <9311191300.AA12693@juliet.pac.sc.ti.com> Subject: Re: X-Listprocessor-Version To: riscy@sunsite.unc.edu Date: Fri, 19 Nov 93 7:00:41 CST In-Reply-To: <9311190922.AA19333@dutecai.et.tudelft.nl>; from "Rogier Wolff" at Nov 19, 93 4:24 am X-Mailer: ELM [version 2.3 PL11] Roger Wolff (wolff@liberator.et.tudelft.nl aka WOLFF@DUTECAI.ET.TUDELFT.NL :-) writes: > Jeeez. If you want to advertize "High End" then you need to support more > than 1024x768 at 24 bits per pixel. To me "High End" is at least 1280x1024, > even at 24 bits per pixel. You don't even need more than 4Mb RAM to > pull this off.... Hey, I said I was sorry for the commercial hype-speak ;-) > According to SGS Thompson info I have at 1600x1280@70Hz, you need a video > bandwidth of 1.3 * 1600 * 1280 * 70 = 186Mhz. With three bytes per pixel > you need 560 Mb per second of video data. At 8 bytes per transfer you > get a 70Mhz transfer rate of video data. This is slightly tricky, but > not unusual for high end systems. > Roger. Umm, not quite. The TVP3020 does 24-bit video for lower resolutions only. (Aside: just what constitutes "lower resolution" here is unclear, but the news article said less than 1600x1280. It may be that it does support 24-bit true color at 1280x1024.) At 1600x1280 it does 16 bits/pixel, so: 1.3 * 1600x1280 * 70(MHz) = 186Mhz *2* bytes per pixel = 372MB / sec divided by 8 bytes per bus transfer = 47 Mhz transfer frequency which, being smaller, I would expect it to be somewhat easier to manage than a 70Mhz transfer frequency. Of course, I'm still just a software weenie (with a math degree ;-) and don't understand what this really means... Russell Kent -- Texas Instruments rkent@lobby.ti.com -or- PO Box 655012 M/S 3624 kent@tifsim.pac.sc.ti.com Dallas, TX 75265 TI-MSG: RAK9 Voice: (214) 917-2285 FAX: (214) 917-5112 From kent@tifsim.pac.sc.ti.com Fri Nov 19 02:06:38 1993 Received: from ti.com by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA11039; Fri, 19 Nov 1993 09:08:08 -0500 Received: from tifsim.pac.sc.ti.com ([128.247.112.4]) by ti.com with SMTP (5.65c/LAI-3.2) id AA15772; Fri, 19 Nov 1993 08:09:40 -0600 Received: by tifsim.pac.sc.ti.com (5.57/Ultrix3.0-C) id AA17182; Fri, 19 Nov 93 08:07:44 -0600 From: kent@tifsim.pac.sc.ti.com (Russell Kent) Received: by juliet.pac.sc.ti.com id ; Fri, 19 Nov 93 08:06:38 CST Message-Id: <9311191406.AA12837@juliet.pac.sc.ti.com> Subject: Re: L2 Caching and SIMMs format To: riscy@sunsite.unc.edu Date: Fri, 19 Nov 93 8:06:38 CST In-Reply-To: <9311191206.AA05272@maupiti.imag.fr>; from "Daniel Veillard" at Nov 19, 93 7:07 am X-Mailer: ELM [version 2.3 PL11] Daniel Veillard writes: > just a few remarks concerning The Board design : > > - maybe we should put the L2 cache memory management > even if most of us won't use it (SRAM == $$$), in order > to preserve the expandability of the beast. Upgrading > to R4400 without L2 cache may not be very interesting. > - What format of SIMMs will be needed, 36 or 72 bits? > I bet most of us spent much $$$ in 36 bit SIMMs and > would be disapointed if these cannot fit onto their > Super Board. But there is probably a bandwith problem > with 36 bits SIMMs. > > Maybe the HW specialists here could comment on these points, > > Daniel Although I'm not one of the "HW specialists" you've asked for comments, I have been thinking about the whole memory subsystem for a while now. I have the following items to throw out for discussion: 1. The R4200 is a 64-bit data bus. This means either we run 64-bit memory bus or we have bus sizing hardware. Both have their pros and cons: A 64-bit bus means twice as many traces on the board, twice as many signals to glitch in a flakey design, more board real estate for those additional traces, and memory must be either 72-bit SIMMs (less common = more $$) or pairs of 36-bit SIMMs (= more board real estate, and memory must be added in pairs). A 32-bit bus has fewer traces (and therefore fewer of the problems cited above), but it requires bus sizing H/W. Bus sizing H/W is tricky business at 33Mhz and beyond. Plus, it *seriously* slows down the processor if the processor stalls, since *2* memory accesses (at page mode rates) are required for every CPU memory access. On balance, I'd say that a 64-bit data bus is easier to get right, and it should be the higher performing design. 2. Since the R4200 is a 64-bit data bus, then a level 2 cache must be 64-bits wide. This strikes me as being *very* hard to do in a cost-effective manner. 3. If we do without a level 2 cache (see #2), then the next obvious place to try to squeeze more performance is by interleaving the DRAM. Let's see, a 64-bit data bus 2-way interleaved is 128 traces (yuck!), and 4-way interleaved would be 256 traces (har! har! har!). The 2-way (128 trace) interleave is do-able, but I think the 4-way (256 trace) is unreasonable. 4. What about the RAMTRON EDRAM part? (DM 1M36SJ) It uses a JEDEC standard form (= least cost sockets), has a 512x36 integrated cache with a 2Kbit-wide interface to the DRAM (yowza!) so a cache-miss causes a 2048-bit cache fill in a 35ns cycle time. All memory access goes through the integrated cache, so cache coherency between the CPU and any funky DMA peripherals is a non-issue. Cons: - it's a 36-bit part, so they'd need to be added in pairs. - it's not the ubiquitous PC SIMM, so those folks who are/were planning to use PC SIMMs are out-of-luck. (or they run without cache: the RAMTRON DRAM controller handles standard SIMMs, too!) - it is not really a set-associative cache; it only has one working-set. This means that highly localized references win, but random accesses cause cache misses. That last con I think could be a killer. That and the cost of the part. Does anyone have a cost for the EDRAM? I suppose a hybrid 2-way interleaved EDRAM solution could be done, but for that much trouble it seems like a level 2 cache would be no harder, and probably higher performing. Russell Kent -- Texas Instruments rkent@lobby.ti.com -or- PO Box 655012 M/S 3624 kent@tifsim.pac.sc.ti.com Dallas, TX 75265 TI-MSG: RAK9 Voice: (214) 917-2285 FAX: (214) 917-5112 From kent@tifsim.pac.sc.ti.com Fri Nov 19 02:26:05 1993 Received: from ti.com by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA13172; Fri, 19 Nov 1993 09:27:34 -0500 Received: from tifsim.pac.sc.ti.com ([128.247.112.4]) by ti.com with SMTP (5.65c/LAI-3.2) id AA16538; Fri, 19 Nov 1993 08:29:06 -0600 Received: by tifsim.pac.sc.ti.com (5.57/Ultrix3.0-C) id AA17717; Fri, 19 Nov 93 08:27:11 -0600 From: kent@tifsim.pac.sc.ti.com (Russell Kent) Received: by juliet.pac.sc.ti.com id ; Fri, 19 Nov 93 08:26:06 CST Message-Id: <9311191426.AA12916@juliet.pac.sc.ti.com> Subject: Re: TVP3020 To: riscy@sunsite.unc.edu Date: Fri, 19 Nov 93 8:26:05 CST In-Reply-To: <9311191300.AA12693@juliet.pac.sc.ti.com>; from "Russell Kent" at Nov 19, 93 8:17 am X-Mailer: ELM [version 2.3 PL11] Duhhh! Stupid me. Sorry Roger Wolff; I just re-read your posting and my response. I now understand that Roger was calculating what a hypothetical 1600x1280 x 24bit x 70Mhz system would require, *not* what the TVP3020 requires. The TVP3020 can't do 1600x1280 x 24-bits (only x 16-bits at that resolution). I cheerfully pointed out Roger's error (which it wasn't), and then proceeded to calculate what the TVP3020 needs to do 1600x1280 at 16-bits x 70Mhz. Once again, sorry Roger. I rummaged through my riscy archives, and have determined that the TVP3020 seems to be an alternative to the IMS G365 discussed earlier. The IMS G365 is an updated version of the IMS G364 (obsoleted) which is used in the ARC design video board. Can some video hardware specialist determine how (if at all) the TVP3020 is different from the IMS G365 part? I have ordered (as of today) the TVP3020 data manual from T.I. Russell Kent Texas Instruments rkent@lobby.ti.com -or- PO Box 655012 M/S 3624 kent@tifsim.pac.sc.ti.com Dallas, TX 75265 TI-MSG: RAK9 Voice: (214) 917-2285 FAX: (214) 917-5112 From popiel@hollerith.Colorado.EDU Fri Nov 19 00:39:28 1993 Received: from boulder.Colorado.EDU by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA14399; Fri, 19 Nov 1993 09:39:37 -0500 Received: from hollerith.Colorado.EDU by boulder.Colorado.EDU with SMTP id AA03158 (5.65c/IDA-1.4.4 for ); Fri, 19 Nov 1993 07:39:35 -0700 Received: by hollerith.colorado.edu (cu.generic.890828) Message-Id: <9311191439.AA18273@hollerith.colorado.edu> To: riscy@sunsite.unc.edu Cc: popiel@hollerith.Colorado.EDU Subject: Re: Hideous mailing list software In-Reply-To: Your message of "Fri, 19 Nov 93 00:56:12 EST." <199311190554.WAA06563@kinglear.cs.Colorado.EDU> Date: Fri, 19 Nov 93 07:39:28 -0700 From: popiel@hollerith.Colorado.EDU X-Mts: smtp In message: <199311190554.WAA06563@kinglear.cs.Colorado.EDU> Drew Eckhardt writes: > >(ie, drew@colorado.edu doesn't go to a real machine) -------- Um - colorado.edu does to to a real machine: bruno.cs.colorado.edu. Otherwise it would not work. - Alex From hp@quasi.vmars.tuwien.ac.at Fri Nov 19 10:02:51 1993 Received: from quasi.vmars.tuwien.ac.at by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA16673; Fri, 19 Nov 1993 10:02:51 -0500 Received: by quasi.vmars.tuwien.ac.at id AA08655 (5.64+/IDA-1.3.4 for riscy@sunsite.unc.edu); Fri, 19 Nov 93 16:02:19 +0100 From: Peter Holzer Message-Id: <9311191502.AA08655@quasi.vmars.tuwien.ac.at> Subject: Re: L2 Caching and SIMMs format To: riscy@sunsite.unc.edu Date: Fri, 19 Nov 93 16:02:18 MET In-Reply-To: <9311191406.AA12837@juliet.pac.sc.ti.com>; from "Russell Kent" at Nov 19, 93 9:13 am Reply-To: hp@vmars.vmars.tuwien.ac.at X-Return-Receipt-To: hp@vmars.tuwien.ac.at X-Mailer: ELM [version 2.3 PL5] You (Russell Kent) wrote: > > 4. What about the RAMTRON EDRAM part? (DM 1M36SJ) It uses a JEDEC > standard form (= least cost sockets), has a 512x36 integrated > cache with a 2Kbit-wide interface to the DRAM (yowza!) so a > cache-miss causes a 2048-bit cache fill in a 35ns cycle time. > All memory access goes through the integrated cache, so cache > coherency between the CPU and any funky DMA peripherals is a > non-issue. > Cons: - it's a 36-bit part, so they'd need to be added in pairs. > - it's not the ubiquitous PC SIMM, so those folks who > are/were planning to use PC SIMMs are out-of-luck. > (or they run without cache: the RAMTRON DRAM controller > handles standard SIMMs, too!) > - it is not really a set-associative cache; it only has one > working-set. This means that highly localized references > win, but random accesses cause cache misses. > > That last con I think could be a killer. That and the cost of > the part. Does anyone have a cost for the EDRAM? 35ns is still almost twice as fast as normal dram. If this is really the cache-miss time this part sounds very interesting. I'm getting really curious about its cost. hp -- _ | hp@vmars.tuwien.ac.at | Peter Holzer | TU Vienna | CS/Real-Time Systems |_|_) |------------------------------------------------------------------------ | | | ...and it's finished! It only has to be written. __/ | -- Karl Lehenbauer From wolff@dutecai.et.tudelft.nl Fri Nov 19 17:15:15 1993 Received: from dutecai.et.tudelft.nl by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA17882; Fri, 19 Nov 1993 10:16:24 -0500 Received: by dutecai.et.tudelft.nl (4.1/1.34JP) id AA20772; Fri, 19 Nov 93 16:15:16 +0100 From: wolff@dutecai.et.tudelft.nl (Rogier Wolff) Message-Id: <9311191515.AA20772@dutecai.et.tudelft.nl> Subject: Re: TVP3020 To: riscy@sunsite.unc.edu Date: Fri, 19 Nov 1993 16:15:15 +0100 (MET) In-Reply-To: <9311191426.AA12916@juliet.pac.sc.ti.com> from "Russell Kent" at Nov 19, 93 09:28:52 am X-Mailer: ELM [version 2.4 PL21] Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 964 > > Duhhh! Stupid me. Sorry Roger Wolff; I just re-read your posting and No problem. (I don't see what went wrong but oh well..... :-) > > I rummaged through my riscy archives, and have determined that the > TVP3020 seems to be an alternative to the IMS G365 discussed earlier. > The IMS G365 is an updated version of the IMS G364 (obsoleted) which > is used in the ARC design video board. Can some video hardware ^^^^^^^^^^^^^^^ > specialist determine how (if at all) the TVP3020 is different from the ^^^^^^^^^^^^^ > IMS G365 part? Ah.. That's me.. :-) [now where's that F....ing Gxxx manual.... ahhh there it is....] The G365 is the high end of the G3xx color video controllers. It has a max bandwidth of 135 Mhz. Otherwise is seems to have more or less the same specs as the TVP3020. I'll be willing to answer any questions about the G364 or G365 that you may have. Roger. From tthorn@daimi.aau.dk Fri Nov 19 17:22:35 1993 Received: from avignon.daimi.aau.dk by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA18554; Fri, 19 Nov 1993 10:22:42 -0500 Received: by avignon.daimi.aau.dk id AA08663 (5.65c8/IDA-1.4.4 for riscy@sunsite.unc.edu); Fri, 19 Nov 1993 16:22:35 +0100 Date: Fri, 19 Nov 1993 16:22:35 +0100 From: Tommy Thorn Message-Id: <199311191522.AA08663@avignon.daimi.aau.dk> To: riscy@sunsite.unc.edu Subject: Re: L2 Caching and SIMMs format References: <9311191406.AA12837@juliet.pac.sc.ti.com> Reply-To: Tommy.Thorn@daimi.aau.dk As Andreas has already said zillions of times, he would prefer using an existing design. The best bet yet, the riscWS/EISA (aka NEC ARCset 100) doesn't include a secondary cache. There is really little point in discussion such details before we have the specs. for the riscWS design. For those who join in recently, here is a report of the features of riscWS/EISA: Andy writes: > But perhaps we still are confused by some technical things. > I'll summarize what my favourite design (NEC ARCset 100 or > MTI riscWS/EISA, these are the same) is: > > - intended for a R4000PC/50. > - On board SCSI, Floppy Controller, Ethernet Controller (AUI), > 2 serial and 1 parallel port. > - 4 free EISA slots. > - Audio and mouse subsystem (serial #3) on an optional card (not EISA). > - Video on an optional card (not EISA). > - max. 128 MB Ram, two-way interleaved. > > We probably have the chance to use CPU modules without changing > the board design, which is a *very* important issue. -- Tommy.Thorn@daimi.aau.dk Staff-programmer Aarhus University, Ny Munkegade 116 Phone: +45 89423223 DK-8000 Aarhus C, Denmark. Fax: +45 86135725 PGP Public Key fingerprint: E7B1175FC30D9E96B67AF61D89A70A1F From tor@tss.no Fri Nov 19 17:17:57 1993 Received: from benoni.Uit.No by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA18920; Fri, 19 Nov 1993 10:26:59 -0500 Received: from benoni by ppenoni.uit.no with SMTP (PP) id <12477-0@ppenoni.uit.no>; Fri, 19 Nov 1993 16:26:29 +0000 Received: from unas.tss.no by benoni.uit.no (5.65+IDA/Babel-1.15/ABaa-1.2/Ultrix) id AAbenoni12473; Fri, 19 Nov 1993 16:26:25 +0100 Received: by unas.tss.no (4.0/ABaa-1.3mini) id AA25586; Fri, 19 Nov 93 16:17:58 +0100 Message-Id: <9311191517.AA25586@unas.tss.no> From: tor@tss.no (Tor Arntsen) Date: Fri, 19 Nov 1993 16:17:57 +0100 In-Reply-To: Drew Eckhardt "Re: riscy status?" (Nov 19, 2:07am) X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: riscy@sunsite.unc.edu Subject: Re: riscy status? Cc: d@unas.tss.no On Nov 19, 2:07am, Drew Eckhardt wrote: [...] >No one would commit to the 53cf94 even though no better alternative >had been proposed and the price and complexity difference between it >and NCR busmasters is significant (the later is a microcontroller, >meaning you have to write an assembler for it and debugging is >nastier, the 53c700/800 series are also closer to $60 in the >same quantities that the NCR53cf94 is $25, and you won't get any >better throughput with the increased costs). The NCR53cx9x series looks like the very best alternative IMHO. Of those the NCR53cf94 seems to be a good choice. Tor (tor@spacetec.no) From vince@cardiothoracic.ucsf.edu Sat Nov 20 04:42:20 1993 Received: from cardiothoracic.ucsf.EDU by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA05926; Fri, 19 Nov 1993 12:44:15 -0500 Received: by cardiothoracic.ucsf.edu (MX V3.3 VAX) id 6478; Sat, 20 Nov 1993 09:42:22 EST Date: Sat, 20 Nov 1993 09:42:20 EST From: vince@cardiothoracic.ucsf.edu To: riscy@sunsite.unc.edu Message-Id: <00975D12.01E3A640.6478@cardiothoracic.ucsf.edu> Subject: RE: L2 Caching and SIMMs format Daniel, Maybe you missed a post I made about a week or so ago. A company called ramtron makes 72 pin simms with the sram cache integrated into the simms. The sisimms have some cahche cohernecy function built in, but for best use, a new simmcontroller module is needed. These simms have quite a few advantages over standard simms; maximum access time of 35ns, with a minimum access time of 15ns.Board space and circuitry for a separate L2 cache can be eliminated. A board thTtakes these simms could still accept standard 72 pin simms. All memory added to the system is cached(with most systems, only the first 64mb is cachable). The simms cost less than the simm/sram combo they replace. And of course the most important advantage is that the system can run much faster with memory so fast. :) The disadvantage? The cost more than regular simms. (I can't remember by how much... I believe around 20-30% though.) Vince Reed UCSF Cardiothoracic Surgery vince@cardiothoracic.ucsf.edu From broadley@neurocog.lrdc.pitt.edu Fri Nov 19 08:47:04 1993 Received: from neurocog.lrdc.pitt.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA12976; Fri, 19 Nov 1993 13:47:05 -0500 Received: from localhost (broadley@localhost) by neurocog.lrdc.pitt.edu (8.6.4/8.6.4) id NAA09756 for riscy@sunsite.unc.edu; Fri, 19 Nov 1993 13:47:04 -0500 From: Bill Broadley Message-Id: <199311191847.NAA09756@neurocog.lrdc.pitt.edu> Subject: Cache, Simms, design etc. To: riscy@sunsite.unc.edu Date: Fri, 19 Nov 1993 13:47:04 -0500 (EST) X-Mailer: ELM [version 2.4 PL21] Content-Type: text Content-Length: 1089 I pinged a ram vendor and got the following prices: 4 MB x 9 bit 70 ns $128 each (min order 40) 1 MB x 35 bit 70 ns $149 each If anyone actually wants to use ramtron simms they should post a price on 50 pieces or so. Anyone have a contact at mips to find out about the announced reference designs? I suspect that they include a L2 cache which makes alot of the recent discussion irrelevant. The specnumbers for the 4200 were reached with a cheap 486'ish 256k cache. I want a fast box as much as the next guy but we should plan very minor modifications to any design that the group purchases. If we can't find a design with an L2 cache we should just do the best we can without one. BTW I'm all for Eric's development of the NCR scsi board, but I'm not in the position to guarentee that his work will be used can we reach a concensus?? Or at least Andy's support??? -- Bill 1st> Broadley@neurocog.lrdc.pitt.edu Broadley@schneider3.lrdc.pitt.edu <2nd 3rd> Broadley+@pitt.edu Linux is great. Bike to live, live to bike. PGP-ok From jcallen@Think.COM Fri Nov 19 09:03:30 1993 Received: from Mail.Think.COM by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA15291; Fri, 19 Nov 1993 14:03:54 -0500 Received: from Luna.Think.COM by mail.think.com; Fri, 19 Nov 93 14:03:32 -0500 From: Jerry Callen Received: by luna.think.com (4.1/Think-1.2) id AA02591; Fri, 19 Nov 93 14:03:30 EST Date: Fri, 19 Nov 93 14:03:30 EST Message-Id: <9311191903.AA02591@luna.think.com> To: broadley@neurocog.lrdc.pitt.edu Cc: riscy@sunsite.unc.edu In-Reply-To: Bill Broadley's message of Fri, 19 Nov 1993 13:49:31 -0500 <199311191847.NAA09756@neurocog.lrdc.pitt.edu> Subject: Cache, Simms, design etc. Date: Fri, 19 Nov 1993 13:49:31 -0500 From: Bill Broadley I pinged a ram vendor and got the following prices: 4 MB x 9 bit 70 ns $128 each (min order 40) 1 MB x 35 bit 70 ns $149 each ^^^^^^ 35 bit?!? Maybe 36? -- Jerry Callen jcallen@world.std.com (preferred) jcallen@think.com (OK, too) {uunet,harvard}!think!jcallen (if you must) From jem Fri Nov 19 10:07:50 1993 Received: by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) id AA25071; Fri, 19 Nov 1993 15:09:16 -0500 Date: Fri, 19 Nov 1993 15:07:50 -0500 (EST) From: Jonathan Magid Subject: list software To: riscy@SunSite.unc.edu Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII We have changed the list to accept messages from non-subscribers. If you have further problems and/or complaints you can send them to me.. there is no need for bile. cheers, jem. From tim@ubitrex.mb.ca Fri Nov 19 09:35:17 1993 Received: from ubitrex.mb.ca (ubiserver.ubitrex.mb.ca) by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA06942; Fri, 19 Nov 1993 16:35:20 -0500 Received: from ska.ubitrex.mb.ca ([192.75.16.23]) by ubitrex.mb.ca (4.1/SMI-4.1) id AA24503; Fri, 19 Nov 93 15:35:17 CST Date: Fri, 19 Nov 93 15:35:17 CST From: tim@ubitrex.mb.ca (Tim Braun) Message-Id: <9311192135.AA24503@ubitrex.mb.ca> To: riscy@SunSITE.Unc.EDU Subject: Re: NCR 53cf94 scsi by Eric It looks like this chip fits our requirements, I say "let Eric begin." ________________________________________________________________ Tim Braun | Ubitrex Corporation | Voice: 204-942-2992 ext 228 1900-155 Carlton St | FAX: 204-942-3001 Winnipeg, Manitoba, Canada R3C 3H8 | Email: tim@ubitrex.mb.ca From ksh@charybdis.prl.ufl.edu Fri Nov 19 12:10:54 1993 Received: from charybdis.prl.ufl.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA00772; Fri, 19 Nov 1993 17:09:36 -0500 Received: by charybdis.prl.ufl.edu (4.1/1.34) id AA20495; Fri, 19 Nov 93 17:10:54 EST Date: Fri, 19 Nov 93 17:10:54 EST From: ksh@charybdis.prl.ufl.edu (Kevin S Ho) Message-Id: <9311192210.AA20495@charybdis.prl.ufl.edu> To: riscy@sunsite.unc.edu Subject: Re: L2 Caching and SIMMs format I still say we go with a 64 bit data bus, plan for the future. KsH From Steven.D.Ligett@Dartmouth.EDU Thu Nov 21 17:02:46 1993 Received: from coos.dartmouth.edu by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA28919; Sun, 21 Nov 1993 22:03:45 -0500 Received: by coos.dartmouth.edu (5.65/DEC-Ultrix/4.3) id AA22815; Sun, 21 Nov 1993 22:02:44 -0500 Message-Id: <7695313@prancer.Dartmouth.EDU> Date: 21 Nov 93 22:02:46 EST From: Steven.D.Ligett@Dartmouth.EDU (Steven D. Ligett) Subject: SCSI chips To: tor@tss.no, riscy@sunsite.unc.edu (Multiple recipients of list) --- tor@tss.no (Tor Arntsen) wrote: The NCR53cx9x series looks like the very best alternative IMHO. Of those the NCR53cf94 seems to be a good choice. --- end of quoted material --- I have no source for NCR parts. Is there a second source for this? I know that AMD makes the 53c94, and I can get AMD parts. Note that the 53c(f)96 might also be considered; it's essentially the same part though it's capable of differential output, and comes in a smaller, 100 pin package. From andy@waldorf-gmbh.de Wed Nov 24 11:32:07 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA22052; Wed, 24 Nov 1993 04:40:30 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id TG17495; Wed, 24 Nov 1993 10:41:16 +0100 Received: from resi From: Andreas Busse Date: Wed, 24 Nov 93 10:32:07 +0100 Message-Id: <9311240932.AA09173@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA09173; Wed, 24 Nov 93 10:32:07 +0100 To: riscy@sunsite.unc.edu Subject: PING... Cc: andy@resi.waldorf-gmbh.de I wonder if there's still activity on the list. I haven't received any messages since a couple of days. Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From tthorn@daimi.aau.dk Wed Nov 24 12:16:32 1993 Received: from avignon.daimi.aau.dk by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA24335; Wed, 24 Nov 1993 05:16:41 -0500 Received: by avignon.daimi.aau.dk id AA01413 (5.65c8/IDA-1.4.4 for riscy@sunsite.unc.edu); Wed, 24 Nov 1993 11:16:32 +0100 Date: Wed, 24 Nov 1993 11:16:32 +0100 From: Tommy Thorn Message-Id: <199311241016.AA01413@avignon.daimi.aau.dk> To: riscy@sunsite.unc.edu Subject: Re: PING... Reply-To: Tommy.Thorn@daimi.aau.dk Andreas Busse writes: > I wonder if there's still activity on the list. > I haven't received any messages since a couple of days. I assume people, like me, are holding their breath waiting. The news from COMDEX sounds very promissing. I hope our design won't differ to much from what others are doing, 'course I'd would simply *love* to buy a r4200 based notebook in some future. Just to comment a *very* **very** old discussion on endian: It seems, contrary to what was said at some point, that we actually *can* switch endian more-or-less on the fly. p. 5-6 in R4000 User's Manual the status register is described. Bit RE: Reverse Endian in User Mode: "The Reverse Endian (RE) bit, bit 25, is used to reverse the endianness of the machine in User mode. R-Series processors are configured as either Little-endian or Big-endian at system reset. This selection is used in Kernel and Supervisor modes, and in the User mode when the RE bit is 0; setting this bit to 1 inverts the selection in User mode." What endian is selected at reset on motherboards targeted at Win-NT? From Daniel.Veillard@imag.fr Wed Nov 24 12:51:10 1993 Received: from imag.imag.fr by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AB26770; Wed, 24 Nov 1993 05:51:14 -0500 Received: from maupiti.imag.fr by imag.imag.fr with SMTP id AA08415 (5.65c8/IDA-1.4.4 for ); Wed, 24 Nov 1993 11:48:40 +0100 Received: by maupiti.imag.fr (5.65/5.17) id AA26107; Wed, 24 Nov 1993 11:51:11 +0100 From: Daniel.Veillard@imag.fr (Daniel Veillard) Message-Id: <9311241051.AA26107@maupiti.imag.fr> To: tthorn@daimi.aau.dk Cc: Multiple recipients of list Subject: Re: PING... In-Reply-To: Your message of "Wed, 24 Nov 93 05:19:10 EST." <199311241016.AA01413@avignon.daimi.aau.dk> Date: Wed, 24 Nov 93 11:51:10 +0100 >Just to comment a *very* **very** old discussion on endian: >It seems, contrary to what was said at some point, that we actually >*can* switch endian more-or-less on the fly. > >p. 5-6 in R4000 User's Manual the status register is described. >Bit RE: Reverse Endian in User Mode: > "The Reverse Endian (RE) bit, bit 25, is used to reverse the endianness > of the machine in User mode. R-Series processors are configured as > either Little-endian or Big-endian at system reset. This selection is > used in Kernel and Supervisor modes, and in the User mode when the > RE bit is 0; setting this bit to 1 inverts the selection in User mode." > >What endian is selected at reset on motherboards targeted at Win-NT? Win-NT HAL set the R4000 in little endian mode (presumably to provide better interroperability with PC based Windows), while UNIX implementation usually put the board in big endian mode :-) . Using the RE bit seems tricky since you have an user application running little endian and the OS (in Kernel and Supervisor space) running big endian. Each system call should be checked to change the endianness of the parameters if needed ! my 2 centimes (approx 0.003 $), Daniel From andy@waldorf-gmbh.de Wed Nov 24 13:24:29 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA29426; Wed, 24 Nov 1993 06:30:11 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id TJ23775; Wed, 24 Nov 1993 12:30:57 +0100 Received: from resi From: Andreas Busse Date: Wed, 24 Nov 93 12:24:29 +0100 Message-Id: <9311241124.AA09565@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA09565; Wed, 24 Nov 93 12:24:29 +0100 To: riscy@sunsite.unc.edu Subject: Listserver Seems the listserver has a new bug: Date: Wed, 24 Nov 1993 05:51:38 -0500 Errors-To: caret@c-side.com Reply-To: Daniel.Veillard@imag.fr ^^^^^^^^^^^^^^^^^^^^^^^ shouldn't it be riscy@sunsite.unc.edu ??? Originator: riscy@sunsite.unc.edu Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From andy@waldorf-gmbh.de Wed Nov 24 13:21:01 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA29447; Wed, 24 Nov 1993 06:30:26 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id TJ23742; Wed, 24 Nov 1993 12:30:49 +0100 Received: from resi From: Andreas Busse Date: Wed, 24 Nov 93 12:21:01 +0100 Message-Id: <9311241121.AA09552@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA09552; Wed, 24 Nov 93 12:21:01 +0100 To: tthorn@daimi.aau.dk Subject: Re: PING... Cc: riscy@sunsite.unc.edu > I assume people, like me, are holding their breath waiting. > The news from COMDEX sounds very promissing. I hope our design > won't differ to much from what others are doing, 'course I'd > would simply *love* to buy a r4200 based notebook in some future. Well, I just had the feeling that I was removed from the list :-) A few minutes ago I sent a reminder to the guy at MTI. I hope I'll get some specs these days. I don't expect the riscWS/EISA to be very different to other designs since it is ARC (Advanced Risc Computing) compliant. Perhaps you remember: In 1991 MIPS founded the ACE initiative whose goal was to build R4xxx boards on which RiscOS (Mips-Unix), SCO ODT and Windows NT should run. Well, ACE is down the tubes but Windows NT is still there (better: coming now). > Just to comment a *very* **very** old discussion on endian: > It seems, contrary to what was said at some point, that we actually > *can* switch endian more-or-less on the fly. Yes and no. When I remember right, switching on the fly has some disadvantages, but together with the board design comes a config disk which lets you select between big- (RiscOS, Irix) and little (Windows NT) endian. > What endian is selected at reset on motherboards targeted at Win-NT? See above. Cheers, Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From atk@agua.colorado.edu Tue Nov 23 21:33:15 1993 Received: from boulder.Colorado.EDU by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA29655; Wed, 24 Nov 1993 06:33:26 -0500 Received: from agua.Colorado.EDU by boulder.Colorado.EDU with SMTP id AA05524 (5.65c/IDA-1.4.4 for ); Wed, 24 Nov 1993 04:33:16 -0700 Received: by agua.colorado.edu (cu.generic.890828) Date: Wed, 24 Nov 93 04:33:15 MST From: Alan Krantz Message-Id: <9311241133.AA10744@agua.colorado.edu> To: riscy@sunsite.unc.edu Subject: R4600 This might be interest - byte (this dec issue) had a brief descripton of the R4600. It is currently being sold, is pin compat with R4400, has spec int and float point > 60 and is around $230 in quantities of 1000. atk From andy@waldorf-gmbh.de Thu Nov 25 18:31:38 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA15553; Thu, 25 Nov 1993 11:40:39 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id VA07095; Thu, 25 Nov 1993 17:41:26 +0100 Received: from resi From: Andreas Busse Date: Thu, 25 Nov 93 17:31:38 +0100 Message-Id: <9311251631.AA00819@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA00819; Thu, 25 Nov 93 17:31:38 +0100 To: riscy@sunsite.unc.edu Subject: NEWS Hi there ! I just received a license contract from MTI US regarding the riscWS/EISA design. The guy at MTI promised me to send a part list these days. As soon I've got it I'll post a summary. In advance, here's what the kit includes: - Board specs - Bill of materials (what I'm waiting for) - Design database (netlist) - Gerber tape - PLD equations - Fab drawing - Assembly drawing - riscWS/EISA firmware - Boot PROM binaries For some extra $$$ we can buy the Boot PROM and firmware sources, but I doubt that I can distribute them (no GPL...) Cheers, Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From jem Sun Nov 28 17:26:42 1993 Received: by SunSITE.unc.edu (SMI4.1/FvK 1.02) id AA00226; Sun, 28 Nov 93 17:26:42 EST Date: Sun, 28 Nov 93 17:26:42 EST From: "Jonathan Magid" Message-Id: <9311282226.AA00226@SunSITE.unc.edu> To: riscy@sunsite.unc.edu Subject: testing test. From andy@waldorf-gmbh.de Mon Nov 29 10:14:34 1993 Received: from mail.Germany.EU.net by SunSITE.unc.edu (SMI4.1/FvK 1.02) id AA24851; Mon, 29 Nov 93 10:14:34 EST Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id cD04632; Mon, 29 Nov 1993 16:15:22 +0100 Received: from resi From: Andreas Busse Date: Mon, 29 Nov 93 10:09:23 +0100 Message-Id: <9311290909.AA03369@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA03369; Mon, 29 Nov 93 10:09:23 +0100 To: riscy@sunsite.unc.edu Subject: Board specs Hi there ! Since riscy had some trouble again for some days, I'll try to post this the third time now: ----------- Oh, I've found the board specs somewhere in the fax from MTI: The kit includes *both* PC and SC designs. riscWS/EISA System Specifications: CPU: R4000PC/SC or R4400PC/SC I/D Cache: 8k/16k on chip Sec. Cache: 1 MB external with R4000SC/R4400SC CPU/Cache Bandwidth: 800 MB/sec Cache/Memory BW (read): 84 MB/sec Cache/Memory BW (write): 104 MB/sec Audio I/O: stereo Mouse/Keyboard: PC compatible DMA transfer rate: 40 MB/sec SCSI II Controller: 10 MB/sec Ethernet Controller: 1.25 MB/sec Power Dissipation: 55 Watts Video Resolution: 1280x1024 No. of colors: 256 Video Bandwith: 66 MB/sec Hope this helps, Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From rj_ingra@pat.uwe-bristol.ac.uk Mon Nov 29 11:35:24 1993 Received: from sun2.nsfnet-relay.ac.uk by SunSITE.unc.edu (SMI4.1/FvK 1.02) id AA02935; Mon, 29 Nov 93 11:35:24 EST Via: uk.ac.uwe-bristol.pat; Mon, 29 Nov 1993 15:49:36 +0000 From: RJ Ingram Date: Mon, 29 Nov 93 15:51:00 GMT Message-Id: <14499.9311291551@pat.uwe.ac.uk> To: riscy@sunsite.unc.edu Subject: Re: Board specs Hi ! Now andy@de.waldorf-gmbh has the MTI board specs does this mean we may be approaching the point of getting a concrete start date for board design/manufacture ? I'll be losing my net connection on 17th December for a while so any news would be great ? Thanks. Rich From andy@waldorf-gmbh.de Mon Nov 29 11:47:56 1993 Received: from mail.Germany.EU.net by SunSITE.unc.edu (SMI4.1/FvK 1.02) id AA04633; Mon, 29 Nov 93 11:47:56 EST Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id cF10394; Mon, 29 Nov 1993 17:48:45 +0100 Received: from resi From: Andreas Busse Date: Mon, 29 Nov 93 17:48:04 +0100 Message-Id: <9311291648.AA03936@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA03936; Mon, 29 Nov 93 17:48:04 +0100 To: riscy@sunsite.unc.edu Subject: Re: Board specs Hi ! > Now andy@de.waldorf-gmbh > has the MTI board specs does this mean we may be approaching the point of > getting a concrete start date for board design/manufacture ? Yes, I think we are approaching the point of a concrete board production (not design, since it is already designed). > I'll be losing my net connection on 17th December for a while so any > news would be great ? As soon I have news, I'll let you know. Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From amoss@cs.huji.ac.il Mon Nov 29 14:24:26 1993 Received: from cs.huji.ac.il by SunSITE.unc.edu (SMI4.1/FvK 1.02) id AA22370; Mon, 29 Nov 93 14:24:26 EST Received: from picton.cs.huji.ac.il by cs.huji.ac.il with SMTP id AA28464 (5.65c/HUJI 4.144 for riscy@sunsite.unc.edu); Mon, 29 Nov 1993 21:23:59 +0200 Received: from localhost by picton.cs.huji.ac.il with SMTP id AA00528 (5.65c/HUJI 4.1 for riscy@sunsite.unc.edu); Mon, 29 Nov 1993 21:24:07 +0200 Message-Id: <199311291924.AA00528@picton.cs.huji.ac.il> To: andy@waldorf-gmbh.de Cc: riscy@sunsite.unc.edu Subject: Re: Board specs In-Reply-To: Your message of Mon, 29 Nov 93 10:16:25 EST . <9311290909.AA03369@resi.waldorf-gmbh.de> From: Amos Shapira Date: Mon, 29 Nov 1993 21:24:02 +0200 Sender: amoss@CS.HUJI.AC.IL In message <9311290909.AA03369@resi.waldorf-gmbh.de> you write: |Oh, I've found the board specs somewhere in the fax from MTI: | |The kit includes *both* PC and SC designs. | |riscWS/EISA System Specifications: | |CPU: R4000PC/SC or R4400PC/SC |I/D Cache: 8k/16k on chip |Sec. Cache: 1 MB external with R4000SC/R4400SC |CPU/Cache Bandwidth: 800 MB/sec |Cache/Memory BW (read): 84 MB/sec |Cache/Memory BW (write): 104 MB/sec |Audio I/O: stereo |Mouse/Keyboard: PC compatible |DMA transfer rate: 40 MB/sec |SCSI II Controller: 10 MB/sec |Ethernet Controller: 1.25 MB/sec |Power Dissipation: 55 Watts |Video Resolution: 1280x1024 |No. of colors: 256 |Video Bandwith: 66 MB/sec Sounds terrific! *I* am satisfied with this setup (btw, what Mhz is it? Is it restricted to 50Mhz(R4000)/100Mhz(R4400) like the Indigo's or what?). So what's the next step? |Hope this helps, Surely helped my morale :) Bye, --Amos --Amos Shapira (Jumper Extraordinaire) | "War does not determine who is right, C.S. System Group, Hebrew University, | but who is left" Jerusalem 91904, ISRAEL | amoss@cs.huji.ac.il | -- Anonymous? From bergstro@src.honeywell.com Mon Nov 29 14:45:03 1993 Received: from src.honeywell.com (moon.src.honeywell.com) by SunSITE.unc.edu (SMI4.1/FvK 1.02) id AA24792; Mon, 29 Nov 93 14:45:03 EST Return-Path: Received: from data.src.honeywell.com by src.honeywell.com (4.1/smail2.6.3/SRCv0.25); Mon, 29 Nov 93 13:44:57 CST id AA12847 for riscy@sunsite.unc.edu at sunsite.unc.edu Posted-Date: Mon, 29 Nov 93 13:44:54 CST Received: by data.src.honeywell.com (4.1/SMI-3.2) id AA11947; Mon, 29 Nov 93 13:44:54 CST Date: Mon, 29 Nov 93 13:44:54 CST From: bergstro@src.honeywell.com (Pete Bergstrom) Message-Id: <9311291944.AA11947@data.src.honeywell.com> To: riscy@sunsite.unc.edu Subject: Ballpark cost for MIPS board? I've been folowing the discussion for a couple of months now and would very much like to know if there is a current target price for the board? The capabilities of the design recently posted look very good, but I'd like some sort of idea of what everyone expects to pay to get one of these (I know - if you have to ask, you can't afford it). Thanks, Pete From andy@waldorf-gmbh.de Tue Nov 30 10:43:43 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA07220; Tue, 30 Nov 1993 03:44:07 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id dB11296; Tue, 30 Nov 1993 09:44:24 +0100 Received: from resi From: Andreas Busse Date: Tue, 30 Nov 93 09:43:43 +0100 Message-Id: <9311300843.AA04887@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA04887; Tue, 30 Nov 93 09:43:43 +0100 To: amoss@cs.huji.ac.il, andy@waldorf-gmbh.de Subject: Re: Board specs Cc: riscy@sunsite.unc.edu > *I* am satisfied with this setup (btw, what Mhz is it? Is it restricted > to 50Mhz(R4000)/100Mhz(R4400) like the Indigo's or what?). I guess so, since the chipset is limited to 50 MHz. It might be possible to run the cpu faster, but I can't promise that since I don't have schematics yet. > So what's the next step? Waiting for the partlist, then making a cost estimation. > |Hope this helps, > > Surely helped my morale :) It was meant as this :-) Cheers, Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From andy@waldorf-gmbh.de Tue Nov 30 11:15:10 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA08613; Tue, 30 Nov 1993 04:15:03 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id dC13322; Tue, 30 Nov 1993 10:15:50 +0100 Received: from resi From: Andreas Busse Date: Tue, 30 Nov 93 10:15:10 +0100 Message-Id: <9311300915.AA04982@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA04982; Tue, 30 Nov 93 10:15:10 +0100 To: riscy@sunsite.unc.edu Subject: Don't reply !! This is just something administrative: Since the riscy listprocessor generates Reply-To: lines with the address of the original sender, a reply will ***not*** go to the list again. Please don't reply to messages, use the "mail" or whatever command instead. Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From andy@waldorf-gmbh.de Tue Nov 30 11:13:26 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA08643; Tue, 30 Nov 1993 04:15:43 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id dC13251; Tue, 30 Nov 1993 10:14:05 +0100 Received: from resi From: Andreas Busse Date: Tue, 30 Nov 93 10:13:26 +0100 Message-Id: <9311300913.AA04973@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA04973; Tue, 30 Nov 93 10:13:26 +0100 To: riscy@sunsite.unc.edu Subject: Re: Ballpark cost for MIPS board? > I've been folowing the discussion for a couple of months now and would very > much like to know if there is a current target price for the board? > > The capabilities of the design recently posted look very good, but I'd like > some sort of idea of what everyone expects to pay to get one of these (I > know - if you have to ask, you can't afford it). I can't tell you at the moment. All I can say is (this hasn't changed) that Waldorf will not produce the board to make profit. That means that the board will be less expensive than every other R4000 board you can buy, but I don't know *how* cheap. Since we are licensing a design from a company which is interested to see their licensees making profit (no other way to make the mips architecture interesting) we will have to make a special deal with the riscy members, a kind of "developer agreement". Cheers, Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From wolff@liberator.et.tudelft.nl Tue Nov 30 14:07:59 1993 Received: from liberator.et.tudelft.nl by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA16258; Tue, 30 Nov 1993 07:08:35 -0500 Received: by liberator.et.tudelft.nl (4.1/1.34JP) id AA07400; Tue, 30 Nov 93 13:08:04 +0100 From: wolff@liberator.et.tudelft.nl (Rogier Wolff) Message-Id: <9311301208.AA07400@liberator.et.tudelft.nl> Subject: Re: Board specs To: andy@waldorf-gmbh.de Date: Tue, 30 Nov 1993 13:07:59 +0100 (MET) Cc: riscy@sunsite.unc.edu In-Reply-To: <9311290909.AA03369@resi.waldorf-gmbh.de> from "Andreas Busse" at Nov 29, 93 10:16:25 am X-Mailer: ELM [version 2.4 PL21] Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 180 > > Video Resolution: 1280x1024 > No. of colors: 256 > Video Bandwith: 66 MB/sec You won't get an acceptable 1280x1024 at 66Mb/sec. (at most 4 bits per pixel) Roger. From andy@waldorf-gmbh.de Tue Nov 30 14:24:40 1993 Received: from mail.Germany.EU.net by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA17353; Tue, 30 Nov 1993 07:24:37 -0500 Received: by mail.Germany.EU.net(EUnetD-2.3.0.j) via EUnet id dI21825; Tue, 30 Nov 1993 13:25:17 +0100 Received: from resi From: Andreas Busse Date: Tue, 30 Nov 93 13:24:40 +0100 Message-Id: <9311301224.AA05298@resi.waldorf-gmbh.de> Received: by resi.waldorf-gmbh.de (5.61/GEN-1.0.7) via EUnet for scotty.waldorf-gmbh.de id AA05298; Tue, 30 Nov 93 13:24:40 +0100 To: riscy@sunsite.unc.edu Subject: Re: Board specs > You won't get an acceptable 1280x1024 at 66Mb/sec. (at most 4 bits per pixel) The specs don't say wether this is the pixel rate or the transfer rate into the video ram. I guess it's the transfer rate, what do you think ? Andy ------------------------------------------------------------------------------- Waldorf Electronics GmbH | Phone: +49 (0)2636-80294 R&D Department | Fax: +49 (0)2636-80188 Neustrasse 9-12, 53498 Waldorf, Germany | email: andy@waldorf-gmbh.de ------------------------------------------------------------------------------- From hp@quasi.vmars.tuwien.ac.at Tue Nov 30 07:34:09 1993 Received: from quasi.vmars.tuwien.ac.at by SunSITE.Unc.EDU (5.65c+IDA/FvK-1.06) with SMTP id AA17892; Tue, 30 Nov 1993 07:34:09 -0500 Received: by quasi.vmars.tuwien.ac.at id AA05764 (5.64+/IDA-1.3.4 for riscy@sunsite.unc.edu); Tue, 30 Nov 93 13:33:56 +0100 From: Peter Holzer Message-Id: <9311301233.AA05764@quasi.vmars.tuwien.ac.at> Subject: Re: Board specs To: riscy@sunsite.unc.edu Date: Tue, 30 Nov 93 13:33:55 MET In-Reply-To: <9311301224.AA05298@resi.waldorf-gmbh.de>; from "Andreas Busse" at Nov 30, 93 7:25 am Reply-To: hp@vmars.vmars.tuwien.ac.at X-Return-Receipt-To: hp@vmars.tuwien.ac.at X-Mailer: ELM [version 2.3 PL5] You (Andreas Busse) wrote: > > > You won't get an acceptable 1280x1024 at 66Mb/sec. (at most 4 bits per pixel) > > The specs don't say wether this is the pixel rate or the transfer > rate into the video ram. I guess it's the transfer rate, what > do you think ? You mean from the CPU to video RAM? With 64bit writes that would be 120ns per write. Sounds reasonable. hp -- _ | hp@vmars.tuwien.ac.at | Peter Holzer | TU Vienna | CS/Real-Time Systems |_|_) |------------------------------------------------------------------------ | | | ...and it's finished! It only has to be written. __/ | -- Karl Lehenbauer