From chris@linux-mips.org Mon Jul 4 13:15:32 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Mon, 04 Jul 2005 14:15:32 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Mon, 04 Jul 2005 14:15:32 +0100 X-archive-position: 8 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/04 14:15:31 Modified files: linux/arch/mips/configs: Tag: MaltaRef_2_6 malta_defconfig Log message: Updated configuration file to use MIPSR2 by default diff -urN malta/linux/arch/mips/configs/malta_defconfig malta/linux/arch/mips/configs/malta_defconfig --- malta/linux/arch/mips/configs/malta_defconfig 2005/06/21 13:23:49 1.7.1000.6 +++ malta/linux/arch/mips/configs/malta_defconfig 2005/07/04 13:15:31 1.7.1000.7 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc6 -# Thu Jun 16 09:49:37 2005 +# Fri Jul 1 17:51:40 2005 # CONFIG_MIPS=y @@ -46,13 +46,7 @@ # # Loadable module support # -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y +# CONFIG_MODULES is not set # # Machine selection @@ -129,8 +123,8 @@ # # CPU selection # -CONFIG_CPU_MIPS32R1=y -# CONFIG_CPU_MIPS32R2 is not set +# CONFIG_CPU_MIPS32R1 is not set +CONFIG_CPU_MIPS32R2=y # CONFIG_CPU_MIPS64R1 is not set # CONFIG_CPU_MIPS64R2 is not set # CONFIG_CPU_R3000 is not set @@ -158,7 +152,7 @@ CONFIG_MIPS32=y # CONFIG_MIPS64 is not set CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPSR1=y +CONFIG_CPU_MIPSR2=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -166,10 +160,7 @@ # CONFIG_CPU_HAS_PREFETCH is not set CONFIG_VTAG_ICACHE=y CONFIG_CPU_MIPS32_24K=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_VPE_LOADER=y -CONFIG_MIPS_VPE_LOADER_TOM=y -CONFIG_MIPS_VPE_APSP_API=y +# CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y @@ -230,15 +221,15 @@ # # Block devices # -CONFIG_BLK_DEV_FD=m +CONFIG_BLK_DEV_FD=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_UMEM=m +CONFIG_BLK_DEV_UMEM=y # CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +CONFIG_BLK_DEV_NBD=y # CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 @@ -246,7 +237,7 @@ # CONFIG_BLK_DEV_INITRD is not set CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set @@ -257,7 +248,7 @@ CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m +CONFIG_ATA_OVER_ETH=y # # ATA/ATAPI/MFM/RLL support @@ -274,7 +265,6 @@ CONFIG_BLK_DEV_IDECD=y # CONFIG_BLK_DEV_IDETAPE is not set # CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set # @@ -319,98 +309,16 @@ # # SCSI device support # -CONFIG_SCSI=m -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=m -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=m -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=m - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_ISCSI_ATTRS=m - -# -# SCSI low-level drivers -# -CONFIG_BLK_DEV_3W_XXXX_RAID=m -CONFIG_SCSI_3W_9XXX=m -CONFIG_SCSI_ACARD=m -CONFIG_SCSI_AACRAID=m -CONFIG_SCSI_AIC7XXX=m -CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 -CONFIG_AIC7XXX_RESET_DELAY_MS=15000 -# CONFIG_AIC7XXX_DEBUG_ENABLE is not set -CONFIG_AIC7XXX_DEBUG_MASK=0 -CONFIG_AIC7XXX_REG_PRETTY_PRINT=y -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=m -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI is not set # # Multi-device support (RAID and LVM) # -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID5=m -CONFIG_MD_RAID6=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_EMC=m +# CONFIG_MD is not set # # Fusion MPT device support # -# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -446,25 +354,25 @@ CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE=y CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y # CONFIG_ARPD is not set CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_TUNNEL=y +CONFIG_IP_TCPDIAG=y CONFIG_IP_TCPDIAG_IPV6=y # # IP: Virtual Server Configuration # -CONFIG_IP_VS=m +CONFIG_IP_VS=y # CONFIG_IP_VS_DEBUG is not set CONFIG_IP_VS_TAB_BITS=12 @@ -479,28 +387,28 @@ # # IPVS scheduler # -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_RR=y +CONFIG_IP_VS_WRR=y +CONFIG_IP_VS_LC=y +CONFIG_IP_VS_WLC=y +CONFIG_IP_VS_LBLC=y +CONFIG_IP_VS_LBLCR=y +CONFIG_IP_VS_DH=y +CONFIG_IP_VS_SH=y +CONFIG_IP_VS_SED=y +CONFIG_IP_VS_NQ=y # # IPVS application helper # -CONFIG_IP_VS_FTP=m -CONFIG_IPV6=m +CONFIG_IP_VS_FTP=y +CONFIG_IPV6=y CONFIG_IPV6_PRIVACY=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_INET6_TUNNEL=m -CONFIG_IPV6_TUNNEL=m +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_INET6_TUNNEL=y +CONFIG_IPV6_TUNNEL=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set CONFIG_BRIDGE_NETFILTER=y @@ -508,141 +416,141 @@ # # IP: Netfilter Configuration # -CONFIG_IP_NF_CONNTRACK=m +CONFIG_IP_NF_CONNTRACK=y CONFIG_IP_NF_CT_ACCT=y CONFIG_IP_NF_CONNTRACK_MARK=y -CONFIG_IP_NF_CT_PROTO_SCTP=m -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_MAC=m -CONFIG_IP_NF_MATCH_PKTTYPE=m -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_DSCP=m -CONFIG_IP_NF_MATCH_AH_ESP=m -CONFIG_IP_NF_MATCH_LENGTH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_TCPMSS=m -CONFIG_IP_NF_MATCH_HELPER=m -CONFIG_IP_NF_MATCH_STATE=m -CONFIG_IP_NF_MATCH_CONNTRACK=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_PHYSDEV=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_REALM=m -CONFIG_IP_NF_MATCH_SCTP=m -CONFIG_IP_NF_MATCH_COMMENT=m -CONFIG_IP_NF_MATCH_CONNMARK=m -CONFIG_IP_NF_MATCH_HASHLIMIT=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_TARGET_TCPMSS=m -CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_CT_PROTO_SCTP=y +CONFIG_IP_NF_FTP=y +CONFIG_IP_NF_IRC=y +CONFIG_IP_NF_TFTP=y +CONFIG_IP_NF_AMANDA=y +CONFIG_IP_NF_QUEUE=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_LIMIT=y +CONFIG_IP_NF_MATCH_IPRANGE=y +CONFIG_IP_NF_MATCH_MAC=y +CONFIG_IP_NF_MATCH_PKTTYPE=y +CONFIG_IP_NF_MATCH_MARK=y +CONFIG_IP_NF_MATCH_MULTIPORT=y +CONFIG_IP_NF_MATCH_TOS=y +CONFIG_IP_NF_MATCH_RECENT=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_DSCP=y +CONFIG_IP_NF_MATCH_AH_ESP=y +CONFIG_IP_NF_MATCH_LENGTH=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_MATCH_TCPMSS=y +CONFIG_IP_NF_MATCH_HELPER=y +CONFIG_IP_NF_MATCH_STATE=y +CONFIG_IP_NF_MATCH_CONNTRACK=y +CONFIG_IP_NF_MATCH_OWNER=y +CONFIG_IP_NF_MATCH_PHYSDEV=y +CONFIG_IP_NF_MATCH_ADDRTYPE=y +CONFIG_IP_NF_MATCH_REALM=y +CONFIG_IP_NF_MATCH_SCTP=y +CONFIG_IP_NF_MATCH_COMMENT=y +CONFIG_IP_NF_MATCH_CONNMARK=y +CONFIG_IP_NF_MATCH_HASHLIMIT=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_LOG=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_IP_NF_TARGET_TCPMSS=y +CONFIG_IP_NF_NAT=y CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_IP_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_FTP=m -CONFIG_IP_NF_NAT_TFTP=m -CONFIG_IP_NF_NAT_AMANDA=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_DSCP=m -CONFIG_IP_NF_TARGET_MARK=m -CONFIG_IP_NF_TARGET_CLASSIFY=m -CONFIG_IP_NF_TARGET_CONNMARK=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_TARGET_NOTRACK=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_SAME=y +CONFIG_IP_NF_NAT_SNMP_BASIC=y +CONFIG_IP_NF_NAT_IRC=y +CONFIG_IP_NF_NAT_FTP=y +CONFIG_IP_NF_NAT_TFTP=y +CONFIG_IP_NF_NAT_AMANDA=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_TOS=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_DSCP=y +CONFIG_IP_NF_TARGET_MARK=y +CONFIG_IP_NF_TARGET_CLASSIFY=y +CONFIG_IP_NF_TARGET_CONNMARK=y +CONFIG_IP_NF_TARGET_CLUSTERIP=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_TARGET_NOTRACK=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y # # IPv6: Netfilter Configuration (EXPERIMENTAL) # -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_LIMIT=m -CONFIG_IP6_NF_MATCH_MAC=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_MULTIPORT=m -CONFIG_IP6_NF_MATCH_OWNER=m -CONFIG_IP6_NF_MATCH_MARK=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AHESP=m -CONFIG_IP6_NF_MATCH_LENGTH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_PHYSDEV=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_TARGET_MARK=m -CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_QUEUE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_LIMIT=y +CONFIG_IP6_NF_MATCH_MAC=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_MULTIPORT=y +CONFIG_IP6_NF_MATCH_OWNER=y +CONFIG_IP6_NF_MATCH_MARK=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_AHESP=y +CONFIG_IP6_NF_MATCH_LENGTH=y +CONFIG_IP6_NF_MATCH_EUI64=y +CONFIG_IP6_NF_MATCH_PHYSDEV=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_LOG=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_TARGET_MARK=y +CONFIG_IP6_NF_RAW=y # # Bridge: Netfilter Configuration # -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_802_3=y +CONFIG_BRIDGE_EBT_AMONG=y +CONFIG_BRIDGE_EBT_ARP=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_LIMIT=y +CONFIG_BRIDGE_EBT_MARK=y +CONFIG_BRIDGE_EBT_PKTTYPE=y +CONFIG_BRIDGE_EBT_STP=y +CONFIG_BRIDGE_EBT_VLAN=y +CONFIG_BRIDGE_EBT_ARPREPLY=y +CONFIG_BRIDGE_EBT_DNAT=y +CONFIG_BRIDGE_EBT_MARK_T=y +CONFIG_BRIDGE_EBT_REDIRECT=y +CONFIG_BRIDGE_EBT_SNAT=y +CONFIG_BRIDGE_EBT_LOG=y +CONFIG_BRIDGE_EBT_ULOG=y CONFIG_XFRM=y -CONFIG_XFRM_USER=m +CONFIG_XFRM_USER=y # # SCTP Configuration (EXPERIMENTAL) # -CONFIG_IP_SCTP=m +CONFIG_IP_SCTP=y # CONFIG_SCTP_DBG_MSG is not set # CONFIG_SCTP_DBG_OBJCNT is not set # CONFIG_SCTP_HMAC_NONE is not set # CONFIG_SCTP_HMAC_SHA1 is not set CONFIG_SCTP_HMAC_MD5=y # CONFIG_ATM is not set -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y # CONFIG_DECNET is not set -CONFIG_LLC=m +CONFIG_LLC=y # CONFIG_LLC2 is not set # CONFIG_IPX is not set -CONFIG_ATALK=m +CONFIG_ATALK=y CONFIG_DEV_APPLETALK=y -CONFIG_IPDDP=m +CONFIG_IPDDP=y CONFIG_IPDDP_ENCAP=y CONFIG_IPDDP_DECAP=y # CONFIG_X25 is not set @@ -658,32 +566,32 @@ CONFIG_NET_SCH_CLK_JIFFIES=y # CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set # CONFIG_NET_SCH_CLK_CPU is not set -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_CBQ=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_HFSC=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_RED=y +CONFIG_NET_SCH_SFQ=y +CONFIG_NET_SCH_TEQL=y +CONFIG_NET_SCH_TBF=y +CONFIG_NET_SCH_GRED=y +CONFIG_NET_SCH_DSMARK=y +CONFIG_NET_SCH_NETEM=y +CONFIG_NET_SCH_INGRESS=y CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_TCINDEX=y +CONFIG_NET_CLS_ROUTE4=y CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y # CONFIG_CLS_U32_PERF is not set CONFIG_NET_CLS_IND=y # CONFIG_CLS_U32_MARK is not set -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_RSVP=y +CONFIG_NET_CLS_RSVP6=y # CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -698,10 +606,10 @@ # CONFIG_IRDA is not set # CONFIG_BT is not set CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y # # ARCnet devices @@ -782,7 +690,6 @@ # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set @@ -950,62 +857,48 @@ # File systems # CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set # # XFS support # -CONFIG_XFS_FS=m +CONFIG_XFS_FS=y CONFIG_XFS_EXPORT=y # CONFIG_XFS_RT is not set CONFIG_XFS_QUOTA=y CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y -CONFIG_MINIX_FS=m -CONFIG_ROMFS_FS=m -CONFIG_QUOTA=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set CONFIG_QUOTACTL=y -CONFIG_DNOTIFY=y -CONFIG_AUTOFS_FS=y +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # # CD-ROM/DVD Filesystems # -CONFIG_ISO9660_FS=m +CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y -CONFIG_ZISOFS_FS=m -CONFIG_UDF_FS=m +CONFIG_ZISOFS_FS=y +CONFIG_UDF_FS=y CONFIG_UDF_NLS=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_NTFS_FS is not set @@ -1027,20 +920,18 @@ # Miscellaneous filesystems # # CONFIG_ADFS_FS is not set -CONFIG_AFFS_FS=m -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_CRAMFS=m -CONFIG_VXFS_FS=m +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set # # Network File Systems @@ -1075,46 +966,46 @@ # # Native Language Support # -CONFIG_NLS=m +CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set # # Profiling support @@ -1141,28 +1032,28 @@ # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_TEST is not set # @@ -1174,8 +1065,8 @@ # # CONFIG_CRC_CCITT is not set CONFIG_CRC32=y -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y From beth@linux-mips.org Tue Jul 12 16:23:41 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Tue, 12 Jul 2005 17:23:41 +0100 (BST) From: beth@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Tue, 12 Jul 2005 17:23:41 +0100 X-archive-position: 9 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: beth@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: beth@ftp.linux-mips.org 05/07/12 17:23:41 Modified files: linux/arch/mips/kernel: Tag: MaltaRef_2_6 traps.c Log message: Some uses of set_handler, and simulate_rdhwr got mangled in the last merge. diff -urN malta/linux/arch/mips/kernel/traps.c malta/linux/arch/mips/kernel/traps.c --- malta/linux/arch/mips/kernel/traps.c 2005/06/21 13:24:03 1.193.1000.5 +++ malta/linux/arch/mips/kernel/traps.c 2005/07/12 16:23:40 1.193.1000.6 @@ -525,6 +525,26 @@ int rd = (opcode & RD) >> 11; int rt = (opcode & RT) >> 16; switch (rd) { + case 0: /* CPU number */ + regs->regs[rt] = smp_processor_id(); + break; + case 1: /* SYNCI length */ + regs->regs[rt] = min(current_cpu_data.dcache.linesz, + current_cpu_data.icache.linesz); + break; + case 2: /* Read count register */ + regs->regs[rt] = read_c0_count(); + break; + case 3: /* Count register resolution */ + switch (current_cpu_data.cputype) { + case CPU_20KC: + case CPU_25KF: + regs->regs[rt] = 1; + break; + default: + regs->regs[rt] = 2; + } + break; case 29: regs->regs[rt] = ti->tp_value; break; @@ -1303,10 +1323,6 @@ //set_except_vector(15, handle_ndc); } - - if (board_nmi_handler_setup) - board_nmi_handler_setup(); - if (cpu_has_fpu && !cpu_has_nofpuex) set_except_vector(15, handle_fpe); @@ -1320,11 +1336,14 @@ if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); + set_handler(0x180, &except_vec3_r4000, 0x100); else if (cpu_has_4kex) - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); + set_handler(0x180, &except_vec3_generic, 0x80); else - memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); + set_handler(0x080, &except_vec3_generic, 0x80); + + if (board_nmi_handler_setup) + board_nmi_handler_setup(); signal_init(); #ifdef CONFIG_MIPS32_COMPAT From chris@linux-mips.org Tue Jul 19 13:07:46 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Tue, 19 Jul 2005 14:07:46 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Tue, 19 Jul 2005 14:07:46 +0100 X-archive-position: 10 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/19 14:07:45 Modified files: linux/arch/mips/mm: Tag: MaltaRef_2_6 tlbex.c Log message: (build_tlb_write_entry): Insert nop before tlbw for the 4KC diff -urN malta/linux/arch/mips/mm/tlbex.c malta/linux/arch/mips/mm/tlbex.c --- malta/linux/arch/mips/mm/tlbex.c 2005/06/21 13:24:14 1.23.1000.1 +++ malta/linux/arch/mips/mm/tlbex.c 2005/07/19 13:07:45 1.23.1000.2 @@ -840,13 +840,13 @@ case CPU_AU1500: case CPU_AU1550: case CPU_AU1200: + case CPU_4KC: i_nop(p); tlbw(p); break; case CPU_R10000: case CPU_R12000: - case CPU_4KC: case CPU_SB1: case CPU_4KSC: case CPU_20KC: From beth@linux-mips.org Wed Jul 20 15:46:01 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Wed, 20 Jul 2005 16:46:01 +0100 (BST) From: beth@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Wed, 20 Jul 2005 16:46:01 +0100 X-archive-position: 11 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: beth@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: beth@ftp.linux-mips.org 05/07/20 16:46:00 Modified files: linux/include/asm-mips: Tag: MaltaRef_2_6 mipsmtregs.h Log message: Replace mips_ihb() which was lost. diff -urN malta/linux/include/asm-mips/mipsmtregs.h malta/linux/include/asm-mips/mipsmtregs.h --- malta/linux/include/asm-mips/mipsmtregs.h 2005/07/14 08:16:04 1.2 +++ malta/linux/include/asm-mips/mipsmtregs.h 2005/07/20 15:45:59 1.2.1000.1 @@ -179,7 +179,7 @@ " .set reorder \n" : "=r" (res)); - instruction_hazard(); + mips_ihb(); return res; } @@ -219,7 +219,7 @@ " .set reorder \n" : "=r" (res)); - instruction_hazard(); + mips_ihb(); return res; } From beth@linux-mips.org Fri Jul 22 13:21:44 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Fri, 22 Jul 2005 14:21:44 +0100 (BST) From: beth@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Fri, 22 Jul 2005 14:21:44 +0100 X-archive-position: 12 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: beth@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: beth@ftp.linux-mips.org 05/07/22 14:21:43 Modified files: linux/arch/mips/kernel: Tag: MaltaRef_2_6 irq_cpu.c linux/include/asm-mips: Tag: MaltaRef_2_6 interrupt.h Log message: Fix missing CONFIG_CPU_MIPSR2 and MT stuff following the merge-that-shall-remain-nameless. diff -urN malta/linux/arch/mips/kernel/irq_cpu.c malta/linux/arch/mips/kernel/irq_cpu.c --- malta/linux/arch/mips/kernel/irq_cpu.c 2005/06/21 13:24:03 1.8.1000.2 +++ malta/linux/arch/mips/kernel/irq_cpu.c 2005/07/22 13:21:43 1.8.1000.3 @@ -37,8 +37,22 @@ static int mips_cpu_irq_base; + static inline void unmask_mips_irq(unsigned int irq) { +#ifdef CONFIG_MIPS_MT + /* + * So long as cross-VPE interrupts are done via + * MFTR/MTTR read-modify-writes of Cause, we need + * to stop other VPEs whenever the local VPE does + * anything similar. + */ + unsigned int vpflags = dvpe(); +#endif /* CONFIG_MIPS_MT */ + clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); +#ifdef CONFIG_MIPS_MT + evpe(vpflags); +#endif /* CONFIG_MIPS_MT */ set_c0_status(0x100 << (irq - mips_cpu_irq_base)); irq_enable_hazard(); } @@ -82,9 +96,16 @@ */ static void mips_cpu_irq_ack(unsigned int irq) { +#ifdef CONFIG_MIPS_MT + unsigned int vpflags = dvpe(); +#endif /* CONFIG_MIPS_MT */ + /* Only necessary for soft interrupts */ clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); +#ifdef CONFIG_MIPS_MT + evpe(vpflags); +#endif /* CONFIG_MIPS_MT */ mask_mips_irq(irq); } @@ -95,13 +116,14 @@ } static hw_irq_controller mips_cpu_irq_controller = { - .typename = "MIPS", - .startup = mips_cpu_irq_startup, - .shutdown = mips_cpu_irq_shutdown, - .enable = mips_cpu_irq_enable, - .disable = mips_cpu_irq_disable, - .ack = mips_cpu_irq_ack, - .end = mips_cpu_irq_end, + "MIPS", + mips_cpu_irq_startup, + mips_cpu_irq_shutdown, + mips_cpu_irq_enable, + mips_cpu_irq_disable, + mips_cpu_irq_ack, + mips_cpu_irq_end, + NULL /* no affinity stuff for UP */ }; diff -urN malta/linux/include/asm-mips/interrupt.h malta/linux/include/asm-mips/interrupt.h --- malta/linux/include/asm-mips/interrupt.h 2005/06/21 13:36:23 1.1.1000.1 +++ malta/linux/include/asm-mips/interrupt.h 2005/07/22 13:21:43 1.1.1000.2 @@ -13,28 +13,52 @@ #include + +#ifdef CONFIG_CPU_MIPSR2 +#if !defined(CONFIG_MIPS_MT_SMTC) __asm__ ( - ".macro\tlocal_irq_enable\n\t" - ".set\tpush\n\t" - ".set\treorder\n\t" - ".set\tnoat\n\t" - "mfc0\t$1,$12\n\t" - "ori\t$1,0x1f\n\t" - "xori\t$1,0x1e\n\t" - "mtc0\t$1,$12\n\t" - "irq_enable_hazard\n\t" - ".set\tpop\n\t" - ".endm"); + ".macro\tlocal_irq_enable\n\t" + "ei\n\t" + ".endm"); +#else /* SMTC - clear TCStatus.IXMT */ +__asm__ ( + ".macro\tlocal_irq_enable\n\t" + ".set\tpush\n\t" + ".set\treorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1,$2,1\n\t" + "ori\t$1,0x400\n\t" + "xori\t$1,0x400\n\t" + "mtc0\t$1,$2,1\n\t" + "ehb\n\t" + ".set\tpop\n\t" + ".endm"); +#endif /* CONFIG_MIPS_MT_SMTC */ +#else /* not MIPS32R2 */ +__asm__ ( + ".macro\tlocal_irq_enable\n\t" + ".set\tpush\n\t" + ".set\treorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1,$12\n\t" + "ori\t$1,0x1f\n\t" + "xori\t$1,0x1e\n\t" + "mtc0\t$1,$12\n\t" + "irq_enable_hazard\n\t" + ".set\tpop\n\t" + ".endm"); +#endif static inline void local_irq_enable(void) { - __asm__ __volatile__( - "local_irq_enable" - : /* no outputs */ - : /* no inputs */ - : "memory"); + __asm__ __volatile__( + "local_irq_enable" + : /* no outputs */ + : /* no inputs */ + : "memory"); } + /* * For cli() we have to insert nops to make sure that the new value * has actually arrived in the status register before the end of this @@ -42,6 +66,28 @@ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs * no nops at all. */ + +#ifdef CONFIG_CPU_MIPSR2 +#if !defined(CONFIG_MIPS_MT_SMTC) +__asm__ ( + ".macro\tlocal_irq_disable\n\t" + "di\n\t" + "ehb\n\t" + ".endm"); +#else /* SMTC - set TCStatus.IXMT */ +__asm__ ( + ".macro\tlocal_irq_disable\n\t" + ".set\tpush\n\t" + ".set\tnoat\n\t" + "mfc0\t$1,$2,1\n\t" + "ori\t$1,0x400\n\t" + ".set\tnoreorder\n\t" + "mtc0\t$1,$2,1\n\t" + "ehb\n\t" + ".set\tpop\n\t" + ".endm"); +#endif /* CONFIG_MIPS_MT_SMTC */ +#else /* not MIPS32R2 */ __asm__ ( ".macro\tlocal_irq_disable\n\t" ".set\tpush\n\t" @@ -54,6 +100,7 @@ "irq_disable_hazard\n\t" ".set\tpop\n\t" ".endm"); +#endif static inline void local_irq_disable(void) { @@ -64,6 +111,15 @@ : "memory"); } +#if defined(CONFIG_MIPS_MT_SMTC) +__asm__ ( + ".macro\tlocal_save_flags flags\n\t" + ".set\tpush\n\t" + ".set\treorder\n\t" + "mfc0\t\\flags, $2,1\n\t" + ".set\tpop\n\t" + ".endm"); +#else /* Not SMTC */ __asm__ ( ".macro\tlocal_save_flags flags\n\t" ".set\tpush\n\t" @@ -71,12 +127,35 @@ "mfc0\t\\flags, $12\n\t" ".set\tpop\n\t" ".endm"); +#endif /* CONFIG_MIPS_MT_SMTC */ #define local_save_flags(x) \ __asm__ __volatile__( \ "local_save_flags %0" \ : "=r" (x)) +#ifdef CONFIG_CPU_MIPSR2 +#if !defined(CONFIG_MIPS_MT_SMTC) +__asm__ ( + ".macro\tlocal_irq_save result\n\t" + "di\t\\result\n\t" + "ehb\n\t" + ".endm"); +#else /* SMTC - get/set TCStatus.IXMT */ +__asm__ ( + ".macro\tlocal_irq_save result\n\t" + ".set\tpush\n\t" + ".set\treorder\n\t" + ".set\tnoat\n\t" + "mfc0\t\\result, $2,1\n\t" + "ori\t$1, \\result, 0x400\n\t" + ".set\tnoreorder\n\t" + "mtc0\t$1, $2,1\n\t" + "ehb\n\t" + ".set\tpop\n\t" + ".endm"); +#endif /* CONFIG_MIPS_MT_SMTC */ +#else /* not MIPS32R2 */ __asm__ ( ".macro\tlocal_irq_save result\n\t" ".set\tpush\n\t" @@ -90,6 +169,7 @@ "irq_disable_hazard\n\t" ".set\tpop\n\t" ".endm"); +#endif #define local_irq_save(x) \ __asm__ __volatile__( \ @@ -98,6 +178,36 @@ : /* no inputs */ \ : "memory") +#ifdef CONFIG_CPU_MIPSR2 +#if !defined(CONFIG_MIPS_MT_SMTC) +__asm__ ( + ".macro\tlocal_irq_restore flags\n\t" + ".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1, $12\n\t" + "ins\t$1, \\flags, 0, 1\n\t" + "mtc0\t$1, $12\n\t" + "ehb\n\t" + ".set\tpop\n\t" + ".endm"); +#else /* SMTC - restore TCStatus IXMT */ +__asm__ ( + ".macro\tlocal_irq_restore flags\n\t" + ".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1, $2, 1\n\t" + "andi\t\\flags, 0x400\n\t" + "ori\t$1, 0x400\n\t" + "xori\t$1, 0x400\n\t" + "or\t\\flags, $1\n\t" + "mtc0\t\\flags, $2, 1\n\t" + "ehb\n\t" + ".set\tpop\n\t" + ".endm"); +#endif /* CONFIG_MIPS_MT_SMTC */ +#else /* not MIPS32R2 */ __asm__ ( ".macro\tlocal_irq_restore flags\n\t" ".set\tnoreorder\n\t" @@ -112,6 +222,7 @@ ".set\tat\n\t" ".set\treorder\n\t" ".endm"); +#endif #define local_irq_restore(flags) \ do { \ @@ -124,11 +235,34 @@ : "memory"); \ } while(0) +#if !defined(CONFIG_MIPS_MT_SMTC) #define irqs_disabled() \ ({ \ unsigned long flags; \ local_save_flags(flags); \ !(flags & 1); \ }) +#else /* SMTC */ +/* + * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU + */ + +static inline unsigned long irqs_disabled(void) +{ + unsigned long __result; + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips32\n\t" + "mfc0\t%0,$2,1\n\t" + "andi\t%0,0x400\n\t" + "slt\t%0,$0,%0\n\t" + ".set mips0\n\t" + ".set reorder\n\t" + : "=r" (__result)); + return (__result); +} + +#endif /* CONFIG_MIPS_MT_SMTC */ + #endif /* _ASM_INTERRUPT_H */ From chris@linux-mips.org Mon Jul 25 18:08:00 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Mon, 25 Jul 2005 19:08:00 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Mon, 25 Jul 2005 19:08:00 +0100 X-archive-position: 13 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/25 19:07:59 Modified files: linux/include/asm-mips: Tag: MaltaRef_2_6 mipsregs.h Log message: Only include mipsmtregs.h if CONFIG_MIPS_MT is defined diff -urN malta/linux/include/asm-mips/mipsregs.h malta/linux/include/asm-mips/mipsregs.h --- malta/linux/include/asm-mips/mipsregs.h 2005/06/21 13:36:23 1.62.1000.4 +++ malta/linux/include/asm-mips/mipsregs.h 2005/07/25 18:07:59 1.62.1000.5 @@ -37,7 +37,9 @@ #define _ULCAST_ (unsigned long) #endif +#ifdef CONFIG_MIPS_MT #include +#endif /* * Coprocessor 0 register names From chris@linux-mips.org Mon Jul 25 18:08:27 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Mon, 25 Jul 2005 19:08:27 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Mon, 25 Jul 2005 19:08:27 +0100 X-archive-position: 14 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/25 19:08:26 Modified files: linux/arch/mips/mm: Tag: MaltaRef_2_6 tlbex.c Log message: Part 2 of the 4Kc TLB handler fixups for TI parts diff -urN malta/linux/arch/mips/mm/tlbex.c malta/linux/arch/mips/mm/tlbex.c --- malta/linux/arch/mips/mm/tlbex.c 2005/07/19 13:07:45 1.23.1000.2 +++ malta/linux/arch/mips/mm/tlbex.c 2005/07/25 18:08:25 1.23.1000.3 @@ -1622,7 +1622,6 @@ l_smp_pgtable_change(l, *p); # endif iPTE_LW(p, l, pte, ptr); /* get even pte */ - build_tlb_probe_entry(p); } static void __init @@ -1663,6 +1662,7 @@ build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); + build_tlb_probe_entry(&p); build_make_valid(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); @@ -1702,6 +1702,7 @@ build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); + build_tlb_probe_entry(&p); build_make_write(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); @@ -1741,6 +1742,7 @@ build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); + build_tlb_probe_entry(&p); /* Present and writable bits set, set accessed and dirty bits. */ build_make_write(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); From beth@linux-mips.org Wed Jul 27 13:38:10 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Wed, 27 Jul 2005 14:38:12 +0100 (BST) From: beth@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Wed, 27 Jul 2005 14:38:10 +0100 X-archive-position: 15 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: beth@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: beth@ftp.linux-mips.org 05/07/27 14:38:04 Modified files: linux/arch/mips: Tag: MaltaRef_2_6 Kconfig linux/arch/mips/kernel: Tag: MaltaRef_2_6 Makefile rtlx.c vpe.c linux/include/asm-mips: Tag: MaltaRef_2_6 rtlx.h Added files: linux/arch/mips/kernel: Tag: MaltaRef_2_6 kspd.c linux/include/asm-mips: Tag: MaltaRef_2_6 kspd.h vpe.h Log message: Add support for APSP file IO. diff -urN malta/linux/arch/mips/Kconfig malta/linux/arch/mips/Kconfig --- malta/linux/arch/mips/Kconfig 2005/06/21 13:23:39 1.73.1000.6 +++ malta/linux/arch/mips/Kconfig 2005/07/27 13:37:39 1.73.1000.7 @@ -1163,7 +1163,7 @@ default y help The loader can use memory that is present but has been hidden from - Linux using the kernel command line option "mem=xxMB". It's up to + Linux using the kernel command line option "memsize=xxM". It's up to you to ensure the amount you put in the option and the space your program requires is less or equal to the amount physically present. @@ -1173,6 +1173,15 @@ depends on MIPS_VPE_LOADER help +config MIPS_APSP_KSPD + bool "Enable KSPD" + depends on MIPS_VPE_APSP_API + help + KSPD is a kernel daemon that accepts syscall requests from the SP side, + actions them and returns the results. It also handles the "exit" syscall + notifying other kernel modules the SP program is exiting. + You probably want to say yes here. + config SB1_PASS_1_WORKAROUNDS bool depends on CPU_SB1_PASS_1 diff -urN malta/linux/arch/mips/kernel/kspd.c malta/linux/arch/mips/kernel/kspd.c --- malta/linux/arch/mips/kernel/Attic/kspd.c 1970/01/01 00:00:00 +++ malta/linux/arch/mips/kernel/Attic/kspd.c 2005-07-27 14:37:54.201261000 +0100 1.1.1000.1 @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static struct workqueue_struct *workqueue = NULL; +static struct work_struct work; + +struct sp_request { + int cmd; + int arg0; + int arg1; + int arg2; + int ret; +}; + +static struct list_head kspd_notifylist; +static int sp_stopping = 0; + +/* these should match with those in the SDE kit */ +#define MTSP_SYSCALL_BASE 0 +#define MTSP_SYSCALL_EXIT (MTSP_SYSCALL_BASE + 0) +#define MTSP_SYSCALL_OPEN (MTSP_SYSCALL_BASE + 5) + +#define MTSP_O_RDONLY 0x0000 +#define MTSP_O_WRONLY 0x0001 +#define MTSP_O_RDWR 0x0002 +#define MTSP_O_NONBLOCK 0x0004 +#define MTSP_O_APPEND 0x0008 +#define MTSP_O_SHLOCK 0x0010 +#define MTSP_O_EXLOCK 0x0020 +#define MTSP_O_ASYNC 0x0040 +#define MTSP_O_FSYNC O_SYNC +#define MTSP_O_NOFOLLOW 0x0100 +#define MTSP_O_SYNC 0x0080 +#define MTSP_O_CREAT 0x0200 +#define MTSP_O_TRUNC 0x0400 +#define MTSP_O_EXCL 0x0800 +#define MTSP_O_BINARY 0x8000 + +#define SP_VPE 1 + +struct apsp_table { + int sp; + int ap; +}; + +/* we might want to do the mode flags too */ +struct apsp_table open_flags_table[] = { + {MTSP_O_RDWR, O_RDWR}, + {MTSP_O_WRONLY, O_WRONLY}, + {MTSP_O_CREAT, O_CREAT}, + {MTSP_O_TRUNC, O_TRUNC}, + {MTSP_O_NONBLOCK, O_NONBLOCK}, + {MTSP_O_APPEND, O_APPEND}, + {MTSP_O_NOFOLLOW, O_NOFOLLOW} +}; + +static int sp_syscall(int num, int arg0, int arg1, int arg2) +{ + register long int _num __asm__ ("$2") = num; + register long int _arg0 __asm__ ("$4") = arg0; + register long int _arg1 __asm__ ("$5") = arg1; + register long int _arg2 __asm__ ("$6") = arg2; + register long int eflag __asm__ ("$7") = 1; + + mm_segment_t old_fs; + + old_fs = get_fs(); + set_fs (KERNEL_DS); + + __asm__ __volatile__ ( + "syscall\n\t" + : "=r" (_num), "=r" (eflag) + : "r" (_num), "r" (_arg0), "r" (_arg1), "r" (_arg2) + ); + + set_fs (old_fs); + + if (eflag) + return -_num; + + return _num; +} + +static int translate_open_flags(int flags) +{ + int i; + unsigned int ret = 0; + + for (i = 0; i < (sizeof(open_flags_table) / sizeof(struct apsp_table)); + i++) { + if( (flags & open_flags_table[i].sp) ) { + ret |= open_flags_table[i].ap; + } + } + + return ret; +} + +static void sp_setfsuidgid( uid_t uid, gid_t gid) +{ + current->fsuid = uid; + current->fsgid = gid; + + key_fsuid_changed(current); + key_fsgid_changed(current); +} + +/* Expects a request to be on the sysio channel. Reads it. + Decides whether its a linux syscall and runs it, or whatever. + Puts the return code back into the request and sends the + whole thing back. +*/ +void sp_work_handle_request(void) +{ + struct sp_request spreq; + struct kspd_notifications *n; + char *vcwd; + mm_segment_t old_fs; + + spreq.ret = -1; + + if (!rtlx_read(RTLX_CHANNEL_SYSIO, &spreq, sizeof(struct sp_request), 0)) { + printk(KERN_ERR "Expected request but nothing to read\n"); + return; + } + + /* run the syscall at the priviledge of the user who loaded the + SP program */ + + if (vpe_getuid(SP_VPE)) + sp_setfsuidgid( vpe_getuid(SP_VPE), vpe_getgid(SP_VPE)); + + /* Linux compatible syscalls can be actioned directly */ + if ((spreq.cmd >= __NR_Linux) && + (spreq.cmd <= (__NR_Linux + __NR_Linux_syscalls))) { + /* its a linux syscall */ + + spreq.ret = sp_syscall(spreq.cmd, spreq.arg0, spreq.arg1, + spreq.arg2); + + } + else { + switch (spreq.cmd) { + + /* needs the flags argument translating from SDE kit to + linux */ + case MTSP_SYSCALL_OPEN: + spreq.arg1 = translate_open_flags(spreq.arg1); + + vcwd = vpe_getcwd(SP_VPE); + + /* change to the cwd of the process that loaded the SP program */ + old_fs = get_fs(); + set_fs (KERNEL_DS); + sys_chdir(vcwd); + set_fs (old_fs); + + spreq.ret = sp_syscall(__NR_open, spreq.arg0, spreq.arg1, + spreq.arg2); + + break; + + case MTSP_SYSCALL_EXIT: + list_for_each_entry(n, &kspd_notifylist, list) { + n->kspd_sp_exit(SP_VPE); + } + sp_stopping = 1; + break; + + default: + printk(KERN_WARNING "KSPD: Invalid SP syscall number %d\n", + spreq.cmd); + break; + } + } + + if (vpe_getuid(SP_VPE)) + sp_setfsuidgid( 0, 0); + + if ((rtlx_write(RTLX_CHANNEL_SYSIO, &spreq, sizeof(struct sp_request), 0)) + < sizeof(struct sp_request)) + printk("KSPD: sp_work_handle_request failed to send to SP\n"); +} + +static int channel_open = 0; + +/* the work handler */ +static void sp_work( void *data) +{ + if (!channel_open) { + if( rtlx_open(RTLX_CHANNEL_SYSIO, 1) != 0) + printk("KSPD: unable to open sp channel\n"); + else { + channel_open++; + printk(KERN_DEBUG "KSPD: SP channel opened\n"); + } + } else { + /* wait for some data, allow it to sleep */ + rtlx_read_poll(RTLX_CHANNEL_SYSIO, 1); + + sp_work_handle_request(); + } + + if (!sp_stopping) + queue_work(workqueue, &work); +} + +static void startwork(int vpe) +{ + sp_stopping = channel_open = 0; + + if (workqueue == NULL) { + if ((workqueue = create_singlethread_workqueue("kspd")) == NULL) { + printk(KERN_ERR "unable to start kspd\n"); + return; + } + + INIT_WORK(&work, sp_work, NULL); + queue_work(workqueue, &work); + } + else + queue_work(workqueue, &work); + +} + +static void stopwork(int vpe) +{ + sp_stopping = 1; + + printk(KERN_DEBUG "KSPD: SP stopping\n"); +} + +void kspd_notify(struct kspd_notifications *notify) +{ + list_add(¬ify->list, &kspd_notifylist); +} + +static struct vpe_notifications notify; +static int kspd_module_init(void) +{ + INIT_LIST_HEAD(&kspd_notifylist); + + notify.start = startwork; + notify.stop = stopwork; + vpe_notify(SP_VPE, ¬ify); + + return 0; +} + +static void kspd_module_exit(void) +{ + +} + +module_init(kspd_module_init); +module_exit(kspd_module_exit); +MODULE_DESCRIPTION("MIPS KSPD"); +MODULE_AUTHOR("Elizabeth Clarke, MIPS Technologies, Inc"); +MODULE_LICENSE("GPL"); diff -urN malta/linux/arch/mips/kernel/Makefile malta/linux/arch/mips/kernel/Makefile --- malta/linux/arch/mips/kernel/Makefile 2005/06/21 13:24:02 1.80.1000.4 +++ malta/linux/arch/mips/kernel/Makefile 2005/07/27 13:37:54 1.80.1000.5 @@ -36,6 +36,7 @@ obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o +obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o obj-$(CONFIG_NO_ISA) += dma-no-isa.o obj-$(CONFIG_I8259) += i8259.o diff -urN malta/linux/arch/mips/kernel/rtlx.c malta/linux/arch/mips/kernel/rtlx.c --- malta/linux/arch/mips/kernel/rtlx.c 2005/07/14 15:57:16 1.1 +++ malta/linux/arch/mips/kernel/rtlx.c 2005/07/27 13:37:54 1.1.1000.1 @@ -38,6 +38,7 @@ #include #include #include +#include #include #define RTLX_MAJOR 64 @@ -46,7 +47,7 @@ struct rtlx_info *rtlx; static int major; static char module_name[] = "rtlx"; -static inline int spacefree(int read, int write, int size); +static inline int write_spacefree(int read, int write, int size); static struct chan_waitqueues { wait_queue_head_t rt_queue; @@ -55,23 +56,27 @@ static struct irqaction irq; static int irq_num; +static struct vpe_notifications notify; +static int sp_stopping = 0; extern void *vpe_get_shared(int index); +static int rtlx_init(struct rtlx_info *rtlxi); static void rtlx_dispatch(struct pt_regs *regs) { do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ, regs); } + +/* Interrupt handler may be called before rtlx_init has otherwise had + a chance to run. +*/ irqreturn_t rtlx_interrupt(int irq, void *dev_id, struct pt_regs *regs) { irqreturn_t r = IRQ_HANDLED; int i; for (i = 0; i < RTLX_CHANNELS; i++) { - struct rtlx_channel *chan = &rtlx->channel[i]; - - if (chan->lx_read != chan->lx_write) wake_up_interruptible(&channel_wqs[i].lx_queue); } @@ -104,82 +109,247 @@ /* call when we have the address of the shared structure from the SP side. */ static int rtlx_init(struct rtlx_info *rtlxi) { - int i; - if (rtlxi->id != RTLX_ID) { - printk(KERN_WARNING "no valid RTLX id at 0x%p\n", rtlxi); - return (-ENOEXEC); + printk(KERN_ERR "no valid RTLX id at 0x%p\n", rtlxi); + return -ENOEXEC; } - /* initialise the wait queues */ - for (i = 0; i < RTLX_CHANNELS; i++) { - init_waitqueue_head(&channel_wqs[i].rt_queue); - init_waitqueue_head(&channel_wqs[i].lx_queue); - } + rtlx = rtlxi; + return 0; +} - /* set up for interrupt handling */ - memset(&irq, 0, sizeof(struct irqaction)); +/* notifications */ +static void starting(int vpe) +{ + int i; + sp_stopping = 0; - if (cpu_has_vint) { - set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); - } + /* force a reload of rtlx */ + rtlx=NULL; - irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ; - irq.handler = rtlx_interrupt; - irq.flags = SA_INTERRUPT; - irq.name = "RTLX"; - irq.dev_id = rtlx; - setup_irq(irq_num, &irq); + /* wake up any sleeping rtlx_open's */ + for (i = 0; i < RTLX_CHANNELS; i++) + wake_up_interruptible(&channel_wqs[i].lx_queue); +} +static void stopping(int vpe) +{ + int i; - rtlx = rtlxi; - return (0); + sp_stopping = 1; + for (i = 0; i < RTLX_CHANNELS; i++) + wake_up_interruptible(&channel_wqs[i].lx_queue); } -/* only allow one open process at a time to open each channel */ -static int rtlx_open(struct inode *inode, struct file *filp) + +int rtlx_open(int index, int can_sleep) { - int minor, ret; + int ret; struct rtlx_channel *chan; - - /* assume only 1 device at the mo. */ - minor = MINOR(inode->i_rdev); + volatile struct rtlx_info **p; if (rtlx == NULL) { - struct rtlx_info **p; if( (p = vpe_get_shared(RTLX_TARG_VPE)) == NULL) { - printk(" vpe_get_shared is NULL. Has an SP program been loaded?\n"); - return (-EFAULT); + if (can_sleep) { + DECLARE_WAITQUEUE(wait, current); + + /* go to sleep */ + add_wait_queue(&channel_wqs[index].lx_queue, &wait); + + set_current_state(TASK_INTERRUPTIBLE); + while ((p = vpe_get_shared(RTLX_TARG_VPE)) == NULL) { + schedule(); + } + + set_current_state(TASK_RUNNING); + remove_wait_queue(&channel_wqs[index].lx_queue, &wait); + + /* back running */ + } } if (*p == NULL) { - printk(" vpe_shared %p %p\n", p, *p); - return (-EFAULT); + if (can_sleep) { + DECLARE_WAITQUEUE(wait, current); + + + /* go to sleep */ + add_wait_queue(&channel_wqs[index].lx_queue, &wait); + + set_current_state(TASK_INTERRUPTIBLE); + while (*p == NULL) { + schedule(); + } + + set_current_state(TASK_RUNNING); + remove_wait_queue(&channel_wqs[index].lx_queue, &wait); + + /* back running */ + } + else { + printk(" *vpe_get_shared is NULL. " + "Has an SP program been loaded?\n"); + return -ENOSYS; + } } - + if ((ret = rtlx_init(*p)) < 0) - return (ret); + return ret; } - - chan = &rtlx->channel[minor]; - + + chan = &rtlx->channel[index]; + /* already open? */ if (chan->lx_state == RTLX_STATE_OPENED) - return (-EBUSY); + return -EBUSY; chan->lx_state = RTLX_STATE_OPENED; - return (0); + return 0; +} + +int rtlx_release(int index) +{ + rtlx->channel[index].lx_state = RTLX_STATE_UNUSED; + return 0; } -static int rtlx_release(struct inode *inode, struct file *filp) +unsigned int rtlx_read_poll(int index, int can_sleep) { - int minor; + struct rtlx_channel *chan = &rtlx->channel[index]; + + /* data available to read? */ + if (chan->lx_read == chan->lx_write) { + if (can_sleep) { + DECLARE_WAITQUEUE(wait, current); + + /* go to sleep */ + add_wait_queue(&channel_wqs[index].lx_queue, &wait); + + set_current_state(TASK_INTERRUPTIBLE); + while (chan->lx_read == chan->lx_write) { + schedule(); + + set_current_state(TASK_INTERRUPTIBLE); + + if (sp_stopping) { + set_current_state(TASK_RUNNING); + remove_wait_queue(&channel_wqs[index].lx_queue, &wait); + return 0; + } + } + + set_current_state(TASK_RUNNING); + remove_wait_queue(&channel_wqs[index].lx_queue, &wait); + + /* back running */ + } + else + return 0; + } + + return (chan->lx_write + chan->buffer_size - chan->lx_read) + % chan->buffer_size; +} + +unsigned int rtlx_write_poll(int index) +{ + struct rtlx_channel *chan = &rtlx->channel[index]; + return(write_spacefree(chan->rt_read, chan->rt_write, chan->buffer_size)); +} + +static inline void copy_to(void *dst, void *src, size_t count, int user) +{ + if (user) + copy_to_user (dst, src, count); + else + memcpy(dst,src,count); +} + +static inline void copy_from(void *dst, void *src, size_t count, int user) +{ + if (user) + copy_from_user (dst, src, count); + else + memcpy (dst, src, count); +} + +ssize_t rtlx_read(int index, void *buff, size_t count, int user) +{ + size_t fl = 0L; + struct rtlx_channel *lx; + + if (rtlx == NULL) + return(-ENOSYS); + + lx = &rtlx->channel[index]; + + /* find out how much in total */ + count = min( count, + (size_t)(lx->lx_write + lx->buffer_size - lx->lx_read) + % lx->buffer_size); + + /* then how much from the read pointer onwards */ + fl = min( count, (size_t)lx->buffer_size - lx->lx_read); + + copy_to (buff, &lx->lx_buffer[lx->lx_read], fl, user); + + /* and if there is anything left at the beginning of the buffer */ + if ( count - fl ) + copy_to (buff + fl, lx->lx_buffer, count - fl, user); + /* update the index */ + lx->lx_read += count; + lx->lx_read %= lx->buffer_size; + + return count; +} + +ssize_t rtlx_write(int index, void *buffer, size_t count, int user) +{ + struct rtlx_channel *rt; + size_t fl; + + if (rtlx == NULL) + return(-ENOSYS); + + rt = &rtlx->channel[index]; + + /* total number of bytes to copy */ + count = min( count, + (size_t)write_spacefree(rt->rt_read, rt->rt_write, + rt->buffer_size)); + + /* first bit from write pointer to the end of the buffer, or count */ + fl = min(count, (size_t) rt->buffer_size - rt->rt_write); + + copy_from (&rt->rt_buffer[rt->rt_write], buffer, fl, user); + + /* if there's any left copy to the beginning of the buffer */ + if( count - fl ) + copy_from (rt->rt_buffer, buffer + fl, count - fl, user); + + rt->rt_write += count; + rt->rt_write %= rt->buffer_size; + + return(count); +} + + +static int file_open(struct inode *inode, struct file *filp) +{ + int minor = MINOR(inode->i_rdev); + + return rtlx_open(minor, 0); +} + +static int file_release(struct inode *inode, struct file *filp) +{ + int minor; minor = MINOR(inode->i_rdev); - rtlx->channel[minor].lx_state = RTLX_STATE_UNUSED; - return (0); + + return rtlx_release(minor); } -static unsigned int rtlx_poll(struct file *file, poll_table * wait) +static unsigned int file_poll(struct file *file, poll_table * wait) { int minor; unsigned int mask = 0; @@ -192,141 +362,117 @@ poll_wait(file, &channel_wqs[minor].lx_queue, wait); /* data available to read? */ - if (chan->lx_read != chan->lx_write) + if (rtlx_read_poll(minor, 0)) mask |= POLLIN | POLLRDNORM; /* space to write */ - if (spacefree(chan->rt_read, chan->rt_write, chan->buffer_size)) + if (rtlx_write_poll(minor)) mask |= POLLOUT | POLLWRNORM; - return (mask); + return mask; } -static ssize_t rtlx_read(struct file *file, char __user * buffer, size_t count, +static ssize_t file_read(struct file *file, char __user * buffer, size_t count, loff_t * ppos) { - size_t fl = 0L; - int minor; - struct rtlx_channel *lx; - DECLARE_WAITQUEUE(wait, current); - - minor = MINOR(file->f_dentry->d_inode->i_rdev); - lx = &rtlx->channel[minor]; + int minor = MINOR(file->f_dentry->d_inode->i_rdev); /* data available? */ - if (lx->lx_write == lx->lx_read) { - if (file->f_flags & O_NONBLOCK) - return (0); // -EAGAIN makes cat whinge - - /* go to sleep */ - add_wait_queue(&channel_wqs[minor].lx_queue, &wait); - set_current_state(TASK_INTERRUPTIBLE); - - while (lx->lx_write == lx->lx_read) - schedule(); - - set_current_state(TASK_RUNNING); - remove_wait_queue(&channel_wqs[minor].lx_queue, &wait); - - /* back running */ + if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK))) { + return 0; // -EAGAIN makes cat whinge } - - /* find out how much in total */ - count = min( count, - (size_t)(lx->lx_write + lx->buffer_size - lx->lx_read) % lx->buffer_size); - - /* then how much from the read pointer onwards */ - fl = min( count, (size_t)lx->buffer_size - lx->lx_read); - - copy_to_user (buffer, &lx->lx_buffer[lx->lx_read], fl); - - /* and if there is anything left at the beginning of the buffer */ - if ( count - fl ) - copy_to_user (buffer + fl, lx->lx_buffer, count - fl); - - /* update the index */ - lx->lx_read += count; - lx->lx_read %= lx->buffer_size; - - return (count); + + return rtlx_read(minor, buffer, count, 1); } -static inline int spacefree(int read, int write, int size) +static inline int write_spacefree(int read, int write, int size) { if (read == write) { - /* never fill the buffer completely, so indexes are always equal if empty - and only empty, or !equal if data available */ - return (size - 1); + /* never fill the buffer completely, so indexes are + always equal if empty and only empty, or !equal + if data available */ + return size - 1; } return ((read + size - write) % size) - 1; } -static ssize_t rtlx_write(struct file *file, const char __user * buffer, +static ssize_t file_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos) { int minor; struct rtlx_channel *rt; - size_t fl; DECLARE_WAITQUEUE(wait, current); minor = MINOR(file->f_dentry->d_inode->i_rdev); rt = &rtlx->channel[minor]; /* any space left... */ - if (!spacefree(rt->rt_read, rt->rt_write, rt->buffer_size)) { + if (!rtlx_write_poll(minor)) { if (file->f_flags & O_NONBLOCK) - return (-EAGAIN); + return -EAGAIN; add_wait_queue(&channel_wqs[minor].rt_queue, &wait); set_current_state(TASK_INTERRUPTIBLE); - while (!spacefree(rt->rt_read, rt->rt_write, rt->buffer_size)) + while (!rtlx_write_poll(minor)) schedule(); set_current_state(TASK_RUNNING); remove_wait_queue(&channel_wqs[minor].rt_queue, &wait); } - /* total number of bytes to copy */ - count = min( count, (size_t)spacefree(rt->rt_read, rt->rt_write, rt->buffer_size) ); - - /* first bit from write pointer to the end of the buffer, or count */ - fl = min(count, (size_t) rt->buffer_size - rt->rt_write); - - copy_from_user(&rt->rt_buffer[rt->rt_write], buffer, fl); - - /* if there's any left copy to the beginning of the buffer */ - if( count - fl ) - copy_from_user(rt->rt_buffer, buffer + fl, count - fl); - - rt->rt_write += count; - rt->rt_write %= rt->buffer_size; - - return(count); + return rtlx_write(minor, (void *)buffer, count, 1); } static struct file_operations rtlx_fops = { - .owner = THIS_MODULE, - .open = rtlx_open, - .release = rtlx_release, - .write = rtlx_write, - .read = rtlx_read, - .poll = rtlx_poll + .owner = THIS_MODULE, + .open = file_open, + .release = file_release, + .write = file_write, + .read = file_read, + .poll = file_poll }; static int rtlx_module_init(void) { + int i; + if ((major = register_chrdev(RTLX_MAJOR, module_name, &rtlx_fops)) < 0) { printk("rtlx_module_init: unable to register device\n"); - return (-EBUSY); + return -EBUSY; } if (major == 0) major = RTLX_MAJOR; - return (0); + /* initialise the wait queues */ + for (i = 0; i < RTLX_CHANNELS; i++) { + init_waitqueue_head(&channel_wqs[i].rt_queue); + init_waitqueue_head(&channel_wqs[i].lx_queue); + } + + /* set up notifiers */ + notify.start = starting; + notify.stop = stopping; + vpe_notify(RTLX_TARG_VPE, ¬ify); + + /* set up for interrupt handling */ + memset(&irq, 0, sizeof(struct irqaction)); + + if (cpu_has_vint) { + set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); + } + + irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ; + irq.handler = rtlx_interrupt; + irq.flags = SA_INTERRUPT; + irq.name = "RTLX"; + irq.dev_id = rtlx; + setup_irq(irq_num, &irq); + + return 0; } static void rtlx_module_exit(void) diff -urN malta/linux/arch/mips/kernel/vpe.c malta/linux/arch/mips/kernel/vpe.c --- malta/linux/arch/mips/kernel/vpe.c 2005/07/14 15:57:16 1.1 +++ malta/linux/arch/mips/kernel/vpe.c 2005/07/27 13:37:54 1.1.1000.1 @@ -31,6 +31,7 @@ * You'll need to have the following device files. * mknod /dev/vpe0 c 63 0 * mknod /dev/vpe1 c 63 1 + * */ #include @@ -54,9 +55,17 @@ #include #include #include +#include +#include typedef void *vpe_handle; +#if 0 +#define DEBUGP printk +#else +#define DEBUGP(fmt , a...) +#endif + // defined here because the kernel module loader doesn't have // anything to do with it. #define SHN_MIPS_SCOMMON 0xff03 @@ -68,12 +77,15 @@ /* If this is set, the section belongs in the init part of the module */ #define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) -// temp number, +// temp number, #define VPE_MAJOR 63 static char module_name[] = "vpe"; static int major = 0; +static struct kspd_notifications kspd_events; +static int kspd_events_reqd = 0; + /* grab the likely amount of memory we will need. */ #ifdef CONFIG_MIPS_VPE_LOADER_TOM #define P_SIZE (2 * 1024 * 1024) @@ -84,13 +96,15 @@ #define MAX_VPES 16 +#define VPE_PATH_MAX 256 + enum vpe_state { VPE_STATE_UNUSED = 0, VPE_STATE_INUSE, VPE_STATE_RUNNING }; -enum tc_state { +enum tc_state { TC_STATE_UNUSED = 0, TC_STATE_INUSE, TC_STATE_RUNNING, @@ -104,7 +118,7 @@ /* parent VPE */ struct vpe *pvpe; - + /* The list of TC's with this VPE */ struct list_head tc; @@ -123,6 +137,8 @@ u32 len; char *pbuffer; u32 plen; + unsigned int uid, gid; + char cwd[VPE_PATH_MAX]; unsigned long __start; @@ -134,6 +150,9 @@ /* shared symbol address */ void *shared_ptr; + + /* the list of who wants to know when something major happens */ + struct list_head notify; } vpe_t; struct vpecontrol_ { @@ -206,6 +225,7 @@ INIT_LIST_HEAD(&v->tc); list_add_tail(&v->list, &vpecontrol.vpe_list); + INIT_LIST_HEAD(&v->notify); v->minor = minor; return v; } @@ -361,10 +381,11 @@ else { /* .sbss + gp(relative) + offset */ /* kludge! */ + rel = (int)(short)((int)v + gp_offs + (int)(short)(*location & 0xffff) - gp_addr); } - + if( (rel > 32768) || (rel < -32768) ) { printk(KERN_ERR "apply_r_mips_gprel16: relative address out of range 0x%x %d\n", @@ -373,7 +394,7 @@ } *location = (*location & 0xffff0000) | (rel & 0xffff); - + return 0; } @@ -384,15 +405,14 @@ rel = (((unsigned int)v - (unsigned int)location)); rel >>= 2; // because the offset is in _instructions_ not bytes. rel -= 1; // and one instruction less due to the branch delay slot. - + if( (rel > 32768) || (rel < -32768) ) { printk(KERN_ERR "apply_r_mips_pc16: relative address out of range 0x%x\n", rel); return -ENOEXEC; } - + *location = (*location & 0xffff0000) | (rel & 0xffff); - return 0; } @@ -474,7 +494,7 @@ printk("%d != %d\n", v, l->value); goto out_danger; } - + /* * Do the HI16 relocation. Note that we actually don't @@ -552,7 +572,7 @@ /* This is the symbol it is referring to */ sym = (Elf32_Sym *)sechdrs[symindex].sh_addr + ELF32_R_SYM(r_info); - + if (!sym->st_value) { printk(KERN_DEBUG "%s: undefined weak symbol %s\n", me->name, strtab + sym->st_name); @@ -561,6 +581,7 @@ v = sym->st_value; + res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); if( res ) { printk(KERN_DEBUG @@ -581,6 +602,9 @@ { gp_addr = secbase + rel; gp_offs = gp_addr - (secbase & 0xffff0000); + + printk(KERN_DEBUG "save_gp_address gp_addr 0x%x gp_offs 0x%x secbase 0x%x rel 0x%x\n", + gp_addr, gp_offs, secbase, rel); } /* end module-elf32.c */ @@ -600,14 +624,19 @@ /* find the .bss section for COMMON symbols */ for (i = 0; i < nsecs; i++) { - if (strncmp(secstrings + sechdrs[i].sh_name, ".bss", 4) == 0) + if (strncmp(secstrings + sechdrs[i].sh_name, ".bss", 4) == 0) { bssbase = sechdrs[i].sh_addr; + break; + } } for (i = 1; i < n; i++) { + switch (sym[i].st_shndx) { + case SHN_COMMON: - /* Allocate space for the symbol in the .bss section. st_value is currently size. + /* Allocate space for the symbol in the .bss section. + st_value is currently size. We want it to have the address of the symbol. */ size = sym[i].st_value; @@ -626,11 +655,11 @@ case SHN_MIPS_SCOMMON: - printk(KERN_DEBUG - "simplify_symbols: ignoring SHN_MIPS_SCOMMON symbol <%s> st_shndx %d\n", - strtab + sym[i].st_name, sym[i].st_shndx); + printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON" + "symbol <%s> st_shndx %d\n", strtab + sym[i].st_name, + sym[i].st_shndx); - // .sbss section + // .sbss section break; default: @@ -643,7 +672,7 @@ sym[i].st_value += secbase; break; } - + } return ret; @@ -669,6 +698,7 @@ printk(KERN_WARNING "VPE: TC index %d TCStatus 0x%lx halt 0x%lx\n", t->index, read_tc_c0_tcstatus(), read_tc_c0_tchalt()); printk(KERN_WARNING "VPE: tcrestart 0x%lx\n", read_tc_c0_tcrestart()); + printk(KERN_WARNING "VPE: tcbind 0x%lx\n", read_tc_c0_tcbind()); } static void dump_tclist(void) @@ -685,6 +715,7 @@ { unsigned long val; struct tc *t; + struct vpe_notifications *n; /* check we are the Master VPE */ val = read_c0_vpeconf0(); @@ -725,47 +756,52 @@ return -ENOEXEC; } + /* Write the address we want it to start running from in the TCPC register. */ write_tc_c0_tcrestart((unsigned long)v->__start); /* write the sivc_info address to tccontext */ write_tc_c0_tccontext((unsigned long)0); - /* Set up the XTC bit in vpeconf0 to point at our tc */ - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (t->index << VPECONF0_XTC_SHIFT)); - - /* mark the TC as activated, not interrupt exempt and not dynamically allocatable */ + /* mark the TC as activated, not interrupt exempt and not dynamically + allocatable */ val = read_tc_c0_tcstatus(); val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A; write_tc_c0_tcstatus(val); - + write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); - /* set up VPE1 */ - write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); // no multiple TC's - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); // enable this VPE - /* The sde-kit passes 'memsize' to __start in $a3, so set something here... Or set $a3 to zero and define DFLT_STACK_SIZE and DFLT_HEAP_SIZE when you compile your program */ mttgpr($7, 0); - /* set config to be the same as vpe0, particularly kseg0 coherency alg */ - write_vpe_c0_config(read_c0_config()); + /* set up VPE1 */ + /* bind the TC to VPE 1 as late as possible so we only have the final VPE + registers to set up, and so an EJTAG probe can trigger on it */ + write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | v->minor); - /* clear out any left overs from a previous program */ - write_vpe_c0_cause(0); + /* Set up the XTC bit in vpeconf0 to point at our tc */ + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (t->index << VPECONF0_XTC_SHIFT)); + + /* enable this VPE */ + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); /* take system out of configuration state */ write_c0_mvpcontrol(read_c0_mvpcontrol() & ~MVPCONTROL_VPC); - /* clear interrupts enabled IE, ERL, EXL, and KSU from c0 status */ - write_vpe_c0_status(read_vpe_c0_status() & ~(ST0_ERL | ST0_KSU | ST0_IE | ST0_EXL)); + + dump_tc(t); + /* set it running */ evpe(EVPE_ENABLE); + list_for_each_entry(n, &v->notify, list) { + n->start(v->minor); + } + return 0; } @@ -803,7 +839,7 @@ struct module mod; // so we can re-use the relocations code memset(&mod, 0, sizeof(struct module)); - strcpy(mod.name, "VPE dummy prog module"); + strcpy(mod.name, "VPE loader"); hdr = (Elf_Ehdr *) v->pbuffer; len = v->plen; @@ -873,6 +909,9 @@ sechdrs[i].sh_size); /* Update sh_addr to point to copy in image. */ sechdrs[i].sh_addr = (unsigned long)dest; + + printk(KERN_DEBUG " section sh_name %s sh_addr 0x%x\n", + secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr); } /* Fix up syms, so that st_value is a pointer to location. */ @@ -940,11 +979,56 @@ } } -/* checks for VPE is unused and gets ready to load program */ +static void cleanup_tc(struct tc *tc) +{ + int tmp; + + /* Put MVPE's into 'configuration state' */ + write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_VPC); + + settc(tc->index); + tmp = read_tc_c0_tcstatus(); + + /* mark not allocated and not dynamically allocatable */ + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ + write_tc_c0_tcstatus(tmp); + + write_tc_c0_tchalt(TCHALT_H); + + /* clear out any left overs from a previous program */ + write_vpe_c0_cause(0); + + /* clear interrupts enabled IE, ERL, EXL, and KSU from c0 status */ + write_vpe_c0_status(read_vpe_c0_status() & ~(ST0_ERL | ST0_KSU | ST0_IE | ST0_EXL)); + + /* bind it to anything other than VPE1 */ + write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE + + write_c0_mvpcontrol(read_c0_mvpcontrol() & ~MVPCONTROL_VPC); +} + +static int getcwd(char *buff, int size) +{ + mm_segment_t old_fs; + int ret; + + old_fs = get_fs(); + set_fs (KERNEL_DS); + + ret = sys_getcwd(buff,size); + + set_fs(old_fs); + + return ret; +} + +/* checks VPE is unused and gets ready to load program */ static int vpe_open(struct inode *inode, struct file *filp) { - int minor; + int minor, ret; vpe_t *v; + struct vpe_notifications *not; /* assume only 1 device at the mo. */ if ((minor = MINOR(inode->i_rdev)) != 1) { @@ -958,31 +1042,16 @@ } if (v->state != VPE_STATE_UNUSED) { - unsigned long tmp; - struct tc *t; - - printk(KERN_WARNING "VPE: device %d already in use\n", minor); - dvpe(); - dump_vpe(v); - - printk(KERN_WARNING "VPE: re-initialising %d\n", minor); - + + list_for_each_entry(not, &v->notify, list) { + not->stop(minor); + } + release_progmem(v->load_addr); - - t = get_tc(minor); - settc(minor); - tmp = read_tc_c0_tcstatus(); - - /* mark not allocated and not dynamically allocatable */ - tmp &= ~(TCSTATUS_A | TCSTATUS_DA); - tmp |= TCSTATUS_IXMT; /* interrupt exempt */ - write_tc_c0_tcstatus(tmp); - - write_tc_c0_tchalt(TCHALT_H); - + cleanup_tc(get_tc(minor)); } - + // allocate it so when we get write ops we know it's expected. v->state = VPE_STATE_INUSE; @@ -992,6 +1061,20 @@ v->load_addr = NULL; v->len = 0; + v->uid = filp->f_uid; + v->gid = filp->f_gid; + + /* get kspd to tell us when a syscall_exit happens */ + if( !kspd_events_reqd ) { + kspd_notify( &kspd_events ); + kspd_events_reqd++; + } + + v->cwd[0] = 0; + if ((ret = getcwd(v->cwd, VPE_PATH_MAX)) < 0) { + printk("VPE: open, getcwd returned %d\n", ret); + } + return 0; } @@ -1165,7 +1248,65 @@ EXPORT_SYMBOL(vpe_get_shared); -static int __init vpe_module_init(void) +int vpe_getuid(int index) +{ + struct vpe *v; + + if ((v = get_vpe(index)) == NULL) { + printk(KERN_WARNING "vpe: invalid vpe index %d\n", index); + return -1; + } + + return v->uid; +} +EXPORT_SYMBOL(vpe_getuid); + +int vpe_getgid(int index) +{ + struct vpe *v; + + if ((v = get_vpe(index)) == NULL) { + printk(KERN_WARNING "vpe: invalid vpe index %d\n", index); + return -1; + } + + return v->gid; +} +EXPORT_SYMBOL(vpe_getgid); + +int vpe_notify(int index, struct vpe_notifications *notify) +{ + struct vpe *v; + + if ((v = get_vpe(index)) == NULL) { + printk(KERN_WARNING "vpe: invalid vpe index %d\n", index); + return -1; + } + + list_add(¬ify->list, &v->notify); + return 0; +} +EXPORT_SYMBOL(vpe_notify); + +char *vpe_getcwd(int index) +{ + struct vpe *v; + + if ((v = get_vpe(index)) == NULL) { + printk(KERN_WARNING "vpe: invalid vpe index %d\n", index); + return NULL; + } + + return v->cwd; +} +EXPORT_SYMBOL(vpe_getcwd); + +static void kspd_sp_exit( int sp_id) +{ + cleanup_tc(get_tc(sp_id)); +} + +static int vpe_module_init(void) { struct vpe *v = NULL; struct tc *t; @@ -1209,7 +1350,8 @@ return -ENODEV; } - list_add(&t->tc, &v->tc); /* add the tc to the list of this vpe's tc's. */ + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); /* deactivate all but vpe0 */ if (i != 0) { @@ -1230,35 +1372,40 @@ ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0); - /* set config to be the same as vpe0, particularly kseg0 coherency alg */ + /* set config to be the same as vpe0, + particularly kseg0 coherency alg */ write_vpe_c0_config(read_c0_config()); } - } - + /* TC's */ t->pvpe = v; /* set the parent vpe */ if (i != 0) { unsigned long tmp; - /* tc 0 will of course be running.... */ - if (i == 0) - t->state = TC_STATE_RUNNING; - settc(i); - /* bind a TC to each VPE, May as well put all excess TC's - on the last VPE */ - if (i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1)) - write_tc_c0_tcbind(read_tc_c0_tcbind() | - ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)); - else - write_tc_c0_tcbind(read_tc_c0_tcbind() | i); + /* Any TC that is bound to VPE0 gets left as is - in case + we are running SMTC on VPE0. A TC that is bound to any + other VPE gets bound to VPE0, ideally I'd like to make + it homeless but it doesn't appear to let me bind a TC + to a non-existent VPE. Which is perfectly reasonable. + + The (un)bound state is visible to an EJTAG probe so may + notify GDB... + */ + + if (((tmp = read_tc_c0_tcbind()) & TCBIND_CURVPE)) { + /* tc is bound >vpe0 */ + write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE); + t->pvpe = get_vpe(0); /* set the parent vpe */ + } + tmp = read_tc_c0_tcstatus(); - /* mark not allocated and not dynamically allocatable */ + /* mark not activated and not dynamically allocatable */ tmp &= ~(TCSTATUS_A | TCSTATUS_DA); tmp |= TCSTATUS_IXMT; /* interrupt exempt */ write_tc_c0_tcstatus(tmp); @@ -1270,10 +1417,12 @@ /* release config state */ write_c0_mvpcontrol(read_c0_mvpcontrol() & ~MVPCONTROL_VPC); + kspd_events.kspd_sp_exit = kspd_sp_exit; + return 0; } -static void __exit vpe_module_exit(void) +static void vpe_module_exit(void) { struct vpe *v, *n; diff -urN malta/linux/include/asm-mips/kspd.h malta/linux/include/asm-mips/kspd.h --- malta/linux/include/asm-mips/Attic/kspd.h 1970/01/01 00:00:00 +++ malta/linux/include/asm-mips/Attic/kspd.h 2005-07-27 14:38:04.682649000 +0100 1.1.1000.1 @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#ifndef _ASM_KSPD_H +#define _ASM_KSPD_H + +struct kspd_notifications { + void (*kspd_sp_exit)(int sp_id); + + struct list_head list; +}; + +extern void kspd_notify(struct kspd_notifications *notify); + +#endif diff -urN malta/linux/include/asm-mips/vpe.h malta/linux/include/asm-mips/vpe.h --- malta/linux/include/asm-mips/Attic/vpe.h 1970/01/01 00:00:00 +++ malta/linux/include/asm-mips/Attic/vpe.h 2005-07-27 14:38:04.724691000 +0100 1.1.1000.1 @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#ifndef _ASM_VPE_H +#define _ASM_VPE_H + +struct vpe_notifications { + void (*start)(int vpe); + void (*stop)(int vpe); + + struct list_head list; +}; + + +extern int vpe_notify(int index, struct vpe_notifications *notify); + +extern void *vpe_get_shared(int index); +extern int vpe_getuid(int index); +extern int vpe_getgid(int index); +extern char *vpe_getcwd(int index); + +#endif diff -urN malta/linux/include/asm-mips/rtlx.h malta/linux/include/asm-mips/rtlx.h --- malta/linux/include/asm-mips/rtlx.h 2005/07/14 15:57:17 1.1 +++ malta/linux/include/asm-mips/rtlx.h 2005/07/27 13:38:04 1.1.1000.1 @@ -3,12 +3,12 @@ * */ -#ifndef _RTLX_H -#define _RTLX_H_ +#ifndef _ASM_RTLX_H +#define _ASM_RTLX_H_ #define LX_NODE_BASE 10 -#define MIPSCPU_INT_BASE 16 +#define MIPSCPU_INT_BASE 16 #define MIPS_CPU_RTLX_IRQ 0 #define RTLX_VERSION 1 @@ -16,6 +16,17 @@ #define RTLX_ID (RTLX_xID | RTLX_VERSION) #define RTLX_CHANNELS 8 +#define RTLX_CHANNEL_STDIO 0 +#define RTLX_CHANNEL_DBG 1 +#define RTLX_CHANNEL_SYSIO 2 + +extern int rtlx_open(int index, int can_sleep); +extern int rtlx_release(int index); +extern ssize_t rtlx_read(int index, void *buff, size_t count, int user); +extern ssize_t rtlx_write(int index, void *buffer, size_t count, int user); +extern unsigned int rtlx_read_poll(int index, int can_sleep); +extern unsigned int rtlx_write_poll(int index); + enum rtlx_state { RTLX_STATE_UNUSED = 0, RTLX_STATE_INITIALISED, From beth@linux-mips.org Wed Jul 27 14:17:19 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Wed, 27 Jul 2005 15:17:19 +0100 (BST) From: beth@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Wed, 27 Jul 2005 15:17:19 +0100 X-archive-position: 16 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: beth@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: beth@ftp.linux-mips.org 05/07/27 15:17:18 Modified files: linux/arch/mips: Tag: MaltaRef_2_6 Kconfig Log message: Make selecting the VPE loader and APSP stuff more friendly. diff -urN malta/linux/arch/mips/Kconfig malta/linux/arch/mips/Kconfig --- malta/linux/arch/mips/Kconfig 2005/07/27 13:37:39 1.73.1000.7 +++ malta/linux/arch/mips/Kconfig 2005/07/27 14:17:17 1.73.1000.8 @@ -1153,6 +1153,7 @@ config MIPS_VPE_LOADER bool "VPE loader support." depends on MIPS_MT + select MODULES help Includes a loader for loading an elf relocatable object onto another VPE and running it. @@ -1171,11 +1172,13 @@ config MIPS_VPE_APSP_API bool "Enable support for AP/SP API (RTLX)" depends on MIPS_VPE_LOADER + default y help config MIPS_APSP_KSPD bool "Enable KSPD" depends on MIPS_VPE_APSP_API + default y help KSPD is a kernel daemon that accepts syscall requests from the SP side, actions them and returns the results. It also handles the "exit" syscall From beth@linux-mips.org Wed Jul 27 14:25:21 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Wed, 27 Jul 2005 15:25:21 +0100 (BST) From: beth@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Wed, 27 Jul 2005 15:25:21 +0100 X-archive-position: 17 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: beth@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: beth@ftp.linux-mips.org 05/07/27 15:25:20 Modified files: linux/arch/mips/mips-boards/generic: Tag: MaltaRef_2_6 init.c Log message: Make it compile with debug enabled. diff -urN malta/linux/arch/mips/mips-boards/generic/init.c malta/linux/arch/mips/mips-boards/generic/init.c --- malta/linux/arch/mips/mips-boards/generic/init.c 2005/06/21 13:24:12 1.17.1000.3 +++ malta/linux/arch/mips/mips-boards/generic/init.c 2005/07/27 14:25:20 1.17.1000.4 @@ -220,7 +220,6 @@ generic_putDebugChar (*s++); } - kgdb_enabled = 1; /* Breakpoint is invoked after interrupts are initialised */ } } From chris@linux-mips.org Thu Jul 28 17:19:39 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:19:40 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:19:39 +0100 X-archive-position: 18 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:19:38 Modified files: linux/arch/mips/mips-boards/generic: Tag: MaltaRef_2_6 init.c pci.c linux/arch/mips/mips-boards/malta: Tag: MaltaRef_2_6 malta_int.c linux/include/asm-mips/mips-boards: Tag: MaltaRef_2_6 generic.h Log message: * include/asm-mips/mips-boards/generic.h (MIPS_REVISION_CORID_CORE_FPGA3): CoreFPGA3 support. * arch/mips/mips-boards/malta/malta_int.c (mips_pcibios_iack): CoreFPGA3 support. (get_int): Spurious interrupt detection doesn't work on SMP because it requires atomic access to the interrupt controller. Rely on the generic code to detect spurious interrupts. (corehi_irqdispatch): CoreFPGA3 support. (arch_init_irq): CoreFPGA3 support * arch/mips/mips-boards/generic/pci.c (pcibios_init): CoreFPGA3 support. * arch/mips/mips-boards/generic/init.c (prom_init): CoreFPGA3 support. diff -urN malta/linux/arch/mips/mips-boards/generic/init.c malta/linux/arch/mips/mips-boards/generic/init.c --- malta/linux/arch/mips/mips-boards/generic/init.c 2005/07/27 14:25:20 1.17.1000.4 +++ malta/linux/arch/mips/mips-boards/generic/init.c 2005/07/28 17:19:38 1.17.1000.5 @@ -336,6 +336,7 @@ case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); diff -urN malta/linux/arch/mips/mips-boards/generic/pci.c malta/linux/arch/mips/mips-boards/generic/pci.c --- malta/linux/arch/mips/mips-boards/generic/pci.c 2005/06/21 13:24:12 1.26.1000.3 +++ malta/linux/arch/mips/mips-boards/generic/pci.c 2005/07/28 17:19:38 1.26.1000.4 @@ -197,6 +197,7 @@ case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: /* Set up resource ranges from the controller's registers. */ MSC_READ(MSC01_PCI_SC2PMBASL, start); diff -urN malta/linux/arch/mips/mips-boards/malta/malta_int.c malta/linux/arch/mips/mips-boards/malta/malta_int.c --- malta/linux/arch/mips/mips-boards/malta/malta_int.c 2005/06/21 13:24:13 1.20.1000.3 +++ malta/linux/arch/mips/mips-boards/malta/malta_int.c 2005/07/28 17:19:38 1.20.1000.4 @@ -57,6 +57,7 @@ switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: MSC_READ(MSC01_PCI_IACK, irq); irq &= 0xff; @@ -103,22 +104,10 @@ irq = mips_pcibios_iack(); /* - * IRQ7 is used to detect spurious interrupts. - * The interrupt acknowledge cycle returns IRQ7, if no - * interrupts is requested. - * We can differentiate between this situation and a - * "Normal" IRQ7 by reading the ISR. + * The only way we can decide if an interrupt is spurious + * is by checking the 8259 registers. This needs a spinlock + * on an SMP system, so leave it up to the generic code... */ - if (irq == 7) - { - outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, - PIIX4_ICTLR1_OCW3); - if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) { - irq = -1; /* Spurious interrupt */ - printk("We got a spurious interrupt from PIIX4.\n"); - atomic_inc(&irq_err_count); - } - } spin_unlock_irqrestore(&mips_irq_lock, flags); @@ -153,6 +142,7 @@ switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: ll_msc_irq(regs); break; @@ -233,6 +223,7 @@ switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: if (cpu_has_veic) init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); diff -urN malta/linux/include/asm-mips/mips-boards/generic.h malta/linux/include/asm-mips/mips-boards/generic.h --- malta/linux/include/asm-mips/mips-boards/generic.h 2004/01/20 13:04:44 1.6 +++ malta/linux/include/asm-mips/mips-boards/generic.h 2005/07/28 17:19:38 1.6.1000.1 @@ -66,6 +66,7 @@ #define MIPS_REVISION_CORID_CORE_EMUL 6 #define MIPS_REVISION_CORID_CORE_FPGA2 7 #define MIPS_REVISION_CORID_CORE_FPGAR2 8 +#define MIPS_REVISION_CORID_CORE_FPGA3 9 /**** Artificial corid defines ****/ /* From chris@linux-mips.org Thu Jul 28 17:20:32 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:20:32 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:20:32 +0100 X-archive-position: 19 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:20:31 Modified files: linux/init : Tag: MaltaRef_2_6 Kconfig Log message: * init/Kconfig: Support -Os on MIPS diff -urN malta/linux/init/Kconfig malta/linux/init/Kconfig --- malta/linux/init/Kconfig 2005/06/21 13:38:18 1.18.1000.3 +++ malta/linux/init/Kconfig 2005/07/28 17:20:31 1.18.1000.4 @@ -321,7 +321,7 @@ config CC_OPTIMIZE_FOR_SIZE bool "Optimize for size" if EMBEDDED - default y if ARM || H8300 + default y if ARM || H8300 || MIPS help Enabling this option will pass "-Os" instead of "-O2" to gcc resulting in a smaller kernel. From chris@linux-mips.org Thu Jul 28 17:21:35 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:21:35 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:21:35 +0100 X-archive-position: 20 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:21:34 Modified files: linux/include/asm-mips/mach-mips: Tag: MaltaRef_2_6 cpu-feature-overrides.h Log message: * include/asm-mips/mach-mips/cpu-feature-overrides.h (cpu_icache_snoops_remote_store): Always true(?) diff -urN malta/linux/include/asm-mips/mach-mips/cpu-feature-overrides.h malta/linux/include/asm-mips/mach-mips/cpu-feature-overrides.h --- malta/linux/include/asm-mips/mach-mips/cpu-feature-overrides.h 2005/06/21 13:36:40 1.1.1000.2 +++ malta/linux/include/asm-mips/mach-mips/cpu-feature-overrides.h 2005/07/28 17:21:34 1.1.1000.3 @@ -37,6 +37,7 @@ /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_subset_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 #endif #ifdef CONFIG_CPU_MIPS64 @@ -62,6 +63,7 @@ /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_subset_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 #endif #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ From chris@linux-mips.org Thu Jul 28 17:21:50 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:21:50 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:21:50 +0100 X-archive-position: 21 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:21:49 Modified files: linux/include/asm-mips: Tag: MaltaRef_2_6 system.h Log message: * include/asm-mips/system.h: comment typo diff -urN malta/linux/include/asm-mips/system.h malta/linux/include/asm-mips/system.h --- malta/linux/include/asm-mips/system.h 2005/06/21 13:36:24 1.69.1000.3 +++ malta/linux/include/asm-mips/system.h 2005/07/28 17:21:49 1.69.1000.4 @@ -71,7 +71,7 @@ * does not enforce ordering, since there is no data dependency between * the read of "a" and the read of "b". Therefore, on some CPUs, such * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() - * in cases like thiswhere there are no data dependencies. + * in cases like this where there are no data dependencies. */ #define read_barrier_depends() do { } while(0) From chris@linux-mips.org Thu Jul 28 17:22:01 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:22:01 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:22:01 +0100 X-archive-position: 22 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:22:00 Modified files: linux/include/asm-mips: Tag: MaltaRef_2_6 spinlock.h Log message: * include/asm-mips/spinlock.h: Added DEBUG_SPINLOCK support. diff -urN malta/linux/include/asm-mips/spinlock.h malta/linux/include/asm-mips/spinlock.h --- malta/linux/include/asm-mips/spinlock.h 2005/06/21 13:36:24 1.23.1000.2 +++ malta/linux/include/asm-mips/spinlock.h 2005/07/28 17:22:00 1.23.1000.3 @@ -18,14 +18,25 @@ typedef struct { volatile unsigned int lock; +#ifdef CONFIG_DEBUG_SPINLOCK + unsigned int magic; +#endif #ifdef CONFIG_PREEMPT unsigned int break_lock; #endif } spinlock_t; -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } +#define SPINLOCK_MAGIC 0xdead4ead + +#ifdef CONFIG_DEBUG_SPINLOCK +#define SPINLOCK_MAGIC_INIT , SPINLOCK_MAGIC +#else +#define SPINLOCK_MAGIC_INIT /* */ +#endif -#define spin_lock_init(x) do { (x)->lock = 0; } while(0) +#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 SPINLOCK_MAGIC_INIT } + +#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0) #define spin_is_locked(x) ((x)->lock != 0) #define spin_unlock_wait(x) do { barrier(); } while ((x)->lock) @@ -42,6 +53,14 @@ { unsigned int tmp; +#ifdef CONFIG_DEBUG_SPINLOCK +here: + if (unlikely(lock->magic != SPINLOCK_MAGIC)) { + printk("eip: %p\n", &&here); + BUG(); + } +#endif + if (R10000_LLSC_WAR) { __asm__ __volatile__( " .set noreorder # _raw_spin_lock \n" @@ -74,6 +93,10 @@ static inline void _raw_spin_unlock(spinlock_t *lock) { +#ifdef CONFIG_DEBUG_SPINLOCK + BUG_ON(lock->magic != SPINLOCK_MAGIC); + BUG_ON(!spin_is_locked(lock)); +#endif __asm__ __volatile__( " .set noreorder # _raw_spin_unlock \n" " sync \n" @@ -131,12 +154,23 @@ typedef struct { volatile unsigned int lock; +#ifdef CONFIG_DEBUG_SPINLOCK + unsigned magic; +#endif #ifdef CONFIG_PREEMPT unsigned int break_lock; #endif } rwlock_t; -#define RW_LOCK_UNLOCKED (rwlock_t) { 0 } +#define RWLOCK_MAGIC 0xdeaf1eed + +#ifdef CONFIG_DEBUG_SPINLOCK +#define RWLOCK_MAGIC_INIT , RWLOCK_MAGIC +#else +#define RWLOCK_MAGIC_INIT /* */ +#endif + +#define RW_LOCK_UNLOCKED (rwlock_t) { 0 RWLOCK_MAGIC_INIT } #define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0) @@ -156,6 +190,9 @@ { unsigned int tmp; +#ifdef CONFIG_DEBUG_SPINLOCK + BUG_ON(rw->magic != RWLOCK_MAGIC); +#endif if (R10000_LLSC_WAR) { __asm__ __volatile__( " .set noreorder # _raw_read_lock \n" @@ -193,6 +230,9 @@ { unsigned int tmp; +#ifdef CONFIG_DEBUG_SPINLOCK + BUG_ON(rw->magic != RWLOCK_MAGIC); +#endif if (R10000_LLSC_WAR) { __asm__ __volatile__( "1: ll %1, %2 # _raw_read_unlock \n" @@ -222,6 +262,9 @@ { unsigned int tmp; +#ifdef CONFIG_DEBUG_SPINLOCK + BUG_ON(rw->magic != RWLOCK_MAGIC); +#endif if (R10000_LLSC_WAR) { __asm__ __volatile__( " .set noreorder # _raw_write_lock \n" @@ -253,6 +296,9 @@ static inline void _raw_write_unlock(rwlock_t *rw) { +#ifdef CONFIG_DEBUG_SPINLOCK + BUG_ON(rw->magic != RWLOCK_MAGIC); +#endif __asm__ __volatile__( " sync # _raw_write_unlock \n" " sw $0, %0 \n" @@ -268,6 +314,9 @@ unsigned int tmp; int ret; +#ifdef CONFIG_DEBUG_SPINLOCK + BUG_ON(rw->magic != RWLOCK_MAGIC); +#endif if (R10000_LLSC_WAR) { __asm__ __volatile__( " .set noreorder # _raw_write_trylock \n" From chris@linux-mips.org Thu Jul 28 17:22:14 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:22:14 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:22:14 +0100 X-archive-position: 23 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:22:13 Modified files: linux/include/asm-mips: Tag: MaltaRef_2_6 mipsmtregs.h Log message: * include/asm-mips/mipsmtregs.h: Minor formatting changes diff -urN malta/linux/include/asm-mips/mipsmtregs.h malta/linux/include/asm-mips/mipsmtregs.h --- malta/linux/include/asm-mips/mipsmtregs.h 2005/07/20 15:45:59 1.2.1000.1 +++ malta/linux/include/asm-mips/mipsmtregs.h 2005/07/28 17:22:13 1.2.1000.2 @@ -33,7 +33,7 @@ #define read_c0_tcbind() __read_32bit_c0_register($2, 2) #define read_c0_tccontext() __read_32bit_c0_register($2, 5) -#define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) +#define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) #else /* Assembly */ /* @@ -71,7 +71,7 @@ #define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT) #define MVPCONTROL_STLB_SHIFT 2 -#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) +#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) /* MVPConf0 fields */ @@ -235,8 +235,8 @@ " .set reorder"); } -/* enable multiVPE if previous suggested it should be. - EVPE_ENABLE to force */ +/* enable multiMT if previous suggested it should be. + EMT_ENABLE to force */ #define EMT_ENABLE VPECONTROL_TE @@ -251,8 +251,6 @@ __asm__ __volatile__("ehb"); } -// rt rd swapped in the documentation? -// idioms appear to be plausible. #define mftc0(rt,sel) \ ({ \ unsigned long __res; \ @@ -330,7 +328,7 @@ #define read_vpe_c0_status() mftc0($12, 0) #define write_vpe_c0_status(val) mttc0($12, 0, val) #define read_vpe_c0_cause() mftc0($13, 0) -#define write_vpe_c0_cause(val) mttc0($13, 0, val) +#define write_vpe_c0_cause(val) mttc0($13, 0, val) #define read_vpe_c0_config() mftc0($16, 0) #define write_vpe_c0_config(val) mttc0($16, 0, val) #define read_vpe_c0_config1() mftc0($16, 1) @@ -338,7 +336,7 @@ #define read_vpe_c0_config7() mftc0($16, 7) #define write_vpe_c0_config7(val) mttc0($16, 7, val) #define read_vpe_c0_ebase() mftc0($15,1) -#define write_vpe_c0_ebase(val) mttc0($15, 1, val) +#define write_vpe_c0_ebase(val) mttc0($15, 1, val) #define write_vpe_c0_compare(val) mttc0($11, 0, val) @@ -346,11 +344,11 @@ #define read_tc_c0_tcstatus() mftc0($2, 1) #define write_tc_c0_tcstatus(val) mttc0($2,1,val) #define read_tc_c0_tcbind() mftc0($2, 2) -#define write_tc_c0_tcbind(val) mttc0($2,2,val) +#define write_tc_c0_tcbind(val) mttc0($2,2,val) #define read_tc_c0_tcrestart() mftc0($2, 3) #define write_tc_c0_tcrestart(val) mttc0($2,3,val) #define read_tc_c0_tchalt() mftc0($2, 4) -#define write_tc_c0_tchalt(val) mttc0($2,4,val) +#define write_tc_c0_tchalt(val) mttc0($2,4,val) #define read_tc_c0_tccontext() mftc0($2, 5) #define write_tc_c0_tccontext(val) mttc0($2,5,val) From chris@linux-mips.org Thu Jul 28 17:23:50 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:23:50 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:23:50 +0100 X-archive-position: 24 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:23:49 Modified files: linux/arch/mips/kernel: Tag: MaltaRef_2_6 cpu-probe.c proc.c setup.c linux/include/asm-mips: Tag: MaltaRef_2_6 cpu-features.h cpu.h Log message: * include/asm-mips/cpu.h (MIPS_ASE_MIPSMT): ASE, not option. * include/asm-mips/cpu-features.h (cpu_has_mipsmt): MIPSMT is an ASE, not an option. * arch/mips/kernel/setup.c (setup_arch): Initialise current->switch_lock.lock (primarily for spinlock debugging) (dsp_disable): DSP is an ase, not an option. * arch/mips/kernel/proc.c (show_cpuinfo): Report DSP and MT ASEs. * arch/mips/kernel/cpu-probe.c: MIPS_CPU_VINT and MIPS_CPU_VEIC go in options and not ases. MIPSMT is an ase, not an option. diff -urN malta/linux/arch/mips/kernel/cpu-probe.c malta/linux/arch/mips/kernel/cpu-probe.c --- malta/linux/arch/mips/kernel/cpu-probe.c 2005/06/21 13:24:02 1.35.1000.6 +++ malta/linux/arch/mips/kernel/cpu-probe.c 2005/07/28 17:23:49 1.35.1000.7 @@ -505,11 +505,11 @@ if (config3 & MIPS_CONF3_DSP) c->ases |= MIPS_ASE_DSP; if (config3 & MIPS_CONF3_VINT) - c->ases |= MIPS_CPU_VINT; + c->options |= MIPS_CPU_VINT; if (config3 & MIPS_CONF3_VEIC) - c->ases |= MIPS_CPU_VEIC; + c->options |= MIPS_CPU_VEIC; if (config3 & MIPS_CONF3_MT) - c->ases |= MIPS_CPU_MIPSMT; + c->ases |= MIPS_ASE_MIPSMT; return config3 & MIPS_CONF_M; } diff -urN malta/linux/arch/mips/kernel/proc.c malta/linux/arch/mips/kernel/proc.c --- malta/linux/arch/mips/kernel/proc.c 2005/06/21 13:24:03 1.53.1000.2 +++ malta/linux/arch/mips/kernel/proc.c 2005/07/28 17:23:49 1.53.1000.3 @@ -120,11 +120,14 @@ cpu_has_divec ? "yes" : "no"); seq_printf(m, "hardware watchpoint\t: %s\n", cpu_has_watch ? "yes" : "no"); - seq_printf(m, "ASEs implemented\t:%s%s%s%s\n", + seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", cpu_has_mips16 ? " mips16" : "", cpu_has_mdmx ? " mdmx" : "", cpu_has_mips3d ? " mips3d" : "", - cpu_has_smartmips ? " smartmips" : ""); + cpu_has_smartmips ? " smartmips" : "", + cpu_has_dsp ? " dsp" : "", + cpu_has_mipsmt ? " mipsmt" : "" + ); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", cpu_has_vce ? "%u" : "not available"); diff -urN malta/linux/arch/mips/kernel/setup.c malta/linux/arch/mips/kernel/setup.c --- malta/linux/arch/mips/kernel/setup.c 2005/06/21 13:24:03 1.168.1000.3 +++ malta/linux/arch/mips/kernel/setup.c 2005/07/28 17:23:49 1.168.1000.4 @@ -539,6 +539,10 @@ prom_init(); cpu_report(); +#if defined(CONFIG_SMP) + current->switch_lock.lock = 1; +#endif + #if defined(CONFIG_VT) #if defined(CONFIG_VGA_CONSOLE) conswitchp = &vga_con; @@ -572,7 +576,7 @@ int __init dsp_disable(char *s) { - cpu_data[0].options &= ~MIPS_ASE_DSP; + cpu_data[0].ases &= ~MIPS_ASE_DSP; return 1; } diff -urN malta/linux/include/asm-mips/cpu-features.h malta/linux/include/asm-mips/cpu-features.h --- malta/linux/include/asm-mips/cpu-features.h 2005/06/21 13:36:22 1.4.1000.4 +++ malta/linux/include/asm-mips/cpu-features.h 2005/07/28 17:23:49 1.4.1000.5 @@ -120,7 +120,7 @@ #define PLAT_TRAMPOLINE_STUFF_LINE 0UL #endif #ifndef cpu_has_mipsmt -# define cpu_has_mipsmt (cpu_data[0].ases & MIPS_CPU_MIPSMT) +# define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) #endif #ifdef CONFIG_MIPS32 diff -urN malta/linux/include/asm-mips/cpu.h malta/linux/include/asm-mips/cpu.h --- malta/linux/include/asm-mips/cpu.h 2005/06/21 13:36:23 1.52.1000.3 +++ malta/linux/include/asm-mips/cpu.h 2005/07/28 17:23:49 1.52.1000.4 @@ -228,7 +228,6 @@ #define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ -#define MIPS_CPU_MIPSMT 0x00400000 /* CPU supports MIPS MT */ /* * CPU ASE encodings @@ -238,5 +237,7 @@ #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ +#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ + #endif /* _ASM_CPU_H */ From chris@linux-mips.org Thu Jul 28 17:24:17 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:24:17 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:24:17 +0100 X-archive-position: 25 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:24:16 Modified files: linux/drivers/serial: Tag: MaltaRef_2_6 8250.c Log message: * drivers/serial/8250.c (serial8250_console_write): Grab spinlock before modifying the interrupt mask register. diff -urN malta/linux/drivers/serial/8250.c malta/linux/drivers/serial/8250.c --- malta/linux/drivers/serial/8250.c 2005/06/21 13:33:05 1.21.1000.3 +++ malta/linux/drivers/serial/8250.c 2005/07/28 17:24:16 1.21.1000.4 @@ -2115,8 +2115,11 @@ unsigned int ier; int i; + spin_lock(&up->port.lock); + + /* - * First save the UER then disable the interrupts + * First save the IER then disable the interrupts */ ier = serial_in(up, UART_IER); @@ -2148,6 +2151,8 @@ */ wait_for_xmitr(up); serial_out(up, UART_IER, ier); + + spin_unlock(&up->port.lock); } static int serial8250_console_setup(struct console *co, char *options) From chris@linux-mips.org Thu Jul 28 17:24:25 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:24:25 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:24:25 +0100 X-archive-position: 26 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:24:24 Modified files: linux/arch/mips/sibyte/sb1250: Tag: MaltaRef_2_6 time.c Log message: * arch/mips/sibyte/sb1250/time.c (sb1250_timer_interrupt): ll_timer_interrupt calls ll_local_timer_interrupt. diff -urN malta/linux/arch/mips/sibyte/sb1250/time.c malta/linux/arch/mips/sibyte/sb1250/time.c --- malta/linux/arch/mips/sibyte/sb1250/time.c 2005/06/21 13:24:27 1.15.1000.1 +++ malta/linux/arch/mips/sibyte/sb1250/time.c 2005/07/28 17:24:23 1.15.1000.2 @@ -108,17 +108,18 @@ ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); - /* - * CPU 0 handles the global timer interrupt job - */ if (cpu == 0) { + /* + * CPU 0 handles the global timer interrupt job + */ ll_timer_interrupt(irq, regs); } - - /* - * every CPU should do profiling and process accouting - */ - ll_local_timer_interrupt(irq, regs); + else { + /* + * other CPUs should just do profiling and process accounting + */ + ll_local_timer_interrupt(irq, regs); + } } /* From chris@linux-mips.org Thu Jul 28 17:24:54 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:24:55 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:24:55 +0100 X-archive-position: 27 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:24:53 Modified files: linux/arch/mips/lib-32: Tag: MaltaRef_2_6 dump_tlb.c Log message: * arch/mips/lib-32/dump_tlb.c (dump_list_process): Don't crash if t->mm is not set. diff -urN malta/linux/arch/mips/lib-32/dump_tlb.c malta/linux/arch/mips/lib-32/dump_tlb.c --- malta/linux/arch/mips/lib-32/dump_tlb.c 2005/06/21 13:24:06 1.3.1000.1 +++ malta/linux/arch/mips/lib-32/dump_tlb.c 2005/07/28 17:24:53 1.3.1000.2 @@ -151,41 +151,49 @@ if (addr > KSEG0) page_dir = pgd_offset_k(0); - else + else if (t->mm) page_dir = pgd_offset(t->mm, 0); + else + page_dir = NULL; + printk("page_dir == %08x\n", (unsigned int) page_dir); if (addr > KSEG0) pgd = pgd_offset_k(addr); - else + else if (t->mm) pgd = pgd_offset(t->mm, addr); + else + pgd = NULL; + printk("pgd == %08x, ", (unsigned int) pgd); - pud = pud_offset(pgd, addr); - printk("pud == %08x, ", (unsigned int) pud); + if (pgd) { + pud = pud_offset(pgd, addr); + printk("pud == %08x, ", (unsigned int) pud); - pmd = pmd_offset(pud, addr); - printk("pmd == %08x, ", (unsigned int) pmd); + pmd = pmd_offset(pud, addr); + printk("pmd == %08x, ", (unsigned int) pmd); - pte = pte_offset(pmd, addr); - printk("pte == %08x, ", (unsigned int) pte); + pte = pte_offset(pmd, addr); + printk("pte == %08x, ", (unsigned int) pte); - page = *pte; + page = *pte; #ifdef CONFIG_64BIT_PHYS_ADDR - printk("page == %08Lx\n", pte_val(page)); + printk("page == %08Lx\n", pte_val(page)); #else - printk("page == %08lx\n", pte_val(page)); + printk("page == %08lx\n", pte_val(page)); #endif - val = pte_val(page); - if (val & _PAGE_PRESENT) printk("present "); - if (val & _PAGE_READ) printk("read "); - if (val & _PAGE_WRITE) printk("write "); - if (val & _PAGE_ACCESSED) printk("accessed "); - if (val & _PAGE_MODIFIED) printk("modified "); - if (val & _PAGE_R4KBUG) printk("r4kbug "); - if (val & _PAGE_GLOBAL) printk("global "); - if (val & _PAGE_VALID) printk("valid "); + val = pte_val(page); + if (val & _PAGE_PRESENT) printk("present "); + if (val & _PAGE_READ) printk("read "); + if (val & _PAGE_WRITE) printk("write "); + if (val & _PAGE_ACCESSED) printk("accessed "); + if (val & _PAGE_MODIFIED) printk("modified "); + if (val & _PAGE_R4KBUG) printk("r4kbug "); + if (val & _PAGE_GLOBAL) printk("global "); + if (val & _PAGE_VALID) printk("valid "); + } printk("\n"); } From chris@linux-mips.org Thu Jul 28 17:25:18 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:25:19 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:25:19 +0100 X-archive-position: 28 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:25:18 Modified files: linux/arch/mips/kernel: Tag: MaltaRef_2_6 smp.c Log message: * arch/mips/kernel/smp.c (smp_tune_scheduling): Remove unused bandwidth variable. (smp_call_function): kgdb_wait needs special handling. Clear call_data before smp_call_function returns. (smp_call_function_interrupt): Check for call_data being set... catches case where unexpect IPI occurs. diff -urN malta/linux/arch/mips/kernel/smp.c malta/linux/arch/mips/kernel/smp.c --- malta/linux/arch/mips/kernel/smp.c 2005/06/21 13:24:03 1.66.1000.2 +++ malta/linux/arch/mips/kernel/smp.c 2005/07/28 17:25:17 1.66.1000.3 @@ -50,7 +50,6 @@ { struct cache_desc *cd = ¤t_cpu_data.scache; unsigned long cachesize; /* kB */ - unsigned long bandwidth = 350; /* MB/s */ unsigned long cpu_khz; /* @@ -145,8 +144,32 @@ if (!cpus) return 0; - /* Can deadlock when called with interrupts disabled */ +#ifdef CONFIG_KGDB + /* GDB will call this function with interrupts disabled, so it gets special handling */ + { + extern void kgdb_wait(void *); + if (func == kgdb_wait) { + if (spin_is_locked(&smp_call_lock)) { + /* + * Some other processor is trying to make us do something + * but we're not going to respond... give up + */ + return -1; + } + /* + * We will continue here, accepting the fact that + * the kernel may deadlock if another CPU attempts + * to call smp_call_function now... + */ + } + else { + /* Any other callers get treated normally */ + WARN_ON(irqs_disabled()); + } + } +#else WARN_ON(irqs_disabled()); +#endif data.func = func; data.info = info; @@ -172,6 +195,7 @@ if (wait) while (atomic_read(&data.finished) != cpus) barrier(); + call_data = NULL; spin_unlock(&smp_call_lock); return 0; @@ -179,9 +203,17 @@ void smp_call_function_interrupt(void) { - void (*func) (void *info) = call_data->func; - void *info = call_data->info; - int wait = call_data->wait; + void (*func) (void *info); + void *info; + int wait; + + if (call_data == NULL) { + printk ("CPU %d: smp_call_function_interrupt with no call_data\n", smp_processor_id()); + return; + } + func = call_data->func; + info = call_data->info; + wait = call_data->wait; /* * Notify initiating CPU that I've grabbed the data and am From chris@linux-mips.org Thu Jul 28 17:25:31 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:25:31 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:25:31 +0100 X-archive-position: 29 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:25:30 Modified files: linux/arch/mips/kernel: Tag: MaltaRef_2_6 i8259.c Log message: * arch/mips/kernel/i8259.c (init_i8259_irqs): Comment typo. diff -urN malta/linux/arch/mips/kernel/i8259.c malta/linux/arch/mips/kernel/i8259.c --- malta/linux/arch/mips/kernel/i8259.c 2005/06/21 13:24:02 1.16.1000.2 +++ malta/linux/arch/mips/kernel/i8259.c 2005/07/28 17:25:30 1.16.1000.3 @@ -307,7 +307,7 @@ /* * On systems with i8259-style interrupt controllers we assume for - * driver compatibility reasons interrupts 0 - 15 to be the i8295 + * driver compatibility reasons interrupts 0 - 15 to be the i8259 * interrupts even if the hardware uses a different interrupt numbering. */ void __init init_i8259_irqs (void) From chris@linux-mips.org Thu Jul 28 17:25:42 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:25:42 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:25:42 +0100 X-archive-position: 30 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:25:41 Modified files: linux/arch/mips/kernel: Tag: MaltaRef_2_6 head.S Log message: * arch/mips/kernel/head.S: Put a jump to kernel_start near the beginning of the code. This allows to to start execution at the load address (usually). diff -urN malta/linux/arch/mips/kernel/head.S malta/linux/arch/mips/kernel/head.S --- malta/linux/arch/mips/kernel/head.S 2005/06/21 13:24:02 1.59.1000.2 +++ malta/linux/arch/mips/kernel/head.S 2005/07/28 17:25:41 1.59.1000.3 @@ -130,7 +130,13 @@ EXPORT(stext) # used for profiling EXPORT(_stext) - + + /* + * Give us a fighting chance of running if execution beings + * at the kernel load address + */ + j kernel_entry + __INIT NESTED(kernel_entry, 16, sp) # kernel entry point From chris@linux-mips.org Thu Jul 28 17:26:21 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:26:21 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:26:21 +0100 X-archive-position: 31 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:26:20 Modified files: linux/arch/mips: Tag: MaltaRef_2_6 Kconfig Makefile linux/arch/mips/kernel: Tag: MaltaRef_2_6 Makefile genex.S irq_cpu.c traps.c linux/arch/mips/mips-boards/generic: Tag: MaltaRef_2_6 time.c Log message: * arch/mips/mips-boards/generic/time.c (mips_timer_interrupt): SMP timer support. * arch/mips/kernel/traps.c (do_mt): MT exception handler. (mips_srs_alloc): Corrected spinlock usage. (mips_srs_free): Corrected spinlock usage. (per_cpu_trap_init): Disable VPE operation before changing cause register (not strictly necessary because 2nd VPE shouldn't be running...) (trap_init): Install MT exception handler. * arch/mips/kernel/irq_cpu.c: Check cpu_has_mipsmt before using dvpe/evpe. * arch/mips/kernel/genex.S: Added MT exception. * arch/mips/kernel/Makefile: Added smp_mt.c. * arch/mips/Makefile: Added CONFIG_MIPS_MIPSSIM support. * arch/mips/Kconfig: Added MIPS_MIPSSIM and MIPS_MT_SMP. Make SMP dependent on MIPS_MT_SMP. diff -urN malta/linux/arch/mips/Kconfig malta/linux/arch/mips/Kconfig --- malta/linux/arch/mips/Kconfig 2005/07/27 14:17:17 1.73.1000.8 +++ malta/linux/arch/mips/Kconfig 2005/07/28 17:26:18 1.73.1000.9 @@ -289,6 +289,12 @@ This enables support for the MIPS Technologies SEAD evaluation board. +config MIPS_MIPSSIM + bool 'Support for MIPS simulator (MIPSsim)' + select IRQ_CPU + help + This enables support for the MIPS Technologies MIPSsim simulator. + config MOMENCO_JAGUAR_ATX bool "Support for Momentum Jaguar board" select BOOT_ELF32 @@ -1150,6 +1156,14 @@ config MIPS_MT bool "Enable MIPS MT" +choice + prompt "MIPS MT options" + depends on MIPS_MT + +config MIPS_MT_SMP + bool "Use 1 TC on each available VPE for SMP" + select SMP + config MIPS_VPE_LOADER bool "VPE loader support." depends on MIPS_MT @@ -1158,6 +1172,8 @@ Includes a loader for loading an elf relocatable object onto another VPE and running it. +endchoice + config MIPS_VPE_LOADER_TOM bool "Load VPE program into memory hidden from linux" depends on MIPS_VPE_LOADER @@ -1291,7 +1307,7 @@ config SMP bool "Multi-Processing support" - depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27 + depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP ---help--- This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If diff -urN malta/linux/arch/mips/Makefile malta/linux/arch/mips/Makefile --- malta/linux/arch/mips/Makefile 2005/06/21 13:23:40 1.167.1000.5 +++ malta/linux/arch/mips/Makefile 2005/07/28 17:26:18 1.167.1000.6 @@ -423,6 +423,13 @@ load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 # +# MIPS simulator (MIPSsim) +# +core-$(CONFIG_MIPS_MIPSSIM) += arch/mips/mips-boards/sim/ +cflags-$(CONFIG_MIPS_MIPSSIM) += -Iinclude/asm-mips/mach-sim +load-$(CONFIG_MIPS_MIPSSIM) += 0xffffffff80100000 + +# # Momentum Ocelot board # # The Ocelot setup.o must be linked early - it does the ioremap() for the diff -urN malta/linux/arch/mips/kernel/Makefile malta/linux/arch/mips/kernel/Makefile --- malta/linux/arch/mips/kernel/Makefile 2005/07/27 13:37:54 1.80.1000.5 +++ malta/linux/arch/mips/kernel/Makefile 2005/07/28 17:26:19 1.80.1000.6 @@ -34,6 +34,8 @@ obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_MIPS_MT_SMP) += smp_mt.o + obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o diff -urN malta/linux/arch/mips/kernel/genex.S malta/linux/arch/mips/kernel/genex.S --- malta/linux/arch/mips/kernel/genex.S 2005/06/21 13:24:02 1.7.1000.2 +++ malta/linux/arch/mips/kernel/genex.S 2005/07/28 17:26:19 1.7.1000.3 @@ -323,6 +323,7 @@ BUILD_HANDLER mdmx mdmx sti silent /* #22 */ BUILD_HANDLER watch watch sti verbose /* #23 */ BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ + BUILD_HANDLER mt mt sti verbose /* #25 */ BUILD_HANDLER dsp dsp sti silent /* #26 */ BUILD_HANDLER reserved reserved sti verbose /* others */ diff -urN malta/linux/arch/mips/kernel/irq_cpu.c malta/linux/arch/mips/kernel/irq_cpu.c --- malta/linux/arch/mips/kernel/irq_cpu.c 2005/07/22 13:21:43 1.8.1000.3 +++ malta/linux/arch/mips/kernel/irq_cpu.c 2005/07/28 17:26:19 1.8.1000.4 @@ -47,11 +47,12 @@ * to stop other VPEs whenever the local VPE does * anything similar. */ - unsigned int vpflags = dvpe(); + unsigned int vpflags = cpu_has_mipsmt ? dvpe() : 0; #endif /* CONFIG_MIPS_MT */ clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); #ifdef CONFIG_MIPS_MT - evpe(vpflags); + if (cpu_has_mipsmt) + evpe(vpflags); #endif /* CONFIG_MIPS_MT */ set_c0_status(0x100 << (irq - mips_cpu_irq_base)); irq_enable_hazard(); @@ -97,14 +98,15 @@ static void mips_cpu_irq_ack(unsigned int irq) { #ifdef CONFIG_MIPS_MT - unsigned int vpflags = dvpe(); + unsigned int vpflags = cpu_has_mipsmt ? dvpe() : 0; #endif /* CONFIG_MIPS_MT */ /* Only necessary for soft interrupts */ clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); #ifdef CONFIG_MIPS_MT - evpe(vpflags); + if (cpu_has_mipsmt) + evpe(vpflags); #endif /* CONFIG_MIPS_MT */ mask_mips_irq(irq); } diff -urN malta/linux/arch/mips/kernel/traps.c malta/linux/arch/mips/kernel/traps.c --- malta/linux/arch/mips/kernel/traps.c 2005/07/12 16:23:40 1.193.1000.6 +++ malta/linux/arch/mips/kernel/traps.c 2005/07/28 17:26:19 1.193.1000.7 @@ -56,6 +56,7 @@ extern asmlinkage void handle_fpe(void); extern asmlinkage void handle_mdmx(void); extern asmlinkage void handle_watch(void); +extern asmlinkage void handle_mt(void); extern asmlinkage void handle_dsp(void); extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); @@ -801,6 +802,44 @@ (regs->cp0_status & ST0_TS) ? "" : "not "); } +asmlinkage void do_mt(struct pt_regs *regs) +{ + int subcode; + + die_if_kernel("MIPS MT Thread exception in kernel", regs); + + if (cpu_has_mipsmt) { + subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) + >> VPECONTROL_EXCPT_SHIFT; + switch(subcode) { + case 0: + printk("Thread Underflow\n"); + break; + case 1: + printk("Thread Overflow\n"); + break; + case 2: + printk("Invalid YIELD Qualifier\n"); + break; + case 3: + printk("Gating Storage Exception\n"); + break; + case 4: + printk("YIELD Scheduler Exception\n"); + break; + case 5: + printk("Gating Storage Schedulier Exception\n"); + break; + default: + printk("*** UNKNOWN THREAD EXCEPTION %d ***\n", + subcode); + break; + } + } + force_sig(SIGILL, current); +} + + asmlinkage void do_dsp(struct pt_regs *regs) { if (cpu_has_dsp) @@ -996,18 +1035,18 @@ int set; long flags; - spin_lock_irqsave(sr->sr_lock, flags); + spin_lock_irqsave(&sr->sr_lock, flags); for (set = 0; set < sr->sr_supported; set++) { if ((sr->sr_allocated & (1 << set)) == 0) { sr->sr_allocated |= 1 << set; - spin_unlock_irqrestore(sr->sr_lock, flags); + spin_unlock_irqrestore(&sr->sr_lock, flags); return set; } } /* None available */ - spin_unlock_irqrestore(sr->sr_lock, flags); + spin_unlock_irqrestore(&sr->sr_lock, flags); return -1; } @@ -1016,9 +1055,9 @@ struct shadow_registers *sr = &shadow_registers; long flags; - spin_lock_irqsave(sr->sr_lock, flags); + spin_lock_irqsave(&sr->sr_lock, flags); sr->sr_allocated &= ~(1 << set); - spin_unlock_irqrestore(sr->sr_lock, flags); + spin_unlock_irqrestore(&sr->sr_lock, flags); } void *set_vi_srs_handler (int n, void *addr, int srs) @@ -1189,8 +1228,17 @@ /* Setting vector spacing enables EI/VI mode */ change_c0_intctl (0x3e0, VECTORSPACING); } - if (cpu_has_divec) + if (cpu_has_divec) { +#ifdef CONFIG_MIPS_MT + unsigned int vpflags; + vpflags = cpu_has_mipsmt ? dvpe() : 0; +#endif set_c0_cause(CAUSEF_IV); +#ifdef CONFIG_MIPS_MT + if (cpu_has_mipsmt) + evpe(vpflags); +#endif + } cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; TLBMISS_HANDLER_SETUP(); @@ -1331,6 +1379,9 @@ if (cpu_has_mcheck) set_except_vector(24, handle_mcheck); + if (cpu_has_mipsmt) + set_except_vector(25, handle_mt); + if (cpu_has_dsp) set_except_vector(26, handle_dsp); diff -urN malta/linux/arch/mips/mips-boards/generic/time.c malta/linux/arch/mips/mips-boards/generic/time.c --- malta/linux/arch/mips/mips-boards/generic/time.c 2005/06/21 13:24:12 1.23.1000.3 +++ malta/linux/arch/mips/mips-boards/generic/time.c 2005/07/28 17:26:20 1.23.1000.4 @@ -61,6 +61,15 @@ static unsigned int timer_tick_count=0; static int mips_cpu_timer_irq; +static inline void scroll_display_message(void) +{ + if ((timer_tick_count++ % HZ) == 0) { + mips_display_message(&display_string[display_count++]); + if (display_count == MAX_DISPLAY_COUNT) + display_count = 0; + } +} + static void mips_timer_dispatch (struct pt_regs *regs) { do_IRQ (mips_cpu_timer_irq, regs); @@ -68,17 +77,42 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { +#ifdef CONFIG_SMP + int cpu = smp_processor_id(); + + if (cpu == 0) { + /* + * CPU 0 handles the global timer interrupt job and process accounting + * resets count/compare registers to trigger next timer int. + */ + (void) timer_interrupt(irq, dev_id, regs); + scroll_display_message(); + } + else { + /* Everyone else needs to reset the timer int here as + ll_local_timer_interrupt doesn't */ + /* + * FIXME: need to cope with counter underflow. + * More support needs to be added to kernel/time for + * counter/timer interrupts on multiple CPU's + */ + write_c0_compare (read_c0_count() + (mips_hpt_frequency/HZ)); + /* + * other CPUs should do profiling and process accounting + */ + local_timer_interrupt (irq, dev_id, regs); + } + + return IRQ_HANDLED; +#else irqreturn_t r; r = timer_interrupt(irq, dev_id, regs); - if ((timer_tick_count++ % HZ) == 0) { - mips_display_message(&display_string[display_count++]); - if (display_count == MAX_DISPLAY_COUNT) - display_count = 0; - } + scroll_display_message(); return r; +#endif } /* @@ -89,7 +123,7 @@ unsigned int prid = read_c0_prid() & 0xffff00; unsigned int count; -#ifdef CONFIG_MIPS_SEAD +#if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_MIPSSIM) /* * The SEAD board doesn't have a real time clock, so we can't * really calculate the timer frequency @@ -176,6 +210,13 @@ irq->handler = mips_timer_interrupt; /* we use our own handler */ setup_irq(mips_cpu_timer_irq, irq); +#ifdef CONFIG_SMP + /* irq_desc(riptor) is a global resource, when the interrupt overlaps + on seperate cpu's the first one tries to handle the second interrupt. + The effect is that the int remains disabled on the second cpu. + Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ + irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; +#endif /* to generate the first timer interrupt */ write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); From chris@linux-mips.org Thu Jul 28 17:50:41 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Thu, 28 Jul 2005 18:50:41 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Thu, 28 Jul 2005 18:50:41 +0100 X-archive-position: 32 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/28 18:50:41 Added files: linux/arch/mips/kernel: Tag: MaltaRef_2_6 smp_mt.c Log message: MT SMP support diff -urN malta/linux/arch/mips/kernel/smp_mt.c malta/linux/arch/mips/kernel/smp_mt.c --- malta/linux/arch/mips/kernel/Attic/smp_mt.c 1970/01/01 00:00:00 +++ malta/linux/arch/mips/kernel/Attic/smp_mt.c 2005-07-28 18:50:41.057883000 +0100 1.1.1000.1 @@ -0,0 +1,374 @@ +/* + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * + * Elizabeth Clarke (beth@mips.com) + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int cpu_ipi_resched_irq, cpu_ipi_call_irq; +#define MIPS_CPU_IPI_RESCHED_IRQ 0 +#define MIPS_CPU_IPI_CALL_IRQ 1 + +static struct irqaction irq_call, irq_resched; + +static void ipi_resched_dispatch (struct pt_regs *regs); +static void ipi_call_dispatch (struct pt_regs *regs); +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs); +static irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs); + +static void dump_mtregisters(int vpe, int tc) +{ + printk("vpe %d tc %d\n", vpe, tc); + + settc(tc); + + printk(" c0 status 0x%lx\n", read_vpe_c0_status()); + printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol()); + printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0()); + printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus()); + printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart()); + printk(" tcbind 0x%lx\n", read_tc_c0_tcbind()); + printk(" tchalt 0x%lx\n", read_tc_c0_tchalt()); +} + +void __init sanitize_tlb_entries(void) +{ + int i, tlbsiz; + unsigned long mvpconf0, ncpu; + + if (!cpu_has_mipsmt) + return; + + write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC ); + + /* Disable TLB sharing */ + write_c0_mvpcontrol( read_c0_mvpcontrol() & ~MVPCONTROL_STLB ); + + mvpconf0 = read_c0_mvpconf0(); + + printk("MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0, + (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT, + (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT); + + tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT; + ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; + + printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu); + + if (tlbsiz > 0) { + /* share them out across the vpe's */ + tlbsiz /= ncpu; + + printk("setting Config1.MMU_size to %d\n", tlbsiz); + + for (i = 0; i < ncpu; i++) { + settc(i); + + if( i == 0 ) + write_c0_config1( (read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25) ); + else + write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) | + (tlbsiz << 25) ); + } + } + + write_c0_mvpcontrol( read_c0_mvpcontrol() & ~MVPCONTROL_VPC ); +} + +#if 0 +/* + * Use c0_MVPConf0 to find out how many CPUs are available, setting up + * phys_cpu_present_map and the logical/physical mappings. + */ +void __init prom_build_cpu_map(void) +{ + int i, num, ncpus; + + cpus_clear(phys_cpu_present_map); + + /* assume we boot on cpu 0.... */ + cpu_set(0, phys_cpu_present_map); + __cpu_number_map[0] = 0; + __cpu_logical_map[0] = 0; + + if (cpu_has_mipsmt) { + ncpus = ((read_c0_mvpconf0() & (MVPCONF0_PVPE)) >> MVPCONF0_PVPE_SHIFT) + 1; + for (i=1, num=0; i< NR_CPUS && i> MVPCONF0_PTC_SHIFT); i++) { + settc(i); + + /* VPE's */ + if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) { + + /* deactivate all but vpe0 */ + if (i != 0) { + unsigned long tmp = read_vpe_c0_vpeconf0(); + + tmp &= ~VPECONF0_VPA; + + /* master VPE */ + tmp |= VPECONF0_MVP; + write_vpe_c0_vpeconf0(tmp); + + /* Record this as available CPU */ + if (i < max_cpus) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = ++num; + __cpu_logical_map[num] = i; + } + } + + /* disable multi-threading with TC's */ + write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); + + if (i != 0) { + write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0); + write_vpe_c0_cause(read_vpe_c0_cause() & ~CAUSEF_IP); + + /* set config to be the same as vpe0, particularly kseg0 coherency alg */ + write_vpe_c0_config( read_c0_config()); + } + + } + + /* TC's */ + + if (i != 0) { + unsigned long tmp; + + /* bind a TC to each VPE, May as well put all excess TC's + on the last VPE */ + if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) ) + write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) ); + else { + write_tc_c0_tcbind( read_tc_c0_tcbind() | i); + + /* and set XTC */ + write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT)); + } + + tmp = read_tc_c0_tcstatus(); + + /* mark not allocated and not dynamically allocatable */ + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ + write_tc_c0_tcstatus(tmp); + + write_tc_c0_tchalt(TCHALT_H); + } + } + + /* release config state */ + write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); + + /* we'll wait until starting the secondary cpu(s) before starting MVPE */ + + printk("Detected %i available secondary CPU(s)\n", num); + + /* set up ipi interrupts */ + memset( &irq_call, 0, sizeof(struct irqaction)); + memset( &irq_resched, 0, sizeof(struct irqaction)); + + if (cpu_has_vint) { + set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); + set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); + } + + cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ; + cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ; + + irq_resched.handler = ipi_resched_interrupt; + irq_resched.flags = SA_INTERRUPT; + irq_resched.name = "IPI_resched"; + + irq_call.handler = ipi_call_interrupt; + irq_call.flags = SA_INTERRUPT; + irq_call.name = "IPI_call"; + + setup_irq(cpu_ipi_resched_irq, &irq_resched); + setup_irq(cpu_ipi_call_irq, &irq_call); + + /* need to mark IPI's as IRQ_PER_CPU */ + irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; + irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; +} + + +/* + * Setup the PC, SP, and GP of a secondary processor and start it + * running! + * smp_bootstrap is the place to resume from + * __KSTK_TOS(idle) is apparently the stack pointer + * (unsigned long)idle->thread_info the gp + * assumes a 1:1 mapping of TC => VPE + * + */ +void prom_boot_secondary(int cpu, struct task_struct *idle) +{ + + dvpe(); + write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC ); + + settc(cpu); + + /* restart */ + write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); + + /* enable the tc this vpe/cpu will be running */ + write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A); + + write_tc_c0_tchalt(0); + + /* enable the VPE */ + write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | VPECONF0_VPA); + + /* stack pointer */ + write_tc_gpr_sp( __KSTK_TOS(idle) ); + + /* global pointer */ + write_tc_gpr_gp( (unsigned long)idle->thread_info ); + + flush_icache_range((unsigned long)idle->thread_info, + (unsigned long)idle->thread_info + + sizeof(struct thread_info)); + + /* finally out of configuration and into chaos */ + write_c0_mvpcontrol( read_c0_mvpcontrol() & ~MVPCONTROL_VPC ); + + evpe(EVPE_ENABLE); +} + +void prom_init_secondary(void) +{ + write_c0_status((read_c0_status() & ~ST0_IM ) + | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7)); +} + +void prom_smp_finish(void) +{ + write_c0_compare (read_c0_count() + (8* mips_hpt_frequency/HZ)); + + local_irq_enable(); +} + +void prom_cpus_done(void) +{} + +void core_send_ipi(int cpu, unsigned int action) +{ + int i; + unsigned long flags; + int vpflags; + + local_irq_save (flags); + + vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ + + switch( action ) { + + case SMP_CALL_FUNCTION: + i = C_SW1; + break; + + default: + case SMP_RESCHEDULE_YOURSELF: + i = C_SW0; + break; + } + + /* 1:1 mapping of vpe and tc... */ + settc(cpu); + write_vpe_c0_cause(read_vpe_c0_cause() | i); + evpe(vpflags); + + local_irq_restore (flags); +} + +static void ipi_resched_dispatch (struct pt_regs *regs) +{ + do_IRQ (MIPS_CPU_IPI_RESCHED_IRQ, regs); +} + +static void ipi_call_dispatch (struct pt_regs *regs) +{ + do_IRQ (MIPS_CPU_IPI_CALL_IRQ, regs); +} + +irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + irqreturn_t r = IRQ_HANDLED; + return r; +} + +irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + irqreturn_t r = IRQ_HANDLED; + smp_call_function_interrupt(); + return r; +} From chris@linux-mips.org Fri Jul 29 18:55:01 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Fri, 29 Jul 2005 19:55:01 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Fri, 29 Jul 2005 19:55:01 +0100 X-archive-position: 33 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/29 19:54:59 Modified files: linux/arch/mips: Tag: MaltaRef_2_6 Makefile Log message: Backed out MIPSSIM support until it appears in HEAD. diff -urN malta/linux/arch/mips/Makefile malta/linux/arch/mips/Makefile --- malta/linux/arch/mips/Makefile 2005/07/28 17:26:18 1.167.1000.6 +++ malta/linux/arch/mips/Makefile 2005/07/29 18:54:57 1.167.1000.7 @@ -423,13 +423,6 @@ load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 # -# MIPS simulator (MIPSsim) -# -core-$(CONFIG_MIPS_MIPSSIM) += arch/mips/mips-boards/sim/ -cflags-$(CONFIG_MIPS_MIPSSIM) += -Iinclude/asm-mips/mach-sim -load-$(CONFIG_MIPS_MIPSSIM) += 0xffffffff80100000 - -# # Momentum Ocelot board # # The Ocelot setup.o must be linked early - it does the ioremap() for the From chris@linux-mips.org Fri Jul 29 19:09:48 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Fri, 29 Jul 2005 20:09:48 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Fri, 29 Jul 2005 20:09:48 +0100 X-archive-position: 34 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/29 20:09:47 Modified files: linux/arch/mips/configs: Tag: MaltaRef_2_6 malta_defconfig Log message: Regenerated diff -urN malta/linux/arch/mips/configs/malta_defconfig malta/linux/arch/mips/configs/malta_defconfig --- malta/linux/arch/mips/configs/malta_defconfig 2005/07/04 13:15:31 1.7.1000.7 +++ malta/linux/arch/mips/configs/malta_defconfig 2005/07/29 19:09:47 1.7.1000.8 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc6 -# Fri Jul 1 17:51:40 2005 +# Fri Jul 29 20:10:47 2005 # CONFIG_MIPS=y @@ -75,6 +75,7 @@ # CONFIG_MIPS_ATLAS is not set CONFIG_MIPS_MALTA=y # CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_MIPSSIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_MOMENCO_OCELOT_3 is not set From chris@linux-mips.org Fri Jul 29 19:27:00 2005 Received: with ECARTIS (v1.0.0; list maltalinux-cvs-patches); Fri, 29 Jul 2005 20:27:00 +0100 (BST) From: chris@linux-mips.org To: maltalinux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: malta Date: Fri, 29 Jul 2005 20:27:00 +0100 X-archive-position: 35 X-ecartis-version: Ecartis v1.0.0 Sender: maltalinux-cvs-patches-bounce@linux-mips.org Errors-to: maltalinux-cvs-patches-bounce@linux-mips.org X-original-sender: chris@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: maltalinux-cvs-patches CVSROOT: /home/cvs Module name: malta Changes by: chris@ftp.linux-mips.org 05/07/29 20:26:59 Modified files: linux/include/asm-mips: Tag: MaltaRef_2_6 mipsregs.h Log message: * include/asm-mips/mipsregs.h: Don't make the include of mipsmtregs.h dependent on CONFIG_MIPS_MT for now. The do_mt handler in traps.c may be be built regardless of CONFIG_MIPS_MT. diff -urN malta/linux/include/asm-mips/mipsregs.h malta/linux/include/asm-mips/mipsregs.h --- malta/linux/include/asm-mips/mipsregs.h 2005/07/25 18:07:59 1.62.1000.5 +++ malta/linux/include/asm-mips/mipsregs.h 2005/07/29 19:26:59 1.62.1000.6 @@ -37,9 +37,7 @@ #define _ULCAST_ (unsigned long) #endif -#ifdef CONFIG_MIPS_MT #include -#endif /* * Coprocessor 0 register names