From kumba@gentoo.org Tue Jan 1 04:25:26 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jan 2013 04:25:28 +0100 (CET) Received: from qmta03.westchester.pa.mail.comcast.net ([76.96.62.32]:38609 "EHLO qmta03.westchester.pa.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816743Ab3AADZ0Unopd (ORCPT ); Tue, 1 Jan 2013 04:25:26 +0100 Received: from omta02.westchester.pa.mail.comcast.net ([76.96.62.19]) by qmta03.westchester.pa.mail.comcast.net with comcast id iTGB1k00D0QuhwU53TRKZo; Tue, 01 Jan 2013 03:25:19 +0000 Received: from [192.168.1.13] ([76.106.69.86]) by omta02.westchester.pa.mail.comcast.net with comcast id iTRG1k00r1rgsis3NTRJKT; Tue, 01 Jan 2013 03:25:19 +0000 Message-ID: <50E2571C.50607@gentoo.org> Date: Mon, 31 Dec 2012 22:25:16 -0500 From: Joshua Kinard User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Ralf Baechle CC: Linux MIPS List Subject: Re: Unhandled kernel unaligned access on IP32 w/ network I/O && 3.7.1? References: <50DD1FB9.6060707@gentoo.org> <20121228215225.GC6786@linux-mips.org> <50DFFA07.1040302@gentoo.org> In-Reply-To: <50DFFA07.1040302@gentoo.org> X-Enigmail-Version: 1.4.6 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig2A9F43BBD9D9FBA432D91D15" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=comcast.net; s=q20121106; t=1357010719; bh=k4S/Pow3uP9HLeFVuoPzVOK8Hcz6u+6XAgteWtwxubQ=; h=Received:Received:Message-ID:Date:From:MIME-Version:To:Subject: Content-Type; b=SLsAQh9/kSYRa9nLQhf5LkSFoTPY//JiM/cBTS98Sd2Xr8BrI8ineX91hahN//FaV 7MJpxf0zky9BdEWnOabL+mb99VmCD36xcyYTJMN/giLhSfbogT5UG81SNkdymKetyR DDDGm3qvoeH0Zw3dyKeV5EcWhcuh7rlzp6F5xJBIoZuDOKkGfxUE/ja648PWiw5vq1 eGcwx0wRZp0lNatcxq7/qbFQuF/TgJjE939cz56YN7DdBPBz2JnIA4LnYyvOv2o7N3 TG1BEf7y3Fqpq6fYycbzRjH7SOZX2WPtK37m+Bwt2FxSW2NJBMmsl8gPcD7K1xGd/D WDaKGT1PPc0qA== X-archive-position: 35351 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6147 Lines: 167 This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig2A9F43BBD9D9FBA432D91D15 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On 12/30/2012 3:23 AM, Joshua Kinard wrote: >=20 > Here's an untainted oops from IP32. Triggered by logging in over SSH o= n > IPv6 and running 'dmesg': >=20 > Unhandled kernel unaligned access[#1]: > Cpu 0 > $ 0 : 0000000000000000 0000000000000010 0000000000000000 bfffff005e17= aac4 > $ 4 : 0000000000000000 0000000000000000 0000000000000000 000000000000= 0000 > $ 8 : 980000005e00e000 0000000000000000 980000005e00e000 000000000000= 0410 > $12 : ffffffff9001fce1 000000001000001e fffffffffffff000 000000000000= 001f > $16 : 980000005e03fa40 ffffffffde0300b8 ffffff0000000000 000000000000= 0034 > $20 : 00000000006532d8 0000000000000594 00000000004a1134 00000000004a= 0000 > $24 : 0000000000000001 00000000000003f0 > $28 : 980000005e03c000 980000005e03fa10 0000000000000000 ffffffff8000= 59a0 > Hi : 000000000011a02a > Lo : 000000000005e00e > epc : ffffffff8000b700 do_ade+0x1b0/0x480 > Not tainted > ra : ffffffff800059a0 ret_from_exception+0x0/0x24 > Status: 9001fce3 KX SX UX KERNEL EXL IE > Cause : 00000010 > BadVA : bfffff005e17aac4 > PrId : 00002733 (RM7000) > Process sshd (pid: 1323, threadinfo=3D980000005e03c000, task=3D98000000= 5fe76000, > tls=3D0000000077010490) > Stack : 980000005e00e6a0 980000005e17aa0c 980000005faef000 000000000000= 0594 > 0000000000000034 ffffffff800059a0 0000000000000000 000000000000= 0010 > 00000000000000d0 0000000000000000 980000005faef000 000000000000= 08a0 > 0000000000000000 0000000000000000 980000005e00e000 000000000000= 0000 > 980000005e00e000 0000000000000410 0000000000000020 ffffffff8022= 3b6c > fffffffffffff000 000000000000001f 980000005e17aa0c 980000005fae= f000 > 0000000000000594 0000000000000034 00000000006532d8 000000000000= 0594 > 00000000004a1134 00000000004a0000 0000000000000001 000000000000= 03f0 > 0000000000000014 ffffffff802de0d0 980000005e03c000 980000005e03= fb70 > 0000000000000000 ffffffff80334ef8 ffffffff9001fce3 000000000011= a02a > ... > Call Trace: > [] do_ade+0x1b0/0x480 > [] ret_from_exception+0x0/0x24 > [] sk_stream_alloc_skb+0x6c/0x118 > [] tcp_sendmsg+0x6fc/0xe90 > [] sock_aio_write+0x10c/0x150 > [] do_sync_write+0x9c/0x108 > [] vfs_write+0x168/0x180 > [] SyS_write+0x54/0xb8 > [] handle_sys+0x118/0x13c >=20 >=20 > Code: 00441024 5440ffe6 de030100 <68730000> 6c730007 24030000 14600= 040 > 00000000 8e020124 > ---[ end trace 8127ff095caa30f9 ]--- >=20 >=20 > Turns out it is non-fatal. The serial console is still alive, but sshd= was > terminated as a result (it's in the 'Ds' state under ps ux output). Some quick digging via objdump and a new oops, from a rebuilt kernel including full debugging, points at an inlined call to skb_reserve from within sk_stream_alloc_skb in net/ipv4/tcp.c. Bottom of new oops: Call Trace: [] do_ade+0x1b0/0x480 [] ret_from_exception+0x0/0x24 [] sk_stream_alloc_skb+0x6c/0x118 [] tcp_sendmsg+0x6fc/0xe98 [] sock_aio_write+0x10c/0x150 [] do_sync_write+0x9c/0x108 [] vfs_write+0x168/0x180 [] SyS_write+0x54/0xb8 [] handle_sys+0x118/0x13c Disassembly of vmlinux, and match of address ffffffff803352dc yields this= : if (sk_wmem_schedule(sk, skb->truesize)) { skb_reserve(skb, sk->sk_prot->max_header); ffffffff803352d8: 8c420108 lw v0,264(v0) * Increase the headroom of an empty &sk_buff by reducing the tail * room. This is only allowed for an empty buffer. */ static inline void skb_reserve(struct sk_buff *skb, int len) { skb->data +=3D len; ffffffff803352dc: de0300b8 ld v1,184(s0) skb->tail +=3D len; ffffffff803352e0: 8e0400a8 lw a0,168(s0) * Increase the headroom of an empty &sk_buff by reducing the tail * room. This is only allowed for an empty buffer. */ I looked around at several files in git, mainly, net/ipv4/tcp.c, and none= of the recent changes to 3.7 sticks out immediately as the cause. I'll eith= er have to use git bisect or run kgdb on it to figure anything else out. Does this look like a case of scheduling while atomic? There's a fix in davem's -next tree that addresses such a cause, but I haven't tried that just yet to see if it's the same issue. --=20 Joshua Kinard Gentoo/MIPS kumba@gentoo.org 4096R/D25D95E3 2011-03-28 "The past tempts us, the present confuses us, the future frightens us. A= nd our lives slip away, moment by moment, lost in that vast, terrible in-bet= ween." --Emperor Turhan, Centauri Republic --------------enig2A9F43BBD9D9FBA432D91D15 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.17 (MingW32) iQIcBAEBAgAGBQJQ4lciAAoJENsjoH7SXZXj6KcQAJtGZ6kSCfKDbC/uDaq+L8UL NQX8PAIKSjLLFDhfVxa2AIZirtqvvUq7DxO2R6YCcIOSXqySe+m6n1a0crK1TfSM cAdTKEkOum8zIganEHKCwM60E4H0ODH6WNrRBr0x0esL/0ryb0tx6hnOSVgf8Z7m di3Bbl2XMNWzk0tXn8hN8YWqSp5/bhCeqjzspvFtxKEVhta5fKwYlA0zaHU8Y2pE KJ2BujmJ6x6pZ3KyQGP1S27tjCdyA4krQiDS/wZ/49D/ReqbrrNUqBVlCyehvdzE CZtMwnpNfhBa0jonDTgd2+nSzk4U1Eln6YruayB29qPnuFS42rpfagKzoc/LRoe/ CKqrRDAF0axIStMJwrLwRX1MwjTUP4NkMR1wSx0f5lfGZxFSHhmhkK3+JtJ3gir/ ulHMLYaGjio64LD+i+YIaLNLNkoxQDkmnU1Noumy2bGHqD32uoisAw7qdBJd2jlY VSGEZUVsWUQCsiTM9YA+mafJ6zMIRyjgtoaF70k9EIYSGTLu6VIri/jWEkQ6dRYx s/dQzh7hXyW7DmINZrPrqWbBkpRxG6UbNk+avCcytxAyi5bb+6a6JJQ20gO5CFLb iMzE4ZBJOsE/yLBUxLGSY/vqv01zdDh29Ya6DfP95P3z/rdJTMlPbrgZA2TfiI3U 02z56RXXj4W5hbsTZV6J =zAGi -----END PGP SIGNATURE----- --------------enig2A9F43BBD9D9FBA432D91D15-- From shmulik.ladkani@gmail.com Tue Jan 1 10:23:54 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jan 2013 10:23:56 +0100 (CET) Received: from mail-wg0-f49.google.com ([74.125.82.49]:63250 "EHLO mail-wg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815858Ab3AAJXyY5mP5 (ORCPT ); Tue, 1 Jan 2013 10:23:54 +0100 Received: by mail-wg0-f49.google.com with SMTP id 15so5898130wgd.28 for ; Tue, 01 Jan 2013 01:23:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:date:from:to:cc:subject:message-id:mime-version :content-type:content-transfer-encoding; bh=KResWqwBYFV8OI+rN34d2Zyu16NSfjuhNhpYdMfilOc=; b=Z5VorQUmyend4B2yYshIFaJrtuVikHkVyi/7PTE+v1jxPdpz547uIQx/tr1AUAYFZQ Bm0+uoYlB1cX9l5HKWzIroRrs20Bq6sCigF48wUY27kAZC7CvINUHIAt5MYYjGSaOnTd 0OhB8C04hUDr8tPYpiWIhyCFV0YnKalGMpbB53cO61WPrYaUbeNuUs7odJ59d8DziF6m YxLu/Yt52e/Nzypp06RPEZDLpnTWORKLcxMSTAwG4wM3esa47k+Gi9pAEzNZpqPhgmAd X5HfGe76vf1Hsn8ZGW6B3Jum2s+Al6+t2mIyERnyBG9cWhtQ2XPHexWjikoEjx5ySoap +EQg== X-Received: by 10.194.235.6 with SMTP id ui6mr68052077wjc.12.1357032228807; Tue, 01 Jan 2013 01:23:48 -0800 (PST) Received: from pixies.home.jungo.com (212-150-239-254.bb.netvision.net.il. [212.150.239.254]) by mx.google.com with ESMTPS id bd6sm48237324wib.10.2013.01.01.01.23.46 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 01 Jan 2013 01:23:47 -0800 (PST) Date: Tue, 1 Jan 2013 11:23:40 +0200 From: Shmulik Ladkani To: Ralf Baechle Cc: linux-mips@linux-mips.org, Kevin Cernekee , Shmulik Ladkani Subject: Regarding commit a16dad7 [MIPS: Fix potencial corruption] Message-ID: <20130101112340.0a0e8c08@pixies.home.jungo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 35352 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shmulik.ladkani@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1300 Lines: 41 Hi, Commit a16dad77 (MIPS: Fix potencial corruption) seems as a revert of a8ca8b64 (MIPS: Avoid destructive invalidation on partial cachelines). Snip of a16dad77: @@ -643,9 +640,6 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) * hit ops with insufficient alignment. Solved by * aligning the address to cache line size. */ - cache_op(Hit_Writeback_Inv_SD, addr & almask); - cache_op(Hit_Writeback_Inv_SD, - (addr + size - 1) & almask); However, (1) The comment above the removed 'cache_op' instructions, which was originally added as part of a8ca8b64, was not reverted, and now looks out-of-context. Any reason to keep the comment? If not, I'll submit a patch removing it. (2) Following a8ca8b64, another commit was submitted, adding similar 'cache_op' instructions to 'mips_sc_inv' - namely 96983ffe (MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines). Its purpose was to extend a8ca8b64, aligning behavior of 'mips_sc_inv' to be similar to 'r4k_dma_cache_inv'. Since the explicit 'cache_op' instrcutions are now removed from 'r4k_dma_cache_inv' (as of a16dad77), it probably makes sense to remove them from 'mips_sc_inv' as well. Any reason to keep these 'cache_op's? If not, I'll submit a patch. Regards, Shmulik From cernekee@gmail.com Tue Jan 1 10:47:59 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jan 2013 10:48:00 +0100 (CET) Received: from mail-da0-f51.google.com ([209.85.210.51]:34409 "EHLO mail-da0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815858Ab3AAJr7SrKp- (ORCPT ); Tue, 1 Jan 2013 10:47:59 +0100 Received: by mail-da0-f51.google.com with SMTP id i30so6039100dad.24 for ; Tue, 01 Jan 2013 01:47:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=9I4L2Bb0VjBiaa8azq5VOB3nhCN8YUzRQFrR3iw0ksk=; b=IUVzkpmvY4dHx/L/1y5vCMEw7vN0mKVRs58/MhYJSsGhEkJGR4ez8Wr47QB7oFvnoN GNLmVgwZwrrOufq/2Jx30U8nrG2T9YZQ+j9f5lm5b7rb8VoKuo0xoR1sSes6scjjtFxb KGylyUqWFdHJ+gJ4eH+FPJvfXIoJoVB3R3nVDt1JDsQTV2VXHujLm7FqfecvOshGHIpv 2zObU1G2iO6cv1AsSNWqNKwTks1KjNgUb9jBTCwBxeLTGkttW0B09kXk7r+GpRtAFUiF 6g1LPhQAKgjWwhpURH8XwZ+GqAFHCqCg9XZo4/aIHEIJNnt3SHBCFy/XR85n1ZxkoEWp HspQ== MIME-Version: 1.0 Received: by 10.68.194.6 with SMTP id hs6mr134421114pbc.77.1357033672369; Tue, 01 Jan 2013 01:47:52 -0800 (PST) Received: by 10.68.135.41 with HTTP; Tue, 1 Jan 2013 01:47:52 -0800 (PST) In-Reply-To: <20130101112340.0a0e8c08@pixies.home.jungo.com> References: <20130101112340.0a0e8c08@pixies.home.jungo.com> Date: Tue, 1 Jan 2013 01:47:52 -0800 Message-ID: Subject: Re: Regarding commit a16dad7 [MIPS: Fix potencial corruption] From: Kevin Cernekee To: Shmulik Ladkani Cc: Ralf Baechle , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 35353 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1052 Lines: 23 On Tue, Jan 1, 2013 at 1:23 AM, Shmulik Ladkani wrote: > Following a8ca8b64, another commit was submitted, adding similar > 'cache_op' instructions to 'mips_sc_inv' - namely 96983ffe > (MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines). > > Its purpose was to extend a8ca8b64, aligning behavior of 'mips_sc_inv' > to be similar to 'r4k_dma_cache_inv'. > > Since the explicit 'cache_op' instrcutions are now removed from > 'r4k_dma_cache_inv' (as of a16dad77), it probably makes sense to remove > them from 'mips_sc_inv' as well. > > Any reason to keep these 'cache_op's? If not, I'll submit a patch. There were a couple of USB drivers that stored DMA buffers inside a struct with other data, and invalidating the whole cacheline tended to clobber the other data. For instance, intr_buff in drivers/net/usb/pegasus.h . Does CONFIG_DMA_API_DEBUG complain if it sees unaligned start addresses or sizes? That would be a much nicer way of catching the problem, than troubleshooting random corruption. From shmulik.ladkani@gmail.com Tue Jan 1 12:29:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jan 2013 12:29:15 +0100 (CET) Received: from mail-wg0-f48.google.com ([74.125.82.48]:48252 "EHLO mail-wg0-f48.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815858Ab3AAL3OYW0qJ (ORCPT ); Tue, 1 Jan 2013 12:29:14 +0100 Received: by mail-wg0-f48.google.com with SMTP id dt10so5965815wgb.15 for ; Tue, 01 Jan 2013 03:29:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=ltC5HGHh5ze4QK6BcCyO+5cXUbETgTd3JXZJopn1HEY=; b=MKc35v3GnQw+7vn1IPmMaoeuzsc+TJj/AGsJTYVbZ5nmfUNp5Vapwcl6/sB56yS8gw lJRE9Bdiq6F9IKNKKeSLmH4ra+heaDtdWaGBAfMYfSATOeiXHNoIcTsWxvo0jJnf8sfh XbcgtWx1MHeNB3/N5kuDB1LKwzbMD2EWQ9bk1SH+w68sbpggepWyN9MZFu1DAq7gnbp4 DAJoHWbfSUo+9fHwujfkx+BRZfc8bP0xZduIWLr1BVmZ8Y9eg3vBEeS+gBgk0wfkiyKb 9iyq89rnYLFOtc9zOxLLJv2IT8QjJAa4AB25LnuYGXkuff5HRi40lWefnK8bln9V+K8f 347A== X-Received: by 10.180.24.70 with SMTP id s6mr66705840wif.22.1357039749062; Tue, 01 Jan 2013 03:29:09 -0800 (PST) Received: from pixies.home.jungo.com (212-150-239-254.bb.netvision.net.il. [212.150.239.254]) by mx.google.com with ESMTPS id t17sm74595913wiv.6.2013.01.01.03.29.07 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 01 Jan 2013 03:29:08 -0800 (PST) Date: Tue, 1 Jan 2013 13:29:05 +0200 From: Shmulik Ladkani To: Kevin Cernekee Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: Regarding commit a16dad7 [MIPS: Fix potencial corruption] Message-ID: <20130101132905.0c733b69@pixies.home.jungo.com> In-Reply-To: References: <20130101112340.0a0e8c08@pixies.home.jungo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 35354 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shmulik.ladkani@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1561 Lines: 41 Hi Kevin, On Tue, 1 Jan 2013 01:47:52 -0800 Kevin Cernekee wrote: > On Tue, Jan 1, 2013 at 1:23 AM, Shmulik Ladkani > wrote: > > Following a8ca8b64, another commit was submitted, adding similar > > 'cache_op' instructions to 'mips_sc_inv' - namely 96983ffe > > (MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines). > > > > Its purpose was to extend a8ca8b64, aligning behavior of 'mips_sc_inv' > > to be similar to 'r4k_dma_cache_inv'. > > > > Since the explicit 'cache_op' instrcutions are now removed from > > 'r4k_dma_cache_inv' (as of a16dad77), it probably makes sense to remove > > them from 'mips_sc_inv' as well. > > > > Any reason to keep these 'cache_op's? If not, I'll submit a patch. > > There were a couple of USB drivers that stored DMA buffers inside a > struct with other data, and invalidating the whole cacheline tended to > clobber the other data. For instance, intr_buff in > drivers/net/usb/pegasus.h . I see. > Does CONFIG_DMA_API_DEBUG complain if it sees unaligned start > addresses or sizes? That would be a much nicer way of catching the > problem, than troubleshooting random corruption. Have no idea ;) Hoping for Ralf to examine this. I accidentally happened to notice an anomaly in the code: a revert was executed (by Ralf Baechle in a16dad77), but it was incomplete: (1) the comment was left, (2) revert wasn't executed on 'mips_sc_inv'. Just pointing out the anomalies, for Ralf to acknowledge whether they were deliberate or not. Regards, Shmulik From Julia.Lawall@lip6.fr Thu Jan 3 10:34:30 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jan 2013 10:34:32 +0100 (CET) Received: from mail1-relais-roc.national.inria.fr ([192.134.164.82]:2829 "EHLO mail1-relais-roc.national.inria.fr" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab3ACJeauDha1 (ORCPT ); Thu, 3 Jan 2013 10:34:30 +0100 X-IronPort-AV: E=Sophos;i="4.84,402,1355094000"; d="scan'208";a="188308018" Received: from palace.lip6.fr (HELO localhost.localdomain) ([132.227.105.202]) by mail1-relais-roc.national.inria.fr with ESMTP/TLS/DHE-RSA-AES256-SHA; 03 Jan 2013 10:34:25 +0100 From: Julia Lawall To: Ralf Baechle Cc: kernel-janitors@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] arch/mips/kernel/cpufreq/loongson2_cpufreq.c: use clk API instead of direct dereferences Date: Thu, 3 Jan 2013 11:34:20 +0100 Message-Id: <1357209260-15412-2-git-send-email-Julia.Lawall@lip6.fr> X-Mailer: git-send-email 1.7.8.6 X-archive-position: 35355 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Julia.Lawall@lip6.fr Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1800 Lines: 70 From: Julia Lawall A struct clk value is intended to be an abstract pointer, so it should be manipulated using the various API functions. clk_put is additionally added on the failure paths. The semantic match that finds the first problem is as follows: (http://coccinelle.lip6.fr/) // @@ expression e,e1; identifier i; @@ *e = clk_get(...) ... when != e = e1 when any *e->i // Signed-off-by: Julia Lawall --- I am not able to compile this code. arch/mips/kernel/cpufreq/loongson2_cpufreq.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c index e7c98e2..51f5b68 100644 --- a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c +++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c @@ -107,6 +107,8 @@ static int loongson2_cpufreq_target(struct cpufreq_policy *policy, static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy) { int i; + unsigned long rate; + int ret; if (!cpu_online(policy->cpu)) return -ENODEV; @@ -117,15 +119,22 @@ static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy) return PTR_ERR(cpuclk); } - cpuclk->rate = cpu_clock_freq / 1000; - if (!cpuclk->rate) + rate = cpu_clock_freq / 1000; + if (!rate) { + clk_put(cpuclk); return -EINVAL; + } + ret = clk_set_rate(cpuclk, rate); + if (ret) { + clk_put(cpuclk); + return ret; + } /* clock table init */ for (i = 2; (loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) - loongson2_clockmod_table[i].frequency = (cpuclk->rate * i) / 8; + loongson2_clockmod_table[i].frequency = (rate * i) / 8; policy->cur = loongson2_cpufreq_get(policy->cpu); From sjhill@mips.com Thu Jan 3 21:02:09 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jan 2013 21:02:11 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:43179 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822150Ab3ACUCJTvvS7 (ORCPT ); Thu, 3 Jan 2013 21:02:09 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TqqzI-0005U0-EA; Thu, 03 Jan 2013 14:02:00 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, florian@openwrt.org Subject: [PATCH v3] MIPS: dsp: Add assembler support for DSP ASEs. Date: Thu, 3 Jan 2013 14:01:52 -0600 Message-Id: <1357243312-23070-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35356 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3880 Lines: 139 From: "Steven J. Hill" Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mipsregs.h | 53 ++++++++++++++++++++++++++------------ arch/mips/kernel/Makefile | 31 ++++++++++++++++++++++ 2 files changed, 67 insertions(+), 17 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 3e36745..5781322 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1155,36 +1155,26 @@ do { \ : "=r" (__res)); \ __res;}) +#ifdef HAVE_AS_DSP #define rddsp(mask) \ ({ \ - unsigned int __res; \ + unsigned int __dspctl; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ + " rddsp %0, %x1 \n" \ + : "=r" (__dspctl) \ : "i" (mask)); \ - __res; \ + __dspctl; \ }) #define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ - " .set pop \n" \ - : \ + " wrdsp %0, %x1 \n" \ + : \ : "r" (val), "i" (mask)); \ } while (0) -#if 0 /* Need DSP ASE capable assembler ... */ #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) @@ -1207,6 +1197,35 @@ do { \ #else +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ + " .set pop \n" \ + : \ + : "r" (val), "i" (mask)); \ +} while (0) + #define mfhi0() \ ({ \ unsigned long __treg; \ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index de119c6..f416de3 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -99,4 +99,35 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o +# +# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe +# to enable DSP assembler support here even if the MIPS Release 2 CPU we +# are targetting does not support DSP because all code-paths making use of +# it properly check that the running CPU *actually does* support these +# instructions. +# +ifeq ($(CONFIG_CPU_MIPSR2), y) +CFLAGS_DSP = -DHAVE_AS_DSP + +# +# Check if assembler supports DSP ASE +# +ifeq ($(call cc-option-yn,-mdsp), y) +CFLAGS_DSP += -mdsp +endif + +# +# Check if assembler supports DSP ASE Rev2 +# +ifeq ($(call cc-option-yn,-mdspr2), y) +CFLAGS_DSP += -mdspr2 +endif + +CFLAGS_signal.o = $(CFLAGS_DSP) +CFLAGS_signal32.o = $(CFLAGS_DSP) +CFLAGS_process.o = $(CFLAGS_DSP) +CFLAGS_branch.o = $(CFLAGS_DSP) +CFLAGS_ptrace.o = $(CFLAGS_DSP) +endif + CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) -- 1.7.9.5 From sjhill@mips.com Thu Jan 3 22:45:51 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jan 2013 22:45:52 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:43328 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823014Ab3ACVpvBIvXO (ORCPT ); Thu, 3 Jan 2013 22:45:51 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tqsbd-0005YS-Sh; Thu, 03 Jan 2013 15:45:41 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, jchandra@broadcom.com, ddaney.cavm@gmail.com Subject: [PATCH v2] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. Date: Thu, 3 Jan 2013 15:45:36 -0600 Message-Id: <1357249536-2308-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35357 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3697 Lines: 99 From: "Steven J. Hill" The EXT and INS instructions can be used to decrease code size and thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/uasm.h | 1 + arch/mips/mm/tlbex.c | 25 +++++++++++++++++++++++++ arch/mips/mm/uasm.c | 4 +++- 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 7e0bf17..e9af35b 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -77,6 +77,7 @@ Ip_u1u2s3(_bne); Ip_u2s3u1(_cache); Ip_u2u1s3(_daddiu); Ip_u3u1u2(_daddu); +Ip_u2u1msbu3(_dext); Ip_u2u1msbu3(_dins); Ip_u2u1msbu3(_dinsm); Ip_u1u2u3(_dmfc0); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 074d659..588258f 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -977,6 +977,13 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) #endif uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); + + if (cpu_has_mips_r2) { + uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT)); + uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT)); + return; + } + uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -1012,6 +1019,24 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { + if (cpu_has_mips_r2) { + /* PTE ptr offset is obtained from BadVAddr */ + UASM_i_MFC0(p, tmp, C0_BADVADDR); + UASM_i_LW(p, ptr, 0, ptr); +#ifdef CONFIG_CPU_MIPS64 + uasm_i_dext(p, tmp, tmp, (PAGE_SHIFT + 1), + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1)); + uasm_i_dins(p, ptr, tmp, (PTE_T_LOG2 + 1), + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1)); +#else + uasm_i_ext(p, tmp, tmp, (PAGE_SHIFT + 1), + (PGDIR_SHIFT - PAGE_SHIFT - 1); + uasm_i_ins(p, ptr, tmp, (PTE_T_LOG2 + 1), + (PGDIR_SHIFT - PAGE_SHIFT - 1); +#endif + return; + } + /* * Bug workaround for the Nevada. It seems as if under certain * circumstances the move from cp0_context might produce a diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 39b8910..5bfb75a 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -60,7 +60,7 @@ enum opcode { insn_invalid, insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, - insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm, + insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dext, insn_dins, insn_dinsm, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, @@ -103,6 +103,7 @@ static struct insn insn_table[] __uasminitdata = { { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, + { insn_dext, M(spec3_op, 0, 0, 0, 0, dext_op), RS | RT | RD | RE}, { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, @@ -435,6 +436,7 @@ I_0(_tlbwi) I_0(_tlbwr) I_u3u1u2(_xor) I_u2u1u3(_xori) +I_u2u1msbdu3(_dext) I_u2u1msbu3(_dins); I_u2u1msb32u3(_dinsm); I_u1(_syscall); -- 1.7.9.5 From sjhill@mips.com Thu Jan 3 22:48:32 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jan 2013 22:48:33 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:43333 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822150Ab3ACVscVWl7R (ORCPT ); Thu, 3 Jan 2013 22:48:32 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TqseH-0005Yd-Vs; Thu, 03 Jan 2013 15:48:25 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, mcdonald.shane@gmail.com Subject: [PATCH v2] MIPS: Add option to disable software I/O coherency. Date: Thu, 3 Jan 2013 15:48:21 -0600 Message-Id: <1357249701-2386-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35358 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6695 Lines: 230 From: "Steven J. Hill" Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mach-generic/dma-coherence.h | 5 +- arch/mips/mm/c-r4k.c | 37 +++++++--- arch/mips/mm/dma-default.c | 6 +- arch/mips/mti-malta/malta-setup.c | 71 ++++++++++++++++++++ 4 files changed, 108 insertions(+), 11 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177..cd17f22 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -57,13 +57,16 @@ static inline int plat_dma_mapping_error(struct device *dev, return 0; } +extern int coherentio; +extern int hw_coherentio; + static inline int plat_device_is_coherent(struct device *dev) { #ifdef CONFIG_DMA_COHERENT return 1; #endif #ifdef CONFIG_DMA_NONCOHERENT - return 0; + return coherentio; #endif } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 606e828..bdb0ea7 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1379,19 +1379,37 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; +int coherentio = -1; /* no DMA cache coherency (may be set by user) */ +int hw_coherentio = 0; /* no HW DMA cache coherency (reflects real HW) */ static int __init setcoherentio(char *str) { - coherentio = 1; + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); return 0; } - early_param("coherentio", setcoherentio); -#endif + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 0; +} +early_param("nocoherentio", setnocoherentio); static void __cpuinit r4k_cache_error_setup(void) { @@ -1415,6 +1433,7 @@ void __cpuinit r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); + extern int coherentio; struct cpuinfo_mips *c = ¤t_cpu_data; probe_pcache(); @@ -1474,9 +1493,11 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* We want to run CMP kernels on core(s) with and without coherent caches */ + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); board_cache_error_setup = r4k_cache_error_setup; } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 3fab204..aad5f7e 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -115,7 +115,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, if (!plat_device_is_coherent(dev)) { dma_cache_wback_inv((unsigned long) ret, size); - ret = UNCAC_ADDR(ret); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } } @@ -143,7 +144,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) - addr = CAC_ADDR(addr); + if (!hw_coherentio) + addr = CAC_ADDR(addr); free_pages(addr, get_order(size)); } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index ed68073..4187102 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -104,6 +105,74 @@ static void __init fd_activate(void) } #endif +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(fw_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + hw_coherentio = supported; + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -205,6 +274,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif -- 1.7.9.5 From sjhill@mips.com Thu Jan 3 23:09:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jan 2013 23:09:51 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:33694 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822150Ab3ACWJuV1UBx convert rfc822-to-8bit (ORCPT ); Thu, 3 Jan 2013 23:09:50 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r03M9gQW021690 for ; Thu, 3 Jan 2013 14:09:43 -0800 X-WSS-ID: 0MG2LK0-01-1SJ-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2126F36465C for ; Thu, 3 Jan 2013 14:09:36 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.02.0247.003; Thu, 3 Jan 2013 14:09:33 -0800 From: "Hill, Steven" To: kbuild test robot CC: "linux-mips@linux-mips.org" Subject: RE: [mips-sjhill:mti-next 31/35] dma-default.c:(.text+0xb958): undefined reference to `hw_coherentio' Thread-Topic: [mips-sjhill:mti-next 31/35] dma-default.c:(.text+0xb958): undefined reference to `hw_coherentio' Thread-Index: AQHN1GRl0PGov6lWJkKPg2zkrF5Dg5g4T2xX Date: Thu, 3 Jan 2013 22:09:32 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AF086@exchdb03.mips.com> References: <50c1c2f5.TyQEXFiN4QI5UfpT%fengguang.wu@intel.com> In-Reply-To: <50c1c2f5.TyQEXFiN4QI5UfpT%fengguang.wu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: 8zZzdHKLd4JPxitlrtaSmQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35359 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 84 Lines: 1 Fixed by the patch "[PATCH v2] MIPS: Add option to disable software I/O coherency." From ddaney.cavm@gmail.com Thu Jan 3 23:38:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jan 2013 23:38:10 +0100 (CET) Received: from mail-da0-f47.google.com ([209.85.210.47]:63163 "EHLO mail-da0-f47.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823014Ab3ACWiGYbjmz (ORCPT ); Thu, 3 Jan 2013 23:38:06 +0100 Received: by mail-da0-f47.google.com with SMTP id s35so7170721dak.34 for ; Thu, 03 Jan 2013 14:37:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=sq4HBGXbNAUWQKVXuCpC5tkNnOOoUOZn1GR58x/C1q4=; b=mNUO6phBOd4fnnQEWsIqHudGXmBiE04O3tHCtpiBXLh5SFDHVCbZD9jDDZXtgB3PtG pAr5HuxSgqetBir0/t2zhxPpcbiThp+R8k7skOlZijkV2d1+4f9WwvehKV/OEolAzulN 9c8spwwn2iD3v1rYq6vPpi3qVq7aau8y4Q2BfeeEamzawUaddGwfuYamzFcgzYaRuBIb fw8M1Qp04dSqjXTC1SmI2/4/je1fW6abNbTGs3iuig7ItqJ4qwGaSv9O72PoBt68TIg4 oTICy7G/AlOXvhqUZpOBLHIcTDmynMgfSl/UYyEJlBkZ2lQO/FXEH3gQm5jLTK4ml0ao MPHA== X-Received: by 10.66.72.225 with SMTP id g1mr149039326pav.79.1357252679475; Thu, 03 Jan 2013 14:37:59 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id t1sm31930503paw.11.2013.01.03.14.37.58 (version=SSLv3 cipher=OTHER); Thu, 03 Jan 2013 14:37:58 -0800 (PST) Message-ID: <50E60845.9060700@gmail.com> Date: Thu, 03 Jan 2013 14:37:57 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org, jchandra@broadcom.com Subject: Re: [PATCH v2] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. References: <1357249536-2308-1-git-send-email-sjhill@mips.com> In-Reply-To: <1357249536-2308-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35360 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1591 Lines: 48 On 01/03/2013 01:45 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > The EXT and INS instructions can be used to decrease code size and > thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores. > [...] > @@ -1012,6 +1019,24 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) > > static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) > { > + if (cpu_has_mips_r2) { > + /* PTE ptr offset is obtained from BadVAddr */ > + UASM_i_MFC0(p, tmp, C0_BADVADDR); > + UASM_i_LW(p, ptr, 0, ptr); > +#ifdef CONFIG_CPU_MIPS64 Is this the right condition? Is is correct for a 32-bit kernel running on a 64-bit CPU? Will OCTEON be covered? (no, but it should) > + uasm_i_dext(p, tmp, tmp, (PAGE_SHIFT + 1), > + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1)); > + uasm_i_dins(p, ptr, tmp, (PTE_T_LOG2 + 1), > + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1)); > +#else > + uasm_i_ext(p, tmp, tmp, (PAGE_SHIFT + 1), > + (PGDIR_SHIFT - PAGE_SHIFT - 1); Did you even compile this? It looks like a mismatch in the number of '(' and ')'. > + uasm_i_ins(p, ptr, tmp, (PTE_T_LOG2 + 1), > + (PGDIR_SHIFT - PAGE_SHIFT - 1); > +#endif > + return; > + } Can this whole thing be made more clear by defining UASM_i_EXT(...) that does the proper thing for either 32 or 64 bit kernels as the rest of the capitolized versions of the macros do? Is (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1) != (PGDIR_SHIFT - PAGE_SHIFT - 1) for any combinations of config options? Why are they different for the two cases? David Daney From sjhill@mips.com Fri Jan 4 00:00:39 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 00:00:40 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:47424 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab3ACXAjvunWN convert rfc822-to-8bit (ORCPT ); Fri, 4 Jan 2013 00:00:39 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r03N0WwU022536; Thu, 3 Jan 2013 15:00:32 -0800 X-WSS-ID: 0MG2NWS-01-1TI-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 29D0236464B; Thu, 3 Jan 2013 15:00:28 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.02.0247.003; Thu, 3 Jan 2013 15:00:26 -0800 From: "Hill, Steven" To: David Daney CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "jchandra@broadcom.com" Subject: RE: [PATCH v2] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. Thread-Topic: [PATCH v2] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. Thread-Index: AQHN6fuyFYyNoBfwFkawzkGY5WNW8Jg4uBmA//99ra8= Date: Thu, 3 Jan 2013 23:00:24 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AF09D@exchdb03.mips.com> References: <1357249536-2308-1-git-send-email-sjhill@mips.com>,<50E60845.9060700@gmail.com> In-Reply-To: <50E60845.9060700@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: 4+XaOD2R76cQfdm1fZtJYA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35361 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1071 Lines: 24 >> + if (cpu_has_mips_r2) { >> + /* PTE ptr offset is obtained from BadVAddr */ >> + UASM_i_MFC0(p, tmp, C0_BADVADDR); >> + UASM_i_LW(p, ptr, 0, ptr); >> +#ifdef CONFIG_CPU_MIPS64 > > Is this the right condition? Is is correct for a 32-bit kernel running > on a 64-bit CPU? Will OCTEON be covered? (no, but it should) > You're right. The condition should be using CONFIG_64BIT instead. With regards to OCTEON, please test on your platforms and give me a patch. > Can this whole thing be made more clear by defining UASM_i_EXT(...) that > does the proper thing for either 32 or 64 bit kernels as the rest of the > capitolized versions of the macros do? > Certainly. > Is (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1) != (PGDIR_SHIFT - > PAGE_SHIFT - 1) for any combinations of config options? Why are they > different for the two cases? > I do not have 64-bit R2 hardware access. I plugged in the value that jchandra gave to me that worked for him. Other platform testers and their input would be appreciated and welcomed. -Steve From vatsa@codeaurora.org Fri Jan 4 03:58:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 03:58:39 +0100 (CET) Received: from wolverine01.qualcomm.com ([199.106.114.254]:35945 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823003Ab3ADC6fimaD0 (ORCPT ); Fri, 4 Jan 2013 03:58:35 +0100 X-IronPort-AV: E=Sophos;i="4.84,406,1355126400"; d="scan'208";a="17669274" Received: from pdmz-ns-snip_115_219.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.115.219]) by wolverine01.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 03 Jan 2013 18:58:26 -0800 Received: from svaddagi-linux.qualcomm.com (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 93B6810004BE; Thu, 3 Jan 2013 18:58:26 -0800 (PST) From: Srivatsa Vaddagiri To: Russell King , "Paul E. McKenney" , Stephen Boyd , linux-arm-kernel@lists.infradead.org, Mike Frysinger , uclinux-dist-devel@blackfin.uclinux.org, Ralf Baechle , linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , linux-s390@vger.kernel.org, Paul Mundt , linux-sh@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, mhocko@suse.cz, srivatsa.bhat@linux.vnet.ibm.com Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Srivatsa Vaddagiri Subject: [PATCH 0/2] cpuhotplug/nohz: Fix issue of "negative" idle time Date: Thu, 3 Jan 2013 18:58:10 -0800 Message-Id: <1357268290-7956-1-git-send-email-vatsa@codeaurora.org> X-Mailer: git-send-email 1.7.8.3 X-archive-position: 35362 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vatsa@codeaurora.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3075 Lines: 64 On most architectures (arm, mips, s390, sh and x86) idle thread of a cpu does not cleanly exit nohz state before dying upon hot-remove. As a result, offline cpu is seen to be in nohz mode (ts->idle_active = 1) and its offline time can potentially be included in total idle time reported via /proc/stat. When the same cpu later comes online, its offline time however is not included in its idle time statistics, thus causing a rollback in total idle time to be observed by applications like top. Example output from Android top command highlighting this issue is below: User 232%, System 70%, IOW 46%, IRQ 1% User 1322 + Nice 0 + Sys 399 + Idle -1423 + IOW 264 + IRQ 0 + SIRQ 7 = 569 top is reporting system to be idle for -1423 ticks over some sampling period. This happens as total idle time reported in cpu line of /proc/stat *dropped* from the last value observed (cached) by top command. While this was originally seen on a ARM platform running 3.4 based kernel, I could easily recreate it on my x86 desktop running latest tip/master kernel (HEAD 3a7bfcad). Online/offline a cpu in a tight loop and in another loop read /proc/stat and observe if total idle time drops from previously read value. Although commit 7386cdbf (nohz: Fix idle ticks in cpu summary line of /proc/stat) aims to avoid this bug, its not preemption proof. A thread could get preempted after the cpu_online() check in get_idle_time(), thus potentially leading to get_cpu_idle_time_us() being invoked on a offline cpu. One potential fix is to serialize hotplug with /proc/stat read operation (via use of get/put_online_cpus()), which I disliked in favor of the other solution proposed in this series. In this patch series: - Patch 1/2 modifies idle loop on architectures arm, mips, s390, sh and x86 to exit nohz state before the associated idle thread dies upon hotremove. This fixes the idle time accounting bug. Patch 1/2 also modifies idle loop on all architectures supporting cpu hotplug to have idle thread of a dying cpu die immediately after schedule() returns control to it. I see no point in wasting time via calls to *_enter()/*_exit() before noticing the need to die and dying. - Patch 2/2 reverts commit 7386cdbf (nohz: Fix idle ticks in cpu summary line of /proc/stat). The cpu_online() check introduced by it is no longer necessary with Patch 1/2 applied. Having fewer code sites worry about online status of cpus is a good thing! --- arch/arm/kernel/process.c | 9 ++++----- arch/arm/kernel/smp.c | 2 +- arch/blackfin/kernel/process.c | 8 ++++---- arch/mips/kernel/process.c | 6 +++--- arch/powerpc/kernel/idle.c | 2 +- arch/s390/kernel/process.c | 4 ++-- arch/sh/kernel/idle.c | 5 ++--- arch/sparc/kernel/process_64.c | 3 ++- arch/x86/kernel/process.c | 5 ++--- fs/proc/stat.c | 14 ++++---------- 10 files changed, 25 insertions(+), 33 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation From vatsa@codeaurora.org Fri Jan 4 03:58:53 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 03:58:59 +0100 (CET) Received: from wolverine01.qualcomm.com ([199.106.114.254]:35993 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823019Ab3ADC6xjkBTJ (ORCPT ); Fri, 4 Jan 2013 03:58:53 +0100 X-IronPort-AV: E=Sophos;i="4.84,406,1355126400"; d="scan'208";a="17669315" Received: from pdmz-ns-snip_115_219.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.115.219]) by wolverine01.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 03 Jan 2013 18:58:46 -0800 Received: from svaddagi-linux.qualcomm.com (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 8CDF910004BE; Thu, 3 Jan 2013 18:58:46 -0800 (PST) From: Srivatsa Vaddagiri To: Russell King , "Paul E. McKenney" , Stephen Boyd , linux-arm-kernel@lists.infradead.org, Mike Frysinger , uclinux-dist-devel@blackfin.uclinux.org, Ralf Baechle , linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , linux-s390@vger.kernel.org, Paul Mundt , linux-sh@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, mhocko@suse.cz, srivatsa.bhat@linux.vnet.ibm.com Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Srivatsa Vaddagiri Subject: [PATCH 1/2] cpuhotplug/nohz: Remove offline cpus from nohz-idle state Date: Thu, 3 Jan 2013 18:58:38 -0800 Message-Id: <1357268318-7993-1-git-send-email-vatsa@codeaurora.org> X-Mailer: git-send-email 1.7.8.3 X-archive-position: 35363 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vatsa@codeaurora.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7371 Lines: 250 Modify idle loop of arm, mips, s390, sh and x86 architectures to exit from nohz state before dying upon hot-remove. This change is needed to avoid userspace tools like top command from seeing a rollback in total idle time over some sampling periods. Additionaly, modify idle loop on all architectures supporting cpu hotplug to have idle thread of a dying cpu die immediately after scheduler returns control to it. There is no point in wasting time via calls to *_enter()/*_exit() before noticing the need to die and dying. Additional ARM specific change: Revert commit ff081e05 ("ARM: 7457/1: smp: Fix suspicious RCU originating from cpu_die()"), which added a RCU_NONIDLE() wrapper around call to complete(). That wrapper is no longer needed as cpu_die() is now called outside of a rcu_idle_enter()/exit() section. I also think that the wait_for_completion() based wait in ARM's __cpu_die() can be replaced with a busy-loop based one, as the wait there in general should be terminated within few cycles. Cc: Russell King Cc: Paul E. McKenney Cc: Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org Cc: Mike Frysinger Cc: uclinux-dist-devel@blackfin.uclinux.org Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: Benjamin Herrenschmidt Cc: linuxppc-dev@lists.ozlabs.org Cc: Martin Schwidefsky Cc: linux-s390@vger.kernel.org Cc: Paul Mundt Cc: linux-sh@vger.kernel.org Cc: "David S. Miller" Cc: sparclinux@vger.kernel.org Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: mhocko@suse.cz Cc: srivatsa.bhat@linux.vnet.ibm.com Signed-off-by: Srivatsa Vaddagiri --- arch/arm/kernel/process.c | 9 ++++----- arch/arm/kernel/smp.c | 2 +- arch/blackfin/kernel/process.c | 8 ++++---- arch/mips/kernel/process.c | 6 +++--- arch/powerpc/kernel/idle.c | 2 +- arch/s390/kernel/process.c | 4 ++-- arch/sh/kernel/idle.c | 5 ++--- arch/sparc/kernel/process_64.c | 3 ++- arch/x86/kernel/process.c | 5 ++--- 9 files changed, 21 insertions(+), 23 deletions(-) diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index c6dec5f..254099b 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -191,11 +191,6 @@ void cpu_idle(void) rcu_idle_enter(); ledtrig_cpu(CPU_LED_IDLE_START); while (!need_resched()) { -#ifdef CONFIG_HOTPLUG_CPU - if (cpu_is_offline(smp_processor_id())) - cpu_die(); -#endif - /* * We need to disable interrupts here * to ensure we don't miss a wakeup call. @@ -224,6 +219,10 @@ void cpu_idle(void) rcu_idle_exit(); tick_nohz_idle_exit(); schedule_preempt_disabled(); +#ifdef CONFIG_HOTPLUG_CPU + if (cpu_is_offline(smp_processor_id())) + cpu_die(); +#endif } } diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 84f4cbf..a8e3b8a 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -251,7 +251,7 @@ void __ref cpu_die(void) mb(); /* Tell __cpu_die() that this CPU is now safe to dispose of */ - RCU_NONIDLE(complete(&cpu_died)); + complete(&cpu_died); /* * actual CPU shutdown procedure is at least platform (if not diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 3e16ad9..2bee1af 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -83,10 +83,6 @@ void cpu_idle(void) while (1) { void (*idle)(void) = pm_idle; -#ifdef CONFIG_HOTPLUG_CPU - if (cpu_is_offline(smp_processor_id())) - cpu_die(); -#endif if (!idle) idle = default_idle; tick_nohz_idle_enter(); @@ -98,6 +94,10 @@ void cpu_idle(void) preempt_enable_no_resched(); schedule(); preempt_disable(); +#ifdef CONFIG_HOTPLUG_CPU + if (cpu_is_offline(smp_processor_id())) + cpu_die(); +#endif } } diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index a11c6f9..41102a0 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -71,13 +71,13 @@ void __noreturn cpu_idle(void) start_critical_timings(); } } + rcu_idle_exit(); + tick_nohz_idle_exit(); + schedule_preempt_disabled(); #ifdef CONFIG_HOTPLUG_CPU if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map)) play_dead(); #endif - rcu_idle_exit(); - tick_nohz_idle_exit(); - schedule_preempt_disabled(); } } diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c index ea78761..39ad029 100644 --- a/arch/powerpc/kernel/idle.c +++ b/arch/powerpc/kernel/idle.c @@ -102,11 +102,11 @@ void cpu_idle(void) ppc64_runlatch_on(); rcu_idle_exit(); tick_nohz_idle_exit(); + schedule_preempt_disabled(); if (cpu_should_die()) { sched_preempt_enable_no_resched(); cpu_die(); } - schedule_preempt_disabled(); } } diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index 536d645..5290556 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -66,8 +66,6 @@ unsigned long thread_saved_pc(struct task_struct *tsk) */ static void default_idle(void) { - if (cpu_is_offline(smp_processor_id())) - cpu_die(); local_irq_disable(); if (need_resched()) { local_irq_enable(); @@ -95,6 +93,8 @@ void cpu_idle(void) if (test_thread_flag(TIF_MCCK_PENDING)) s390_handle_mcck(); schedule_preempt_disabled(); + if (cpu_is_offline(smp_processor_id())) + cpu_die(); } } diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c index 0c91016..f8bc2f0 100644 --- a/arch/sh/kernel/idle.c +++ b/arch/sh/kernel/idle.c @@ -96,9 +96,6 @@ void cpu_idle(void) check_pgt_cache(); rmb(); - if (cpu_is_offline(cpu)) - play_dead(); - local_irq_disable(); /* Don't trace irqs off for idle */ stop_critical_timings(); @@ -115,6 +112,8 @@ void cpu_idle(void) rcu_idle_exit(); tick_nohz_idle_exit(); schedule_preempt_disabled(); + if (cpu_is_offline(cpu)) + play_dead(); } } diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c index cdb80b2..01589e7 100644 --- a/arch/sparc/kernel/process_64.c +++ b/arch/sparc/kernel/process_64.c @@ -105,13 +105,14 @@ void cpu_idle(void) rcu_idle_exit(); tick_nohz_idle_exit(); + schedule_preempt_disabled(); + #ifdef CONFIG_HOTPLUG_CPU if (cpu_is_offline(cpu)) { sched_preempt_enable_no_resched(); cpu_play_dead(); } #endif - schedule_preempt_disabled(); } } diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 2ed787f..3d5f142 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -331,9 +331,6 @@ void cpu_idle(void) while (!need_resched()) { rmb(); - if (cpu_is_offline(smp_processor_id())) - play_dead(); - /* * Idle routines should keep interrupts disabled * from here on, until they go to idle. @@ -366,6 +363,8 @@ void cpu_idle(void) preempt_enable_no_resched(); schedule(); preempt_disable(); + if (cpu_is_offline(smp_processor_id())) + play_dead(); } } -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation From vatsa@codeaurora.org Fri Jan 4 03:59:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 03:59:17 +0100 (CET) Received: from wolverine01.qualcomm.com ([199.106.114.254]:36046 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823044Ab3ADC7GyLNJ6 (ORCPT ); Fri, 4 Jan 2013 03:59:06 +0100 X-IronPort-AV: E=Sophos;i="4.84,406,1355126400"; d="scan'208";a="17669351" Received: from pdmz-ns-snip_115_219.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.115.219]) by wolverine01.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 03 Jan 2013 18:59:00 -0800 Received: from svaddagi-linux.qualcomm.com (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id C8F7610004DC; Thu, 3 Jan 2013 18:58:59 -0800 (PST) From: Srivatsa Vaddagiri To: Russell King , "Paul E. McKenney" , Stephen Boyd , linux-arm-kernel@lists.infradead.org, Mike Frysinger , uclinux-dist-devel@blackfin.uclinux.org, Ralf Baechle , linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , linux-s390@vger.kernel.org, Paul Mundt , linux-sh@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, mhocko@suse.cz, srivatsa.bhat@linux.vnet.ibm.com Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Srivatsa Vaddagiri Subject: [PATCH 2/2] Revert "nohz: Fix idle ticks in cpu summary line of /proc/stat" (commit 7386cdbf2f57ea8cff3c9fde93f206e58b9fe13f). Date: Thu, 3 Jan 2013 18:58:57 -0800 Message-Id: <1357268337-8025-1-git-send-email-vatsa@codeaurora.org> X-Mailer: git-send-email 1.7.8.3 X-archive-position: 35364 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vatsa@codeaurora.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1755 Lines: 52 With offline cpus no longer beeing seen in nohz mode (ts->idle_active=0), we don't need the check for cpu_online() introduced in commit 7386cdbf. Offline cpu's idle time as last recorded in its ts->idle_sleeptime will be reported (thus excluding its offline time as part of idle time statistics). Cc: mhocko@suse.cz Cc: srivatsa.bhat@linux.vnet.ibm.com Signed-off-by: Srivatsa Vaddagiri --- fs/proc/stat.c | 14 ++++---------- 1 files changed, 4 insertions(+), 10 deletions(-) diff --git a/fs/proc/stat.c b/fs/proc/stat.c index e296572..64c3b31 100644 --- a/fs/proc/stat.c +++ b/fs/proc/stat.c @@ -45,13 +45,10 @@ static cputime64_t get_iowait_time(int cpu) static u64 get_idle_time(int cpu) { - u64 idle, idle_time = -1ULL; - - if (cpu_online(cpu)) - idle_time = get_cpu_idle_time_us(cpu, NULL); + u64 idle, idle_time = get_cpu_idle_time_us(cpu, NULL); if (idle_time == -1ULL) - /* !NO_HZ or cpu offline so we can rely on cpustat.idle */ + /* !NO_HZ so we can rely on cpustat.idle */ idle = kcpustat_cpu(cpu).cpustat[CPUTIME_IDLE]; else idle = usecs_to_cputime64(idle_time); @@ -61,13 +58,10 @@ static u64 get_idle_time(int cpu) static u64 get_iowait_time(int cpu) { - u64 iowait, iowait_time = -1ULL; - - if (cpu_online(cpu)) - iowait_time = get_cpu_iowait_time_us(cpu, NULL); + u64 iowait, iowait_time = get_cpu_iowait_time_us(cpu, NULL); if (iowait_time == -1ULL) - /* !NO_HZ or cpu offline so we can rely on cpustat.iowait */ + /* !NO_HZ so we can rely on cpustat.iowait */ iowait = kcpustat_cpu(cpu).cpustat[CPUTIME_IOWAIT]; else iowait = usecs_to_cputime64(iowait_time); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation From mcdonald.shane@gmail.com Fri Jan 4 04:40:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 04:40:16 +0100 (CET) Received: from mail-ia0-f169.google.com ([209.85.210.169]:59424 "EHLO mail-ia0-f169.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816383Ab3ADDkOrtgQm (ORCPT ); Fri, 4 Jan 2013 04:40:14 +0100 Received: by mail-ia0-f169.google.com with SMTP id u20so6877732iag.14 for ; Thu, 03 Jan 2013 19:40:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:date:message-id:to:subject:from; bh=dWuFON15dyQb57+zeH11EuVJTmhE2D6tcROiMI+DH1E=; b=SxcblVaq2PSZg+M/tLChFOmt3NcoKw7QwG6PPNHmYP+JpFzAiNOvhT6lres61Bkq3h dhEikKpOtvpN01Z5yEbxl76zIpQ9F3rMGpzr5s9soXS9IQirk952/Y90gmpVtQx6AXvb IJyfNpm5mWSLNRyHFPVc36bra77sSofSTRvAgLvKFsD+tpXiAmi5YeGwGABg/Qc8we0P RoLPnLTky8+0WUDqOY7PBXsX4MpFElN5ndoNbZIRS3I8k0ZMhhoXoHOkMpqBCYPp2p5w Yt7XEeUEehnPmnHO9bvaLHlNOB5tgraqSGIXKNG71KvVdC0QlzUtNkvHniX6ini55c4b 6LAg== X-Received: by 10.50.197.169 with SMTP id iv9mr42550192igc.32.1357270807448; Thu, 03 Jan 2013 19:40:07 -0800 (PST) Received: from localhost ([207.47.250.72]) by mx.google.com with ESMTPS id eu3sm46094529igc.7.2013.01.03.19.40.05 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 03 Jan 2013 19:40:06 -0800 (PST) Received: from shane by localhost with local (Exim 4.72) (envelope-from ) id 1Tqy8Z-0003Uc-Cm; Thu, 03 Jan 2013 21:40:03 -0600 Date: Thu, 03 Jan 2013 21:40:03 -0600 Message-Id: To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH] MIPS: Fix build failure of msp71xx default configuration From: Shane McDonald X-archive-position: 35365 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1740 Lines: 43 The msp71xx default configuration fails to compile in Linux 3.8-rc2: In file included from /home/shane/linux-mips/linux/arch/mips/include/asm/bitops.h:22, from include/linux/bitops.h:22, from include/linux/kernel.h:10, from include/asm-generic/bug.h:13, from /home/shane/linux-mips/linux/arch/mips/include/asm/bug.h:41, from include/linux/bug.h:4, from include/linux/page-flags.h:9, from kernel/bounds.c:9: /home/shane/linux-mips/linux/arch/mips/include/asm/war.h:12:17: error: war.h: No such file or directory This is because the Platform file points at the incorrect include file location, and therefore the war.h file cannot be found. This patch changes the Platform file to point to the correct location. Caused by a combination of the following lmo-only patches: 13a347ef60c68e490809dad8fcf79c25eabc4d58 [MIPS: MSP71xx: Move code.] a89c0370cb5429891d49abcc66f93c63b43c7dbe [MIPS: Fix make distclean after moving the PMC-Sierra code.] Signed-off-by: Shane McDonald --- arch/mips/pmcs-msp71xx/Platform | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/pmcs-msp71xx/Platform b/arch/mips/pmcs-msp71xx/Platform index e42a4d6..9a86e29 100644 --- a/arch/mips/pmcs-msp71xx/Platform +++ b/arch/mips/pmcs-msp71xx/Platform @@ -2,6 +2,6 @@ # PMC-Sierra MSP SOCs # platform-$(CONFIG_PMC_MSP) += pmcs-msp71xx/ -cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/pmc-sierra \ +cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \ -mno-branch-likely load-$(CONFIG_PMC_MSP) += 0xffffffff80100000 -- 1.7.2.5 From sshtylyov@mvista.com Fri Jan 4 13:13:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 13:13:54 +0100 (CET) Received: from mail-la0-f53.google.com ([209.85.215.53]:61365 "EHLO mail-la0-f53.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816671Ab3ADMNwmzPkl (ORCPT ); Fri, 4 Jan 2013 13:13:52 +0100 Received: by mail-la0-f53.google.com with SMTP id fn20so9660077lab.12 for ; Fri, 04 Jan 2013 04:13:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=dt4zimQaJ0mzs/+SodCArpnmuFEx4aIMTG3htFMAUjs=; b=Sx2ZzeTenhRmd3l5VFI0GdgPrHnwitP//8bB4G9PrFemd350DlDYEWTEUJorikLCf9 69xlksC//LYXx71+yT+EVKpQ/NSuNLkVvTrGNcU9KNgkPxeoxdDaThFwzkEXp10NcICN JOR7e4TMYbp6718AXZ+iGW9jxWz1dKWKm7vUGOxJHGcZfRH2Ziqc+Yc6aznPeMWXvL/y N1Xi52O5rfRr+1Kl4l/t6IkIUDHF7fx2luw6ZvDSTpRfN/tV7xCr0WpD/V+BmgXhTU9l +wwji8KW9qr4l9aJ+rvkLugqBtYi8O9bKXD0Zhc6B6vvc61B56z0eeY+ulRlLX3QOv3z VngQ== X-Received: by 10.112.54.6 with SMTP id f6mr21393757lbp.71.1357301626691; Fri, 04 Jan 2013 04:13:46 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-95-142.pppoe.mtu-net.ru. [91.79.95.142]) by mx.google.com with ESMTPS id fh4sm17879228lbb.7.2013.01.04.04.13.43 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Jan 2013 04:13:45 -0800 (PST) Message-ID: <50E6C776.7060707@mvista.com> Date: Fri, 04 Jan 2013 16:13:42 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Srivatsa Vaddagiri CC: Russell King , "Paul E. McKenney" , Stephen Boyd , linux-arm-kernel@lists.infradead.org, Mike Frysinger , uclinux-dist-devel@blackfin.uclinux.org, Ralf Baechle , linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , linux-s390@vger.kernel.org, Paul Mundt , linux-sh@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, mhocko@suse.cz, srivatsa.bhat@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH 2/2] Revert "nohz: Fix idle ticks in cpu summary line of /proc/stat" (commit 7386cdbf2f57ea8cff3c9fde93f206e58b9fe13f). References: <1357268337-8025-1-git-send-email-vatsa@codeaurora.org> In-Reply-To: <1357268337-8025-1-git-send-email-vatsa@codeaurora.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQmcrg/lCFAZMvVWKZQbTpjDWNSEy7sIQrF/oW15y39S3UB7BWe74wNEkjheYyuA8/UUAJEo X-archive-position: 35366 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 581 Lines: 19 Hello. On 04-01-2013 6:58, Srivatsa Vaddagiri wrote: > With offline cpus no longer beeing seen in nohz mode (ts->idle_active=0), we > don't need the check for cpu_online() introduced in commit 7386cdbf. Offline Please also specify the summary of that commit in parens (or however you like). > cpu's idle time as last recorded in its ts->idle_sleeptime will be reported > (thus excluding its offline time as part of idle time statistics). > Cc: mhocko@suse.cz > Cc: srivatsa.bhat@linux.vnet.ibm.com > Signed-off-by: Srivatsa Vaddagiri WBR, Sergei From sjhill@mips.com Fri Jan 4 18:59:30 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 18:59:31 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:45023 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab3ADR7aZEOjQ (ORCPT ); Fri, 4 Jan 2013 18:59:30 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TrBY8-000726-WE; Fri, 04 Jan 2013 11:59:21 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, jchandra@broadcom.com, ddaney.cavm@gmail.com Subject: [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. Date: Fri, 4 Jan 2013 11:59:15 -0600 Message-Id: <1357322355-31622-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35367 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4870 Lines: 118 From: "Steven J. Hill" The EXT and INS instructions can be used to decrease code size and thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/uasm.h | 5 +++++ arch/mips/mm/tlbex.c | 26 ++++++++++++++++++++++++++ arch/mips/mm/uasm.c | 4 +++- 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 7e0bf17..e7cacce 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -77,6 +77,7 @@ Ip_u1u2s3(_bne); Ip_u2s3u1(_cache); Ip_u2u1s3(_daddiu); Ip_u3u1u2(_daddu); +Ip_u2u1msbu3(_dext); Ip_u2u1msbu3(_dins); Ip_u2u1msbu3(_dinsm); Ip_u1u2u3(_dmfc0); @@ -151,6 +152,8 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ #ifdef CONFIG_64BIT # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val) # define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd) +# define UASM_i_EXT(buf, rs, rt, msbd, lsb) uasm_i_dext(buf, rs, rt, msbd, lsb) +# define UASM_i_INS(buf, rs, rt, msbd, lsb) uasm_i_dins(buf, rs, rt, msbd, lsb) # define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off) # define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off) # define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd) @@ -167,6 +170,8 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ #else # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val) # define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd) +# define UASM_i_EXT(buf, rs, rt, msbd, lsb) uasm_i_ext(buf, rs, rt, msbd, lsb) +# define UASM_i_INS(buf, rs, rt, msbd, lsb) uasm_i_ins(buf, rs, rt, msbd, lsb) # define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off) # define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off) # define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 074d659..5681623 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -977,6 +977,13 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) #endif uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); + + if (cpu_has_mips_r2) { + uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT)); + uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT)); + return; + } + uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -1012,6 +1019,25 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { + if (cpu_has_mips_r2) { + /* PTE ptr offset is obtained from BadVAddr */ + UASM_i_MFC0(p, tmp, C0_BADVADDR); + UASM_i_LW(p, ptr, 0, ptr); + UASM_i_EXT(p, tmp, tmp, (PAGE_SHIFT + 1), +#ifdef CONFIG_64BIT + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1)); +#else + (PGDIR_SHIFT - PAGE_SHIFT - 1)); +#endif + UASM_i_INS(p, ptr, tmp, (PTE_T_LOG2 + 1), +#ifdef CONFIG_64BIT + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1)); +#else + (PGDIR_SHIFT - PAGE_SHIFT - 1)); +#endif + return; + } + /* * Bug workaround for the Nevada. It seems as if under certain * circumstances the move from cp0_context might produce a diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 39b8910..5bfb75a 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -60,7 +60,7 @@ enum opcode { insn_invalid, insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, - insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm, + insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dext, insn_dins, insn_dinsm, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, @@ -103,6 +103,7 @@ static struct insn insn_table[] __uasminitdata = { { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, + { insn_dext, M(spec3_op, 0, 0, 0, 0, dext_op), RS | RT | RD | RE}, { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, @@ -435,6 +436,7 @@ I_0(_tlbwi) I_0(_tlbwr) I_u3u1u2(_xor) I_u2u1u3(_xori) +I_u2u1msbdu3(_dext) I_u2u1msbu3(_dins); I_u2u1msb32u3(_dinsm); I_u1(_syscall); -- 1.7.9.5 From arend@broadcom.com Fri Jan 4 19:11:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 19:11:06 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:3914 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab3ADSLEvMkfP (ORCPT ); Fri, 4 Jan 2013 19:11:04 +0100 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 04 Jan 2013 10:07:14 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 4 Jan 2013 10:10:03 -0800 Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.17.16.106]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 7C4C040FE9; Fri, 4 Jan 2013 10:10:15 -0800 (PST) Received: from arend-vb-linux (unknown [10.177.252.106]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 0B919207C0; Fri, 4 Jan 2013 10:10:14 -0800 (PST) Received: from arend by arend-vb-linux with local (Exim 4.80) ( envelope-from ) id 1TrBig-0007II-CZ; Fri, 04 Jan 2013 19:10:14 +0100 From: "Arend van Spriel" To: "Ralf Baechle" cc: linux-mips@linux-mips.org, "Arend van Spriel" , "Hauke Mehrtens" Subject: [PATCH] mips: bcm47xx: select GPIOLIB for BCMA on bcm47xx platform Date: Fri, 4 Jan 2013 19:10:05 +0100 Message-ID: <1357323005-28008-1-git-send-email-arend@broadcom.com> X-Mailer: git-send-email 1.7.10.4 MIME-Version: 1.0 X-WSS-ID: 7CF9C5D83Q4639643-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35368 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arend@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1557 Lines: 50 The Kconfig items BCM47XX_BCMA and BCM47XX_SSB selected respectively BCMA_DRIVER_GPIO and SSB_DRIVER_GPIO. These options depend on GPIOLIB without explicitly selecting it so it results in a warning when GPIOLIB is not set: scripts/kconfig/conf --oldconfig Kconfig warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO ... unmet direct dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO ... unmet direct dependencies (SSB_POSSIBLE && SSB && GPIOLIB) which subsequently results in compile errors. Cc: Hauke Mehrtens Signed-off-by: Arend van Spriel --- Fixing a Kconfig issue in our nightly Jenkins build. Gr. AvS --- arch/mips/bcm47xx/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig index d7af29f..ba61192 100644 --- a/arch/mips/bcm47xx/Kconfig +++ b/arch/mips/bcm47xx/Kconfig @@ -8,8 +8,10 @@ config BCM47XX_SSB select SSB_DRIVER_EXTIF select SSB_EMBEDDED select SSB_B43_PCI_BRIDGE if PCI + select SSB_DRIVER_PCICORE if PCI select SSB_PCICORE_HOSTMODE if PCI select SSB_DRIVER_GPIO + select GPIOLIB default y help Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. @@ -25,6 +27,7 @@ config BCM47XX_BCMA select BCMA_HOST_PCI if PCI select BCMA_DRIVER_PCI_HOSTMODE if PCI select BCMA_DRIVER_GPIO + select GPIOLIB default y help Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus. -- 1.7.10.4 From ddaney.cavm@gmail.com Fri Jan 4 19:14:25 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 19:14:26 +0100 (CET) Received: from mail-da0-f50.google.com ([209.85.210.50]:53360 "EHLO mail-da0-f50.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab3ADSOZq3gtN (ORCPT ); Fri, 4 Jan 2013 19:14:25 +0100 Received: by mail-da0-f50.google.com with SMTP id h15so7626689dan.9 for ; Fri, 04 Jan 2013 10:14:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=2wvmZ8TQzoebBFkKr93wPyWHqgIwGcFwipYnbXi6YxI=; b=l0JZDLBmAz293hEWXdN7kNG/Cv1XK4kkBFmqJ1RfRc+SV1CMWz4AA9IqyvfX7MDrrb ALMvHsoTglydn+E3xJGmcwI6HfwUL0n0YgLt/htqyax4A9dOgq6GL1tmVMLBWQdFJq19 6puXRNCp/jot6T04CGTrzHvejp/lS7kULp5lKQsHZHBk+4pe6Bw70k9jiS95JXnSRgfP GmqVAayA+ZuHl816tgqDEkUOOUr3FCRJl+ac0gz60dT2yH+u33hsJqcmRgSRPeNEDI8C EGFPbMMcyak5llKRxphlRorshsqN/uSIBHpmKnK8pXvXnpx5B69nCUJ6EEtcZnDz7Ajt kgOQ== X-Received: by 10.66.86.71 with SMTP id n7mr156601970paz.77.1357323258764; Fri, 04 Jan 2013 10:14:18 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id m3sm33581884pav.4.2013.01.04.10.14.17 (version=SSLv3 cipher=OTHER); Fri, 04 Jan 2013 10:14:17 -0800 (PST) Message-ID: <50E71BF8.3050308@gmail.com> Date: Fri, 04 Jan 2013 10:14:16 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org, jchandra@broadcom.com Subject: Re: [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. References: <1357322355-31622-1-git-send-email-sjhill@mips.com> In-Reply-To: <1357322355-31622-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35369 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 670 Lines: 24 On 01/04/2013 09:59 AM, Steven J. Hill wrote: > From: "Steven J. Hill" > > The EXT and INS instructions can be used to decrease code size and > thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores. > > Signed-off-by: Steven J. Hill [...] > +#ifdef CONFIG_64BIT > + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1)); > +#else > + (PGDIR_SHIFT - PAGE_SHIFT - 1)); > +#endif > + UASM_i_INS(p, ptr, tmp, (PTE_T_LOG2 + 1), As far as I can tell, (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1) and (PGDIR_SHIFT - PAGE_SHIFT - 1) are the same thing. So why the two cases? Can you give an example of where they might differ? David Daney From sjhill@mips.com Fri Jan 4 19:25:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 19:25:49 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:59818 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab3ADSZscWZwy convert rfc822-to-8bit (ORCPT ); Fri, 4 Jan 2013 19:25:48 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r04IPeQ1009287; Fri, 4 Jan 2013 10:25:40 -0800 X-WSS-ID: 0MG45TP-01-24M-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 229D236465C; Fri, 4 Jan 2013 10:25:00 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.02.0247.003; Fri, 4 Jan 2013 10:24:55 -0800 From: "Hill, Steven" To: David Daney CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "jchandra@broadcom.com" Subject: RE: [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. Thread-Topic: [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. Thread-Index: AQHN6qU9UKBlTq5FeUuwhULMCz9AMZg5/24A//97J4Y= Date: Fri, 4 Jan 2013 18:24:54 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AF100@exchdb03.mips.com> References: <1357322355-31622-1-git-send-email-sjhill@mips.com>,<50E71BF8.3050308@gmail.com> In-Reply-To: <50E71BF8.3050308@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: NtxUHQ/gjj18I5uxbWYO/Q== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35370 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 823 Lines: 17 >> +#ifdef CONFIG_64BIT >> + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1)); >> +#else >> + (PGDIR_SHIFT - PAGE_SHIFT - 1)); >> +#endif >> + UASM_i_INS(p, ptr, tmp, (PTE_T_LOG2 + 1), > > As far as I can tell, (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1) and > (PGDIR_SHIFT - PAGE_SHIFT - 1) are the same thing. So why the two cases? > >Can you give an example of where they might differ? > David, Actually, no I cannot. The calculation was given to me by 'jchandra' and since I do not have 64-bit R2 hardware let alone the Broadcom platform, he said it worked on his platform and I took it from him as is. So does this patch work on Cavium platforms using both calculation methods? It would be nice if 'jchandra' could chime in, but he may be on holiday or something. -Steve From sjhill@mips.com Fri Jan 4 19:38:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 19:38:45 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:33005 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab3ADSinkQhQ0 convert rfc822-to-8bit (ORCPT ); Fri, 4 Jan 2013 19:38:43 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r04Ica87009682; Fri, 4 Jan 2013 10:38:36 -0800 X-WSS-ID: 0MG46GC-01-252-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2776436465C; Fri, 4 Jan 2013 10:38:36 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.02.0247.003; Fri, 4 Jan 2013 10:38:34 -0800 From: "Hill, Steven" To: David Daney , "Maciej W. Rozycki" CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: RE: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs. Thread-Topic: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs. Thread-Index: AQHN2X9pyfb9ZaeD/km09iPLMrJAg5gX5feAgAADMQCAIbbgOA== Date: Fri, 4 Jan 2013 18:38:32 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AF10B@exchdb03.mips.com> References: <1355436915-24381-1-git-send-email-sjhill@mips.com> ,<50CA6712.1060809@gmail.com> In-Reply-To: <50CA6712.1060809@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: /Khdoq2rU3xB5aGaH5PAOA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35371 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 721 Lines: 8 > You're exporting privileged context outside the kernel -- have all the > security implications been considered? > Maciej, I have gone through the config registers bit-by-bit and I do not see where there are any security implications. There are maybe 7 bits total in config registers 0 through 5 that are R/W and this patch, of course, is providing RO access. A motivated person could download the PRA documents from our website even without this patch to discover what was implemented in the system. I could certainly see security implications if we were exporting the STATUS, CAUSE, and other critical registers. Unless you can provide a counterexample, this patch does not compromise the system in anyway. -Steve From ddaney.cavm@gmail.com Fri Jan 4 20:05:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 20:05:15 +0100 (CET) Received: from mail-pb0-f53.google.com ([209.85.160.53]:63355 "EHLO mail-pb0-f53.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab3ADTFOfCl9C (ORCPT ); Fri, 4 Jan 2013 20:05:14 +0100 Received: by mail-pb0-f53.google.com with SMTP id jt11so9314620pbb.26 for ; Fri, 04 Jan 2013 11:05:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=ORHSDGg59oCKhIKA9/cwFsuJVM/1NJ1zxemBLh1Y7Bo=; b=DZ+ynN3bFLXzm28YK2mHiSUZNq4BQQMiyNy8u4aJalgOp4LE4mssmuX2eId+5UNHhn u8lPqFZUfr1F2Ei6TWkEoyXn7JX908y87g3Hv+zdBwh7BuZ72dtR5dsjhvWROJ7o7aEK iDVartADHjNV7kwXbBJvGeriMBIcFbT3WsPmi3Z2L2UXdVy5K9Nys0O+tUkeenC5LdXu zAnUAaTLw7IclCT9kL7+iO9UyX9zgqMmfboP/Kn69DsaM6ZWRm+Y6R/VQ7CQNSFkvB5q v0Z8ICaex2yRy4nMz4T3LxwZwvvRGE6lmn8o9zHrxRrxIXGriczEekraMZr0gp75XbvN gxeQ== X-Received: by 10.68.209.230 with SMTP id mp6mr163572503pbc.8.1357326307601; Fri, 04 Jan 2013 11:05:07 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id pm8sm32665936pbb.29.2013.01.04.11.05.06 (version=SSLv3 cipher=OTHER); Fri, 04 Jan 2013 11:05:06 -0800 (PST) Message-ID: <50E727E1.8040604@gmail.com> Date: Fri, 04 Jan 2013 11:05:05 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Hill, Steven" CC: "Maciej W. Rozycki" , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: Re: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs. References: <1355436915-24381-1-git-send-email-sjhill@mips.com> ,<50CA6712.1060809@gmail.com> <31E06A9FC96CEC488B43B19E2957C1B801146AF10B@exchdb03.mips.com> In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B801146AF10B@exchdb03.mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35372 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 538 Lines: 19 On 01/04/2013 10:38 AM, Hill, Steven wrote: >> You're exporting privileged context outside the kernel -- have all the >> security implications been considered? >> > Maciej, > > I have gone through the config registers bit-by-bit and I do not see > where there are any security implications. [...] > Unless you can provide a counterexample, > this patch does not compromise the system in anyway. > The patch stands alone. Any security problems it might have are completely unrelated to any hypothetical Counter Examples. David Daney From vatsa@codeaurora.org Fri Jan 4 20:29:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 20:29:47 +0100 (CET) Received: from wolverine02.qualcomm.com ([199.106.114.251]:35537 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6820513Ab3ADT3nXyAnV (ORCPT ); Fri, 4 Jan 2013 20:29:43 +0100 X-IronPort-AV: E=Sophos;i="4.84,412,1355126400"; d="scan'208";a="17972381" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine02.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 04 Jan 2013 11:29:35 -0800 Received: from quicinc.com (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 4D60D10004BE; Fri, 4 Jan 2013 11:29:35 -0800 (PST) Date: Fri, 4 Jan 2013 11:29:34 -0800 From: Srivatsa Vaddagiri To: Sergei Shtylyov Cc: Russell King , "Paul E. McKenney" , Stephen Boyd , linux-arm-kernel@lists.infradead.org, Mike Frysinger , uclinux-dist-devel@blackfin.uclinux.org, Ralf Baechle , linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , linux-s390@vger.kernel.org, Paul Mundt , linux-sh@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, mhocko@suse.cz, srivatsa.bhat@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH 2/2] Revert "nohz: Fix idle ticks in cpu summary line of /proc/stat" (commit 7386cdbf2f57ea8cff3c9fde93f206e58b9fe13f). Message-ID: <20130104192934.GB29866@quicinc.com> Reply-To: Srivatsa Vaddagiri References: <1357268337-8025-1-git-send-email-vatsa@codeaurora.org> <50E6C776.7060707@mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <50E6C776.7060707@mvista.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 35373 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vatsa@codeaurora.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 508 Lines: 13 * Sergei Shtylyov [2013-01-04 16:13:42]: > >With offline cpus no longer beeing seen in nohz mode (ts->idle_active=0), we > >don't need the check for cpu_online() introduced in commit 7386cdbf. Offline > > Please also specify the summary of that commit in parens (or > however you like). I had that in Subject line, but yes would be good to include in commit message as well. I will incorporate that change alongwith anything else required in next version of this patch. - vatsa From sjhill@mips.com Fri Jan 4 20:30:45 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 20:30:46 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:49974 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6820513Ab3ADTapQHtjF convert rfc822-to-8bit (ORCPT ); Fri, 4 Jan 2013 20:30:45 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r04JUbEb010958; Fri, 4 Jan 2013 11:30:37 -0800 X-WSS-ID: 0MG48UY-01-26P-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 231F936465C; Fri, 4 Jan 2013 11:30:34 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.02.0247.003; Fri, 4 Jan 2013 11:30:33 -0800 From: "Hill, Steven" To: David Daney CC: "Maciej W. Rozycki" , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: RE: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs. Thread-Topic: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs. Thread-Index: AQHN2X9pyfb9ZaeD/km09iPLMrJAg5gX5feAgAADMQCAIbbgOIAAj+WA//+AxrE= Date: Fri, 4 Jan 2013 19:30:31 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AF11F@exchdb03.mips.com> References: <1355436915-24381-1-git-send-email-sjhill@mips.com> ,<50CA6712.1060809@gmail.com> <31E06A9FC96CEC488B43B19E2957C1B801146AF10B@exchdb03.mips.com>,<50E727E1.8040604@gmail.com> In-Reply-To: <50E727E1.8040604@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: T1AhJZHQKcGYobS2TeX/pA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35374 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 189 Lines: 6 > The patch stands alone. Any security problems it might have are > completely unrelated to any hypothetical Counter Examples. > Indeed. So, can I get an ACK or what next? Thanks. -Steve From sshtylyov@mvista.com Fri Jan 4 20:44:19 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 20:44:20 +0100 (CET) Received: from mail-la0-f51.google.com ([209.85.215.51]:49260 "EHLO mail-la0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6820513Ab3ADToTquM6i (ORCPT ); Fri, 4 Jan 2013 20:44:19 +0100 Received: by mail-la0-f51.google.com with SMTP id fj20so10097213lab.24 for ; Fri, 04 Jan 2013 11:44:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=f/qIS7csv+7S92xYwzs8Yh7E285UKmwCDR7VTITzdH4=; b=T84xqdlkpf21hd8+36WhqqsIywL4Ph+N+Buo8Br1khj8x2eZfOj/QjnBW3TgiUKYpC vWnrQ2I+GZ4cv23JPEM51EnI+IArF60clvWSYbNub+nyDLuaE38FXJNwHyqwe1E1NJNz VKvEJk8+1l5GLwN0usVjAi+34AseYrwEFRlzqW08GD2OAfNDgVx3+Q9I0tFElG9aw7iN uX86rlWuC5D81RIOJB/YmXaH4YjNP6iCk/VXvGcQQCOKPrOjhZZpWOL+pqpmWHXJ/jHm KjtKvktqpB/LNxR2PtNCPqCWjjXNIr5Luiun2d9nEAD15SKHKBo3Q8v3SmhXjuvJ2JbT 0mAQ== X-Received: by 10.112.17.108 with SMTP id n12mr20489224lbd.21.1357328653767; Fri, 04 Jan 2013 11:44:13 -0800 (PST) Received: from wasted.dev.rtsoft.ru (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id u5sm18214231lbm.8.2013.01.04.11.44.11 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Jan 2013 11:44:12 -0800 (PST) Message-ID: <50E73EB6.9090100@mvista.com> Date: Fri, 04 Jan 2013 23:42:30 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Srivatsa Vaddagiri CC: Russell King , "Paul E. McKenney" , Stephen Boyd , linux-arm-kernel@lists.infradead.org, Mike Frysinger , uclinux-dist-devel@blackfin.uclinux.org, Ralf Baechle , linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , linux-s390@vger.kernel.org, Paul Mundt , linux-sh@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, mhocko@suse.cz, srivatsa.bhat@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH 2/2] Revert "nohz: Fix idle ticks in cpu summary line of /proc/stat" (commit 7386cdbf2f57ea8cff3c9fde93f206e58b9fe13f). References: <1357268337-8025-1-git-send-email-vatsa@codeaurora.org> <50E6C776.7060707@mvista.com> <20130104192934.GB29866@quicinc.com> In-Reply-To: <20130104192934.GB29866@quicinc.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQloT3DHFxnSeSz8+laetL+MAz4Cfz38wkd59v9RYheqelRB+20PukV1bbfqAoch+RpiGpN8 X-archive-position: 35375 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 634 Lines: 21 Hello. On 01/04/2013 10:29 PM, Srivatsa Vaddagiri wrote: >>> With offline cpus no longer beeing seen in nohz mode (ts->idle_active=0), we >>> don't need the check for cpu_online() introduced in commit 7386cdbf. Offline >> Please also specify the summary of that commit in parens (or >> however you like). > I had that in Subject line, but yes would be good to include in commit message > as well. I will incorporate that change alongwith anything else required in > next version of this patch. Ah, that was a revert with atypical subject -- didn't notice. Then there's no need to specify it twice. > - vatsa WBR, Sergei From hauke@hauke-m.de Fri Jan 4 20:48:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 20:48:49 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:50445 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6820513Ab3ADTso175tw (ORCPT ); Fri, 4 Jan 2013 20:48:44 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id BFA608F60; Fri, 4 Jan 2013 20:48:43 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id alMnWY4YDExe; Fri, 4 Jan 2013 20:48:37 +0100 (CET) Received: from [IPv6:2001:470:1f0b:447:89b9:649b:29b7:7863] (unknown [IPv6:2001:470:1f0b:447:89b9:649b:29b7:7863]) by hauke-m.de (Postfix) with ESMTPSA id EF3098E1C; Fri, 4 Jan 2013 20:48:36 +0100 (CET) Message-ID: <50E73212.60003@hauke-m.de> Date: Fri, 04 Jan 2013 20:48:34 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Arend van Spriel CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] mips: bcm47xx: select GPIOLIB for BCMA on bcm47xx platform References: <1357323005-28008-1-git-send-email-arend@broadcom.com> In-Reply-To: <1357323005-28008-1-git-send-email-arend@broadcom.com> X-Enigmail-Version: 1.4.6 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35376 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1075 Lines: 31 On 01/04/2013 07:10 PM, Arend van Spriel wrote: > The Kconfig items BCM47XX_BCMA and BCM47XX_SSB selected > respectively BCMA_DRIVER_GPIO and SSB_DRIVER_GPIO. These > options depend on GPIOLIB without explicitly selecting it > so it results in a warning when GPIOLIB is not set: > > scripts/kconfig/conf --oldconfig Kconfig > warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO ... unmet direct > dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) > warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO ... unmet direct > dependencies (SSB_POSSIBLE && SSB && GPIOLIB) > > which subsequently results in compile errors. > > Cc: Hauke Mehrtens > Signed-off-by: Arend van Spriel Acked-by: Hauke Mehrtens > --- > Fixing a Kconfig issue in our nightly Jenkins build. > > Gr. AvS Thanks for spotting and fixing this. This should also go into 3.8. This was a missing piece of a fix by Geert Uytterhoeven for an other bug in Kconfig of bcma and ssb: https://lkml.org/lkml/2012/12/16/68 https://lkml.org/lkml/2012/12/16/69 Hauke From jchandra@broadcom.com Fri Jan 4 20:50:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jan 2013 20:50:33 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:1676 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823011Ab3ADTubaT1P0 (ORCPT ); Fri, 4 Jan 2013 20:50:31 +0100 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 04 Jan 2013 11:47:13 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 4 Jan 2013 11:50:02 -0800 Received: from jayachandranc.netlogicmicro.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 0FE4B40FF1; Fri, 4 Jan 2013 11:50:04 -0800 (PST) Date: Sat, 5 Jan 2013 01:21:58 +0530 From: "Jayachandran C." To: "Hill, Steven" cc: "David Daney" , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: Re: [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. Message-ID: <20130104195157.GA2140@jayachandranc.netlogicmicro.com> References: <1357322355-31622-1-git-send-email-sjhill@mips.com> <50E71BF8.3050308@gmail.com> <31E06A9FC96CEC488B43B19E2957C1B801146AF100@exchdb03.mips.com> MIME-Version: 1.0 In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B801146AF100@exchdb03.mips.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-WSS-ID: 7CF9EE4B3Q4705309-01-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit X-archive-position: 35377 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1303 Lines: 29 On Fri, Jan 04, 2013 at 06:24:54PM +0000, Hill, Steven wrote: > >> +#ifdef CONFIG_64BIT > >> + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1)); > >> +#else > >> + (PGDIR_SHIFT - PAGE_SHIFT - 1)); > >> +#endif > >> + UASM_i_INS(p, ptr, tmp, (PTE_T_LOG2 + 1), > > > > As far as I can tell, (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1) and > > (PGDIR_SHIFT - PAGE_SHIFT - 1) are the same thing. So why the two cases? > > > >Can you give an example of where they might differ? > > > David, > > Actually, no I cannot. The calculation was given to me by 'jchandra' and since I do not have 64-bit R2 hardware let alone the Broadcom platform, he said it worked on his platform and I took it from him as is. So does this patch work on Cavium platforms using both calculation methods? It would be nice if 'jchandra' could chime in, but he may be on holiday or something. This does not really need hardware. On 64bit, with 16k page, the expansion of the macro is (from tlbex.i): uasm_i_dext(p, tmp, tmp, 14 +1, ((14 + (14 + 0 - 3)) + (14 + 0 - 3))-14 -1); This evaluates to 21, which is obviously wrong (should be 10). I had sent the generated tlb handler which showed the incorrect size to sjhill, but that probably got lost in the new year holiday mails. JC. From linux@arm.linux.org.uk Sat Jan 5 11:42:32 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Jan 2013 11:42:33 +0100 (CET) Received: from caramon.arm.linux.org.uk ([78.32.30.218]:47071 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817419Ab3AEKmcNhF-v (ORCPT ); Sat, 5 Jan 2013 11:42:32 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=caramon; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=jbSseclF9gdDoy8T9I67kyHqUdPYmyudsA98UVl52Tc=; b=cy2cx5ne6AL1+JSmLXYwQxU8ety66/XHcxRZQVaIMS/wMeYSHFyItZmgPwNQBo3xzXF8ZPsgrZsPSk10Hpqnjz9NwJVANtAAbELYAvfA2/glvajaDy5bYkZW2ECvpg11KI/TjgWnzaVvDiwG6+peihdJ9MFzL31XTT1Gn2Us00g=; Received: from n2100.arm.linux.org.uk ([2002:4e20:1eda:1:214:fdff:fe10:4f86]:36638) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1TrR77-0005SY-D3; Sat, 05 Jan 2013 10:36:29 +0000 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1TrR76-0000Qo-0m; Sat, 05 Jan 2013 10:36:28 +0000 Date: Sat, 5 Jan 2013 10:36:27 +0000 From: Russell King - ARM Linux To: Srivatsa Vaddagiri Cc: "Paul E. McKenney" , Stephen Boyd , linux-arm-kernel@lists.infradead.org, Mike Frysinger , uclinux-dist-devel@blackfin.uclinux.org, Ralf Baechle , linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , linux-s390@vger.kernel.org, Paul Mundt , linux-sh@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, mhocko@suse.cz, srivatsa.bhat@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH 1/2] cpuhotplug/nohz: Remove offline cpus from nohz-idle state Message-ID: <20130105103627.GU2631@n2100.arm.linux.org.uk> References: <1357268318-7993-1-git-send-email-vatsa@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1357268318-7993-1-git-send-email-vatsa@codeaurora.org> User-Agent: Mutt/1.5.19 (2009-01-05) X-archive-position: 35378 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux@arm.linux.org.uk Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 837 Lines: 16 On Thu, Jan 03, 2013 at 06:58:38PM -0800, Srivatsa Vaddagiri wrote: > I also think that the > wait_for_completion() based wait in ARM's __cpu_die() can be replaced with a > busy-loop based one, as the wait there in general should be terminated within > few cycles. Why open-code this stuff when we have infrastructure already in the kernel for waiting for stuff to happen? I chose to use the standard infrastructure because its better tested, and avoids having to think about whether we need CPU barriers and such like to ensure that updates are seen in a timely manner. My stance on a lot of this idle/cpu dying code is that much of it can probably be cleaned up and merged into a single common implementation - in which case the use of standard infrastructure for things like waiting for other CPUs do stuff is even more justified. From sshtylyov@mvista.com Sat Jan 5 12:33:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Jan 2013 12:33:24 +0100 (CET) Received: from mail-la0-f52.google.com ([209.85.215.52]:40794 "EHLO mail-la0-f52.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817387Ab3AELdXS0siT (ORCPT ); Sat, 5 Jan 2013 12:33:23 +0100 Received: by mail-la0-f52.google.com with SMTP id fq12so11304854lab.11 for ; Sat, 05 Jan 2013 03:33:17 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=9yJkSsmemYzbFv4p5d02ccZaO+1fsx1wgGqAaOpmCpM=; b=Ips29w5dz6cjMdmX5qSKw/ggs6zgS59iMCvNB49mZCKc2PPEotLAaIT0w5rYJrNyLt /Dfkh3wxK03lrdryc3+qKvWiYq1Hl1l1ghZIsmZZ1s7iGd6o/dktUHOFN+0Ou9CjxHWD khQ6tqvDHzHwN2FFX7fCPCjlo/MXSWZcp2Kyk4IhkvkcDnt0x/KE1uAAWpt6fV3fZXwJ HpSzK+b3dM878DrF84pkOzKlRMh7XkAREs9dx8j5v5vGKI8an8UPoMrfMSzBdpa+UAMk fTZUHF8BmV35nPMQdefoDpZCnxIbm4yFI3G8ScZblEUHwMl9p7+T2zKq9+t/kwcGSSAn n4sg== X-Received: by 10.112.28.9 with SMTP id x9mr22385612lbg.27.1357385597645; Sat, 05 Jan 2013 03:33:17 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-72-139.pppoe.mtu-net.ru. [91.79.72.139]) by mx.google.com with ESMTPS id sv4sm1769491lab.0.2013.01.05.03.33.14 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 05 Jan 2013 03:33:15 -0800 (PST) Message-ID: <50E80F78.9030901@mvista.com> Date: Sat, 05 Jan 2013 15:33:12 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Arend van Spriel CC: Ralf Baechle , linux-mips@linux-mips.org, Hauke Mehrtens Subject: Re: [PATCH] mips: bcm47xx: select GPIOLIB for BCMA on bcm47xx platform References: <1357323005-28008-1-git-send-email-arend@broadcom.com> In-Reply-To: <1357323005-28008-1-git-send-email-arend@broadcom.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQk9OuSIs4Gl7w597LsASKqhNMsUV3QSJQJH/pmka44i7iRmeJxokpFLaNCvRkqOGDyTG+3n X-archive-position: 35379 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1314 Lines: 42 Hello. On 04-01-2013 22:10, Arend van Spriel wrote: > The Kconfig items BCM47XX_BCMA and BCM47XX_SSB selected > respectively BCMA_DRIVER_GPIO and SSB_DRIVER_GPIO. These > options depend on GPIOLIB without explicitly selecting it > so it results in a warning when GPIOLIB is not set: > scripts/kconfig/conf --oldconfig Kconfig > warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO ... unmet direct > dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) > warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO ... unmet direct > dependencies (SSB_POSSIBLE && SSB && GPIOLIB) > which subsequently results in compile errors. > Cc: Hauke Mehrtens > Signed-off-by: Arend van Spriel > --- > Fixing a Kconfig issue in our nightly Jenkins build. > Gr. AvS > --- > arch/mips/bcm47xx/Kconfig | 3 +++ > 1 file changed, 3 insertions(+) > diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig > index d7af29f..ba61192 100644 > --- a/arch/mips/bcm47xx/Kconfig > +++ b/arch/mips/bcm47xx/Kconfig > @@ -8,8 +8,10 @@ config BCM47XX_SSB > select SSB_DRIVER_EXTIF > select SSB_EMBEDDED > select SSB_B43_PCI_BRIDGE if PCI > + select SSB_DRIVER_PCICORE if PCI This change doesn';t seem to be documented in your changelog. Maybe it's worth another patch? WBR, Sergei From florian@openwrt.org Sat Jan 5 13:49:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Jan 2013 13:49:45 +0100 (CET) Received: from mail-wg0-f49.google.com ([74.125.82.49]:49784 "EHLO mail-wg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816671Ab3AEMtolLRsu (ORCPT ); Sat, 5 Jan 2013 13:49:44 +0100 Received: by mail-wg0-f49.google.com with SMTP id 15so7962565wgd.28 for ; Sat, 05 Jan 2013 04:49:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=DXshXF46SqE7eUI5iGfj9egc/93oOpJwlfULEQcDr/A=; b=cuz1LuCgs+CVpa9dPmFGi6ExaDZuWaoh8iBB+ac5KIghw1JH77FHV4eC696W3mys2b XJXeTNOM+alAp4pA3Nei6XhuUgrQD2T8TziLuMPyy39APOOGBTyFU7Ya/S0kywaLj2xr khpNYXXPzFeqlyQOzOtawp9EKNrMvjayr+gLWSi/pfbINMnUHmAmjnBE+EbC7o/SjqpE bnoUtl+Dw9NLVQWksNM0mA5d2anRGi0ExDP8A+jlcAYCQbT1dUlohtqcAY8CX0Y+UbbB kCBNppglbymyRhqgLNKGbw/wtlxii3TpvUxO0+p507F1+wRZhTsl14zeDk1sZIR6XTaj r9dQ== X-Received: by 10.194.76.165 with SMTP id l5mr87953451wjw.14.1357390179132; Sat, 05 Jan 2013 04:49:39 -0800 (PST) Received: from bender.localnet ([2a01:e35:2f70:4010:a1f8:aa2f:bb07:776a]) by mx.google.com with ESMTPS id t17sm3539655wiv.6.2013.01.05.04.49.38 (version=SSLv3 cipher=OTHER); Sat, 05 Jan 2013 04:49:38 -0800 (PST) From: Florian Fainelli To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: Re: [PATCH v3] MIPS: dsp: Add assembler support for DSP ASEs. Date: Sat, 05 Jan 2013 13:49:35 +0100 Message-ID: <28281784.2mN2Dnoq8K@bender> Organization: OpenWrt User-Agent: KMail/4.9.3 (Linux/3.5.0-21-generic; KDE/4.9.3; x86_64; ; ) In-Reply-To: <1357243312-23070-1-git-send-email-sjhill@mips.com> References: <1357243312-23070-1-git-send-email-sjhill@mips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="utf-8" X-archive-position: 35380 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 438 Lines: 14 On Thursday 03 January 2013 14:01:52 Steven J. Hill wrote: > From: "Steven J. Hill" > > Newer toolchains support the DSP and DSP Rev2 instructions. This patch > performs a check for that support and adds compiler and assembler > flags for only the files that need use those instructions. > > Signed-off-by: Steven J. Hill Acked-by: Florian Fainelli Thanks Steven! -- Florian From mcdonald.shane@gmail.com Sun Jan 6 15:49:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 Jan 2013 15:49:16 +0100 (CET) Received: from mail-la0-f51.google.com ([209.85.215.51]:43182 "EHLO mail-la0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817128Ab3AFOtOLzNMm (ORCPT ); Sun, 6 Jan 2013 15:49:14 +0100 Received: by mail-la0-f51.google.com with SMTP id fj20so13274511lab.38 for ; Sun, 06 Jan 2013 06:49:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=qtkM/7er6/jOUoSNAyiuydlapo7HxifrkeqNP6joOwE=; b=zN+2/23SVZpeihnp1eTtv89TYtEmewXnARDpDNrmf08+gqYBj2b99srtCn+Igw4sJi zHhJD2lR64E+jPaWkGJRIwLSVERSxMcUhq8/NjBnr3aBQXRSYw0b6yn36DPSq7A3SgRa ThJV9RG1w0Wa1oNvSize2ztuQycNvz3nALWLrzZn7QHdY7QfpiWVkE5IjNQXUxB5T6dZ wCmKLpOkYUb3LO0uLqnv7fpwCtHJYXVZgyJCLBVtIB4ACDno4cxgpU47MvyVenBd2bUe UtakdoG1qU/8Pjv+IuPO0y1XLcf1FVcGlsWFmTQ+KWtlK1DeURlLHnbT4tOJWjmF6zSD hJyQ== MIME-Version: 1.0 Received: by 10.152.144.38 with SMTP id sj6mr54560419lab.48.1357483748258; Sun, 06 Jan 2013 06:49:08 -0800 (PST) Received: by 10.112.114.37 with HTTP; Sun, 6 Jan 2013 06:49:07 -0800 (PST) In-Reply-To: <1357249701-2386-1-git-send-email-sjhill@mips.com> References: <1357249701-2386-1-git-send-email-sjhill@mips.com> Date: Sun, 6 Jan 2013 08:49:07 -0600 Message-ID: Subject: Re: [PATCH v2] MIPS: Add option to disable software I/O coherency. From: Shane McDonald To: "Steven J. Hill" Cc: linux-mips , Ralf Baechle Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35381 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13525 Lines: 351 Hi Steven: On Thu, Jan 3, 2013 at 3:48 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Some MIPS controllers have hardware I/O coherency. This patch > detects those and turns off software coherency. A new kernel > command line option also allows the user to manually turn > software coherency on or off. > > Signed-off-by: Steven J. Hill I have tested this patch on my RM7035C-based system on l-m.o's 3.8-rc2 kernel. My configuration files sets CONFIG_DMA_NONCOHERENT. Using my standard kernel command line, the kernel hangs while booting. I am able to get it to run normally by adding the new kernel parameter "nocoherentio" to the command line. I'm not that crazy that this patch requires me to change the way I normally boot my machine, and I suspect everyone with a CONFIG_DMA_NONCOHERENT configuration will have the same issue. I don't think that's too difficult to fix, though; see my comments in-line. Disclaimer: I'm far from an expert on the coherency issues, so take my comments with a grain of salt. > --- > arch/mips/include/asm/mach-generic/dma-coherence.h | 5 +- > arch/mips/mm/c-r4k.c | 37 +++++++--- > arch/mips/mm/dma-default.c | 6 +- > arch/mips/mti-malta/malta-setup.c | 71 ++++++++++++++++++++ > 4 files changed, 108 insertions(+), 11 deletions(-) > > diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h > index 9c95177..cd17f22 100644 > --- a/arch/mips/include/asm/mach-generic/dma-coherence.h > +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h > @@ -57,13 +57,16 @@ static inline int plat_dma_mapping_error(struct device *dev, > return 0; > } > > +extern int coherentio; > +extern int hw_coherentio; > + > static inline int plat_device_is_coherent(struct device *dev) > { > #ifdef CONFIG_DMA_COHERENT > return 1; > #endif > #ifdef CONFIG_DMA_NONCOHERENT > - return 0; > + return coherentio; > #endif > } Just thinking out loud here: if CONFIG_DMA_COHERENT is defined, we're always report the device as coherent; if CONFIG_DMA_NONCOHERENT is defined, we can override it with a command line parameter to report it's coherent. Is this something we want to do? If I understand correctly, in c-r4k.c, when we have this situation, we report that "this will break". Should we not just leave the old behaviour as-is? > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > index 606e828..bdb0ea7 100644 > --- a/arch/mips/mm/c-r4k.c > +++ b/arch/mips/mm/c-r4k.c > @@ -1379,19 +1379,37 @@ static void __cpuinit coherency_setup(void) > } > } > > -#if defined(CONFIG_DMA_NONCOHERENT) > - > -static int __cpuinitdata coherentio; > +int coherentio = -1; /* no DMA cache coherency (may be set by user) */ > +int hw_coherentio = 0; /* no HW DMA cache coherency (reflects real HW) */ Thank you for the comments on those lines -- just those two little snippets made the code so much easier for me to follow! Would it make sense to only allow the "coherentio" parameter to be set when CONFIG_DMA_NONCOHERENT is defined, and to only allow the "nocoherentio" parameter to be set when it's CONFIG_DMA_NONCOHERENT is not defined? Also, and this is my biggest concern in this whole patch, by setting coherentio to -1, you are requiring every platform to implement code to change this setting, as you've done with the Malta in the plat_setup_iocoherency() function. Would it be better to set it to 0 if CONFIG_DMA_NONCOHERENT is defined and to 1 if it's not defined? Platforms would still have the option of overriding this setting with their own (now optional) plat_setup_iocoherency() call. Otherwise, I believe this patch breaks every CONFIG_DMA_NONCOHERENT platform. I did test a modified patch on my platform where I set the initial value of coherentio to 0 here, and it worked fine -- no command line parameter changes required. > > static int __init setcoherentio(char *str) > { > - coherentio = 1; > + if (coherentio < 0) > + pr_info("Command line checking done before" > + " plat_setup_iocoherency!!\n"); Again, we're forcing every platform to add a plat_setup_iocoherency(). > + if (coherentio == 0) > + pr_info("Command line enabling coherentio" > + " (this will break...)!!\n"); If it will break (and my platform does), should we not just panic here? Or even better, not allow coherentio to be specified in this case? I'm probably wrong, though, because I believe the pre-patch code allows this to be set. > > + coherentio = 1; > + pr_info("Hardware DMA cache coherency (command line)\n"); > return 0; > } > - > early_param("coherentio", setcoherentio); > -#endif > + > +static int __init setnocoherentio(char *str) > +{ > + if (coherentio < 0) > + pr_info("Command line checking done before" > + " plat_setup_iocoherency!!\n"); > + if (coherentio == 1) > + pr_info("Command line disabling coherentio\n"); > + > + coherentio = 0; > + pr_info("Software DMA cache coherency (command line)\n"); > + return 0; > +} > +early_param("nocoherentio", setnocoherentio); Same comments as for coherentio -- does it make sense to allow this when CONFIG_DMA_NONCOHERENT is defined? And, any platform that doesn't define their own plat_setup_iocoherency() will get an info message. If you're adding a new kernel parameter, I'd really like to see it documented in Documentation/kernel-parameters.txt. I know that there are lots of other ones that aren't documented, including both coherentio and cca that are handled in this file, but we might as well do the right thing. The next few code changes are way beyond my level of knowledge, so I would have no rationale comments -- if this is doing what you want, I'm assuming it's good. I didn't notice any averse behaviour on my system. > > static void __cpuinit r4k_cache_error_setup(void) > { > @@ -1415,6 +1433,7 @@ void __cpuinit r4k_cache_init(void) > { > extern void build_clear_page(void); > extern void build_copy_page(void); > + extern int coherentio; > struct cpuinfo_mips *c = ¤t_cpu_data; > > probe_pcache(); > @@ -1474,9 +1493,11 @@ void __cpuinit r4k_cache_init(void) > > build_clear_page(); > build_copy_page(); > -#if !defined(CONFIG_MIPS_CMP) > + > + /* We want to run CMP kernels on core(s) with and without coherent caches */ > + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ > local_r4k___flush_cache_all(NULL); > -#endif > + > coherency_setup(); > board_cache_error_setup = r4k_cache_error_setup; > } > diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c > index 3fab204..aad5f7e 100644 > --- a/arch/mips/mm/dma-default.c > +++ b/arch/mips/mm/dma-default.c > @@ -115,7 +115,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, > > if (!plat_device_is_coherent(dev)) { > dma_cache_wback_inv((unsigned long) ret, size); > - ret = UNCAC_ADDR(ret); > + if (!hw_coherentio) > + ret = UNCAC_ADDR(ret); > } > } > > @@ -143,7 +144,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, > plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); > > if (!plat_device_is_coherent(dev)) > - addr = CAC_ADDR(addr); > + if (!hw_coherentio) > + addr = CAC_ADDR(addr); > > free_pages(addr, get_order(size)); > } > diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c > index ed68073..4187102 100644 > --- a/arch/mips/mti-malta/malta-setup.c > +++ b/arch/mips/mti-malta/malta-setup.c > @@ -31,6 +31,7 @@ > #include > #include > #include > +#include > #ifdef CONFIG_VT > #include > #endif > @@ -104,6 +105,74 @@ static void __init fd_activate(void) > } > #endif > > +static int __init > +plat_enable_iocoherency(void) I found this function name confusing -- does this enable iocoherency, or is it just checking to see if the HW supports iocoherency? Perhaps a better name might be something like "plat_is_iocoherency_supported", although I don't like that name either. > +{ > + int supported = 0; > + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { > + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { > + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; > + pr_info("Enabled Bonito CPU coherency\n"); > + supported = 1; > + } > + if (strstr(fw_getcmdline(), "iobcuncached")) { > + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; > + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & > + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | > + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); > + pr_info("Disabled Bonito IOBC coherency\n"); > + } else { > + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; > + BONITO_PCIMEMBASECFG |= > + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | > + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); > + pr_info("Enabled Bonito IOBC coherency\n"); > + } > + } else if (gcmp_niocu() != 0) { > + /* Nothing special needs to be done to enable coherency */ > + pr_info("CMP IOCU detected\n"); > + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { Do you have any #define's for these? I found the BONITO_* defines above to be quite easy to follow; can the same be done for these numbers? > + pr_crit("IOCU OPERATION DISABLED BY SWITCH" > + " - DEFAULTING TO SW IO COHERENCY\n"); > + return 0; Oh, an early return in a non-error case; I don't like that. Can't you just set supported to 0 in this case, and put the following "supported = 1;" in an else, and let things fall through as normal? But maybe that messes up your value of hw_coherentio, although if I understand correctly, setting that switch at bf403000 essentially turns off hw io concurrency support? > + } > + supported = 1; > + } > + hw_coherentio = supported; > + return supported; > +} > + > +static void __init > +plat_setup_iocoherency(void) > +{ > +#ifdef CONFIG_DMA_NONCOHERENT > + /* > + * Kernel has been configured with software coherency > + * but we might choose to turn it off > + */ > + if (plat_enable_iocoherency()) { I'm a little confused -- does this situation ever come up? You've got a kernel configured that says hardware DMA cache coherency is not supported (CONFIG_DMA_NONCOHERENT is defined), but the hardware does support it, but then you're turning it off on the command line? Would it not just be easier to configure the kernel differently? Of course, if you're going to run the same kernel on both coherent and non-coherent hardware, I guess you've got no choice. > + if (coherentio == 0) > + pr_info("Hardware DMA cache coherency supported" > + " but disabled from command line\n"); > + else { > + coherentio = 1; > + printk(KERN_INFO "Hardware DMA cache coherency\n"); pr_info? > + } > + } else { > + if (coherentio == 1) > + pr_info("Hardware DMA cache coherency not supported" > + " but enabled from command line\n"); If this is the case, would you want to panic() instead, like what you've done later when the kernel is configured for hardware coherency support but the platform doesn't support it? > + else { > + coherentio = 0; > + pr_info("Software DMA cache coherency\n"); > + } > + } > +#else > + if (!plat_enable_iocoherency()) > + panic("Hardware DMA cache coherency not supported"); > +#endif This is the panic I've mentioned a couple times in my previous comments. > +} > + > #ifdef CONFIG_BLK_DEV_IDE > static void __init pci_clock_check(void) > { > @@ -205,6 +274,8 @@ void __init plat_mem_setup(void) > if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) > bonito_quirks_setup(); > > + plat_setup_iocoherency(); > + > #ifdef CONFIG_BLK_DEV_IDE > pci_clock_check(); > #endif > -- > 1.7.9.5 > You know, I'd almost suggest splitting this into two patches. The first patch could deal with the kernel parameters, assuming that you update it so that it doesn't break existing systems. The second patch could then add in the Malta code that does the plat_setup_iocoherency() and related calls. Shane From arend@broadcom.com Sun Jan 6 22:14:11 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 Jan 2013 22:14:15 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:2338 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816511Ab3AFVOLExitu (ORCPT ); Sun, 6 Jan 2013 22:14:11 +0100 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Sun, 06 Jan 2013 13:10:54 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Sun, 6 Jan 2013 13:13:45 -0800 Received: from [10.0.2.15] (unknown [10.177.252.159]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 0694340FE3; Sun, 6 Jan 2013 13:13:55 -0800 (PST) Message-ID: <50E9E914.9030900@broadcom.com> Date: Sun, 6 Jan 2013 22:13:56 +0100 From: "Arend van Spriel" User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Sergei Shtylyov" cc: "Ralf Baechle" , linux-mips@linux-mips.org, "Hauke Mehrtens" Subject: Re: [PATCH] mips: bcm47xx: select GPIOLIB for BCMA on bcm47xx platform References: <1357323005-28008-1-git-send-email-arend@broadcom.com> <50E80F78.9030901@mvista.com> In-Reply-To: <50E80F78.9030901@mvista.com> X-Enigmail-Version: 1.4.6 X-WSS-ID: 7CF737D43Q41305152-01-01 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35382 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arend@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1642 Lines: 55 On 01/05/2013 12:33 PM, Sergei Shtylyov wrote: > Hello. > > On 04-01-2013 22:10, Arend van Spriel wrote: > >> The Kconfig items BCM47XX_BCMA and BCM47XX_SSB selected >> respectively BCMA_DRIVER_GPIO and SSB_DRIVER_GPIO. These >> options depend on GPIOLIB without explicitly selecting it >> so it results in a warning when GPIOLIB is not set: > >> scripts/kconfig/conf --oldconfig Kconfig >> warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO ... unmet direct >> dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) >> warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO ... unmet direct >> dependencies (SSB_POSSIBLE && SSB && GPIOLIB) > >> which subsequently results in compile errors. > >> Cc: Hauke Mehrtens >> Signed-off-by: Arend van Spriel >> --- >> Fixing a Kconfig issue in our nightly Jenkins build. > >> Gr. AvS >> --- >> arch/mips/bcm47xx/Kconfig | 3 +++ >> 1 file changed, 3 insertions(+) > >> diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig >> index d7af29f..ba61192 100644 >> --- a/arch/mips/bcm47xx/Kconfig >> +++ b/arch/mips/bcm47xx/Kconfig >> @@ -8,8 +8,10 @@ config BCM47XX_SSB >> select SSB_DRIVER_EXTIF >> select SSB_EMBEDDED >> select SSB_B43_PCI_BRIDGE if PCI >> + select SSB_DRIVER_PCICORE if PCI > > This change doesn';t seem to be documented in your changelog. Maybe > it's worth another patch? > > WBR, Sergei > Very observant. ;-) Yes. After fixing the other ones I got a warning on that one. I could resubmit the change with a more generic description or split it up as you suggest. Ralf, Please advice. Gr. AvS From jchandra@broadcom.com Mon Jan 7 15:19:22 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jan 2013 15:19:24 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:3101 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817419Ab3AGOTWKTzBC (ORCPT ); Mon, 7 Jan 2013 15:19:22 +0100 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 07 Jan 2013 06:16:01 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Mon, 7 Jan 2013 06:18:52 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 21BAB40FE4; Mon, 7 Jan 2013 06:19:02 -0800 (PST) From: "Jayachandran C" To: ralf@linux-mips.org cc: "Jayachandran C" , linux-mips@linux-mips.org Subject: [PATCH] MIPS: Netlogic: Fix UP compilation on XLR Date: Mon, 7 Jan 2013 19:51:08 +0530 Message-ID: <1357568468-1876-1-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-WSS-ID: 7CF4072B3Q41524953-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35383 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 987 Lines: 34 The commit 2a37b1a "MIPS: Netlogic: Move from u32 cpumask to cpumask_t" breaks uniprocessor compilation on XLR with: arch/mips/netlogic/xlr/setup.c: In function 'prom_init': arch/mips/netlogic/xlr/setup.c:196:6: error: unused variable 'i' Fix by defining 'i' only when CONFIG_SMP is defined. Signed-off-by: Jayachandran C --- arch/mips/netlogic/xlr/setup.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index 4e7f49d..c5ce699 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -193,8 +193,11 @@ static void nlm_init_node(void) void __init prom_init(void) { - int i, *argv, *envp; /* passed as 32 bit ptrs */ + int *argv, *envp; /* passed as 32 bit ptrs */ struct psb_info *prom_infop; +#ifdef CONFIG_SMP + int i; +#endif /* truncate to 32 bit and sign extend all args */ argv = (int *)(long)(int)fw_arg1; -- 1.7.9.5 From dczhu@mips.com Mon Jan 7 19:05:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jan 2013 19:05:46 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:44297 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822501Ab3AGSFoZU4Kw (ORCPT ); Mon, 7 Jan 2013 19:05:44 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r07I5ZEm030372; Mon, 7 Jan 2013 10:05:36 -0800 X-WSS-ID: 0MG9OXB-01-2WE-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 21FA236464E; Mon, 7 Jan 2013 10:05:35 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.2.247.3; Mon, 7 Jan 2013 10:05:32 -0800 From: Deng-Cheng Zhu To: , , , , CC: , Subject: [RESEND PATCH v3 0/5] MIPS: enable APRP (APSP) and add features - v3 Date: Mon, 7 Jan 2013 10:05:09 -0800 Message-ID: <1357581914-4589-1-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: 68sWoQjeMm1eouQeJOhD4w== X-archive-position: 35384 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2627 Lines: 56 The APRP model makes it possible that one or more CPUs run the Linux kernel whereas a dedicated CPU runs special real-time or signal processing program. This patchset adds the following to the current APRP support: 1. Several bug fixes; 2. Running floating point heavy jobs on the RP side; 3. Waking up RP side read by interrupt; 4. CPS multicore APRP support. A mp3 player program was ported to run in the APRP (APSP exactly) model. Considerable performance benefits were observed on the player program. CodeSourcery tools instead of the old SDE tools were used to build the example. Changes: v3 - v2: o Split CMP/MT flavors into different files -cmp/-mt. o Put Malta needed changes into a separate patch. o Code style adjustments in rtlx/vpe files. o Remove kspd.h which might have been left out in Ralf's kspd removal. v2 - v1: o Rebase the patches to the latest kernel, and fix a bunch of warnings and errors reported by the current scripts/checkpatch.pl. o Add MIPS_MALTA dependency to Kconfig since modifications of Malta files are needed. But it should be easy to port changes to other platforms. Deng-Cheng Zhu (5): MIPS: APRP (APSP): fix/enrich functionality MIPS: APRP (APSP): split vpe-loader and rtlx into cmp/mt flavors MIPS: APRP (APSP): remove kspd.h MIPS: let amon_cpu_start() report results MIPS: APRP (APSP): malta board support arch/mips/Kconfig | 9 + arch/mips/include/asm/amon.h | 2 +- arch/mips/include/asm/kspd.h | 32 - .../include/asm/mach-malta/cpu-feature-overrides.h | 3 + arch/mips/include/asm/rtlx.h | 45 +- arch/mips/include/asm/vpe.h | 118 +++- arch/mips/kernel/Makefile | 9 +- arch/mips/kernel/rtlx-cmp.c | 125 +++ arch/mips/kernel/rtlx-mt.c | 160 ++++ arch/mips/kernel/rtlx.c | 205 +---- arch/mips/kernel/vpe-cmp.c | 202 +++++ arch/mips/kernel/vpe-mt.c | 534 +++++++++++++ arch/mips/kernel/vpe.c | 815 +++----------------- arch/mips/mti-malta/malta-amon.c | 8 +- arch/mips/mti-malta/malta-int.c | 22 +- 15 files changed, 1351 insertions(+), 938 deletions(-) delete mode 100644 arch/mips/include/asm/kspd.h create mode 100644 arch/mips/kernel/rtlx-cmp.c create mode 100644 arch/mips/kernel/rtlx-mt.c create mode 100644 arch/mips/kernel/vpe-cmp.c create mode 100644 arch/mips/kernel/vpe-mt.c From dczhu@mips.com Mon Jan 7 19:05:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jan 2013 19:06:09 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:44299 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823008Ab3AGSFsHnyGq (ORCPT ); Mon, 7 Jan 2013 19:05:48 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r07I5e0B030379; Mon, 7 Jan 2013 10:05:40 -0800 X-WSS-ID: 0MG9OXG-01-2WF-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 23DCC36464E; Mon, 7 Jan 2013 10:05:40 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.2.247.3; Mon, 7 Jan 2013 10:05:36 -0800 From: Deng-Cheng Zhu To: , , , , CC: , Subject: [RESEND PATCH v3 1/5] MIPS: APRP (APSP): fix/enrich functionality Date: Mon, 7 Jan 2013 10:05:10 -0800 Message-ID: <1357581914-4589-2-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1357581914-4589-1-git-send-email-dczhu@mips.com> References: <1357581914-4589-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: hFvekXq9FRgFo1yTJguSrw== X-archive-position: 35385 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 29324 Lines: 1041 This patch makes 34K and CPS like multicore 1004K APRP (also known as APSP) work. Also, it allows the RP side to run floating point heavy jobs and uses interrupt to wake up RP side read. These functionalities need proper RP code to work correctly. To run programs in APRP (APSP) mode on CPS, for example, a 3 core 1004K CPU, one can run SMVP Linux on the first 2 cores and leave a VPE of the 3rd core to run RTOS or signal processing program. The kernel command line option "maxcpus=" needs to be appointed. To run FP intensive RP/SP side program on a Kf CPU, currently we simply disable the FPU on the AP side. And RP will init it and use it exclusively. Cc: Steven J. Hill Signed-off-by: Deng-Cheng Zhu --- arch/mips/Kconfig | 9 ++ arch/mips/include/asm/rtlx.h | 5 + arch/mips/kernel/rtlx.c | 190 +++++++++++++++++++++----- arch/mips/kernel/vpe.c | 302 ++++++++++++++++++++++++++++++------------ 4 files changed, 381 insertions(+), 125 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index dba9390..f4d4888 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2036,6 +2036,15 @@ config MIPS_VPE_LOADER_TOM you to ensure the amount you put in the option and the space your program requires is less or equal to the amount physically present. +config MIPS_SP_FP_INTENSIVE + bool "SP is used for running FP-intensive jobs" + depends on MIPS_VPE_LOADER + ---help--- + If you intend to use the SP to run FP-intensive jobs, you probably + want to say yes here. Your FPU will then be exclusively used by the + SP, and the Linux on the AP side will not see the FPU. Make sure you + know what it does when choosing this option. + # this should possibly be in drivers/char, but it is rather cpu related. Hmmm config MIPS_VPE_APSP_API bool "Enable support for AP/SP API (RTLX)" diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h index 4ca3063..478349e 100644 --- a/arch/mips/include/asm/rtlx.h +++ b/arch/mips/include/asm/rtlx.h @@ -28,6 +28,8 @@ extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count); extern unsigned int rtlx_read_poll(int index, int can_sleep); extern unsigned int rtlx_write_poll(int index); +extern void (*aprp_hook)(void); + enum rtlx_state { RTLX_STATE_UNUSED = 0, RTLX_STATE_INITIALISED, @@ -58,6 +60,9 @@ struct rtlx_channel { struct rtlx_info { unsigned long id; enum rtlx_state state; +#ifdef CONFIG_MIPS_CMP + int ap_int_pending; +#endif struct rtlx_channel channel[RTLX_CHANNELS]; }; diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index b8c18dc..eeda8a2 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2005, 2012 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2005, 06 Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can distribute it and/or modify it @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -54,15 +55,40 @@ static struct chan_waitqueues { static struct vpe_notifications notify; static int sp_stopping; +static int cpu_idx; +static void null_aprp_hook(void) {}; + +void (*aprp_hook)(void) = null_aprp_hook; extern void *vpe_get_shared(int index); +#ifdef CONFIG_MIPS_CMP +static void rtlx_interrupt(void) +{ + int i; + struct rtlx_info *info; + struct rtlx_info **p = vpe_get_shared(cpu_idx); + + if (p == NULL || *p == NULL) + return; + + info = *p; + + if (info->ap_int_pending == 1 && smp_processor_id() == 0) { + for (i = 0; i < RTLX_CHANNELS; i++) { + wake_up(&channel_wqs[i].lx_queue); + wake_up(&channel_wqs[i].rt_queue); + } + info->ap_int_pending = 0; + } +} +#else static void rtlx_dispatch(void) { - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); + if (read_c0_cause() & read_c0_status() & C_SW0) + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); } - /* Interrupt handler may be called before rtlx_init has otherwise had a chance to run. */ @@ -81,12 +107,13 @@ static irqreturn_t rtlx_interrupt(int irq, void *dev_id) local_irq_restore(flags); for (i = 0; i < RTLX_CHANNELS; i++) { - wake_up(&channel_wqs[i].lx_queue); - wake_up(&channel_wqs[i].rt_queue); + wake_up(&channel_wqs[i].lx_queue); + wake_up(&channel_wqs[i].rt_queue); } return IRQ_HANDLED; } +#endif static void __used dump_rtlx(void) { @@ -115,8 +142,7 @@ static void __used dump_rtlx(void) static int rtlx_init(struct rtlx_info *rtlxi) { if (rtlxi->id != RTLX_ID) { - printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n", - rtlxi, rtlxi->id); + pr_err("no valid RTLX id at 0x%p 0x%lx\n", rtlxi, rtlxi->id); return -ENOEXEC; } @@ -157,30 +183,30 @@ int rtlx_open(int index, int can_sleep) int ret = 0; if (index >= RTLX_CHANNELS) { - printk(KERN_DEBUG "rtlx_open index out of range\n"); + pr_debug("rtlx_open index out of range\n"); return -ENOSYS; } if (atomic_inc_return(&channel_wqs[index].in_open) > 1) { - printk(KERN_DEBUG "rtlx_open channel %d already opened\n", - index); + pr_debug("rtlx_open channel %d already opened\n", index); ret = -EBUSY; goto out_fail; } if (rtlx == NULL) { - if( (p = vpe_get_shared(tclimit)) == NULL) { - if (can_sleep) { - __wait_event_interruptible(channel_wqs[index].lx_queue, - (p = vpe_get_shared(tclimit)), ret); - if (ret) + p = vpe_get_shared(cpu_idx); + if (p == NULL) { + if (can_sleep) { + __wait_event_interruptible( + channel_wqs[index].lx_queue, + (p = vpe_get_shared(cpu_idx)), ret); + if (ret) + goto out_fail; + } else { + pr_debug("No SP program loaded, and device opened with O_NONBLOCK\n"); + ret = -ENOSYS; goto out_fail; - } else { - printk(KERN_DEBUG "No SP program loaded, and device " - "opened with O_NONBLOCK\n"); - ret = -ENOSYS; - goto out_fail; - } + } } smp_rmb(); @@ -204,16 +230,14 @@ int rtlx_open(int index, int can_sleep) } finish_wait(&channel_wqs[index].lx_queue, &wait); } else { - pr_err(" *vpe_get_shared is NULL. " - "Has an SP program been loaded?\n"); + pr_err(" *vpe_get_shared is NULL. Has an SP program been loaded?\n"); ret = -ENOSYS; goto out_fail; } } if ((unsigned int)*p < KSEG0) { - printk(KERN_WARNING "vpe_get_shared returned an " - "invalid pointer maybe an error code %d\n", + pr_warn("vpe_get_shared returned an invalid pointer maybe an error code %d\n", (int)*p); ret = -ENOSYS; goto out_fail; @@ -343,6 +367,25 @@ out: return count; } +#ifdef CONFIG_MIPS_CMP +static void _interrupt_sp(void) +{ + smp_send_reschedule(cpu_idx); +} +#else +static void _interrupt_sp(void) +{ + unsigned long flags; + + local_irq_save(flags); + dvpe(); + settc(1); + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); + evpe(EVPE_ENABLE); + local_irq_restore(flags); +} +#endif + ssize_t rtlx_write(int index, const void __user *buffer, size_t count) { struct rtlx_channel *rt; @@ -383,6 +426,8 @@ out: smp_wmb(); mutex_unlock(&channel_wqs[index].mutex); + _interrupt_sp(); + return count; } @@ -470,6 +515,72 @@ static const struct file_operations rtlx_fops = { .llseek = noop_llseek, }; +static char register_chrdev_failed[] __initdata = + KERN_ERR "rtlx_module_init: unable to register device\n"; + +#ifdef CONFIG_MIPS_CMP +static int __init rtlx_module_init(void) +{ + struct device *dev; + int i, err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + cpu_idx = setup_max_cpus; + + if (num_possible_cpus() - cpu_idx < 1) { + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" + "Pass maxcpus= argument as kernel argument\n"); + + return -ENODEV; + } + + major = register_chrdev(0, module_name, &rtlx_fops); + if (major < 0) { + printk(register_chrdev_failed); + return major; + } + + /* initialise the wait queues */ + for (i = 0; i < RTLX_CHANNELS; i++) { + init_waitqueue_head(&channel_wqs[i].rt_queue); + init_waitqueue_head(&channel_wqs[i].lx_queue); + atomic_set(&channel_wqs[i].in_open, 0); + mutex_init(&channel_wqs[i].mutex); + + dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, + "%s%d", module_name, i); + if (IS_ERR(dev)) { + err = PTR_ERR(dev); + goto out_chrdev; + } + } + + /* set up notifiers */ + notify.start = starting; + notify.stop = stopping; + vpe_notify(cpu_idx, ¬ify); + + if (cpu_has_vint) { + aprp_hook = rtlx_interrupt; + } else { + pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); + err = -ENODEV; + goto out_chrdev; + } + + return 0; + +out_chrdev: + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + return err; +} +#else static struct irqaction rtlx_irq = { .handler = rtlx_interrupt, .name = "RTLX", @@ -477,23 +588,21 @@ static struct irqaction rtlx_irq = { static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; -static char register_chrdev_failed[] __initdata = - KERN_ERR "rtlx_module_init: unable to register device\n"; - static int __init rtlx_module_init(void) { struct device *dev; int i, err; if (!cpu_has_mipsmt) { - printk("VPE loader: not a MIPS MT capable processor\n"); + pr_warn("VPE loader: not a MIPS MT capable processor\n"); return -ENODEV; } - if (tclimit == 0) { - printk(KERN_WARNING "No TCs reserved for AP/SP, not " - "initializing RTLX.\nPass maxtcs= argument as kernel " - "argument\n"); + cpu_idx = tclimit; + + if (cpu_idx == 0) { + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" + "Pass maxtcs= argument as kernel argument\n"); return -ENODEV; } @@ -522,11 +631,16 @@ static int __init rtlx_module_init(void) /* set up notifiers */ notify.start = starting; notify.stop = stopping; - vpe_notify(tclimit, ¬ify); + vpe_notify(cpu_idx, ¬ify); - if (cpu_has_vint) - set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); - else { + if (cpu_has_vint) { + /* + * set_vi_handler() doesn't work in some cases: When sw0 + * gets set, a hw interrupt is signaled as well. Here we + * are hooking it into platform specific dispatch. + */ + aprp_hook = rtlx_dispatch; + } else { pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); err = -ENODEV; goto out_chrdev; @@ -543,6 +657,7 @@ out_chrdev: return err; } +#endif static void __exit rtlx_module_exit(void) { @@ -552,6 +667,7 @@ static void __exit rtlx_module_exit(void) device_destroy(mt_class, MKDEV(major, i)); unregister_chrdev(major, module_name); + aprp_hook = null_aprp_hook; } module_init(rtlx_module_init); diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index eec690a..a558bbe 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2004, 2005, 2012 MIPS Technologies, Inc. All rights reserved. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -63,6 +63,7 @@ typedef void *vpe_handle; /* * The number of TCs and VPEs physically available on the core */ +static int cpu_idx; static int hw_tcs, hw_vpes; static char module_name[] = "vpe"; static int major; @@ -365,9 +366,8 @@ static int apply_r_mips_gprel16(struct module *me, uint32_t *location, } if( (rel > 32768) || (rel < -32768) ) { - printk(KERN_DEBUG "VPE loader: apply_r_mips_gprel16: " - "relative address 0x%x out of range of gp register\n", - rel); + pr_debug("VPE loader: apply_r_mips_gprel16: relative address 0x%x out of range of gp register\n", + rel); return -ENOEXEC; } @@ -381,12 +381,12 @@ static int apply_r_mips_pc16(struct module *me, uint32_t *location, { int rel; rel = (((unsigned int)v - (unsigned int)location)); - rel >>= 2; // because the offset is in _instructions_ not bytes. - rel -= 1; // and one instruction less due to the branch delay slot. + rel >>= 2; /* because the offset is in _instructions_ not bytes. */ + rel -= 1; /* and one instruction less due to the branch delay slot. */ if( (rel > 32768) || (rel < -32768) ) { - printk(KERN_DEBUG "VPE loader: " - "apply_r_mips_pc16: relative address out of range 0x%x\n", rel); + pr_debug("VPE loader: apply_r_mips_pc16: relative address out of range 0x%x\n", + rel); return -ENOEXEC; } @@ -407,8 +407,7 @@ static int apply_r_mips_26(struct module *me, uint32_t *location, Elf32_Addr v) { if (v % 4) { - printk(KERN_DEBUG "VPE loader: apply_r_mips_26 " - " unaligned relocation\n"); + pr_debug("VPE loader: apply_r_mips_26 unaligned relocation\n"); return -ENOEXEC; } @@ -471,9 +470,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, * The value for the HI16 had best be the same. */ if (v != l->value) { - printk(KERN_DEBUG "VPE loader: " - "apply_r_mips_lo16/hi16: \t" - "inconsistent value information\n"); + pr_debug("VPE loader: apply_r_mips_lo16/hi16: \tinconsistent value information\n"); goto out_free; } @@ -569,7 +566,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs, + ELF32_R_SYM(r_info); if (!sym->st_value) { - printk(KERN_DEBUG "%s: undefined weak symbol %s\n", + pr_debug("%s: undefined weak symbol %s\n", me->name, strtab + sym->st_name); /* just print the warning, dont barf */ } @@ -579,10 +576,9 @@ static int apply_relocations(Elf32_Shdr *sechdrs, res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); if( res ) { char *r = rstrs[ELF32_R_TYPE(r_info)]; - printk(KERN_WARNING "VPE loader: .text+0x%x " - "relocation type %s for symbol \"%s\" failed\n", - rel[i].r_offset, r ? r : "UNKNOWN", - strtab + sym->st_name); + pr_warn("VPE loader: .text+0x%x relocation type %s for symbol \"%s\" failed\n", + rel[i].r_offset, r ? r : "UNKNOWN", + strtab + sym->st_name); return res; } } @@ -641,10 +637,9 @@ static void simplify_symbols(Elf_Shdr * sechdrs, break; case SHN_MIPS_SCOMMON: - printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON " - "symbol <%s> st_shndx %d\n", strtab + sym[i].st_name, - sym[i].st_shndx); - // .sbss section + pr_debug("simplify_symbols: ignoring SHN_MIPS_SCOMMON symbol <%s> st_shndx %d\n", + strtab + sym[i].st_name, sym[i].st_shndx); + /* .sbss section */ break; default: @@ -667,14 +662,17 @@ static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex, Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); - printk(KERN_DEBUG "dump_elfsymbols: n %d\n", n); + pr_debug("dump_elfsymbols: n %d\n", n); for (i = 1; i < n; i++) { - printk(KERN_DEBUG " i %d name <%s> 0x%x\n", i, - strtab + sym[i].st_name, sym[i].st_value); + pr_debug(" i %d name <%s> 0x%x\n", i, strtab + sym[i].st_name, + sym[i].st_value); } } #endif +#ifdef CONFIG_MIPS_CMP +#error CMP vpe_run() not implemented! +#else /* We are prepared so configure and start the VPE... */ static int vpe_run(struct vpe * v) { @@ -687,8 +685,7 @@ static int vpe_run(struct vpe * v) local_irq_save(flags); val = read_c0_vpeconf0(); if (!(val & VPECONF0_MVP)) { - printk(KERN_WARNING - "VPE loader: only Master VPE's are allowed to configure MT\n"); + pr_warn("VPE loader: only Master VPE's are allowed to configure MT\n"); local_irq_restore(flags); return -1; @@ -703,9 +700,8 @@ static int vpe_run(struct vpe * v) emt(dmt_flag); local_irq_restore(flags); - printk(KERN_WARNING - "VPE loader: TC %d is already in use.\n", - t->index); + pr_warn("VPE loader: TC %d is already in use.\n", + t->index); return -ENOEXEC; } } else { @@ -713,9 +709,8 @@ static int vpe_run(struct vpe * v) emt(dmt_flag); local_irq_restore(flags); - printk(KERN_WARNING - "VPE loader: No TC's associated with VPE %d\n", - v->minor); + pr_warn("VPE loader: No TC's associated with VPE %d\n", + v->minor); return -ENOEXEC; } @@ -731,8 +726,7 @@ static int vpe_run(struct vpe * v) emt(dmt_flag); local_irq_restore(flags); - printk(KERN_WARNING "VPE loader: TC %d is already active!\n", - t->index); + pr_warn("VPE loader: TC %d is already active!\n", t->index); return -ENOEXEC; } @@ -804,6 +798,7 @@ static int vpe_run(struct vpe * v) return 0; } +#endif /* CONFIG_MIPS_CMP */ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, unsigned int symindex, const char *strtab, @@ -854,8 +849,7 @@ static int vpe_elfload(struct vpe * v) || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) || !elf_check_arch(hdr) || hdr->e_shentsize != sizeof(*sechdrs)) { - printk(KERN_WARNING - "VPE loader: program wrong arch or weird elf version\n"); + pr_warn("VPE loader: program wrong arch or weird elf version\n"); return -ENOEXEC; } @@ -864,8 +858,7 @@ static int vpe_elfload(struct vpe * v) relocate = 1; if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { - printk(KERN_ERR "VPE loader: program length %u truncated\n", - len); + pr_err("VPE loader: program length %u truncated\n", len); return -ENOEXEC; } @@ -882,7 +875,7 @@ static int vpe_elfload(struct vpe * v) for (i = 1; i < hdr->e_shnum; i++) { if (sechdrs[i].sh_type != SHT_NOBITS && len < sechdrs[i].sh_offset + sechdrs[i].sh_size) { - printk(KERN_ERR "VPE program length %u truncated\n", + pr_err("VPE program length %u truncated\n", len); return -ENOEXEC; } @@ -922,8 +915,9 @@ static int vpe_elfload(struct vpe * v) /* Update sh_addr to point to copy in image. */ sechdrs[i].sh_addr = (unsigned long)dest; - printk(KERN_DEBUG " section sh_name %s sh_addr 0x%x\n", - secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr); + pr_debug(" section sh_name %s sh_addr 0x%x\n", + secstrings + sechdrs[i].sh_name, + sechdrs[i].sh_addr); } /* Fix up syms, so that st_value is a pointer to location. */ @@ -987,21 +981,25 @@ static int vpe_elfload(struct vpe * v) if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { if (v->__start == 0) { - printk(KERN_WARNING "VPE loader: program does not contain " - "a __start symbol\n"); + pr_warn("VPE loader: program does not contain a __start symbol\n"); return -ENOEXEC; } if (v->shared_ptr == NULL) - printk(KERN_WARNING "VPE loader: " - "program does not contain vpe_shared symbol.\n" - " Unable to use AMVP (AP/SP) facilities.\n"); + pr_warn("VPE loader: program does not contain vpe_shared symbol.\n" + " Unable to use AMVP (AP/SP) facilities.\n"); } - printk(" elf loaded\n"); + pr_info(" elf loaded\n"); return 0; } +#ifdef CONFIG_MIPS_CMP +static void cleanup_tc(struct tc *tc) +{ + +} +#else static void cleanup_tc(struct tc *tc) { unsigned long flags; @@ -1033,6 +1031,7 @@ static void cleanup_tc(struct tc *tc) emt(mtflags); local_irq_restore(flags); } +#endif static int getcwd(char *buff, int size) { @@ -1064,7 +1063,8 @@ static int vpe_open(struct inode *inode, struct file *filp) return -ENODEV; } - if ((v = get_vpe(tclimit)) == NULL) { + v = get_vpe(cpu_idx); + if (v == NULL) { pr_warning("VPE loader: unable to get vpe\n"); return -ENODEV; @@ -1072,14 +1072,14 @@ static int vpe_open(struct inode *inode, struct file *filp) state = xchg(&v->state, VPE_STATE_INUSE); if (state != VPE_STATE_UNUSED) { - printk(KERN_DEBUG "VPE loader: tc in use dumping regs\n"); + pr_debug("VPE loader: tc in use dumping regs\n"); list_for_each_entry(not, &v->notify, list) { - not->stop(tclimit); + not->stop(cpu_idx); } release_progmem(v->load_addr); - cleanup_tc(get_tc(tclimit)); + cleanup_tc(get_tc(cpu_idx)); } /* this of-course trashes what was there before... */ @@ -1098,7 +1098,7 @@ static int vpe_open(struct inode *inode, struct file *filp) v->cwd[0] = 0; ret = getcwd(v->cwd, VPE_PATH_MAX); if (ret < 0) - printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret); + pr_warn("VPE loader: open, getcwd returned %d\n", ret); v->shared_ptr = NULL; v->__start = 0; @@ -1112,7 +1112,8 @@ static int vpe_release(struct inode *inode, struct file *filp) Elf_Ehdr *hdr; int ret = 0; - v = get_vpe(tclimit); + v = get_vpe(cpu_idx); + if (v == NULL) return -ENODEV; @@ -1121,11 +1122,11 @@ static int vpe_release(struct inode *inode, struct file *filp) if (vpe_elfload(v) >= 0) { vpe_run(v); } else { - printk(KERN_WARNING "VPE loader: ELF load failed.\n"); + pr_warn("VPE loader: ELF load failed.\n"); ret = -ENOEXEC; } } else { - printk(KERN_WARNING "VPE loader: only elf files are supported\n"); + pr_warn("VPE loader: only elf files are supported\n"); ret = -ENOEXEC; } @@ -1152,7 +1153,8 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, if (iminor(file->f_path.dentry->d_inode) != minor) return -ENODEV; - v = get_vpe(tclimit); + v = get_vpe(cpu_idx); + if (v == NULL) return -ENODEV; @@ -1178,6 +1180,7 @@ static const struct file_operations vpe_fops = { .llseek = noop_llseek, }; +#ifndef CONFIG_MIPS_CMP /* module wrapper entry points */ /* give me a vpe */ vpe_handle vpe_alloc(void) @@ -1265,6 +1268,7 @@ int vpe_free(vpe_handle vpe) } EXPORT_SYMBOL(vpe_free); +#endif /* CONFIG_MIPS_CMP */ void *vpe_get_shared(int index) { @@ -1327,18 +1331,62 @@ char *vpe_getcwd(int index) EXPORT_SYMBOL(vpe_getcwd); +#ifdef CONFIG_MIPS_CMP static ssize_t store_kill(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { - struct vpe *vpe = get_vpe(tclimit); + struct vpe *vpe = get_vpe(cpu_idx); struct vpe_notifications *not; list_for_each_entry(not, &vpe->notify, list) { - not->stop(tclimit); + not->stop(cpu_idx); } release_progmem(vpe->load_addr); - cleanup_tc(get_tc(tclimit)); + vpe->state = VPE_STATE_UNUSED; + + return len; +} + +static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, + char *buf) +{ + struct vpe *vpe = get_vpe(cpu_idx); + + return sprintf(buf, "%d\n", vpe->ntcs); +} + +static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(cpu_idx); + unsigned long new; + int ret; + + ret = kstrtoul(buf, 0, &new); + if (ret < 0) + return ret; + + if (new != 1) + return -EINVAL; + + vpe->ntcs = new; + + return len; +} +#else +static ssize_t store_kill(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(cpu_idx); + struct vpe_notifications *not; + + list_for_each_entry(not, &vpe->notify, list) { + not->stop(cpu_idx); + } + + release_progmem(vpe->load_addr); + cleanup_tc(get_tc(cpu_idx)); vpe_stop(vpe); vpe_free(vpe); @@ -1348,7 +1396,7 @@ static ssize_t store_kill(struct device *dev, struct device_attribute *attr, static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, char *buf) { - struct vpe *vpe = get_vpe(tclimit); + struct vpe *vpe = get_vpe(cpu_idx); return sprintf(buf, "%d\n", vpe->ntcs); } @@ -1356,24 +1404,22 @@ static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { - struct vpe *vpe = get_vpe(tclimit); + struct vpe *vpe = get_vpe(cpu_idx); unsigned long new; - char *endp; + int ret; - new = simple_strtoul(buf, &endp, 0); - if (endp == buf) - goto out_einval; + ret = kstrtoul(buf, 0, &new); + if (ret < 0) + return ret; - if (new == 0 || new > (hw_tcs - tclimit)) - goto out_einval; + if (new == 0 || new > (hw_tcs - cpu_idx)) + return -EINVAL; vpe->ntcs = new; return len; - -out_einval: - return -EINVAL; } +#endif /* CONFIG_MIPS_CMP */ static struct device_attribute vpe_class_attributes[] = { __ATTR(kill, S_IWUSR, NULL, store_kill), @@ -1395,6 +1441,84 @@ struct class vpe_class = { struct device vpe_device; +#ifdef CONFIG_MIPS_CMP +static int __init vpe_module_init(void) +{ + struct vpe *v = NULL; + struct tc *t; + int err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + cpu_idx = setup_max_cpus; + + if (num_possible_cpus() - cpu_idx < 1) { + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxcpus= argument as kernel argument\n"); + return -ENODEV; + } + + major = register_chrdev(0, module_name, &vpe_fops); + if (major < 0) { + pr_warn("VPE loader: unable to register character device\n"); + return major; + } + + err = class_register(&vpe_class); + if (err) { + pr_err("vpe_class registration failed\n"); + goto out_chrdev; + } + + device_initialize(&vpe_device); + vpe_device.class = &vpe_class, + vpe_device.parent = NULL, + dev_set_name(&vpe_device, "vpe_sp"); + vpe_device.devt = MKDEV(major, minor); + err = device_add(&vpe_device); + if (err) { + pr_err("Adding vpe_device failed\n"); + goto out_class; + } + + t = alloc_tc(cpu_idx); + if (!t) { + pr_warn("VPE: unable to allocate TC\n"); + err = -ENOMEM; + goto out; + } + + /* VPE */ + v = alloc_vpe(cpu_idx); + if (v == NULL) { + pr_warn("VPE: unable to allocate VPE\n"); + kfree(t); + err = -ENOMEM; + goto out; + } + + v->ntcs = 1; + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); + + /* TC */ + t->pvpe = v; /* set the parent vpe */ + + return 0; + +out_class: + class_unregister(&vpe_class); +out_chrdev: + unregister_chrdev(major, module_name); + +out: + return err; +} +#else static int __init vpe_module_init(void) { unsigned int mtflags, vpflags; @@ -1404,35 +1528,35 @@ static int __init vpe_module_init(void) int tc, err; if (!cpu_has_mipsmt) { - printk("VPE loader: not a MIPS MT capable processor\n"); + pr_warn("VPE loader: not a MIPS MT capable processor\n"); return -ENODEV; } if (vpelimit == 0) { - printk(KERN_WARNING "No VPEs reserved for AP/SP, not " - "initializing VPE loader.\nPass maxvpes= argument as " - "kernel argument\n"); + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxvpes= argument as kernel argument\n"); return -ENODEV; } - if (tclimit == 0) { - printk(KERN_WARNING "No TCs reserved for AP/SP, not " - "initializing VPE loader.\nPass maxtcs= argument as " - "kernel argument\n"); + cpu_idx = tclimit; + + if (cpu_idx == 0) { + pr_warn("No TCs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxtcs= argument as kernel argument\n"); return -ENODEV; } major = register_chrdev(0, module_name, &vpe_fops); if (major < 0) { - printk("VPE loader: unable to register character device\n"); + pr_warn("VPE loader: unable to register character device\n"); return major; } err = class_register(&vpe_class); if (err) { - printk(KERN_ERR "vpe_class registration failed\n"); + pr_err("vpe_class registration failed\n"); goto out_chrdev; } @@ -1443,7 +1567,7 @@ static int __init vpe_module_init(void) vpe_device.devt = MKDEV(major, minor); err = device_add(&vpe_device); if (err) { - printk(KERN_ERR "Adding vpe_device failed\n"); + pr_err("Adding vpe_device failed\n"); goto out_class; } @@ -1460,7 +1584,7 @@ static int __init vpe_module_init(void) hw_tcs = (val & MVPCONF0_PTC) + 1; hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; - for (tc = tclimit; tc < hw_tcs; tc++) { + for (tc = cpu_idx; tc < hw_tcs; tc++) { /* * Must re-enable multithreading temporarily or in case we * reschedule send IPIs or similar we might hang. @@ -1484,19 +1608,20 @@ static int __init vpe_module_init(void) if (tc < hw_tcs) { settc(tc); - if ((v = alloc_vpe(tc)) == NULL) { - printk(KERN_WARNING "VPE: unable to allocate VPE\n"); + v = alloc_vpe(tc); + if (v == NULL) { + pr_warn("VPE: unable to allocate VPE\n"); goto out_reenable; } - v->ntcs = hw_tcs - tclimit; + v->ntcs = hw_tcs - cpu_idx; /* add the tc to the list of this vpe's tc's. */ list_add(&t->tc, &v->tc); /* deactivate all but vpe0 */ - if (tc >= tclimit) { + if (tc >= cpu_idx) { unsigned long tmp = read_vpe_c0_vpeconf0(); tmp &= ~VPECONF0_VPA; @@ -1521,7 +1646,7 @@ static int __init vpe_module_init(void) /* TC's */ t->pvpe = v; /* set the parent vpe */ - if (tc >= tclimit) { + if (tc >= cpu_idx) { unsigned long tmp; settc(tc); @@ -1574,6 +1699,7 @@ out_chrdev: out: return err; } +#endif /* CONFIG_MIPS_CMP */ static void __exit vpe_module_exit(void) { -- 1.7.1 From dczhu@mips.com Mon Jan 7 19:05:56 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jan 2013 19:06:35 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:44303 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823003Ab3AGSF4HkSBQ (ORCPT ); Mon, 7 Jan 2013 19:05:56 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r07I5mZQ030382; Mon, 7 Jan 2013 10:05:49 -0800 X-WSS-ID: 0MG9OXL-01-2WG-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2861536465B; Mon, 7 Jan 2013 10:05:45 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.2.247.3; Mon, 7 Jan 2013 10:05:41 -0800 From: Deng-Cheng Zhu To: , , , , CC: , Subject: [RESEND PATCH v3 2/5] MIPS: APRP (APSP): split vpe-loader and rtlx into cmp/mt flavors Date: Mon, 7 Jan 2013 10:05:11 -0800 Message-ID: <1357581914-4589-3-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1357581914-4589-1-git-send-email-dczhu@mips.com> References: <1357581914-4589-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: Rhr5b82P/a0f4fVz8kRsBg== X-archive-position: 35386 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 68177 Lines: 2790 Remove CONFIG_MIPS_CMP #ifdef's by using -cmp/-mt files. Coding style adjustments are made as well. Cc: Steven J. Hill Signed-off-by: Deng-Cheng Zhu --- arch/mips/include/asm/rtlx.h | 40 ++- arch/mips/include/asm/vpe.h | 118 ++++++- arch/mips/kernel/Makefile | 9 +- arch/mips/kernel/rtlx-cmp.c | 125 ++++++ arch/mips/kernel/rtlx-mt.c | 160 ++++++++ arch/mips/kernel/rtlx.c | 285 ++------------- arch/mips/kernel/vpe-cmp.c | 185 +++++++++ arch/mips/kernel/vpe-mt.c | 534 ++++++++++++++++++++++++++ arch/mips/kernel/vpe.c | 873 +++--------------------------------------- 9 files changed, 1238 insertions(+), 1091 deletions(-) create mode 100644 arch/mips/kernel/rtlx-cmp.c create mode 100644 arch/mips/kernel/rtlx-mt.c create mode 100644 arch/mips/kernel/vpe-cmp.c create mode 100644 arch/mips/kernel/vpe-mt.c diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h index 478349e..4f27eab 100644 --- a/arch/mips/include/asm/rtlx.h +++ b/arch/mips/include/asm/rtlx.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2004, 2005, 2012 MIPS Technologies, Inc. All rights reserved. * */ @@ -8,6 +8,8 @@ #include +#define RTLX_MODULE_NAME "rtlx" + #define LX_NODE_BASE 10 #define MIPS_CPU_RTLX_IRQ 0 @@ -15,19 +17,31 @@ #define RTLX_VERSION 2 #define RTLX_xID 0x12345600 #define RTLX_ID (RTLX_xID | RTLX_VERSION) +#define RTLX_BUFFER_SIZE 2048 #define RTLX_CHANNELS 8 #define RTLX_CHANNEL_STDIO 0 #define RTLX_CHANNEL_DBG 1 #define RTLX_CHANNEL_SYSIO 2 -extern int rtlx_open(int index, int can_sleep); -extern int rtlx_release(int index); -extern ssize_t rtlx_read(int index, void __user *buff, size_t count); -extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count); -extern unsigned int rtlx_read_poll(int index, int can_sleep); -extern unsigned int rtlx_write_poll(int index); +void rtlx_starting(int vpe); +void rtlx_stopping(int vpe); + +int rtlx_open(int index, int can_sleep); +int rtlx_release(int index); +ssize_t rtlx_read(int index, void __user *buff, size_t count); +ssize_t rtlx_write(int index, const void __user *buffer, size_t count); +unsigned int rtlx_read_poll(int index, int can_sleep); +unsigned int rtlx_write_poll(int index); + +int __init rtlx_module_init(void); +void __exit rtlx_module_exit(void); +void _interrupt_sp(void); + +extern struct vpe_notifications rtlx_notify; +extern const struct file_operations rtlx_fops; +static inline void null_aprp_hook(void) { } extern void (*aprp_hook)(void); enum rtlx_state { @@ -37,7 +51,12 @@ enum rtlx_state { RTLX_STATE_OPENED }; -#define RTLX_BUFFER_SIZE 2048 +extern struct chan_waitqueues { + wait_queue_head_t rt_queue; + wait_queue_head_t lx_queue; + atomic_t in_open; + struct mutex mutex; +} channel_wqs[RTLX_CHANNELS]; /* each channel supports read and write. linux (vpe0) reads lx_buffer and writes rt_buffer @@ -57,7 +76,7 @@ struct rtlx_channel { char *lx_buffer; }; -struct rtlx_info { +extern struct rtlx_info { unsigned long id; enum rtlx_state state; #ifdef CONFIG_MIPS_CMP @@ -65,6 +84,5 @@ struct rtlx_info { #endif struct rtlx_channel channel[RTLX_CHANNELS]; -}; - +} *rtlx; #endif /* __ASM_RTLX_H_ */ diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index c6e1b96..4cfc4fd 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2005, 2012 MIPS Technologies, Inc. All rights reserved. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -19,6 +19,88 @@ #ifndef _ASM_VPE_H #define _ASM_VPE_H +#include +#include +#include +#include + +#define VPE_MODULE_NAME "vpe" +#define VPE_MODULE_MINOR 1 + +/* grab the likely amount of memory we will need. */ +#ifdef CONFIG_MIPS_VPE_LOADER_TOM +#define P_SIZE (2 * 1024 * 1024) +#else +/* add an overhead to the max kmalloc size for non-striped symbols/etc */ +#define P_SIZE (256 * 1024) +#endif + +#define MAX_VPES 16 +#define VPE_PATH_MAX 256 + +static inline int aprp_cpu_index(void) +{ +#ifdef CONFIG_MIPS_CMP + return setup_max_cpus; +#else + extern int tclimit; + return tclimit; +#endif +} + +enum vpe_state { + VPE_STATE_UNUSED = 0, + VPE_STATE_INUSE, + VPE_STATE_RUNNING +}; + +enum tc_state { + TC_STATE_UNUSED = 0, + TC_STATE_INUSE, + TC_STATE_RUNNING, + TC_STATE_DYNAMIC +}; + +struct vpe { + enum vpe_state state; + + /* (device) minor associated with this vpe */ + int minor; + + /* elfloader stuff */ + void *load_addr; + unsigned long len; + char *pbuffer; + unsigned long plen; + unsigned int uid, gid; + char cwd[VPE_PATH_MAX]; + + unsigned long __start; + + /* tc's associated with this vpe */ + struct list_head tc; + + /* The list of vpe's */ + struct list_head list; + + /* shared symbol address */ + void *shared_ptr; + + /* the list of who wants to know when something major happens */ + struct list_head notify; + + unsigned int ntcs; +}; + +struct tc { + enum tc_state state; + int index; + + struct vpe *pvpe; /* parent VPE */ + struct list_head tc; /* The list of TC's with this VPE */ + struct list_head list; /* The global list of tc's */ +}; + struct vpe_notifications { void (*start)(int vpe); void (*stop)(int vpe); @@ -26,12 +108,36 @@ struct vpe_notifications { struct list_head list; }; +struct vpe_control { + spinlock_t vpe_list_lock; + struct list_head vpe_list; /* Virtual processing elements */ + spinlock_t tc_list_lock; + struct list_head tc_list; /* Thread contexts */ +}; + +extern unsigned long physical_memsize; +extern struct vpe_control vpecontrol; +extern const struct file_operations vpe_fops; + +int vpe_notify(int index, struct vpe_notifications *notify); + +void *vpe_get_shared(int index); +int vpe_getuid(int index); +int vpe_getgid(int index); +char *vpe_getcwd(int index); + +struct vpe *get_vpe(int minor); +struct tc *get_tc(int index); +struct vpe *alloc_vpe(int minor); +struct tc *alloc_tc(int index); +void release_vpe(struct vpe *v); -extern int vpe_notify(int index, struct vpe_notifications *notify); +void *alloc_progmem(unsigned long len); +void release_progmem(void *ptr); -extern void *vpe_get_shared(int index); -extern int vpe_getuid(int index); -extern int vpe_getgid(int index); -extern char *vpe_getcwd(int index); +int vpe_run(struct vpe *v); +void cleanup_tc(struct tc *tc); +int __init vpe_module_init(void); +void __exit vpe_module_exit(void); #endif /* _ASM_VPE_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 8b28bc4..16f581a 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -52,8 +52,13 @@ obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o obj-$(CONFIG_MIPS_CMP) += smp-cmp.o obj-$(CONFIG_CPU_MIPSR2) += spram.o -obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o -obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o +ifdef CONFIG_MIPS_CMP +obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o vpe-cmp.o +obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o rtlx-cmp.o +else +obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o vpe-mt.o +obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o rtlx-mt.o +endif obj-$(CONFIG_I8259) += i8259.o obj-$(CONFIG_IRQ_CPU) += irq_cpu.o diff --git a/arch/mips/kernel/rtlx-cmp.c b/arch/mips/kernel/rtlx-cmp.c new file mode 100644 index 0000000..61d848b --- /dev/null +++ b/arch/mips/kernel/rtlx-cmp.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2005, 2012 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static int major; + +static void rtlx_interrupt(void) +{ + int i; + struct rtlx_info *info; + struct rtlx_info **p = vpe_get_shared(aprp_cpu_index()); + + if (p == NULL || *p == NULL) + return; + + info = *p; + + if (info->ap_int_pending == 1 && smp_processor_id() == 0) { + for (i = 0; i < RTLX_CHANNELS; i++) { + wake_up(&channel_wqs[i].lx_queue); + wake_up(&channel_wqs[i].rt_queue); + } + info->ap_int_pending = 0; + } +} + +void _interrupt_sp(void) +{ + smp_send_reschedule(aprp_cpu_index()); +} + +int __init rtlx_module_init(void) +{ + struct device *dev; + int i, err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if (num_possible_cpus() - aprp_cpu_index() < 1) { + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" + "Pass maxcpus= argument as kernel argument\n"); + + return -ENODEV; + } + + major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops); + if (major < 0) { + pr_err("rtlx_module_init: unable to register device\n"); + return major; + } + + /* initialise the wait queues */ + for (i = 0; i < RTLX_CHANNELS; i++) { + init_waitqueue_head(&channel_wqs[i].rt_queue); + init_waitqueue_head(&channel_wqs[i].lx_queue); + atomic_set(&channel_wqs[i].in_open, 0); + mutex_init(&channel_wqs[i].mutex); + + dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, + "%s%d", RTLX_MODULE_NAME, i); + if (IS_ERR(dev)) { + err = PTR_ERR(dev); + goto out_chrdev; + } + } + + /* set up notifiers */ + rtlx_notify.start = rtlx_starting; + rtlx_notify.stop = rtlx_stopping; + vpe_notify(aprp_cpu_index(), &rtlx_notify); + + if (cpu_has_vint) { + aprp_hook = rtlx_interrupt; + } else { + pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); + err = -ENODEV; + goto out_chrdev; + } + + return 0; + +out_chrdev: + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + return err; +} + +void __exit rtlx_module_exit(void) +{ + int i; + + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + unregister_chrdev(major, RTLX_MODULE_NAME); + aprp_hook = null_aprp_hook; +} diff --git a/arch/mips/kernel/rtlx-mt.c b/arch/mips/kernel/rtlx-mt.c new file mode 100644 index 0000000..679480a --- /dev/null +++ b/arch/mips/kernel/rtlx-mt.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2005, 2012 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static int major; + +static void rtlx_dispatch(void) +{ + if (read_c0_cause() & read_c0_status() & C_SW0) + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); +} + +/* + * Interrupt handler may be called before rtlx_init has otherwise had + * a chance to run. + */ +static irqreturn_t rtlx_interrupt(int irq, void *dev_id) +{ + unsigned int vpeflags; + unsigned long flags; + int i; + + /* Ought not to be strictly necessary for SMTC builds */ + local_irq_save(flags); + vpeflags = dvpe(); + set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ); + irq_enable_hazard(); + evpe(vpeflags); + local_irq_restore(flags); + + for (i = 0; i < RTLX_CHANNELS; i++) { + wake_up(&channel_wqs[i].lx_queue); + wake_up(&channel_wqs[i].rt_queue); + } + + return IRQ_HANDLED; +} + +static struct irqaction rtlx_irq = { + .handler = rtlx_interrupt, + .name = "RTLX", +}; + +static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; + +void _interrupt_sp(void) +{ + unsigned long flags; + + local_irq_save(flags); + dvpe(); + settc(1); + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); + evpe(EVPE_ENABLE); + local_irq_restore(flags); +} + +int __init rtlx_module_init(void) +{ + struct device *dev; + int i, err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if (aprp_cpu_index() == 0) { + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" + "Pass maxtcs= argument as kernel argument\n"); + + return -ENODEV; + } + + major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops); + if (major < 0) { + pr_err("rtlx_module_init: unable to register device\n"); + return major; + } + + /* initialise the wait queues */ + for (i = 0; i < RTLX_CHANNELS; i++) { + init_waitqueue_head(&channel_wqs[i].rt_queue); + init_waitqueue_head(&channel_wqs[i].lx_queue); + atomic_set(&channel_wqs[i].in_open, 0); + mutex_init(&channel_wqs[i].mutex); + + dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, + "%s%d", RTLX_MODULE_NAME, i); + if (IS_ERR(dev)) { + err = PTR_ERR(dev); + goto out_chrdev; + } + } + + /* set up notifiers */ + rtlx_notify.start = rtlx_starting; + rtlx_notify.stop = rtlx_stopping; + vpe_notify(aprp_cpu_index(), &rtlx_notify); + + if (cpu_has_vint) { + /* + * set_vi_handler() doesn't work in some cases: When sw0 + * gets set, a hw interrupt is signaled as well. Here we + * are hooking it into platform specific dispatch. + */ + aprp_hook = rtlx_dispatch; + } else { + pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); + err = -ENODEV; + goto out_chrdev; + } + + rtlx_irq.dev_id = rtlx; + setup_irq(rtlx_irq_num, &rtlx_irq); + + return 0; + +out_chrdev: + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + return err; +} + +void __exit rtlx_module_exit(void) +{ + int i; + + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + unregister_chrdev(major, RTLX_MODULE_NAME); + aprp_hook = null_aprp_hook; +} diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index eeda8a2..287e244 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -36,105 +36,39 @@ #include #include #include -#include #include #include #include #include -static struct rtlx_info *rtlx; -static int major; -static char module_name[] = "rtlx"; - -static struct chan_waitqueues { - wait_queue_head_t rt_queue; - wait_queue_head_t lx_queue; - atomic_t in_open; - struct mutex mutex; -} channel_wqs[RTLX_CHANNELS]; - -static struct vpe_notifications notify; static int sp_stopping; -static int cpu_idx; -static void null_aprp_hook(void) {}; - -void (*aprp_hook)(void) = null_aprp_hook; - -extern void *vpe_get_shared(int index); - -#ifdef CONFIG_MIPS_CMP -static void rtlx_interrupt(void) -{ - int i; - struct rtlx_info *info; - struct rtlx_info **p = vpe_get_shared(cpu_idx); - - if (p == NULL || *p == NULL) - return; - - info = *p; - if (info->ap_int_pending == 1 && smp_processor_id() == 0) { - for (i = 0; i < RTLX_CHANNELS; i++) { - wake_up(&channel_wqs[i].lx_queue); - wake_up(&channel_wqs[i].rt_queue); - } - info->ap_int_pending = 0; - } -} -#else -static void rtlx_dispatch(void) -{ - if (read_c0_cause() & read_c0_status() & C_SW0) - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); -} - -/* Interrupt handler may be called before rtlx_init has otherwise had - a chance to run. -*/ -static irqreturn_t rtlx_interrupt(int irq, void *dev_id) -{ - unsigned int vpeflags; - unsigned long flags; - int i; - - /* Ought not to be strictly necessary for SMTC builds */ - local_irq_save(flags); - vpeflags = dvpe(); - set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ); - irq_enable_hazard(); - evpe(vpeflags); - local_irq_restore(flags); - - for (i = 0; i < RTLX_CHANNELS; i++) { - wake_up(&channel_wqs[i].lx_queue); - wake_up(&channel_wqs[i].rt_queue); - } - - return IRQ_HANDLED; -} -#endif +struct rtlx_info *rtlx; +struct chan_waitqueues channel_wqs[RTLX_CHANNELS]; +struct vpe_notifications rtlx_notify; +void (*aprp_hook)(void); +EXPORT_SYMBOL(aprp_hook); static void __used dump_rtlx(void) { int i; - printk("id 0x%lx state %d\n", rtlx->id, rtlx->state); + pr_debug("id 0x%lx state %d\n", rtlx->id, rtlx->state); for (i = 0; i < RTLX_CHANNELS; i++) { struct rtlx_channel *chan = &rtlx->channel[i]; - printk(" rt_state %d lx_state %d buffer_size %d\n", + pr_debug(" rt_state %d lx_state %d buffer_size %d\n", chan->rt_state, chan->lx_state, chan->buffer_size); - printk(" rt_read %d rt_write %d\n", + pr_debug(" rt_read %d rt_write %d\n", chan->rt_read, chan->rt_write); - printk(" lx_read %d lx_write %d\n", + pr_debug(" lx_read %d lx_write %d\n", chan->lx_read, chan->lx_write); - printk(" rt_buffer <%s>\n", chan->rt_buffer); - printk(" lx_buffer <%s>\n", chan->lx_buffer); + pr_debug(" rt_buffer <%s>\n", chan->rt_buffer); + pr_debug(" lx_buffer <%s>\n", chan->lx_buffer); } } @@ -152,7 +86,7 @@ static int rtlx_init(struct rtlx_info *rtlxi) } /* notifications */ -static void starting(int vpe) +void rtlx_starting(int vpe) { int i; sp_stopping = 0; @@ -165,7 +99,7 @@ static void starting(int vpe) wake_up_interruptible(&channel_wqs[i].lx_queue); } -static void stopping(int vpe) +void rtlx_stopping(int vpe) { int i; @@ -194,12 +128,13 @@ int rtlx_open(int index, int can_sleep) } if (rtlx == NULL) { - p = vpe_get_shared(cpu_idx); + p = vpe_get_shared(aprp_cpu_index()); if (p == NULL) { if (can_sleep) { __wait_event_interruptible( channel_wqs[index].lx_queue, - (p = vpe_get_shared(cpu_idx)), ret); + (p = vpe_get_shared(aprp_cpu_index())), + ret); if (ret) goto out_fail; } else { @@ -238,7 +173,7 @@ int rtlx_open(int index, int can_sleep) if ((unsigned int)*p < KSEG0) { pr_warn("vpe_get_shared returned an invalid pointer maybe an error code %d\n", - (int)*p); + (int)*p); ret = -ENOSYS; goto out_fail; } @@ -276,12 +211,12 @@ int rtlx_release(int index) unsigned int rtlx_read_poll(int index, int can_sleep) { - struct rtlx_channel *chan; + struct rtlx_channel *chan; - if (rtlx == NULL) - return 0; + if (rtlx == NULL) + return 0; - chan = &rtlx->channel[index]; + chan = &rtlx->channel[index]; /* data available to read? */ if (chan->lx_read == chan->lx_write) { @@ -367,25 +302,6 @@ out: return count; } -#ifdef CONFIG_MIPS_CMP -static void _interrupt_sp(void) -{ - smp_send_reschedule(cpu_idx); -} -#else -static void _interrupt_sp(void) -{ - unsigned long flags; - - local_irq_save(flags); - dvpe(); - settc(1); - write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); - evpe(EVPE_ENABLE); - local_irq_restore(flags); -} -#endif - ssize_t rtlx_write(int index, const void __user *buffer, size_t count) { struct rtlx_channel *rt; @@ -473,7 +389,7 @@ static ssize_t file_read(struct file *file, char __user * buffer, size_t count, /* data available? */ if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1)) { - return 0; // -EAGAIN makes cat whinge + return 0; /* -EAGAIN makes cat whinge */ } return rtlx_read(minor, buffer, count); @@ -505,7 +421,7 @@ static ssize_t file_write(struct file *file, const char __user * buffer, return rtlx_write(minor, buffer, count); } -static const struct file_operations rtlx_fops = { +const struct file_operations rtlx_fops = { .owner = THIS_MODULE, .open = file_open, .release = file_release, @@ -515,161 +431,6 @@ static const struct file_operations rtlx_fops = { .llseek = noop_llseek, }; -static char register_chrdev_failed[] __initdata = - KERN_ERR "rtlx_module_init: unable to register device\n"; - -#ifdef CONFIG_MIPS_CMP -static int __init rtlx_module_init(void) -{ - struct device *dev; - int i, err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - cpu_idx = setup_max_cpus; - - if (num_possible_cpus() - cpu_idx < 1) { - pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" - "Pass maxcpus= argument as kernel argument\n"); - - return -ENODEV; - } - - major = register_chrdev(0, module_name, &rtlx_fops); - if (major < 0) { - printk(register_chrdev_failed); - return major; - } - - /* initialise the wait queues */ - for (i = 0; i < RTLX_CHANNELS; i++) { - init_waitqueue_head(&channel_wqs[i].rt_queue); - init_waitqueue_head(&channel_wqs[i].lx_queue); - atomic_set(&channel_wqs[i].in_open, 0); - mutex_init(&channel_wqs[i].mutex); - - dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, - "%s%d", module_name, i); - if (IS_ERR(dev)) { - err = PTR_ERR(dev); - goto out_chrdev; - } - } - - /* set up notifiers */ - notify.start = starting; - notify.stop = stopping; - vpe_notify(cpu_idx, ¬ify); - - if (cpu_has_vint) { - aprp_hook = rtlx_interrupt; - } else { - pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); - err = -ENODEV; - goto out_chrdev; - } - - return 0; - -out_chrdev: - for (i = 0; i < RTLX_CHANNELS; i++) - device_destroy(mt_class, MKDEV(major, i)); - - return err; -} -#else -static struct irqaction rtlx_irq = { - .handler = rtlx_interrupt, - .name = "RTLX", -}; - -static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; - -static int __init rtlx_module_init(void) -{ - struct device *dev; - int i, err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - cpu_idx = tclimit; - - if (cpu_idx == 0) { - pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" - "Pass maxtcs= argument as kernel argument\n"); - - return -ENODEV; - } - - major = register_chrdev(0, module_name, &rtlx_fops); - if (major < 0) { - printk(register_chrdev_failed); - return major; - } - - /* initialise the wait queues */ - for (i = 0; i < RTLX_CHANNELS; i++) { - init_waitqueue_head(&channel_wqs[i].rt_queue); - init_waitqueue_head(&channel_wqs[i].lx_queue); - atomic_set(&channel_wqs[i].in_open, 0); - mutex_init(&channel_wqs[i].mutex); - - dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, - "%s%d", module_name, i); - if (IS_ERR(dev)) { - err = PTR_ERR(dev); - goto out_chrdev; - } - } - - /* set up notifiers */ - notify.start = starting; - notify.stop = stopping; - vpe_notify(cpu_idx, ¬ify); - - if (cpu_has_vint) { - /* - * set_vi_handler() doesn't work in some cases: When sw0 - * gets set, a hw interrupt is signaled as well. Here we - * are hooking it into platform specific dispatch. - */ - aprp_hook = rtlx_dispatch; - } else { - pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); - err = -ENODEV; - goto out_chrdev; - } - - rtlx_irq.dev_id = rtlx; - setup_irq(rtlx_irq_num, &rtlx_irq); - - return 0; - -out_chrdev: - for (i = 0; i < RTLX_CHANNELS; i++) - device_destroy(mt_class, MKDEV(major, i)); - - return err; -} -#endif - -static void __exit rtlx_module_exit(void) -{ - int i; - - for (i = 0; i < RTLX_CHANNELS; i++) - device_destroy(mt_class, MKDEV(major, i)); - - unregister_chrdev(major, module_name); - aprp_hook = null_aprp_hook; -} - module_init(rtlx_module_init); module_exit(rtlx_module_exit); diff --git a/arch/mips/kernel/vpe-cmp.c b/arch/mips/kernel/vpe-cmp.c new file mode 100644 index 0000000..9d0c375 --- /dev/null +++ b/arch/mips/kernel/vpe-cmp.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2004, 2005, 2012 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include + +#include + +static int major; + +#error CMP vpe_run() not implemented! + +void cleanup_tc(struct tc *tc) +{ + +} + +static ssize_t store_kill(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + struct vpe_notifications *not; + + list_for_each_entry(not, &vpe->notify, list) { + not->stop(aprp_cpu_index()); + } + + release_progmem(vpe->load_addr); + vpe->state = VPE_STATE_UNUSED; + + return len; +} + +static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, + char *buf) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + + return sprintf(buf, "%d\n", vpe->ntcs); +} + +static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + unsigned long new; + int ret; + + ret = kstrtoul(buf, 0, &new); + if (ret < 0) + return ret; + + if (new != 1) + return -EINVAL; + + vpe->ntcs = new; + + return len; +} + +static struct device_attribute vpe_class_attributes[] = { + __ATTR(kill, S_IWUSR, NULL, store_kill), + __ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs), + {} +}; + +static void vpe_device_release(struct device *cd) +{ + kfree(cd); +} + +static struct class vpe_class = { + .name = "vpe", + .owner = THIS_MODULE, + .dev_release = vpe_device_release, + .dev_attrs = vpe_class_attributes, +}; + +static struct device vpe_device; + +int __init vpe_module_init(void) +{ + struct vpe *v = NULL; + struct tc *t; + int err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if (num_possible_cpus() - aprp_cpu_index() < 1) { + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxcpus= argument as kernel argument\n"); + return -ENODEV; + } + + major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops); + if (major < 0) { + pr_warn("VPE loader: unable to register character device\n"); + return major; + } + + err = class_register(&vpe_class); + if (err) { + pr_err("vpe_class registration failed\n"); + goto out_chrdev; + } + + device_initialize(&vpe_device); + vpe_device.class = &vpe_class, + vpe_device.parent = NULL, + dev_set_name(&vpe_device, "vpe_sp"); + vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR); + err = device_add(&vpe_device); + if (err) { + pr_err("Adding vpe_device failed\n"); + goto out_class; + } + + t = alloc_tc(aprp_cpu_index()); + if (!t) { + pr_warn("VPE: unable to allocate TC\n"); + err = -ENOMEM; + goto out; + } + + /* VPE */ + v = alloc_vpe(aprp_cpu_index()); + if (v == NULL) { + pr_warn("VPE: unable to allocate VPE\n"); + kfree(t); + err = -ENOMEM; + goto out; + } + + v->ntcs = 1; + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); + + /* TC */ + t->pvpe = v; /* set the parent vpe */ + + return 0; + +out_class: + class_unregister(&vpe_class); +out_chrdev: + unregister_chrdev(major, VPE_MODULE_NAME); + +out: + return err; +} + +void __exit vpe_module_exit(void) +{ + struct vpe *v, *n; + + device_del(&vpe_device); + unregister_chrdev(major, VPE_MODULE_NAME); + + /* No locking needed here */ + list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) { + if (v->state != VPE_STATE_UNUSED) + release_vpe(v); + } +} diff --git a/arch/mips/kernel/vpe-mt.c b/arch/mips/kernel/vpe-mt.c new file mode 100644 index 0000000..0f71d30 --- /dev/null +++ b/arch/mips/kernel/vpe-mt.c @@ -0,0 +1,534 @@ +/* + * Copyright (C) 2004, 2005, 2012 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static int major; +/* The number of TCs and VPEs physically available on the core */ +static int hw_tcs, hw_vpes; + +/* We are prepared so configure and start the VPE... */ +int vpe_run(struct vpe *v) +{ + unsigned long flags, val, dmt_flag; + struct vpe_notifications *n; + unsigned int vpeflags; + struct tc *t; + + /* check we are the Master VPE */ + local_irq_save(flags); + val = read_c0_vpeconf0(); + if (!(val & VPECONF0_MVP)) { + pr_warn("VPE loader: only Master VPE's are able to config MT\n"); + local_irq_restore(flags); + + return -1; + } + + dmt_flag = dmt(); + vpeflags = dvpe(); + + if (!list_empty(&v->tc)) { + t = list_entry(v->tc.next, struct tc, tc); + if (t == NULL) { + evpe(vpeflags); + emt(dmt_flag); + local_irq_restore(flags); + + pr_warn("VPE loader: TC %d is already in use.\n", + t->index); + return -ENOEXEC; + } + } else { + evpe(vpeflags); + emt(dmt_flag); + local_irq_restore(flags); + + pr_warn("VPE loader: No TC's associated with VPE %d\n", + v->minor); + + return -ENOEXEC; + } + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + settc(t->index); + + /* should check it is halted, and not activated */ + if ((read_tc_c0_tcstatus() & TCSTATUS_A) || + !(read_tc_c0_tchalt() & TCHALT_H)) { + evpe(vpeflags); + emt(dmt_flag); + local_irq_restore(flags); + + pr_warn("VPE loader: TC %d is already active!\n", + t->index); + + return -ENOEXEC; + } + + /* + * Write the address we want it to start running from in the TCPC + * register. + */ + write_tc_c0_tcrestart((unsigned long)v->__start); + write_tc_c0_tccontext((unsigned long)0); + + /* + * Mark the TC as activated, not interrupt exempt and not dynamically + * allocatable + */ + val = read_tc_c0_tcstatus(); + val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A; + write_tc_c0_tcstatus(val); + + write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); + + /* + * The sde-kit passes 'memsize' to __start in $a3, so set something + * here... Or set $a3 to zero and define DFLT_STACK_SIZE and + * DFLT_HEAP_SIZE when you compile your program + */ + mttgpr(6, v->ntcs); + mttgpr(7, physical_memsize); + + /* set up VPE1 */ + /* + * bind the TC to VPE 1 as late as possible so we only have the final + * VPE registers to set up, and so an EJTAG probe can trigger on it + */ + write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1); + + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); + + back_to_back_c0_hazard(); + + /* Set up the XTC bit in vpeconf0 to point at our tc */ + write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC)) + | (t->index << VPECONF0_XTC_SHIFT)); + + back_to_back_c0_hazard(); + + /* enable this VPE */ + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); + + /* clear out any left overs from a previous program */ + write_vpe_c0_status(0); + write_vpe_c0_cause(0); + + /* take system out of configuration state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + /* + * SMTC/SMVP kernels manage VPE enable independently, + * but uniprocessor kernels need to turn it on, even + * if that wasn't the pre-dvpe() state. + */ +#ifdef CONFIG_SMP + evpe(vpeflags); +#else + evpe(EVPE_ENABLE); +#endif + emt(dmt_flag); + local_irq_restore(flags); + + list_for_each_entry(n, &v->notify, list) + n->start(VPE_MODULE_MINOR); + + return 0; +} + +void cleanup_tc(struct tc *tc) +{ + unsigned long flags; + unsigned int mtflags, vpflags; + int tmp; + + local_irq_save(flags); + mtflags = dmt(); + vpflags = dvpe(); + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + settc(tc->index); + tmp = read_tc_c0_tcstatus(); + + /* mark not allocated and not dynamically allocatable */ + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ + write_tc_c0_tcstatus(tmp); + + write_tc_c0_tchalt(TCHALT_H); + mips_ihb(); + + clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); +} + +/* module wrapper entry points */ +/* give me a vpe */ +void *vpe_alloc(void) +{ + int i; + struct vpe *v; + + /* find a vpe */ + for (i = 1; i < MAX_VPES; i++) { + v = get_vpe(i); + if (v != NULL) { + v->state = VPE_STATE_INUSE; + return v; + } + } + return NULL; +} +EXPORT_SYMBOL(vpe_alloc); + +/* start running from here */ +int vpe_start(void *vpe, unsigned long start) +{ + struct vpe *v = vpe; + + v->__start = start; + return vpe_run(v); +} +EXPORT_SYMBOL(vpe_start); + +/* halt it for now */ +int vpe_stop(void *vpe) +{ + struct vpe *v = vpe; + struct tc *t; + unsigned int evpe_flags; + + evpe_flags = dvpe(); + + t = list_entry(v->tc.next, struct tc, tc); + if (t != NULL) { + settc(t->index); + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); + } + + evpe(evpe_flags); + + return 0; +} +EXPORT_SYMBOL(vpe_stop); + +/* I've done with it thank you */ +int vpe_free(void *vpe) +{ + struct vpe *v = vpe; + struct tc *t; + unsigned int evpe_flags; + + t = list_entry(v->tc.next, struct tc, tc); + if (t == NULL) + return -ENOEXEC; + + evpe_flags = dvpe(); + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + settc(t->index); + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); + + /* halt the TC */ + write_tc_c0_tchalt(TCHALT_H); + mips_ihb(); + + /* mark the TC unallocated */ + write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A); + + v->state = VPE_STATE_UNUSED; + + clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(evpe_flags); + + return 0; +} +EXPORT_SYMBOL(vpe_free); + +static ssize_t store_kill(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + struct vpe_notifications *not; + + list_for_each_entry(not, &vpe->notify, list) { + not->stop(aprp_cpu_index()); + } + + release_progmem(vpe->load_addr); + cleanup_tc(get_tc(aprp_cpu_index())); + vpe_stop(vpe); + vpe_free(vpe); + + return len; +} + +static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, + char *buf) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + + return sprintf(buf, "%d\n", vpe->ntcs); +} + +static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + unsigned long new; + int ret; + + ret = kstrtoul(buf, 0, &new); + if (ret < 0) + return ret; + + if (new == 0 || new > (hw_tcs - aprp_cpu_index())) + return -EINVAL; + + vpe->ntcs = new; + + return len; +} + +static struct device_attribute vpe_class_attributes[] = { + __ATTR(kill, S_IWUSR, NULL, store_kill), + __ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs), + {} +}; + +static void vpe_device_release(struct device *cd) +{ + kfree(cd); +} + +static struct class vpe_class = { + .name = "vpe", + .owner = THIS_MODULE, + .dev_release = vpe_device_release, + .dev_attrs = vpe_class_attributes, +}; + +static struct device vpe_device; + +int __init vpe_module_init(void) +{ + unsigned int mtflags, vpflags; + unsigned long flags, val; + struct vpe *v = NULL; + struct tc *t; + int tc, err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if (vpelimit == 0) { + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxvpes= argument as kernel argument\n"); + + return -ENODEV; + } + + if (aprp_cpu_index() == 0) { + pr_warn("No TCs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxtcs= argument as kernel argument\n"); + + return -ENODEV; + } + + major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops); + if (major < 0) { + pr_warn("VPE loader: unable to register character device\n"); + return major; + } + + err = class_register(&vpe_class); + if (err) { + pr_err("vpe_class registration failed\n"); + goto out_chrdev; + } + + device_initialize(&vpe_device); + vpe_device.class = &vpe_class, + vpe_device.parent = NULL, + dev_set_name(&vpe_device, "vpe1"); + vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR); + err = device_add(&vpe_device); + if (err) { + pr_err("Adding vpe_device failed\n"); + goto out_class; + } + + local_irq_save(flags); + mtflags = dmt(); + vpflags = dvpe(); + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + val = read_c0_mvpconf0(); + hw_tcs = (val & MVPCONF0_PTC) + 1; + hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; + + for (tc = aprp_cpu_index(); tc < hw_tcs; tc++) { + /* + * Must re-enable multithreading temporarily or in case we + * reschedule send IPIs or similar we might hang. + */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); + t = alloc_tc(tc); + if (!t) { + err = -ENOMEM; + goto out; + } + + local_irq_save(flags); + mtflags = dmt(); + vpflags = dvpe(); + set_c0_mvpcontrol(MVPCONTROL_VPC); + + /* VPE's */ + if (tc < hw_tcs) { + settc(tc); + + v = alloc_vpe(tc); + if (v == NULL) { + pr_warn("VPE: unable to allocate VPE\n"); + goto out_reenable; + } + + v->ntcs = hw_tcs - aprp_cpu_index(); + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); + + /* deactivate all but vpe0 */ + if (tc >= aprp_cpu_index()) { + unsigned long tmp = read_vpe_c0_vpeconf0(); + + tmp &= ~VPECONF0_VPA; + + /* master VPE */ + tmp |= VPECONF0_MVP; + write_vpe_c0_vpeconf0(tmp); + } + + /* disable multi-threading with TC's */ + write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & + ~VPECONTROL_TE); + + if (tc >= vpelimit) { + /* + * Set config to be the same as vpe0, + * particularly kseg0 coherency alg + */ + write_vpe_c0_config(read_c0_config()); + } + } + + /* TC's */ + t->pvpe = v; /* set the parent vpe */ + + if (tc >= aprp_cpu_index()) { + unsigned long tmp; + + settc(tc); + + /* Any TC that is bound to VPE0 gets left as is - in + * case we are running SMTC on VPE0. A TC that is bound + * to any other VPE gets bound to VPE0, ideally I'd like + * to make it homeless but it doesn't appear to let me + * bind a TC to a non-existent VPE. Which is perfectly + * reasonable. + * + * The (un)bound state is visible to an EJTAG probe so + * may notify GDB... + */ + tmp = read_tc_c0_tcbind(); + if (tmp & TCBIND_CURVPE) { + /* tc is bound >vpe0 */ + write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE); + + t->pvpe = get_vpe(0); /* set the parent vpe */ + } + + /* halt the TC */ + write_tc_c0_tchalt(TCHALT_H); + mips_ihb(); + + tmp = read_tc_c0_tcstatus(); + + /* mark not activated and not dynamically allocatable */ + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ + write_tc_c0_tcstatus(tmp); + } + } + +out_reenable: + /* release config state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); + + return 0; + +out_class: + class_unregister(&vpe_class); +out_chrdev: + unregister_chrdev(major, VPE_MODULE_NAME); + +out: + return err; +} + +void __exit vpe_module_exit(void) +{ + struct vpe *v, *n; + + device_del(&vpe_device); + unregister_chrdev(major, VPE_MODULE_NAME); + + /* No locking needed here */ + list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) { + if (v->state != VPE_STATE_UNUSED) + release_vpe(v); + } +} diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index a558bbe..e84bc7b 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -51,8 +51,6 @@ #include #include -typedef void *vpe_handle; - #ifndef ARCH_SHF_SMALL #define ARCH_SHF_SMALL 0 #endif @@ -60,97 +58,15 @@ typedef void *vpe_handle; /* If this is set, the section belongs in the init part of the module */ #define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) -/* - * The number of TCs and VPEs physically available on the core - */ -static int cpu_idx; -static int hw_tcs, hw_vpes; -static char module_name[] = "vpe"; -static int major; -static const int minor = 1; /* fixed for now */ - -/* grab the likely amount of memory we will need. */ -#ifdef CONFIG_MIPS_VPE_LOADER_TOM -#define P_SIZE (2 * 1024 * 1024) -#else -/* add an overhead to the max kmalloc size for non-striped symbols/etc */ -#define P_SIZE (256 * 1024) -#endif - -extern unsigned long physical_memsize; - -#define MAX_VPES 16 -#define VPE_PATH_MAX 256 - -enum vpe_state { - VPE_STATE_UNUSED = 0, - VPE_STATE_INUSE, - VPE_STATE_RUNNING -}; - -enum tc_state { - TC_STATE_UNUSED = 0, - TC_STATE_INUSE, - TC_STATE_RUNNING, - TC_STATE_DYNAMIC -}; - -struct vpe { - enum vpe_state state; - - /* (device) minor associated with this vpe */ - int minor; - - /* elfloader stuff */ - void *load_addr; - unsigned long len; - char *pbuffer; - unsigned long plen; - unsigned int uid, gid; - char cwd[VPE_PATH_MAX]; - - unsigned long __start; - - /* tc's associated with this vpe */ - struct list_head tc; - - /* The list of vpe's */ - struct list_head list; - - /* shared symbol address */ - void *shared_ptr; - - /* the list of who wants to know when something major happens */ - struct list_head notify; - - unsigned int ntcs; -}; - -struct tc { - enum tc_state state; - int index; - - struct vpe *pvpe; /* parent VPE */ - struct list_head tc; /* The list of TC's with this VPE */ - struct list_head list; /* The global list of tc's */ -}; - -struct { - spinlock_t vpe_list_lock; - struct list_head vpe_list; /* Virtual processing elements */ - spinlock_t tc_list_lock; - struct list_head tc_list; /* Thread contexts */ -} vpecontrol = { +struct vpe_control vpecontrol = { .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) }; -static void release_progmem(void *ptr); - /* get the vpe associated with this minor */ -static struct vpe *get_vpe(int minor) +struct vpe *get_vpe(int minor) { struct vpe *res, *v; @@ -160,7 +76,7 @@ static struct vpe *get_vpe(int minor) res = NULL; spin_lock(&vpecontrol.vpe_list_lock); list_for_each_entry(v, &vpecontrol.vpe_list, list) { - if (v->minor == minor) { + if (v->minor == VPE_MODULE_MINOR) { res = v; break; } @@ -171,7 +87,7 @@ static struct vpe *get_vpe(int minor) } /* get the vpe associated with this minor */ -static struct tc *get_tc(int index) +struct tc *get_tc(int index) { struct tc *res, *t; @@ -189,7 +105,7 @@ static struct tc *get_tc(int index) } /* allocate a vpe and associate it with this minor (or index) */ -static struct vpe *alloc_vpe(int minor) +struct vpe *alloc_vpe(int minor) { struct vpe *v; @@ -202,13 +118,13 @@ static struct vpe *alloc_vpe(int minor) spin_unlock(&vpecontrol.vpe_list_lock); INIT_LIST_HEAD(&v->notify); - v->minor = minor; + v->minor = VPE_MODULE_MINOR; return v; } /* allocate a tc. At startup only tc0 is running, all other can be halted. */ -static struct tc *alloc_tc(int index) +struct tc *alloc_tc(int index) { struct tc *tc; @@ -227,7 +143,7 @@ out: } /* clean up and free everything */ -static void release_vpe(struct vpe *v) +void release_vpe(struct vpe *v) { list_del(&v->list); if (v->load_addr) @@ -235,28 +151,8 @@ static void release_vpe(struct vpe *v) kfree(v); } -static void __maybe_unused dump_mtregs(void) -{ - unsigned long val; - - val = read_c0_config3(); - printk("config3 0x%lx MT %ld\n", val, - (val & CONFIG3_MT) >> CONFIG3_MT_SHIFT); - - val = read_c0_mvpcontrol(); - printk("MVPControl 0x%lx, STLB %ld VPC %ld EVP %ld\n", val, - (val & MVPCONTROL_STLB) >> MVPCONTROL_STLB_SHIFT, - (val & MVPCONTROL_VPC) >> MVPCONTROL_VPC_SHIFT, - (val & MVPCONTROL_EVP)); - - val = read_c0_mvpconf0(); - printk("mvpconf0 0x%lx, PVPE %ld PTC %ld M %ld\n", val, - (val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT, - val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); -} - /* Find some VPE program space */ -static void *alloc_progmem(unsigned long len) +void *alloc_progmem(unsigned long len) { void *addr; @@ -275,7 +171,7 @@ static void *alloc_progmem(unsigned long len) return addr; } -static void release_progmem(void *ptr) +void release_progmem(void *ptr) { #ifndef CONFIG_MIPS_VPE_LOADER_TOM kfree(ptr); @@ -317,7 +213,6 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr, for (i = 0; i < hdr->e_shnum; ++i) { Elf_Shdr *s = &sechdrs[i]; - // || strncmp(secstrings + s->sh_name, ".init", 5) == 0) if ((s->sh_flags & masks[m][0]) != masks[m][0] || (s->sh_flags & masks[m][1]) || s->sh_entsize != ~0UL) @@ -332,7 +227,6 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr, } } - /* from module-elf32.c, but subverted a little */ struct mips_hi16 { @@ -407,7 +301,7 @@ static int apply_r_mips_26(struct module *me, uint32_t *location, Elf32_Addr v) { if (v % 4) { - pr_debug("VPE loader: apply_r_mips_26 unaligned relocation\n"); + pr_debug("VPE loader: apply_r_mips_26: unaligned relocation\n"); return -ENOEXEC; } @@ -469,8 +363,8 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, /* * The value for the HI16 had best be the same. */ - if (v != l->value) { - pr_debug("VPE loader: apply_r_mips_lo16/hi16: \tinconsistent value information\n"); + if (v != l->value) { + pr_debug("VPE loader: apply_r_mips_lo16/hi16: inconsistent value information\n"); goto out_free; } @@ -567,7 +461,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs, if (!sym->st_value) { pr_debug("%s: undefined weak symbol %s\n", - me->name, strtab + sym->st_name); + me->name, strtab + sym->st_name); /* just print the warning, dont barf */ } @@ -593,8 +487,6 @@ static inline void save_gp_address(unsigned int secbase, unsigned int rel) } /* end module-elf32.c */ - - /* Change all symbols so that sh_value encodes the pointer directly. */ static void simplify_symbols(Elf_Shdr * sechdrs, unsigned int symindex, @@ -670,136 +562,6 @@ static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex, } #endif -#ifdef CONFIG_MIPS_CMP -#error CMP vpe_run() not implemented! -#else -/* We are prepared so configure and start the VPE... */ -static int vpe_run(struct vpe * v) -{ - unsigned long flags, val, dmt_flag; - struct vpe_notifications *n; - unsigned int vpeflags; - struct tc *t; - - /* check we are the Master VPE */ - local_irq_save(flags); - val = read_c0_vpeconf0(); - if (!(val & VPECONF0_MVP)) { - pr_warn("VPE loader: only Master VPE's are allowed to configure MT\n"); - local_irq_restore(flags); - - return -1; - } - - dmt_flag = dmt(); - vpeflags = dvpe(); - - if (!list_empty(&v->tc)) { - if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { - evpe(vpeflags); - emt(dmt_flag); - local_irq_restore(flags); - - pr_warn("VPE loader: TC %d is already in use.\n", - t->index); - return -ENOEXEC; - } - } else { - evpe(vpeflags); - emt(dmt_flag); - local_irq_restore(flags); - - pr_warn("VPE loader: No TC's associated with VPE %d\n", - v->minor); - - return -ENOEXEC; - } - - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - settc(t->index); - - /* should check it is halted, and not activated */ - if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) { - evpe(vpeflags); - emt(dmt_flag); - local_irq_restore(flags); - - pr_warn("VPE loader: TC %d is already active!\n", t->index); - - return -ENOEXEC; - } - - /* Write the address we want it to start running from in the TCPC register. */ - write_tc_c0_tcrestart((unsigned long)v->__start); - write_tc_c0_tccontext((unsigned long)0); - - /* - * Mark the TC as activated, not interrupt exempt and not dynamically - * allocatable - */ - val = read_tc_c0_tcstatus(); - val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A; - write_tc_c0_tcstatus(val); - - write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); - - /* - * The sde-kit passes 'memsize' to __start in $a3, so set something - * here... Or set $a3 to zero and define DFLT_STACK_SIZE and - * DFLT_HEAP_SIZE when you compile your program - */ - mttgpr(6, v->ntcs); - mttgpr(7, physical_memsize); - - /* set up VPE1 */ - /* - * bind the TC to VPE 1 as late as possible so we only have the final - * VPE registers to set up, and so an EJTAG probe can trigger on it - */ - write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1); - - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); - - back_to_back_c0_hazard(); - - /* Set up the XTC bit in vpeconf0 to point at our tc */ - write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC)) - | (t->index << VPECONF0_XTC_SHIFT)); - - back_to_back_c0_hazard(); - - /* enable this VPE */ - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); - - /* clear out any left overs from a previous program */ - write_vpe_c0_status(0); - write_vpe_c0_cause(0); - - /* take system out of configuration state */ - clear_c0_mvpcontrol(MVPCONTROL_VPC); - - /* - * SMTC/SMVP kernels manage VPE enable independently, - * but uniprocessor kernels need to turn it on, even - * if that wasn't the pre-dvpe() state. - */ -#ifdef CONFIG_SMP - evpe(vpeflags); -#else - evpe(EVPE_ENABLE); -#endif - emt(dmt_flag); - local_irq_restore(flags); - - list_for_each_entry(n, &v->notify, list) - n->start(minor); - - return 0; -} -#endif /* CONFIG_MIPS_CMP */ - static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, unsigned int symindex, const char *strtab, struct module *mod) @@ -835,7 +597,7 @@ static int vpe_elfload(struct vpe * v) long err = 0; char *secstrings, *strtab = NULL; unsigned int len, i, symindex = 0, strindex = 0, relocate = 0; - struct module mod; // so we can re-use the relocations code + struct module mod; /* so we can re-use the relocations code */ memset(&mod, 0, sizeof(struct module)); strcpy(mod.name, "VPE loader"); @@ -920,35 +682,36 @@ static int vpe_elfload(struct vpe * v) sechdrs[i].sh_addr); } - /* Fix up syms, so that st_value is a pointer to location. */ - simplify_symbols(sechdrs, symindex, strtab, secstrings, - hdr->e_shnum, &mod); + /* Fix up syms, so that st_value is a pointer to location. */ + simplify_symbols(sechdrs, symindex, strtab, secstrings, + hdr->e_shnum, &mod); - /* Now do relocations. */ - for (i = 1; i < hdr->e_shnum; i++) { - const char *strtab = (char *)sechdrs[strindex].sh_addr; - unsigned int info = sechdrs[i].sh_info; + /* Now do relocations. */ + for (i = 1; i < hdr->e_shnum; i++) { + const char *strtab = (char *)sechdrs[strindex].sh_addr; + unsigned int info = sechdrs[i].sh_info; - /* Not a valid relocation section? */ - if (info >= hdr->e_shnum) - continue; + /* Not a valid relocation section? */ + if (info >= hdr->e_shnum) + continue; - /* Don't bother with non-allocated sections */ - if (!(sechdrs[info].sh_flags & SHF_ALLOC)) - continue; + /* Don't bother with non-allocated sections */ + if (!(sechdrs[info].sh_flags & SHF_ALLOC)) + continue; - if (sechdrs[i].sh_type == SHT_REL) - err = apply_relocations(sechdrs, strtab, symindex, i, - &mod); - else if (sechdrs[i].sh_type == SHT_RELA) - err = apply_relocate_add(sechdrs, strtab, symindex, i, - &mod); - if (err < 0) - return err; + if (sechdrs[i].sh_type == SHT_REL) + err = apply_relocations(sechdrs, strtab, + symindex, i, &mod); + else if (sechdrs[i].sh_type == SHT_RELA) + err = apply_relocate_add(sechdrs, strtab, + symindex, i, &mod); + if (err < 0) + return err; - } - } else { - struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); + } + } else { + struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + + hdr->e_phoff); for (i = 0; i < hdr->e_phnum; i++) { if (phdr->p_type == PT_LOAD) { @@ -962,16 +725,20 @@ static int vpe_elfload(struct vpe * v) } for (i = 0; i < hdr->e_shnum; i++) { - /* Internal symbols and strings. */ - if (sechdrs[i].sh_type == SHT_SYMTAB) { - symindex = i; - strindex = sechdrs[i].sh_link; - strtab = (char *)hdr + sechdrs[strindex].sh_offset; - - /* mark the symtab's address for when we try to find the - magic symbols */ - sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; - } + /* Internal symbols and strings. */ + if (sechdrs[i].sh_type == SHT_SYMTAB) { + symindex = i; + strindex = sechdrs[i].sh_link; + strtab = (char *)hdr + + sechdrs[strindex].sh_offset; + + /* + * mark the symtab's address for when we try to + * find the magic symbols + */ + sechdrs[i].sh_addr = (size_t) hdr + + sechdrs[i].sh_offset; + } } } @@ -994,45 +761,6 @@ static int vpe_elfload(struct vpe * v) return 0; } -#ifdef CONFIG_MIPS_CMP -static void cleanup_tc(struct tc *tc) -{ - -} -#else -static void cleanup_tc(struct tc *tc) -{ - unsigned long flags; - unsigned int mtflags, vpflags; - int tmp; - - local_irq_save(flags); - mtflags = dmt(); - vpflags = dvpe(); - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - settc(tc->index); - tmp = read_tc_c0_tcstatus(); - - /* mark not allocated and not dynamically allocatable */ - tmp &= ~(TCSTATUS_A | TCSTATUS_DA); - tmp |= TCSTATUS_IXMT; /* interrupt exempt */ - write_tc_c0_tcstatus(tmp); - - write_tc_c0_tchalt(TCHALT_H); - mips_ihb(); - - /* bind it to anything other than VPE1 */ -// write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE - - clear_c0_mvpcontrol(MVPCONTROL_VPC); - evpe(vpflags); - emt(mtflags); - local_irq_restore(flags); -} -#endif - static int getcwd(char *buff, int size) { mm_segment_t old_fs; @@ -1056,14 +784,14 @@ static int vpe_open(struct inode *inode, struct file *filp) struct vpe *v; int ret; - if (minor != iminor(inode)) { + if (VPE_MODULE_MINOR != iminor(inode)) { /* assume only 1 device at the moment. */ pr_warning("VPE loader: only vpe1 is supported\n"); return -ENODEV; } - v = get_vpe(cpu_idx); + v = get_vpe(aprp_cpu_index()); if (v == NULL) { pr_warning("VPE loader: unable to get vpe\n"); @@ -1075,11 +803,11 @@ static int vpe_open(struct inode *inode, struct file *filp) pr_debug("VPE loader: tc in use dumping regs\n"); list_for_each_entry(not, &v->notify, list) { - not->stop(cpu_idx); + not->stop(aprp_cpu_index()); } release_progmem(v->load_addr); - cleanup_tc(get_tc(cpu_idx)); + cleanup_tc(get_tc(aprp_cpu_index())); } /* this of-course trashes what was there before... */ @@ -1112,7 +840,7 @@ static int vpe_release(struct inode *inode, struct file *filp) Elf_Ehdr *hdr; int ret = 0; - v = get_vpe(cpu_idx); + v = get_vpe(aprp_cpu_index()); if (v == NULL) return -ENODEV; @@ -1150,17 +878,16 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, size_t ret = count; struct vpe *v; - if (iminor(file->f_path.dentry->d_inode) != minor) + if (iminor(file->f_path.dentry->d_inode) != VPE_MODULE_MINOR) return -ENODEV; - v = get_vpe(cpu_idx); + v = get_vpe(aprp_cpu_index()); if (v == NULL) return -ENODEV; if ((count + v->len) > v->plen) { - printk(KERN_WARNING - "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + pr_warn("VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); return -ENOMEM; } @@ -1172,7 +899,7 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, return ret; } -static const struct file_operations vpe_fops = { +const struct file_operations vpe_fops = { .owner = THIS_MODULE, .open = vpe_open, .release = vpe_release, @@ -1180,96 +907,6 @@ static const struct file_operations vpe_fops = { .llseek = noop_llseek, }; -#ifndef CONFIG_MIPS_CMP -/* module wrapper entry points */ -/* give me a vpe */ -vpe_handle vpe_alloc(void) -{ - int i; - struct vpe *v; - - /* find a vpe */ - for (i = 1; i < MAX_VPES; i++) { - if ((v = get_vpe(i)) != NULL) { - v->state = VPE_STATE_INUSE; - return v; - } - } - return NULL; -} - -EXPORT_SYMBOL(vpe_alloc); - -/* start running from here */ -int vpe_start(vpe_handle vpe, unsigned long start) -{ - struct vpe *v = vpe; - - v->__start = start; - return vpe_run(v); -} - -EXPORT_SYMBOL(vpe_start); - -/* halt it for now */ -int vpe_stop(vpe_handle vpe) -{ - struct vpe *v = vpe; - struct tc *t; - unsigned int evpe_flags; - - evpe_flags = dvpe(); - - if ((t = list_entry(v->tc.next, struct tc, tc)) != NULL) { - - settc(t->index); - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); - } - - evpe(evpe_flags); - - return 0; -} - -EXPORT_SYMBOL(vpe_stop); - -/* I've done with it thank you */ -int vpe_free(vpe_handle vpe) -{ - struct vpe *v = vpe; - struct tc *t; - unsigned int evpe_flags; - - if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { - return -ENOEXEC; - } - - evpe_flags = dvpe(); - - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - settc(t->index); - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); - - /* halt the TC */ - write_tc_c0_tchalt(TCHALT_H); - mips_ihb(); - - /* mark the TC unallocated */ - write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A); - - v->state = VPE_STATE_UNUSED; - - clear_c0_mvpcontrol(MVPCONTROL_VPC); - evpe(evpe_flags); - - return 0; -} - -EXPORT_SYMBOL(vpe_free); -#endif /* CONFIG_MIPS_CMP */ - void *vpe_get_shared(int index) { struct vpe *v; @@ -1331,390 +968,6 @@ char *vpe_getcwd(int index) EXPORT_SYMBOL(vpe_getcwd); -#ifdef CONFIG_MIPS_CMP -static ssize_t store_kill(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(cpu_idx); - struct vpe_notifications *not; - - list_for_each_entry(not, &vpe->notify, list) { - not->stop(cpu_idx); - } - - release_progmem(vpe->load_addr); - vpe->state = VPE_STATE_UNUSED; - - return len; -} - -static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, - char *buf) -{ - struct vpe *vpe = get_vpe(cpu_idx); - - return sprintf(buf, "%d\n", vpe->ntcs); -} - -static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(cpu_idx); - unsigned long new; - int ret; - - ret = kstrtoul(buf, 0, &new); - if (ret < 0) - return ret; - - if (new != 1) - return -EINVAL; - - vpe->ntcs = new; - - return len; -} -#else -static ssize_t store_kill(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(cpu_idx); - struct vpe_notifications *not; - - list_for_each_entry(not, &vpe->notify, list) { - not->stop(cpu_idx); - } - - release_progmem(vpe->load_addr); - cleanup_tc(get_tc(cpu_idx)); - vpe_stop(vpe); - vpe_free(vpe); - - return len; -} - -static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, - char *buf) -{ - struct vpe *vpe = get_vpe(cpu_idx); - - return sprintf(buf, "%d\n", vpe->ntcs); -} - -static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(cpu_idx); - unsigned long new; - int ret; - - ret = kstrtoul(buf, 0, &new); - if (ret < 0) - return ret; - - if (new == 0 || new > (hw_tcs - cpu_idx)) - return -EINVAL; - - vpe->ntcs = new; - - return len; -} -#endif /* CONFIG_MIPS_CMP */ - -static struct device_attribute vpe_class_attributes[] = { - __ATTR(kill, S_IWUSR, NULL, store_kill), - __ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs), - {} -}; - -static void vpe_device_release(struct device *cd) -{ - kfree(cd); -} - -struct class vpe_class = { - .name = "vpe", - .owner = THIS_MODULE, - .dev_release = vpe_device_release, - .dev_attrs = vpe_class_attributes, -}; - -struct device vpe_device; - -#ifdef CONFIG_MIPS_CMP -static int __init vpe_module_init(void) -{ - struct vpe *v = NULL; - struct tc *t; - int err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - cpu_idx = setup_max_cpus; - - if (num_possible_cpus() - cpu_idx < 1) { - pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" - "Pass maxcpus= argument as kernel argument\n"); - return -ENODEV; - } - - major = register_chrdev(0, module_name, &vpe_fops); - if (major < 0) { - pr_warn("VPE loader: unable to register character device\n"); - return major; - } - - err = class_register(&vpe_class); - if (err) { - pr_err("vpe_class registration failed\n"); - goto out_chrdev; - } - - device_initialize(&vpe_device); - vpe_device.class = &vpe_class, - vpe_device.parent = NULL, - dev_set_name(&vpe_device, "vpe_sp"); - vpe_device.devt = MKDEV(major, minor); - err = device_add(&vpe_device); - if (err) { - pr_err("Adding vpe_device failed\n"); - goto out_class; - } - - t = alloc_tc(cpu_idx); - if (!t) { - pr_warn("VPE: unable to allocate TC\n"); - err = -ENOMEM; - goto out; - } - - /* VPE */ - v = alloc_vpe(cpu_idx); - if (v == NULL) { - pr_warn("VPE: unable to allocate VPE\n"); - kfree(t); - err = -ENOMEM; - goto out; - } - - v->ntcs = 1; - - /* add the tc to the list of this vpe's tc's. */ - list_add(&t->tc, &v->tc); - - /* TC */ - t->pvpe = v; /* set the parent vpe */ - - return 0; - -out_class: - class_unregister(&vpe_class); -out_chrdev: - unregister_chrdev(major, module_name); - -out: - return err; -} -#else -static int __init vpe_module_init(void) -{ - unsigned int mtflags, vpflags; - unsigned long flags, val; - struct vpe *v = NULL; - struct tc *t; - int tc, err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - if (vpelimit == 0) { - pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" - "Pass maxvpes= argument as kernel argument\n"); - - return -ENODEV; - } - - cpu_idx = tclimit; - - if (cpu_idx == 0) { - pr_warn("No TCs reserved for AP/SP, not initialize VPE loader\n" - "Pass maxtcs= argument as kernel argument\n"); - - return -ENODEV; - } - - major = register_chrdev(0, module_name, &vpe_fops); - if (major < 0) { - pr_warn("VPE loader: unable to register character device\n"); - return major; - } - - err = class_register(&vpe_class); - if (err) { - pr_err("vpe_class registration failed\n"); - goto out_chrdev; - } - - device_initialize(&vpe_device); - vpe_device.class = &vpe_class, - vpe_device.parent = NULL, - dev_set_name(&vpe_device, "vpe1"); - vpe_device.devt = MKDEV(major, minor); - err = device_add(&vpe_device); - if (err) { - pr_err("Adding vpe_device failed\n"); - goto out_class; - } - - local_irq_save(flags); - mtflags = dmt(); - vpflags = dvpe(); - - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - /* dump_mtregs(); */ - - val = read_c0_mvpconf0(); - hw_tcs = (val & MVPCONF0_PTC) + 1; - hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; - - for (tc = cpu_idx; tc < hw_tcs; tc++) { - /* - * Must re-enable multithreading temporarily or in case we - * reschedule send IPIs or similar we might hang. - */ - clear_c0_mvpcontrol(MVPCONTROL_VPC); - evpe(vpflags); - emt(mtflags); - local_irq_restore(flags); - t = alloc_tc(tc); - if (!t) { - err = -ENOMEM; - goto out; - } - - local_irq_save(flags); - mtflags = dmt(); - vpflags = dvpe(); - set_c0_mvpcontrol(MVPCONTROL_VPC); - - /* VPE's */ - if (tc < hw_tcs) { - settc(tc); - - v = alloc_vpe(tc); - if (v == NULL) { - pr_warn("VPE: unable to allocate VPE\n"); - - goto out_reenable; - } - - v->ntcs = hw_tcs - cpu_idx; - - /* add the tc to the list of this vpe's tc's. */ - list_add(&t->tc, &v->tc); - - /* deactivate all but vpe0 */ - if (tc >= cpu_idx) { - unsigned long tmp = read_vpe_c0_vpeconf0(); - - tmp &= ~VPECONF0_VPA; - - /* master VPE */ - tmp |= VPECONF0_MVP; - write_vpe_c0_vpeconf0(tmp); - } - - /* disable multi-threading with TC's */ - write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); - - if (tc >= vpelimit) { - /* - * Set config to be the same as vpe0, - * particularly kseg0 coherency alg - */ - write_vpe_c0_config(read_c0_config()); - } - } - - /* TC's */ - t->pvpe = v; /* set the parent vpe */ - - if (tc >= cpu_idx) { - unsigned long tmp; - - settc(tc); - - /* Any TC that is bound to VPE0 gets left as is - in case - we are running SMTC on VPE0. A TC that is bound to any - other VPE gets bound to VPE0, ideally I'd like to make - it homeless but it doesn't appear to let me bind a TC - to a non-existent VPE. Which is perfectly reasonable. - - The (un)bound state is visible to an EJTAG probe so may - notify GDB... - */ - - if (((tmp = read_tc_c0_tcbind()) & TCBIND_CURVPE)) { - /* tc is bound >vpe0 */ - write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE); - - t->pvpe = get_vpe(0); /* set the parent vpe */ - } - - /* halt the TC */ - write_tc_c0_tchalt(TCHALT_H); - mips_ihb(); - - tmp = read_tc_c0_tcstatus(); - - /* mark not activated and not dynamically allocatable */ - tmp &= ~(TCSTATUS_A | TCSTATUS_DA); - tmp |= TCSTATUS_IXMT; /* interrupt exempt */ - write_tc_c0_tcstatus(tmp); - } - } - -out_reenable: - /* release config state */ - clear_c0_mvpcontrol(MVPCONTROL_VPC); - - evpe(vpflags); - emt(mtflags); - local_irq_restore(flags); - - return 0; - -out_class: - class_unregister(&vpe_class); -out_chrdev: - unregister_chrdev(major, module_name); - -out: - return err; -} -#endif /* CONFIG_MIPS_CMP */ - -static void __exit vpe_module_exit(void) -{ - struct vpe *v, *n; - - device_del(&vpe_device); - unregister_chrdev(major, module_name); - - /* No locking needed here */ - list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) { - if (v->state != VPE_STATE_UNUSED) - release_vpe(v); - } -} - module_init(vpe_module_init); module_exit(vpe_module_exit); MODULE_DESCRIPTION("MIPS VPE Loader"); -- 1.7.1 From dczhu@mips.com Mon Jan 7 19:06:00 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jan 2013 19:06:53 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:44305 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823034Ab3AGSGA32i0e (ORCPT ); Mon, 7 Jan 2013 19:06:00 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r07I5roY030386; Mon, 7 Jan 2013 10:05:54 -0800 X-WSS-ID: 0MG9OXQ-01-2WH-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 27C7536465B; Mon, 7 Jan 2013 10:05:50 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.2.247.3; Mon, 7 Jan 2013 10:05:46 -0800 From: Deng-Cheng Zhu To: , , , , CC: , Subject: [RESEND PATCH v3 3/5] MIPS: APRP (APSP): remove kspd.h Date: Mon, 7 Jan 2013 10:05:12 -0800 Message-ID: <1357581914-4589-4-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1357581914-4589-1-git-send-email-dczhu@mips.com> References: <1357581914-4589-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: XH9gudUC4gK9Wz1hVklPNg== X-archive-position: 35387 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1492 Lines: 50 Now that KSPD is gone, kspd.h has no reason to be there. Cc: Steven J. Hill Signed-off-by: Deng-Cheng Zhu --- arch/mips/include/asm/kspd.h | 32 -------------------------------- 1 files changed, 0 insertions(+), 32 deletions(-) delete mode 100644 arch/mips/include/asm/kspd.h diff --git a/arch/mips/include/asm/kspd.h b/arch/mips/include/asm/kspd.h deleted file mode 100644 index ec68329..0000000 --- a/arch/mips/include/asm/kspd.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ - -#ifndef _ASM_KSPD_H -#define _ASM_KSPD_H - -struct kspd_notifications { - void (*kspd_sp_exit)(int sp_id); - - struct list_head list; -}; - -static inline void kspd_notify(struct kspd_notifications *notify) -{ -} - -#endif -- 1.7.1 From dczhu@mips.com Mon Jan 7 19:06:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jan 2013 19:07:14 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:44307 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823046Ab3AGSGFgIAi6 (ORCPT ); Mon, 7 Jan 2013 19:06:05 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r07I5xsv030390; Mon, 7 Jan 2013 10:05:59 -0800 X-WSS-ID: 0MG9OXV-01-2WI-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 26CAD36464E; Mon, 7 Jan 2013 10:05:55 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.2.247.3; Mon, 7 Jan 2013 10:05:51 -0800 From: Deng-Cheng Zhu To: , , , , CC: , Subject: [RESEND PATCH v3 4/5] MIPS: let amon_cpu_start() report results Date: Mon, 7 Jan 2013 10:05:13 -0800 Message-ID: <1357581914-4589-5-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1357581914-4589-1-git-send-email-dczhu@mips.com> References: <1357581914-4589-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: gnDsv3oBvgs1AvuMAPA5lA== X-archive-position: 35388 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1524 Lines: 56 Change the return type of amon_cpu_start() from void to int. Cc: Steven J. Hill Signed-off-by: Deng-Cheng Zhu --- arch/mips/include/asm/amon.h | 2 +- arch/mips/mti-malta/malta-amon.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/amon.h b/arch/mips/include/asm/amon.h index c3dc1a6..c8af6b0 100644 --- a/arch/mips/include/asm/amon.h +++ b/arch/mips/include/asm/amon.h @@ -3,5 +3,5 @@ */ int amon_cpu_avail(int); -void amon_cpu_start(int, unsigned long, unsigned long, +int amon_cpu_start(int, unsigned long, unsigned long, unsigned long, unsigned long); diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index 469d9b0..fcd69cb 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c @@ -48,7 +48,7 @@ int amon_cpu_avail(int cpu) return 1; } -void amon_cpu_start(int cpu, +int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp, unsigned long gp, unsigned long a0) { @@ -56,10 +56,10 @@ void amon_cpu_start(int cpu, (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); if (!amon_cpu_avail(cpu)) - return; + return -1; if (cpu == smp_processor_id()) { pr_debug("launch: I am cpu%d!\n", cpu); - return; + return -1; } launch += cpu; @@ -78,4 +78,6 @@ void amon_cpu_start(int cpu, ; smp_rmb(); /* Target will be updating flags soon */ pr_debug("launch: cpu%d gone!\n", cpu); + + return 0; } -- 1.7.1 From dczhu@mips.com Mon Jan 7 19:06:10 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jan 2013 19:07:42 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:44311 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822501Ab3AGSGKmJ3Kz (ORCPT ); Mon, 7 Jan 2013 19:06:10 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r07I64G5030394; Mon, 7 Jan 2013 10:06:04 -0800 X-WSS-ID: 0MG9OY0-01-2WJ-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 26D0636464E; Mon, 7 Jan 2013 10:06:00 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.2.247.3; Mon, 7 Jan 2013 10:05:56 -0800 From: Deng-Cheng Zhu To: , , , , CC: , Subject: [RESEND PATCH v3 5/5] MIPS: APRP (APSP): malta board support Date: Mon, 7 Jan 2013 10:05:14 -0800 Message-ID: <1357581914-4589-6-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1357581914-4589-1-git-send-email-dczhu@mips.com> References: <1357581914-4589-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: cirqJNRCtQ0vG6JiHl3CRQ== X-archive-position: 35389 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3246 Lines: 117 APRP is supposed to be platform independent, however, this patch is needed for Malta for various reasons, see code and code comments. Cc: Steven J. Hill Signed-off-by: Deng-Cheng Zhu --- .../include/asm/mach-malta/cpu-feature-overrides.h | 3 ++ arch/mips/kernel/vpe-cmp.c | 17 +++++++++++++++ arch/mips/mti-malta/malta-int.c | 22 +++++++++++++++++++- 3 files changed, 41 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h index 37e3583..0bf3872 100644 --- a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h @@ -17,6 +17,9 @@ #define cpu_has_tlb 1 #define cpu_has_4kex 1 #define cpu_has_4k_cache 1 +#ifdef CONFIG_MIPS_SP_FP_INTENSIVE +#define cpu_has_fpu 0 +#endif /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 diff --git a/arch/mips/kernel/vpe-cmp.c b/arch/mips/kernel/vpe-cmp.c index 9d0c375..20f4497 100644 --- a/arch/mips/kernel/vpe-cmp.c +++ b/arch/mips/kernel/vpe-cmp.c @@ -25,7 +25,24 @@ static int major; +#ifdef CONFIG_MIPS_MALTA +#include + +int vpe_run(struct vpe *v) +{ + struct vpe_notifications *n; + + if (amon_cpu_start(aprp_cpu_index(), v->__start, 0, 0, 0) < 0) + return -1; + + list_for_each_entry(n, &v->notify, list) + n->start(VPE_MODULE_MINOR); + + return 0; +} +#else #error CMP vpe_run() not implemented! +#endif void cleanup_tc(struct tc *tc) { diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 647b863..cddda99 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -1,6 +1,6 @@ /* * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2000, 2001, 2004, 2012 MIPS Technologies, Inc. * Copyright (C) 2001 Ralf Baechle * * This program is free software; you can distribute it and/or modify it @@ -45,6 +45,9 @@ #include #include #include +#ifdef CONFIG_MIPS_VPE_APSP_API +#include +#endif int gcmp_present = -1; int gic_present; @@ -128,6 +131,15 @@ static void malta_hw0_irqdispatch(void) } do_IRQ(MALTA_INT_BASE + irq); + +#if defined(CONFIG_MIPS_VPE_APSP_API) && !defined(CONFIG_MIPS_CMP) + /* + * When sw0 gets set, a spurious hw interrupt is signaled as well. + * The sw0 will not be handled until the hw interrupt is cleared. + * We use the hook to handle sw0 and the hw interrupt gets cleared. + */ + aprp_hook(); +#endif } static void malta_ipi_irqdispatch(void) @@ -312,6 +324,10 @@ static void ipi_call_dispatch(void) static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) { +#if defined(CONFIG_MIPS_VPE_APSP_API) && defined(CONFIG_MIPS_CMP) + aprp_hook(); +#endif + scheduler_ipi(); return IRQ_HANDLED; @@ -622,6 +638,10 @@ void __init arch_init_irq(void) arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); #endif } + +#ifdef CONFIG_MIPS_VPE_APSP_API + aprp_hook = null_aprp_hook; +#endif } void malta_be_init(void) -- 1.7.1 From herton.krzesinski@canonical.com Mon Jan 7 21:39:07 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jan 2013 21:39:11 +0100 (CET) Received: from youngberry.canonical.com ([91.189.89.112]:36167 "EHLO youngberry.canonical.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817128Ab3AGUjHvO1QA (ORCPT ); Mon, 7 Jan 2013 21:39:07 +0100 Received: from 189.114.234.143.dynamic.adsl.gvt.net.br ([189.114.234.143] helo=canonical.com) by youngberry.canonical.com with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1TsJTJ-0003EV-Ii; Mon, 07 Jan 2013 20:39:02 +0000 From: Herton Ronaldo Krzesinski To: Huacai Chen Cc: Hongliang Tao , Hua Yan , Yong Zhang , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Fuxin Zhang , Zhangjin Wu , Ralf Baechle , Herton Ronaldo Krzesinski , kernel-team@lists.ubuntu.com Subject: [ 3.5.y.z extended stable ] Patch "MIPS: Fix poweroff failure when HOTPLUG_CPU configured." has been added to staging queue Date: Mon, 7 Jan 2013 18:38:56 -0200 Message-Id: <1357591136-22589-1-git-send-email-herton.krzesinski@canonical.com> X-Mailer: git-send-email 1.7.9.5 X-Extended-Stable: 3.5 X-archive-position: 35390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herton.krzesinski@canonical.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2297 Lines: 67 This is a note to let you know that I have just added a patch titled MIPS: Fix poweroff failure when HOTPLUG_CPU configured. to the linux-3.5.y-queue branch of the 3.5.y.z extended stable tree which can be found at: http://kernel.ubuntu.com/git?p=ubuntu/linux.git;a=shortlog;h=refs/heads/linux-3.5.y-queue If you, or anyone else, feels it should not be added to this tree, please reply to this email. For more information about the 3.5.y.z tree, see https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable Thanks. -Herton ------ >From 81d3bedcd96bc0c48c5e8dec5193719bbce7511f Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Mon, 13 Aug 2012 20:52:24 +0800 Subject: [PATCH] MIPS: Fix poweroff failure when HOTPLUG_CPU configured. commit 8add1ecb81f541ef2fcb0b85a5470ad9ecfb4a84 upstream. When poweroff machine, kernel_power_off() call disable_nonboot_cpus(). And if we have HOTPLUG_CPU configured, disable_nonboot_cpus() is not an empty function but attempt to actually disable the nonboot cpus. Since system state is SYSTEM_POWER_OFF, play_dead() won't be called and thus disable_nonboot_cpus() hangs. Therefore, we make this patch to avoid poweroff failure. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan Cc: Yong Zhang Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Fuxin Zhang Cc: Zhangjin Wu Patchwork: https://patchwork.linux-mips.org/patch/4211/ Signed-off-by: Ralf Baechle Signed-off-by: Herton Ronaldo Krzesinski --- arch/mips/kernel/process.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index e9a5fd7..69b17a9 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -72,9 +72,7 @@ void __noreturn cpu_idle(void) } } #ifdef CONFIG_HOTPLUG_CPU - if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map) && - (system_state == SYSTEM_RUNNING || - system_state == SYSTEM_BOOTING)) + if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map)) play_dead(); #endif rcu_idle_exit(); -- 1.7.9.5 From srivatsa.bhat@linux.vnet.ibm.com Tue Jan 8 07:57:53 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jan 2013 07:57:54 +0100 (CET) Received: from e23smtp04.au.ibm.com ([202.81.31.146]:46042 "EHLO e23smtp04.au.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823003Ab3AHG5xL9XhY (ORCPT ); Tue, 8 Jan 2013 07:57:53 +0100 Received: from /spool/local by e23smtp04.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 8 Jan 2013 16:50:21 +1000 Received: from d23relay05.au.ibm.com (d23relay05.au.ibm.com [9.190.235.152]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id 867A62CE804A; Tue, 8 Jan 2013 17:57:37 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay05.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r086jxBJ58851496; Tue, 8 Jan 2013 17:45:59 +1100 Received: from d23av03.au.ibm.com (loopback [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r086vYQe022837; Tue, 8 Jan 2013 17:57:36 +1100 Received: from srivatsabhat.in.ibm.com (srivatsabhat.in.ibm.com [9.124.35.111] (may be forged)) by d23av03.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id r086vTw4022727; Tue, 8 Jan 2013 17:57:30 +1100 Message-ID: <50EBC2F9.70303@linux.vnet.ibm.com> Date: Tue, 08 Jan 2013 12:25:53 +0530 From: "Srivatsa S. Bhat" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: Russell King - ARM Linux CC: Srivatsa Vaddagiri , linux-mips@linux-mips.org, linux-sh@vger.kernel.org, mhocko@suse.cz, "H. Peter Anvin" , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, x86@kernel.org, Ingo Molnar , "Paul E. McKenney" , Mike Frysinger , linux-arm-msm@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Stephen Boyd , linux-kernel@vger.kernel.org, Ralf Baechle , Paul Mundt , Martin Schwidefsky , uclinux-dist-devel@blackfin.uclinux.org, linuxppc-dev@lists.ozlabs.org, "David S. Miller" , Nikunj A Dadhania , Peter Zijlstra , "rusty@rustcorp.com.au" Subject: Re: [PATCH 1/2] cpuhotplug/nohz: Remove offline cpus from nohz-idle state References: <1357268318-7993-1-git-send-email-vatsa@codeaurora.org> <20130105103627.GU2631@n2100.arm.linux.org.uk> In-Reply-To: <20130105103627.GU2631@n2100.arm.linux.org.uk> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13010806-9264-0000-0000-000002F4F48B X-archive-position: 35391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: srivatsa.bhat@linux.vnet.ibm.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1796 Lines: 39 On 01/05/2013 04:06 PM, Russell King - ARM Linux wrote: > On Thu, Jan 03, 2013 at 06:58:38PM -0800, Srivatsa Vaddagiri wrote: >> I also think that the >> wait_for_completion() based wait in ARM's __cpu_die() can be replaced with a >> busy-loop based one, as the wait there in general should be terminated within >> few cycles. > > Why open-code this stuff when we have infrastructure already in the kernel > for waiting for stuff to happen? I chose to use the standard infrastructure > because its better tested, and avoids having to think about whether we need > CPU barriers and such like to ensure that updates are seen in a timely > manner. > > My stance on a lot of this idle/cpu dying code is that much of it can > probably be cleaned up and merged into a single common implementation - > in which case the use of standard infrastructure for things like waiting > for other CPUs do stuff is even more justified. On similar lines, Nikunj (in CC) and I had posted a patchset sometime ago to consolidate some of the CPU hotplug related code in the various architectures into a common standard implementation [1]. However, we ended up hitting a problem with Xen, because its existing code was unlike the other arch/ pieces [2]. At that time, we decided that we will first make the CPU online and offline paths symmetric in the generic code and then provide a common implementation of the duplicated bits in arch/, for the new CPU hotplug model [3]. I guess we should probably revisit it sometime, consolidating the code in incremental steps if not all at a time... -- [1]. http://lwn.net/Articles/500185/ [2]. http://thread.gmane.org/gmane.linux.kernel.cross-arch/14342/focus=14430 [3]. http://thread.gmane.org/gmane.linux.kernel.cross-arch/14342/focus=15567 Regards, Srivatsa S. Bhat From juhosg@openwrt.org Tue Jan 8 08:14:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jan 2013 10:57:29 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:60599 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822664Ab3AHHO1fUp7q (ORCPT ); Tue, 8 Jan 2013 08:14:27 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 3396B258B42; Tue, 8 Jan 2013 08:14:22 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HCzsSkAV0056; Tue, 8 Jan 2013 08:14:22 +0100 (CET) Received: from [127.0.0.1] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by phoenix3.szarvasnet.hu (Postfix) with ESMTPSA id 8C758258B3B; Tue, 8 Jan 2013 08:14:21 +0100 (CET) Message-ID: <50EBC74C.6070602@openwrt.org> Date: Tue, 08 Jan 2013 08:14:20 +0100 From: Gabor Juhos User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Ralf Baechle CC: Grant Likely , John Crispin , Thomas Gleixner , Dezhong Diao , Geert Uytterhoeven , David Daney , linux-mips@linux-mips.org, Daniel Schwierzeck , u-boot@lists.denx.de Subject: Proposal for an interface to pass a DT to the kernel on MIPS X-Enigmail-Version: 1.4.6 Content-Type: multipart/mixed; boundary="------------090002030000070605090100" X-Antivirus: avast! (VPS 130107-1, 2013.01.07), Outbound message X-Antivirus-Status: Clean X-archive-position: 35392 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13030 Lines: 379 This is a multi-part message in MIME format. --------------090002030000070605090100 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sorry for the duplicated post. The first version did not go through to the e-mail addresses at the linux-mips.org domain due to problems with the SMTP server. --- Hi Everyone! I'm working on adding device tree support for the ath79 platform. I have experimental patches for several things already however my main problem currently is how the DT should be passed to the kernel. There were a thread [1] about that on the lmo list in 2011 already, but there were no clear statements about the correct method. I'm using a simple approach during my tests to resolve this problem. The bootloader puts a magic value to the 'a0' register and the address of the FDT blob is stored in the 'a1' register. I have created the attached patch for U-Boot and that that implements this method. It is against the 'testing' branch of the MIPS U-Boot Custodian Tree [2]. I would like to hear others' opinion about it, before I would invest too much time into an unusable solution. :) Regards, Gabor 1. http://www.linux-mips.org/archives/linux-mips/2011-06/msg00059.html 2. git://git.denx.de/u-boot-mips.git 3. bootlog with the patched U-Boot: > U-Boot> setenv bootargs 'console=ttyATH0,115200 init=/etc/preinit' > U-Boot> setenv serverip 192.168.1.254; setenv ipaddr 192.168.1.1 > U-Boot> tftp 0xa0800000 tl-wr703n.dtb > dup 1 speed 100 > Using eth0 device > TFTP from server 192.168.1.254; our IP address is 192.168.1.1 > Filename 'tl-wr703n.dtb'. > Load address: 0xa0800000 > Loading: # > done > Bytes transferred = 1957 (7a5 hex) > U-Boot> tftp 0xa0900000 openwrt-ath79-uImage-initramfs-lzma.bin > Using eth0 device > TFTP from server 192.168.1.254; our IP address is 192.168.1.1 > Filename 'openwrt-ath79-uImage-initramfs-lzma.bin'. > Load address: 0xa0900000 > Loading: ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ########################################################### > done > Bytes transferred = 2627551 (2817df hex) > U-Boot> bootm 0xa0900000 - 0xa0800000 > ## Booting kernel from Legacy Image at a0900000 ... > Image Name: MIPS OpenWrt Linux-3.8-rc2 > Created: 2013-01-07 19:54:05 UTC > Image Type: MIPS Linux Kernel Image (lzma compressed) > Data Size: 2627487 Bytes = 2.5 MiB > Load Address: 80060000 > Entry Point: 80060000 > Verifying Checksum ... OK > ## Flattened Device Tree blob at a0800000 > Booting using the fdt blob at 0xa0800000 > Uncompressing Kernel Image ... OK > Loading Device Tree to 81f72000, end 81f757a4 ... OK > > Starting kernel ... > > Linux version 3.8.0-rc2 (juhosg@mag2) (gcc version 4.6.4 20121106 (prerelease) (Linaro GCC 4.6-2012.11) ) #456 Mon Jan 7 20:53:57 CET 2013 > ath79: using Device Tree passed by bootloader > bootconsole [early0] enabled > CPU revision is: 00019374 (MIPS 24Kc) > SoC: Atheros AR9330 rev 1 > Clocks: CPU:400.000MHz, DDR:400.000MHz, AHB:200.000MHz, Ref:25.000MHz > Determined physical RAM map: > memory: 02000000 @ 80000000 (usable) > memory: 02000000 @ 00000000 (usable) > Initrd not found or empty - disabling initrd > Zone ranges: > Normal [mem 0x00000000-0x1fffffff] > Movable zone start for each node > Early memory node ranges > node 0: [mem 0x00000000-0x01ffffff] > Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes. > Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes > Built 1 zonelists in Zone order, mobility grouping on. Total pages: 8128 > Kernel command line: console=ttyATH0,115200 init=/etc/preinit rootfstype=squashfs,yaffs,jffs2 noinitrd > PID hash table entries: 128 (order: -3, 512 bytes) > Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) > Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) > __ex_table already sorted, skipping sort > Writing ErrCtl register=00000000 > Readback ErrCtl register=00000000 > Memory: 26784k/32768k available (2682k kernel code, 5984k reserved, 822k data, 1548k init, 0k highmem) > SLUB: Genslabs=9, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 > NR_IRQS:51 > Calibrating delay loop... 265.42 BogoMIPS (lpj=1327104) > pid_max: default: 32768 minimum: 301 > Mount-cache hash table entries: 512 > NET: Registered protocol family 16 > ATH79: using Flattened Device Tree > bio: create slab at 0 > cfg80211: Calling CRDA to update world regulatory domain > Switching to clocksource MIPS > NET: Registered protocol family 2 > TCP established hash table entries: 512 (order: 0, 4096 bytes) > TCP bind hash table entries: 512 (order: -1, 2048 bytes) > TCP: Hash tables configured (established 512 bind 512) > TCP: reno registered > UDP hash table entries: 256 (order: 0, 4096 bytes) > UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) > NET: Registered protocol family 1 > squashfs: version 4.0 (2009/01/31) Phillip Lougher > jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc. > msgmni has been set to 52 > io scheduler noop registered > io scheduler deadline registered (default) > Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled > 18020000.uart: ttyATH0 at MMIO 0x18020000 (irq = 11) is a AR933X UART > console [ttyATH0] enabled, bootconsole disabled > console [ttyATH0] enabled, bootconsole disabled > ieee80211 phy0: Atheros AR9330 Rev:0 mem=0xb8100000, irq=2 > TCP: cubic registered > NET: Registered protocol family 17 > 8021q: 802.1Q VLAN Support v1.8 > Freeing unused kernel memory: 1548k freed > input: buttons.3 as /devices/buttons.3/input/input0 > - preinit - > Press the [f] key and hit [enter] to enter failsafe mode > - regular preinit - > - init - > SCSI subsystem initialized > usbcore: registered new interface driver usbfs > usbcore: registered new interface driver hub > usbcore: registered new device driver usb > PPP generic driver version 2.4.2 > ip_tables: (C) 2000-2006 Netfilter Core Team > NET: Registered protocol family 24 > ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver > nf_conntrack version 0.5.0 (442 buckets, 1768 max) > ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver > Initializing USB Mass Storage driver... > usbcore: registered new interface driver usb-storage > USB Mass Storage support registered. > usbcore: registered new interface driver ums-alauda > usbcore: registered new interface driver ums-cypress > usbcore: registered new interface driver ums-datafab > usbcore: registered new interface driver ums-freecom > usbcore: registered new interface driver ums-isd200 > usbcore: registered new interface driver ums-jumpshot > usbcore: registered new interface driver ums-karma > usbcore: registered new interface driver ums-sddr09 > usbcore: registered new interface driver ums-sddr55 > usbcore: registered new interface driver ums-usbat > > Please press Enter to activate this console. > > > BusyBox v1.19.4 (2013-01-06 20:43:13 CET) built-in shell (ash) > Enter 'help' for a list of built-in commands. > > _______ ________ __ > | |.-----.-----.-----.| | | |.----.| |_ > | - || _ | -__| || | | || _|| _| > |_______|| __|_____|__|__||________||__| |____| > |__| W I R E L E S S F R E E D O M > ----------------------------------------------------- > BARRIER BREAKER (Bleeding Edge, r35026) > ----------------------------------------------------- > * 1/2 oz Galliano Pour all ingredients into > * 4 oz cold Coffee an irish coffee mug filled > * 1 1/2 oz Dark Rum with crushed ice. Stir. > * 2 tsp. Creme de Cacao > ----------------------------------------------------- > root@OpenWrt:/# --------------090002030000070605090100 Content-Type: text/x-patch; name="0001-MIPS-bootm.c-add-support-for-passing-device-tree-to-.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0001-MIPS-bootm.c-add-support-for-passing-device-tree-to-.pa"; filename*1="tch" >From 40fd1ec80a4396faf85013c66004f8d95ed3c554 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 3 Jan 2013 21:19:11 +0100 Subject: [PATCH] MIPS: bootm.c: add support for passing device-tree to Linux Signed-off-by: Gabor Juhos --- arch/mips/include/asm/config.h | 1 + arch/mips/lib/bootm.c | 121 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 120 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h index 02fbfb3..82c4148 100644 --- a/arch/mips/include/asm/config.h +++ b/arch/mips/include/asm/config.h @@ -22,5 +22,6 @@ #define _ASM_CONFIG_H_ #define CONFIG_NEEDS_MANUAL_RELOC +#define CONFIG_LMB #endif diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index a36154a..e57066c 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -27,6 +27,9 @@ #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -43,7 +46,36 @@ static int linux_env_idx; static void linux_params_init(ulong start, char *commandline); static void linux_env_set(char *env_name, char *env_val); -static void boot_prep_linux(bootm_headers_t *images) +static ulong arch_get_sp(void) +{ + ulong ret; + + asm("move %0, $sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + ulong sp; + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + sp = arch_get_sp(); + debug("## Current stack ends at 0x%08lx\n", sp); + + /* adjust sp by 4K to be safe */ + sp -= 4096; + lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp); +} + +static void boot_prep_linux_legacy(bootm_headers_t *images) { char *commandline = getenv("bootargs"); char env_buf[12]; @@ -83,9 +115,90 @@ static void boot_prep_linux(bootm_headers_t *images) linux_env_set("eth1addr", cp); } +#ifdef CONFIG_OF_LIBFDT +static int boot_get_ft_len(bootm_headers_t *images) +{ + return images->ft_len; +} + +static char *boot_get_ft_addr(bootm_headers_t *images) +{ + return images->ft_addr; +} + +static int create_fdt(bootm_headers_t *images) +{ + ulong of_size = images->ft_len; + char **of_flat_tree = &images->ft_addr; + ulong *initrd_start = &images->initrd_start; + ulong *initrd_end = &images->initrd_end; + struct lmb *lmb = &images->lmb; + ulong rd_len; + int ret; + + boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); + + ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); + if (ret) + return ret; + + fdt_chosen(*of_flat_tree, 1); + fdt_fixup_memory(*of_flat_tree, CONFIG_SYS_SDRAM_BASE, gd->ram_size); + fdt_fixup_ethernet(*of_flat_tree); + fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); + +#ifdef CONFIG_OF_BOARD_SETUP + ft_board_setup(*of_flat_tree, gd->bd); +#endif + + return 0; +} + +static int boot_prep_linux_fdt(bootm_headers_t *images) +{ + if (!images->ft_len) + return -1; + + debug("using: FDT\n"); + if (create_fdt(images)) { + printf("FDT creation failed! hanging..."); + hang(); + } + + return 0; +} +#else +static inline int boot_get_ft_len(bootm_headers_t *images) +{ + return 0; +} + +static inline char **boot_get_ft_addr(bootm_headers_t *images) +{ + return 0; +} + +static inline int boot_prep_linux_fdt(bootm_headers_t *images) +{ + return -1; +} +#endif /* CONFIG_OF_LIBFDT */ + +static void boot_prep_linux(bootm_headers_t *images) +{ + int ret; + + ret = boot_prep_linux_fdt(images); + if (!ret) + return; + + boot_prep_linux_legacy(images); +} + static void boot_jump_linux(bootm_headers_t *images) { void (*theKernel) (int, char **, char **, int *); + ulong ft_len; /* find kernel entry point */ theKernel = (void (*)(int, char **, char **, int *))images->ep; @@ -98,7 +211,11 @@ static void boot_jump_linux(bootm_headers_t *images) /* we assume that the kernel is in place */ printf("\nStarting kernel ...\n\n"); - theKernel(linux_argc, linux_argv, linux_env, 0); + ft_len = boot_get_ft_len(images); + if (ft_len) + theKernel(FDT_MAGIC, boot_get_ft_addr(images), NULL, 0); + else + theKernel(linux_argc, linux_argv, linux_env, 0); } int do_bootm_linux(int flag, int argc, char * const argv[], -- 1.7.10 --------------090002030000070605090100-- From jchandra@broadcom.com Tue Jan 8 13:54:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jan 2013 13:54:52 +0100 (CET) Received: from mms1.broadcom.com ([216.31.210.17]:4844 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822664Ab3AHMyubX7nR (ORCPT ); Tue, 8 Jan 2013 13:54:50 +0100 Received: from [10.9.200.133] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 Jan 2013 04:52:31 -0800 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 Jan 2013 04:54:19 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 816EE40FE4; Tue, 8 Jan 2013 04:54:29 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 1/3] MIPS: Allow platform specific scratch registers Date: Tue, 8 Jan 2013 18:26:27 +0530 Message-ID: <1357649789-3423-2-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1357649789-3423-1-git-send-email-jchandra@broadcom.com> References: <1357649789-3423-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CF2C9051ZK11268582-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5669 Lines: 176 XLR/XLP COP0 scratch is register 22, sel 0-7. Add a function kscratch_reg() which returns the scratch register for the platform, and use the return value while generating TLB handlers. Setup kscratch_mask to 0xf for XLR/XLP since the config4 register does not exist. This allows the kernel to allocate scratch registers 0-3 if needed. Signed-off-by: Jayachandran C --- arch/mips/kernel/cpu-probe.c | 1 + arch/mips/mm/tlbex.c | 43 +++++++++++++++++++++++++++--------------- 2 files changed, 29 insertions(+), 15 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index cce3782..936c117 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1113,6 +1113,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) c->isa_level = MIPS_CPU_ISA_M64R1; c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; } + c->kscratch_mask = 0xf; } #ifdef CONFIG_64BIT diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 8855b50..c14f63f 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -265,6 +265,17 @@ static int check_for_high_segbits __cpuinitdata; static unsigned int kscratch_used_mask __cpuinitdata; +static inline int __maybe_unused kscratch_reg(void) +{ + switch (current_cpu_type()) { + case CPU_XLP: + case CPU_XLR: + return 22; + default: + return 31; + } +} + static int __cpuinit allocate_kscratch(void) { int r; @@ -282,6 +293,7 @@ static int __cpuinit allocate_kscratch(void) return r; } +static int c0_kscratch __cpuinitdata; static int scratch_reg __cpuinitdata; static int pgd_reg __cpuinitdata; enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; @@ -296,7 +308,7 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p) if (scratch_reg > 0) { /* Save in CPU local C0_KScratch? */ - UASM_i_MTC0(p, 1, 31, scratch_reg); + UASM_i_MTC0(p, 1, c0_kscratch, scratch_reg); r.r1 = K0; r.r2 = K1; r.r3 = 1; @@ -345,7 +357,7 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p) static void __cpuinit build_restore_work_registers(u32 **p) { if (scratch_reg > 0) { - UASM_i_MFC0(p, 1, 31, scratch_reg); + UASM_i_MFC0(p, 1, c0_kscratch, scratch_reg); return; } /* K0 already points to save area, restore $1 and $2 */ @@ -653,7 +665,7 @@ static __cpuinit void build_restore_pagemask(u32 **p, uasm_il_b(p, r, lid); } if (scratch_reg > 0) - UASM_i_MFC0(p, 1, 31, scratch_reg); + UASM_i_MFC0(p, 1, c0_kscratch, scratch_reg); else UASM_i_LW(p, 1, scratchpad_offset(0), 0); } else { @@ -796,7 +808,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, #ifdef CONFIG_MIPS_PGD_C0_CONTEXT if (pgd_reg != -1) { /* pgd is in pgd_reg */ - UASM_i_MFC0(p, ptr, 31, pgd_reg); + UASM_i_MFC0(p, ptr, c0_kscratch, pgd_reg); } else { /* * &pgd << 11 stored in CONTEXT [23..63]. @@ -909,7 +921,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, if (mode == refill_scratch) { if (scratch_reg > 0) - UASM_i_MFC0(p, 1, 31, scratch_reg); + UASM_i_MFC0(p, 1, c0_kscratch, scratch_reg); else UASM_i_LW(p, 1, scratchpad_offset(0), 0); } else { @@ -1075,7 +1087,7 @@ struct mips_huge_tlb_info { static struct mips_huge_tlb_info __cpuinit build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, struct uasm_reloc **r, unsigned int tmp, - unsigned int ptr, int c0_scratch) + unsigned int ptr, int c0_scratch_reg) { struct mips_huge_tlb_info rv; unsigned int even, odd; @@ -1089,12 +1101,12 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, UASM_i_MFC0(p, tmp, C0_BADVADDR); if (pgd_reg != -1) - UASM_i_MFC0(p, ptr, 31, pgd_reg); + UASM_i_MFC0(p, ptr, c0_kscratch, pgd_reg); else UASM_i_MFC0(p, ptr, C0_CONTEXT); - if (c0_scratch >= 0) - UASM_i_MTC0(p, scratch, 31, c0_scratch); + if (c0_scratch_reg >= 0) + UASM_i_MTC0(p, scratch, c0_kscratch, c0_scratch_reg); else UASM_i_SW(p, scratch, scratchpad_offset(0), 0); @@ -1109,14 +1121,14 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, } } else { if (pgd_reg != -1) - UASM_i_MFC0(p, ptr, 31, pgd_reg); + UASM_i_MFC0(p, ptr, c0_kscratch, pgd_reg); else UASM_i_MFC0(p, ptr, C0_CONTEXT); UASM_i_MFC0(p, tmp, C0_BADVADDR); - if (c0_scratch >= 0) - UASM_i_MTC0(p, scratch, 31, c0_scratch); + if (c0_scratch_reg >= 0) + UASM_i_MTC0(p, scratch, c0_kscratch, c0_scratch_reg); else UASM_i_SW(p, scratch, scratchpad_offset(0), 0); @@ -1221,8 +1233,8 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, } UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ - if (c0_scratch >= 0) { - UASM_i_MFC0(p, scratch, 31, c0_scratch); + if (c0_scratch_reg >= 0) { + UASM_i_MFC0(p, scratch, c0_kscratch, c0_scratch_reg); build_tlb_write_entry(p, l, r, tlb_random); uasm_l_leave(l, *p); rv.restore_scratch = 1; @@ -1471,7 +1483,7 @@ static void __cpuinit build_r4000_setup_pgd(void) } else { /* PGD in c0_KScratch */ uasm_i_jr(&p, 31); - UASM_i_MTC0(&p, a0, 31, pgd_reg); + UASM_i_MTC0(&p, a0, c0_kscratch, pgd_reg); } if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd)) panic("tlbmiss_handler_setup_pgd space exceeded"); @@ -2159,6 +2171,7 @@ void __cpuinit build_tlb_refill_handler(void) default: if (!run_once) { + c0_kscratch = kscratch_reg(); scratch_reg = allocate_kscratch(); #ifdef CONFIG_MIPS_PGD_C0_CONTEXT build_r4000_setup_pgd(); -- 1.7.9.5 From jchandra@broadcom.com Tue Jan 8 13:54:51 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jan 2013 13:55:10 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:2137 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823036Ab3AHMyvh-ZVx (ORCPT ); Tue, 8 Jan 2013 13:54:51 +0100 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 Jan 2013 04:51:33 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 Jan 2013 04:54:22 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id BFAF940FE3; Tue, 8 Jan 2013 04:54:32 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 3/3] MIPS: Move definition of SMP processor id register to header file Date: Tue, 8 Jan 2013 18:26:29 +0530 Message-ID: <1357649789-3423-4-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1357649789-3423-1-git-send-email-jchandra@broadcom.com> References: <1357649789-3423-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CF2C9DF3Q42189231-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 9264 Lines: 304 The definition of the CP0 register used to save the smp processor id is repicated in many files, move them all to thread_info.h. Signed-off-by: Jayachandran C --- arch/mips/include/asm/mmu_context.h | 18 +++----- arch/mips/include/asm/stackframe.h | 25 ++++------- arch/mips/include/asm/thread_info.h | 33 ++++++++++++++- arch/mips/kernel/genex.S | 1 - arch/mips/mm/tlbex.c | 78 +++++++---------------------------- 5 files changed, 62 insertions(+), 93 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 9d06a96..0415ce9 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -26,17 +26,18 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd); -#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ +#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ tlbmiss_handler_setup_pgd((unsigned long)(pgd)) #ifdef CONFIG_MIPS_PGD_C0_CONTEXT #define TLBMISS_HANDLER_SETUP() \ do { \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ - write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ + write_c0_xcontext((unsigned long) smp_processor_id() << \ + SMP_CPUID_REGSHIFT); \ } while (0) -#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ +#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ /* * For the fast tlb miss handlers, we keep a per cpu array of pointers @@ -45,18 +46,11 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd); */ extern unsigned long pgd_current[]; -#ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 25); \ + write_c0_context((unsigned long) smp_processor_id() << \ + SMP_CPUID_REGSHIFT); \ back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif -#ifdef CONFIG_64BIT -#define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 26); \ - back_to_back_c0_hazard(); \ - TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index cb41af5..80b0fa5 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -17,6 +17,7 @@ #include #include #include +#include /* * For SMTC kernel, global IE should be left set, and interrupts @@ -86,20 +87,12 @@ #ifdef CONFIG_SMP #ifdef CONFIG_MIPS_MT_SMTC -#define PTEBASE_SHIFT 19 /* TCBIND */ -#define CPU_ID_REG CP0_TCBIND -#define CPU_ID_MFC0 mfc0 -#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) -#define PTEBASE_SHIFT 48 /* XCONTEXT */ -#define CPU_ID_REG CP0_XCONTEXT -#define CPU_ID_MFC0 MFC0 +#define SMP_CPUID_MFC0 mfc0 #else -#define PTEBASE_SHIFT 23 /* CONTEXT */ -#define CPU_ID_REG CP0_CONTEXT -#define CPU_ID_MFC0 MFC0 +#define SMP_CPUID_MFC0 MFC0 #endif .macro get_saved_sp /* SMP variation */ - CPU_ID_MFC0 k0, CPU_ID_REG + SMP_CPUID_MFC0 k0, SMP_CPUID_REG #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -109,17 +102,17 @@ daddiu k1, %hi(kernelsp) dsll k1, 16 #endif - LONG_SRL k0, PTEBASE_SHIFT + LONG_SRL k0, SMP_CPUID_PTRSHIFT LONG_ADDU k1, k0 LONG_L k1, %lo(kernelsp)(k1) .endm .macro set_saved_sp stackp temp temp2 - CPU_ID_MFC0 \temp, CPU_ID_REG - LONG_SRL \temp, PTEBASE_SHIFT + SMP_CPUID_MFC0 \temp, SMP_CPUID_REG + LONG_SRL \temp, SMP_CPUID_PTRSHIFT LONG_S \stackp, kernelsp(\temp) .endm -#else +#else /* !CONFIG_SMP */ .macro get_saved_sp /* Uniprocessor variation */ #ifdef CONFIG_CPU_JUMP_WORKAROUNDS /* @@ -139,7 +132,7 @@ 1: move ra, k0 li k0, 3 mtc0 k0, $22 -#endif /* CONFIG_CPU_LOONGSON2F */ +#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */ #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 18806a5..81dbc6c 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -135,6 +135,37 @@ register struct thread_info *__current_thread_info __asm__("$28"); /* work to do on any return to u-space */ #define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT) -#endif /* __KERNEL__ */ +/* + * We stash processor id into a COP0 register to retrieve it fast + * at kernel exception entry. The register and shift used for this. + */ +#ifdef CONFIG_MIPS_MT_SMTC +#ifdef __ASSEMBLY__ +#define SMP_CPUID_REG $2, 2 /* TCBIND */ +#else +#define SMP_CPUID_REG 2, 2 +#endif +#define SMP_CPUID_PTRSHIFT 19 +#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) +#ifdef __ASSEMBLY__ +#define SMP_CPUID_REG $20, 0 /* XCONTEXT */ +#else +#define SMP_CPUID_REG 20, 0 +#endif +#define SMP_CPUID_PTRSHIFT 48 +#else +#ifdef __ASSEMBLY__ +#define SMP_CPUID_REG $4, 0 /* CONTEXT */ +#else +#define SMP_CPUID_REG 4, 0 +#endif +#define SMP_CPUID_PTRSHIFT 23 +#endif +#ifdef CONFIG_64BIT +#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3) +#else +#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2) +#endif +#endif /* __KERNEL__ */ #endif /* _ASM_THREAD_INFO_H */ diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index f166d61..0dbdd3b 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -20,7 +20,6 @@ #include #include #include -#include #define PANIC_PIC(msg) \ .set push; \ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index ffbdedf..ff4131b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -302,10 +302,6 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p) { struct work_registers r; - int smp_processor_id_reg; - int smp_processor_id_sel; - int smp_processor_id_shift; - if (scratch_reg > 0) { /* Save in CPU local C0_KScratch? */ UASM_i_MTC0(p, 1, c0_kscratch, scratch_reg); @@ -316,25 +312,9 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p) } if (num_possible_cpus() > 1) { -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - smp_processor_id_shift = 51; - smp_processor_id_reg = 20; /* XContext */ - smp_processor_id_sel = 0; -#else -# ifdef CONFIG_32BIT - smp_processor_id_shift = 25; - smp_processor_id_reg = 4; /* Context */ - smp_processor_id_sel = 0; -# endif -# ifdef CONFIG_64BIT - smp_processor_id_shift = 26; - smp_processor_id_reg = 4; /* Context */ - smp_processor_id_sel = 0; -# endif -#endif /* Get smp_processor_id */ - UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel); - UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift); + UASM_i_MFC0(p, K0, SMP_CPUID_REG); + UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); /* handler_reg_save index in K0 */ UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); @@ -823,20 +803,12 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, uasm_i_drotr(p, ptr, ptr, 11); #else #if defined(CONFIG_SMP) -# ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC uses TCBind value as "CPU" index - */ - uasm_i_mfc0(p, ptr, C0_TCBIND); - uasm_i_dsrl_safe(p, ptr, ptr, 19); -# else - /* - * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 - * stored in CONTEXT. - */ - uasm_i_dmfc0(p, ptr, C0_CONTEXT); - uasm_i_dsrl_safe(p, ptr, ptr, 23); -# endif +#ifdef CONFIG_MIPS_MT_SMTC + uasm_i_mfc0(p, ptr, SMP_CPUID_REG); +#else + uasm_i_dmfc0(p, ptr, SMP_CPUID_REG); +#endif + uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); UASM_i_LA_mostly(p, tmp, pgdc); uasm_i_daddu(p, ptr, ptr, tmp); uasm_i_dmfc0(p, tmp, C0_BADVADDR); @@ -950,21 +922,9 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ #ifdef CONFIG_SMP -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC uses TCBind value as "CPU" index - */ - uasm_i_mfc0(p, ptr, C0_TCBIND); + uasm_i_mfc0(p, ptr, SMP_CPUID_REG); UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, 19); -#else - /* - * smp_processor_id() << 3 is stored in CONTEXT. - */ - uasm_i_mfc0(p, ptr, C0_CONTEXT); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, 23); -#endif + uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); uasm_i_addu(p, ptr, tmp, ptr); #else UASM_i_LA_mostly(p, ptr, pgdc); @@ -1501,19 +1461,11 @@ static void __cpuinit build_setup_pgd(void) #else #if defined(CONFIG_SMP) # ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC uses TCBind value as "CPU" index - */ - uasm_i_mfc0(&p, a1, C0_TCBIND); - uasm_i_dsrl_safe(&p, a1, a1, 19); -# else - /* - * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 - * stored in CONTEXT. - */ - UASM_i_MFC0(&p, a1, C0_CONTEXT); - uasm_i_dsrl_safe(&p, a1, a1, 23); -# endif + uasm_i_mfc0(&p, a1, SMP_CPUID_REG); +#else + UASM_i_MFC0(&p, a1, SMP_CPUID_REG); +#endif + uasm_i_dsrl_safe(&p, a1, a1, SMP_CPUID_PTRSHIFT); UASM_i_LA_mostly(&p, a2, pgdc); UASM_i_ADDU(&p, a2, a2, a1); UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); -- 1.7.9.5 From jchandra@broadcom.com Tue Jan 8 13:54:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jan 2013 13:55:29 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:4336 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823089Ab3AHMywyf64I (ORCPT ); Tue, 8 Jan 2013 13:54:52 +0100 Received: from [10.9.200.133] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 Jan 2013 04:49:26 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 Jan 2013 04:54:17 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2019F40FE4; Tue, 8 Jan 2013 04:54:27 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [RFC PATCH 0/3] Use scratch registers on XLR/XLS/XLP Date: Tue, 8 Jan 2013 18:26:26 +0530 Message-ID: <1357649789-3423-1-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-WSS-ID: 7CF2CA5C39W24205961-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1769 Lines: 45 This set of patches enable the use of scratch registers on XLR/XLS and XLP (cop0 reg 22, sel 0-7) to optimize the genearted TLB handlers. The current code assumes scratch is 31, which is fixed by the first patch. The second patch enables use of a scratch register when it is available, even on a 32-bit or non-r2 platform. The third patch is a cleanup to consolidate all the defines needed into one file, this patch does not have any change in logic. In the earlier scheme, if MIPS_PGD_C0_CONTEXT was defined, the CP0 CONTEXT register or a scratch register would contain the current PGD, and the XCONTEXT would contain the smp_processor_id shifted to index pointers. In the new scheme, the behavior when MIPS_PGD_C0_CONTEXT is defined remains the same. But when it is not defined, we tries to allocate a scratch register for the current pgd, the smp processor id remains in CONTEXT. The additional change is generate tlbmiss_handler_setup_pgd() function that stores pgd even when MIPS_PGD_C0_CONTEXT is not defined. This function will save the PGD in pgd_current[] and also in the scratch register if one has been allocated. Comments/testing welcome. Thanks, JC. Jayachandran C (3): MIPS: Allow platform specific scratch registers MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT MIPS: Move definition of SMP processor id register to header file arch/mips/include/asm/mmu_context.h | 26 ++--- arch/mips/include/asm/stackframe.h | 25 ++--- arch/mips/include/asm/thread_info.h | 33 +++++- arch/mips/kernel/cpu-probe.c | 1 + arch/mips/kernel/genex.S | 1 - arch/mips/mm/tlbex.c | 188 ++++++++++++++++++----------------- 6 files changed, 146 insertions(+), 128 deletions(-) -- 1.7.9.5 From jchandra@broadcom.com Tue Jan 8 13:54:53 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jan 2013 13:55:54 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:4329 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823080Ab3AHMyxmw2mO (ORCPT ); Tue, 8 Jan 2013 13:54:53 +0100 Received: from [10.9.200.133] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 Jan 2013 04:49:29 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 Jan 2013 04:54:20 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 235D540FE3; Tue, 8 Jan 2013 04:54:30 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 2/3] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT Date: Tue, 8 Jan 2013 18:26:28 +0530 Message-ID: <1357649789-3423-3-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1357649789-3423-1-git-send-email-jchandra@broadcom.com> References: <1357649789-3423-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CF2CA5339W24205984-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 9359 Lines: 288 Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, and this was also tied to using scratch registers for PGD. This commit will allow usage of scratch register to store the current pgd, if one can be allocated for the platform, even in other cases (i.e when MIPS_PGD_C0_CONTEXT is not set). The processor id will be kept in the CP0 Context register in this case. The code to store the current pgd for the TLB miss handler is now generated in all cases, and if scratch register is available, the pgd is also stored in the scratch register. Signed-off-by: Jayachandran C --- arch/mips/include/asm/mmu_context.h | 8 +- arch/mips/mm/tlbex.c | 139 ++++++++++++++++++++++------------- 2 files changed, 91 insertions(+), 56 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 9b02cfb..9d06a96 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -24,13 +24,12 @@ #endif /* SMTC */ #include -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT +extern void tlbmiss_handler_setup_pgd(unsigned long pgd); #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ tlbmiss_handler_setup_pgd((unsigned long)(pgd)) -extern void tlbmiss_handler_setup_pgd(unsigned long pgd); - +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT #define TLBMISS_HANDLER_SETUP() \ do { \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ @@ -46,9 +45,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd); */ extern unsigned long pgd_current[]; -#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ - pgd_current[smp_processor_id()] = (unsigned long)(pgd) - #ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << 25); \ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index c14f63f..ffbdedf 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -805,11 +805,11 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, } /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT if (pgd_reg != -1) { /* pgd is in pgd_reg */ UASM_i_MFC0(p, ptr, c0_kscratch, pgd_reg); } else { +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT /* * &pgd << 11 stored in CONTEXT [23..63]. */ @@ -821,30 +821,32 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* 1 0 1 0 1 << 6 xkphys cached */ uasm_i_ori(p, ptr, ptr, 0x540); uasm_i_drotr(p, ptr, ptr, 11); - } -#elif defined(CONFIG_SMP) +#else +#if defined(CONFIG_SMP) # ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC uses TCBind value as "CPU" index - */ - uasm_i_mfc0(p, ptr, C0_TCBIND); - uasm_i_dsrl_safe(p, ptr, ptr, 19); + /* + * SMTC uses TCBind value as "CPU" index + */ + uasm_i_mfc0(p, ptr, C0_TCBIND); + uasm_i_dsrl_safe(p, ptr, ptr, 19); # else - /* - * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 - * stored in CONTEXT. - */ - uasm_i_dmfc0(p, ptr, C0_CONTEXT); - uasm_i_dsrl_safe(p, ptr, ptr, 23); + /* + * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 + * stored in CONTEXT. + */ + uasm_i_dmfc0(p, ptr, C0_CONTEXT); + uasm_i_dsrl_safe(p, ptr, ptr, 23); # endif - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_daddu(p, ptr, ptr, tmp); - uasm_i_dmfc0(p, tmp, C0_BADVADDR); - uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_daddu(p, ptr, ptr, tmp); + uasm_i_dmfc0(p, tmp, C0_BADVADDR); + uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); #else - UASM_i_LA_mostly(p, ptr, pgdc); - uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); -#endif + UASM_i_LA_mostly(p, ptr, pgdc); + uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); +#endif /* SMP */ +#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ + } uasm_l_vmalloc_done(l, *p); @@ -939,31 +941,37 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, static void __cpuinit __maybe_unused build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) { - long pgdc = (long)pgd_current; + if (pgd_reg != -1) { + /* pgd is in pgd_reg */ + uasm_i_mfc0(p, ptr, c0_kscratch, pgd_reg); + uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + } else { + long pgdc = (long)pgd_current; - /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ + /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ #ifdef CONFIG_SMP #ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC uses TCBind value as "CPU" index - */ - uasm_i_mfc0(p, ptr, C0_TCBIND); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, 19); + /* + * SMTC uses TCBind value as "CPU" index + */ + uasm_i_mfc0(p, ptr, C0_TCBIND); + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_srl(p, ptr, ptr, 19); #else - /* - * smp_processor_id() << 3 is stored in CONTEXT. - */ - uasm_i_mfc0(p, ptr, C0_CONTEXT); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, 23); + /* + * smp_processor_id() << 3 is stored in CONTEXT. + */ + uasm_i_mfc0(p, ptr, C0_CONTEXT); + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_srl(p, ptr, ptr, 23); #endif - uasm_i_addu(p, ptr, tmp, ptr); + uasm_i_addu(p, ptr, tmp, ptr); #else - UASM_i_LA_mostly(p, ptr, pgdc); + UASM_i_LA_mostly(p, ptr, pgdc); #endif - uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ - uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); + uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); + } uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -1446,16 +1454,17 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned; -static void __cpuinit build_r4000_setup_pgd(void) +static void __cpuinit build_setup_pgd(void) { const int a0 = 4; - const int a1 = 5; + const int __maybe_unused a1 = 5; + const int a2 = 6; u32 *p = tlbmiss_handler_setup_pgd; - struct uasm_label *l = labels; - struct uasm_reloc *r = relocs; +#ifndef CONFIG_MIPS_PGD_C0_CONTEXT + long pgdc = (long)pgd_current; +#endif memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd)); memset(labels, 0, sizeof(labels)); @@ -1463,7 +1472,11 @@ static void __cpuinit build_r4000_setup_pgd(void) pgd_reg = allocate_kscratch(); +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT if (pgd_reg == -1) { + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + /* PGD << 11 in c0_Context */ /* * If it is a ckseg0 address, convert to a physical @@ -1485,6 +1498,36 @@ static void __cpuinit build_r4000_setup_pgd(void) uasm_i_jr(&p, 31); UASM_i_MTC0(&p, a0, c0_kscratch, pgd_reg); } +#else +#if defined(CONFIG_SMP) +# ifdef CONFIG_MIPS_MT_SMTC + /* + * SMTC uses TCBind value as "CPU" index + */ + uasm_i_mfc0(&p, a1, C0_TCBIND); + uasm_i_dsrl_safe(&p, a1, a1, 19); +# else + /* + * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 + * stored in CONTEXT. + */ + UASM_i_MFC0(&p, a1, C0_CONTEXT); + uasm_i_dsrl_safe(&p, a1, a1, 23); +# endif + UASM_i_LA_mostly(&p, a2, pgdc); + UASM_i_ADDU(&p, a2, a2, a1); + UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); +#else + UASM_i_LA_mostly(&p, a2, pgdc); + UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); +#endif /* SMP */ + uasm_i_jr(&p, 31); + if (pgd_reg != -1) { + /* PGD also in c0_KScratch */ + UASM_i_MTC0(&p, a0, c0_kscratch, pgd_reg); + } else + uasm_i_nop(&p); +#endif if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd)) panic("tlbmiss_handler_setup_pgd space exceeded"); uasm_resolve_relocs(relocs, labels); @@ -1494,7 +1537,6 @@ static void __cpuinit build_r4000_setup_pgd(void) dump_handler(tlbmiss_handler_setup_pgd, ARRAY_SIZE(tlbmiss_handler_setup_pgd)); } -#endif static void __cpuinit iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) @@ -2150,6 +2192,7 @@ void __cpuinit build_tlb_refill_handler(void) #ifndef CONFIG_MIPS_PGD_C0_CONTEXT build_r3000_tlb_refill_handler(); if (!run_once) { + build_setup_pgd(); build_r3000_tlb_load_handler(); build_r3000_tlb_store_handler(); build_r3000_tlb_modify_handler(); @@ -2173,9 +2216,7 @@ void __cpuinit build_tlb_refill_handler(void) if (!run_once) { c0_kscratch = kscratch_reg(); scratch_reg = allocate_kscratch(); -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - build_r4000_setup_pgd(); -#endif + build_setup_pgd(); build_r4000_tlb_load_handler(); build_r4000_tlb_store_handler(); build_r4000_tlb_modify_handler(); @@ -2193,8 +2234,6 @@ void __cpuinit flush_tlb_handlers(void) (unsigned long)handle_tlbs + sizeof(handle_tlbs)); local_flush_icache_range((unsigned long)handle_tlbm, (unsigned long)handle_tlbm + sizeof(handle_tlbm)); -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm)); -#endif } -- 1.7.9.5 From zajec5@gmail.com Wed Jan 9 10:24:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Jan 2013 10:24:49 +0100 (CET) Received: from mail-wi0-f178.google.com ([209.85.212.178]:63627 "EHLO mail-wi0-f178.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823099Ab3AIJYoy7lZW convert rfc822-to-8bit (ORCPT ); Wed, 9 Jan 2013 10:24:44 +0100 Received: by mail-wi0-f178.google.com with SMTP id hn3so394558wib.17 for ; Wed, 09 Jan 2013 01:24:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:in-reply-to:references:date:message-id :subject:from:to:cc:content-type:content-transfer-encoding; bh=AuOu3Rs+GcmOEXrwyB9kI/y+GVwAUAq/uq9XlOouwY8=; b=upFmVkks80AJwAeLDzkJtc3YeOJA5ZtyZR+TabIGM14RWE/Nt5NrkXs+xSEZbfQD1+ cHhb4ZW17GCA2Jl4MNNzOTFnDQCti5Fllzt367LHDmDzKchls9hwcyt3wnoMevSCtk8K JhEQ2A7UWJvFK/KZI+MOi8qFlAu67481LVVnw5QiJk8VKsL1uPRdAwV5Ld5CnDxfOOUc 2MabiyHfYQp0Zaq5XCtVpDgagpUSV9fi2P5cpgxDMq1wd//QUA4J9vSv8uMG90wD0SPP iA3wVK0kF95eEumFw4Q1hgYKAJAmJZvMJXisgboi7DlgJOkklboXtpcYVymS3E0Hhaxn Mydw== MIME-Version: 1.0 X-Received: by 10.180.84.193 with SMTP id b1mr1996450wiz.26.1357723477041; Wed, 09 Jan 2013 01:24:37 -0800 (PST) Received: by 10.216.21.8 with HTTP; Wed, 9 Jan 2013 01:24:36 -0800 (PST) In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> Date: Wed, 9 Jan 2013 10:24:36 +0100 Message-ID: Subject: Re: [PATCH v3 00/11] watchdog/bcm47xx/bcma/ssb: add support for SoCs with PMU From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: Hauke Mehrtens Cc: linville@tuxdriver.com, wim@iguana.be, linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 35397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zajec5@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1032 Lines: 24 2012/12/5 Hauke Mehrtens : > This patch series improves the functions for setting the watchdog > driver in ssb amd bcma. It also makes ssb and bcma register a platform > device which could be used by a watchdog driver to better set the times > where the system should restart. The patches for the watchdog driver > will be send later and were removed in v3. > > This code is currently based on the wireless-testing/master tree by > John Linville. > > v3: > * Remove changes done to the watchdog driver so John could pull this > into wireless-testing, this sill works with the old watchdog driver. > The patches changing the watchdog driver will be send later. > This was done to get this into 3.8 because Wim Van Sebroeck is > neither giving an Ack or a Nack on these patches and we want to do > more changes to bcma/ssb on top of these. Your changes are already in Linus's tree, do you plan to re-send watchdog patches dropped in V3 through linux-watchdog? Can you take care of this? -- RafaÅ‚ From wim@iguana.be Wed Jan 9 13:45:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Jan 2013 13:45:49 +0100 (CET) Received: from ns1.pc-advies.be ([83.149.101.17]:42127 "EHLO spo001.leaseweb.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6817030Ab3AIMps1rmad (ORCPT ); Wed, 9 Jan 2013 13:45:48 +0100 Received: from wimvs by spo001.leaseweb.com with local (Exim 4.50) id 1Tsv2G-0008Ju-SJ; Wed, 09 Jan 2013 13:45:36 +0100 Date: Wed, 9 Jan 2013 13:45:36 +0100 From: Wim Van Sebroeck To: =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= Cc: Hauke Mehrtens , linville@tuxdriver.com, linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, linux-mips@linux-mips.org Subject: Re: [PATCH v3 00/11] watchdog/bcm47xx/bcma/ssb: add support for SoCs with PMU Message-ID: <20130109124536.GG10667@spo001.leaseweb.com> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.4.1i X-archive-position: 35398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1184 Lines: 31 Hi Rafal, this will probably be done after I reviewed the v2 watchdog part first. Kind regards, Wim. > 2012/12/5 Hauke Mehrtens : > > This patch series improves the functions for setting the watchdog > > driver in ssb amd bcma. It also makes ssb and bcma register a platform > > device which could be used by a watchdog driver to better set the times > > where the system should restart. The patches for the watchdog driver > > will be send later and were removed in v3. > > > > This code is currently based on the wireless-testing/master tree by > > John Linville. > > > > v3: > > * Remove changes done to the watchdog driver so John could pull this > > into wireless-testing, this sill works with the old watchdog driver. > > The patches changing the watchdog driver will be send later. > > This was done to get this into 3.8 because Wim Van Sebroeck is > > neither giving an Ack or a Nack on these patches and we want to do > > more changes to bcma/ssb on top of these. > > Your changes are already in Linus's tree, do you plan to re-send > watchdog patches dropped in V3 through linux-watchdog? Can you take > care of this? > > -- > RafaÅ‚ From ddaney@caviumnetworks.com Fri Jan 11 02:58:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Jan 2013 02:58:50 +0100 (CET) Received: from co9ehsobe004.messaging.microsoft.com ([207.46.163.27]:2858 "EHLO co9outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823015Ab3AKB6su076J (ORCPT ); Fri, 11 Jan 2013 02:58:48 +0100 Received: from mail220-co9-R.bigfish.com (10.236.132.234) by CO9EHSOBE006.bigfish.com (10.236.130.69) with Microsoft SMTP Server id 14.1.225.23; Fri, 11 Jan 2013 01:58:39 +0000 Received: from mail220-co9 (localhost [127.0.0.1]) by mail220-co9-R.bigfish.com (Postfix) with ESMTP id 2CBEA3C02F9; Fri, 11 Jan 2013 01:58:39 +0000 (UTC) X-Forefront-Antispam-Report: CIP:132.245.2.69;KIP:(null);UIP:(null);IPV:NLI;H:BN1PRD0712HT003.namprd07.prod.outlook.com;RD:none;EFVD:NLI X-SpamScore: -1 X-BigFish: PS-1(zz1443Izz1ee6h1de0h1202h1e76h1d1ah1d2ahzzz2dh2a8h668h839h947hd25he5bhf0ah1288h12a5h12a9h12bdh137ah13b6h1441h14ddh1504h1537h153bh162dh1631h1758h1765h1155h) Received: from mail220-co9 (localhost.localdomain [127.0.0.1]) by mail220-co9 (MessageSwitch) id 1357869517164784_27553; Fri, 11 Jan 2013 01:58:37 +0000 (UTC) Received: from CO9EHSMHS004.bigfish.com (unknown [10.236.132.242]) by mail220-co9.bigfish.com (Postfix) with ESMTP id 22FC416004F; Fri, 11 Jan 2013 01:58:37 +0000 (UTC) Received: from BN1PRD0712HT003.namprd07.prod.outlook.com (132.245.2.69) by CO9EHSMHS004.bigfish.com (10.236.130.14) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 11 Jan 2013 01:58:37 +0000 Received: from dl.caveonetworks.com (64.2.3.195) by pod51018.outlook.com (10.255.196.36) with Microsoft SMTP Server (TLS) id 14.16.257.4; Fri, 11 Jan 2013 01:58:35 +0000 Message-ID: <50EF71C9.4010907@caviumnetworks.com> Date: Thu, 10 Jan 2013 17:58:33 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Steven Rostedt CC: Ralf Baechle , linux-mips , Linux Kernel Mailing List Subject: Ftrace test failure on MIPS - Looking for insight.. Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.195] X-OriginatorOrg: caviumnetworks.com X-archive-position: 35399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1101 Lines: 42 Hi Steven, I am trying to track down the cause of: . . . Brought up 32 CPUs Testing tracer function: PASSED Testing dynamic ftrace: .. filter failed count=0 ..FAILED! ------------[ cut here ]------------ WARNING: at kernel/trace/trace.c:878 register_tracer+0x23c/0x300() Modules linked in: Call Trace: [] dump_stack+0x14/0x40 [] warn_slowpath_common+0x84/0xb0 [] register_tracer+0x23c/0x300 [] do_one_initcall+0x110/0x178 [] kernel_init+0x174/0x318 [] ret_from_kernel_thread+0x14/0x1c ---[ end trace 204112383c2d190e ]--- . . . This is a MIPS64 kernel build from Linus' tree of today (commit 254adaa465c40151df11fc1f88f93e6e86eb61d4) I think the failure is long standing (since 3.4.x at least). If you have any ideas off the top of your head as to what the cause might be, I would love to hear them. In any event, I will try to track down the root cause and fix it. But if something jumped out at you, that could speed up my search for the cause. Thanks in advance, David Daney From rostedt@goodmis.org Fri Jan 11 03:54:38 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Jan 2013 03:54:40 +0100 (CET) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:28864 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6820116Ab3AKCyiFXrB1 (ORCPT ); Fri, 11 Jan 2013 03:54:38 +0100 X-Authority-Analysis: v=2.0 cv=T70Ovo2Q c=1 sm=0 a=rXTBtCOcEpjy1lPqhTCpEQ==:17 a=mNMOxpOpBa8A:10 a=YVIWcjBVNvEA:10 a=5SG0PmZfjMsA:10 a=Q9fys5e9bTEA:10 a=meVymXHHAAAA:8 a=B2Q2Fn0tczoA:10 a=ayC55rCoAAAA:8 a=m0D0claWAAAA:8 a=-90oljrv8j-shKSv9rgA:9 a=PUjeQqilurYA:10 a=E6k37eg1NvgA:10 a=rXTBtCOcEpjy1lPqhTCpEQ==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 74.67.115.198 Received: from [74.67.115.198] ([74.67.115.198:51916] helo=[192.168.23.10]) by hrndva-oedge02.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id A5/6F-03129-AEE7FE05; Fri, 11 Jan 2013 02:54:35 +0000 Message-ID: <1357872874.5141.28.camel@gandalf.local.home> Subject: Re: Ftrace test failure on MIPS - Looking for insight.. From: Steven Rostedt To: David Daney Cc: Ralf Baechle , linux-mips , Linux Kernel Mailing List Date: Thu, 10 Jan 2013 21:54:34 -0500 In-Reply-To: <50EF71C9.4010907@caviumnetworks.com> References: <50EF71C9.4010907@caviumnetworks.com> Content-Type: text/plain; charset="ISO-8859-15" X-Mailer: Evolution 3.4.4-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-archive-position: 35400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2550 Lines: 78 On Thu, 2013-01-10 at 17:58 -0800, David Daney wrote: > Hi Steven, > > I am trying to track down the cause of: > > . > . > . > Brought up 32 CPUs > Testing tracer function: PASSED > Testing dynamic ftrace: .. filter failed count=0 ..FAILED! > ------------[ cut here ]------------ > WARNING: at kernel/trace/trace.c:878 register_tracer+0x23c/0x300() > Modules linked in: > Call Trace: > [] dump_stack+0x14/0x40 > [] warn_slowpath_common+0x84/0xb0 > [] register_tracer+0x23c/0x300 > [] do_one_initcall+0x110/0x178 > [] kernel_init+0x174/0x318 > [] ret_from_kernel_thread+0x14/0x1c > > ---[ end trace 204112383c2d190e ]--- > . > . > . > > > This is a MIPS64 kernel build from Linus' tree of today (commit > 254adaa465c40151df11fc1f88f93e6e86eb61d4) > > I think the failure is long standing (since 3.4.x at least). > > If you have any ideas off the top of your head as to what the cause > might be, I would love to hear them. > > In any event, I will try to track down the root cause and fix it. But > if something jumped out at you, that could speed up my search for the cause. The failure is that it set the tracing filter to be DYN_FTRACE_TEST_NAME (which is defined as trace_selftest_dynamic_test_func) and then it called the function and then checked how many events were in the trace. But there wasn't any (count=0). For some reason dynamic function tracing didn't trace the function when it was called. Some reasons fro this to happen: 1) tracing was some how disabled (tracing_on set to zero). But as the function tracer passed, I don't think this would be the case. 2) the function wasn't properly set in the filter. That is, could mips have another name for that function? Where it wouldn't add it? 3) well, just about anything :-) I could suggest adding printks in the code, and that might help you. Look into ftrace_set_global_filter (kernel/trace/ftrace.c) and follow that code. Follow it all the way to __ftrace_hash_rec_update(), and make sure the rec get's updated. You may add a printk right after the inc (although, you may also want to set a variable to not do that printk until the dynamic test runs). Something like this: rec->flags++; if (ok_to_printk) printk("setting rec %p %pS\n", (void*)rec->ip, (void*)rec->ip); and at the start of the dynamic test have: ok_to_printk = 1; pr_info("Testing dynamic ftarce: "); You should see the record being set. If not, you know why it broke. -- Steve From aaro.koskinen@iki.fi Fri Jan 11 08:17:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Jan 2013 08:17:20 +0100 (CET) Received: from filtteri2.pp.htv.fi ([213.243.153.185]:42658 "EHLO filtteri2.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816635Ab3AKHRQzZ6rv (ORCPT ); Fri, 11 Jan 2013 08:17:16 +0100 Received: from localhost (localhost [127.0.0.1]) by filtteri2.pp.htv.fi (Postfix) with ESMTP id E219A19BC9B; Fri, 11 Jan 2013 09:17:15 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp5.welho.com ([213.243.153.39]) by localhost (filtteri2.pp.htv.fi [213.243.153.185]) (amavisd-new, port 10024) with ESMTP id MIy6BqOafCwK; Fri, 11 Jan 2013 09:17:15 +0200 (EET) Received: from musicnaut.iki.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp5.welho.com (Postfix) with SMTP id 9136B5BC005; Fri, 11 Jan 2013 09:17:14 +0200 (EET) Received: by musicnaut.iki.fi (sSMTP sendmail emulation); Fri, 11 Jan 2013 09:17:10 +0200 Date: Fri, 11 Jan 2013 09:17:10 +0200 From: Aaro Koskinen To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: 3.8-rc3: yet another MIPS build failure Message-ID: <20130111071710.GE12712@blackmetal.musicnaut.iki.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 743 Lines: 20 Hi, Commit d3ce88431892b703b04769566338a89eda6b0477 (MIPS: Fix modpost error in modules attepting to use virt_addr_valid()) broke the 64-bit MIPS build: LD init/built-in.o kernel/built-in.o: In function `memory_bm_free': snapshot.c:(.text+0x3c76c): undefined reference to `__virt_addr_valid' snapshot.c:(.text+0x3c800): undefined reference to `__virt_addr_valid' kernel/built-in.o: In function `snapshot_write_next': (.text+0x3e094): undefined reference to `__virt_addr_valid' kernel/built-in.o: In function `snapshot_write_next': (.text+0x3e468): undefined reference to `__virt_addr_valid' make[4]: *** [vmlinux] Error 1 A quick workaround is to compile ioremap.c always, but it adds ~2KB unused code for 64-bit-only kernels... A. From alcooperx@gmail.com Fri Jan 11 15:34:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Jan 2013 15:35:39 +0100 (CET) Received: from mms1.broadcom.com ([216.31.210.17]:2826 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823016Ab3AKOekBeDEs (ORCPT ); Fri, 11 Jan 2013 15:34:40 +0100 Received: from [10.9.208.26] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 11 Jan 2013 06:31:58 -0800 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHCAS05.corp.ad.broadcom.com (10.9.208.26) with Microsoft SMTP Server id 14.1.355.2; Fri, 11 Jan 2013 06:33:53 -0800 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 9C28040FE6; Fri, 11 Jan 2013 06:33:52 -0800 (PST) From: "Al Cooper" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org cc: "Al Cooper" Subject: [PATCH] mips: function tracer: Fix broken function tracing Date: Fri, 11 Jan 2013 09:33:30 -0500 Message-ID: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: References: MIME-Version: 1.0 X-WSS-ID: 7CEEFDD41ZS4162332-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35402 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4293 Lines: 128 Function tracing is currently broken for all 32 bit MIPS platforms. When tracing is enabled, the kernel immediately hangs on boot. This is a result of commit b732d439cb43336cd6d7e804ecb2c81193ef63b0 that changes the kernel/trace/Kconfig file so that is no longer forces FRAME_POINTER when FUNCTION_TRACING is enabled. MIPS frame pointers are generally considered to be useless because they cannot be used to unwind the stack. Unfortunately the MIPS function tracing code has bugs that are masked by the use of frame pointers. This commit fixes the bugs so that MIPS frame pointers do not need to be enabled. The bugs are a result of the odd calling sequence used to call the trace routine. This calling sequence is inserted into every tracable function when the tracing CONFIG option is enabled. This sequence is generated for 32bit MIPS platforms by the compiler via the "-pg" flag. Part of the sequence is "addiu sp,sp,-8" in the delay slot after every call to the trace routine "_mcount" (some legacy thing where 2 arguments used to be pushed on the stack). The _mcount routine is expected to adjust the sp by +8 before returning. One of the bugs is that when tracing is disabled for a function, the "jalr _mcount" instruction is replaced with a nop, but the "addiu sp,sp,-8" is still executed and the stack pointer is left trashed. When frame pointers are enabled the problem is masked because any access to the stack is done through the frame pointer and the stack pointer is restored from the frame pointer when the function returns. This patch uses a branch likely instruction "bltzl zero, f1" instead of "nop" to disable the call because this instruction will not execute the "addiu sp,sp,-8" instruction in the delay slot. The other possible solution would be to nop out both the jalr and the "addiu sp,sp,-8", but this would need to be interrupt and SMP safe and would be much more intrusive. A few other bugs were fixed where the _mcount routine itself did not always fix the sp on return. Signed-off-by: Al Cooper --- arch/mips/kernel/ftrace.c | 9 ++++++++- arch/mips/kernel/mcount.S | 14 ++++++++++---- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 6a2d758..f761130 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -46,6 +46,13 @@ static inline int in_kernel_space(unsigned long ip) #define JUMP_RANGE_MASK ((1UL << 28) - 1) #define INSN_NOP 0x00000000 /* nop */ + +/* + * This branch likely instruction is used to nop the call to _mcount + * and skip the stack adjust instruction in the delay slot. + */ +#define INSN_NOP_SKIP 0x04020001 /* bltzl zero, f1 */ + #define INSN_JAL(addr) \ ((unsigned int)(JAL | (((addr) >> 2) & ADDR_MASK))) @@ -130,7 +137,7 @@ int ftrace_make_nop(struct module *mod, * If ip is in kernel space, no long call, otherwise, long call is * needed. */ - new = in_kernel_space(ip) ? INSN_NOP : INSN_B_1F; + new = in_kernel_space(ip) ? INSN_NOP_SKIP : INSN_B_1F; return ftrace_modify_code(ip, new); } diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S index 4c968e7..78ac3cc 100644 --- a/arch/mips/kernel/mcount.S +++ b/arch/mips/kernel/mcount.S @@ -68,10 +68,10 @@ NESTED(ftrace_caller, PT_SIZE, ra) .globl _mcount _mcount: - b ftrace_stub + b ftrace_stub_restore_sp nop lw t1, function_trace_stop - bnez t1, ftrace_stub + bnez t1, ftrace_stub_restore_sp nop MCOUNT_SAVE_REGS @@ -96,13 +96,16 @@ ftrace_graph_call: .globl ftrace_stub ftrace_stub: RETURN_BACK +ftrace_stub_restore_sp: + PTR_ADDIU sp, 8 + RETURN_BACK END(ftrace_caller) #else /* ! CONFIG_DYNAMIC_FTRACE */ NESTED(_mcount, PT_SIZE, ra) lw t1, function_trace_stop - bnez t1, ftrace_stub + bnez t1, ftrace_stub_restore_sp nop PTR_LA t1, ftrace_stub PTR_L t2, ftrace_trace_function /* Prepare t2 for (1) */ @@ -118,7 +121,7 @@ NESTED(_mcount, PT_SIZE, ra) bne t1, t3, ftrace_graph_caller nop #endif - b ftrace_stub + b ftrace_stub_restore_sp nop static_trace: @@ -132,6 +135,9 @@ static_trace: .globl ftrace_stub ftrace_stub: RETURN_BACK +ftrace_stub_restore_sp: + PTR_ADDIU sp, 8 + RETURN_BACK END(_mcount) #endif /* ! CONFIG_DYNAMIC_FTRACE */ -- 1.7.6 From ddaney.cavm@gmail.com Fri Jan 11 18:01:10 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Jan 2013 18:01:11 +0100 (CET) Received: from mail-pb0-f51.google.com ([209.85.160.51]:61752 "EHLO mail-pb0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6818323Ab3AKRBKSGB-I (ORCPT ); Fri, 11 Jan 2013 18:01:10 +0100 Received: by mail-pb0-f51.google.com with SMTP id ro12so1047350pbb.38 for ; Fri, 11 Jan 2013 09:01:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=2SV2OxWpELTs07N0aG9QprxqOl1yqFranzACXKFwLYc=; b=ixRS5oEHEN1lrf1JqlYYC6Fljt5LutjHNxBIBhC1854k668O8E2hikSeq/COkHRSEq hY7O0zZuWDBfys/iCOYRzkFArBzSvNBeQvHUNEuYJx526Wbr97lKjb7OavQdVZXCds6q EsQEYktAu72iHRk7CB1us57hvJ0R/YBq/HNY0U86sa6KDScev++Mc+E1wbYzhtIklBdg 5V0c5mc0wWktG5Tq8TXR642FdQJuRii0CDPVhFDNPI7qx+yMQPOzLfIefI53YjMJ9zh0 ieZbjhuzA1AkKNmsH0hcu8ewnqMbD3gptWa6c3HIeWkMbuRf89HAX1+qUWRlOFSNT594 svGQ== X-Received: by 10.68.130.135 with SMTP id oe7mr62374996pbb.38.1357923663210; Fri, 11 Jan 2013 09:01:03 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id rk6sm3075655pbc.20.2013.01.11.09.01.01 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 11 Jan 2013 09:01:02 -0800 (PST) Message-ID: <50F0454D.5060109@gmail.com> Date: Fri, 11 Jan 2013 09:01:01 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Al Cooper CC: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> In-Reply-To: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35403 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2794 Lines: 58 On 01/11/2013 06:33 AM, Al Cooper wrote: > Function tracing is currently broken for all 32 bit MIPS platforms. > When tracing is enabled, the kernel immediately hangs on boot. > This is a result of commit b732d439cb43336cd6d7e804ecb2c81193ef63b0 > that changes the kernel/trace/Kconfig file so that is no longer > forces FRAME_POINTER when FUNCTION_TRACING is enabled. > > MIPS frame pointers are generally considered to be useless because > they cannot be used to unwind the stack. Unfortunately the MIPS > function tracing code has bugs that are masked by the use of frame > pointers. This commit fixes the bugs so that MIPS frame pointers do > not need to be enabled. > > The bugs are a result of the odd calling sequence used to call the trace > routine. This calling sequence is inserted into every tracable function > when the tracing CONFIG option is enabled. This sequence is generated > for 32bit MIPS platforms by the compiler via the "-pg" flag. > Part of the sequence is "addiu sp,sp,-8" in the delay slot after every > call to the trace routine "_mcount" (some legacy thing where 2 arguments > used to be pushed on the stack). The _mcount routine is expected to > adjust the sp by +8 before returning. > > One of the bugs is that when tracing is disabled for a function, the > "jalr _mcount" instruction is replaced with a nop, but the > "addiu sp,sp,-8" is still executed and the stack pointer is left > trashed. When frame pointers are enabled the problem is masked > because any access to the stack is done through the frame > pointer and the stack pointer is restored from the frame pointer when > the function returns. This patch uses a branch likely instruction > "bltzl zero, f1" instead of "nop" to disable the call because this > instruction will not execute the "addiu sp,sp,-8" instruction in > the delay slot. The other possible solution would be to nop out both > the jalr and the "addiu sp,sp,-8", but this would need to be interrupt > and SMP safe and would be much more intrusive. I thought all CPUs were in stop_machine() when the modifications were done, so that there is no issue with multi-word instruction patching. Am I wrong about this? So really I think you can do two NOP just as easily. The only reason I bring this up is that I am not sure all 32-bit CPUs implement the 'Likely' branch variants. Also there may be an affect on the branch predictor. A third possibility would be to replace the JALR with 'ADDIU SP,SP,8' That way the following adjustment would be canceled out. This would work well on single-issue CPUs, but the instructions may not be able to dual-issue on a multi issue machine due to data dependencies. David Daney > > A few other bugs were fixed where the _mcount routine itself did not > always fix the sp on return. > From sjhill@mips.com Fri Jan 11 22:55:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Jan 2013 22:55:42 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:59550 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825698Ab3AKVzkmcz9a (ORCPT ); Fri, 11 Jan 2013 22:55:40 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TtmZX-00060R-Dr; Fri, 11 Jan 2013 15:55:31 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, mcdonald.shane@gmail.com Subject: [PATCH v3] MIPS: Add option to disable software I/O coherency. Date: Fri, 11 Jan 2013 15:55:25 -0600 Message-Id: <1357941325-25718-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35404 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6588 Lines: 227 From: "Steven J. Hill" Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mach-generic/dma-coherence.h | 5 +- arch/mips/mm/c-r4k.c | 34 +++++++--- arch/mips/mm/dma-default.c | 6 +- arch/mips/mti-malta/malta-setup.c | 71 ++++++++++++++++++++ 4 files changed, 105 insertions(+), 11 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177..cd17f22 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -57,13 +57,16 @@ static inline int plat_dma_mapping_error(struct device *dev, return 0; } +extern int coherentio; +extern int hw_coherentio; + static inline int plat_device_is_coherent(struct device *dev) { #ifdef CONFIG_DMA_COHERENT return 1; #endif #ifdef CONFIG_DMA_NONCOHERENT - return 0; + return coherentio; #endif } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 606e828..e4ee358 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1379,19 +1379,34 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; +int coherentio = 0; /* no DMA cache coherency (may be set by user) */ +int hw_coherentio = 0; /* no HW DMA cache coherency (reflects real HW) */ static int __init setcoherentio(char *str) { - coherentio = 1; + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); return 0; } - early_param("coherentio", setcoherentio); -#endif + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 0; +} +early_param("nocoherentio", setnocoherentio); static void __cpuinit r4k_cache_error_setup(void) { @@ -1415,6 +1430,7 @@ void __cpuinit r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); + extern int coherentio; struct cpuinfo_mips *c = ¤t_cpu_data; probe_pcache(); @@ -1474,9 +1490,11 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* We want to run CMP kernels on core(s) with and without coherent caches */ + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); board_cache_error_setup = r4k_cache_error_setup; } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 3fab204..aad5f7e 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -115,7 +115,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, if (!plat_device_is_coherent(dev)) { dma_cache_wback_inv((unsigned long) ret, size); - ret = UNCAC_ADDR(ret); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } } @@ -143,7 +144,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) - addr = CAC_ADDR(addr); + if (!hw_coherentio) + addr = CAC_ADDR(addr); free_pages(addr, get_order(size)); } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index ed68073..4187102 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -104,6 +105,74 @@ static void __init fd_activate(void) } #endif +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(fw_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + hw_coherentio = supported; + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -205,6 +274,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif -- 1.7.9.5 From mcdonald.shane@gmail.com Sat Jan 12 03:31:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Jan 2013 03:31:29 +0100 (CET) Received: from mail-la0-f54.google.com ([209.85.215.54]:65192 "EHLO mail-la0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825700Ab3ALCb1yNJZt (ORCPT ); Sat, 12 Jan 2013 03:31:27 +0100 Received: by mail-la0-f54.google.com with SMTP id fp12so2303909lab.41 for ; Fri, 11 Jan 2013 18:31:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=GQsymRpZylKC4vcpvkPD8m+B7LUjxy2QcpyyFDnAsjU=; b=V/VBNxfOC/MjFhrd1OfAG8dPxXSsbFqJY6mVXFyToivfM5rb27M8uM3iGKWW/T/xI7 HxqXIpf7YNycArKLZhMucbHyoNlAZJCxBQMIYoqWDCJlmBKaCOgjAKS6Wpn+0zckcWyR Bdm6aDvrOy7I0xZC+fZ8CEYhSXapBpOe+K2OdSqvSBsqbvbexOJ08ST3zTw9MxbVBnWJ OJRaVe3aMYsUHVCbYv9qvqBeMeKeULScSlHbGoEgvQySvxlYpO53Gh1rDtwR+JPoGLF8 yYJzx6gf0Hx/NC9Ck89yRrgjbsYoara+gEaGl/0cbDncZ5P+Nd062B8Zi914fz4EbZbr Phpw== MIME-Version: 1.0 Received: by 10.112.46.70 with SMTP id t6mr32401632lbm.107.1357957881993; Fri, 11 Jan 2013 18:31:21 -0800 (PST) Received: by 10.112.114.37 with HTTP; Fri, 11 Jan 2013 18:31:21 -0800 (PST) In-Reply-To: <1357941325-25718-1-git-send-email-sjhill@mips.com> References: <1357941325-25718-1-git-send-email-sjhill@mips.com> Date: Fri, 11 Jan 2013 20:31:21 -0600 Message-ID: Subject: Re: [PATCH v3] MIPS: Add option to disable software I/O coherency. From: Shane McDonald To: "Steven J. Hill" Cc: linux-mips , Ralf Baechle Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35405 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 918 Lines: 21 On Fri, Jan 11, 2013 at 3:55 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Some MIPS controllers have hardware I/O coherency. This patch > detects those and turns off software coherency. A new kernel > command line option also allows the user to manually turn > software coherency on or off. > > Signed-off-by: Steven J. Hill > --- > arch/mips/include/asm/mach-generic/dma-coherence.h | 5 +- > arch/mips/mm/c-r4k.c | 34 +++++++--- > arch/mips/mm/dma-default.c | 6 +- > arch/mips/mti-malta/malta-setup.c | 71 ++++++++++++++++++++ > 4 files changed, 105 insertions(+), 11 deletions(-) Tested successfully on my RM7035C-based system that has CONFIG_DMA_NONCOHERENT set. My system works fine with this patch applied. Tested-by: Shane McDonald From hauke@hauke-m.de Sat Jan 12 18:14:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Jan 2013 18:14:29 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45911 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817419Ab3ALRO3Ic016 (ORCPT ); Sat, 12 Jan 2013 18:14:29 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 38A788F62; Sat, 12 Jan 2013 18:14:27 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RfpghOZFfKTw; Sat, 12 Jan 2013 18:14:17 +0100 (CET) Received: from hauke-desktop.lan (spit-414.wohnheim.uni-bremen.de [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 879908F61; Sat, 12 Jan 2013 18:14:17 +0100 (CET) From: Hauke Mehrtens To: wim@iguana.be Cc: linux-watchdog@vger.kernel.org, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v4 0/5] watchdog: bcm47xx_wdt.c: add support for SoCs with PMU Date: Sat, 12 Jan 2013 18:14:06 +0100 Message-Id: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35406 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1508 Lines: 40 This patch series improves the functions for setting the watchdog driver for bcm47xx based SoCs using ssb and bcma. This makes the watchdog driver use the platform device provided by bcma or ssb. This code is currently based on the linux-watchdog/master tree by Wim Van Sebroeck. v4: * Just the parts changing the watchdog driver itself and not ssb or bcma. v3: * Remove changes done to the watchdog driver so John could pull this into wireless-testing, this sill works with the old watchdog driver. The patches changing the watchdog driver will be send later. This was done to get this into 3.8 because Wim Van Sebroeck is neither giving an Ack or a Nack on these patches and we want to do more changes to bcma/ssb on top of these. v2: * reword some commit messages * rebase on current wireless-testing/master with "ssb: extif: fix compile errors" applied on top of it. * do not change value of WDT_SOFTTIMER_MAX * moved some small changes in the bcm47xx_wdt.c patches Hauke Mehrtens (5): watchdog: bcm47xx_wdt.c: convert to watchdog core api watchdog: bcm47xx_wdt.c: use platform device watchdog: bcm47xx_wdt.c: rename ops methods watchdog: bcm47xx_wdt.c: rename wdt_time to timeout watchdog: bcm47xx_wdt.c: add hard timer drivers/watchdog/Kconfig | 1 + drivers/watchdog/bcm47xx_wdt.c | 339 +++++++++++++++++----------------------- include/linux/bcm47xx_wdt.h | 9 ++ 3 files changed, 154 insertions(+), 195 deletions(-) -- 1.7.10.4 From hauke@hauke-m.de Sat Jan 12 18:14:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Jan 2013 18:14:47 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45912 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816206Ab3ALRO3Jw5g1 (ORCPT ); Sat, 12 Jan 2013 18:14:29 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 9ECB38F6A; Sat, 12 Jan 2013 18:14:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kd+rRvRSs7DC; Sat, 12 Jan 2013 18:14:18 +0100 (CET) Received: from hauke-desktop.lan (spit-414.wohnheim.uni-bremen.de [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id E31958F62; Sat, 12 Jan 2013 18:14:17 +0100 (CET) From: Hauke Mehrtens To: wim@iguana.be Cc: linux-watchdog@vger.kernel.org, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v4 1/5] watchdog: bcm47xx_wdt.c: convert to watchdog core api Date: Sat, 12 Jan 2013 18:14:07 +0100 Message-Id: <1358010851-28077-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> References: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35407 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6884 Lines: 275 Convert the bcm47xx_wdt.c driver to the new watchdog core api. The nowayout parameter is now added unconditionally to the module. Signed-off-by: Hauke Mehrtens --- drivers/watchdog/Kconfig | 1 + drivers/watchdog/bcm47xx_wdt.c | 152 ++++++---------------------------------- 2 files changed, 23 insertions(+), 130 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 7f809fd..e6eb363 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -971,6 +971,7 @@ config ATH79_WDT config BCM47XX_WDT tristate "Broadcom BCM47xx Watchdog Timer" depends on BCM47XX + select WATCHDOG_CORE help Hardware driver for the Broadcom BCM47xx Watchdog Timer. diff --git a/drivers/watchdog/bcm47xx_wdt.c b/drivers/watchdog/bcm47xx_wdt.c index bc0e91e..4c520d6 100644 --- a/drivers/watchdog/bcm47xx_wdt.c +++ b/drivers/watchdog/bcm47xx_wdt.c @@ -14,15 +14,12 @@ #include #include -#include #include #include -#include #include #include #include #include -#include #include #include #include @@ -41,15 +38,11 @@ module_param(wdt_time, int, 0); MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default=" __MODULE_STRING(WDT_DEFAULT_TIME) ")"); -#ifdef CONFIG_WATCHDOG_NOWAYOUT module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -#endif -static unsigned long bcm47xx_wdt_busy; -static char expect_release; static struct timer_list wdt_timer; static atomic_t ticks; @@ -97,29 +90,31 @@ static void bcm47xx_timer_tick(unsigned long unused) } } -static inline void bcm47xx_wdt_pet(void) +static int bcm47xx_wdt_keepalive(struct watchdog_device *wdd) { atomic_set(&ticks, wdt_time); + + return 0; } -static void bcm47xx_wdt_start(void) +static int bcm47xx_wdt_start(struct watchdog_device *wdd) { bcm47xx_wdt_pet(); bcm47xx_timer_tick(0); + + return 0; } -static void bcm47xx_wdt_pause(void) +static int bcm47xx_wdt_stop(struct watchdog_device *wdd) { del_timer_sync(&wdt_timer); bcm47xx_wdt_hw_stop(); -} -static void bcm47xx_wdt_stop(void) -{ - bcm47xx_wdt_pause(); + return 0; } -static int bcm47xx_wdt_settimeout(int new_time) +static int bcm47xx_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int new_time) { if ((new_time <= 0) || (new_time > WDT_MAX_TIME)) return -EINVAL; @@ -128,51 +123,6 @@ static int bcm47xx_wdt_settimeout(int new_time) return 0; } -static int bcm47xx_wdt_open(struct inode *inode, struct file *file) -{ - if (test_and_set_bit(0, &bcm47xx_wdt_busy)) - return -EBUSY; - - bcm47xx_wdt_start(); - return nonseekable_open(inode, file); -} - -static int bcm47xx_wdt_release(struct inode *inode, struct file *file) -{ - if (expect_release == 42) { - bcm47xx_wdt_stop(); - } else { - pr_crit("Unexpected close, not stopping watchdog!\n"); - bcm47xx_wdt_start(); - } - - clear_bit(0, &bcm47xx_wdt_busy); - expect_release = 0; - return 0; -} - -static ssize_t bcm47xx_wdt_write(struct file *file, const char __user *data, - size_t len, loff_t *ppos) -{ - if (len) { - if (!nowayout) { - size_t i; - - expect_release = 0; - - for (i = 0; i != len; i++) { - char c; - if (get_user(c, data + i)) - return -EFAULT; - if (c == 'V') - expect_release = 42; - } - } - bcm47xx_wdt_pet(); - } - return len; -} - static const struct watchdog_info bcm47xx_wdt_info = { .identity = DRV_NAME, .options = WDIOF_SETTIMEOUT | @@ -180,80 +130,25 @@ static const struct watchdog_info bcm47xx_wdt_info = { WDIOF_MAGICCLOSE, }; -static long bcm47xx_wdt_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - void __user *argp = (void __user *)arg; - int __user *p = argp; - int new_value, retval = -EINVAL; - - switch (cmd) { - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &bcm47xx_wdt_info, - sizeof(bcm47xx_wdt_info)) ? -EFAULT : 0; - - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - - case WDIOC_SETOPTIONS: - if (get_user(new_value, p)) - return -EFAULT; - - if (new_value & WDIOS_DISABLECARD) { - bcm47xx_wdt_stop(); - retval = 0; - } - - if (new_value & WDIOS_ENABLECARD) { - bcm47xx_wdt_start(); - retval = 0; - } - - return retval; - - case WDIOC_KEEPALIVE: - bcm47xx_wdt_pet(); - return 0; - - case WDIOC_SETTIMEOUT: - if (get_user(new_value, p)) - return -EFAULT; - - if (bcm47xx_wdt_settimeout(new_value)) - return -EINVAL; - - bcm47xx_wdt_pet(); - - case WDIOC_GETTIMEOUT: - return put_user(wdt_time, p); - - default: - return -ENOTTY; - } -} - static int bcm47xx_wdt_notify_sys(struct notifier_block *this, - unsigned long code, void *unused) + unsigned long code, void *unused) { if (code == SYS_DOWN || code == SYS_HALT) bcm47xx_wdt_stop(); return NOTIFY_DONE; } -static const struct file_operations bcm47xx_wdt_fops = { +static struct watchdog_ops bcm47xx_wdt_ops = { .owner = THIS_MODULE, - .llseek = no_llseek, - .unlocked_ioctl = bcm47xx_wdt_ioctl, - .open = bcm47xx_wdt_open, - .release = bcm47xx_wdt_release, - .write = bcm47xx_wdt_write, + .start = bcm47xx_wdt_start, + .stop = bcm47xx_wdt_stop, + .ping = bcm47xx_wdt_keepalive, + .set_timeout = bcm47xx_wdt_set_timeout, }; -static struct miscdevice bcm47xx_wdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &bcm47xx_wdt_fops, +static struct watchdog_device bcm47xx_wdt_wdd = { + .info = &bcm47xx_wdt_info, + .ops = &bcm47xx_wdt_ops, }; static struct notifier_block bcm47xx_wdt_notifier = { @@ -274,12 +169,13 @@ static int __init bcm47xx_wdt_init(void) pr_info("wdt_time value must be 0 < wdt_time < %d, using %d\n", (WDT_MAX_TIME + 1), wdt_time); } + watchdog_set_nowayout(&bcm47xx_wdt_wdd, nowayout); ret = register_reboot_notifier(&bcm47xx_wdt_notifier); if (ret) return ret; - ret = misc_register(&bcm47xx_wdt_miscdev); + ret = watchdog_register_device(&bcm47xx_wdt_wdd); if (ret) { unregister_reboot_notifier(&bcm47xx_wdt_notifier); return ret; @@ -292,10 +188,7 @@ static int __init bcm47xx_wdt_init(void) static void __exit bcm47xx_wdt_exit(void) { - if (!nowayout) - bcm47xx_wdt_stop(); - - misc_deregister(&bcm47xx_wdt_miscdev); + watchdog_unregister_device(&bcm47xx_wdt_wdd); unregister_reboot_notifier(&bcm47xx_wdt_notifier); } @@ -306,4 +199,3 @@ module_exit(bcm47xx_wdt_exit); MODULE_AUTHOR("Aleksandar Radovanovic"); MODULE_DESCRIPTION("Watchdog driver for Broadcom BCM47xx"); MODULE_LICENSE("GPL"); -MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- 1.7.10.4 From hauke@hauke-m.de Sat Jan 12 18:14:32 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Jan 2013 18:15:08 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45924 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6820505Ab3ALROc5sBly (ORCPT ); Sat, 12 Jan 2013 18:14:32 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 9BDE48F61; Sat, 12 Jan 2013 18:14:32 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KpMZiZr3JRpo; Sat, 12 Jan 2013 18:14:27 +0100 (CET) Received: from hauke-desktop.lan (spit-414.wohnheim.uni-bremen.de [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 7C9798F67; Sat, 12 Jan 2013 18:14:18 +0100 (CET) From: Hauke Mehrtens To: wim@iguana.be Cc: linux-watchdog@vger.kernel.org, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v4 3/5] watchdog: bcm47xx_wdt.c: rename ops methods Date: Sat, 12 Jan 2013 18:14:09 +0100 Message-Id: <1358010851-28077-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> References: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35408 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3755 Lines: 114 Rename the methods registered to struct watchdog_ops bcm47xx_wdt_ops in order to add an other struct watchdog_ops using different ops in the next patch. Also rename WDT_MAX_TIME to WDT_SOFTTIMER_MAX. Signed-off-by: Hauke Mehrtens --- drivers/watchdog/bcm47xx_wdt.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/watchdog/bcm47xx_wdt.c b/drivers/watchdog/bcm47xx_wdt.c index cf1191b..ed10762 100644 --- a/drivers/watchdog/bcm47xx_wdt.c +++ b/drivers/watchdog/bcm47xx_wdt.c @@ -30,7 +30,7 @@ #define DRV_NAME "bcm47xx_wdt" #define WDT_DEFAULT_TIME 30 /* seconds */ -#define WDT_MAX_TIME 255 /* seconds */ +#define WDT_SOFTTIMER_MAX 255 /* seconds */ static int wdt_time = WDT_DEFAULT_TIME; static bool nowayout = WATCHDOG_NOWAYOUT; @@ -49,7 +49,7 @@ static inline struct bcm47xx_wdt *bcm47xx_wdt_get(struct watchdog_device *wdd) return container_of(wdd, struct bcm47xx_wdt, wdd); } -static void bcm47xx_timer_tick(unsigned long data) +static void bcm47xx_wdt_soft_timer_tick(unsigned long data) { struct bcm47xx_wdt *wdt = (struct bcm47xx_wdt *)data; u32 next_tick = min(wdt->wdd.timeout * 1000, wdt->max_timer_ms); @@ -62,7 +62,7 @@ static void bcm47xx_timer_tick(unsigned long data) } } -static int bcm47xx_wdt_keepalive(struct watchdog_device *wdd) +static int bcm47xx_wdt_soft_keepalive(struct watchdog_device *wdd) { struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); @@ -71,17 +71,17 @@ static int bcm47xx_wdt_keepalive(struct watchdog_device *wdd) return 0; } -static int bcm47xx_wdt_start(struct watchdog_device *wdd) +static int bcm47xx_wdt_soft_start(struct watchdog_device *wdd) { struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); - bcm47xx_wdt_keepalive(wdd); - bcm47xx_timer_tick((unsigned long)wdt); + bcm47xx_wdt_soft_keepalive(wdd); + bcm47xx_wdt_soft_timer_tick((unsigned long)wdt); return 0; } -static int bcm47xx_wdt_stop(struct watchdog_device *wdd) +static int bcm47xx_wdt_soft_stop(struct watchdog_device *wdd) { struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); @@ -91,12 +91,12 @@ static int bcm47xx_wdt_stop(struct watchdog_device *wdd) return 0; } -static int bcm47xx_wdt_set_timeout(struct watchdog_device *wdd, - unsigned int new_time) +static int bcm47xx_wdt_soft_set_timeout(struct watchdog_device *wdd, + unsigned int new_time) { - if (new_time < 1 || new_time > WDT_MAX_TIME) { + if (new_time < 1 || new_time > WDT_SOFTTIMER_MAX) { pr_warn("timeout value must be 1<=x<=%d, using %d\n", - WDT_MAX_TIME, new_time); + WDT_SOFTTIMER_MAX, new_time); return -EINVAL; } @@ -122,12 +122,12 @@ static int bcm47xx_wdt_notify_sys(struct notifier_block *this, return NOTIFY_DONE; } -static struct watchdog_ops bcm47xx_wdt_ops = { +static struct watchdog_ops bcm47xx_wdt_soft_ops = { .owner = THIS_MODULE, - .start = bcm47xx_wdt_start, - .stop = bcm47xx_wdt_stop, - .ping = bcm47xx_wdt_keepalive, - .set_timeout = bcm47xx_wdt_set_timeout, + .start = bcm47xx_wdt_soft_start, + .stop = bcm47xx_wdt_soft_stop, + .ping = bcm47xx_wdt_soft_keepalive, + .set_timeout = bcm47xx_wdt_soft_set_timeout, }; static int __devinit bcm47xx_wdt_probe(struct platform_device *pdev) @@ -138,10 +138,10 @@ static int __devinit bcm47xx_wdt_probe(struct platform_device *pdev) if (!wdt) return -ENXIO; - setup_timer(&wdt->soft_timer, bcm47xx_timer_tick, + setup_timer(&wdt->soft_timer, bcm47xx_wdt_soft_timer_tick, (long unsigned int)wdt); - wdt->wdd.ops = &bcm47xx_wdt_ops; + wdt->wdd.ops = &bcm47xx_wdt_soft_ops; wdt->wdd.info = &bcm47xx_wdt_info; wdt->wdd.timeout = WDT_DEFAULT_TIME; ret = wdt->wdd.ops->set_timeout(&wdt->wdd, timeout); -- 1.7.10.4 From hauke@hauke-m.de Sat Jan 12 18:14:34 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Jan 2013 18:15:26 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45930 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823015Ab3ALROeib7TE (ORCPT ); Sat, 12 Jan 2013 18:14:34 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 5007D8F61; Sat, 12 Jan 2013 18:14:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fFzfDbJETiMY; Sat, 12 Jan 2013 18:14:26 +0100 (CET) Received: from hauke-desktop.lan (spit-414.wohnheim.uni-bremen.de [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 3111B8F65; Sat, 12 Jan 2013 18:14:18 +0100 (CET) From: Hauke Mehrtens To: wim@iguana.be Cc: linux-watchdog@vger.kernel.org, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v4 2/5] watchdog: bcm47xx_wdt.c: use platform device Date: Sat, 12 Jan 2013 18:14:08 +0100 Message-Id: <1358010851-28077-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> References: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35409 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8302 Lines: 300 Instead of accessing the function to set the watchdog timer directly, register a platform driver the platform could register to use this watchdog driver. Signed-off-by: Hauke Mehrtens --- drivers/watchdog/bcm47xx_wdt.c | 156 ++++++++++++++++++++-------------------- include/linux/bcm47xx_wdt.h | 9 +++ 2 files changed, 87 insertions(+), 78 deletions(-) diff --git a/drivers/watchdog/bcm47xx_wdt.c b/drivers/watchdog/bcm47xx_wdt.c index 4c520d6..cf1191b 100644 --- a/drivers/watchdog/bcm47xx_wdt.c +++ b/drivers/watchdog/bcm47xx_wdt.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008 Aleksandar Radovanovic * Copyright (C) 2009 Matthieu CASTET + * Copyright (C) 2012 Hauke Mehrtens * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -12,19 +13,19 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include #include #include #include +#include #include #include #include #include #include -#include -#include #define DRV_NAME "bcm47xx_wdt" @@ -43,48 +44,19 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -static struct timer_list wdt_timer; -static atomic_t ticks; - -static inline void bcm47xx_wdt_hw_start(void) +static inline struct bcm47xx_wdt *bcm47xx_wdt_get(struct watchdog_device *wdd) { - /* this is 2,5s on 100Mhz clock and 2s on 133 Mhz */ - switch (bcm47xx_bus_type) { -#ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0xfffffff); - break; -#endif -#ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: - bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, - 0xfffffff); - break; -#endif - } + return container_of(wdd, struct bcm47xx_wdt, wdd); } -static inline int bcm47xx_wdt_hw_stop(void) +static void bcm47xx_timer_tick(unsigned long data) { - switch (bcm47xx_bus_type) { -#ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - return ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0); -#endif -#ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: - bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0); - return 0; -#endif - } - return -EINVAL; -} + struct bcm47xx_wdt *wdt = (struct bcm47xx_wdt *)data; + u32 next_tick = min(wdt->wdd.timeout * 1000, wdt->max_timer_ms); -static void bcm47xx_timer_tick(unsigned long unused) -{ - if (!atomic_dec_and_test(&ticks)) { - bcm47xx_wdt_hw_start(); - mod_timer(&wdt_timer, jiffies + HZ); + if (!atomic_dec_and_test(&wdt->soft_ticks)) { + wdt->timer_set_ms(wdt, next_tick); + mod_timer(&wdt->soft_timer, jiffies + HZ); } else { pr_crit("Watchdog will fire soon!!!\n"); } @@ -92,23 +64,29 @@ static void bcm47xx_timer_tick(unsigned long unused) static int bcm47xx_wdt_keepalive(struct watchdog_device *wdd) { - atomic_set(&ticks, wdt_time); + struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); + + atomic_set(&wdt->soft_ticks, wdd->timeout); return 0; } static int bcm47xx_wdt_start(struct watchdog_device *wdd) { - bcm47xx_wdt_pet(); - bcm47xx_timer_tick(0); + struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); + + bcm47xx_wdt_keepalive(wdd); + bcm47xx_timer_tick((unsigned long)wdt); return 0; } static int bcm47xx_wdt_stop(struct watchdog_device *wdd) { - del_timer_sync(&wdt_timer); - bcm47xx_wdt_hw_stop(); + struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); + + del_timer_sync(&wdt->soft_timer); + wdt->timer_set(wdt, 0); return 0; } @@ -116,10 +94,13 @@ static int bcm47xx_wdt_stop(struct watchdog_device *wdd) static int bcm47xx_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_time) { - if ((new_time <= 0) || (new_time > WDT_MAX_TIME)) + if (new_time < 1 || new_time > WDT_MAX_TIME) { + pr_warn("timeout value must be 1<=x<=%d, using %d\n", + WDT_MAX_TIME, new_time); return -EINVAL; + } - wdt_time = new_time; + wdd->timeout = new_time; return 0; } @@ -133,8 +114,11 @@ static const struct watchdog_info bcm47xx_wdt_info = { static int bcm47xx_wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { + struct bcm47xx_wdt *wdt; + + wdt = container_of(this, struct bcm47xx_wdt, notifier); if (code == SYS_DOWN || code == SYS_HALT) - bcm47xx_wdt_stop(); + wdt->wdd.ops->stop(&wdt->wdd); return NOTIFY_DONE; } @@ -146,56 +130,72 @@ static struct watchdog_ops bcm47xx_wdt_ops = { .set_timeout = bcm47xx_wdt_set_timeout, }; -static struct watchdog_device bcm47xx_wdt_wdd = { - .info = &bcm47xx_wdt_info, - .ops = &bcm47xx_wdt_ops, -}; - -static struct notifier_block bcm47xx_wdt_notifier = { - .notifier_call = bcm47xx_wdt_notify_sys, -}; - -static int __init bcm47xx_wdt_init(void) +static int __devinit bcm47xx_wdt_probe(struct platform_device *pdev) { int ret; + struct bcm47xx_wdt *wdt = dev_get_platdata(&pdev->dev); - if (bcm47xx_wdt_hw_stop() < 0) - return -ENODEV; + if (!wdt) + return -ENXIO; - setup_timer(&wdt_timer, bcm47xx_timer_tick, 0L); + setup_timer(&wdt->soft_timer, bcm47xx_timer_tick, + (long unsigned int)wdt); - if (bcm47xx_wdt_settimeout(wdt_time)) { - bcm47xx_wdt_settimeout(WDT_DEFAULT_TIME); - pr_info("wdt_time value must be 0 < wdt_time < %d, using %d\n", - (WDT_MAX_TIME + 1), wdt_time); - } - watchdog_set_nowayout(&bcm47xx_wdt_wdd, nowayout); + wdt->wdd.ops = &bcm47xx_wdt_ops; + wdt->wdd.info = &bcm47xx_wdt_info; + wdt->wdd.timeout = WDT_DEFAULT_TIME; + ret = wdt->wdd.ops->set_timeout(&wdt->wdd, timeout); + if (ret) + goto err_timer; + watchdog_set_nowayout(&wdt->wdd, nowayout); + + wdt->notifier.notifier_call = &bcm47xx_wdt_notify_sys; - ret = register_reboot_notifier(&bcm47xx_wdt_notifier); + ret = register_reboot_notifier(&wdt->notifier); if (ret) - return ret; + goto err_timer; - ret = watchdog_register_device(&bcm47xx_wdt_wdd); - if (ret) { - unregister_reboot_notifier(&bcm47xx_wdt_notifier); - return ret; - } + ret = watchdog_register_device(&wdt->wdd); + if (ret) + goto err_notifier; pr_info("BCM47xx Watchdog Timer enabled (%d seconds%s)\n", wdt_time, nowayout ? ", nowayout" : ""); return 0; + +err_notifier: + unregister_reboot_notifier(&wdt->notifier); +err_timer: + del_timer_sync(&wdt->soft_timer); + + return ret; } -static void __exit bcm47xx_wdt_exit(void) +static int __devexit bcm47xx_wdt_remove(struct platform_device *pdev) { - watchdog_unregister_device(&bcm47xx_wdt_wdd); + struct bcm47xx_wdt *wdt = dev_get_platdata(&pdev->dev); + + if (!wdt) + return -ENXIO; + + watchdog_unregister_device(&wdt->wdd); + unregister_reboot_notifier(&wdt->notifier); - unregister_reboot_notifier(&bcm47xx_wdt_notifier); + return 0; } -module_init(bcm47xx_wdt_init); -module_exit(bcm47xx_wdt_exit); +static struct platform_driver bcm47xx_wdt_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "bcm47xx-wdt", + }, + .probe = bcm47xx_wdt_probe, + .remove = __devexit_p(bcm47xx_wdt_remove), +}; + +module_platform_driver(bcm47xx_wdt_driver); MODULE_AUTHOR("Aleksandar Radovanovic"); +MODULE_AUTHOR("Hauke Mehrtens "); MODULE_DESCRIPTION("Watchdog driver for Broadcom BCM47xx"); MODULE_LICENSE("GPL"); diff --git a/include/linux/bcm47xx_wdt.h b/include/linux/bcm47xx_wdt.h index e5dfc25..b708786 100644 --- a/include/linux/bcm47xx_wdt.h +++ b/include/linux/bcm47xx_wdt.h @@ -1,7 +1,10 @@ #ifndef LINUX_BCM47XX_WDT_H_ #define LINUX_BCM47XX_WDT_H_ +#include +#include #include +#include struct bcm47xx_wdt { @@ -10,6 +13,12 @@ struct bcm47xx_wdt { u32 max_timer_ms; void *driver_data; + + struct watchdog_device wdd; + struct notifier_block notifier; + + struct timer_list soft_timer; + atomic_t soft_ticks; }; static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt) -- 1.7.10.4 From hauke@hauke-m.de Sat Jan 12 18:14:39 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Jan 2013 18:15:44 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45941 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823116Ab3ALROj0OP3G (ORCPT ); Sat, 12 Jan 2013 18:14:39 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 0E6088F61; Sat, 12 Jan 2013 18:14:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hGnmqNNzwGHw; Sat, 12 Jan 2013 18:14:32 +0100 (CET) Received: from hauke-desktop.lan (spit-414.wohnheim.uni-bremen.de [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id C96488F68; Sat, 12 Jan 2013 18:14:18 +0100 (CET) From: Hauke Mehrtens To: wim@iguana.be Cc: linux-watchdog@vger.kernel.org, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v4 4/5] watchdog: bcm47xx_wdt.c: rename wdt_time to timeout Date: Sat, 12 Jan 2013 18:14:10 +0100 Message-Id: <1358010851-28077-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> References: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35410 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1226 Lines: 39 Rename wdt_time to timeout to name it like the other watchdog driver do it. Signed-off-by: Hauke Mehrtens --- drivers/watchdog/bcm47xx_wdt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/bcm47xx_wdt.c b/drivers/watchdog/bcm47xx_wdt.c index ed10762..f188097 100644 --- a/drivers/watchdog/bcm47xx_wdt.c +++ b/drivers/watchdog/bcm47xx_wdt.c @@ -32,11 +32,11 @@ #define WDT_DEFAULT_TIME 30 /* seconds */ #define WDT_SOFTTIMER_MAX 255 /* seconds */ -static int wdt_time = WDT_DEFAULT_TIME; +static int timeout = WDT_DEFAULT_TIME; static bool nowayout = WATCHDOG_NOWAYOUT; -module_param(wdt_time, int, 0); -MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default=" +module_param(timeout, int, 0); +MODULE_PARM_DESC(timeout, "Watchdog time in seconds. (default=" __MODULE_STRING(WDT_DEFAULT_TIME) ")"); module_param(nowayout, bool, 0); @@ -160,7 +160,7 @@ static int __devinit bcm47xx_wdt_probe(struct platform_device *pdev) goto err_notifier; pr_info("BCM47xx Watchdog Timer enabled (%d seconds%s)\n", - wdt_time, nowayout ? ", nowayout" : ""); + timeout, nowayout ? ", nowayout" : ""); return 0; err_notifier: -- 1.7.10.4 From hauke@hauke-m.de Sat Jan 12 18:14:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Jan 2013 18:16:02 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45945 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823910Ab3ALROnu1JBl (ORCPT ); Sat, 12 Jan 2013 18:14:43 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 76C938F61; Sat, 12 Jan 2013 18:14:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gLrO6aO8GJAW; Sat, 12 Jan 2013 18:14:34 +0100 (CET) Received: from hauke-desktop.lan (spit-414.wohnheim.uni-bremen.de [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 23A678F69; Sat, 12 Jan 2013 18:14:19 +0100 (CET) From: Hauke Mehrtens To: wim@iguana.be Cc: linux-watchdog@vger.kernel.org, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v4 5/5] watchdog: bcm47xx_wdt.c: add hard timer Date: Sat, 12 Jan 2013 18:14:11 +0100 Message-Id: <1358010851-28077-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> References: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35411 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3676 Lines: 126 The more recent devices have a watchdog timer which could be configured for over 2 hours and not just 2 seconds like the first generation devices. For those devices do not use the extra software timer, but directly program the time into the register. This will automatically be used if the timer supports more than a minute. Signed-off-by: Hauke Mehrtens --- drivers/watchdog/bcm47xx_wdt.c | 69 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 63 insertions(+), 6 deletions(-) diff --git a/drivers/watchdog/bcm47xx_wdt.c b/drivers/watchdog/bcm47xx_wdt.c index f188097..9cb69ad 100644 --- a/drivers/watchdog/bcm47xx_wdt.c +++ b/drivers/watchdog/bcm47xx_wdt.c @@ -31,6 +31,7 @@ #define WDT_DEFAULT_TIME 30 /* seconds */ #define WDT_SOFTTIMER_MAX 255 /* seconds */ +#define WDT_SOFTTIMER_THRESHOLD 60 /* seconds */ static int timeout = WDT_DEFAULT_TIME; static bool nowayout = WATCHDOG_NOWAYOUT; @@ -49,6 +50,53 @@ static inline struct bcm47xx_wdt *bcm47xx_wdt_get(struct watchdog_device *wdd) return container_of(wdd, struct bcm47xx_wdt, wdd); } +static int bcm47xx_wdt_hard_keepalive(struct watchdog_device *wdd) +{ + struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); + + wdt->timer_set_ms(wdt, wdd->timeout * 1000); + + return 0; +} + +static int bcm47xx_wdt_hard_start(struct watchdog_device *wdd) +{ + return 0; +} + +static int bcm47xx_wdt_hard_stop(struct watchdog_device *wdd) +{ + struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); + + wdt->timer_set(wdt, 0); + + return 0; +} + +static int bcm47xx_wdt_hard_set_timeout(struct watchdog_device *wdd, + unsigned int new_time) +{ + struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); + u32 max_timer = wdt->max_timer_ms; + + if (new_time < 1 || new_time > max_timer / 1000) { + pr_warn("timeout value must be 1<=x<=%d, using %d\n", + max_timer / 1000, new_time); + return -EINVAL; + } + + wdd->timeout = new_time; + return 0; +} + +static struct watchdog_ops bcm47xx_wdt_hard_ops = { + .owner = THIS_MODULE, + .start = bcm47xx_wdt_hard_start, + .stop = bcm47xx_wdt_hard_stop, + .ping = bcm47xx_wdt_hard_keepalive, + .set_timeout = bcm47xx_wdt_hard_set_timeout, +}; + static void bcm47xx_wdt_soft_timer_tick(unsigned long data) { struct bcm47xx_wdt *wdt = (struct bcm47xx_wdt *)data; @@ -133,15 +181,22 @@ static struct watchdog_ops bcm47xx_wdt_soft_ops = { static int __devinit bcm47xx_wdt_probe(struct platform_device *pdev) { int ret; + bool soft; struct bcm47xx_wdt *wdt = dev_get_platdata(&pdev->dev); if (!wdt) return -ENXIO; - setup_timer(&wdt->soft_timer, bcm47xx_wdt_soft_timer_tick, - (long unsigned int)wdt); + soft = wdt->max_timer_ms < WDT_SOFTTIMER_THRESHOLD * 1000; + + if (soft) { + wdt->wdd.ops = &bcm47xx_wdt_soft_ops; + setup_timer(&wdt->soft_timer, bcm47xx_wdt_soft_timer_tick, + (long unsigned int)wdt); + } else { + wdt->wdd.ops = &bcm47xx_wdt_hard_ops; + } - wdt->wdd.ops = &bcm47xx_wdt_soft_ops; wdt->wdd.info = &bcm47xx_wdt_info; wdt->wdd.timeout = WDT_DEFAULT_TIME; ret = wdt->wdd.ops->set_timeout(&wdt->wdd, timeout); @@ -159,14 +214,16 @@ static int __devinit bcm47xx_wdt_probe(struct platform_device *pdev) if (ret) goto err_notifier; - pr_info("BCM47xx Watchdog Timer enabled (%d seconds%s)\n", - timeout, nowayout ? ", nowayout" : ""); + dev_info(&pdev->dev, "BCM47xx Watchdog Timer enabled (%d seconds%s%s)\n", + timeout, nowayout ? ", nowayout" : "", + soft ? ", Software Timer" : ""); return 0; err_notifier: unregister_reboot_notifier(&wdt->notifier); err_timer: - del_timer_sync(&wdt->soft_timer); + if (soft) + del_timer_sync(&wdt->soft_timer); return ret; } -- 1.7.10.4 From sjhill@mips.com Sun Jan 13 00:38:13 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 13 Jan 2013 00:38:15 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:33366 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824768Ab3ALXiNjusER (ORCPT ); Sun, 13 Jan 2013 00:38:13 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TuAeK-0006pC-Dr; Sat, 12 Jan 2013 17:38:04 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, mcdonald.shane@gmail.com Subject: [PATCH v4] MIPS: Add option to disable software I/O coherency. Date: Sat, 12 Jan 2013 17:38:00 -0600 Message-Id: <1358033880-18652-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35412 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7127 Lines: 243 From: "Steven J. Hill" Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mach-generic/dma-coherence.h | 5 +- arch/mips/mm/c-r4k.c | 34 +++++++--- arch/mips/mm/dma-default.c | 6 +- arch/mips/mti-malta/malta-setup.c | 71 ++++++++++++++++++++ arch/mips/mti-sead3/sead3-setup.c | 4 +- 5 files changed, 106 insertions(+), 14 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177..cd17f22 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -57,13 +57,16 @@ static inline int plat_dma_mapping_error(struct device *dev, return 0; } +extern int coherentio; +extern int hw_coherentio; + static inline int plat_device_is_coherent(struct device *dev) { #ifdef CONFIG_DMA_COHERENT return 1; #endif #ifdef CONFIG_DMA_NONCOHERENT - return 0; + return coherentio; #endif } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 606e828..e4ee358 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1379,19 +1379,34 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; +int coherentio = 0; /* no DMA cache coherency (may be set by user) */ +int hw_coherentio = 0; /* no HW DMA cache coherency (reflects real HW) */ static int __init setcoherentio(char *str) { - coherentio = 1; + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); return 0; } - early_param("coherentio", setcoherentio); -#endif + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 0; +} +early_param("nocoherentio", setnocoherentio); static void __cpuinit r4k_cache_error_setup(void) { @@ -1415,6 +1430,7 @@ void __cpuinit r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); + extern int coherentio; struct cpuinfo_mips *c = ¤t_cpu_data; probe_pcache(); @@ -1474,9 +1490,11 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* We want to run CMP kernels on core(s) with and without coherent caches */ + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); board_cache_error_setup = r4k_cache_error_setup; } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 3fab204..aad5f7e 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -115,7 +115,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, if (!plat_device_is_coherent(dev)) { dma_cache_wback_inv((unsigned long) ret, size); - ret = UNCAC_ADDR(ret); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } } @@ -143,7 +144,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) - addr = CAC_ADDR(addr); + if (!hw_coherentio) + addr = CAC_ADDR(addr); free_pages(addr, get_order(size)); } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index ed68073..4187102 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -104,6 +105,74 @@ static void __init fd_activate(void) } #endif +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(fw_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + hw_coherentio = supported; + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -205,6 +274,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c index af8903d..7610069 100644 --- a/arch/mips/mti-sead3/sead3-setup.c +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -11,9 +11,7 @@ #include #include - -int coherentio; /* 0 => no DMA cache coherency (may be set by user) */ -int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */ +#include const char *get_system_type(void) { -- 1.7.9.5 From sjhill@mips.com Sun Jan 13 00:38:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 13 Jan 2013 00:38:34 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:33370 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824793Ab3ALXiQvPRnP (ORCPT ); Sun, 13 Jan 2013 00:38:16 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TuAeQ-0006pH-SO; Sat, 12 Jan 2013 17:38:10 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2] MIPS: microMIPS: Add breakpoints. Date: Sat, 12 Jan 2013 17:38:06 -0600 Message-Id: <1358033886-18686-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35413 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1142 Lines: 33 From: "Steven J. Hill" Redefine BRK_BUG and BRK_KDB values for a pure microMIPS kernel. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/break.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 9161e68..487feb8 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -27,9 +27,16 @@ #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ + +#ifdef CONFIG_CPU_MICROMIPS +#define BRK_BUG 12 /* Used by BUG() */ +#define BRK_KDB 13 /* Used in KDB_ENTER() */ +#define BRK_MEMU 14 /* Used by FPU emulator */ +#else #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ #define BRK_MEMU 514 /* Used by FPU emulator */ +#endif #define BRK_KPROBE_BP 515 /* Kprobe break */ #define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */ #define BRK_MULOVF 1023 /* Multiply overflow */ -- 1.7.9.5 From sjhill@mips.com Sun Jan 13 00:38:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 13 Jan 2013 00:38:59 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:33371 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824787Ab3ALXiXLbEw- (ORCPT ); Sun, 13 Jan 2013 00:38:23 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TuAeW-0006pN-F5; Sat, 12 Jan 2013 17:38:16 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, Leonid Yegoshin Subject: [PATCH v100,03/13] MIPS: microMIPS: Floating point support for 16-bit instructions. Date: Sat, 12 Jan 2013 17:38:12 -0600 Message-Id: <1358033892-18721-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35414 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 33439 Lines: 1010 From: "Steven J. Hill" Add logic needed to do floating point emulation when in microMIPS or MIPS16e modes. Signed-off-by: Leonid Yegoshin Signed-off-by: Steven J. Hill --- arch/mips/include/asm/fpu_emulator.h | 6 + arch/mips/kernel/traps.c | 2 +- arch/mips/math-emu/cp1emu.c | 766 ++++++++++++++++++++++++++++++---- arch/mips/math-emu/dsemul.c | 37 +- 4 files changed, 714 insertions(+), 97 deletions(-) diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 3b40927..e7edb84 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -54,6 +54,12 @@ do { \ extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); extern int do_dsemulret(struct pt_regs *xcp); +extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, + struct mips_fpu_struct *ctx, int has_fpu, + void *__user *fault_addr); +int process_fpemu_return(int sig, void __user *fault_addr); +int mm_isBranchInstr(struct pt_regs *regs, struct decoded_instn dec_insn, + unsigned long *contpc); /* * Instruction inserted following the badinst to further tag the sequence diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e3a5f3d..313fc68 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -675,7 +675,7 @@ asmlinkage void do_ov(struct pt_regs *regs) force_sig_info(SIGFPE, &info, current); } -static int process_fpemu_return(int sig, void __user *fault_addr) +int process_fpemu_return(int sig, void __user *fault_addr) { if (sig == SIGSEGV || sig == SIGBUS) { struct siginfo si = {0}; diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 47c77e7..d0fd160 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -110,6 +111,477 @@ static const unsigned int fpucondbit[8] = { }; #endif +/* convert 16-bit register encoding to 32-bit register encoding */ +static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; + +/* convert micro_mips to mips32 format */ +static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; +static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; +static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; +static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; + +/* + * This functions translates a 32 bit micro_mips instr into a 32 bit mips32 instr. + * It return 0 or SIGILL. + */ +static int micro_mips32_to_mips32(union mips_instruction *insn_ptr) +{ + union mips_instruction insn = *insn_ptr; + union mips_instruction mips32_insn = insn; /* assume they are the same */ + int func; + int fmt; + int op; + + switch (insn.mm_i_format.opcode) { + case mm_ldc132_op: + mips32_insn.mm_i_format.opcode = ldc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_lwc132_op: + mips32_insn.mm_i_format.opcode = lwc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_sdc132_op: + mips32_insn.mm_i_format.opcode = sdc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_swc132_op: + mips32_insn.mm_i_format.opcode = swc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_pool32i_op: + /* NOTE: offset is << by 1 if in micro_mips mode */ + if ((insn.mm_i_format.rt == mm_bc1f_op) || (insn.mm_i_format.rt == mm_bc1t_op)) { + mips32_insn.fb_format.opcode = cop1_op; + mips32_insn.fb_format.bc = bc_op; + mips32_insn.fb_format.flag = (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; + } else + return SIGILL; + break; + case mm_pool32f_op: + switch (insn.mm_fp0_format.func) { + case mm_32f_01_op: + case mm_32f_11_op: + case mm_32f_02_op: + case mm_32f_12_op: + case mm_32f_41_op: + case mm_32f_51_op: + case mm_32f_42_op: + case mm_32f_52_op: + op = insn.mm_fp0_format.func; + if (op == mm_32f_01_op) + func = madd_s_op; + else if (op == mm_32f_11_op) + func = madd_d_op; + else if (op == mm_32f_02_op) + func = nmadd_s_op; + else if (op == mm_32f_12_op) + func = nmadd_d_op; + else if (op == mm_32f_41_op) + func = msub_s_op; + else if (op == mm_32f_51_op) + func = msub_d_op; + else if (op == mm_32f_42_op) + func = nmsub_s_op; + else + func = nmsub_d_op; + mips32_insn.fp6_format.opcode = cop1x_op; + mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; + mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; + mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; + mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; + mips32_insn.fp6_format.func = func; + break; + case mm_32f_10_op: + func = -1; /* set to invalid value */ + op = insn.mm_fp5_format.op & 0x7; + if (op == mm_ldxc1_op) + func = ldxc1_op; + else if (op == mm_sdxc1_op) + func = sdxc1_op; + else if (op == mm_lwxc1_op) + func = lwxc1_op; + else if (op == mm_swxc1_op) + func = swxc1_op; + + if (func != -1) { + mips32_insn.r_format.opcode = cop1x_op; + mips32_insn.r_format.rs = insn.mm_fp5_format.base; + mips32_insn.r_format.rt = insn.mm_fp5_format.index; + mips32_insn.r_format.rd = 0; + mips32_insn.r_format.re = insn.mm_fp5_format.fd; + mips32_insn.r_format.func = func; + } else + return SIGILL; + break; + case mm_32f_40_op: + op = -1; /* set to invalid value */ + if (insn.mm_fp2_format.op == mm_fmovt_op) + op = 1; + else if (insn.mm_fp2_format.op == mm_fmovf_op) + op = 0; + if (op != -1) { + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp2_format.fmt]; + mips32_insn.fp0_format.ft = (insn.mm_fp2_format.cc<<2) + op; + mips32_insn.fp0_format.fs = insn.mm_fp2_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp2_format.fd; + mips32_insn.fp0_format.func = fmovc_op; + } else + return SIGILL; + break; + case mm_32f_60_op: + func = -1; /* set to invalid value */ + if (insn.mm_fp0_format.op == mm_fadd_op) + func = fadd_op; + else if (insn.mm_fp0_format.op == mm_fsub_op) + func = fsub_op; + else if (insn.mm_fp0_format.op == mm_fmul_op) + func = fmul_op; + else if (insn.mm_fp0_format.op == mm_fdiv_op) + func = fdiv_op; + if (func != -1) { + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp0_format.fmt]; + mips32_insn.fp0_format.ft = insn.mm_fp0_format.ft; + mips32_insn.fp0_format.fs = insn.mm_fp0_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp0_format.fd; + mips32_insn.fp0_format.func = func; + } else + return SIGILL; + break; + case mm_32f_70_op: + func = -1; /* set to invalid value */ + if (insn.mm_fp0_format.op == mm_fmovn_op) + func = fmovn_op; + else if (insn.mm_fp0_format.op == mm_fmovz_op) + func = fmovz_op; + if (func != -1) { + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp0_format.fmt]; + mips32_insn.fp0_format.ft = insn.mm_fp0_format.ft; + mips32_insn.fp0_format.fs = insn.mm_fp0_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp0_format.fd; + mips32_insn.fp0_format.func = func; + } else + return SIGILL; + break; + case mm_32f_73_op: /* POOL32FXF */ + switch (insn.mm_fp1_format.op) { + case mm_movf0_op: + case mm_movf1_op: + case mm_movt0_op: + case mm_movt1_op: + if ((insn.mm_fp1_format.op & 0x7f) == mm_movf0_op) + op = 0; + else + op = 1; + mips32_insn.r_format.opcode = spec_op; + mips32_insn.r_format.rs = insn.mm_fp4_format.fs; + mips32_insn.r_format.rt = (insn.mm_fp4_format.cc<<2) + op; + mips32_insn.r_format.rd = insn.mm_fp4_format.rt; + mips32_insn.r_format.re = 0; + mips32_insn.r_format.func = movc_op; + break; + case mm_fcvtd0_op: + case mm_fcvtd1_op: + case mm_fcvts0_op: + case mm_fcvts1_op: + if ((insn.mm_fp1_format.op & 0x7f) == mm_fcvtd0_op) { + func = fcvtd_op; + fmt = swl_format[insn.mm_fp3_format.fmt]; + } else { + func = fcvts_op; + fmt = dwl_format[insn.mm_fp3_format.fmt]; + } + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = fmt; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp3_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp3_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_fmov0_op: + case mm_fmov1_op: + case mm_fabs0_op: + case mm_fabs1_op: + case mm_fneg0_op: + case mm_fneg1_op: + if ((insn.mm_fp1_format.op & 0x7f) == mm_fmov0_op) + func = fmov_op; + else if ((insn.mm_fp1_format.op & 0x7f) == mm_fabs0_op) + func = fabs_op; + else + func = fneg_op; + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp3_format.fmt]; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp3_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp3_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_ffloorl_op: + case mm_ffloorw_op: + case mm_fceill_op: + case mm_fceilw_op: + case mm_ftruncl_op: + case mm_ftruncw_op: + case mm_froundl_op: + case mm_froundw_op: + case mm_fcvtl_op: + case mm_fcvtw_op: + if (insn.mm_fp1_format.op == mm_ffloorl_op) + func = ffloorl_op; + else if (insn.mm_fp1_format.op == mm_ffloorw_op) + func = ffloor_op; + else if (insn.mm_fp1_format.op == mm_fceill_op) + func = fceill_op; + else if (insn.mm_fp1_format.op == mm_fceilw_op) + func = fceil_op; + else if (insn.mm_fp1_format.op == mm_ftruncl_op) + func = ftruncl_op; + else if (insn.mm_fp1_format.op == mm_ftruncw_op) + func = ftrunc_op; + else if (insn.mm_fp1_format.op == mm_froundl_op) + func = froundl_op; + else if (insn.mm_fp1_format.op == mm_froundw_op) + func = fround_op; + else if (insn.mm_fp1_format.op == mm_fcvtl_op) + func = fcvtl_op; + else + func = fcvtw_op; + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sd_format[insn.mm_fp1_format.fmt]; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp1_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp1_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_frsqrt_op: + case mm_fsqrt_op: + case mm_frecip_op: + if (insn.mm_fp1_format.op == mm_frsqrt_op) + func = frsqrt_op; + else if (insn.mm_fp1_format.op == mm_fsqrt_op) + func = fsqrt_op; + else + func = frecip_op; + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp1_format.fmt]; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp1_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp1_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_mfc1_op: + case mm_mtc1_op: + case mm_cfc1_op: + case mm_ctc1_op: + if (insn.mm_fp1_format.op == mm_mfc1_op) + op = mfc_op; + else if (insn.mm_fp1_format.op == mm_mtc1_op) + op = mtc_op; + else if (insn.mm_fp1_format.op == mm_cfc1_op) + op = cfc_op; + else + op = ctc_op; + mips32_insn.fp1_format.opcode = cop1_op; + mips32_insn.fp1_format.op = op; + mips32_insn.fp1_format.rt = insn.mm_fp1_format.rt; + mips32_insn.fp1_format.fs = insn.mm_fp1_format.fs; + mips32_insn.fp1_format.fd = 0; + mips32_insn.fp1_format.func = 0; + break; + default: + return SIGILL; + break; + } + break; + case mm_32f_74_op: /* c.cond.fmt */ + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp4_format.fmt]; + mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; + mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc<<2; + mips32_insn.fp0_format.func = insn.mm_fp4_format.cond | MIPS32_COND_FC; + break; + default: + return SIGILL; + break; + } + break; + default: + return SIGILL; + break; + } + + *insn_ptr = mips32_insn; + return 0; +} + +/* micro_mips version of isBranchInstr() */ +int mm_isBranchInstr(struct pt_regs *regs, struct decoded_instn dec_insn, + unsigned long *contpc) +{ + union mips_instruction insn = (union mips_instruction)dec_insn.insn; + int bc_false = 0; + unsigned int fcr31; + unsigned int bit; + + /* NOTE: for 16-bit instructions, they are duplicated and stored as a 32-bit value. */ + switch (insn.mm_i_format.opcode) { + case mm_pool32a_op: + if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MSK) == mm_pool32axf_op) { + switch (insn.mm_i_format.simmediate >> MM_POOL32A_MINOR_SFT) { + case mm_jalr_op: + case mm_jalrhb_op: + case mm_jalrs_op: + case mm_jalrshb_op: + if (insn.mm_i_format.rt != 0) /* not a mm_jr_op */ + regs->regs[insn.mm_i_format.rt] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + *contpc = regs->regs[insn.mm_i_format.rs]; + return 1; + break; + } + } + break; + case mm_pool32i_op: + switch (insn.mm_i_format.rt) { + case mm_bltzals_op: + case mm_bltzal_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_bltz_op: + if ((long)regs->regs[insn.mm_i_format.rs] < 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bgezals_op: + case mm_bgezal_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_bgez_op: + if ((long)regs->regs[insn.mm_i_format.rs] >= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_blez_op: + if ((long)regs->regs[insn.mm_i_format.rs] <= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bgtz_op: + if ((long)regs->regs[insn.mm_i_format.rs] <= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bc2f_op: + case mm_bc1f_op: + bc_false = 1; + /* Fall through */ + case mm_bc2t_op: + case mm_bc1t_op: + preempt_disable(); + if (is_fpu_owner()) + asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); + else + fcr31 = current->thread.fpu.fcr31; + preempt_enable(); + + if (bc_false) + fcr31 = ~fcr31; + + bit = (insn.mm_i_format.rs >> 2); + bit += (bit != 0); + bit += 23; + if (fcr31 & (1 << bit)) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + } + break; + case mm_pool16c_op: + switch (insn.mm_i_format.rt) { + case mm_jalr16_op: + case mm_jalrs16_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_jr16_op: + *contpc = regs->regs[insn.mm_i_format.rs]; + return 1; + break; + } + break; + case mm_beqz16_op: + if ((long)regs->regs[reg16to32map[insn.mm16b1_format.rs]] == 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm16b1_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bnez16_op: + if ((long)regs->regs[reg16to32map[insn.mm16b1_format.rs]] != 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm16b1_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_b16_op: + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm16b0_format.simmediate << 1); + return 1; + break; + case mm_beq32_op: + if (regs->regs[insn.mm_i_format.rs] == regs->regs[insn.mm_i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bne32_op: + if (regs->regs[insn.mm_i_format.rs] != regs->regs[insn.mm_i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_jalx32_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + + dec_insn.next_pc_inc; + *contpc = regs->cp0_epc + dec_insn.pc_inc; + *contpc >>= 28; + *contpc <<= 28; + *contpc |= (insn.j_format.target << 2); + return 1; + break; + case mm_jals32_op: + case mm_jal32_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_j32_op: + *contpc = regs->cp0_epc + dec_insn.pc_inc; + *contpc >>= 27; + *contpc <<= 27; + *contpc |= (insn.j_format.target << 1); + *contpc |= MIPS_ISA_MODE; + return 1; + break; + } + return 0; +} /* * Redundant with logic already in kernel/branch.c, @@ -117,53 +589,134 @@ static const unsigned int fpucondbit[8] = { * a single subroutine should be used across both * modules. */ -static int isBranchInstr(mips_instruction * i) +static int isBranchInstr(struct pt_regs *regs, struct decoded_instn dec_insn, unsigned long *contpc) { - switch (MIPSInst_OPCODE(*i)) { + union mips_instruction insn = (union mips_instruction)dec_insn.insn; + unsigned int fcr31; + unsigned int bit = 0; + + switch (insn.i_format.opcode) { case spec_op: - switch (MIPSInst_FUNC(*i)) { + switch (insn.r_format.func) { case jalr_op: + regs->regs[insn.r_format.rd] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ case jr_op: + *contpc = regs->regs[insn.r_format.rs]; return 1; + break; } break; - case bcond_op: - switch (MIPSInst_RT(*i)) { + switch (insn.i_format.rt) { + case bltzal_op: + case bltzall_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ case bltz_op: - case bgez_op: case bltzl_op: - case bgezl_op: - case bltzal_op: + if ((long)regs->regs[insn.i_format.rs] < 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; case bgezal_op: - case bltzall_op: case bgezall_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case bgez_op: + case bgezl_op: + if ((long)regs->regs[insn.i_format.rs] >= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; + break; } break; - - case j_op: - case jal_op: case jalx_op: + bit = MIPS_ISA_MODE; + case jal_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case j_op: + *contpc = regs->cp0_epc + dec_insn.pc_inc; + *contpc >>= 28; + *contpc <<= 28; + *contpc |= (insn.j_format.target << 2); + /* set micro_mips mode bit: xor for jalx. LY22 */ + *contpc ^= bit; + return 1; + break; case beq_op: - case bne_op: - case blez_op: - case bgtz_op: case beql_op: + if (regs->regs[insn.i_format.rs] == regs->regs[insn.i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case bne_op: case bnel_op: + if (regs->regs[insn.i_format.rs] != regs->regs[insn.i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case blez_op: case blezl_op: + if ((long)regs->regs[insn.i_format.rs] <= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case bgtz_op: case bgtzl_op: + if ((long)regs->regs[insn.i_format.rs] > 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - + break; case cop0_op: case cop1_op: case cop2_op: case cop1x_op: - if (MIPSInst_RS(*i) == bc_op) - return 1; + if (insn.i_format.rs == bc_op) { + preempt_disable(); + if (is_fpu_owner()) + asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); + else + fcr31 = current->thread.fpu.fcr31; + preempt_enable(); + + bit = (insn.i_format.rt >> 2); + bit += (bit != 0); + bit += 23; + switch (insn.i_format.rt & 3) { + case 0: /* bc1f */ + case 2: /* bc1fl */ + if (~fcr31 & (1 << bit)) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case 1: /* bc1t */ + case 3: /* bc1tl */ + if (fcr31 & (1 << bit)) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + } /* end of inner switch-statement */ + } break; } - return 0; } @@ -210,26 +763,23 @@ static inline int cop1_64bit(struct pt_regs *xcp) */ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - void *__user *fault_addr) + struct decoded_instn dec_insn, void *__user *fault_addr) { mips_instruction ir; - unsigned long emulpc, contpc; + unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; unsigned int cond; - - if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGBUS; - } - if (__get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGSEGV; - } + int pc_inc; /* XXX NEC Vr54xx bug workaround */ - if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir)) - xcp->cp0_cause &= ~CAUSEF_BD; + if (xcp->cp0_cause & CAUSEF_BD) { + if (dec_insn.micro_mips_mode) { + if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) + xcp->cp0_cause &= ~CAUSEF_BD; + } else { + if (!isBranchInstr(xcp, dec_insn, &contpc)) + xcp->cp0_cause &= ~CAUSEF_BD; + } + } if (xcp->cp0_cause & CAUSEF_BD) { /* @@ -244,32 +794,27 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * Linux MIPS branch emulator operates on context, updating the * cp0_epc. */ - emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */ - if (__compute_return_epc(xcp) < 0) { -#ifdef CP1DBG - printk("failed to emulate branch at %p\n", - (void *) (xcp->cp0_epc)); -#endif - return SIGILL; - } - if (!access_ok(VERIFY_READ, emulpc, sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)emulpc; - return SIGBUS; - } - if (__get_user(ir, (mips_instruction __user *) emulpc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)emulpc; - return SIGSEGV; - } - /* __compute_return_epc() will have updated cp0_epc */ - contpc = xcp->cp0_epc; - /* In order not to confuse ptrace() et al, tweak context */ - xcp->cp0_epc = emulpc - 4; + /* NOTE: contpc is modified by isBranchInstr() if it is a branch instr */ + + ir = dec_insn.next_insn; /* process delay slot instr */ + pc_inc = dec_insn.next_pc_inc; } else { - emulpc = xcp->cp0_epc; - contpc = xcp->cp0_epc + 4; + ir = dec_insn.insn; /* process current instr */ + pc_inc = dec_insn.pc_inc; + } + + /* Since micro_mips FPU instructios are a subset of mips32 FPU instructions, */ + /* we want to convert micro_mips FPU instructions into mips32 instrunction so */ + /* that we could reuse all of the FPU emulation code. */ + /* NOTE: we can't do this for branch instructions since they are not a subset */ + /* ex: can't emulate a 16-bit aligned target address with a mips32 instn */ + if (dec_insn.micro_mips_mode) { + /* if next instn is a 16-bit instn then it can't be FPU instn */ + /* This could happen since this function can be called with non FPU instructions. */ + if ((pc_inc == 2) || + (micro_mips32_to_mips32((union mips_instruction *)&ir) == SIGILL)) + return SIGILL; } emul: @@ -474,22 +1019,30 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, /* branch taken: emulate dslot * instruction */ - xcp->cp0_epc += 4; - contpc = (xcp->cp0_epc + - (MIPSInst_SIMM(ir) << 2)); - - if (!access_ok(VERIFY_READ, xcp->cp0_epc, - sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGBUS; - } - if (__get_user(ir, - (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGSEGV; - } + xcp->cp0_epc += dec_insn.pc_inc; + + contpc = MIPSInst_SIMM(ir); + ir = dec_insn.next_insn; + if (dec_insn.micro_mips_mode) { + contpc = (xcp->cp0_epc + (contpc << 1)); + + /* if next instn is a 16-bit instn then it can't be FPU instn */ + if ((dec_insn.next_pc_inc == 2) || + (micro_mips32_to_mips32((union mips_instruction *)&ir) == SIGILL)) { + + /* since this instn will be put on the stack with 32-bit words */ + /* get around this problem by putting a NOP16 as the 2nd instn */ + if (dec_insn.next_pc_inc == 2) + ir = (ir & (~0xffff)) | MM_NOP16; + + /* + * Single step the non-cp1 + * instruction in the dslot + */ + return mips_dsemul(xcp, ir, contpc); + } + } else + contpc = (xcp->cp0_epc + (contpc << 2)); switch (MIPSInst_OPCODE(ir)) { case lwc1_op: @@ -525,8 +1078,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * branch likely nullifies * dslot if not taken */ - xcp->cp0_epc += 4; - contpc += 4; + xcp->cp0_epc += dec_insn.pc_inc; + contpc += dec_insn.pc_inc; /* * else continue & execute * dslot as normal insn @@ -1313,25 +1866,58 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu, void *__user *fault_addr) { unsigned long oldepc, prevepc; - mips_instruction insn; + struct decoded_instn dec_insn; + u16 instr[4]; + u16 *instr_ptr; int sig = 0; oldepc = xcp->cp0_epc; do { prevepc = xcp->cp0_epc; - if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGBUS; - } - if (__get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGSEGV; + if (is16mode(xcp) && cpu_has_mmips) { + /* get the next 2 micro_mips instn and decode them into 2 mips32 instn */ + if ((get_user(instr[0], (u16 __user *)(xcp->cp0_epc & ~MIPS_ISA_MODE))) || + (get_user(instr[1], (u16 __user *)((xcp->cp0_epc+2) & ~MIPS_ISA_MODE))) || + (get_user(instr[2], (u16 __user *)((xcp->cp0_epc+4) & ~MIPS_ISA_MODE))) || + (get_user(instr[3], (u16 __user *)((xcp->cp0_epc+6) & ~MIPS_ISA_MODE)))) { + MIPS_FPU_EMU_INC_STATS(errors); + return SIGBUS; + } + instr_ptr = instr; + /* get 1st instruction */ + if (mm_is16bit(*instr_ptr)) { + dec_insn.insn = (*instr_ptr << 16) | (*instr_ptr); /* duplicate the half-word */ + dec_insn.pc_inc = 2; /* 16 bit instr */ + instr_ptr += 1; + } else { + dec_insn.insn = (*instr_ptr << 16) | *(instr_ptr+1); + dec_insn.pc_inc = 4; /* 32 bit instr */ + instr_ptr += 2; + } + /* get 2nd instruction */ + if (mm_is16bit(*instr_ptr)) { + dec_insn.next_insn = (*instr_ptr << 16) | (*instr_ptr); /* duplicate the half-word */ + dec_insn.next_pc_inc = 2; /* 16 bit instr */ + } else { + dec_insn.next_insn = (*instr_ptr << 16) | *(instr_ptr+1); + dec_insn.next_pc_inc = 4; /* 32 bit instr */ + } + dec_insn.micro_mips_mode = 1; + } else { + if ((get_user(dec_insn.insn, (mips_instruction __user *) xcp->cp0_epc)) || + (get_user(dec_insn.next_insn, (mips_instruction __user *)(xcp->cp0_epc+4)))) { + MIPS_FPU_EMU_INC_STATS(errors); + return SIGBUS; + } + dec_insn.pc_inc = 4; + dec_insn.next_pc_inc = 4; + dec_insn.micro_mips_mode = 0; } - if (insn == 0) - xcp->cp0_epc += 4; /* skip nops */ + + if ((dec_insn.insn == 0) || + ((dec_insn.pc_inc == 2) && ((dec_insn.insn & 0xffff) == MM_NOP16))) + xcp->cp0_epc += dec_insn.pc_inc; /* skip nops */ else { /* * The 'ieee754_csr' is an alias of @@ -1341,7 +1927,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, */ /* convert to ieee library modes */ ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; - sig = cop1Emulate(xcp, ctx, fault_addr); + sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); /* revert to mips rounding mode */ ieee754_csr.rm = mips_rm[ieee754_csr.rm]; } @@ -1359,6 +1945,8 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, /* but if epc has advanced, then ignore it */ sig = 0; + /*if (sig == SIGILL) printk("Illegal micro_mips FPU instruction: 0x%x, 0x%x\n", dec_insn.insn, dec_insn.next_insn);*/ + return sig; } diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 384a3b0..46dcf29 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -54,8 +54,15 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) extern asmlinkage void handle_dsemulret(void); struct emuframe __user *fr; int err; + int nop = 0; - if (ir == 0) { /* a nop is easy */ + if (regs->cp0_epc & 1) { + if ((ir >> 16) == MM_NOP16) + nop = 1; + } else if (ir == 0) + nop = 1; + + if (nop == 1) { /* a nop is easy */ regs->cp0_epc = cpc; regs->cp0_cause &= ~CAUSEF_BD; return 0; @@ -91,8 +98,17 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) return SIGBUS; - err = __put_user(ir, &fr->emul); - err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); + if (regs->cp0_epc & 1) { + err = __put_user(ir >> 16, (u16 __user *)(&fr->emul)); + err |= __put_user(ir & 0xffff, (u16 __user *)((long)(&fr->emul) + 2)); + err |= __put_user(BREAK_MATH >> 16, (u16 __user *)(&fr->badinst)); + err |= __put_user(BREAK_MATH & 0xffff, (u16 __user *)((long)(&fr->badinst) + 2)); + } else { + err = __put_user(ir, &fr->emul); + err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); + } + + /* NOTE: assume the 2nd instn is never executed => can leave as mips32 instr */ err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); err |= __put_user(cpc, &fr->epc); @@ -101,7 +117,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) return SIGBUS; } - regs->cp0_epc = (unsigned long) &fr->emul; + regs->cp0_epc = ((unsigned long) &fr->emul) | (regs->cp0_epc & 1); flush_cache_sigtramp((unsigned long)&fr->badinst); @@ -114,9 +130,11 @@ int do_dsemulret(struct pt_regs *xcp) unsigned long epc; u32 insn, cookie; int err = 0; + u32 break_math = BREAK_MATH; + u16 instr[2]; fr = (struct emuframe __user *) - (xcp->cp0_epc - sizeof(mips_instruction)); + ((xcp->cp0_epc & (~1)) - sizeof(mips_instruction)); /* * If we can't even access the area, something is very wrong, but we'll @@ -131,10 +149,15 @@ int do_dsemulret(struct pt_regs *xcp) * - Is the instruction pointed to by the EPC an BREAK_MATH? * - Is the following memory word the BD_COOKIE? */ - err = __get_user(insn, &fr->badinst); + if (xcp->cp0_epc & 1) { + err = __get_user(instr[0], (u16 __user *)(&fr->badinst)); + err |= __get_user(instr[1], (u16 __user *)((long)(&fr->badinst) + 2)); + insn = (instr[0] << 16) | instr[1]; + } else + err = __get_user(insn, &fr->badinst); err |= __get_user(cookie, &fr->cookie); - if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { + if (unlikely(err || (insn != break_math) || (cookie != BD_COOKIE))) { MIPS_FPU_EMU_INC_STATS(errors); return 0; } -- 1.7.9.5 From sjhill@mips.com Sun Jan 13 01:29:39 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 13 Jan 2013 01:29:40 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:33432 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817419Ab3AMA3jYemoZ (ORCPT ); Sun, 13 Jan 2013 01:29:39 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TuBS7-0006qh-L0; Sat, 12 Jan 2013 18:29:31 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, cernekee@gmail.com Subject: [PATCH] MIPS: Whitespace clean-ups. Date: Sat, 12 Jan 2013 18:29:27 -0600 Message-Id: <1358036967-21858-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35415 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7921 Lines: 305 From: "Steven J. Hill" Clean-up tabs, spaces, macros, etc. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/inst.h | 168 +++++++++++++++++++------------------- arch/mips/include/asm/mipsregs.h | 26 +++--- arch/mips/kernel/traps.c | 4 +- 3 files changed, 101 insertions(+), 97 deletions(-) diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index ab84064..69b072f 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -197,71 +197,71 @@ enum lx_func { */ #ifdef __MIPSEB__ struct j_format { /* Jump format */ - unsigned int opcode : 6; - unsigned int target : 26; + unsigned int opcode:6; + unsigned int target:26; }; struct i_format { /* Immediate format (addi, lw, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - signed int simmediate : 16; + unsigned int opcode:6; + unsigned int rs:5; + unsigned int rt:5; + signed int simmediate:16; }; struct u_format { /* Unsigned immediate format (ori, xori, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int uimmediate : 16; + unsigned int opcode:6; + unsigned int rs:5; + unsigned int rt:5; + unsigned int uimmediate:16; }; struct c_format { /* Cache (>= R6000) format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int c_op : 3; - unsigned int cache : 2; - unsigned int simmediate : 16; + unsigned int opcode:6; + unsigned int rs:5; + unsigned int c_op:3; + unsigned int cache:2; + unsigned int simmediate:16; }; struct r_format { /* Register format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; + unsigned int opcode:6; + unsigned int rs:5; + unsigned int rt:5; + unsigned int rd:5; + unsigned int re:5; + unsigned int func:6; }; struct p_format { /* Performance counter format (R10000) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; + unsigned int opcode:6; + unsigned int rs:5; + unsigned int rt:5; + unsigned int rd:5; + unsigned int re:5; + unsigned int func:6; }; struct f_format { /* FPU register format */ - unsigned int opcode : 6; - unsigned int : 1; - unsigned int fmt : 4; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; + unsigned int opcode:6; + unsigned int :1; + unsigned int fmt:4; + unsigned int rt:5; + unsigned int rd:5; + unsigned int re:5; + unsigned int func:6; }; struct ma_format { /* FPU multiply and add format (MIPS IV) */ - unsigned int opcode : 6; - unsigned int fr : 5; - unsigned int ft : 5; - unsigned int fs : 5; - unsigned int fd : 5; - unsigned int func : 4; - unsigned int fmt : 2; + unsigned int opcode:6; + unsigned int fr:5; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:4; + unsigned int fmt:2; }; -struct b_format { /* BREAK and SYSCALL */ +struct b_format { /* BREAK and SYSCALL */ unsigned int opcode:6; unsigned int code:20; unsigned int func:6; @@ -270,71 +270,71 @@ struct b_format { /* BREAK and SYSCALL */ #elif defined(__MIPSEL__) struct j_format { /* Jump format */ - unsigned int target : 26; - unsigned int opcode : 6; + unsigned int target:26; + unsigned int opcode:6; }; struct i_format { /* Immediate format */ - signed int simmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + signed int simmediate:16; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct u_format { /* Unsigned immediate format */ - unsigned int uimmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int uimmediate:16; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct c_format { /* Cache (>= R6000) format */ - unsigned int simmediate : 16; - unsigned int cache : 2; - unsigned int c_op : 3; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int simmediate:16; + unsigned int cache:2; + unsigned int c_op:3; + unsigned int rs:5; + unsigned int opcode:6; }; struct r_format { /* Register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct p_format { /* Performance counter format (R10000) */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct f_format { /* FPU register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int fmt : 4; - unsigned int : 1; - unsigned int opcode : 6; + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int fmt:4; + unsigned int :1; + unsigned int opcode:6; }; struct ma_format { /* FPU multiply and add format (MIPS IV) */ - unsigned int fmt : 2; - unsigned int func : 4; - unsigned int fd : 5; - unsigned int fs : 5; - unsigned int ft : 5; - unsigned int fr : 5; - unsigned int opcode : 6; + unsigned int fmt:2; + unsigned int func:4; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fr:5; + unsigned int opcode:6; }; -struct b_format { /* BREAK and SYSCALL */ +struct b_format { /* BREAK and SYSCALL */ unsigned int func:6; unsigned int code:20; unsigned int opcode:6; diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7e4e6f8..1ad3e34 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1142,17 +1142,21 @@ do { \ /* * Macros to access the floating point coprocessor control registers */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) +#define read_32bit_cp1_register(source) \ +({ \ + int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set reorder \n" \ + " # gas fails to assemble cfc1 for some archs, \n" \ + " # like Octeon. \n" \ + " .set mips1 \n" \ + " cfc1 %0,"STR(source)" \n" \ + " .set pop \n" \ + : "=r" (__res)); \ + __res; \ +}) #define rddsp(mask) \ ({ \ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index cf7ac54..e3a5f3d 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -518,7 +518,7 @@ static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); if ((unsigned long)vaddr & 3) return SIGBUS; @@ -558,7 +558,7 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); reg = (opcode & RT) >> 16; if ((unsigned long)vaddr & 3) -- 1.7.9.5 From kirill.shutemov@linux.intel.com Mon Jan 14 16:15:49 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 16:15:51 +0100 (CET) Received: from mga01.intel.com ([192.55.52.88]:34023 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831947Ab3ANPPtvnVGJ (ORCPT ); Mon, 14 Jan 2013 16:15:49 +0100 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 14 Jan 2013 07:15:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,468,1355126400"; d="asc'?scan'208";a="276659674" Received: from blue.fi.intel.com ([10.237.72.156]) by fmsmga002.fm.intel.com with ESMTP; 14 Jan 2013 07:15:39 -0800 Received: by blue.fi.intel.com (Postfix, from userid 1000) id C0CB4E0073; Mon, 14 Jan 2013 17:16:41 +0200 (EET) Date: Mon, 14 Jan 2013 17:16:41 +0200 From: "Kirill A. Shutemov" To: Andrew Morton Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-mips@linux-mips.org, Aaro Koskinen Subject: Re: 3.8-rc1 build failure with MIPS/SPARSEMEM Message-ID: <20130114151641.GA17996@otc-wbsnb-06> References: <20121222122757.GB6847@blackmetal.musicnaut.iki.fi> <20121226003434.GA27760@otc-wbsnb-06> <20121227121607.GA7097@blackmetal.musicnaut.iki.fi> <20121230103850.GA5424@otc-wbsnb-06> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="TB36FDmn/VVEgNH/" Content-Disposition: inline In-Reply-To: <20121230103850.GA5424@otc-wbsnb-06> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35417 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kirill.shutemov@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2513 Lines: 67 --TB36FDmn/VVEgNH/ Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Dec 30, 2012 at 12:38:50PM +0200, Kirill A. Shutemov wrote: > On Thu, Dec 27, 2012 at 02:16:07PM +0200, Aaro Koskinen wrote: > > Hi, > >=20 > > On Wed, Dec 26, 2012 at 02:34:35AM +0200, Kirill A. Shutemov wrote: > > > On MIPS if SPARSEMEM is enabled we've got this: > > >=20 > > > In file included from /home/kas/git/public/linux/arch/mips/include/as= m/pgtable.h:552, > > > from include/linux/mm.h:44, > > > from arch/mips/kernel/asm-offsets.c:14: > > > include/asm-generic/pgtable.h: In function =E2=80=98my_zero_pfn=E2=80= =99: > > > include/asm-generic/pgtable.h:466: error: implicit declaration of fun= ction =E2=80=98page_to_section=E2=80=99 > > > In file included from arch/mips/kernel/asm-offsets.c:14: > > > include/linux/mm.h: At top level: > > > include/linux/mm.h:738: error: conflicting types for =E2=80=98page_to= _section=E2=80=99 > > > include/asm-generic/pgtable.h:466: note: previous implicit declaratio= n of =E2=80=98page_to_section=E2=80=99 was here > > >=20 > > > Due header files inter-dependencies, the only way I see to fix it is > > > convert my_zero_pfn() for __HAVE_COLOR_ZERO_PAGE to macros. > > >=20 > > > Signed-off-by: Kirill A. Shutemov > >=20 > > Thanks, this works. > >=20 > > Tested-by: Aaro Koskinen >=20 > Andrew, could you take the patch? ping? --=20 Kirill A. Shutemov --TB36FDmn/VVEgNH/ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBAgAGBQJQ9CFZAAoJEAd+omnVudOMbdUP/24tVWl2QDuay6OFsj6muPt+ fyeM0Rjl+vwOi3UaIz5Xhckf7mVJEE1P/xMkxL2GLf8anJL4fRxrYDE30phPOuOz YRQ4xGEDzjmfHNLQJgzgUdbcM03RwNazwteFYOHh67/Ag8CkPDUEqWgd/cmDjeKy Q/DFpxuqrVmgRQ0Mekei5vMGDd/k05piDgGzglsORTcAKxmFTH8R7XA8TtX7VzyN xI1+TA1hnGbS2lYJVNsoB1Q7FQUSHri06RtBzC8lbk5NDqrrNdilKqwZomuCPwuz 9Qbaiht0+LoVbipPylAspJpJ+wNMCLE7UpGsfwB326Y/io/1lW9D4UAWgYzIVcNw o48a9v7C8GA0K5VWQg6Ps2t8FsRPsDDIE0asTp6w3yLhrwlvgl46kD5wVlXQDww9 C0CKqV4UYLkyhmK6vHsoH9E9+pgsg420Xd9B7bPmoMOQVshtor9PyMnqNT500v3W feefsvorH+gDacvIzpHVd685dgi2EcGrNFv3St+qOlMUUJ7STBP8+WF7J8SpTY7/ 4OqTyavnLuAwYoQ7fri5S7pBITAPLCrcBe4oIKWFY9d5l6hsCokeMka8en1LBimA fGaI9i9dOim+aCKbMrCj4Lg18HIxJ45pAfoGnuvoRasslyFW8NhkIClQVI/gbmUq LFUita7qoobzjt4YCPG7 =M1Vh -----END PGP SIGNATURE----- --TB36FDmn/VVEgNH/-- From jchandra@broadcom.com Mon Jan 14 17:09:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:09:53 +0100 (CET) Received: from mms1.broadcom.com ([216.31.210.17]:4921 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831938Ab3ANQJsHnmzF (ORCPT ); Mon, 14 Jan 2013 17:09:48 +0100 Received: from [10.9.200.133] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:07:36 -0800 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Mon, 14 Jan 2013 08:09:21 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id C7ECE40FE7; Mon, 14 Jan 2013 08:09:30 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 03/10] MIPS: PCI: Byteswap not needed in little-endian mode Date: Mon, 14 Jan 2013 21:41:55 +0530 Message-ID: <1358179922-26663-4-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF2C21ZS6640570-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35418 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1033 Lines: 43 Wrap the xlp_enable_pci_bswap() function and its call with '#ifdef __BIG_ENDIAN'. On Netlogic XLP, the PCIe initialization code to setup to byteswap is needed only in big-endian mode. Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 140557a..fe435fc 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -191,6 +191,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) return 0; } +#ifdef __BIG_ENDIAN static int xlp_enable_pci_bswap(void) { uint64_t pciebase, sysbase; @@ -224,6 +225,7 @@ static int xlp_enable_pci_bswap(void) } return 0; } +#endif static int __init pcibios_init(void) { @@ -235,7 +237,9 @@ static int __init pcibios_init(void) ioport_resource.start = 0; ioport_resource.end = ~0; +#ifdef __BIG_ENDIAN xlp_enable_pci_bswap(); +#endif set_io_port_base(CKSEG1); nlm_pci_controller.io_map_base = CKSEG1; -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:10:02 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:10:14 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:4248 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831946Ab3ANQKC3cS-7 (ORCPT ); Mon, 14 Jan 2013 17:10:02 +0100 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:06:37 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Mon, 14 Jan 2013 08:09:33 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 827CA40FE8; Mon, 14 Jan 2013 08:09:39 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 09/10] MIPS: Netlogic: Fix for quad-XLP boot Date: Mon, 14 Jan 2013 21:42:01 +0530 Message-ID: <1358179922-26663-10-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF2873QS854723-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35419 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2618 Lines: 90 On multi-chip boards, the first core on slave SoCs may take much more time to wakeup. Add code to wait for the core to come up before proceeding with the rest of the boot up. Update xlp_wakeup_core to also skip the boot node and the boot CPU initialization which is already complete. Signed-off-by: Jayachandran C --- arch/mips/netlogic/xlp/wakeup.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index cb90106..abb3e08 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -51,7 +51,7 @@ #include #include -static int xlp_wakeup_core(uint64_t sysbase, int core) +static int xlp_wakeup_core(uint64_t sysbase, int node, int core) { uint32_t coremask, value; int count; @@ -82,36 +82,51 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) struct nlm_soc_info *nodep; uint64_t syspcibase; uint32_t syscoremask; - int core, n, cpu; + int core, n, cpu, count, val; for (n = 0; n < NLM_NR_NODES; n++) { syspcibase = nlm_get_sys_pcibase(n); if (nlm_read_reg(syspcibase, 0) == 0xffffffff) break; - /* read cores in reset from SYS and account for boot cpu */ - nlm_node_init(n); + /* read cores in reset from SYS */ + if (n != 0) + nlm_node_init(n); nodep = nlm_get_node(n); syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET); - if (n == 0) + /* The boot cpu */ + if (n == 0) { syscoremask |= 1; + nodep->coremask = 1; + } for (core = 0; core < NLM_CORES_PER_NODE; core++) { + /* we will be on node 0 core 0 */ + if (n == 0 && core == 0) + continue; + /* see if the core exists */ if ((syscoremask & (1 << core)) == 0) continue; - /* see if at least the first thread is enabled */ + /* see if at least the first hw thread is enabled */ cpu = (n * NLM_CORES_PER_NODE + core) * NLM_THREADS_PER_CORE; if (!cpumask_test_cpu(cpu, wakeup_mask)) continue; /* wake up the core */ - if (xlp_wakeup_core(nodep->sysbase, core)) - nodep->coremask |= 1u << core; - else - pr_err("Failed to enable core %d\n", core); + if (!xlp_wakeup_core(nodep->sysbase, n, core)) + continue; + + /* core is up */ + nodep->coremask |= 1u << core; + + /* spin until the first hw thread sets its ready */ + count = 0x20000000; + do { + val = *(volatile int *)&nlm_cpu_ready[cpu]; + } while (val == 0 && --count > 0); } } } -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:10:02 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:10:35 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:4258 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831947Ab3ANQKCadJ1N (ORCPT ); Mon, 14 Jan 2013 17:10:02 +0100 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:06:38 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Mon, 14 Jan 2013 08:09:34 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 38C4741012; Mon, 14 Jan 2013 08:09:40 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 10/10] MIPS: PCI: Multi-node PCI support for Netlogic XLP Date: Mon, 14 Jan 2013 21:42:02 +0530 Message-ID: <1358179922-26663-11-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF2843QS854727-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35420 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5120 Lines: 175 On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCI on all the nodes. Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlp.c | 106 +++++++++++++++++++++++++++++------------------ 1 file changed, 65 insertions(+), 41 deletions(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 5cd95a0..f6b1c70 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -46,6 +46,7 @@ #include #include +#include #include #include @@ -161,32 +162,38 @@ struct pci_controller nlm_pci_controller = { .io_offset = 0x00000000UL, }; -static int get_irq_vector(const struct pci_dev *dev) +static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) { - /* - * For XLP PCIe, there is an IRQ per Link, find out which - * link the device is on to assign interrupts - */ - if (dev->bus->self == NULL) - return 0; + struct pci_bus *bus, *p; - switch (dev->bus->self->devfn) { - case 0x8: - return PIC_PCIE_LINK_0_IRQ; - case 0x9: - return PIC_PCIE_LINK_1_IRQ; - case 0xa: - return PIC_PCIE_LINK_2_IRQ; - case 0xb: - return PIC_PCIE_LINK_3_IRQ; - } - WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); - return 0; + /* Find the bridge on bus 0 */ + bus = dev->bus; + for (p = bus->parent; p && p->number != 0; p = p->parent) + bus = p; + + return p ? bus->self : NULL; +} + +static inline int nlm_pci_link_to_irq(int link) +{ + return PIC_PCIE_LINK_0_IRQ + link; } int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - return get_irq_vector(dev); + struct pci_dev *lnkdev; + int lnkslot, lnkfunc, irq; + + /* + * For XLP PCIe, there is an IRQ per Link, find out which + * link the device is on to assign interrupts + */ + lnkdev = xlp_get_pcie_link(dev); + if (lnkdev == NULL) + return 0; + lnkfunc = PCI_FUNC(lnkdev->devfn); + lnkslot = PCI_SLOT(lnkdev->devfn); + return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc)); } /* Do platform specific device initialization at pci_enable_device() time */ @@ -196,43 +203,41 @@ int pcibios_plat_dev_init(struct pci_dev *dev) } #ifdef __BIG_ENDIAN -static int xlp_enable_pci_bswap(void) +static int xlp_enable_pci_bswap(int node, int link) { - uint64_t pciebase, sysbase; - int node, i; + uint64_t nbubase, lnkbase; u32 reg; - /* Chip-0 so node set to 0 */ - node = 0; - sysbase = nlm_get_bridge_regbase(node); + nbubase = nlm_get_bridge_regbase(node); + lnkbase = nlm_get_pcie_base(node, link); + /* * Enable byte swap in hardware. Program each link's PCIe SWAP regions * from the link's address ranges. */ - for (i = 0; i < 4; i++) { - pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i)); - if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) - continue; + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, - reg | 0xfff); + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); - } return 0; } #endif static int __init pcibios_init(void) { + struct nlm_soc_info *nodep; + uint64_t pciebase; + int link, n; + u32 reg; + /* Firmware assigns PCI resources */ pci_set_flags(PCI_PROBE_ONLY); pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); @@ -241,9 +246,28 @@ static int __init pcibios_init(void) ioport_resource.start = 0; ioport_resource.end = ~0; + for (n = 0; n < NLM_NR_NODES; n++) { + nodep = nlm_get_node(n); + if (!nodep->coremask) + continue; /* node does not exist */ + + for (link = 0; link < 4; link++) { + pciebase = nlm_get_pcie_base(n, link); + if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) + continue; #ifdef __BIG_ENDIAN - xlp_enable_pci_bswap(); + xlp_enable_pci_bswap(n, link); #endif + + /* put in intpin and irq - u-boot does not */ + reg = nlm_read_pci_reg(pciebase, 0xf); + reg &= ~0x1fu; + reg |= (1 << 8) | nlm_pci_link_to_irq(link); + nlm_write_pci_reg(pciebase, 0xf, reg); + pr_info("XLP PCIe: Link %d initialized\n", link); + } + } + set_io_port_base(CKSEG1); nlm_pci_controller.io_map_base = CKSEG1; -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:10:10 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:10:56 +0100 (CET) Received: from mms1.broadcom.com ([216.31.210.17]:4921 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831953Ab3ANQKKs4VYZ (ORCPT ); Mon, 14 Jan 2013 17:10:10 +0100 Received: from [10.9.200.133] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:07:33 -0800 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Mon, 14 Jan 2013 08:09:18 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 858E740FE4; Mon, 14 Jan 2013 08:09:27 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 01/10] MIPS: Netlogic: add XLS6xx to FMN config Date: Mon, 14 Jan 2013 21:41:53 +0530 Message-ID: <1358179922-26663-2-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF2CF1ZS6640503-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35421 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 783 Lines: 25 Add support for XLS6xx CPUs to the Fast Message Network (FMN) configuration. Signed-off-by: Jayachandran C --- arch/mips/netlogic/xlr/fmn-config.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/netlogic/xlr/fmn-config.c b/arch/mips/netlogic/xlr/fmn-config.c index bed2cff..e8071d6 100644 --- a/arch/mips/netlogic/xlr/fmn-config.c +++ b/arch/mips/netlogic/xlr/fmn-config.c @@ -216,6 +216,8 @@ void xlr_board_info_setup(void) case PRID_IMP_NETLOGIC_XLS404B: case PRID_IMP_NETLOGIC_XLS408B: case PRID_IMP_NETLOGIC_XLS416B: + case PRID_IMP_NETLOGIC_XLS608B: + case PRID_IMP_NETLOGIC_XLS616B: setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, FMN_STNID_GMAC0_TX3, 8, 8, 32); setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0, -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:10:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:11:20 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:2056 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831950Ab3ANQKSZ4GtZ (ORCPT ); Mon, 14 Jan 2013 17:10:18 +0100 Received: from [10.9.200.131] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:04:50 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Mon, 14 Jan 2013 08:09:34 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 93C0C40FE5; Mon, 14 Jan 2013 08:09:33 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 05/10] MIPS: Netlogic: Use PIC timer as a clocksource Date: Mon, 14 Jan 2013 21:41:57 +0530 Message-ID: <1358179922-26663-6-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF3283Q42009767-13-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35422 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8111 Lines: 255 The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC frequencey. One of these can be used as a clocksource to provide timestamps that is common across cores. This can be used in place of the count/compare clocksource which is per-CPU. On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits of the PIC counter. On XLP, the whole 64-bit can be used. Provide common macros and functions for PIC timer registers on XLR/XLS and XLP, and use them to register a PIC clocksource. Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlp-hal/pic.h | 12 +++++- arch/mips/include/asm/netlogic/xlr/pic.h | 48 ++++++++++++++++++++++-- arch/mips/netlogic/common/irq.c | 2 +- arch/mips/netlogic/common/time.c | 52 ++++++++++++++++++++++++++ arch/mips/netlogic/xlr/platform.c | 2 +- arch/mips/netlogic/xlr/setup.c | 2 +- 6 files changed, 110 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h index b2e53a5..ea6768c 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h @@ -261,6 +261,8 @@ #define PIC_LOCAL_SCHEDULING 1 #define PIC_GLOBAL_SCHEDULING 0 +#define PIC_CLK_HZ 133333333 + #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) @@ -315,6 +317,12 @@ nlm_pic_read_timer(uint64_t base, int timer) return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); } +static inline uint32_t +nlm_pic_read_timer32(uint64_t base, int timer) +{ + return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); +} + static inline void nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) { @@ -376,9 +384,9 @@ nlm_pic_ack(uint64_t base, int irt_num) } static inline void -nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) +nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) { - nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt); + nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt); } int nlm_irq_to_irt(int irq); diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h index 9a691b1..effa337 100644 --- a/arch/mips/include/asm/netlogic/xlr/pic.h +++ b/arch/mips/include/asm/netlogic/xlr/pic.h @@ -35,10 +35,11 @@ #ifndef _ASM_NLM_XLR_PIC_H #define _ASM_NLM_XLR_PIC_H -#define PIC_CLKS_PER_SEC 66666666ULL +#define PIC_CLK_HZ 66666666 /* PIC hardware interrupt numbers */ #define PIC_IRT_WD_INDEX 0 #define PIC_IRT_TIMER_0_INDEX 1 +#define PIC_IRT_TIMER_INDEX(i) ((i) + PIC_IRT_TIMER_0_INDEX) #define PIC_IRT_TIMER_1_INDEX 2 #define PIC_IRT_TIMER_2_INDEX 3 #define PIC_IRT_TIMER_3_INDEX 4 @@ -99,6 +100,7 @@ /* PIC Registers */ #define PIC_CTRL 0x00 +#define PIC_CTRL_STE 8 /* timer enable start bit */ #define PIC_IPI 0x04 #define PIC_INT_ACK 0x06 @@ -251,12 +253,52 @@ nlm_pic_ack(uint64_t base, int irt) } static inline void -nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) +nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) { nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); /* local scheduling, invalid, level by default */ nlm_write_reg(base, PIC_IRT_1(irt), - (1 << 30) | (1 << 6) | irq); + (en << 30) | (1 << 6) | irq); +} + +static inline uint64_t +nlm_pic_read_timer(uint64_t base, int timer) +{ + uint32_t up1, up2, low; + + up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); + low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); + up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); + + if (up1 != up2) /* wrapped, get the new low */ + low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); + return ((uint64_t)up2 << 32) | low; + +} + +static inline uint32_t +nlm_pic_read_timer32(uint64_t base, int timer) +{ + return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); +} + +static inline void +nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) +{ + uint32_t up, low; + uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL); + int en; + + en = (irq > 0); + up = value >> 32; + low = value & 0xFFFFFFFF; + nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low); + nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up); + nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0); + + /* enable the timer */ + pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); + nlm_write_reg(base, PIC_CTRL, pic_ctrl); } #endif #endif /* _ASM_NLM_XLR_PIC_H */ diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c index d42cd1a..642f1e4 100644 --- a/arch/mips/netlogic/common/irq.c +++ b/arch/mips/netlogic/common/irq.c @@ -217,7 +217,7 @@ static void nlm_init_node_irqs(int node) nlm_setup_pic_irq(node, i, i, irt); /* set interrupts to first cpu in node */ nlm_pic_init_irt(nodep->picbase, irt, i, - node * NLM_CPUS_PER_NODE); + node * NLM_CPUS_PER_NODE, 0); irqmask |= (1ull << i); } nodep->irqmask = irqmask; diff --git a/arch/mips/netlogic/common/time.c b/arch/mips/netlogic/common/time.c index bd3e498..20f89bc 100644 --- a/arch/mips/netlogic/common/time.c +++ b/arch/mips/netlogic/common/time.c @@ -35,16 +35,68 @@ #include #include +#include + #include #include +#include +#include + +#if defined(CONFIG_CPU_XLP) +#include +#include +#include +#elif defined(CONFIG_CPU_XLR) +#include +#include +#include +#else +#error "Unknown CPU" +#endif unsigned int __cpuinit get_c0_compare_int(void) { return IRQ_TIMER; } +static cycle_t nlm_get_pic_timer(struct clocksource *cs) +{ + uint64_t picbase = nlm_get_node(0)->picbase; + + return ~nlm_pic_read_timer(picbase, PIC_CLOCK_TIMER); +} + +static cycle_t nlm_get_pic_timer32(struct clocksource *cs) +{ + uint64_t picbase = nlm_get_node(0)->picbase; + + return ~nlm_pic_read_timer32(picbase, PIC_CLOCK_TIMER); +} + +static struct clocksource csrc_pic = { + .name = "PIC", + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void nlm_init_pic_timer(void) +{ + uint64_t picbase = nlm_get_node(0)->picbase; + + nlm_pic_set_timer(picbase, PIC_CLOCK_TIMER, ~0ULL, 0, 0); + if (current_cpu_data.cputype == CPU_XLR) { + csrc_pic.mask = CLOCKSOURCE_MASK(32); + csrc_pic.read = nlm_get_pic_timer32; + } else { + csrc_pic.mask = CLOCKSOURCE_MASK(64); + csrc_pic.read = nlm_get_pic_timer; + } + csrc_pic.rating = 1000; + clocksource_register_hz(&csrc_pic, PIC_CLK_HZ); +} + void __init plat_time_init(void) { + nlm_init_pic_timer(); mips_hpt_frequency = nlm_get_cpu_frequency(); pr_info("MIPS counter frequency [%ld]\n", (unsigned long)mips_hpt_frequency); diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c index 507230e..ce838f9 100644 --- a/arch/mips/netlogic/xlr/platform.c +++ b/arch/mips/netlogic/xlr/platform.c @@ -64,7 +64,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) .iotype = UPIO_MEM32, \ .flags = (UPF_SKIP_TEST | \ UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\ - .uartclk = PIC_CLKS_PER_SEC, \ + .uartclk = PIC_CLK_HZ, \ .type = PORT_16550A, \ .serial_in = nlm_xlr_uart_in, \ .serial_out = nlm_xlr_uart_out, \ diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index 4e7f49d..f72f92e 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -70,7 +70,7 @@ static void __init nlm_early_serial_setup(void) s.iotype = UPIO_MEM32; s.regshift = 2; s.irq = PIC_UART_0_IRQ; - s.uartclk = PIC_CLKS_PER_SEC; + s.uartclk = PIC_CLK_HZ; s.serial_in = nlm_xlr_uart_in; s.serial_out = nlm_xlr_uart_out; s.mapbase = uart_base; -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:10:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:11:38 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:2054 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831955Ab3ANQKSZ-rDk (ORCPT ); Mon, 14 Jan 2013 17:10:18 +0100 Received: from [10.9.200.131] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:04:50 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Mon, 14 Jan 2013 08:09:33 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 3301B40FE5; Mon, 14 Jan 2013 08:09:31 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 04/10] MIPS: Netlogic: Split XLP L1 i-cache among threads Date: Mon, 14 Jan 2013 21:41:56 +0530 Message-ID: <1358179922-26663-5-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF3283Q42009767-12-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35423 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1391 Lines: 46 Since we now use r4k cache code for Netlogic XLP, it is better to split L1 icache among the active threads, so that threads won't step on each other while flushing icache. The L1 dcache is already split among the threads in the core. Signed-off-by: Jayachandran C --- .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 2 ++ arch/mips/netlogic/common/smpboot.S | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h index 7b63a6b..6d2e58a 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h @@ -46,6 +46,8 @@ #define CPU_BLOCKID_FPU 9 #define CPU_BLOCKID_MAP 10 +#define ICU_DEFEATURE 0x100 + #define LSU_DEFEATURE 0x304 #define LSU_DEBUG_ADDR 0x305 #define LSU_DEBUG_DATA0 0x306 diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index a0b7487..d772a87 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -69,6 +69,12 @@ #endif mtcr t1, t0 + li t0, ICU_DEFEATURE + mfcr t1, t0 + ori t1, 0x1000 /* Enable Icache partitioning */ + mtcr t1, t0 + + #ifdef XLP_AX_WORKAROUND li t0, SCHED_DEFEATURE lui t1, 0x0100 /* Disable BRU accepting ALU ops */ -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:10:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:11:58 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:2063 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831956Ab3ANQKSZ-rDk (ORCPT ); Mon, 14 Jan 2013 17:10:18 +0100 Received: from [10.9.200.131] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:04:51 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Mon, 14 Jan 2013 08:09:37 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id B168340FE5; Mon, 14 Jan 2013 08:09:36 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 07/10] MIPS: Netlogic: No hazards needed for XLR/XLS Date: Mon, 14 Jan 2013 21:41:59 +0530 Message-ID: <1358179922-26663-8-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF3283Q42009767-16-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35424 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 858 Lines: 26 TLB and COP0 hazards are handled in hardware for Netlogic XLR/XLS SoCs. Update hazards.h to pick more optimal set of definitions when compiling for XLR/XLS. Signed-off-by: Jayachandran C --- arch/mips/include/asm/hazards.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index f0324e9..9c309ae 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -141,7 +141,7 @@ do { \ #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ - defined(CONFIG_CPU_R5500) + defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:10:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:12:17 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:2059 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831952Ab3ANQKS19jtC (ORCPT ); Mon, 14 Jan 2013 17:10:18 +0100 Received: from [10.9.200.131] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:04:51 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Mon, 14 Jan 2013 08:09:36 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 39DFC40FE5; Mon, 14 Jan 2013 08:09:35 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 06/10] MIPS: PCI: Prevent hang on XLP reg read Date: Mon, 14 Jan 2013 21:41:58 +0530 Message-ID: <1358179922-26663-7-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF3283Q42009767-15-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35425 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 866 Lines: 31 Reading PCI extended register at 0x255 on a bridge will hang if there is no device connected on the link. Make PCI read routine skip this register. Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlp.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index fe435fc..5cd95a0 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -64,8 +64,12 @@ static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, u32 data; u32 *cfgaddr; + where &= ~3; + if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) + return 0xffffffff; + cfgaddr = (u32 *)(pci_config_base + - pci_cfg_addr(bus->number, devfn, where & ~3)); + pci_cfg_addr(bus->number, devfn, where)); data = *cfgaddr; return data; } -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:12:38 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:12:40 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:4185 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831955Ab3ANQMiGwC-c (ORCPT ); Mon, 14 Jan 2013 17:12:38 +0100 Received: from [10.9.208.53] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:07:16 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by irvexchcas06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server id 14.1.355.2; Mon, 14 Jan 2013 08:09:30 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 3024640FE4; Mon, 14 Jan 2013 08:09:28 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 02/10] MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bit Date: Mon, 14 Jan 2013 21:41:54 +0530 Message-ID: <1358179922-26663-3-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF2BE3Q42012102-05-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35426 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5936 Lines: 230 Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr() and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations and update the interrupt handling code to use these functions. Also, use the EIMR register functions to mask interrupts in the irq code. The 64-bit interrupt request and mask registers (EIRR and EIMR) are accessed when the interrupts are off, and the common operations are to set or clear a bit in these registers. Using the 64-bit c0 access functions for these operations is not optimal in 32-bit, because it will disable/restore interrupts and split/join the 64-bit value during each register access. Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/mips-extns.h | 79 +++++++++++++++++++++++++++ arch/mips/netlogic/common/irq.c | 39 +++++-------- arch/mips/netlogic/common/smp.c | 8 ++- 3 files changed, 98 insertions(+), 28 deletions(-) diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h index 32ba6d9..cc42965 100644 --- a/arch/mips/include/asm/netlogic/mips-extns.h +++ b/arch/mips/include/asm/netlogic/mips-extns.h @@ -68,6 +68,85 @@ do { \ __write_64bit_c0_register($9, 7, (val)); \ } while (0) +/* + * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with + * standard functions will be very inefficient. This provides + * optimized functions for the normal operations on the registers. + * + * Call with interrupts disabled. + */ +static inline void ack_c0_eirr(int irq) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set mips64\n\t" + ".set noat\n\t" + "li $1, 1\n\t" + "dsllv $1, $1, %0\n\t" + "dmtc0 $1, $9, 6\n\t" + ".set pop" + : : "r" (irq)); +} + +static inline void set_c0_eimr(int irq) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set mips64\n\t" + ".set noat\n\t" + "li $1, 1\n\t" + "dsllv %0, $1, %0\n\t" + "dmfc0 $1, $9, 7\n\t" + "or $1, %0\n\t" + "dmtc0 $1, $9, 7\n\t" + ".set pop" + : "+r" (irq)); +} + +static inline void clear_c0_eimr(int irq) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set mips64\n\t" + ".set noat\n\t" + "li $1, 1\n\t" + "dsllv %0, $1, %0\n\t" + "dmfc0 $1, $9, 7\n\t" + "or $1, %0\n\t" + "xor $1, %0\n\t" + "dmtc0 $1, $9, 7\n\t" + ".set pop" + : "+r" (irq)); +} + +/* + * Read c0 eimr and c0 eirr, do AND of the two values, the result is + * the interrupts which are raised and are not masked. + */ +static inline uint64_t read_c0_eirr_and_eimr(void) +{ + uint64_t val; + +#ifdef CONFIG_64BIT + val = read_c0_eimr() & read_c0_eirr(); +#else + __asm__ __volatile__( + ".set push\n\t" + ".set mips64\n\t" + ".set noat\n\t" + "dmfc0 %M0, $9, 6\n\t" + "dmfc0 %L0, $9, 7\n\t" + "and %M0, %L0\n\t" + "dsll %L0, %M0, 32\n\t" + "dsra %M0, %M0, 32\n\t" + "dsra %L0, %L0, 32\n\t" + ".set pop" + : "=r" (val)); +#endif + + return val; +} + static inline int hard_smp_processor_id(void) { return __read_32bit_c0_register($15, 1) & 0x3ff; diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c index 00dcc7a..d42cd1a 100644 --- a/arch/mips/netlogic/common/irq.c +++ b/arch/mips/netlogic/common/irq.c @@ -105,21 +105,23 @@ static void xlp_pic_disable(struct irq_data *d) static void xlp_pic_mask_ack(struct irq_data *d) { struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); - uint64_t mask = 1ull << pd->picirq; - write_c0_eirr(mask); /* ack by writing EIRR */ + clear_c0_eimr(pd->picirq); + ack_c0_eirr(pd->picirq); } static void xlp_pic_unmask(struct irq_data *d) { struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); - if (!pd) - return; + BUG_ON(!pd); if (pd->extra_ack) pd->extra_ack(d); + /* re-enable the intr on this cpu */ + set_c0_eimr(pd->picirq); + /* Ack is a single write, no need to lock */ nlm_pic_ack(pd->node->picbase, pd->irt); } @@ -134,32 +136,17 @@ static struct irq_chip xlp_pic = { static void cpuintr_disable(struct irq_data *d) { - uint64_t eimr; - uint64_t mask = 1ull << d->irq; - - eimr = read_c0_eimr(); - write_c0_eimr(eimr & ~mask); + clear_c0_eimr(d->irq); } static void cpuintr_enable(struct irq_data *d) { - uint64_t eimr; - uint64_t mask = 1ull << d->irq; - - eimr = read_c0_eimr(); - write_c0_eimr(eimr | mask); + set_c0_eimr(d->irq); } static void cpuintr_ack(struct irq_data *d) { - uint64_t mask = 1ull << d->irq; - - write_c0_eirr(mask); -} - -static void cpuintr_nop(struct irq_data *d) -{ - WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq); + ack_c0_eirr(d->irq); } /* @@ -170,9 +157,9 @@ struct irq_chip nlm_cpu_intr = { .name = "XLP-CPU-INTR", .irq_enable = cpuintr_enable, .irq_disable = cpuintr_disable, - .irq_mask = cpuintr_nop, - .irq_ack = cpuintr_nop, - .irq_eoi = cpuintr_ack, + .irq_mask = cpuintr_disable, + .irq_ack = cpuintr_ack, + .irq_eoi = cpuintr_enable, }; static void __init nlm_init_percpu_irqs(void) @@ -265,7 +252,7 @@ asmlinkage void plat_irq_dispatch(void) int i, node; node = nlm_nodeid(); - eirr = read_c0_eirr() & read_c0_eimr(); + eirr = read_c0_eirr_and_eimr(); i = __ilog2_u64(eirr); if (i == -1) diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index a080d9e..2bb95dc 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -84,15 +84,19 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) /* IRQ_IPI_SMP_FUNCTION Handler */ void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) { - write_c0_eirr(1ull << irq); + clear_c0_eimr(irq); + ack_c0_eirr(irq); smp_call_function_interrupt(); + set_c0_eimr(irq); } /* IRQ_IPI_SMP_RESCHEDULE handler */ void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) { - write_c0_eirr(1ull << irq); + clear_c0_eimr(irq); + ack_c0_eirr(irq); scheduler_ipi(); + set_c0_eimr(irq); } /* -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:12:38 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:13:01 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:4121 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831953Ab3ANQMiRa4eY (ORCPT ); Mon, 14 Jan 2013 17:12:38 +0100 Received: from [10.9.208.53] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:07:16 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by irvexchcas06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server id 14.1.355.2; Mon, 14 Jan 2013 08:09:27 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2B0BF40FE3; Mon, 14 Jan 2013 08:09:25 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 00/10] Netlogic: Fixes and updates for 3.9 Date: Mon, 14 Jan 2013 21:41:52 +0530 Message-ID: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-WSS-ID: 7CEAF2BE3Q42012102-04-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35427 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2034 Lines: 45 Here are the updates and fixes to Netlogic XLR/XLS/XLP platform code for 3.9. The major changes in the patchset are: - Update PIC and irq code to optimize EIMR/EIRR register access in 32-bit kernel. - Add PIC timer 7 as a clocksource for both XLR and XLP. This is a better clocksource compared with Cop0 count, and the PIC timer count register is available to all cores. - Fix quad-XLP boards boot problem, and add support for PCIe devices on all the SoCs on quad-XLP boards. The rest are minor fixes for various issues. JC. Jayachandran C (10): MIPS: Netlogic: add XLS6xx to FMN config MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bit MIPS: PCI: Byteswap not needed in little-endian mode MIPS: Netlogic: Split XLP L1 i-cache among threads MIPS: Netlogic: Use PIC timer as a clocksource MIPS: PCI: Prevent hang on XLP reg read MIPS: Netlogic: No hazards needed for XLR/XLS MIPS: Netlogic: use preset loops per jiffy MIPS: Netlogic: Fix for quad-XLP boot MIPS: PCI: Multi-node PCI support for Netlogic XLP arch/mips/include/asm/hazards.h | 2 +- arch/mips/include/asm/netlogic/mips-extns.h | 79 +++++++++++++ .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 2 + arch/mips/include/asm/netlogic/xlp-hal/pic.h | 12 +- arch/mips/include/asm/netlogic/xlr/pic.h | 48 +++++++- arch/mips/netlogic/common/irq.c | 41 +++---- arch/mips/netlogic/common/smp.c | 8 +- arch/mips/netlogic/common/smpboot.S | 6 + arch/mips/netlogic/common/time.c | 56 ++++++++++ arch/mips/netlogic/xlp/wakeup.c | 35 ++++-- arch/mips/netlogic/xlr/fmn-config.c | 2 + arch/mips/netlogic/xlr/platform.c | 2 +- arch/mips/netlogic/xlr/setup.c | 2 +- arch/mips/pci/pci-xlp.c | 116 +++++++++++++------- 14 files changed, 322 insertions(+), 89 deletions(-) -- 1.7.9.5 From jchandra@broadcom.com Mon Jan 14 17:12:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:13:20 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:4472 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831952Ab3ANQMnlFnPm (ORCPT ); Mon, 14 Jan 2013 17:12:43 +0100 Received: from [10.9.208.53] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 08:07:16 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by irvexchcas06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server id 14.1.355.2; Mon, 14 Jan 2013 08:09:38 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 1B7E240FE5; Mon, 14 Jan 2013 08:09:37 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 08/10] MIPS: Netlogic: use preset loops per jiffy Date: Mon, 14 Jan 2013 21:42:00 +0530 Message-ID: <1358179922-26663-9-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEAF2BE3Q42012102-07-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35428 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1074 Lines: 31 Doing calibrate delay on a hardware thread will be inaccurate since it depends on the load on other threads in the core. It will also slow down the boot process when done for 128 hardware threads. Switch to a pre-computed loops per jiffy based on the core frequency. The value is computed based on the core frequency and roughly matches the value calculated by calibrate_delay(). Signed-off-by: Jayachandran C --- arch/mips/netlogic/common/time.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/netlogic/common/time.c b/arch/mips/netlogic/common/time.c index 20f89bc..5c56555 100644 --- a/arch/mips/netlogic/common/time.c +++ b/arch/mips/netlogic/common/time.c @@ -98,6 +98,10 @@ void __init plat_time_init(void) { nlm_init_pic_timer(); mips_hpt_frequency = nlm_get_cpu_frequency(); + if (current_cpu_type() == CPU_XLR) + preset_lpj = mips_hpt_frequency / (3 * HZ); + else + preset_lpj = mips_hpt_frequency / (2 * HZ); pr_info("MIPS counter frequency [%ld]\n", (unsigned long)mips_hpt_frequency); } -- 1.7.9.5 From sshtylyov@mvista.com Mon Jan 14 17:50:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 17:50:06 +0100 (CET) Received: from mail-lb0-f180.google.com ([209.85.217.180]:55916 "EHLO mail-lb0-f180.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831958Ab3ANQuFfYfXW (ORCPT ); Mon, 14 Jan 2013 17:50:05 +0100 Received: by mail-lb0-f180.google.com with SMTP id gj3so3112438lbb.11 for ; Mon, 14 Jan 2013 08:49:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=Vo0S6UhJzSGACyZsohm+5buZhF/rynbvYb68CUtlhmU=; b=b0jlCGm5n0EzCMrKNYFpZulOX8QKc+Hkjtit2Ijua4AiXjnvvaJ8SGXJvr+14jzEl+ NACvddCMYOQ6zmdr6+QMD2n5l4bfZbIR+8LcLt2h7GEvrZrfa8auXizuWD/ARVlK1E63 caPV2hSDhcGmZOwiER2Eo7wmmwdL7GyM5q2HDg8HX4hjt/aYiM9/5d6etkx4piH9ji2n lytXSpL8RGO/Ad4a/PiKNYVtjwKFcRGqABDkg2rlRcVs853Wgvlm2STa06cz1SdJ8MHf MN7zoURqlMa1jqEODP8hvO/Dl6p1NXNGHauVs7o1AUMBpcEK0ldZg1yxcYAUcGUy1p3c +/NQ== X-Received: by 10.112.11.33 with SMTP id n1mr36050558lbb.18.1358182199651; Mon, 14 Jan 2013 08:49:59 -0800 (PST) Received: from wasted.dev.rtsoft.ru (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id v7sm5682909lbj.13.2013.01.14.08.49.57 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 14 Jan 2013 08:49:58 -0800 (PST) Message-ID: <50F444DC.1010307@mvista.com> Date: Mon, 14 Jan 2013 20:48:12 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130107 Thunderbird/17.0.2 MIME-Version: 1.0 To: Jayachandran C CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 03/10] MIPS: PCI: Byteswap not needed in little-endian mode References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> <1358179922-26663-4-git-send-email-jchandra@broadcom.com> In-Reply-To: <1358179922-26663-4-git-send-email-jchandra@broadcom.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQnTq5n/MS1uSt8yTgMMunrCZgnunyAQfbmHhIw0x9C94+NEAmijjixXQXlb6Hcpxe/vInRx X-archive-position: 35429 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1205 Lines: 46 Hello. On 01/14/2013 07:11 PM, Jayachandran C wrote: > Wrap the xlp_enable_pci_bswap() function and its call with > '#ifdef __BIG_ENDIAN'. On Netlogic XLP, the PCIe initialization code > to setup to byteswap is needed only in big-endian mode. > Signed-off-by: Jayachandran C > --- > arch/mips/pci/pci-xlp.c | 4 ++++ > 1 file changed, 4 insertions(+) > diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c > index 140557a..fe435fc 100644 > --- a/arch/mips/pci/pci-xlp.c > +++ b/arch/mips/pci/pci-xlp.c > @@ -191,6 +191,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) > return 0; > } > > +#ifdef __BIG_ENDIAN > static int xlp_enable_pci_bswap(void) > { > uint64_t pciebase, sysbase; > @@ -224,6 +225,7 @@ static int xlp_enable_pci_bswap(void) > } > return 0; > } > +#endif > > static int __init pcibios_init(void) > { > @@ -235,7 +237,9 @@ static int __init pcibios_init(void) > ioport_resource.start = 0; > ioport_resource.end = ~0; > > +#ifdef __BIG_ENDIAN > xlp_enable_pci_bswap(); > +#endif Define empty inline function for the non-BE case instead. That's what Documentation/SubmittingPatches tells us to do. WBR, Sergei From dinggnu@gmail.com Mon Jan 14 18:23:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 18:23:45 +0100 (CET) Received: from mail-qc0-f178.google.com ([209.85.216.178]:46119 "EHLO mail-qc0-f178.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831940Ab3ANRXofLzOM (ORCPT ); Mon, 14 Jan 2013 18:23:44 +0100 Received: by mail-qc0-f178.google.com with SMTP id j34so2619766qco.23 for ; Mon, 14 Jan 2013 09:23:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=MO5qI+NeMafd+DAeDXrxddwLJhGZWaqUpn0xDWRa4SI=; b=ICaF5h+YoPXsYXlTZFzjQ4SDGZUbi+NBxyqxs/D7hIBJ+PLHkkGmXOWg20nE8f2wdq 7Ng9DQiwl7AobeYHXXre+ZYf8VN5KymfnA/wtvwXmdSQWC47nSc5F0d7tZ8ArzL648Pn pkyceTuYdnOTEKsG3gp+BOhYKz6TYmgPjOJsncYaKwgCYRMDy4tfJm5yod/Es2CtOUbG y+FUAsqa+9vPxWdtQ4OFyziJD1koEtXva2tXd3QUrHlfMsu9Tc87EdRmpMuzqwwCTp7Z 5hHQM17cO0JokS+JI4vwqTFMoUHEjEqIaL+Xqbi2BTdDAY+neTBGzEWJnxCngti7JCGG oR5g== X-Received: by 10.49.105.73 with SMTP id gk9mr86160436qeb.40.1358184218189; Mon, 14 Jan 2013 09:23:38 -0800 (PST) Received: from localhost.localdomain (ec2-54-243-39-165.compute-1.amazonaws.com. [54.243.39.165]) by mx.google.com with ESMTPS id x9sm9246556qen.1.2013.01.14.09.23.37 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 14 Jan 2013 09:23:37 -0800 (PST) From: Cong Ding To: Ralf Baechle , David Howells , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Cong Ding Subject: [PATCH] mips: kernel/vpe.c: fix wrong KERN_WARNING message Date: Mon, 14 Jan 2013 17:23:29 +0000 Message-Id: <1358184212-30381-1-git-send-email-dinggnu@gmail.com> X-Mailer: git-send-email 1.7.4.5 X-archive-position: 35430 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dinggnu@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 655 Lines: 24 in the printk, the variable t euqals to NULL, so there is no t->index, we use v->tc->index instead. Signed-off-by: Cong Ding --- arch/mips/kernel/vpe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index eec690a..3e20c33 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -705,7 +705,7 @@ static int vpe_run(struct vpe * v) printk(KERN_WARNING "VPE loader: TC %d is already in use.\n", - t->index); + v->tc->index); return -ENOEXEC; } } else { -- 1.7.9.5 From alcooperx@gmail.com Mon Jan 14 22:10:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 22:10:56 +0100 (CET) Received: from mail-qa0-f51.google.com ([209.85.216.51]:50034 "EHLO mail-qa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831949Ab3ANVKzJTSC3 (ORCPT ); Mon, 14 Jan 2013 22:10:55 +0100 Received: by mail-qa0-f51.google.com with SMTP id i20so1830734qad.3 for ; Mon, 14 Jan 2013 13:10:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=s2IGupGF8+TAZK37IxyuPUmBSUASbr4iMV1j0AWGKDQ=; b=tPQV3aeh99hTsQo+Ecs5R7ay5ZNCND8Sfgv+h1muv1dHzQunobVUf0zr+yWSqionG+ vikTyKc9sIQE044sKgpEHMtbLCuxxM5cu1g1jmMbhF+pGKlwQdWbEgP4KmvfGto+c+gB fqP2tjor1iXhQczwsyNI1/oFU+GwL8uGkItuV3bFyuLp0MKWOXix2KVGeSFPMrHURoeH 4kMVScDNc+eB13OPzC/WjDQieYAGbRLeq2Yor/H2f5j2B/95Jm5r3mx8PjwOLxeqghc9 5RzPqKwkrtV7HeK1w/IV+aDVwLNcJ6C36YLQnaz9bAQekptAMTG92xgww/5GKVX4ZxvZ o/yg== MIME-Version: 1.0 Received: by 10.224.216.9 with SMTP id hg9mr16533454qab.44.1358197848888; Mon, 14 Jan 2013 13:10:48 -0800 (PST) Received: by 10.49.117.161 with HTTP; Mon, 14 Jan 2013 13:10:48 -0800 (PST) In-Reply-To: <50F0454D.5060109@gmail.com> References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> Date: Mon, 14 Jan 2013 16:10:48 -0500 Message-ID: Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing From: Alan Cooper To: David Daney Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35431 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3792 Lines: 80 I already tried using "adddiu sp, sp, 8" and it caused the kernel to randomly crash. After many hours of debugging the reason occurred to me while in bed in the middle of the night. The problem is that if we get an interrupt between the add 8 and the add -8 instructions, we trash the existing stack. The problem with the 2 nop approach is that there are a series of subroutines used to write each nop and these nested subroutines are traceable. This means on the second call to these subroutines they execute with only one nop and crash. I could write some new code that wrote the 2 nops at once, but (now that I understand "stop_machine") with the branch likely solution we should be able to stop using "stop_machine" when we write nops to the 20-30 thousand Linux functions. It looks like other platforms have stopped using stop_machine. Al On Fri, Jan 11, 2013 at 12:01 PM, David Daney wrote: > On 01/11/2013 06:33 AM, Al Cooper wrote: >> >> Function tracing is currently broken for all 32 bit MIPS platforms. >> When tracing is enabled, the kernel immediately hangs on boot. >> This is a result of commit b732d439cb43336cd6d7e804ecb2c81193ef63b0 >> that changes the kernel/trace/Kconfig file so that is no longer >> forces FRAME_POINTER when FUNCTION_TRACING is enabled. >> >> MIPS frame pointers are generally considered to be useless because >> they cannot be used to unwind the stack. Unfortunately the MIPS >> function tracing code has bugs that are masked by the use of frame >> pointers. This commit fixes the bugs so that MIPS frame pointers do >> not need to be enabled. >> >> The bugs are a result of the odd calling sequence used to call the trace >> routine. This calling sequence is inserted into every tracable function >> when the tracing CONFIG option is enabled. This sequence is generated >> for 32bit MIPS platforms by the compiler via the "-pg" flag. >> Part of the sequence is "addiu sp,sp,-8" in the delay slot after every >> call to the trace routine "_mcount" (some legacy thing where 2 arguments >> used to be pushed on the stack). The _mcount routine is expected to >> adjust the sp by +8 before returning. >> >> One of the bugs is that when tracing is disabled for a function, the >> "jalr _mcount" instruction is replaced with a nop, but the >> "addiu sp,sp,-8" is still executed and the stack pointer is left >> trashed. When frame pointers are enabled the problem is masked >> because any access to the stack is done through the frame >> pointer and the stack pointer is restored from the frame pointer when >> the function returns. This patch uses a branch likely instruction >> "bltzl zero, f1" instead of "nop" to disable the call because this >> instruction will not execute the "addiu sp,sp,-8" instruction in >> the delay slot. The other possible solution would be to nop out both >> the jalr and the "addiu sp,sp,-8", but this would need to be interrupt >> and SMP safe and would be much more intrusive. > > > I thought all CPUs were in stop_machine() when the modifications were done, > so that there is no issue with multi-word instruction patching. > > Am I wrong about this? > > So really I think you can do two NOP just as easily. > > The only reason I bring this up is that I am not sure all 32-bit CPUs > implement the 'Likely' branch variants. Also there may be an affect on the > branch predictor. > > A third possibility would be to replace the JALR with 'ADDIU SP,SP,8' That > way the following adjustment would be canceled out. This would work well on > single-issue CPUs, but the instructions may not be able to dual-issue on a > multi issue machine due to data dependencies. > > David Daney > > >> >> A few other bugs were fixed where the _mcount routine itself did not >> always fix the sp on return. >> > From dinggnu@gmail.com Mon Jan 14 22:47:22 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 22:47:23 +0100 (CET) Received: from mail-bk0-f50.google.com ([209.85.214.50]:62929 "EHLO mail-bk0-f50.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816553Ab3ANVrWmGnQn (ORCPT ); Mon, 14 Jan 2013 22:47:22 +0100 Received: by mail-bk0-f50.google.com with SMTP id jf3so2248632bkc.9 for ; Mon, 14 Jan 2013 13:47:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=EJMR/91ORBZazX8OjfrrvuqX3NT52WjsgmoDCdzCH4c=; b=Nt2Z8vNj8j6mPU4cvK12w+/l1pNH5h00aKqVqWDxTcjoFZSIwTREYjgKahS2zOKD1Y RIZAfy6c/e/vJR6VimqujbMdgqbvrmE2uiGaSOliPeUWN0CndQtk1529YdBeyjf4nwd1 G+AHVow7mxsqQHE3oYbs+yVNyJ9uDUWjyBSHp8R++1MZnS8sfd+XmgGC9wZJ5kbtSj18 G6TmwaDqRkDBGCsu+m6fnCCMJhW+eXKqLmJgYBdKnIr/wDbrystQtB03eLs+X76yqKJA K8t1nkKCBpbNWskY90x5CQU4ABmF3FgigI3G8nnqvTQ/TgzjGM0jGtKkSsvE3l9lXJnz UaTQ== X-Received: by 10.205.125.137 with SMTP id gs9mr39392534bkc.22.1358200037211; Mon, 14 Jan 2013 13:47:17 -0800 (PST) Received: from localhost.localdomain (p5B2F5DF4.dip.t-dialin.net. [91.47.93.244]) by mx.google.com with ESMTPS id c10sm11225050bkw.1.2013.01.14.13.47.14 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 14 Jan 2013 13:47:16 -0800 (PST) From: Cong Ding To: Ralf Baechle , Jim Quinlan , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Cong Ding Subject: [PATCH] mpis: cavium-octeon/executive/cvmx-l2c.c: fix uninitialized variable Date: Mon, 14 Jan 2013 22:47:03 +0100 Message-Id: <1358200025-15994-1-git-send-email-dinggnu@gmail.com> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35432 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dinggnu@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 754 Lines: 23 the variable dummy is used without initialization. Signed-off-by: Cong Ding --- arch/mips/cavium-octeon/executive/cvmx-l2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c index 9f883bf..d7e07af 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c @@ -286,7 +286,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter) static void fault_in(uint64_t addr, int len) { volatile char *ptr; - volatile char dummy; + volatile char dummy = 0; /* * Adjust addr and length so we get all cache lines even for * small ranges spanning two cache lines. -- 1.7.9.5 From ddaney.cavm@gmail.com Mon Jan 14 23:03:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 23:03:49 +0100 (CET) Received: from mail-da0-f54.google.com ([209.85.210.54]:38292 "EHLO mail-da0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816553Ab3ANWDsh4ltB (ORCPT ); Mon, 14 Jan 2013 23:03:48 +0100 Received: by mail-da0-f54.google.com with SMTP id n2so1998542dad.13 for ; Mon, 14 Jan 2013 14:03:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=a0TlSNYfbB1r95RlGIlRUMYS4zVt3LagTgk+bXSBRpg=; b=yz7MMBJ/BejBph7urYy6qaJcicEjehQZHbQDeBL233vRHXXlURJ/e9xmceCtqPZJdv 7I6ngQnfQQoLV42HMvWGN2DBUmnhHA6vBy7FK2yGFpA++ZfYmdGgwGUYeET14f4NVuyM Qtk1Yu16tXzgqqw+gFDZGwEtivSQcMqPe1NDk6L0ZUHg62A/2dzob/ahm46lpCV/0ySe ngOisDS+VoWgZx6jLRJdXFHhCBbxEdeoWB/qYAQfARBB4MZEFOPPvRzUk0PTUQtmhY5r pyrepqIK92O0GEFdGPzI1nVTV9Pjp/tq7QteBwuvE4spP44MrlEN57+rbYcYshUakKe3 sSpg== X-Received: by 10.68.238.8 with SMTP id vg8mr259956102pbc.26.1358201021634; Mon, 14 Jan 2013 14:03:41 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id im5sm7786845pbc.55.2013.01.14.14.03.40 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 14 Jan 2013 14:03:40 -0800 (PST) Message-ID: <50F480BB.6070105@gmail.com> Date: Mon, 14 Jan 2013 14:03:39 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Kirill A. Shutemov" , Andrew Morton CC: linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-mips@linux-mips.org, Aaro Koskinen Subject: Re: 3.8-rc1 build failure with MIPS/SPARSEMEM References: <20121222122757.GB6847@blackmetal.musicnaut.iki.fi> <20121226003434.GA27760@otc-wbsnb-06> <20121227121607.GA7097@blackmetal.musicnaut.iki.fi> <20121230103850.GA5424@otc-wbsnb-06> <20130114151641.GA17996@otc-wbsnb-06> In-Reply-To: <20130114151641.GA17996@otc-wbsnb-06> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35433 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1455 Lines: 37 On 01/14/2013 07:16 AM, Kirill A. Shutemov wrote: > On Sun, Dec 30, 2012 at 12:38:50PM +0200, Kirill A. Shutemov wrote: >> On Thu, Dec 27, 2012 at 02:16:07PM +0200, Aaro Koskinen wrote: >>> Hi, >>> >>> On Wed, Dec 26, 2012 at 02:34:35AM +0200, Kirill A. Shutemov wrote: >>>> On MIPS if SPARSEMEM is enabled we've got this: >>>> >>>> In file included from /home/kas/git/public/linux/arch/mips/include/asm/pgtable.h:552, >>>> from include/linux/mm.h:44, >>>> from arch/mips/kernel/asm-offsets.c:14: >>>> include/asm-generic/pgtable.h: In function ‘my_zero_pfn’: >>>> include/asm-generic/pgtable.h:466: error: implicit declaration of function ‘page_to_section’ >>>> In file included from arch/mips/kernel/asm-offsets.c:14: >>>> include/linux/mm.h: At top level: >>>> include/linux/mm.h:738: error: conflicting types for ‘page_to_section’ >>>> include/asm-generic/pgtable.h:466: note: previous implicit declaration of ‘page_to_section’ was here >>>> >>>> Due header files inter-dependencies, the only way I see to fix it is >>>> convert my_zero_pfn() for __HAVE_COLOR_ZERO_PAGE to macros. >>>> >>>> Signed-off-by: Kirill A. Shutemov >>> >>> Thanks, this works. >>> >>> Tested-by: Aaro Koskinen >> >> Andrew, could you take the patch? I found the same problem and arrived at an equivalent solution. Acked-by: David Daney > > ping? > From ddaney.cavm@gmail.com Mon Jan 14 23:12:45 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Jan 2013 23:12:48 +0100 (CET) Received: from mail-pa0-f47.google.com ([209.85.220.47]:55383 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816553Ab3ANWMp7KLta (ORCPT ); Mon, 14 Jan 2013 23:12:45 +0100 Received: by mail-pa0-f47.google.com with SMTP id fa10so2472592pad.20 for ; Mon, 14 Jan 2013 14:12:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=cci795w+LrnfnvjjrxAaV+XhYQpnwB0+NX4FIpaLcX0=; b=r5lHZGKXYwM2LmuSbLEwtRLLpeQuwhHoUeRBcdZpm3Q3Wt0g1ZDY5S72SekRsyJDu9 EYIHijGBoZ7F1bdGNU1B9oVJx51xwhqGIc7DV0ZCQaQb47yKOi+U+4XgAmDWCl34rsgF 39j5F9AT9Ycal5JZevk+DcqJxuR4aZ1WV+jCnHdo6yjzFXGZEfGFqfh1/0Pa+ex4CZS+ /h2yUm2b7chGJ+ochvQpgZ4SVcYr1etVaLY7qIbItnfXXI+/49+wvOOhaMT1x+1DA6Ag 5YhdwrO13bSp87CKj0hj7xWOVgD5U/Yj0MvV1r3Rb8j34IxENk4xAjZ+haS5jOOoCtjW +xUg== X-Received: by 10.66.88.37 with SMTP id bd5mr235900323pab.75.1358201559395; Mon, 14 Jan 2013 14:12:39 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id nm2sm8873081pbc.43.2013.01.14.14.12.33 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 14 Jan 2013 14:12:38 -0800 (PST) Message-ID: <50F482D1.4090301@gmail.com> Date: Mon, 14 Jan 2013 14:12:33 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Alan Cooper CC: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35434 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4269 Lines: 98 On 01/14/2013 01:10 PM, Alan Cooper wrote: > I already tried using "adddiu sp, sp, 8" and it caused the kernel to > randomly crash. After many hours of debugging the reason occurred to > me while in bed in the middle of the night. The problem is that if we > get an interrupt between the add 8 and the add -8 instructions, we > trash the existing stack. > > The problem with the 2 nop approach is that there are a series of > subroutines used to write each nop and these nested subroutines are > traceable. This seems like a bug. The low-level code used to do code patching probably should be CFLAGS_REMOVE_file.o = -pg > This means on the second call to these subroutines they > execute with only one nop and crash. I could write some new code > that wrote the 2 nops at once, but (now that I understand > "stop_machine") with the branch likely solution we should be able to > stop using "stop_machine" when we write nops to the 20-30 thousand > Linux functions. It looks like other platforms have stopped using > stop_machine. I don't particularly object to the 'branch likely solution', but I think the failures of the other approaches indicates underlying bugs in the tracing code. Those bugs should probably be fixed. David Daney > > Al > > On Fri, Jan 11, 2013 at 12:01 PM, David Daney wrote: >> On 01/11/2013 06:33 AM, Al Cooper wrote: >>> >>> Function tracing is currently broken for all 32 bit MIPS platforms. >>> When tracing is enabled, the kernel immediately hangs on boot. >>> This is a result of commit b732d439cb43336cd6d7e804ecb2c81193ef63b0 >>> that changes the kernel/trace/Kconfig file so that is no longer >>> forces FRAME_POINTER when FUNCTION_TRACING is enabled. >>> >>> MIPS frame pointers are generally considered to be useless because >>> they cannot be used to unwind the stack. Unfortunately the MIPS >>> function tracing code has bugs that are masked by the use of frame >>> pointers. This commit fixes the bugs so that MIPS frame pointers do >>> not need to be enabled. >>> >>> The bugs are a result of the odd calling sequence used to call the trace >>> routine. This calling sequence is inserted into every tracable function >>> when the tracing CONFIG option is enabled. This sequence is generated >>> for 32bit MIPS platforms by the compiler via the "-pg" flag. >>> Part of the sequence is "addiu sp,sp,-8" in the delay slot after every >>> call to the trace routine "_mcount" (some legacy thing where 2 arguments >>> used to be pushed on the stack). The _mcount routine is expected to >>> adjust the sp by +8 before returning. >>> >>> One of the bugs is that when tracing is disabled for a function, the >>> "jalr _mcount" instruction is replaced with a nop, but the >>> "addiu sp,sp,-8" is still executed and the stack pointer is left >>> trashed. When frame pointers are enabled the problem is masked >>> because any access to the stack is done through the frame >>> pointer and the stack pointer is restored from the frame pointer when >>> the function returns. This patch uses a branch likely instruction >>> "bltzl zero, f1" instead of "nop" to disable the call because this >>> instruction will not execute the "addiu sp,sp,-8" instruction in >>> the delay slot. The other possible solution would be to nop out both >>> the jalr and the "addiu sp,sp,-8", but this would need to be interrupt >>> and SMP safe and would be much more intrusive. >> >> >> I thought all CPUs were in stop_machine() when the modifications were done, >> so that there is no issue with multi-word instruction patching. >> >> Am I wrong about this? >> >> So really I think you can do two NOP just as easily. >> >> The only reason I bring this up is that I am not sure all 32-bit CPUs >> implement the 'Likely' branch variants. Also there may be an affect on the >> branch predictor. >> >> A third possibility would be to replace the JALR with 'ADDIU SP,SP,8' That >> way the following adjustment would be canceled out. This would work well on >> single-issue CPUs, but the instructions may not be able to dual-issue on a >> multi issue machine due to data dependencies. >> >> David Daney >> >> >>> >>> A few other bugs were fixed where the _mcount routine itself did not >>> always fix the sp on return. >>> >> > > From alcooperx@gmail.com Tue Jan 15 01:14:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 01:14:07 +0100 (CET) Received: from mail-qc0-f177.google.com ([209.85.216.177]:40054 "EHLO mail-qc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816553Ab3AOAOGHMm8r (ORCPT ); Tue, 15 Jan 2013 01:14:06 +0100 Received: by mail-qc0-f177.google.com with SMTP id u28so2858859qcs.8 for ; Mon, 14 Jan 2013 16:14:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=vFFcDAxHLW6nkEhPatD8Gm2WwaE598544FKJEzMHx6w=; b=KX08VgyTORdKm14LWVf8CT5fgHojpD6oF2OaRsLizc8thzQueTc73hAl1tgEUJigG0 SbiACzqp6W+SgpgDFd7cZqH7edPZHCTgnTJFtVExlB0vSulbrsPqsGT0QZALCw14uDDK qFDsdJtdBRTMjl8iY9zUGeEE7PoDsp2hPCa3fUZ/4MkjHCqop8kdHXPif5Fndno4PFPL B34SnB/YKSDnHqD1O3EjT4ZmzL2KN3OcBlHKQCc2u+sztDBjNVBhubM1JsXQaiAOj/aB 4459vkHj7j9QOl9EXzLWnAULnS1gAgDpH3vRV+Y2IzdGrtDTbGsjyKwcbVMHh75pzxZi 9UKA== MIME-Version: 1.0 Received: by 10.49.118.38 with SMTP id kj6mr86749940qeb.53.1358208840066; Mon, 14 Jan 2013 16:14:00 -0800 (PST) Received: by 10.49.117.161 with HTTP; Mon, 14 Jan 2013 16:13:59 -0800 (PST) In-Reply-To: <50F482D1.4090301@gmail.com> References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> <50F482D1.4090301@gmail.com> Date: Mon, 14 Jan 2013 19:13:59 -0500 Message-ID: Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing From: Alan Cooper To: David Daney Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35435 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5150 Lines: 127 On Mon, Jan 14, 2013 at 5:12 PM, David Daney wrote: > On 01/14/2013 01:10 PM, Alan Cooper wrote: >> >> I already tried using "adddiu sp, sp, 8" and it caused the kernel to >> randomly crash. After many hours of debugging the reason occurred to >> me while in bed in the middle of the night. The problem is that if we >> get an interrupt between the add 8 and the add -8 instructions, we >> trash the existing stack. >> >> The problem with the 2 nop approach is that there are a series of >> subroutines used to write each nop and these nested subroutines are >> traceable. > > > This seems like a bug. The low-level code used to do code patching probably > should be CFLAGS_REMOVE_file.o = -pg While tracing mcount cannot be done because it's recursive, allowing tracing of the code to enable/disable the call to mcount can be done and seems useful. Also, fixing the 2 nop solution this way will still not allow us to stop using stop_machine() which is hugely disruptive to a running system. Remember that when tracing is enabled and disabled we end up modifying 20 to 30 thousand functions. Moving this functionality out of stop_machine() seems like a big benefit. > > > >> This means on the second call to these subroutines they >> execute with only one nop and crash. I could write some new code >> that wrote the 2 nops at once, but (now that I understand >> "stop_machine") with the branch likely solution we should be able to >> stop using "stop_machine" when we write nops to the 20-30 thousand >> Linux functions. It looks like other platforms have stopped using >> stop_machine. > > > I don't particularly object to the 'branch likely solution', but I think the > failures of the other approaches indicates underlying bugs in the tracing > code. Those bugs should probably be fixed. If a solution can be found that modifies a single 32bit instruction to enable/disable tracing, I don't see any bugs in the underlying code. Plus we can avoid using stop_machine(). > > David Daney > > > >> >> Al >> >> On Fri, Jan 11, 2013 at 12:01 PM, David Daney >> wrote: >>> >>> On 01/11/2013 06:33 AM, Al Cooper wrote: >>>> >>>> >>>> Function tracing is currently broken for all 32 bit MIPS platforms. >>>> When tracing is enabled, the kernel immediately hangs on boot. >>>> This is a result of commit b732d439cb43336cd6d7e804ecb2c81193ef63b0 >>>> that changes the kernel/trace/Kconfig file so that is no longer >>>> forces FRAME_POINTER when FUNCTION_TRACING is enabled. >>>> >>>> MIPS frame pointers are generally considered to be useless because >>>> they cannot be used to unwind the stack. Unfortunately the MIPS >>>> function tracing code has bugs that are masked by the use of frame >>>> pointers. This commit fixes the bugs so that MIPS frame pointers do >>>> not need to be enabled. >>>> >>>> The bugs are a result of the odd calling sequence used to call the trace >>>> routine. This calling sequence is inserted into every tracable function >>>> when the tracing CONFIG option is enabled. This sequence is generated >>>> for 32bit MIPS platforms by the compiler via the "-pg" flag. >>>> Part of the sequence is "addiu sp,sp,-8" in the delay slot after every >>>> call to the trace routine "_mcount" (some legacy thing where 2 arguments >>>> used to be pushed on the stack). The _mcount routine is expected to >>>> adjust the sp by +8 before returning. >>>> >>>> One of the bugs is that when tracing is disabled for a function, the >>>> "jalr _mcount" instruction is replaced with a nop, but the >>>> "addiu sp,sp,-8" is still executed and the stack pointer is left >>>> trashed. When frame pointers are enabled the problem is masked >>>> because any access to the stack is done through the frame >>>> pointer and the stack pointer is restored from the frame pointer when >>>> the function returns. This patch uses a branch likely instruction >>>> "bltzl zero, f1" instead of "nop" to disable the call because this >>>> instruction will not execute the "addiu sp,sp,-8" instruction in >>>> the delay slot. The other possible solution would be to nop out both >>>> the jalr and the "addiu sp,sp,-8", but this would need to be interrupt >>>> and SMP safe and would be much more intrusive. >>> >>> >>> >>> I thought all CPUs were in stop_machine() when the modifications were >>> done, >>> so that there is no issue with multi-word instruction patching. >>> >>> Am I wrong about this? >>> >>> So really I think you can do two NOP just as easily. >>> >>> The only reason I bring this up is that I am not sure all 32-bit CPUs >>> implement the 'Likely' branch variants. Also there may be an affect on >>> the >>> branch predictor. >>> >>> A third possibility would be to replace the JALR with 'ADDIU SP,SP,8' >>> That >>> way the following adjustment would be canceled out. This would work well >>> on >>> single-issue CPUs, but the instructions may not be able to dual-issue on >>> a >>> multi issue machine due to data dependencies. >>> >>> David Daney >>> >>> >>>> >>>> A few other bugs were fixed where the _mcount routine itself did not >>>> always fix the sp on return. >>>> >>> >> >> > From ddaney.cavm@gmail.com Tue Jan 15 01:36:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 01:36:30 +0100 (CET) Received: from mail-pa0-f48.google.com ([209.85.220.48]:45936 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831941Ab3AOAg31c8Tx (ORCPT ); Tue, 15 Jan 2013 01:36:29 +0100 Received: by mail-pa0-f48.google.com with SMTP id fa1so2544013pad.21 for ; Mon, 14 Jan 2013 16:36:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=3lc4zhVtjitxuGmGFppojqbb/7qGIG7cK5dTcij5a2s=; b=AeiXQ28p7LxvWwSpwYkMFd7YbwZxknZyTMYdMeDK/ErONolX1ZaQD2hkfCKd3FP6RQ E83FG1wb35cEsM7rZzDY1uZfN4Fi4UJZYxYyBNumHUDOf7pXa7EXCn4hDTiCzJ1sGE7O kJdR0qGMIen6+aXmUVl3aadlflm+RkQ7gcEpldIEFpTExebIfO8sti1AyNQxzNxkm5R1 YUULyQHvtfVO4vsKd49MNE22C0bow9OKhPPCM3Z8kfGHgIF8B0eAriNOdAbZe8Al2aE0 PX8RyI0AnfVJ5CLllwyIyqD97HEbfXPA2hYNxe9moEK4QBHDq4Z7qStH9KYbUwTG8LLO b50g== X-Received: by 10.68.216.134 with SMTP id oq6mr258991752pbc.162.1358210182740; Mon, 14 Jan 2013 16:36:22 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id kl5sm9060722pbc.74.2013.01.14.16.36.21 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 14 Jan 2013 16:36:22 -0800 (PST) Message-ID: <50F4A484.4010506@gmail.com> Date: Mon, 14 Jan 2013 16:36:20 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Alan Cooper CC: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> <50F482D1.4090301@gmail.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35436 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6087 Lines: 152 On 01/14/2013 04:13 PM, Alan Cooper wrote: > On Mon, Jan 14, 2013 at 5:12 PM, David Daney wrote: >> On 01/14/2013 01:10 PM, Alan Cooper wrote: >>> >>> I already tried using "adddiu sp, sp, 8" and it caused the kernel to >>> randomly crash. After many hours of debugging the reason occurred to >>> me while in bed in the middle of the night. The problem is that if we >>> get an interrupt between the add 8 and the add -8 instructions, we >>> trash the existing stack. >>> >>> The problem with the 2 nop approach is that there are a series of >>> subroutines used to write each nop and these nested subroutines are >>> traceable. >> >> >> This seems like a bug. The low-level code used to do code patching probably >> should be CFLAGS_REMOVE_file.o = -pg > > While tracing mcount cannot be done because it's recursive, allowing > tracing of the code to enable/disable the call to mcount can be done > and seems useful. Also, fixing the 2 nop solution this way will still > not allow us to stop using stop_machine() which is hugely disruptive > to a running system. Remember that when tracing is enabled and > disabled we end up modifying 20 to 30 thousand functions. Moving this > functionality out of stop_machine() seems like a big benefit. The main point of code patching is to have the Tracing Off state be very low overhead. So low that it might be acceptable to leave it on in a production kernel. Now imagine a highly pipe-lined CPU architecture with a good branch predictor. Issuing a NOP instruction is very low overhead. At most one cycle (a fraction of a cycle on a multi-issue CPU). A Branch Likely that mispredicts (as all of these probably will) can incur a full pipeline flush which can be 10 or more cycles on some machines. This is quite a hit for something that is supposed to be low overhead. It is better than nothing I guess, but I think a better approach would be to modify GCC to generate something easier to handle (this is what we did for MIPS64). > >> >> >> >>> This means on the second call to these subroutines they >>> execute with only one nop and crash. I could write some new code >>> that wrote the 2 nops at once, but (now that I understand >>> "stop_machine") with the branch likely solution we should be able to >>> stop using "stop_machine" when we write nops to the 20-30 thousand >>> Linux functions. It looks like other platforms have stopped using >>> stop_machine. >> >> >> I don't particularly object to the 'branch likely solution', but I think the >> failures of the other approaches indicates underlying bugs in the tracing >> code. Those bugs should probably be fixed. > > If a solution can be found that modifies a single 32bit instruction to > enable/disable tracing, I don't see any bugs in the underlying code. > Plus we can avoid using stop_machine(). > >> >> David Daney >> >> >> >>> >>> Al >>> >>> On Fri, Jan 11, 2013 at 12:01 PM, David Daney >>> wrote: >>>> >>>> On 01/11/2013 06:33 AM, Al Cooper wrote: >>>>> >>>>> >>>>> Function tracing is currently broken for all 32 bit MIPS platforms. >>>>> When tracing is enabled, the kernel immediately hangs on boot. >>>>> This is a result of commit b732d439cb43336cd6d7e804ecb2c81193ef63b0 >>>>> that changes the kernel/trace/Kconfig file so that is no longer >>>>> forces FRAME_POINTER when FUNCTION_TRACING is enabled. >>>>> >>>>> MIPS frame pointers are generally considered to be useless because >>>>> they cannot be used to unwind the stack. Unfortunately the MIPS >>>>> function tracing code has bugs that are masked by the use of frame >>>>> pointers. This commit fixes the bugs so that MIPS frame pointers do >>>>> not need to be enabled. >>>>> >>>>> The bugs are a result of the odd calling sequence used to call the trace >>>>> routine. This calling sequence is inserted into every tracable function >>>>> when the tracing CONFIG option is enabled. This sequence is generated >>>>> for 32bit MIPS platforms by the compiler via the "-pg" flag. >>>>> Part of the sequence is "addiu sp,sp,-8" in the delay slot after every >>>>> call to the trace routine "_mcount" (some legacy thing where 2 arguments >>>>> used to be pushed on the stack). The _mcount routine is expected to >>>>> adjust the sp by +8 before returning. >>>>> >>>>> One of the bugs is that when tracing is disabled for a function, the >>>>> "jalr _mcount" instruction is replaced with a nop, but the >>>>> "addiu sp,sp,-8" is still executed and the stack pointer is left >>>>> trashed. When frame pointers are enabled the problem is masked >>>>> because any access to the stack is done through the frame >>>>> pointer and the stack pointer is restored from the frame pointer when >>>>> the function returns. This patch uses a branch likely instruction >>>>> "bltzl zero, f1" instead of "nop" to disable the call because this >>>>> instruction will not execute the "addiu sp,sp,-8" instruction in >>>>> the delay slot. The other possible solution would be to nop out both >>>>> the jalr and the "addiu sp,sp,-8", but this would need to be interrupt >>>>> and SMP safe and would be much more intrusive. >>>> >>>> >>>> >>>> I thought all CPUs were in stop_machine() when the modifications were >>>> done, >>>> so that there is no issue with multi-word instruction patching. >>>> >>>> Am I wrong about this? >>>> >>>> So really I think you can do two NOP just as easily. >>>> >>>> The only reason I bring this up is that I am not sure all 32-bit CPUs >>>> implement the 'Likely' branch variants. Also there may be an affect on >>>> the >>>> branch predictor. >>>> >>>> A third possibility would be to replace the JALR with 'ADDIU SP,SP,8' >>>> That >>>> way the following adjustment would be canceled out. This would work well >>>> on >>>> single-issue CPUs, but the instructions may not be able to dual-issue on >>>> a >>>> multi issue machine due to data dependencies. >>>> >>>> David Daney >>>> >>>> >>>>> >>>>> A few other bugs were fixed where the _mcount routine itself did not >>>>> always fix the sp on return. >>>>> >>>> >>> >>> >> > > From rostedt@goodmis.org Tue Jan 15 04:40:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 04:40:15 +0100 (CET) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:27909 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816511Ab3AODkOejDsz (ORCPT ); Tue, 15 Jan 2013 04:40:14 +0100 X-Authority-Analysis: v=2.0 cv=O9a7TWBW c=1 sm=0 a=rXTBtCOcEpjy1lPqhTCpEQ==:17 a=mNMOxpOpBa8A:10 a=wom5GMh1gUkA:10 a=79wlbEtt-9EA:10 a=5SG0PmZfjMsA:10 a=kj9zAlcOel0A:10 a=meVymXHHAAAA:8 a=pX4miy-IAAsA:10 a=zIuCNmsNwhn0J9T5-rMA:9 a=CjuIK1q_8ugA:10 a=rXTBtCOcEpjy1lPqhTCpEQ==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 74.67.115.198 Received: from [74.67.115.198] ([74.67.115.198:52742] helo=goliath) by hrndva-oedge04.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id 6C/2F-01424-79FC4F05; Tue, 15 Jan 2013 03:40:07 +0000 Received: by goliath (Postfix, from userid 5657) id CAE1E3E0AD; Mon, 14 Jan 2013 22:40:06 -0500 (EST) Date: Mon, 14 Jan 2013 22:40:06 -0500 From: Steven Rostedt To: David Daney Cc: Al Cooper , ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing Message-ID: <20130115034006.GA3854@home.goodmis.org> References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50F0454D.5060109@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35437 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1840 Lines: 69 On Fri, Jan 11, 2013 at 09:01:01AM -0800, David Daney wrote: > > I thought all CPUs were in stop_machine() when the modifications > were done, so that there is no issue with multi-word instruction > patching. > > Am I wrong about this? > > So really I think you can do two NOP just as easily. The problem with double NOPs is that it can only work if there's no problem executing one nop and a non NOP. Which I think is an issue here. If you have something like: bl _mcount addiu sp,sp,-8 And you convert that to: nop nop Now if you convert that back to: bl ftrace_caller addiu sp,sp,-8 then you can have an issue if the task was preempted after that first nop. Because stop_machine() doesn't wait for tasks to exit kernel space. If you have a CONFIG_PREEMPT kernel, a task can be sleeping anywhere. Thus you have a task execute the first nop, get preempted. You update the code to be: bl ftrace_caller addiu sp,sp,-8 When that task gets scheduled back in, it will act like it just executed: nop addiu sp,sp,-8 Which is the problem you're trying to solve in the first place. Now that said, There's no reason we need that addiu sp,sp,-8 there. That's just what the mips defined mcount requires. But as you can see above, with dynamic ftrace, the defined mcount is only called at boot up, and never again. That means at boot up you can convert to: nop nop and then when you enable tracing just convert it to: bl ftrace_caller nop There's nothing that states what the ftrace caller must be. We can have it do a proper stack update. That is, only at boot up do we need to handle the defined mcount. After that, those instructions are just place holders for our own algorithms. If the addiu was needed for the defined mcount, there's no reason to keep it for our own ftrace_caller. Would that work? -- Steve From sjhill@mips.com Tue Jan 15 07:13:54 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 07:13:56 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:37838 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832184Ab3AOGNyfL-jC (ORCPT ); Tue, 15 Jan 2013 07:13:54 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TuzmL-000077-72; Tue, 15 Jan 2013 00:13:45 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, cernekee@gmail.com, kevink@paralogos.com Subject: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. Date: Tue, 15 Jan 2013 00:13:40 -0600 Message-Id: <1358230420-3575-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35438 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 11658 Lines: 359 From: "Steven J. Hill" This patch shows the use of macros in place of 'union mips_instruction' type. I converted all usages of 'j_format' and 'r_format' to show how the code and macros could look and be defined. I have tested these changes on big and little endian platforms. I want input from everyone, please!!! I want consensus on the macro definitions, placement of parenthesis for them, spacing in the header file, etc. This is your chance to be completely anal and have fun arguments over how things should be. I would also like input on how the maintainers would like the patchsets to look like. For example: [1/X] - Convert 'j_format' [2/X] - Convert 'r_format' [3/X] - Convert 'f_format' [4/X] - Convert 'u_format' ... [X/X] - Remove usage of 'union mips_instruction' type completely. Also, I noticed 'p_format' is not used anywhere. Can we kill it? Be picky and help with this conversion. Thanks. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/inst.h | 66 +++++++++++----------------------------- arch/mips/kernel/branch.c | 13 ++++---- arch/mips/kernel/jump_label.c | 10 +++--- arch/mips/kernel/kgdb.c | 10 ++---- arch/mips/kernel/kprobes.c | 18 +++++------ arch/mips/kernel/process.c | 10 +++--- arch/mips/oprofile/backtrace.c | 2 +- 7 files changed, 46 insertions(+), 83 deletions(-) diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index ab84064..856b14e 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -192,15 +192,27 @@ enum lx_func { lbx_op = 0x16, }; +#define INSN_OPCODE(insn) (insn >> 26) +#define INSN_RS(insn) ((insn >> 21) & 0x1f) +#define INSN_RT(insn) ((insn >> 16) & 0x1f) +#define INSN_RD(insn) ((insn >> 11) & 0x1f) +#define INSN_RE(insn) ((insn >> 6) & 0x1f) +#define INSN_FUNC(insn) (insn & 0x0000003f) + +#define J_INSN(op,target) ((op << 26) | target) +#define J_INSN_TARGET(insn) (insn & 0x03ffffff) +#define R_INSN(op,rs,rt,rd,re,func) ((op << 26) | (rs << 21) | \ + (rt << 16) | (rd << 11) | \ + (re << 6) | func) +#define F_INSN(op,fmt,rt,rd,re,func) R_INSN(op,fmt,rt,rd,re,func) +#define F_INSN_FMT(insn) INSN_RS(insn) +#define U_INSN(op,rs,uimm) ((op << 26) | (rs << 21) | uimmediate) +#define U_INSN_UIMM(insn) (insn & 0x0000ffff) + /* * Damn ... bitfields depend from byteorder :-( */ #ifdef __MIPSEB__ -struct j_format { /* Jump format */ - unsigned int opcode : 6; - unsigned int target : 26; -}; - struct i_format { /* Immediate format (addi, lw, ...) */ unsigned int opcode : 6; unsigned int rs : 5; @@ -223,24 +235,6 @@ struct c_format { /* Cache (>= R6000) format */ unsigned int simmediate : 16; }; -struct r_format { /* Register format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - struct f_format { /* FPU register format */ unsigned int opcode : 6; unsigned int : 1; @@ -268,12 +262,6 @@ struct b_format { /* BREAK and SYSCALL */ }; #elif defined(__MIPSEL__) - -struct j_format { /* Jump format */ - unsigned int target : 26; - unsigned int opcode : 6; -}; - struct i_format { /* Immediate format */ signed int simmediate : 16; unsigned int rt : 5; @@ -296,24 +284,6 @@ struct c_format { /* Cache (>= R6000) format */ unsigned int opcode : 6; }; -struct r_format { /* Register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - struct f_format { /* FPU register format */ unsigned int func : 6; unsigned int re : 5; @@ -348,11 +318,9 @@ union mips_instruction { unsigned int word; unsigned short halfword[2]; unsigned char byte[4]; - struct j_format j_format; struct i_format i_format; struct u_format u_format; struct c_format c_format; - struct r_format r_format; struct f_format f_format; struct ma_format ma_format; struct b_format b_format; diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index 4d735d0..d51fa79 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -34,18 +34,19 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, unsigned int bit, fcr31, dspcontrol; long epc = regs->cp0_epc; int ret = 0; + unsigned int n_insn = insn.word; switch (insn.i_format.opcode) { /* - * jr and jalr are in r_format format. + * jr and jalr are in return instruction format. */ case spec_op: - switch (insn.r_format.func) { + switch (INSN_FUNC(n_insn)) { case jalr_op: - regs->regs[insn.r_format.rd] = epc + 8; + regs->regs[INSN_RD(n_insn)] = epc + 8; /* Fall through */ case jr_op: - regs->cp0_epc = regs->regs[insn.r_format.rs]; + regs->cp0_epc = regs->regs[INSN_RS(n_insn)]; break; } break; @@ -119,7 +120,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, break; /* - * These are unconditional and in j_format. + * These are unconditional and are jump instruction format. */ case jal_op: regs->regs[31] = regs->cp0_epc + 8; @@ -127,7 +128,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, epc += 4; epc >>= 28; epc <<= 28; - epc |= (insn.j_format.target << 2); + epc |= (J_INSN_TARGET(n_insn) << 2); regs->cp0_epc = epc; break; diff --git a/arch/mips/kernel/jump_label.c b/arch/mips/kernel/jump_label.c index 6001610..d938642 100644 --- a/arch/mips/kernel/jump_label.c +++ b/arch/mips/kernel/jump_label.c @@ -23,9 +23,8 @@ void arch_jump_label_transform(struct jump_entry *e, enum jump_label_type type) { - union mips_instruction insn; - union mips_instruction *insn_p = - (union mips_instruction *)(unsigned long)e->code; + unsigned int insn; + unsigned int *insn_p = (unsigned int *)(unsigned long)e->code; /* Jump only works within a 256MB aligned region. */ BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK)); @@ -34,10 +33,9 @@ void arch_jump_label_transform(struct jump_entry *e, BUG_ON((e->target & 3) != 0); if (type == JUMP_LABEL_ENABLE) { - insn.j_format.opcode = j_op; - insn.j_format.target = (e->target & J_RANGE_MASK) >> 2; + insn = J_INSN(j_op, (e->target & J_RANGE_MASK) >> 2); } else { - insn.word = 0; /* nop */ + insn = 0; /* nop */ } get_online_cpus(); diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index 23817a6..89887c5 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -368,13 +368,9 @@ struct kgdb_arch arch_kgdb_ops; */ int kgdb_arch_init(void) { - union mips_instruction insn = { - .r_format = { - .opcode = spec_op, - .func = break_op, - } - }; - memcpy(arch_kgdb_ops.gdb_bpt_instr, insn.byte, BREAK_INSTR_SIZE); + unsigned int insn = R_INSN(spec_op, 0, 0, 0, 0, break_op); + + memcpy(arch_kgdb_ops.gdb_bpt_instr, &insn, BREAK_INSTR_SIZE); register_die_notifier(&kgdb_notifier); diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c index 158467d..bc24241 100644 --- a/arch/mips/kernel/kprobes.c +++ b/arch/mips/kernel/kprobes.c @@ -53,16 +53,16 @@ static const union mips_instruction breakpoint2_insn = { DEFINE_PER_CPU(struct kprobe *, current_kprobe); DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); -static int __kprobes insn_has_delayslot(union mips_instruction insn) +static int __kprobes insn_has_delayslot(unsigned int insn) { - switch (insn.i_format.opcode) { + switch (INSN_OPCODE(insn)) { /* * This group contains: - * jr and jalr are in r_format format. + * jr and jalr are in return instruction format. */ case spec_op: - switch (insn.r_format.func) { + switch (R_INSN_FUNC(insn)) { case jr_op: case jalr_op: break; @@ -78,7 +78,7 @@ static int __kprobes insn_has_delayslot(union mips_instruction insn) case bcond_op: /* - * These are unconditional and in j_format. + * These are unconditional and in jump instruction format. */ case jal_op: case j_op: @@ -155,7 +155,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) if ((probe_kernel_read(&prev_insn, p->addr - 1, sizeof(mips_instruction)) == 0) && - insn_has_delayslot(prev_insn)) { + insn_has_delayslot(prev_insn.word)) { pr_notice("Kprobes for branch delayslot are not supported\n"); ret = -EINVAL; goto out; @@ -181,7 +181,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) * using a normal breakpoint instruction in the next slot. * So, read the instruction and save it for later execution. */ - if (insn_has_delayslot(insn)) + if (insn_has_delayslot(insn.word)) memcpy(&p->ainsn.insn[0], p->addr + 1, sizeof(kprobe_opcode_t)); else memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t)); @@ -294,7 +294,7 @@ static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs, if (p->opcode.word == breakpoint_insn.word || p->opcode.word == breakpoint2_insn.word) regs->cp0_epc = (unsigned long)p->addr; - else if (insn_has_delayslot(p->opcode)) { + else if (insn_has_delayslot(((union mips_instruction)p->opcode).word)) { ret = evaluate_branch_instruction(p, regs, kcb); if (ret < 0) { pr_notice("Kprobes: Error in evaluating branch\n"); @@ -320,7 +320,7 @@ static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb) { - if (insn_has_delayslot(p->opcode)) + if (insn_has_delayslot(((union mips_instruction)p->opcode).word)) regs->cp0_epc = kcb->target_epc; else { unsigned long orig_epc = kcb->kprobe_saved_epc; diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index a11c6f9..e160923 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -248,13 +248,13 @@ static inline int is_ra_save_ins(union mips_instruction *ip) ip->i_format.rt == 31; } -static inline int is_jal_jalr_jr_ins(union mips_instruction *ip) +static inline int is_jal_jalr_jr_ins(unsigned int insn) { - if (ip->j_format.opcode == jal_op) + if (INSN_OPCODE(insn) == jal_op) return 1; - if (ip->r_format.opcode != spec_op) + if (INSN_OPCODE(insn) != spec_op) return 0; - return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; + return INSN_FUNC(insn) == jalr_op || INSN_FUNC(insn) == jr_op; } static inline int is_sp_move_ins(union mips_instruction *ip) @@ -285,7 +285,7 @@ static int get_frame_info(struct mips_frame_info *info) for (i = 0; i < max_insns; i++, ip++) { - if (is_jal_jalr_jr_ins(ip)) + if (is_jal_jalr_jr_ins(ip->word)) break; if (!info->frame_size) { if (is_sp_move_ins(ip)) diff --git a/arch/mips/oprofile/backtrace.c b/arch/mips/oprofile/backtrace.c index 6854ed5..26d05cd 100644 --- a/arch/mips/oprofile/backtrace.c +++ b/arch/mips/oprofile/backtrace.c @@ -52,7 +52,7 @@ static inline int is_sp_move_ins(union mips_instruction *ip) static inline int is_end_of_function_marker(union mips_instruction *ip) { /* jr ra */ - if (ip->r_format.func == jr_op && ip->r_format.rs == 31) + if (R_INSN_FUNC(ip->word) && R_INSN_RS(ip->word) == 31) return 1; /* lui gp */ if (ip->i_format.opcode == lui_op && ip->i_format.rt == 28) -- 1.7.9.5 From jchandra@broadcom.com Tue Jan 15 07:16:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 07:16:48 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:1877 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832184Ab3AOGQog7lFb (ORCPT ); Tue, 15 Jan 2013 07:16:44 +0100 Received: from [10.9.200.131] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 22:11:14 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Mon, 14 Jan 2013 22:16:25 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id C8A0C40FE3; Mon, 14 Jan 2013 22:16:23 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 03/10] MIPS: PCI: Byteswap not needed in little-endian mode Date: Tue, 15 Jan 2013 11:49:06 +0530 Message-ID: <1358230746-13785-1-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-4-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-4-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEA2C883Q42207037-02-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35439 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1417 Lines: 51 Wrap the xlp_enable_pci_bswap() function and its call with '#ifdef __BIG_ENDIAN'. On Netlogic XLP, the PCIe initialization code to setup to byteswap is needed only in big-endian mode. Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlp.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 140557a..d201efa 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -191,8 +191,14 @@ int pcibios_plat_dev_init(struct pci_dev *dev) return 0; } -static int xlp_enable_pci_bswap(void) +/* + * If big-endian, enable hardware byteswap on the PCIe bridges. + * This will make both the SoC and PCIe devices behave consistently with + * readl/writel. + */ +static void xlp_config_pci_bswap(void) { +#ifdef __BIG_ENDIAN uint64_t pciebase, sysbase; int node, i; u32 reg; @@ -222,7 +228,7 @@ static int xlp_enable_pci_bswap(void) reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); } - return 0; +#endif } static int __init pcibios_init(void) @@ -235,7 +241,7 @@ static int __init pcibios_init(void) ioport_resource.start = 0; ioport_resource.end = ~0; - xlp_enable_pci_bswap(); + xlp_config_pci_bswap(); set_io_port_base(CKSEG1); nlm_pci_controller.io_map_base = CKSEG1; -- 1.7.9.5 From jchandra@broadcom.com Tue Jan 15 07:18:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 07:18:06 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:3027 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832184Ab3AOGSEm7ZVK (ORCPT ); Tue, 15 Jan 2013 07:18:04 +0100 Received: from [10.9.208.26] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 22:14:42 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHCAS05.corp.ad.broadcom.com (10.9.208.26) with Microsoft SMTP Server id 14.1.355.2; Mon, 14 Jan 2013 22:17:48 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 87DD440FE8; Mon, 14 Jan 2013 22:17:46 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 10/10] MIPS: PCI: Multi-node PCI support for Netlogic XLP Date: Tue, 15 Jan 2013 11:50:29 +0530 Message-ID: <1358230829-13820-1-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-11-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-11-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEA2C583QG29118-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35440 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5179 Lines: 173 On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCI on all the nodes. Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlp.c | 107 ++++++++++++++++++++++++++++------------------- 1 file changed, 65 insertions(+), 42 deletions(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 5f1a6de..920b715 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -46,6 +46,7 @@ #include #include +#include #include #include @@ -161,32 +162,38 @@ struct pci_controller nlm_pci_controller = { .io_offset = 0x00000000UL, }; -static int get_irq_vector(const struct pci_dev *dev) +static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) { - /* - * For XLP PCIe, there is an IRQ per Link, find out which - * link the device is on to assign interrupts - */ - if (dev->bus->self == NULL) - return 0; + struct pci_bus *bus, *p; - switch (dev->bus->self->devfn) { - case 0x8: - return PIC_PCIE_LINK_0_IRQ; - case 0x9: - return PIC_PCIE_LINK_1_IRQ; - case 0xa: - return PIC_PCIE_LINK_2_IRQ; - case 0xb: - return PIC_PCIE_LINK_3_IRQ; - } - WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); - return 0; + /* Find the bridge on bus 0 */ + bus = dev->bus; + for (p = bus->parent; p && p->number != 0; p = p->parent) + bus = p; + + return p ? bus->self : NULL; +} + +static inline int nlm_pci_link_to_irq(int link) +{ + return PIC_PCIE_LINK_0_IRQ + link; } int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - return get_irq_vector(dev); + struct pci_dev *lnkdev; + int lnkslot, lnkfunc, irq; + + /* + * For XLP PCIe, there is an IRQ per Link, find out which + * link the device is on to assign interrupts + */ + lnkdev = xlp_get_pcie_link(dev); + if (lnkdev == NULL) + return 0; + lnkfunc = PCI_FUNC(lnkdev->devfn); + lnkslot = PCI_SLOT(lnkdev->devfn); + return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc)); } /* Do platform specific device initialization at pci_enable_device() time */ @@ -200,43 +207,40 @@ int pcibios_plat_dev_init(struct pci_dev *dev) * This will make both the SoC and PCIe devices behave consistently with * readl/writel. */ -static void xlp_config_pci_bswap(void) +static int xlp_config_pci_bswap(int node, int link) { #ifdef __BIG_ENDIAN - uint64_t pciebase, sysbase; - int node, i; + uint64_t nbubase, lnkbase; u32 reg; - /* Chip-0 so node set to 0 */ - node = 0; - sysbase = nlm_get_bridge_regbase(node); + nbubase = nlm_get_bridge_regbase(node); + lnkbase = nlm_get_pcie_base(node, link); + /* * Enable byte swap in hardware. Program each link's PCIe SWAP regions * from the link's address ranges. */ - for (i = 0; i < 4; i++) { - pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i)); - if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) - continue; + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, - reg | 0xfff); + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); - - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); - } + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); #endif } static int __init pcibios_init(void) { + struct nlm_soc_info *nodep; + uint64_t pciebase; + int link, n; + u32 reg; + /* Firmware assigns PCI resources */ pci_set_flags(PCI_PROBE_ONLY); pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); @@ -245,7 +249,26 @@ static int __init pcibios_init(void) ioport_resource.start = 0; ioport_resource.end = ~0; - xlp_config_pci_bswap(); + for (n = 0; n < NLM_NR_NODES; n++) { + nodep = nlm_get_node(n); + if (!nodep->coremask) + continue; /* node does not exist */ + + for (link = 0; link < 4; link++) { + pciebase = nlm_get_pcie_base(n, link); + if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) + continue; + xlp_config_pci_bswap(n, link); + + /* put in intpin and irq - u-boot does not */ + reg = nlm_read_pci_reg(pciebase, 0xf); + reg &= ~0x1fu; + reg |= (1 << 8) | nlm_pci_link_to_irq(link); + nlm_write_pci_reg(pciebase, 0xf, reg); + pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); + } + } + set_io_port_base(CKSEG1); nlm_pci_controller.io_map_base = CKSEG1; -- 1.7.9.5 From jchandra@broadcom.com Tue Jan 15 07:36:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 07:36:06 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:4831 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832072Ab3AOGgEgUbWc (ORCPT ); Tue, 15 Jan 2013 07:36:04 +0100 Received: from [10.9.208.53] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 22:30:35 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by irvexchcas06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server id 14.1.355.2; Mon, 14 Jan 2013 22:35:46 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id C565840FE5; Mon, 14 Jan 2013 22:35:45 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 10/10] MIPS: PCI: Multi-node PCI support for Netlogic XLP Date: Tue, 15 Jan 2013 12:08:27 +0530 Message-ID: <1358231908-14458-1-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358179922-26663-11-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-11-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEA28013Q42212848-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35441 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5179 Lines: 173 On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCI on all the nodes. Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlp.c | 107 ++++++++++++++++++++++++++++------------------- 1 file changed, 65 insertions(+), 42 deletions(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 5f1a6de..920b715 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -46,6 +46,7 @@ #include #include +#include #include #include @@ -161,32 +162,38 @@ struct pci_controller nlm_pci_controller = { .io_offset = 0x00000000UL, }; -static int get_irq_vector(const struct pci_dev *dev) +static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) { - /* - * For XLP PCIe, there is an IRQ per Link, find out which - * link the device is on to assign interrupts - */ - if (dev->bus->self == NULL) - return 0; + struct pci_bus *bus, *p; - switch (dev->bus->self->devfn) { - case 0x8: - return PIC_PCIE_LINK_0_IRQ; - case 0x9: - return PIC_PCIE_LINK_1_IRQ; - case 0xa: - return PIC_PCIE_LINK_2_IRQ; - case 0xb: - return PIC_PCIE_LINK_3_IRQ; - } - WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); - return 0; + /* Find the bridge on bus 0 */ + bus = dev->bus; + for (p = bus->parent; p && p->number != 0; p = p->parent) + bus = p; + + return p ? bus->self : NULL; +} + +static inline int nlm_pci_link_to_irq(int link) +{ + return PIC_PCIE_LINK_0_IRQ + link; } int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - return get_irq_vector(dev); + struct pci_dev *lnkdev; + int lnkslot, lnkfunc, irq; + + /* + * For XLP PCIe, there is an IRQ per Link, find out which + * link the device is on to assign interrupts + */ + lnkdev = xlp_get_pcie_link(dev); + if (lnkdev == NULL) + return 0; + lnkfunc = PCI_FUNC(lnkdev->devfn); + lnkslot = PCI_SLOT(lnkdev->devfn); + return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc)); } /* Do platform specific device initialization at pci_enable_device() time */ @@ -200,43 +207,40 @@ int pcibios_plat_dev_init(struct pci_dev *dev) * This will make both the SoC and PCIe devices behave consistently with * readl/writel. */ -static void xlp_config_pci_bswap(void) +static int xlp_config_pci_bswap(int node, int link) { #ifdef __BIG_ENDIAN - uint64_t pciebase, sysbase; - int node, i; + uint64_t nbubase, lnkbase; u32 reg; - /* Chip-0 so node set to 0 */ - node = 0; - sysbase = nlm_get_bridge_regbase(node); + nbubase = nlm_get_bridge_regbase(node); + lnkbase = nlm_get_pcie_base(node, link); + /* * Enable byte swap in hardware. Program each link's PCIe SWAP regions * from the link's address ranges. */ - for (i = 0; i < 4; i++) { - pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i)); - if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) - continue; + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, - reg | 0xfff); + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); - - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); - } + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); #endif } static int __init pcibios_init(void) { + struct nlm_soc_info *nodep; + uint64_t pciebase; + int link, n; + u32 reg; + /* Firmware assigns PCI resources */ pci_set_flags(PCI_PROBE_ONLY); pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); @@ -245,7 +249,26 @@ static int __init pcibios_init(void) ioport_resource.start = 0; ioport_resource.end = ~0; - xlp_config_pci_bswap(); + for (n = 0; n < NLM_NR_NODES; n++) { + nodep = nlm_get_node(n); + if (!nodep->coremask) + continue; /* node does not exist */ + + for (link = 0; link < 4; link++) { + pciebase = nlm_get_pcie_base(n, link); + if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) + continue; + xlp_config_pci_bswap(n, link); + + /* put in intpin and irq - u-boot does not */ + reg = nlm_read_pci_reg(pciebase, 0xf); + reg &= ~0x1fu; + reg |= (1 << 8) | nlm_pci_link_to_irq(link); + nlm_write_pci_reg(pciebase, 0xf, reg); + pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); + } + } + set_io_port_base(CKSEG1); nlm_pci_controller.io_map_base = CKSEG1; -- 1.7.9.5 From jchandra@broadcom.com Tue Jan 15 07:36:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 07:36:24 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:4833 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832184Ab3AOGgErhaUT (ORCPT ); Tue, 15 Jan 2013 07:36:04 +0100 Received: from [10.9.208.26] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 14 Jan 2013 22:30:38 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHCAS05.corp.ad.broadcom.com (10.9.208.26) with Microsoft SMTP Server id 14.1.355.2; Mon, 14 Jan 2013 22:35:49 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id BEF2740FE8; Mon, 14 Jan 2013 22:35:47 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 03/10] MIPS: PCI: Byteswap not needed in little-endian mode Date: Tue, 15 Jan 2013 12:08:28 +0530 Message-ID: <1358231908-14458-2-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358231908-14458-1-git-send-email-jchandra@broadcom.com> References: <1358179922-26663-11-git-send-email-jchandra@broadcom.com> <1358231908-14458-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CEA28043Q42212864-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35442 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1642 Lines: 57 Rename xlp_enable_pci_bswap() to xlp_config_pci_bswap(), and add '#ifdef __BIG_ENDIAN' to its contents so that it is an empty function when compiled in little-endian mode. On Netlogic XLP, the PCIe initialization code to enable byteswap is needed only in big-endian mode. Signed-off-by: Jayachandran C --- [Update comments to reflect changes in updated patch. The changes are based on a suggestion on #ifdef usage by sshtylyov@mvista.com ] arch/mips/pci/pci-xlp.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 140557a..d201efa 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -191,8 +191,14 @@ int pcibios_plat_dev_init(struct pci_dev *dev) return 0; } -static int xlp_enable_pci_bswap(void) +/* + * If big-endian, enable hardware byteswap on the PCIe bridges. + * This will make both the SoC and PCIe devices behave consistently with + * readl/writel. + */ +static void xlp_config_pci_bswap(void) { +#ifdef __BIG_ENDIAN uint64_t pciebase, sysbase; int node, i; u32 reg; @@ -222,7 +228,7 @@ static int xlp_enable_pci_bswap(void) reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); } - return 0; +#endif } static int __init pcibios_init(void) @@ -235,7 +241,7 @@ static int __init pcibios_init(void) ioport_resource.start = 0; ioport_resource.end = ~0; - xlp_enable_pci_bswap(); + xlp_config_pci_bswap(); set_io_port_base(CKSEG1); nlm_pci_controller.io_map_base = CKSEG1; -- 1.7.9.5 From ralf@linux-mips.org Tue Jan 15 09:25:00 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 09:25:01 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59789 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6832188Ab3AOIZAhC-H- (ORCPT ); Tue, 15 Jan 2013 09:25:00 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0F8Ow27012004; Tue, 15 Jan 2013 09:24:58 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0F8OuVD012003; Tue, 15 Jan 2013 09:24:56 +0100 Date: Tue, 15 Jan 2013 09:24:56 +0100 From: Ralf Baechle To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, cernekee@gmail.com, kevink@paralogos.com Subject: Re: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. Message-ID: <20130115082456.GA17364@linux-mips.org> References: <1358230420-3575-1-git-send-email-sjhill@mips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1358230420-3575-1-git-send-email-sjhill@mips.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35443 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1164 Lines: 29 On Tue, Jan 15, 2013 at 12:13:40AM -0600, Steven J. Hill wrote: > From: "Steven J. Hill" > > This patch shows the use of macros in place of 'union mips_instruction' > type. I converted all usages of 'j_format' and 'r_format' to show how > the code and macros could look and be defined. I have tested these > changes on big and little endian platforms. > > I want input from everyone, please!!! I want consensus on the macro > definitions, placement of parenthesis for them, spacing in the header > file, etc. This is your chance to be completely anal and have fun > arguments over how things should be. I would also like input on how > the maintainers would like the patchsets to look like. For example: > > [1/X] - Convert 'j_format' > [2/X] - Convert 'r_format' > [3/X] - Convert 'f_format' > [4/X] - Convert 'u_format' > ... > [X/X] - Remove usage of 'union mips_instruction' type completely. > > Also, I noticed 'p_format' is not used anywhere. Can we kill it? Be > picky and help with this conversion. Thanks. Mayne not kill it completely abut leave a comment mentioning its existence for the sake of completeness. Ralf From sshtylyov@mvista.com Tue Jan 15 12:58:20 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 12:58:23 +0100 (CET) Received: from mail-lb0-f176.google.com ([209.85.217.176]:65217 "EHLO mail-lb0-f176.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832189Ab3AOL6UYvV8M (ORCPT ); Tue, 15 Jan 2013 12:58:20 +0100 Received: by mail-lb0-f176.google.com with SMTP id k6so88392lbo.35 for ; Tue, 15 Jan 2013 03:58:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=a7noR6qYczR2mahHcn8u1ETApKJ0N33iHwch57gc7vs=; b=QEVEGdL85nxnGZVDgouB34+502yF4D1ynLiip9l5OHej8qmDDieQnNukaBzWsTQIrn b8ipz28a/cOsz2tLq3vQRPH46Z+P7kDuhU4st+29hoZUOKvwZYQdK9S84iccWu4lAdKP neLp7RLr5NtXcK8bAW9HYoa2YbZYgDGVEjwI3KIuHkjhFNsDJyT+b8wVDsJRia67In3Q 4DI/ABwcbdv1PqZa7siRrJ6t1+c/sKQtPEsZGdoaweWo3l9YbJLjrMfNtIUu01Ja69cx bba5TSMHZgHxnRCGOXoYnN7TdN0HIBUKWNhMnTCD4nh2Rd235sNFzChNvMgAvBDoETGJ JkHw== X-Received: by 10.112.13.229 with SMTP id k5mr36168767lbc.125.1358251094613; Tue, 15 Jan 2013 03:58:14 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-80-168.pppoe.mtu-net.ru. [91.79.80.168]) by mx.google.com with ESMTPS id ee5sm6658031lbb.14.2013.01.15.03.58.11 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 15 Jan 2013 03:58:13 -0800 (PST) Message-ID: <50F5444C.5020209@mvista.com> Date: Tue, 15 Jan 2013 15:58:04 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130107 Thunderbird/17.0.2 MIME-Version: 1.0 To: Jayachandran C CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 03/10] MIPS: PCI: Byteswap not needed in little-endian mode References: <1358179922-26663-4-git-send-email-jchandra@broadcom.com> <1358230746-13785-1-git-send-email-jchandra@broadcom.com> In-Reply-To: <1358230746-13785-1-git-send-email-jchandra@broadcom.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlEjbOvXeeXqHoFnQXo962r3mXYTHqd7DTVdonqwufNsBxDB67DTkJtW3KU2ezyiU7WeNre X-archive-position: 35444 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1373 Lines: 45 Hello. On 15-01-2013 10:19, Jayachandran C wrote: > Wrap the xlp_enable_pci_bswap() function and its call with > '#ifdef __BIG_ENDIAN'. On Netlogic XLP, the PCIe initialization code > to setup to byteswap is needed only in big-endian mode. > Signed-off-by: Jayachandran C > --- > arch/mips/pci/pci-xlp.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c > index 140557a..d201efa 100644 > --- a/arch/mips/pci/pci-xlp.c > +++ b/arch/mips/pci/pci-xlp.c > @@ -191,8 +191,14 @@ int pcibios_plat_dev_init(struct pci_dev *dev) > return 0; > } > > -static int xlp_enable_pci_bswap(void) > +/* > + * If big-endian, enable hardware byteswap on the PCIe bridges. > + * This will make both the SoC and PCIe devices behave consistently with > + * readl/writel. > + */ > +static void xlp_config_pci_bswap(void) > { > +#ifdef __BIG_ENDIAN > uint64_t pciebase, sysbase; > int node, i; > u32 reg; > @@ -222,7 +228,7 @@ static int xlp_enable_pci_bswap(void) > reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); > nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); > } > - return 0; > +#endif You misunderstood. #ifdef within functions are frowned upon. Thios patch is hardly better than previous then. WBR, Sergei From florian@openwrt.org Tue Jan 15 13:18:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 13:18:56 +0100 (CET) Received: from mail-la0-f51.google.com ([209.85.215.51]:46515 "EHLO mail-la0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832195Ab3AOMSz2Of-q (ORCPT ); Tue, 15 Jan 2013 13:18:55 +0100 Received: by mail-la0-f51.google.com with SMTP id fj20so24754lab.24 for ; Tue, 15 Jan 2013 04:18:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:message-id:date:from:organization:user-agent :mime-version:to:cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=+PPuMZX3q7q/QYf4TPilurslNaYh1jyOQuSOKQUsKvc=; b=EX2E1vvM2q/O53XPt+++O/Y6Izw5cd4PrQNSq//bzZlr9xlQXdv6reg+AI1OQLWCaA 7+tG9Bgp71BCguR9S/TAp3SRmt1dVO8aXhCPuejUVscl8bDi4Cua6/DjgdbT1gQq0V5N cw8qfavf0yHQ9xnYFRTbVt5+gogQfCsoZb6YGM6zb5dQ/7RI/EWvrjFEzVaL3POteVNu /xxCgwO6bn5PeDCBL31tB6P7w3d8iVSf5eZ4CP2l0fXoG1A0V+z+U/OE57nDuF5W4/Nm SU2FLoUKK7F62vEP4S/w/00JFYQtj+h8gSxQ6HIVfdLOf0sFOR3ObWg/YH5Qj/fajRX1 fc1Q== X-Received: by 10.152.145.37 with SMTP id sr5mr28713094lab.33.1358252329757; Tue, 15 Jan 2013 04:18:49 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id v7sm6686079lbj.13.2013.01.15.04.18.48 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 15 Jan 2013 04:18:49 -0800 (PST) Message-ID: <50F5488C.4010006@openwrt.org> Date: Tue, 15 Jan 2013 13:16:12 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: Sergei Shtylyov CC: Jayachandran C , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 03/10] MIPS: PCI: Byteswap not needed in little-endian mode References: <1358179922-26663-4-git-send-email-jchandra@broadcom.com> <1358230746-13785-1-git-send-email-jchandra@broadcom.com> <50F5444C.5020209@mvista.com> In-Reply-To: <50F5444C.5020209@mvista.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35445 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1302 Lines: 47 On 01/15/2013 12:58 PM, Sergei Shtylyov wrote: > Hello. > > On 15-01-2013 10:19, Jayachandran C wrote: > >> Wrap the xlp_enable_pci_bswap() function and its call with >> '#ifdef __BIG_ENDIAN'. On Netlogic XLP, the PCIe initialization code >> to setup to byteswap is needed only in big-endian mode. > >> Signed-off-by: Jayachandran C [snip] >> +/* >> + * If big-endian, enable hardware byteswap on the PCIe bridges. >> + * This will make both the SoC and PCIe devices behave consistently with >> + * readl/writel. >> + */ >> +static void xlp_config_pci_bswap(void) >> { >> +#ifdef __BIG_ENDIAN >> uint64_t pciebase, sysbase; >> int node, i; >> u32 reg; >> @@ -222,7 +228,7 @@ static int xlp_enable_pci_bswap(void) >> reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); >> nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | >> 0xfff); >> } >> - return 0; >> +#endif > > You misunderstood. #ifdef within functions are frowned upon. Thios > patch is hardly better than previous then. Jayachandran, you probably need something like this: #ifdef __BIG_ENDIAN static void xlp_config_pci_bswap(void) { /* perform the actual swapping */ } #else static inline void xlp_config_pci_bswap(void) { } #endif -- Florian From alcooperx@gmail.com Tue Jan 15 18:53:07 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 18:53:08 +0100 (CET) Received: from mail-qa0-f41.google.com ([209.85.216.41]:36018 "EHLO mail-qa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832207Ab3AORxHmngS3 (ORCPT ); Tue, 15 Jan 2013 18:53:07 +0100 Received: by mail-qa0-f41.google.com with SMTP id o19so2612570qap.14 for ; Tue, 15 Jan 2013 09:53:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=eXVA+JLHeye3fE9u6QNZg4QFfKFxF2EGYouEeKF5RaE=; b=NV8VW1h081Oq5/TfrQNuDB3/Cupyc3bjzumQgND5ajZG+q0Y6blMpTARZHZJAUNAVn 1vQjz9ErgshmccBMiHWPqiaOxmaHE7Jtsp5zKBV+fUhgEbwBrfBmPugtZZthSnnwDzQX 0w/CORnLUCnNjX47j0P7rdwo6Wr466bUCRicazkcXaYKrDSPPjUijIAEUKzNI2sMRNxd l8mbx7oObeQdrldYxWuEErZfDdrvbfoxAAmb/sij9GQjyF63UH2RsjDGBGcTl5uvs/cn /gz0ozuQ50bFIE42pQkZjcRR94gzUjVpHyOq1ztK6aZFPX48cmYz3NeG7W4Bywx5IDNG MWhQ== MIME-Version: 1.0 Received: by 10.224.59.135 with SMTP id l7mr74488205qah.25.1358272381177; Tue, 15 Jan 2013 09:53:01 -0800 (PST) Received: by 10.49.117.161 with HTTP; Tue, 15 Jan 2013 09:53:00 -0800 (PST) In-Reply-To: <20130115034006.GA3854@home.goodmis.org> References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> <20130115034006.GA3854@home.goodmis.org> Date: Tue, 15 Jan 2013 12:53:00 -0500 Message-ID: Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing From: Alan Cooper To: Steven Rostedt Cc: David Daney , ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35446 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2150 Lines: 70 On Mon, Jan 14, 2013 at 10:40 PM, Steven Rostedt wrote: > On Fri, Jan 11, 2013 at 09:01:01AM -0800, David Daney wrote: >> >> I thought all CPUs were in stop_machine() when the modifications >> were done, so that there is no issue with multi-word instruction >> patching. >> >> Am I wrong about this? >> >> So really I think you can do two NOP just as easily. > > The problem with double NOPs is that it can only work if there's no > problem executing one nop and a non NOP. Which I think is an issue here. > > > If you have something like: > > bl _mcount > addiu sp,sp,-8 > > And you convert that to: > > nop > nop > > Now if you convert that back to: > > bl ftrace_caller > addiu sp,sp,-8 > > then you can have an issue if the task was preempted after that first > nop. Because stop_machine() doesn't wait for tasks to exit kernel space. > If you have a CONFIG_PREEMPT kernel, a task can be sleeping anywhere. > Thus you have a task execute the first nop, get preempted. You update > the code to be: > > bl ftrace_caller > addiu sp,sp,-8 > > When that task gets scheduled back in, it will act like it just > executed: > > nop > addiu sp,sp,-8 > > Which is the problem you're trying to solve in the first place. > > Now that said, There's no reason we need that addiu sp,sp,-8 there. > That's just what the mips defined mcount requires. But as you can see > above, with dynamic ftrace, the defined mcount is only called at boot > up, and never again. That means at boot up you can convert to: > > nop > nop > > and then when you enable tracing just convert it to: > > bl ftrace_caller > nop > > There's nothing that states what the ftrace caller must be. We can have > it do a proper stack update. That is, only at boot up do we need to > handle the defined mcount. After that, those instructions are just place > holders for our own algorithms. If the addiu was needed for the defined > mcount, there's no reason to keep it for our own ftrace_caller. > > Would that work? > > -- Steve > From ddaney.cavm@gmail.com Tue Jan 15 18:55:39 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 18:55:39 +0100 (CET) Received: from mail-pa0-f46.google.com ([209.85.220.46]:35400 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832191Ab3AORzjAA-Z1 (ORCPT ); Tue, 15 Jan 2013 18:55:39 +0100 Received: by mail-pa0-f46.google.com with SMTP id bh2so244782pad.19 for ; Tue, 15 Jan 2013 09:55:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=KNQPESryOR/5+HTe6k3e9yU7OVjnyuKDm8AW6vymrsc=; b=TWfsadgbSTW9zm3kUSR/Qibz1QpG05VuXJzD9cl52wAhk/hcZJYFK8YmV74pvpDTwg wJvKEicztDxXjWT65Rx/IvutOMG34YuahI17cLNqfaccbeukqatN6KMiGoK8OPQL0SQu p+yid/aDh+a40ilerM3Z6SmC+yPEkSQFboi0tCsDOQny0MCkEkzjcZRo3FbkmGtr364M bjdCH1IfZEZ+caLvZ7rAVPg6s8b5DHEs9law+Q4ai5dQbArk7OEtzERha4IxWcqCWkCn d/ro82eGnYFEm/lyzJLOjLtLkMwN4A/L2aVAn/jQ9aVsCe8lfq4dkd3dkOoyuP+H9rpz /bow== X-Received: by 10.66.79.74 with SMTP id h10mr223227002pax.25.1358272531931; Tue, 15 Jan 2013 09:55:31 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id gv9sm10591737pbc.21.2013.01.15.09.55.30 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 15 Jan 2013 09:55:31 -0800 (PST) Message-ID: <50F59812.6040806@gmail.com> Date: Tue, 15 Jan 2013 09:55:30 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Steven Rostedt , Al Cooper , ralf@linux-mips.org CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> <20130115034006.GA3854@home.goodmis.org> In-Reply-To: <20130115034006.GA3854@home.goodmis.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35447 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2473 Lines: 89 On 01/14/2013 07:40 PM, Steven Rostedt wrote: > On Fri, Jan 11, 2013 at 09:01:01AM -0800, David Daney wrote: >> >> I thought all CPUs were in stop_machine() when the modifications >> were done, so that there is no issue with multi-word instruction >> patching. >> >> Am I wrong about this? >> >> So really I think you can do two NOP just as easily. > > The problem with double NOPs is that it can only work if there's no > problem executing one nop and a non NOP. Which I think is an issue here. > > > If you have something like: > > bl _mcount > addiu sp,sp,-8 > > And you convert that to: > > nop > nop > > Now if you convert that back to: > > bl ftrace_caller > addiu sp,sp,-8 > > then you can have an issue if the task was preempted after that first > nop. Because stop_machine() doesn't wait for tasks to exit kernel space. > If you have a CONFIG_PREEMPT kernel, a task can be sleeping anywhere. > Thus you have a task execute the first nop, get preempted. You update > the code to be: Thanks for the explanation Steven. This is the part I was missing. Given all of this, I think the most expedient course for the short term is to use the branch-likely-false trick. Although the performance will probably not be great, I think it is probably race free. In the longer term... > > bl ftrace_caller > addiu sp,sp,-8 > > When that task gets scheduled back in, it will act like it just > executed: > > nop > addiu sp,sp,-8 > > Which is the problem you're trying to solve in the first place. > > Now that said, There's no reason we need that addiu sp,sp,-8 there. > That's just what the mips defined mcount requires. But as you can see > above, with dynamic ftrace, the defined mcount is only called at boot > up, and never again. That means at boot up you can convert to: > > nop > nop > > and then when you enable tracing just convert it to: > > bl ftrace_caller > nop > > There's nothing that states what the ftrace caller must be. We can have > it do a proper stack update. That is, only at boot up do we need to > handle the defined mcount. After that, those instructions are just place > holders for our own algorithms. If the addiu was needed for the defined > mcount, there's no reason to keep it for our own ftrace_caller. > > Would that work? ... either do as you suggest and dynamically change the ABI of the target function. Or add support to GCC for a better tracing ABI (as I already said we did for mips64). Thanks, David Daney From ralf@linux-mips.org Tue Jan 15 19:04:54 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 19:04:59 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:34121 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6832191Ab3AOSEylkxOW (ORCPT ); Tue, 15 Jan 2013 19:04:54 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0FI4mUH008075; Tue, 15 Jan 2013 19:04:48 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0FI4lGA008074; Tue, 15 Jan 2013 19:04:47 +0100 Date: Tue, 15 Jan 2013 19:04:46 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 04/10] MIPS: Netlogic: Split XLP L1 i-cache among threads Message-ID: <20130115180446.GA4526@linux-mips.org> References: <1358179922-26663-1-git-send-email-jchandra@broadcom.com> <1358179922-26663-5-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1358179922-26663-5-git-send-email-jchandra@broadcom.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35448 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 609 Lines: 15 On Mon, Jan 14, 2013 at 09:41:56PM +0530, Jayachandran C wrote: > Since we now use r4k cache code for Netlogic XLP, it is > better to split L1 icache among the active threads, so that > threads won't step on each other while flushing icache. > > The L1 dcache is already split among the threads in the core. It's a bit orthogonal to your patch but you may want to look at adding support for SYS_SUPPORTS_SCHED_SMT which scheduler support for SMT that is tries to schedule threads in a shared cache friendly way. See 0ab7aefc4d43a6dee26c891b41ef9c7a67d2379b [[MIPS] MT: Scheduler support for SMT]. Ralf From ddaney.cavm@gmail.com Tue Jan 15 20:41:13 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 20:41:17 +0100 (CET) Received: from mail-da0-f48.google.com ([209.85.210.48]:64543 "EHLO mail-da0-f48.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832208Ab3AOTlNDq0lB (ORCPT ); Tue, 15 Jan 2013 20:41:13 +0100 Received: by mail-da0-f48.google.com with SMTP id k18so186328dae.7 for ; Tue, 15 Jan 2013 11:41:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=AHnlWPAyEij0BReHwacG16bM6bZMCMls3qVspKTG5LY=; b=zwR8z0TKK48f7mz/Bc2nNUVY2HMQHlW4EN1ROFXB7YjrXWNP6K7BKjPwO4vaEXZify lZXrzxWs16zs+I6hItr+4TX5R9G/z/OBsjkgZzTibyrj9MC4QsVj/bBXpV4mSWvWOKmP HAdvqzvnQUo5061ahXU0WVieqkAfoePrSrGnkYJps9oGwm6RR70UvtHnsARvDeV3BkVm XsnepsLINKMvtzc2CvB9ldTwPdhwrCXwgooWnYHc2iBbk6hXCkMyv6ZtAXMQ0V0qJ8EW Lm3Ax3YYDNK/Gb3X4MeH+P3Eojjjsb9iu1yb+eVQndgmQFy3BliI9BbnXUHzfTfDKjB3 OLqg== X-Received: by 10.68.220.6 with SMTP id ps6mr267007958pbc.80.1358278866272; Tue, 15 Jan 2013 11:41:06 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id tq4sm10721802pbc.50.2013.01.15.11.41.05 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 15 Jan 2013 11:41:05 -0800 (PST) Message-ID: <50F5B0D0.9010604@gmail.com> Date: Tue, 15 Jan 2013 11:41:04 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org, cernekee@gmail.com, kevink@paralogos.com Subject: Re: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. References: <1358230420-3575-1-git-send-email-sjhill@mips.com> In-Reply-To: <1358230420-3575-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35449 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2885 Lines: 80 On 01/14/2013 10:13 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > This patch shows the use of macros in place of 'union mips_instruction' > type. Why? What are the benefits of doing this? > I converted all usages of 'j_format' and 'r_format' to show how > the code and macros could look and be defined. I have tested these > changes on big and little endian platforms. > > I want input from everyone, please!!! I want consensus on the macro > definitions, placement of parenthesis for them, spacing in the header > file, etc. This is your chance to be completely anal and have fun > arguments over how things should be. I would also like input on how > the maintainers would like the patchsets to look like. For example: > > [1/X] - Convert 'j_format' > [2/X] - Convert 'r_format' > [3/X] - Convert 'f_format' > [4/X] - Convert 'u_format' > ... > [X/X] - Remove usage of 'union mips_instruction' type completely. > > Also, I noticed 'p_format' is not used anywhere. Can we kill it? Be > picky and help with this conversion. Thanks. > > Signed-off-by: Steven J. Hill > --- > arch/mips/include/asm/inst.h | 66 +++++++++++----------------------------- > arch/mips/kernel/branch.c | 13 ++++---- > arch/mips/kernel/jump_label.c | 10 +++--- > arch/mips/kernel/kgdb.c | 10 ++---- > arch/mips/kernel/kprobes.c | 18 +++++------ > arch/mips/kernel/process.c | 10 +++--- > arch/mips/oprofile/backtrace.c | 2 +- > 7 files changed, 46 insertions(+), 83 deletions(-) > > diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h > index ab84064..856b14e 100644 > --- a/arch/mips/include/asm/inst.h > +++ b/arch/mips/include/asm/inst.h > @@ -192,15 +192,27 @@ enum lx_func { > lbx_op = 0x16, > }; > > +#define INSN_OPCODE(insn) (insn >> 26) > +#define INSN_RS(insn) ((insn >> 21) & 0x1f) > +#define INSN_RT(insn) ((insn >> 16) & 0x1f) > +#define INSN_RD(insn) ((insn >> 11) & 0x1f) > +#define INSN_RE(insn) ((insn >> 6) & 0x1f) > +#define INSN_FUNC(insn) (insn & 0x0000003f) > + > +#define J_INSN(op,target) ((op << 26) | target) What is the type of J_INSN()? What happens if target overflows into the 'op' field? > +#define J_INSN_TARGET(insn) (insn & 0x03ffffff) > +#define R_INSN(op,rs,rt,rd,re,func) ((op << 26) | (rs << 21) | \ > + (rt << 16) | (rd << 11) | \ > + (re << 6) | func) > +#define F_INSN(op,fmt,rt,rd,re,func) R_INSN(op,fmt,rt,rd,re,func) > +#define F_INSN_FMT(insn) INSN_RS(insn) > +#define U_INSN(op,rs,uimm) ((op << 26) | (rs << 21) | uimmediate) [...] > + unsigned int n_insn = insn.word; I don't like that the width of an insn is not obvious by looking at the code. Can we, assuming we merge something like this, make it something like u32, or insn_t? I'm not sure which is better. [...] David Daney From rostedt@goodmis.org Tue Jan 15 22:07:37 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 22:07:43 +0100 (CET) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:17960 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832214Ab3AOVHhlPcZq (ORCPT ); Tue, 15 Jan 2013 22:07:37 +0100 X-Authority-Analysis: v=2.0 cv=e+OEuNV/ c=1 sm=0 a=rXTBtCOcEpjy1lPqhTCpEQ==:17 a=mNMOxpOpBa8A:10 a=79wlbEtt-9EA:10 a=5SG0PmZfjMsA:10 a=Q9fys5e9bTEA:10 a=meVymXHHAAAA:8 a=pX4miy-IAAsA:10 a=2Jtw9-WZmrLkOvoCA9IA:9 a=PUjeQqilurYA:10 a=rXTBtCOcEpjy1lPqhTCpEQ==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 74.67.115.198 Received: from [74.67.115.198] ([74.67.115.198:51664] helo=[192.168.23.10]) by hrndva-oedge03.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id 42/55-25872-215C5F05; Tue, 15 Jan 2013 21:07:30 +0000 Message-ID: <1358284049.4068.21.camel@gandalf.local.home> Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing From: Steven Rostedt To: David Daney Cc: Al Cooper , ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Date: Tue, 15 Jan 2013 16:07:29 -0500 In-Reply-To: <50F59812.6040806@gmail.com> References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> <20130115034006.GA3854@home.goodmis.org> <50F59812.6040806@gmail.com> Content-Type: text/plain; charset="ISO-8859-15" X-Mailer: Evolution 3.4.4-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-archive-position: 35450 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1682 Lines: 47 On Tue, 2013-01-15 at 09:55 -0800, David Daney wrote: > > There's nothing that states what the ftrace caller must be. We can have > > it do a proper stack update. That is, only at boot up do we need to > > handle the defined mcount. After that, those instructions are just place > > holders for our own algorithms. If the addiu was needed for the defined > > mcount, there's no reason to keep it for our own ftrace_caller. > > > > Would that work? > > ... either do as you suggest and dynamically change the ABI of the > target function. We already change the ABI. We have it call ftrace_caller instead of mcount. BTW, I've just compiled with gcc 4.6.3 against mips, and I don't see the issue. I have: 0000000000000000 : 0: 03e0082d move at,ra 4: 0c000000 jal 0 4: R_MIPS_26 _mcount 4: R_MIPS_NONE *ABS* 4: R_MIPS_NONE *ABS* 8: 0000602d move t0,zero c: 2402000d li v0,13 10: 3c030000 lui v1,0x0 10: R_MIPS_HI16 mem_section 10: R_MIPS_NONE *ABS* 10: R_MIPS_NONE *ABS* 14: 000216fc dsll32 v0,v0,0x1b 18: 64630000 daddiu v1,v1,0 Is it dependent on the config? > > Or add support to GCC for a better tracing ABI (as I already said we did > for mips64). I wouldn't waste time changing gcc for this. If you're going to change gcc than please implement the -mfentry option. Look at x86_64 to understand this more. -- Steve From rostedt@goodmis.org Tue Jan 15 22:08:09 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 22:08:14 +0100 (CET) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:3350 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832213Ab3AOVIJ05GvZ (ORCPT ); Tue, 15 Jan 2013 22:08:09 +0100 X-Authority-Analysis: v=2.0 cv=T70Ovo2Q c=1 sm=0 a=rXTBtCOcEpjy1lPqhTCpEQ==:17 a=mNMOxpOpBa8A:10 a=79wlbEtt-9EA:10 a=5SG0PmZfjMsA:10 a=Q9fys5e9bTEA:10 a=meVymXHHAAAA:8 a=pX4miy-IAAsA:10 a=V_axDqPMZ-kZQ1pBRDUA:9 a=PUjeQqilurYA:10 a=jeBq3FmKZ4MA:10 a=rXTBtCOcEpjy1lPqhTCpEQ==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 74.67.115.198 Received: from [74.67.115.198] ([74.67.115.198:51672] helo=[192.168.23.10]) by hrndva-oedge02.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id 1B/82-03129-235C5F05; Tue, 15 Jan 2013 21:08:03 +0000 Message-ID: <1358284082.4068.22.camel@gandalf.local.home> Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing From: Steven Rostedt To: Alan Cooper Cc: David Daney , ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Date: Tue, 15 Jan 2013 16:08:02 -0500 In-Reply-To: References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> <20130115034006.GA3854@home.goodmis.org> Content-Type: text/plain; charset="ISO-8859-15" X-Mailer: Evolution 3.4.4-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-archive-position: 35451 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2377 Lines: 77 On Tue, 2013-01-15 at 12:53 -0500, Alan Cooper wrote: > On Mon, Jan 14, 2013 at 10:40 PM, Steven Rostedt wrote: > > On Fri, Jan 11, 2013 at 09:01:01AM -0800, David Daney wrote: > >> > >> I thought all CPUs were in stop_machine() when the modifications > >> were done, so that there is no issue with multi-word instruction > >> patching. > >> > >> Am I wrong about this? > >> > >> So really I think you can do two NOP just as easily. > > > > The problem with double NOPs is that it can only work if there's no > > problem executing one nop and a non NOP. Which I think is an issue here. > > > > > > If you have something like: > > > > bl _mcount > > addiu sp,sp,-8 > > > > And you convert that to: > > > > nop > > nop > > > > Now if you convert that back to: > > > > bl ftrace_caller > > addiu sp,sp,-8 > > > > then you can have an issue if the task was preempted after that first > > nop. Because stop_machine() doesn't wait for tasks to exit kernel space. > > If you have a CONFIG_PREEMPT kernel, a task can be sleeping anywhere. > > Thus you have a task execute the first nop, get preempted. You update > > the code to be: > > > > bl ftrace_caller > > addiu sp,sp,-8 > > > > When that task gets scheduled back in, it will act like it just > > executed: > > > > nop > > addiu sp,sp,-8 > > > > Which is the problem you're trying to solve in the first place. > > > > Now that said, There's no reason we need that addiu sp,sp,-8 there. > > That's just what the mips defined mcount requires. But as you can see > > above, with dynamic ftrace, the defined mcount is only called at boot > > up, and never again. That means at boot up you can convert to: > > > > nop > > nop > > > > and then when you enable tracing just convert it to: > > > > bl ftrace_caller > > nop > > > > There's nothing that states what the ftrace caller must be. We can have > > it do a proper stack update. That is, only at boot up do we need to > > handle the defined mcount. After that, those instructions are just place > > holders for our own algorithms. If the addiu was needed for the defined > > mcount, there's no reason to keep it for our own ftrace_caller. > > > > Would that work? > > > > -- Steve > > Lost for words? :-) -- Steve From ddaney.cavm@gmail.com Tue Jan 15 22:35:02 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 22:35:07 +0100 (CET) Received: from mail-pb0-f53.google.com ([209.85.160.53]:65210 "EHLO mail-pb0-f53.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832212Ab3AOVfCZDk7W (ORCPT ); Tue, 15 Jan 2013 22:35:02 +0100 Received: by mail-pb0-f53.google.com with SMTP id jt11so292369pbb.26 for ; Tue, 15 Jan 2013 13:34:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=nlJQmd7CWZJw6H/TnNoVPtwb3l3ULhmo/Zw8e6L2hx4=; b=kzwagbgj+s+Qu2GNlNlSlAa59yHUGnXVa77P96HIy4pPvk2e0YW0Kdk1vHoyLnHzJZ csXFcAXuQnah4zRC8QJP/GlbM+9GbcdCma7qwPrQX6WuNyLqDHZHAsLhYYu580XMXGFP oqLZhbB+72HaNt4r81kcTzLprptT4A5Lg3hBtHFPiJinDprqYXVMj0Q7YCfESqfup840 EJpve948blvC3bMlISpMAsbg3O9dnU1AoYuUpmDGxd0Z2CfngW+oqE6W2skNmQdl0Q4V 8rtZyKrcx0tgJEznIHQnyuw8wOd1ghy3wYG6BeJp5jhXfwQeMUPvQeZgATzJnuz41d98 BwXw== X-Received: by 10.68.242.134 with SMTP id wq6mr98198965pbc.146.1358285695290; Tue, 15 Jan 2013 13:34:55 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ux4sm5620409pbc.25.2013.01.15.13.34.49 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 15 Jan 2013 13:34:54 -0800 (PST) Message-ID: <50F5CB78.20800@gmail.com> Date: Tue, 15 Jan 2013 13:34:48 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Steven Rostedt CC: Al Cooper , ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> <20130115034006.GA3854@home.goodmis.org> <50F59812.6040806@gmail.com> <1358284049.4068.21.camel@gandalf.local.home> In-Reply-To: <1358284049.4068.21.camel@gandalf.local.home> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35452 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2146 Lines: 62 On 01/15/2013 01:07 PM, Steven Rostedt wrote: > On Tue, 2013-01-15 at 09:55 -0800, David Daney wrote: > >>> There's nothing that states what the ftrace caller must be. We can have >>> it do a proper stack update. That is, only at boot up do we need to >>> handle the defined mcount. After that, those instructions are just place >>> holders for our own algorithms. If the addiu was needed for the defined >>> mcount, there's no reason to keep it for our own ftrace_caller. >>> >>> Would that work? >> >> ... either do as you suggest and dynamically change the ABI of the >> target function. > > We already change the ABI. We have it call ftrace_caller instead of > mcount. > > BTW, I've just compiled with gcc 4.6.3 against mips, and I don't see the > issue. I have: > > 0000000000000000 : > 0: 03e0082d move at,ra > 4: 0c000000 jal 0 > 4: R_MIPS_26 _mcount > 4: R_MIPS_NONE *ABS* > 4: R_MIPS_NONE *ABS* > 8: 0000602d move t0,zero > c: 2402000d li v0,13 > 10: 3c030000 lui v1,0x0 > 10: R_MIPS_HI16 mem_section > 10: R_MIPS_NONE *ABS* > 10: R_MIPS_NONE *ABS* > 14: 000216fc dsll32 v0,v0,0x1b > 18: 64630000 daddiu v1,v1,0 > > Is it dependent on the config? Yes. You need to select a 32-bit kernel (which in turn may require selecting a board type that also supports it). The ABI is different for 32-bit and 64-bit _mcount. David Daney > >> >> Or add support to GCC for a better tracing ABI (as I already said we did >> for mips64). > > I wouldn't waste time changing gcc for this. If you're going to change > gcc than please implement the -mfentry option. Look at x86_64 to > understand this more. A good point. But I don't really plan on doing any work related to 32-bit mips things at this point, so any such change would have to be done by someone else. David Daney From sjhill@mips.com Tue Jan 15 23:20:24 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 23:20:29 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:51031 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832214Ab3AOWUY1G3Si convert rfc822-to-8bit (ORCPT ); Tue, 15 Jan 2013 23:20:24 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r0FMKGtE005120; Tue, 15 Jan 2013 14:20:16 -0800 X-WSS-ID: 0MGOU0P-01-0FP-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2AF7B36467A; Tue, 15 Jan 2013 14:19:37 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.02.0247.003; Tue, 15 Jan 2013 14:19:32 -0800 From: "Hill, Steven" To: David Daney CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "cernekee@gmail.com" , "kevink@paralogos.com" Subject: RE: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. Thread-Topic: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. Thread-Index: AQHN8ud/23VXA8A/UkelDJ80Zymw1ZhLUM8A//+kFDE= Date: Tue, 15 Jan 2013 22:19:31 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146C51CC@exchdb03.mips.com> References: <1358230420-3575-1-git-send-email-sjhill@mips.com>,<50F5B0D0.9010604@gmail.com> In-Reply-To: <50F5B0D0.9010604@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: JUJ4vq3SnmL5aHhi7nOVqA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35453 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1629 Lines: 34 >> This patch shows the use of macros in place of 'union mips_instruction' >> type. >> > Why? What are the benefits of doing this? > The microMIPS patches will not make it in due to the 4x size increase of this structure. Also, as was mentioned on the list previously by Ralf, it should have been done like this years back. >> + >> +#define J_INSN(op,target) ((op << 26) | target) > > What is the type of J_INSN()? What happens if target overflows into the > 'op' field? > Jump instruction, which is evident from the code removed in the patch. The macros are not done, this is a prototype and bounds checking will of course be done for the final. I mostly wanted to see if people were happy with the macro names, how they are laid out in the header file and syntactical nits. >> +#define J_INSN_TARGET(insn) (insn & 0x03ffffff) >> +#define R_INSN(op,rs,rt,rd,re,func) ((op << 26) | (rs << 21) | \ >> + (rt << 16) | (rd << 11) | \ >> + (re << 6) | func) >> +#define F_INSN(op,fmt,rt,rd,re,func) R_INSN(op,fmt,rt,rd,re,func) >> +#define F_INSN_FMT(insn) INSN_RS(insn) >> +#define U_INSN(op,rs,uimm) ((op << 26) | (rs << 21) | uimmediate) >>[...] >> + unsigned int n_insn = insn.word; > > I don't like that the width of an insn is not obvious by looking at the > code. > > Can we, assuming we merge something like this, make it something like > u32, or insn_t? I'm not sure which is better. > I was planning on making it a 'u32' but I am open to either one. Ralf, which would you prefer? -Steve From ddaney.cavm@gmail.com Tue Jan 15 23:39:25 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 23:39:32 +0100 (CET) Received: from mail-pa0-f50.google.com ([209.85.220.50]:35877 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832223Ab3AOWjZo1qbp (ORCPT ); Tue, 15 Jan 2013 23:39:25 +0100 Received: by mail-pa0-f50.google.com with SMTP id hz10so389526pad.9 for ; Tue, 15 Jan 2013 14:39:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=zgHJALfcFZ3VMS6u/qD4E25LrZoWlcPPoqT7BFz9tKg=; b=t4tB/JTeD2xi0NRX10nHGeHxfBmhSeUfwhmvlajwsA5Xpa2f3oXclqcjHEfnzRT8v1 +UDR4umSOq255441DMqL1NyTFcV/hxU1RIzMB6g2WRHkmwgPBN7ARfD88unakW0J4fb/ +y/ts7Iw6cSwf+wtCkN0/T7fFyD+jPbicbcsz8xTSx3s/e1E/O2R4PMVS0dkIieeVRVo wdUutXt2h/1Iw59+bhYYARZydXrqMP628TAmKWJYff2XinzYZ3wLnqCoCgQkcKMnxJFP uu5Agah4bSxj9Y5/SgScgx3zuMOwaF32gQnNYZbK6i66D/vG2xisZm5BISKH2W4HMZEh s1bA== X-Received: by 10.68.247.39 with SMTP id yb7mr272938105pbc.15.1358289558647; Tue, 15 Jan 2013 14:39:18 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id p10sm11602694pax.27.2013.01.15.14.39.16 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 15 Jan 2013 14:39:17 -0800 (PST) Message-ID: <50F5DA93.2080706@gmail.com> Date: Tue, 15 Jan 2013 14:39:15 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Hill, Steven" , "ralf@linux-mips.org" CC: "linux-mips@linux-mips.org" , "cernekee@gmail.com" , "kevink@paralogos.com" Subject: Re: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. References: <1358230420-3575-1-git-send-email-sjhill@mips.com>,<50F5B0D0.9010604@gmail.com> <31E06A9FC96CEC488B43B19E2957C1B801146C51CC@exchdb03.mips.com> In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B801146C51CC@exchdb03.mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35454 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2638 Lines: 74 On 01/15/2013 02:19 PM, Hill, Steven wrote: >>> This patch shows the use of macros in place of 'union mips_instruction' >>> type. >>> >> Why? What are the benefits of doing this? >> > The microMIPS patches will not make it in due to the 4x size increase of this structure. Also, as was mentioned on the list previously by Ralf, it should have been done like this years back. A matter of opinion. Bitfields have a certain elegance Personally I would investigate machine generating the file with the structure definitions. That way you could insure consistency between big and little endian versions. > >>> + >>> +#define J_INSN(op,target) ((op << 26) | target) >> >> What is the type of J_INSN()? What happens if target overflows into the >> 'op' field? >> > Jump instruction, which is evident from the code removed in the patch. The macros are not done, this is a prototype and bounds checking will of course be done for the final. I mostly wanted to see if people were happy with the macro names, how they are laid out in the header file and syntactical nits. > For me it is much more important that the data types be correct and the overflow conditions are handled (and perhaps also warned about). The order in the file I don't care about. >>> +#define J_INSN_TARGET(insn) (insn & 0x03ffffff) INSN_J_TARGET ... >>> +#define R_INSN(op,rs,rt,rd,re,func) ((op << 26) | (rs << 21) | \ >>> + (rt << 16) | (rd << 11) | \ >>> + (re << 6) | func) #define INSN_RANGE_CHECK(v, bits) ({ \ u32 val = (v); \ u32 mask = (1 << bits) - 1; \ WARN((v & mask) != v, "YOU LOSE"); \ val; \ }) #define INSN_TYPE_R(op, rs, rt, rd, re, func) \ ((INSN_RANGE_CHECK((op), 6) << 26 | \ (INSN_RANGE_CHECK((rs), 5) << 21 | \ (INSN_RANGE_CHECK((rt), 5) << 16 | \ (INSN_RANGE_CHECK((rd), 5) << 11 | \ (INSN_RANGE_CHECK((re), 5) << 6 | \ (INSN_RANGE_CHECK((func), 6)) But you cannot use that as a static initializer. >>> +#define F_INSN(op,fmt,rt,rd,re,func) R_INSN(op,fmt,rt,rd,re,func) >>> +#define F_INSN_FMT(insn) INSN_RS(insn) >>> +#define U_INSN(op,rs,uimm) ((op << 26) | (rs << 21) | uimmediate) >>> [...] >>> + unsigned int n_insn = insn.word; >> >> I don't like that the width of an insn is not obvious by looking at the >> code. >> >> Can we, assuming we merge something like this, make it something like >> u32, or insn_t? I'm not sure which is better. >> > I was planning on making it a 'u32' but I am open to either one. Ralf, which would you prefer? > > -Steve > From alcooperx@gmail.com Tue Jan 15 23:42:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Jan 2013 23:42:54 +0100 (CET) Received: from mail-qa0-f49.google.com ([209.85.216.49]:63760 "EHLO mail-qa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832213Ab3AOWms7XiZS (ORCPT ); Tue, 15 Jan 2013 23:42:48 +0100 Received: by mail-qa0-f49.google.com with SMTP id r4so676136qaq.1 for ; Tue, 15 Jan 2013 14:42:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=u6lTZo6rOHmqenH4v4yK3W42lJhYO2hlCOBbkohliQg=; b=xpxxhDKWA3ve0XGVRqTXFJwRSOk1GAjXKP70HxwAUvqEjPzUbMOU0uaGlhcveWJACp pirBeuZj1XE+1AS33WBMWjA3TZ9m0fUjXFOKcnyUGi/Ei9OW6tMUXR6zKR3DXiFJt3GQ j5oHfqaGOWc3GysqGjcNQc56TTX/bZmqj0dE4JAhL50Y/D7POwSFVesTc3QnW3NoBiiz YgPuEg4qpxc9NZxmbY5jsSQAzZMxXbadaZKY6ck5ZM2glanTwKjAsMtkDVctGSgdhoUX FUsn4rwzrxDUBZBndx95zrmRCHeQo0+Y0z8yIepVTVfcF4szqWvg6sVOn99FuMWj9luq KF8g== MIME-Version: 1.0 Received: by 10.224.207.72 with SMTP id fx8mr36948786qab.66.1358289762605; Tue, 15 Jan 2013 14:42:42 -0800 (PST) Received: by 10.49.117.161 with HTTP; Tue, 15 Jan 2013 14:42:42 -0800 (PST) In-Reply-To: <50F5CB78.20800@gmail.com> References: <1357914810-20656-1-git-send-email-alcooperx@gmail.com> <50F0454D.5060109@gmail.com> <20130115034006.GA3854@home.goodmis.org> <50F59812.6040806@gmail.com> <1358284049.4068.21.camel@gandalf.local.home> <50F5CB78.20800@gmail.com> Date: Tue, 15 Jan 2013 17:42:42 -0500 Message-ID: Subject: Re: [PATCH] mips: function tracer: Fix broken function tracing From: Alan Cooper To: David Daney Cc: Steven Rostedt , ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35455 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2794 Lines: 84 On Tue, Jan 15, 2013 at 4:34 PM, David Daney wrote: > On 01/15/2013 01:07 PM, Steven Rostedt wrote: >> >> On Tue, 2013-01-15 at 09:55 -0800, David Daney wrote: >> >>>> There's nothing that states what the ftrace caller must be. We can have >>>> it do a proper stack update. That is, only at boot up do we need to >>>> handle the defined mcount. After that, those instructions are just place >>>> holders for our own algorithms. If the addiu was needed for the defined >>>> mcount, there's no reason to keep it for our own ftrace_caller. >>>> >>>> Would that work? >>> >>> >>> ... either do as you suggest and dynamically change the ABI of the >>> target function. >> >> >> We already change the ABI. We have it call ftrace_caller instead of >> mcount. >> >> BTW, I've just compiled with gcc 4.6.3 against mips, and I don't see the >> issue. I have: >> >> 0000000000000000 : >> 0: 03e0082d move at,ra >> 4: 0c000000 jal 0 >> 4: R_MIPS_26 _mcount >> 4: R_MIPS_NONE *ABS* >> 4: R_MIPS_NONE *ABS* >> 8: 0000602d move t0,zero >> c: 2402000d li v0,13 >> 10: 3c030000 lui v1,0x0 >> 10: R_MIPS_HI16 mem_section >> 10: R_MIPS_NONE *ABS* >> 10: R_MIPS_NONE *ABS* >> 14: 000216fc dsll32 v0,v0,0x1b >> 18: 64630000 daddiu v1,v1,0 >> >> Is it dependent on the config? > > > Yes. > > You need to select a 32-bit kernel (which in turn may require selecting a > board type that also supports it). > > The ABI is different for 32-bit and 64-bit _mcount. > > David Daney > Building for MIPS malta will show the problem. > > >> >>> >>> Or add support to GCC for a better tracing ABI (as I already said we did >>> for mips64). >> >> >> I wouldn't waste time changing gcc for this. If you're going to change >> gcc than please implement the -mfentry option. Look at x86_64 to >> understand this more. > > > A good point. But I don't really plan on doing any work related to 32-bit > mips things at this point, so any such change would have to be done by > someone else. > > David Daney > I love the idea of removing the useless stack adjust stuff at run time! The issue still remains for the initial writing of the 2 nops. It looks like the initial call to write the nops is done from ftrace_init which is called before SMP is up, so if I write the 2 nops via a single call to a function with interrupts disabled it should be safe. I also need to do this for modules at insmod time. This has been GREAT feedback! Thanks From thierry.reding@avionic-design.de Wed Jan 16 08:07:21 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 08:07:26 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.17.10]:56405 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832221Ab3APHHVYFFg3 (ORCPT ); Wed, 16 Jan 2013 08:07:21 +0100 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap0) with ESMTP (Nemesis) id 0Lr4CZ-1THcUi3Q5D-00eRwP; Wed, 16 Jan 2013 08:07:15 +0100 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id E762D2A2815F; Wed, 16 Jan 2013 08:07:14 +0100 (CET) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AYJp9or6CKSl; Wed, 16 Jan 2013 08:07:13 +0100 (CET) Received: from mailman.adnet.avionic-design.de (mailman.adnet.avionic-design.de [172.20.31.172]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id A70E52A28066; Wed, 16 Jan 2013 08:07:13 +0100 (CET) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) by mailman.adnet.avionic-design.de (Postfix) with ESMTP id C2E73100424; Wed, 16 Jan 2013 08:07:09 +0100 (CET) From: Thierry Reding To: Ralf Baechle Cc: Florian Fainelli , linux-mips@linux-mips.org Subject: [PATCH] MIPS: PNX8550: Fix build failures Date: Wed, 16 Jan 2013 08:07:13 +0100 Message-Id: <1358320033-30032-1-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.8.1 X-Provags-ID: V02:K0:kD7qVj8EQieDcDxTc/HJam3wEEW03PNeg4RjgMaqiwS EvtjNl4leRxZoByrfKqSCS0aBpAY/IDJI2hBPUodZyGXci3c7y K4/cWKN2OeYC/lRtkVCK7Lpdb7xFUYTjVRqkhJo4B/FpWfTJ6R ycNduMMVPNuvQt3gH6KokLVOAcRNEaArftOp+QKMC5gQLbD8IX DDToYrcG4bkJU0NicPVTLFoyHl9Yl+C0x02o67Vd1+OZ/R6JD8 Wt7W7DXgDit+jTWJHM3KiMaalIYqLEomgwT6MF/ncIaLi9ArJW w+NEFBQPXi6r1LAbAmSgrmlUsuWNB+mT9+4fCLNvrvdmnsUHK6 UaGpebHrjgYPDIFPu6Th1QiDJR2vTgGgEwmBvhmk5Nk3gFB2gS l3RK/sbb2OZQQCHs1BkdKH06RmRGXKreu7lSL+1xqzJbw5NyWt 1VOdp X-archive-position: 35456 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 841 Lines: 29 The OHCI support code fails to build because the PCI_BASE and udelay() macros which are defined in pci.h and linux/time.h respectively. Adding corresponding includes fixes these build failures. Signed-off-by: Thierry Reding --- arch/mips/pnx8550/common/platform.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/pnx8550/common/platform.c b/arch/mips/pnx8550/common/platform.c index 0a8faea..9782fde 100644 --- a/arch/mips/pnx8550/common/platform.c +++ b/arch/mips/pnx8550/common/platform.c @@ -19,10 +19,12 @@ #include #include #include +#include #include #include #include +#include #include #include -- 1.8.1 From thierry.reding@avionic-design.de Wed Jan 16 08:28:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 08:28:19 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.126.187]:64886 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6821310Ab3APH2OY1peR (ORCPT ); Wed, 16 Jan 2013 08:28:14 +0100 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu3) with ESMTP (Nemesis) id 0LzDgT-1Srk7N3Upt-014WFQ; Wed, 16 Jan 2013 08:28:08 +0100 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 3478B2A28109; Wed, 16 Jan 2013 08:28:08 +0100 (CET) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fRo54UK1HdOJ; Wed, 16 Jan 2013 08:28:07 +0100 (CET) Received: from mailman.adnet.avionic-design.de (mailman.adnet.avionic-design.de [172.20.31.172]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 35BBB2A28154; Wed, 16 Jan 2013 08:28:07 +0100 (CET) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) by mailman.adnet.avionic-design.de (Postfix) with ESMTP id 73E87100424; Wed, 16 Jan 2013 08:28:03 +0100 (CET) From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: [PATCH] MIPS: bcm47xx: Fix BCMA build failure Date: Wed, 16 Jan 2013 08:28:06 +0100 Message-Id: <1358321286-8695-1-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.8.1 X-Provags-ID: V02:K0:M7pFCoCq2kerIonxw1txCFC9Hr1ZIbB2kA7ptbgUAGu ajZIjrxz56PxHnOP3W6QnryiWGpEFXUSJYpcYsAvHpqPN+suVQ 6Ylw1tsJeCueOQUyflCHUUH10Oj4TXW7DHlV0yWK1RFWtneyEH jSoXZqx+D//xmTKYtkvoyXY6OFXux196r9fZHZDKBNfN3FBijD ntJHgT0wK4EN0f4vvtMRwAP4QvH6z6su1m6rF9Ve65czmz3r5s n2b0CzqzLIgKtrCCT5+VexNPjoVj1dakHZElgn69LYUPgYtpcJ gPua8h9UjXLiwCe6C3w4H0ixpzragqzlAmvlvhlpGU2LLzI56b oaabgQy2z719eKUl5SFun+82coHwrVkjtq2IJ7H3m01DMqGcfq dTIDjg68y67WiGLAApGzxvTnlCrLKN3D93ifF+5ffqToiHZUSr puz1c X-archive-position: 35457 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1267 Lines: 32 Enabling the BCMA driver automatically selects BCMA_DRIVER_GPIO, which in turn depends on GPIOLIB. GPIOLIB support is not enabled by default, however, so Kconfig complains about it: warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO which has unmet direct dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO which has unmet direct dependencies (SSB_POSSIBLE && SSB && GPIOLIB) warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO which has unmet direct dependencies (SSB_POSSIBLE && SSB && GPIOLIB) warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO which has unmet direct dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) This patch fixes the issue by explicitly selecting GPIOLIB if BCM47XX_BCMA is enabled. Signed-off-by: Thierry Reding --- arch/mips/bcm47xx/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig index d7af29f..0f95b5e 100644 --- a/arch/mips/bcm47xx/Kconfig +++ b/arch/mips/bcm47xx/Kconfig @@ -19,6 +19,7 @@ config BCM47XX_SSB config BCM47XX_BCMA bool "BCMA Support for Broadcom BCM47XX" select SYS_HAS_CPU_MIPS32_R2 + select GPIOLIB select BCMA select BCMA_HOST_SOC select BCMA_DRIVER_MIPS -- 1.8.1 From florian@openwrt.org Wed Jan 16 10:18:19 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 10:18:20 +0100 (CET) Received: from mail-lb0-f182.google.com ([209.85.217.182]:43073 "EHLO mail-lb0-f182.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6821310Ab3APJSTsJ9vC (ORCPT ); Wed, 16 Jan 2013 10:18:19 +0100 Received: by mail-lb0-f182.google.com with SMTP id gg6so230146lbb.13 for ; Wed, 16 Jan 2013 01:18:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:message-id:date:from:organization:user-agent :mime-version:to:cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=bPjldk2Q6/TXBHs2RiufpdaPr/lVvxMzkPENjUKF/es=; b=YmTaWxAAcWcvRS9uZ0QyquNyBSn1OuVz02ZTIlaoyJpukARD9gUls+uGnsS/6pCWWL Pc8Kmw8gk1HV/N356/aBdV1YrJw0qtpga75i+TirfgdNPiAsUB5sR+yWRShfqj7dcS/d jIOnmtSdKHaQaq0nrMUitiPtT4iQIJnvTLPWCni8Qd3R1Ns2xDfJ1/Sz+Vs7TUcLdIiE E7tmbhnW+CyKu2AUY3H6+tWCG9pWa1C+K4RlAOWZid2M/6cCGCk078w9rENS01vtA0mE RW3J/Ev32WBLpHSyZ+4n+8PNJjc7i3ItScSUeub4UOnlnPRpwH6m+6J/WN1iiKinpcwG +fFw== X-Received: by 10.112.29.104 with SMTP id j8mr356181lbh.0.1358327894008; Wed, 16 Jan 2013 01:18:14 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id v7sm7728346lbj.13.2013.01.16.01.18.12 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 16 Jan 2013 01:18:13 -0800 (PST) Message-ID: <50F66FB8.7030207@openwrt.org> Date: Wed, 16 Jan 2013 10:15:36 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PNX8550: Fix build failures References: <1358320033-30032-1-git-send-email-thierry.reding@avionic-design.de> In-Reply-To: <1358320033-30032-1-git-send-email-thierry.reding@avionic-design.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35458 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1089 Lines: 34 On 01/16/2013 08:07 AM, Thierry Reding wrote: > The OHCI support code fails to build because the PCI_BASE and udelay() > macros which are defined in pci.h and linux/time.h respectively. Adding > corresponding includes fixes these build failures. > > Signed-off-by: Thierry Reding Thanks for fixing this Thierry, I completely missed that when moving the OHCI code to platform.c Acked-by: Florian Fainelli > --- > arch/mips/pnx8550/common/platform.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/mips/pnx8550/common/platform.c b/arch/mips/pnx8550/common/platform.c > index 0a8faea..9782fde 100644 > --- a/arch/mips/pnx8550/common/platform.c > +++ b/arch/mips/pnx8550/common/platform.c > @@ -19,10 +19,12 @@ > #include > #include > #include > +#include > #include > #include > > #include > +#include > #include > #include > From hauke@hauke-m.de Wed Jan 16 10:47:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 10:47:17 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:55042 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823034Ab3APJrQriM8w (ORCPT ); Wed, 16 Jan 2013 10:47:16 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id F1EC78F61; Wed, 16 Jan 2013 10:47:15 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pcC5qMX4gE7t; Wed, 16 Jan 2013 10:47:08 +0100 (CET) Received: from [IPv6:2001:470:1f0b:447:a03b:8863:ffdb:a382] (unknown [IPv6:2001:470:1f0b:447:a03b:8863:ffdb:a382]) by hauke-m.de (Postfix) with ESMTPSA id AB3628E1C; Wed, 16 Jan 2013 10:47:07 +0100 (CET) Message-ID: <50F67719.5010005@hauke-m.de> Date: Wed, 16 Jan 2013 10:47:05 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, Arend van Spriel Subject: Re: [PATCH] MIPS: bcm47xx: Fix BCMA build failure References: <1358321286-8695-1-git-send-email-thierry.reding@avionic-design.de> In-Reply-To: <1358321286-8695-1-git-send-email-thierry.reding@avionic-design.de> X-Enigmail-Version: 1.4.6 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35459 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1567 Lines: 39 On 01/16/2013 08:28 AM, Thierry Reding wrote: > Enabling the BCMA driver automatically selects BCMA_DRIVER_GPIO, which > in turn depends on GPIOLIB. GPIOLIB support is not enabled by default, > however, so Kconfig complains about it: > > warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO which has unmet direct dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) > warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO which has unmet direct dependencies (SSB_POSSIBLE && SSB && GPIOLIB) > warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO which has unmet direct dependencies (SSB_POSSIBLE && SSB && GPIOLIB) > warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO which has unmet direct dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) > > This patch fixes the issue by explicitly selecting GPIOLIB if > BCM47XX_BCMA is enabled. > > Signed-off-by: Thierry Reding Arend van Spriel already send a similar patch fixing this issue, but it was not applied yet: https://patchwork.linux-mips.org/patch/4759/ CONFIG_GPIOLIB should also be selected by CONFIG_BCM47XX_SSB. > --- > arch/mips/bcm47xx/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig > index d7af29f..0f95b5e 100644 > --- a/arch/mips/bcm47xx/Kconfig > +++ b/arch/mips/bcm47xx/Kconfig > @@ -19,6 +19,7 @@ config BCM47XX_SSB > config BCM47XX_BCMA > bool "BCMA Support for Broadcom BCM47XX" > select SYS_HAS_CPU_MIPS32_R2 > + select GPIOLIB > select BCMA > select BCMA_HOST_SOC > select BCMA_DRIVER_MIPS > From thierry.reding@avionic-design.de Wed Jan 16 10:51:26 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 10:51:28 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.17.10]:52067 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823034Ab3APJv0Z9Wlw (ORCPT ); Wed, 16 Jan 2013 10:51:26 +0100 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu0) with ESMTP (Nemesis) id 0MRQIm-1TX6Rp2kyu-00SqKL; Wed, 16 Jan 2013 10:51:17 +0100 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id EC4102A28162; Wed, 16 Jan 2013 10:51:16 +0100 (CET) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TAWXlbPpfWvR; Wed, 16 Jan 2013 10:51:15 +0100 (CET) Received: from mailman.adnet.avionic-design.de (mailman.adnet.avionic-design.de [172.20.31.172]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 4824E2A28066; Wed, 16 Jan 2013 10:51:15 +0100 (CET) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) by mailman.adnet.avionic-design.de (Postfix) with ESMTP id 6938A1003EB; Wed, 16 Jan 2013 10:51:11 +0100 (CET) Date: Wed, 16 Jan 2013 10:51:14 +0100 From: Thierry Reding To: Hauke Mehrtens Cc: Ralf Baechle , linux-mips@linux-mips.org, Arend van Spriel Subject: Re: [PATCH] MIPS: bcm47xx: Fix BCMA build failure Message-ID: <20130116095114.GC18848@avionic-0098.adnet.avionic-design.de> References: <1358321286-8695-1-git-send-email-thierry.reding@avionic-design.de> <50F67719.5010005@hauke-m.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="dkEUBIird37B8yKS" Content-Disposition: inline In-Reply-To: <50F67719.5010005@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:gZfzY3MOLKk0mTW/Jp6S5O8OGup52RgaFFVrvvFim4j 3nMi0CubbCB6ZLXwcgxZBD/ZwbtGbMeNATRZAQ6KPvU8B5LqI+ Og5151TNjtGjalbJ71bC5Gijfl4uNZ0Zl/dL3kQFJgafjYrpdU MhY7TRK+FPV4+XRBH9iWlH2JDxyYpeXVNPuGbGmVysP+F3wgWN 6GLfLU/pxVIJywT2VnXcvfVxYc4X5ioa3hQOCG05pBXavYFgpM /4srPIH3nSYiPcLUZY9FqY4M8frWd0ufC9CGPwfPLja++3+7Y1 onUpnEp5mAPyk4oyj0dxc35HLRXWO+onn6g28rp7AckqnICbxn KBMhu/8xTjLGkbsXyEyXKwBJPkpsWESkVU0SdY0+otoZB9UzER ndaMJ7NwDyLg9zP1Gt3qw7tAtswWcjTHMQ= X-archive-position: 35460 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2330 Lines: 58 --dkEUBIird37B8yKS Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jan 16, 2013 at 10:47:05AM +0100, Hauke Mehrtens wrote: > On 01/16/2013 08:28 AM, Thierry Reding wrote: > > Enabling the BCMA driver automatically selects BCMA_DRIVER_GPIO, which > > in turn depends on GPIOLIB. GPIOLIB support is not enabled by default, > > however, so Kconfig complains about it: > >=20 > > warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO which has unmet direc= t dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) > > warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO which has unmet direct = dependencies (SSB_POSSIBLE && SSB && GPIOLIB) > > warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO which has unmet direct = dependencies (SSB_POSSIBLE && SSB && GPIOLIB) > > warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO which has unmet direc= t dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) > >=20 > > This patch fixes the issue by explicitly selecting GPIOLIB if > > BCM47XX_BCMA is enabled. > >=20 > > Signed-off-by: Thierry Reding >=20 > Arend van Spriel already send a similar patch fixing this issue, but it > was not applied yet: > https://patchwork.linux-mips.org/patch/4759/ >=20 > CONFIG_GPIOLIB should also be selected by CONFIG_BCM47XX_SSB. Okay, great. I wasn't aware of it, sorry for the noise. Thierry --dkEUBIird37B8yKS Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQ9ngSAAoJEN0jrNd/PrOhtxoQALCFlWIKnW7TUXuLQRNjs70K CkjcX6qrAAsS7lUlP+pE/6JMi0xYwpKP/VfEA+uZh0uU4UA0e0mZpteOcjuA/o/S +zH/hcoWJ7mmC1E/IFD5sSchlsAdsp0qHcITBV9SpLXBM6omh7YJrA3OV+L2s6SI k5tF6KM4PT4dZRDdgTcC1WSxClvyEXOHcQ/wAU7c5WRA1HyOfskC5OO4T33Vvixd lgAlWoaTn27pM9q272FvAJNGfF/OZKwopXt8noaWvhETJI/Iid8+7dE0/4T+bM3F 3Asf2fB+BnuRpfy4VwylNIJF60dl/uWfsm8qMsiZvdAWNBIplyNqPR5UXLjGkSNz /fQMmQ5aMvMFkiEPYrOkRUkF9Opeevr7DI76h+5KjZ2TQJWmzalP/7UrihMRCh7q zoLAlyct1sHZ3YJ6OwxtVJusiSnmG3233SktiLQ+O0mHdLm8VFlj3Kf64yndGvbp uqg4HBpub6MxxeXEAjkuQls0cIf7e+XXtXNApxBe1QbBtUUXBCn7eVZWZGZnM2Tw ox1hj0D9C90yHnI+lRUlm2sAAuXuUXiT6pGVU/+jGSdy7zqCnptAsxz9iNHEPIC0 wzXggVb1FFATjvoBfgECIGVsy/PJlkPD34c/WeeVc3PTmIbgHEwN2oHmoVv46J3v j5N8CvkXm10V6Cyz82Zv =EWfH -----END PGP SIGNATURE----- --dkEUBIird37B8yKS-- From geert@linux-m68k.org Wed Jan 16 10:51:53 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 10:51:54 +0100 (CET) Received: from mail-vb0-f51.google.com ([209.85.212.51]:41310 "EHLO mail-vb0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823034Ab3APJvxu4q8D (ORCPT ); Wed, 16 Jan 2013 10:51:53 +0100 Received: by mail-vb0-f51.google.com with SMTP id fq11so1097357vbb.24 for ; Wed, 16 Jan 2013 01:51:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=1shXhpzl2Ee/qd2brAzr2dBY68W5bdvYRXsoD/ACQOo=; b=mU0+lWBMhha4gRozGTX6KdkUiN1v7RJ+rd5M1lL3WqtB1IoweRl7BHOeSnzUM10O9e ZuWKRMHveUhTQvUtea9q0Hifib1pIq+shQHm0OtqaBfkL6H4OyK+U+n0BRqTCKWukNxX sotYyDCfrpx/UqzjSUr2ocGi1B+fjzI//0iwSg37JuylCfai6hJLosNVftXQw7Lsqlvu 1vqx+cC9P2ke4ttBc/PJ0DWDyYCURS4b+31v+WWa6H62gHmfiRp8Iq5vbdSdGJsMcJXF ZAeLafNqJaO/8geq0vKgf/KMP98YjOGkvUV5q67LjjxfFVyQ5tgK1nTXzBXMezKxRFvS 2XhQ== MIME-Version: 1.0 X-Received: by 10.220.231.138 with SMTP id jq10mr456758vcb.29.1358329907501; Wed, 16 Jan 2013 01:51:47 -0800 (PST) Received: by 10.58.227.168 with HTTP; Wed, 16 Jan 2013 01:51:47 -0800 (PST) In-Reply-To: <1358320033-30032-1-git-send-email-thierry.reding@avionic-design.de> References: <1358320033-30032-1-git-send-email-thierry.reding@avionic-design.de> Date: Wed, 16 Jan 2013 10:51:47 +0100 X-Google-Sender-Auth: uYOHyEzO4lfbyWdXJVxmPZ6t5Z0 Message-ID: Subject: Re: [PATCH] MIPS: PNX8550: Fix build failures From: Geert Uytterhoeven To: Thierry Reding Cc: Ralf Baechle , Florian Fainelli , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 35461 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 629 Lines: 19 On Wed, Jan 16, 2013 at 8:07 AM, Thierry Reding wrote: > The OHCI support code fails to build because the PCI_BASE and udelay() > macros which are defined in pci.h and linux/time.h respectively. Adding > +#include time.h or delay.h? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From thierry.reding@avionic-design.de Wed Jan 16 11:04:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 11:04:11 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.126.187]:56009 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817128Ab3APKEGfT-X3 (ORCPT ); Wed, 16 Jan 2013 11:04:06 +0100 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0MIjEq-1Txbhm10Ce-002gOT; Wed, 16 Jan 2013 11:03:58 +0100 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 28EBF2A28162; Wed, 16 Jan 2013 11:03:57 +0100 (CET) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4rD0Ku2GQvA5; Wed, 16 Jan 2013 11:03:53 +0100 (CET) Received: from mailman.adnet.avionic-design.de (mailman.adnet.avionic-design.de [172.20.31.172]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id E87422A28066; Wed, 16 Jan 2013 11:03:52 +0100 (CET) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) by mailman.adnet.avionic-design.de (Postfix) with ESMTP id 1A4E51003EB; Wed, 16 Jan 2013 11:03:49 +0100 (CET) Date: Wed, 16 Jan 2013 11:03:52 +0100 From: Thierry Reding To: Geert Uytterhoeven Cc: Ralf Baechle , Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PNX8550: Fix build failures Message-ID: <20130116100352.GB13628@avionic-0098.adnet.avionic-design.de> References: <1358320033-30032-1-git-send-email-thierry.reding@avionic-design.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="QTprm0S8XgL7H0Dt" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:7NlDnT+FFyryV0RqUzSbx+qU5noTe61xLmSdj+YbxOK t+MrbwnLN9/DW47tdrqOwniJrp5zc9bZ6PyZof9crqB+DZtkr+ 5Cdjc6GPjEj+PF8lV3METfJqUQmGiZCHRmTrRPykyYwc5jFYNN Y4L5atDGfYwWNlyjN5Q9MTptdrT3dgFSnOKIk+i0sZ1QB9ofjf epIzv4MmuX+7kAE5WCqY5fSc6Iu2qsIN2op2IAT2zBjhJbq0hd NIvch3sX0X9ePgTQF5Y9mm2m38kuX2iGjm197K0C8PQiTJxwmH r7roHJH99XJ76ZlSIfX5GrB7knFxZiSbDvgOgutqjZ1KT+aMhK qbhQny3oDAKfbZAeqHw92dIw87T/nhfRXF2GxxLijxeFkodc4X aYEXEe5jzN8nsCnORfNgPGTFbN/nU0+dtQ= X-archive-position: 35462 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1526 Lines: 43 --QTprm0S8XgL7H0Dt Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jan 16, 2013 at 10:51:47AM +0100, Geert Uytterhoeven wrote: > On Wed, Jan 16, 2013 at 8:07 AM, Thierry Reding > wrote: > > The OHCI support code fails to build because the PCI_BASE and udelay() > > macros which are defined in pci.h and linux/time.h respectively. Adding >=20 > > +#include >=20 > time.h or delay.h? That'd be delay.h. Can this be fixed up when the patch is committed or shall I resend? Thierry --QTprm0S8XgL7H0Dt Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQ9nsIAAoJEN0jrNd/PrOhHn0P/1nppxrNzncmsmIigCENM2aW ahvyDSfGpA9zbCpz0d2lfGDCD4EiBmn+a765GqvUAuSrYWsnHBzT8fp13/sby1/m EUDBgbHQh9DDe0bNFPkjFYzgKYZ9P1P9pc5F+41E21k5uw3vHo+Ni9wKhi+oJPsK gLUoASG6KMwGjMhtQ40XeiuPqGn0cb/4vZykG9sAS0E8AQdf4pY0l7R7W2qhl8TO mc+GYd7KGuKObxQ0n4715AWh0m/upovTkp0sxWMBaVm2VgD9qwX3CPj7Hk4r7ii9 MFsqWpeJ26iF33wkpFoX0NdLTlC4XkwPAW6o8aOT8ZkLaOwm7Ul3760YJx/+gwOc LnBdtofLFxTGbqYdurMaS/xUVbSRiV1cDwrTIcfDtrfEJO6P+Vmox9s+qL76hBQv uJ8ZxdMZQMH8MU6ourpDan+JAXTlVkk0gvSuFWuMOVsmZGMmCkSVjjPHT6ItddNS kcTKzITNbec5Q8eSqvhIs/eWUKth6XH0Oz7QAt6bT+CA6qoxM7qoSXxxweFt3QQ6 JXJxdLOU8fHwwLyYJXsZHeeSLXQaiFYNfvVHfV8LPpwqNEwmqkq0A5lFtnLLc+EW OWSbab8aNxnV6c31VQNsweeqV9Xi4cIs6I6dZL+pIT5sbrzsKJVRKLtj/zC/HuAa /L6NelrJKPhJ0bCbT7ES =DQhD -----END PGP SIGNATURE----- --QTprm0S8XgL7H0Dt-- From ralf@linux-mips.org Wed Jan 16 11:30:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 11:30:28 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:39166 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6821310Ab3APKa1b0Tsg (ORCPT ); Wed, 16 Jan 2013 11:30:27 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0GAUP8Z010250; Wed, 16 Jan 2013 11:30:25 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0GAUOOm010249; Wed, 16 Jan 2013 11:30:24 +0100 Date: Wed, 16 Jan 2013 11:30:24 +0100 From: Ralf Baechle To: Cong Ding Cc: David Howells , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: kernel/vpe.c: fix wrong KERN_WARNING message Message-ID: <20130116103024.GA26569@linux-mips.org> References: <1358184212-30381-1-git-send-email-dinggnu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1358184212-30381-1-git-send-email-dinggnu@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35463 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 26 Lines: 4 Thanks, applied. Ralf From ralf@linux-mips.org Wed Jan 16 11:58:03 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 11:58:04 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:39402 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6821310Ab3APK6DUVJBX (ORCPT ); Wed, 16 Jan 2013 11:58:03 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0GAw0iV011608; Wed, 16 Jan 2013 11:58:00 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0GAvvvm011607; Wed, 16 Jan 2013 11:57:57 +0100 Date: Wed, 16 Jan 2013 11:57:57 +0100 From: Ralf Baechle To: Cong Ding Cc: Jim Quinlan , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Subject: Re: [PATCH] mpis: cavium-octeon/executive/cvmx-l2c.c: fix uninitialized variable Message-ID: <20130116105757.GB26569@linux-mips.org> References: <1358200025-15994-1-git-send-email-dinggnu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1358200025-15994-1-git-send-email-dinggnu@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35464 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1378 Lines: 42 On Mon, Jan 14, 2013 at 10:47:03PM +0100, Cong Ding wrote: > the variable dummy is used without initialization. Interesting - I wonder how you found this one. My compiler (gcc 4.7) doesn't warn about this one. Nor does gcc notice that the whole summing up business is wasted efford. So here's my counter proposal. It works because ptr is a volatile pointer so the compiler will always dereference it even if the returned value is not being used. The resulting code is a bit smaller. Ralf Signed-off-by: Ralf Baechle arch/mips/cavium-octeon/executive/cvmx-l2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c index 9f883bf..ec3e059 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c @@ -286,7 +286,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter) static void fault_in(uint64_t addr, int len) { volatile char *ptr; - volatile char dummy; + /* * Adjust addr and length so we get all cache lines even for * small ranges spanning two cache lines. @@ -300,7 +300,7 @@ static void fault_in(uint64_t addr, int len) */ CVMX_DCACHE_INVALIDATE; while (len > 0) { - dummy += *ptr; + *ptr; len -= CVMX_CACHE_LINE_SIZE; ptr += CVMX_CACHE_LINE_SIZE; } From jchandra@broadcom.com Wed Jan 16 13:10:10 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 13:10:16 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:2002 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823001Ab3APMKK7XMR3 (ORCPT ); Wed, 16 Jan 2013 13:10:10 +0100 Received: from [10.9.208.53] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 16 Jan 2013 04:04:40 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by irvexchcas06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server id 14.1.355.2; Wed, 16 Jan 2013 04:09:53 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 34D0040FE3; Wed, 16 Jan 2013 04:09:51 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 03/10] MIPS: PCI: Byteswap not needed in little-endian mode Date: Wed, 16 Jan 2013 17:42:40 +0530 Message-ID: <1358338361-15499-1-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358231908-14458-2-git-send-email-jchandra@broadcom.com> References: <1358231908-14458-2-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CE848D23Q43158774-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35465 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1736 Lines: 58 Rename function xlp_enable_pci_bswap() to xlp_config_pci_bswap(), which is a better description for its functionality. When compiled in big-endian mode, xlp_config_pci_bswap() will configure the PCIe links to byteswap. In little-endian mode, no swap configuration is needed for the PCIe controller, and the function is empty. Signed-off-by: Jayachandran C --- [ New version with updated #ifdef style ] arch/mips/pci/pci-xlp.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 140557a..5077148 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -191,7 +191,13 @@ int pcibios_plat_dev_init(struct pci_dev *dev) return 0; } -static int xlp_enable_pci_bswap(void) +/* + * If big-endian, enable hardware byteswap on the PCIe bridges. + * This will make both the SoC and PCIe devices behave consistently with + * readl/writel. + */ +#ifdef __BIG_ENDIAN +static void xlp_config_pci_bswap(void) { uint64_t pciebase, sysbase; int node, i; @@ -222,8 +228,11 @@ static int xlp_enable_pci_bswap(void) reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); } - return 0; } +#else +/* Swap configuration not needed in little-endian mode */ +static inline void xlp_config_pci_bswap(void) {} +#endif /* __BIG_ENDIAN */ static int __init pcibios_init(void) { @@ -235,7 +244,7 @@ static int __init pcibios_init(void) ioport_resource.start = 0; ioport_resource.end = ~0; - xlp_enable_pci_bswap(); + xlp_config_pci_bswap(); set_io_port_base(CKSEG1); nlm_pci_controller.io_map_base = CKSEG1; -- 1.7.9.5 From jchandra@broadcom.com Wed Jan 16 13:10:11 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 13:10:33 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:2009 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832211Ab3APMKLnn9EW (ORCPT ); Wed, 16 Jan 2013 13:10:11 +0100 Received: from [10.9.208.53] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 16 Jan 2013 04:04:42 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by irvexchcas06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server id 14.1.355.2; Wed, 16 Jan 2013 04:09:54 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 9014740FE3; Wed, 16 Jan 2013 04:09:53 -0800 (PST) From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 10/10] MIPS: PCI: Multi-node PCI support for Netlogic XLP Date: Wed, 16 Jan 2013 17:42:41 +0530 Message-ID: <1358338361-15499-2-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358338361-15499-1-git-send-email-jchandra@broadcom.com> References: <1358231908-14458-2-git-send-email-jchandra@broadcom.com> <1358338361-15499-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7CE848D03Q43158780-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35466 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5336 Lines: 178 On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCIe on all the nodes. Signed-off-by: Jayachandran C --- [ Updated for the new PATCH 3/10] arch/mips/pci/pci-xlp.c | 109 ++++++++++++++++++++++++++++------------------- 1 file changed, 66 insertions(+), 43 deletions(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index fbf001a..dd2d3eb 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -46,6 +46,7 @@ #include #include +#include #include #include @@ -161,32 +162,38 @@ struct pci_controller nlm_pci_controller = { .io_offset = 0x00000000UL, }; -static int get_irq_vector(const struct pci_dev *dev) +static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) { - /* - * For XLP PCIe, there is an IRQ per Link, find out which - * link the device is on to assign interrupts - */ - if (dev->bus->self == NULL) - return 0; + struct pci_bus *bus, *p; - switch (dev->bus->self->devfn) { - case 0x8: - return PIC_PCIE_LINK_0_IRQ; - case 0x9: - return PIC_PCIE_LINK_1_IRQ; - case 0xa: - return PIC_PCIE_LINK_2_IRQ; - case 0xb: - return PIC_PCIE_LINK_3_IRQ; - } - WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); - return 0; + /* Find the bridge on bus 0 */ + bus = dev->bus; + for (p = bus->parent; p && p->number != 0; p = p->parent) + bus = p; + + return p ? bus->self : NULL; +} + +static inline int nlm_pci_link_to_irq(int link) +{ + return PIC_PCIE_LINK_0_IRQ + link; } int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - return get_irq_vector(dev); + struct pci_dev *lnkdev; + int lnkslot, lnkfunc; + + /* + * For XLP PCIe, there is an IRQ per Link, find out which + * link the device is on to assign interrupts + */ + lnkdev = xlp_get_pcie_link(dev); + if (lnkdev == NULL) + return 0; + lnkfunc = PCI_FUNC(lnkdev->devfn); + lnkslot = PCI_SLOT(lnkdev->devfn); + return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc)); } /* Do platform specific device initialization at pci_enable_device() time */ @@ -201,45 +208,42 @@ int pcibios_plat_dev_init(struct pci_dev *dev) * readl/writel. */ #ifdef __BIG_ENDIAN -static void xlp_config_pci_bswap(void) +static void xlp_config_pci_bswap(int node, int link) { - uint64_t pciebase, sysbase; - int node, i; + uint64_t nbubase, lnkbase; u32 reg; - /* Chip-0 so node set to 0 */ - node = 0; - sysbase = nlm_get_bridge_regbase(node); + nbubase = nlm_get_bridge_regbase(node); + lnkbase = nlm_get_pcie_base(node, link); + /* * Enable byte swap in hardware. Program each link's PCIe SWAP regions * from the link's address ranges. */ - for (i = 0; i < 4; i++) { - pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i)); - if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) - continue; + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, - reg | 0xfff); + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); - - reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); - } + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); } #else /* Swap configuration not needed in little-endian mode */ -static inline void xlp_config_pci_bswap(void) {} +static inline void xlp_config_pci_bswap(int node, int link) {} #endif /* __BIG_ENDIAN */ static int __init pcibios_init(void) { + struct nlm_soc_info *nodep; + uint64_t pciebase; + int link, n; + u32 reg; + /* Firmware assigns PCI resources */ pci_set_flags(PCI_PROBE_ONLY); pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); @@ -248,7 +252,26 @@ static int __init pcibios_init(void) ioport_resource.start = 0; ioport_resource.end = ~0; - xlp_config_pci_bswap(); + for (n = 0; n < NLM_NR_NODES; n++) { + nodep = nlm_get_node(n); + if (!nodep->coremask) + continue; /* node does not exist */ + + for (link = 0; link < 4; link++) { + pciebase = nlm_get_pcie_base(n, link); + if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) + continue; + xlp_config_pci_bswap(n, link); + + /* put in intpin and irq - u-boot does not */ + reg = nlm_read_pci_reg(pciebase, 0xf); + reg &= ~0x1fu; + reg |= (1 << 8) | nlm_pci_link_to_irq(link); + nlm_write_pci_reg(pciebase, 0xf, reg); + pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); + } + } + set_io_port_base(CKSEG1); nlm_pci_controller.io_map_base = CKSEG1; -- 1.7.9.5 From ralf@linux-mips.org Wed Jan 16 15:16:22 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 15:16:28 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40351 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6832228Ab3APOQW7PiFq (ORCPT ); Wed, 16 Jan 2013 15:16:22 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0GEGKNa021184; Wed, 16 Jan 2013 15:16:20 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0GEGI6f021183; Wed, 16 Jan 2013 15:16:18 +0100 Date: Wed, 16 Jan 2013 15:16:18 +0100 From: Ralf Baechle To: David Daney Cc: "Hill, Steven" , "linux-mips@linux-mips.org" , "cernekee@gmail.com" , "kevink@paralogos.com" Subject: Re: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. Message-ID: <20130116141618.GC26569@linux-mips.org> References: <1358230420-3575-1-git-send-email-sjhill@mips.com> <50F5B0D0.9010604@gmail.com> <31E06A9FC96CEC488B43B19E2957C1B801146C51CC@exchdb03.mips.com> <50F5DA93.2080706@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50F5DA93.2080706@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35467 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6818 Lines: 267 On Tue, Jan 15, 2013 at 02:39:15PM -0800, David Daney wrote: So this should be fairly readable, far less code and in especially no more variants for endianess except a single simple macro. What do you think? Ralf Signed-off-by: Ralf Baechle arch/mips/include/asm/inst.h | 227 +++++++++++++++++-------------------------- 1 file changed, 87 insertions(+), 140 deletions(-) diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index ab84064..442e7a4 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -196,154 +196,100 @@ enum lx_func { * Damn ... bitfields depend from byteorder :-( */ #ifdef __MIPSEB__ -struct j_format { /* Jump format */ - unsigned int opcode : 6; - unsigned int target : 26; -}; - -struct i_format { /* Immediate format (addi, lw, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - signed int simmediate : 16; -}; - -struct u_format { /* Unsigned immediate format (ori, xori, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int uimmediate : 16; -}; - -struct c_format { /* Cache (>= R6000) format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int c_op : 3; - unsigned int cache : 2; - unsigned int simmediate : 16; -}; - -struct r_format { /* Register format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct f_format { /* FPU register format */ - unsigned int opcode : 6; - unsigned int : 1; - unsigned int fmt : 4; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct ma_format { /* FPU multiply and add format (MIPS IV) */ - unsigned int opcode : 6; - unsigned int fr : 5; - unsigned int ft : 5; - unsigned int fs : 5; - unsigned int fd : 5; - unsigned int func : 4; - unsigned int fmt : 2; -}; - -struct b_format { /* BREAK and SYSCALL */ - unsigned int opcode:6; - unsigned int code:20; - unsigned int func:6; -}; +#define BITFIELD_FIELD(field, more) \ + field; \ + more #elif defined(__MIPSEL__) -struct j_format { /* Jump format */ - unsigned int target : 26; - unsigned int opcode : 6; -}; - -struct i_format { /* Immediate format */ - signed int simmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct u_format { /* Unsigned immediate format */ - unsigned int uimmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct c_format { /* Cache (>= R6000) format */ - unsigned int simmediate : 16; - unsigned int cache : 2; - unsigned int c_op : 3; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct r_format { /* Register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct f_format { /* FPU register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int fmt : 4; - unsigned int : 1; - unsigned int opcode : 6; -}; - -struct ma_format { /* FPU multiply and add format (MIPS IV) */ - unsigned int fmt : 2; - unsigned int func : 4; - unsigned int fd : 5; - unsigned int fs : 5; - unsigned int ft : 5; - unsigned int fr : 5; - unsigned int opcode : 6; -}; - -struct b_format { /* BREAK and SYSCALL */ - unsigned int func:6; - unsigned int code:20; - unsigned int opcode:6; -}; +#define BITFIELD_FIELD(field, more) \ + more \ + field; #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" #endif +struct j_format { + BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ + BITFIELD_FIELD(unsigned int target : 26, + )) +}; + +struct i_format { /* signed immediate format */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rs : 5, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(signed int simmediate : 16, + )))) +}; + +struct u_format { /* unsigned immediate format */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rs : 5, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(unsigned int uimmediate : 16, + )))) +}; + +struct c_format { /* Cache (>= R6000) format */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rs : 5, + BITFIELD_FIELD(unsigned int c_op : 3, + BITFIELD_FIELD(unsigned int cache : 2, + BITFIELD_FIELD(unsigned int simmediate : 16, + ))))) +}; + +struct r_format { /* Register format */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rs : 5, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(unsigned int rd : 5, + BITFIELD_FIELD(unsigned int re : 5, + BITFIELD_FIELD(unsigned int func : 6, + )))))) +}; + +struct p_format { /* Performance counter format (R10000) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rs : 5, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(unsigned int rd : 5, + BITFIELD_FIELD(unsigned int re : 5, + BITFIELD_FIELD(unsigned int func : 6, + )))))) +}; + +struct f_format { /* FPU register format */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int : 1, + BITFIELD_FIELD(unsigned int fmt : 4, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(unsigned int rd : 5, + BITFIELD_FIELD(unsigned int re : 5, + BITFIELD_FIELD(unsigned int func : 6, + ))))))) +}; + +struct ma_format { /* FPU multiply and add format (MIPS IV) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int fr : 5, + BITFIELD_FIELD(unsigned int ft : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int fd : 5, + BITFIELD_FIELD(unsigned int func : 4, + BITFIELD_FIELD(unsigned int fmt : 2, + ))))))) +}; + +struct b_format { /* BREAK and SYSCALL */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int code : 20, + BITFIELD_FIELD(unsigned int func : 6, + ))) +}; + union mips_instruction { unsigned int word; unsigned short halfword[2]; @@ -353,6 +299,7 @@ union mips_instruction { struct u_format u_format; struct c_format c_format; struct r_format r_format; + struct p_format p_format; struct f_format f_format; struct ma_format ma_format; struct b_format b_format; From ralf@linux-mips.org Wed Jan 16 15:50:19 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 15:50:20 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40618 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6832230Ab3APOuTnbAxh (ORCPT ); Wed, 16 Jan 2013 15:50:19 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0GEo7qT022841; Wed, 16 Jan 2013 15:50:07 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0GEo05T022821; Wed, 16 Jan 2013 15:50:00 +0100 Date: Wed, 16 Jan 2013 15:50:00 +0100 From: Ralf Baechle To: Arend van Spriel Cc: Sergei Shtylyov , linux-mips@linux-mips.org, Hauke Mehrtens Subject: Re: [PATCH] mips: bcm47xx: select GPIOLIB for BCMA on bcm47xx platform Message-ID: <20130116145000.GD26569@linux-mips.org> References: <1357323005-28008-1-git-send-email-arend@broadcom.com> <50E80F78.9030901@mvista.com> <50E9E914.9030900@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50E9E914.9030900@broadcom.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35468 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 590 Lines: 21 On Sun, Jan 06, 2013 at 10:13:56PM +0100, Arend van Spriel wrote: > > This change doesn';t seem to be documented in your changelog. Maybe > > it's worth another patch? > > > > WBR, Sergei > > > > Very observant. ;-) Yes. After fixing the other ones I got a warning on > that one. I could resubmit the change with a more generic description or > split it up as you suggest. > > Ralf, > > Please advice. For simplicity's sake I'm going to split this myself BUT putting changes that are not explained in changelog comments is a good way to get your dear maintainer grumpy :) Ralf From herton.krzesinski@canonical.com Wed Jan 16 17:04:30 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 17:04:32 +0100 (CET) Received: from youngberry.canonical.com ([91.189.89.112]:50508 "EHLO youngberry.canonical.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832234Ab3APQEangn4y (ORCPT ); Wed, 16 Jan 2013 17:04:30 +0100 Received: from [177.132.109.150] (helo=canonical.com) by youngberry.canonical.com with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1TvVTT-0006po-BK; Wed, 16 Jan 2013 16:04:24 +0000 From: Herton Ronaldo Krzesinski To: linux-kernel@vger.kernel.org, stable@vger.kernel.org, kernel-team@lists.ubuntu.com Cc: Huacai Chen , Hongliang Tao , Hua Yan , Yong Zhang , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Ralf Baechle , Herton Ronaldo Krzesinski Subject: [PATCH 109/222] MIPS: Fix poweroff failure when HOTPLUG_CPU configured. Date: Wed, 16 Jan 2013 13:55:09 -0200 Message-Id: <1358351822-7675-110-git-send-email-herton.krzesinski@canonical.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358351822-7675-1-git-send-email-herton.krzesinski@canonical.com> References: <1358351822-7675-1-git-send-email-herton.krzesinski@canonical.com> X-Extended-Stable: 3.5 X-archive-position: 35469 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herton.krzesinski@canonical.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1679 Lines: 48 3.5.7.3 -stable review patch. If anyone has any objections, please let me know. ------------------ From: Huacai Chen commit 8add1ecb81f541ef2fcb0b85a5470ad9ecfb4a84 upstream. When poweroff machine, kernel_power_off() call disable_nonboot_cpus(). And if we have HOTPLUG_CPU configured, disable_nonboot_cpus() is not an empty function but attempt to actually disable the nonboot cpus. Since system state is SYSTEM_POWER_OFF, play_dead() won't be called and thus disable_nonboot_cpus() hangs. Therefore, we make this patch to avoid poweroff failure. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan Cc: Yong Zhang Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Fuxin Zhang Cc: Zhangjin Wu Patchwork: https://patchwork.linux-mips.org/patch/4211/ Signed-off-by: Ralf Baechle Signed-off-by: Herton Ronaldo Krzesinski --- arch/mips/kernel/process.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index e9a5fd7..69b17a9 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -72,9 +72,7 @@ void __noreturn cpu_idle(void) } } #ifdef CONFIG_HOTPLUG_CPU - if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map) && - (system_state == SYSTEM_RUNNING || - system_state == SYSTEM_BOOTING)) + if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map)) play_dead(); #endif rcu_idle_exit(); -- 1.7.9.5 From ddaney@caviumnetworks.com Wed Jan 16 18:57:10 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 18:57:11 +0100 (CET) Received: from co9ehsobe003.messaging.microsoft.com ([207.46.163.26]:38944 "EHLO co9outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832231Ab3APR5KCYuq3 (ORCPT ); Wed, 16 Jan 2013 18:57:10 +0100 Received: from mail143-co9-R.bigfish.com (10.236.132.246) by CO9EHSOBE025.bigfish.com (10.236.130.88) with Microsoft SMTP Server id 14.1.225.23; Wed, 16 Jan 2013 17:57:01 +0000 Received: from mail143-co9 (localhost [127.0.0.1]) by mail143-co9-R.bigfish.com (Postfix) with ESMTP id 3498B1E01DB; Wed, 16 Jan 2013 17:57:00 +0000 (UTC) X-Forefront-Antispam-Report: CIP:132.245.1.197;KIP:(null);UIP:(null);IPV:NLI;H:BLUPRD0712HT002.namprd07.prod.outlook.com;RD:none;EFVD:NLI X-SpamScore: -4 X-BigFish: PS-4(zzbb2dI98dI9371I1432Izz1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275dhz2dh2a8h668h839h947hd25he5bhf0ah1288h12a5h12a9h12bdh137ah13b6h1441h14ddh1504h1537h153bh162dh1631h1758h1765h1155h) Received: from mail143-co9 (localhost.localdomain [127.0.0.1]) by mail143-co9 (MessageSwitch) id 1358358976557001_31265; Wed, 16 Jan 2013 17:56:16 +0000 (UTC) Received: from CO9EHSMHS026.bigfish.com (unknown [10.236.132.245]) by mail143-co9.bigfish.com (Postfix) with ESMTP id F3A7E400B4; Wed, 16 Jan 2013 17:56:09 +0000 (UTC) Received: from BLUPRD0712HT002.namprd07.prod.outlook.com (132.245.1.197) by CO9EHSMHS026.bigfish.com (10.236.130.36) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 16 Jan 2013 17:56:09 +0000 Received: from dl.caveonetworks.com (64.2.3.195) by pod51018.outlook.com (10.255.218.163) with Microsoft SMTP Server (TLS) id 14.16.257.4; Wed, 16 Jan 2013 17:56:05 +0000 Message-ID: <50F6E9B3.5010202@caviumnetworks.com> Date: Wed, 16 Jan 2013 09:56:03 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Ralf Baechle CC: Cong Ding , Jim Quinlan , , Subject: Re: [PATCH] mpis: cavium-octeon/executive/cvmx-l2c.c: fix uninitialized variable References: <1358200025-15994-1-git-send-email-dinggnu@gmail.com> <20130116105757.GB26569@linux-mips.org> In-Reply-To: <20130116105757.GB26569@linux-mips.org> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.195] X-OriginatorOrg: caviumnetworks.com X-archive-position: 35470 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1618 Lines: 54 On 01/16/2013 02:57 AM, Ralf Baechle wrote: > On Mon, Jan 14, 2013 at 10:47:03PM +0100, Cong Ding wrote: > >> the variable dummy is used without initialization. > > Interesting - I wonder how you found this one. My compiler (gcc 4.7) > doesn't warn about this one. > I get no warnings either. So I wonder what the point of churning up the code is. David Daney > Nor does gcc notice that the whole summing up business is wasted efford. > > So here's my counter proposal. It works because ptr is a volatile pointer > so the compiler will always dereference it even if the returned value is > not being used. The resulting code is a bit smaller. > > Ralf > > Signed-off-by: Ralf Baechle > > arch/mips/cavium-octeon/executive/cvmx-l2c.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c > index 9f883bf..ec3e059 100644 > --- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c > +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c > @@ -286,7 +286,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter) > static void fault_in(uint64_t addr, int len) > { > volatile char *ptr; > - volatile char dummy; > + > /* > * Adjust addr and length so we get all cache lines even for > * small ranges spanning two cache lines. > @@ -300,7 +300,7 @@ static void fault_in(uint64_t addr, int len) > */ > CVMX_DCACHE_INVALIDATE; > while (len > 0) { > - dummy += *ptr; > + *ptr; > len -= CVMX_CACHE_LINE_SIZE; > ptr += CVMX_CACHE_LINE_SIZE; > } > > > From geert@linux-m68k.org Wed Jan 16 19:09:25 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 19:09:26 +0100 (CET) Received: from mail-vb0-f52.google.com ([209.85.212.52]:50330 "EHLO mail-vb0-f52.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832221Ab3APSJZY102B (ORCPT ); Wed, 16 Jan 2013 19:09:25 +0100 Received: by mail-vb0-f52.google.com with SMTP id ez10so1616777vbb.39 for ; Wed, 16 Jan 2013 10:09:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=0tg41AYSFwqmwHoR+CxX34iOehT9wdxGIcF1UqVPI5c=; b=szvLsjEVRYhvp88Pr/Xj5NQ7iNGXi1c6fVv+9bZA76KZnDpzyT7SbZowsr3TKl3Xdt sQpC4wfZBrwlRAJWigvuOupI2eX4LDEF+rjHkvBQZGwEr94QF8YCtdNpwFhVo+HNTuVo 9oEiUipk4S9+t1H1reu+J4Teklo7V0kZlIjpyAJScIgDx5dhoVqX7yZuHSqgCvnZbUSL IaO63dbE3V4+tocXovC5Chvn0w8qDfNe+WxdRt7n6V/7J0SXVGUrheOvge71l/xUOkEF 4pu0WHYiEWu/cwwHYdXpeolWIvLstpkAcwavNSzdFwHQ8aWVBNiIKAC/64K0rtLVOeb0 fR4A== MIME-Version: 1.0 X-Received: by 10.52.177.103 with SMTP id cp7mr1954660vdc.113.1358359758799; Wed, 16 Jan 2013 10:09:18 -0800 (PST) Received: by 10.58.227.168 with HTTP; Wed, 16 Jan 2013 10:09:18 -0800 (PST) In-Reply-To: <20130116105757.GB26569@linux-mips.org> References: <1358200025-15994-1-git-send-email-dinggnu@gmail.com> <20130116105757.GB26569@linux-mips.org> Date: Wed, 16 Jan 2013 19:09:18 +0100 X-Google-Sender-Auth: TymiDhQJkbc45H2Muq9g2Nngzto Message-ID: Subject: Re: [PATCH] mpis: cavium-octeon/executive/cvmx-l2c.c: fix uninitialized variable From: Geert Uytterhoeven To: Ralf Baechle Cc: Cong Ding , Jim Quinlan , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Content-Type: text/plain; charset=UTF-8 X-archive-position: 35471 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2175 Lines: 61 On Wed, Jan 16, 2013 at 11:57 AM, Ralf Baechle wrote: > On Mon, Jan 14, 2013 at 10:47:03PM +0100, Cong Ding wrote: > >> the variable dummy is used without initialization. > > Interesting - I wonder how you found this one. My compiler (gcc 4.7) > doesn't warn about this one. Probably older gcc does. > Nor does gcc notice that the whole summing up business is wasted efford. > > So here's my counter proposal. It works because ptr is a volatile pointer > so the compiler will always dereference it even if the returned value is > not being used. The resulting code is a bit smaller. > > Ralf > > Signed-off-by: Ralf Baechle > > arch/mips/cavium-octeon/executive/cvmx-l2c.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c > index 9f883bf..ec3e059 100644 > --- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c > +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c > @@ -286,7 +286,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter) > static void fault_in(uint64_t addr, int len) > { > volatile char *ptr; > - volatile char dummy; > + > /* > * Adjust addr and length so we get all cache lines even for > * small ranges spanning two cache lines. > @@ -300,7 +300,7 @@ static void fault_in(uint64_t addr, int len) > */ > CVMX_DCACHE_INVALIDATE; > while (len > 0) { > - dummy += *ptr; > + *ptr; Alternatively, to make clearer what's intended: - drop the "volatile" from "ptr" and from the cast when assigning to it, - use "ACCESS_ONCE(*ptr)" instead of "*ptr". > len -= CVMX_CACHE_LINE_SIZE; > ptr += CVMX_CACHE_LINE_SIZE; > } Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From ddaney.cavm@gmail.com Wed Jan 16 19:58:03 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 19:58:05 +0100 (CET) Received: from mail-pa0-f53.google.com ([209.85.220.53]:50463 "EHLO mail-pa0-f53.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832245Ab3APS6D3Z7Af (ORCPT ); Wed, 16 Jan 2013 19:58:03 +0100 Received: by mail-pa0-f53.google.com with SMTP id hz1so947877pad.40 for ; Wed, 16 Jan 2013 10:57:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=nQk/I5n3bGk7dtcksvzHqj2jd5+Ib54AkOaBPw4wIz4=; b=tN4Wepu/xY7cyTKfWJID9lyKcB20CHNy+rA3MmJ7AWKD8NCuadwAwWRV12y4FPbvsb uiOmF/snFRWu87J3ATVRqTR//J4GszaSwpXBUvS8KZLr2KGC8hUhTRyx8kkHx/B3wz3p ffvMmoJGTaeuDp6LYR5hLEaawDLLgO/XrS5NEKGCHG7LneMCjni1LT99wVrIF/vvuTf9 xqRsGabO9EoFKKJTg1Lbxn3xCoKOQKG4jtt6NFcVciz5Y18EWaO6tp/9+OlLtsLiPrSr Dh+51GsLfilwnmcvv8PFpZMYlE+kuYdMJMHDc5pqI8MdqyHZ9f9H6we3oA6kUFJsTytg smIg== X-Received: by 10.68.252.100 with SMTP id zr4mr5449030pbc.103.1358362676317; Wed, 16 Jan 2013 10:57:56 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id v2sm13440485paz.36.2013.01.16.10.57.55 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 16 Jan 2013 10:57:55 -0800 (PST) Message-ID: <50F6F832.1060807@gmail.com> Date: Wed, 16 Jan 2013 10:57:54 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Hill, Steven" , "ralf@linux-mips.org" CC: "linux-mips@linux-mips.org" , "cernekee@gmail.com" , "kevink@paralogos.com" , "Daney, David" Subject: Re: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. References: <1358230420-3575-1-git-send-email-sjhill@mips.com>,<50F5B0D0.9010604@gmail.com> <31E06A9FC96CEC488B43B19E2957C1B801146C51CC@exchdb03.mips.com> <50F5DA93.2080706@gmail.com> In-Reply-To: <50F5DA93.2080706@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35472 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5226 Lines: 193 On 01/15/2013 02:39 PM, David Daney wrote: > On 01/15/2013 02:19 PM, Hill, Steven wrote: >>>> This patch shows the use of macros in place of 'union mips_instruction' >>>> type. >>>> >>> Why? What are the benefits of doing this? >>> >> The microMIPS patches will not make it in due to the 4x size increase >> of this structure. Also, as was mentioned on the list previously by >> Ralf, it should have been done like this years back. > > A matter of opinion. Bitfields have a certain elegance > > Personally I would investigate machine generating the file with the > structure definitions. That way you could insure consistency between > big and little endian versions. Like this: ------------------8<------------------ #include struct mips_insn_field { const char *field_name; const char *field_type; int width; }; struct mips_insn_format { const char *format_name; const char *comment; struct mips_insn_field *fields; }; static struct mips_insn_format *insn_types[] = { &(struct mips_insn_format){"j_format", "Jump format", (struct mips_insn_field[]){{"opcode", "unsigned", 6}, {"target", "unsigned", 26}, {0}}}, &(struct mips_insn_format){"i_format", "Immediate format (addi, lw, ...)", (struct mips_insn_field[]){{"opcode", "unsigned", 6}, {"rs", "unsigned", 5}, {"rt", "unsigned", 5}, {"simmediate", "signed", 5}, {0}}}, &(struct mips_insn_format){"u_format", "Unsigned immediate format (ori, xori, ...)", (struct mips_insn_field[]){{"opcode", "unsigned", 6}, {"rs", "unsigned", 5}, {"rt", "unsigned", 5}, {"uimmediate", "unsigned", 5}, {0}}}, &(struct mips_insn_format){"c_format", "Cache (>= R6000) format", (struct mips_insn_field[]){{"opcode", "unsigned", 6}, {"rs", "unsigned", 5}, {"c_op", "unsigned", 3}, {"cacge", "unsigned", 2}, {"simmediate", "signed", 5}, {0}}}, NULL }; static void print_one_field(struct mips_insn_field *field) { printf("\t%s int %s:%d\n", field->field_type, field->field_name, field->width); } static void print_one_format(struct mips_insn_format *type) { int i; int num_fields = 0; struct mips_insn_field *field; field = type->fields; while (field->field_name) { num_fields++; field++; } printf("struct %s {", type->format_name); if (type->comment) printf("\t/* %s */\n", type->comment); else printf("\n"); printf("#ifdef __MIPSEB__\n"); for (i = 0; i < num_fields; i++) print_one_field(&type->fields[i]); printf("#else\n"); for (i = num_fields - 1; i >= 0; i--) print_one_field(&type->fields[i]); printf("#endif\n"); printf("};\n"); } int main(int argc, char *argv[]) { struct mips_insn_format **type = insn_types; printf("/* Machine generated, do not edit. */\n"); printf("/* Edit gen_mips_insns.c instead. */\n"); while (*type) { print_one_format(*type); type++; } return 0; } ------------------8<------------------ > > >> >>>> + >>>> +#define J_INSN(op,target) ((op << 26) | target) >>> >>> What is the type of J_INSN()? What happens if target overflows into the >>> 'op' field? >>> >> Jump instruction, which is evident from the code removed in the patch. >> The macros are not done, this is a prototype and bounds checking will >> of course be done for the final. I mostly wanted to see if people were >> happy with the macro names, how they are laid out in the header file >> and syntactical nits. >> > > For me it is much more important that the data types be correct and the > overflow conditions are handled (and perhaps also warned about). > > The order in the file I don't care about. > >>>> +#define J_INSN_TARGET(insn) (insn & 0x03ffffff) > > INSN_J_TARGET ... > >>>> +#define R_INSN(op,rs,rt,rd,re,func) ((op << 26) | (rs << 21) | \ >>>> + (rt << 16) | (rd << 11) | \ >>>> + (re << 6) | func) > > > #define INSN_RANGE_CHECK(v, bits) ({ \ > u32 val = (v); \ > u32 mask = (1 << bits) - 1; \ > WARN((v & mask) != v, "YOU LOSE"); \ > val; \ > }) > > #define INSN_TYPE_R(op, rs, rt, rd, re, func) \ > ((INSN_RANGE_CHECK((op), 6) << 26 | \ > (INSN_RANGE_CHECK((rs), 5) << 21 | \ > (INSN_RANGE_CHECK((rt), 5) << 16 | \ > (INSN_RANGE_CHECK((rd), 5) << 11 | \ > (INSN_RANGE_CHECK((re), 5) << 6 | \ > (INSN_RANGE_CHECK((func), 6)) > > But you cannot use that as a static initializer. > > >>>> +#define F_INSN(op,fmt,rt,rd,re,func) R_INSN(op,fmt,rt,rd,re,func) >>>> +#define F_INSN_FMT(insn) INSN_RS(insn) >>>> +#define U_INSN(op,rs,uimm) ((op << 26) | (rs << 21) | >>>> uimmediate) >>>> [...] >>>> + unsigned int n_insn = insn.word; >>> >>> I don't like that the width of an insn is not obvious by looking at the >>> code. >>> >>> Can we, assuming we merge something like this, make it something like >>> u32, or insn_t? I'm not sure which is better. >>> >> I was planning on making it a 'u32' but I am open to either one. Ralf, >> which would you prefer? >> >> -Steve >> > From sjhill@mips.com Wed Jan 16 22:50:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 22:50:28 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:43156 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832246Ab3APVu1QoFVa convert rfc822-to-8bit (ORCPT ); Wed, 16 Jan 2013 22:50:27 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r0GLoJ76031578; Wed, 16 Jan 2013 13:50:19 -0800 X-WSS-ID: 0MGQNBS-01-0ZF-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 27A9B364671; Wed, 16 Jan 2013 13:50:16 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.02.0247.003; Wed, 16 Jan 2013 13:50:11 -0800 From: "Hill, Steven" To: David Daney , "ralf@linux-mips.org" CC: "linux-mips@linux-mips.org" , "cernekee@gmail.com" , "kevink@paralogos.com" , "Daney, David" Subject: RE: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. Thread-Topic: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. Thread-Index: AQHN8ud/23VXA8A/UkelDJ80Zymw1ZhLUM8A//+kFDGAAI21gIABVHwA//+plwM= Date: Wed, 16 Jan 2013 21:50:10 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146C627E@exchdb03.mips.com> References: <1358230420-3575-1-git-send-email-sjhill@mips.com>,<50F5B0D0.9010604@gmail.com> <31E06A9FC96CEC488B43B19E2957C1B801146C51CC@exchdb03.mips.com> <50F5DA93.2080706@gmail.com>,<50F6F832.1060807@gmail.com> In-Reply-To: <50F6F832.1060807@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: iUjMj2nGx/bp020DVNHFlQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35473 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 106 Lines: 1 I will take whatever method everyone chooses. This is the path I need for microMIPS, so I am an agnostic. From ddaney.cavm@gmail.com Wed Jan 16 23:24:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Jan 2013 23:24:36 +0100 (CET) Received: from mail-pa0-f42.google.com ([209.85.220.42]:48967 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832241Ab3APWYf2GgRB (ORCPT ); Wed, 16 Jan 2013 23:24:35 +0100 Received: by mail-pa0-f42.google.com with SMTP id rl6so1049332pac.15 for ; Wed, 16 Jan 2013 14:24:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=xTjGF6BNRU/liX+6gyfa74qGWG1QFfl28GWN0yGLXJA=; b=0HpGoH1fe3kG1aJ0+WBXnx1A9ifbPrEXVmw42TKY9KbJ1SYh+rLZDD1+buYVpQifXr /H6g+FqfOCZg1xrbzMO4OL1aqtM0Uhp5SPnT50zFWLVF0W9FwoULcvS0bfVAIiG3QFzO wofhdY0L4y5LsxCw4kOYTLDD0Vbmk0dNbUtw8wXfWehVvQ04Dz4J0gCVo9Wq16Yk2N37 cDJxTDpenentcF7oavz/O8jaDdymAAkplgO0sYzGm2i8GHAo9AlB4k4gVNvXodna/wHG aYWo7w9qGnq1lh2zaJ+8g1TNL97wOh1Y5i8PRN3gdb+3SPyCOweghMXh2fvz/rWd3T+A teUA== X-Received: by 10.68.203.198 with SMTP id ks6mr7063136pbc.35.1358375068553; Wed, 16 Jan 2013 14:24:28 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id oj1sm12990330pbb.19.2013.01.16.14.24.27 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 16 Jan 2013 14:24:27 -0800 (PST) Message-ID: <50F7289A.3000102@gmail.com> Date: Wed, 16 Jan 2013 14:24:26 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Ralf Baechle CC: "Hill, Steven" , "linux-mips@linux-mips.org" , "cernekee@gmail.com" , "kevink@paralogos.com" Subject: Re: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. References: <1358230420-3575-1-git-send-email-sjhill@mips.com> <50F5B0D0.9010604@gmail.com> <31E06A9FC96CEC488B43B19E2957C1B801146C51CC@exchdb03.mips.com> <50F5DA93.2080706@gmail.com> <20130116141618.GC26569@linux-mips.org> In-Reply-To: <20130116141618.GC26569@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35474 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3686 Lines: 130 On 01/16/2013 06:16 AM, Ralf Baechle wrote: > On Tue, Jan 15, 2013 at 02:39:15PM -0800, David Daney wrote: > > So this should be fairly readable, far less code and in especially no > more variants for endianess except a single simple macro. > > What do you think? Very tricky. I like it. However, a small change is needed... [...] > +#define BITFIELD_FIELD(field, more) \ > + field; \ > + more > > #elif defined(__MIPSEL__) > [...] > +#define BITFIELD_FIELD(field, more) \ > + more \ > + field; > > #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ > #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" > #endif > > +struct j_format { > + BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ > + BITFIELD_FIELD(unsigned int target : 26, ... In the very last BITFIELD_FIELD(), you need a valid token as the second parameter, otherwise (according to Pinski) C90 behavior is undefined. Use a ';' > + )) > +}; > + > +struct i_format { /* signed immediate format */ > + BITFIELD_FIELD(unsigned int opcode : 6, > + BITFIELD_FIELD(unsigned int rs : 5, > + BITFIELD_FIELD(unsigned int rt : 5, > + BITFIELD_FIELD(signed int simmediate : 16, > + )))) > +}; > + > +struct u_format { /* unsigned immediate format */ > + BITFIELD_FIELD(unsigned int opcode : 6, > + BITFIELD_FIELD(unsigned int rs : 5, > + BITFIELD_FIELD(unsigned int rt : 5, > + BITFIELD_FIELD(unsigned int uimmediate : 16, > + )))) > +}; > + > +struct c_format { /* Cache (>= R6000) format */ > + BITFIELD_FIELD(unsigned int opcode : 6, > + BITFIELD_FIELD(unsigned int rs : 5, > + BITFIELD_FIELD(unsigned int c_op : 3, > + BITFIELD_FIELD(unsigned int cache : 2, > + BITFIELD_FIELD(unsigned int simmediate : 16, > + ))))) > +}; > + > +struct r_format { /* Register format */ > + BITFIELD_FIELD(unsigned int opcode : 6, > + BITFIELD_FIELD(unsigned int rs : 5, > + BITFIELD_FIELD(unsigned int rt : 5, > + BITFIELD_FIELD(unsigned int rd : 5, > + BITFIELD_FIELD(unsigned int re : 5, > + BITFIELD_FIELD(unsigned int func : 6, > + )))))) > +}; > + > +struct p_format { /* Performance counter format (R10000) */ > + BITFIELD_FIELD(unsigned int opcode : 6, > + BITFIELD_FIELD(unsigned int rs : 5, > + BITFIELD_FIELD(unsigned int rt : 5, > + BITFIELD_FIELD(unsigned int rd : 5, > + BITFIELD_FIELD(unsigned int re : 5, > + BITFIELD_FIELD(unsigned int func : 6, > + )))))) > +};BITFIELD_FIELD( > + > +struct f_format { /* FPU register format */ > + BITFIELD_FIELD(unsigned int opcode : 6, > + BITFIELD_FIELD(unsigned int : 1, > + BITFIELD_FIELD(unsigned int fmt : 4, > + BITFIELD_FIELD(unsigned int rt : 5, > + BITFIELD_FIELD(unsigned int rd : 5, > + BITFIELD_FIELD(unsigned int re : 5, > + BITFIELD_FIELD(unsigned int func : 6, > + ))))))) > +}; > + > +struct ma_format { /* FPU multiply and add format (MIPS IV) */ > + BITFIELD_FIELD(unsigned int opcode : 6, > + BITFIELD_FIELD(unsigned int fr : 5, > + BITFIELD_FIELD(unsigned int ft : 5, > + BITFIELD_FIELD(unsigned int fs : 5, > + BITFIELD_FIELD(unsigned int fd : 5, > + BITFIELD_FIELD(unsigned int func : 4, > + BITFIELD_FIELD(unsigned int fmt : 2, > + ))))))) > +}; > + > +struct b_format { /* BREAK and SYSCALL */ > + BITFIELD_FIELD(unsigned int opcode : 6, > + BITFIELD_FIELD(unsigned int code : 20, > + BITFIELD_FIELD(unsigned int func : 6, > + ))) > +}; > + > union mips_instruction { > unsigned int word; > unsigned short halfword[2]; > @@ -353,6 +299,7 @@ union mips_instruction { > struct u_format u_format; > struct c_format c_format; > struct r_format r_format; > + struct p_format p_format; > struct f_format f_format; > struct ma_format ma_format; > struct b_format b_format; > > From alcooperx@gmail.com Thu Jan 17 00:44:20 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 00:44:22 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:2054 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832247Ab3APXoU2Fro9 (ORCPT ); Thu, 17 Jan 2013 00:44:20 +0100 Received: from [10.9.208.53] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 16 Jan 2013 15:38:44 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by irvexchcas06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server id 14.1.355.2; Wed, 16 Jan 2013 15:43:56 -0800 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 3B40640FE4; Wed, 16 Jan 2013 15:43:56 -0800 (PST) From: "Al Cooper" To: rostedt@goodmis.org, ddaney.cavm@gmail.com, ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org cc: "Al Cooper" Subject: [PATCH V2] mips: function tracer: Fix broken function tracing Date: Wed, 16 Jan 2013 18:43:28 -0500 Message-ID: <1358379808-16449-1-git-send-email-alcooperx@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: References: MIME-Version: 1.0 X-WSS-ID: 7CE9E58E3Q43364463-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35475 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4717 Lines: 138 This is my second attempt and is the result of some GREAT feedback from David Daney and Steven Rostedt. Function tracing is currently broken for all 32 bit MIPS platforms. When tracing is enabled, the kernel immediately hangs on boot. This is a result of commit b732d439cb43336cd6d7e804ecb2c81193ef63b0 that changes the kernel/trace/Kconfig file so that is no longer forces FRAME_POINTER when FUNCTION_TRACING is enabled. MIPS frame pointers are generally considered to be useless because they cannot be used to unwind the stack. Unfortunately the MIPS function tracing code has bugs that are masked by the use of frame pointers. This commit fixes the bugs so that MIPS frame pointers don't need to be enabled. The bugs are a result of the odd calling sequence used to call the trace routine. This calling sequence is inserted into every traceable function when the tracing CONFIG option is enabled. This sequence is generated for 32bit MIPS platforms by the compiler via the "-pg" flag. Part of the sequence is "addiu sp,sp,-8" in the delay slot after every call to the trace routine "_mcount" (some legacy thing where 2 arguments used to be pushed on the stack). The _mcount routine is expected to adjust the sp by +8 before returning. The problem is that when tracing is disabled for a function, the "jalr _mcount" instruction is replaced with a nop, but the "addiu sp,sp,-8" is still executed and the stack pointer is left trashed. When frame pointers are enabled the problem is masked because any access to the stack is done through the frame pointer and the stack pointer is restored from the frame pointer when the function returns. This patch writes two nops starting at the address of the "jalr _mcount" instruction whenever tracing is disabled. This means that the "addiu sp,sp.-8" will be converted to a nop along with the "jalr". This is SMP safe because the first time this happens is during ftrace_init() which is before any other processor has been started. Subsequent calls to enable/disable tracing when other CPUs ARE running will still be safe because the enable will only change the first nop to a "jalr" and the disable, while writing 2 nops, will only be changing the "jalr". This patch also stops using stop_machine() to call the tracer enable/disable routines and calls them directly because the routines are SMP safe. Signed-off-by: Al Cooper --- arch/mips/kernel/ftrace.c | 34 +++++++++++++++++++++++++++++++++- arch/mips/kernel/mcount.S | 5 ++--- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 6a2d758..6bcb678 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -25,6 +25,12 @@ #define MCOUNT_OFFSET_INSNS 4 #endif +/* Arch override because MIPS doesn't need to run this from stop_machine() */ +void arch_ftrace_update_code(int command) +{ + ftrace_modify_all_code(command); +} + /* * Check if the address is in kernel space * @@ -89,6 +95,22 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) return 0; } +static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1, + unsigned int new_code2) +{ + int faulted; + + safe_store_code(new_code1, ip, faulted); + if (unlikely(faulted)) + return -EFAULT; + ip += 4; + safe_store_code(new_code2, ip, faulted); + if (unlikely(faulted)) + return -EFAULT; + flush_icache_range(ip, ip + 8); /* original ip + 12 */ + return 0; +} + /* * The details about the calling site of mcount on MIPS * @@ -131,8 +153,18 @@ int ftrace_make_nop(struct module *mod, * needed. */ new = in_kernel_space(ip) ? INSN_NOP : INSN_B_1F; - +#ifdef CONFIG_64BIT return ftrace_modify_code(ip, new); +#else + /* + * On 32 bit MIPS platforms, gcc adds a stack adjust + * instruction in the delay slot after the branch to + * mcount and expects mcount to restore the sp on return. + * This is based on a legacy API and does nothing but + * waste instructions so it's being removed at runtime. + */ + return ftrace_modify_code_2(ip, new, INSN_NOP); +#endif } int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S index 4c968e7..35ccaf7 100644 --- a/arch/mips/kernel/mcount.S +++ b/arch/mips/kernel/mcount.S @@ -46,9 +46,8 @@ PTR_L a5, PT_R9(sp) PTR_L a6, PT_R10(sp) PTR_L a7, PT_R11(sp) - PTR_ADDIU sp, PT_SIZE #else - PTR_ADDIU sp, (PT_SIZE + 8) + PTR_ADDIU sp, PT_SIZE #endif .endm @@ -69,7 +68,7 @@ NESTED(ftrace_caller, PT_SIZE, ra) .globl _mcount _mcount: b ftrace_stub - nop + addiu sp,sp,8 lw t1, function_trace_stop bnez t1, ftrace_stub nop -- 1.7.6 From geert@linux-m68k.org Thu Jan 17 07:27:26 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 07:27:27 +0100 (CET) Received: from mail-vb0-f42.google.com ([209.85.212.42]:38838 "EHLO mail-vb0-f42.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823008Ab3AQG10JbU60 (ORCPT ); Thu, 17 Jan 2013 07:27:26 +0100 Received: by mail-vb0-f42.google.com with SMTP id fa15so2199260vbb.29 for ; Wed, 16 Jan 2013 22:27:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=N1qNzm1W67FE8FoAgiJ4unQxDRFrLnQRjSEWoMXwkso=; b=Zs6AIwouBwJtCOrIs9SNj+sF5WAPdpcIqEnddDAofJUlO75YMf9P1uQc45hpMkE4l5 7Nnem/Hwja7Yi9f99qxo3tjWCB2XFf7rK+TdjrnwJUHhuVDxShkK17Zc9AXoWMLmKXQb 6TQBT8JZnzVa6H6Zk4h56Fsjr/zv0fhkGYvxP/laEvpVC+zHNKwYAx5XKmG8QVJC3351 74QHDnQx/5ToQ5lWiDUv1nxhnYie/NIDkM2ilwJS8E5iufv+mN60MA8Ayjv3+lCGL1we hRfPnaXDJcrf984V0abEyJyM+i3+9QMTpW5HSCIYCVU01z+UfK4cWoSAhlGe9mSrQJU4 IBEg== MIME-Version: 1.0 X-Received: by 10.52.30.108 with SMTP id r12mr3801905vdh.72.1358404039799; Wed, 16 Jan 2013 22:27:19 -0800 (PST) Received: by 10.58.227.168 with HTTP; Wed, 16 Jan 2013 22:27:19 -0800 (PST) In-Reply-To: <1358379808-16449-1-git-send-email-alcooperx@gmail.com> References: <1358379808-16449-1-git-send-email-alcooperx@gmail.com> Date: Thu, 17 Jan 2013 07:27:19 +0100 X-Google-Sender-Auth: LkTbMTicR-wlVa3713-ojwaW_RA Message-ID: Subject: Re: [PATCH V2] mips: function tracer: Fix broken function tracing From: Geert Uytterhoeven To: Al Cooper Cc: rostedt@goodmis.org, ddaney.cavm@gmail.com, ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 35476 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2238 Lines: 55 On Thu, Jan 17, 2013 at 12:43 AM, Al Cooper wrote: > Part of the sequence is "addiu sp,sp,-8" in the delay slot after every > call to the trace routine "_mcount" (some legacy thing where 2 arguments > used to be pushed on the stack). The _mcount routine is expected to > adjust the sp by +8 before returning. So when not disabled, the original jalr and addiu will be there, so _mcount has to adjust sp. > The problem is that when tracing is disabled for a function, the > "jalr _mcount" instruction is replaced with a nop, but the > "addiu sp,sp,-8" is still executed and the stack pointer is left > trashed. When frame pointers are enabled the problem is masked > because any access to the stack is done through the frame > pointer and the stack pointer is restored from the frame pointer when > the function returns. > > This patch writes two nops starting at the address of the "jalr _mcount" > instruction whenever tracing is disabled. This means that the > "addiu sp,sp.-8" will be converted to a nop along with the "jalr". When disabled, there will be two nops. > This is SMP safe because the first time this happens is during > ftrace_init() which is before any other processor has been started. > Subsequent calls to enable/disable tracing when other CPUs ARE running > will still be safe because the enable will only change the first nop > to a "jalr" and the disable, while writing 2 nops, will only be changing When re-enabled, there will be a jalr and a nop, which differs from the initial case, so _mcount doesn't have to adjust sp? > @@ -69,7 +68,7 @@ NESTED(ftrace_caller, PT_SIZE, ra) > .globl _mcount > _mcount: > b ftrace_stub > - nop > + addiu sp,sp,8 > lw t1, function_trace_stop > bnez t1, ftrace_stub > nop But _mcount will always adjust the stack pointer? What am I missing? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From arend@broadcom.com Thu Jan 17 12:07:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 12:07:54 +0100 (CET) Received: from mms1.broadcom.com ([216.31.210.17]:4931 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832251Ab3AQLHwclWNi convert rfc822-to-8bit (ORCPT ); Thu, 17 Jan 2013 12:07:52 +0100 Received: from [10.16.192.232] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Thu, 17 Jan 2013 03:05:33 -0800 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from SJEXCHCAS05.corp.ad.broadcom.com (10.16.203.13) by SJEXCHHUB02.corp.ad.broadcom.com (10.16.192.232) with Microsoft SMTP Server (TLS) id 8.2.247.2; Thu, 17 Jan 2013 03:07:29 -0800 Received: from SJEXCHMB13.corp.ad.broadcom.com ( [fe80::9d40:1e86:a7dc:c46a]) by SJEXCHCAS05.corp.ad.broadcom.com ( [::1]) with mapi id 14.01.0355.002; Thu, 17 Jan 2013 03:07:09 -0800 From: "Arend Van Spriel" To: "Ralf Baechle" cc: "linux-mips@linux-mips.org" , "Hauke Mehrtens" Subject: RE: [PATCH] mips: bcm47xx: select GPIOLIB for BCMA on bcm47xx platform Thread-Topic: [PATCH] mips: bcm47xx: select GPIOLIB for BCMA on bcm47xx platform Thread-Index: AQHN6qa/v/GGymUgq0KH5rR7YPhodZhNb2Hj Date: Thu, 17 Jan 2013 11:07:08 +0000 Message-ID: References: <1357323005-28008-1-git-send-email-arend@broadcom.com> In-Reply-To: <1357323005-28008-1-git-send-email-arend@broadcom.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.9.208.53] MIME-Version: 1.0 X-WSS-ID: 7CE905771ZS8202305-01-01 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8BIT X-archive-position: 35477 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arend@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 923 Lines: 29 > From: Arend van Spriel [arend@broadcom.com] > Sent: Friday, January 04, 2013 7:10 PM > > The Kconfig items BCM47XX_BCMA and BCM47XX_SSB selected > respectively BCMA_DRIVER_GPIO and SSB_DRIVER_GPIO. These > options depend on GPIOLIB without explicitly selecting it > so it results in a warning when GPIOLIB is not set: Hi Ralf Are you still intending to take this patch or did it slip by? Gr. AvS > scripts/kconfig/conf --oldconfig Kconfig > warning: (BCM47XX_BCMA) selects BCMA_DRIVER_GPIO ... unmet direct > dependencies (BCMA_POSSIBLE && BCMA && GPIOLIB) > warning: (BCM47XX_SSB) selects SSB_DRIVER_GPIO ... unmet direct > dependencies (SSB_POSSIBLE && SSB && GPIOLIB) > > which subsequently results in compile errors. > > Cc: Hauke Mehrtens > Signed-off-by: Arend van Spriel > --- > Fixing a Kconfig issue in our nightly Jenkins build. > > Gr. AvS > --- From hauke@hauke-m.de Thu Jan 17 13:57:36 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 13:57:37 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58355 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832832Ab3AQM5gEVh1c (ORCPT ); Thu, 17 Jan 2013 13:57:36 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 3B9388F61; Thu, 17 Jan 2013 13:57:35 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eIp0TCh5FupW; Thu, 17 Jan 2013 13:57:29 +0100 (CET) Received: from [IPv6:2001:470:1f0b:447:bcb8:fe27:f188:5366] (unknown [IPv6:2001:470:1f0b:447:bcb8:fe27:f188:5366]) by hauke-m.de (Postfix) with ESMTPSA id 073318E1C; Thu, 17 Jan 2013 13:57:28 +0100 (CET) Message-ID: <50F7F537.6020000@hauke-m.de> Date: Thu, 17 Jan 2013 13:57:27 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: Arend Van Spriel CC: Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [PATCH] mips: bcm47xx: select GPIOLIB for BCMA on bcm47xx platform References: <1357323005-28008-1-git-send-email-arend@broadcom.com> In-Reply-To: X-Enigmail-Version: 1.4.6 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35478 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 928 Lines: 25 On 01/17/2013 12:07 PM, Arend Van Spriel wrote: >> From: Arend van Spriel [arend@broadcom.com] >> Sent: Friday, January 04, 2013 7:10 PM >> >> The Kconfig items BCM47XX_BCMA and BCM47XX_SSB selected >> respectively BCMA_DRIVER_GPIO and SSB_DRIVER_GPIO. These >> options depend on GPIOLIB without explicitly selecting it >> so it results in a warning when GPIOLIB is not set: > > Hi Ralf > > Are you still intending to take this patch or did it slip by? > > Gr. AvS This was applied by Ralf in his tree for linux next integration [0] [1]. @Ralf could you please also send these patches to Linus for 3.8. Hauke [0]: http://git.linux-mips.org/?p=ralf/upstream-sfr.git;a=commitdiff;h=a9e985783ed936376de9f27eff54e37d584fb855;hp=3d2d03247632920aa21b42a0b032a4ffd44ce15e [1]: http://git.linux-mips.org/?p=ralf/upstream-sfr.git;a=commitdiff;h=b26d9ac76b22f53f1553d63c676dc2e70a8e3157;hp=a9e985783ed936376de9f27eff54e37d584fb855 From ralf@linux-mips.org Thu Jan 17 15:05:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 15:05:17 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:46212 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6832832Ab3AQOFQ4nW6v (ORCPT ); Thu, 17 Jan 2013 15:05:16 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0HE5Eai026534; Thu, 17 Jan 2013 15:05:14 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0HE5Alw026533; Thu, 17 Jan 2013 15:05:10 +0100 Date: Thu, 17 Jan 2013 15:05:10 +0100 From: Ralf Baechle To: David Daney Cc: "Hill, Steven" , "linux-mips@linux-mips.org" , "cernekee@gmail.com" , "kevink@paralogos.com" Subject: Re: [PATCH] [RFC] Proposed changes to eliminate 'union mips_instruction' type. Message-ID: <20130117140510.GA19406@linux-mips.org> References: <1358230420-3575-1-git-send-email-sjhill@mips.com> <50F5B0D0.9010604@gmail.com> <31E06A9FC96CEC488B43B19E2957C1B801146C51CC@exchdb03.mips.com> <50F5DA93.2080706@gmail.com> <20130116141618.GC26569@linux-mips.org> <50F7289A.3000102@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50F7289A.3000102@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35479 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 461 Lines: 14 On Wed, Jan 16, 2013 at 02:24:26PM -0800, David Daney wrote: > ... In the very last BITFIELD_FIELD(), you need a valid token as the > second parameter, otherwise (according to Pinski) C90 behavior is > undefined. > > Use a ';' While Andrew is correct, I don't think this argument matters unless we're going to export to userspace. Should we? Historically it was meant to be exported and accessed by application code from . Ralf From alcooperx@gmail.com Thu Jan 17 15:58:58 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 15:58:59 +0100 (CET) Received: from mail-qc0-f180.google.com ([209.85.216.180]:57284 "EHLO mail-qc0-f180.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832261Ab3AQO66C0o4k (ORCPT ); Thu, 17 Jan 2013 15:58:58 +0100 Received: by mail-qc0-f180.google.com with SMTP id v28so1711780qcm.11 for ; Thu, 17 Jan 2013 06:58:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:in-reply-to:references:date:message-id :subject:from:to:cc:content-type; bh=VnxVNsFYAC4NMFZhitLHz7QY0hm8lbe3vkFu34DPjNY=; b=h8smIGh1VGDUc0GDyZmeQNpi3WTtJJqtHZFinfY+0jB0fDIGnlRn61N8Lrzr7KLKVW EyLrM+oUPqITgJbijSD5PCFiG61zn+a1bDK4sXsbgAl8RgfzyipFILDaS/99LcryjHe9 42qR+hce8vR3aR9/Frzybykw+7rESzd4XZyUg3pRqYTlROQKoV8uxjeT5J2kYKwfcDdH Ah0nZDkMeWrhH9t+SPfM2PU0nHB0pJHHewCmBnniXiHKloiN2Linjc3psP4GtTZK/+vI qUZFCur5n5E4FxY7dyBGDeh5NLXQj5QrnZmEsnIDxvYuxGuoU/ZV3DSuHJfVuHBf3+qO DMuA== MIME-Version: 1.0 X-Received: by 10.224.216.9 with SMTP id hg9mr5858877qab.44.1358434731776; Thu, 17 Jan 2013 06:58:51 -0800 (PST) Received: by 10.49.117.161 with HTTP; Thu, 17 Jan 2013 06:58:51 -0800 (PST) In-Reply-To: References: <1358379808-16449-1-git-send-email-alcooperx@gmail.com> Date: Thu, 17 Jan 2013 09:58:51 -0500 Message-ID: Subject: Re: [PATCH V2] mips: function tracer: Fix broken function tracing From: Alan Cooper To: Geert Uytterhoeven Cc: rostedt@goodmis.org, ddaney.cavm@gmail.com, ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35480 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2796 Lines: 65 When the kernel first boots we have to be able to handle the gcc generated jalr, addui sequence until ftrace_init gets a chance to run and change the sequence. At this point mcount just adjusts the stack and returns. When ftrace_init runs, we convert the jalr/addui to nops. Then whenever tracing is enabled we convert the first nop to a "jalr mcount+8". The mcount+8 entry point skips the stack adjust. On Thu, Jan 17, 2013 at 1:27 AM, Geert Uytterhoeven wrote: > On Thu, Jan 17, 2013 at 12:43 AM, Al Cooper wrote: >> Part of the sequence is "addiu sp,sp,-8" in the delay slot after every >> call to the trace routine "_mcount" (some legacy thing where 2 arguments >> used to be pushed on the stack). The _mcount routine is expected to >> adjust the sp by +8 before returning. > > So when not disabled, the original jalr and addiu will be there, so _mcount has > to adjust sp. > >> The problem is that when tracing is disabled for a function, the >> "jalr _mcount" instruction is replaced with a nop, but the >> "addiu sp,sp,-8" is still executed and the stack pointer is left >> trashed. When frame pointers are enabled the problem is masked >> because any access to the stack is done through the frame >> pointer and the stack pointer is restored from the frame pointer when >> the function returns. >> >> This patch writes two nops starting at the address of the "jalr _mcount" >> instruction whenever tracing is disabled. This means that the >> "addiu sp,sp.-8" will be converted to a nop along with the "jalr". > > When disabled, there will be two nops. > >> This is SMP safe because the first time this happens is during >> ftrace_init() which is before any other processor has been started. >> Subsequent calls to enable/disable tracing when other CPUs ARE running >> will still be safe because the enable will only change the first nop >> to a "jalr" and the disable, while writing 2 nops, will only be changing > > When re-enabled, there will be a jalr and a nop, which differs from the initial > case, so _mcount doesn't have to adjust sp? > >> @@ -69,7 +68,7 @@ NESTED(ftrace_caller, PT_SIZE, ra) >> .globl _mcount >> _mcount: >> b ftrace_stub >> - nop >> + addiu sp,sp,8 >> lw t1, function_trace_stop >> bnez t1, ftrace_stub >> nop > > But _mcount will always adjust the stack pointer? > What am I missing? > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds From rostedt@goodmis.org Thu Jan 17 16:35:51 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 16:35:56 +0100 (CET) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:29820 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832832Ab3AQPfvF0Fbf (ORCPT ); Thu, 17 Jan 2013 16:35:51 +0100 X-Authority-Analysis: v=2.0 cv=O9a7TWBW c=1 sm=0 a=rXTBtCOcEpjy1lPqhTCpEQ==:17 a=mNMOxpOpBa8A:10 a=RAYXirgi3N4A:10 a=5SG0PmZfjMsA:10 a=Q9fys5e9bTEA:10 a=meVymXHHAAAA:8 a=iAK3kXgEXMMA:10 a=9tU1zQue3W_4dtgYghAA:9 a=PUjeQqilurYA:10 a=rXTBtCOcEpjy1lPqhTCpEQ==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 74.67.115.198 Received: from [74.67.115.198] ([74.67.115.198:51200] helo=[192.168.23.10]) by hrndva-oedge04.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id B6/BB-01424-15A18F05; Thu, 17 Jan 2013 15:35:46 +0000 Message-ID: <1358436945.23211.10.camel@gandalf.local.home> Subject: Re: [PATCH V2] mips: function tracer: Fix broken function tracing From: Steven Rostedt To: Alan Cooper Cc: Geert Uytterhoeven , ddaney.cavm@gmail.com, ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Date: Thu, 17 Jan 2013 10:35:45 -0500 In-Reply-To: References: <1358379808-16449-1-git-send-email-alcooperx@gmail.com> Content-Type: text/plain; charset="ISO-8859-15" X-Mailer: Evolution 3.4.4-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-archive-position: 35481 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 960 Lines: 34 On Thu, 2013-01-17 at 09:58 -0500, Alan Cooper wrote: > When the kernel first boots we have to be able to handle the gcc > generated jalr, addui sequence until ftrace_init gets a chance to run > and change the sequence. At this point mcount just adjusts the stack > and returns. When ftrace_init runs, we convert the jalr/addui to nops. > Then whenever tracing is enabled we convert the first nop to a "jalr > mcount+8". The mcount+8 entry point skips the stack adjust. > I was confused by that too. > > On Thu, Jan 17, 2013 at 1:27 AM, Geert Uytterhoeven > > > >> @@ -69,7 +68,7 @@ NESTED(ftrace_caller, PT_SIZE, ra) > >> .globl _mcount > >> _mcount: > >> b ftrace_stub > >> - nop > >> + addiu sp,sp,8 Can you add a comment here: /* When tracing is activated, it calls ftrace_caller+8 (aka here) */ > >> lw t1, function_trace_stop > >> bnez t1, ftrace_stub > >> nop > > -- Steve From sjhill@mips.com Thu Jan 17 18:37:03 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 18:37:07 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:42801 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833222Ab3AQRhDzaNpJ (ORCPT ); Thu, 17 Jan 2013 18:37:03 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TvtOZ-0003Gq-C4; Thu, 17 Jan 2013 11:36:55 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2] MIPS: malta: Code clean-ups. Date: Thu, 17 Jan 2013 11:36:50 -0600 Message-Id: <1358444210-17179-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35483 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13640 Lines: 388 From: "Steven J. Hill" Do whitespace/formatting clean-up and remove obsolete header file. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mips-boards/prom.h | 47 ------------------------ arch/mips/mti-malta/malta-display.c | 39 +++++++++----------- arch/mips/mti-malta/malta-init.c | 58 ++++++++++++++---------------- arch/mips/mti-malta/malta-memory.c | 42 +++++++++------------- arch/mips/mti-malta/malta-setup.c | 15 ++++---- 5 files changed, 66 insertions(+), 135 deletions(-) delete mode 100644 arch/mips/include/asm/mips-boards/prom.h diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h deleted file mode 100644 index a9db576..0000000 --- a/arch/mips/include/asm/mips-boards/prom.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * MIPS boards bootprom interface for the Linux kernel. - * - */ - -#ifndef _MIPS_PROM_H -#define _MIPS_PROM_H - -extern char *prom_getcmdline(void); -extern char *prom_getenv(char *name); -extern void prom_init_cmdline(void); -extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); -extern void mips_display_message(const char *str); -extern void mips_display_word(unsigned int num); -extern void mips_scroll_message(void); -extern int get_ethernet_addr(char *ethernet_addr); - -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - unsigned long base; /* Within KSEG0. */ - unsigned int size; /* In bytes. */ - unsigned int type; /* free or prom memory */ -}; - -#endif /* !(_MIPS_PROM_H) */ diff --git a/arch/mips/mti-malta/malta-display.c b/arch/mips/mti-malta/malta-display.c index 2a0057c..04826d7 100644 --- a/arch/mips/mti-malta/malta-display.c +++ b/arch/mips/mti-malta/malta-display.c @@ -1,26 +1,19 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Display routines for display messages in MIPS boards ascii display. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ - #include #include -#include +#include + #include extern const char display_string[]; @@ -29,17 +22,17 @@ static unsigned int max_display_count; void mips_display_message(const char *str) { - static unsigned int __iomem *display = NULL; + static unsigned int __iomem *display; int i; if (unlikely(display == NULL)) display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int)); - for (i = 0; i <= 14; i=i+2) { - if (*str) - __raw_writel(*str++, display + i); - else - __raw_writel(' ', display + i); + for (i = 0; i <= 14; i += 2) { + if (*str) + __raw_writel(*str++, display + i); + else + __raw_writel(' ', display + i); } } diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 6c61e94..0ae857a 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -1,42 +1,29 @@ /* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * PROM library initialisation code. + * + * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * Steven J. Hill */ #include #include #include -#include -#include #include #include #include #include #include #include -#include -#include - #include -int init_debug; +extern void mips_display_message(const char *str); static int mips_revision_corid; int mips_revision_sconid; @@ -64,12 +51,18 @@ static void __init console_config(void) if (s) { while (*s >= '0' && *s <= '9') baud = baud*10 + *s++ - '0'; - if (*s == ',') s++; - if (*s) parity = *s++; - if (*s == ',') s++; - if (*s) bits = *s++; - if (*s == ',') s++; - if (*s == 'h') flow = 'r'; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; } if (baud == 0) baud = 38400; @@ -79,7 +72,8 @@ static void __init console_config(void) bits = '8'; if (flow == '\0') flow = 'r'; - sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, + parity, bits, flow); strcat(fw_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } @@ -223,7 +217,7 @@ void __init prom_init(void) case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); - mips_pci_controller: +mips_pci_controller: mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); @@ -265,7 +259,7 @@ void __init prom_init(void) default: /* Unknown system controller */ mips_display_message("SC Error"); - while (1); /* We die here... */ + while (1); /* We die here... */ } board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index 06fa4ad..391960a 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -1,31 +1,21 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * PROM library functions for acquiring/using memory descriptors given to * us from the YAMON. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ #include -#include #include -#include #include #include -#include #include #include @@ -36,19 +26,20 @@ unsigned long physical_memsize = 0L; fw_memblock_t * __init fw_getmdesc(void) { - char *memsize_str; + char *memsize_str, *ptr; unsigned int memsize; - char *ptr; static char cmdline[COMMAND_LINE_SIZE] __initdata; + long val; + int tmp; /* otherwise look in the environment */ memsize_str = fw_getenv("memsize"); if (!memsize_str) { - printk(KERN_WARNING - "memsize not set in boot prom, set to default (32Mb)\n"); + pr_warn("memsize not set in YAMON, set to default (32Mb)\n"); physical_memsize = 0x02000000; } else { - physical_memsize = simple_strtol(memsize_str, NULL, 0); + tmp = kstrtol(memsize_str, 0, &val); + physical_memsize = (unsigned long)val; } #ifdef CONFIG_CPU_BIG_ENDIAN @@ -92,7 +83,8 @@ fw_memblock_t * __init fw_getmdesc(void) mdesc[3].type = fw_dontuse; mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - + mdesc[3].base; mdesc[4].type = fw_free; mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); @@ -142,7 +134,7 @@ void __init prom_free_prom_memory(void) continue; addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", + free_init_pages("YAMON memory", addr, addr + boot_mem_map.map[i].size); } } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 08cdf8f..ed68073 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -117,13 +117,12 @@ static void __init pci_clock_check(void) char *argptr = fw_getcmdline(); if (pciclock != 33 && !strstr(argptr, "idebus=")) { - printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " - "setting idebus\n", pciclock); + pr_warn("WARNING: PCI clock is %dMHz, setting idebus\n", + pciclock); argptr += strlen(argptr); sprintf(argptr, " idebus=%d", pciclock); if (pciclock < 20 || pciclock > 66) - printk(KERN_WARNING "WARNING: IDE timing " - "calculations will be incorrect\n"); + pr_warn("WARNING: IDE timing calculations will be incorrect\n"); } } #endif @@ -155,14 +154,14 @@ static void __init bonito_quirks_setup(void) argptr = fw_getcmdline(); if (strstr(argptr, "debug")) { BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; - printk(KERN_INFO "Enabled Bonito debug mode\n"); + pr_info("Enabled Bonito debug mode\n"); } else BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; #ifdef CONFIG_DMA_COHERENT if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; - printk(KERN_INFO "Enabled Bonito CPU coherency\n"); + pr_info("Enabled Bonito CPU coherency\n"); argptr = fw_getcmdline(); if (strstr(argptr, "iobcuncached")) { @@ -170,13 +169,13 @@ static void __init bonito_quirks_setup(void) BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Disabled Bonito IOBC coherency\n"); + pr_info("Disabled Bonito IOBC coherency\n"); } else { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG |= (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Enabled Bonito IOBC coherency\n"); + pr_info("Enabled Bonito IOBC coherency\n"); } } else panic("Hardware DMA cache coherency not supported"); -- 1.7.9.5 From sjhill@mips.com Thu Jan 17 18:37:07 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 18:37:28 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:42803 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833221Ab3AQRhHTDeme (ORCPT ); Thu, 17 Jan 2013 18:37:07 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TvtOf-0003Gv-Bc; Thu, 17 Jan 2013 11:37:01 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: microMIPS: Redefine value of BRK_BUG. Date: Thu, 17 Jan 2013 11:36:56 -0600 Message-Id: <1358444216-17213-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35484 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1473 Lines: 44 From: "Steven J. Hill" The BRK_BUG value is used in the BUG and __BUG_ON inline macros. For standard MIPS cores the code in the 'tne' instruction is 10-bits long. In microMIPS, the 'tne' instruction is recoded and the code can only be 4-bits long. We use the value of 12 instead of 512 when building a microMIPS kernel. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/break.h | 1 + arch/mips/include/asm/bug.h | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 9161e68..df9d090 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -27,6 +27,7 @@ #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ +#define BRK_BUG_MM 12 /* Used by BUG() in microMIPS mode */ #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ #define BRK_MEMU 514 /* Used by FPU emulator */ diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h index 540c98a..b716fb9 100644 --- a/arch/mips/include/asm/bug.h +++ b/arch/mips/include/asm/bug.h @@ -7,6 +7,10 @@ #ifdef CONFIG_BUG #include +#ifdef CONFIG_CPU_MICROMIPS +#undef BRK_BUG +#define BRK_BUG BRK_BUG_MM +#endif static inline void __noreturn BUG(void) { -- 1.7.9.5 From sjhill@mips.com Thu Jan 17 18:37:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 18:37:48 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:42805 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832251Ab3AQRhOfNf8U (ORCPT ); Thu, 17 Jan 2013 18:37:14 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TvtOm-0003H0-CY; Thu, 17 Jan 2013 11:37:08 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v4] OF: MIPS: sead3: Implement OF support. Date: Thu, 17 Jan 2013 11:37:03 -0600 Message-Id: <1358444223-17247-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35485 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8592 Lines: 314 From: "Steven J. Hill" Activate USE_OF for SEAD-3 platform. Add basic DTS file and convert memory detection and reservations to use OF. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 1 + arch/mips/include/asm/mips-boards/generic.h | 4 + arch/mips/mti-sead3/Makefile | 10 +- arch/mips/mti-sead3/sead3-init.c | 5 +- arch/mips/mti-sead3/sead3-memory.c | 138 --------------------------- arch/mips/mti-sead3/sead3-setup.c | 27 ++++++ arch/mips/mti-sead3/sead3.dts | 26 +++++ 7 files changed, 70 insertions(+), 141 deletions(-) delete mode 100644 arch/mips/mti-sead3/sead3-memory.c create mode 100644 arch/mips/mti-sead3/sead3.dts diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 86153b6..88af14c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -355,6 +355,7 @@ config MIPS_SEAD3 select USB_ARCH_HAS_EHCI select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO + select USE_OF help This enables support for the MIPS Technologies SEAD3 evaluation board. diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index 6e23ceb..c01e286 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -87,6 +87,10 @@ extern int mips_revision_sconid; +#ifdef CONFIG_OF +extern struct boot_param_header __dtb_start; +#endif + #ifdef CONFIG_PCI extern void mips_pcibios_init(void); #else diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile index 626afea..10ec701 100644 --- a/arch/mips/mti-sead3/Makefile +++ b/arch/mips/mti-sead3/Makefile @@ -5,10 +5,12 @@ # Copyright (C) 2008 Wind River Systems, Inc. # written by Ralf Baechle # +# Copyright (C) 2012 MIPS Technoligies, Inc. All rights reserved. +# Steven J. Hill +# obj-y := sead3-lcd.o sead3-cmdline.o \ sead3-display.o sead3-init.o sead3-int.o \ - sead3-mtd.o sead3-net.o \ - sead3-memory.o sead3-platform.o \ + sead3-mtd.o sead3-net.o sead3-platform.o \ sead3-reset.o sead3-setup.o sead3-time.o obj-y += sead3-i2c-dev.o sead3-i2c.o \ @@ -17,3 +19,7 @@ obj-y += sead3-i2c-dev.o sead3-i2c.o \ obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o +obj-$(CONFIG_OF) += sead3.dtb.o + +$(obj)/%.dtb: $(obj)/%.dts + $(call if_changed,dtc) diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c index 802fce2..6939254 100644 --- a/arch/mips/mti-sead3/sead3-init.c +++ b/arch/mips/mti-sead3/sead3-init.c @@ -125,7 +125,6 @@ void __init prom_init(void) board_ejtag_handler_setup = mips_ejtag_setup; prom_init_cmdline(); - prom_meminit(); #ifdef CONFIG_EARLY_PRINTK if ((strstr(prom_getcmdline(), "console=ttyS0")) != NULL) prom_init_early_console(0); @@ -137,3 +136,7 @@ void __init prom_init(void) strcat(prom_getcmdline(), " console=ttyS0,38400n8r"); #endif } + +void prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/mti-sead3/sead3-memory.c b/arch/mips/mti-sead3/sead3-memory.c deleted file mode 100644 index da92441..0000000 --- a/arch/mips/mti-sead3/sead3-memory.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. - */ -#include - -#include -#include -#include - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; - -static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -/* determined physical memory size, not overridden by command line args */ -unsigned long physical_memsize = 0L; - -struct prom_pmemblock * __init prom_getmdesc(void) -{ - char *memsize_str, *ptr; - unsigned int memsize; - static char cmdline[COMMAND_LINE_SIZE] __initdata; - long val; - int tmp; - - /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - pr_warn("memsize not set in boot prom, set to default 32Mb\n"); - physical_memsize = 0x02000000; - } else { - tmp = kstrtol(memsize_str, 0, &val); - physical_memsize = (unsigned long)val; - } - -#ifdef CONFIG_CPU_BIG_ENDIAN - /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last - word of physical memory */ - physical_memsize -= PAGE_SIZE; -#endif - - /* Check the command line for a memsize directive that overrides - the physical/default amount */ - strcpy(cmdline, arcs_cmdline); - ptr = strstr(cmdline, "memsize="); - if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) - ptr = strstr(ptr, " memsize="); - - if (ptr) - memsize = memparse(ptr + 8, &ptr); - else - memsize = physical_memsize; - - memset(mdesc, 0, sizeof(mdesc)); - - mdesc[0].type = yamon_dontuse; - mdesc[0].base = 0x00000000; - mdesc[0].size = 0x00001000; - - mdesc[1].type = yamon_prom; - mdesc[1].base = 0x00001000; - mdesc[1].size = 0x000ef000; - - /* - * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the - * south bridge and PCI access always forwarded to the ISA Bus and - * BIOSCS# is always generated. - * This mean that this area can't be used as DMA memory for PCI - * devices. - */ - mdesc[2].type = yamon_dontuse; - mdesc[2].base = 0x000f0000; - mdesc[2].size = 0x00010000; - - mdesc[3].type = yamon_dontuse; - mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - - mdesc[3].base; - - mdesc[4].type = yamon_free; - mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); - mdesc[4].size = memsize - mdesc[4].base; - - return &mdesc[0]; -} - -static int __init prom_memtype_classify(unsigned int type) -{ - switch (type) { - case yamon_free: - return BOOT_MEM_RAM; - case yamon_prom: - return BOOT_MEM_ROM_DATA; - default: - return BOOT_MEM_RESERVED; - } -} - -void __init prom_meminit(void) -{ - struct prom_pmemblock *p; - - p = prom_getmdesc(); - - while (p->size) { - long type; - unsigned long base, size; - - type = prom_memtype_classify(p->type); - base = p->base; - size = p->size; - - add_memory_region(base, size, type); - p++; - } -} - -void __init prom_free_prom_memory(void) -{ - unsigned long addr; - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c index 8ad46ad..f012fd1 100644 --- a/arch/mips/mti-sead3/sead3-setup.c +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -6,6 +6,12 @@ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include +#include +#include +#include + +#include +#include int coherentio; /* 0 => no DMA cache coherency (may be set by user) */ int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */ @@ -17,4 +23,25 @@ const char *get_system_type(void) void __init plat_mem_setup(void) { + /* + * Load the builtin devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + __dt_setup_arch(&__dtb_start); +} + +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); } diff --git a/arch/mips/mti-sead3/sead3.dts b/arch/mips/mti-sead3/sead3.dts new file mode 100644 index 0000000..658f437 --- /dev/null +++ b/arch/mips/mti-sead3/sead3.dts @@ -0,0 +1,26 @@ +/dts-v1/; + +/memreserve/ 0x00000000 0x00001000; // reserved +/memreserve/ 0x00001000 0x000ef000; // ROM data +/memreserve/ 0x000f0000 0x004cc000; // reserved + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mti,sead-3"; + + cpus { + cpu@0 { + compatible = "mti,mips14KEc", "mti,mips14Kc"; + }; + }; + + chosen { + bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; -- 1.7.9.5 From sjhill@mips.com Thu Jan 17 18:40:28 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 18:40:32 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:42813 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832251Ab3AQRk2OcEDQ (ORCPT ); Thu, 17 Jan 2013 18:40:28 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TvtRt-0003He-O7; Thu, 17 Jan 2013 11:40:21 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2,4/4] MIPS: malta: Code clean-ups. Date: Thu, 17 Jan 2013 11:40:16 -0600 Message-Id: <1358444416-17457-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35486 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13640 Lines: 388 From: "Steven J. Hill" Do whitespace/formatting clean-up and remove obsolete header file. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mips-boards/prom.h | 47 ------------------------ arch/mips/mti-malta/malta-display.c | 39 +++++++++----------- arch/mips/mti-malta/malta-init.c | 58 ++++++++++++++---------------- arch/mips/mti-malta/malta-memory.c | 42 +++++++++------------- arch/mips/mti-malta/malta-setup.c | 15 ++++---- 5 files changed, 66 insertions(+), 135 deletions(-) delete mode 100644 arch/mips/include/asm/mips-boards/prom.h diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h deleted file mode 100644 index a9db576..0000000 --- a/arch/mips/include/asm/mips-boards/prom.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * MIPS boards bootprom interface for the Linux kernel. - * - */ - -#ifndef _MIPS_PROM_H -#define _MIPS_PROM_H - -extern char *prom_getcmdline(void); -extern char *prom_getenv(char *name); -extern void prom_init_cmdline(void); -extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); -extern void mips_display_message(const char *str); -extern void mips_display_word(unsigned int num); -extern void mips_scroll_message(void); -extern int get_ethernet_addr(char *ethernet_addr); - -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - unsigned long base; /* Within KSEG0. */ - unsigned int size; /* In bytes. */ - unsigned int type; /* free or prom memory */ -}; - -#endif /* !(_MIPS_PROM_H) */ diff --git a/arch/mips/mti-malta/malta-display.c b/arch/mips/mti-malta/malta-display.c index 2a0057c..04826d7 100644 --- a/arch/mips/mti-malta/malta-display.c +++ b/arch/mips/mti-malta/malta-display.c @@ -1,26 +1,19 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Display routines for display messages in MIPS boards ascii display. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ - #include #include -#include +#include + #include extern const char display_string[]; @@ -29,17 +22,17 @@ static unsigned int max_display_count; void mips_display_message(const char *str) { - static unsigned int __iomem *display = NULL; + static unsigned int __iomem *display; int i; if (unlikely(display == NULL)) display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int)); - for (i = 0; i <= 14; i=i+2) { - if (*str) - __raw_writel(*str++, display + i); - else - __raw_writel(' ', display + i); + for (i = 0; i <= 14; i += 2) { + if (*str) + __raw_writel(*str++, display + i); + else + __raw_writel(' ', display + i); } } diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 6c61e94..0ae857a 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -1,42 +1,29 @@ /* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * PROM library initialisation code. + * + * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * Steven J. Hill */ #include #include #include -#include -#include #include #include #include #include #include #include -#include -#include - #include -int init_debug; +extern void mips_display_message(const char *str); static int mips_revision_corid; int mips_revision_sconid; @@ -64,12 +51,18 @@ static void __init console_config(void) if (s) { while (*s >= '0' && *s <= '9') baud = baud*10 + *s++ - '0'; - if (*s == ',') s++; - if (*s) parity = *s++; - if (*s == ',') s++; - if (*s) bits = *s++; - if (*s == ',') s++; - if (*s == 'h') flow = 'r'; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; } if (baud == 0) baud = 38400; @@ -79,7 +72,8 @@ static void __init console_config(void) bits = '8'; if (flow == '\0') flow = 'r'; - sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, + parity, bits, flow); strcat(fw_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } @@ -223,7 +217,7 @@ void __init prom_init(void) case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); - mips_pci_controller: +mips_pci_controller: mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); @@ -265,7 +259,7 @@ void __init prom_init(void) default: /* Unknown system controller */ mips_display_message("SC Error"); - while (1); /* We die here... */ + while (1); /* We die here... */ } board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index 06fa4ad..391960a 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -1,31 +1,21 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * PROM library functions for acquiring/using memory descriptors given to * us from the YAMON. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ #include -#include #include -#include #include #include -#include #include #include @@ -36,19 +26,20 @@ unsigned long physical_memsize = 0L; fw_memblock_t * __init fw_getmdesc(void) { - char *memsize_str; + char *memsize_str, *ptr; unsigned int memsize; - char *ptr; static char cmdline[COMMAND_LINE_SIZE] __initdata; + long val; + int tmp; /* otherwise look in the environment */ memsize_str = fw_getenv("memsize"); if (!memsize_str) { - printk(KERN_WARNING - "memsize not set in boot prom, set to default (32Mb)\n"); + pr_warn("memsize not set in YAMON, set to default (32Mb)\n"); physical_memsize = 0x02000000; } else { - physical_memsize = simple_strtol(memsize_str, NULL, 0); + tmp = kstrtol(memsize_str, 0, &val); + physical_memsize = (unsigned long)val; } #ifdef CONFIG_CPU_BIG_ENDIAN @@ -92,7 +83,8 @@ fw_memblock_t * __init fw_getmdesc(void) mdesc[3].type = fw_dontuse; mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - + mdesc[3].base; mdesc[4].type = fw_free; mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); @@ -142,7 +134,7 @@ void __init prom_free_prom_memory(void) continue; addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", + free_init_pages("YAMON memory", addr, addr + boot_mem_map.map[i].size); } } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 08cdf8f..ed68073 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -117,13 +117,12 @@ static void __init pci_clock_check(void) char *argptr = fw_getcmdline(); if (pciclock != 33 && !strstr(argptr, "idebus=")) { - printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " - "setting idebus\n", pciclock); + pr_warn("WARNING: PCI clock is %dMHz, setting idebus\n", + pciclock); argptr += strlen(argptr); sprintf(argptr, " idebus=%d", pciclock); if (pciclock < 20 || pciclock > 66) - printk(KERN_WARNING "WARNING: IDE timing " - "calculations will be incorrect\n"); + pr_warn("WARNING: IDE timing calculations will be incorrect\n"); } } #endif @@ -155,14 +154,14 @@ static void __init bonito_quirks_setup(void) argptr = fw_getcmdline(); if (strstr(argptr, "debug")) { BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; - printk(KERN_INFO "Enabled Bonito debug mode\n"); + pr_info("Enabled Bonito debug mode\n"); } else BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; #ifdef CONFIG_DMA_COHERENT if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; - printk(KERN_INFO "Enabled Bonito CPU coherency\n"); + pr_info("Enabled Bonito CPU coherency\n"); argptr = fw_getcmdline(); if (strstr(argptr, "iobcuncached")) { @@ -170,13 +169,13 @@ static void __init bonito_quirks_setup(void) BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Disabled Bonito IOBC coherency\n"); + pr_info("Disabled Bonito IOBC coherency\n"); } else { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG |= (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Enabled Bonito IOBC coherency\n"); + pr_info("Enabled Bonito IOBC coherency\n"); } } else panic("Hardware DMA cache coherency not supported"); -- 1.7.9.5 From ddaney.cavm@gmail.com Thu Jan 17 19:15:59 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 19:16:03 +0100 (CET) Received: from mail-da0-f52.google.com ([209.85.210.52]:48033 "EHLO mail-da0-f52.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833223Ab3AQSP7Gb3wv (ORCPT ); Thu, 17 Jan 2013 19:15:59 +0100 Received: by mail-da0-f52.google.com with SMTP id f10so1230877dak.39 for ; Thu, 17 Jan 2013 10:15:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=hEY41LKmAPuTq2DlL6N1C2edmWkfzm6zyXHT0qbtKbQ=; b=Xsd2pylbVOiIyr8xg1bq+hGRaF498g0d58V9YZVewuuknAgNv2wLVyfV3oSj9vSL5X E6Gn87w5in+7ZnoQrehqnl/KUeOpDFuOyLAHpv9R3l1Yxs8atZXe7d4MkoW1vjf+P5a+ grjiTSe34wiZD6BBtqNXqCkEbhE9/yMd+v1QSnjhIl2VMOAeVwARNDqd7g22hhhbfwI/ qfiKqIQ7wFLJ/Q8VdymyMs1RNkS7AY3HX64PLIgUi4tsJfzk36pVw6Blskbv9U127NtL c7x6Jtz6zPHSoJXxWhHtIR43dj9xlYLwdqpdJ846tnXRdpqQi1gTfa968NcE81LJtBuo AF4g== X-Received: by 10.68.137.131 with SMTP id qi3mr15847313pbb.114.1358446552013; Thu, 17 Jan 2013 10:15:52 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id oi2sm1453158pbb.62.2013.01.17.10.15.50 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 17 Jan 2013 10:15:51 -0800 (PST) Message-ID: <50F83FD5.2060908@gmail.com> Date: Thu, 17 Jan 2013 10:15:49 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] MIPS: microMIPS: Redefine value of BRK_BUG. References: <1358444216-17213-1-git-send-email-sjhill@mips.com> In-Reply-To: <1358444216-17213-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35487 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1937 Lines: 58 On 01/17/2013 09:36 AM, Steven J. Hill wrote: > From: "Steven J. Hill" > > The BRK_BUG value is used in the BUG and __BUG_ON inline macros. For > standard MIPS cores the code in the 'tne' instruction is 10-bits long. > In microMIPS, the 'tne' instruction is recoded and the code can only be > 4-bits long. We use the value of 12 instead of 512 when building a > microMIPS kernel. > > Signed-off-by: Steven J. Hill > --- > arch/mips/include/asm/break.h | 1 + > arch/mips/include/asm/bug.h | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h > index 9161e68..df9d090 100644 > --- a/arch/mips/include/asm/break.h > +++ b/arch/mips/include/asm/break.h > @@ -27,6 +27,7 @@ > #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ > #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ > #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ > +#define BRK_BUG_MM 12 /* Used by BUG() in microMIPS mode */ > #define BRK_BUG 512 /* Used by BUG() */ Can we move the CONFIG_CPU_MICROMIPS to here and just call the thing BRK_BUG? Or perhaps redefining it unconditionally. I am not sure what the implications of doing that would be. That way... > #define BRK_KDB 513 /* Used in KDB_ENTER() */ > #define BRK_MEMU 514 /* Used by FPU emulator */ > diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h > index 540c98a..b716fb9 100644 > --- a/arch/mips/include/asm/bug.h > +++ b/arch/mips/include/asm/bug.h > @@ -7,6 +7,10 @@ > #ifdef CONFIG_BUG > > #include > +#ifdef CONFIG_CPU_MICROMIPS > +#undef BRK_BUG > +#define BRK_BUG BRK_BUG_MM > +#endif > ...We don't need this bit. Doing an #undef risks using different values for BRK_BUG depending on whether or not asm/bug.h is included. > static inline void __noreturn BUG(void) > { > From sjhill@mips.com Thu Jan 17 20:07:19 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 20:07:20 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:45961 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832261Ab3AQTHTT-jhs convert rfc822-to-8bit (ORCPT ); Thu, 17 Jan 2013 20:07:19 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r0HJ7Bjv021208; Thu, 17 Jan 2013 11:07:11 -0800 X-WSS-ID: 0MGSAFZ-01-1JH-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.67]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2298136467D; Thu, 17 Jan 2013 11:07:10 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([::1]) with mapi id 14.02.0247.003; Thu, 17 Jan 2013 11:07:06 -0800 From: "Hill, Steven" To: David Daney CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: RE: [PATCH] MIPS: microMIPS: Redefine value of BRK_BUG. Thread-Topic: [PATCH] MIPS: microMIPS: Redefine value of BRK_BUG. Thread-Index: AQHN9NlEm+9CcxJkN0q8N792sqGhLphOWcSA//+HK/U= Date: Thu, 17 Jan 2013 19:07:05 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146C7186@exchdb03.mips.com> References: <1358444216-17213-1-git-send-email-sjhill@mips.com>,<50F83FD5.2060908@gmail.com> In-Reply-To: <50F83FD5.2060908@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: G5e6A7fuWJSQTPCxKzn4vA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35488 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1176 Lines: 29 >> diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h >> index 9161e68..df9d090 100644 >> --- a/arch/mips/include/asm/break.h >> +++ b/arch/mips/include/asm/break.h >> @@ -27,6 +27,7 @@ >> #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ >> #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ >> #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ >> +#define BRK_BUG_MM 12 /* Used by BUG() in microMIPS mode */ >> #define BRK_BUG 512 /* Used by BUG() */ > > Can we move the CONFIG_CPU_MICROMIPS to here and just call the thing > BRK_BUG? > No, because this header file is exported in 'arch/mips/include/uapi/asm' now. I already discussed this with Ralf. >> #include >> +#ifdef CONFIG_CPU_MICROMIPS >> +#undef BRK_BUG >> +#define BRK_BUG BRK_BUG_MM >> +#endif >> > > ...We don't need this bit. Doing an #undef risks using different > values for BRK_BUG depending on whether or not asm/bug.h is included. > I was trying to avoid two #ifdef's in 'bug.h' but I can certainly get rid of the above and use two #ifdef's instead. -Steve From ralf@linux-mips.org Thu Jan 17 23:54:13 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Jan 2013 23:54:14 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:48877 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6833227Ab3AQWyNgL88h (ORCPT ); Thu, 17 Jan 2013 23:54:13 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0HMsBeM017711; Thu, 17 Jan 2013 23:54:11 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0HMsAIW017710; Thu, 17 Jan 2013 23:54:10 +0100 Date: Thu, 17 Jan 2013 23:54:10 +0100 From: Ralf Baechle To: David Daney Cc: "Steven J. Hill" , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: microMIPS: Redefine value of BRK_BUG. Message-ID: <20130117225410.GB19406@linux-mips.org> References: <1358444216-17213-1-git-send-email-sjhill@mips.com> <50F83FD5.2060908@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50F83FD5.2060908@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35489 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2022 Lines: 62 On Thu, Jan 17, 2013 at 10:15:49AM -0800, David Daney wrote: > >diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h > >index 9161e68..df9d090 100644 > >--- a/arch/mips/include/asm/break.h > >+++ b/arch/mips/include/asm/break.h > >@@ -27,6 +27,7 @@ > > #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ > > #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ > > #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ > >+#define BRK_BUG_MM 12 /* Used by BUG() in microMIPS mode */ > > #define BRK_BUG 512 /* Used by BUG() */ > > Can we move the CONFIG_CPU_MICROMIPS to here and just call the thing > BRK_BUG? > > Or perhaps redefining it unconditionally. I am not sure what the > implications of doing that would be. > > That way... The kernel decodes break and trap instruction in traps.c. For a microMIPS- enabled kernel it needs to be able to decode both classic and microMIPS encoded instructions so we want separate symbols. Or we do something like #define BRK_MM_BUG 12 /* Used by BUG() in microMIPS mode */ #define BRK_CM_BUG 512 /* Used by BUG() */ #ifdef __mips_micromips #define BRK_BUG BRK_MM_BUG #else #define BRK_BUG BRK_CM_BUG #endif This makes the BRK_MM_* / BRK_CM_* macros available for decoding instructions and the microMIPS-agnostic BRK_BUG for code such as BUG(). > > #define BRK_KDB 513 /* Used in KDB_ENTER() */ > > #define BRK_MEMU 514 /* Used by FPU emulator */ > >diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h > >index 540c98a..b716fb9 100644 > >--- a/arch/mips/include/asm/bug.h > >+++ b/arch/mips/include/asm/bug.h > >@@ -7,6 +7,10 @@ > > #ifdef CONFIG_BUG > > > > #include > >+#ifdef CONFIG_CPU_MICROMIPS > >+#undef BRK_BUG > >+#define BRK_BUG BRK_BUG_MM > >+#endif > > > > ...We don't need this bit. Doing an #undef risks using different > values for BRK_BUG depending on whether or not asm/bug.h is > included. And generally is not very elegant. Ralf From ddaney.cavm@gmail.com Fri Jan 18 01:42:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Jan 2013 01:42:51 +0100 (CET) Received: from mail-pa0-f46.google.com ([209.85.220.46]:58918 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824789Ab3ARAmu1hcTk (ORCPT ); Fri, 18 Jan 2013 01:42:50 +0100 Received: by mail-pa0-f46.google.com with SMTP id kp14so401642pab.5 for ; Thu, 17 Jan 2013 16:42:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=5tnTxl/f8DMTaIdTEfxAcpYDNP15eAHVj/zRF1JyPxc=; b=eQxfeUMdr8sh1iOLoFudgIgsVA4cyOOLjI8Mqc2eWlGr7rLOHMuE8qDFge2LDd4t2x A2UU1jxjVmGkMzRrJXPGyKsctdX/9rfQeDdEbrkG6Psy7olgdEmXPwuhTMzc3kyw5ipX ErsyJpd+uafj6GdTEldudeAv8u9izvk3PmCVQiOpnYF0Y0awf7TnT2YE+uYbmXkZgZZ+ Za5snX9jH44lmOG4KLwXO0WsRKiQfxoBC/yWrAsNKodY8e89LBkIbscMQ//RFEpL58cH LWsrXn1HpziLbngmi8UM1l6Adm9yFaEZyKfYiybzOdq7e7BUrayoFh0791A6D7EwfQ2j p1XA== X-Received: by 10.68.229.169 with SMTP id sr9mr18492721pbc.120.1358469763217; Thu, 17 Jan 2013 16:42:43 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id bv10sm2250882pab.14.2013.01.17.16.42.41 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 17 Jan 2013 16:42:42 -0800 (PST) Message-ID: <50F89A81.8040703@gmail.com> Date: Thu, 17 Jan 2013 16:42:41 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Ralf Baechle CC: "Steven J. Hill" , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: microMIPS: Redefine value of BRK_BUG. References: <1358444216-17213-1-git-send-email-sjhill@mips.com> <50F83FD5.2060908@gmail.com> <20130117225410.GB19406@linux-mips.org> In-Reply-To: <20130117225410.GB19406@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35490 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2501 Lines: 77 On 01/17/2013 02:54 PM, Ralf Baechle wrote: > On Thu, Jan 17, 2013 at 10:15:49AM -0800, David Daney wrote: > >>> diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h >>> index 9161e68..df9d090 100644 >>> --- a/arch/mips/include/asm/break.h >>> +++ b/arch/mips/include/asm/break.h >>> @@ -27,6 +27,7 @@ >>> #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ >>> #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ >>> #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ >>> +#define BRK_BUG_MM 12 /* Used by BUG() in microMIPS mode */ >>> #define BRK_BUG 512 /* Used by BUG() */ >> >> Can we move the CONFIG_CPU_MICROMIPS to here and just call the thing >> BRK_BUG? >> >> Or perhaps redefining it unconditionally. I am not sure what the >> implications of doing that would be. >> >> That way... > > The kernel decodes break and trap instruction in traps.c. For a microMIPS- > enabled kernel it needs to be able to decode both classic and microMIPS > encoded instructions so we want separate symbols. For any given kernel, BUG() will be implemented using exactly one trap value. That should be the value tested in traps.c So we could make non-microMIPS use the same value as microMIPS and then we don't have to test for two values. Side note: The values used only internally to the kernel should not be exported in a userspace visible header file. > > Or we do something like > > #define BRK_MM_BUG 12 /* Used by BUG() in microMIPS mode */ > #define BRK_CM_BUG 512 /* Used by BUG() */ > > #ifdef __mips_micromips > #define BRK_BUG BRK_MM_BUG > #else > #define BRK_BUG BRK_CM_BUG > #endif > > This makes the BRK_MM_* / BRK_CM_* macros available for decoding instructions > and the microMIPS-agnostic BRK_BUG for code such as BUG(). > >>> #define BRK_KDB 513 /* Used in KDB_ENTER() */ >>> #define BRK_MEMU 514 /* Used by FPU emulator */ >>> diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h >>> index 540c98a..b716fb9 100644 >>> --- a/arch/mips/include/asm/bug.h >>> +++ b/arch/mips/include/asm/bug.h >>> @@ -7,6 +7,10 @@ >>> #ifdef CONFIG_BUG >>> >>> #include >>> +#ifdef CONFIG_CPU_MICROMIPS >>> +#undef BRK_BUG >>> +#define BRK_BUG BRK_BUG_MM >>> +#endif >>> >> >> ...We don't need this bit. Doing an #undef risks using different >> values for BRK_BUG depending on whether or not asm/bug.h is >> included. > > And generally is not very elegant. > > Ralf > > From ralf@linux-mips.org Fri Jan 18 14:25:01 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Jan 2013 14:25:06 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:50977 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6823128Ab3ARNZBIsggt (ORCPT ); Fri, 18 Jan 2013 14:25:01 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0IDP05M027875; Fri, 18 Jan 2013 14:25:00 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0IDOxcZ027874; Fri, 18 Jan 2013 14:24:59 +0100 Date: Fri, 18 Jan 2013 14:24:59 +0100 From: Ralf Baechle To: "Steven J. Hill" Cc: linux-mips@linux-mips.org Subject: Re: [PATCH v4] OF: MIPS: sead3: Implement OF support. Message-ID: <20130118132459.GC19406@linux-mips.org> References: <1358444223-17247-1-git-send-email-sjhill@mips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1358444223-17247-1-git-send-email-sjhill@mips.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35491 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1107 Lines: 40 On Thu, Jan 17, 2013 at 11:37:03AM -0600, Steven J. Hill wrote: > From: "Steven J. Hill" > > Activate USE_OF for SEAD-3 platform. Add basic DTS file and convert > memory detection and reservations to use OF. Applied with this little patch on top: arch/mips/include/asm/mips-boards/generic.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index c01e286..3fc764a 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -20,6 +20,7 @@ #ifndef __ASM_MIPS_BOARDS_GENERIC_H #define __ASM_MIPS_BOARDS_GENERIC_H +#include #include #include #include Otherwise including generic.h might result in an error if has not been included before. @@ -87,9 +88,7 @@ extern int mips_revision_sconid; -#ifdef CONFIG_OF extern struct boot_param_header __dtb_start; -#endif There's no need to wrap this declaration. Ralf From sjhill@mips.com Fri Jan 18 18:53:34 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Jan 2013 18:53:35 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:44755 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824763Ab3ARRxeDavWM (ORCPT ); Fri, 18 Jan 2013 18:53:34 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TwG85-00043O-Gh; Fri, 18 Jan 2013 11:53:25 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2] MIPS: microMIPS: Redefine value of BRK_BUG. Date: Fri, 18 Jan 2013 11:53:20 -0600 Message-Id: <1358531600-5330-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35492 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1130 Lines: 29 From: "Steven J. Hill" The BRK_BUG value is used in the BUG and __BUG_ON inline macros. For standard MIPS cores the code in the 'tne' instruction is 10-bits long. In microMIPS, the 'tne' instruction is recoded and the code can only be 4-bits long. We change the value to 12 instead of 512 so that both classic and microMIPS kernels build. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/break.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 9161e68..51e1535 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -27,7 +27,7 @@ #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ -#define BRK_BUG 512 /* Used by BUG() */ +#define BRK_BUG 12 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ #define BRK_MEMU 514 /* Used by FPU emulator */ #define BRK_KPROBE_BP 515 /* Kprobe break */ -- 1.7.9.5 From ddaney.cavm@gmail.com Fri Jan 18 19:10:30 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Jan 2013 19:10:31 +0100 (CET) Received: from mail-pb0-f41.google.com ([209.85.160.41]:50194 "EHLO mail-pb0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824764Ab3ARSKal9S7y (ORCPT ); Fri, 18 Jan 2013 19:10:30 +0100 Received: by mail-pb0-f41.google.com with SMTP id xa7so2191471pbc.0 for ; Fri, 18 Jan 2013 10:10:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=u+4lHJt5Nwa1So+AXdCJcNmTySJ5Yv6QwstShCcRNmc=; b=N3c6V7uZFpIvZu1BtGLdKAlGP+ggeH7nICD1ByZtdmRvSmPhtwxga2XNwTesZZMe5j Vk6A3bruHPaOQBmrkBLh3OrDp4tlGvFw7i5BM7JtX3bAA0r/GzIgIq6pNRD2Tmh4v0fE pkBnYP1XIK2oSznph+5zrDlaGzk3qi+x7a+Kjcxul/OA/6OVCNZaWShascoUWdLKgIoI CtgRIC7M+lXsYsCm7fgKJA9TVT8KGPegiV34bvC0QJt0GepfNs67WoDyxOxeXj4cHFno h+cQqh1PddtS639LuA/xVW029b/nPcUpJjdhkAf5i4MrW8udua7OuS9XUliB0v/HZg68 gncw== X-Received: by 10.68.248.70 with SMTP id yk6mr7667661pbc.160.1358532624091; Fri, 18 Jan 2013 10:10:24 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id pj1sm3467323pbb.71.2013.01.18.10.10.19 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 18 Jan 2013 10:10:20 -0800 (PST) Message-ID: <50F9900A.9070804@gmail.com> Date: Fri, 18 Jan 2013 10:10:18 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Kirill A. Shutemov" , Ralf Baechle , Andrew Morton , Linus Torvalds CC: Aaro Koskinen , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-mips@linux-mips.org Subject: 3.8-rc4 build regression (was: Re: 3.8-rc1 build failure with MIPS/SPARSEMEM) References: <20121222122757.GB6847@blackmetal.musicnaut.iki.fi> <20121226003434.GA27760@otc-wbsnb-06> In-Reply-To: <20121226003434.GA27760@otc-wbsnb-06> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35493 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3667 Lines: 90 Linus, Andrew and Ralf, 3.8 doesn't build on MIPS any more. Please consider this patch ... On 12/25/2012 04:34 PM, Kirill A. Shutemov wrote: > On Sat, Dec 22, 2012 at 02:27:57PM +0200, Aaro Koskinen wrote: >> Hi, >> >> It looks like commit 816422ad76474fed8052b6f7b905a054d082e59a >> (asm-generic, mm: pgtable: consolidate zero page helpers) broke >> MIPS/SPARSEMEM build in 3.8-rc1: >> >> CHK include/generated/uapi/linux/version.h >> CHK include/generated/utsrelease.h >> Checking missing-syscalls for N32 >> CC arch/mips/kernel/asm-offsets.s >> In file included from /home/aaro/git/linux/arch/mips/include/asm/pgtable.h:388:0, >> from include/linux/mm.h:44, >> from arch/mips/kernel/asm-offsets.c:14: >> include/asm-generic/pgtable.h: In function 'my_zero_pfn': >> include/asm-generic/pgtable.h:462:9: error: implicit declaration of function 'page_to_section' [-Werror=implicit-function-declaration] >> In file included from arch/mips/kernel/asm-offsets.c:14:0: >> include/linux/mm.h: At top level: >> include/linux/mm.h:708:29: error: conflicting types for 'page_to_section' >> In file included from /home/aaro/git/linux/arch/mips/include/asm/pgtable.h:388:0, >> from include/linux/mm.h:44, >> from arch/mips/kernel/asm-offsets.c:14: >> include/asm-generic/pgtable.h:462:9: note: previous implicit declaration of 'page_to_section' was here >> cc1: some warnings being treated as errors >> make[1]: *** [arch/mips/kernel/asm-offsets.s] Error 1 >> make: *** [archprepare] Error 2 > > The patch below works for me. Could you try? > > From a123a406fdc3aee7ca0eae04b6b4a231872dbb51 Mon Sep 17 00:00:00 2001 > From: "Kirill A. Shutemov" > Date: Wed, 26 Dec 2012 03:19:55 +0300 > Subject: [PATCH] asm-generic, mm: pgtable: convert my_zero_pfn() to macros to > fix build > MIME-Version: 1.0 > Content-Type: text/plain; charset=UTF-8 > Content-Transfer-Encoding: 8bit > > On MIPS if SPARSEMEM is enabled we've got this: > > In file included from /home/kas/git/public/linux/arch/mips/include/asm/pgtable.h:552, > from include/linux/mm.h:44, > from arch/mips/kernel/asm-offsets.c:14: > include/asm-generic/pgtable.h: In function ‘my_zero_pfn’: > include/asm-generic/pgtable.h:466: error: implicit declaration of function ‘page_to_section’ > In file included from arch/mips/kernel/asm-offsets.c:14: > include/linux/mm.h: At top level: > include/linux/mm.h:738: error: conflicting types for ‘page_to_section’ > include/asm-generic/pgtable.h:466: note: previous implicit declaration of ‘page_to_section’ was here > > Due header files inter-dependencies, the only way I see to fix it is > convert my_zero_pfn() for __HAVE_COLOR_ZERO_PAGE to macros. > > Signed-off-by: Kirill A. Shutemov I arrived (independently) at the identical solution. Acked-by: David Daney > --- > include/asm-generic/pgtable.h | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h > index 701beab..5cf680a 100644 > --- a/include/asm-generic/pgtable.h > +++ b/include/asm-generic/pgtable.h > @@ -461,10 +461,8 @@ static inline int is_zero_pfn(unsigned long pfn) > return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); > } > > -static inline unsigned long my_zero_pfn(unsigned long addr) > -{ > - return page_to_pfn(ZERO_PAGE(addr)); > -} > +#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) > + > #else > static inline int is_zero_pfn(unsigned long pfn) > { > From ddaney.cavm@gmail.com Fri Jan 18 20:16:53 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Jan 2013 20:16:54 +0100 (CET) Received: from mail-da0-f49.google.com ([209.85.210.49]:41549 "EHLO mail-da0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824811Ab3ARTQxZhuMs (ORCPT ); Fri, 18 Jan 2013 20:16:53 +0100 Received: by mail-da0-f49.google.com with SMTP id v40so1749296dad.8 for ; Fri, 18 Jan 2013 11:16:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=T6YwWIa1kCDtE4E8jmcdXmY47NZ+S6gieRO3GBNO+NE=; b=ra+IZlnTeZuGor3QALwTrXCGHu3XRhuKQehe8SiVUGoLVMVNnQHzGsA7nijKZMVTpt aRF2ivZaWq8kfUvyYjEmVEMMPmw8YbY/QsafHUPVxjIUrO1yMWqbxfR8054syDEX9/Nv jRRmMVrouXNZ8yR1SRTD10LXI82Z5daHzOCyEcVLwqr3xNTGQXA8EYr1ozoexkwG7F0X pTRiQpWIbVsv+rs5OW0zJNOc7Rr4BM9dO8xcHetvWFrQ7/u9oxD8SSOUFCYuYVIXaxEe Sbh4HUwpvVNnAEbTmWS9wIFI274sgXyS+Ftaour/y8MIypsyNxghWU88KODgCUyGJLpV fcEw== X-Received: by 10.69.1.73 with SMTP id be9mr8243156pbd.116.1358536606537; Fri, 18 Jan 2013 11:16:46 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id oj5sm3554574pbb.47.2013.01.18.11.16.43 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 18 Jan 2013 11:16:45 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r0IJGgLH013618; Fri, 18 Jan 2013 11:16:42 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r0IJGgLg013617; Fri, 18 Jan 2013 11:16:42 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Fix build failure by adding definition of pfn_pmd(). Date: Fri, 18 Jan 2013 11:16:40 -0800 Message-Id: <1358536600-13584-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-archive-position: 35494 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1291 Lines: 41 From: David Daney With CONFIG_TRANSPARENT_HUGEPAGE=y and CONFIG_HUGETLBFS=y we get the following build failure: . . . CC mm/huge_memory.o mm/huge_memory.c: In function 'set_huge_zero_page': mm/huge_memory.c:780:2: error: implicit declaration of function 'pfn_pmd' [-Werror=implicit-function-declaration] mm/huge_memory.c:780:8: error: incompatible types when assigning to type 'pmd_t' from type 'int' . . . Add a definition of pfn_pmd() for 64-bit kernels (the only place huge pages are currently supported). Signed-off-by: David Daney --- Failing v3.8-rc1 and later. Ralf, please consider for 3.8. arch/mips/include/asm/pgtable-64.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index c631910..013d5f7 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -230,6 +230,7 @@ static inline void pud_clear(pud_t *pudp) #else #define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) #define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot)) +#define pfn_pmd(pfn, prot) __pmd(((pfn) << _PFN_SHIFT) | pgprot_val(prot)) #endif #define __pgd_offset(address) pgd_index(address) -- 1.7.11.7 From blogic@openwrt.org Sat Jan 19 10:57:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 19 Jan 2013 10:57:08 +0100 (CET) Received: from nbd.name ([46.4.11.11]:42354 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833241Ab3ASJ5E2Uaqa (ORCPT ); Sat, 19 Jan 2013 10:57:04 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 1/5] MIPS: lantiq: trivial typo fix Date: Sat, 19 Jan 2013 10:54:23 +0100 Message-Id: <1358589267-11514-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35495 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 748 Lines: 23 "nodes" is written with a single "s" Signed-off-by: John Crispin --- arch/mips/lantiq/xway/sysctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 3925e66..1aaa726 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -305,7 +305,7 @@ void __init ltq_soc_init(void) /* check if all the core register ranges are available */ if (!np_pmu || !np_cgu || !np_ebu) - panic("Failed to load core nodess from devicetree"); + panic("Failed to load core nodes from devicetree"); if (of_address_to_resource(np_pmu, 0, &res_pmu) || of_address_to_resource(np_cgu, 0, &res_cgu) || -- 1.7.10.4 From blogic@openwrt.org Sat Jan 19 10:57:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 19 Jan 2013 10:57:26 +0100 (CET) Received: from nbd.name ([46.4.11.11]:42356 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833244Ab3ASJ5FED6m1 (ORCPT ); Sat, 19 Jan 2013 10:57:05 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 2/5] MIPS: lantiq: adds static clock for PP32 Date: Sat, 19 Jan 2013 10:54:24 +0100 Message-Id: <1358589267-11514-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358589267-11514-1-git-send-email-blogic@openwrt.org> References: <1358589267-11514-1-git-send-email-blogic@openwrt.org> X-archive-position: 35496 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6466 Lines: 213 The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin --- arch/mips/include/asm/mach-lantiq/lantiq.h | 1 + arch/mips/lantiq/clk.c | 12 ++++++-- arch/mips/lantiq/clk.h | 7 ++++- arch/mips/lantiq/falcon/sysctrl.c | 4 +-- arch/mips/lantiq/xway/clk.c | 43 ++++++++++++++++++++++++++++ arch/mips/lantiq/xway/sysctrl.c | 12 ++++---- 6 files changed, 69 insertions(+), 10 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index 5e8a6e9..76be7a0 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -41,6 +41,7 @@ extern void clk_deactivate(struct clk *clk); extern struct clk *clk_get_cpu(void); extern struct clk *clk_get_fpi(void); extern struct clk *clk_get_io(void); +extern struct clk *clk_get_ppe(void); /* find out what bootsource we have */ extern unsigned char ltq_boot_select(void); diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index ce2f129..d903560 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -26,13 +26,15 @@ #include "prom.h" /* lantiq socs have 3 static clocks */ -static struct clk cpu_clk_generic[3]; +static struct clk cpu_clk_generic[4]; -void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io) +void clkdev_add_static(unsigned long cpu, unsigned long fpi, + unsigned long io, unsigned long ppe) { cpu_clk_generic[0].rate = cpu; cpu_clk_generic[1].rate = fpi; cpu_clk_generic[2].rate = io; + cpu_clk_generic[3].rate = ppe; } struct clk *clk_get_cpu(void) @@ -51,6 +53,12 @@ struct clk *clk_get_io(void) return &cpu_clk_generic[2]; } +struct clk *clk_get_ppe(void) +{ + return &cpu_clk_generic[3]; +} +EXPORT_SYMBOL_GPL(clk_get_ppe); + static inline int clk_good(struct clk *clk) { return clk && !IS_ERR(clk); diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h index fa67060..77e4bdb 100644 --- a/arch/mips/lantiq/clk.h +++ b/arch/mips/lantiq/clk.h @@ -27,12 +27,15 @@ #define CLOCK_167M 166666667 #define CLOCK_196_608M 196608000 #define CLOCK_200M 200000000 +#define CLOCK_222M 222000000 +#define CLOCK_240M 240000000 #define CLOCK_250M 250000000 #define CLOCK_266M 266666666 #define CLOCK_300M 300000000 #define CLOCK_333M 333333333 #define CLOCK_393M 393215332 #define CLOCK_400M 400000000 +#define CLOCK_450M 450000000 #define CLOCK_500M 500000000 #define CLOCK_600M 600000000 @@ -64,15 +67,17 @@ struct clk { }; extern void clkdev_add_static(unsigned long cpu, unsigned long fpi, - unsigned long io); + unsigned long io, unsigned long ppe); extern unsigned long ltq_danube_cpu_hz(void); extern unsigned long ltq_danube_fpi_hz(void); +extern unsigned long ltq_danube_pp32_hz(void); extern unsigned long ltq_ar9_cpu_hz(void); extern unsigned long ltq_ar9_fpi_hz(void); extern unsigned long ltq_vr9_cpu_hz(void); extern unsigned long ltq_vr9_fpi_hz(void); +extern unsigned long ltq_vr9_pp32_hz(void); #endif diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c index 2d4ced3..ff4894a 100644 --- a/arch/mips/lantiq/falcon/sysctrl.c +++ b/arch/mips/lantiq/falcon/sysctrl.c @@ -241,9 +241,9 @@ void __init ltq_soc_init(void) /* get our 3 static rates for cpu, fpi and io clocks */ if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV) - clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M); + clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0); else - clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M); + clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0); /* add our clock domains */ clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0); diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c index 9aa17f7..1ab576d 100644 --- a/arch/mips/lantiq/xway/clk.c +++ b/arch/mips/lantiq/xway/clk.c @@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void) } } +unsigned long ltq_danube_pp32_hz(void) +{ + unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3; + unsigned long clk; + + switch (clksys) { + case 1: + clk = CLOCK_240M; + break; + case 2: + clk = CLOCK_222M; + break; + case 3: + clk = CLOCK_133M; + break; + default: + clk = CLOCK_266M; + break; + } + + return clk; +} + unsigned long ltq_ar9_sys_hz(void) { if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2) @@ -149,3 +172,23 @@ unsigned long ltq_vr9_fpi_hz(void) return clk; } + +unsigned long ltq_vr9_pp32_hz(void) +{ + unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3; + unsigned long clk; + + switch (clksys) { + case 1: + clk = CLOCK_450M; + break; + case 2: + clk = CLOCK_300M; + break; + default: + clk = CLOCK_500M; + break; + } + + return clk; +} diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 1aaa726..3390fcd 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -356,14 +356,16 @@ void __init ltq_soc_init(void) if (of_machine_is_compatible("lantiq,ase")) { if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) - clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); + clkdev_add_static(CLOCK_266M, CLOCK_133M, + CLOCK_133M, CLOCK_266M); else - clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); + clkdev_add_static(CLOCK_133M, CLOCK_133M, + CLOCK_133M, CLOCK_133M); clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY), clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY); } else if (of_machine_is_compatible("lantiq,vr9")) { clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), - ltq_vr9_fpi_hz()); + ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz()); clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY); clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK); clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI); @@ -376,10 +378,10 @@ void __init ltq_soc_init(void) PMU_PPE_QSB | PMU_PPE_TOP); } else if (of_machine_is_compatible("lantiq,ar9")) { clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), - ltq_ar9_fpi_hz()); + ltq_ar9_fpi_hz(), CLOCK_250M); clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH); } else { clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), - ltq_danube_fpi_hz()); + ltq_danube_fpi_hz(), ltq_danube_pp32_hz()); } } -- 1.7.10.4 From blogic@openwrt.org Sat Jan 19 10:57:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 19 Jan 2013 10:57:43 +0100 (CET) Received: from nbd.name ([46.4.11.11]:42358 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833245Ab3ASJ5Fe4ITg (ORCPT ); Sat, 19 Jan 2013 10:57:05 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 3/5] MIPS: lantiq: add GPHY clock gate bits Date: Sat, 19 Jan 2013 10:54:25 +0100 Message-Id: <1358589267-11514-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358589267-11514-1-git-send-email-blogic@openwrt.org> References: <1358589267-11514-1-git-send-email-blogic@openwrt.org> X-archive-position: 35497 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1576 Lines: 47 Explicitly enable the clock gate of the internal GPHYs found on xrx200. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/reset.c | 9 +++++++++ arch/mips/lantiq/xway/sysctrl.c | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c index 544dbb7..1fa0f17 100644 --- a/arch/mips/lantiq/xway/reset.c +++ b/arch/mips/lantiq/xway/reset.c @@ -78,10 +78,19 @@ static struct ltq_xrx200_gphy_reset { /* reset and boot a gphy. these phys only exist on xrx200 SoC */ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr) { + struct clk *clk; + if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) { dev_err(dev, "this SoC has no GPHY\n"); return -EINVAL; } + + clk = clk_get_sys("1f203000.rcu", "gphy"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + clk_enable(clk); + if (id > 1) { dev_err(dev, "%u is an invalid gphy id\n", id); return -EINVAL; diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 3390fcd..c24924f 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -376,6 +376,7 @@ void __init ltq_soc_init(void) PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | PMU_PPE_QSB | PMU_PPE_TOP); + clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY); } else if (of_machine_is_compatible("lantiq,ar9")) { clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), ltq_ar9_fpi_hz(), CLOCK_250M); -- 1.7.10.4 From blogic@openwrt.org Sat Jan 19 10:57:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 19 Jan 2013 10:58:00 +0100 (CET) Received: from nbd.name ([46.4.11.11]:42362 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833246Ab3ASJ5GDszt3 (ORCPT ); Sat, 19 Jan 2013 10:57:06 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 4/5] MIPS: lantiq: improve pci reset gpio handling Date: Sat, 19 Jan 2013 10:54:26 +0100 Message-Id: <1358589267-11514-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358589267-11514-1-git-send-email-blogic@openwrt.org> References: <1358589267-11514-1-git-send-email-blogic@openwrt.org> X-archive-position: 35498 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1040 Lines: 34 We need to make sure that the reset gpio is available and also set a sane default state. Signed-off-by: John Crispin --- arch/mips/pci/pci-lantiq.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 9568178..f32664b 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -129,8 +129,16 @@ static int ltq_pci_startup(struct platform_device *pdev) /* setup reset gpio used by pci */ reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); - if (gpio_is_valid(reset_gpio)) - devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset"); + if (gpio_is_valid(reset_gpio)) { + int ret = devm_gpio_request(&pdev->dev, + reset_gpio, "pci-reset"); + if (ret) { + dev_err(&pdev->dev, + "failed to request gpio %d\n", reset_gpio); + return ret; + } + gpio_direction_output(reset_gpio, 1); + } /* enable auto-switching between PCI and EBU */ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); -- 1.7.10.4 From blogic@openwrt.org Sat Jan 19 10:57:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 19 Jan 2013 10:58:20 +0100 (CET) Received: from nbd.name ([46.4.11.11]:42365 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833247Ab3ASJ5Glf0FH (ORCPT ); Sat, 19 Jan 2013 10:57:06 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 5/5] MIPS: lantiq: rework external irq code Date: Sat, 19 Jan 2013 10:54:27 +0100 Message-Id: <1358589267-11514-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358589267-11514-1-git-send-email-blogic@openwrt.org> References: <1358589267-11514-1-git-send-email-blogic@openwrt.org> X-archive-position: 35499 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6152 Lines: 210 This code makes the irqs used by the EIU loadable from the DT. Additionally we add a helper that allows the pinctrl layer to map external irqs to real irq numbers. Signed-off-by: John Crispin --- arch/mips/include/asm/mach-lantiq/lantiq.h | 1 + arch/mips/lantiq/irq.c | 105 +++++++++++++++++++--------- 2 files changed, 74 insertions(+), 32 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index 76be7a0..f196cce 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -34,6 +34,7 @@ extern spinlock_t ebu_lock; extern void ltq_disable_irq(struct irq_data *data); extern void ltq_mask_and_ack_irq(struct irq_data *data); extern void ltq_enable_irq(struct irq_data *data); +extern int ltq_eiu_get_irq(int exin); /* clock handling */ extern int clk_activate(struct clk *clk); diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index f36acd1..6f84009 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -33,17 +33,10 @@ /* register definitions - external irqs */ #define LTQ_EIU_EXIN_C 0x0000 #define LTQ_EIU_EXIN_INIC 0x0004 +#define LTQ_EIU_EXIN_INC 0x0008 #define LTQ_EIU_EXIN_INEN 0x000C -/* irq numbers used by the external interrupt unit (EIU) */ -#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30) -#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31) -#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26) -#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0 -#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1) -#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2) -#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30) -#define XWAY_EXIN_COUNT 3 +/* number of external interrupts */ #define MAX_EIU 6 /* the performance counter */ @@ -72,20 +65,19 @@ int gic_present; #endif -static unsigned short ltq_eiu_irq[MAX_EIU] = { - LTQ_EIU_IR0, - LTQ_EIU_IR1, - LTQ_EIU_IR2, - LTQ_EIU_IR3, - LTQ_EIU_IR4, - LTQ_EIU_IR5, -}; - static int exin_avail; +static struct resource ltq_eiu_irq[MAX_EIU]; static void __iomem *ltq_icu_membase[MAX_IM]; static void __iomem *ltq_eiu_membase; static struct irq_domain *ltq_domain; +int ltq_eiu_get_irq(int exin) +{ + if (exin < exin_avail) + return ltq_eiu_irq[exin].start; + return -1; +} + void ltq_disable_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; @@ -128,19 +120,65 @@ void ltq_enable_irq(struct irq_data *d) ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); } +static int ltq_eiu_settype(struct irq_data *d, unsigned int type) +{ + int i; + + for (i = 0; i < MAX_EIU; i++) { + if (d->hwirq == ltq_eiu_irq[i].start) { + int val = 0; + int edge = 0; + + switch (type) { + case IRQF_TRIGGER_NONE: + break; + case IRQF_TRIGGER_RISING: + val = 1; + edge = 1; + break; + case IRQF_TRIGGER_FALLING: + val = 2; + edge = 1; + break; + case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING: + val = 3; + edge = 1; + break; + case IRQF_TRIGGER_HIGH: + val = 5; + break; + case IRQF_TRIGGER_LOW: + val = 6; + break; + default: + pr_err("invalid type %d for irq %ld\n", + type, d->hwirq); + return -EINVAL; + } + + if (edge) + irq_set_handler(d->hwirq, handle_edge_irq); + + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | + (val << (i * 4)), LTQ_EIU_EXIN_C); + } + } + + return 0; +} + static unsigned int ltq_startup_eiu_irq(struct irq_data *d) { int i; ltq_enable_irq(d); for (i = 0; i < MAX_EIU; i++) { - if (d->hwirq == ltq_eiu_irq[i]) { - /* low level - we should really handle set_type */ - ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | - (0x6 << (i * 4)), LTQ_EIU_EXIN_C); + if (d->hwirq == ltq_eiu_irq[i].start) { + /* by default we are low level triggered */ + ltq_eiu_settype(d, IRQF_TRIGGER_LOW); /* clear all pending */ - ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i), - LTQ_EIU_EXIN_INIC); + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i), + LTQ_EIU_EXIN_INC); /* enable */ ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i), LTQ_EIU_EXIN_INEN); @@ -157,7 +195,7 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d) ltq_disable_irq(d); for (i = 0; i < MAX_EIU; i++) { - if (d->hwirq == ltq_eiu_irq[i]) { + if (d->hwirq == ltq_eiu_irq[i].start) { /* disable */ ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i), LTQ_EIU_EXIN_INEN); @@ -186,6 +224,7 @@ static struct irq_chip ltq_eiu_type = { .irq_ack = ltq_ack_irq, .irq_mask = ltq_disable_irq, .irq_mask_ack = ltq_mask_and_ack_irq, + .irq_set_type = ltq_eiu_settype, }; static void ltq_hw_irqdispatch(int module) @@ -301,7 +340,7 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) return 0; for (i = 0; i < exin_avail; i++) - if (hw == ltq_eiu_irq[i]) + if (hw == ltq_eiu_irq[i].start) chip = <q_eiu_type; irq_set_chip_and_handler(hw, chip, handle_level_irq); @@ -323,7 +362,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) { struct device_node *eiu_node; struct resource res; - int i; + int i, ret; for (i = 0; i < MAX_IM; i++) { if (of_address_to_resource(node, i, &res)) @@ -340,17 +379,19 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) } /* the external interrupts are optional and xway only */ - eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu"); + eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway"); if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) { /* find out how many external irq sources we have */ - const __be32 *count = of_get_property(node, - "lantiq,count", NULL); + exin_avail = of_irq_count(eiu_node); - if (count) - exin_avail = *count; if (exin_avail > MAX_EIU) exin_avail = MAX_EIU; + ret = of_irq_to_resource_table(eiu_node, + ltq_eiu_irq, exin_avail); + if (ret != exin_avail) + panic("failed to load external irq resources\n"); + if (request_mem_region(res.start, resource_size(&res), res.name) < 0) pr_err("Failed to request eiu memory"); -- 1.7.10.4 From blogic@openwrt.org Sat Jan 19 10:58:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 19 Jan 2013 10:58:56 +0100 (CET) Received: from nbd.name ([46.4.11.11]:42440 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833241Ab3ASJ6zoO3hJ (ORCPT ); Sat, 19 Jan 2013 10:58:55 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH] MIPS: show correct cpu name for 24KEc Date: Sat, 19 Jan 2013 10:56:15 +0100 Message-Id: <1358589375-11631-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35500 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 821 Lines: 29 Make sure 24KEc is properly identified inside /proc/cpuinfo Signed-off-by: John Crispin --- arch/mips/kernel/cpu-probe.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 8db7a47..ba16902 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -841,10 +841,13 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "MIPS 20Kc"; break; case PRID_IMP_24K: - case PRID_IMP_24KE: c->cputype = CPU_24K; __cpu_name[cpu] = "MIPS 24Kc"; break; + case PRID_IMP_24KE: + c->cputype = CPU_24K; + __cpu_name[cpu] = "MIPS 24KEc"; + break; case PRID_IMP_25KF: c->cputype = CPU_25KF; __cpu_name[cpu] = "MIPS 25Kc"; -- 1.7.10.4 From arend@broadcom.com Mon Jan 21 10:41:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 21 Jan 2013 10:41:29 +0100 (CET) Received: from mms1.broadcom.com ([216.31.210.17]:3696 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823732Ab3AUJl153GnU (ORCPT ); Mon, 21 Jan 2013 10:41:27 +0100 Received: from [10.9.208.26] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 21 Jan 2013 01:38:57 -0800 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHCAS05.corp.ad.broadcom.com (10.9.208.26) with Microsoft SMTP Server id 14.1.355.2; Mon, 21 Jan 2013 01:40:59 -0800 Received: from [10.176.68.30] (unknown [10.176.68.30]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id DCA8340FE4; Mon, 21 Jan 2013 01:40:57 -0800 (PST) Message-ID: <50FD0D28.8070905@broadcom.com> Date: Mon, 21 Jan 2013 10:40:56 +0100 From: "Arend van Spriel" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: "Ralf Baechle" cc: "Sergei Shtylyov" , linux-mips@linux-mips.org, "Hauke Mehrtens" Subject: Re: [PATCH] mips: bcm47xx: select GPIOLIB for BCMA on bcm47xx platform References: <1357323005-28008-1-git-send-email-arend@broadcom.com> <50E80F78.9030901@mvista.com> <50E9E914.9030900@broadcom.com> <20130116145000.GD26569@linux-mips.org> In-Reply-To: <20130116145000.GD26569@linux-mips.org> X-Enigmail-Version: 1.4.6 X-WSS-ID: 7CE3D33B1Z4102130-01-01 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35501 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arend@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 733 Lines: 32 On 01/16/2013 03:50 PM, Ralf Baechle wrote: > On Sun, Jan 06, 2013 at 10:13:56PM +0100, Arend van Spriel wrote: > >>> This change doesn';t seem to be documented in your changelog. Maybe >>> it's worth another patch? >>> >>> WBR, Sergei >>> >> >> Very observant. ;-) Yes. After fixing the other ones I got a warning on >> that one. I could resubmit the change with a more generic description or >> split it up as you suggest. >> >> Ralf, >> >> Please advice. > > For simplicity's sake I'm going to split this myself BUT putting changes > that are not explained in changelog comments is a good way to get your > dear maintainer grumpy :) Thanks, Ralf Appreciated. Hope you can keep that smile ;-) Regards, Arend > Ralf > From thierry.reding@avionic-design.de Mon Jan 21 11:09:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 21 Jan 2013 11:09:52 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.17.10]:55459 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833282Ab3AUKJuWAQp0 (ORCPT ); Mon, 21 Jan 2013 11:09:50 +0100 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap1) with ESMTP (Nemesis) id 0MM0ZY-1TpWfy2YVY-008Dqg; Mon, 21 Jan 2013 11:09:35 +0100 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 04F232A28162; Mon, 21 Jan 2013 11:09:33 +0100 (CET) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pMW0sufz4i0W; Mon, 21 Jan 2013 11:09:30 +0100 (CET) Received: from mailman.adnet.avionic-design.de (mailman.adnet.avionic-design.de [172.20.31.172]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id D0B1E2A28164; Mon, 21 Jan 2013 11:09:26 +0100 (CET) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) by mailman.adnet.avionic-design.de (Postfix) with ESMTP id 15B5910081C; Mon, 21 Jan 2013 11:09:23 +0100 (CET) From: Thierry Reding To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , Dmitry Torokhov , Arnd Bergmann , Wolfram Sang , Ralf Baechle , linux-mips@linux-mips.org Subject: [PATCH 03/33] MIPS: Convert to devm_ioremap_resource() Date: Mon, 21 Jan 2013 11:08:56 +0100 Message-Id: <1358762966-20791-4-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.8.1.1 In-Reply-To: <1358762966-20791-1-git-send-email-thierry.reding@avionic-design.de> References: <1358762966-20791-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:G56bKa1q85yUSC5wKFRWGTzobspycbJI9P3mIEzhaXh ruC3P8EYVbOoZXaJ9l5e9tvMrh9y8otsjKx1yDhJFx6N8cDCqJ VwtqkYzFc3wxELLQQT+Ku6Q64bVLKXyKGe7uAjknIO8V45YLq2 vBm2KS3D6n2csGbbflb+tb2BcgLvdS6qsoPhi1PTWTSCkJiCTQ vFNDQnRuDvPZNJZbi9uWa9c7dj7sy5MIkuz1jcFGr/EkFqJ98p quQIhvrb4f8jlYeEMR14RU+RYD+mXoWlSrTIHxv1noSLtMkTPX zAQE0qacSnm/eTy/v2xwPLSFi+vfDqXMVreXEYWkbFNuqSUWgJ u3wD1rJCqw1G2wj55XQqKJNJ7IA4HE37ijml6m0bZvLesub+/A F/CEC2g0FLFe5OHFSvm+QqZpBrNnxuYXasexP6MaWnba5rkqxJ zWkag X-archive-position: 35502 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2823 Lines: 84 Convert all uses of devm_request_and_ioremap() to the newly introduced devm_ioremap_resource() which provides more consistent error handling. devm_ioremap_resource() provides its own error messages so all explicit error messages can be removed from the failure code paths. Signed-off-by: Thierry Reding Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/lantiq/xway/dma.c | 5 +++-- arch/mips/lantiq/xway/gptu.c | 8 +++----- arch/mips/pci/pci-lantiq.c | 12 ++++++------ 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index e44a186..08f7ebd 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -223,8 +224,8 @@ ltq_dma_init(struct platform_device *pdev) panic("Failed to get dma resource"); /* remap dma register range */ - ltq_dma_membase = devm_request_and_ioremap(&pdev->dev, res); - if (!ltq_dma_membase) + ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ltq_dma_membase)) panic("Failed to remap dma resource"); /* power up and reset the dma engine */ diff --git a/arch/mips/lantiq/xway/gptu.c b/arch/mips/lantiq/xway/gptu.c index e30b1ed..9861c86 100644 --- a/arch/mips/lantiq/xway/gptu.c +++ b/arch/mips/lantiq/xway/gptu.c @@ -150,11 +150,9 @@ static int gptu_probe(struct platform_device *pdev) } /* remap gptu register range */ - gptu_membase = devm_request_and_ioremap(&pdev->dev, res); - if (!gptu_membase) { - dev_err(&pdev->dev, "Failed to remap resource\n"); - return -ENOMEM; - } + gptu_membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(gptu_membase)) + return PTR_ERR(gptu_membase); /* enable our clock */ clk = clk_get(&pdev->dev, NULL); diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 9568178..910fb4c 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -214,13 +214,13 @@ static int ltq_pci_probe(struct platform_device *pdev) return -EINVAL; } - ltq_pci_membase = devm_request_and_ioremap(&pdev->dev, res_bridge); - ltq_pci_mapped_cfg = devm_request_and_ioremap(&pdev->dev, res_cfg); + ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge); + if (IS_ERR(ltq_pci_membase)) + return PTR_ERR(ltq_pci_membase); - if (!ltq_pci_membase || !ltq_pci_mapped_cfg) { - dev_err(&pdev->dev, "failed to remap resources\n"); - return -ENOMEM; - } + ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg); + if (IS_ERR(ltq_pci_mapped_cfg)) + return PTR_ERR(ltq_pci_mapped_cfg); ltq_pci_startup(pdev); -- 1.8.1.1 From aaro.koskinen@iki.fi Mon Jan 21 12:19:28 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 21 Jan 2013 12:19:30 +0100 (CET) Received: from filtteri5.pp.htv.fi ([213.243.153.188]:43246 "EHLO filtteri5.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816206Ab3AULT2oKAto (ORCPT ); Mon, 21 Jan 2013 12:19:28 +0100 Received: from localhost (localhost [127.0.0.1]) by filtteri5.pp.htv.fi (Postfix) with ESMTP id 036055A6CF1; Mon, 21 Jan 2013 13:19:28 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp5.welho.com ([213.243.153.39]) by localhost (filtteri5.pp.htv.fi [213.243.153.188]) (amavisd-new, port 10024) with ESMTP id 4H-b3NrZYoz4; Mon, 21 Jan 2013 13:19:27 +0200 (EET) Received: from blackmetal.pp.htv.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp5.welho.com (Postfix) with ESMTP id 985F15BC003; Mon, 21 Jan 2013 13:19:27 +0200 (EET) From: Aaro Koskinen To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Aaro Koskinen Subject: [PATCH] MIPS: fix 64-bit kernel build Date: Mon, 21 Jan 2013 13:19:19 +0200 Message-Id: <1358767159-19585-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35503 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2117 Lines: 64 Commit d3ce88431892b703b04769566338a89eda6b0477 (MIPS: Fix modpost error in modules attepting to use virt_addr_valid()) in 3.8-rc3 broke the 64-bit MIPS build: LD init/built-in.o kernel/built-in.o: In function `memory_bm_free': snapshot.c:(.text+0x3c76c): undefined reference to `__virt_addr_valid' snapshot.c:(.text+0x3c800): undefined reference to `__virt_addr_valid' kernel/built-in.o: In function `snapshot_write_next': (.text+0x3e094): undefined reference to `__virt_addr_valid' kernel/built-in.o: In function `snapshot_write_next': (.text+0x3e468): undefined reference to `__virt_addr_valid' Fix by providing __virt_addr_valid also when CONFIG_32BIT is not set. Signed-off-by: Aaro Koskinen --- arch/mips/mm/Makefile | 6 +++--- arch/mips/mm/ioremap.c | 4 ++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 90ceb963..cbfec8c 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -3,10 +3,10 @@ # obj-y += cache.o dma-default.o extable.o fault.o \ - gup.o init.o mmap.o page.o page-funcs.o \ - tlbex.o tlbex-fault.o uasm.o + gup.o init.o ioremap.o mmap.o page.o \ + page-funcs.o tlbex.o tlbex-fault.o uasm.o -obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o +obj-$(CONFIG_32BIT) += pgtable-32.o obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c index 7657fd2..a7a14e3 100644 --- a/arch/mips/mm/ioremap.c +++ b/arch/mips/mm/ioremap.c @@ -16,6 +16,8 @@ #include #include +#ifdef CONFIG_32BIT + static inline void remap_area_pte(pte_t * pte, unsigned long address, phys_t size, phys_t phys_addr, unsigned long flags) { @@ -191,6 +193,8 @@ void __iounmap(const volatile void __iomem *addr) EXPORT_SYMBOL(__ioremap); EXPORT_SYMBOL(__iounmap); +#endif /* CONFIG_32BIT */ + int __virt_addr_valid(const volatile void *kaddr) { return pfn_valid(PFN_DOWN(virt_to_phys(kaddr))); -- 1.7.10.4 From ralf@linux-mips.org Tue Jan 22 12:54:47 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Jan 2013 12:54:54 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:35672 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6825653Ab3AVLyracLpZ (ORCPT ); Tue, 22 Jan 2013 12:54:47 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0MBsiBu031340; Tue, 22 Jan 2013 12:54:44 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0MBshFc031333; Tue, 22 Jan 2013 12:54:43 +0100 Date: Tue, 22 Jan 2013 12:54:43 +0100 From: Ralf Baechle To: John Stultz Cc: Yong Zhang , linux-mips@linux-mips.org Subject: Re: Any NXP PNX user left (was: Re: pnx_clocksource broken?) Message-ID: <20130122115443.GB14944@linux-mips.org> References: <4F84E531.3010001@linaro.org> <20120416140040.GA2378@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120416140040.GA2378@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35504 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 988 Lines: 24 On Mon, Apr 16, 2012 at 04:00:40PM +0200, Ralf Baechle wrote: > > Looking at arch/mips/pnx8550/common/time.c the pnx_clocksource never > > seems to be assigned a mult/shift value before it calls > > clocksource_register(). Clearly this is broken and I suspect this > > clocksource is never used. > > > > I was hoping to convert this driver over (its the last of 3 > > remaining) to use clocksource_register_hz/khz() but I'm not sure > > what the actual frequency of the hardware should be. Is > > mips_hpt_frequency the right value here? > > > > Even so, if this is clocksource is never used, should it just be removed? > > Iow PNX has not had a functioning clocksource for a very long time. Equally > there has not been any user feedback for ages and I wonder if that makes the > PNX code a candidate for removal. > > Any remaining PNX users should raise their voice now or PNX will be > toast. Soon. Not soon at all but nobody's answered so I've removed all of PNX8550. Ralf From zajec5@gmail.com Wed Jan 23 11:45:24 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 11:45:26 +0100 (CET) Received: from mail-we0-f180.google.com ([74.125.82.180]:45690 "EHLO mail-we0-f180.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831954Ab3AWKpYVL0pg convert rfc822-to-8bit (ORCPT ); Wed, 23 Jan 2013 11:45:24 +0100 Received: by mail-we0-f180.google.com with SMTP id k14so538581wer.25 for ; Wed, 23 Jan 2013 02:45:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:date:message-id:subject:from:to :content-type:content-transfer-encoding; bh=6IM1K/YzQZDjtonWJ51mhRaX2H25MVyWq5sY7hXUC0Y=; b=t1d0w2yqfflVTR37SrTdXIpac5U4YVFvIftyAfbsDWRi1SQI4rfRG/tqsBpOocn4Sd PT+nzNDAR9zF3BsUn0jKO0yjhNcHRhhKffLmNFUQo8gYM8zgrI+OuLgHovPWOH+37+Yq +iHLy2pDTKUAsdL4SseBN6CPezXUEQMVZtD0ilA6JOl5M8+QT3r2NghevA9YIXmIPngH qy1HX4/JB+wqIqQikiTrhS6wWxLWG27M6WHcrhh739oTf3FVMVN8q/PfzQDzn7xIhb9R BSvEkpE8+V2p7fKR/xi0TlUmP/5NpchKCXdNNWFffto692WmceMwdgm2zEP25zLpE0Z5 Dbkg== MIME-Version: 1.0 X-Received: by 10.180.20.138 with SMTP id n10mr31027020wie.0.1358937917261; Wed, 23 Jan 2013 02:45:17 -0800 (PST) Received: by 10.216.72.134 with HTTP; Wed, 23 Jan 2013 02:45:16 -0800 (PST) Date: Wed, 23 Jan 2013 11:45:16 +0100 Message-ID: Subject: git (linux-queue.git) not available: access denied or repository not exported From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 35505 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zajec5@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 257 Lines: 9 # git clone git://git.linux-mips.org/pub/scm/ralf/linux-queue.git Cloning into 'linux-queue'... fatal: remote error: access denied or repository not exported: /pub/scm/ralf/linux-queue.git I've tried this on two machines. Is there some mirror? -- RafaÅ‚ From blogic@openwrt.org Wed Jan 23 13:08:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:08:44 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52008 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831954Ab3AWMIl1Ay7c (ORCPT ); Wed, 23 Jan 2013 13:08:41 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 00/11] MIPS: ralink: adds support for ralink platform Date: Wed, 23 Jan 2013 13:05:44 +0100 Message-Id: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35506 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2735 Lines: 58 This series adds support for the ralink SoC family. Currently RT305X type SoC is supported. RT2880/3883 are in my local queue already but require further testing. John Crispin (11): MIPS: allow platforms to override cp0_compare_irq MIPS: ralink: adds include files MIPS: ralink: adds irq code MIPS: ralink: adds reset code MIPS: ralink: adds prom and cmdline code MIPS: ralink: adds clkdev code MIPS: ralink: adds OF code MIPS: ralink: adds early_printk support MIPS: ralink: adds support for RT305x SoC family MIPS: ralink: adds rt305x devicetree MIPS: ralink: adds Kbuild files arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 19 +- arch/mips/include/asm/mach-ralink/ralink_regs.h | 39 ++++ arch/mips/include/asm/mach-ralink/rt305x.h | 139 ++++++++++++++ arch/mips/include/asm/mach-ralink/war.h | 25 +++ arch/mips/include/asm/time.h | 1 + arch/mips/kernel/traps.c | 7 +- arch/mips/ralink/Kconfig | 27 +++ arch/mips/ralink/Makefile | 15 ++ arch/mips/ralink/Platform | 11 ++ arch/mips/ralink/clk.c | 72 +++++++ arch/mips/ralink/common.h | 43 +++++ arch/mips/ralink/dts/Makefile | 1 + arch/mips/ralink/dts/rt305x.dts | 156 +++++++++++++++ arch/mips/ralink/early_printk.c | 43 +++++ arch/mips/ralink/irq.c | 182 ++++++++++++++++++ arch/mips/ralink/of.c | 105 +++++++++++ arch/mips/ralink/prom.c | 69 +++++++ arch/mips/ralink/reset.c | 44 +++++ arch/mips/ralink/rt305x.c | 231 +++++++++++++++++++++++ 20 files changed, 1228 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/mach-ralink/ralink_regs.h create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h create mode 100644 arch/mips/include/asm/mach-ralink/war.h create mode 100644 arch/mips/ralink/Kconfig create mode 100644 arch/mips/ralink/Makefile create mode 100644 arch/mips/ralink/Platform create mode 100644 arch/mips/ralink/clk.c create mode 100644 arch/mips/ralink/common.h create mode 100644 arch/mips/ralink/dts/Makefile create mode 100644 arch/mips/ralink/dts/rt305x.dts create mode 100644 arch/mips/ralink/early_printk.c create mode 100644 arch/mips/ralink/irq.c create mode 100644 arch/mips/ralink/of.c create mode 100644 arch/mips/ralink/prom.c create mode 100644 arch/mips/ralink/reset.c create mode 100644 arch/mips/ralink/rt305x.c -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:08:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:09:03 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52010 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833383Ab3AWMIlyA7bx (ORCPT ); Wed, 23 Jan 2013 13:08:41 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 01/11] MIPS: allow platforms to override cp0_compare_irq Date: Wed, 23 Jan 2013 13:05:45 +0100 Message-Id: <1358942755-25371-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35507 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1676 Lines: 49 Ralink SoC needs to be able to override cp0_compare_irq. We do this similar to the way in which how cp0_compare_int can be overridden. Signed-off-by: John Crispin --- arch/mips/include/asm/time.h | 1 + arch/mips/kernel/traps.c | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index 761f2e9..c5ad468 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -51,6 +51,7 @@ extern int (*perf_irq)(void); * Initialize the calling CPU's compare interrupt as clockevent device */ extern unsigned int __weak get_c0_compare_int(void); +extern unsigned int __weak get_c0_compare_irq(void); extern int r4k_clockevent_init(void); static inline int mips_clockevent_init(void) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index cf7ac54..260d7f6 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -55,6 +55,7 @@ #include #include #include +#include extern void check_wait(void); extern asmlinkage void r4k_wait(void); @@ -1616,7 +1617,11 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) */ if (cpu_has_mips_r2) { cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; - cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; + if (get_c0_compare_irq) + cp0_compare_irq = get_c0_compare_irq(); + else + cp0_compare_irq = + (read_c0_intctl() >> INTCTLB_IPTI) & 7; cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; if (cp0_perfcount_irq == cp0_compare_irq) cp0_perfcount_irq = -1; -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:08:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:09:23 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52012 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833386Ab3AWMImNigr0 (ORCPT ); Wed, 23 Jan 2013 13:08:42 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 02/11] MIPS: ralink: adds include files Date: Wed, 23 Jan 2013 13:05:46 +0100 Message-Id: <1358942755-25371-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35508 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4082 Lines: 140 Before we start adding the platform code we add the common include files. Signed-off-by: John Crispin --- arch/mips/include/asm/mach-ralink/ralink_regs.h | 39 ++++++++++++++++++++ arch/mips/include/asm/mach-ralink/war.h | 25 +++++++++++++ arch/mips/ralink/common.h | 43 +++++++++++++++++++++++ 3 files changed, 107 insertions(+) create mode 100644 arch/mips/include/asm/mach-ralink/ralink_regs.h create mode 100644 arch/mips/include/asm/mach-ralink/war.h create mode 100644 arch/mips/ralink/common.h diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h new file mode 100644 index 0000000..5a508f9 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h @@ -0,0 +1,39 @@ +/* + * Ralink SoC register definitions + * + * Copyright (C) 2013 John Crispin + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RALINK_REGS_H_ +#define _RALINK_REGS_H_ + +extern __iomem void *rt_sysc_membase; +extern __iomem void *rt_memc_membase; + +static inline void rt_sysc_w32(u32 val, unsigned reg) +{ + __raw_writel(val, rt_sysc_membase + reg); +} + +static inline u32 rt_sysc_r32(unsigned reg) +{ + return __raw_readl(rt_sysc_membase + reg); +} + +static inline void rt_memc_w32(u32 val, unsigned reg) +{ + __raw_writel(val, rt_memc_membase + reg); +} + +static inline u32 rt_memc_r32(unsigned reg) +{ + return __raw_readl(rt_memc_membase + reg); +} + +#endif /* _RALINK_REGS_H_ */ diff --git a/arch/mips/include/asm/mach-ralink/war.h b/arch/mips/include/asm/mach-ralink/war.h new file mode 100644 index 0000000..a7b712c --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_RALINK_WAR_H +#define __ASM_MACH_RALINK_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_RALINK_WAR_H */ diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h new file mode 100644 index 0000000..8c751f5 --- /dev/null +++ b/arch/mips/ralink/common.h @@ -0,0 +1,43 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2013 John Crispin + */ + +#ifndef _RALINK_COMMON_H__ +#define _RALINK_COMMON_H__ + +#define RAMIPS_SYS_TYPE_LEN 0x100 + +struct ralink_pinmux_grp { + const char *name; + u32 mask; + int gpio_first; + int gpio_last; +}; + +struct ralink_pinmux { + struct ralink_pinmux_grp *mode; + struct ralink_pinmux_grp *uart; + int uart_shift; + void (*wdt_reset)(void); +}; +extern struct ralink_pinmux gpio_pinmux; + +struct ralink_soc_info { + unsigned char *name; + unsigned char sys_type[RAMIPS_SYS_TYPE_LEN]; + unsigned char *compatible; +}; +extern struct ralink_soc_info soc_info; + +extern void ralink_of_remap(void); + +extern void ralink_clk_init(void); +extern void ralink_clk_add(const char *dev, unsigned long rate); + +extern void prom_soc_init(struct ralink_soc_info *soc_info); + +#endif /* _RALINK_COMMON_H__ */ -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:08:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:09:42 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52014 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833395Ab3AWMImeOaEY (ORCPT ); Wed, 23 Jan 2013 13:08:42 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 03/11] MIPS: ralink: adds irq code Date: Wed, 23 Jan 2013 13:05:47 +0100 Message-Id: <1358942755-25371-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35509 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4831 Lines: 200 All of the Ralink Wifi SoC currently supported by this series share the same interrupt controller (INTC). Signed-off-by: John Crispin --- arch/mips/ralink/irq.c | 182 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 182 insertions(+) create mode 100644 arch/mips/ralink/irq.c diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c new file mode 100644 index 0000000..f858d5d --- /dev/null +++ b/arch/mips/ralink/irq.c @@ -0,0 +1,182 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2009 Gabor Juhos + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" + +/* INTC register offsets */ +#define INTC_REG_STATUS0 0x00 +#define INTC_REG_STATUS1 0x04 +#define INTC_REG_TYPE 0x20 +#define INTC_REG_RAW_STATUS 0x30 +#define INTC_REG_ENABLE 0x34 +#define INTC_REG_DISABLE 0x38 + +#define INTC_INT_GLOBAL BIT(31) +#define INTC_IRQ_COUNT 32 + +#define RALINK_CPU_IRQ_BASE 0 + +#define RALINK_CPU_IRQ_INTC (RALINK_CPU_IRQ_BASE + 2) +#define RALINK_CPU_IRQ_FE (RALINK_CPU_IRQ_BASE + 5) +#define RALINK_CPU_IRQ_WIFI (RALINK_CPU_IRQ_BASE + 6) +#define RALINK_CPU_IRQ_COUNTER (RALINK_CPU_IRQ_BASE + 7) + +/* we have a cascade of 8 irqs */ +#define MIPS_CPU_IRQ_CASCADE 8 + +/* we have 32 SoC irqs */ +#define RALINK_INTC_IRQ_COUNT 32 + +#define RALINK_INTC_IRQ_PERFC (MIPS_CPU_IRQ_CASCADE + 9) + +static void __iomem *rt_intc_membase; + +static inline void rt_intc_w32(u32 val, unsigned reg) +{ + __raw_writel(val, rt_intc_membase + reg); +} + +static inline u32 rt_intc_r32(unsigned reg) +{ + return __raw_readl(rt_intc_membase + reg); +} + +static void ralink_intc_irq_unmask(struct irq_data *d) +{ + unsigned int irq = d->irq - MIPS_CPU_IRQ_CASCADE; + + rt_intc_w32((1 << irq), INTC_REG_ENABLE); +} + +static void ralink_intc_irq_mask(struct irq_data *d) +{ + unsigned int irq = d->irq - MIPS_CPU_IRQ_CASCADE; + + rt_intc_w32((1 << irq), INTC_REG_DISABLE); +} + +static struct irq_chip ralink_intc_irq_chip = { + .name = "INTC", + .irq_unmask = ralink_intc_irq_unmask, + .irq_mask = ralink_intc_irq_mask, + .irq_mask_ack = ralink_intc_irq_mask, +}; + +static struct irqaction ralink_intc_irqaction = { + .handler = no_action, + .name = "cascade [INTC]", +}; + +unsigned int __cpuinit get_c0_compare_irq(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void ralink_intc_dispatch(void) +{ + u32 pending = rt_intc_r32(INTC_REG_STATUS0); + + do_IRQ((int)(__ffs(pending) + MIPS_CPU_IRQ_CASCADE)); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long pending; + + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(RALINK_CPU_IRQ_COUNTER); + + else if (pending & STATUSF_IP5) + do_IRQ(RALINK_CPU_IRQ_FE); + + else if (pending & STATUSF_IP6) + do_IRQ(RALINK_CPU_IRQ_WIFI); + + else if (pending & STATUSF_IP2) + ralink_intc_dispatch(); + + else + spurious_interrupt(); +} + +static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + if (hw < MIPS_CPU_IRQ_CASCADE) + return 0; + + irq_set_chip_and_handler(hw, &ralink_intc_irq_chip, handle_level_irq); + + return 0; +} + +static const struct irq_domain_ops irq_domain_ops = { + .xlate = irq_domain_xlate_onetwocell, + .map = intc_map, +}; + +int __init intc_of_init(struct device_node *node, struct device_node *parent) +{ + struct resource res; + + mips_cpu_irq_init(); + + if (of_address_to_resource(node, 0, &res)) + panic("Failed to get intc memory range"); + + if (request_mem_region(res.start, resource_size(&res), + res.name) < 0) + pr_err("Failed to request intc memory"); + + rt_intc_membase = ioremap_nocache(res.start, + resource_size(&res)); + if (!rt_intc_membase) + panic("Failed to remap intc memory"); + + /* disable all interrupts */ + rt_intc_w32(~0, INTC_REG_DISABLE); + + /* route all INTC interrupts to MIPS HW0 interrupt */ + rt_intc_w32(0, INTC_REG_TYPE); + + setup_irq(RALINK_CPU_IRQ_INTC, &ralink_intc_irqaction); + + irq_domain_add_linear(node, + MIPS_CPU_IRQ_CASCADE + RALINK_INTC_IRQ_COUNT, + &irq_domain_ops, 0); + + rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE); + + cp0_perfcount_irq = RALINK_INTC_IRQ_PERFC; + + return 0; +} + +static struct of_device_id __initdata of_irq_ids[] = { + { .compatible = "ralink,intc", .data = intc_of_init }, + {}, +}; + +void __init arch_init_irq(void) +{ + of_irq_init(of_irq_ids); +} + -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:08:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:10:01 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52016 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833392Ab3AWMInEEPyI (ORCPT ); Wed, 23 Jan 2013 13:08:43 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 04/11] MIPS: ralink: adds reset code Date: Wed, 23 Jan 2013 13:05:48 +0100 Message-Id: <1358942755-25371-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35510 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1495 Lines: 61 Resetting these SoCs requires no real magic. The code is straight forward. Signed-off-by: John Crispin --- arch/mips/ralink/reset.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/mips/ralink/reset.c diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c new file mode 100644 index 0000000..22120e5 --- /dev/null +++ b/arch/mips/ralink/reset.c @@ -0,0 +1,44 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2013 John Crispin + */ + +#include +#include + +#include + +#include + +/* Reset Control */ +#define SYSC_REG_RESET_CTRL 0x034 +#define RSTCTL_RESET_SYSTEM BIT(0) + +static void ralink_restart(char *command) +{ + local_irq_disable(); + rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL); + unreachable(); +} + +static void ralink_halt(void) +{ + local_irq_disable(); + unreachable(); +} + +static int __init mips_reboot_setup(void) +{ + _machine_restart = ralink_restart; + _machine_halt = ralink_halt; + pm_power_off = ralink_halt; + + return 0; +} + +arch_initcall(mips_reboot_setup); -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:08:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:10:20 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52021 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833396Ab3AWMIniwO8U (ORCPT ); Wed, 23 Jan 2013 13:08:43 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 05/11] MIPS: ralink: adds prom and cmdline code Date: Wed, 23 Jan 2013 13:05:49 +0100 Message-Id: <1358942755-25371-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35511 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2006 Lines: 86 Add minimal code to handle commandlines. Signed-off-by: John Crispin --- arch/mips/ralink/prom.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 arch/mips/ralink/prom.c diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c new file mode 100644 index 0000000..49238d3 --- /dev/null +++ b/arch/mips/ralink/prom.c @@ -0,0 +1,69 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2009 Gabor Juhos + * Copyright (C) 2010 Joonas Lahtinen + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include + +#include +#include + +#include "common.h" + +struct ralink_soc_info soc_info; + +const char *get_system_type(void) +{ + return soc_info.sys_type; +} + +static __init void prom_init_cmdline(int argc, char **argv) +{ + int i; + + pr_debug("prom: fw_arg0=%08x fw_arg1=%08x fw_arg2=%08x fw_arg3=%08x\n", + (unsigned int)fw_arg0, (unsigned int)fw_arg1, + (unsigned int)fw_arg2, (unsigned int)fw_arg3); + + argc = fw_arg0; + argv = (char **) KSEG1ADDR(fw_arg1); + + if (!argv) { + pr_debug("argv=%p is invalid, skipping\n", + argv); + return; + } + + for (i = 0; i < argc; i++) { + char *p = (char *) KSEG1ADDR(argv[i]); + + if (CPHYSADDR(p) && *p) { + pr_debug("argv[%d]: %s\n", i, p); + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + } + } +} + +void __init prom_init(void) +{ + int argc; + char **argv; + + prom_soc_init(&soc_info); + + pr_info("CPU Type: %s\n", get_system_type()); + + prom_init_cmdline(argc, argv); +} + +void __init prom_free_prom_memory(void) +{ +} -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:08:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:10:39 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52025 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833398Ab3AWMIoTFhnX (ORCPT ); Wed, 23 Jan 2013 13:08:44 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 06/11] MIPS: ralink: adds clkdev code Date: Wed, 23 Jan 2013 13:05:50 +0100 Message-Id: <1358942755-25371-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35512 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1941 Lines: 90 These SoCs have a limited number of fixed rate clocks. Add support for the clk and clkdev api. Signed-off-by: John Crispin --- arch/mips/ralink/clk.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 arch/mips/ralink/clk.c diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c new file mode 100644 index 0000000..8dfa22f --- /dev/null +++ b/arch/mips/ralink/clk.c @@ -0,0 +1,72 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Gabor Juhos + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "common.h" + +struct clk { + struct clk_lookup cl; + unsigned long rate; +}; + +void ralink_clk_add(const char *dev, unsigned long rate) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + if (!clk) + panic("failed to add clock\n"); + + clk->cl.dev_id = dev; + clk->cl.clk = clk; + + clk->rate = rate; + + clkdev_add(&clk->cl); +} + +/* + * Linux clock API + */ +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL_GPL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL_GPL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL_GPL(clk_get_rate); + +void __init plat_time_init(void) +{ + struct clk *clk; + + ralink_of_remap(); + + ralink_clk_init(); + clk = clk_get_sys("cpu", NULL); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); + mips_hpt_frequency = clk_get_rate(clk) / 2; + clk_put(clk); +} -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:08:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:10:58 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52031 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833397Ab3AWMIo4CqDi (ORCPT ); Wed, 23 Jan 2013 13:08:44 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 07/11] MIPS: ralink: adds OF code Date: Wed, 23 Jan 2013 13:05:51 +0100 Message-Id: <1358942755-25371-8-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35513 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3428 Lines: 124 Until there is a generic MIPS way of handing the DTB over from bootloader to kernel we rely on a built in devicetrees. The OF code also remaps those register ranges that we use global in our drivers. Signed-off-by: John Crispin --- arch/mips/ralink/of.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/mips/ralink/of.c diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c new file mode 100644 index 0000000..02814b3 --- /dev/null +++ b/arch/mips/ralink/of.c @@ -0,0 +1,105 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" + +__iomem void *rt_sysc_membase; +__iomem void *rt_memc_membase; + +extern struct boot_param_header __dtb_start; + +void __init ralink_of_remap(void) +{ + struct resource res_sysc, res_memc; + struct device_node *np_sysc = + of_find_compatible_node(NULL, NULL, "ralink,sysc"); + struct device_node *np_memc = + of_find_compatible_node(NULL, NULL, "ralink,memc"); + + if (!np_sysc || !np_memc) + panic("Failed to load core nodes from devicetree"); + + if (of_address_to_resource(np_sysc, 0, &res_sysc) || + of_address_to_resource(np_memc, 0, &res_memc)) + panic("Failed to get core resources"); + + if ((request_mem_region(res_sysc.start, resource_size(&res_sysc), + res_sysc.name) < 0) || + (request_mem_region(res_memc.start, resource_size(&res_memc), + res_memc.name) < 0)) + pr_err("Failed to request core resources"); + + rt_sysc_membase = ioremap_nocache(res_sysc.start, + resource_size(&res_sysc)); + rt_memc_membase = ioremap_nocache(res_memc.start, + resource_size(&res_memc)); + + if (!rt_sysc_membase || !rt_memc_membase) + panic("Failed to remap core resources"); +} + +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(KSEG1); + + /* + * Load the builtin devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + __dt_setup_arch(&__dtb_start); +} + +static int __init plat_of_setup(void) +{ + static struct of_device_id of_ids[3]; + int len = sizeof(of_ids[0].compatible); + + if (!of_have_populated_dt()) + panic("device tree not present"); + + strncpy(of_ids[0].compatible, soc_info.compatible, len); + strncpy(of_ids[1].compatible, "palmbus", len); + + if (of_platform_populate(NULL, of_ids, NULL, NULL)) + panic("failed to populate DT\n"); + + return 0; +} + +arch_initcall(plat_of_setup); -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:08:45 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:11:16 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52039 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833401Ab3AWMIp2Bw-o (ORCPT ); Wed, 23 Jan 2013 13:08:45 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 08/11] MIPS: ralink: adds early_printk support Date: Wed, 23 Jan 2013 13:05:52 +0100 Message-Id: <1358942755-25371-9-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35514 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1648 Lines: 60 Add the code needed to make early printk work. Signed-off-by: John Crispin --- arch/mips/ralink/early_printk.c | 43 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 arch/mips/ralink/early_printk.c diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c new file mode 100644 index 0000000..c610084 --- /dev/null +++ b/arch/mips/ralink/early_printk.c @@ -0,0 +1,43 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011-2012 Gabor Juhos + */ + +#include +#include + +#include + +/* UART registers */ +#define EARLY_UART_BASE 0x10000c00 + +#define UART_REG_RX 0 +#define UART_REG_TX 1 +#define UART_REG_IER 2 +#define UART_REG_IIR 3 +#define UART_REG_FCR 4 +#define UART_REG_LCR 5 +#define UART_REG_MCR 6 +#define UART_REG_LSR 7 + +static inline void uart_w32(u32 val, unsigned reg) +{ + __raw_writel((val), + (void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg))); +} + +static inline u32 uart_r32(unsigned reg) +{ + return __raw_readl( + (void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg))); +} + +void prom_putchar(unsigned char ch) +{ + while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0); + uart_w32(UART_REG_TX, ch); + while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0); +} -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:08:46 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:11:38 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52041 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833400Ab3AWMIqPZIp5 (ORCPT ); Wed, 23 Jan 2013 13:08:46 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 09/11] MIPS: ralink: adds support for RT305x SoC family Date: Wed, 23 Jan 2013 13:05:53 +0100 Message-Id: <1358942755-25371-10-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35515 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10970 Lines: 397 Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin --- arch/mips/include/asm/mach-ralink/rt305x.h | 139 +++++++++++++++++ arch/mips/ralink/rt305x.c | 231 ++++++++++++++++++++++++++++ 2 files changed, 370 insertions(+) create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h create mode 100644 arch/mips/ralink/rt305x.c diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h new file mode 100644 index 0000000..7d344f2 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -0,0 +1,139 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2013 John Crispin + */ + +#ifndef _RT305X_REGS_H_ +#define _RT305X_REGS_H_ + +enum rt305x_soc_type { + RT305X_SOC_UNKNOWN = 0, + RT305X_SOC_RT3050, + RT305X_SOC_RT3052, + RT305X_SOC_RT3350, + RT305X_SOC_RT3352, + RT305X_SOC_RT5350, +}; + +extern enum rt305x_soc_type rt305x_soc; + +static inline int soc_is_rt3050(void) +{ + return rt305x_soc == RT305X_SOC_RT3050; +} + +static inline int soc_is_rt3052(void) +{ + return rt305x_soc == RT305X_SOC_RT3052; +} + +static inline int soc_is_rt305x(void) +{ + return soc_is_rt3050() || soc_is_rt3052(); +} + +static inline int soc_is_rt3350(void) +{ + return rt305x_soc == RT305X_SOC_RT3350; +} + +static inline int soc_is_rt3352(void) +{ + return rt305x_soc == RT305X_SOC_RT3352; +} + +static inline int soc_is_rt5350(void) +{ + return rt305x_soc == RT305X_SOC_RT5350; +} + +#define RT305X_SYSC_BASE 0x10000000 + +#define SYSC_REG_CHIP_NAME0 0x00 +#define SYSC_REG_CHIP_NAME1 0x04 +#define SYSC_REG_CHIP_ID 0x0c +#define SYSC_REG_SYSTEM_CONFIG 0x10 + +#define RT3052_CHIP_NAME0 0x30335452 +#define RT3052_CHIP_NAME1 0x20203235 + +#define RT3350_CHIP_NAME0 0x33335452 +#define RT3350_CHIP_NAME1 0x20203035 + +#define RT3352_CHIP_NAME0 0x33335452 +#define RT3352_CHIP_NAME1 0x20203235 + +#define RT5350_CHIP_NAME0 0x33355452 +#define RT5350_CHIP_NAME1 0x20203035 + +#define CHIP_ID_ID_MASK 0xff +#define CHIP_ID_ID_SHIFT 8 +#define CHIP_ID_REV_MASK 0xff + +#define RT305X_SYSCFG_CPUCLK_SHIFT 18 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1 +#define RT305X_SYSCFG_CPUCLK_LOW 0x0 +#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 + +#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1 +#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1 + +#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 +#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 +#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 +#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 + +#define RT5350_SYSCFG0_CPUCLK_SHIFT 8 +#define RT5350_SYSCFG0_CPUCLK_MASK 0x3 +#define RT5350_SYSCFG0_CPUCLK_360 0x0 +#define RT5350_SYSCFG0_CPUCLK_320 0x2 +#define RT5350_SYSCFG0_CPUCLK_300 0x3 + +/* multi function gpio pins */ +#define RT305X_GPIO_I2C_SD 1 +#define RT305X_GPIO_I2C_SCLK 2 +#define RT305X_GPIO_SPI_EN 3 +#define RT305X_GPIO_SPI_CLK 4 +/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */ +#define RT305X_GPIO_7 7 +#define RT305X_GPIO_10 10 +#define RT305X_GPIO_14 14 +#define RT305X_GPIO_UART1_TXD 15 +#define RT305X_GPIO_UART1_RXD 16 +#define RT305X_GPIO_JTAG_TDO 17 +#define RT305X_GPIO_JTAG_TDI 18 +#define RT305X_GPIO_MDIO_MDC 22 +#define RT305X_GPIO_MDIO_MDIO 23 +#define RT305X_GPIO_SDRAM_MD16 24 +#define RT305X_GPIO_SDRAM_MD31 39 +#define RT305X_GPIO_GE0_TXD0 40 +#define RT305X_GPIO_GE0_RXCLK 51 + +#define RT305X_GPIO_MODE_I2C BIT(0) +#define RT305X_GPIO_MODE_SPI BIT(1) +#define RT305X_GPIO_MODE_UART0_SHIFT 2 +#define RT305X_GPIO_MODE_UART0_MASK 0x7 +#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) +#define RT305X_GPIO_MODE_UARTF 0x0 +#define RT305X_GPIO_MODE_PCM_UARTF 0x1 +#define RT305X_GPIO_MODE_PCM_I2S 0x2 +#define RT305X_GPIO_MODE_I2S_UARTF 0x3 +#define RT305X_GPIO_MODE_PCM_GPIO 0x4 +#define RT305X_GPIO_MODE_GPIO_UARTF 0x5 +#define RT305X_GPIO_MODE_GPIO_I2S 0x6 +#define RT305X_GPIO_MODE_GPIO 0x7 +#define RT305X_GPIO_MODE_UART1 BIT(5) +#define RT305X_GPIO_MODE_JTAG BIT(6) +#define RT305X_GPIO_MODE_MDIO BIT(7) +#define RT305X_GPIO_MODE_SDRAM BIT(8) +#define RT305X_GPIO_MODE_RGMII BIT(9) + +#endif diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c new file mode 100644 index 0000000..23ea087 --- /dev/null +++ b/arch/mips/ralink/rt305x.c @@ -0,0 +1,231 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + */ + +#include +#include +#include + +#include +#include +#include + +#include "common.h" + +enum rt305x_soc_type rt305x_soc; + +struct ralink_pinmux_grp mode_mux[] = { + { + .name = "i2c", + .mask = RT305X_GPIO_MODE_I2C, + .gpio_first = RT305X_GPIO_I2C_SD, + .gpio_last = RT305X_GPIO_I2C_SCLK, + }, { + .name = "spi", + .mask = RT305X_GPIO_MODE_SPI, + .gpio_first = RT305X_GPIO_SPI_EN, + .gpio_last = RT305X_GPIO_SPI_CLK, + }, { + .name = "uartlite", + .mask = RT305X_GPIO_MODE_UART1, + .gpio_first = RT305X_GPIO_UART1_TXD, + .gpio_last = RT305X_GPIO_UART1_RXD, + }, { + .name = "jtag", + .mask = RT305X_GPIO_MODE_JTAG, + .gpio_first = RT305X_GPIO_JTAG_TDO, + .gpio_last = RT305X_GPIO_JTAG_TDI, + }, { + .name = "mdio", + .mask = RT305X_GPIO_MODE_MDIO, + .gpio_first = RT305X_GPIO_MDIO_MDC, + .gpio_last = RT305X_GPIO_MDIO_MDIO, + }, { + .name = "sdram", + .mask = RT305X_GPIO_MODE_SDRAM, + .gpio_first = RT305X_GPIO_SDRAM_MD16, + .gpio_last = RT305X_GPIO_SDRAM_MD31, + }, { + .name = "rgmii", + .mask = RT305X_GPIO_MODE_RGMII, + .gpio_first = RT305X_GPIO_GE0_TXD0, + .gpio_last = RT305X_GPIO_GE0_RXCLK, + }, {0} +}; + +struct ralink_pinmux_grp uart_mux[] = { + { + .name = "uartf", + .mask = RT305X_GPIO_MODE_UARTF, + .gpio_first = RT305X_GPIO_7, + .gpio_last = RT305X_GPIO_14, + }, { + .name = "pcm uartf", + .mask = RT305X_GPIO_MODE_PCM_UARTF, + .gpio_first = RT305X_GPIO_7, + .gpio_last = RT305X_GPIO_14, + }, { + .name = "pcm i2s", + .mask = RT305X_GPIO_MODE_PCM_I2S, + .gpio_first = RT305X_GPIO_7, + .gpio_last = RT305X_GPIO_14, + }, { + .name = "i2s uartf", + .mask = RT305X_GPIO_MODE_I2S_UARTF, + .gpio_first = RT305X_GPIO_7, + .gpio_last = RT305X_GPIO_14, + }, { + .name = "pcm gio", + .mask = RT305X_GPIO_MODE_PCM_GPIO, + .gpio_first = RT305X_GPIO_10, + .gpio_last = RT305X_GPIO_14, + }, { + .name = "gpio uartf", + .mask = RT305X_GPIO_MODE_GPIO_UARTF, + .gpio_first = RT305X_GPIO_7, + .gpio_last = RT305X_GPIO_14, + }, { + .name = "gpio i2s", + .mask = RT305X_GPIO_MODE_GPIO_I2S, + .gpio_first = RT305X_GPIO_7, + .gpio_last = RT305X_GPIO_14, + }, { + .name = "gpio", + .mask = RT305X_GPIO_MODE_GPIO, + }, {0} +}; + +void rt305x_wdt_reset(void) +{ + u32 t; + + /* enable WDT reset output on pin SRAM_CS_N */ + t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); + t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT << + RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT; + rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG); +} + +struct ralink_pinmux gpio_pinmux = { + .mode = mode_mux, + .uart = uart_mux, + .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT, + .wdt_reset = rt305x_wdt_reset, +}; + +void __init ralink_clk_init(void) +{ + unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; + u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); + + if (soc_is_rt305x() || soc_is_rt3350()) { + t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & + RT305X_SYSCFG_CPUCLK_MASK; + switch (t) { + case RT305X_SYSCFG_CPUCLK_LOW: + cpu_rate = 320000000; + break; + case RT305X_SYSCFG_CPUCLK_HIGH: + cpu_rate = 384000000; + break; + } + sys_rate = uart_rate = wdt_rate = cpu_rate / 3; + } else if (soc_is_rt3352()) { + t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & + RT3352_SYSCFG0_CPUCLK_MASK; + switch (t) { + case RT3352_SYSCFG0_CPUCLK_LOW: + cpu_rate = 384000000; + break; + case RT3352_SYSCFG0_CPUCLK_HIGH: + cpu_rate = 400000000; + break; + } + sys_rate = wdt_rate = cpu_rate / 3; + uart_rate = 40000000; + } else if (soc_is_rt5350()) { + t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & + RT5350_SYSCFG0_CPUCLK_MASK; + switch (t) { + case RT5350_SYSCFG0_CPUCLK_360: + cpu_rate = 360000000; + sys_rate = cpu_rate / 3; + break; + case RT5350_SYSCFG0_CPUCLK_320: + cpu_rate = 320000000; + sys_rate = cpu_rate / 4; + break; + case RT5350_SYSCFG0_CPUCLK_300: + cpu_rate = 300000000; + sys_rate = cpu_rate / 3; + break; + default: + BUG(); + } + uart_rate = 40000000; + wdt_rate = sys_rate; + } else { + BUG(); + } + + ralink_clk_add("cpu", cpu_rate); + ralink_clk_add("10000b00.spi", sys_rate); + ralink_clk_add("10000100.timer", wdt_rate); + ralink_clk_add("10000500.uart", uart_rate); + ralink_clk_add("10000c00.uartlite", uart_rate); +} + +void prom_soc_init(struct ralink_soc_info *soc_info) +{ + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); + u32 n0; + u32 n1; + u32 id; + + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); + + if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { + unsigned long icache_sets; + + icache_sets = (read_c0_config1() >> 22) & 7; + if (icache_sets == 1) { + rt305x_soc = RT305X_SOC_RT3050; + soc_info->name = "RT3050"; + soc_info->compatible = "ralink,rt3050"; + } else { + rt305x_soc = RT305X_SOC_RT3052; + soc_info->name = "RT3052"; + soc_info->compatible = "ralink,rt3052"; + } + } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { + rt305x_soc = RT305X_SOC_RT3350; + soc_info->name = "RT3350"; + soc_info->compatible = "ralink,rt3250"; + } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { + rt305x_soc = RT305X_SOC_RT3352; + soc_info->name = "RT3352"; + soc_info->compatible = "ralink,rt3352"; + } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { + rt305x_soc = RT305X_SOC_RT5350; + soc_info->name = "RT5350"; + soc_info->compatible = "ralink,rt5350"; + } else { + panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); + } + + id = __raw_readl(sysc + SYSC_REG_CHIP_ID); + + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, + "Ralink %s id:%u rev:%u", + soc_info->name, + (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, + (id & CHIP_ID_REV_MASK)); +} -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:09:01 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:11:56 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52055 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833402Ab3AWMJBukEaA (ORCPT ); Wed, 23 Jan 2013 13:09:01 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 10/11] MIPS: ralink: adds rt305x devicetree Date: Wed, 23 Jan 2013 13:05:54 +0100 Message-Id: <1358942755-25371-11-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35516 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3134 Lines: 173 This adds the devicetree file that describes the rt305x evaluation kit. Signed-off-by: John Crispin --- arch/mips/ralink/dts/rt305x.dts | 156 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 arch/mips/ralink/dts/rt305x.dts diff --git a/arch/mips/ralink/dts/rt305x.dts b/arch/mips/ralink/dts/rt305x.dts new file mode 100644 index 0000000..6554cfd --- /dev/null +++ b/arch/mips/ralink/dts/rt305x.dts @@ -0,0 +1,156 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,rt305x"; + + cpus { + cpu@0 { + compatible = "mips,mips24KEc"; + }; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600 init=/init"; + }; + + palmbus@10000000 { + compatible = "palmbus"; + reg = <0x10000000 0x200000>; + ranges = <0x0 0x10000000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc@0 { + compatible = "ralink,sysc"; + reg = <0x0 0x100>; + + ralink,pinmmux = "uartlite", "spi"; + ralink,uartmux = "gpio"; + ralink,wdtmux = <0>; + }; + + timer@100 { + compatible = "ralink,wdt"; + reg = <0x100 0x100>; + }; + + intc: intc@200 { + compatible = "ralink,intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memc@300 { + compatible = "ralink,memc"; + reg = <0x300 0x100>; + }; + + gpio0: gpio@600 { + compatible = "ralink,gpio"; + reg = <0x600 0x34>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,ngpio = <24>; + ralink,regs = [ 00 04 08 0c + 20 24 28 2c + 30 34 ]; + }; + + gpio1: gpio@638 { + compatible = "ralink,gpio"; + reg = <0x638 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,ngpio = <16>; + ralink,regs = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + }; + + gpio2: gpio@660 { + compatible = "ralink,gpio"; + reg = <0x660 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,ngpio = <12>; + ralink,regs = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + }; + + spi@b00 { + compatible = "ralink,spi"; + reg = <0xb00 0x100>; + }; + + uartlite@c00 { + compatible = "ns16550a"; + reg = <0xc00 0x100>; + + interrupt-parent = <&intc>; + interrupts = <20>; + + reg-shift = <2>; + }; + + fe@100000 { + compatible = "ralink,fe"; + reg = <0x100000 0x10000>; + }; + + esw@110000 { + compatible = "ralink,esw"; + reg = <0x110000 0x8000>; + }; + + dwc_otg@1c0000 { + compatible = "dwc_otg"; + reg = <0x1c0000 0x40000>; + }; + }; + + cfi@1f000000 { + compatible = "cfi-flash"; + reg = <0x1f000000 0x800000>; + + bank-width = <2>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + partition@30000 { + label = "uboot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + partition@40000 { + label = "calibration"; + reg = <0x40000 0x10000>; + read-only; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x7b0000>; + }; + }; +}; -- 1.7.10.4 From blogic@openwrt.org Wed Jan 23 13:09:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:12:18 +0100 (CET) Received: from nbd.name ([46.4.11.11]:52061 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833407Ab3AWMJGS6uYa (ORCPT ); Wed, 23 Jan 2013 13:09:06 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [RFC 11/11] MIPS: ralink: adds Kbuild files Date: Wed, 23 Jan 2013 13:05:55 +0100 Message-Id: <1358942755-25371-12-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> X-archive-position: 35517 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4368 Lines: 154 Add the Kbuild symbols and Makefiles needed to actually build the ralink code from this series Signed-off-by: John Crispin --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 19 ++++++++++++++++++- arch/mips/ralink/Kconfig | 27 +++++++++++++++++++++++++++ arch/mips/ralink/Makefile | 15 +++++++++++++++ arch/mips/ralink/Platform | 11 +++++++++++ arch/mips/ralink/dts/Makefile | 1 + 6 files changed, 73 insertions(+), 1 deletion(-) create mode 100644 arch/mips/ralink/Kconfig create mode 100644 arch/mips/ralink/Makefile create mode 100644 arch/mips/ralink/Platform create mode 100644 arch/mips/ralink/dts/Makefile diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 91b9d69..9a73ce6 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -22,6 +22,7 @@ platforms += pmc-sierra platforms += pnx833x platforms += pnx8550 platforms += powertv +platforms += ralink platforms += rb532 platforms += sgi-ip22 platforms += sgi-ip27 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2ac626a..89c92d3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -434,6 +434,22 @@ config POWERTV help This enables support for the Cisco PowerTV Platform. +config RALINK + bool "Ralink based machines" + select CEVT_R4K + select CSRC_R4K + select BOOT_RAW + select DMA_NONCOHERENT + select IRQ_CPU + select USE_OF + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + select HAVE_MACH_CLKDEV + select CLKDEV_LOOKUP + config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" select FW_ARC @@ -846,6 +862,7 @@ source "arch/mips/lantiq/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/powertv/Kconfig" +source "arch/mips/ralink/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" @@ -1160,7 +1177,7 @@ config BOOT_ELF32 config MIPS_L1_CACHE_SHIFT int - default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL + default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || RALINK_RT288X default "6" if MIPS_CPU_SCACHE default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON default "5" diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig new file mode 100644 index 0000000..1be044c --- /dev/null +++ b/arch/mips/ralink/Kconfig @@ -0,0 +1,27 @@ +if RALINK + +choice + prompt "Ralink SoC selection" + default SOC_RT305X + help + Select Ralink MIPS SoC type. + + config SOC_RT305X + bool "RT305x" + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI + +endchoice + +choice + prompt "Devicetree selection" + default DTB_RT305X_EVAL + help + Select the devicetree. + + config DTB_RT305X_EVAL + bool "RT305x eval kit" + +endchoice + +endif diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile new file mode 100644 index 0000000..939757f --- /dev/null +++ b/arch/mips/ralink/Makefile @@ -0,0 +1,15 @@ +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation.# +# Makefile for the Ralink common stuff +# +# Copyright (C) 2009-2011 Gabor Juhos +# Copyright (C) 2013 John Crispin + +obj-y := prom.o of.o reset.o clk.o irq.o + +obj-$(CONFIG_SOC_RT305X) += rt305x.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-y += dts/ diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform new file mode 100644 index 0000000..1d7e8fb --- /dev/null +++ b/arch/mips/ralink/Platform @@ -0,0 +1,11 @@ +# +# Ralink SoC common stuff +# +core-$(CONFIG_RALINK) += arch/mips/ralink/ +cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink + +# +# Ralink RT305x +# +cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x +load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000 diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile new file mode 100644 index 0000000..e2ce7b4 --- /dev/null +++ b/arch/mips/ralink/dts/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_DTB_RT305X_EVAL) := rt305x.dtb.o -- 1.7.10.4 From zajec5@gmail.com Wed Jan 23 13:13:59 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 13:14:00 +0100 (CET) Received: from mail-wi0-f174.google.com ([209.85.212.174]:41395 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833402Ab3AWMN7htCFw convert rfc822-to-8bit (ORCPT ); Wed, 23 Jan 2013 13:13:59 +0100 Received: by mail-wi0-f174.google.com with SMTP id hq4so632404wib.13 for ; Wed, 23 Jan 2013 04:13:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:date:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=Buu41WyhP5DF7zOdjjLGomDK9DtRxQrUi9HKagfUDuI=; b=JuTX+nuo9NjaKuU4FTaYFvp2x23nsGODtIUBJ/RLMhElI1+A2chZ9WoYwqpFVUte0D lxC0Ikd+t/E5kow81yJIQr4rvCRHW9/rU/wIDvMlOPea+/8ptZNBV56iQwKSRBrl6lmA awAluy7rvPGcfiskQJQRLmU41Sjr/itT1CeBsyTmVY0jwWGaJalLjnPCSOyIPFPwe9u3 KSbdIyE1AqB5L4jvzwmEBacbhh136tyLeRO7qd0aXA4WZwewjn9sgWVHDY4azaPuA0Tt y0dJfbs5f+vJDbuDuT93wUA/4ehcbupjzpMBx7uqbhqdIxbqZLBGSdLQRN5i5vRhYP6A 5P9Q== MIME-Version: 1.0 X-Received: by 10.180.88.134 with SMTP id bg6mr2076897wib.26.1358943234005; Wed, 23 Jan 2013 04:13:54 -0800 (PST) Received: by 10.216.72.134 with HTTP; Wed, 23 Jan 2013 04:13:53 -0800 (PST) Date: Wed, 23 Jan 2013 13:13:53 +0100 Message-ID: Subject: Upcoming cross-tree build breakage on merge window From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: john@phrozen.org, ralf@linux-mips.org, "David S. Miller" Cc: linux-mips@linux-mips.org, Network Development , Hauke Mehrtens Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 35518 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zajec5@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 621 Lines: 18 I've noticed possible build breakage when two trees get merged: net-next and linux-john (MIPS). This is about two following commits: http://git.kernel.org/?p=linux/kernel/git/davem/net-next.git;a=commit;h=dd4544f05469aaaeee891d7dc54d66430344321e http://git.linux-mips.org/?p=john/linux-john.git;a=commit;h=a008ca117bc85a9d66c47cd5ab18a6c332411919 The first one adds "bgmac" driver which uses asm/mach-bcm47xx/nvram.h and nvram_getenv. The second one renames them. Can you handle this in some clever way during merge window, please? The fix is trivial: 1) Use 2) Use bcm47xx_nvram_getenv -- RafaÅ‚ From ralf@linux-mips.org Wed Jan 23 20:15:51 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 20:15:52 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:41327 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6833413Ab3AWTPvxZD-v (ORCPT ); Wed, 23 Jan 2013 20:15:51 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r0NJFomo008685; Wed, 23 Jan 2013 20:15:50 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r0NJFoFc008684; Wed, 23 Jan 2013 20:15:50 +0100 Date: Wed, 23 Jan 2013 20:15:50 +0100 From: Ralf Baechle To: =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= Cc: linux-mips@linux-mips.org Subject: Re: git (linux-queue.git) not available: access denied or repository not exported Message-ID: <20130123191549.GB7294@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35519 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 524 Lines: 15 On Wed, Jan 23, 2013 at 11:45:16AM +0100, RafaÅ‚ MiÅ‚ecki wrote: > # git clone git://git.linux-mips.org/pub/scm/ralf/linux-queue.git > Cloning into 'linux-queue'... > fatal: remote error: access denied or repository not exported: > /pub/scm/ralf/linux-queue.git > > I've tried this on two machines. Is there some mirror? The repository has been superseeded by upstream-sfr.git. linux-queue.git used to serve almost the same purpose and has been dropped. Is there a stale reference to linux-queue.git somewhere? Ralf From florian@openwrt.org Wed Jan 23 20:23:20 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 20:23:44 +0100 (CET) Received: from mail-bk0-f51.google.com ([209.85.214.51]:61596 "EHLO mail-bk0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833416Ab3AWTXUzZAGl (ORCPT ); Wed, 23 Jan 2013 20:23:20 +0100 Received: by mail-bk0-f51.google.com with SMTP id ik5so182574bkc.10 for ; Wed, 23 Jan 2013 11:23:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:message-id:date:from:organization:user-agent :mime-version:to:cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=KwK1dDsTRPwm/KCnDfPB4NAt8hYkX+GWdqzwh+uD3FM=; b=udBM7oYLArnyBOH39UcTIPsCK1KcZ7hSkSLmdMk/aGmWm62IyjD7Mzj03ATgTnBGEV DpJS9sMTHasf+5+POiBMnP/Ga7QD8BSf1Mis8SM6IUQDsDa+KD2AF/O1bNSkEdGTaGw9 c7BeZtIYJIXV8VpsdA/rVwS0enLwxjVpwlbwzX9YoCvC9XKVBpe3dR29y/a7WglVC7FU dDG4bATgjH0EUWCYrwK0ZE3nAMGWPF5EbwFzKA7yKKs6FhTYRsYPrlIF1Gym8m6jmH+k FdrvkAZscdsKHj/5j3RS3QVbXBPX+Lfn3l1Fh1tQBASXQFRh5cwn8aMjHHw8Ftq8aLPR se+g== X-Received: by 10.204.9.4 with SMTP id j4mr800742bkj.36.1358968989324; Wed, 23 Jan 2013 11:23:09 -0800 (PST) Received: from ?IPv6:2a01:e35:2f70:4010:b1d4:3529:4271:81d8? ([2a01:e35:2f70:4010:b1d4:3529:4271:81d8]) by mx.google.com with ESMTPS id c10sm15211315bkw.1.2013.01.23.11.23.07 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 23 Jan 2013 11:23:08 -0800 (PST) Message-ID: <510038A8.6020606@openwrt.org> Date: Wed, 23 Jan 2013 20:23:20 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130107 Thunderbird/17.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [RFC 08/11] MIPS: ralink: adds early_printk support References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> <1358942755-25371-9-git-send-email-blogic@openwrt.org> In-Reply-To: <1358942755-25371-9-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35520 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2181 Lines: 73 Hey John, Le 23/01/2013 13:05, John Crispin a écrit : > Add the code needed to make early printk work. > > Signed-off-by: John Crispin > --- > arch/mips/ralink/early_printk.c | 43 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 arch/mips/ralink/early_printk.c > > diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c > new file mode 100644 > index 0000000..c610084 > --- /dev/null > +++ b/arch/mips/ralink/early_printk.c > @@ -0,0 +1,43 @@ > +/* > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + * > + * Copyright (C) 2011-2012 Gabor Juhos > + */ > + > +#include > +#include > + > +#include > + > +/* UART registers */ > +#define EARLY_UART_BASE 0x10000c00 > + > +#define UART_REG_RX 0 > +#define UART_REG_TX 1 > +#define UART_REG_IER 2 > +#define UART_REG_IIR 3 > +#define UART_REG_FCR 4 > +#define UART_REG_LCR 5 > +#define UART_REG_MCR 6 > +#define UART_REG_LSR 7 Is that really required considering that you already include serial_reg.h and could use defines from there? At some point I think that we might be able to come up with a some kind of generic 8250 earlyprintk code where people just tell what's the base address of their UART. Something like: #define UART_BASE KSEG1ADDR(MY_UART_BASE) #include > + > +static inline void uart_w32(u32 val, unsigned reg) > +{ > + __raw_writel((val), > + (void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg))); > +} > + > +static inline u32 uart_r32(unsigned reg) > +{ > + return __raw_readl( > + (void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg))); > +} > + > +void prom_putchar(unsigned char ch) > +{ > + while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0); > + uart_w32(UART_REG_TX, ch); > + while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0); > +} > From florian@openwrt.org Wed Jan 23 20:25:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 20:25:43 +0100 (CET) Received: from mail-bk0-f44.google.com ([209.85.214.44]:37794 "EHLO mail-bk0-f44.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833412Ab3AWTZm1kHZE (ORCPT ); Wed, 23 Jan 2013 20:25:42 +0100 Received: by mail-bk0-f44.google.com with SMTP id j4so985172bkw.3 for ; Wed, 23 Jan 2013 11:25:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:message-id:date:from:organization:user-agent :mime-version:to:cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=4L6apWVDO7Eh2oumITPJBjByTMFWnjR7JGjZk6cVZC8=; b=Tg0okz0gJLvzngZ1lOvL/CLWQVct20OanXaFa/X1FNpC1MXhq1V5Xu4vvImR01xSdc z2VdUP5Rv6DwugXJmiWd2mJoHZO5XsOzqY7jBc3BLwDQhm4Mc7aB1GSLrh29Eg2n6iC7 rU1mKuxu8cHMv5cQp3oWDAfUaanylx3CgajayoBoNwdGsv3sAjEJS06kJbu2oWpiuvnA u7DO/xn/8z+l6Kcl51Ji+7jgWne4DnyyyxNXU1hCROwakLTumgUdLv28ECYUAUwX7z44 TwtBaSALKS/3qXavQQjYBOrmQuw7yRsTOB3xBgTmhlQc+muWWLzDhOoXeQ/I4rcpiox+ J4rA== X-Received: by 10.204.150.199 with SMTP id z7mr803393bkv.139.1358969137022; Wed, 23 Jan 2013 11:25:37 -0800 (PST) Received: from ?IPv6:2a01:e35:2f70:4010:b1d4:3529:4271:81d8? ([2a01:e35:2f70:4010:b1d4:3529:4271:81d8]) by mx.google.com with ESMTPS id v8sm15227410bku.6.2013.01.23.11.25.35 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 23 Jan 2013 11:25:36 -0800 (PST) Message-ID: <5100393D.9010700@openwrt.org> Date: Wed, 23 Jan 2013 20:25:49 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130107 Thunderbird/17.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [RFC 00/11] MIPS: ralink: adds support for ralink platform References: <1358942755-25371-1-git-send-email-blogic@openwrt.org> In-Reply-To: <1358942755-25371-1-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35521 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3214 Lines: 67 Hey John, Le 23/01/2013 13:05, John Crispin a écrit : > This series adds support for the ralink SoC family. Currently RT305X type > SoC is supported. RT2880/3883 are in my local queue already but require > further testing. This looks very good, and the diffstat is looking good too. Besides the lack of Device Tree bindings documentation for the bindings you add, I don't have particular comments. Maybe Gabor should be CC'd on these patches so he gets a chance to speak loud if he objects? Thanks! > > John Crispin (11): > MIPS: allow platforms to override cp0_compare_irq > MIPS: ralink: adds include files > MIPS: ralink: adds irq code > MIPS: ralink: adds reset code > MIPS: ralink: adds prom and cmdline code > MIPS: ralink: adds clkdev code > MIPS: ralink: adds OF code > MIPS: ralink: adds early_printk support > MIPS: ralink: adds support for RT305x SoC family > MIPS: ralink: adds rt305x devicetree > MIPS: ralink: adds Kbuild files > > arch/mips/Kbuild.platforms | 1 + > arch/mips/Kconfig | 19 +- > arch/mips/include/asm/mach-ralink/ralink_regs.h | 39 ++++ > arch/mips/include/asm/mach-ralink/rt305x.h | 139 ++++++++++++++ > arch/mips/include/asm/mach-ralink/war.h | 25 +++ > arch/mips/include/asm/time.h | 1 + > arch/mips/kernel/traps.c | 7 +- > arch/mips/ralink/Kconfig | 27 +++ > arch/mips/ralink/Makefile | 15 ++ > arch/mips/ralink/Platform | 11 ++ > arch/mips/ralink/clk.c | 72 +++++++ > arch/mips/ralink/common.h | 43 +++++ > arch/mips/ralink/dts/Makefile | 1 + > arch/mips/ralink/dts/rt305x.dts | 156 +++++++++++++++ > arch/mips/ralink/early_printk.c | 43 +++++ > arch/mips/ralink/irq.c | 182 ++++++++++++++++++ > arch/mips/ralink/of.c | 105 +++++++++++ > arch/mips/ralink/prom.c | 69 +++++++ > arch/mips/ralink/reset.c | 44 +++++ > arch/mips/ralink/rt305x.c | 231 +++++++++++++++++++++++ > 20 files changed, 1228 insertions(+), 2 deletions(-) > create mode 100644 arch/mips/include/asm/mach-ralink/ralink_regs.h > create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h > create mode 100644 arch/mips/include/asm/mach-ralink/war.h > create mode 100644 arch/mips/ralink/Kconfig > create mode 100644 arch/mips/ralink/Makefile > create mode 100644 arch/mips/ralink/Platform > create mode 100644 arch/mips/ralink/clk.c > create mode 100644 arch/mips/ralink/common.h > create mode 100644 arch/mips/ralink/dts/Makefile > create mode 100644 arch/mips/ralink/dts/rt305x.dts > create mode 100644 arch/mips/ralink/early_printk.c > create mode 100644 arch/mips/ralink/irq.c > create mode 100644 arch/mips/ralink/of.c > create mode 100644 arch/mips/ralink/prom.c > create mode 100644 arch/mips/ralink/reset.c > create mode 100644 arch/mips/ralink/rt305x.c > From zajec5@gmail.com Wed Jan 23 21:08:20 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 21:08:22 +0100 (CET) Received: from mail-wi0-f170.google.com ([209.85.212.170]:57232 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833408Ab3AWUIUy7sZe convert rfc822-to-8bit (ORCPT ); Wed, 23 Jan 2013 21:08:20 +0100 Received: by mail-wi0-f170.google.com with SMTP id hq7so4770441wib.3 for ; Wed, 23 Jan 2013 12:08:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:in-reply-to:references:date:message-id :subject:from:to:cc:content-type:content-transfer-encoding; bh=6IMbL/jknWsyPOgXnPphZsjk1YPYRK7xBqCbMbdkJdQ=; b=S0DO5H81mPT+OKoD98nYYLwuP0ZlNKONFPfkNq97Rs3I5Dnj2oFNXPtQ5gHEwUdkEI 6KKEOAkyRQirijKwhOH6GjxNDOB1yTYNvTC+MzWBQXLFne71inN+O8n2YUifAGdjnw47 upF8X3GrkZvVOldcxvc7OoKbSNPpg+FGapcEPrCljghSVRPMzFSweofIarjF0PtZ9WEt 8HP1wcp+Sg5yI2Q9CKyBrxLYBZu2GLjpRGA4co1yDbiYxbWFUzLVp85Tbl5OjpJcQLVD QECquWAAcPN39cx6I9iFM53r/6G0lwBfjIeFZImBt986ZcXMGpvzCrbug1UilokURJqX U9Xg== MIME-Version: 1.0 X-Received: by 10.194.88.98 with SMTP id bf2mr4834534wjb.49.1358971695520; Wed, 23 Jan 2013 12:08:15 -0800 (PST) Received: by 10.216.72.134 with HTTP; Wed, 23 Jan 2013 12:08:15 -0800 (PST) In-Reply-To: <20130123191549.GB7294@linux-mips.org> References: <20130123191549.GB7294@linux-mips.org> Date: Wed, 23 Jan 2013 21:08:15 +0100 Message-ID: Subject: Re: git (linux-queue.git) not available: access denied or repository not exported From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 35522 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zajec5@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 753 Lines: 22 2013/1/23 Ralf Baechle : > On Wed, Jan 23, 2013 at 11:45:16AM +0100, RafaÅ‚ MiÅ‚ecki wrote: > >> # git clone git://git.linux-mips.org/pub/scm/ralf/linux-queue.git >> Cloning into 'linux-queue'... >> fatal: remote error: access denied or repository not exported: >> /pub/scm/ralf/linux-queue.git >> >> I've tried this on two machines. Is there some mirror? > > The repository has been superseeded by upstream-sfr.git. linux-queue.git > used to serve almost the same purpose and has been dropped. > > Is there a stale reference to linux-queue.git somewhere? Yes: http://www.linux-mips.org/wiki/Git Would be nice to update that page and probably include also web access URLs. Quick task for someone with wiki account :) -- RafaÅ‚ From sshtylyov@mvista.com Wed Jan 23 22:55:07 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Jan 2013 22:55:09 +0100 (CET) Received: from mail-la0-f49.google.com ([209.85.215.49]:50370 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833416Ab3AWVzHqsqNs (ORCPT ); Wed, 23 Jan 2013 22:55:07 +0100 Received: by mail-la0-f49.google.com with SMTP id fs13so3092719lab.36 for ; Wed, 23 Jan 2013 13:55:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=6TKmiFgS7ghLLobDtIaN60j5fzw5pC76bzdN8Wr5YvQ=; b=i6aGnF3hmzoD2/YEeQi8j4mx3Qg7c3xK/sOOG5c30zD7xXwB67KyQrA4jbzt68oa7E lfO45CtFmTHcvMBDMlONb4O5Q18YdqpQmh2T/4ca1rLzrdq7JD9vTp0y457H/MCSI6sr MROUTiCv3TwX/3xrF7TD7/h/6lsLYVpyPNPmXa/pw9vppoDP0Kggy5UQHVdS9zYEKZvc TW1bk89yaa2dGBoqd6qHt5LTWm/uoSo+sYuIQMfFyTVyZx8Ey412UkZD2Q87hIoFgDx7 xs7rwULrbbAnMhgUJ3xHe8qjyDz8e14w11uwtEbEtyQ