From ddaney@caviumnetworks.com Sat Dec 1 01:23:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Dec 2012 01:23:27 +0100 (CET) Received: from db3ehsobe001.messaging.microsoft.com ([213.199.154.139]:50834 "EHLO db3outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6828008Ab2LAAXZ200cC (ORCPT ); Sat, 1 Dec 2012 01:23:25 +0100 Received: from mail15-db3-R.bigfish.com (10.3.81.237) by DB3EHSOBE010.bigfish.com (10.3.84.30) with Microsoft SMTP Server id 14.1.225.23; Sat, 1 Dec 2012 00:23:17 +0000 Received: from mail15-db3 (localhost [127.0.0.1]) by mail15-db3-R.bigfish.com (Postfix) with ESMTP id 68520480094; Sat, 1 Dec 2012 00:23:17 +0000 (UTC) X-Forefront-Antispam-Report: CIP:157.56.240.213;KIP:(null);UIP:(null);IPV:NLI;H:BL2PRD0711HT002.namprd07.prod.outlook.com;RD:none;EFVD:NLI X-SpamScore: 0 X-BigFish: PS0(zz936eIzz1de0h1202h1d1ah1d2ahzz177df4h8275eh17326ah8275dha1495iz2dh2a8h668h839h947hd25he5bhf0ah1288h12a5h12a9h12bdh137ah13b6h1441h14ddh1504h1537h153bh162dh1631h1155h) Received: from mail15-db3 (localhost.localdomain [127.0.0.1]) by mail15-db3 (MessageSwitch) id 1354321395192378_4310; Sat, 1 Dec 2012 00:23:15 +0000 (UTC) Received: from DB3EHSMHS018.bigfish.com (unknown [10.3.81.252]) by mail15-db3.bigfish.com (Postfix) with ESMTP id 2D1902E0054; Sat, 1 Dec 2012 00:23:15 +0000 (UTC) Received: from BL2PRD0711HT002.namprd07.prod.outlook.com (157.56.240.213) by DB3EHSMHS018.bigfish.com (10.3.87.118) with Microsoft SMTP Server (TLS) id 14.1.225.23; Sat, 1 Dec 2012 00:23:09 +0000 Received: from dl.caveonetworks.com (64.2.3.195) by pod51018.outlook.com (10.255.104.165) with Microsoft SMTP Server (TLS) id 14.16.239.5; Sat, 1 Dec 2012 00:23:09 +0000 Message-ID: <50B94DEB.3020608@caviumnetworks.com> Date: Fri, 30 Nov 2012 16:23:07 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Ralf Baechle , linux-mips Subject: Pull request for v3.8 Octeon specific changes. Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.195] X-OriginatorOrg: caviumnetworks.com X-archive-position: 35164 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2321 Lines: 55 Hi Ralf, The ATA changes are alredy Acked-by the ATA mainainer. The EDAC changes are just an extension of what you added for 3.8, they were sent to the EDAC list here: http://marc.info/?l=linux-edac&m=135302283022318&w=2 But no response yet. My reasoning is that they should be OK as they just improve things that only touch OCTEON. The following changes since commit fbb3876de77cd31739fbca01bd82a1bc56e2ed5e: Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into mips-for-linux-next (2012-11-30 17:34:25 +0100) are available in the git repository at: git://git.linux-mips.org/pub/scm/daney/upstream-daney.git octeon-for-3.8 for you to fetch changes up to d2eb0719add2c471adf1ffb116e38bd5776c66d5: MIPS/EDAC: Improve OCTEON EDAC support. (2012-11-30 15:32:11 -0800) ---------------------------------------------------------------- David Daney (5): MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree. ata: pata_octeon_cf: Use correct byte order for DMA in when built little-endian. MIPS: OCTEON: Add OCTEON family defintions to octeon-model.h MIPS: OCTEON: Add definitions for OCTEON memory contoller registers. MIPS/EDAC: Improve OCTEON EDAC support. arch/mips/cavium-octeon/octeon-irq.c | 1 - arch/mips/cavium-octeon/octeon-platform.c | 102 - arch/mips/cavium-octeon/setup.c | 30 +- arch/mips/include/asm/mach-cavium-octeon/irq.h | 1 - arch/mips/include/asm/octeon/cvmx-lmcx-defs.h | 3457 ++++++++++++++++++++++++ arch/mips/include/asm/octeon/octeon-model.h | 6 + arch/mips/include/asm/octeon/octeon.h | 7 - arch/mips/mm/c-octeon.c | 39 +- arch/mips/pci/pci-octeon.c | 3 +- drivers/ata/pata_octeon_cf.c | 423 ++- drivers/edac/octeon_edac-l2c.c | 178 +- drivers/edac/octeon_edac-lmc.c | 232 +- drivers/edac/octeon_edac-lmc.h | 78 - drivers/edac/octeon_edac-pc.c | 137 +- drivers/edac/octeon_edac-pci.c | 44 +- 15 files changed, 4157 insertions(+), 581 deletions(-) create mode 100644 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h delete mode 100644 drivers/edac/octeon_edac-lmc.h From vsubbiah@caviumnetworks.com Sun Dec 2 02:51:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Dec 2012 02:51:33 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10381 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823082Ab2LBBvbh61U4 (ORCPT ); Sun, 2 Dec 2012 02:51:31 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Sat, 01 Dec 2012 17:53:23 -0800 Received: from casmarthost.caveonetworks.com ([192.168.16.225]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Sat, 1 Dec 2012 17:51:28 -0800 Received: from localhost (vs-lnx.caveonetworks.com [10.18.104.167]) by casmarthost.caveonetworks.com (8.13.8/8.13.8) with ESMTP id qB21pRBH017839; Sat, 1 Dec 2012 17:51:28 -0800 From: vsubbiah@caviumnetworks.com To: linux-mips@linux-mips.org, ralf@linux-mips.org, ddaney@caviumnetworks.com Subject: [PATCH] MIPS: Octeon: Adding driver to measure interrupt latency on Octeon. Date: Sat, 1 Dec 2012 17:51:26 -0800 Message-Id: <1354413086-25162-1-git-send-email-vsubbiah@caviumnetworks.com> X-Mailer: git-send-email 1.7.9.5 X-OriginalArrivalTime: 02 Dec 2012 01:51:28.0298 (UTC) FILETIME=[8B50C8A0:01CDD02F] X-archive-position: 35165 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vsubbiah@caviumnetworks.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6709 Lines: 257 From: Venkat Subbiah Signed-off-by: Venkat Subbiah [Rewrote timeing calculations] Signed-off-by: David Daney --- arch/mips/cavium-octeon/Kconfig | 9 ++ arch/mips/cavium-octeon/Makefile | 1 + arch/mips/cavium-octeon/oct_ilm.c | 206 +++++++++++++++++++++++++++++++++++++ 3 files changed, 216 insertions(+) create mode 100644 arch/mips/cavium-octeon/oct_ilm.c diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 2f4f6d5..75a6df7 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -94,4 +94,13 @@ config SWIOTLB select NEED_SG_DMA_LENGTH +config OCTEON_ILM + tristate "Module to measure interrupt latency using Octeon CIU Timer" + help + This driver is a module to measure interrupt latency using the + the CIU Timers on Octeon. + + To compile this driver as a module, choose M here. The module + will be called octeon-ilm + endif # CPU_CAVIUM_OCTEON diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index bc96e29..614db10 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -18,6 +18,7 @@ obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o DTS_FILES = octeon_3xxx.dts octeon_68xx.dts DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) diff --git a/arch/mips/cavium-octeon/oct_ilm.c b/arch/mips/cavium-octeon/oct_ilm.c new file mode 100644 index 0000000..71b213d --- /dev/null +++ b/arch/mips/cavium-octeon/oct_ilm.c @@ -0,0 +1,206 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_NUM 3 + +static bool reset_stats; + +struct latency_info { + u64 io_interval; + u64 cpu_interval; + u64 timer_start1; + u64 timer_start2; + u64 max_latency; + u64 min_latency; + u64 latency_sum; + u64 average_latency; + u64 interrupt_cnt; +}; + +static struct latency_info li; +static struct dentry *dir; + +static int show_latency(struct seq_file *m, void *v) +{ + u64 cpuclk, avg, max, min; + struct latency_info curr_li = li; + + cpuclk = octeon_get_clock_rate(); + + max = (curr_li.max_latency * 1000000000) / cpuclk; + min = (curr_li.min_latency * 1000000000) / cpuclk; + avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt); + + seq_printf(m, "cnt: %10lld, avg: %7lld ns, max: %7lld ns, min: %7lld ns\n", + curr_li.interrupt_cnt, avg, max, min); + return 0; +} + +static int oct_ilm_open(struct inode *inode, struct file *file) +{ + return single_open(file, show_latency, NULL); +} + +static const struct file_operations oct_ilm_ops = { + .open = oct_ilm_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int reset_statistics(void *data, u64 value) +{ + reset_stats = true; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(reset_statistics_ops, NULL, reset_statistics, "%llu\n"); + +static int init_debufs(void) +{ + struct dentry *show_dentry; + dir = debugfs_create_dir("oct_ilm", 0); + if (!dir) { + pr_err("oct_ilm: failed to create debugfs entry oct_ilm\n"); + return -1; + } + + show_dentry = debugfs_create_file("statistics", 0222, dir, NULL, + &oct_ilm_ops); + if (!show_dentry) { + pr_err("oct_ilm: failed to create debugfs entry oct_ilm/statistics\n"); + return -1; + } + + show_dentry = debugfs_create_file("reset", 0222, dir, NULL, + &reset_statistics_ops); + if (!show_dentry) { + pr_err("oct_ilm: failed to create debugfs entry oct_ilm/reset\n"); + return -1; + } + + return 0; + +} + +static void init_latency_info(struct latency_info *li, int startup) +{ + /* interval in milli seconds after which the interrupt will + * be triggered + */ + int interval = 1; + + if (startup) { + /* Calculating by the amounts io clock and cpu clock would + * increment in interval amount of ms + */ + li->io_interval = (octeon_get_io_clock_rate() * interval) / 1000; + li->cpu_interval = (octeon_get_clock_rate() * interval) / 1000; + } + li->timer_start1 = 0; + li->timer_start2 = 0; + li->max_latency = 0; + li->min_latency = (u64)-1; + li->latency_sum = 0; + li->interrupt_cnt = 0; +} + + +static void start_timer(int timer, u64 interval) +{ + union cvmx_ciu_timx timx; + unsigned long flags; + + timx.u64 = 0; + timx.s.one_shot = 1; + timx.s.len = interval; + raw_local_irq_save(flags); + li.timer_start1 = read_c0_cvmcount(); + cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64); + /* Read it back to force wait until register is written. */ + timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer)); + li.timer_start2 = read_c0_cvmcount(); + raw_local_irq_restore(flags); +} + + +static irqreturn_t cvm_oct_ciu_timer_interrupt(int cpl, void *dev_id) +{ + u64 last_latency; + u64 last_int_cnt; + + if (reset_stats) { + init_latency_info(&li, 0); + reset_stats = false; + } else { + last_int_cnt = read_c0_cvmcount(); + last_latency = last_int_cnt - (li.timer_start1 + li.cpu_interval); + li.interrupt_cnt++; + li.latency_sum += last_latency; + if (last_latency > li.max_latency) + li.max_latency = last_latency; + if (last_latency < li.min_latency) + li.min_latency = last_latency; + } + start_timer(TIMER_NUM, li.io_interval); + return IRQ_HANDLED; +} + +static void disable_timer(int timer) +{ + union cvmx_ciu_timx timx; + + timx.s.one_shot = 0; + timx.s.len = 0; + cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64); + /* Read it back to force immediate write of timer register*/ + timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer)); +} + +static __init int oct_ilm_module_init(void) +{ + int rc; + int irq = OCTEON_IRQ_TIMER0 + TIMER_NUM; + + rc = init_debufs(); + if (rc) { + WARN(1, "Could not create debugfs entries"); + return rc; + } + + rc = request_irq(irq, cvm_oct_ciu_timer_interrupt, IRQF_NO_THREAD, + "oct_ilm", 0); + if (rc) { + WARN(1, "Could not acquire IRQ %d", irq); + goto err_irq; + } + + init_latency_info(&li, 1); + start_timer(TIMER_NUM, li.io_interval); + + return 0; +err_irq: + debugfs_remove_recursive(dir); + return rc; +} + +static __exit void oct_ilm_module_exit(void) +{ + disable_timer(TIMER_NUM); + if (dir) + debugfs_remove_recursive(dir); + free_irq(OCTEON_IRQ_TIMER0 + TIMER_NUM, 0); +} + +module_exit(oct_ilm_module_exit); +module_init(oct_ilm_module_init); +MODULE_AUTHOR("Venkat Subbiah, Cavium"); +MODULE_DESCRIPTION("Measures interrupt latency on Octeon chips."); +MODULE_LICENSE("GPL"); -- 1.7.9.5 From joro@8bytes.org Sun Dec 2 15:06:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Dec 2012 15:06:49 +0100 (CET) Received: from 8bytes.org ([85.214.48.195]:43795 "EHLO mail.8bytes.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823252Ab2LBOGsONhOy (ORCPT ); Sun, 2 Dec 2012 15:06:48 +0100 Received: from localhost (localhost [127.0.0.1]) by mail.8bytes.org (Postfix) with SMTP id 9F7F912AFB8 for ; Sun, 2 Dec 2012 15:06:47 +0100 (CET) Received: by mail.8bytes.org (Postfix, from userid 1000) id 1CED212AF14; Sun, 2 Dec 2012 15:06:45 +0100 (CET) Date: Sun, 2 Dec 2012 15:06:45 +0100 From: Joerg Roedel To: Marek Szyprowski Cc: shuah.khan@hp.com, a-jacquiot@ti.com, fenghua.yu@intel.com, catalin.marinas@arm.com, lethal@linux-sh.org, benh@kernel.crashing.org, ralf@linux-mips.org, tony.luck@intel.com, davem@davemloft.net, msalter@redhat.com, monstr@monstr.eu, Ming Lei , linux-arm-kernel@lists.infradead.org, LKML , linux-c6x-dev@linux-c6x.org, linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, microblaze-uclinux@itee.uq.edu.au, shuahkhan@gmail.com Subject: Re: [PATCH 0/9] dma_debug: add debug_dma_mapping_error support to architectures that support DMA_DEBUG_API Message-ID: <20121202140644.GP30633@8bytes.org> References: <1353706142.5270.93.camel@lorien2> <50B34B0F.3080204@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50B34B0F.3080204@samsung.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-DSPAM-Result: Whitelisted X-DSPAM-Processed: Sun Dec 2 15:06:47 2012 X-DSPAM-Confidence: 0.9989 X-DSPAM-Probability: 0.0000 X-DSPAM-Signature: 50bb607722971091017827 X-archive-position: 35166 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joro@8bytes.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 494 Lines: 16 Hi Marek, On Mon, Nov 26, 2012 at 11:57:19AM +0100, Marek Szyprowski wrote: > I've took all the patches to the next-dma-debug branch in my tree, I sorry > that You have to wait so long for it. My branch is based on Joerg's > dma-debug branch and I've included it for testing in linux-next branch. The patches are now two times in next. One version from my tree and one from yours. Please remove the version from your tree, the patches should go upstream via my dma-debug branch. Joerg From zajec5@gmail.com Mon Dec 3 09:45:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Dec 2012 09:45:35 +0100 (CET) Received: from mail-wg0-f45.google.com ([74.125.82.45]:51858 "EHLO mail-wg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823123Ab2LCIpcaAKnH convert rfc822-to-8bit (ORCPT ); Mon, 3 Dec 2012 09:45:32 +0100 Received: by mail-wg0-f45.google.com with SMTP id dq12so1306760wgb.24 for ; Mon, 03 Dec 2012 00:45:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=6+HwqQTBn/Uvd4qypeIUAkUpx2j80DMFAxt/8R9466c=; b=pa70If8B+oWSrTJITQ6f5kaEd418wCMCXoVn/G9DOaRxSZPFkfNwVvbhxmpE4C8FJe amSIIkvNoja2nYtJs7Ov1xnSeHj6YKe7qsglUf8IBnQMetXE9D8IiVA6jJOU8mySj6Hm FsAwPOiwLxdw0FMNIAGLDBChEhGgrBOK+KE7FbMvEamwcEXJdD6vhkccwoa7ZfAbricA XkPeHlU7/XZLR3OWPBjsFfNPlxLwutjVUO+tTGl9Zli2W+8/LbA6NjnGg5lMaHacNNcV fyqj8nuz3/36N5OXiPImXXVuS1n/hQQ7s53r+I3ImlAytjMIU6hU7QZhe7sbJoUokMcW cr7w== MIME-Version: 1.0 Received: by 10.180.99.5 with SMTP id em5mr8057679wib.8.1354524326775; Mon, 03 Dec 2012 00:45:26 -0800 (PST) Received: by 10.216.21.8 with HTTP; Mon, 3 Dec 2012 00:45:26 -0800 (PST) In-Reply-To: <1353975925-32056-1-git-send-email-hauke@hauke-m.de> References: <1353975925-32056-1-git-send-email-hauke@hauke-m.de> Date: Mon, 3 Dec 2012 09:45:26 +0100 Message-ID: Subject: Re: [PATCH v2 00/15] watchdog/bcm47xx/bcma/ssb: add support for SoCs with PMU From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: Hauke Mehrtens Cc: linville@tuxdriver.com, wim@iguana.be, linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 35169 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zajec5@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1085 Lines: 27 2012/11/27 Hauke Mehrtens : > This patch series improves the watchdog driver used on the Broadcom > bcm47xx SoCs. > The watchdog driver does not access the functions directly any more, > but it registers as a platform device driver and ssb and bcma are > registering a device for this watchdog driver. > This also adds support for SoCs with a power management unit (PMU), > which have different clock rates. > > This code is currently based on the wireless-testing/master tree by > John Linville, because there are some changes in ssb and bcma in that > tree queued for 3.8 which will conflict with these changes, if this > would be based on an other tree. I have no problem with rebasing this > onto any other tree. > > @Wim Could you give me an ACK on the "watchdog: bcm47xx_wdt.c:" patches > so that John could take them trough the wireless-testing tree, or > provide me with some feedback on what I should change. Hi Wim, Have you got a chance to look at that patches? I've some additional bcma changes I wish to submit on top of this :) -- Rafał From m.szyprowski@samsung.com Mon Dec 3 09:52:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Dec 2012 09:52:14 +0100 (CET) Received: from mailout4.w1.samsung.com ([210.118.77.14]:50239 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823123Ab2LCIwF4SZq8 (ORCPT ); Mon, 3 Dec 2012 09:52:05 +0100 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MEG009JZ61DGE30@mailout4.w1.samsung.com>; Mon, 03 Dec 2012 08:54:43 +0000 (GMT) X-AuditID: cbfec7f4-b7f6d6d000001620-16-50bc682c1d78 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id DE.E8.05664.C286CB05; Mon, 03 Dec 2012 08:51:56 +0000 (GMT) Received: from [127.0.0.1] ([106.116.147.30]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MEG00IUH5YHQ700@eusync2.samsung.com>; Mon, 03 Dec 2012 08:51:56 +0000 (GMT) Message-id: <50BC6829.4060205@samsung.com> Date: Mon, 03 Dec 2012 09:51:53 +0100 From: Marek Szyprowski User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-version: 1.0 To: Joerg Roedel Cc: shuah.khan@hp.com, a-jacquiot@ti.com, fenghua.yu@intel.com, catalin.marinas@arm.com, lethal@linux-sh.org, benh@kernel.crashing.org, ralf@linux-mips.org, tony.luck@intel.com, davem@davemloft.net, msalter@redhat.com, monstr@monstr.eu, Ming Lei , linux-arm-kernel@lists.infradead.org, LKML , linux-c6x-dev@linux-c6x.org, linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, microblaze-uclinux@itee.uq.edu.au, shuahkhan@gmail.com Subject: Re: [PATCH 0/9] dma_debug: add debug_dma_mapping_error support to architectures that support DMA_DEBUG_API References: <1353706142.5270.93.camel@lorien2> <50B34B0F.3080204@samsung.com> <20121202140644.GP30633@8bytes.org> In-reply-to: <20121202140644.GP30633@8bytes.org> Content-type: text/plain; charset=UTF-8; format=flowed Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjluLIzCtJLcpLzFFi42I5/e/4FV2djD0BBrtv8FhMmDqJ3eLSHhUH Jo+jK9cyBTBGcdmkpOZklqUW6dslcGUsXZ5W8IWt4vDcm2wNjPtYuxg5OCQETCSu3XbrYuQE MsUkLtxbz9bFyMUhJLCUUWLTllvsEE4zk8SWFc/ZQKp4BbQkfh36zw5iswioSqzomMkKYrMJ GEp0ve0CqxEV8JWY9usaE0S9oMSPyfdYQGwRASWJ659bweqZBU6xSDSccgexhQVKJTp+P2MG sYUEiiXavl5nAjmOU8BA4sGbWohyM4lHLeuYIWx5ic1r3jJPYBSYhWTDLCRls5CULWBkXsUo mlqaXFCclJ5rqFecmFtcmpeul5yfu4kREoZfdjAuPmZ1iFGAg1GJh/fBl90BQqyJZcWVuYcY JTiYlUR4o6z3BAjxpiRWVqUW5ccXleakFh9iZOLglGpgbFvhtyftHUP+pL+HRJ8odtlEZi++ Kfmiv+yDoWjZs2dX7hg5ObJxht0W7zpQvqVy8aSNc77s5TpuLWDEEewnrSH85pnHjGh1jpQd PxpVLP4aScyemxW1cpK0cT63WLB47Z0Nv3OLRW4Kle7blHgh+p7/jqDX0qbb7sVsXfY7XGXd Jf3VmxS6lViKMxINtZiLihMBAT1oLCECAAA= X-archive-position: 35170 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.szyprowski@samsung.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 861 Lines: 25 On 12/2/2012 3:06 PM, Joerg Roedel wrote: > Hi Marek, > > On Mon, Nov 26, 2012 at 11:57:19AM +0100, Marek Szyprowski wrote: > > > I've took all the patches to the next-dma-debug branch in my tree, I sorry > > that You have to wait so long for it. My branch is based on Joerg's > > dma-debug branch and I've included it for testing in linux-next branch. > > The patches are now two times in next. One version from my tree and one > from yours. Please remove the version from your tree, the patches should > go upstream via my dma-debug branch. Ok, I've removed them from my dma-mapping-next tree. Please add/cherry-pick the missing patch for ARM architecture, which I've accidentally already pushed to mainline some time ago and then reverted. See commit 871ae57adc5ed092 (and 697575896670ba). Best regards -- Marek Szyprowski Samsung Poland R&D Center From rostedt@goodmis.org Mon Dec 3 15:40:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Dec 2012 15:40:55 +0100 (CET) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:28342 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6826638Ab2LCOkxW4ywh (ORCPT ); Mon, 3 Dec 2012 15:40:53 +0100 X-Authority-Analysis: v=2.0 cv=f9bK9ZOM c=1 sm=0 a=rXTBtCOcEpjy1lPqhTCpEQ==:17 a=mNMOxpOpBa8A:10 a=XlK8ECWECGUA:10 a=5SG0PmZfjMsA:10 a=Q9fys5e9bTEA:10 a=meVymXHHAAAA:8 a=aYz5cAgaFdEA:10 a=1g4hhj49uufQi-hBbH4A:9 a=PUjeQqilurYA:10 a=rXTBtCOcEpjy1lPqhTCpEQ==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 74.67.115.198 Received: from [74.67.115.198] ([74.67.115.198:52910] helo=[192.168.23.10]) by hrndva-oedge03.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id 3E/1F-18789-0F9BCB05; Mon, 03 Dec 2012 14:40:48 +0000 Message-ID: <1354545648.6276.202.camel@gandalf.local.home> Subject: Re: MIPS Function Tracer question From: Steven Rostedt To: David Daney Cc: Alan Cooper , ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Date: Mon, 03 Dec 2012 09:40:48 -0500 In-Reply-To: <50B7E91C.6070403@gmail.com> References: <50B7E91C.6070403@gmail.com> Content-Type: text/plain; charset="ISO-8859-15" X-Mailer: Evolution 3.4.3-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-archive-position: 35171 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1605 Lines: 35 On Thu, 2012-11-29 at 15:00 -0800, David Daney wrote: > On 11/29/2012 01:04 PM, Alan Cooper wrote: > > I've been doing some testing of the MIPS Function Tracer functionality > > on the 3.3 kernel. I was surprised to find that the option to generate > > frame pointers was required for tracing. > > It is not really required for MIPS function tracing, but the Kconfigs > for some reason set it. > The issue is with x86. Gcc wont compile if you have -pg and -fomit-frame-pointer on x86. I originally forced function tracing to select FRAME_POINTER, but because now on x86 with -mfentry, -pg no longer requires frame pointers being set, I just let -pg complain one way or the other. I believe that gcc by default will not add frame pointers. Thus adding function tracing just prevents -fomit-frame-pointer from being set, and if -pg requires frame pointers it will automatically enable them otherwise they should not be enabled. -- Steve > > When I don't enable > > FRAME_POINTER along with FUNCTION_TRACER, the kernel hangs on boot. I > > also noticed that a checkin to the 3.4 kernel > > (b732d439cb43336cd6d7e804ecb2c81193ef63b0) no longer forces on > > FRAME_POINTER when FUNCTION_TRACER is selected. I was wondering how it > > works in 3.4 and beyond, so I built a Malta kernel from the latest > > MIPS tree with FUNCTION_TRACING enabled and tested it with QEMU. The > > kernel hung the same way. I can think of 2 reasons for this: > > 1. Function tracing is broken for MIPS in 3.4 and beyond. > > 2. The 4.5.3 GNU C compiler I'm using is generating different code for > > function tracing. > From ralf@linux-mips.org Mon Dec 3 17:13:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Dec 2012 17:13:53 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:52260 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6831627Ab2LCQNvjmNDj (ORCPT ); Mon, 3 Dec 2012 17:13:51 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qB3GDmaF029676; Mon, 3 Dec 2012 17:13:48 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qB3GDkin029675; Mon, 3 Dec 2012 17:13:46 +0100 Date: Mon, 3 Dec 2012 17:13:46 +0100 From: Ralf Baechle To: Steven Rostedt Cc: David Daney , Alan Cooper , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: MIPS Function Tracer question Message-ID: <20121203161346.GA29573@linux-mips.org> References: <50B7E91C.6070403@gmail.com> <1354545648.6276.202.camel@gandalf.local.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1354545648.6276.202.camel@gandalf.local.home> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35172 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 744 Lines: 15 On Mon, Dec 03, 2012 at 09:40:48AM -0500, Steven Rostedt wrote: > The issue is with x86. Gcc wont compile if you have -pg and > -fomit-frame-pointer on x86. I originally forced function tracing to > select FRAME_POINTER, but because now on x86 with -mfentry, -pg no > longer requires frame pointers being set, I just let -pg complain one > way or the other. I believe that gcc by default will not add frame > pointers. Thus adding function tracing just prevents > -fomit-frame-pointer from being set, and if -pg requires frame pointers > it will automatically enable them otherwise they should not be enabled. On architectures such as MIPS where a frame pointer is not required for debugging -O and higher imply -fomit-frame-pointer. Ralf From rostedt@goodmis.org Mon Dec 3 18:51:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Dec 2012 18:51:09 +0100 (CET) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:25411 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831625Ab2LCRvHy9Hz3 (ORCPT ); Mon, 3 Dec 2012 18:51:07 +0100 X-Authority-Analysis: v=2.0 cv=Mv7QGhme c=1 sm=0 a=rXTBtCOcEpjy1lPqhTCpEQ==:17 a=mNMOxpOpBa8A:10 a=XlK8ECWECGUA:10 a=5SG0PmZfjMsA:10 a=Q9fys5e9bTEA:10 a=meVymXHHAAAA:8 a=aYz5cAgaFdEA:10 a=s-gwoRVtHMEgTxDo564A:9 a=PUjeQqilurYA:10 a=rXTBtCOcEpjy1lPqhTCpEQ==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 74.67.115.198 Received: from [74.67.115.198] ([74.67.115.198:51994] helo=[192.168.23.10]) by hrndva-oedge02.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id 3F/3F-01392-586ECB05; Mon, 03 Dec 2012 17:51:02 +0000 Message-ID: <1354557056.6276.203.camel@gandalf.local.home> Subject: Re: MIPS Function Tracer question From: Steven Rostedt To: Ralf Baechle Cc: David Daney , Alan Cooper , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Date: Mon, 03 Dec 2012 12:50:56 -0500 In-Reply-To: <20121203161346.GA29573@linux-mips.org> References: <50B7E91C.6070403@gmail.com> <1354545648.6276.202.camel@gandalf.local.home> <20121203161346.GA29573@linux-mips.org> Content-Type: text/plain; charset="ISO-8859-15" X-Mailer: Evolution 3.4.3-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-archive-position: 35173 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 872 Lines: 20 On Mon, 2012-12-03 at 17:13 +0100, Ralf Baechle wrote: > On Mon, Dec 03, 2012 at 09:40:48AM -0500, Steven Rostedt wrote: > > > The issue is with x86. Gcc wont compile if you have -pg and > > -fomit-frame-pointer on x86. I originally forced function tracing to > > select FRAME_POINTER, but because now on x86 with -mfentry, -pg no > > longer requires frame pointers being set, I just let -pg complain one > > way or the other. I believe that gcc by default will not add frame > > pointers. Thus adding function tracing just prevents > > -fomit-frame-pointer from being set, and if -pg requires frame pointers > > it will automatically enable them otherwise they should not be enabled. > > On architectures such as MIPS where a frame pointer is not required for > debugging -O and higher imply -fomit-frame-pointer. Then this shouldn't be an issue for MIPS. -- Steve From ddaney.cavm@gmail.com Mon Dec 3 21:45:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Dec 2012 21:45:45 +0100 (CET) Received: from mail-da0-f49.google.com ([209.85.210.49]:53575 "EHLO mail-da0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831636Ab2LCUpoOvw-L (ORCPT ); Mon, 3 Dec 2012 21:45:44 +0100 Received: by mail-da0-f49.google.com with SMTP id v40so1254200dad.36 for ; Mon, 03 Dec 2012 12:45:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=m+HJq0Wq33Ox8SSh3LJc1eZ1UdkikjWZTanMcBGfa6E=; b=JCJcdEMD6G7xVijHZjQZ1JLrYevrcytt6S5d/Aft5v6ivRSPx4KxLQaV3ATW2nfkk5 HU7f+ALML5bedn9hcC8zMU2VMR2TTmXe9Q1/ciLcgShl1gaM5dZqBl51mYBSeJoXVKsR gddBC6dJZ9qbjQkkutSVS9lkXRL4KWYBwDT61XKhI3MLD0TlW8QihvvN+EG4FoTMi9bO XeUkPEplVNUY/zz4QNrfBC/b9WTE4uSl3FU28ooIGRAmLCcWVAYi8WsVbaB0bR7+1ngK L252NxgP0vx1KKulTLgm9abnwKTf5mtzq557wkrJeiJ4tpetNcR6e0S8jfV+D7i1k2br MHRQ== Received: by 10.68.241.136 with SMTP id wi8mr32648551pbc.95.1354567537076; Mon, 03 Dec 2012 12:45:37 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id is3sm8586189pbc.6.2012.12.03.12.45.33 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 03 Dec 2012 12:45:34 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id qB3KiWYS023605; Mon, 3 Dec 2012 12:44:32 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id qB3KiSH2023603; Mon, 3 Dec 2012 12:44:28 -0800 From: David Daney To: linux-mips@linux-mips.org, Ralf Baechle , linux-kernel@vger.kernel.org Cc: Hillf Danton , David Daney Subject: [PATCH] MIPS: Avoid Machine Check by flushing entire page range in huge_ptep_set_access_flags(). Date: Mon, 3 Dec 2012 12:44:26 -0800 Message-Id: <1354567466-23571-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-archive-position: 35174 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3482 Lines: 104 From: David Daney Problem: 1) Huge page mapping of anonymous memory is initially invalid. Will be faulted in by copy-on-write mechanism. 2) Userspace attempts store at the end of the huge mapping. 3) TLB Refill exception handler fill TLB with a normal (4K sized) invalid page at the end of the huge mapping virtual address range. 4) Userspace restarted, and re-attempts the store at the end of the huge mapping. 5) Page from #3 is invalid, we get a fault and go to the hugepage fault handler. This tries to map a huge page and calls huge_ptep_set_access_flags() to install the mapping. 6) We just call the generic ptep_set_access_flags() to set up the page tables, but the flush there assumes a normal (4K sized) page and only tries to flush the first part of the huge page virtual address out of the TLB, since the existing entry from step #3 doesn't conflict, nothing is flushed. 7) We attempt to load the mapping into the TLB, but because it conflicts with the entry from step #3, we get a Machine Check exception. The fix: Flush the entire rage covered by the huge page in huge_ptep_set_access_flags(), and remove the optimization in local_flush_tlb_range() so that the flush actually does the correct thing. Signed-off-by: David Daney --- arch/mips/include/asm/hugetlb.h | 12 +++++++++++- arch/mips/mm/tlb-r4k.c | 18 ++++-------------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h index 58d3688..68670b1 100644 --- a/arch/mips/include/asm/hugetlb.h +++ b/arch/mips/include/asm/hugetlb.h @@ -95,7 +95,17 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep, pte_t pte, int dirty) { - return ptep_set_access_flags(vma, addr, ptep, pte, dirty); + int changed = !pte_same(*ptep, pte); + + if (changed) { + set_pte_at(vma->vm_mm, addr, ptep, pte); + /* + * There could be some standard sized pages in there, + * get them all. + */ + flush_tlb_range(vma, addr, addr + HPAGE_SIZE); + } + return changed; } static inline pte_t huge_ptep_get(pte_t *ptep) diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index d2572cb..1df4d2f 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -120,18 +120,11 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, if (cpu_context(cpu, mm) != 0) { unsigned long size, flags; - int huge = is_vm_hugetlb_page(vma); ENTER_CRITICAL(flags); - if (huge) { - start = round_down(start, HPAGE_SIZE); - end = round_up(end, HPAGE_SIZE); - size = (end - start) >> HPAGE_SHIFT; - } else { - start = round_down(start, PAGE_SIZE << 1); - end = round_up(end, PAGE_SIZE << 1); - size = (end - start) >> (PAGE_SHIFT + 1); - } + start = round_down(start, PAGE_SIZE << 1); + end = round_up(end, PAGE_SIZE << 1); + size = (end - start) >> (PAGE_SHIFT + 1); if (size <= current_cpu_data.tlbsize/2) { int oldpid = read_c0_entryhi(); int newpid = cpu_asid(cpu, mm); @@ -140,10 +133,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, int idx; write_c0_entryhi(start | newpid); - if (huge) - start += HPAGE_SIZE; - else - start += (PAGE_SIZE << 1); + start += (PAGE_SIZE << 1); mtc0_tlbw_hazard(); tlb_probe(); tlb_probe_hazard(); -- 1.7.11.7 From ralf@linux-mips.org Tue Dec 4 16:54:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Dec 2012 16:54:53 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:56085 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6831636Ab2LDPyvv20rQ (ORCPT ); Tue, 4 Dec 2012 16:54:51 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qB4Fsmci019541; Tue, 4 Dec 2012 16:54:48 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qB4FskiT019540; Tue, 4 Dec 2012 16:54:46 +0100 Date: Tue, 4 Dec 2012 16:54:46 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Hillf Danton , David Daney Subject: Re: [PATCH] MIPS: Avoid Machine Check by flushing entire page range in huge_ptep_set_access_flags(). Message-ID: <20121204155446.GA19472@linux-mips.org> References: <1354567466-23571-1-git-send-email-ddaney.cavm@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1354567466-23571-1-git-send-email-ddaney.cavm@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35175 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 142 Lines: 7 On Mon, Dec 03, 2012 at 12:44:26PM -0800, David Daney wrote: Looks good and has survived my testing so far. Applied. Thanks David! Ralf From ralf@linux-mips.org Tue Dec 4 17:22:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Dec 2012 17:22:29 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:56330 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6829678Ab2LDQWZQYc1n (ORCPT ); Tue, 4 Dec 2012 17:22:25 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qB4GMN9Y021324; Tue, 4 Dec 2012 17:22:23 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qB4GMN1x021323; Tue, 4 Dec 2012 17:22:23 +0100 Date: Tue, 4 Dec 2012 17:22:23 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips Subject: Re: Pull request for v3.8 Octeon specific changes. Message-ID: <20121204162222.GA21111@linux-mips.org> References: <50B94DEB.3020608@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50B94DEB.3020608@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35176 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 618 Lines: 21 On Fri, Nov 30, 2012 at 04:23:07PM -0800, David Daney wrote: > > The ATA changes are alredy Acked-by the ATA mainainer. > > The EDAC changes are just an extension of what you added for 3.8, they > were sent to the EDAC list here: > > http://marc.info/?l=linux-edac&m=135302283022318&w=2 > > But no response yet. My reasoning is that they should be OK as they > just improve things that only touch OCTEON. Yes and it'd be nice to have EDAC flying properly. Lots of MIPS hardware has some EDAC capability. I hope now that there is at least one well supported platform EDAC support will spread. Thanks, Ralf From dczhu@mips.com Wed Dec 5 00:55:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 00:55:16 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:33038 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831642Ab2LDXzOf6xjP (ORCPT ); Wed, 5 Dec 2012 00:55:14 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qB4Nsn3d014708; Tue, 4 Dec 2012 15:54:54 -0800 X-WSS-ID: 0MEJ6FB-01-0OY-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2F0A1364674; Tue, 4 Dec 2012 15:54:46 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Tue, 4 Dec 2012 15:54:45 -0800 From: Deng-Cheng Zhu To: , , , , CC: Subject: [PATCH v3 0/5] MIPS: enable APRP (APSP) and add features - v3 Date: Tue, 4 Dec 2012 15:54:27 -0800 Message-ID: <1354665272-22759-1-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: 2FKDBYOVYDJsx4RzA450JA== X-archive-position: 35178 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2627 Lines: 56 The APRP model makes it possible that one or more CPUs run the Linux kernel whereas a dedicated CPU runs special real-time or signal processing program. This patchset adds the following to the current APRP support: 1. Several bug fixes; 2. Running floating point heavy jobs on the RP side; 3. Waking up RP side read by interrupt; 4. CPS multicore APRP support. A mp3 player program was ported to run in the APRP (APSP exactly) model. Considerable performance benefits were observed on the player program. CodeSourcery tools instead of the old SDE tools were used to build the example. Changes: v3 - v2: o Split CMP/MT flavors into different files -cmp/-mt. o Put Malta needed changes into a separate patch. o Code style adjustments in rtlx/vpe files. o Remove kspd.h which might have been left out in Ralf's kspd removal. v2 - v1: o Rebase the patches to the latest kernel, and fix a bunch of warnings and errors reported by the current scripts/checkpatch.pl. o Add MIPS_MALTA dependency to Kconfig since modifications of Malta files are needed. But it should be easy to port changes to other platforms. Deng-Cheng Zhu (5): MIPS: APRP (APSP): fix/enrich functionality MIPS: APRP (APSP): split vpe-loader and rtlx into cmp/mt flavors MIPS: APRP (APSP): remove kspd.h MIPS: let amon_cpu_start() report results MIPS: APRP (APSP): malta board support arch/mips/Kconfig | 9 + arch/mips/include/asm/amon.h | 2 +- arch/mips/include/asm/kspd.h | 32 - .../include/asm/mach-malta/cpu-feature-overrides.h | 3 + arch/mips/include/asm/rtlx.h | 45 +- arch/mips/include/asm/vpe.h | 118 +++- arch/mips/kernel/Makefile | 9 +- arch/mips/kernel/rtlx-cmp.c | 125 +++ arch/mips/kernel/rtlx-mt.c | 160 ++++ arch/mips/kernel/rtlx.c | 205 +---- arch/mips/kernel/vpe-cmp.c | 202 +++++ arch/mips/kernel/vpe-mt.c | 534 +++++++++++++ arch/mips/kernel/vpe.c | 815 +++----------------- arch/mips/mti-malta/malta-amon.c | 8 +- arch/mips/mti-malta/malta-int.c | 22 +- 15 files changed, 1351 insertions(+), 938 deletions(-) delete mode 100644 arch/mips/include/asm/kspd.h create mode 100644 arch/mips/kernel/rtlx-cmp.c create mode 100644 arch/mips/kernel/rtlx-mt.c create mode 100644 arch/mips/kernel/vpe-cmp.c create mode 100644 arch/mips/kernel/vpe-mt.c From dczhu@mips.com Wed Dec 5 00:55:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 00:55:37 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:33039 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831644Ab2LDXzSo2aOg (ORCPT ); Wed, 5 Dec 2012 00:55:18 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qB4Nssnx014709; Tue, 4 Dec 2012 15:54:58 -0800 X-WSS-ID: 0MEJ6FG-01-0OZ-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2E893364677; Tue, 4 Dec 2012 15:54:51 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Tue, 4 Dec 2012 15:54:46 -0800 From: Deng-Cheng Zhu To: , , , , CC: Subject: [PATCH v3 1/5] MIPS: APRP (APSP): fix/enrich functionality Date: Tue, 4 Dec 2012 15:54:28 -0800 Message-ID: <1354665272-22759-2-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1354665272-22759-1-git-send-email-dczhu@mips.com> References: <1354665272-22759-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: U6UHDacMnzNbMn7mOtZ9OA== X-archive-position: 35179 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 29287 Lines: 1040 This patch makes 34K and CPS like multicore 1004K APRP (also known as APSP) work. Also, it allows the RP side to run floating point heavy jobs and uses interrupt to wake up RP side read. These functionalities need proper RP code to work correctly. To run programs in APRP (APSP) mode on CPS, for example, a 3 core 1004K CPU, one can run SMVP Linux on the first 2 cores and leave a VPE of the 3rd core to run RTOS or signal processing program. The kernel command line option "maxcpus=" needs to be appointed. To run FP intensive RP/SP side program on a Kf CPU, currently we simply disable the FPU on the AP side. And RP will init it and use it exclusively. Signed-off-by: Deng-Cheng Zhu --- arch/mips/Kconfig | 9 ++ arch/mips/include/asm/rtlx.h | 5 + arch/mips/kernel/rtlx.c | 190 +++++++++++++++++++++----- arch/mips/kernel/vpe.c | 302 ++++++++++++++++++++++++++++++------------ 4 files changed, 381 insertions(+), 125 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index dba9390..f4d4888 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2036,6 +2036,15 @@ config MIPS_VPE_LOADER_TOM you to ensure the amount you put in the option and the space your program requires is less or equal to the amount physically present. +config MIPS_SP_FP_INTENSIVE + bool "SP is used for running FP-intensive jobs" + depends on MIPS_VPE_LOADER + ---help--- + If you intend to use the SP to run FP-intensive jobs, you probably + want to say yes here. Your FPU will then be exclusively used by the + SP, and the Linux on the AP side will not see the FPU. Make sure you + know what it does when choosing this option. + # this should possibly be in drivers/char, but it is rather cpu related. Hmmm config MIPS_VPE_APSP_API bool "Enable support for AP/SP API (RTLX)" diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h index 4ca3063..478349e 100644 --- a/arch/mips/include/asm/rtlx.h +++ b/arch/mips/include/asm/rtlx.h @@ -28,6 +28,8 @@ extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count); extern unsigned int rtlx_read_poll(int index, int can_sleep); extern unsigned int rtlx_write_poll(int index); +extern void (*aprp_hook)(void); + enum rtlx_state { RTLX_STATE_UNUSED = 0, RTLX_STATE_INITIALISED, @@ -58,6 +60,9 @@ struct rtlx_channel { struct rtlx_info { unsigned long id; enum rtlx_state state; +#ifdef CONFIG_MIPS_CMP + int ap_int_pending; +#endif struct rtlx_channel channel[RTLX_CHANNELS]; }; diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index b8c18dc..eeda8a2 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2005, 2012 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2005, 06 Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can distribute it and/or modify it @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -54,15 +55,40 @@ static struct chan_waitqueues { static struct vpe_notifications notify; static int sp_stopping; +static int cpu_idx; +static void null_aprp_hook(void) {}; + +void (*aprp_hook)(void) = null_aprp_hook; extern void *vpe_get_shared(int index); +#ifdef CONFIG_MIPS_CMP +static void rtlx_interrupt(void) +{ + int i; + struct rtlx_info *info; + struct rtlx_info **p = vpe_get_shared(cpu_idx); + + if (p == NULL || *p == NULL) + return; + + info = *p; + + if (info->ap_int_pending == 1 && smp_processor_id() == 0) { + for (i = 0; i < RTLX_CHANNELS; i++) { + wake_up(&channel_wqs[i].lx_queue); + wake_up(&channel_wqs[i].rt_queue); + } + info->ap_int_pending = 0; + } +} +#else static void rtlx_dispatch(void) { - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); + if (read_c0_cause() & read_c0_status() & C_SW0) + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); } - /* Interrupt handler may be called before rtlx_init has otherwise had a chance to run. */ @@ -81,12 +107,13 @@ static irqreturn_t rtlx_interrupt(int irq, void *dev_id) local_irq_restore(flags); for (i = 0; i < RTLX_CHANNELS; i++) { - wake_up(&channel_wqs[i].lx_queue); - wake_up(&channel_wqs[i].rt_queue); + wake_up(&channel_wqs[i].lx_queue); + wake_up(&channel_wqs[i].rt_queue); } return IRQ_HANDLED; } +#endif static void __used dump_rtlx(void) { @@ -115,8 +142,7 @@ static void __used dump_rtlx(void) static int rtlx_init(struct rtlx_info *rtlxi) { if (rtlxi->id != RTLX_ID) { - printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n", - rtlxi, rtlxi->id); + pr_err("no valid RTLX id at 0x%p 0x%lx\n", rtlxi, rtlxi->id); return -ENOEXEC; } @@ -157,30 +183,30 @@ int rtlx_open(int index, int can_sleep) int ret = 0; if (index >= RTLX_CHANNELS) { - printk(KERN_DEBUG "rtlx_open index out of range\n"); + pr_debug("rtlx_open index out of range\n"); return -ENOSYS; } if (atomic_inc_return(&channel_wqs[index].in_open) > 1) { - printk(KERN_DEBUG "rtlx_open channel %d already opened\n", - index); + pr_debug("rtlx_open channel %d already opened\n", index); ret = -EBUSY; goto out_fail; } if (rtlx == NULL) { - if( (p = vpe_get_shared(tclimit)) == NULL) { - if (can_sleep) { - __wait_event_interruptible(channel_wqs[index].lx_queue, - (p = vpe_get_shared(tclimit)), ret); - if (ret) + p = vpe_get_shared(cpu_idx); + if (p == NULL) { + if (can_sleep) { + __wait_event_interruptible( + channel_wqs[index].lx_queue, + (p = vpe_get_shared(cpu_idx)), ret); + if (ret) + goto out_fail; + } else { + pr_debug("No SP program loaded, and device opened with O_NONBLOCK\n"); + ret = -ENOSYS; goto out_fail; - } else { - printk(KERN_DEBUG "No SP program loaded, and device " - "opened with O_NONBLOCK\n"); - ret = -ENOSYS; - goto out_fail; - } + } } smp_rmb(); @@ -204,16 +230,14 @@ int rtlx_open(int index, int can_sleep) } finish_wait(&channel_wqs[index].lx_queue, &wait); } else { - pr_err(" *vpe_get_shared is NULL. " - "Has an SP program been loaded?\n"); + pr_err(" *vpe_get_shared is NULL. Has an SP program been loaded?\n"); ret = -ENOSYS; goto out_fail; } } if ((unsigned int)*p < KSEG0) { - printk(KERN_WARNING "vpe_get_shared returned an " - "invalid pointer maybe an error code %d\n", + pr_warn("vpe_get_shared returned an invalid pointer maybe an error code %d\n", (int)*p); ret = -ENOSYS; goto out_fail; @@ -343,6 +367,25 @@ out: return count; } +#ifdef CONFIG_MIPS_CMP +static void _interrupt_sp(void) +{ + smp_send_reschedule(cpu_idx); +} +#else +static void _interrupt_sp(void) +{ + unsigned long flags; + + local_irq_save(flags); + dvpe(); + settc(1); + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); + evpe(EVPE_ENABLE); + local_irq_restore(flags); +} +#endif + ssize_t rtlx_write(int index, const void __user *buffer, size_t count) { struct rtlx_channel *rt; @@ -383,6 +426,8 @@ out: smp_wmb(); mutex_unlock(&channel_wqs[index].mutex); + _interrupt_sp(); + return count; } @@ -470,6 +515,72 @@ static const struct file_operations rtlx_fops = { .llseek = noop_llseek, }; +static char register_chrdev_failed[] __initdata = + KERN_ERR "rtlx_module_init: unable to register device\n"; + +#ifdef CONFIG_MIPS_CMP +static int __init rtlx_module_init(void) +{ + struct device *dev; + int i, err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + cpu_idx = setup_max_cpus; + + if (num_possible_cpus() - cpu_idx < 1) { + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" + "Pass maxcpus= argument as kernel argument\n"); + + return -ENODEV; + } + + major = register_chrdev(0, module_name, &rtlx_fops); + if (major < 0) { + printk(register_chrdev_failed); + return major; + } + + /* initialise the wait queues */ + for (i = 0; i < RTLX_CHANNELS; i++) { + init_waitqueue_head(&channel_wqs[i].rt_queue); + init_waitqueue_head(&channel_wqs[i].lx_queue); + atomic_set(&channel_wqs[i].in_open, 0); + mutex_init(&channel_wqs[i].mutex); + + dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, + "%s%d", module_name, i); + if (IS_ERR(dev)) { + err = PTR_ERR(dev); + goto out_chrdev; + } + } + + /* set up notifiers */ + notify.start = starting; + notify.stop = stopping; + vpe_notify(cpu_idx, ¬ify); + + if (cpu_has_vint) { + aprp_hook = rtlx_interrupt; + } else { + pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); + err = -ENODEV; + goto out_chrdev; + } + + return 0; + +out_chrdev: + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + return err; +} +#else static struct irqaction rtlx_irq = { .handler = rtlx_interrupt, .name = "RTLX", @@ -477,23 +588,21 @@ static struct irqaction rtlx_irq = { static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; -static char register_chrdev_failed[] __initdata = - KERN_ERR "rtlx_module_init: unable to register device\n"; - static int __init rtlx_module_init(void) { struct device *dev; int i, err; if (!cpu_has_mipsmt) { - printk("VPE loader: not a MIPS MT capable processor\n"); + pr_warn("VPE loader: not a MIPS MT capable processor\n"); return -ENODEV; } - if (tclimit == 0) { - printk(KERN_WARNING "No TCs reserved for AP/SP, not " - "initializing RTLX.\nPass maxtcs= argument as kernel " - "argument\n"); + cpu_idx = tclimit; + + if (cpu_idx == 0) { + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" + "Pass maxtcs= argument as kernel argument\n"); return -ENODEV; } @@ -522,11 +631,16 @@ static int __init rtlx_module_init(void) /* set up notifiers */ notify.start = starting; notify.stop = stopping; - vpe_notify(tclimit, ¬ify); + vpe_notify(cpu_idx, ¬ify); - if (cpu_has_vint) - set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); - else { + if (cpu_has_vint) { + /* + * set_vi_handler() doesn't work in some cases: When sw0 + * gets set, a hw interrupt is signaled as well. Here we + * are hooking it into platform specific dispatch. + */ + aprp_hook = rtlx_dispatch; + } else { pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); err = -ENODEV; goto out_chrdev; @@ -543,6 +657,7 @@ out_chrdev: return err; } +#endif static void __exit rtlx_module_exit(void) { @@ -552,6 +667,7 @@ static void __exit rtlx_module_exit(void) device_destroy(mt_class, MKDEV(major, i)); unregister_chrdev(major, module_name); + aprp_hook = null_aprp_hook; } module_init(rtlx_module_init); diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index eec690a..a558bbe 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2004, 2005, 2012 MIPS Technologies, Inc. All rights reserved. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -63,6 +63,7 @@ typedef void *vpe_handle; /* * The number of TCs and VPEs physically available on the core */ +static int cpu_idx; static int hw_tcs, hw_vpes; static char module_name[] = "vpe"; static int major; @@ -365,9 +366,8 @@ static int apply_r_mips_gprel16(struct module *me, uint32_t *location, } if( (rel > 32768) || (rel < -32768) ) { - printk(KERN_DEBUG "VPE loader: apply_r_mips_gprel16: " - "relative address 0x%x out of range of gp register\n", - rel); + pr_debug("VPE loader: apply_r_mips_gprel16: relative address 0x%x out of range of gp register\n", + rel); return -ENOEXEC; } @@ -381,12 +381,12 @@ static int apply_r_mips_pc16(struct module *me, uint32_t *location, { int rel; rel = (((unsigned int)v - (unsigned int)location)); - rel >>= 2; // because the offset is in _instructions_ not bytes. - rel -= 1; // and one instruction less due to the branch delay slot. + rel >>= 2; /* because the offset is in _instructions_ not bytes. */ + rel -= 1; /* and one instruction less due to the branch delay slot. */ if( (rel > 32768) || (rel < -32768) ) { - printk(KERN_DEBUG "VPE loader: " - "apply_r_mips_pc16: relative address out of range 0x%x\n", rel); + pr_debug("VPE loader: apply_r_mips_pc16: relative address out of range 0x%x\n", + rel); return -ENOEXEC; } @@ -407,8 +407,7 @@ static int apply_r_mips_26(struct module *me, uint32_t *location, Elf32_Addr v) { if (v % 4) { - printk(KERN_DEBUG "VPE loader: apply_r_mips_26 " - " unaligned relocation\n"); + pr_debug("VPE loader: apply_r_mips_26 unaligned relocation\n"); return -ENOEXEC; } @@ -471,9 +470,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, * The value for the HI16 had best be the same. */ if (v != l->value) { - printk(KERN_DEBUG "VPE loader: " - "apply_r_mips_lo16/hi16: \t" - "inconsistent value information\n"); + pr_debug("VPE loader: apply_r_mips_lo16/hi16: \tinconsistent value information\n"); goto out_free; } @@ -569,7 +566,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs, + ELF32_R_SYM(r_info); if (!sym->st_value) { - printk(KERN_DEBUG "%s: undefined weak symbol %s\n", + pr_debug("%s: undefined weak symbol %s\n", me->name, strtab + sym->st_name); /* just print the warning, dont barf */ } @@ -579,10 +576,9 @@ static int apply_relocations(Elf32_Shdr *sechdrs, res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); if( res ) { char *r = rstrs[ELF32_R_TYPE(r_info)]; - printk(KERN_WARNING "VPE loader: .text+0x%x " - "relocation type %s for symbol \"%s\" failed\n", - rel[i].r_offset, r ? r : "UNKNOWN", - strtab + sym->st_name); + pr_warn("VPE loader: .text+0x%x relocation type %s for symbol \"%s\" failed\n", + rel[i].r_offset, r ? r : "UNKNOWN", + strtab + sym->st_name); return res; } } @@ -641,10 +637,9 @@ static void simplify_symbols(Elf_Shdr * sechdrs, break; case SHN_MIPS_SCOMMON: - printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON " - "symbol <%s> st_shndx %d\n", strtab + sym[i].st_name, - sym[i].st_shndx); - // .sbss section + pr_debug("simplify_symbols: ignoring SHN_MIPS_SCOMMON symbol <%s> st_shndx %d\n", + strtab + sym[i].st_name, sym[i].st_shndx); + /* .sbss section */ break; default: @@ -667,14 +662,17 @@ static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex, Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); - printk(KERN_DEBUG "dump_elfsymbols: n %d\n", n); + pr_debug("dump_elfsymbols: n %d\n", n); for (i = 1; i < n; i++) { - printk(KERN_DEBUG " i %d name <%s> 0x%x\n", i, - strtab + sym[i].st_name, sym[i].st_value); + pr_debug(" i %d name <%s> 0x%x\n", i, strtab + sym[i].st_name, + sym[i].st_value); } } #endif +#ifdef CONFIG_MIPS_CMP +#error CMP vpe_run() not implemented! +#else /* We are prepared so configure and start the VPE... */ static int vpe_run(struct vpe * v) { @@ -687,8 +685,7 @@ static int vpe_run(struct vpe * v) local_irq_save(flags); val = read_c0_vpeconf0(); if (!(val & VPECONF0_MVP)) { - printk(KERN_WARNING - "VPE loader: only Master VPE's are allowed to configure MT\n"); + pr_warn("VPE loader: only Master VPE's are allowed to configure MT\n"); local_irq_restore(flags); return -1; @@ -703,9 +700,8 @@ static int vpe_run(struct vpe * v) emt(dmt_flag); local_irq_restore(flags); - printk(KERN_WARNING - "VPE loader: TC %d is already in use.\n", - t->index); + pr_warn("VPE loader: TC %d is already in use.\n", + t->index); return -ENOEXEC; } } else { @@ -713,9 +709,8 @@ static int vpe_run(struct vpe * v) emt(dmt_flag); local_irq_restore(flags); - printk(KERN_WARNING - "VPE loader: No TC's associated with VPE %d\n", - v->minor); + pr_warn("VPE loader: No TC's associated with VPE %d\n", + v->minor); return -ENOEXEC; } @@ -731,8 +726,7 @@ static int vpe_run(struct vpe * v) emt(dmt_flag); local_irq_restore(flags); - printk(KERN_WARNING "VPE loader: TC %d is already active!\n", - t->index); + pr_warn("VPE loader: TC %d is already active!\n", t->index); return -ENOEXEC; } @@ -804,6 +798,7 @@ static int vpe_run(struct vpe * v) return 0; } +#endif /* CONFIG_MIPS_CMP */ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, unsigned int symindex, const char *strtab, @@ -854,8 +849,7 @@ static int vpe_elfload(struct vpe * v) || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) || !elf_check_arch(hdr) || hdr->e_shentsize != sizeof(*sechdrs)) { - printk(KERN_WARNING - "VPE loader: program wrong arch or weird elf version\n"); + pr_warn("VPE loader: program wrong arch or weird elf version\n"); return -ENOEXEC; } @@ -864,8 +858,7 @@ static int vpe_elfload(struct vpe * v) relocate = 1; if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { - printk(KERN_ERR "VPE loader: program length %u truncated\n", - len); + pr_err("VPE loader: program length %u truncated\n", len); return -ENOEXEC; } @@ -882,7 +875,7 @@ static int vpe_elfload(struct vpe * v) for (i = 1; i < hdr->e_shnum; i++) { if (sechdrs[i].sh_type != SHT_NOBITS && len < sechdrs[i].sh_offset + sechdrs[i].sh_size) { - printk(KERN_ERR "VPE program length %u truncated\n", + pr_err("VPE program length %u truncated\n", len); return -ENOEXEC; } @@ -922,8 +915,9 @@ static int vpe_elfload(struct vpe * v) /* Update sh_addr to point to copy in image. */ sechdrs[i].sh_addr = (unsigned long)dest; - printk(KERN_DEBUG " section sh_name %s sh_addr 0x%x\n", - secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr); + pr_debug(" section sh_name %s sh_addr 0x%x\n", + secstrings + sechdrs[i].sh_name, + sechdrs[i].sh_addr); } /* Fix up syms, so that st_value is a pointer to location. */ @@ -987,21 +981,25 @@ static int vpe_elfload(struct vpe * v) if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { if (v->__start == 0) { - printk(KERN_WARNING "VPE loader: program does not contain " - "a __start symbol\n"); + pr_warn("VPE loader: program does not contain a __start symbol\n"); return -ENOEXEC; } if (v->shared_ptr == NULL) - printk(KERN_WARNING "VPE loader: " - "program does not contain vpe_shared symbol.\n" - " Unable to use AMVP (AP/SP) facilities.\n"); + pr_warn("VPE loader: program does not contain vpe_shared symbol.\n" + " Unable to use AMVP (AP/SP) facilities.\n"); } - printk(" elf loaded\n"); + pr_info(" elf loaded\n"); return 0; } +#ifdef CONFIG_MIPS_CMP +static void cleanup_tc(struct tc *tc) +{ + +} +#else static void cleanup_tc(struct tc *tc) { unsigned long flags; @@ -1033,6 +1031,7 @@ static void cleanup_tc(struct tc *tc) emt(mtflags); local_irq_restore(flags); } +#endif static int getcwd(char *buff, int size) { @@ -1064,7 +1063,8 @@ static int vpe_open(struct inode *inode, struct file *filp) return -ENODEV; } - if ((v = get_vpe(tclimit)) == NULL) { + v = get_vpe(cpu_idx); + if (v == NULL) { pr_warning("VPE loader: unable to get vpe\n"); return -ENODEV; @@ -1072,14 +1072,14 @@ static int vpe_open(struct inode *inode, struct file *filp) state = xchg(&v->state, VPE_STATE_INUSE); if (state != VPE_STATE_UNUSED) { - printk(KERN_DEBUG "VPE loader: tc in use dumping regs\n"); + pr_debug("VPE loader: tc in use dumping regs\n"); list_for_each_entry(not, &v->notify, list) { - not->stop(tclimit); + not->stop(cpu_idx); } release_progmem(v->load_addr); - cleanup_tc(get_tc(tclimit)); + cleanup_tc(get_tc(cpu_idx)); } /* this of-course trashes what was there before... */ @@ -1098,7 +1098,7 @@ static int vpe_open(struct inode *inode, struct file *filp) v->cwd[0] = 0; ret = getcwd(v->cwd, VPE_PATH_MAX); if (ret < 0) - printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret); + pr_warn("VPE loader: open, getcwd returned %d\n", ret); v->shared_ptr = NULL; v->__start = 0; @@ -1112,7 +1112,8 @@ static int vpe_release(struct inode *inode, struct file *filp) Elf_Ehdr *hdr; int ret = 0; - v = get_vpe(tclimit); + v = get_vpe(cpu_idx); + if (v == NULL) return -ENODEV; @@ -1121,11 +1122,11 @@ static int vpe_release(struct inode *inode, struct file *filp) if (vpe_elfload(v) >= 0) { vpe_run(v); } else { - printk(KERN_WARNING "VPE loader: ELF load failed.\n"); + pr_warn("VPE loader: ELF load failed.\n"); ret = -ENOEXEC; } } else { - printk(KERN_WARNING "VPE loader: only elf files are supported\n"); + pr_warn("VPE loader: only elf files are supported\n"); ret = -ENOEXEC; } @@ -1152,7 +1153,8 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, if (iminor(file->f_path.dentry->d_inode) != minor) return -ENODEV; - v = get_vpe(tclimit); + v = get_vpe(cpu_idx); + if (v == NULL) return -ENODEV; @@ -1178,6 +1180,7 @@ static const struct file_operations vpe_fops = { .llseek = noop_llseek, }; +#ifndef CONFIG_MIPS_CMP /* module wrapper entry points */ /* give me a vpe */ vpe_handle vpe_alloc(void) @@ -1265,6 +1268,7 @@ int vpe_free(vpe_handle vpe) } EXPORT_SYMBOL(vpe_free); +#endif /* CONFIG_MIPS_CMP */ void *vpe_get_shared(int index) { @@ -1327,18 +1331,62 @@ char *vpe_getcwd(int index) EXPORT_SYMBOL(vpe_getcwd); +#ifdef CONFIG_MIPS_CMP static ssize_t store_kill(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { - struct vpe *vpe = get_vpe(tclimit); + struct vpe *vpe = get_vpe(cpu_idx); struct vpe_notifications *not; list_for_each_entry(not, &vpe->notify, list) { - not->stop(tclimit); + not->stop(cpu_idx); } release_progmem(vpe->load_addr); - cleanup_tc(get_tc(tclimit)); + vpe->state = VPE_STATE_UNUSED; + + return len; +} + +static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, + char *buf) +{ + struct vpe *vpe = get_vpe(cpu_idx); + + return sprintf(buf, "%d\n", vpe->ntcs); +} + +static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(cpu_idx); + unsigned long new; + int ret; + + ret = kstrtoul(buf, 0, &new); + if (ret < 0) + return ret; + + if (new != 1) + return -EINVAL; + + vpe->ntcs = new; + + return len; +} +#else +static ssize_t store_kill(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(cpu_idx); + struct vpe_notifications *not; + + list_for_each_entry(not, &vpe->notify, list) { + not->stop(cpu_idx); + } + + release_progmem(vpe->load_addr); + cleanup_tc(get_tc(cpu_idx)); vpe_stop(vpe); vpe_free(vpe); @@ -1348,7 +1396,7 @@ static ssize_t store_kill(struct device *dev, struct device_attribute *attr, static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, char *buf) { - struct vpe *vpe = get_vpe(tclimit); + struct vpe *vpe = get_vpe(cpu_idx); return sprintf(buf, "%d\n", vpe->ntcs); } @@ -1356,24 +1404,22 @@ static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { - struct vpe *vpe = get_vpe(tclimit); + struct vpe *vpe = get_vpe(cpu_idx); unsigned long new; - char *endp; + int ret; - new = simple_strtoul(buf, &endp, 0); - if (endp == buf) - goto out_einval; + ret = kstrtoul(buf, 0, &new); + if (ret < 0) + return ret; - if (new == 0 || new > (hw_tcs - tclimit)) - goto out_einval; + if (new == 0 || new > (hw_tcs - cpu_idx)) + return -EINVAL; vpe->ntcs = new; return len; - -out_einval: - return -EINVAL; } +#endif /* CONFIG_MIPS_CMP */ static struct device_attribute vpe_class_attributes[] = { __ATTR(kill, S_IWUSR, NULL, store_kill), @@ -1395,6 +1441,84 @@ struct class vpe_class = { struct device vpe_device; +#ifdef CONFIG_MIPS_CMP +static int __init vpe_module_init(void) +{ + struct vpe *v = NULL; + struct tc *t; + int err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + cpu_idx = setup_max_cpus; + + if (num_possible_cpus() - cpu_idx < 1) { + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxcpus= argument as kernel argument\n"); + return -ENODEV; + } + + major = register_chrdev(0, module_name, &vpe_fops); + if (major < 0) { + pr_warn("VPE loader: unable to register character device\n"); + return major; + } + + err = class_register(&vpe_class); + if (err) { + pr_err("vpe_class registration failed\n"); + goto out_chrdev; + } + + device_initialize(&vpe_device); + vpe_device.class = &vpe_class, + vpe_device.parent = NULL, + dev_set_name(&vpe_device, "vpe_sp"); + vpe_device.devt = MKDEV(major, minor); + err = device_add(&vpe_device); + if (err) { + pr_err("Adding vpe_device failed\n"); + goto out_class; + } + + t = alloc_tc(cpu_idx); + if (!t) { + pr_warn("VPE: unable to allocate TC\n"); + err = -ENOMEM; + goto out; + } + + /* VPE */ + v = alloc_vpe(cpu_idx); + if (v == NULL) { + pr_warn("VPE: unable to allocate VPE\n"); + kfree(t); + err = -ENOMEM; + goto out; + } + + v->ntcs = 1; + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); + + /* TC */ + t->pvpe = v; /* set the parent vpe */ + + return 0; + +out_class: + class_unregister(&vpe_class); +out_chrdev: + unregister_chrdev(major, module_name); + +out: + return err; +} +#else static int __init vpe_module_init(void) { unsigned int mtflags, vpflags; @@ -1404,35 +1528,35 @@ static int __init vpe_module_init(void) int tc, err; if (!cpu_has_mipsmt) { - printk("VPE loader: not a MIPS MT capable processor\n"); + pr_warn("VPE loader: not a MIPS MT capable processor\n"); return -ENODEV; } if (vpelimit == 0) { - printk(KERN_WARNING "No VPEs reserved for AP/SP, not " - "initializing VPE loader.\nPass maxvpes= argument as " - "kernel argument\n"); + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxvpes= argument as kernel argument\n"); return -ENODEV; } - if (tclimit == 0) { - printk(KERN_WARNING "No TCs reserved for AP/SP, not " - "initializing VPE loader.\nPass maxtcs= argument as " - "kernel argument\n"); + cpu_idx = tclimit; + + if (cpu_idx == 0) { + pr_warn("No TCs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxtcs= argument as kernel argument\n"); return -ENODEV; } major = register_chrdev(0, module_name, &vpe_fops); if (major < 0) { - printk("VPE loader: unable to register character device\n"); + pr_warn("VPE loader: unable to register character device\n"); return major; } err = class_register(&vpe_class); if (err) { - printk(KERN_ERR "vpe_class registration failed\n"); + pr_err("vpe_class registration failed\n"); goto out_chrdev; } @@ -1443,7 +1567,7 @@ static int __init vpe_module_init(void) vpe_device.devt = MKDEV(major, minor); err = device_add(&vpe_device); if (err) { - printk(KERN_ERR "Adding vpe_device failed\n"); + pr_err("Adding vpe_device failed\n"); goto out_class; } @@ -1460,7 +1584,7 @@ static int __init vpe_module_init(void) hw_tcs = (val & MVPCONF0_PTC) + 1; hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; - for (tc = tclimit; tc < hw_tcs; tc++) { + for (tc = cpu_idx; tc < hw_tcs; tc++) { /* * Must re-enable multithreading temporarily or in case we * reschedule send IPIs or similar we might hang. @@ -1484,19 +1608,20 @@ static int __init vpe_module_init(void) if (tc < hw_tcs) { settc(tc); - if ((v = alloc_vpe(tc)) == NULL) { - printk(KERN_WARNING "VPE: unable to allocate VPE\n"); + v = alloc_vpe(tc); + if (v == NULL) { + pr_warn("VPE: unable to allocate VPE\n"); goto out_reenable; } - v->ntcs = hw_tcs - tclimit; + v->ntcs = hw_tcs - cpu_idx; /* add the tc to the list of this vpe's tc's. */ list_add(&t->tc, &v->tc); /* deactivate all but vpe0 */ - if (tc >= tclimit) { + if (tc >= cpu_idx) { unsigned long tmp = read_vpe_c0_vpeconf0(); tmp &= ~VPECONF0_VPA; @@ -1521,7 +1646,7 @@ static int __init vpe_module_init(void) /* TC's */ t->pvpe = v; /* set the parent vpe */ - if (tc >= tclimit) { + if (tc >= cpu_idx) { unsigned long tmp; settc(tc); @@ -1574,6 +1699,7 @@ out_chrdev: out: return err; } +#endif /* CONFIG_MIPS_CMP */ static void __exit vpe_module_exit(void) { -- 1.7.1 From dczhu@mips.com Wed Dec 5 00:55:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 00:56:02 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:33041 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831647Ab2LDXzYtkfBF (ORCPT ); Wed, 5 Dec 2012 00:55:24 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qB4Nsxk5014711; Tue, 4 Dec 2012 15:55:03 -0800 X-WSS-ID: 0MEJ6FL-01-0P1-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2384336465A; Tue, 4 Dec 2012 15:54:56 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Tue, 4 Dec 2012 15:54:51 -0800 From: Deng-Cheng Zhu To: , , , , CC: Subject: [PATCH v3 2/5] MIPS: APRP (APSP): split vpe-loader and rtlx into cmp/mt flavors Date: Tue, 4 Dec 2012 15:54:29 -0800 Message-ID: <1354665272-22759-3-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1354665272-22759-1-git-send-email-dczhu@mips.com> References: <1354665272-22759-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: e+xXdxp9PwErpVs1r12lPA== X-archive-position: 35180 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 68140 Lines: 2789 Remove CONFIG_MIPS_CMP #ifdef's by using -cmp/-mt files. Coding style adjustments are made as well. Signed-off-by: Deng-Cheng Zhu --- arch/mips/include/asm/rtlx.h | 40 ++- arch/mips/include/asm/vpe.h | 118 ++++++- arch/mips/kernel/Makefile | 9 +- arch/mips/kernel/rtlx-cmp.c | 125 ++++++ arch/mips/kernel/rtlx-mt.c | 160 ++++++++ arch/mips/kernel/rtlx.c | 285 ++------------- arch/mips/kernel/vpe-cmp.c | 185 +++++++++ arch/mips/kernel/vpe-mt.c | 534 ++++++++++++++++++++++++++ arch/mips/kernel/vpe.c | 873 +++--------------------------------------- 9 files changed, 1238 insertions(+), 1091 deletions(-) create mode 100644 arch/mips/kernel/rtlx-cmp.c create mode 100644 arch/mips/kernel/rtlx-mt.c create mode 100644 arch/mips/kernel/vpe-cmp.c create mode 100644 arch/mips/kernel/vpe-mt.c diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h index 478349e..4f27eab 100644 --- a/arch/mips/include/asm/rtlx.h +++ b/arch/mips/include/asm/rtlx.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2004, 2005, 2012 MIPS Technologies, Inc. All rights reserved. * */ @@ -8,6 +8,8 @@ #include +#define RTLX_MODULE_NAME "rtlx" + #define LX_NODE_BASE 10 #define MIPS_CPU_RTLX_IRQ 0 @@ -15,19 +17,31 @@ #define RTLX_VERSION 2 #define RTLX_xID 0x12345600 #define RTLX_ID (RTLX_xID | RTLX_VERSION) +#define RTLX_BUFFER_SIZE 2048 #define RTLX_CHANNELS 8 #define RTLX_CHANNEL_STDIO 0 #define RTLX_CHANNEL_DBG 1 #define RTLX_CHANNEL_SYSIO 2 -extern int rtlx_open(int index, int can_sleep); -extern int rtlx_release(int index); -extern ssize_t rtlx_read(int index, void __user *buff, size_t count); -extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count); -extern unsigned int rtlx_read_poll(int index, int can_sleep); -extern unsigned int rtlx_write_poll(int index); +void rtlx_starting(int vpe); +void rtlx_stopping(int vpe); + +int rtlx_open(int index, int can_sleep); +int rtlx_release(int index); +ssize_t rtlx_read(int index, void __user *buff, size_t count); +ssize_t rtlx_write(int index, const void __user *buffer, size_t count); +unsigned int rtlx_read_poll(int index, int can_sleep); +unsigned int rtlx_write_poll(int index); + +int __init rtlx_module_init(void); +void __exit rtlx_module_exit(void); +void _interrupt_sp(void); + +extern struct vpe_notifications rtlx_notify; +extern const struct file_operations rtlx_fops; +static inline void null_aprp_hook(void) { } extern void (*aprp_hook)(void); enum rtlx_state { @@ -37,7 +51,12 @@ enum rtlx_state { RTLX_STATE_OPENED }; -#define RTLX_BUFFER_SIZE 2048 +extern struct chan_waitqueues { + wait_queue_head_t rt_queue; + wait_queue_head_t lx_queue; + atomic_t in_open; + struct mutex mutex; +} channel_wqs[RTLX_CHANNELS]; /* each channel supports read and write. linux (vpe0) reads lx_buffer and writes rt_buffer @@ -57,7 +76,7 @@ struct rtlx_channel { char *lx_buffer; }; -struct rtlx_info { +extern struct rtlx_info { unsigned long id; enum rtlx_state state; #ifdef CONFIG_MIPS_CMP @@ -65,6 +84,5 @@ struct rtlx_info { #endif struct rtlx_channel channel[RTLX_CHANNELS]; -}; - +} *rtlx; #endif /* __ASM_RTLX_H_ */ diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index c6e1b96..4cfc4fd 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2005, 2012 MIPS Technologies, Inc. All rights reserved. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -19,6 +19,88 @@ #ifndef _ASM_VPE_H #define _ASM_VPE_H +#include +#include +#include +#include + +#define VPE_MODULE_NAME "vpe" +#define VPE_MODULE_MINOR 1 + +/* grab the likely amount of memory we will need. */ +#ifdef CONFIG_MIPS_VPE_LOADER_TOM +#define P_SIZE (2 * 1024 * 1024) +#else +/* add an overhead to the max kmalloc size for non-striped symbols/etc */ +#define P_SIZE (256 * 1024) +#endif + +#define MAX_VPES 16 +#define VPE_PATH_MAX 256 + +static inline int aprp_cpu_index(void) +{ +#ifdef CONFIG_MIPS_CMP + return setup_max_cpus; +#else + extern int tclimit; + return tclimit; +#endif +} + +enum vpe_state { + VPE_STATE_UNUSED = 0, + VPE_STATE_INUSE, + VPE_STATE_RUNNING +}; + +enum tc_state { + TC_STATE_UNUSED = 0, + TC_STATE_INUSE, + TC_STATE_RUNNING, + TC_STATE_DYNAMIC +}; + +struct vpe { + enum vpe_state state; + + /* (device) minor associated with this vpe */ + int minor; + + /* elfloader stuff */ + void *load_addr; + unsigned long len; + char *pbuffer; + unsigned long plen; + unsigned int uid, gid; + char cwd[VPE_PATH_MAX]; + + unsigned long __start; + + /* tc's associated with this vpe */ + struct list_head tc; + + /* The list of vpe's */ + struct list_head list; + + /* shared symbol address */ + void *shared_ptr; + + /* the list of who wants to know when something major happens */ + struct list_head notify; + + unsigned int ntcs; +}; + +struct tc { + enum tc_state state; + int index; + + struct vpe *pvpe; /* parent VPE */ + struct list_head tc; /* The list of TC's with this VPE */ + struct list_head list; /* The global list of tc's */ +}; + struct vpe_notifications { void (*start)(int vpe); void (*stop)(int vpe); @@ -26,12 +108,36 @@ struct vpe_notifications { struct list_head list; }; +struct vpe_control { + spinlock_t vpe_list_lock; + struct list_head vpe_list; /* Virtual processing elements */ + spinlock_t tc_list_lock; + struct list_head tc_list; /* Thread contexts */ +}; + +extern unsigned long physical_memsize; +extern struct vpe_control vpecontrol; +extern const struct file_operations vpe_fops; + +int vpe_notify(int index, struct vpe_notifications *notify); + +void *vpe_get_shared(int index); +int vpe_getuid(int index); +int vpe_getgid(int index); +char *vpe_getcwd(int index); + +struct vpe *get_vpe(int minor); +struct tc *get_tc(int index); +struct vpe *alloc_vpe(int minor); +struct tc *alloc_tc(int index); +void release_vpe(struct vpe *v); -extern int vpe_notify(int index, struct vpe_notifications *notify); +void *alloc_progmem(unsigned long len); +void release_progmem(void *ptr); -extern void *vpe_get_shared(int index); -extern int vpe_getuid(int index); -extern int vpe_getgid(int index); -extern char *vpe_getcwd(int index); +int vpe_run(struct vpe *v); +void cleanup_tc(struct tc *tc); +int __init vpe_module_init(void); +void __exit vpe_module_exit(void); #endif /* _ASM_VPE_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 8b28bc4..16f581a 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -52,8 +52,13 @@ obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o obj-$(CONFIG_MIPS_CMP) += smp-cmp.o obj-$(CONFIG_CPU_MIPSR2) += spram.o -obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o -obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o +ifdef CONFIG_MIPS_CMP +obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o vpe-cmp.o +obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o rtlx-cmp.o +else +obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o vpe-mt.o +obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o rtlx-mt.o +endif obj-$(CONFIG_I8259) += i8259.o obj-$(CONFIG_IRQ_CPU) += irq_cpu.o diff --git a/arch/mips/kernel/rtlx-cmp.c b/arch/mips/kernel/rtlx-cmp.c new file mode 100644 index 0000000..61d848b --- /dev/null +++ b/arch/mips/kernel/rtlx-cmp.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2005, 2012 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static int major; + +static void rtlx_interrupt(void) +{ + int i; + struct rtlx_info *info; + struct rtlx_info **p = vpe_get_shared(aprp_cpu_index()); + + if (p == NULL || *p == NULL) + return; + + info = *p; + + if (info->ap_int_pending == 1 && smp_processor_id() == 0) { + for (i = 0; i < RTLX_CHANNELS; i++) { + wake_up(&channel_wqs[i].lx_queue); + wake_up(&channel_wqs[i].rt_queue); + } + info->ap_int_pending = 0; + } +} + +void _interrupt_sp(void) +{ + smp_send_reschedule(aprp_cpu_index()); +} + +int __init rtlx_module_init(void) +{ + struct device *dev; + int i, err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if (num_possible_cpus() - aprp_cpu_index() < 1) { + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" + "Pass maxcpus= argument as kernel argument\n"); + + return -ENODEV; + } + + major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops); + if (major < 0) { + pr_err("rtlx_module_init: unable to register device\n"); + return major; + } + + /* initialise the wait queues */ + for (i = 0; i < RTLX_CHANNELS; i++) { + init_waitqueue_head(&channel_wqs[i].rt_queue); + init_waitqueue_head(&channel_wqs[i].lx_queue); + atomic_set(&channel_wqs[i].in_open, 0); + mutex_init(&channel_wqs[i].mutex); + + dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, + "%s%d", RTLX_MODULE_NAME, i); + if (IS_ERR(dev)) { + err = PTR_ERR(dev); + goto out_chrdev; + } + } + + /* set up notifiers */ + rtlx_notify.start = rtlx_starting; + rtlx_notify.stop = rtlx_stopping; + vpe_notify(aprp_cpu_index(), &rtlx_notify); + + if (cpu_has_vint) { + aprp_hook = rtlx_interrupt; + } else { + pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); + err = -ENODEV; + goto out_chrdev; + } + + return 0; + +out_chrdev: + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + return err; +} + +void __exit rtlx_module_exit(void) +{ + int i; + + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + unregister_chrdev(major, RTLX_MODULE_NAME); + aprp_hook = null_aprp_hook; +} diff --git a/arch/mips/kernel/rtlx-mt.c b/arch/mips/kernel/rtlx-mt.c new file mode 100644 index 0000000..679480a --- /dev/null +++ b/arch/mips/kernel/rtlx-mt.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2005, 2012 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static int major; + +static void rtlx_dispatch(void) +{ + if (read_c0_cause() & read_c0_status() & C_SW0) + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); +} + +/* + * Interrupt handler may be called before rtlx_init has otherwise had + * a chance to run. + */ +static irqreturn_t rtlx_interrupt(int irq, void *dev_id) +{ + unsigned int vpeflags; + unsigned long flags; + int i; + + /* Ought not to be strictly necessary for SMTC builds */ + local_irq_save(flags); + vpeflags = dvpe(); + set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ); + irq_enable_hazard(); + evpe(vpeflags); + local_irq_restore(flags); + + for (i = 0; i < RTLX_CHANNELS; i++) { + wake_up(&channel_wqs[i].lx_queue); + wake_up(&channel_wqs[i].rt_queue); + } + + return IRQ_HANDLED; +} + +static struct irqaction rtlx_irq = { + .handler = rtlx_interrupt, + .name = "RTLX", +}; + +static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; + +void _interrupt_sp(void) +{ + unsigned long flags; + + local_irq_save(flags); + dvpe(); + settc(1); + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); + evpe(EVPE_ENABLE); + local_irq_restore(flags); +} + +int __init rtlx_module_init(void) +{ + struct device *dev; + int i, err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if (aprp_cpu_index() == 0) { + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" + "Pass maxtcs= argument as kernel argument\n"); + + return -ENODEV; + } + + major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops); + if (major < 0) { + pr_err("rtlx_module_init: unable to register device\n"); + return major; + } + + /* initialise the wait queues */ + for (i = 0; i < RTLX_CHANNELS; i++) { + init_waitqueue_head(&channel_wqs[i].rt_queue); + init_waitqueue_head(&channel_wqs[i].lx_queue); + atomic_set(&channel_wqs[i].in_open, 0); + mutex_init(&channel_wqs[i].mutex); + + dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, + "%s%d", RTLX_MODULE_NAME, i); + if (IS_ERR(dev)) { + err = PTR_ERR(dev); + goto out_chrdev; + } + } + + /* set up notifiers */ + rtlx_notify.start = rtlx_starting; + rtlx_notify.stop = rtlx_stopping; + vpe_notify(aprp_cpu_index(), &rtlx_notify); + + if (cpu_has_vint) { + /* + * set_vi_handler() doesn't work in some cases: When sw0 + * gets set, a hw interrupt is signaled as well. Here we + * are hooking it into platform specific dispatch. + */ + aprp_hook = rtlx_dispatch; + } else { + pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); + err = -ENODEV; + goto out_chrdev; + } + + rtlx_irq.dev_id = rtlx; + setup_irq(rtlx_irq_num, &rtlx_irq); + + return 0; + +out_chrdev: + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + return err; +} + +void __exit rtlx_module_exit(void) +{ + int i; + + for (i = 0; i < RTLX_CHANNELS; i++) + device_destroy(mt_class, MKDEV(major, i)); + + unregister_chrdev(major, RTLX_MODULE_NAME); + aprp_hook = null_aprp_hook; +} diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index eeda8a2..287e244 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -36,105 +36,39 @@ #include #include #include -#include #include #include #include #include -static struct rtlx_info *rtlx; -static int major; -static char module_name[] = "rtlx"; - -static struct chan_waitqueues { - wait_queue_head_t rt_queue; - wait_queue_head_t lx_queue; - atomic_t in_open; - struct mutex mutex; -} channel_wqs[RTLX_CHANNELS]; - -static struct vpe_notifications notify; static int sp_stopping; -static int cpu_idx; -static void null_aprp_hook(void) {}; - -void (*aprp_hook)(void) = null_aprp_hook; - -extern void *vpe_get_shared(int index); - -#ifdef CONFIG_MIPS_CMP -static void rtlx_interrupt(void) -{ - int i; - struct rtlx_info *info; - struct rtlx_info **p = vpe_get_shared(cpu_idx); - - if (p == NULL || *p == NULL) - return; - - info = *p; - if (info->ap_int_pending == 1 && smp_processor_id() == 0) { - for (i = 0; i < RTLX_CHANNELS; i++) { - wake_up(&channel_wqs[i].lx_queue); - wake_up(&channel_wqs[i].rt_queue); - } - info->ap_int_pending = 0; - } -} -#else -static void rtlx_dispatch(void) -{ - if (read_c0_cause() & read_c0_status() & C_SW0) - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); -} - -/* Interrupt handler may be called before rtlx_init has otherwise had - a chance to run. -*/ -static irqreturn_t rtlx_interrupt(int irq, void *dev_id) -{ - unsigned int vpeflags; - unsigned long flags; - int i; - - /* Ought not to be strictly necessary for SMTC builds */ - local_irq_save(flags); - vpeflags = dvpe(); - set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ); - irq_enable_hazard(); - evpe(vpeflags); - local_irq_restore(flags); - - for (i = 0; i < RTLX_CHANNELS; i++) { - wake_up(&channel_wqs[i].lx_queue); - wake_up(&channel_wqs[i].rt_queue); - } - - return IRQ_HANDLED; -} -#endif +struct rtlx_info *rtlx; +struct chan_waitqueues channel_wqs[RTLX_CHANNELS]; +struct vpe_notifications rtlx_notify; +void (*aprp_hook)(void); +EXPORT_SYMBOL(aprp_hook); static void __used dump_rtlx(void) { int i; - printk("id 0x%lx state %d\n", rtlx->id, rtlx->state); + pr_debug("id 0x%lx state %d\n", rtlx->id, rtlx->state); for (i = 0; i < RTLX_CHANNELS; i++) { struct rtlx_channel *chan = &rtlx->channel[i]; - printk(" rt_state %d lx_state %d buffer_size %d\n", + pr_debug(" rt_state %d lx_state %d buffer_size %d\n", chan->rt_state, chan->lx_state, chan->buffer_size); - printk(" rt_read %d rt_write %d\n", + pr_debug(" rt_read %d rt_write %d\n", chan->rt_read, chan->rt_write); - printk(" lx_read %d lx_write %d\n", + pr_debug(" lx_read %d lx_write %d\n", chan->lx_read, chan->lx_write); - printk(" rt_buffer <%s>\n", chan->rt_buffer); - printk(" lx_buffer <%s>\n", chan->lx_buffer); + pr_debug(" rt_buffer <%s>\n", chan->rt_buffer); + pr_debug(" lx_buffer <%s>\n", chan->lx_buffer); } } @@ -152,7 +86,7 @@ static int rtlx_init(struct rtlx_info *rtlxi) } /* notifications */ -static void starting(int vpe) +void rtlx_starting(int vpe) { int i; sp_stopping = 0; @@ -165,7 +99,7 @@ static void starting(int vpe) wake_up_interruptible(&channel_wqs[i].lx_queue); } -static void stopping(int vpe) +void rtlx_stopping(int vpe) { int i; @@ -194,12 +128,13 @@ int rtlx_open(int index, int can_sleep) } if (rtlx == NULL) { - p = vpe_get_shared(cpu_idx); + p = vpe_get_shared(aprp_cpu_index()); if (p == NULL) { if (can_sleep) { __wait_event_interruptible( channel_wqs[index].lx_queue, - (p = vpe_get_shared(cpu_idx)), ret); + (p = vpe_get_shared(aprp_cpu_index())), + ret); if (ret) goto out_fail; } else { @@ -238,7 +173,7 @@ int rtlx_open(int index, int can_sleep) if ((unsigned int)*p < KSEG0) { pr_warn("vpe_get_shared returned an invalid pointer maybe an error code %d\n", - (int)*p); + (int)*p); ret = -ENOSYS; goto out_fail; } @@ -276,12 +211,12 @@ int rtlx_release(int index) unsigned int rtlx_read_poll(int index, int can_sleep) { - struct rtlx_channel *chan; + struct rtlx_channel *chan; - if (rtlx == NULL) - return 0; + if (rtlx == NULL) + return 0; - chan = &rtlx->channel[index]; + chan = &rtlx->channel[index]; /* data available to read? */ if (chan->lx_read == chan->lx_write) { @@ -367,25 +302,6 @@ out: return count; } -#ifdef CONFIG_MIPS_CMP -static void _interrupt_sp(void) -{ - smp_send_reschedule(cpu_idx); -} -#else -static void _interrupt_sp(void) -{ - unsigned long flags; - - local_irq_save(flags); - dvpe(); - settc(1); - write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); - evpe(EVPE_ENABLE); - local_irq_restore(flags); -} -#endif - ssize_t rtlx_write(int index, const void __user *buffer, size_t count) { struct rtlx_channel *rt; @@ -473,7 +389,7 @@ static ssize_t file_read(struct file *file, char __user * buffer, size_t count, /* data available? */ if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1)) { - return 0; // -EAGAIN makes cat whinge + return 0; /* -EAGAIN makes cat whinge */ } return rtlx_read(minor, buffer, count); @@ -505,7 +421,7 @@ static ssize_t file_write(struct file *file, const char __user * buffer, return rtlx_write(minor, buffer, count); } -static const struct file_operations rtlx_fops = { +const struct file_operations rtlx_fops = { .owner = THIS_MODULE, .open = file_open, .release = file_release, @@ -515,161 +431,6 @@ static const struct file_operations rtlx_fops = { .llseek = noop_llseek, }; -static char register_chrdev_failed[] __initdata = - KERN_ERR "rtlx_module_init: unable to register device\n"; - -#ifdef CONFIG_MIPS_CMP -static int __init rtlx_module_init(void) -{ - struct device *dev; - int i, err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - cpu_idx = setup_max_cpus; - - if (num_possible_cpus() - cpu_idx < 1) { - pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" - "Pass maxcpus= argument as kernel argument\n"); - - return -ENODEV; - } - - major = register_chrdev(0, module_name, &rtlx_fops); - if (major < 0) { - printk(register_chrdev_failed); - return major; - } - - /* initialise the wait queues */ - for (i = 0; i < RTLX_CHANNELS; i++) { - init_waitqueue_head(&channel_wqs[i].rt_queue); - init_waitqueue_head(&channel_wqs[i].lx_queue); - atomic_set(&channel_wqs[i].in_open, 0); - mutex_init(&channel_wqs[i].mutex); - - dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, - "%s%d", module_name, i); - if (IS_ERR(dev)) { - err = PTR_ERR(dev); - goto out_chrdev; - } - } - - /* set up notifiers */ - notify.start = starting; - notify.stop = stopping; - vpe_notify(cpu_idx, ¬ify); - - if (cpu_has_vint) { - aprp_hook = rtlx_interrupt; - } else { - pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); - err = -ENODEV; - goto out_chrdev; - } - - return 0; - -out_chrdev: - for (i = 0; i < RTLX_CHANNELS; i++) - device_destroy(mt_class, MKDEV(major, i)); - - return err; -} -#else -static struct irqaction rtlx_irq = { - .handler = rtlx_interrupt, - .name = "RTLX", -}; - -static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; - -static int __init rtlx_module_init(void) -{ - struct device *dev; - int i, err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - cpu_idx = tclimit; - - if (cpu_idx == 0) { - pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" - "Pass maxtcs= argument as kernel argument\n"); - - return -ENODEV; - } - - major = register_chrdev(0, module_name, &rtlx_fops); - if (major < 0) { - printk(register_chrdev_failed); - return major; - } - - /* initialise the wait queues */ - for (i = 0; i < RTLX_CHANNELS; i++) { - init_waitqueue_head(&channel_wqs[i].rt_queue); - init_waitqueue_head(&channel_wqs[i].lx_queue); - atomic_set(&channel_wqs[i].in_open, 0); - mutex_init(&channel_wqs[i].mutex); - - dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, - "%s%d", module_name, i); - if (IS_ERR(dev)) { - err = PTR_ERR(dev); - goto out_chrdev; - } - } - - /* set up notifiers */ - notify.start = starting; - notify.stop = stopping; - vpe_notify(cpu_idx, ¬ify); - - if (cpu_has_vint) { - /* - * set_vi_handler() doesn't work in some cases: When sw0 - * gets set, a hw interrupt is signaled as well. Here we - * are hooking it into platform specific dispatch. - */ - aprp_hook = rtlx_dispatch; - } else { - pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); - err = -ENODEV; - goto out_chrdev; - } - - rtlx_irq.dev_id = rtlx; - setup_irq(rtlx_irq_num, &rtlx_irq); - - return 0; - -out_chrdev: - for (i = 0; i < RTLX_CHANNELS; i++) - device_destroy(mt_class, MKDEV(major, i)); - - return err; -} -#endif - -static void __exit rtlx_module_exit(void) -{ - int i; - - for (i = 0; i < RTLX_CHANNELS; i++) - device_destroy(mt_class, MKDEV(major, i)); - - unregister_chrdev(major, module_name); - aprp_hook = null_aprp_hook; -} - module_init(rtlx_module_init); module_exit(rtlx_module_exit); diff --git a/arch/mips/kernel/vpe-cmp.c b/arch/mips/kernel/vpe-cmp.c new file mode 100644 index 0000000..9d0c375 --- /dev/null +++ b/arch/mips/kernel/vpe-cmp.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2004, 2005, 2012 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include + +#include + +static int major; + +#error CMP vpe_run() not implemented! + +void cleanup_tc(struct tc *tc) +{ + +} + +static ssize_t store_kill(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + struct vpe_notifications *not; + + list_for_each_entry(not, &vpe->notify, list) { + not->stop(aprp_cpu_index()); + } + + release_progmem(vpe->load_addr); + vpe->state = VPE_STATE_UNUSED; + + return len; +} + +static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, + char *buf) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + + return sprintf(buf, "%d\n", vpe->ntcs); +} + +static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + unsigned long new; + int ret; + + ret = kstrtoul(buf, 0, &new); + if (ret < 0) + return ret; + + if (new != 1) + return -EINVAL; + + vpe->ntcs = new; + + return len; +} + +static struct device_attribute vpe_class_attributes[] = { + __ATTR(kill, S_IWUSR, NULL, store_kill), + __ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs), + {} +}; + +static void vpe_device_release(struct device *cd) +{ + kfree(cd); +} + +static struct class vpe_class = { + .name = "vpe", + .owner = THIS_MODULE, + .dev_release = vpe_device_release, + .dev_attrs = vpe_class_attributes, +}; + +static struct device vpe_device; + +int __init vpe_module_init(void) +{ + struct vpe *v = NULL; + struct tc *t; + int err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if (num_possible_cpus() - aprp_cpu_index() < 1) { + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxcpus= argument as kernel argument\n"); + return -ENODEV; + } + + major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops); + if (major < 0) { + pr_warn("VPE loader: unable to register character device\n"); + return major; + } + + err = class_register(&vpe_class); + if (err) { + pr_err("vpe_class registration failed\n"); + goto out_chrdev; + } + + device_initialize(&vpe_device); + vpe_device.class = &vpe_class, + vpe_device.parent = NULL, + dev_set_name(&vpe_device, "vpe_sp"); + vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR); + err = device_add(&vpe_device); + if (err) { + pr_err("Adding vpe_device failed\n"); + goto out_class; + } + + t = alloc_tc(aprp_cpu_index()); + if (!t) { + pr_warn("VPE: unable to allocate TC\n"); + err = -ENOMEM; + goto out; + } + + /* VPE */ + v = alloc_vpe(aprp_cpu_index()); + if (v == NULL) { + pr_warn("VPE: unable to allocate VPE\n"); + kfree(t); + err = -ENOMEM; + goto out; + } + + v->ntcs = 1; + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); + + /* TC */ + t->pvpe = v; /* set the parent vpe */ + + return 0; + +out_class: + class_unregister(&vpe_class); +out_chrdev: + unregister_chrdev(major, VPE_MODULE_NAME); + +out: + return err; +} + +void __exit vpe_module_exit(void) +{ + struct vpe *v, *n; + + device_del(&vpe_device); + unregister_chrdev(major, VPE_MODULE_NAME); + + /* No locking needed here */ + list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) { + if (v->state != VPE_STATE_UNUSED) + release_vpe(v); + } +} diff --git a/arch/mips/kernel/vpe-mt.c b/arch/mips/kernel/vpe-mt.c new file mode 100644 index 0000000..0f71d30 --- /dev/null +++ b/arch/mips/kernel/vpe-mt.c @@ -0,0 +1,534 @@ +/* + * Copyright (C) 2004, 2005, 2012 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static int major; +/* The number of TCs and VPEs physically available on the core */ +static int hw_tcs, hw_vpes; + +/* We are prepared so configure and start the VPE... */ +int vpe_run(struct vpe *v) +{ + unsigned long flags, val, dmt_flag; + struct vpe_notifications *n; + unsigned int vpeflags; + struct tc *t; + + /* check we are the Master VPE */ + local_irq_save(flags); + val = read_c0_vpeconf0(); + if (!(val & VPECONF0_MVP)) { + pr_warn("VPE loader: only Master VPE's are able to config MT\n"); + local_irq_restore(flags); + + return -1; + } + + dmt_flag = dmt(); + vpeflags = dvpe(); + + if (!list_empty(&v->tc)) { + t = list_entry(v->tc.next, struct tc, tc); + if (t == NULL) { + evpe(vpeflags); + emt(dmt_flag); + local_irq_restore(flags); + + pr_warn("VPE loader: TC %d is already in use.\n", + t->index); + return -ENOEXEC; + } + } else { + evpe(vpeflags); + emt(dmt_flag); + local_irq_restore(flags); + + pr_warn("VPE loader: No TC's associated with VPE %d\n", + v->minor); + + return -ENOEXEC; + } + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + settc(t->index); + + /* should check it is halted, and not activated */ + if ((read_tc_c0_tcstatus() & TCSTATUS_A) || + !(read_tc_c0_tchalt() & TCHALT_H)) { + evpe(vpeflags); + emt(dmt_flag); + local_irq_restore(flags); + + pr_warn("VPE loader: TC %d is already active!\n", + t->index); + + return -ENOEXEC; + } + + /* + * Write the address we want it to start running from in the TCPC + * register. + */ + write_tc_c0_tcrestart((unsigned long)v->__start); + write_tc_c0_tccontext((unsigned long)0); + + /* + * Mark the TC as activated, not interrupt exempt and not dynamically + * allocatable + */ + val = read_tc_c0_tcstatus(); + val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A; + write_tc_c0_tcstatus(val); + + write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); + + /* + * The sde-kit passes 'memsize' to __start in $a3, so set something + * here... Or set $a3 to zero and define DFLT_STACK_SIZE and + * DFLT_HEAP_SIZE when you compile your program + */ + mttgpr(6, v->ntcs); + mttgpr(7, physical_memsize); + + /* set up VPE1 */ + /* + * bind the TC to VPE 1 as late as possible so we only have the final + * VPE registers to set up, and so an EJTAG probe can trigger on it + */ + write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1); + + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); + + back_to_back_c0_hazard(); + + /* Set up the XTC bit in vpeconf0 to point at our tc */ + write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC)) + | (t->index << VPECONF0_XTC_SHIFT)); + + back_to_back_c0_hazard(); + + /* enable this VPE */ + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); + + /* clear out any left overs from a previous program */ + write_vpe_c0_status(0); + write_vpe_c0_cause(0); + + /* take system out of configuration state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + /* + * SMTC/SMVP kernels manage VPE enable independently, + * but uniprocessor kernels need to turn it on, even + * if that wasn't the pre-dvpe() state. + */ +#ifdef CONFIG_SMP + evpe(vpeflags); +#else + evpe(EVPE_ENABLE); +#endif + emt(dmt_flag); + local_irq_restore(flags); + + list_for_each_entry(n, &v->notify, list) + n->start(VPE_MODULE_MINOR); + + return 0; +} + +void cleanup_tc(struct tc *tc) +{ + unsigned long flags; + unsigned int mtflags, vpflags; + int tmp; + + local_irq_save(flags); + mtflags = dmt(); + vpflags = dvpe(); + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + settc(tc->index); + tmp = read_tc_c0_tcstatus(); + + /* mark not allocated and not dynamically allocatable */ + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ + write_tc_c0_tcstatus(tmp); + + write_tc_c0_tchalt(TCHALT_H); + mips_ihb(); + + clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); +} + +/* module wrapper entry points */ +/* give me a vpe */ +void *vpe_alloc(void) +{ + int i; + struct vpe *v; + + /* find a vpe */ + for (i = 1; i < MAX_VPES; i++) { + v = get_vpe(i); + if (v != NULL) { + v->state = VPE_STATE_INUSE; + return v; + } + } + return NULL; +} +EXPORT_SYMBOL(vpe_alloc); + +/* start running from here */ +int vpe_start(void *vpe, unsigned long start) +{ + struct vpe *v = vpe; + + v->__start = start; + return vpe_run(v); +} +EXPORT_SYMBOL(vpe_start); + +/* halt it for now */ +int vpe_stop(void *vpe) +{ + struct vpe *v = vpe; + struct tc *t; + unsigned int evpe_flags; + + evpe_flags = dvpe(); + + t = list_entry(v->tc.next, struct tc, tc); + if (t != NULL) { + settc(t->index); + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); + } + + evpe(evpe_flags); + + return 0; +} +EXPORT_SYMBOL(vpe_stop); + +/* I've done with it thank you */ +int vpe_free(void *vpe) +{ + struct vpe *v = vpe; + struct tc *t; + unsigned int evpe_flags; + + t = list_entry(v->tc.next, struct tc, tc); + if (t == NULL) + return -ENOEXEC; + + evpe_flags = dvpe(); + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + settc(t->index); + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); + + /* halt the TC */ + write_tc_c0_tchalt(TCHALT_H); + mips_ihb(); + + /* mark the TC unallocated */ + write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A); + + v->state = VPE_STATE_UNUSED; + + clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(evpe_flags); + + return 0; +} +EXPORT_SYMBOL(vpe_free); + +static ssize_t store_kill(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + struct vpe_notifications *not; + + list_for_each_entry(not, &vpe->notify, list) { + not->stop(aprp_cpu_index()); + } + + release_progmem(vpe->load_addr); + cleanup_tc(get_tc(aprp_cpu_index())); + vpe_stop(vpe); + vpe_free(vpe); + + return len; +} + +static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, + char *buf) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + + return sprintf(buf, "%d\n", vpe->ntcs); +} + +static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(aprp_cpu_index()); + unsigned long new; + int ret; + + ret = kstrtoul(buf, 0, &new); + if (ret < 0) + return ret; + + if (new == 0 || new > (hw_tcs - aprp_cpu_index())) + return -EINVAL; + + vpe->ntcs = new; + + return len; +} + +static struct device_attribute vpe_class_attributes[] = { + __ATTR(kill, S_IWUSR, NULL, store_kill), + __ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs), + {} +}; + +static void vpe_device_release(struct device *cd) +{ + kfree(cd); +} + +static struct class vpe_class = { + .name = "vpe", + .owner = THIS_MODULE, + .dev_release = vpe_device_release, + .dev_attrs = vpe_class_attributes, +}; + +static struct device vpe_device; + +int __init vpe_module_init(void) +{ + unsigned int mtflags, vpflags; + unsigned long flags, val; + struct vpe *v = NULL; + struct tc *t; + int tc, err; + + if (!cpu_has_mipsmt) { + pr_warn("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if (vpelimit == 0) { + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxvpes= argument as kernel argument\n"); + + return -ENODEV; + } + + if (aprp_cpu_index() == 0) { + pr_warn("No TCs reserved for AP/SP, not initialize VPE loader\n" + "Pass maxtcs= argument as kernel argument\n"); + + return -ENODEV; + } + + major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops); + if (major < 0) { + pr_warn("VPE loader: unable to register character device\n"); + return major; + } + + err = class_register(&vpe_class); + if (err) { + pr_err("vpe_class registration failed\n"); + goto out_chrdev; + } + + device_initialize(&vpe_device); + vpe_device.class = &vpe_class, + vpe_device.parent = NULL, + dev_set_name(&vpe_device, "vpe1"); + vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR); + err = device_add(&vpe_device); + if (err) { + pr_err("Adding vpe_device failed\n"); + goto out_class; + } + + local_irq_save(flags); + mtflags = dmt(); + vpflags = dvpe(); + + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + + val = read_c0_mvpconf0(); + hw_tcs = (val & MVPCONF0_PTC) + 1; + hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; + + for (tc = aprp_cpu_index(); tc < hw_tcs; tc++) { + /* + * Must re-enable multithreading temporarily or in case we + * reschedule send IPIs or similar we might hang. + */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); + t = alloc_tc(tc); + if (!t) { + err = -ENOMEM; + goto out; + } + + local_irq_save(flags); + mtflags = dmt(); + vpflags = dvpe(); + set_c0_mvpcontrol(MVPCONTROL_VPC); + + /* VPE's */ + if (tc < hw_tcs) { + settc(tc); + + v = alloc_vpe(tc); + if (v == NULL) { + pr_warn("VPE: unable to allocate VPE\n"); + goto out_reenable; + } + + v->ntcs = hw_tcs - aprp_cpu_index(); + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); + + /* deactivate all but vpe0 */ + if (tc >= aprp_cpu_index()) { + unsigned long tmp = read_vpe_c0_vpeconf0(); + + tmp &= ~VPECONF0_VPA; + + /* master VPE */ + tmp |= VPECONF0_MVP; + write_vpe_c0_vpeconf0(tmp); + } + + /* disable multi-threading with TC's */ + write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & + ~VPECONTROL_TE); + + if (tc >= vpelimit) { + /* + * Set config to be the same as vpe0, + * particularly kseg0 coherency alg + */ + write_vpe_c0_config(read_c0_config()); + } + } + + /* TC's */ + t->pvpe = v; /* set the parent vpe */ + + if (tc >= aprp_cpu_index()) { + unsigned long tmp; + + settc(tc); + + /* Any TC that is bound to VPE0 gets left as is - in + * case we are running SMTC on VPE0. A TC that is bound + * to any other VPE gets bound to VPE0, ideally I'd like + * to make it homeless but it doesn't appear to let me + * bind a TC to a non-existent VPE. Which is perfectly + * reasonable. + * + * The (un)bound state is visible to an EJTAG probe so + * may notify GDB... + */ + tmp = read_tc_c0_tcbind(); + if (tmp & TCBIND_CURVPE) { + /* tc is bound >vpe0 */ + write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE); + + t->pvpe = get_vpe(0); /* set the parent vpe */ + } + + /* halt the TC */ + write_tc_c0_tchalt(TCHALT_H); + mips_ihb(); + + tmp = read_tc_c0_tcstatus(); + + /* mark not activated and not dynamically allocatable */ + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ + write_tc_c0_tcstatus(tmp); + } + } + +out_reenable: + /* release config state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); + + return 0; + +out_class: + class_unregister(&vpe_class); +out_chrdev: + unregister_chrdev(major, VPE_MODULE_NAME); + +out: + return err; +} + +void __exit vpe_module_exit(void) +{ + struct vpe *v, *n; + + device_del(&vpe_device); + unregister_chrdev(major, VPE_MODULE_NAME); + + /* No locking needed here */ + list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) { + if (v->state != VPE_STATE_UNUSED) + release_vpe(v); + } +} diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index a558bbe..e84bc7b 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -51,8 +51,6 @@ #include #include -typedef void *vpe_handle; - #ifndef ARCH_SHF_SMALL #define ARCH_SHF_SMALL 0 #endif @@ -60,97 +58,15 @@ typedef void *vpe_handle; /* If this is set, the section belongs in the init part of the module */ #define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) -/* - * The number of TCs and VPEs physically available on the core - */ -static int cpu_idx; -static int hw_tcs, hw_vpes; -static char module_name[] = "vpe"; -static int major; -static const int minor = 1; /* fixed for now */ - -/* grab the likely amount of memory we will need. */ -#ifdef CONFIG_MIPS_VPE_LOADER_TOM -#define P_SIZE (2 * 1024 * 1024) -#else -/* add an overhead to the max kmalloc size for non-striped symbols/etc */ -#define P_SIZE (256 * 1024) -#endif - -extern unsigned long physical_memsize; - -#define MAX_VPES 16 -#define VPE_PATH_MAX 256 - -enum vpe_state { - VPE_STATE_UNUSED = 0, - VPE_STATE_INUSE, - VPE_STATE_RUNNING -}; - -enum tc_state { - TC_STATE_UNUSED = 0, - TC_STATE_INUSE, - TC_STATE_RUNNING, - TC_STATE_DYNAMIC -}; - -struct vpe { - enum vpe_state state; - - /* (device) minor associated with this vpe */ - int minor; - - /* elfloader stuff */ - void *load_addr; - unsigned long len; - char *pbuffer; - unsigned long plen; - unsigned int uid, gid; - char cwd[VPE_PATH_MAX]; - - unsigned long __start; - - /* tc's associated with this vpe */ - struct list_head tc; - - /* The list of vpe's */ - struct list_head list; - - /* shared symbol address */ - void *shared_ptr; - - /* the list of who wants to know when something major happens */ - struct list_head notify; - - unsigned int ntcs; -}; - -struct tc { - enum tc_state state; - int index; - - struct vpe *pvpe; /* parent VPE */ - struct list_head tc; /* The list of TC's with this VPE */ - struct list_head list; /* The global list of tc's */ -}; - -struct { - spinlock_t vpe_list_lock; - struct list_head vpe_list; /* Virtual processing elements */ - spinlock_t tc_list_lock; - struct list_head tc_list; /* Thread contexts */ -} vpecontrol = { +struct vpe_control vpecontrol = { .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) }; -static void release_progmem(void *ptr); - /* get the vpe associated with this minor */ -static struct vpe *get_vpe(int minor) +struct vpe *get_vpe(int minor) { struct vpe *res, *v; @@ -160,7 +76,7 @@ static struct vpe *get_vpe(int minor) res = NULL; spin_lock(&vpecontrol.vpe_list_lock); list_for_each_entry(v, &vpecontrol.vpe_list, list) { - if (v->minor == minor) { + if (v->minor == VPE_MODULE_MINOR) { res = v; break; } @@ -171,7 +87,7 @@ static struct vpe *get_vpe(int minor) } /* get the vpe associated with this minor */ -static struct tc *get_tc(int index) +struct tc *get_tc(int index) { struct tc *res, *t; @@ -189,7 +105,7 @@ static struct tc *get_tc(int index) } /* allocate a vpe and associate it with this minor (or index) */ -static struct vpe *alloc_vpe(int minor) +struct vpe *alloc_vpe(int minor) { struct vpe *v; @@ -202,13 +118,13 @@ static struct vpe *alloc_vpe(int minor) spin_unlock(&vpecontrol.vpe_list_lock); INIT_LIST_HEAD(&v->notify); - v->minor = minor; + v->minor = VPE_MODULE_MINOR; return v; } /* allocate a tc. At startup only tc0 is running, all other can be halted. */ -static struct tc *alloc_tc(int index) +struct tc *alloc_tc(int index) { struct tc *tc; @@ -227,7 +143,7 @@ out: } /* clean up and free everything */ -static void release_vpe(struct vpe *v) +void release_vpe(struct vpe *v) { list_del(&v->list); if (v->load_addr) @@ -235,28 +151,8 @@ static void release_vpe(struct vpe *v) kfree(v); } -static void __maybe_unused dump_mtregs(void) -{ - unsigned long val; - - val = read_c0_config3(); - printk("config3 0x%lx MT %ld\n", val, - (val & CONFIG3_MT) >> CONFIG3_MT_SHIFT); - - val = read_c0_mvpcontrol(); - printk("MVPControl 0x%lx, STLB %ld VPC %ld EVP %ld\n", val, - (val & MVPCONTROL_STLB) >> MVPCONTROL_STLB_SHIFT, - (val & MVPCONTROL_VPC) >> MVPCONTROL_VPC_SHIFT, - (val & MVPCONTROL_EVP)); - - val = read_c0_mvpconf0(); - printk("mvpconf0 0x%lx, PVPE %ld PTC %ld M %ld\n", val, - (val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT, - val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); -} - /* Find some VPE program space */ -static void *alloc_progmem(unsigned long len) +void *alloc_progmem(unsigned long len) { void *addr; @@ -275,7 +171,7 @@ static void *alloc_progmem(unsigned long len) return addr; } -static void release_progmem(void *ptr) +void release_progmem(void *ptr) { #ifndef CONFIG_MIPS_VPE_LOADER_TOM kfree(ptr); @@ -317,7 +213,6 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr, for (i = 0; i < hdr->e_shnum; ++i) { Elf_Shdr *s = &sechdrs[i]; - // || strncmp(secstrings + s->sh_name, ".init", 5) == 0) if ((s->sh_flags & masks[m][0]) != masks[m][0] || (s->sh_flags & masks[m][1]) || s->sh_entsize != ~0UL) @@ -332,7 +227,6 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr, } } - /* from module-elf32.c, but subverted a little */ struct mips_hi16 { @@ -407,7 +301,7 @@ static int apply_r_mips_26(struct module *me, uint32_t *location, Elf32_Addr v) { if (v % 4) { - pr_debug("VPE loader: apply_r_mips_26 unaligned relocation\n"); + pr_debug("VPE loader: apply_r_mips_26: unaligned relocation\n"); return -ENOEXEC; } @@ -469,8 +363,8 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, /* * The value for the HI16 had best be the same. */ - if (v != l->value) { - pr_debug("VPE loader: apply_r_mips_lo16/hi16: \tinconsistent value information\n"); + if (v != l->value) { + pr_debug("VPE loader: apply_r_mips_lo16/hi16: inconsistent value information\n"); goto out_free; } @@ -567,7 +461,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs, if (!sym->st_value) { pr_debug("%s: undefined weak symbol %s\n", - me->name, strtab + sym->st_name); + me->name, strtab + sym->st_name); /* just print the warning, dont barf */ } @@ -593,8 +487,6 @@ static inline void save_gp_address(unsigned int secbase, unsigned int rel) } /* end module-elf32.c */ - - /* Change all symbols so that sh_value encodes the pointer directly. */ static void simplify_symbols(Elf_Shdr * sechdrs, unsigned int symindex, @@ -670,136 +562,6 @@ static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex, } #endif -#ifdef CONFIG_MIPS_CMP -#error CMP vpe_run() not implemented! -#else -/* We are prepared so configure and start the VPE... */ -static int vpe_run(struct vpe * v) -{ - unsigned long flags, val, dmt_flag; - struct vpe_notifications *n; - unsigned int vpeflags; - struct tc *t; - - /* check we are the Master VPE */ - local_irq_save(flags); - val = read_c0_vpeconf0(); - if (!(val & VPECONF0_MVP)) { - pr_warn("VPE loader: only Master VPE's are allowed to configure MT\n"); - local_irq_restore(flags); - - return -1; - } - - dmt_flag = dmt(); - vpeflags = dvpe(); - - if (!list_empty(&v->tc)) { - if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { - evpe(vpeflags); - emt(dmt_flag); - local_irq_restore(flags); - - pr_warn("VPE loader: TC %d is already in use.\n", - t->index); - return -ENOEXEC; - } - } else { - evpe(vpeflags); - emt(dmt_flag); - local_irq_restore(flags); - - pr_warn("VPE loader: No TC's associated with VPE %d\n", - v->minor); - - return -ENOEXEC; - } - - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - settc(t->index); - - /* should check it is halted, and not activated */ - if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) { - evpe(vpeflags); - emt(dmt_flag); - local_irq_restore(flags); - - pr_warn("VPE loader: TC %d is already active!\n", t->index); - - return -ENOEXEC; - } - - /* Write the address we want it to start running from in the TCPC register. */ - write_tc_c0_tcrestart((unsigned long)v->__start); - write_tc_c0_tccontext((unsigned long)0); - - /* - * Mark the TC as activated, not interrupt exempt and not dynamically - * allocatable - */ - val = read_tc_c0_tcstatus(); - val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A; - write_tc_c0_tcstatus(val); - - write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); - - /* - * The sde-kit passes 'memsize' to __start in $a3, so set something - * here... Or set $a3 to zero and define DFLT_STACK_SIZE and - * DFLT_HEAP_SIZE when you compile your program - */ - mttgpr(6, v->ntcs); - mttgpr(7, physical_memsize); - - /* set up VPE1 */ - /* - * bind the TC to VPE 1 as late as possible so we only have the final - * VPE registers to set up, and so an EJTAG probe can trigger on it - */ - write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1); - - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); - - back_to_back_c0_hazard(); - - /* Set up the XTC bit in vpeconf0 to point at our tc */ - write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC)) - | (t->index << VPECONF0_XTC_SHIFT)); - - back_to_back_c0_hazard(); - - /* enable this VPE */ - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); - - /* clear out any left overs from a previous program */ - write_vpe_c0_status(0); - write_vpe_c0_cause(0); - - /* take system out of configuration state */ - clear_c0_mvpcontrol(MVPCONTROL_VPC); - - /* - * SMTC/SMVP kernels manage VPE enable independently, - * but uniprocessor kernels need to turn it on, even - * if that wasn't the pre-dvpe() state. - */ -#ifdef CONFIG_SMP - evpe(vpeflags); -#else - evpe(EVPE_ENABLE); -#endif - emt(dmt_flag); - local_irq_restore(flags); - - list_for_each_entry(n, &v->notify, list) - n->start(minor); - - return 0; -} -#endif /* CONFIG_MIPS_CMP */ - static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, unsigned int symindex, const char *strtab, struct module *mod) @@ -835,7 +597,7 @@ static int vpe_elfload(struct vpe * v) long err = 0; char *secstrings, *strtab = NULL; unsigned int len, i, symindex = 0, strindex = 0, relocate = 0; - struct module mod; // so we can re-use the relocations code + struct module mod; /* so we can re-use the relocations code */ memset(&mod, 0, sizeof(struct module)); strcpy(mod.name, "VPE loader"); @@ -920,35 +682,36 @@ static int vpe_elfload(struct vpe * v) sechdrs[i].sh_addr); } - /* Fix up syms, so that st_value is a pointer to location. */ - simplify_symbols(sechdrs, symindex, strtab, secstrings, - hdr->e_shnum, &mod); + /* Fix up syms, so that st_value is a pointer to location. */ + simplify_symbols(sechdrs, symindex, strtab, secstrings, + hdr->e_shnum, &mod); - /* Now do relocations. */ - for (i = 1; i < hdr->e_shnum; i++) { - const char *strtab = (char *)sechdrs[strindex].sh_addr; - unsigned int info = sechdrs[i].sh_info; + /* Now do relocations. */ + for (i = 1; i < hdr->e_shnum; i++) { + const char *strtab = (char *)sechdrs[strindex].sh_addr; + unsigned int info = sechdrs[i].sh_info; - /* Not a valid relocation section? */ - if (info >= hdr->e_shnum) - continue; + /* Not a valid relocation section? */ + if (info >= hdr->e_shnum) + continue; - /* Don't bother with non-allocated sections */ - if (!(sechdrs[info].sh_flags & SHF_ALLOC)) - continue; + /* Don't bother with non-allocated sections */ + if (!(sechdrs[info].sh_flags & SHF_ALLOC)) + continue; - if (sechdrs[i].sh_type == SHT_REL) - err = apply_relocations(sechdrs, strtab, symindex, i, - &mod); - else if (sechdrs[i].sh_type == SHT_RELA) - err = apply_relocate_add(sechdrs, strtab, symindex, i, - &mod); - if (err < 0) - return err; + if (sechdrs[i].sh_type == SHT_REL) + err = apply_relocations(sechdrs, strtab, + symindex, i, &mod); + else if (sechdrs[i].sh_type == SHT_RELA) + err = apply_relocate_add(sechdrs, strtab, + symindex, i, &mod); + if (err < 0) + return err; - } - } else { - struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); + } + } else { + struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + + hdr->e_phoff); for (i = 0; i < hdr->e_phnum; i++) { if (phdr->p_type == PT_LOAD) { @@ -962,16 +725,20 @@ static int vpe_elfload(struct vpe * v) } for (i = 0; i < hdr->e_shnum; i++) { - /* Internal symbols and strings. */ - if (sechdrs[i].sh_type == SHT_SYMTAB) { - symindex = i; - strindex = sechdrs[i].sh_link; - strtab = (char *)hdr + sechdrs[strindex].sh_offset; - - /* mark the symtab's address for when we try to find the - magic symbols */ - sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; - } + /* Internal symbols and strings. */ + if (sechdrs[i].sh_type == SHT_SYMTAB) { + symindex = i; + strindex = sechdrs[i].sh_link; + strtab = (char *)hdr + + sechdrs[strindex].sh_offset; + + /* + * mark the symtab's address for when we try to + * find the magic symbols + */ + sechdrs[i].sh_addr = (size_t) hdr + + sechdrs[i].sh_offset; + } } } @@ -994,45 +761,6 @@ static int vpe_elfload(struct vpe * v) return 0; } -#ifdef CONFIG_MIPS_CMP -static void cleanup_tc(struct tc *tc) -{ - -} -#else -static void cleanup_tc(struct tc *tc) -{ - unsigned long flags; - unsigned int mtflags, vpflags; - int tmp; - - local_irq_save(flags); - mtflags = dmt(); - vpflags = dvpe(); - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - settc(tc->index); - tmp = read_tc_c0_tcstatus(); - - /* mark not allocated and not dynamically allocatable */ - tmp &= ~(TCSTATUS_A | TCSTATUS_DA); - tmp |= TCSTATUS_IXMT; /* interrupt exempt */ - write_tc_c0_tcstatus(tmp); - - write_tc_c0_tchalt(TCHALT_H); - mips_ihb(); - - /* bind it to anything other than VPE1 */ -// write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE - - clear_c0_mvpcontrol(MVPCONTROL_VPC); - evpe(vpflags); - emt(mtflags); - local_irq_restore(flags); -} -#endif - static int getcwd(char *buff, int size) { mm_segment_t old_fs; @@ -1056,14 +784,14 @@ static int vpe_open(struct inode *inode, struct file *filp) struct vpe *v; int ret; - if (minor != iminor(inode)) { + if (VPE_MODULE_MINOR != iminor(inode)) { /* assume only 1 device at the moment. */ pr_warning("VPE loader: only vpe1 is supported\n"); return -ENODEV; } - v = get_vpe(cpu_idx); + v = get_vpe(aprp_cpu_index()); if (v == NULL) { pr_warning("VPE loader: unable to get vpe\n"); @@ -1075,11 +803,11 @@ static int vpe_open(struct inode *inode, struct file *filp) pr_debug("VPE loader: tc in use dumping regs\n"); list_for_each_entry(not, &v->notify, list) { - not->stop(cpu_idx); + not->stop(aprp_cpu_index()); } release_progmem(v->load_addr); - cleanup_tc(get_tc(cpu_idx)); + cleanup_tc(get_tc(aprp_cpu_index())); } /* this of-course trashes what was there before... */ @@ -1112,7 +840,7 @@ static int vpe_release(struct inode *inode, struct file *filp) Elf_Ehdr *hdr; int ret = 0; - v = get_vpe(cpu_idx); + v = get_vpe(aprp_cpu_index()); if (v == NULL) return -ENODEV; @@ -1150,17 +878,16 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, size_t ret = count; struct vpe *v; - if (iminor(file->f_path.dentry->d_inode) != minor) + if (iminor(file->f_path.dentry->d_inode) != VPE_MODULE_MINOR) return -ENODEV; - v = get_vpe(cpu_idx); + v = get_vpe(aprp_cpu_index()); if (v == NULL) return -ENODEV; if ((count + v->len) > v->plen) { - printk(KERN_WARNING - "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + pr_warn("VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); return -ENOMEM; } @@ -1172,7 +899,7 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, return ret; } -static const struct file_operations vpe_fops = { +const struct file_operations vpe_fops = { .owner = THIS_MODULE, .open = vpe_open, .release = vpe_release, @@ -1180,96 +907,6 @@ static const struct file_operations vpe_fops = { .llseek = noop_llseek, }; -#ifndef CONFIG_MIPS_CMP -/* module wrapper entry points */ -/* give me a vpe */ -vpe_handle vpe_alloc(void) -{ - int i; - struct vpe *v; - - /* find a vpe */ - for (i = 1; i < MAX_VPES; i++) { - if ((v = get_vpe(i)) != NULL) { - v->state = VPE_STATE_INUSE; - return v; - } - } - return NULL; -} - -EXPORT_SYMBOL(vpe_alloc); - -/* start running from here */ -int vpe_start(vpe_handle vpe, unsigned long start) -{ - struct vpe *v = vpe; - - v->__start = start; - return vpe_run(v); -} - -EXPORT_SYMBOL(vpe_start); - -/* halt it for now */ -int vpe_stop(vpe_handle vpe) -{ - struct vpe *v = vpe; - struct tc *t; - unsigned int evpe_flags; - - evpe_flags = dvpe(); - - if ((t = list_entry(v->tc.next, struct tc, tc)) != NULL) { - - settc(t->index); - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); - } - - evpe(evpe_flags); - - return 0; -} - -EXPORT_SYMBOL(vpe_stop); - -/* I've done with it thank you */ -int vpe_free(vpe_handle vpe) -{ - struct vpe *v = vpe; - struct tc *t; - unsigned int evpe_flags; - - if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { - return -ENOEXEC; - } - - evpe_flags = dvpe(); - - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - settc(t->index); - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); - - /* halt the TC */ - write_tc_c0_tchalt(TCHALT_H); - mips_ihb(); - - /* mark the TC unallocated */ - write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A); - - v->state = VPE_STATE_UNUSED; - - clear_c0_mvpcontrol(MVPCONTROL_VPC); - evpe(evpe_flags); - - return 0; -} - -EXPORT_SYMBOL(vpe_free); -#endif /* CONFIG_MIPS_CMP */ - void *vpe_get_shared(int index) { struct vpe *v; @@ -1331,390 +968,6 @@ char *vpe_getcwd(int index) EXPORT_SYMBOL(vpe_getcwd); -#ifdef CONFIG_MIPS_CMP -static ssize_t store_kill(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(cpu_idx); - struct vpe_notifications *not; - - list_for_each_entry(not, &vpe->notify, list) { - not->stop(cpu_idx); - } - - release_progmem(vpe->load_addr); - vpe->state = VPE_STATE_UNUSED; - - return len; -} - -static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, - char *buf) -{ - struct vpe *vpe = get_vpe(cpu_idx); - - return sprintf(buf, "%d\n", vpe->ntcs); -} - -static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(cpu_idx); - unsigned long new; - int ret; - - ret = kstrtoul(buf, 0, &new); - if (ret < 0) - return ret; - - if (new != 1) - return -EINVAL; - - vpe->ntcs = new; - - return len; -} -#else -static ssize_t store_kill(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(cpu_idx); - struct vpe_notifications *not; - - list_for_each_entry(not, &vpe->notify, list) { - not->stop(cpu_idx); - } - - release_progmem(vpe->load_addr); - cleanup_tc(get_tc(cpu_idx)); - vpe_stop(vpe); - vpe_free(vpe); - - return len; -} - -static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr, - char *buf) -{ - struct vpe *vpe = get_vpe(cpu_idx); - - return sprintf(buf, "%d\n", vpe->ntcs); -} - -static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(cpu_idx); - unsigned long new; - int ret; - - ret = kstrtoul(buf, 0, &new); - if (ret < 0) - return ret; - - if (new == 0 || new > (hw_tcs - cpu_idx)) - return -EINVAL; - - vpe->ntcs = new; - - return len; -} -#endif /* CONFIG_MIPS_CMP */ - -static struct device_attribute vpe_class_attributes[] = { - __ATTR(kill, S_IWUSR, NULL, store_kill), - __ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs), - {} -}; - -static void vpe_device_release(struct device *cd) -{ - kfree(cd); -} - -struct class vpe_class = { - .name = "vpe", - .owner = THIS_MODULE, - .dev_release = vpe_device_release, - .dev_attrs = vpe_class_attributes, -}; - -struct device vpe_device; - -#ifdef CONFIG_MIPS_CMP -static int __init vpe_module_init(void) -{ - struct vpe *v = NULL; - struct tc *t; - int err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - cpu_idx = setup_max_cpus; - - if (num_possible_cpus() - cpu_idx < 1) { - pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" - "Pass maxcpus= argument as kernel argument\n"); - return -ENODEV; - } - - major = register_chrdev(0, module_name, &vpe_fops); - if (major < 0) { - pr_warn("VPE loader: unable to register character device\n"); - return major; - } - - err = class_register(&vpe_class); - if (err) { - pr_err("vpe_class registration failed\n"); - goto out_chrdev; - } - - device_initialize(&vpe_device); - vpe_device.class = &vpe_class, - vpe_device.parent = NULL, - dev_set_name(&vpe_device, "vpe_sp"); - vpe_device.devt = MKDEV(major, minor); - err = device_add(&vpe_device); - if (err) { - pr_err("Adding vpe_device failed\n"); - goto out_class; - } - - t = alloc_tc(cpu_idx); - if (!t) { - pr_warn("VPE: unable to allocate TC\n"); - err = -ENOMEM; - goto out; - } - - /* VPE */ - v = alloc_vpe(cpu_idx); - if (v == NULL) { - pr_warn("VPE: unable to allocate VPE\n"); - kfree(t); - err = -ENOMEM; - goto out; - } - - v->ntcs = 1; - - /* add the tc to the list of this vpe's tc's. */ - list_add(&t->tc, &v->tc); - - /* TC */ - t->pvpe = v; /* set the parent vpe */ - - return 0; - -out_class: - class_unregister(&vpe_class); -out_chrdev: - unregister_chrdev(major, module_name); - -out: - return err; -} -#else -static int __init vpe_module_init(void) -{ - unsigned int mtflags, vpflags; - unsigned long flags, val; - struct vpe *v = NULL; - struct tc *t; - int tc, err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - if (vpelimit == 0) { - pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" - "Pass maxvpes= argument as kernel argument\n"); - - return -ENODEV; - } - - cpu_idx = tclimit; - - if (cpu_idx == 0) { - pr_warn("No TCs reserved for AP/SP, not initialize VPE loader\n" - "Pass maxtcs= argument as kernel argument\n"); - - return -ENODEV; - } - - major = register_chrdev(0, module_name, &vpe_fops); - if (major < 0) { - pr_warn("VPE loader: unable to register character device\n"); - return major; - } - - err = class_register(&vpe_class); - if (err) { - pr_err("vpe_class registration failed\n"); - goto out_chrdev; - } - - device_initialize(&vpe_device); - vpe_device.class = &vpe_class, - vpe_device.parent = NULL, - dev_set_name(&vpe_device, "vpe1"); - vpe_device.devt = MKDEV(major, minor); - err = device_add(&vpe_device); - if (err) { - pr_err("Adding vpe_device failed\n"); - goto out_class; - } - - local_irq_save(flags); - mtflags = dmt(); - vpflags = dvpe(); - - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - /* dump_mtregs(); */ - - val = read_c0_mvpconf0(); - hw_tcs = (val & MVPCONF0_PTC) + 1; - hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; - - for (tc = cpu_idx; tc < hw_tcs; tc++) { - /* - * Must re-enable multithreading temporarily or in case we - * reschedule send IPIs or similar we might hang. - */ - clear_c0_mvpcontrol(MVPCONTROL_VPC); - evpe(vpflags); - emt(mtflags); - local_irq_restore(flags); - t = alloc_tc(tc); - if (!t) { - err = -ENOMEM; - goto out; - } - - local_irq_save(flags); - mtflags = dmt(); - vpflags = dvpe(); - set_c0_mvpcontrol(MVPCONTROL_VPC); - - /* VPE's */ - if (tc < hw_tcs) { - settc(tc); - - v = alloc_vpe(tc); - if (v == NULL) { - pr_warn("VPE: unable to allocate VPE\n"); - - goto out_reenable; - } - - v->ntcs = hw_tcs - cpu_idx; - - /* add the tc to the list of this vpe's tc's. */ - list_add(&t->tc, &v->tc); - - /* deactivate all but vpe0 */ - if (tc >= cpu_idx) { - unsigned long tmp = read_vpe_c0_vpeconf0(); - - tmp &= ~VPECONF0_VPA; - - /* master VPE */ - tmp |= VPECONF0_MVP; - write_vpe_c0_vpeconf0(tmp); - } - - /* disable multi-threading with TC's */ - write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); - - if (tc >= vpelimit) { - /* - * Set config to be the same as vpe0, - * particularly kseg0 coherency alg - */ - write_vpe_c0_config(read_c0_config()); - } - } - - /* TC's */ - t->pvpe = v; /* set the parent vpe */ - - if (tc >= cpu_idx) { - unsigned long tmp; - - settc(tc); - - /* Any TC that is bound to VPE0 gets left as is - in case - we are running SMTC on VPE0. A TC that is bound to any - other VPE gets bound to VPE0, ideally I'd like to make - it homeless but it doesn't appear to let me bind a TC - to a non-existent VPE. Which is perfectly reasonable. - - The (un)bound state is visible to an EJTAG probe so may - notify GDB... - */ - - if (((tmp = read_tc_c0_tcbind()) & TCBIND_CURVPE)) { - /* tc is bound >vpe0 */ - write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE); - - t->pvpe = get_vpe(0); /* set the parent vpe */ - } - - /* halt the TC */ - write_tc_c0_tchalt(TCHALT_H); - mips_ihb(); - - tmp = read_tc_c0_tcstatus(); - - /* mark not activated and not dynamically allocatable */ - tmp &= ~(TCSTATUS_A | TCSTATUS_DA); - tmp |= TCSTATUS_IXMT; /* interrupt exempt */ - write_tc_c0_tcstatus(tmp); - } - } - -out_reenable: - /* release config state */ - clear_c0_mvpcontrol(MVPCONTROL_VPC); - - evpe(vpflags); - emt(mtflags); - local_irq_restore(flags); - - return 0; - -out_class: - class_unregister(&vpe_class); -out_chrdev: - unregister_chrdev(major, module_name); - -out: - return err; -} -#endif /* CONFIG_MIPS_CMP */ - -static void __exit vpe_module_exit(void) -{ - struct vpe *v, *n; - - device_del(&vpe_device); - unregister_chrdev(major, module_name); - - /* No locking needed here */ - list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) { - if (v->state != VPE_STATE_UNUSED) - release_vpe(v); - } -} - module_init(vpe_module_init); module_exit(vpe_module_exit); MODULE_DESCRIPTION("MIPS VPE Loader"); -- 1.7.1 From dczhu@mips.com Wed Dec 5 00:55:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 00:56:21 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:33043 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831648Ab2LDXzZqlx6m (ORCPT ); Wed, 5 Dec 2012 00:55:25 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qB4Nt48l014718; Tue, 4 Dec 2012 15:55:08 -0800 X-WSS-ID: 0MEJ6FQ-01-0P2-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2DA1C364674; Tue, 4 Dec 2012 15:55:01 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Tue, 4 Dec 2012 15:54:56 -0800 From: Deng-Cheng Zhu To: , , , , CC: Subject: [PATCH v3 3/5] MIPS: APRP (APSP): remove kspd.h Date: Tue, 4 Dec 2012 15:54:30 -0800 Message-ID: <1354665272-22759-4-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1354665272-22759-1-git-send-email-dczhu@mips.com> References: <1354665272-22759-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: pA5cYOaASkPqSV6+7AJCNQ== X-archive-position: 35181 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1455 Lines: 49 Now that KSPD is gone, kspd.h has no reason to be there. Signed-off-by: Deng-Cheng Zhu --- arch/mips/include/asm/kspd.h | 32 -------------------------------- 1 files changed, 0 insertions(+), 32 deletions(-) delete mode 100644 arch/mips/include/asm/kspd.h diff --git a/arch/mips/include/asm/kspd.h b/arch/mips/include/asm/kspd.h deleted file mode 100644 index ec68329..0000000 --- a/arch/mips/include/asm/kspd.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ - -#ifndef _ASM_KSPD_H -#define _ASM_KSPD_H - -struct kspd_notifications { - void (*kspd_sp_exit)(int sp_id); - - struct list_head list; -}; - -static inline void kspd_notify(struct kspd_notifications *notify) -{ -} - -#endif -- 1.7.1 From dczhu@mips.com Wed Dec 5 00:55:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 00:56:43 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:33044 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831651Ab2LDXz0lK6zi (ORCPT ); Wed, 5 Dec 2012 00:55:26 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qB4Nt48n014718; Tue, 4 Dec 2012 15:55:12 -0800 X-WSS-ID: 0MEJ6G0-01-0P4-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2D8AE36465A; Tue, 4 Dec 2012 15:55:11 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Tue, 4 Dec 2012 15:55:06 -0800 From: Deng-Cheng Zhu To: , , , , CC: Subject: [PATCH v3 5/5] MIPS: APRP (APSP): malta board support Date: Tue, 4 Dec 2012 15:54:32 -0800 Message-ID: <1354665272-22759-6-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1354665272-22759-1-git-send-email-dczhu@mips.com> References: <1354665272-22759-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: 6KZQfn1T7ANVgeS3a833lA== X-archive-position: 35182 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3209 Lines: 116 APRP is supposed to be platform independent, however, this patch is needed for Malta for various reasons, see code and code comments. Signed-off-by: Deng-Cheng Zhu --- .../include/asm/mach-malta/cpu-feature-overrides.h | 3 ++ arch/mips/kernel/vpe-cmp.c | 17 +++++++++++++++ arch/mips/mti-malta/malta-int.c | 22 +++++++++++++++++++- 3 files changed, 41 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h index 37e3583..0bf3872 100644 --- a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h @@ -17,6 +17,9 @@ #define cpu_has_tlb 1 #define cpu_has_4kex 1 #define cpu_has_4k_cache 1 +#ifdef CONFIG_MIPS_SP_FP_INTENSIVE +#define cpu_has_fpu 0 +#endif /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 diff --git a/arch/mips/kernel/vpe-cmp.c b/arch/mips/kernel/vpe-cmp.c index 9d0c375..20f4497 100644 --- a/arch/mips/kernel/vpe-cmp.c +++ b/arch/mips/kernel/vpe-cmp.c @@ -25,7 +25,24 @@ static int major; +#ifdef CONFIG_MIPS_MALTA +#include + +int vpe_run(struct vpe *v) +{ + struct vpe_notifications *n; + + if (amon_cpu_start(aprp_cpu_index(), v->__start, 0, 0, 0) < 0) + return -1; + + list_for_each_entry(n, &v->notify, list) + n->start(VPE_MODULE_MINOR); + + return 0; +} +#else #error CMP vpe_run() not implemented! +#endif void cleanup_tc(struct tc *tc) { diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 647b863..cddda99 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -1,6 +1,6 @@ /* * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2000, 2001, 2004, 2012 MIPS Technologies, Inc. * Copyright (C) 2001 Ralf Baechle * * This program is free software; you can distribute it and/or modify it @@ -45,6 +45,9 @@ #include #include #include +#ifdef CONFIG_MIPS_VPE_APSP_API +#include +#endif int gcmp_present = -1; int gic_present; @@ -128,6 +131,15 @@ static void malta_hw0_irqdispatch(void) } do_IRQ(MALTA_INT_BASE + irq); + +#if defined(CONFIG_MIPS_VPE_APSP_API) && !defined(CONFIG_MIPS_CMP) + /* + * When sw0 gets set, a spurious hw interrupt is signaled as well. + * The sw0 will not be handled until the hw interrupt is cleared. + * We use the hook to handle sw0 and the hw interrupt gets cleared. + */ + aprp_hook(); +#endif } static void malta_ipi_irqdispatch(void) @@ -312,6 +324,10 @@ static void ipi_call_dispatch(void) static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) { +#if defined(CONFIG_MIPS_VPE_APSP_API) && defined(CONFIG_MIPS_CMP) + aprp_hook(); +#endif + scheduler_ipi(); return IRQ_HANDLED; @@ -622,6 +638,10 @@ void __init arch_init_irq(void) arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); #endif } + +#ifdef CONFIG_MIPS_VPE_APSP_API + aprp_hook = null_aprp_hook; +#endif } void malta_be_init(void) -- 1.7.1 From dczhu@mips.com Wed Dec 5 00:55:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 00:57:02 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:33046 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831649Ab2LDXzaQuwwy (ORCPT ); Wed, 5 Dec 2012 00:55:30 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qB4Nt9j4014727; Tue, 4 Dec 2012 15:55:13 -0800 X-WSS-ID: 0MEJ6FV-01-0P3-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2D3AE364679; Tue, 4 Dec 2012 15:55:06 -0800 (PST) Received: from fun-lab.mips.com (192.168.52.61) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Tue, 4 Dec 2012 15:55:01 -0800 From: Deng-Cheng Zhu To: , , , , CC: Subject: [PATCH v3 4/5] MIPS: let amon_cpu_start() report results Date: Tue, 4 Dec 2012 15:54:31 -0800 Message-ID: <1354665272-22759-5-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1354665272-22759-1-git-send-email-dczhu@mips.com> References: <1354665272-22759-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: 9bFc4MSoXsHwgecOv69Vwg== X-archive-position: 35183 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1487 Lines: 55 Change the return type of amon_cpu_start() from void to int. Signed-off-by: Deng-Cheng Zhu --- arch/mips/include/asm/amon.h | 2 +- arch/mips/mti-malta/malta-amon.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/amon.h b/arch/mips/include/asm/amon.h index c3dc1a6..c8af6b0 100644 --- a/arch/mips/include/asm/amon.h +++ b/arch/mips/include/asm/amon.h @@ -3,5 +3,5 @@ */ int amon_cpu_avail(int); -void amon_cpu_start(int, unsigned long, unsigned long, +int amon_cpu_start(int, unsigned long, unsigned long, unsigned long, unsigned long); diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index 469d9b0..fcd69cb 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c @@ -48,7 +48,7 @@ int amon_cpu_avail(int cpu) return 1; } -void amon_cpu_start(int cpu, +int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp, unsigned long gp, unsigned long a0) { @@ -56,10 +56,10 @@ void amon_cpu_start(int cpu, (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); if (!amon_cpu_avail(cpu)) - return; + return -1; if (cpu == smp_processor_id()) { pr_debug("launch: I am cpu%d!\n", cpu); - return; + return -1; } launch += cpu; @@ -78,4 +78,6 @@ void amon_cpu_start(int cpu, ; smp_rmb(); /* Target will be updating flags soon */ pr_debug("launch: cpu%d gone!\n", cpu); + + return 0; } -- 1.7.1 From hauke@hauke-m.de Wed Dec 5 18:46:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:46:51 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37744 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831673Ab2LERqtsJo56 (ORCPT ); Wed, 5 Dec 2012 18:46:49 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 45CB18F6C; Wed, 5 Dec 2012 18:46:48 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VqkC42Nwgzho; Wed, 5 Dec 2012 18:46:23 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id F2A468F61; Wed, 5 Dec 2012 18:46:21 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 01/11] ssb/bcma: add common header for watchdog Date: Wed, 5 Dec 2012 18:45:58 +0100 Message-Id: <1354729568-19993-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35184 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1020 Lines: 39 This adds a common header for watchdog functions, so a watchdog driver just needs to use this and could provide watchdog functionality for ssb and bcma based SoCs. Patches for a watchdog driver using this interface will be send later. Signed-off-by: Hauke Mehrtens --- include/linux/bcm47xx_wdt.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/linux/bcm47xx_wdt.h diff --git a/include/linux/bcm47xx_wdt.h b/include/linux/bcm47xx_wdt.h new file mode 100644 index 0000000..e5dfc25 --- /dev/null +++ b/include/linux/bcm47xx_wdt.h @@ -0,0 +1,19 @@ +#ifndef LINUX_BCM47XX_WDT_H_ +#define LINUX_BCM47XX_WDT_H_ + +#include + + +struct bcm47xx_wdt { + u32 (*timer_set)(struct bcm47xx_wdt *, u32); + u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32); + u32 max_timer_ms; + + void *driver_data; +}; + +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt) +{ + return wdt->driver_data; +} +#endif /* LINUX_BCM47XX_WDT_H_ */ -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:46:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:47:08 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37753 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831678Ab2LERqv0VggE (ORCPT ); Wed, 5 Dec 2012 18:46:51 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 32EBF8F61; Wed, 5 Dec 2012 18:46:50 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ou0WH85ehPuM; Wed, 5 Dec 2012 18:46:22 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 4DDFE8F60; Wed, 5 Dec 2012 18:46:15 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 00/11] watchdog/bcm47xx/bcma/ssb: add support for SoCs with PMU Date: Wed, 5 Dec 2012 18:45:57 +0100 Message-Id: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35185 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2498 Lines: 58 This patch series improves the functions for setting the watchdog driver in ssb amd bcma. It also makes ssb and bcma register a platform device which could be used by a watchdog driver to better set the times where the system should restart. The patches for the watchdog driver will be send later and were removed in v3. This code is currently based on the wireless-testing/master tree by John Linville. v3: * Remove changes done to the watchdog driver so John could pull this into wireless-testing, this sill works with the old watchdog driver. The patches changing the watchdog driver will be send later. This was done to get this into 3.8 because Wim Van Sebroeck is neither giving an Ack or a Nack on these patches and we want to do more changes to bcma/ssb on top of these. v2: * reword some commit messages * rebase on current wireless-testing/master with "ssb: extif: fix compile errors" applied on top of it. * do not change value of WDT_SOFTTIMER_MAX * moved some small changes in the bcm47xx_wdt.c patches Hauke Mehrtens (11): ssb/bcma: add common header for watchdog bcma: add bcma_chipco_alp_clock bcma: set the pmu watchdog if available bcma: add methods for watchdog driver bcma: register watchdog driver ssb: get alp clock from devices with PMU ssb: set the PMU watchdog if available ssb: add methods for watchdog driver ssb: extif: add check for max value before setting watchdog register ssb: extif: add methods for watchdog driver ssb: register watchdog driver drivers/bcma/bcma_private.h | 2 + drivers/bcma/driver_chipcommon.c | 114 +++++++++++++++++++++++++-- drivers/bcma/main.c | 8 ++ drivers/ssb/driver_chipcommon.c | 100 ++++++++++++++++++++--- drivers/ssb/driver_chipcommon_pmu.c | 27 +++++++ drivers/ssb/driver_extif.c | 24 +++++- drivers/ssb/embedded.c | 35 ++++++++ drivers/ssb/main.c | 8 ++ drivers/ssb/ssb_private.h | 31 ++++++++ include/linux/bcm47xx_wdt.h | 19 +++++ include/linux/bcma/bcma_driver_chipcommon.h | 7 +- include/linux/ssb/ssb.h | 2 + include/linux/ssb/ssb_driver_chipcommon.h | 5 +- include/linux/ssb/ssb_driver_extif.h | 10 ++- 14 files changed, 368 insertions(+), 24 deletions(-) create mode 100644 include/linux/bcm47xx_wdt.h -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:47:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:47:30 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37769 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831668Ab2LERr3i-2nm (ORCPT ); Wed, 5 Dec 2012 18:47:29 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 82FCE8F61; Wed, 5 Dec 2012 18:47:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vyPF2enVWUjN; Wed, 5 Dec 2012 18:46:52 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 161818F62; Wed, 5 Dec 2012 18:46:23 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 02/11] bcma: add bcma_chipco_alp_clock Date: Wed, 5 Dec 2012 18:45:59 +0100 Message-Id: <1354729568-19993-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35186 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1422 Lines: 47 For devices without a PMU the alp clock is always 20000000. Signed-off-by: Hauke Mehrtens --- drivers/bcma/driver_chipcommon.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c index ffd74e5..ef68553 100644 --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c @@ -4,6 +4,7 @@ * * Copyright 2005, Broadcom Corporation * Copyright 2006, 2007, Michael Buesch + * Copyright 2012, Hauke Mehrtens * * Licensed under the GNU/GPL. See COPYING for details. */ @@ -22,6 +23,14 @@ static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, return value; } +static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc) +{ + if (cc->capabilities & BCMA_CC_CAP_PMU) + return bcma_pmu_alp_clock(cc); + + return 20000000; +} + void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) { if (cc->early_setup_done) @@ -131,8 +140,7 @@ void bcma_chipco_serial_init(struct bcma_drv_cc *cc) struct bcma_serial_port *ports = cc->serial_ports; if (ccrev >= 11 && ccrev != 15) { - /* Fixed ALP clock */ - baud_base = bcma_pmu_alp_clock(cc); + baud_base = bcma_chipco_alp_clock(cc); if (ccrev >= 21) { /* Turn off UART clock before switching clocksource. */ bcma_cc_write32(cc, BCMA_CC_CORECTL, -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:47:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:47:51 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37783 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831680Ab2LERrtX67Qh (ORCPT ); Wed, 5 Dec 2012 18:47:49 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 314A88F70; Wed, 5 Dec 2012 18:47:48 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6GdgHn1JZEHr; Wed, 5 Dec 2012 18:47:31 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id BBCFC8F64; Wed, 5 Dec 2012 18:46:26 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 04/11] bcma: add methods for watchdog driver Date: Wed, 5 Dec 2012 18:46:01 +0100 Message-Id: <1354729568-19993-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35187 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3683 Lines: 113 The watchdog driver wants to set the watchdog timeout in ms and not in ticks, which is depending on the SoC type and the clock. Calculate the number of ticks per millisecond and provide two functions for the watchdog driver. Also return the ticks or millisecond the timer was set to in case the provided value was bigger than the max allowed value. Signed-off-by: Hauke Mehrtens --- drivers/bcma/driver_chipcommon.c | 38 ++++++++++++++++++++++++++- include/linux/bcma/bcma_driver_chipcommon.h | 4 +-- 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c index 7c132e5..1172226 100644 --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c @@ -10,6 +10,7 @@ */ #include "bcma_private.h" +#include #include #include @@ -52,6 +53,39 @@ static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) return (1 << nb) - 1; } +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, + u32 ticks) +{ + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); + + return bcma_chipco_watchdog_timer_set(cc, ticks); +} + +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt, + u32 ms) +{ + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); + u32 ticks; + + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); + return ticks / cc->ticks_per_ms; +} + +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) +{ + struct bcma_bus *bus = cc->core->bus; + + if (cc->capabilities & BCMA_CC_CAP_PMU) { + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */ + return bcma_chipco_alp_clock(cc) / 4000; + else + /* based on 32KHz ILP clock */ + return 32; + } else { + return bcma_chipco_alp_clock(cc) / 1000; + } +} void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) { @@ -100,12 +134,13 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); cc->setup_done = true; } /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) { u32 maxt; enum bcma_clkmode clkmode; @@ -125,6 +160,7 @@ void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) /* instant NMI */ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); } + return ticks; } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h index 145f3c5..2f9b014 100644 --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h @@ -570,6 +570,7 @@ struct bcma_drv_cc { int nr_serial_ports; struct bcma_serial_port serial_ports[4]; #endif /* CONFIG_BCMA_DRIVER_MIPS */ + u32 ticks_per_ms; }; /* Register access */ @@ -593,8 +594,7 @@ extern void bcma_chipco_resume(struct bcma_drv_cc *cc); void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, - u32 ticks); +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:47:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:48:09 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37791 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831681Ab2LERrvIER2R (ORCPT ); Wed, 5 Dec 2012 18:47:51 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 817EB8F64; Wed, 5 Dec 2012 18:47:50 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lYLiLyrmElQb; Wed, 5 Dec 2012 18:47:14 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 414788F63; Wed, 5 Dec 2012 18:46:23 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 03/11] bcma: set the pmu watchdog if available Date: Wed, 5 Dec 2012 18:46:00 +0100 Message-Id: <1354729568-19993-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35188 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2076 Lines: 72 Mostly all bcma based devices have a PMU and the PMU watchdog should be used and not the old one in chip common. This patch also calculates the maximal number the watchdog could be set to. Signed-off-by: Hauke Mehrtens --- drivers/bcma/driver_chipcommon.c | 42 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c index ef68553..7c132e5 100644 --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c @@ -31,6 +31,28 @@ static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc) return 20000000; } +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) +{ + struct bcma_bus *bus = cc->core->bus; + u32 nb; + + if (cc->capabilities & BCMA_CC_CAP_PMU) { + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) + nb = 32; + else if (cc->core->id.rev < 26) + nb = 16; + else + nb = (cc->core->id.rev >= 37) ? 32 : 24; + } else { + nb = 28; + } + if (nb == 32) + return 0xffffffff; + else + return (1 << nb) - 1; +} + + void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) { if (cc->early_setup_done) @@ -85,8 +107,24 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) { - /* instant NMI */ - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); + u32 maxt; + enum bcma_clkmode clkmode; + + maxt = bcma_chipco_watchdog_get_max_timer(cc); + if (cc->capabilities & BCMA_CC_CAP_PMU) { + if (ticks == 1) + ticks = 2; + else if (ticks > maxt) + ticks = maxt; + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); + } else { + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC; + bcma_core_set_clockmode(cc->core, clkmode); + if (ticks > maxt) + ticks = maxt; + /* instant NMI */ + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); + } } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:47:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:48:28 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37808 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831684Ab2LERr6aEIY6 (ORCPT ); Wed, 5 Dec 2012 18:47:58 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id EA5E38F61; Wed, 5 Dec 2012 18:47:56 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id asqumvobD+y2; Wed, 5 Dec 2012 18:47:49 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id D40CF8F65; Wed, 5 Dec 2012 18:46:28 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 05/11] bcma: register watchdog driver Date: Wed, 5 Dec 2012 18:46:02 +0100 Message-Id: <1354729568-19993-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35189 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3701 Lines: 116 Register the watchdog driver to the system if this is a SoC. Using the watchdog on a non SoC device, like a PCIe card, will make the PCIe card die when the timeout expired, but starting it again is not supported by bcma. Signed-off-by: Hauke Mehrtens --- drivers/bcma/bcma_private.h | 2 ++ drivers/bcma/driver_chipcommon.c | 22 ++++++++++++++++++++++ drivers/bcma/main.c | 8 ++++++++ include/linux/bcma/bcma_driver_chipcommon.h | 3 +++ 4 files changed, 35 insertions(+) diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h index 169fc58..bcb830e 100644 --- a/drivers/bcma/bcma_private.h +++ b/drivers/bcma/bcma_private.h @@ -84,6 +84,8 @@ extern void __exit bcma_host_pci_exit(void); /* driver_pci.c */ u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc); + #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c index 1172226..d017f25 100644 --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c @@ -12,6 +12,7 @@ #include "bcma_private.h" #include #include +#include #include static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, @@ -87,6 +88,27 @@ static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) } } +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) +{ + struct bcm47xx_wdt wdt = {}; + struct platform_device *pdev; + + wdt.driver_data = cc; + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; + + pdev = platform_device_register_data(NULL, "bcm47xx-wdt", + cc->core->bus->num, &wdt, + sizeof(wdt)); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + cc->watchdog = pdev; + + return 0; +} + void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) { if (cc->early_setup_done) diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c index a971889..debd4f1 100644 --- a/drivers/bcma/main.c +++ b/drivers/bcma/main.c @@ -165,6 +165,12 @@ static int bcma_register_cores(struct bcma_bus *bus) } #endif + if (bus->hosttype == BCMA_HOSTTYPE_SOC) { + err = bcma_chipco_watchdog_register(&bus->drv_cc); + if (err) + bcma_err(bus, "Error registering watchdog driver\n"); + } + return 0; } @@ -177,6 +183,8 @@ static void bcma_unregister_cores(struct bcma_bus *bus) if (core->dev_registered) device_unregister(&core->dev); } + if (bus->hosttype == BCMA_HOSTTYPE_SOC) + platform_device_unregister(bus->drv_cc.watchdog); } int __devinit bcma_bus_register(struct bcma_bus *bus) diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h index 2f9b014..e513591 100644 --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h @@ -1,6 +1,8 @@ #ifndef LINUX_BCMA_DRIVER_CC_H_ #define LINUX_BCMA_DRIVER_CC_H_ +#include + /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF @@ -571,6 +573,7 @@ struct bcma_drv_cc { struct bcma_serial_port serial_ports[4]; #endif /* CONFIG_BCMA_DRIVER_MIPS */ u32 ticks_per_ms; + struct platform_device *watchdog; }; /* Register access */ -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:48:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:48:46 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37821 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831678Ab2LERsH3eEHx (ORCPT ); Wed, 5 Dec 2012 18:48:07 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 066718F72; Wed, 5 Dec 2012 18:48:07 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id amzgzd3hZ3J5; Wed, 5 Dec 2012 18:47:51 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 39B948F66; Wed, 5 Dec 2012 18:46:30 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 06/11] ssb: get alp clock from devices with PMU Date: Wed, 5 Dec 2012 18:46:03 +0100 Message-Id: <1354729568-19993-7-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35190 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3100 Lines: 95 If there is a PMU in the device, get the alp clock from that part and do not assume 20000000. Signed-off-by: Hauke Mehrtens --- drivers/ssb/driver_chipcommon.c | 15 +++++++++------ drivers/ssb/driver_chipcommon_pmu.c | 27 +++++++++++++++++++++++++++ drivers/ssb/ssb_private.h | 1 + 3 files changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c index e9d2ca1..603b630 100644 --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c @@ -280,6 +280,14 @@ static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) cc->fast_pwrup_delay = tmp; } +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc) +{ + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) + return ssb_pmu_get_alp_clock(cc); + + return 20000000; +} + void ssb_chipcommon_init(struct ssb_chipcommon *cc) { if (!cc->dev) @@ -473,12 +481,7 @@ int ssb_chipco_serial_init(struct ssb_chipcommon *cc, chipco_read32(cc, SSB_CHIPCO_CORECTL) | SSB_CHIPCO_CORECTL_UARTCLK0); } else if ((ccrev >= 11) && (ccrev != 15)) { - /* Fixed ALP clock */ - baud_base = 20000000; - if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { - /* FIXME: baud_base is different for devices with a PMU */ - SSB_WARN_ON(1); - } + baud_base = ssb_chipco_alp_clock(cc); div = 1; if (ccrev >= 21) { /* Turn off UART clock before switching clocksource. */ diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c index d7d5804..a43415a 100644 --- a/drivers/ssb/driver_chipcommon_pmu.c +++ b/drivers/ssb/driver_chipcommon_pmu.c @@ -618,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on) EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage); EXPORT_SYMBOL(ssb_pmu_set_ldo_paref); +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc) +{ + u32 crystalfreq; + const struct pmu0_plltab_entry *e = NULL; + + crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) & + SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT; + e = pmu0_plltab_find_entry(crystalfreq); + BUG_ON(!e); + return e->freq * 1000; +} + +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc) +{ + struct ssb_bus *bus = cc->dev->bus; + + switch (bus->chip_id) { + case 0x5354: + ssb_pmu_get_alp_clock_clk0(cc); + default: + ssb_printk(KERN_ERR PFX + "ERROR: PMU alp clock unknown for device %04X\n", + bus->chip_id); + return 0; + } +} + u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc) { struct ssb_bus *bus = cc->dev->bus; diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h index a305550..98b2915 100644 --- a/drivers/ssb/ssb_private.h +++ b/drivers/ssb/ssb_private.h @@ -210,5 +210,6 @@ static inline void b43_pci_ssb_bridge_exit(void) /* driver_chipcommon_pmu.c */ extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc); extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc); +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc); #endif /* LINUX_SSB_PRIVATE_H_ */ -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:48:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:49:04 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37826 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831682Ab2LERsJmWS4Z (ORCPT ); Wed, 5 Dec 2012 18:48:09 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id D57CD8F73; Wed, 5 Dec 2012 18:48:08 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wDAUStfEcFPF; Wed, 5 Dec 2012 18:47:58 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 326E38F67; Wed, 5 Dec 2012 18:46:35 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 07/11] ssb: set the PMU watchdog if available Date: Wed, 5 Dec 2012 18:46:04 +0100 Message-Id: <1354729568-19993-8-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35191 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2003 Lines: 69 Some ssb based devices have a PMU and the PMU watchdog register should be used instead of the register in the chip common part, if the device has a PMU. This patch also calculates the maximal number the watchdog could be set to. Signed-off-by: Hauke Mehrtens --- drivers/ssb/driver_chipcommon.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c index 603b630..6e080f6 100644 --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c @@ -288,6 +288,24 @@ static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc) return 20000000; } +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc) +{ + u32 nb; + + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { + if (cc->dev->id.revision < 26) + nb = 16; + else + nb = (cc->dev->id.revision >= 37) ? 32 : 24; + } else { + nb = 28; + } + if (nb == 32) + return 0xffffffff; + else + return (1 << nb) - 1; +} + void ssb_chipcommon_init(struct ssb_chipcommon *cc) { if (!cc->dev) @@ -405,8 +423,24 @@ void ssb_chipco_timing_init(struct ssb_chipcommon *cc, /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) { - /* instant NMI */ - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); + u32 maxt; + enum ssb_clkmode clkmode; + + maxt = ssb_chipco_watchdog_get_max_timer(cc); + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { + if (ticks == 1) + ticks = 2; + else if (ticks > maxt) + ticks = maxt; + chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks); + } else { + clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC; + ssb_chipco_set_clockmode(cc, clkmode); + if (ticks > maxt) + ticks = maxt; + /* instant NMI */ + chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); + } } void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:48:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:49:23 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37839 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831686Ab2LERsOCPJMn (ORCPT ); Wed, 5 Dec 2012 18:48:14 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id B6D108F64; Wed, 5 Dec 2012 18:48:13 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bSFQhcyoQakZ; Wed, 5 Dec 2012 18:48:09 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 1C3458F69; Wed, 5 Dec 2012 18:46:37 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 09/11] ssb: extif: add check for max value before setting watchdog register Date: Wed, 5 Dec 2012 18:46:06 +0100 Message-Id: <1354729568-19993-10-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35192 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1269 Lines: 41 Prevent the watchdog register on the extif core to be set to a too high value. Signed-off-by: Hauke Mehrtens --- drivers/ssb/driver_extif.c | 5 +++-- include/linux/ssb/ssb_driver_extif.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/ssb/driver_extif.c b/drivers/ssb/driver_extif.c index dc47f30..0aa4c2a 100644 --- a/drivers/ssb/driver_extif.c +++ b/drivers/ssb/driver_extif.c @@ -112,9 +112,10 @@ void ssb_extif_get_clockcontrol(struct ssb_extif *extif, *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB); } -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, - u32 ticks) +void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks) { + if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER) + ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER; extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks); } diff --git a/include/linux/ssb/ssb_driver_extif.h b/include/linux/ssb/ssb_driver_extif.h index 2604efa..b618188 100644 --- a/include/linux/ssb/ssb_driver_extif.h +++ b/include/linux/ssb/ssb_driver_extif.h @@ -152,6 +152,7 @@ /* watchdog */ #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */ +#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1) #ifdef CONFIG_SSB_DRIVER_EXTIF -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:48:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:49:42 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37852 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831680Ab2LERsRKKhxS (ORCPT ); Wed, 5 Dec 2012 18:48:17 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id D2CF48F70; Wed, 5 Dec 2012 18:48:16 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PFFx6Dsnvg62; Wed, 5 Dec 2012 18:48:07 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 093488F68; Wed, 5 Dec 2012 18:46:36 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 08/11] ssb: add methods for watchdog driver Date: Wed, 5 Dec 2012 18:46:05 +0100 Message-Id: <1354729568-19993-9-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35193 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4993 Lines: 154 The watchdog driver wants to set the watchdog timeout in ms and not in ticks, which is depending on the SoC type and the clock. Calculate the number of ticks per millisecond and provide two functions for the watchdog driver. Also return the ticks or millisecond the timer was set to in case the provided value was bigger than the max allowed value. Signed-off-by: Hauke Mehrtens --- drivers/ssb/driver_chipcommon.c | 47 ++++++++++++++++++++++++++++- drivers/ssb/ssb_private.h | 5 +++ include/linux/ssb/ssb_driver_chipcommon.h | 5 +-- 3 files changed, 54 insertions(+), 3 deletions(-) diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c index 6e080f6..95c33a0 100644 --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c @@ -4,6 +4,7 @@ * * Copyright 2005, Broadcom Corporation * Copyright 2006, 2007, Michael Buesch + * Copyright 2012, Hauke Mehrtens * * Licensed under the GNU/GPL. See COPYING for details. */ @@ -12,6 +13,7 @@ #include #include #include +#include #include "ssb_private.h" @@ -306,6 +308,43 @@ static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc) return (1 << nb) - 1; } +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks) +{ + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt); + + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB) + return 0; + + return ssb_chipco_watchdog_timer_set(cc, ticks); +} + +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms) +{ + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt); + u32 ticks; + + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB) + return 0; + + ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); + return ticks / cc->ticks_per_ms; +} + +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc) +{ + struct ssb_bus *bus = cc->dev->bus; + + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { + /* based on 32KHz ILP clock */ + return 32; + } else { + if (cc->dev->id.revision < 18) + return ssb_clockspeed(bus) / 1000; + else + return ssb_chipco_alp_clock(cc) / 1000; + } +} + void ssb_chipcommon_init(struct ssb_chipcommon *cc) { if (!cc->dev) @@ -323,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc) chipco_powercontrol_init(cc); ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); calc_fast_powerup_delay(cc); + + if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) { + cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc); + cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; + } } void ssb_chipco_suspend(struct ssb_chipcommon *cc) @@ -421,7 +465,7 @@ void ssb_chipco_timing_init(struct ssb_chipcommon *cc, } /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) { u32 maxt; enum ssb_clkmode clkmode; @@ -441,6 +485,7 @@ void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) /* instant NMI */ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); } + return ticks; } void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h index 98b2915..03cc40a 100644 --- a/drivers/ssb/ssb_private.h +++ b/drivers/ssb/ssb_private.h @@ -3,6 +3,7 @@ #include #include +#include #define PFX "ssb: " @@ -212,4 +213,8 @@ extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc); extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc); extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc); +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, + u32 ticks); +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); + #endif /* LINUX_SSB_PRIVATE_H_ */ diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h index c2b02a5..38339fd 100644 --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h @@ -591,6 +591,8 @@ struct ssb_chipcommon { /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; struct ssb_chipcommon_pmu pmu; + u32 ticks_per_ms; + u32 max_timer_ms; }; static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) @@ -630,8 +632,7 @@ enum ssb_clkmode { extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, enum ssb_clkmode mode); -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, - u32 ticks); +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks); void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:48:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:50:00 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37863 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831687Ab2LERsUt7Gfm (ORCPT ); Wed, 5 Dec 2012 18:48:20 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 79D2C8F74; Wed, 5 Dec 2012 18:48:20 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id plAdivTLXjBQ; Wed, 5 Dec 2012 18:48:13 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id B68C28F6A; Wed, 5 Dec 2012 18:46:37 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 10/11] ssb: extif: add methods for watchdog driver Date: Wed, 5 Dec 2012 18:46:07 +0100 Message-Id: <1354729568-19993-11-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35194 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3807 Lines: 110 The watchdog driver wants to set the watchdog timeout in ms and not in ticks, add a method converting ms to ticks before setting the watchdog register. Return the ticks or millisecond the timer was set to in case the provided value was bigger than the max allowed value. Signed-off-by: Hauke Mehrtens --- drivers/ssb/driver_extif.c | 21 ++++++++++++++++++++- drivers/ssb/ssb_private.h | 15 +++++++++++++++ include/linux/ssb/ssb_driver_extif.h | 9 +++++---- 3 files changed, 40 insertions(+), 5 deletions(-) diff --git a/drivers/ssb/driver_extif.c b/drivers/ssb/driver_extif.c index 0aa4c2a..553227a 100644 --- a/drivers/ssb/driver_extif.c +++ b/drivers/ssb/driver_extif.c @@ -112,11 +112,30 @@ void ssb_extif_get_clockcontrol(struct ssb_extif *extif, *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB); } -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks) +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks) +{ + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt); + + return ssb_extif_watchdog_timer_set(extif, ticks); +} + +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms) +{ + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt); + u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms; + + ticks = ssb_extif_watchdog_timer_set(extif, ticks); + + return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK; +} + +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks) { if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER) ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER; extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks); + + return ticks; } u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h index 03cc40a..50ea028 100644 --- a/drivers/ssb/ssb_private.h +++ b/drivers/ssb/ssb_private.h @@ -217,4 +217,19 @@ extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks); extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); +#ifdef CONFIG_SSB_DRIVER_EXTIF +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks); +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); +#else +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, + u32 ticks) +{ + return 0; +} +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, + u32 ms) +{ + return 0; +} +#endif #endif /* LINUX_SSB_PRIVATE_H_ */ diff --git a/include/linux/ssb/ssb_driver_extif.h b/include/linux/ssb/ssb_driver_extif.h index b618188..99511d0 100644 --- a/include/linux/ssb/ssb_driver_extif.h +++ b/include/linux/ssb/ssb_driver_extif.h @@ -153,6 +153,8 @@ #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */ #define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1) +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \ + / (SSB_EXTIF_WATCHDOG_CLK / 1000)) #ifdef CONFIG_SSB_DRIVER_EXTIF @@ -172,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(struct ssb_extif *extif, extern void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns); -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, - u32 ticks); +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks); /* Extif GPIO pin access */ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask); @@ -211,9 +212,9 @@ void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns) } static inline -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, - u32 ticks) +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks) { + return 0; } static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 5 18:48:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 18:50:22 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:37871 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831685Ab2LERsXLechY (ORCPT ); Wed, 5 Dec 2012 18:48:23 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id D7AF28F61; Wed, 5 Dec 2012 18:48:22 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Gox2yLRcTivK; Wed, 5 Dec 2012 18:48:17 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 49BD48F6B; Wed, 5 Dec 2012 18:46:38 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com, wim@iguana.be Cc: linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v3 11/11] ssb: register watchdog driver Date: Wed, 5 Dec 2012 18:46:08 +0100 Message-Id: <1354729568-19993-12-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35195 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4297 Lines: 146 Register the watchdog driver to the system if it is a SoC. Using the watchdog on a non SoC device, like a PCI card, will make the PCI card die when the timeout expired, but starting it again is not supported by ssb. Signed-off-by: Hauke Mehrtens --- drivers/ssb/embedded.c | 35 +++++++++++++++++++++++++++++++++++ drivers/ssb/main.c | 8 ++++++++ drivers/ssb/ssb_private.h | 10 ++++++++++ include/linux/ssb/ssb.h | 2 ++ 4 files changed, 55 insertions(+) diff --git a/drivers/ssb/embedded.c b/drivers/ssb/embedded.c index 9ef124f..bb18d76 100644 --- a/drivers/ssb/embedded.c +++ b/drivers/ssb/embedded.c @@ -4,11 +4,13 @@ * * Copyright 2005-2008, Broadcom Corporation * Copyright 2006-2008, Michael Buesch + * Copyright 2012, Hauke Mehrtens * * Licensed under the GNU/GPL. See COPYING for details. */ #include +#include #include #include #include @@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks) } EXPORT_SYMBOL(ssb_watchdog_timer_set); +int ssb_watchdog_register(struct ssb_bus *bus) +{ + struct bcm47xx_wdt wdt = {}; + struct platform_device *pdev; + + if (ssb_chipco_available(&bus->chipco)) { + wdt.driver_data = &bus->chipco; + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt; + wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms; + wdt.max_timer_ms = bus->chipco.max_timer_ms; + } else if (ssb_extif_available(&bus->extif)) { + wdt.driver_data = &bus->extif; + wdt.timer_set = ssb_extif_watchdog_timer_set_wdt; + wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms; + wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS; + } else { + return -ENODEV; + } + + pdev = platform_device_register_data(NULL, "bcm47xx-wdt", + bus->busnumber, &wdt, + sizeof(wdt)); + if (IS_ERR(pdev)) { + ssb_dprintk(KERN_INFO PFX + "can not register watchdog device, err: %li\n", + PTR_ERR(pdev)); + return PTR_ERR(pdev); + } + + bus->watchdog = pdev; + return 0; +} + u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask) { unsigned long flags; diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c index df0f145..58c7da2 100644 --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -433,6 +434,11 @@ static void ssb_devices_unregister(struct ssb_bus *bus) if (sdev->dev) device_unregister(sdev->dev); } + +#ifdef CONFIG_SSB_EMBEDDED + if (bus->bustype == SSB_BUSTYPE_SSB) + platform_device_unregister(bus->watchdog); +#endif } void ssb_bus_unregister(struct ssb_bus *bus) @@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_buses(void) if (err) goto error; ssb_pcicore_init(&bus->pcicore); + if (bus->bustype == SSB_BUSTYPE_SSB) + ssb_watchdog_register(bus); ssb_bus_may_powerdown(bus); err = ssb_devices_register(bus); diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h index 50ea028..8942db1 100644 --- a/drivers/ssb/ssb_private.h +++ b/drivers/ssb/ssb_private.h @@ -232,4 +232,14 @@ static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, return 0; } #endif + +#ifdef CONFIG_SSB_EMBEDDED +extern int ssb_watchdog_register(struct ssb_bus *bus); +#else /* CONFIG_SSB_EMBEDDED */ +static inline int ssb_watchdog_register(struct ssb_bus *bus) +{ + return 0; +} +#endif /* CONFIG_SSB_EMBEDDED */ + #endif /* LINUX_SSB_PRIVATE_H_ */ diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index bb674c0..1f64e3f 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -8,6 +8,7 @@ #include #include #include +#include #include @@ -432,6 +433,7 @@ struct ssb_bus { #ifdef CONFIG_SSB_EMBEDDED /* Lock for GPIO register access. */ spinlock_t gpio_lock; + struct platform_device *watchdog; #endif /* EMBEDDED */ /* Internal-only stuff follows. Do not touch. */ -- 1.7.10.4 From julian.calaby@gmail.com Wed Dec 5 23:22:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Dec 2012 23:22:47 +0100 (CET) Received: from mail-ea0-f177.google.com ([209.85.215.177]:60729 "EHLO mail-ea0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831685Ab2LEWWpVuIw8 (ORCPT ); Wed, 5 Dec 2012 23:22:45 +0100 Received: by mail-ea0-f177.google.com with SMTP id c10so2222654eaa.36 for ; Wed, 05 Dec 2012 14:22:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=r7fkgQr+CsD4GMPFB5s0zN/5zgtTM0ouJWb/3Cc/lMI=; b=o9kqjekaOtBBxmH02N66jD8xZ9KtFHhkO8/kNRrXU7zrr+xtCYB1Suas7AlXstOx+k BKSNVNtgRH7rQdyDWXlRxyit0/z3JspqmUjfJOwTuc2ZBtkRqBDY63CTZ/IArWtIExZq egTNv64BNegz/LRLiFSSV9Qnh+D9+1YPzIEtQGjmv/RRUpYH3q0yTJ7T7ERB9kZZzvkB zQFWk/GGXfb6MoZ8+SKjkHn+KUKoISuNpLkoRFt3J69aNcb7pc+VwahOnrT4MeZvXcON MQQdSPRqil285OBw9DGOH3/tnZ2BmWV5b5oLClRO1zZsRyUZsDsuwzqkTl3Z2YTO0OT+ A/FA== Received: by 10.14.177.1 with SMTP id c1mr65207416eem.8.1354746159925; Wed, 05 Dec 2012 14:22:39 -0800 (PST) MIME-Version: 1.0 Received: by 10.14.224.129 with HTTP; Wed, 5 Dec 2012 14:22:19 -0800 (PST) In-Reply-To: <1354729568-19993-7-git-send-email-hauke@hauke-m.de> References: <1354729568-19993-1-git-send-email-hauke@hauke-m.de> <1354729568-19993-7-git-send-email-hauke@hauke-m.de> From: Julian Calaby Date: Thu, 6 Dec 2012 09:22:19 +1100 Message-ID: Subject: Re: [PATCH v3 06/11] ssb: get alp clock from devices with PMU To: Hauke Mehrtens Cc: linville@tuxdriver.com, wim@iguana.be, linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35196 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julian.calaby@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2185 Lines: 66 Hi Hauke, Sorry this is so late, I only just noticed. On Thu, Dec 6, 2012 at 4:46 AM, Hauke Mehrtens wrote: > If there is a PMU in the device, get the alp clock from that part and > do not assume 20000000. > > Signed-off-by: Hauke Mehrtens > --- > drivers/ssb/driver_chipcommon.c | 15 +++++++++------ > drivers/ssb/driver_chipcommon_pmu.c | 27 +++++++++++++++++++++++++++ > drivers/ssb/ssb_private.h | 1 + > 3 files changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c > index d7d5804..a43415a 100644 > --- a/drivers/ssb/driver_chipcommon_pmu.c > +++ b/drivers/ssb/driver_chipcommon_pmu.c > @@ -618,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on) > EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage); > EXPORT_SYMBOL(ssb_pmu_set_ldo_paref); > > +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc) > +{ > + u32 crystalfreq; > + const struct pmu0_plltab_entry *e = NULL; > + > + crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) & > + SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT; > + e = pmu0_plltab_find_entry(crystalfreq); > + BUG_ON(!e); > + return e->freq * 1000; > +} > + > +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc) > +{ > + struct ssb_bus *bus = cc->dev->bus; > + > + switch (bus->chip_id) { > + case 0x5354: > + ssb_pmu_get_alp_clock_clk0(cc); > + default: > + ssb_printk(KERN_ERR PFX > + "ERROR: PMU alp clock unknown for device %04X\n", > + bus->chip_id); > + return 0; Would it be better to return the default here (or handle this case in ssb_chipco_alp_clock() ) so these chips have a clock rate? > + } > +} > + > u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc) > { > struct ssb_bus *bus = cc->dev->bus; Thanks, -- Julian Calaby Email: julian.calaby@gmail.com Profile: http://www.google.com/profiles/julian.calaby/ .Plan: http://sites.google.com/site/juliancalaby/ From ralf@linux-mips.org Thu Dec 6 17:00:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Dec 2012 17:00:58 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36788 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6831874Ab2LFQAyQ4KkT (ORCPT ); Thu, 6 Dec 2012 17:00:54 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qB6G0rjE003756; Thu, 6 Dec 2012 17:00:53 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qB6G0qlV003755; Thu, 6 Dec 2012 17:00:52 +0100 Date: Thu, 6 Dec 2012 17:00:52 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: RM9000 / E9000, MSP71xx class processors, SOCs and eval boards Message-ID: <20121206160052.GB32620@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35197 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 426 Lines: 12 Folks, since many years the support code for those devices is rusting away in the lmo git tree and frankly, I'd get rid of it because there's been very few patch submissions or any kind of indication that somebody still cares. In short, this has turned into a waste of resource not least my time. So, is anybody still interested in maintaining that code? If so, you better attach a bunch of patches to your reply. Ralf From geert@linux-m68k.org Thu Dec 6 20:12:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Dec 2012 20:12:32 +0100 (CET) Received: from georges.telenet-ops.be ([195.130.137.68]:47161 "EHLO georges.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831900Ab2LFTMbCrOMd (ORCPT ); Thu, 6 Dec 2012 20:12:31 +0100 Received: from ayla.of.borg ([84.193.72.141]) by georges.telenet-ops.be with bizsmtp id YKCS1k00Y32ts5g06KCSbZ; Thu, 06 Dec 2012 20:12:28 +0100 Received: from geert by ayla.of.borg with local (Exim 4.71) (envelope-from ) id 1Tggry-0001yS-HI; Thu, 06 Dec 2012 20:12:26 +0100 From: Geert Uytterhoeven To: Ralf Baechle , David Daney Cc: linux-mips@linux-mips.org, Geert Uytterhoeven Subject: [PATCH] MIPS: Check BITS_PER_LONG instead of __SIZEOF_LONG__ Date: Thu, 6 Dec 2012 20:12:17 +0100 Message-Id: <1354821137-7562-1-git-send-email-geert@linux-m68k.org> X-Mailer: git-send-email 1.7.0.4 X-archive-position: 35198 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1123 Lines: 37 When building a 32-bit kernel for RBTX4927 with gcc version 4.1.2 20061115 (prerelease) (Ubuntu 4.1.1-21), I get: arch/mips/lib/delay.c:24:5: warning: "__SIZEOF_LONG__" is not defined As a consequence, __delay() always uses the 64-bit "dsubu" instruction. Replace the check for "__SIZEOF_LONG__ == 4" by "BITS_PER_LONG == 32" to fix this. Introduced by commit 5210edcd527773c227465ad18e416a894966324f ("MIPS: Make __{,n,u}delay declarations match definitions and generic delay.h") Signed-off-by: Geert Uytterhoeven -- Untested on real hardware. Ralf, is this sufficient to prevent you from nuking RBTX4927 support? ;-) --- arch/mips/lib/delay.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c index dc81ca8..288f795 100644 --- a/arch/mips/lib/delay.c +++ b/arch/mips/lib/delay.c @@ -21,7 +21,7 @@ void __delay(unsigned long loops) " .set noreorder \n" " .align 3 \n" "1: bnez %0, 1b \n" -#if __SIZEOF_LONG__ == 4 +#if BITS_PER_LONG == 32 " subu %0, 1 \n" #else " dsubu %0, 1 \n" -- 1.7.0.4 From ddaney@caviumnetworks.com Thu Dec 6 20:17:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Dec 2012 20:17:11 +0100 (CET) Received: from tx2ehsobe003.messaging.microsoft.com ([65.55.88.13]:30852 "EHLO tx2outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831898Ab2LFTRJzkZ31 (ORCPT ); Thu, 6 Dec 2012 20:17:09 +0100 Received: from mail175-tx2-R.bigfish.com (10.9.14.244) by TX2EHSOBE012.bigfish.com (10.9.40.32) with Microsoft SMTP Server id 14.1.225.23; Thu, 6 Dec 2012 19:17:06 +0000 Received: from mail175-tx2 (localhost [127.0.0.1]) by mail175-tx2-R.bigfish.com (Postfix) with ESMTP id 0B60532019C; Thu, 6 Dec 2012 19:17:06 +0000 (UTC) X-Forefront-Antispam-Report: CIP:157.56.236.213;KIP:(null);UIP:(null);IPV:NLI;H:BY2PRD0711HT002.namprd07.prod.outlook.com;RD:none;EFVD:NLI X-SpamScore: -4 X-BigFish: PS-4(zzbb2dI98dI9371I1432Izz1de0h1202h1d1ah1d2ahzz8275bh8275dhz2dh2a8h668h839h947hd25he5bhf0ah1288h12a5h12a9h12bdh137ah13b6h1441h14ddh1504h1537h153bh162dh1631h1155h) Received: from mail175-tx2 (localhost.localdomain [127.0.0.1]) by mail175-tx2 (MessageSwitch) id 1354821424347728_19019; Thu, 6 Dec 2012 19:17:04 +0000 (UTC) Received: from TX2EHSMHS038.bigfish.com (unknown [10.9.14.241]) by mail175-tx2.bigfish.com (Postfix) with ESMTP id 4917030019D; Thu, 6 Dec 2012 19:17:04 +0000 (UTC) Received: from BY2PRD0711HT002.namprd07.prod.outlook.com (157.56.236.213) by TX2EHSMHS038.bigfish.com (10.9.99.138) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 6 Dec 2012 19:17:03 +0000 Received: from dl.caveonetworks.com (64.2.3.195) by pod51018.outlook.com (10.255.88.165) with Microsoft SMTP Server (TLS) id 14.16.245.2; Thu, 6 Dec 2012 19:17:01 +0000 Message-ID: <50C0EF2C.3080705@caviumnetworks.com> Date: Thu, 6 Dec 2012 11:17:00 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Geert Uytterhoeven , Ralf Baechle CC: David Daney , Subject: Re: [PATCH] MIPS: Check BITS_PER_LONG instead of __SIZEOF_LONG__ References: <1354821137-7562-1-git-send-email-geert@linux-m68k.org> In-Reply-To: <1354821137-7562-1-git-send-email-geert@linux-m68k.org> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.195] X-OriginatorOrg: caviumnetworks.com X-archive-position: 35199 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1283 Lines: 41 On 12/06/2012 11:12 AM, Geert Uytterhoeven wrote: > When building a 32-bit kernel for RBTX4927 with gcc version 4.1.2 20061115 > (prerelease) (Ubuntu 4.1.1-21), I get: > > arch/mips/lib/delay.c:24:5: warning: "__SIZEOF_LONG__" is not defined > > As a consequence, __delay() always uses the 64-bit "dsubu" instruction. > > Replace the check for "__SIZEOF_LONG__ == 4" by "BITS_PER_LONG == 32" to > fix this. > > Introduced by commit 5210edcd527773c227465ad18e416a894966324f ("MIPS: Make > __{,n,u}delay declarations match definitions and generic delay.h") > > Signed-off-by: Geert Uytterhoeven Acked-by: David Daney > -- > Untested on real hardware. > Ralf, is this sufficient to prevent you from nuking RBTX4927 support? ;-) > --- > arch/mips/lib/delay.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c > index dc81ca8..288f795 100644 > --- a/arch/mips/lib/delay.c > +++ b/arch/mips/lib/delay.c > @@ -21,7 +21,7 @@ void __delay(unsigned long loops) > " .set noreorder \n" > " .align 3 \n" > "1: bnez %0, 1b \n" > -#if __SIZEOF_LONG__ == 4 > +#if BITS_PER_LONG == 32 > " subu %0, 1 \n" > #else > " dsubu %0, 1 \n" > From mcdonald.shane@gmail.com Thu Dec 6 22:28:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Dec 2012 22:28:24 +0100 (CET) Received: from mail-la0-f49.google.com ([209.85.215.49]:38653 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823118Ab2LFV2XRO-Bs (ORCPT ); Thu, 6 Dec 2012 22:28:23 +0100 Received: by mail-la0-f49.google.com with SMTP id r15so5159030lag.36 for ; Thu, 06 Dec 2012 13:28:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=JQ2nrOU/dfh1hXQld9/BvzmciAaC5Ckd/XcHonKQ504=; b=ptuBkwQqDpBEkp8Tjmw1AgAIXCTnGO62ELiFEJLaa5VG2Vkn26crzaelf1wIWFpyqk uMm7lcOIqDU7CM4VNLQBkEwNumLE9/FJZq/HM5uD4rAFZCrMRuJ1mNvmtJOrHrDIGVQV 8AGREi9X8NtpoaVPEAB86hb/cXhUBBXMLq2ZtAjhwrWijkOmumr86R/MZdEStMeal4YR wJGTN3/IyO4JeLBO5lIJQowmpslfRkiUXICDBCnkO1+7jUgSq4yxNlrn9tdmD5VcplO/ Jft8PgvMl1sAdNIfFUQXFM4GGm5RxLQKhny8DjreSHDLLvdK6oFZSusr88kGmnFlQAam nXew== MIME-Version: 1.0 Received: by 10.152.113.225 with SMTP id jb1mr3273402lab.23.1354829297427; Thu, 06 Dec 2012 13:28:17 -0800 (PST) Received: by 10.112.114.37 with HTTP; Thu, 6 Dec 2012 13:28:17 -0800 (PST) In-Reply-To: <20121206160052.GB32620@linux-mips.org> References: <20121206160052.GB32620@linux-mips.org> Date: Thu, 6 Dec 2012 15:28:17 -0600 Message-ID: Subject: Re: RM9000 / E9000, MSP71xx class processors, SOCs and eval boards From: Shane McDonald To: Ralf Baechle Cc: linux-mips , linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35200 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1036 Lines: 29 On Thu, Dec 6, 2012 at 10:00 AM, Ralf Baechle wrote: > Folks, > > since many years the support code for those devices is rusting away in > the lmo git tree and frankly, I'd get rid of it because there's been > very few patch submissions or any kind of indication that somebody > still cares. In short, this has turned into a waste of resource not > least my time. > > So, is anybody still interested in maintaining that code? If so, you > better attach a bunch of patches to your reply. > > Ralf > I'm interested in the MSP71xx eval board, although I may be the only person in the world who cares. Specifically, I use the msp71xx_defconfig. 3.7-rc8 compiles with gcc-4.6.3 without requiring any patches. I don't know when the last time the RM9000 was compilable, but I have no interest in that, nor do I have interest in the FPGA or eval board versions of the MSP7120 (no hardware to test with). I had hoped that someone from PMC-Sierra would respond, but maybe they don't care anymore... Shane McDonald From hauke@hauke-m.de Thu Dec 6 23:25:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Dec 2012 23:25:15 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:46245 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831901Ab2LFWZNoMXdH (ORCPT ); Thu, 6 Dec 2012 23:25:13 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id EC7998F66; Thu, 6 Dec 2012 23:25:12 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zjkvW2t8vCQ4; Thu, 6 Dec 2012 23:25:07 +0100 (CET) Received: from hauke-desktop.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 1648F8F63; Thu, 6 Dec 2012 23:25:06 +0100 (CET) From: Hauke Mehrtens To: john@phrozen.org, ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH] MIPS: BCM47XX: use fallback sprom var for board_{rev,type} Date: Thu, 6 Dec 2012 23:25:05 +0100 Message-Id: <1354832705-5926-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35201 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1363 Lines: 32 An SoC normally do not define path variables for board_rev and board_type and the Broadcom SDK also uses the nvram values without a prefix in such cases. Do the same to fill these sprom attributes from nvram and do not leave them empty, because brcmsmac do not like this. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/sprom.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c index 289cc0a..009c1ec 100644 --- a/arch/mips/bcm47xx/sprom.c +++ b/arch/mips/bcm47xx/sprom.c @@ -652,12 +652,10 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix, bool fallback) { - nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0, - fallback); + nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0, true); nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0, fallback); - nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, - fallback); + nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, true); nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, &sprom->boardflags_hi, fallback); nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo, -- 1.7.10.4 From ddaney.cavm@gmail.com Fri Dec 7 00:46:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 00:46:37 +0100 (CET) Received: from mail-gh0-f177.google.com ([209.85.160.177]:43118 "EHLO mail-gh0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831864Ab2LFXqgENiKH (ORCPT ); Fri, 7 Dec 2012 00:46:36 +0100 Received: by mail-gh0-f177.google.com with SMTP id g22so1182474ghb.36 for ; Thu, 06 Dec 2012 15:46:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=C8fytjMOHkHE5jAPCA4kxYlukDxaezm26ftd2Q3XZ+c=; b=b2SMt1OLpZm1Tx7CW/hmZlX2Gu3Ca6oEPHRIuRnzXtc5587qZNSSaosqtojN4bX9lK ausLv+S/mDc6ZSdze2bt8HZSiAc0Bprv+PkbAyl8/L4j9tfNlebQKeDtZYMedleER/9h h+nB9HOajRrm+GWJEJrK98hk5iQfYQKKpmoVrTJGZm+dVpy/pE4pX2PhBBTDuci2GF8G Z/Cgz7HMzQ+qJbGJXiskdvTQyes0LqIMfuISJDNHJ60p+Yvxvdb5MQ3GMtoEEX6ErubW UK9TQjfN0svKHPxpeossk6yUglwl6qHG+sS0jLjzfTZhVCd884DzyFzDHd4l2TLJ8dHR hP0Q== Received: by 10.236.92.172 with SMTP id j32mr4884558yhf.37.1354837589608; Thu, 06 Dec 2012 15:46:29 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id n20sm10334376anl.19.2012.12.06.15.46.26 (version=SSLv3 cipher=OTHER); Thu, 06 Dec 2012 15:46:27 -0800 (PST) Message-ID: <50C12E52.7010802@gmail.com> Date: Thu, 06 Dec 2012 15:46:26 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Geert Uytterhoeven CC: Ralf Baechle , David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Check BITS_PER_LONG instead of __SIZEOF_LONG__ References: <1354821137-7562-1-git-send-email-geert@linux-m68k.org> In-Reply-To: <1354821137-7562-1-git-send-email-geert@linux-m68k.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35202 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1360 Lines: 43 On 12/06/2012 11:12 AM, Geert Uytterhoeven wrote: > When building a 32-bit kernel for RBTX4927 with gcc version 4.1.2 20061115 > (prerelease) (Ubuntu 4.1.1-21), I get: > > arch/mips/lib/delay.c:24:5: warning: "__SIZEOF_LONG__" is not defined Sorry, looks like it may have been added in GCC-4.3. I didn't check any earlier versions when I made the original patch. > > As a consequence, __delay() always uses the 64-bit "dsubu" instruction. > > Replace the check for "__SIZEOF_LONG__ == 4" by "BITS_PER_LONG == 32" to > fix this. > > Introduced by commit 5210edcd527773c227465ad18e416a894966324f ("MIPS: Make > __{,n,u}delay declarations match definitions and generic delay.h") > > Signed-off-by: Geert Uytterhoeven > -- > Untested on real hardware. > Ralf, is this sufficient to prevent you from nuking RBTX4927 support? ;-) > --- > arch/mips/lib/delay.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c > index dc81ca8..288f795 100644 > --- a/arch/mips/lib/delay.c > +++ b/arch/mips/lib/delay.c > @@ -21,7 +21,7 @@ void __delay(unsigned long loops) > " .set noreorder \n" > " .align 3 \n" > "1: bnez %0, 1b \n" > -#if __SIZEOF_LONG__ == 4 > +#if BITS_PER_LONG == 32 > " subu %0, 1 \n" > #else > " dsubu %0, 1 \n" > From sjhill@mips.com Fri Dec 7 05:50:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 05:50:52 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60238 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816191Ab2LGEuvLxU80 (ORCPT ); Fri, 7 Dec 2012 05:50:51 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgptb-0007Jd-4v; Thu, 06 Dec 2012 22:50:43 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Remove usage of CSRC_R4K_LIB config option. Date: Thu, 6 Dec 2012 22:50:37 -0600 Message-Id: <1354855837-28187-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35203 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1806 Lines: 65 From: "Steven J. Hill" The CSRC_R4K_LIB is redundant and can safely be removed. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 6 +----- arch/mips/include/asm/time.h | 2 +- arch/mips/kernel/Makefile | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index dba9390..40cb646 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -54,7 +54,7 @@ config MIPS_ALCHEMY bool "Alchemy processor based machines" select 64BIT_PHYS_ADDR select CEVT_R4K_LIB - select CSRC_R4K_LIB + select CSRC_R4K select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL @@ -946,11 +946,7 @@ config CSRC_IOASIC config CSRC_POWERTV bool -config CSRC_R4K_LIB - bool - config CSRC_R4K - select CSRC_R4K_LIB bool config CSRC_SB1250 diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index bc14447..6be93a4 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -71,7 +71,7 @@ static inline int mips_clockevent_init(void) /* * Initialize the count register as a clocksource */ -#ifdef CONFIG_CSRC_R4K_LIB +#ifdef CONFIG_CSRC_R4K extern int init_r4k_clocksource(void); #endif diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 8b28bc4..e4260b6 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -25,7 +25,7 @@ obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o -obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o +obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 05:51:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 05:51:18 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60243 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816191Ab2LGEvQoY68l (ORCPT ); Fri, 7 Dec 2012 05:51:16 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgpu2-0007Jn-HG; Thu, 06 Dec 2012 22:51:10 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Add new GIC clocksource. Date: Thu, 6 Dec 2012 22:51:04 -0600 Message-Id: <1354855864-28226-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35204 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8107 Lines: 290 From: "Steven J. Hill" Add new clocksource that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 4 ++ arch/mips/include/asm/gic.h | 1 + arch/mips/include/asm/time.h | 2 +- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/csrc-gic.c | 49 ++++++++++++++++++++++ arch/mips/mti-malta/malta-time.c | 83 +++++++++++++++++++++++--------------- 6 files changed, 106 insertions(+), 34 deletions(-) create mode 100644 arch/mips/kernel/csrc-gic.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 40cb646..99c3ad7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -293,6 +293,7 @@ config MIPS_MALTA select BOOT_RAW select CEVT_R4K select CSRC_R4K + select CSRC_GIC select DMA_NONCOHERENT select GENERIC_ISA_DMA select HAVE_PCSPKR_PLATFORM @@ -949,6 +950,9 @@ config CSRC_POWERTV config CSRC_R4K bool +config CSRC_GIC + bool + config CSRC_SB1250 bool diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 37620db..bbddd25 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -359,6 +359,7 @@ struct gic_shared_intr_map { /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ #define GIC_PIN_TO_VEC_OFFSET (1) +extern int gic_present; extern unsigned long _gic_base; extern unsigned int gic_irq_base; extern unsigned int gic_irq_flags[]; diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index 6be93a4..d0e3cb5 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -77,7 +77,7 @@ extern int init_r4k_clocksource(void); static inline int init_mips_clocksource(void) { -#ifdef CONFIG_CSRC_R4K +#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC) return init_r4k_clocksource(); #else return 0; diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index e4260b6..99dc7f9 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o +obj-$(CONFIG_CSRC_GIC) += csrc-gic.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o obj-$(CONFIG_STACKTRACE) += stacktrace.o diff --git a/arch/mips/kernel/csrc-gic.c b/arch/mips/kernel/csrc-gic.c new file mode 100644 index 0000000..5dca24b --- /dev/null +++ b/arch/mips/kernel/csrc-gic.c @@ -0,0 +1,49 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include + +#include +#include + +static cycle_t gic_hpt_read(struct clocksource *cs) +{ + unsigned int hi, hi2, lo; + + do { + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi); + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo); + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2); + } while (hi2 != hi); + + return (((cycle_t) hi) << 32) + lo; +} + +static struct clocksource gic_clocksource = { + .name = "GIC", + .read = gic_hpt_read, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void __init gic_clocksource_init(unsigned int frequency) +{ + unsigned int config, bits; + + /* Calculate the clocksource mask. */ + GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), config); + bits = 32 + ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> + (GIC_SH_CONFIG_COUNTBITS_SHF - 2)); + + /* Set clocksource mask. */ + gic_clocksource.mask = CLOCKSOURCE_MASK(bits); + + /* Calculate a somewhat reasonable rating value. */ + gic_clocksource.rating = 200 + frequency / 10000000; + + clocksource_register_hz(&gic_clocksource, frequency); +} diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 115f5bc..a144b89 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -17,7 +17,6 @@ * * Setting up the clock on the MIPS boards. */ - #include #include #include @@ -25,7 +24,6 @@ #include #include #include -#include #include #include @@ -34,11 +32,11 @@ #include #include #include -#include #include #include #include #include +#include #include #include @@ -46,6 +44,7 @@ #include unsigned long cpu_khz; +int gic_frequency; static int mips_cpu_timer_irq; static int mips_cpu_perf_irq; @@ -61,44 +60,50 @@ static void mips_perf_dispatch(void) do_IRQ(mips_cpu_perf_irq); } +static unsigned int freqround(unsigned int freq, unsigned int amount) +{ + freq += amount; + freq -= freq % (amount*2); + return freq; +} + /* - * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect + * Estimate CPU and GIC frequencies. */ -static unsigned int __init estimate_cpu_frequency(void) +static void __init estimate_frequencies(void) { - unsigned int prid = read_c0_prid() & 0xffff00; - unsigned int count; - unsigned long flags; - unsigned int start; + unsigned int count, start; + unsigned int giccount = 0, gicstart = 0; local_irq_save(flags); - /* Start counter exactly on falling edge of update flag */ + /* Start counter exactly on falling edge of update flag. */ while (CMOS_READ(RTC_REG_A) & RTC_UIP); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - /* Start r4k counter. */ + /* Initialize counters. */ start = read_c0_count(); + if (gic_present) + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart); - /* Read counter exactly on falling edge of update flag */ + /* Read counter exactly on falling edge of update flag. */ while (CMOS_READ(RTC_REG_A) & RTC_UIP); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - count = read_c0_count() - start; + count = read_c0_count(); + if (gic_present) + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount); - /* restore interrupts */ local_irq_restore(flags); - mips_hpt_frequency = count; - if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && - (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) - count *= 2; - - count += 5000; /* round */ - count -= count%10000; + count -= start; + if (gic_present) + giccount -= gicstart; - return count; + mips_hpt_frequency = count; + if (gic_present) + gic_frequency = giccount; } void read_persistent_clock(struct timespec *ts) @@ -144,22 +149,34 @@ unsigned int __cpuinit get_c0_compare_int(void) void __init plat_time_init(void) { - unsigned int est_freq; - - /* Set Data mode - binary. */ - CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - - est_freq = estimate_cpu_frequency(); + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int freq; - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, - (est_freq%1000000)*100/1000000); + estimate_frequencies(); - cpu_khz = est_freq / 1000; + freq = mips_hpt_frequency; + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + freq *= 2; + freq = freqround(freq, 5000); + pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000, + (freq%1000000)*100/1000000); + cpu_khz = freq / 1000; + + if (gic_present) { + freq = freqround(gic_frequency, 5000); + pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000, + (freq%1000000)*100/1000000); + gic_clocksource_init(gic_frequency); + } else + init_r4k_clocksource(); - mips_scroll_message(); -#ifdef CONFIG_I8253 /* Only Malta has a PIT */ +#ifdef CONFIG_I8253 + /* Only Malta has a PIT. */ setup_pit_timer(); #endif + mips_scroll_message(); + plat_perf_setup(); } -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 05:51:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 05:51:48 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60247 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816191Ab2LGEvrMNzON (ORCPT ); Fri, 7 Dec 2012 05:51:47 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgpuX-0007Jz-49; Thu, 06 Dec 2012 22:51:41 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Add support for the M14KEc core. Date: Thu, 6 Dec 2012 22:51:35 -0600 Message-Id: <1354855895-28269-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35205 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5060 Lines: 154 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu-features.h | 3 +++ arch/mips/include/asm/cpu.h | 3 +++ arch/mips/include/asm/mipsregs.h | 1 + arch/mips/kernel/cpu-probe.c | 7 +++++++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 4 ++++ 8 files changed, 21 insertions(+) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index c507b93..00171cd 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -98,6 +98,9 @@ #ifndef cpu_has_rixi #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) #endif +#ifndef cpu_has_mmips +#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) +#endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 52c4e91..7bb9079 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -96,6 +96,7 @@ #define PRID_IMP_1004K 0x9900 #define PRID_IMP_1074K 0x9a00 #define PRID_IMP_M14KC 0x9c00 +#define PRID_IMP_M14KEC 0x9e00 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -264,6 +265,7 @@ enum cpu_type_enum { CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, + CPU_M14KEC, /* * MIPS64 class processors @@ -322,6 +324,7 @@ enum cpu_type_enum { #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ #define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ #define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ +#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ /* * CPU ASE encodings diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index eb74289..bec253f 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -595,6 +595,7 @@ #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) +#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index cce3782..8db7a47 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -201,6 +201,7 @@ void __init check_wait(void) break; case CPU_M14KC: + case CPU_M14KEC: case CPU_24K: case CPU_34K: case CPU_1004K: @@ -439,6 +440,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->ases |= MIPS_ASE_MIPSMT; if (config3 & MIPS_CONF3_ULRI) c->options |= MIPS_CPU_ULRI; + if (config3 & MIPS_CONF3_ISA) + c->options |= MIPS_CPU_MICROMIPS; return config3 & MIPS_CONF_M; } @@ -858,6 +861,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_M14KC; __cpu_name[cpu] = "MIPS M14Kc"; break; + case PRID_IMP_M14KEC: + c->cputype = CPU_M14KEC; + __cpu_name[cpu] = "MIPS M14KEc"; + break; case PRID_IMP_1004K: c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 2b61462..c0f27c8 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1060,6 +1060,7 @@ static void __cpuinit probe_pcache(void) break; case CPU_M14KC: + case CPU_M14KEC: case CPU_24K: case CPU_34K: case CPU_74K: diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 2833dcb..6f3d4007 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -539,6 +539,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_4KC: case CPU_4KEC: case CPU_M14KC: + case CPU_M14KEC: case CPU_SB1: case CPU_SB1A: case CPU_4KSC: diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index f80480a..48399be 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -79,6 +79,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) switch (current_cpu_type()) { case CPU_5KC: case CPU_M14KC: + case CPU_M14KEC: case CPU_20KC: case CPU_24K: case CPU_25KF: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 28ea1a4..efa7fbb 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -326,6 +326,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/M14Kc"; break; + case CPU_M14KEC: + op_model_mipsxx_ops.cpu_type = "mips/M14KEc"; + break; + case CPU_20KC: op_model_mipsxx_ops.cpu_type = "mips/20K"; break; -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 05:52:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 05:52:16 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60253 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822126Ab2LGEwPUZR8- (ORCPT ); Fri, 7 Dec 2012 05:52:15 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgpuz-0007KH-6n; Thu, 06 Dec 2012 22:52:09 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: dsp: Fix DSP mask for registers. Date: Thu, 6 Dec 2012 22:52:03 -0600 Message-Id: <1354855923-28310-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35206 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 611 Lines: 25 From: "Steven J. Hill" The DSP bit mask for the rddsp and wrdsp instructions was wrong. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/dsp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h index e9bfc08..7bfad05 100644 --- a/arch/mips/include/asm/dsp.h +++ b/arch/mips/include/asm/dsp.h @@ -16,7 +16,7 @@ #include #define DSP_DEFAULT 0x00000000 -#define DSP_MASK 0x3ff +#define DSP_MASK 0x3f #define __enable_dsp_hazard() \ do { \ -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 05:52:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 05:52:49 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60255 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822126Ab2LGEwsT3LWC (ORCPT ); Fri, 7 Dec 2012 05:52:48 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgpvW-0007KS-DB; Thu, 06 Dec 2012 22:52:42 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: microMIPS: Add breakpoints. Date: Thu, 6 Dec 2012 22:52:37 -0600 Message-Id: <1354855957-28353-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35207 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1240 Lines: 35 From: "Steven J. Hill" Redefine BRK_BUG and BRK_KDB values when using a pure microMIPS kernel. Add MM_BRK_MEMU for running microMIPS user binaries on a standard kernel. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/break.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 9161e68..c4744aa 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -27,9 +27,16 @@ #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ + +#ifdef CONFIG_CPU_MICROMIPS +#define BRK_BUG 12 /* Used by BUG() */ +#define BRK_KDB 13 /* Used in KDB_ENTER() */ +#else #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ +#endif #define BRK_MEMU 514 /* Used by FPU emulator */ +#define MM_BRK_MEMU 14 /* Used by FPU emulator for microMIPS */ #define BRK_KPROBE_BP 515 /* Kprobe break */ #define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */ #define BRK_MULOVF 1023 /* Multiply overflow */ -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 05:53:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 05:53:14 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60260 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822126Ab2LGExNMUHpL (ORCPT ); Fri, 7 Dec 2012 05:53:13 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgpvv-0007Kf-5d; Thu, 06 Dec 2012 22:53:07 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: dsp: Add assembler support for DSP ASEs. Date: Thu, 6 Dec 2012 22:53:01 -0600 Message-Id: <1354855981-28392-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35208 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3712 Lines: 132 From: "Steven J. Hill" Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mipsregs.h | 53 ++++++++++++++++++++++++++------------ arch/mips/kernel/Makefile | 24 +++++++++++++++++ 2 files changed, 60 insertions(+), 17 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index bec253f..5d400d2 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1163,36 +1163,26 @@ do { \ : "=r" (__res)); \ __res;}) +#ifdef HAVE_AS_DSP #define rddsp(mask) \ ({ \ - unsigned int __res; \ + unsigned int __dspctl; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ + " rddsp %0, %x1 \n" \ + : "=r" (__dspctl) \ : "i" (mask)); \ - __res; \ + __dspctl; \ }) #define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ - " .set pop \n" \ - : \ + " wrdsp %0, %x1 \n" \ + : \ : "r" (val), "i" (mask)); \ } while (0) -#if 0 /* Need DSP ASE capable assembler ... */ #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) @@ -1215,6 +1205,35 @@ do { \ #else +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ + " .set pop \n" \ + : \ + : "r" (val), "i" (mask)); \ +} while (0) + #define mfhi0() \ ({ \ unsigned long __treg; \ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 99dc7f9..e034ad6 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -99,4 +99,28 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o +ifeq ($(CONFIG_CPU_MIPS32), y) +# +# Check if assembler supports DSP ASE +# +ifeq ($(call cc-option-yn,-mdsp), y) +CFLAGS_signal.o = -mdsp -DHAVE_AS_DSP +CFLAGS_signal32.o = -mdsp -DHAVE_AS_DSP +CFLAGS_process.o = -mdsp -DHAVE_AS_DSP +CFLAGS_branch.o = -mdsp -DHAVE_AS_DSP +CFLAGS_ptrace.o = -mdsp -DHAVE_AS_DSP +endif + +# +# Check if assembler supports DSP ASE Rev2 +# +ifeq ($(call cc-option-yn,-mdsp2), y) +CFLAGS_signal.o = -mdsp2 -DHAVE_AS_DSP +CFLAGS_signal32.o = -mdsp2 -DHAVE_AS_DSP +CFLAGS_process.o = -mdsp2 -DHAVE_AS_DSP +CFLAGS_branch.o = -mdsp2 -DHAVE_AS_DSP +CFLAGS_ptrace.o = -mdsp2 -DHAVE_AS_DSP +endif +endif + CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 05:53:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 05:53:42 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60262 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822126Ab2LGExlmbKqK (ORCPT ); Fri, 7 Dec 2012 05:53:41 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgpwN-0007Kp-I3; Thu, 06 Dec 2012 22:53:35 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: dsp: Support toolchains without DSP ASE and microMIPS. Date: Thu, 6 Dec 2012 22:53:29 -0600 Message-Id: <1354856009-28432-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35209 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3190 Lines: 120 From: "Steven J. Hill" Add macros to support the DSP ASE with microMIPS kernels when the toolchain does not have support. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mipsregs.h | 89 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 5d400d2..c1e0221 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1205,6 +1205,94 @@ do { \ #else +#ifdef CONFIG_CPU_MICROMIPS +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # wrdsp $1, %x1 \n" \ + " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ + " .set pop \n" \ + : \ + : "r" (val), "i" (mask)); \ +} while (0) + +#define _umips_dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) + +#define _umips_dsp_mtxxx(val, ins) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ + " .set pop \n" \ + : \ + : "r" (val), "i" (ins)); \ +} while (0) + +#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) +#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) + +#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) +#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) + +#define mflo0() _umips_dsp_mflo(0) +#define mflo1() _umips_dsp_mflo(1) +#define mflo2() _umips_dsp_mflo(2) +#define mflo3() _umips_dsp_mflo(3) + +#define mfhi0() _umips_dsp_mfhi(0) +#define mfhi1() _umips_dsp_mfhi(1) +#define mfhi2() _umips_dsp_mfhi(2) +#define mfhi3() _umips_dsp_mfhi(3) + +#define mtlo0(x) _umips_dsp_mtlo(x, 0) +#define mtlo1(x) _umips_dsp_mtlo(x, 1) +#define mtlo2(x) _umips_dsp_mtlo(x, 2) +#define mtlo3(x) _umips_dsp_mtlo(x, 3) + +#define mthi0(x) _umips_dsp_mthi(x, 0) +#define mthi1(x) _umips_dsp_mthi(x, 1) +#define mthi2(x) _umips_dsp_mthi(x, 2) +#define mthi3(x) _umips_dsp_mthi(x, 3) + +#else /* !CONFIG_CPU_MICROMIPS */ #define rddsp(mask) \ ({ \ unsigned int __res; \ @@ -1458,6 +1546,7 @@ do { \ : "r" (x)); \ } while (0) +#endif /* CONFIG_CPU_MICROMIPS */ #endif /* -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 05:54:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 05:54:07 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60265 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823142Ab2LGEyEz6JYO (ORCPT ); Fri, 7 Dec 2012 05:54:04 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgpwk-0007Kw-Ob; Thu, 06 Dec 2012 22:53:58 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: dsp: Simplify the DSP macros. Date: Thu, 6 Dec 2012 22:53:52 -0600 Message-Id: <1354856032-28475-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35210 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6517 Lines: 277 From: "Steven J. Hill" Simplify the DSP macros for vanilla (non-microMIPS) kernels and toolchains that do not support the DSP ASEs. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mipsregs.h | 231 +++++--------------------------------- 1 file changed, 30 insertions(+), 201 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index c1e0221..0c0e4a6 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1322,229 +1322,58 @@ do { \ : "r" (val), "i" (mask)); \ } while (0) -#define mfhi0() \ +#define _dsp_mfxxx(ins) \ ({ \ unsigned long __treg; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac0 \n" \ - " .word 0x00000810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac1 \n" \ - " .word 0x00200810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac2 \n" \ - " .word 0x00400810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac3 \n" \ - " .word 0x00600810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac0 \n" \ - " .word 0x00000812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac1 \n" \ - " .word 0x00200812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac2 \n" \ - " .word 0x00400812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac3 \n" \ - " .word 0x00600812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mthi0(x) \ -do { \ - __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac0 \n" \ - " .word 0x00200011 \n" \ + " .word (0x00000810 | %1) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mthi1(x) \ +#define _dsp_mtxxx(val, ins) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mthi $1, $ac1 \n" \ - " .word 0x00200811 \n" \ + " .word (0x00200011 | %1) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (ins)); \ } while (0) -#define mthi2(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac2 \n" \ - " .word 0x00201011 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) +#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) +#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) -#define mthi3(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac3 \n" \ - " .word 0x00201811 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) +#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) +#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) -#define mtlo0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac0 \n" \ - " .word 0x00200013 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) +#define mflo0() _dsp_mflo(0) +#define mflo1() _dsp_mflo(1) +#define mflo2() _dsp_mflo(2) +#define mflo3() _dsp_mflo(3) -#define mtlo1(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac1 \n" \ - " .word 0x00200813 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) +#define mfhi0() _dsp_mfhi(0) +#define mfhi1() _dsp_mfhi(1) +#define mfhi2() _dsp_mfhi(2) +#define mfhi3() _dsp_mfhi(3) -#define mtlo2(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac2 \n" \ - " .word 0x00201013 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) +#define mtlo0(x) _dsp_mtlo(x, 0) +#define mtlo1(x) _dsp_mtlo(x, 1) +#define mtlo2(x) _dsp_mtlo(x, 2) +#define mtlo3(x) _dsp_mtlo(x, 3) -#define mtlo3(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac3 \n" \ - " .word 0x00201813 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) +#define mthi0(x) _dsp_mthi(x, 0) +#define mthi1(x) _dsp_mthi(x, 1) +#define mthi2(x) _dsp_mthi(x, 2) +#define mthi3(x) _dsp_mthi(x, 3) #endif /* CONFIG_CPU_MICROMIPS */ #endif -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:05:51 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60304 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815793Ab2LGFFtn7xi0 (ORCPT ); Fri, 7 Dec 2012 06:05:49 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq86-0007MA-T8; Thu, 06 Dec 2012 23:05:42 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,00/13] Add support for pure microMIPS kernel. Date: Thu, 6 Dec 2012 23:05:24 -0600 Message-Id: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35211 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2927 Lines: 63 From: "Steven J. Hill" This set of patches is to support building a pure microMIPS kernel image using only instructions from the microMIPS ISA. The result is a kernel binary size reduction of more than 20% and an increase in the speed of execution due to the smaller and faster instructions. Douglas Leung (1): MIPS: microMIPS: Add vdso support. Steven J. Hill (12): MIPS: microMIPS: Add support for microMIPS instructions. MIPS: Whitespace clean-ups after microMIPS additions. MIPS: microMIPS: Floating point support for 16-bit instructions. MIPS: microMIPS: Add support for exception handling. MIPS: microMIPS: Support handling of delay slots. MIPS: microMIPS: Add unaligned access support. MIPS: microMIPS: Add configuration option for microMIPS kernel. MIPS: microMIPS: Work-around for assembler bug. MIPS: microMIPS: Optimise 'memset' core library function. MIPS: microMIPS: Optimise 'strncpy' core library function. MIPS: microMIPS: Optimise 'strlen' core library function. MIPS: microMIPS: Optimise 'strnlen' core library function. arch/mips/Kconfig | 11 + arch/mips/Makefile | 1 + arch/mips/configs/sead3micro_defconfig | 125 +++ arch/mips/include/asm/asm.h | 2 + arch/mips/include/asm/branch.h | 33 +- arch/mips/include/asm/fpu_emulator.h | 7 + arch/mips/include/asm/inst.h | 858 +++++++++++++++++- arch/mips/include/asm/mipsregs.h | 41 +- arch/mips/include/asm/stackframe.h | 12 +- arch/mips/include/asm/uaccess.h | 14 +- arch/mips/kernel/branch.c | 183 +++- arch/mips/kernel/cpu-probe.c | 3 + arch/mips/kernel/genex.S | 74 +- arch/mips/kernel/proc.c | 5 + arch/mips/kernel/process.c | 101 +++ arch/mips/kernel/scall32-o32.S | 9 + arch/mips/kernel/signal.c | 6 + arch/mips/kernel/smtc-asm.S | 3 + arch/mips/kernel/traps.c | 296 +++++-- arch/mips/kernel/unaligned.c | 1496 +++++++++++++++++++++++++++----- arch/mips/lib/memset.S | 84 +- arch/mips/lib/strlen_user.S | 9 +- arch/mips/lib/strncpy_user.S | 28 +- arch/mips/lib/strnlen_user.S | 2 +- arch/mips/math-emu/cp1emu.c | 766 ++++++++++++++-- arch/mips/math-emu/dsemul.c | 40 +- arch/mips/mm/tlbex.c | 21 + arch/mips/mm/uasm-micromips.c | 194 +++++ arch/mips/mm/uasm-mips.c | 178 ++++ arch/mips/mm/uasm.c | 211 +---- arch/mips/mti-sead3/sead3-init.c | 48 + 31 files changed, 4159 insertions(+), 702 deletions(-) create mode 100644 arch/mips/configs/sead3micro_defconfig create mode 100644 arch/mips/mm/uasm-micromips.c create mode 100644 arch/mips/mm/uasm-mips.c -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:06:15 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60306 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823707Ab2LGFFv3cq6I (ORCPT ); Fri, 7 Dec 2012 06:05:51 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq88-0007MA-5D; Thu, 06 Dec 2012 23:05:44 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,01/13] MIPS: microMIPS: Add support for microMIPS instructions. Date: Thu, 6 Dec 2012 23:05:25 -0600 Message-Id: <1354856737-28678-2-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35212 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 42186 Lines: 1513 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/inst.h | 771 +++++++++++++++++++++++++++++++++++++++++ arch/mips/mm/uasm-micromips.c | 194 +++++++++++ arch/mips/mm/uasm-mips.c | 178 ++++++++++ arch/mips/mm/uasm.c | 211 ++--------- 4 files changed, 1177 insertions(+), 177 deletions(-) create mode 100644 arch/mips/mm/uasm-micromips.c create mode 100644 arch/mips/mm/uasm-mips.c diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index ab84064..c76899f 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -7,6 +7,7 @@ * * Copyright (C) 1996, 2000 by Ralf Baechle * Copyright (C) 2006 by Thiemo Seufer + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #ifndef _ASM_INST_H #define _ASM_INST_H @@ -267,6 +268,225 @@ struct b_format { /* BREAK and SYSCALL */ unsigned int func:6; }; +struct fb_format { /* FPU branch format */ + unsigned int opcode:6; + unsigned int bc:5; + unsigned int cc:3; + unsigned int flag:2; + unsigned int simmediate:16; +}; + +struct fp0_format { /* FPU multipy and add format (MIPS32) */ + unsigned int opcode:6; + unsigned int fmt:5; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:6; +}; + +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ + unsigned int opcode:6; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int fmt:3; + unsigned int op:2; + unsigned int func:6; +}; + +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ + unsigned int opcode:6; + unsigned int op:5; + unsigned int rt:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:6; +}; + +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int fs:5; + unsigned int fmt:2; + unsigned int op:8; + unsigned int func:6; +}; + +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ + unsigned int opcode:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int cc:3; + unsigned int zero:2; + unsigned int fmt:2; + unsigned int op:3; + unsigned int func:6; +}; + +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int fs:5; + unsigned int fmt:3; + unsigned int op:7; + unsigned int func:6; +}; + +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int fs:5; + unsigned int cc:3; + unsigned int fmt:3; + unsigned int cond:4; + unsigned int func:6; +}; + +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ + unsigned int opcode:6; + unsigned int index:5; + unsigned int base:5; + unsigned int fd:5; + unsigned int op:5; + unsigned int func:6; +}; + +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ + unsigned int opcode:6; + unsigned int fr:5; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:6; +}; + +struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ + unsigned int opcode:6; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int fr:5; + unsigned int func:6; +}; + +struct mm16b1_format { /* microMIPS 16-bit branch format */ + unsigned int opcode:6; + unsigned int rs:3; + signed int simmediate:7; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm16b0_format { /* microMIPS 16-bit branch format */ + unsigned int opcode:6; + signed int simmediate:10; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm_i_format { /* Immediate format (addi, lw, ...) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int rs:5; + signed int simmediate:16; +}; + +/* MIPS16e */ + +struct rr { + unsigned int opcode:5; + unsigned int rx:3; + unsigned int nd:1; + unsigned int l:1; + unsigned int ra:1; + unsigned int func:5; +}; + +struct jal { + unsigned int opcode:5; + unsigned int x:1; + unsigned int imm20_16:5; + signed int imm25_21:5; + /* unsigned int imm20_15:0; here is only first 16bits in first HW */ +}; + +struct i64 { + unsigned int opcode:5; + unsigned int func:3; + unsigned int imm:8; +}; + +struct ri64 { + unsigned int opcode:5; + unsigned int func:3; + unsigned int ry:3; + unsigned int imm:5; +}; + +struct ri { + unsigned int opcode:5; + unsigned int rx:3; + unsigned int imm:8; +}; + +struct rri { + unsigned int opcode:5; + unsigned int rx:3; + unsigned int ry:3; + unsigned int imm:5; +}; + +struct i8 { + unsigned int opcode:5; + unsigned int func:3; + unsigned int imm:8; +}; + +struct mm_m_format { + unsigned int opcode:6; + unsigned int rd:5; + unsigned int base:5; + unsigned int func:4; + signed int simmediate:12; +}; + +struct mm_x_format { + unsigned int opcode:6; + unsigned int index:5; + unsigned int base:5; + unsigned int rd:5; + unsigned int func:11; +}; + +struct mm16_m_format { + unsigned int opcode:6; + unsigned int func:4; + unsigned int rlist:2; + unsigned int imm:4; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm16_rb_format { + unsigned int opcode:6; + unsigned int rt:3; + unsigned int base:3; + signed int simmediate:4; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm16_r5_format { + unsigned int opcode:6; + unsigned int rt:5; + signed int simmediate:5; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm16_r3_format { + unsigned int opcode:6; + unsigned int rt:3; + signed int simmediate:7; + unsigned int duplicate:16; /* a copy of the instr */ +}; + #elif defined(__MIPSEL__) struct j_format { /* Jump format */ @@ -340,6 +560,225 @@ struct b_format { /* BREAK and SYSCALL */ unsigned int opcode:6; }; +struct fb_format { /* FPU branch format */ + unsigned int simmediate:16; + unsigned int flag:2; + unsigned int cc:3; + unsigned int bc:5; + unsigned int opcode:6; +}; + +struct fp0_format { /* FPU multipy and add format (MIPS32) */ + unsigned int func:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fmt:5; + unsigned int opcode:6; +}; + +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ + unsigned int func:6; + unsigned int op:2; + unsigned int fmt:3; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int opcode:6; +}; + +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ + unsigned int func:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int rt:5; + unsigned int op:5; + unsigned int opcode:6; +}; + +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ + unsigned int func:6; + unsigned int op:8; + unsigned int fmt:2; + unsigned int fs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ + unsigned int func:6; + unsigned int op:3; + unsigned int fmt:2; + unsigned int zero:2; + unsigned int cc:3; + unsigned int fs:5; + unsigned int fd:5; + unsigned int opcode:6; +}; + +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ + unsigned int func:6; + unsigned int op:7; + unsigned int fmt:3; + unsigned int fs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ + unsigned int func:6; + unsigned int cond:4; + unsigned int fmt:3; + unsigned int cc:3; + unsigned int fs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ + unsigned int func:6; + unsigned int op:5; + unsigned int fd:5; + unsigned int base:5; + unsigned int index:5; + unsigned int opcode:6; +}; + +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ + unsigned int func:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fr:5; + unsigned int opcode:6; +}; + +struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ + unsigned int func:6; + unsigned int fr:5; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int opcode:6; +}; + +struct mm16b1_format { /* microMIPS 16-bit branch format */ + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:7; + unsigned int rs:3; + unsigned int opcode:6; +}; + +struct mm16b0_format { /* microMIPS 16-bit branch format */ + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:10; + unsigned int opcode:6; +}; + +struct mm_i_format { /* Immediate format */ + signed int simmediate:16; + unsigned int rs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +/* MIPS16e */ + +struct rr { + unsigned int func:5; + unsigned int ra:1; + unsigned int l:1; + unsigned int nd:1; + unsigned int rx:3; + unsigned int opcode:5; +}; + +struct jal { + /* unsigned int imm20_15:0; here is only first 16bits in first HW */ + signed int imm25_21:5; + unsigned int imm20_16:5; + unsigned int x:1; + unsigned int opcode:5; +}; + +struct i64 { + unsigned int imm:8; + unsigned int func:3; + unsigned int opcode:5; +}; + +struct ri64 { + unsigned int imm:5; + unsigned int ry:3; + unsigned int func:3; + unsigned int opcode:5; +}; + +struct ri { + unsigned int imm:8; + unsigned int rx:3; + unsigned int opcode:5; +}; + +struct rri { + unsigned int imm:5; + unsigned int ry:3; + unsigned int rx:3; + unsigned int opcode:5; +}; + +struct i8 { + unsigned int imm:8; + unsigned int func:3; + unsigned int opcode:5; +}; + +struct mm_m_format { + signed int simmediate:12; + unsigned int func:4; + unsigned int base:5; + unsigned int rd:5; + unsigned int opcode:6; +}; + +struct mm_x_format { + unsigned int func:11; + unsigned int rd:5; + unsigned int base:5; + unsigned int index:5; + unsigned int opcode:6; +}; + +struct mm16_m_format { + unsigned int duplicate:16; /* a copy of the instr */ + unsigned int imm:4; + unsigned int rlist:2; + unsigned int func:4; + unsigned int opcode:6; +}; + +struct mm16_rb_format { + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:4; + unsigned int base:3; + unsigned int rt:3; + unsigned int opcode:6; +}; + +struct mm16_r5_format { + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm16_r3_format { + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:7; + unsigned int rt:3; + unsigned int opcode:6; +}; + #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" #endif @@ -356,6 +795,26 @@ union mips_instruction { struct f_format f_format; struct ma_format ma_format; struct b_format b_format; + struct mm16b0_format mm16b0_format; + struct mm16b1_format mm16b1_format; + struct mm_i_format mm_i_format; + struct fb_format fb_format; + struct fp0_format fp0_format; + struct fp1_format fp1_format; + struct fp6_format fp6_format; + struct mm_fp0_format mm_fp0_format; + struct mm_fp1_format mm_fp1_format; + struct mm_fp2_format mm_fp2_format; + struct mm_fp3_format mm_fp3_format; + struct mm_fp4_format mm_fp4_format; + struct mm_fp5_format mm_fp5_format; + struct mm_fp6_format mm_fp6_format; + struct mm_m_format mm_m_format; + struct mm_x_format mm_x_format; + struct mm16_m_format mm16_m_format; + struct mm16_rb_format mm16_rb_format; + struct mm16_r3_format mm16_r3_format; + struct mm16_r5_format mm16_r5_format; }; /* HACHACHAHCAHC ... */ @@ -418,4 +877,316 @@ union mips_instruction { typedef unsigned int mips_instruction; +/* The following are for microMIPS mode */ +#define MM_16_OPCODE_SFT 10 +#define MM_NOP16 0x0c00 +#define MM_POOL32A_MINOR_MSK 0x3f +#define MM_POOL32A_MINOR_SFT 0x6 +#define MIPS32_COND_FC 0x30 + +/* + * Major opcodes; microMIPS mode. + */ +enum mm_major_op { + mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, + mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, + mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, + mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, + mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, + mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, + mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, + mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, + mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, + mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, + mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, + mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, + mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, + mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, + mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, + mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, +}; + +/* + * POOL32I minor opcodes. + */ +enum mm_32i_minor_op { + mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, + mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, + mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, + mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, + mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, + mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, + mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, + mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, + mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, +}; + +/* + * POOL32A minor opcodes. + */ +enum mm_32a_minor_op { + mm_sll32_op = 0x000, + mm_ins_op = 0x00c, + mm_ext_op = 0x02c, + mm_pool32axf_op = 0x03c, + mm_srl32_op = 0x040, + mm_sra_op = 0x080, + mm_rotr_op = 0x0c0, + mm_lwxs_op = 0x118, + mm_addu32_op = 0x150, + mm_subu32_op = 0x1d0, + mm_and_op = 0x250, + mm_or32_op = 0x290, + mm_xor32_op = 0x310, +}; + +/* + * POOL32B functions. + */ +enum mm_32b_func { + mm_lwc2_func = 0x0, + mm_lwp_func = 0x1, + mm_ldc2_func = 0x2, + mm_ldp_func = 0x4, + mm_lwm32_func = 0x5, + mm_cache_func = 0x6, + mm_ldm_func = 0x7, + mm_swc2_func = 0x8, + mm_swp_func = 0x9, + mm_sdc2_func = 0xa, + mm_sdp_func = 0xc, + mm_swm32_func = 0xd, + mm_sdm_func = 0xf, +}; + +/* + * POOL32C functions. + */ +enum mm_32c_func { + mm_pref_func = 0x2, + mm_ll_func = 0x3, + mm_swr_func = 0x9, + mm_sc_func = 0xb, + mm_lwu_func = 0xe, +}; + +/* + * POOL32AXF minor opcodes. + */ +enum mm_32axf_minor_op { + mm_mfc0_op = 0x003, + mm_mtc0_op = 0x00b, + mm_tlbp_op = 0x00d, + mm_jalr_op = 0x03c, + mm_tlbr_op = 0x04d, + mm_jalrhb_op = 0x07c, + mm_tlbwi_op = 0x08d, + mm_tlbwr_op = 0x0cd, + mm_jalrs_op = 0x13c, + mm_jalrshb_op = 0x17c, + mm_syscall_op = 0x22d, + mm_eret_op = 0x3cd, +}; + +/* + * POOL32F minor opcodes. + */ +enum mm_32f_minor_op { + mm_32f_00_op = 0x00, + mm_32f_01_op = 0x01, + mm_32f_02_op = 0x02, + mm_32f_10_op = 0x08, + mm_32f_11_op = 0x09, + mm_32f_12_op = 0x0a, + mm_32f_20_op = 0x10, + mm_32f_30_op = 0x18, + mm_32f_40_op = 0x20, + mm_32f_41_op = 0x21, + mm_32f_42_op = 0x22, + mm_32f_50_op = 0x28, + mm_32f_51_op = 0x29, + mm_32f_52_op = 0x2a, + mm_32f_60_op = 0x30, + mm_32f_70_op = 0x38, + mm_32f_73_op = 0x3b, + mm_32f_74_op = 0x3c, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_10_minor_op { + mm_lwxc1_op = 0x1, + mm_swxc1_op, + mm_ldxc1_op, + mm_sdxc1_op, + mm_luxc1_op, + mm_suxc1_op, +}; + +enum mm_32f_func { + mm_lwxc1_func = 0x048, + mm_swxc1_func = 0x088, + mm_ldxc1_func = 0x0c8, + mm_sdxc1_func = 0x108, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_40_minor_op { + mm_fmovf_op, + mm_fmovt_op, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_60_minor_op { + mm_fadd_op, + mm_fsub_op, + mm_fmul_op, + mm_fdiv_op, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_70_minor_op { + mm_fmovn_op, + mm_fmovz_op, +}; + +/* + * POOL32F secondary minor opcodes (POOL32FXF). + */ +enum mm_32f_73_minor_op { + mm_fmov0_op = 0x01, + mm_fcvtl_op = 0x04, + mm_movf0_op = 0x05, + mm_frsqrt_op = 0x08, + mm_ffloorl_op = 0x0c, + mm_fabs0_op = 0x0d, + mm_fcvtw_op = 0x24, + mm_movt0_op = 0x25, + mm_fsqrt_op = 0x28, + mm_ffloorw_op = 0x2c, + mm_fneg0_op = 0x2d, + mm_cfc1_op = 0x40, + mm_frecip_op = 0x48, + mm_fceill_op = 0x4c, + mm_fcvtd0_op = 0x4d, + mm_ctc1_op = 0x60, + mm_fceilw_op = 0x6c, + mm_fcvts0_op = 0x6d, + mm_mfc1_op = 0x80, + mm_fmov1_op = 0x81, + mm_movf1_op = 0x85, + mm_ftruncl_op = 0x8c, + mm_fabs1_op = 0x8d, + mm_mtc1_op = 0xa0, + mm_movt1_op = 0xa5, + mm_ftruncw_op = 0xac, + mm_fneg1_op = 0xad, + mm_froundl_op = 0xcc, + mm_fcvtd1_op = 0xcd, + mm_froundw_op = 0xec, + mm_fcvts1_op = 0xed, +}; + +/* + * POOL16C minor opcodes. + */ +enum mm_16c_minor_op { + mm_lwm16_op = 0x04, + mm_swm16_op = 0x05, + mm_jr16_op = 0x18, + mm_jrc_op = 0x1a, + mm_jalr16_op = 0x1c, + mm_jalrs16_op = 0x1e, +}; + +/* + * POOL16D minor opcodes. + */ +enum mm_16d_minor_op { + mm_addius5_func, + mm_addiusp_func, +}; + +struct decoded_instn { + mips_instruction insn; + mips_instruction next_insn; + int pc_inc; + int next_pc_inc; + int micro_mips_mode; +}; + +union mips16e_instruction { + unsigned int full:16; + struct rr rr; + struct jal jal; + struct i64 i64; + struct ri64 ri64; + struct ri ri; + struct rri rri; + struct i8 i8; +}; + +enum MIPS16e_ops { + MIPS16e_jal_op = 003, + MIPS16e_ld_op = 007, + MIPS16e_i8_op = 014, + MIPS16e_sd_op = 017, + MIPS16e_lb_op = 020, + MIPS16e_lh_op = 021, + MIPS16e_lwsp_op = 022, + MIPS16e_lw_op = 023, + MIPS16e_lbu_op = 024, + MIPS16e_lhu_op = 025, + MIPS16e_lwpc_op = 026, + MIPS16e_lwu_op = 027, + MIPS16e_sb_op = 030, + MIPS16e_sh_op = 031, + MIPS16e_swsp_op = 032, + MIPS16e_sw_op = 033, + MIPS16e_rr_op = 035, + MIPS16e_extend_op = 036, + MIPS16e_i64_op = 037, +}; + +enum MIPS16e_i64_func { + MIPS16e_ldsp_func, + MIPS16e_sdsp_func, + MIPS16e_sdrasp_func, + MIPS16e_dadjsp_func, + MIPS16e_ldpc_func, +}; + +enum MIPS16e_rr_func { + MIPS16e_jr_func, +}; + +enum MIPS6e_i8_func { + MIPS16e_swrasp_func = 02, +}; + +/* + * This functions returns 1 if the microMIPS instr is a 16 bit instr. + * Otherwise return 0. + */ +#define MIPS_ISA_MODE 01 +#define is16mode(regs) (regs->cp0_epc & MIPS_ISA_MODE) + +static inline int mm_is16bit(u16 instr) +{ + /* take LS 3 bits */ + u16 opcode_low = (instr >> MM_16_OPCODE_SFT) & 0x7; + + if (opcode_low >= 1 && opcode_low <= 3) + return 1; + else + return 0; +} + #endif /* _ASM_INST_H */ diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c new file mode 100644 index 0000000..f2b834a --- /dev/null +++ b/arch/mips/mm/uasm-micromips.c @@ -0,0 +1,194 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ + +#define RS_MASK 0x1f +#define RS_SH 16 +#define RT_MASK 0x1f +#define RT_SH 21 +#define SCIMM_MASK 0x3ff +#define SCIMM_SH 16 + +/* This macro sets the non-variable bits of an instruction. */ +#define M(a, b, c, d, e, f) \ + ((a) << OP_SH \ + | (b) << RT_SH \ + | (c) << RS_SH \ + | (d) << RD_SH \ + | (e) << RE_SH \ + | (f) << FUNC_SH) + +static struct insn insn_table[] __uasminitdata = { + { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD }, + { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD }, + { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_beql, 0, 0 }, + { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM }, + { insn_bgezl, 0, 0 }, + { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM }, + { insn_bltzl, 0, 0 }, + { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM }, + { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM }, + { insn_daddu, 0, 0 }, + { insn_daddiu, 0, 0 }, + { insn_dmfc0, 0, 0 }, + { insn_dmtc0, 0, 0 }, + { insn_dsll, 0, 0 }, + { insn_dsll32, 0, 0 }, + { insn_dsra, 0, 0 }, + { insn_dsrl, 0, 0 }, + { insn_dsrl32, 0, 0 }, + { insn_drotr, 0, 0 }, + { insn_drotr32, 0, 0 }, + { insn_dsubu, 0, 0 }, + { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 }, + { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE }, + { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE }, + { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS }, + { insn_ld, 0, 0 }, + { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM }, + { insn_lld, 0, 0 }, + { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM }, + { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, + { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, + { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, + { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM }, + { insn_rfe, 0, 0 }, + { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM }, + { insn_scd, 0, 0 }, + { insn_sd, 0, 0 }, + { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD }, + { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD }, + { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD }, + { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, + { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, + { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 }, + { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, + { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, + { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 }, + { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD }, + { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_dins, 0, 0 }, + { insn_dinsm, 0, 0 }, + { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM}, + { insn_bbit0, 0, 0 }, + { insn_bbit1, 0, 0 }, + { insn_lwx, 0, 0 }, + { insn_ldx, 0, 0 }, + { insn_invalid, 0, 0 } +}; + +#undef M + +static inline __uasminit u32 build_bimm(s32 arg) +{ + if(arg > 0xffff || arg < -0x10000) + printk(KERN_WARNING "Micro-assembler field overflow\n"); + + if(arg & 0x3) + printk(KERN_WARNING "Invalid micro-assembler branch target\n"); + + return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff); +} + +static inline __uasminit u32 build_jimm(u32 arg) +{ + if ((arg & ~(JIMM_MASK << 1)) - 1) + printk(KERN_WARNING "Micro-assembler field overflow\n"); + + return (arg >> 1) & JIMM_MASK; +} + +/* + * The order of opcode arguments is implicitly left to right, + * starting with RS and ending with FUNC or IMM. + */ +static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) +{ + struct insn *ip = NULL; + unsigned int i; + va_list ap; + u32 op; + + for (i = 0; insn_table[i].opcode != insn_invalid; i++) + if (insn_table[i].opcode == opc) { + ip = &insn_table[i]; + break; + } + + if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) + panic("Unsupported Micro-assembler instruction %d", opc); + + op = ip->match; + va_start(ap, opc); + if (ip->fields & RS) { + if (opc == insn_mfc0 || opc == insn_mtc0) + op |= build_rt(va_arg(ap, u32)); + else + op |= build_rs(va_arg(ap, u32)); + } + if (ip->fields & RT) { + if (opc == insn_mfc0 || opc == insn_mtc0) + op |= build_rs(va_arg(ap, u32)); + else + op |= build_rt(va_arg(ap, u32)); + } + if (ip->fields & RD) + op |= build_rd(va_arg(ap, u32)); + if (ip->fields & RE) + op |= build_re(va_arg(ap, u32)); + if (ip->fields & SIMM) + op |= build_simm(va_arg(ap, s32)); + if (ip->fields & UIMM) + op |= build_uimm(va_arg(ap, u32)); + if (ip->fields & BIMM) + op |= build_bimm(va_arg(ap, s32)); + if (ip->fields & JIMM) + op |= build_jimm(va_arg(ap, u32)); + if (ip->fields & FUNC) + op |= build_func(va_arg(ap, u32)); + if (ip->fields & SET) + op |= build_set(va_arg(ap, u32)); + if (ip->fields & SCIMM) + op |= build_scimm(va_arg(ap, u32)); + va_end(ap); + +#ifdef CONFIG_CPU_LITTLE_ENDIAN + **buf = ((op & 0xffff) << 16) | (op >> 16); +#else + **buf = op; +#endif + (*buf)++; +} + +static inline void __uasminit +__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) +{ + long laddr = (long)lab->addr; + long raddr = (long)rel->addr; + + switch (rel->type) { + case R_MIPS_PC16: +#ifdef CONFIG_CPU_LITTLE_ENDIAN + *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16); +#else + *rel->addr |= build_bimm(laddr - (raddr + 4)); +#endif + break; + + default: + panic("Unsupported Micro-assembler relocation %d", + rel->type); + } +} diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c new file mode 100644 index 0000000..e86334b --- /dev/null +++ b/arch/mips/mm/uasm-mips.c @@ -0,0 +1,178 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ + +#define RS_MASK 0x1f +#define RS_SH 21 +#define RT_MASK 0x1f +#define RT_SH 16 +#define SCIMM_MASK 0xfffff +#define SCIMM_SH 6 + +/* This macro sets the non-variable bits of an instruction. */ +#define M(a, b, c, d, e, f) \ + ((a) << OP_SH \ + | (b) << RS_SH \ + | (c) << RT_SH \ + | (d) << RD_SH \ + | (e) << RE_SH \ + | (f) << FUNC_SH) + +static struct insn insn_table[] __uasminitdata = { + { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, + { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, + { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, + { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, + { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, + { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, + { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, + { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, + { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, + { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, + { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, + { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, + { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, + { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, + { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, + { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, + { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, + { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, + { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, + { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, + { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, + { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, + { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, + { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, + { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, + { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, + { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, + { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, + { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, + { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, + { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, + { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, + { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, + { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, + { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, + { insn_invalid, 0, 0 } +}; + +#undef M + +static inline __uasminit u32 build_bimm(s32 arg) +{ + if(arg > 0x1ffff || arg < -0x20000) + printk(KERN_WARNING "Micro-assembler field overflow\n"); + + if(arg & 0x3) + printk(KERN_WARNING "Invalid micro-assembler branch target\n"); + + return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); +} + +static inline __uasminit u32 build_jimm(u32 arg) +{ + if(arg & ~(JIMM_MASK << 2)) + printk(KERN_WARNING "Micro-assembler field overflow\n"); + + return (arg >> 2) & JIMM_MASK; +} + +/* + * The order of opcode arguments is implicitly left to right, + * starting with RS and ending with FUNC or IMM. + */ +static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) +{ + struct insn *ip = NULL; + unsigned int i; + va_list ap; + u32 op; + + for (i = 0; insn_table[i].opcode != insn_invalid; i++) + if (insn_table[i].opcode == opc) { + ip = &insn_table[i]; + break; + } + + if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) + panic("Unsupported Micro-assembler instruction %d", opc); + + op = ip->match; + va_start(ap, opc); + if (ip->fields & RS) + op |= build_rs(va_arg(ap, u32)); + if (ip->fields & RT) + op |= build_rt(va_arg(ap, u32)); + if (ip->fields & RD) + op |= build_rd(va_arg(ap, u32)); + if (ip->fields & RE) + op |= build_re(va_arg(ap, u32)); + if (ip->fields & SIMM) + op |= build_simm(va_arg(ap, s32)); + if (ip->fields & UIMM) + op |= build_uimm(va_arg(ap, u32)); + if (ip->fields & BIMM) + op |= build_bimm(va_arg(ap, s32)); + if (ip->fields & JIMM) + op |= build_jimm(va_arg(ap, u32)); + if (ip->fields & FUNC) + op |= build_func(va_arg(ap, u32)); + if (ip->fields & SET) + op |= build_set(va_arg(ap, u32)); + if (ip->fields & SCIMM) + op |= build_scimm(va_arg(ap, u32)); + va_end(ap); + + **buf = op; + (*buf)++; +} + +static inline void __uasminit +__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) +{ + long laddr = (long)lab->addr; + long raddr = (long)rel->addr; + + switch (rel->type) { + case R_MIPS_PC16: + *rel->addr |= build_bimm(laddr - (raddr + 4)); + break; + + default: + panic("Unsupported Micro-assembler relocation %d", + rel->type); + } +} diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 39b8910..d3b01b90 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -10,6 +10,7 @@ * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer * Copyright (C) 2005, 2007 Maciej W. Rozycki * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include @@ -38,9 +39,18 @@ enum fields { #define OP_MASK 0x3f #define OP_SH 26 #define RS_MASK 0x1f -#define RS_SH 21 #define RT_MASK 0x1f +#ifdef CONFIG_CPU_MICROMIPS +#define RS_SH 16 +#define RT_SH 21 +#define SCIMM_MASK 0x3ff +#define SCIMM_SH 16 +#else +#define RS_SH 21 #define RT_SH 16 +#define SCIMM_MASK 0xfffff +#define SCIMM_SH 6 +#endif #define RD_MASK 0x1f #define RD_SH 11 #define RE_MASK 0x1f @@ -53,8 +63,6 @@ enum fields { #define FUNC_SH 0 #define SET_MASK 0x7 #define SET_SH 0 -#define SCIMM_MASK 0xfffff -#define SCIMM_SH 6 enum opcode { insn_invalid, @@ -77,217 +85,83 @@ struct insn { enum fields fields; }; -/* This macro sets the non-variable bits of an instruction. */ -#define M(a, b, c, d, e, f) \ - ((a) << OP_SH \ - | (b) << RS_SH \ - | (c) << RT_SH \ - | (d) << RD_SH \ - | (e) << RE_SH \ - | (f) << FUNC_SH) - -static struct insn insn_table[] __uasminitdata = { - { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, - { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, - { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, - { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, - { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, - { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, - { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, - { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, - { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, - { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, - { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, - { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, - { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, - { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, - { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, - { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, - { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, - { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, - { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, - { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, - { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, - { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, - { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, - { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, - { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, - { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, - { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, - { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, - { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, - { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, - { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, - { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, - { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, - { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, - { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, - { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, - { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, - { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, - { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, - { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, - { insn_invalid, 0, 0 } -}; - -#undef M - static inline __uasminit u32 build_rs(u32 arg) { - WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RS_MASK) + printk(KERN_WARNING "Micro-assembler RS field overflow\n"); return (arg & RS_MASK) << RS_SH; } static inline __uasminit u32 build_rt(u32 arg) { - WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RT_MASK) + printk(KERN_WARNING "Micro-assembler RT field overflow\n"); return (arg & RT_MASK) << RT_SH; } static inline __uasminit u32 build_rd(u32 arg) { - WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RD_MASK) + printk(KERN_WARNING "Micro-assembler RD field overflow\n"); return (arg & RD_MASK) << RD_SH; } static inline __uasminit u32 build_re(u32 arg) { - WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RE_MASK) + printk(KERN_WARNING "Micro-assembler RE field overflow\n"); return (arg & RE_MASK) << RE_SH; } static inline __uasminit u32 build_simm(s32 arg) { - WARN(arg > 0x7fff || arg < -0x8000, - KERN_WARNING "Micro-assembler field overflow\n"); + if (arg > 0x7fff || arg < -0x8000) + printk(KERN_WARNING "Micro-assembler SIMM field overflow\n"); return arg & 0xffff; } static inline __uasminit u32 build_uimm(u32 arg) { - WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~IMM_MASK) + printk(KERN_WARNING "Micro-assembler UIMM field overflow\n"); return arg & IMM_MASK; } -static inline __uasminit u32 build_bimm(s32 arg) -{ - WARN(arg > 0x1ffff || arg < -0x20000, - KERN_WARNING "Micro-assembler field overflow\n"); - - WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); - - return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); -} - -static inline __uasminit u32 build_jimm(u32 arg) -{ - WARN(arg & ~(JIMM_MASK << 2), - KERN_WARNING "Micro-assembler field overflow\n"); - - return (arg >> 2) & JIMM_MASK; -} - static inline __uasminit u32 build_scimm(u32 arg) { - WARN(arg & ~SCIMM_MASK, - KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~SCIMM_MASK) + printk(KERN_WARNING "Micro-assembler SCIMM field overflow\n"); return (arg & SCIMM_MASK) << SCIMM_SH; } static inline __uasminit u32 build_func(u32 arg) { - WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~FUNC_MASK) + printk(KERN_WARNING "Micro-assembler FUNC field overflow\n"); return arg & FUNC_MASK; } static inline __uasminit u32 build_set(u32 arg) { - WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~SET_MASK) + printk(KERN_WARNING "Micro-assembler SET field overflow\n"); return arg & SET_MASK; } -/* - * The order of opcode arguments is implicitly left to right, - * starting with RS and ending with FUNC or IMM. - */ -static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) -{ - struct insn *ip = NULL; - unsigned int i; - va_list ap; - u32 op; - - for (i = 0; insn_table[i].opcode != insn_invalid; i++) - if (insn_table[i].opcode == opc) { - ip = &insn_table[i]; - break; - } - - if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) - panic("Unsupported Micro-assembler instruction %d", opc); - - op = ip->match; - va_start(ap, opc); - if (ip->fields & RS) - op |= build_rs(va_arg(ap, u32)); - if (ip->fields & RT) - op |= build_rt(va_arg(ap, u32)); - if (ip->fields & RD) - op |= build_rd(va_arg(ap, u32)); - if (ip->fields & RE) - op |= build_re(va_arg(ap, u32)); - if (ip->fields & SIMM) - op |= build_simm(va_arg(ap, s32)); - if (ip->fields & UIMM) - op |= build_uimm(va_arg(ap, u32)); - if (ip->fields & BIMM) - op |= build_bimm(va_arg(ap, s32)); - if (ip->fields & JIMM) - op |= build_jimm(va_arg(ap, u32)); - if (ip->fields & FUNC) - op |= build_func(va_arg(ap, u32)); - if (ip->fields & SET) - op |= build_set(va_arg(ap, u32)); - if (ip->fields & SCIMM) - op |= build_scimm(va_arg(ap, u32)); - va_end(ap); - - **buf = op; - (*buf)++; -} +#ifdef CONFIG_CPU_MICROMIPS +#include "uasm-micromips.c" +#else +#include "uasm-mips.c" +#endif #define I_u1u2u3(op) \ Ip_u1u2u3(op) \ @@ -552,23 +426,6 @@ uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) } UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); -static inline void __uasminit -__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) -{ - long laddr = (long)lab->addr; - long raddr = (long)rel->addr; - - switch (rel->type) { - case R_MIPS_PC16: - *rel->addr |= build_bimm(laddr - (raddr + 4)); - break; - - default: - panic("Unsupported Micro-assembler relocation %d", - rel->type); - } -} - void __uasminit uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) { -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:06:33 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60307 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823732Ab2LGFFvujJVR (ORCPT ); Fri, 7 Dec 2012 06:05:51 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq89-0007MA-6E; Thu, 06 Dec 2012 23:05:45 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,02/13] MIPS: Whitespace clean-ups after microMIPS additions. Date: Thu, 6 Dec 2012 23:05:26 -0600 Message-Id: <1354856737-28678-3-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35213 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 14178 Lines: 453 From: "Steven J. Hill" Clean-up tabs, spaces, macros, etc. after adding in microMIPS instructions for the micro-assembler. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/inst.h | 134 +++++++++++++++++++------------------- arch/mips/include/asm/mipsregs.h | 40 +++++++----- arch/mips/kernel/proc.c | 1 + arch/mips/kernel/traps.c | 4 +- 4 files changed, 92 insertions(+), 87 deletions(-) diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index c76899f..2b2e0e3 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -262,7 +262,7 @@ struct ma_format { /* FPU multiply and add format (MIPS IV) */ unsigned int fmt : 2; }; -struct b_format { /* BREAK and SYSCALL */ +struct b_format { /* BREAK and SYSCALL */ unsigned int opcode:6; unsigned int code:20; unsigned int func:6; @@ -276,7 +276,7 @@ struct fb_format { /* FPU branch format */ unsigned int simmediate:16; }; -struct fp0_format { /* FPU multipy and add format (MIPS32) */ +struct fp0_format { /* FPU multipy and add format (MIPS32) */ unsigned int opcode:6; unsigned int fmt:5; unsigned int ft:5; @@ -285,7 +285,7 @@ struct fp0_format { /* FPU multipy and add format (MIPS32) */ unsigned int func:6; }; -struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ unsigned int opcode:6; unsigned int ft:5; unsigned int fs:5; @@ -295,7 +295,7 @@ struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ unsigned int func:6; }; -struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ unsigned int opcode:6; unsigned int op:5; unsigned int rt:5; @@ -304,7 +304,7 @@ struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ unsigned int func:6; }; -struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ unsigned int opcode:6; unsigned int rt:5; unsigned int fs:5; @@ -313,7 +313,7 @@ struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ unsigned int func:6; }; -struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ unsigned int opcode:6; unsigned int fd:5; unsigned int fs:5; @@ -324,7 +324,7 @@ struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ unsigned int func:6; }; -struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ unsigned int opcode:6; unsigned int rt:5; unsigned int fs:5; @@ -333,7 +333,7 @@ struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ unsigned int func:6; }; -struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ unsigned int opcode:6; unsigned int rt:5; unsigned int fs:5; @@ -343,7 +343,7 @@ struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ unsigned int func:6; }; -struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ unsigned int opcode:6; unsigned int index:5; unsigned int base:5; @@ -370,20 +370,20 @@ struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ unsigned int func:6; }; -struct mm16b1_format { /* microMIPS 16-bit branch format */ +struct mm16b1_format { /* microMIPS 16-bit branch format */ unsigned int opcode:6; unsigned int rs:3; signed int simmediate:7; unsigned int duplicate:16; /* a copy of the instr */ }; -struct mm16b0_format { /* microMIPS 16-bit branch format */ +struct mm16b0_format { /* microMIPS 16-bit branch format */ unsigned int opcode:6; signed int simmediate:10; unsigned int duplicate:16; /* a copy of the instr */ }; -struct mm_i_format { /* Immediate format (addi, lw, ...) */ +struct mm_i_format { /* Immediate format (addi, lw, ...) */ unsigned int opcode:6; unsigned int rt:5; unsigned int rs:5; @@ -495,72 +495,72 @@ struct j_format { /* Jump format */ }; struct i_format { /* Immediate format */ - signed int simmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + signed int simmediate:16; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct u_format { /* Unsigned immediate format */ - unsigned int uimmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int uimmediate:16; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct c_format { /* Cache (>= R6000) format */ - unsigned int simmediate : 16; - unsigned int cache : 2; - unsigned int c_op : 3; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int simmediate:16; + unsigned int cache:2; + unsigned int c_op:3; + unsigned int rs:5; + unsigned int opcode:6; }; struct r_format { /* Register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct p_format { /* Performance counter format (R10000) */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct f_format { /* FPU register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int fmt : 4; - unsigned int : 1; - unsigned int opcode : 6; + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int fmt:4; + unsigned int:1; + unsigned int opcode:6; }; -struct ma_format { /* FPU multiply and add format (MIPS IV) */ - unsigned int fmt : 2; - unsigned int func : 4; - unsigned int fd : 5; - unsigned int fs : 5; - unsigned int ft : 5; - unsigned int fr : 5; - unsigned int opcode : 6; +struct ma_format { /* FPU multipy and add format (MIPS IV) */ + unsigned int fmt:2; + unsigned int func:4; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fr:5; + unsigned int opcode:6; }; -struct b_format { /* BREAK and SYSCALL */ +struct b_format { /* BREAK and SYSCALL */ unsigned int func:6; unsigned int code:20; unsigned int opcode:6; }; -struct fb_format { /* FPU branch format */ +struct fb_format { /* FPU branch format */ unsigned int simmediate:16; unsigned int flag:2; unsigned int cc:3; @@ -568,7 +568,7 @@ struct fb_format { /* FPU branch format */ unsigned int opcode:6; }; -struct fp0_format { /* FPU multipy and add format (MIPS32) */ +struct fp0_format { /* FPU multipy and add format (MIPS32) */ unsigned int func:6; unsigned int fd:5; unsigned int fs:5; @@ -577,7 +577,7 @@ struct fp0_format { /* FPU multipy and add format (MIPS32) */ unsigned int opcode:6; }; -struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ unsigned int func:6; unsigned int op:2; unsigned int fmt:3; @@ -587,7 +587,7 @@ struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ unsigned int opcode:6; }; -struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ unsigned int func:6; unsigned int fd:5; unsigned int fs:5; @@ -596,7 +596,7 @@ struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ unsigned int opcode:6; }; -struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ unsigned int func:6; unsigned int op:8; unsigned int fmt:2; @@ -605,7 +605,7 @@ struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ unsigned int opcode:6; }; -struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ unsigned int func:6; unsigned int op:3; unsigned int fmt:2; @@ -616,7 +616,7 @@ struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ unsigned int opcode:6; }; -struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ unsigned int func:6; unsigned int op:7; unsigned int fmt:3; @@ -625,7 +625,7 @@ struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ unsigned int opcode:6; }; -struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ unsigned int func:6; unsigned int cond:4; unsigned int fmt:3; @@ -635,7 +635,7 @@ struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ unsigned int opcode:6; }; -struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ unsigned int func:6; unsigned int op:5; unsigned int fd:5; @@ -644,7 +644,7 @@ struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ unsigned int opcode:6; }; -struct fp6_format { /* FPU madd and msub format (MIPS IV) */ +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ unsigned int func:6; unsigned int fd:5; unsigned int fs:5; @@ -653,7 +653,7 @@ struct fp6_format { /* FPU madd and msub format (MIPS IV) */ unsigned int opcode:6; }; -struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ +struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ unsigned int func:6; unsigned int fr:5; unsigned int fd:5; @@ -662,20 +662,20 @@ struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ unsigned int opcode:6; }; -struct mm16b1_format { /* microMIPS 16-bit branch format */ +struct mm16b1_format { /* microMIPS 16-bit branch format */ unsigned int duplicate:16; /* a copy of the instr */ signed int simmediate:7; unsigned int rs:3; unsigned int opcode:6; }; -struct mm16b0_format { /* microMIPS 16-bit branch format */ +struct mm16b0_format { /* microMIPS 16-bit branch format */ unsigned int duplicate:16; /* a copy of the instr */ signed int simmediate:10; unsigned int opcode:6; }; -struct mm_i_format { /* Immediate format */ +struct mm_i_format { /* Immediate format */ signed int simmediate:16; unsigned int rs:5; unsigned int rt:5; diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 0c0e4a6..4b55a5a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1151,17 +1151,21 @@ do { \ /* * Macros to access the floating point coprocessor control registers */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) +#define read_32bit_cp1_register(source) \ +({ \ + int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set reorder \n" \ + " # gas fails to assemble cfc1 for some archs, \n" \ + " # like Octeon. \n" \ + " .set mips1 \n" \ + " cfc1 %0,"STR(source)" \n" \ + " .set pop \n" \ + : "=r" (__res)); \ + __res; \ +}) #ifdef HAVE_AS_DSP #define rddsp(mask) \ @@ -1298,12 +1302,12 @@ do { \ unsigned int __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ : "=r" (__res) \ : "i" (mask)); \ __res; \ @@ -1318,7 +1322,7 @@ do { \ " # wrdsp $1, %x1 \n" \ " .word 0x7c2004f8 | (%x1 << 11) \n" \ " .set pop \n" \ - : \ + : \ : "r" (val), "i" (mask)); \ } while (0) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 07dff54..239ae03 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -73,6 +73,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_has_dsp) seq_printf(m, "%s", " dsp"); if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); + if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); seq_printf(m, "\n"); seq_printf(m, "shadow register sets\t: %d\n", diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 9260986..cc7f4cc 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -514,7 +514,7 @@ static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); if ((unsigned long)vaddr & 3) return SIGBUS; @@ -554,7 +554,7 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); reg = (opcode & RT) >> 16; if ((unsigned long)vaddr & 3) -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:06:56 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60310 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823763Ab2LGFFwpirV1 (ORCPT ); Fri, 7 Dec 2012 06:05:52 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq89-0007MA-O8; Thu, 06 Dec 2012 23:05:45 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, Leonid Yegoshin Subject: [PATCH v99,03/13] MIPS: microMIPS: Floating point support for 16-bit instructions. Date: Thu, 6 Dec 2012 23:05:27 -0600 Message-Id: <1354856737-28678-4-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35214 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 33776 Lines: 1020 From: "Steven J. Hill" Add logic needed to do floating point emulation when in microMIPS or MIPS16e modes. Signed-off-by: Leonid Yegoshin Signed-off-by: Steven J. Hill --- arch/mips/include/asm/fpu_emulator.h | 7 + arch/mips/kernel/traps.c | 2 +- arch/mips/math-emu/cp1emu.c | 766 ++++++++++++++++++++++++++++++---- arch/mips/math-emu/dsemul.c | 40 +- 4 files changed, 718 insertions(+), 97 deletions(-) diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 3b40927..67d5028 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -54,6 +54,12 @@ do { \ extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); extern int do_dsemulret(struct pt_regs *xcp); +extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, + struct mips_fpu_struct *ctx, int has_fpu, + void *__user *fault_addr); +int process_fpemu_return(int sig, void __user *fault_addr); +int mm_isBranchInstr(struct pt_regs *regs, struct decoded_instn dec_insn, + unsigned long *contpc); /* * Instruction inserted following the badinst to further tag the sequence @@ -64,5 +70,6 @@ extern int do_dsemulret(struct pt_regs *xcp); * Break instruction with special math emu break code set */ #define BREAK_MATH (0x0000000d | (BRK_MEMU << 16)) +#define MM_BREAK_MATH (0x00000007 | (MM_BRK_MEMU << 16)) #endif /* _ASM_FPU_EMULATOR_H */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index cc7f4cc..c0dc176 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -671,7 +671,7 @@ asmlinkage void do_ov(struct pt_regs *regs) force_sig_info(SIGFPE, &info, current); } -static int process_fpemu_return(int sig, void __user *fault_addr) +int process_fpemu_return(int sig, void __user *fault_addr) { if (sig == SIGSEGV || sig == SIGBUS) { struct siginfo si = {0}; diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 47c77e7..d0fd160 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -110,6 +111,477 @@ static const unsigned int fpucondbit[8] = { }; #endif +/* convert 16-bit register encoding to 32-bit register encoding */ +static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; + +/* convert micro_mips to mips32 format */ +static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; +static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; +static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; +static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; + +/* + * This functions translates a 32 bit micro_mips instr into a 32 bit mips32 instr. + * It return 0 or SIGILL. + */ +static int micro_mips32_to_mips32(union mips_instruction *insn_ptr) +{ + union mips_instruction insn = *insn_ptr; + union mips_instruction mips32_insn = insn; /* assume they are the same */ + int func; + int fmt; + int op; + + switch (insn.mm_i_format.opcode) { + case mm_ldc132_op: + mips32_insn.mm_i_format.opcode = ldc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_lwc132_op: + mips32_insn.mm_i_format.opcode = lwc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_sdc132_op: + mips32_insn.mm_i_format.opcode = sdc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_swc132_op: + mips32_insn.mm_i_format.opcode = swc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_pool32i_op: + /* NOTE: offset is << by 1 if in micro_mips mode */ + if ((insn.mm_i_format.rt == mm_bc1f_op) || (insn.mm_i_format.rt == mm_bc1t_op)) { + mips32_insn.fb_format.opcode = cop1_op; + mips32_insn.fb_format.bc = bc_op; + mips32_insn.fb_format.flag = (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; + } else + return SIGILL; + break; + case mm_pool32f_op: + switch (insn.mm_fp0_format.func) { + case mm_32f_01_op: + case mm_32f_11_op: + case mm_32f_02_op: + case mm_32f_12_op: + case mm_32f_41_op: + case mm_32f_51_op: + case mm_32f_42_op: + case mm_32f_52_op: + op = insn.mm_fp0_format.func; + if (op == mm_32f_01_op) + func = madd_s_op; + else if (op == mm_32f_11_op) + func = madd_d_op; + else if (op == mm_32f_02_op) + func = nmadd_s_op; + else if (op == mm_32f_12_op) + func = nmadd_d_op; + else if (op == mm_32f_41_op) + func = msub_s_op; + else if (op == mm_32f_51_op) + func = msub_d_op; + else if (op == mm_32f_42_op) + func = nmsub_s_op; + else + func = nmsub_d_op; + mips32_insn.fp6_format.opcode = cop1x_op; + mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; + mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; + mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; + mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; + mips32_insn.fp6_format.func = func; + break; + case mm_32f_10_op: + func = -1; /* set to invalid value */ + op = insn.mm_fp5_format.op & 0x7; + if (op == mm_ldxc1_op) + func = ldxc1_op; + else if (op == mm_sdxc1_op) + func = sdxc1_op; + else if (op == mm_lwxc1_op) + func = lwxc1_op; + else if (op == mm_swxc1_op) + func = swxc1_op; + + if (func != -1) { + mips32_insn.r_format.opcode = cop1x_op; + mips32_insn.r_format.rs = insn.mm_fp5_format.base; + mips32_insn.r_format.rt = insn.mm_fp5_format.index; + mips32_insn.r_format.rd = 0; + mips32_insn.r_format.re = insn.mm_fp5_format.fd; + mips32_insn.r_format.func = func; + } else + return SIGILL; + break; + case mm_32f_40_op: + op = -1; /* set to invalid value */ + if (insn.mm_fp2_format.op == mm_fmovt_op) + op = 1; + else if (insn.mm_fp2_format.op == mm_fmovf_op) + op = 0; + if (op != -1) { + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp2_format.fmt]; + mips32_insn.fp0_format.ft = (insn.mm_fp2_format.cc<<2) + op; + mips32_insn.fp0_format.fs = insn.mm_fp2_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp2_format.fd; + mips32_insn.fp0_format.func = fmovc_op; + } else + return SIGILL; + break; + case mm_32f_60_op: + func = -1; /* set to invalid value */ + if (insn.mm_fp0_format.op == mm_fadd_op) + func = fadd_op; + else if (insn.mm_fp0_format.op == mm_fsub_op) + func = fsub_op; + else if (insn.mm_fp0_format.op == mm_fmul_op) + func = fmul_op; + else if (insn.mm_fp0_format.op == mm_fdiv_op) + func = fdiv_op; + if (func != -1) { + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp0_format.fmt]; + mips32_insn.fp0_format.ft = insn.mm_fp0_format.ft; + mips32_insn.fp0_format.fs = insn.mm_fp0_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp0_format.fd; + mips32_insn.fp0_format.func = func; + } else + return SIGILL; + break; + case mm_32f_70_op: + func = -1; /* set to invalid value */ + if (insn.mm_fp0_format.op == mm_fmovn_op) + func = fmovn_op; + else if (insn.mm_fp0_format.op == mm_fmovz_op) + func = fmovz_op; + if (func != -1) { + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp0_format.fmt]; + mips32_insn.fp0_format.ft = insn.mm_fp0_format.ft; + mips32_insn.fp0_format.fs = insn.mm_fp0_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp0_format.fd; + mips32_insn.fp0_format.func = func; + } else + return SIGILL; + break; + case mm_32f_73_op: /* POOL32FXF */ + switch (insn.mm_fp1_format.op) { + case mm_movf0_op: + case mm_movf1_op: + case mm_movt0_op: + case mm_movt1_op: + if ((insn.mm_fp1_format.op & 0x7f) == mm_movf0_op) + op = 0; + else + op = 1; + mips32_insn.r_format.opcode = spec_op; + mips32_insn.r_format.rs = insn.mm_fp4_format.fs; + mips32_insn.r_format.rt = (insn.mm_fp4_format.cc<<2) + op; + mips32_insn.r_format.rd = insn.mm_fp4_format.rt; + mips32_insn.r_format.re = 0; + mips32_insn.r_format.func = movc_op; + break; + case mm_fcvtd0_op: + case mm_fcvtd1_op: + case mm_fcvts0_op: + case mm_fcvts1_op: + if ((insn.mm_fp1_format.op & 0x7f) == mm_fcvtd0_op) { + func = fcvtd_op; + fmt = swl_format[insn.mm_fp3_format.fmt]; + } else { + func = fcvts_op; + fmt = dwl_format[insn.mm_fp3_format.fmt]; + } + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = fmt; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp3_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp3_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_fmov0_op: + case mm_fmov1_op: + case mm_fabs0_op: + case mm_fabs1_op: + case mm_fneg0_op: + case mm_fneg1_op: + if ((insn.mm_fp1_format.op & 0x7f) == mm_fmov0_op) + func = fmov_op; + else if ((insn.mm_fp1_format.op & 0x7f) == mm_fabs0_op) + func = fabs_op; + else + func = fneg_op; + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp3_format.fmt]; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp3_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp3_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_ffloorl_op: + case mm_ffloorw_op: + case mm_fceill_op: + case mm_fceilw_op: + case mm_ftruncl_op: + case mm_ftruncw_op: + case mm_froundl_op: + case mm_froundw_op: + case mm_fcvtl_op: + case mm_fcvtw_op: + if (insn.mm_fp1_format.op == mm_ffloorl_op) + func = ffloorl_op; + else if (insn.mm_fp1_format.op == mm_ffloorw_op) + func = ffloor_op; + else if (insn.mm_fp1_format.op == mm_fceill_op) + func = fceill_op; + else if (insn.mm_fp1_format.op == mm_fceilw_op) + func = fceil_op; + else if (insn.mm_fp1_format.op == mm_ftruncl_op) + func = ftruncl_op; + else if (insn.mm_fp1_format.op == mm_ftruncw_op) + func = ftrunc_op; + else if (insn.mm_fp1_format.op == mm_froundl_op) + func = froundl_op; + else if (insn.mm_fp1_format.op == mm_froundw_op) + func = fround_op; + else if (insn.mm_fp1_format.op == mm_fcvtl_op) + func = fcvtl_op; + else + func = fcvtw_op; + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sd_format[insn.mm_fp1_format.fmt]; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp1_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp1_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_frsqrt_op: + case mm_fsqrt_op: + case mm_frecip_op: + if (insn.mm_fp1_format.op == mm_frsqrt_op) + func = frsqrt_op; + else if (insn.mm_fp1_format.op == mm_fsqrt_op) + func = fsqrt_op; + else + func = frecip_op; + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp1_format.fmt]; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp1_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp1_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_mfc1_op: + case mm_mtc1_op: + case mm_cfc1_op: + case mm_ctc1_op: + if (insn.mm_fp1_format.op == mm_mfc1_op) + op = mfc_op; + else if (insn.mm_fp1_format.op == mm_mtc1_op) + op = mtc_op; + else if (insn.mm_fp1_format.op == mm_cfc1_op) + op = cfc_op; + else + op = ctc_op; + mips32_insn.fp1_format.opcode = cop1_op; + mips32_insn.fp1_format.op = op; + mips32_insn.fp1_format.rt = insn.mm_fp1_format.rt; + mips32_insn.fp1_format.fs = insn.mm_fp1_format.fs; + mips32_insn.fp1_format.fd = 0; + mips32_insn.fp1_format.func = 0; + break; + default: + return SIGILL; + break; + } + break; + case mm_32f_74_op: /* c.cond.fmt */ + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp4_format.fmt]; + mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; + mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc<<2; + mips32_insn.fp0_format.func = insn.mm_fp4_format.cond | MIPS32_COND_FC; + break; + default: + return SIGILL; + break; + } + break; + default: + return SIGILL; + break; + } + + *insn_ptr = mips32_insn; + return 0; +} + +/* micro_mips version of isBranchInstr() */ +int mm_isBranchInstr(struct pt_regs *regs, struct decoded_instn dec_insn, + unsigned long *contpc) +{ + union mips_instruction insn = (union mips_instruction)dec_insn.insn; + int bc_false = 0; + unsigned int fcr31; + unsigned int bit; + + /* NOTE: for 16-bit instructions, they are duplicated and stored as a 32-bit value. */ + switch (insn.mm_i_format.opcode) { + case mm_pool32a_op: + if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MSK) == mm_pool32axf_op) { + switch (insn.mm_i_format.simmediate >> MM_POOL32A_MINOR_SFT) { + case mm_jalr_op: + case mm_jalrhb_op: + case mm_jalrs_op: + case mm_jalrshb_op: + if (insn.mm_i_format.rt != 0) /* not a mm_jr_op */ + regs->regs[insn.mm_i_format.rt] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + *contpc = regs->regs[insn.mm_i_format.rs]; + return 1; + break; + } + } + break; + case mm_pool32i_op: + switch (insn.mm_i_format.rt) { + case mm_bltzals_op: + case mm_bltzal_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_bltz_op: + if ((long)regs->regs[insn.mm_i_format.rs] < 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bgezals_op: + case mm_bgezal_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_bgez_op: + if ((long)regs->regs[insn.mm_i_format.rs] >= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_blez_op: + if ((long)regs->regs[insn.mm_i_format.rs] <= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bgtz_op: + if ((long)regs->regs[insn.mm_i_format.rs] <= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bc2f_op: + case mm_bc1f_op: + bc_false = 1; + /* Fall through */ + case mm_bc2t_op: + case mm_bc1t_op: + preempt_disable(); + if (is_fpu_owner()) + asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); + else + fcr31 = current->thread.fpu.fcr31; + preempt_enable(); + + if (bc_false) + fcr31 = ~fcr31; + + bit = (insn.mm_i_format.rs >> 2); + bit += (bit != 0); + bit += 23; + if (fcr31 & (1 << bit)) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + } + break; + case mm_pool16c_op: + switch (insn.mm_i_format.rt) { + case mm_jalr16_op: + case mm_jalrs16_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_jr16_op: + *contpc = regs->regs[insn.mm_i_format.rs]; + return 1; + break; + } + break; + case mm_beqz16_op: + if ((long)regs->regs[reg16to32map[insn.mm16b1_format.rs]] == 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm16b1_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bnez16_op: + if ((long)regs->regs[reg16to32map[insn.mm16b1_format.rs]] != 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm16b1_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_b16_op: + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm16b0_format.simmediate << 1); + return 1; + break; + case mm_beq32_op: + if (regs->regs[insn.mm_i_format.rs] == regs->regs[insn.mm_i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bne32_op: + if (regs->regs[insn.mm_i_format.rs] != regs->regs[insn.mm_i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_jalx32_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + + dec_insn.next_pc_inc; + *contpc = regs->cp0_epc + dec_insn.pc_inc; + *contpc >>= 28; + *contpc <<= 28; + *contpc |= (insn.j_format.target << 2); + return 1; + break; + case mm_jals32_op: + case mm_jal32_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_j32_op: + *contpc = regs->cp0_epc + dec_insn.pc_inc; + *contpc >>= 27; + *contpc <<= 27; + *contpc |= (insn.j_format.target << 1); + *contpc |= MIPS_ISA_MODE; + return 1; + break; + } + return 0; +} /* * Redundant with logic already in kernel/branch.c, @@ -117,53 +589,134 @@ static const unsigned int fpucondbit[8] = { * a single subroutine should be used across both * modules. */ -static int isBranchInstr(mips_instruction * i) +static int isBranchInstr(struct pt_regs *regs, struct decoded_instn dec_insn, unsigned long *contpc) { - switch (MIPSInst_OPCODE(*i)) { + union mips_instruction insn = (union mips_instruction)dec_insn.insn; + unsigned int fcr31; + unsigned int bit = 0; + + switch (insn.i_format.opcode) { case spec_op: - switch (MIPSInst_FUNC(*i)) { + switch (insn.r_format.func) { case jalr_op: + regs->regs[insn.r_format.rd] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ case jr_op: + *contpc = regs->regs[insn.r_format.rs]; return 1; + break; } break; - case bcond_op: - switch (MIPSInst_RT(*i)) { + switch (insn.i_format.rt) { + case bltzal_op: + case bltzall_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ case bltz_op: - case bgez_op: case bltzl_op: - case bgezl_op: - case bltzal_op: + if ((long)regs->regs[insn.i_format.rs] < 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; case bgezal_op: - case bltzall_op: case bgezall_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case bgez_op: + case bgezl_op: + if ((long)regs->regs[insn.i_format.rs] >= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; + break; } break; - - case j_op: - case jal_op: case jalx_op: + bit = MIPS_ISA_MODE; + case jal_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case j_op: + *contpc = regs->cp0_epc + dec_insn.pc_inc; + *contpc >>= 28; + *contpc <<= 28; + *contpc |= (insn.j_format.target << 2); + /* set micro_mips mode bit: xor for jalx. LY22 */ + *contpc ^= bit; + return 1; + break; case beq_op: - case bne_op: - case blez_op: - case bgtz_op: case beql_op: + if (regs->regs[insn.i_format.rs] == regs->regs[insn.i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case bne_op: case bnel_op: + if (regs->regs[insn.i_format.rs] != regs->regs[insn.i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case blez_op: case blezl_op: + if ((long)regs->regs[insn.i_format.rs] <= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case bgtz_op: case bgtzl_op: + if ((long)regs->regs[insn.i_format.rs] > 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - + break; case cop0_op: case cop1_op: case cop2_op: case cop1x_op: - if (MIPSInst_RS(*i) == bc_op) - return 1; + if (insn.i_format.rs == bc_op) { + preempt_disable(); + if (is_fpu_owner()) + asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); + else + fcr31 = current->thread.fpu.fcr31; + preempt_enable(); + + bit = (insn.i_format.rt >> 2); + bit += (bit != 0); + bit += 23; + switch (insn.i_format.rt & 3) { + case 0: /* bc1f */ + case 2: /* bc1fl */ + if (~fcr31 & (1 << bit)) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case 1: /* bc1t */ + case 3: /* bc1tl */ + if (fcr31 & (1 << bit)) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + } /* end of inner switch-statement */ + } break; } - return 0; } @@ -210,26 +763,23 @@ static inline int cop1_64bit(struct pt_regs *xcp) */ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - void *__user *fault_addr) + struct decoded_instn dec_insn, void *__user *fault_addr) { mips_instruction ir; - unsigned long emulpc, contpc; + unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; unsigned int cond; - - if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGBUS; - } - if (__get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGSEGV; - } + int pc_inc; /* XXX NEC Vr54xx bug workaround */ - if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir)) - xcp->cp0_cause &= ~CAUSEF_BD; + if (xcp->cp0_cause & CAUSEF_BD) { + if (dec_insn.micro_mips_mode) { + if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) + xcp->cp0_cause &= ~CAUSEF_BD; + } else { + if (!isBranchInstr(xcp, dec_insn, &contpc)) + xcp->cp0_cause &= ~CAUSEF_BD; + } + } if (xcp->cp0_cause & CAUSEF_BD) { /* @@ -244,32 +794,27 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * Linux MIPS branch emulator operates on context, updating the * cp0_epc. */ - emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */ - if (__compute_return_epc(xcp) < 0) { -#ifdef CP1DBG - printk("failed to emulate branch at %p\n", - (void *) (xcp->cp0_epc)); -#endif - return SIGILL; - } - if (!access_ok(VERIFY_READ, emulpc, sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)emulpc; - return SIGBUS; - } - if (__get_user(ir, (mips_instruction __user *) emulpc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)emulpc; - return SIGSEGV; - } - /* __compute_return_epc() will have updated cp0_epc */ - contpc = xcp->cp0_epc; - /* In order not to confuse ptrace() et al, tweak context */ - xcp->cp0_epc = emulpc - 4; + /* NOTE: contpc is modified by isBranchInstr() if it is a branch instr */ + + ir = dec_insn.next_insn; /* process delay slot instr */ + pc_inc = dec_insn.next_pc_inc; } else { - emulpc = xcp->cp0_epc; - contpc = xcp->cp0_epc + 4; + ir = dec_insn.insn; /* process current instr */ + pc_inc = dec_insn.pc_inc; + } + + /* Since micro_mips FPU instructios are a subset of mips32 FPU instructions, */ + /* we want to convert micro_mips FPU instructions into mips32 instrunction so */ + /* that we could reuse all of the FPU emulation code. */ + /* NOTE: we can't do this for branch instructions since they are not a subset */ + /* ex: can't emulate a 16-bit aligned target address with a mips32 instn */ + if (dec_insn.micro_mips_mode) { + /* if next instn is a 16-bit instn then it can't be FPU instn */ + /* This could happen since this function can be called with non FPU instructions. */ + if ((pc_inc == 2) || + (micro_mips32_to_mips32((union mips_instruction *)&ir) == SIGILL)) + return SIGILL; } emul: @@ -474,22 +1019,30 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, /* branch taken: emulate dslot * instruction */ - xcp->cp0_epc += 4; - contpc = (xcp->cp0_epc + - (MIPSInst_SIMM(ir) << 2)); - - if (!access_ok(VERIFY_READ, xcp->cp0_epc, - sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGBUS; - } - if (__get_user(ir, - (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGSEGV; - } + xcp->cp0_epc += dec_insn.pc_inc; + + contpc = MIPSInst_SIMM(ir); + ir = dec_insn.next_insn; + if (dec_insn.micro_mips_mode) { + contpc = (xcp->cp0_epc + (contpc << 1)); + + /* if next instn is a 16-bit instn then it can't be FPU instn */ + if ((dec_insn.next_pc_inc == 2) || + (micro_mips32_to_mips32((union mips_instruction *)&ir) == SIGILL)) { + + /* since this instn will be put on the stack with 32-bit words */ + /* get around this problem by putting a NOP16 as the 2nd instn */ + if (dec_insn.next_pc_inc == 2) + ir = (ir & (~0xffff)) | MM_NOP16; + + /* + * Single step the non-cp1 + * instruction in the dslot + */ + return mips_dsemul(xcp, ir, contpc); + } + } else + contpc = (xcp->cp0_epc + (contpc << 2)); switch (MIPSInst_OPCODE(ir)) { case lwc1_op: @@ -525,8 +1078,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * branch likely nullifies * dslot if not taken */ - xcp->cp0_epc += 4; - contpc += 4; + xcp->cp0_epc += dec_insn.pc_inc; + contpc += dec_insn.pc_inc; /* * else continue & execute * dslot as normal insn @@ -1313,25 +1866,58 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu, void *__user *fault_addr) { unsigned long oldepc, prevepc; - mips_instruction insn; + struct decoded_instn dec_insn; + u16 instr[4]; + u16 *instr_ptr; int sig = 0; oldepc = xcp->cp0_epc; do { prevepc = xcp->cp0_epc; - if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGBUS; - } - if (__get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGSEGV; + if (is16mode(xcp) && cpu_has_mmips) { + /* get the next 2 micro_mips instn and decode them into 2 mips32 instn */ + if ((get_user(instr[0], (u16 __user *)(xcp->cp0_epc & ~MIPS_ISA_MODE))) || + (get_user(instr[1], (u16 __user *)((xcp->cp0_epc+2) & ~MIPS_ISA_MODE))) || + (get_user(instr[2], (u16 __user *)((xcp->cp0_epc+4) & ~MIPS_ISA_MODE))) || + (get_user(instr[3], (u16 __user *)((xcp->cp0_epc+6) & ~MIPS_ISA_MODE)))) { + MIPS_FPU_EMU_INC_STATS(errors); + return SIGBUS; + } + instr_ptr = instr; + /* get 1st instruction */ + if (mm_is16bit(*instr_ptr)) { + dec_insn.insn = (*instr_ptr << 16) | (*instr_ptr); /* duplicate the half-word */ + dec_insn.pc_inc = 2; /* 16 bit instr */ + instr_ptr += 1; + } else { + dec_insn.insn = (*instr_ptr << 16) | *(instr_ptr+1); + dec_insn.pc_inc = 4; /* 32 bit instr */ + instr_ptr += 2; + } + /* get 2nd instruction */ + if (mm_is16bit(*instr_ptr)) { + dec_insn.next_insn = (*instr_ptr << 16) | (*instr_ptr); /* duplicate the half-word */ + dec_insn.next_pc_inc = 2; /* 16 bit instr */ + } else { + dec_insn.next_insn = (*instr_ptr << 16) | *(instr_ptr+1); + dec_insn.next_pc_inc = 4; /* 32 bit instr */ + } + dec_insn.micro_mips_mode = 1; + } else { + if ((get_user(dec_insn.insn, (mips_instruction __user *) xcp->cp0_epc)) || + (get_user(dec_insn.next_insn, (mips_instruction __user *)(xcp->cp0_epc+4)))) { + MIPS_FPU_EMU_INC_STATS(errors); + return SIGBUS; + } + dec_insn.pc_inc = 4; + dec_insn.next_pc_inc = 4; + dec_insn.micro_mips_mode = 0; } - if (insn == 0) - xcp->cp0_epc += 4; /* skip nops */ + + if ((dec_insn.insn == 0) || + ((dec_insn.pc_inc == 2) && ((dec_insn.insn & 0xffff) == MM_NOP16))) + xcp->cp0_epc += dec_insn.pc_inc; /* skip nops */ else { /* * The 'ieee754_csr' is an alias of @@ -1341,7 +1927,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, */ /* convert to ieee library modes */ ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; - sig = cop1Emulate(xcp, ctx, fault_addr); + sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); /* revert to mips rounding mode */ ieee754_csr.rm = mips_rm[ieee754_csr.rm]; } @@ -1359,6 +1945,8 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, /* but if epc has advanced, then ignore it */ sig = 0; + /*if (sig == SIGILL) printk("Illegal micro_mips FPU instruction: 0x%x, 0x%x\n", dec_insn.insn, dec_insn.next_insn);*/ + return sig; } diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 384a3b0..67bf6d5 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -54,8 +54,15 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) extern asmlinkage void handle_dsemulret(void); struct emuframe __user *fr; int err; + int nop = 0; - if (ir == 0) { /* a nop is easy */ + if (regs->cp0_epc & 1) { + if ((ir >> 16) == MM_NOP16) + nop = 1; + } else if (ir == 0) + nop = 1; + + if (nop == 1) { /* a nop is easy */ regs->cp0_epc = cpc; regs->cp0_cause &= ~CAUSEF_BD; return 0; @@ -91,8 +98,17 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) return SIGBUS; - err = __put_user(ir, &fr->emul); - err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); + if (regs->cp0_epc & 1) { + err = __put_user(ir >> 16, (u16 __user *)(&fr->emul)); + err |= __put_user(ir & 0xffff, (u16 __user *)((long)(&fr->emul) + 2)); + err |= __put_user(MM_BREAK_MATH >> 16, (u16 __user *)(&fr->badinst)); + err |= __put_user(MM_BREAK_MATH & 0xffff, (u16 __user *)((long)(&fr->badinst) + 2)); + } else { + err = __put_user(ir, &fr->emul); + err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); + } + + /* NOTE: assume the 2nd instn is never executed => can leave as mips32 instr */ err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); err |= __put_user(cpc, &fr->epc); @@ -101,7 +117,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) return SIGBUS; } - regs->cp0_epc = (unsigned long) &fr->emul; + regs->cp0_epc = ((unsigned long) &fr->emul) | (regs->cp0_epc & 1); flush_cache_sigtramp((unsigned long)&fr->badinst); @@ -114,9 +130,14 @@ int do_dsemulret(struct pt_regs *xcp) unsigned long epc; u32 insn, cookie; int err = 0; + u32 break_math = BREAK_MATH; + u16 instr[2]; + + if (xcp->cp0_epc & 1) + break_math = MM_BREAK_MATH; fr = (struct emuframe __user *) - (xcp->cp0_epc - sizeof(mips_instruction)); + ((xcp->cp0_epc & (~1)) - sizeof(mips_instruction)); /* * If we can't even access the area, something is very wrong, but we'll @@ -131,10 +152,15 @@ int do_dsemulret(struct pt_regs *xcp) * - Is the instruction pointed to by the EPC an BREAK_MATH? * - Is the following memory word the BD_COOKIE? */ - err = __get_user(insn, &fr->badinst); + if (xcp->cp0_epc & 1) { + err = __get_user(instr[0], (u16 __user *)(&fr->badinst)); + err |= __get_user(instr[1], (u16 __user *)((long)(&fr->badinst) + 2)); + insn = (instr[0] << 16) | instr[1]; + } else + err = __get_user(insn, &fr->badinst); err |= __get_user(cookie, &fr->cookie); - if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { + if (unlikely(err || (insn != break_math) || (cookie != BD_COOKIE))) { MIPS_FPU_EMU_INC_STATS(errors); return 0; } -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:07:18 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60313 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824759Ab2LGFFxQkwAk (ORCPT ); Fri, 7 Dec 2012 06:05:53 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8A-0007MA-71; Thu, 06 Dec 2012 23:05:46 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,04/13] MIPS: microMIPS: Add support for exception handling. Date: Thu, 6 Dec 2012 23:05:28 -0600 Message-Id: <1354856737-28678-5-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35215 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 27053 Lines: 907 From: "Steven J. Hill" All exceptions must be taken in microMIPS mode, never in MIPS32R2 mode or the kernel falls apart. A few 'nop' instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mipsregs.h | 1 + arch/mips/include/asm/stackframe.h | 12 +- arch/mips/kernel/cpu-probe.c | 3 + arch/mips/kernel/genex.S | 74 ++++++--- arch/mips/kernel/scall32-o32.S | 9 ++ arch/mips/kernel/smtc-asm.S | 3 + arch/mips/kernel/traps.c | 290 ++++++++++++++++++++++++++---------- arch/mips/mm/tlbex.c | 21 +++ arch/mips/mti-sead3/sead3-init.c | 48 ++++++ 9 files changed, 354 insertions(+), 107 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 4b55a5a..5e9707e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -596,6 +596,7 @@ #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) +#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index cb41af5..335ce06 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -139,7 +139,7 @@ 1: move ra, k0 li k0, 3 mtc0 k0, $22 -#endif /* CONFIG_CPU_LOONGSON2F */ +#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */ #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -189,6 +189,7 @@ LONG_S $0, PT_R0(sp) mfc0 v1, CP0_STATUS LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) #ifdef CONFIG_MIPS_MT_SMTC /* * Ideally, these instructions would be shuffled in @@ -200,21 +201,20 @@ LONG_S k0, PT_TCSTATUS(sp) #endif /* CONFIG_MIPS_MT_SMTC */ LONG_S $4, PT_R4(sp) - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_STATUS(sp) mfc0 v1, CP0_CAUSE - LONG_S $6, PT_R6(sp) - LONG_S $7, PT_R7(sp) + LONG_S $5, PT_R5(sp) LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) #ifdef CONFIG_64BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif + LONG_S v1, PT_EPC(sp) LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) - LONG_S v1, PT_EPC(sp) ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 8db7a47..98eb036 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -442,6 +442,9 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->options |= MIPS_CPU_ULRI; if (config3 & MIPS_CONF3_ISA) c->options |= MIPS_CPU_MICROMIPS; +#ifdef CONFIG_CPU_MICROMIPS + write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE); +#endif return config3 & MIPS_CONF_M; } diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 8882e57..dc7d756 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -5,8 +5,8 @@ * * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. * Copyright (C) 2002, 2007 Maciej W. Rozycki + * Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved. */ #include @@ -22,8 +22,10 @@ #include #include +#ifdef CONFIG_MIPS_MT_SMTC #define PANIC_PIC(msg) \ - .set push; \ + .set push; \ + .set nomicromips; \ .set reorder; \ PTR_LA a0,8f; \ .set noat; \ @@ -32,17 +34,10 @@ 9: b 9b; \ .set pop; \ TEXT(msg) +#endif __INIT -NESTED(except_vec0_generic, 0, sp) - PANIC_PIC("Exception vector 0 called") - END(except_vec0_generic) - -NESTED(except_vec1_generic, 0, sp) - PANIC_PIC("Exception vector 1 called") - END(except_vec1_generic) - /* * General exception vector for all other CPUs. * @@ -139,12 +134,19 @@ LEAF(r4k_wait) nop nop nop +#ifdef CONFIG_CPU_MICROMIPS + nop + nop + nop + nop +#endif .set mips3 wait /* end of rollback region (the region size must be power of two) */ - .set pop 1: jr ra + nop + .set pop END(r4k_wait) .macro BUILD_ROLLBACK_PROLOGUE handler @@ -202,7 +204,11 @@ NESTED(handle_int, PT_SIZE, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) PTR_LA ra, ret_from_irq - j plat_irq_dispatch + PTR_LA v0, plat_irq_dispatch + jr v0 +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif END(handle_int) __INIT @@ -223,11 +229,14 @@ NESTED(except_vec4, 0, sp) /* * EJTAG debug exception handler. * The EJTAG debug exception entry point is 0xbfc00480, which - * normally is in the boot PROM, so the boot PROM must do a + * normally is in the boot PROM, so the boot PROM must do an * unconditional jump to this vector. */ NESTED(except_vec_ejtag_debug, 0, sp) j ejtag_debug_handler +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif END(except_vec_ejtag_debug) __FINIT @@ -252,9 +261,10 @@ NESTED(except_vec_vi, 0, sp) FEXPORT(except_vec_vi_mori) ori a0, $0, 0 #endif /* CONFIG_MIPS_MT_SMTC */ + PTR_LA v1, except_vec_vi_handler FEXPORT(except_vec_vi_lui) lui v0, 0 /* Patched */ - j except_vec_vi_handler + jr v1 FEXPORT(except_vec_vi_ori) ori v0, 0 /* Patched */ .set pop @@ -355,6 +365,9 @@ EXPORT(ejtag_debug_buffer) */ NESTED(except_vec_nmi, 0, sp) j nmi_handler +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif END(except_vec_nmi) __FINIT @@ -501,13 +514,36 @@ NESTED(nmi_handler, PT_SIZE, sp) .set push .set noat .set noreorder - /* 0x7c03e83b: rdhwr v1,$29 */ + /* MIPS32: 0x7c03e83b: rdhwr v1,$29 */ + /* uMIPS: 0x007d6b3c: rdhwr v1,$29 -- in MIPS16e it is */ + /* ADDIUSP $16,0x7d; LI $3,0x3c and never RI. LY22 */ MFC0 k1, CP0_EPC - lui k0, 0x7c03 - lw k1, (k1) - ori k0, 0xe83b - .set reorder +#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2) + and k0, k1, 1 + beqz k0, 1f + xor k1, k0 + lhu k0, (k1) + lhu k1, 2(k1) + ins k1, k0, 16, 16 + lui k0, 0x007d + b docheck + ori k0, 0x6b3c +1: + lui k0, 0x7c03 + lw k1, (k1) + ori k0, 0xe83b +#else + andi k0, k1, 1 + bnez k0, handle_ri + lui k0, 0x7c03 + lw k1, (k1) + ori k0, 0xe83b +#endif + .set reorder +docheck: bne k0, k1, handle_ri /* if not ours */ + +isrdhwr: /* The insn is rdhwr. No need to check CAUSE.BD here. */ get_saved_sp /* k1 := current_thread_info */ .set noreorder diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 374f66e..2c0b071 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -138,9 +138,18 @@ stackargs: 5: jr t1 sw t5, 16(sp) # argument #5 to ksp +#ifdef CONFIG_CPU_MICROMIPS sw t8, 28(sp) # argument #8 to ksp + nop sw t7, 24(sp) # argument #7 to ksp + nop sw t6, 20(sp) # argument #6 to ksp + nop +#else + sw t8, 28(sp) # argument #8 to ksp + sw t7, 24(sp) # argument #7 to ksp + sw t6, 20(sp) # argument #6 to ksp +#endif 6: j stack_done # go back nop .set pop diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index 20938a4..8e9ae50 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S @@ -49,6 +49,9 @@ CAN WE PROVE THAT WE WON'T DO THIS IF INTS DISABLED?? .text .align 5 FEXPORT(__smtc_ipi_vector) +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif .set noat /* Disable thread scheduling to make Status update atomic */ DMT 27 # dmt k1 diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index c0dc176..feccbe8 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -8,8 +8,8 @@ * Copyright (C) 1998 Ulf Carlsson * Copyright (C) 1999 Silicon Graphics, Inc. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 01 MIPS Technologies, Inc. * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. */ #include #include @@ -82,10 +82,6 @@ extern asmlinkage void handle_dsp(void); extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); -extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, - struct mips_fpu_struct *ctx, int has_fpu, - void *__user *fault_addr); - void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); void (*board_nmi_handler_setup)(void); @@ -491,6 +487,12 @@ asmlinkage void do_be(struct pt_regs *regs) #define SYNC 0x0000000f #define RDHWR 0x0000003b +/* microMIPS definitions */ +#define MM_POOL32A_FUNC 0xfc00ffff +#define MM_RDHWR 0x00006b3c +#define MM_RS 0x001f0000 +#define MM_RT 0x03e00000 + /* * The ll_bit is cleared by r*_switch.S */ @@ -605,42 +607,62 @@ static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) * Simulate trapping 'rdhwr' instructions to provide user accessible * registers not implemented in hardware. */ -static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) +static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) { struct thread_info *ti = task_thread_info(current); + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, regs, 0); + switch (rd) { + case 0: /* CPU number */ + regs->regs[rt] = smp_processor_id(); + return 0; + case 1: /* SYNCI length */ + regs->regs[rt] = min(current_cpu_data.dcache.linesz, + current_cpu_data.icache.linesz); + return 0; + case 2: /* Read count register */ + regs->regs[rt] = read_c0_count(); + return 0; + case 3: /* Count register resolution */ + switch (current_cpu_data.cputype) { + case CPU_20KC: + case CPU_25KF: + regs->regs[rt] = 1; + break; + default: + regs->regs[rt] = 2; + } + return 0; + case 29: + regs->regs[rt] = ti->tp_value; + return 0; + default: + return -1; + } +} + +static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) +{ if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { int rd = (opcode & RD) >> 11; int rt = (opcode & RT) >> 16; - perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, - 1, regs, 0); - switch (rd) { - case 0: /* CPU number */ - regs->regs[rt] = smp_processor_id(); - return 0; - case 1: /* SYNCI length */ - regs->regs[rt] = min(current_cpu_data.dcache.linesz, - current_cpu_data.icache.linesz); - return 0; - case 2: /* Read count register */ - regs->regs[rt] = read_c0_count(); - return 0; - case 3: /* Count register resolution */ - switch (current_cpu_data.cputype) { - case CPU_20KC: - case CPU_25KF: - regs->regs[rt] = 1; - break; - default: - regs->regs[rt] = 2; - } - return 0; - case 29: - regs->regs[rt] = ti->tp_value; - return 0; - default: - return -1; - } + + simulate_rdhwr(regs, rd, rt); + return 0; + } + + /* Not ours. */ + return -1; +} + +static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) +{ + if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { + int rd = (opcode & MM_RS) >> 16; + int rt = (opcode & MM_RT) >> 21; + simulate_rdhwr(regs, rd, rt); + return 0; } /* Not ours. */ @@ -822,9 +844,29 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, asmlinkage void do_bp(struct pt_regs *regs) { unsigned int opcode, bcode; - - if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) - goto out_sigsegv; + unsigned long epc; + u16 instr[2]; + + if (regs->cp0_epc & MIPS_ISA_MODE) { + /* calc exception pc */ + epc = exception_epc(regs); + if (cpu_has_mmips) { + if ((__get_user(instr[0], (u16 __user *)(epc & ~MIPS_ISA_MODE))) || + (__get_user(instr[1], (u16 __user *)((epc+2) & ~MIPS_ISA_MODE)))) + goto out_sigsegv; + opcode = (instr[0] << 16) | instr[1]; + } else { + /* MIPS16e mode */ + if (__get_user(instr[0], (u16 __user *)(epc & ~MIPS_ISA_MODE))) + goto out_sigsegv; + bcode = (instr[0] >> 6) & 0x3f; + do_trap_or_bp(regs, bcode, "Break"); + return; + } + } else { + if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) + goto out_sigsegv; + } /* * There is the ancient bug in the MIPS assemblers that the break @@ -865,13 +907,22 @@ out_sigsegv: asmlinkage void do_tr(struct pt_regs *regs) { unsigned int opcode, tcode = 0; + u16 instr[2]; + unsigned long epc = exception_epc(regs); - if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) - goto out_sigsegv; + if ((__get_user(instr[0], (u16 __user *)(epc & ~MIPS_ISA_MODE))) || + (__get_user(instr[1], (u16 __user *)((epc+2) & ~MIPS_ISA_MODE)))) + goto out_sigsegv; + opcode = (instr[0] << 16) | instr[1]; /* Immediate versions don't provide a code. */ - if (!(opcode & OPCODE)) - tcode = ((opcode >> 6) & ((1 << 10) - 1)); + if (!(opcode & OPCODE)) { + if (is16mode(regs)) + /* microMIPS */ + tcode = (opcode >> 12) & 0x1f; + else + tcode = ((opcode >> 6) & ((1 << 10) - 1)); + } do_trap_or_bp(regs, tcode, "Trap"); return; @@ -884,6 +935,7 @@ asmlinkage void do_ri(struct pt_regs *regs) { unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); unsigned long old_epc = regs->cp0_epc; + unsigned long old31 = regs->regs[31]; unsigned int opcode = 0; int status = -1; @@ -896,23 +948,37 @@ asmlinkage void do_ri(struct pt_regs *regs) if (unlikely(compute_return_epc(regs) < 0)) return; - if (unlikely(get_user(opcode, epc) < 0)) - status = SIGSEGV; + if (is16mode(regs)) { + unsigned short mmop[2] = { 0 }; - if (!cpu_has_llsc && status < 0) - status = simulate_llsc(regs, opcode); + if (unlikely(get_user(mmop[0], epc) < 0)) + status = SIGSEGV; + if (unlikely(get_user(mmop[1], epc) < 0)) + status = SIGSEGV; + opcode = (mmop[0] << 16) | mmop[1]; - if (status < 0) - status = simulate_rdhwr(regs, opcode); + if (status < 0) + status = simulate_rdhwr_mm(regs, opcode); + } else { + if (unlikely(get_user(opcode, epc) < 0)) + status = SIGSEGV; - if (status < 0) - status = simulate_sync(regs, opcode); + if (!cpu_has_llsc && status < 0) + status = simulate_llsc(regs, opcode); + + if (status < 0) + status = simulate_rdhwr_normal(regs, opcode); + + if (status < 0) + status = simulate_sync(regs, opcode); + } if (status < 0) status = SIGILL; if (unlikely(status > 0)) { regs->cp0_epc = old_epc; /* Undo skip-over. */ + regs->regs[31] = old31; force_sig(status, current); } } @@ -982,7 +1048,7 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action, asmlinkage void do_cpu(struct pt_regs *regs) { unsigned int __user *epc; - unsigned long old_epc; + unsigned long old_epc, old31; unsigned int opcode; unsigned int cpid; int status; @@ -996,26 +1062,41 @@ asmlinkage void do_cpu(struct pt_regs *regs) case 0: epc = (unsigned int __user *)exception_epc(regs); old_epc = regs->cp0_epc; + old31 = regs->regs[31]; opcode = 0; status = -1; if (unlikely(compute_return_epc(regs) < 0)) return; - if (unlikely(get_user(opcode, epc) < 0)) - status = SIGSEGV; + if (is16mode(regs)) { + unsigned short mmop[2] = { 0 }; - if (!cpu_has_llsc && status < 0) - status = simulate_llsc(regs, opcode); + if (unlikely(get_user(mmop[0], epc) < 0)) + status = SIGSEGV; + if (unlikely(get_user(mmop[1], epc) < 0)) + status = SIGSEGV; + opcode = (mmop[0] << 16) | mmop[1]; - if (status < 0) - status = simulate_rdhwr(regs, opcode); + if (status < 0) + status = simulate_rdhwr_mm(regs, opcode); + } else { + if (unlikely(get_user(opcode, epc) < 0)) + status = SIGSEGV; + + if (!cpu_has_llsc && status < 0) + status = simulate_llsc(regs, opcode); + + if (status < 0) + status = simulate_rdhwr_normal(regs, opcode); + } if (status < 0) status = SIGILL; if (unlikely(status > 0)) { regs->cp0_epc = old_epc; /* Undo skip-over. */ + regs->regs[31] = old31; force_sig(status, current); } @@ -1329,7 +1410,7 @@ asmlinkage void cache_parity_error(void) void ejtag_exception_handler(struct pt_regs *regs) { const int field = 2 * sizeof(unsigned long); - unsigned long depc, old_epc; + unsigned long depc, old_epc, old_ra; unsigned int debug; printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); @@ -1344,10 +1425,12 @@ void ejtag_exception_handler(struct pt_regs *regs) * calculation. */ old_epc = regs->cp0_epc; + old_ra = regs->regs[31]; regs->cp0_epc = depc; - __compute_return_epc(regs); + compute_return_epc(regs); depc = regs->cp0_epc; regs->cp0_epc = old_epc; + regs->regs[31] = old_ra; } else depc += 4; write_c0_depc(depc); @@ -1388,9 +1471,24 @@ void __init *set_except_vector(int n, void *addr) unsigned long handler = (unsigned long) addr; unsigned long old_handler = exception_handlers[n]; +#ifdef CONFIG_CPU_MICROMIPS + /* + * Only the TLB handlers are cache aligned with an even + * address. All other handlers are on an odd address and + * require no modification. Otherwise, MIPS32 mode will + * be entered when handling any TLB exceptions. That + * would be bad...since we must stay in microMIPS mode. + */ + if (!(handler & 0x1)) + handler |= 1; +#endif exception_handlers[n] = handler; if (n == 0 && cpu_has_divec) { +#ifdef CONFIG_CPU_MICROMIPS + unsigned long jump_mask = ~((1 << 27) - 1); +#else unsigned long jump_mask = ~((1 << 28) - 1); +#endif u32 *buf = (u32 *)(ebase + 0x200); unsigned int k0 = 26; if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { @@ -1417,17 +1515,18 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) unsigned long handler; unsigned long old_handler = vi_handlers[n]; int srssets = current_cpu_data.srsets; - u32 *w; + u16 *h; unsigned char *b; BUG_ON(!cpu_has_veic && !cpu_has_vint); + BUG_ON((n < 0) && (n > 9)); if (addr == NULL) { handler = (unsigned long) do_default_vi; srs = 0; } else handler = (unsigned long) addr; - vi_handlers[n] = (unsigned long) addr; + vi_handlers[n] = handler; b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); @@ -1446,9 +1545,8 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) if (srs == 0) { /* * If no shadow set is selected then use the default handler - * that does normal register saving and a standard interrupt exit + * that does normal register saving and standard interrupt exit */ - extern char except_vec_vi, except_vec_vi_lui; extern char except_vec_vi_ori, except_vec_vi_end; extern char rollback_except_vec_vi; @@ -1461,11 +1559,20 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * Status.IM bit to be masked before going there. */ extern char except_vec_vi_mori; +#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) + const int mori_offset = &except_vec_vi_mori - vec_start + 2; +#else const int mori_offset = &except_vec_vi_mori - vec_start; +#endif #endif /* CONFIG_MIPS_MT_SMTC */ - const int handler_len = &except_vec_vi_end - vec_start; +#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) + const int lui_offset = &except_vec_vi_lui - vec_start + 2; + const int ori_offset = &except_vec_vi_ori - vec_start + 2; +#else const int lui_offset = &except_vec_vi_lui - vec_start; const int ori_offset = &except_vec_vi_ori - vec_start; +#endif + const int handler_len = &except_vec_vi_end - vec_start; if (handler_len > VECTORSPACING) { /* @@ -1475,30 +1582,44 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) panic("VECTORSPACING too small"); } - memcpy(b, vec_start, handler_len); + set_handler(((unsigned long)b - ebase), vec_start, +#ifdef CONFIG_CPU_MICROMIPS + (handler_len - 1)); +#else + handler_len); +#endif #ifdef CONFIG_MIPS_MT_SMTC BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ - w = (u32 *)(b + mori_offset); - *w = (*w & 0xffff0000) | (0x100 << n); + h = (u16 *)(b + mori_offset); + *h = (0x100 << n); #endif /* CONFIG_MIPS_MT_SMTC */ - w = (u32 *)(b + lui_offset); - *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); - w = (u32 *)(b + ori_offset); - *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); + h = (u16 *)(b + lui_offset); + *h = (handler >> 16) & 0xffff; + h = (u16 *)(b + ori_offset); + *h = (handler & 0xffff); local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } else { /* - * In other cases jump directly to the interrupt handler - * - * It is the handlers responsibility to save registers if required - * (eg hi/lo) and return from the exception using "eret" + * In other cases jump directly to the interrupt handler. It + * is the handler's responsibility to save registers if required + * (eg hi/lo) and return from the exception using "eret". */ - w = (u32 *)b; - *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ - *w = 0; + u32 insn; + + h = (u16 *)b; + /* j handler */ +#ifdef CONFIG_CPU_MICROMIPS + insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); +#else + insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); +#endif + h[0] = (insn >> 16) & 0xffff; + h[1] = insn & 0xffff; + h[2] = 0; + h[3] = 0; local_flush_icache_range((unsigned long)b, (unsigned long)(b+8)); } @@ -1657,7 +1778,11 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) /* Install CPU exception handler */ void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) { +#ifdef CONFIG_CPU_MICROMIPS + memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); +#else memcpy((void *)(ebase + offset), addr, size); +#endif local_flush_icache_range(ebase + offset, ebase + offset + size); } @@ -1691,8 +1816,9 @@ __setup("rdhwr_noopt", set_rdhwr_noopt); void __init trap_init(void) { - extern char except_vec3_generic, except_vec3_r4000; + extern char except_vec3_generic; extern char except_vec4; + extern char except_vec3_r4000; unsigned long i; int rollback; @@ -1825,11 +1951,11 @@ void __init trap_init(void) if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); + set_handler(0x180, &except_vec3_r4000, 0x100); else if (cpu_has_4kex) - memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); + set_handler(0x180, &except_vec3_generic, 0x80); else - memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); + set_handler(0x080, &except_vec3_generic, 0x80); local_flush_icache_range(ebase, ebase + 0x400); flush_tlb_handlers(); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 6f3d4007..cd9ad1b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2021,6 +2021,13 @@ static void __cpuinit build_r4000_tlb_load_handler(void) uasm_l_nopage_tlbl(&l, p); build_restore_work_registers(&p); +#ifdef CONFIG_CPU_MICROMIPS + if ((unsigned long)tlb_do_page_fault_0 & 1) { + uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); + uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); + uasm_i_jr(&p, K0); + } else +#endif uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); uasm_i_nop(&p); @@ -2068,6 +2075,13 @@ static void __cpuinit build_r4000_tlb_store_handler(void) uasm_l_nopage_tlbs(&l, p); build_restore_work_registers(&p); +#ifdef CONFIG_CPU_MICROMIPS + if ((unsigned long)tlb_do_page_fault_1 & 1) { + uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); + uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); + uasm_i_jr(&p, K0); + } else +#endif uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); @@ -2116,6 +2130,13 @@ static void __cpuinit build_r4000_tlb_modify_handler(void) uasm_l_nopage_tlbm(&l, p); build_restore_work_registers(&p); +#ifdef CONFIG_CPU_MICROMIPS + if ((unsigned long)tlb_do_page_fault_1 & 1) { + uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); + uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); + uasm_i_jr(&p, K0); + } else +#endif uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c index a958cad..802fce2 100644 --- a/arch/mips/mti-sead3/sead3-init.c +++ b/arch/mips/mti-sead3/sead3-init.c @@ -52,7 +52,41 @@ static void __init mips_nmi_setup(void) base = cpu_has_veic ? (void *)(CAC_BASE + 0xa80) : (void *)(CAC_BASE + 0x380); +#ifdef CONFIG_CPU_MICROMIPS + /* + * Decrement the exception vector address by one for microMIPS. + */ + memcpy(base, (&except_vec_nmi - 1), 0x80); + + /* + * This is a hack. We do not know if the boot loader was built with + * microMIPS instructions or not. If it was not, the NMI exception + * code at 0x80000a80 will be taken in MIPS32 mode. The hand coded + * assembly below forces us into microMIPS mode if we are a pure + * microMIPS kernel. The assembly instructions are: + * + * 3C1A8000 lui k0,0x8000 + * 375A0381 ori k0,k0,0x381 + * 03400008 jr k0 + * 00000000 nop + * + * The mode switch occurs by jumping to the unaligned exception + * vector address at 0x80000381 which would have been 0x80000380 + * in MIPS32 mode. The jump to the unaligned address transitions + * us into microMIPS mode. + */ + if (!cpu_has_veic) { + void *base2 = (void *)(CAC_BASE + 0xa80); + *((unsigned int *)base2) = 0x3c1a8000; + *((unsigned int *)base2 + 1) = 0x375a0381; + *((unsigned int *)base2 + 2) = 0x03400008; + *((unsigned int *)base2 + 3) = 0x00000000; + flush_icache_range((unsigned long)base2, + (unsigned long)base2 + 0x10); + } +#else memcpy(base, &except_vec_nmi, 0x80); +#endif flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } @@ -63,7 +97,21 @@ static void __init mips_ejtag_setup(void) base = cpu_has_veic ? (void *)(CAC_BASE + 0xa00) : (void *)(CAC_BASE + 0x300); +#ifdef CONFIG_CPU_MICROMIPS + /* Deja vu... */ + memcpy(base, (&except_vec_ejtag_debug - 1), 0x80); + if (!cpu_has_veic) { + void *base2 = (void *)(CAC_BASE + 0xa00); + *((unsigned int *)base2) = 0x3c1a8000; + *((unsigned int *)base2 + 1) = 0x375a0301; + *((unsigned int *)base2 + 2) = 0x03400008; + *((unsigned int *)base2 + 3) = 0x00000000; + flush_icache_range((unsigned long)base2, + (unsigned long)base2 + 0x10); + } +#else memcpy(base, &except_vec_ejtag_debug, 0x80); +#endif flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:07:36 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60314 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824761Ab2LGFFx11Rwi (ORCPT ); Fri, 7 Dec 2012 06:05:53 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8A-0007MA-MX; Thu, 06 Dec 2012 23:05:46 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, Leonid Yegoshin Subject: [PATCH v99,05/13] MIPS: microMIPS: Support handling of delay slots. Date: Thu, 6 Dec 2012 23:05:29 -0600 Message-Id: <1354856737-28678-6-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35216 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8379 Lines: 325 From: "Steven J. Hill" Add logic needed to properly calculate exceptions for delay slots when in microMIPS or MIPS16e modes. Signed-off-by: Leonid Yegoshin Signed-off-by: Steven J. Hill --- arch/mips/include/asm/branch.h | 33 +++++++- arch/mips/include/asm/inst.h | 3 + arch/mips/kernel/branch.c | 183 +++++++++++++++++++++++++++++++++++++++- arch/mips/kernel/unaligned.c | 3 + 4 files changed, 219 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h index 888766a..ccc938a 100644 --- a/arch/mips/include/asm/branch.h +++ b/arch/mips/include/asm/branch.h @@ -16,11 +16,16 @@ static inline int delay_slot(struct pt_regs *regs) return regs->cp0_cause & CAUSEF_BD; } +extern int __isa_exception_epc(struct pt_regs *regs); + static inline unsigned long exception_epc(struct pt_regs *regs) { - if (!delay_slot(regs)) + if (likely(!delay_slot(regs))) return regs->cp0_epc; + if (is16mode(regs)) + return __isa_exception_epc(regs); + return regs->cp0_epc + 4; } @@ -29,9 +34,20 @@ static inline unsigned long exception_epc(struct pt_regs *regs) extern int __compute_return_epc(struct pt_regs *regs); extern int __compute_return_epc_for_insn(struct pt_regs *regs, union mips_instruction insn); +extern int __MIPS16e_compute_return_epc(struct pt_regs *regs); +extern int __microMIPS_compute_return_epc(struct pt_regs *regs); +/* only for MIPS32/64 but not 16bits variants */ static inline int compute_return_epc(struct pt_regs *regs) { + if (is16mode(regs)) { + if (cpu_has_mips16) + return __MIPS16e_compute_return_epc(regs); + if (cpu_has_mmips) + return __microMIPS_compute_return_epc(regs); + return regs->cp0_epc; + } + if (!delay_slot(regs)) { regs->cp0_epc += 4; return 0; @@ -40,4 +56,19 @@ static inline int compute_return_epc(struct pt_regs *regs) return __compute_return_epc(regs); } +static inline int MIPS16e_compute_return_epc(struct pt_regs *regs, + union mips16e_instruction *inst) +{ + if (likely(!delay_slot(regs))) { + if (inst->ri.opcode == MIPS16e_extend_op) { + regs->cp0_epc += 4; + return 0; + } + regs->cp0_epc += 2; + return 0; + } + + return __MIPS16e_compute_return_epc(regs); +} + #endif /* _ASM_BRANCH_H */ diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index 2b2e0e3..c97b854 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -1122,6 +1122,9 @@ struct decoded_instn { int micro_mips_mode; }; +/* Recode table from MIPS16e register notation to GPR. */ +extern const int mips16e_reg2gpr[]; + union mips16e_instruction { unsigned int full:16; struct rr rr; diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index 4d735d0..01b4e91 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -14,10 +14,188 @@ #include #include #include +#include #include #include #include +/* + * Calculate and return exception epc in case of + * branch delay slot for microMIPS/MIPS16e + * It doesn't clear ISA mode bit. + */ +int __isa_exception_epc(struct pt_regs *regs) +{ + long epc; + union mips16e_instruction inst; + + /* calc exception pc in branch delay slot */ + epc = regs->cp0_epc; + if (__get_user(inst.full, (u16 __user *) (epc & ~MIPS_ISA_MODE))) { + /* it should never happens... because delay slot was checked */ + force_sig(SIGSEGV, current); + return epc; + } + if (cpu_has_mips16) { + if (inst.ri.opcode == MIPS16e_jal_op) + epc += 4; + else + epc += 2; + } else if (mm_is16bit(inst.full)) + epc += 2; + else + epc += 4; + + return epc; +} + +/* + * Compute the return address and do emulate branch simulation in MIPS16e mode, + * if required. + * After exception only - doesn't do 'compact' branch/jumps and can't be used + * during interrupt (compact B/J doesn't do exception) + */ +int __MIPS16e_compute_return_epc(struct pt_regs *regs) +{ + u16 __user *addr; + union mips16e_instruction inst; + u16 inst2; + u32 fullinst; + long epc; + + epc = regs->cp0_epc; + /* + * Read the instruction + */ + addr = (u16 __user *) (epc & ~MIPS_ISA_MODE); + if (__get_user(inst.full, addr)) { + force_sig(SIGSEGV, current); + return -EFAULT; + } + + switch (inst.ri.opcode) { + case MIPS16e_extend_op: + regs->cp0_epc += 4; + return 0; + + /* + * JAL and JALX in MIPS16e mode + */ + case MIPS16e_jal_op: + addr += 1; + if (__get_user(inst2, addr)) { + force_sig(SIGSEGV, current); + return -EFAULT; + } + fullinst = ((unsigned)inst.full << 16) | inst2; + regs->regs[31] = epc + 6; + epc += 4; + epc >>= 28; + epc <<= 28; + /* + * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16 + * + * ......TARGET[15:0].................TARGET[20:16]........... + * ......TARGET[25:21] + */ + epc |= + ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) | + ((fullinst & 0x1f0000) << 7); + if (!inst.jal.x) + epc |= MIPS_ISA_MODE; /* set ISA mode 1 */ + regs->cp0_epc = epc; + return 0; + + /* + * J(AL)R(C) + */ + case MIPS16e_rr_op: + if (inst.rr.func == MIPS16e_jr_func) { + + if (inst.rr.ra) + regs->cp0_epc = regs->regs[31]; + else + regs->cp0_epc = + regs->regs[mips16e_reg2gpr[inst.rr.rx]]; + + if (inst.rr.l) { + if (inst.rr.nd) + regs->regs[31] = epc + 2; + else + regs->regs[31] = epc + 4; + } + return 0; + } + break; + } + + /* all other cases have no branch delay slot and are 16bits, + and branches do not do exception */ + regs->cp0_epc += 2; + + return 0; +} + +/* + * Compute the return address and do emulate branch simulation in + * microMIPS mode, if required. + * After exception only - doesn't do 'compact' branch/jumps and can't be used + * during interrupt (compact B/J doesn't do exception) + */ +int __microMIPS_compute_return_epc(struct pt_regs *regs) +{ + u16 __user *pc16; + u16 halfword; + unsigned int word; + unsigned long contpc; + struct decoded_instn mminst = { 0 }; + + mminst.micro_mips_mode = 1; + + /* + * This load never faults. + */ + pc16 = (unsigned short __user *)(regs->cp0_epc & ~MIPS_ISA_MODE); + __get_user(halfword, pc16); + pc16++; + contpc = regs->cp0_epc + 2; + word = ((unsigned int)halfword << 16); + mminst.pc_inc = 2; + + if (!mm_is16bit(halfword)) { + __get_user(halfword, pc16); + pc16++; + contpc = regs->cp0_epc + 4; + mminst.pc_inc = 4; + word |= halfword; + } + mminst.insn = word; + + if (get_user(halfword, pc16)) + goto sigsegv; + mminst.next_pc_inc = 2; + word = ((unsigned int)halfword << 16); + + if (!mm_is16bit(halfword)) { + pc16++; + if (get_user(halfword, pc16)) + goto sigsegv; + mminst.next_pc_inc = 4; + word |= halfword; + } + mminst.next_insn = word; + + mm_isBranchInstr(regs, mminst, &contpc); + + regs->cp0_epc = contpc; + + return 0; + +sigsegv: + force_sig(SIGSEGV, current); + return -EFAULT; +} + /** * __compute_return_epc_for_insn - Computes the return address and do emulate * branch simulation, if required. @@ -57,7 +235,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, */ case bcond_op: switch (insn.i_format.rt) { - case bltz_op: + case bltz_op: case bltzl_op: if ((long)regs->regs[insn.i_format.rs] < 0) { epc = epc + 4 + (insn.i_format.simmediate << 2); @@ -129,6 +307,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, epc <<= 28; epc |= (insn.j_format.target << 2); regs->cp0_epc = epc; + if (insn.i_format.opcode == jalx_op) + regs->cp0_epc |= MIPS_ISA_MODE; break; /* @@ -289,5 +469,4 @@ unaligned: printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); force_sig(SIGBUS, current); return -EFAULT; - } diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 9c58bdf..ad855db 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -102,6 +102,9 @@ static u32 unaligned_action; #endif extern void show_registers(struct pt_regs *regs); +/* Recode table from MIPS16e register notation to GPR. */ +const int mips16e_reg2gpr[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + static void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int __user *pc) { -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:07:54 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60318 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824772Ab2LGFFyDKpsy (ORCPT ); Fri, 7 Dec 2012 06:05:54 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8B-0007MA-MI; Thu, 06 Dec 2012 23:05:47 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: Douglas Leung , ralf@linux-mips.org, "Steven J. Hill" Subject: [PATCH v99,07/13] MIPS: microMIPS: Add vdso support. Date: Thu, 6 Dec 2012 23:05:31 -0600 Message-Id: <1354856737-28678-8-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35217 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 918 Lines: 37 From: Douglas Leung Support vdso in microMIPS mode. Signed-off-by: Steven J. Hill --- arch/mips/kernel/signal.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index b6aa770..3dc23cd 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "signal-common.h" @@ -518,7 +519,12 @@ static void handle_signal(unsigned long sig, siginfo_t *info, sigset_t *oldset = sigmask_to_save(); int ret; struct mips_abi *abi = current->thread.abi; +#ifdef CONFIG_CPU_MICROMIPS + void *vdso = (void *) + ((unsigned int)current->mm->context.vdso | MIPS_ISA_MODE); +#else void *vdso = current->mm->context.vdso; +#endif if (regs->regs[0]) { switch(regs->regs[2]) { -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:08:16 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60317 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824766Ab2LGFFybtuNs (ORCPT ); Fri, 7 Dec 2012 06:05:54 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8B-0007MA-6X; Thu, 06 Dec 2012 23:05:47 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, Leonid Yegoshin Subject: [PATCH v99,06/13] MIPS: microMIPS: Add unaligned access support. Date: Thu, 6 Dec 2012 23:05:30 -0600 Message-Id: <1354856737-28678-7-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35218 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 47852 Lines: 1806 From: "Steven J. Hill" Add logic needed to properly handle unaligned accesses when in microMIPS or MIPS16e modes. Signed-off-by: Leonid Yegoshin Signed-off-by: Steven J. Hill --- arch/mips/kernel/process.c | 101 +++ arch/mips/kernel/unaligned.c | 1493 ++++++++++++++++++++++++++++++++++++------ 2 files changed, 1388 insertions(+), 206 deletions(-) diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 69b17a9..a64409c 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -7,6 +7,7 @@ * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2004 Thiemo Seufer + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include #include @@ -260,34 +261,115 @@ struct mips_frame_info { static inline int is_ra_save_ins(union mips_instruction *ip) { +#ifdef CONFIG_CPU_MICROMIPS + union mips_instruction mmi; + + /* + * swsp ra,offset + * swm16 reglist,offset(sp) + * swm32 reglist,offset(sp) + * sw32 ra,offset(sp) + * jradiussp - NOT SUPPORTED + * + * microMIPS is way more fun... + */ + if (mm_is16bit(ip->halfword[0])) { + mmi.word = (ip->halfword[0] << 16); + return ((mmi.mm16_r5_format.opcode == mm_swsp16_op && + mmi.mm16_r5_format.rt == 31) || + (mmi.mm16_m_format.opcode == mm_pool16c_op && + mmi.mm16_m_format.func == mm_swm16_op)); + } + else { + mmi.halfword[0] = ip->halfword[1]; + mmi.halfword[1] = ip->halfword[0]; + return ((mmi.mm_m_format.opcode == mm_pool32b_op && + mmi.mm_m_format.rd > 9 && + mmi.mm_m_format.base == 29 && + mmi.mm_m_format.func == mm_swm32_func) || + (mmi.i_format.opcode == mm_sw32_op && + mmi.i_format.rs == 29 && + mmi.i_format.rt == 31)); + } +#else /* sw / sd $ra, offset($sp) */ return (ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && ip->i_format.rs == 29 && ip->i_format.rt == 31; +#endif } static inline int is_jal_jalr_jr_ins(union mips_instruction *ip) { +#ifdef CONFIG_CPU_MICROMIPS + /* + * jr16,jrc,jalr16,jalr16 + * jal + * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb + * jraddiusp - NOT SUPPORTED + * + * microMIPS is kind of more fun... + */ + union mips_instruction mmi; + + mmi.word = (ip->halfword[0] << 16); + + if ((mmi.mm16_r5_format.opcode == mm_pool16c_op && + (mmi.mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op) || + ip->j_format.opcode == mm_jal32_op) + return 1; + if (ip->r_format.opcode != mm_pool32a_op || + ip->r_format.func != mm_pool32axf_op) + return 0; + return (((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op); +#else if (ip->j_format.opcode == jal_op) return 1; if (ip->r_format.opcode != spec_op) return 0; return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; +#endif } static inline int is_sp_move_ins(union mips_instruction *ip) { +#ifdef CONFIG_CPU_MICROMIPS + /* + * addiusp -imm + * addius5 sp,-imm + * addiu32 sp,sp,-imm + * jradiussp - NOT SUPPORTED + * + * microMIPS is not more fun... + */ + if (mm_is16bit(ip->halfword[0])) { + union mips_instruction mmi; + + mmi.word = (ip->halfword[0] << 16); + return ((mmi.mm16_r3_format.opcode == mm_pool16d_op && + mmi.mm16_r3_format.simmediate && mm_addiusp_func) || + (mmi.mm16_r5_format.opcode == mm_pool16d_op && + mmi.mm16_r5_format.rt == 29)); + } + return (ip->mm_i_format.opcode == mm_addiu32_op && + ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29); +#else /* addiu/daddiu sp,sp,-imm */ if (ip->i_format.rs != 29 || ip->i_format.rt != 29) return 0; if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) return 1; +#endif return 0; } static int get_frame_info(struct mips_frame_info *info) { +#ifdef CONFIG_CPU_MICROMIPS + union mips_instruction *ip = (void *) (((char *) info->func) - 1); +#else union mips_instruction *ip = info->func; +#endif unsigned max_insns = info->func_size / sizeof(union mips_instruction); unsigned i; @@ -307,7 +389,26 @@ static int get_frame_info(struct mips_frame_info *info) break; if (!info->frame_size) { if (is_sp_move_ins(ip)) + { +#ifdef CONFIG_CPU_MICROMIPS + if (mm_is16bit(ip->halfword[0])) + { + unsigned short tmp; + + if (ip->halfword[0] & mm_addiusp_func) + { + tmp = (((ip->halfword[0] >> 1) & 0x1ff) << 2); + info->frame_size = -(signed short)(tmp | ((tmp & 0x100) ? 0xfe00 : 0)); + } else { + tmp = (ip->halfword[0] >> 1); + info->frame_size = -(signed short)(tmp & 0xf); + } + ip = (void *) &ip->halfword[1]; + ip--; + } else +#endif info->frame_size = - ip->i_format.simmediate; + } continue; } if (info->pc_offset == -1 && is_ra_save_ins(ip)) { diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index ad855db..3f5f21a 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -85,6 +85,8 @@ #include #include #include +#include +#include #define STR(x) __STR(x) #define __STR(x) #x @@ -105,12 +107,333 @@ extern void show_registers(struct pt_regs *regs); /* Recode table from MIPS16e register notation to GPR. */ const int mips16e_reg2gpr[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; +#ifdef __BIG_ENDIAN +#define LoadHW(addr, value, res) \ + __asm__ __volatile__ (".set\tnoat\n" \ + "1:\tlb\t%0, 0(%2)\n" \ + "2:\tlbu\t$1, 1(%2)\n\t" \ + "sll\t%0, 0x8\n\t" \ + "or\t%0, $1\n\t" \ + "li\t%1, 0\n" \ + "3:\t.set\tat\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tlwl\t%0, (%2)\n" \ + "2:\tlwr\t%0, 3(%2)\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadHWU(addr, value, res) \ + __asm__ __volatile__ ( \ + ".set\tnoat\n" \ + "1:\tlbu\t%0, 0(%2)\n" \ + "2:\tlbu\t$1, 1(%2)\n\t" \ + "sll\t%0, 0x8\n\t" \ + "or\t%0, $1\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".set\tat\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadWU(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tlwl\t%0, (%2)\n" \ + "2:\tlwr\t%0, 3(%2)\n\t" \ + "dsll\t%0, %0, 32\n\t" \ + "dsrl\t%0, %0, 32\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + "\t.section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadDW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tldl\t%0, (%2)\n" \ + "2:\tldr\t%0, 7(%2)\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + "\t.section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define StoreHW(addr, value, res) \ + __asm__ __volatile__ ( \ + ".set\tnoat\n" \ + "1:\tsb\t%1, 1(%2)\n\t" \ + "srl\t$1, %1, 0x8\n" \ + "2:\tsb\t$1, 0(%2)\n\t" \ + ".set\tat\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); + +#define StoreW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tswl\t%1,(%2)\n" \ + "2:\tswr\t%1, 3(%2)\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); + +#define StoreDW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tsdl\t%1,(%2)\n" \ + "2:\tsdr\t%1, 7(%2)\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); +#endif + +#ifdef __LITTLE_ENDIAN +#define LoadHW(addr, value, res) \ + __asm__ __volatile__ (".set\tnoat\n" \ + "1:\tlb\t%0, 1(%2)\n" \ + "2:\tlbu\t$1, 0(%2)\n\t" \ + "sll\t%0, 0x8\n\t" \ + "or\t%0, $1\n\t" \ + "li\t%1, 0\n" \ + "3:\t.set\tat\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tlwl\t%0, 3(%2)\n" \ + "2:\tlwr\t%0, (%2)\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadHWU(addr, value, res) \ + __asm__ __volatile__ ( \ + ".set\tnoat\n" \ + "1:\tlbu\t%0, 1(%2)\n" \ + "2:\tlbu\t$1, 0(%2)\n\t" \ + "sll\t%0, 0x8\n\t" \ + "or\t%0, $1\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".set\tat\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadWU(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tlwl\t%0, 3(%2)\n" \ + "2:\tlwr\t%0, (%2)\n\t" \ + "dsll\t%0, %0, 32\n\t" \ + "dsrl\t%0, %0, 32\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + "\t.section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadDW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tldl\t%0, 7(%2)\n" \ + "2:\tldr\t%0, (%2)\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + "\t.section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define StoreHW(addr, value, res) \ + __asm__ __volatile__ ( \ + ".set\tnoat\n" \ + "1:\tsb\t%1, 0(%2)\n\t" \ + "srl\t$1,%1, 0x8\n" \ + "2:\tsb\t$1, 1(%2)\n\t" \ + ".set\tat\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); + +#define StoreW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tswl\t%1, 3(%2)\n" \ + "2:\tswr\t%1, (%2)\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); + +#define StoreDW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tsdl\t%1, 7(%2)\n" \ + "2:\tsdr\t%1, (%2)\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); +#endif + static void emulate_load_store_insn(struct pt_regs *regs, - void __user *addr, unsigned int __user *pc) + void __user *addr, + unsigned int __user *pc) { union mips_instruction insn; unsigned long value; unsigned int res; + unsigned long origpc; + unsigned long orig31; + void __user *fault_addr = NULL; + + origpc = (unsigned long)pc; + orig31 = regs->regs[31]; perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); @@ -120,22 +443,22 @@ static void emulate_load_store_insn(struct pt_regs *regs, __get_user(insn.word, pc); switch (insn.i_format.opcode) { - /* - * These are instructions that a compiler doesn't generate. We - * can assume therefore that the code is MIPS-aware and - * really buggy. Emulating these instructions would break the - * semantics anyway. - */ + /* + * These are instructions that a compiler doesn't generate. We + * can assume therefore that the code is MIPS-aware and + * really buggy. Emulating these instructions would break the + * semantics anyway. + */ case ll_op: case lld_op: case sc_op: case scd_op: - /* - * For these instructions the only way to create an address - * error is an attempted access to kernel/supervisor address - * space. - */ + /* + * For these instructions the only way to create an address + * error is an attempted access to kernel/supervisor address + * space. + */ case ldl_op: case ldr_op: case lwl_op: @@ -149,36 +472,15 @@ static void emulate_load_store_insn(struct pt_regs *regs, case sb_op: goto sigbus; - /* - * The remaining opcodes are the ones that are really of interest. - */ + /* + * The remaining opcodes are the ones that are really of + * interest. + */ case lh_op: if (!access_ok(VERIFY_READ, addr, 2)) goto sigbus; - __asm__ __volatile__ (".set\tnoat\n" -#ifdef __BIG_ENDIAN - "1:\tlb\t%0, 0(%2)\n" - "2:\tlbu\t$1, 1(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tlb\t%0, 1(%2)\n" - "2:\tlbu\t$1, 0(%2)\n\t" -#endif - "sll\t%0, 0x8\n\t" - "or\t%0, $1\n\t" - "li\t%1, 0\n" - "3:\t.set\tat\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadHW(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -189,26 +491,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_READ, addr, 4)) goto sigbus; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tlwl\t%0, (%2)\n" - "2:\tlwr\t%0, 3(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tlwl\t%0, 3(%2)\n" - "2:\tlwr\t%0, (%2)\n\t" -#endif - "li\t%1, 0\n" - "3:\t.section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadW(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -219,30 +502,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_READ, addr, 2)) goto sigbus; - __asm__ __volatile__ ( - ".set\tnoat\n" -#ifdef __BIG_ENDIAN - "1:\tlbu\t%0, 0(%2)\n" - "2:\tlbu\t$1, 1(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tlbu\t%0, 1(%2)\n" - "2:\tlbu\t$1, 0(%2)\n\t" -#endif - "sll\t%0, 0x8\n\t" - "or\t%0, $1\n\t" - "li\t%1, 0\n" - "3:\t.set\tat\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadHWU(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -261,28 +521,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_READ, addr, 4)) goto sigbus; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tlwl\t%0, (%2)\n" - "2:\tlwr\t%0, 3(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tlwl\t%0, 3(%2)\n" - "2:\tlwr\t%0, (%2)\n\t" -#endif - "dsll\t%0, %0, 32\n\t" - "dsrl\t%0, %0, 32\n\t" - "li\t%1, 0\n" - "3:\t.section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadWU(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -305,26 +544,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_READ, addr, 8)) goto sigbus; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tldl\t%0, (%2)\n" - "2:\tldr\t%0, 7(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tldl\t%0, 7(%2)\n" - "2:\tldr\t%0, (%2)\n\t" -#endif - "li\t%1, 0\n" - "3:\t.section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadDW(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -339,68 +559,22 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, addr, 2)) goto sigbus; + compute_return_epc(regs); value = regs->regs[insn.i_format.rt]; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - ".set\tnoat\n" - "1:\tsb\t%1, 1(%2)\n\t" - "srl\t$1, %1, 0x8\n" - "2:\tsb\t$1, 0(%2)\n\t" - ".set\tat\n\t" -#endif -#ifdef __LITTLE_ENDIAN - ".set\tnoat\n" - "1:\tsb\t%1, 0(%2)\n\t" - "srl\t$1,%1, 0x8\n" - "2:\tsb\t$1, 1(%2)\n\t" - ".set\tat\n\t" -#endif - "li\t%0, 0\n" - "3:\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%0, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=r" (res) - : "r" (value), "r" (addr), "i" (-EFAULT)); + StoreHW(addr, value, res); if (res) goto fault; - compute_return_epc(regs); break; case sw_op: if (!access_ok(VERIFY_WRITE, addr, 4)) goto sigbus; + compute_return_epc(regs); value = regs->regs[insn.i_format.rt]; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tswl\t%1,(%2)\n" - "2:\tswr\t%1, 3(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tswl\t%1, 3(%2)\n" - "2:\tswr\t%1, (%2)\n\t" -#endif - "li\t%0, 0\n" - "3:\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%0, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=r" (res) - : "r" (value), "r" (addr), "i" (-EFAULT)); + StoreW(addr, value, res); if (res) goto fault; - compute_return_epc(regs); break; case sd_op: @@ -415,31 +589,11 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, addr, 8)) goto sigbus; + compute_return_epc(regs); value = regs->regs[insn.i_format.rt]; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tsdl\t%1,(%2)\n" - "2:\tsdr\t%1, 7(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tsdl\t%1, 7(%2)\n" - "2:\tsdr\t%1, (%2)\n\t" -#endif - "li\t%0, 0\n" - "3:\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%0, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=r" (res) - : "r" (value), "r" (addr), "i" (-EFAULT)); + StoreDW(addr, value, res); if (res) goto fault; - compute_return_epc(regs); break; #endif /* CONFIG_64BIT */ @@ -450,10 +604,21 @@ static void emulate_load_store_insn(struct pt_regs *regs, case ldc1_op: case swc1_op: case sdc1_op: - /* - * I herewith declare: this does not happen. So send SIGBUS. - */ - goto sigbus; + die_if_kernel("Unaligned FP access in kernel code", regs); + BUG_ON(!used_math()); + BUG_ON(!is_fpu_owner()); + + lose_fpu(1); /* save the FPU state for the emulator */ + res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, + &fault_addr); + own_fpu(1); /* restore FPU state */ + + /* If something went wrong, signal */ + process_fpemu_return(res, fault_addr); + + if (res == 0) + break; + return; /* * COP2 is available to implementor for application specific use. @@ -491,6 +656,9 @@ static void emulate_load_store_insn(struct pt_regs *regs, return; fault: + /* roll back jump/branch */ + regs->cp0_epc = origpc; + regs->regs[31] = orig31; /* Did we have an exception handler installed? */ if (fixup_exception(regs)) return; @@ -507,7 +675,879 @@ sigbus: return; sigill: - die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); + die_if_kernel + ("Unhandled kernel unaligned access or invalid instruction", regs); + force_sig(SIGILL, current); +} + +/* recode table from micromips register notation to GPR */ +static int mmreg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + +/* recode table from micromips STORE register notation to GPR */ +static int mmreg16to32_st[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; + +void emulate_load_store_microMIPS(struct pt_regs *regs, void __user * addr) +{ + unsigned long value; + unsigned int res; + int i; + unsigned int reg = 0, rvar; + unsigned long orig31; + u16 __user *pc16; + u16 halfword; + unsigned int word; + unsigned long origpc, contpc; + union mips_instruction insn; + struct decoded_instn mminst; + void __user *fault_addr = NULL; + + origpc = regs->cp0_epc; + orig31 = regs->regs[31]; + + mminst.micro_mips_mode = 1; + + /* + * This load never faults. + */ + pc16 = (unsigned short __user *)(regs->cp0_epc & ~MIPS_ISA_MODE); + __get_user(halfword, pc16); + pc16++; + contpc = regs->cp0_epc + 2; + word = ((unsigned int)halfword << 16); + mminst.pc_inc = 2; + + if (!mm_is16bit(halfword)) { + __get_user(halfword, pc16); + pc16++; + contpc = regs->cp0_epc + 4; + mminst.pc_inc = 4; + word |= halfword; + } + mminst.insn = word; + + if (get_user(halfword, pc16)) + goto fault; + mminst.next_pc_inc = 2; + word = ((unsigned int)halfword << 16); + + if (!mm_is16bit(halfword)) { + pc16++; + if (get_user(halfword, pc16)) + goto fault; + mminst.next_pc_inc = 4; + word |= halfword; + } + mminst.next_insn = word; + + insn = (union mips_instruction)(mminst.insn); + if (mm_isBranchInstr(regs, mminst, &contpc)) + insn = (union mips_instruction)(mminst.next_insn); + + /* Parse instruction to find what to do */ + + switch (insn.mm_i_format.opcode) { + + case mm_pool32a_op: + switch (insn.mm_x_format.func) { + case mm_lwxs_op: + reg = insn.mm_x_format.rd; + goto loadW; + } + + goto sigbus; + + case mm_pool32b_op: + switch (insn.mm_m_format.func) { + case mm_lwp_func: + reg = insn.mm_m_format.rd; + if (reg == 31) + goto sigbus; + + if (!access_ok(VERIFY_READ, addr, 8)) + goto sigbus; + + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + addr += 4; + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[reg + 1] = value; + goto success; + + case mm_swp_func: + reg = insn.mm_m_format.rd; + if (reg == 31) + goto sigbus; + + if (!access_ok(VERIFY_WRITE, addr, 8)) + goto sigbus; + + value = regs->regs[reg]; + StoreW(addr, value, res); + if (res) + goto fault; + addr += 4; + value = regs->regs[reg + 1]; + StoreW(addr, value, res); + if (res) + goto fault; + goto success; + + case mm_ldp_func: +#ifdef CONFIG_64BIT + reg = insn.mm_m_format.rd; + if (reg == 31) + goto sigbus; + + if (!access_ok(VERIFY_READ, addr, 16)) + goto sigbus; + + LoadDW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + addr += 8; + LoadDW(addr, value, res); + if (res) + goto fault; + regs->regs[reg + 1] = value; + goto success; +#endif /* CONFIG_64BIT */ + + goto sigill; + + case mm_sdp_func: +#ifdef CONFIG_64BIT + reg = insn.mm_m_format.rd; + if (reg == 31) + goto sigbus; + + if (!access_ok(VERIFY_WRITE, addr, 16)) + goto sigbus; + + value = regs->regs[reg]; + StoreDW(addr, value, res); + if (res) + goto fault; + addr += 8; + value = regs->regs[reg + 1]; + StoreDW(addr, value, res); + if (res) + goto fault; + goto success; +#endif /* CONFIG_64BIT */ + + goto sigill; + + case mm_lwm32_func: + reg = insn.mm_m_format.rd; + rvar = reg & 0xf; + if ((rvar > 9) || !reg) + goto sigill; + if (reg & 0x10) { + if (!access_ok + (VERIFY_READ, addr, 4 * (rvar + 1))) + goto sigbus; + } else { + if (!access_ok(VERIFY_READ, addr, 4 * rvar)) + goto sigbus; + } + if (rvar == 9) + rvar = 8; + for (i = 16; rvar; rvar--, i++) { + LoadW(addr, value, res); + if (res) + goto fault; + addr += 4; + regs->regs[i] = value; + } + if ((reg & 0xf) == 9) { + LoadW(addr, value, res); + if (res) + goto fault; + addr += 4; + regs->regs[30] = value; + } + if (reg & 0x10) { + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[31] = value; + } + goto success; + + case mm_swm32_func: + reg = insn.mm_m_format.rd; + rvar = reg & 0xf; + if ((rvar > 9) || !reg) + goto sigill; + if (reg & 0x10) { + if (!access_ok + (VERIFY_WRITE, addr, 4 * (rvar + 1))) + goto sigbus; + } else { + if (!access_ok(VERIFY_WRITE, addr, 4 * rvar)) + goto sigbus; + } + if (rvar == 9) + rvar = 8; + for (i = 16; rvar; rvar--, i++) { + value = regs->regs[i]; + StoreW(addr, value, res); + if (res) + goto fault; + addr += 4; + } + if ((reg & 0xf) == 9) { + value = regs->regs[30]; + StoreW(addr, value, res); + if (res) + goto fault; + addr += 4; + } + if (reg & 0x10) { + value = regs->regs[31]; + StoreW(addr, value, res); + if (res) + goto fault; + } + goto success; + + case mm_ldm_func: +#ifdef CONFIG_64BIT + reg = insn.mm_m_format.rd; + rvar = reg & 0xf; + if ((rvar > 9) || !reg) + goto sigill; + if (reg & 0x10) { + if (!access_ok + (VERIFY_READ, addr, 8 * (rvar + 1))) + goto sigbus; + } else { + if (!access_ok(VERIFY_READ, addr, 8 * rvar)) + goto sigbus; + } + if (rvar == 9) + rvar = 8; + + for (i = 16; rvar; rvar--, i++) { + LoadDW(addr, value, res); + if (res) + goto fault; + addr += 4; + regs->regs[i] = value; + } + if ((reg & 0xf) == 9) { + LoadDW(addr, value, res); + if (res) + goto fault; + addr += 8; + regs->regs[30] = value; + } + if (reg & 0x10) { + LoadDW(addr, value, res); + if (res) + goto fault; + regs->regs[31] = value; + } + goto success; +#endif /* CONFIG_64BIT */ + + goto sigill; + + case mm_sdm_func: +#ifdef CONFIG_64BIT + reg = insn.mm_m_format.rd; + rvar = reg & 0xf; + if ((rvar > 9) || !reg) + goto sigill; + if (reg & 0x10) { + if (!access_ok + (VERIFY_WRITE, addr, 8 * (rvar + 1))) + goto sigbus; + } else { + if (!access_ok(VERIFY_WRITE, addr, 8 * rvar)) + goto sigbus; + } + if (rvar == 9) + rvar = 8; + + for (i = 16; rvar; rvar--, i++) { + value = regs->regs[i]; + StoreDW(addr, value, res); + if (res) + goto fault; + addr += 8; + } + if ((reg & 0xf) == 9) { + value = regs->regs[30]; + StoreDW(addr, value, res); + if (res) + goto fault; + addr += 8; + } + if (reg & 0x10) { + value = regs->regs[31]; + StoreDW(addr, value, res); + if (res) + goto fault; + } + goto success; +#endif /* CONFIG_64BIT */ + + goto sigill; + + /* LWC2, SWC2, LDC2, SDC2 are not serviced */ + } + + goto sigbus; + + case mm_pool32c_op: + switch (insn.mm_m_format.func) { + case mm_lwu_func: + reg = insn.mm_m_format.rd; + goto loadWU; + } + + /* LL,SC,LLD,SCD are not serviced */ + goto sigbus; + + case mm_pool32f_op: + switch (insn.mm_x_format.func) { + case mm_lwxc1_func: + case mm_swxc1_func: + case mm_ldxc1_func: + case mm_sdxc1_func: + goto fpu_emul; + } + + goto sigbus; + + case mm_ldc132_op: + case mm_sdc132_op: + case mm_lwc132_op: + case mm_swc132_op: +fpu_emul: + /* roll back jump/branch */ + regs->cp0_epc = origpc; + regs->regs[31] = orig31; + + die_if_kernel("Unaligned FP access in kernel code", regs); + BUG_ON(!used_math()); + BUG_ON(!is_fpu_owner()); + + lose_fpu(1); /* save the FPU state for the emulator */ + res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, + &fault_addr); + own_fpu(1); /* restore FPU state */ + + /* If something went wrong, signal */ + process_fpemu_return(res, fault_addr); + + if (res == 0) + goto success; + return; + + case mm_lh32_op: + reg = insn.mm_i_format.rt; + goto loadHW; + + case mm_lhu32_op: + reg = insn.mm_i_format.rt; + goto loadHWU; + + case mm_lw32_op: + reg = insn.mm_i_format.rt; + goto loadW; + + case mm_sh32_op: + reg = insn.mm_i_format.rt; + goto storeHW; + + case mm_sw32_op: + reg = insn.mm_i_format.rt; + goto storeW; + + case mm_ld32_op: + reg = insn.mm_i_format.rt; + goto loadDW; + + case mm_sd32_op: + reg = insn.mm_i_format.rt; + goto storeDW; + + case mm_pool16c_op: + switch (insn.mm16_m_format.func) { + case mm_lwm16_op: + reg = insn.mm16_m_format.rlist; + rvar = reg + 1; + if (!access_ok(VERIFY_READ, addr, 4 * rvar)) + goto sigbus; + + for (i = 16; rvar; rvar--, i++) { + LoadW(addr, value, res); + if (res) + goto fault; + addr += 4; + regs->regs[i] = value; + } + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[31] = value; + + goto success; + + case mm_swm16_op: + reg = insn.mm16_m_format.rlist; + rvar = reg + 1; + if (!access_ok(VERIFY_WRITE, addr, 4 * rvar)) + goto sigbus; + + for (i = 16; rvar; rvar--, i++) { + value = regs->regs[i]; + StoreW(addr, value, res); + if (res) + goto fault; + addr += 4; + } + value = regs->regs[31]; + StoreW(addr, value, res); + if (res) + goto fault; + + goto success; + + } + + goto sigbus; + + case mm_lhu16_op: + reg = mmreg16to32[insn.mm16_rb_format.rt]; + goto loadHWU; + + case mm_lw16_op: + reg = mmreg16to32[insn.mm16_rb_format.rt]; + goto loadW; + + case mm_sh16_op: + reg = mmreg16to32_st[insn.mm16_rb_format.rt]; + goto storeHW; + + case mm_sw16_op: + reg = mmreg16to32_st[insn.mm16_rb_format.rt]; + goto storeW; + + case mm_lwsp16_op: + reg = insn.mm16_r5_format.rt; + goto loadW; + + case mm_swsp16_op: + reg = insn.mm16_r5_format.rt; + goto storeW; + + case mm_lwgp16_op: + reg = mmreg16to32[insn.mm16_r3_format.rt]; + goto loadW; + + default: + goto sigill; + } + +loadHW: + if (!access_ok(VERIFY_READ, addr, 2)) + goto sigbus; + + LoadHW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; + +loadHWU: + if (!access_ok(VERIFY_READ, addr, 2)) + goto sigbus; + + LoadHWU(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; + +loadW: + if (!access_ok(VERIFY_READ, addr, 4)) + goto sigbus; + + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; + +loadWU: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_READ, addr, 4)) + goto sigbus; + + LoadWU(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + +loadDW: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_READ, addr, 8)) + goto sigbus; + + LoadDW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + +storeHW: + if (!access_ok(VERIFY_WRITE, addr, 2)) + goto sigbus; + + value = regs->regs[reg]; + StoreHW(addr, value, res); + if (res) + goto fault; + goto success; + +storeW: + if (!access_ok(VERIFY_WRITE, addr, 4)) + goto sigbus; + + value = regs->regs[reg]; + StoreW(addr, value, res); + if (res) + goto fault; + goto success; + +storeDW: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_WRITE, addr, 8)) + goto sigbus; + + value = regs->regs[reg]; + StoreDW(addr, value, res); + if (res) + goto fault; + goto success; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + +success: + regs->cp0_epc = contpc; /* advance or branch */ + +#ifdef CONFIG_DEBUG_FS + unaligned_instructions++; +#endif + return; + +fault: + /* roll back jump/branch */ + regs->cp0_epc = origpc; + regs->regs[31] = orig31; + /* Did we have an exception handler installed? */ + if (fixup_exception(regs)) + return; + + die_if_kernel("Unhandled kernel unaligned access", regs); + force_sig(SIGSEGV, current); + + return; + +sigbus: + die_if_kernel("Unhandled kernel unaligned access", regs); + force_sig(SIGBUS, current); + + return; + +sigill: + die_if_kernel + ("Unhandled kernel unaligned access or invalid instruction", regs); + force_sig(SIGILL, current); +} + +static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr) +{ + unsigned long value; + unsigned int res; + int reg; + unsigned long orig31; + u16 __user *pc16; + unsigned long origpc; + union mips16e_instruction mips16inst, oldinst; + + origpc = regs->cp0_epc; + orig31 = regs->regs[31]; + pc16 = (unsigned short __user *)(origpc & ~MIPS_ISA_MODE); + /* + * This load never faults. + */ + __get_user(mips16inst.full, pc16); + oldinst = mips16inst; + + /* skip EXTEND instruction */ + if (mips16inst.ri.opcode == MIPS16e_extend_op) { + pc16++; + __get_user(mips16inst.full, pc16); + } else if (delay_slot(regs)) { + /* skip jump instructions */ + /* JAL/JALX are 32 bits but have OPCODE in first short int */ + if (mips16inst.ri.opcode == MIPS16e_jal_op) + pc16++; + pc16++; + if (get_user(mips16inst.full, pc16)) + goto sigbus; + } + + switch (mips16inst.ri.opcode) { + case MIPS16e_i64_op: /* I64 or RI64 instruction */ + switch (mips16inst.i64.func) { /* I64/RI64 func field check */ + case MIPS16e_ldpc_func: + case MIPS16e_ldsp_func: + reg = mips16e_reg2gpr[mips16inst.ri64.ry]; + goto loadDW; + + case MIPS16e_sdsp_func: + reg = mips16e_reg2gpr[mips16inst.ri64.ry]; + goto writeDW; + + case MIPS16e_sdrasp_func: + reg = 29; /* GPRSP */ + goto writeDW; + } + + goto sigbus; + + case MIPS16e_swsp_op: + case MIPS16e_lwpc_op: + case MIPS16e_lwsp_op: + reg = mips16e_reg2gpr[mips16inst.ri.rx]; + break; + + case MIPS16e_i8_op: + if (mips16inst.i8.func != MIPS16e_swrasp_func) + goto sigbus; + reg = 29; /* GPRSP */ + break; + + default: + reg = mips16e_reg2gpr[mips16inst.rri.ry]; + break; + } + + switch (mips16inst.ri.opcode) { + + case MIPS16e_lb_op: + case MIPS16e_lbu_op: + case MIPS16e_sb_op: + goto sigbus; + + case MIPS16e_lh_op: + if (!access_ok(VERIFY_READ, addr, 2)) + goto sigbus; + + LoadHW(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; + + case MIPS16e_lhu_op: + if (!access_ok(VERIFY_READ, addr, 2)) + goto sigbus; + + LoadHWU(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; + + case MIPS16e_lw_op: + case MIPS16e_lwpc_op: + case MIPS16e_lwsp_op: + if (!access_ok(VERIFY_READ, addr, 4)) + goto sigbus; + + LoadW(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; + + case MIPS16e_lwu_op: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_READ, addr, 4)) + goto sigbus; + + LoadWU(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + + case MIPS16e_ld_op: +loadDW: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_READ, addr, 8)) + goto sigbus; + + LoadDW(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + + case MIPS16e_sh_op: + if (!access_ok(VERIFY_WRITE, addr, 2)) + goto sigbus; + + MIPS16e_compute_return_epc(regs, &oldinst); + value = regs->regs[reg]; + StoreHW(addr, value, res); + if (res) + goto fault; + break; + + case MIPS16e_sw_op: + case MIPS16e_swsp_op: + case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */ + if (!access_ok(VERIFY_WRITE, addr, 4)) + goto sigbus; + + MIPS16e_compute_return_epc(regs, &oldinst); + value = regs->regs[reg]; + StoreW(addr, value, res); + if (res) + goto fault; + break; + + case MIPS16e_sd_op: +writeDW: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_WRITE, addr, 8)) + goto sigbus; + + MIPS16e_compute_return_epc(regs, &oldinst); + value = regs->regs[reg]; + StoreDW(addr, value, res); + if (res) + goto fault; + break; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + + default: + /* + * Pheeee... We encountered an yet unknown instruction or + * cache coherence problem. Die sucker, die ... + */ + goto sigill; + } + +#ifdef CONFIG_DEBUG_FS + unaligned_instructions++; +#endif + + return; + +fault: + /* roll back jump/branch */ + regs->cp0_epc = origpc; + regs->regs[31] = orig31; + /* Did we have an exception handler installed? */ + if (fixup_exception(regs)) + return; + + die_if_kernel("Unhandled kernel unaligned access", regs); + force_sig(SIGSEGV, current); + + return; + +sigbus: + die_if_kernel("Unhandled kernel unaligned access", regs); + force_sig(SIGBUS, current); + + return; + +sigill: + die_if_kernel + ("Unhandled kernel unaligned access or invalid instruction", regs); force_sig(SIGILL, current); } @@ -520,23 +1560,64 @@ asmlinkage void do_ade(struct pt_regs *regs) 1, regs, regs->cp0_badvaddr); /* * Did we catch a fault trying to load an instruction? - * Or are we running in MIPS16 mode? */ - if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1)) + if (regs->cp0_badvaddr == regs->cp0_epc) goto sigbus; - pc = (unsigned int __user *) exception_epc(regs); if (user_mode(regs) && !test_thread_flag(TIF_FIXADE)) goto sigbus; if (unaligned_action == UNALIGNED_ACTION_SIGNAL) goto sigbus; - else if (unaligned_action == UNALIGNED_ACTION_SHOW) - show_registers(regs); /* * Do branch emulation only if we didn't forward the exception. * This is all so but ugly ... */ + + /* + * Are we running in MIPS16e/microMIPS mode? + */ + if (is16mode(regs)) { + /* + * Did we catch a fault trying to load an instruction in + * 16bit mode? + */ + if (regs->cp0_badvaddr == (regs->cp0_epc & ~MIPS_ISA_MODE)) + goto sigbus; + if (unaligned_action == UNALIGNED_ACTION_SHOW) + show_registers(regs); + + if (cpu_has_mips16) { + seg = get_fs(); + if (!user_mode(regs)) + set_fs(KERNEL_DS); + emulate_load_store_MIPS16e(regs, + (void __user *)regs-> + cp0_badvaddr); + set_fs(seg); + + return; + } + + if (cpu_has_mmips) { /* micromips unaligned access */ + seg = get_fs(); + if (!user_mode(regs)) + set_fs(KERNEL_DS); + emulate_load_store_microMIPS(regs, + (void __user *)regs-> + cp0_badvaddr); + set_fs(seg); + + return; + } + + goto sigbus; + } + + if (unaligned_action == UNALIGNED_ACTION_SHOW) + show_registers(regs); + pc = (unsigned int __user *)exception_epc(regs); + seg = get_fs(); if (!user_mode(regs)) set_fs(KERNEL_DS); -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:08:34 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60321 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824774Ab2LGFFyw8Axs (ORCPT ); Fri, 7 Dec 2012 06:05:54 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8C-0007MA-Dj; Thu, 06 Dec 2012 23:05:48 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,08/13] MIPS: microMIPS: Add configuration option for microMIPS kernel. Date: Thu, 6 Dec 2012 23:05:32 -0600 Message-Id: <1354856737-28678-9-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35219 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6040 Lines: 212 From: "Steven J. Hill" This adds the option to build the Linux kernel using only the microMIPS ISA. The resulting kernel binary is, at a minimum, 20% smaller than using the MIPS32R2 ISA. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 11 +++ arch/mips/Makefile | 1 + arch/mips/configs/sead3micro_defconfig | 125 ++++++++++++++++++++++++++++++++ arch/mips/kernel/proc.c | 4 + 4 files changed, 141 insertions(+) create mode 100644 arch/mips/configs/sead3micro_defconfig diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 99c3ad7..07f2dff 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -350,6 +350,7 @@ config MIPS_SEAD3 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_SMARTMIPS + select SYS_SUPPORTS_MICROMIPS select USB_ARCH_HAS_EHCI select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO @@ -2087,6 +2088,13 @@ config CPU_HAS_SMARTMIPS you don't know you probably don't have SmartMIPS and should say N here. +config CPU_MICROMIPS + depends on SYS_SUPPORTS_MICROMIPS + bool "Build kernel using microMIPS ISA" + help + When this option is enabled the kernel will be built using the + microMIPS ISA + config CPU_HAS_WB bool @@ -2149,6 +2157,9 @@ config SYS_SUPPORTS_HIGHMEM config SYS_SUPPORTS_SMARTMIPS bool +config SYS_SUPPORTS_MICROMIPS + bool + config ARCH_FLATMEM_ENABLE def_bool y depends on !NUMA && !CPU_LOONGSON2 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 654b1ad..6f829de6 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -114,6 +114,7 @@ cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*e cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le)) cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips) +cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips -mno-jals) cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ -fno-omit-frame-pointer diff --git a/arch/mips/configs/sead3micro_defconfig b/arch/mips/configs/sead3micro_defconfig new file mode 100644 index 0000000..403332f --- /dev/null +++ b/arch/mips/configs/sead3micro_defconfig @@ -0,0 +1,125 @@ +CONFIG_MIPS_SEAD3=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MICROMIPS=y +CONFIG_HZ_100=y +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_ICPLUS_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_CONSOLE_TRANSLATIONS is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=32 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_SPI=y +CONFIG_SENSORS_ADT7475=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_M41T80=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +# CONFIG_FTRACE is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 239ae03..54ac39a 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -76,6 +76,10 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); seq_printf(m, "\n"); + if (cpu_has_mmips) { + seq_printf(m, "micromips kernel\t: %s\n", + (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); + } seq_printf(m, "shadow register sets\t: %d\n", cpu_data[n].srsets); seq_printf(m, "kscratch registers\t: %d\n", -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:05:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:08:52 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60323 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824804Ab2LGFFzGnwJP (ORCPT ); Fri, 7 Dec 2012 06:05:55 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8C-0007MA-Ul; Thu, 06 Dec 2012 23:05:48 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,09/13] MIPS: microMIPS: Work-around for assembler bug. Date: Thu, 6 Dec 2012 23:05:33 -0600 Message-Id: <1354856737-28678-10-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35220 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2579 Lines: 88 From: "Steven J. Hill" When building a microMIPS instructions only kernel, the linker complains about ISA mode switches in the .fixup section. We explicitly add the .insn assembler directive to address this. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/uaccess.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index 3b92efe..d2f99ba 100644 --- a/arch/mips/include/asm/uaccess.h +++ b/arch/mips/include/asm/uaccess.h @@ -261,6 +261,7 @@ do { \ __asm__ __volatile__( \ "1: " insn " %1, %3 \n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -287,7 +288,9 @@ do { \ __asm__ __volatile__( \ "1: lw %1, (%3) \n" \ "2: lw %D1, 4(%3) \n" \ - "3: .section .fixup,\"ax\" \n" \ + "3: \n" \ + " .insn \n" \ + " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " move %1, $0 \n" \ " move %D1, $0 \n" \ @@ -355,6 +358,7 @@ do { \ __asm__ __volatile__( \ "1: " insn " %z2, %3 # __put_user_asm\n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -373,6 +377,7 @@ do { \ "1: sw %2, (%3) # __put_user_asm_ll32 \n" \ "2: sw %D2, 4(%3) \n" \ "3: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " j 3b \n" \ @@ -524,6 +529,7 @@ do { \ __asm__ __volatile__( \ "1: " insn " %1, %3 \n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -549,7 +555,9 @@ do { \ "1: ulw %1, (%3) \n" \ "2: ulw %D1, 4(%3) \n" \ " move %0, $0 \n" \ - "3: .section .fixup,\"ax\" \n" \ + "3: \n" \ + " .insn \n" \ + " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " move %1, $0 \n" \ " move %D1, $0 \n" \ @@ -616,6 +624,7 @@ do { \ __asm__ __volatile__( \ "1: " insn " %z2, %3 # __put_user_unaligned_asm\n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -634,6 +643,7 @@ do { \ "1: sw %2, (%3) # __put_user_unaligned_asm_ll32 \n" \ "2: sw %D2, 4(%3) \n" \ "3: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " j 3b \n" \ -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:09:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:09:12 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60335 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823674Ab2LGFJJr93AX (ORCPT ); Fri, 7 Dec 2012 06:09:09 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8D-0007MA-Ts; Thu, 06 Dec 2012 23:05:49 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,11/13] MIPS: microMIPS: Optimise 'strncpy' core library function. Date: Thu, 6 Dec 2012 23:05:35 -0600 Message-Id: <1354856737-28678-12-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35221 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1608 Lines: 64 From: "Steven J. Hill" Optimise 'strncpy' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill --- arch/mips/lib/strncpy_user.S | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/mips/lib/strncpy_user.S b/arch/mips/lib/strncpy_user.S index 7201b2f..dea9304 100644 --- a/arch/mips/lib/strncpy_user.S +++ b/arch/mips/lib/strncpy_user.S @@ -3,7 +3,8 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1996, 1999 by Ralf Baechle + * Copyright (C) 1996, 1999 by Ralf Baechle + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include #include @@ -33,22 +34,23 @@ LEAF(__strncpy_from_user_asm) bnez v0, .Lfault FEXPORT(__strncpy_from_user_nocheck_asm) - move v0, zero - move v1, a1 .set noreorder -1: EX(lbu, t0, (v1), .Lfault) + move t0, zero + move v1, a1 +1: EX(lbu, v0, (v1), .Lfault) PTR_ADDIU v1, 1 R10KCBARRIER(0(ra)) - beqz t0, 2f - sb t0, (a0) - PTR_ADDIU v0, 1 - .set reorder - PTR_ADDIU a0, 1 - bne v0, a2, 1b -2: PTR_ADDU t0, a1, v0 - xor t0, a1 - bltz t0, .Lfault + beqz v0, 2f + sb v0, (a0) + PTR_ADDIU t0, 1 + bne t0, a2, 1b + PTR_ADDIU a0, 1 +2: PTR_ADDU v0, a1, t0 + xor v0, a1 + bltz v0, .Lfault + nop jr ra # return n + move v0, t0 END(__strncpy_from_user_asm) .Lfault: li v0, -EFAULT -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:09:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:09:31 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60337 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824759Ab2LGFJQB440G (ORCPT ); Fri, 7 Dec 2012 06:09:16 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8D-0007MA-Cy; Thu, 06 Dec 2012 23:05:49 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,10/13] MIPS: microMIPS: Optimise 'memset' core library function. Date: Thu, 6 Dec 2012 23:05:34 -0600 Message-Id: <1354856737-28678-11-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35222 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6225 Lines: 197 From: "Steven J. Hill" Optimise 'memset' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/asm.h | 2 ++ arch/mips/lib/memset.S | 84 +++++++++++++++++++++++++++---------------- 2 files changed, 56 insertions(+), 30 deletions(-) diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 608cfcf..604788f 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -296,6 +296,7 @@ symbol = value #define LONG_SUBU subu #define LONG_L lw #define LONG_S sw +#define LONG_SP swp #define LONG_SLL sll #define LONG_SLLV sllv #define LONG_SRL srl @@ -318,6 +319,7 @@ symbol = value #define LONG_SUBU dsubu #define LONG_L ld #define LONG_S sd +#define LONG_SP sdp #define LONG_SLL dsll #define LONG_SLLV dsllv #define LONG_SRL dsrl diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S index 606c8a9..cf63df8 100644 --- a/arch/mips/lib/memset.S +++ b/arch/mips/lib/memset.S @@ -5,7 +5,8 @@ * * Copyright (C) 1998, 1999, 2000 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki + * Copyright (C) 2007 by Maciej W. Rozycki + * Copyright (C) 2011, 2012 MIPS Technologies, Inc. */ #include #include @@ -19,6 +20,20 @@ #define LONG_S_R sdr #endif +#ifdef CONFIG_CPU_MICROMIPS +#define STORSIZE (LONGSIZE * 2) +#define STORMASK (STORSIZE - 1) +#define FILL64RG t8 +#define FILLPTRG t7 +#undef LONG_S +#define LONG_S LONG_SP +#else +#define STORSIZE LONGSIZE +#define STORMASK LONGMASK +#define FILL64RG a1 +#define FILLPTRG t0 +#endif + #define EX(insn,reg,addr,handler) \ 9: insn reg, addr; \ .section __ex_table,"a"; \ @@ -26,23 +41,25 @@ .previous .macro f_fill64 dst, offset, val, fixup - EX(LONG_S, \val, (\offset + 0 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 1 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 2 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 3 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 4 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 5 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 6 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 7 * LONGSIZE)(\dst), \fixup) -#if LONGSIZE == 4 - EX(LONG_S, \val, (\offset + 8 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 9 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 10 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 11 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 12 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 13 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 14 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 15 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup) +#if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS)) + EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup) +#endif +#if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) + EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup) #endif .endm @@ -71,16 +88,20 @@ LEAF(memset) 1: FEXPORT(__bzero) - sltiu t0, a2, LONGSIZE /* very small region? */ + sltiu t0, a2, STORSIZE /* very small region? */ bnez t0, .Lsmall_memset - andi t0, a0, LONGMASK /* aligned? */ + andi t0, a0, STORMASK /* aligned? */ +#ifdef CONFIG_CPU_MICROMIPS + move t8, a1 /* used by 'swp' instruction */ + move t9, a1 +#endif #ifndef CONFIG_CPU_DADDI_WORKAROUNDS beqz t0, 1f - PTR_SUBU t0, LONGSIZE /* alignment in bytes */ + PTR_SUBU t0, STORSIZE /* alignment in bytes */ #else .set noat - li AT, LONGSIZE + li AT, STORSIZE beqz t0, 1f PTR_SUBU t0, AT /* alignment in bytes */ .set at @@ -99,24 +120,27 @@ FEXPORT(__bzero) 1: ori t1, a2, 0x3f /* # of full blocks */ xori t1, 0x3f beqz t1, .Lmemset_partial /* no block to fill */ - andi t0, a2, 0x40-LONGSIZE + andi t0, a2, 0x40-STORSIZE PTR_ADDU t1, a0 /* end address */ .set reorder 1: PTR_ADDIU a0, 64 R10KCBARRIER(0(ra)) - f_fill64 a0, -64, a1, .Lfwd_fixup + f_fill64 a0, -64, FILL64RG, .Lfwd_fixup bne t1, a0, 1b .set noreorder .Lmemset_partial: R10KCBARRIER(0(ra)) PTR_LA t1, 2f /* where to start */ +#ifdef CONFIG_CPU_MICROMIPS + LONG_SRL t7, t0, 1 +#endif #if LONGSIZE == 4 - PTR_SUBU t1, t0 + PTR_SUBU t1, FILLPTRG #else .set noat - LONG_SRL AT, t0, 1 + LONG_SRL AT, FILLPTRG, 1 PTR_SUBU t1, AT .set at #endif @@ -126,9 +150,9 @@ FEXPORT(__bzero) .set push .set noreorder .set nomacro - f_fill64 a0, -64, a1, .Lpartial_fixup /* ... but first do longs ... */ + f_fill64 a0, -64, FILL64RG, .Lpartial_fixup /* ... but first do longs ... */ 2: .set pop - andi a2, LONGMASK /* At most one long to go */ + andi a2, STORMASK /* At most one long to go */ beqz a2, 1f PTR_ADDU a0, a2 /* What's left */ @@ -169,7 +193,7 @@ FEXPORT(__bzero) .Lpartial_fixup: PTR_L t0, TI_TASK($28) - andi a2, LONGMASK + andi a2, STORMASK LONG_L t0, THREAD_BUADDR(t0) LONG_ADDU a2, t1 jr ra @@ -177,4 +201,4 @@ FEXPORT(__bzero) .Llast_fixup: jr ra - andi v1, a2, LONGMASK + andi v1, a2, STORMASK -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:09:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:09:49 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60340 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823707Ab2LGFJXUAsdg (ORCPT ); Fri, 7 Dec 2012 06:09:23 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8F-0007MA-0J; Thu, 06 Dec 2012 23:05:51 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,13/13] MIPS: microMIPS: Optimise 'strnlen' core library function. Date: Thu, 6 Dec 2012 23:05:37 -0600 Message-Id: <1354856737-28678-14-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35223 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 801 Lines: 27 From: "Steven J. Hill" Optimise 'strnlen' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill --- arch/mips/lib/strnlen_user.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S index 6445716..c5bdf8b 100644 --- a/arch/mips/lib/strnlen_user.S +++ b/arch/mips/lib/strnlen_user.S @@ -35,7 +35,7 @@ FEXPORT(__strnlen_user_nocheck_asm) PTR_ADDU a1, a0 # stop pointer 1: beq v0, a1, 1f # limit reached? EX(lb, t0, (v0), .Lfault) - PTR_ADDU v0, 1 + PTR_ADDIU v0, 1 bnez t0, 1b 1: PTR_SUBU v0, a0 jr ra -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:09:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:10:07 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60341 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824766Ab2LGFJ3XWfXa (ORCPT ); Fri, 7 Dec 2012 06:09:29 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tgq8E-0007MA-Fn; Thu, 06 Dec 2012 23:05:50 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v99,12/13] MIPS: microMIPS: Optimise 'strlen' core library function. Date: Thu, 6 Dec 2012 23:05:36 -0600 Message-Id: <1354856737-28678-13-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354856737-28678-1-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> X-archive-position: 35224 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1253 Lines: 42 From: "Steven J. Hill" Optimise 'strlen' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill --- arch/mips/lib/strlen_user.S | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/mips/lib/strlen_user.S b/arch/mips/lib/strlen_user.S index fdbb970..e362dcd 100644 --- a/arch/mips/lib/strlen_user.S +++ b/arch/mips/lib/strlen_user.S @@ -3,8 +3,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1996, 1998, 1999, 2004 by Ralf Baechle - * Copyright (c) 1999 Silicon Graphics, Inc. + * Copyright (C) 1996, 1998, 1999, 2004 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include #include @@ -28,9 +29,9 @@ LEAF(__strlen_user_asm) FEXPORT(__strlen_user_nocheck_asm) move v0, a0 -1: EX(lb, t0, (v0), .Lfault) +1: EX(lbu, v1, (v0), .Lfault) PTR_ADDIU v0, 1 - bnez t0, 1b + bnez v1, 1b PTR_SUBU v0, a0 jr ra END(__strlen_user_asm) -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:14:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:15:00 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60365 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824759Ab2LGFO73g6nr (ORCPT ); Fri, 7 Dec 2012 06:14:59 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqGz-0007Oy-D6; Thu, 06 Dec 2012 23:14:53 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Reduce code size for MIPS32R2 platforms. Date: Thu, 6 Dec 2012 23:14:49 -0600 Message-Id: <1354857289-28828-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35225 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1793 Lines: 67 From: "Steven J. Hill" If the CPU type is selected to be a MIPS32R2 core, we surround some code with #ifdef's to reduce the kernel binary size. Signed-off-by: Steven J. Hill --- arch/mips/mm/tlbex.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index cd9ad1b..4c23656 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -364,6 +364,7 @@ static void __cpuinit build_restore_work_registers(u32 **p) */ extern unsigned long pgd_current[]; +# ifndef CONFIG_CPU_MIPS32_R2 /* * The R3000 TLB handler is simple. */ @@ -403,6 +404,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void) dump_handler((u32 *)ebase, 32); } +# endif /* !CONFIG_CPU_MIPS32_R2 */ #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ /* @@ -1672,7 +1674,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r, } } -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT +#if !defined(CONFIG_MIPS_PGD_C0_CONTEXT) && !defined(CONFIG_CPU_MIPS32_R2) /* @@ -1826,7 +1828,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void) dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); } -#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ +#endif /* !CONFIG_MIPS_PGD_C0_CONTEXT && !CONFIG_CPU_MIPS32_R2 */ /* * R4000 style TLB load/store/modify handlers. @@ -2164,6 +2166,7 @@ void __cpuinit build_tlb_refill_handler(void) #endif switch (current_cpu_type()) { +#ifndef CONFIG_CPU_MIPS32_R2 case CPU_R2000: case CPU_R3000: case CPU_R3000A: @@ -2193,6 +2196,7 @@ void __cpuinit build_tlb_refill_handler(void) panic("No R8000 TLB refill handler yet"); break; +#endif /* !CONFIG_CPU_MIPS32_R2 */ default: if (!run_once) { scratch_reg = allocate_kscratch(); -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:15:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:15:20 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60369 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824774Ab2LGFPImsP7X (ORCPT ); Fri, 7 Dec 2012 06:15:08 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqH8-0007P3-Co; Thu, 06 Dec 2012 23:15:02 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] OF: MIPS: sead3: Implement OF support. Date: Thu, 6 Dec 2012 23:14:57 -0600 Message-Id: <1354857297-28863-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35226 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8742 Lines: 318 From: "Steven J. Hill" Activate USE_OF for SEAD-3 platform. Add basic DTS file and convert memory detection and reservations to use OF. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 1 + arch/mips/include/asm/mips-boards/prom.h | 2 + arch/mips/mti-sead3/Makefile | 14 ++- arch/mips/mti-sead3/sead3-init.c | 5 +- arch/mips/mti-sead3/sead3-memory.c | 138 ------------------------------ arch/mips/mti-sead3/sead3-setup.c | 31 +++++++ arch/mips/mti-sead3/sead3.dts | 26 ++++++ 7 files changed, 76 insertions(+), 141 deletions(-) delete mode 100644 arch/mips/mti-sead3/sead3-memory.c create mode 100644 arch/mips/mti-sead3/sead3.dts diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 07f2dff..4dad4c6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -354,6 +354,7 @@ config MIPS_SEAD3 select USB_ARCH_HAS_EHCI select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO + select USE_OF help This enables support for the MIPS Technologies SEAD3 evaluation board. diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h index a9db576..2d427aa 100644 --- a/arch/mips/include/asm/mips-boards/prom.h +++ b/arch/mips/include/asm/mips-boards/prom.h @@ -44,4 +44,6 @@ struct prom_pmemblock { unsigned int type; /* free or prom memory */ }; +extern struct boot_param_header __dtb_start; + #endif /* !(_MIPS_PROM_H) */ diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile index 626afea..e2ace8a 100644 --- a/arch/mips/mti-sead3/Makefile +++ b/arch/mips/mti-sead3/Makefile @@ -5,10 +5,12 @@ # Copyright (C) 2008 Wind River Systems, Inc. # written by Ralf Baechle # +# Copyright (C) 2012 MIPS Technoligies, Inc. All rights reserved. +# Steven J. Hill +# obj-y := sead3-lcd.o sead3-cmdline.o \ sead3-display.o sead3-init.o sead3-int.o \ - sead3-mtd.o sead3-net.o \ - sead3-memory.o sead3-platform.o \ + sead3-mtd.o sead3-net.o sead3-platform.o \ sead3-reset.o sead3-setup.o sead3-time.o obj-y += sead3-i2c-dev.o sead3-i2c.o \ @@ -17,3 +19,11 @@ obj-y += sead3-i2c-dev.o sead3-i2c.o \ obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o + +DTS_FILES = sead3.dts +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) + +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) + +$(obj)/%.dtb: $(obj)/%.dts FORCE + $(call if_changed_dep,dtc) diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c index 802fce2..6939254 100644 --- a/arch/mips/mti-sead3/sead3-init.c +++ b/arch/mips/mti-sead3/sead3-init.c @@ -125,7 +125,6 @@ void __init prom_init(void) board_ejtag_handler_setup = mips_ejtag_setup; prom_init_cmdline(); - prom_meminit(); #ifdef CONFIG_EARLY_PRINTK if ((strstr(prom_getcmdline(), "console=ttyS0")) != NULL) prom_init_early_console(0); @@ -137,3 +136,7 @@ void __init prom_init(void) strcat(prom_getcmdline(), " console=ttyS0,38400n8r"); #endif } + +void prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/mti-sead3/sead3-memory.c b/arch/mips/mti-sead3/sead3-memory.c deleted file mode 100644 index da92441..0000000 --- a/arch/mips/mti-sead3/sead3-memory.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. - */ -#include - -#include -#include -#include - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; - -static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -/* determined physical memory size, not overridden by command line args */ -unsigned long physical_memsize = 0L; - -struct prom_pmemblock * __init prom_getmdesc(void) -{ - char *memsize_str, *ptr; - unsigned int memsize; - static char cmdline[COMMAND_LINE_SIZE] __initdata; - long val; - int tmp; - - /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - pr_warn("memsize not set in boot prom, set to default 32Mb\n"); - physical_memsize = 0x02000000; - } else { - tmp = kstrtol(memsize_str, 0, &val); - physical_memsize = (unsigned long)val; - } - -#ifdef CONFIG_CPU_BIG_ENDIAN - /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last - word of physical memory */ - physical_memsize -= PAGE_SIZE; -#endif - - /* Check the command line for a memsize directive that overrides - the physical/default amount */ - strcpy(cmdline, arcs_cmdline); - ptr = strstr(cmdline, "memsize="); - if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) - ptr = strstr(ptr, " memsize="); - - if (ptr) - memsize = memparse(ptr + 8, &ptr); - else - memsize = physical_memsize; - - memset(mdesc, 0, sizeof(mdesc)); - - mdesc[0].type = yamon_dontuse; - mdesc[0].base = 0x00000000; - mdesc[0].size = 0x00001000; - - mdesc[1].type = yamon_prom; - mdesc[1].base = 0x00001000; - mdesc[1].size = 0x000ef000; - - /* - * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the - * south bridge and PCI access always forwarded to the ISA Bus and - * BIOSCS# is always generated. - * This mean that this area can't be used as DMA memory for PCI - * devices. - */ - mdesc[2].type = yamon_dontuse; - mdesc[2].base = 0x000f0000; - mdesc[2].size = 0x00010000; - - mdesc[3].type = yamon_dontuse; - mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - - mdesc[3].base; - - mdesc[4].type = yamon_free; - mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); - mdesc[4].size = memsize - mdesc[4].base; - - return &mdesc[0]; -} - -static int __init prom_memtype_classify(unsigned int type) -{ - switch (type) { - case yamon_free: - return BOOT_MEM_RAM; - case yamon_prom: - return BOOT_MEM_ROM_DATA; - default: - return BOOT_MEM_RESERVED; - } -} - -void __init prom_meminit(void) -{ - struct prom_pmemblock *p; - - p = prom_getmdesc(); - - while (p->size) { - long type; - unsigned long base, size; - - type = prom_memtype_classify(p->type); - base = p->base; - size = p->size; - - add_memory_region(base, size, type); - p++; - } -} - -void __init prom_free_prom_memory(void) -{ - unsigned long addr; - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c index 8ad46ad..83faf68 100644 --- a/arch/mips/mti-sead3/sead3-setup.c +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -6,6 +6,11 @@ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include +#include +#include +#include + +#include int coherentio; /* 0 => no DMA cache coherency (may be set by user) */ int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */ @@ -17,4 +22,30 @@ const char *get_system_type(void) void __init plat_mem_setup(void) { + extern struct boot_param_header __dtb_start; + + /* + * Load the builtin devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + __dt_setup_arch(&__dtb_start); +} + +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); + + /* free the space reserved for the dt blob */ + free_bootmem(base, size); } diff --git a/arch/mips/mti-sead3/sead3.dts b/arch/mips/mti-sead3/sead3.dts new file mode 100644 index 0000000..7d69bb6 --- /dev/null +++ b/arch/mips/mti-sead3/sead3.dts @@ -0,0 +1,26 @@ +/dts-v1/; + +/memreserve/ 0x00000000 0x00001000; // reserved +/memreserve/ 0x00001000 0x000ef000; // ROM data +/memreserve/ 0x000f0000 0x004cc000; // reserved + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mips,sead-3"; + + cpus { + cpu@0 { + compatible = "mips,mips14Kc,mips14KEc"; + }; + }; + + chosen { + bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:15:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:15:38 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60372 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823707Ab2LGFPPTkVtE (ORCPT ); Fri, 7 Dec 2012 06:15:15 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqHF-0007PC-B4; Thu, 06 Dec 2012 23:15:09 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Clean-ups for MIPS Technologies Inc. generic header file. Date: Thu, 6 Dec 2012 23:15:03 -0600 Message-Id: <1354857303-28905-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35227 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2040 Lines: 59 From: "Steven J. Hill" Clean up standard header text and remove unused #define. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mips-boards/generic.h | 28 +++++++-------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index 6e23ceb..fa188ff 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -1,21 +1,14 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive * for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * * Defines of the MIPS boards specific address-MAP, registers, etc. + * + * Copyright (C) 2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ #ifndef __ASM_MIPS_BOARDS_GENERIC_H #define __ASM_MIPS_BOARDS_GENERIC_H @@ -30,13 +23,6 @@ #define ASCII_DISPLAY_WORD_BASE 0x1f000410 #define ASCII_DISPLAY_POS_BASE 0x1f000418 - -/* - * Yamon Prom print address. - */ -#define YAMON_PROM_PRINT_ADDR 0x1fc00504 - - /* * Reset register. */ -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:15:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:15:57 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60374 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824840Ab2LGFPVc-BWH (ORCPT ); Fri, 7 Dec 2012 06:15:21 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqHL-0007PH-Ip; Thu, 06 Dec 2012 23:15:15 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Add declaration to MIPS Technologies Inc. generic header. Date: Thu, 6 Dec 2012 23:15:10 -0600 Message-Id: <1354857310-28943-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35228 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 752 Lines: 24 From: "Steven J. Hill" Add declaration of 'mips_scroll_message' to the common generic header file for the MIPS Technologies Inc. development boards. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mips-boards/generic.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index fa188ff..d99f5b6 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -79,4 +79,6 @@ extern void mips_pcibios_init(void); #define mips_pcibios_init() do { } while (0) #endif +extern void mips_scroll_message(void); + #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:21:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:21:03 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60391 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823707Ab2LGFVB4QUQA (ORCPT ); Fri, 7 Dec 2012 06:21:01 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqMp-0007Pp-6G; Thu, 06 Dec 2012 23:20:55 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 0/4] Add environment variable processing to firmware library. Date: Thu, 6 Dec 2012 23:20:45 -0600 Message-Id: <1354857649-29224-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35229 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1843 Lines: 40 From: "Steven J. Hill" Update firmware library functionality to do environment variable processing. Updates the Malta and SEAD-3 platforms to use the new functionality. Steven J. Hill (4): MIPS: FW: Add environment variable processing. MIPS: sead3: Use new common FW library variable processing. MIPS: malta: Use new common FW library variable processing. MIPS: malta: Code clean-ups. arch/mips/fw/lib/Makefile | 2 + arch/mips/fw/lib/cmdline.c | 101 ++++++++++++++++++ arch/mips/include/asm/fw/fw.h | 47 ++++++++ arch/mips/include/asm/mips-boards/generic.h | 1 + arch/mips/include/asm/mips-boards/prom.h | 49 --------- arch/mips/mti-malta/Makefile | 5 +- arch/mips/mti-malta/malta-cmdline.c | 59 ----------- arch/mips/mti-malta/malta-display.c | 40 +++---- arch/mips/mti-malta/malta-init.c | 153 ++++++--------------------- arch/mips/mti-malta/malta-memory.c | 104 ++++++------------ arch/mips/mti-malta/malta-setup.c | 24 ++--- arch/mips/mti-malta/malta-time.c | 1 - arch/mips/mti-sead3/Makefile | 8 +- arch/mips/mti-sead3/sead3-cmdline.c | 46 -------- arch/mips/mti-sead3/sead3-console.c | 2 +- arch/mips/mti-sead3/sead3-display.c | 1 - arch/mips/mti-sead3/sead3-init.c | 82 +++++++------- arch/mips/mti-sead3/sead3-time.c | 1 - 18 files changed, 296 insertions(+), 430 deletions(-) create mode 100644 arch/mips/fw/lib/cmdline.c create mode 100644 arch/mips/include/asm/fw/fw.h delete mode 100644 arch/mips/include/asm/mips-boards/prom.h delete mode 100644 arch/mips/mti-malta/malta-cmdline.c delete mode 100644 arch/mips/mti-sead3/sead3-cmdline.c -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:21:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:21:21 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60393 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824810Ab2LGFVDDU5L- (ORCPT ); Fri, 7 Dec 2012 06:21:03 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqMq-0007Pp-W9; Thu, 06 Dec 2012 23:20:57 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 1/4] MIPS: FW: Add environment variable processing. Date: Thu, 6 Dec 2012 23:20:46 -0600 Message-Id: <1354857649-29224-2-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354857649-29224-1-git-send-email-sjhill@mips.com> References: <1354857649-29224-1-git-send-email-sjhill@mips.com> X-archive-position: 35230 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4505 Lines: 188 From: "Steven J. Hill" Add parsing of the environment and command line variables passed to the kernel to the firmware library. Signed-off-by: Steven J. Hill --- arch/mips/fw/lib/Makefile | 2 + arch/mips/fw/lib/cmdline.c | 101 +++++++++++++++++++++++++++++++++++++++++ arch/mips/include/asm/fw/fw.h | 47 +++++++++++++++++++ 3 files changed, 150 insertions(+) create mode 100644 arch/mips/fw/lib/cmdline.c create mode 100644 arch/mips/include/asm/fw/fw.h diff --git a/arch/mips/fw/lib/Makefile b/arch/mips/fw/lib/Makefile index 84befc9..5291505 100644 --- a/arch/mips/fw/lib/Makefile +++ b/arch/mips/fw/lib/Makefile @@ -2,4 +2,6 @@ # Makefile for generic prom monitor library routines under Linux. # +lib-y += cmdline.o + lib-$(CONFIG_64BIT) += call_o32.o diff --git a/arch/mips/fw/lib/cmdline.c b/arch/mips/fw/lib/cmdline.c new file mode 100644 index 0000000..ffd0345 --- /dev/null +++ b/arch/mips/fw/lib/cmdline.c @@ -0,0 +1,101 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include + +#include +#include + +int fw_argc; +int *_fw_argv; +int *_fw_envp; + +void __init fw_init_cmdline(void) +{ + int i; + + /* Validate command line parameters. */ + if ((fw_arg0 >= CKSEG0) || (fw_arg1 < CKSEG0)) { + fw_argc = 0; + _fw_argv = NULL; + } else { + fw_argc = (fw_arg0 & 0x0000ffff); + _fw_argv = (int *)fw_arg1; + } + + /* Validate environment pointer. */ + if (fw_arg2 < CKSEG0) + _fw_envp = NULL; + else + _fw_envp = (int *)fw_arg2; + + for (i = 1; i < fw_argc; i++) { + strlcat(arcs_cmdline, fw_argv(i), COMMAND_LINE_SIZE); + if (i < (fw_argc - 1)) + strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); + } +} + +char * __init fw_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +char *fw_getenv(char *envname) +{ + char *result = NULL; + + if (_fw_envp != NULL) { + /* + * Return a pointer to the given environment variable. + * YAMON uses "name", "value" pairs, while U-Boot uses + * "name=value". + */ + int i, yamon, index = 0; + + yamon = (strchr(fw_envp(index), '=') == NULL); + i = strlen(envname); + + while (fw_envp(index)) { + if (strncmp(envname, fw_envp(index), i) == 0) { + if (yamon) { + result = fw_envp(index + 1); + break; + } else if (fw_envp(index)[i] == '=') { + result = (fw_envp(index + 1) + i); + break; + } + } + + /* Increment array index. */ + if (yamon) + index += 2; + else + index += 1; + } + } + + return result; +} + +unsigned long fw_getenvl(char *envname) +{ + unsigned long envl = 0UL; + char *str; + long val; + int tmp; + + str = fw_getenv(envname); + if (str) { + tmp = kstrtol(str, 0, &val); + envl = (unsigned long)val; + } + + return envl; +} diff --git a/arch/mips/include/asm/fw/fw.h b/arch/mips/include/asm/fw/fw.h new file mode 100644 index 0000000..d6c50a7 --- /dev/null +++ b/arch/mips/include/asm/fw/fw.h @@ -0,0 +1,47 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. + */ +#ifndef __ASM_FW_H_ +#define __ASM_FW_H_ + +#include /* For cleaner code... */ + +enum fw_memtypes { + fw_dontuse, + fw_code, + fw_free, +}; + +typedef struct { + unsigned long base; /* Within KSEG0 */ + unsigned int size; /* bytes */ + enum fw_memtypes type; /* fw_memtypes */ +} fw_memblock_t; + +/* Maximum number of memory block descriptors. */ +#define FW_MAX_MEMBLOCKS 32 + +extern int fw_argc; +extern int *_fw_argv; +extern int *_fw_envp; + +/* + * Most firmware like YAMON, PMON, etc. pass arguments and environment + * variables as 32-bit pointers. These take care of sign extension. + */ +#define fw_argv(index) ((char *)(long)_fw_argv[(index)]) +#define fw_envp(index) ((char *)(long)_fw_envp[(index)]) + +extern void fw_init_cmdline(void); +extern char *fw_getcmdline(void); +extern fw_memblock_t *fw_getmdesc(void); +extern void fw_meminit(void); +extern char *fw_getenv(char *name); +extern unsigned long fw_getenvl(char *name); +extern void fw_init_early_console(char port); + +#endif /* __ASM_FW_H_ */ -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:21:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:21:40 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60396 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824804Ab2LGFVDkhGQp (ORCPT ); Fri, 7 Dec 2012 06:21:03 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqMr-0007Pp-Ft; Thu, 06 Dec 2012 23:20:57 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 2/4] MIPS: sead3: Use new common FW library variable processing. Date: Thu, 6 Dec 2012 23:20:47 -0600 Message-Id: <1354857649-29224-3-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354857649-29224-1-git-send-email-sjhill@mips.com> References: <1354857649-29224-1-git-send-email-sjhill@mips.com> X-archive-position: 35231 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6887 Lines: 240 From: "Steven J. Hill" Remove old YAMON prom code and use common firmware library code instead for the SEAD-3 platform. Signed-off-by: Steven J. Hill --- arch/mips/mti-sead3/Makefile | 8 ++-- arch/mips/mti-sead3/sead3-cmdline.c | 46 -------------------- arch/mips/mti-sead3/sead3-console.c | 2 +- arch/mips/mti-sead3/sead3-display.c | 1 - arch/mips/mti-sead3/sead3-init.c | 82 ++++++++++++++++++++--------------- arch/mips/mti-sead3/sead3-time.c | 1 - 6 files changed, 51 insertions(+), 89 deletions(-) delete mode 100644 arch/mips/mti-sead3/sead3-cmdline.c diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile index e2ace8a..fd384b5 100644 --- a/arch/mips/mti-sead3/Makefile +++ b/arch/mips/mti-sead3/Makefile @@ -8,10 +8,10 @@ # Copyright (C) 2012 MIPS Technoligies, Inc. All rights reserved. # Steven J. Hill # -obj-y := sead3-lcd.o sead3-cmdline.o \ - sead3-display.o sead3-init.o sead3-int.o \ - sead3-mtd.o sead3-net.o sead3-platform.o \ - sead3-reset.o sead3-setup.o sead3-time.o +obj-y := sead3-lcd.o sead3-display.o sead3-init.o \ + sead3-int.o sead3-mtd.o sead3-net.o \ + sead3-platform.o sead3-reset.o \ + sead3-setup.o sead3-time.o obj-y += sead3-i2c-dev.o sead3-i2c.o \ sead3-pic32-i2c-drv.o sead3-pic32-bus.o \ diff --git a/arch/mips/mti-sead3/sead3-cmdline.c b/arch/mips/mti-sead3/sead3-cmdline.c deleted file mode 100644 index a2e6cec..0000000 --- a/arch/mips/mti-sead3/sead3-cmdline.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. - */ -#include -#include - -#include - -extern int prom_argc; -extern int *_prom_argv; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension. - */ -#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while (actr < prom_argc) { - strcpy(cp, prom_argv(actr)); - cp += strlen(prom_argv(actr)); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) { - /* get rid of trailing space */ - --cp; - *cp = '\0'; - } -} diff --git a/arch/mips/mti-sead3/sead3-console.c b/arch/mips/mti-sead3/sead3-console.c index b367391..1b6042c 100644 --- a/arch/mips/mti-sead3/sead3-console.c +++ b/arch/mips/mti-sead3/sead3-console.c @@ -26,7 +26,7 @@ static inline void serial_out(int offset, int value, unsigned int base_addr) __raw_writel(value, PORT(base_addr, offset)); } -void __init prom_init_early_console(char port) +void __init fw_init_early_console(char port) { console_port = port; } diff --git a/arch/mips/mti-sead3/sead3-display.c b/arch/mips/mti-sead3/sead3-display.c index 8308c7f..62202e1 100644 --- a/arch/mips/mti-sead3/sead3-display.c +++ b/arch/mips/mti-sead3/sead3-display.c @@ -8,7 +8,6 @@ #include #include #include -#include static unsigned int display_count; static unsigned int max_display_count; diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c index 6939254..bfbd17b 100644 --- a/arch/mips/mti-sead3/sead3-init.c +++ b/arch/mips/mti-sead3/sead3-init.c @@ -12,38 +12,51 @@ #include #include #include -#include - -extern void prom_init_early_console(char port); +#include extern char except_vec_nmi; extern char except_vec_ejtag_debug; -int prom_argc; -int *_prom_argv, *_prom_envp; - -#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) - -char *prom_getenv(char *envname) +#ifdef CONFIG_SERIAL_8250_CONSOLE +static void __init console_config(void) { - /* - * Return a pointer to the given environment variable. - * In 64-bit mode: we're using 64-bit pointers, but all pointers - * in the PROM structures are only 32-bit, so we need some - * workarounds, if we are running in 64-bit mode. - */ - int i, index = 0; - - i = strlen(envname); - - while (prom_envp(index)) { - if (strncmp(envname, prom_envp(index), i) == 0) - return prom_envp(index+1); - index += 2; + char console_string[40]; + int baud = 0; + char parity = '\0', bits = '\0', flow = '\0'; + char *s; + + if ((strstr(fw_getcmdline(), "console=")) == NULL) { + s = fw_getenv("modetty0"); + if (s) { + while (*s >= '0' && *s <= '9') + baud = baud*10 + *s++ - '0'; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; + } + if (baud == 0) + baud = 38400; + if (parity != 'n' && parity != 'o' && parity != 'e') + parity = 'n'; + if (bits != '7' && bits != '8') + bits = '8'; + if (flow == '\0') + flow = 'r'; + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, + parity, bits, flow); + strcat(fw_getcmdline(), console_string); } - - return NULL; } +#endif static void __init mips_nmi_setup(void) { @@ -117,23 +130,20 @@ static void __init mips_ejtag_setup(void) void __init prom_init(void) { - prom_argc = fw_arg0; - _prom_argv = (int *) fw_arg1; - _prom_envp = (int *) fw_arg2; - board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; - prom_init_cmdline(); + fw_init_cmdline(); #ifdef CONFIG_EARLY_PRINTK - if ((strstr(prom_getcmdline(), "console=ttyS0")) != NULL) - prom_init_early_console(0); - else if ((strstr(prom_getcmdline(), "console=ttyS1")) != NULL) - prom_init_early_console(1); + if ((strstr(fw_getcmdline(), "console=ttyS0")) != NULL) + fw_init_early_console(0); + else if ((strstr(fw_getcmdline(), "console=ttyS1")) != NULL) + fw_init_early_console(1); #endif #ifdef CONFIG_SERIAL_8250_CONSOLE - if ((strstr(prom_getcmdline(), "console=")) == NULL) - strcat(prom_getcmdline(), " console=ttyS0,38400n8r"); + if ((strstr(fw_getcmdline(), "console=")) == NULL) + strcat(fw_getcmdline(), " console=ttyS0,38400n8r"); + console_config(); #endif } diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c index 048e781..418c07a 100644 --- a/arch/mips/mti-sead3/sead3-time.c +++ b/arch/mips/mti-sead3/sead3-time.c @@ -11,7 +11,6 @@ #include #include #include -#include unsigned long cpu_khz; -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:21:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:22:00 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60397 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825740Ab2LGFVEYE2n2 (ORCPT ); Fri, 7 Dec 2012 06:21:04 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqMs-0007Pp-1h; Thu, 06 Dec 2012 23:20:58 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 3/4] MIPS: malta: Use new common FW library variable processing. Date: Thu, 6 Dec 2012 23:20:48 -0600 Message-Id: <1354857649-29224-4-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354857649-29224-1-git-send-email-sjhill@mips.com> References: <1354857649-29224-1-git-send-email-sjhill@mips.com> X-archive-position: 35232 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13193 Lines: 467 From: "Steven J. Hill" Remove old YAMON prom code and use common firmware library code instead for the Malta platform. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mips-boards/generic.h | 1 + arch/mips/mti-malta/Makefile | 5 +- arch/mips/mti-malta/malta-cmdline.c | 59 ----------------- arch/mips/mti-malta/malta-display.c | 1 - arch/mips/mti-malta/malta-init.c | 95 ++------------------------- arch/mips/mti-malta/malta-memory.c | 62 +++++------------ arch/mips/mti-malta/malta-setup.c | 9 ++- arch/mips/mti-malta/malta-time.c | 1 - 8 files changed, 29 insertions(+), 204 deletions(-) delete mode 100644 arch/mips/mti-malta/malta-cmdline.c diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index d99f5b6..31b85ed 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -80,5 +80,6 @@ extern void mips_pcibios_init(void); #endif extern void mips_scroll_message(void); +extern void mips_display_message(const char *str); #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile index 6079ef3..0388fc8 100644 --- a/arch/mips/mti-malta/Makefile +++ b/arch/mips/mti-malta/Makefile @@ -5,9 +5,8 @@ # Copyright (C) 2008 Wind River Systems, Inc. # written by Ralf Baechle # -obj-y := malta-amon.o malta-cmdline.o \ - malta-display.o malta-init.o malta-int.o \ - malta-memory.o malta-platform.o \ +obj-y := malta-amon.o malta-display.o malta-init.o \ + malta-int.o malta-memory.o malta-platform.o \ malta-reset.o malta-setup.o malta-time.o obj-$(CONFIG_EARLY_PRINTK) += malta-console.o diff --git a/arch/mips/mti-malta/malta-cmdline.c b/arch/mips/mti-malta/malta-cmdline.c deleted file mode 100644 index 1871c30..0000000 --- a/arch/mips/mti-malta/malta-cmdline.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Kernel command line creation using the prom monitor (YAMON) argc/argv. - */ -#include -#include - -#include - -extern int prom_argc; -extern int *_prom_argv; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension. - */ -#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv(actr)); - cp += strlen(prom_argv(actr)); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) { - /* get rid of trailing space */ - --cp; - *cp = '\0'; - } -} diff --git a/arch/mips/mti-malta/malta-display.c b/arch/mips/mti-malta/malta-display.c index 7c8828f..2a0057c 100644 --- a/arch/mips/mti-malta/malta-display.c +++ b/arch/mips/mti-malta/malta-display.c @@ -22,7 +22,6 @@ #include #include #include -#include extern const char display_string[]; static unsigned int display_count; diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 27a6cdb..6c61e94 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -23,30 +23,19 @@ #include #include -#include #include #include #include #include #include - +#include #include -#include #include #include #include #include -int prom_argc; -int *_prom_argv, *_prom_envp; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension, if running in 64-bit mode. - */ -#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) - int init_debug; static int mips_revision_corid; @@ -62,74 +51,6 @@ unsigned long _pcictrl_gt64120; /* MIPS System controller register base */ unsigned long _pcictrl_msc; -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - * In 64-bit mode: we're using 64-bit pointers, but all pointers - * in the PROM structures are only 32-bit, so we need some - * workarounds, if we are running in 64-bit mode. - */ - int i, index=0; - - i = strlen(envname); - - while (prom_envp(index)) { - if(strncmp(envname, prom_envp(index), i) == 0) { - return(prom_envp(index+1)); - } - index += 2; - } - - return NULL; -} - -static inline unsigned char str2hexnum(unsigned char c) -{ - if (c >= '0' && c <= '9') - return c - '0'; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return 0; /* foo */ -} - -static inline void str2eaddr(unsigned char *ea, unsigned char *str) -{ - int i; - - for (i = 0; i < 6; i++) { - unsigned char num; - - if((*str == '.') || (*str == ':')) - str++; - num = str2hexnum(*str++) << 4; - num |= (str2hexnum(*str++)); - ea[i] = num; - } -} - -int get_ethernet_addr(char *ethernet_addr) -{ - char *ethaddr_str; - - ethaddr_str = prom_getenv("ethaddr"); - if (!ethaddr_str) { - printk("ethaddr not set in boot prom\n"); - return -1; - } - str2eaddr(ethernet_addr, ethaddr_str); - - if (init_debug > 1) { - int i; - printk("get_ethernet_addr: "); - for (i=0; i<5; i++) - printk("%02x:", (unsigned char)*(ethernet_addr+i)); - printk("%02x\n", *(ethernet_addr+i)); - } - - return 0; -} - #ifdef CONFIG_SERIAL_8250_CONSOLE static void __init console_config(void) { @@ -138,8 +59,8 @@ static void __init console_config(void) char parity = '\0', bits = '\0', flow = '\0'; char *s; - if ((strstr(prom_getcmdline(), "console=")) == NULL) { - s = prom_getenv("modetty0"); + if ((strstr(fw_getcmdline(), "console=")) == NULL) { + s = fw_getenv("modetty0"); if (s) { while (*s >= '0' && *s <= '9') baud = baud*10 + *s++ - '0'; @@ -159,7 +80,7 @@ static void __init console_config(void) if (flow == '\0') flow = 'r'; sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); - strcat(prom_getcmdline(), console_string); + strcat(fw_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } } @@ -193,10 +114,6 @@ extern struct plat_smp_ops msmtc_smp_ops; void __init prom_init(void) { - prom_argc = fw_arg0; - _prom_argv = (int *) fw_arg1; - _prom_envp = (int *) fw_arg2; - mips_display_message("LINUX"); /* @@ -353,8 +270,8 @@ void __init prom_init(void) board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; - prom_init_cmdline(); - prom_meminit(); + fw_init_cmdline(); + fw_meminit(); #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index a96d281..06fa4ad 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -27,30 +27,14 @@ #include #include #include +#include -#include - -/*#define DEBUG*/ - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; -static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -#ifdef DEBUG -static char *mtypes[3] = { - "Dont use memory", - "YAMON PROM memory", - "Free memory", -}; -#endif +static fw_memblock_t mdesc[FW_MAX_MEMBLOCKS]; /* determined physical memory size, not overridden by command line args */ unsigned long physical_memsize = 0L; -static struct prom_pmemblock * __init prom_getmdesc(void) +fw_memblock_t * __init fw_getmdesc(void) { char *memsize_str; unsigned int memsize; @@ -58,15 +42,12 @@ static struct prom_pmemblock * __init prom_getmdesc(void) static char cmdline[COMMAND_LINE_SIZE] __initdata; /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); + memsize_str = fw_getenv("memsize"); if (!memsize_str) { printk(KERN_WARNING "memsize not set in boot prom, set to default (32Mb)\n"); physical_memsize = 0x02000000; } else { -#ifdef DEBUG - pr_debug("prom_memsize = %s\n", memsize_str); -#endif physical_memsize = simple_strtol(memsize_str, NULL, 0); } @@ -90,11 +71,11 @@ static struct prom_pmemblock * __init prom_getmdesc(void) memset(mdesc, 0, sizeof(mdesc)); - mdesc[0].type = yamon_dontuse; + mdesc[0].type = fw_dontuse; mdesc[0].base = 0x00000000; mdesc[0].size = 0x00001000; - mdesc[1].type = yamon_prom; + mdesc[1].type = fw_code; mdesc[1].base = 0x00001000; mdesc[1].size = 0x000ef000; @@ -105,55 +86,44 @@ static struct prom_pmemblock * __init prom_getmdesc(void) * This mean that this area can't be used as DMA memory for PCI * devices. */ - mdesc[2].type = yamon_dontuse; + mdesc[2].type = fw_dontuse; mdesc[2].base = 0x000f0000; mdesc[2].size = 0x00010000; - mdesc[3].type = yamon_dontuse; + mdesc[3].type = fw_dontuse; mdesc[3].base = 0x00100000; mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; - mdesc[4].type = yamon_free; + mdesc[4].type = fw_free; mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); mdesc[4].size = memsize - mdesc[4].base; return &mdesc[0]; } -static int __init prom_memtype_classify(unsigned int type) +static int __init fw_memtype_classify(unsigned int type) { switch (type) { - case yamon_free: + case fw_free: return BOOT_MEM_RAM; - case yamon_prom: + case fw_code: return BOOT_MEM_ROM_DATA; default: return BOOT_MEM_RESERVED; } } -void __init prom_meminit(void) +void __init fw_meminit(void) { - struct prom_pmemblock *p; + fw_memblock_t *p; -#ifdef DEBUG - pr_debug("YAMON MEMORY DESCRIPTOR dump:\n"); - p = prom_getmdesc(); - while (p->size) { - int i = 0; - pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", - i, p, p->base, p->size, mtypes[p->type]); - p++; - i++; - } -#endif - p = prom_getmdesc(); + p = fw_getmdesc(); while (p->size) { long type; unsigned long base, size; - type = prom_memtype_classify(p->type); + type = fw_memtype_classify(p->type); base = p->base; size = p->size; diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 2e28f65..08cdf8f 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -25,9 +25,8 @@ #include #include -#include +#include #include -#include #include #include #include @@ -115,7 +114,7 @@ static void __init pci_clock_check(void) 33, 20, 25, 30, 12, 16, 37, 10 }; int pciclock = pciclocks[jmpr]; - char *argptr = prom_getcmdline(); + char *argptr = fw_getcmdline(); if (pciclock != 33 && !strstr(argptr, "idebus=")) { printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " @@ -153,7 +152,7 @@ static void __init bonito_quirks_setup(void) { char *argptr; - argptr = prom_getcmdline(); + argptr = fw_getcmdline(); if (strstr(argptr, "debug")) { BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; printk(KERN_INFO "Enabled Bonito debug mode\n"); @@ -165,7 +164,7 @@ static void __init bonito_quirks_setup(void) BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; printk(KERN_INFO "Enabled Bonito CPU coherency\n"); - argptr = prom_getcmdline(); + argptr = fw_getcmdline(); if (strstr(argptr, "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index a144b89..99b49e3 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -39,7 +39,6 @@ #include #include -#include #include -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:21:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:22:20 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60400 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824840Ab2LGFVFA3yIy (ORCPT ); Fri, 7 Dec 2012 06:21:05 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqMs-0007Pp-LZ; Thu, 06 Dec 2012 23:20:58 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 4/4] MIPS: malta: Code clean-ups. Date: Thu, 6 Dec 2012 23:20:49 -0600 Message-Id: <1354857649-29224-5-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354857649-29224-1-git-send-email-sjhill@mips.com> References: <1354857649-29224-1-git-send-email-sjhill@mips.com> X-archive-position: 35233 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13689 Lines: 390 From: "Steven J. Hill" Do whitespace/formatting clean-up and remove obsolete header file. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mips-boards/prom.h | 49 ------------------------- arch/mips/mti-malta/malta-display.c | 39 +++++++++----------- arch/mips/mti-malta/malta-init.c | 58 ++++++++++++++---------------- arch/mips/mti-malta/malta-memory.c | 42 +++++++++------------- arch/mips/mti-malta/malta-setup.c | 15 ++++---- 5 files changed, 66 insertions(+), 137 deletions(-) delete mode 100644 arch/mips/include/asm/mips-boards/prom.h diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h deleted file mode 100644 index 2d427aa..0000000 --- a/arch/mips/include/asm/mips-boards/prom.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * MIPS boards bootprom interface for the Linux kernel. - * - */ - -#ifndef _MIPS_PROM_H -#define _MIPS_PROM_H - -extern char *prom_getcmdline(void); -extern char *prom_getenv(char *name); -extern void prom_init_cmdline(void); -extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); -extern void mips_display_message(const char *str); -extern void mips_display_word(unsigned int num); -extern void mips_scroll_message(void); -extern int get_ethernet_addr(char *ethernet_addr); - -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - unsigned long base; /* Within KSEG0. */ - unsigned int size; /* In bytes. */ - unsigned int type; /* free or prom memory */ -}; - -extern struct boot_param_header __dtb_start; - -#endif /* !(_MIPS_PROM_H) */ diff --git a/arch/mips/mti-malta/malta-display.c b/arch/mips/mti-malta/malta-display.c index 2a0057c..04826d7 100644 --- a/arch/mips/mti-malta/malta-display.c +++ b/arch/mips/mti-malta/malta-display.c @@ -1,26 +1,19 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Display routines for display messages in MIPS boards ascii display. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ - #include #include -#include +#include + #include extern const char display_string[]; @@ -29,17 +22,17 @@ static unsigned int max_display_count; void mips_display_message(const char *str) { - static unsigned int __iomem *display = NULL; + static unsigned int __iomem *display; int i; if (unlikely(display == NULL)) display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int)); - for (i = 0; i <= 14; i=i+2) { - if (*str) - __raw_writel(*str++, display + i); - else - __raw_writel(' ', display + i); + for (i = 0; i <= 14; i += 2) { + if (*str) + __raw_writel(*str++, display + i); + else + __raw_writel(' ', display + i); } } diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 6c61e94..0ae857a 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -1,42 +1,29 @@ /* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * PROM library initialisation code. + * + * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * Steven J. Hill */ #include #include #include -#include -#include #include #include #include #include #include #include -#include -#include - #include -int init_debug; +extern void mips_display_message(const char *str); static int mips_revision_corid; int mips_revision_sconid; @@ -64,12 +51,18 @@ static void __init console_config(void) if (s) { while (*s >= '0' && *s <= '9') baud = baud*10 + *s++ - '0'; - if (*s == ',') s++; - if (*s) parity = *s++; - if (*s == ',') s++; - if (*s) bits = *s++; - if (*s == ',') s++; - if (*s == 'h') flow = 'r'; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; } if (baud == 0) baud = 38400; @@ -79,7 +72,8 @@ static void __init console_config(void) bits = '8'; if (flow == '\0') flow = 'r'; - sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, + parity, bits, flow); strcat(fw_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } @@ -223,7 +217,7 @@ void __init prom_init(void) case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); - mips_pci_controller: +mips_pci_controller: mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); @@ -265,7 +259,7 @@ void __init prom_init(void) default: /* Unknown system controller */ mips_display_message("SC Error"); - while (1); /* We die here... */ + while (1); /* We die here... */ } board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index 06fa4ad..391960a 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -1,31 +1,21 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * PROM library functions for acquiring/using memory descriptors given to * us from the YAMON. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ #include -#include #include -#include #include #include -#include #include #include @@ -36,19 +26,20 @@ unsigned long physical_memsize = 0L; fw_memblock_t * __init fw_getmdesc(void) { - char *memsize_str; + char *memsize_str, *ptr; unsigned int memsize; - char *ptr; static char cmdline[COMMAND_LINE_SIZE] __initdata; + long val; + int tmp; /* otherwise look in the environment */ memsize_str = fw_getenv("memsize"); if (!memsize_str) { - printk(KERN_WARNING - "memsize not set in boot prom, set to default (32Mb)\n"); + pr_warn("memsize not set in YAMON, set to default (32Mb)\n"); physical_memsize = 0x02000000; } else { - physical_memsize = simple_strtol(memsize_str, NULL, 0); + tmp = kstrtol(memsize_str, 0, &val); + physical_memsize = (unsigned long)val; } #ifdef CONFIG_CPU_BIG_ENDIAN @@ -92,7 +83,8 @@ fw_memblock_t * __init fw_getmdesc(void) mdesc[3].type = fw_dontuse; mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - + mdesc[3].base; mdesc[4].type = fw_free; mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); @@ -142,7 +134,7 @@ void __init prom_free_prom_memory(void) continue; addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", + free_init_pages("YAMON memory", addr, addr + boot_mem_map.map[i].size); } } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 08cdf8f..ed68073 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -117,13 +117,12 @@ static void __init pci_clock_check(void) char *argptr = fw_getcmdline(); if (pciclock != 33 && !strstr(argptr, "idebus=")) { - printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " - "setting idebus\n", pciclock); + pr_warn("WARNING: PCI clock is %dMHz, setting idebus\n", + pciclock); argptr += strlen(argptr); sprintf(argptr, " idebus=%d", pciclock); if (pciclock < 20 || pciclock > 66) - printk(KERN_WARNING "WARNING: IDE timing " - "calculations will be incorrect\n"); + pr_warn("WARNING: IDE timing calculations will be incorrect\n"); } } #endif @@ -155,14 +154,14 @@ static void __init bonito_quirks_setup(void) argptr = fw_getcmdline(); if (strstr(argptr, "debug")) { BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; - printk(KERN_INFO "Enabled Bonito debug mode\n"); + pr_info("Enabled Bonito debug mode\n"); } else BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; #ifdef CONFIG_DMA_COHERENT if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; - printk(KERN_INFO "Enabled Bonito CPU coherency\n"); + pr_info("Enabled Bonito CPU coherency\n"); argptr = fw_getcmdline(); if (strstr(argptr, "iobcuncached")) { @@ -170,13 +169,13 @@ static void __init bonito_quirks_setup(void) BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Disabled Bonito IOBC coherency\n"); + pr_info("Disabled Bonito IOBC coherency\n"); } else { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG |= (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Enabled Bonito IOBC coherency\n"); + pr_info("Enabled Bonito IOBC coherency\n"); } } else panic("Hardware DMA cache coherency not supported"); -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:23:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:23:34 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60409 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab2LGFXdaRc2L (ORCPT ); Fri, 7 Dec 2012 06:23:33 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqPH-0007QJ-15; Thu, 06 Dec 2012 23:23:27 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Add option to disable software I/O coherency. Date: Thu, 6 Dec 2012 23:23:22 -0600 Message-Id: <1354857802-29348-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35234 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7296 Lines: 247 From: "Steven J. Hill" Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mach-generic/dma-coherence.h | 4 +- arch/mips/mm/c-r4k.c | 21 +--- arch/mips/mm/dma-default.c | 8 +- arch/mips/mti-malta/malta-setup.c | 102 ++++++++++++++++++++ 4 files changed, 116 insertions(+), 19 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177..9f1cd31 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -63,7 +63,9 @@ static inline int plat_device_is_coherent(struct device *dev) return 1; #endif #ifdef CONFIG_DMA_NONCOHERENT - return 0; + extern int coherentio; + + return coherentio; #endif } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c0f27c8..7f13f24 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1383,20 +1383,6 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; - -static int __init setcoherentio(char *str) -{ - coherentio = 1; - - return 1; -} - -__setup("coherentio", setcoherentio); -#endif - static void __cpuinit r4k_cache_error_setup(void) { extern char __weak except_vec2_generic; @@ -1419,6 +1405,7 @@ void __cpuinit r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); + extern int coherentio; struct cpuinfo_mips *c = ¤t_cpu_data; probe_pcache(); @@ -1478,9 +1465,11 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* We want to run CMP kernels on core(s) with and without coherent caches */ + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); board_cache_error_setup = r4k_cache_error_setup; } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 3fab204..058c2ca 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -100,6 +100,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); static void *mips_dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) { + extern int hw_coherentio; void *ret; if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) @@ -115,7 +116,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, if (!plat_device_is_coherent(dev)) { dma_cache_wback_inv((unsigned long) ret, size); - ret = UNCAC_ADDR(ret); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } } @@ -134,6 +136,7 @@ EXPORT_SYMBOL(dma_free_noncoherent); static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs) { + extern int hw_coherentio; unsigned long addr = (unsigned long) vaddr; int order = get_order(size); @@ -143,7 +146,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) - addr = CAC_ADDR(addr); + if (!hw_coherentio) + addr = CAC_ADDR(addr); free_pages(addr, get_order(size)); } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index ed68073..0bac429 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -104,6 +105,105 @@ static void __init fd_activate(void) } #endif +int coherentio = -1; /* no DMA cache coherency (may be set by user) */ +int hw_coherentio; /* init to 0 => no HW DMA cache coherency (reflects real HW) */ +static int __init setcoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); + return 1; +} +__setup("coherentio", setcoherentio); + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 1; +} +__setup("nocoherentio", setnocoherentio); + +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(fw_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + hw_coherentio = supported; + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -205,6 +305,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:23:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:23:56 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60411 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831898Ab2LGFXkQJizd (ORCPT ); Fri, 7 Dec 2012 06:23:40 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqPN-0007QO-Nq; Thu, 06 Dec 2012 23:23:33 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: malta: Add new Malta config files. Date: Thu, 6 Dec 2012 23:23:28 -0600 Message-Id: <1354857808-29382-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35235 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 27339 Lines: 1044 From: "Steven J. Hill" Add in new Malta config files for SMVP, SMTC, and APRP. Also update the original 'malta_defconfig' config file. Signed-off-by: Steven J. Hill --- arch/mips/configs/malta_defconfig | 67 ++--------- arch/mips/configs/maltaaprp_defconfig | 197 ++++++++++++++++++++++++++++++++ arch/mips/configs/maltasmtc_defconfig | 198 ++++++++++++++++++++++++++++++++ arch/mips/configs/maltasmvp_defconfig | 201 +++++++++++++++++++++++++++++++++ arch/mips/configs/maltaup_defconfig | 196 ++++++++++++++++++++++++++++++++ 5 files changed, 804 insertions(+), 55 deletions(-) create mode 100644 arch/mips/configs/maltaaprp_defconfig create mode 100644 arch/mips/configs/maltasmtc_defconfig create mode 100644 arch/mips/configs/maltasmvp_defconfig create mode 100644 arch/mips/configs/maltaup_defconfig diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index cd732e5..c55cf15 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -2,30 +2,22 @@ CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y CONFIG_MIPS_MT_SMP=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_HZ_100=y CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=15 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_IPC_NS=y -CONFIG_PID_NS=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_RELAY=y CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_PCI=y -CONFIG_PM=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_XFRM_USER=m @@ -41,8 +33,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y @@ -65,7 +55,6 @@ CONFIG_IPV6_MROUTE=y CONFIG_IPV6_PIMSM_V2=y CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y @@ -136,23 +125,15 @@ CONFIG_IP_VS_DH=m CONFIG_IP_VS_SH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_FTP=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -162,7 +143,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -173,7 +153,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m @@ -247,12 +226,10 @@ CONFIG_MAC80211=m CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_DEFAULT_PID=y CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_LEDS=y CONFIG_RFKILL=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_CONNECTOR=m CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_OOPS=m @@ -271,7 +248,6 @@ CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m CONFIG_ATA_OVER_ETH=m -# CONFIG_MISC_DEVICES is not set CONFIG_IDE=y CONFIG_BLK_DEV_IDECD=y CONFIG_IDE_GENERIC=y @@ -317,13 +293,19 @@ CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_NETDEVICES=y -CONFIG_IFB=m -CONFIG_DUMMY=m CONFIG_BONDING=m -CONFIG_MACVLAN=m +CONFIG_DUMMY=m CONFIG_EQUALIZER=m +CONFIG_IFB=m +CONFIG_MACVLAN=m CONFIG_TUN=m CONFIG_VETH=m +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_PCNET32=y +CONFIG_CHELSIO_T3=m +CONFIG_AX88796=m +CONFIG_NETXEN_NIC=m +CONFIG_TC35815=m CONFIG_MARVELL_PHY=m CONFIG_DAVICOM_PHY=m CONFIG_QSEMI_PHY=m @@ -334,14 +316,6 @@ CONFIG_SMSC_PHY=m CONFIG_BROADCOM_PHY=m CONFIG_ICPLUS_PHY=m CONFIG_REALTEK_PHY=m -CONFIG_MDIO_BITBANG=m -CONFIG_NET_ETHERNET=y -CONFIG_AX88796=m -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -CONFIG_TC35815=m -CONFIG_CHELSIO_T3=m -CONFIG_NETXEN_NIC=m CONFIG_ATMEL=m CONFIG_PCI_ATMEL=m CONFIG_PRISM54=m @@ -352,15 +326,7 @@ CONFIG_HOSTAP_PLX=m CONFIG_HOSTAP_PCI=m CONFIG_IPW2100=m CONFIG_IPW2100_MONITOR=y -CONFIG_IPW2200=m -CONFIG_IPW2200_MONITOR=y -CONFIG_IPW2200_PROMISCUOUS=y -CONFIG_IPW2200_QOS=y CONFIG_LIBERTAS=m -CONFIG_HERMES=m -CONFIG_PLX_HERMES=m -CONFIG_TMD_HERMES=m -CONFIG_NORTEL_HERMES=m # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO_I8042 is not set @@ -373,12 +339,6 @@ CONFIG_FB_CIRRUS=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_HID=m -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_IDE_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_CMOS=y CONFIG_UIO=m @@ -398,7 +358,6 @@ CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_QUOTA=y CONFIG_QFMT_V2=y -CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_ISO9660_FS=m CONFIG_JOLIET=y @@ -425,7 +384,6 @@ CONFIG_ROMFS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NFSD=y CONFIG_NFSD_V3=y @@ -466,7 +424,6 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_LRW=m diff --git a/arch/mips/configs/maltaaprp_defconfig b/arch/mips/configs/maltaaprp_defconfig new file mode 100644 index 0000000..efd6604 --- /dev/null +++ b/arch/mips/configs/maltaaprp_defconfig @@ -0,0 +1,197 @@ +CONFIG_MIPS_MALTA=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_MIPS_VPE_LOADER=y +CONFIG_MIPS_VPE_APSP_API=y +CONFIG_HZ_100=y +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="aprp" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PCI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=m +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +# CONFIG_INET_LRO is not set +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_TUNNEL=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_CLS_IND=y +# CONFIG_WIRELESS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_IDE=y +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_PIIX=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_WLAN is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_G=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/configs/maltasmtc_defconfig b/arch/mips/configs/maltasmtc_defconfig new file mode 100644 index 0000000..ee19a15 --- /dev/null +++ b/arch/mips/configs/maltasmtc_defconfig @@ -0,0 +1,198 @@ +CONFIG_MIPS_MALTA=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_MIPS_MT_SMTC=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_NR_CPUS=9 +CONFIG_HZ_48=y +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="smtc" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PCI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=m +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +# CONFIG_INET_LRO is not set +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_TUNNEL=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_CLS_IND=y +# CONFIG_WIRELESS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_IDE=y +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_PIIX=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_WLAN is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_G=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig new file mode 100644 index 0000000..b0fca9e --- /dev/null +++ b/arch/mips/configs/maltasmvp_defconfig @@ -0,0 +1,201 @@ +CONFIG_MIPS_MALTA=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_MIPS_MT_SMP=y +CONFIG_SCHED_SMT=y +CONFIG_MIPS_CMP=y +CONFIG_NR_CPUS=8 +CONFIG_HZ_48=y +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="cmp" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PCI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=m +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +# CONFIG_INET_LRO is not set +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_TUNNEL=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_CLS_IND=y +# CONFIG_WIRELESS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_IDE=y +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_PIIX=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=4 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_G=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/configs/maltaup_defconfig b/arch/mips/configs/maltaup_defconfig new file mode 100644 index 0000000..c2c4f6e --- /dev/null +++ b/arch/mips/configs/maltaup_defconfig @@ -0,0 +1,196 @@ +CONFIG_MIPS_MALTA=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HZ_100=y +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="up" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PCI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=m +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +# CONFIG_INET_LRO is not set +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_TUNNEL=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_CLS_IND=y +# CONFIG_WIRELESS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_IDE=y +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_PIIX=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_WLAN is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_G=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:30:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:30:34 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60436 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816521Ab2LGFadb3k4p (ORCPT ); Fri, 7 Dec 2012 06:30:33 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqW3-0007R1-DC; Thu, 06 Dec 2012 23:30:27 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 0/2] Support ASID size determination at boot time. Date: Thu, 6 Dec 2012 23:30:20 -0600 Message-Id: <1354858222-29519-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35236 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1001 Lines: 25 From: "Steven J. Hill" With the release of the new Aptiv cores from MIPS Technologies, Inc. the ASID size must be determined at boot time and cannot simply be hardcoded as before. This has been tested on our Malta and SEAD-3 platforms with 1004K, 1074K, M14KEc, proAptiv and interAptiv cores. Steven J. Hill (2): MIPS: Allow ASID size to be determined at boot time. MIPS: microMIPS: Support dynamic ASID sizing. arch/mips/include/asm/mmu_context.h | 84 ++++++++++++++++++++++------------- arch/mips/kernel/genex.S | 2 +- arch/mips/kernel/traps.c | 6 ++- arch/mips/lib/dump_tlb.c | 5 ++- arch/mips/lib/r3k_dump_tlb.c | 6 +-- arch/mips/mm/tlb-r3k.c | 20 ++++----- arch/mips/mm/tlb-r4k.c | 2 +- arch/mips/mm/tlb-r8k.c | 2 +- arch/mips/mm/tlbex.c | 80 +++++++++++++++++++++++++++++++++ 9 files changed, 156 insertions(+), 51 deletions(-) -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:30:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:30:54 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60438 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831898Ab2LGFaeYElFd (ORCPT ); Fri, 7 Dec 2012 06:30:34 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqW4-0007R1-3O; Thu, 06 Dec 2012 23:30:28 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 1/2] MIPS: Allow ASID size to be determined at boot time. Date: Thu, 6 Dec 2012 23:30:21 -0600 Message-Id: <1354858222-29519-2-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354858222-29519-1-git-send-email-sjhill@mips.com> References: <1354858222-29519-1-git-send-email-sjhill@mips.com> X-archive-position: 35237 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13865 Lines: 423 From: "Steven J. Hill" Original patch by Ralf Baechle and removed by Harold Koerfgen with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This allows for more generic kernels since the size of the ASID and corresponding masks can be determined at run-time. This patch is also required for the new Aptiv cores and has been tested on Malta and Malta Aptiv platforms. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mmu_context.h | 84 ++++++++++++++++++++++------------- arch/mips/kernel/genex.S | 2 +- arch/mips/kernel/traps.c | 6 ++- arch/mips/lib/dump_tlb.c | 5 ++- arch/mips/lib/r3k_dump_tlb.c | 6 +-- arch/mips/mm/tlb-r3k.c | 20 ++++----- arch/mips/mm/tlb-r4k.c | 2 +- arch/mips/mm/tlb-r8k.c | 2 +- arch/mips/mm/tlbex.c | 51 +++++++++++++++++++++ 9 files changed, 127 insertions(+), 51 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 9b02cfb..74852ed 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -62,51 +62,73 @@ extern unsigned long pgd_current[]; TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) -#define ASID_INC 0x40 -#define ASID_MASK 0xfc0 - -#elif defined(CONFIG_CPU_R8000) - -#define ASID_INC 0x10 -#define ASID_MASK 0xff0 - -#elif defined(CONFIG_CPU_RM9000) - -#define ASID_INC 0x1 -#define ASID_MASK 0xfff - -/* SMTC/34K debug hack - but maybe we'll keep it */ -#elif defined(CONFIG_MIPS_MT_SMTC) +#ifndef CONFIG_MIPS_MT_SMTC +#define ASID_INC(asid) \ +({ \ + unsigned long __asid = asid; \ + __asm__("1:\taddiu\t%0,1\t\t\t\t# patched\n\t" \ + ".section\t__asid_inc,\"a\"\n\t" \ + ".word\t1b\n\t" \ + ".previous" \ + :"=r" (__asid) \ + :"0" (__asid)); \ + __asid; \ +}) +#define ASID_MASK(asid) \ +({ \ + unsigned long __asid = asid; \ + __asm__("1:\tandi\t%0,%1,0xfc0\t\t\t# patched\n\t" \ + ".section\t__asid_mask,\"a\"\n\t" \ + ".word\t1b\n\t" \ + ".previous" \ + :"=r" (__asid) \ + :"r" (__asid)); \ + __asid; \ +}) +#define ASID_VERSION_MASK \ +({ \ + unsigned long __asid; \ + __asm__("1:\tli\t%0,0xff00\t\t\t\t# patched\n\t" \ + ".section\t__asid_version_mask,\"a\"\n\t" \ + ".word\t1b\n\t" \ + ".previous" \ + :"=r" (__asid)); \ + __asid; \ +}) +#define ASID_FIRST_VERSION \ +({ \ + unsigned long __asid = asid; \ + __asm__("1:\tli\t%0,0x100\t\t\t\t# patched\n\t" \ + ".section\t__asid_first_version,\"a\"\n\t" \ + ".word\t1b\n\t" \ + ".previous" \ + :"=r" (__asid)); \ + __asid; \ +}) + +#define ASID_FIRST_VERSION_R3000 0x1000 +#define ASID_FIRST_VERSION_R4000 0x100 +#define ASID_FIRST_VERSION_R8000 0x1000 +#define ASID_FIRST_VERSION_RM9000 0x1000 +#define ASID_FIRST_VERSION_99K 0x1000 +#else +/* SMTC/34K debug hack. */ #define ASID_INC 0x1 extern unsigned long smtc_asid_mask; #define ASID_MASK (smtc_asid_mask) #define HW_ASID_MASK 0xff -/* End SMTC/34K debug hack */ -#else /* FIXME: not correct for R6000 */ - -#define ASID_INC 0x1 -#define ASID_MASK 0xff - #endif #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) -#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) +#define cpu_asid(cpu, mm) ASID_MASK(cpu_context((cpu), (mm))) #define asid_cache(cpu) (cpu_data[cpu].asid_cache) static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { } -/* - * All unused by hardware upper bits will be considered - * as a software asid extension. - */ -#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) -#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) - #ifndef CONFIG_MIPS_MT_SMTC /* Normal, classic MIPS get_new_mmu_context */ static inline void @@ -114,7 +136,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) { unsigned long asid = asid_cache(cpu); - if (! ((asid += ASID_INC) & ASID_MASK) ) { + if (!ASID_MASK((asid = ASID_INC(asid)))) { if (cpu_has_vtag_icache) flush_icache_all(); local_flush_tlb_all(); /* start new asid cycle */ diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index dc7d756..cff6e06 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -494,7 +494,7 @@ NESTED(nmi_handler, PT_SIZE, sp) .set noreorder /* check if TLB contains a entry for EPC */ MFC0 k1, CP0_ENTRYHI - andi k1, 0xff /* ASID_MASK */ + andi k1, 0xff /* ASID_MASK patched at run-time!! */ MFC0 k0, CP0_EPC PTR_SRL k0, PAGE_SHIFT + 1 PTR_SLL k0, PAGE_SHIFT + 1 diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index feccbe8..0d3d742 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1664,6 +1664,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) unsigned int cpu = smp_processor_id(); unsigned int status_set = ST0_CU0; unsigned int hwrena = cpu_hwrena_impl_bits; + unsigned long asid = 0; #ifdef CONFIG_MIPS_MT_SMTC int secondaryTC = 0; int bootTC = (cpu == 0); @@ -1747,8 +1748,9 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) } #endif /* CONFIG_MIPS_MT_SMTC */ - if (!cpu_data[cpu].asid_cache) - cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; + asid = ASID_FIRST_VERSION; + cpu_data[cpu].asid_cache = asid; + TLBMISS_HANDLER_SETUP(); atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index a99c1d3..27be26c 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -11,6 +11,7 @@ #include #include #include +#include static inline const char *msk2str(unsigned int mask) { @@ -55,7 +56,7 @@ static void dump_tlb(int first, int last) s_pagemask = read_c0_pagemask(); s_entryhi = read_c0_entryhi(); s_index = read_c0_index(); - asid = s_entryhi & 0xff; + asid = ASID_MASK(s_entryhi); for (i = first; i <= last; i++) { write_c0_index(i); @@ -85,7 +86,7 @@ static void dump_tlb(int first, int last) printk("va=%0*lx asid=%02lx\n", width, (entryhi & ~0x1fffUL), - entryhi & 0xff); + ASID_MASK(entryhi)); printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ", width, (entrylo0 << 6) & PAGE_MASK, c0, diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c index 9cee907..361c46c 100644 --- a/arch/mips/lib/r3k_dump_tlb.c +++ b/arch/mips/lib/r3k_dump_tlb.c @@ -21,7 +21,7 @@ static void dump_tlb(int first, int last) unsigned int asid; unsigned long entryhi, entrylo0; - asid = read_c0_entryhi() & 0xfc0; + asid = ASID_MASK(read_c0_entryhi()); for (i = first; i <= last; i++) { write_c0_index(i<<8); @@ -35,7 +35,7 @@ static void dump_tlb(int first, int last) /* Unused entries have a virtual address of KSEG0. */ if ((entryhi & 0xffffe000) != 0x80000000 - && (entryhi & 0xfc0) == asid) { + && (ASID_MASK(entryhi) == asid)) { /* * Only print entries in use */ @@ -44,7 +44,7 @@ static void dump_tlb(int first, int last) printk("va=%08lx asid=%08lx" " [pa=%06lx n=%d d=%d v=%d g=%d]", (entryhi & 0xffffe000), - entryhi & 0xfc0, + ASID_MASK(entryhi), entrylo0 & PAGE_MASK, (entrylo0 & (1 << 11)) ? 1 : 0, (entrylo0 & (1 << 10)) ? 1 : 0, diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index a63d1ed..4a13c15 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -51,7 +51,7 @@ void local_flush_tlb_all(void) #endif local_irq_save(flags); - old_ctx = read_c0_entryhi() & ASID_MASK; + old_ctx = ASID_MASK(read_c0_entryhi()); write_c0_entrylo0(0); entry = r3k_have_wired_reg ? read_c0_wired() : 8; for (; entry < current_cpu_data.tlbsize; entry++) { @@ -87,13 +87,13 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, #ifdef DEBUG_TLB printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", - cpu_context(cpu, mm) & ASID_MASK, start, end); + ASID_MASK(cpu_context(cpu, mm)), start, end); #endif local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; if (size <= current_cpu_data.tlbsize) { - int oldpid = read_c0_entryhi() & ASID_MASK; - int newpid = cpu_context(cpu, mm) & ASID_MASK; + int oldpid = ASID_MASK(read_c0_entryhi()); + int newpid = ASID_MASK(cpu_context(cpu, mm)); start &= PAGE_MASK; end += PAGE_SIZE - 1; @@ -166,10 +166,10 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) #ifdef DEBUG_TLB printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu, vma->vm_mm), page); #endif - newpid = cpu_context(cpu, vma->vm_mm) & ASID_MASK; + newpid = ASID_MASK(cpu_context(cpu, vma->vm_mm)); page &= PAGE_MASK; local_irq_save(flags); - oldpid = read_c0_entryhi() & ASID_MASK; + oldpid = ASID_MASK(read_c0_entryhi()); write_c0_entryhi(page | newpid); BARRIER; tlb_probe(); @@ -197,10 +197,10 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) if (current->active_mm != vma->vm_mm) return; - pid = read_c0_entryhi() & ASID_MASK; + pid = ASID_MASK(read_c0_entryhi()); #ifdef DEBUG_TLB - if ((pid != (cpu_context(cpu, vma->vm_mm) & ASID_MASK)) || (cpu_context(cpu, vma->vm_mm) == 0)) { + if ((pid != ASID_MASK(cpu_context(cpu, vma->vm_mm))) || (cpu_context(cpu, vma->vm_mm) == 0)) { printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n", (cpu_context(cpu, vma->vm_mm)), pid); } @@ -241,7 +241,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, local_irq_save(flags); /* Save old context and create impossible VPN2 value */ - old_ctx = read_c0_entryhi() & ASID_MASK; + old_ctx = ASID_MASK(read_c0_entryhi()); old_pagemask = read_c0_pagemask(); w = read_c0_wired(); write_c0_wired(w + 1); @@ -264,7 +264,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, #endif local_irq_save(flags); - old_ctx = read_c0_entryhi() & ASID_MASK; + old_ctx = ASID_MASK(read_c0_entryhi()); write_c0_entrylo0(entrylo0); write_c0_entryhi(entryhi); write_c0_index(wired); diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 88e79ad..76b9e60 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -285,7 +285,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) ENTER_CRITICAL(flags); - pid = read_c0_entryhi() & ASID_MASK; + pid = ASID_MASK(read_c0_entryhi()); address &= (PAGE_MASK << 1); write_c0_entryhi(address | pid); pgdp = pgd_offset(vma->vm_mm, address); diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c index 91c2499..122f920 100644 --- a/arch/mips/mm/tlb-r8k.c +++ b/arch/mips/mm/tlb-r8k.c @@ -195,7 +195,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) if (current->active_mm != vma->vm_mm) return; - pid = read_c0_entryhi() & ASID_MASK; + pid = ASID_MASK(read_c0_entryhi()); local_irq_save(flags); address &= PAGE_MASK; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4c23656..6983454 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -261,6 +262,54 @@ static struct uasm_reloc relocs[128] __cpuinitdata; static int check_for_high_segbits __cpuinitdata; #endif +#ifndef CONFIG_MIPS_MT_SMTC +/* Fixup an immediate instruction. */ +static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop, + unsigned int i_const) +{ + unsigned int **p, *ip; + + for (p = start; p < stop; p++) { + ip = *p; + *ip = (*ip & 0xffff0000) | i_const; + } +} + +#define asid_insn_fixup(section, const) \ +do { \ + extern unsigned int *__start_ ## section; \ + extern unsigned int *__stop_ ## section; \ + insn_fixup(&__start_ ## section, &__stop_ ## section, const); \ +} while(0) + +/* Caller is assumed to flush the caches before first context switch. */ +static void __cpuinit setup_asid(unsigned int inc, unsigned int mask, + unsigned int version_mask, + unsigned int first_version) +{ + extern asmlinkage void handle_ri_rdhwr_vivt(void); + unsigned long *vivt_exc; + + asid_insn_fixup(__asid_inc, inc); + asid_insn_fixup(__asid_mask, mask); + asid_insn_fixup(__asid_version_mask, version_mask); + asid_insn_fixup(__asid_first_version, first_version); + + /* Patch up the 'handle_ri_rdhwr_vivt' handler. */ + vivt_exc = (unsigned long *) &handle_ri_rdhwr_vivt; + vivt_exc++; + *vivt_exc = (*vivt_exc & ~mask) | mask; + + current_cpu_data.asid_cache = first_version; +} +#else +static void __cpuinit setup_asid(unsigned int inc, unsigned int mask, + unsigned int version_mask, + unsigned int first_version) +{ +} +#endif + static int check_for_high_segbits __cpuinitdata; static unsigned int kscratch_used_mask __cpuinitdata; @@ -2175,6 +2224,7 @@ void __cpuinit build_tlb_refill_handler(void) case CPU_TX3922: case CPU_TX3927: #ifndef CONFIG_MIPS_PGD_C0_CONTEXT + setup_asid(0x40, 0xfc0, 0xf000, ASID_FIRST_VERSION_R3000); build_r3000_tlb_refill_handler(); if (!run_once) { build_r3000_tlb_load_handler(); @@ -2198,6 +2248,7 @@ void __cpuinit build_tlb_refill_handler(void) #endif /* !CONFIG_CPU_MIPS32_R2 */ default: + setup_asid(0x1, 0xff, 0xff00, ASID_FIRST_VERSION_R4000); if (!run_once) { scratch_reg = allocate_kscratch(); #ifdef CONFIG_MIPS_PGD_C0_CONTEXT -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:30:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:31:12 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60440 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831907Ab2LGFaehXUyH (ORCPT ); Fri, 7 Dec 2012 06:30:34 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqW4-0007R1-Jf; Thu, 06 Dec 2012 23:30:28 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 2/2] MIPS: microMIPS: Support dynamic ASID sizing. Date: Thu, 6 Dec 2012 23:30:22 -0600 Message-Id: <1354858222-29519-3-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354858222-29519-1-git-send-email-sjhill@mips.com> References: <1354858222-29519-1-git-send-email-sjhill@mips.com> X-archive-position: 35238 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1994 Lines: 73 From: "Steven J. Hill" Changes for pure microMIPS cores to dynamically determine the ASID size at boot time. Signed-off-by: Steven J. Hill --- arch/mips/mm/tlbex.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 6983454..5ffec3d 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -267,11 +267,29 @@ static int check_for_high_segbits __cpuinitdata; static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop, unsigned int i_const) { - unsigned int **p, *ip; + unsigned int **p; for (p = start; p < stop; p++) { +#ifndef CONFIG_CPU_MICROMIPS + unsigned int *ip; + ip = *p; *ip = (*ip & 0xffff0000) | i_const; +#else + unsigned short *ip; + + ip = ((unsigned short *)((unsigned int)*p - 1)); + if ((*ip & 0xf000) == 0x4000) { + *ip &= 0xfff1; + *ip |= (i_const << 1); + } else if ((*ip & 0xf000) == 0x6000) { + *ip &= 0xfff1; + *ip |= ((i_const >> 2) << 1); + } else { + ip++; + *ip = i_const; + } +#endif } } @@ -290,6 +308,14 @@ static void __cpuinit setup_asid(unsigned int inc, unsigned int mask, extern asmlinkage void handle_ri_rdhwr_vivt(void); unsigned long *vivt_exc; +#ifdef CONFIG_CPU_MICROMIPS + /* + * Worst case optimised microMIPS addiu instructions support + * only a 3-bit immediate value. + */ + if(inc > 7) + panic("Invalid ASID increment value!"); +#endif asid_insn_fixup(__asid_inc, inc); asid_insn_fixup(__asid_mask, mask); asid_insn_fixup(__asid_version_mask, version_mask); @@ -297,6 +323,9 @@ static void __cpuinit setup_asid(unsigned int inc, unsigned int mask, /* Patch up the 'handle_ri_rdhwr_vivt' handler. */ vivt_exc = (unsigned long *) &handle_ri_rdhwr_vivt; +#ifdef CONFIG_CPU_MICROMIPS + vivt_exc = (unsigned long *)((unsigned long) vivt_exc - 1); +#endif vivt_exc++; *vivt_exc = (*vivt_exc & ~mask) | mask; -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:31:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:31:33 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60445 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831905Ab2LGFba4ZvLk (ORCPT ); Fri, 7 Dec 2012 06:31:30 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqWy-0007RM-GZ; Thu, 06 Dec 2012 23:31:24 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Make CP0 config registers readable via sysfs. Date: Thu, 6 Dec 2012 23:31:20 -0600 Message-Id: <1354858280-29576-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35239 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3891 Lines: 130 From: "Steven J. Hill" Allow reading of CP0 config registers via sysfs for each core in the system. The registers will show up in sysfs at the path: /sys/devices/system/cpu/cpuX/configX Only CP0 config registers 0 through 7 are currently supported. Signed-off-by: Steven J. Hill --- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/sysfs.c | 93 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 arch/mips/kernel/sysfs.c diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index e034ad6..e208a6b 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -98,6 +98,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o +obj-y += sysfs.o ifeq ($(CONFIG_CPU_MIPS32), y) # diff --git a/arch/mips/kernel/sysfs.c b/arch/mips/kernel/sysfs.c new file mode 100644 index 0000000..a64f559 --- /dev/null +++ b/arch/mips/kernel/sysfs.c @@ -0,0 +1,93 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include + +#include + + +#define __BUILD_CP0_SYSFS(reg) \ +static DEFINE_PER_CPU(unsigned int, cpu_config##reg); \ +static ssize_t show_config##reg(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct cpu *cpu = container_of(dev, struct cpu, dev); \ + int n = snprintf(buf, PAGE_SIZE-2, "%x\n", \ + per_cpu(cpu_config##reg, cpu->dev.id)); \ + return n; \ +} \ +static DEVICE_ATTR(config##reg, 0444, show_config##reg, NULL); + +__BUILD_CP0_SYSFS(0) +__BUILD_CP0_SYSFS(1) +__BUILD_CP0_SYSFS(2) +__BUILD_CP0_SYSFS(3) +__BUILD_CP0_SYSFS(4) +__BUILD_CP0_SYSFS(5) +__BUILD_CP0_SYSFS(6) +__BUILD_CP0_SYSFS(7) + +static void read_c0_registers(void *arg) +{ + struct device *dev = get_cpu_device(smp_processor_id()); + struct cpu *cpu; + int ok; + + if (dev != NULL) { + cpu = container_of(dev, struct cpu, dev); + per_cpu(cpu_config0, cpu->dev.id) = read_c0_config(); + device_create_file(dev, &dev_attr_config0); + ok = per_cpu(cpu_config0, cpu->dev.id) & MIPS_CONF_M; + } else + return; + + if (ok) { + per_cpu(cpu_config1, cpu->dev.id) = read_c0_config1(); + device_create_file(dev, &dev_attr_config1); + ok = per_cpu(cpu_config1, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config2, cpu->dev.id) = read_c0_config2(); + device_create_file(dev, &dev_attr_config2); + ok = per_cpu(cpu_config2, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config3, cpu->dev.id) = read_c0_config3(); + device_create_file(dev, &dev_attr_config3); + ok = per_cpu(cpu_config3, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config4, cpu->dev.id) = read_c0_config4(); + device_create_file(dev, &dev_attr_config4); + ok = per_cpu(cpu_config4, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config5, cpu->dev.id) = read_c0_config5(); + device_create_file(dev, &dev_attr_config5); + ok = per_cpu(cpu_config5, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config6, cpu->dev.id) = read_c0_config6(); + device_create_file(dev, &dev_attr_config6); + ok = per_cpu(cpu_config6, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config7, cpu->dev.id) = read_c0_config7(); + device_create_file(dev, &dev_attr_config7); + ok = per_cpu(cpu_config7, cpu->dev.id) & MIPS_CONF_M; + } +} + +static int __init mips_sysfs_registers(void) +{ + on_each_cpu(read_c0_registers, NULL, 1); + return 0; +} +late_initcall(mips_sysfs_registers); -- 1.7.9.5 From sjhill@mips.com Fri Dec 7 06:31:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 06:31:51 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60448 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831907Ab2LGFbrCtBa0 (ORCPT ); Fri, 7 Dec 2012 06:31:47 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TgqXE-0007RX-To; Thu, 06 Dec 2012 23:31:40 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Add printing of ISA version in cpuinfo. Date: Thu, 6 Dec 2012 23:31:36 -0600 Message-Id: <1354858296-29620-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35240 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 827 Lines: 29 From: "Steven J. Hill" Display the MIPS ISA version release in the /proc/cpuinfo file. Signed-off-by: Steven J. Hill --- arch/mips/kernel/proc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 54ac39a..27ce57e 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -64,6 +64,12 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_data[n].watch_reg_masks[i]); seq_printf(m, "]\n"); } + if (cpu_has_mips_r) { + seq_printf(m, "ISA version\t\t:"); + if (cpu_has_mips_r1) seq_printf(m, "%s", " r1"); + if (cpu_has_mips_r2) seq_printf(m, "%s", " r2"); + seq_printf(m, "\n"); + } seq_printf(m, "ASEs implemented\t:"); if (cpu_has_mips16) seq_printf(m, "%s", " mips16"); -- 1.7.9.5 From john@phrozen.org Fri Dec 7 08:42:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 08:42:16 +0100 (CET) Received: from nbd.name ([46.4.11.11]:44171 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823012Ab2LGHmP3myGM (ORCPT ); Fri, 7 Dec 2012 08:42:15 +0100 Message-ID: <50C19D6D.5010700@phrozen.org> Date: Fri, 07 Dec 2012 08:40:29 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH] OF: MIPS: sead3: Implement OF support. References: <1354857297-28863-1-git-send-email-sjhill@mips.com> In-Reply-To: <1354857297-28863-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35241 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1075 Lines: 43 Hi, > obj-y += sead3-i2c-dev.o sead3-i2c.o \ > @@ -17,3 +19,11 @@ obj-y += sead3-i2c-dev.o sead3-i2c.o \ > > obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o > obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o > + > +DTS_FILES = sead3.dts > +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) > + > +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) > + > +$(obj)/%.dtb: $(obj)/%.dts FORCE > + $(call if_changed_dep,dtc) there is a patch already in -next that obseletes this > +void __init device_tree_init(void) > +{ > + unsigned long base, size; > + > + if (!initial_boot_params) > + return; > + > + base = virt_to_phys((void *)initial_boot_params); > + size = be32_to_cpu(initial_boot_params->totalsize); > + > + /* Before we do anything, lets reserve the dt blob */ > + reserve_bootmem(base, size, BOOTMEM_DEFAULT); > + > + unflatten_device_tree(); > + > + /* free the space reserved for the dt blob */ > + free_bootmem(base, size); this free is one free too many. it will kill the devcietree. the code where you copied this from has been fixed in -next John From cernekee@gmail.com Fri Dec 7 08:50:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 08:50:18 +0100 (CET) Received: from mail-la0-f49.google.com ([209.85.215.49]:58369 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817667Ab2LGHuQ2J4HG (ORCPT ); Fri, 7 Dec 2012 08:50:16 +0100 Received: by mail-la0-f49.google.com with SMTP id r15so126014lag.36 for ; Thu, 06 Dec 2012 23:50:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=OmVDLNuljPaxFnEcCIvlZiRwCgPMwcGpWOgGLQ4/p8Y=; b=kKnfilgWtCg2XROoRyQm1AjKof3SY07oyjZUMU9kfssQ5sg2EJwx7CtLj9ru140aMA K1IJE75Odey+Cch80J9G9+p2eLeaHYcfKMwqiflm8u+wvA7qBCpzZ2FMGCVXug3PqM+K H/ZRerG+M52SADVKJdobc76EJF9XXdIS7aH+nITunj6KmxLNAOqSJAhjuz0/cZ1QbIr6 4K8QcYuQ5pG40j/dUlw1pt3rkOmK3v5dbJEEHalqjchBs/URR3+arOUX1F84590yMWMQ gdUr68OQCNVkn7lqBDVzrJjGkDwecXZGzdxr6+5ZHr5WFyETyPNemi6bhgEllDOqQUR0 n93w== MIME-Version: 1.0 Received: by 10.112.47.233 with SMTP id g9mr2181270lbn.11.1354866610679; Thu, 06 Dec 2012 23:50:10 -0800 (PST) Received: by 10.114.20.137 with HTTP; Thu, 6 Dec 2012 23:50:10 -0800 (PST) In-Reply-To: <1354856737-28678-2-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> <1354856737-28678-2-git-send-email-sjhill@mips.com> Date: Thu, 6 Dec 2012 23:50:10 -0800 Message-ID: Subject: Re: [PATCH v99,01/13] MIPS: microMIPS: Add support for microMIPS instructions. From: Kevin Cernekee To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 35242 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6547 Lines: 199 On Thu, Dec 6, 2012 at 9:05 PM, Steven J. Hill wrote: > @@ -267,6 +268,225 @@ struct b_format { /* BREAK and SYSCALL */ > unsigned int func:6; > }; > > +struct fb_format { /* FPU branch format */ > + unsigned int opcode:6; > + unsigned int bc:5; > + unsigned int cc:3; > + unsigned int flag:2; > + unsigned int simmediate:16; > +}; Some random thoughts/nitpicks on this section: The microMIPS patch nearly quadruples the number of instruction formats in the mips_instruction union, so it might be worth considering questions like: 1) Is this the optimal way to represent this information, or have we reached a point where it is worth adding more complex "infrastructure" that would support a more compact instruction definition format? 2) Is there a better way to handle the LE/BE bitfield problem, than to duplicate each of the 28+ structs? On the nitpick front: 3) After "struct NAME_format {", are tabs or spaces used to offset the comment? Seems like a mix. (The original code isn't entirely consistent either, but this could be an opportunity to tidy it up.) 4) Spaces around ':' in e.g. "opcode:6" would be more consistent with "most" of the other entries in inst.h 5) Should "FPU multipy" be "FPU multiply"? 6) The names of the special MIPS16e structs (rr, jal, i64, ri*) are a little terse and may create a conflict someday. If you don't want to use "INSTR_format" for specific instruction names, you could use something like "INSTR_instr" instead. > +struct jal { > + unsigned int opcode:5; > + unsigned int x:1; > + unsigned int imm20_16:5; > + signed int imm25_21:5; > + /* unsigned int imm20_15:0; here is only first 16bits in first HW */ I'm assuming this meant to say: "there are only 16 bits in the first halfword"? It might be clearer to just leave a comment like: + signed int imm25_21:5; + /* the subsequent [or previous] halfword contains imm15_0 */ > +/* > + * This functions returns 1 if the microMIPS instr is a 16 bit instr. Suggest "This function returns" > + * Otherwise return 0. > + */ > +#define MIPS_ISA_MODE 01 > +#define is16mode(regs) (regs->cp0_epc & MIPS_ISA_MODE) > + > +static inline int mm_is16bit(u16 instr) Does the comment refer to the is16mode() macro, or to mm_is16bit()? Does is16mode(), which tests EPC during exception handling, belong in the uasm header file? You might want to indicate that the value passed into mm_is16bit() is either a complete 16-bit MM (microMIPS) instruction, or the most significant halfword of a 32-bit MM instruction. i.e. it isn't necessarily a complete instruction > + { insn_bltzl, 0, 0 }, > + { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM }, > + { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM }, > + { insn_daddu, 0, 0 }, > + { insn_daddiu, 0, 0 }, > + { insn_dmfc0, 0, 0 }, Do the "{ insn_X, 0, 0 }" entries indicate that these instructions (which were defined in MIPS mode) are unsupported in MM mode? > +static inline __uasminit u32 build_bimm(s32 arg) > +{ > + if(arg > 0xffff || arg < -0x10000) "if(" triggers a checkpatch violation (there are a few others too). > + printk(KERN_WARNING "Micro-assembler field overflow\n"); Consider pr_warning() > +static inline __uasminit u32 build_jimm(u32 arg) > +{ > + if ((arg & ~(JIMM_MASK << 1)) - 1) > + printk(KERN_WARNING "Micro-assembler field overflow\n"); This expression evaluates to -1 (i.e. print a warning) for small values of arg, like 0 or 4. Would something like this work? arg >>= 1; if (arg & ~JIMM_MASK) pr_warning("Micro-assembler field overflow\n"); return arg & JIMM_MASK; > +/* > + * The order of opcode arguments is implicitly left to right, > + * starting with RS and ending with FUNC or IMM. > + */ > +static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) There are a lot of similarities between the MM and MIPS versions of these functions. Likewise for build_bimm() and build_jimm(), which only differ because the shifts/ranges are not the same. Is there a way to make better reuse of the code? > +#ifdef CONFIG_CPU_LITTLE_ENDIAN > + **buf = ((op & 0xffff) << 16) | (op >> 16); > +#else > + **buf = op; > +#endif If the MM instruction stream can consist of either 16-bit or 32-bit instructions, shouldn't this be a "u16 **" pointer? And if it is, does that make the LE/BE test unnecessary? > diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c > new file mode 100644 > index 0000000..e86334b > --- /dev/null > +++ b/arch/mips/mm/uasm-mips.c It would be good to have a separate commit that JUST splits uasm.c out into uasm-mips.c (no other changes). The commit message would ideally explain the rationale. > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. > + */ Suggest leaving the original uasm.c authors' copyright info in the uasm-mips.c header. > +#ifdef CONFIG_CPU_MICROMIPS > +#define RS_SH 16 > +#define RT_SH 21 > +#define SCIMM_MASK 0x3ff > +#define SCIMM_SH 16 Can these be defined in a single place? > - WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); > + if (arg & ~RS_MASK) > + printk(KERN_WARNING "Micro-assembler RS field overflow\n"); Since this looks unrelated to MM support, it might be best to put it in a separate commit. What is the benefit of changing WARN() to printk()? Also, if printk() absolutely must be used, it might make sense to consolidate the uasm warning prints into a single non-inlined function, so that if somebody sees an overflow message and wants to debug the problem, they can set one breakpoint instead of 10+ breakpoints. WARN() may have helped indicate the source of the failure but printk() won't. > - WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); > + if (arg & ~RT_MASK) > + printk(KERN_WARNING "Micro-assembler RT field overflow\n"); FWIW, using a unique string for each error case means the compiler can no longer point all of these printk's to a single copy of the same string... > +#ifdef CONFIG_CPU_MICROMIPS > +#include "uasm-micromips.c" > +#else > +#include "uasm-mips.c" > +#endif There's an awful lot of potential reuse between these two configurations and I'm not sure if it makes sense to split them this way. If possible it would be good if we didn't have to enable CONFIG_CPU_MICROMIPS to know that the MM code compiles. From cernekee@gmail.com Fri Dec 7 08:59:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 08:59:29 +0100 (CET) Received: from mail-lb0-f177.google.com ([209.85.217.177]:39172 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817318Ab2LGH716YNr0 (ORCPT ); Fri, 7 Dec 2012 08:59:27 +0100 Received: by mail-lb0-f177.google.com with SMTP id n10so185407lbo.36 for ; Thu, 06 Dec 2012 23:59:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=YRmf6SDtwqu7yAxj/jJCzb4Vi6yYXiQIwS8m3jkkjVc=; b=h7mx0Z3VrW958KYF1GRoIIH09ghnGCbdjGNa7t4Bi7GVaXdBSm2T8DoVGz+ua7eLPm izVY4JM5BInpDEH4vCPRGLBPoPmhVo0uXl+zS6FEmXr4sEgRe4DdJiPx1bVsR3gau4XQ dbeBydDVdrpVZulQWMssXSBYtINM40CFVX8MlI34pR1svfzUUFllsrPeRe/gdbvtUGB/ 0TFNol4iHhPLd4Y29XLkmb4PTXIQ2xEkiRotFsYA/Te0jEQpM4+IuCTru73dWq5GI401 wDL9cqAKnT+1JEIND2ZkalwKhyzEeczjFrRTRbtTEFwkEHX0UwOaffucltu2O1vmDlLw GHtQ== MIME-Version: 1.0 Received: by 10.112.43.161 with SMTP id x1mr2198235lbl.32.1354867162281; Thu, 06 Dec 2012 23:59:22 -0800 (PST) Received: by 10.114.20.137 with HTTP; Thu, 6 Dec 2012 23:59:22 -0800 (PST) In-Reply-To: <1354856737-28678-3-git-send-email-sjhill@mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> <1354856737-28678-3-git-send-email-sjhill@mips.com> Date: Thu, 6 Dec 2012 23:59:22 -0800 Message-ID: Subject: Re: [PATCH v99,02/13] MIPS: Whitespace clean-ups after microMIPS additions. From: Kevin Cernekee To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 35243 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1002 Lines: 25 On Thu, Dec 6, 2012 at 9:05 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Clean-up tabs, spaces, macros, etc. after adding in microMIPS > instructions for the micro-assembler. My personal preference would be to fix up the whitespace in the existing code first, then make the new (MM) code follow the convention from the get-go. > -struct fp0_format { /* FPU multipy and add format (MIPS32) */ > +struct fp0_format { /* FPU multipy and add format (MIPS32) */ "multiply" > --- a/arch/mips/kernel/proc.c > +++ b/arch/mips/kernel/proc.c > @@ -73,6 +73,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) > if (cpu_has_dsp) seq_printf(m, "%s", " dsp"); > if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); > if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); > + if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); > seq_printf(m, "\n"); This should probably go into a different commit. From fengguang.wu@intel.com Fri Dec 7 11:19:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 11:19:43 +0100 (CET) Received: from mga11.intel.com ([192.55.52.93]:35839 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817667Ab2LGKTlF-G6S (ORCPT ); Fri, 7 Dec 2012 11:19:41 +0100 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 07 Dec 2012 02:19:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,236,1355126400"; d="scan'208";a="260408354" Received: from bee.sh.intel.com (HELO localhost) ([10.239.97.14]) by fmsmga002.fm.intel.com with ESMTP; 07 Dec 2012 02:19:32 -0800 Received: from [192.168.1.143] (helo=hive.lkp.intel.com) by localhost with smtp (Exim 4.80) (envelope-from ) id 1Tgv17-0002rQ-8X; Fri, 07 Dec 2012 18:18:49 +0800 Date: Fri, 07 Dec 2012 18:20:37 +0800 From: kbuild test robot To: "Steven J. Hill" Cc: linux-mips@linux-mips.org Subject: [mips-sjhill:mti-next 31/35] dma-default.c:(.text+0xb958): undefined reference to `hw_coherentio' Message-ID: <50c1c2f5.TyQEXFiN4QI5UfpT%fengguang.wu@intel.com> User-Agent: Heirloom mailx 12.5 6/20/10 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 192.168.1.143 X-SA-Exim-Mail-From: fengguang.wu@intel.com X-SA-Exim-Scanned: No (on localhost); SAEximRunCond expanded to false X-archive-position: 35244 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fengguang.wu@intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2180 Lines: 37 tree: git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill mti-next head: 76965291af22d5e06b8ffff677cfe2b227a9487a commit: 5e8848b05d0c0a6854c7de9f55122ccf2f47a248 [31/35] MIPS: Add option to disable software I/O coherency. config: make ARCH=mips allnoconfig All error/warnings: arch/mips/built-in.o: In function `mips_dma_map_sg': dma-default.c:(.text+0xb310): undefined reference to `coherentio' dma-default.c:(.text+0xb360): undefined reference to `coherentio' arch/mips/built-in.o: In function `mips_dma_map_page': dma-default.c:(.text+0xb430): undefined reference to `coherentio' dma-default.c:(.text+0xb434): undefined reference to `coherentio' arch/mips/built-in.o: In function `mips_dma_unmap_sg': dma-default.c:(.text+0xb58c): undefined reference to `coherentio' arch/mips/built-in.o:dma-default.c:(.text+0xb5bc): more undefined references to `coherentio' follow arch/mips/built-in.o: In function `mips_dma_free_coherent': dma-default.c:(.text+0xb958): undefined reference to `hw_coherentio' dma-default.c:(.text+0xb95c): undefined reference to `hw_coherentio' arch/mips/built-in.o: In function `mips_dma_alloc_coherent': dma-default.c:(.text+0xbae8): undefined reference to `coherentio' dma-default.c:(.text+0xbaec): undefined reference to `coherentio' dma-default.c:(.text+0xbb3c): undefined reference to `hw_coherentio' dma-default.c:(.text+0xbb40): undefined reference to `hw_coherentio' arch/mips/built-in.o: In function `mips_dma_unmap_page': dma-default.c:(.text+0xbb6c): undefined reference to `coherentio' dma-default.c:(.text+0xbb70): undefined reference to `coherentio' arch/mips/built-in.o: In function `mips_dma_sync_single_for_cpu': dma-default.c:(.text+0xbbf8): undefined reference to `coherentio' dma-default.c:(.text+0xbbfc): undefined reference to `coherentio' arch/mips/built-in.o: In function `mips_dma_sync_single_for_device': dma-default.c:(.text+0xbc84): undefined reference to `coherentio' arch/mips/built-in.o:dma-default.c:(.text+0xbc88): more undefined references to `coherentio' follow --- 0-DAY kernel build testing backend Open Source Technology Center Fengguang Wu, Yuanhan Liu Intel Corporation From kirill.shutemov@linux.intel.com Fri Dec 7 12:52:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 12:52:31 +0100 (CET) Received: from mga01.intel.com ([192.55.52.88]:56955 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823910Ab2LGLw3ySzrb (ORCPT ); Fri, 7 Dec 2012 12:52:29 +0100 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 07 Dec 2012 03:52:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,236,1355126400"; d="scan'208";a="260440328" Received: from blue.fi.intel.com ([10.237.72.156]) by fmsmga002.fm.intel.com with ESMTP; 07 Dec 2012 03:52:18 -0800 Received: by blue.fi.intel.com (Postfix, from userid 1000) id D0A93E0073; Fri, 7 Dec 2012 13:53:42 +0200 (EET) From: "Kirill A. Shutemov" To: Andrew Morton , linux-mm@kvack.org, Arnd Bergmann , linux-arch@vger.kernel.org Cc: linux-s390@vger.kernel.org, Martin Schwidefsky , Heiko Carstens , linux-mips@linux-mips.org, Ralf Baechle , John Crispin , "Kirill A. Shutemov" Subject: [PATCH, RESEND] asm-generic, mm: pgtable: consolidate zero page helpers Date: Fri, 7 Dec 2012 13:53:35 +0200 Message-Id: <1354881215-26257-1-git-send-email-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35245 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kirill.shutemov@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4056 Lines: 138 From: "Kirill A. Shutemov" We have two different implementation of is_zero_pfn() and my_zero_pfn() helpers: for architectures with and without zero page coloring. Let's consolidate them in . Signed-off-by: Kirill A. Shutemov --- arch/mips/include/asm/pgtable.h | 11 +---------- arch/s390/include/asm/pgtable.h | 11 +---------- include/asm-generic/pgtable.h | 26 ++++++++++++++++++++++++++ include/linux/mm.h | 8 -------- mm/memory.c | 7 ------- 5 files changed, 28 insertions(+), 35 deletions(-) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 252202d..ec50d52 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -77,16 +77,7 @@ extern unsigned long zero_page_mask; #define ZERO_PAGE(vaddr) \ (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))) - -#define is_zero_pfn is_zero_pfn -static inline int is_zero_pfn(unsigned long pfn) -{ - extern unsigned long zero_pfn; - unsigned long offset_from_zero_pfn = pfn - zero_pfn; - return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); -} - -#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) +#define __HAVE_COLOR_ZERO_PAGE extern void paging_init(void); diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 23d9a8a..c928dc1 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -54,16 +54,7 @@ extern unsigned long zero_page_mask; #define ZERO_PAGE(vaddr) \ (virt_to_page((void *)(empty_zero_page + \ (((unsigned long)(vaddr)) &zero_page_mask)))) - -#define is_zero_pfn is_zero_pfn -static inline int is_zero_pfn(unsigned long pfn) -{ - extern unsigned long zero_pfn; - unsigned long offset_from_zero_pfn = pfn - zero_pfn; - return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); -} - -#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) +#define __HAVE_COLOR_ZERO_PAGE #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h index d03d0a8..04a398e 100644 --- a/include/asm-generic/pgtable.h +++ b/include/asm-generic/pgtable.h @@ -453,6 +453,32 @@ extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, unsigned long size); #endif +#ifdef __HAVE_COLOR_ZERO_PAGE +static inline int is_zero_pfn(unsigned long pfn) +{ + extern unsigned long zero_pfn; + unsigned long offset_from_zero_pfn = pfn - zero_pfn; + return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); +} + +static inline unsigned long my_zero_pfn(unsigned long addr) +{ + return page_to_pfn(ZERO_PAGE(addr)); +} +#else +static inline int is_zero_pfn(unsigned long pfn) +{ + extern unsigned long zero_pfn; + return pfn == zero_pfn; +} + +static inline unsigned long my_zero_pfn(unsigned long addr) +{ + extern unsigned long zero_pfn; + return zero_pfn; +} +#endif + #ifdef CONFIG_MMU #ifndef CONFIG_TRANSPARENT_HUGEPAGE diff --git a/include/linux/mm.h b/include/linux/mm.h index 2984e07..dad5c73 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -516,14 +516,6 @@ static inline pte_t maybe_mkwrite(pte_t pte, struct vm_area_struct *vma) } #endif -#ifndef my_zero_pfn -static inline unsigned long my_zero_pfn(unsigned long addr) -{ - extern unsigned long zero_pfn; - return zero_pfn; -} -#endif - /* * Multiple processes may "see" the same page. E.g. for untouched * mappings of /dev/null, all processes see the same page full of diff --git a/mm/memory.c b/mm/memory.c index 3db03ed..efd870d 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -725,13 +725,6 @@ static inline bool is_cow_mapping(vm_flags_t flags) return (flags & (VM_SHARED | VM_MAYWRITE)) == VM_MAYWRITE; } -#ifndef is_zero_pfn -static inline int is_zero_pfn(unsigned long pfn) -{ - return pfn == zero_pfn; -} -#endif - /* * vm_normal_page -- This function gets the "struct page" associated with a pte. * -- 1.7.10.4 From ralf@linux-mips.org Fri Dec 7 16:09:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 16:09:53 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:43649 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6824772Ab2LGPJvzSP63 (ORCPT ); Fri, 7 Dec 2012 16:09:51 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qB7F9m8C027574; Fri, 7 Dec 2012 16:09:48 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qB7F9kTD027573; Fri, 7 Dec 2012 16:09:46 +0100 Date: Fri, 7 Dec 2012 16:09:46 +0100 From: Ralf Baechle To: "Steven J. Hill" Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Reduce code size for MIPS32R2 platforms. Message-ID: <20121207150946.GA27226@linux-mips.org> References: <1354857289-28828-1-git-send-email-sjhill@mips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1354857289-28828-1-git-send-email-sjhill@mips.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35246 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10210 Lines: 365 On Thu, Dec 06, 2012 at 11:14:49PM -0600, Steven J. Hill wrote: > From: "Steven J. Hill" > > If the CPU type is selected to be a MIPS32R2 core, we surround > some code with #ifdef's to reduce the kernel binary size. > > Signed-off-by: Steven J. Hill Yes, and a dozen more ifdefs would be needed to handle other places where things could be optimized for a particular CPU type. Best add more random ifdefs across the tree to handle MIPS32R1 and MIPS64R2 and of course Zumbitsu 8000 processors. Below is a half-baked test version of a patch that I have in my git tree since you first posted your patch. For a Cavium kernel this shaves off around 6kB. Obviously this patch relies on a halfway modern compiler's optimization capabilities. Ralf arch/mips/cavium-octeon/csrc-octeon.c | 1 + arch/mips/include/asm/cpu-features.h | 4 - arch/mips/include/asm/cpu-type.h | 119 +++++++++++++++++++++ .../include/asm/mach-ip22/cpu-feature-overrides.h | 2 + .../include/asm/mach-ip27/cpu-feature-overrides.h | 2 + .../include/asm/mach-ip28/cpu-feature-overrides.h | 2 + arch/mips/kernel/cpu-probe.c | 5 +- arch/mips/kernel/time.c | 1 + arch/mips/kernel/traps.c | 1 + arch/mips/mm/c-octeon.c | 6 +- arch/mips/mm/dma-default.c | 1 + arch/mips/mm/page.c | 1 + arch/mips/mm/tlb-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 14 files changed, 139 insertions(+), 8 deletions(-) diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c index ce6483a..3bbe8d6 100644 --- a/arch/mips/cavium-octeon/csrc-octeon.c +++ b/arch/mips/cavium-octeon/csrc-octeon.c @@ -12,6 +12,7 @@ #include #include +#include #include #include diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7..33a54c1 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -13,10 +13,6 @@ #include #include -#ifndef current_cpu_type -#define current_cpu_type() current_cpu_data.cputype -#endif - /* * SMP assumption: Options of CPU 0 are a superset of all processors. * This is true for all known MIPS systems. diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h new file mode 100644 index 0000000..0d0afa4 --- /dev/null +++ b/arch/mips/include/asm/cpu-type.h @@ -0,0 +1,119 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef __ASM_CPU_TYPE_H +#define __ASM_CPU_TYPE_H + +#include + +static inline int __pure current_cpu_type(void) +{ + const int cpu_type = current_cpu_data.cputype; + + switch (cpu_type) { +#ifdef CONFIG_SYS_HAS_CPU_LOONGSON2E +#endif + +#ifdef CONFIG_SYS_HAS_CPU_LOONGSON2F +#endif + +#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R3000 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_TX39XX +#endif + +#ifdef CONFIG_SYS_HAS_CPU_VR41XX +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R4300 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R4X00 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_TX49XX +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R5000 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R5432 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R5500 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R6000 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_NEVADA +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R8000 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R10000 + case CPU_R10000: + case CPU_R12000: +#endif +#ifdef CONFIG_SYS_HAS_CPU_RM7000 + case CPU_RM7000: +#endif +#ifdef CONFIG_SYS_HAS_CPU_RM9000 + case CPU_RM9000: +#endif +#ifdef CONFIG_SYS_HAS_CPU_SB1 + case CPU_SB1: + case CPU_SB1A: +#endif +#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_BMIPS3300 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_BMIPS4350 +#endif + +#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380 +#endif + +#ifdef SYS_HAS_CPU_BMIPS5000 +#endif + +#ifdef SYS_HAS_CPU_XLR +#endif + + break; + default: + unreachable(); + } + + return cpu_type; +} + +#endif /* __ASM_CPU_TYPE_H */ diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h index 9c87351..7b23f44 100644 --- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h @@ -8,6 +8,8 @@ #ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H +#include + /* * IP22 with a variety of processors so we can't use defaults for everything. */ diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h index 7d3112b..53bcb73 100644 --- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h @@ -8,6 +8,8 @@ #ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H +#include + /* * IP27 only comes with R10000 family processors all using the same config */ diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h index 9a53b32..0fb7cb5 100644 --- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h @@ -9,6 +9,8 @@ #ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H +#include + /* * IP28 only comes with R10000 family processors all using the same config */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 8ea65c5..1bc2d80 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -159,7 +160,7 @@ void __init check_wait(void) return; } - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_R3081: case CPU_R3081E: cpu_wait = r3081_wait; @@ -252,7 +253,7 @@ static inline void check_errata(void) { struct cpuinfo_mips *c = ¤t_cpu_data; - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_34K: /* * Erratum "RPS May Cause Incorrect Instruction Execution" diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 99d73b7..abd127e 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 9260986..4c58568 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index 44e69e7..e774176 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -184,9 +185,10 @@ static void __cpuinit probe_octeon(void) unsigned long dcache_size; unsigned int config1; struct cpuinfo_mips *c = ¤t_cpu_data; + int cputype = current_cpu_type(); config1 = read_c0_config1(); - switch (c->cputype) { + switch (cputype) { case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: c->icache.linesz = 2 << ((config1 >> 19) & 7); @@ -197,7 +199,7 @@ static void __cpuinit probe_octeon(void) c->icache.sets * c->icache.ways * c->icache.linesz; c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; c->dcache.linesz = 128; - if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) + if (cputype == CPU_CAVIUM_OCTEON_PLUS) c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ else c->dcache.sets = 1; /* CN3XXX has one Dcache set */ diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 3fab204..72df1e4 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -18,6 +18,7 @@ #include #include +#include #include #include diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 98f530e..a37db2f 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -18,6 +18,7 @@ #include #include +#include #include #include #include diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index d2572cb..ac6a90a 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 03eb0ef..a89e523 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include From ralf@linux-mips.org Fri Dec 7 16:24:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 16:24:50 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:43831 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6823102Ab2LGPYt2knDK (ORCPT ); Fri, 7 Dec 2012 16:24:49 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qB7FOiNF028412; Fri, 7 Dec 2012 16:24:44 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qB7FOckh028411; Fri, 7 Dec 2012 16:24:38 +0100 Date: Fri, 7 Dec 2012 16:24:38 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: "Steven J. Hill" , linux-mips@linux-mips.org, "Kevin D. Kissell" Subject: Re: [PATCH v99,01/13] MIPS: microMIPS: Add support for microMIPS instructions. Message-ID: <20121207152438.GC25923@linux-mips.org> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> <1354856737-28678-2-git-send-email-sjhill@mips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35247 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 881 Lines: 21 On Thu, Dec 06, 2012 at 11:50:10PM -0800, Kevin Cernekee wrote: > Some random thoughts/nitpicks on this section: > > The microMIPS patch nearly quadruples the number of instruction > formats in the mips_instruction union, so it might be worth > considering questions like: > > 1) Is this the optimal way to represent this information, or have we > reached a point where it is worth adding more complex "infrastructure" > that would support a more compact instruction definition format? > > 2) Is there a better way to handle the LE/BE bitfield problem, than to > duplicate each of the 28+ structs? Something based on #defines, for example. Back in the dark ages I figured bitfields would be nicer way to represent instruction formats. Against the warning words of I think Kevin Kissel I went for the bitfields and this would be a good opportunity to change direction. Ralf From mcdonald.shane@gmail.com Fri Dec 7 16:55:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Dec 2012 16:55:35 +0100 (CET) Received: from mail-lb0-f177.google.com ([209.85.217.177]:43312 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824759Ab2LGPzd2BAkK (ORCPT ); Fri, 7 Dec 2012 16:55:33 +0100 Received: by mail-lb0-f177.google.com with SMTP id n10so484827lbo.36 for ; Fri, 07 Dec 2012 07:55:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=A7kOjls63oS0doXNCWP7irJGK66TnEmdmIl3ThH4m/Q=; b=FqEwLGtsGDMND0chMy8zLeIGVTJVEmnRNj9xBZ6oGA2YSI918foJAD4o+l0/hqUBMF 6Iz4JPeQ2Lps2GOR6//IEwPipX92Z0LJ90qaXE13VvstpX6HDUwgGMw1KupPWUCZMrhv wAs+42JWZt8bwG6A7wnt47vyGwKg0hz50rXHEPO4CQw1zEkOdnFq18glt6be/2Et4OT5 eAmiqFGYYTJObpSXjJUbyEQzjTu8wZopEnX/sUAAqIhdXvn2gqL2DIht6qItrF19LwXE cmJpZNteoUbJ1s2dTW8lLU7YCJKdv+xT6IVI4dWtPZ0/J/ETWvcZMdkqc1TCllLezcKB PRBQ== MIME-Version: 1.0 Received: by 10.152.105.68 with SMTP id gk4mr5751592lab.48.1354895727737; Fri, 07 Dec 2012 07:55:27 -0800 (PST) Received: by 10.112.114.37 with HTTP; Fri, 7 Dec 2012 07:55:27 -0800 (PST) In-Reply-To: <1354857802-29348-1-git-send-email-sjhill@mips.com> References: <1354857802-29348-1-git-send-email-sjhill@mips.com> Date: Fri, 7 Dec 2012 09:55:27 -0600 Message-ID: Subject: Re: [PATCH] MIPS: Add option to disable software I/O coherency. From: Shane McDonald To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35248 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 537 Lines: 14 On Thu, Dec 6, 2012 at 11:23 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Some MIPS controllers have hardware I/O coherency. This patch > detects those and turns off software coherency. A new kernel > command line option also allows the user to manually turn > software coherency on or off. > > Signed-off-by: Steven J. Hill This patch conflicts with commit b5b64f2ba4 "MIPS: Move processing of coherency kernel parameters earlier" in the linux-next tree. Shane McDonald From florian@openwrt.org Mon Dec 10 15:58:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Dec 2012 15:58:49 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:36700 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831922Ab2LJO6sHakmk (ORCPT ); Mon, 10 Dec 2012 15:58:48 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 9ACC7B8786B; Mon, 10 Dec 2012 15:58:47 +0100 (CET) X-Virus-Scanned: amavisd-new at localhost Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1kjiged+3EJY; Mon, 10 Dec 2012 15:58:47 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 419DAB83F79; Mon, 10 Dec 2012 15:58:47 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, blogic@openwrt.org, Florian Fainelli Subject: [PATCH 3.7-rc8] MIPS: MT: fix build with CONFIG_UIDGID_STRICT_TYPE_CHECKS=y Date: Mon, 10 Dec 2012 15:56:44 +0100 Message-Id: <1355151404-7499-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35250 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1481 Lines: 41 When CONFIG_UIDGID_STRICT_TYPE_CHECKS is enabled, plain integer checking between different uids/gids is explicitely turned into a build failure by making the k{uid,gid}_t types a structure containing a value: arch/mips/kernel/mips-mt-fpaff.c: In function 'check_same_owner': arch/mips/kernel/mips-mt-fpaff.c:53:22: error: invalid operands to binary == (have 'kuid_t' and 'kuid_t') arch/mips/kernel/mips-mt-fpaff.c:54:15: error: invalid operands to binary == (have 'kuid_t' and 'kuid_t') This problem got introduced with commit 17c04139 (MIPS: MT: Fix FPU affinity.) In order to ensure proper comparison between uids, using the helper function uid_eq() which performs the right thing whenever this config option is turned on or off. Signed-off-by: Florian Fainelli --- Ralf, I think you might want to sneak this into 3.7-rc8 if possible at all. arch/mips/kernel/mips-mt-fpaff.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c index 33f63ba..fd814e0 100644 --- a/arch/mips/kernel/mips-mt-fpaff.c +++ b/arch/mips/kernel/mips-mt-fpaff.c @@ -50,8 +50,8 @@ static bool check_same_owner(struct task_struct *p) rcu_read_lock(); pcred = __task_cred(p); - match = (cred->euid == pcred->euid || - cred->euid == pcred->uid); + match = (uid_eq(cred->euid, pcred->euid) || + uid_eq(cred->euid, pcred->uid)); rcu_read_unlock(); return match; } -- 1.7.10.4 From ralf@linux-mips.org Tue Dec 11 12:14:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Dec 2012 12:14:32 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:53521 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6823908Ab2LKLObMfguU (ORCPT ); Tue, 11 Dec 2012 12:14:31 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qBBBETxi027300; Tue, 11 Dec 2012 12:14:29 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qBBBESgY027266; Tue, 11 Dec 2012 12:14:28 +0100 Date: Tue, 11 Dec 2012 12:14:28 +0100 From: Ralf Baechle To: Shane McDonald Cc: linux-mips , linux-kernel@vger.kernel.org Subject: Re: RM9000 / E9000, MSP71xx class processors, SOCs and eval boards Message-ID: <20121211111427.GA23572@linux-mips.org> References: <20121206160052.GB32620@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35251 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1135 Lines: 28 On Thu, Dec 06, 2012 at 03:28:17PM -0600, Shane McDonald wrote: > I'm interested in the MSP71xx eval board, although I may be > the only person in the world who cares. Specifically, I use the > msp71xx_defconfig. 3.7-rc8 compiles with gcc-4.6.3 > without requiring any patches. > > I don't know when the last time the RM9000 was compilable, > but I have no interest in that, nor do I have interest in the > FPGA or eval board versions of the MSP7120 (no hardware to > test with). > > I had hoped that someone from PMC-Sierra would respond, but > maybe they don't care anymore... Being a crazy tradition set by the Sparc AP1000, I'm happy with a single user :-) The Yosemite stuff scores higher on my kill list anyway. The board support code was never too great but that's not the issue; the SOC's network driver which is rotting away in the linux-mips.org git tree as the last change that can't be merged upstream as it is, stopped even compiling ages ago and while a superior replacement has been posted, nobody cared enough to get it into mergeable shape. Now that 3.7 is finally released, hasta la vista, Yosemite. Ralf From hauke@hauke-m.de Wed Dec 12 02:10:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 02:10:37 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:36929 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831957Ab2LLBKeYN4UK (ORCPT ); Wed, 12 Dec 2012 02:10:34 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id CF38C8F67; Wed, 12 Dec 2012 02:10:31 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HO-qkxwLvUy2; Wed, 12 Dec 2012 02:10:18 +0100 (CET) Received: from hauke-desktop.lan (spit-414.wohnheim.uni-bremen.de [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 422E98F64; Wed, 12 Dec 2012 02:10:17 +0100 (CET) From: Hauke Mehrtens To: john@phrozen.org, ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH] MIPS: BCM47XX: fix compile error in wgt634u.c Date: Wed, 12 Dec 2012 02:10:12 +0100 Message-Id: <1355274612-19167-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 35252 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2104 Lines: 54 After the new GPIO handling for the bcm47xx target was introduced wgt634u.c was not changed. This patch fixes the following compile error: arch/mips/bcm47xx/wgt634u.c: In function ‘gpio_interrupt’: arch/mips/bcm47xx/wgt634u.c:119:2: error: implicit declaration of function ‘gpio_polarity’ [-Werror=implicit-function-declaration] arch/mips/bcm47xx/wgt634u.c: In function ‘wgt634u_init’: arch/mips/bcm47xx/wgt634u.c:153:4: error: implicit declaration of function ‘gpio_intmask’ [-Werror=implicit-function-declaration] Reported-by: Ralf Baechle Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/wgt634u.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) I am planing to remove this entire file, but I haven't come up with code adding support for most of the boards found in the wild. diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c index e9f9ec8..6c28f6d 100644 --- a/arch/mips/bcm47xx/wgt634u.c +++ b/arch/mips/bcm47xx/wgt634u.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -116,7 +117,8 @@ static irqreturn_t gpio_interrupt(int irq, void *ignored) /* Interrupt are level triggered, revert the interrupt polarity to clear the interrupt. */ - gpio_polarity(WGT634U_GPIO_RESET, state); + ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << WGT634U_GPIO_RESET, + state ? 1 << WGT634U_GPIO_RESET : 0); if (!state) { printk(KERN_INFO "Reset button pressed"); @@ -150,7 +152,9 @@ static int __init wgt634u_init(void) gpio_interrupt, IRQF_SHARED, "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) { gpio_direction_input(WGT634U_GPIO_RESET); - gpio_intmask(WGT634U_GPIO_RESET, 1); + ssb_gpio_intmask(&bcm47xx_bus.ssb, + 1 << WGT634U_GPIO_RESET, + 1 << WGT634U_GPIO_RESET); ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco, SSB_CHIPCO_IRQ_GPIO, SSB_CHIPCO_IRQ_GPIO); -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 12 02:17:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 02:17:48 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:36983 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831957Ab2LLBRrqCH0m (ORCPT ); Wed, 12 Dec 2012 02:17:47 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 1174F8F69; Wed, 12 Dec 2012 02:17:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c84WLB66ot6v; Wed, 12 Dec 2012 02:17:24 +0100 (CET) Received: from hauke-desktop.lan (spit-414.wohnheim.uni-bremen.de [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 1812F8F65; Wed, 12 Dec 2012 02:17:22 +0100 (CET) From: Hauke Mehrtens To: john@phrozen.org, ralf@linux-mips.org Cc: linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 2/2] ssb: add gpio_to_irq again Date: Wed, 12 Dec 2012 02:17:11 +0100 Message-Id: <1355275031-19297-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1355275031-19297-1-git-send-email-hauke@hauke-m.de> References: <1355275031-19297-1-git-send-email-hauke@hauke-m.de> X-archive-position: 35253 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2503 Lines: 70 The old code had support for gpio_to_irq, but the new code did not provide this function, but returned -ENXIO all the time. This patch adds the missing function. arch/mips/bcm47xx/wgt634u.c calls gpio_to_irq() and got the correct irq number with the old gpio handling code. With this patch the code in wgt634u.c should work again. I do not have a wgt634u to test this. Signed-off-by: Hauke Mehrtens --- drivers/ssb/driver_gpio.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/ssb/driver_gpio.c b/drivers/ssb/driver_gpio.c index 97ac0a3..accabe3 100644 --- a/drivers/ssb/driver_gpio.c +++ b/drivers/ssb/driver_gpio.c @@ -74,6 +74,16 @@ static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio) ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0); } +static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio) +{ + struct ssb_bus *bus = ssb_gpio_get_bus(chip); + + if (bus->bustype == SSB_BUSTYPE_SSB) + return ssb_mips_irq(bus->chipco.dev) + 2; + else + return -EINVAL; +} + static int ssb_gpio_chipco_init(struct ssb_bus *bus) { struct gpio_chip *chip = &bus->gpio; @@ -86,6 +96,7 @@ static int ssb_gpio_chipco_init(struct ssb_bus *bus) chip->set = ssb_gpio_chipco_set_value; chip->direction_input = ssb_gpio_chipco_direction_input; chip->direction_output = ssb_gpio_chipco_direction_output; + chip->to_irq = ssb_gpio_chipco_to_irq; chip->ngpio = 16; /* There is just one SoC in one device and its GPIO addresses should be * deterministic to address them more easily. The other buses could get @@ -134,6 +145,16 @@ static int ssb_gpio_extif_direction_output(struct gpio_chip *chip, return 0; } +static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio) +{ + struct ssb_bus *bus = ssb_gpio_get_bus(chip); + + if (bus->bustype == SSB_BUSTYPE_SSB) + return ssb_mips_irq(bus->extif.dev) + 2; + else + return -EINVAL; +} + static int ssb_gpio_extif_init(struct ssb_bus *bus) { struct gpio_chip *chip = &bus->gpio; @@ -144,6 +165,7 @@ static int ssb_gpio_extif_init(struct ssb_bus *bus) chip->set = ssb_gpio_extif_set_value; chip->direction_input = ssb_gpio_extif_direction_input; chip->direction_output = ssb_gpio_extif_direction_output; + chip->to_irq = ssb_gpio_extif_to_irq; chip->ngpio = 5; /* There is just one SoC in one device and its GPIO addresses should be * deterministic to address them more easily. The other buses could get -- 1.7.10.4 From hauke@hauke-m.de Wed Dec 12 02:17:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 02:18:05 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:36987 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831966Ab2LLBRsQtH8q (ORCPT ); Wed, 12 Dec 2012 02:17:48 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id EC3508F65; Wed, 12 Dec 2012 02:17:47 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BTL5a0ziM33t; Wed, 12 Dec 2012 02:17:22 +0100 (CET) Received: from hauke-desktop.lan (spit-414.wohnheim.uni-bremen.de [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 8717C8F64; Wed, 12 Dec 2012 02:17:20 +0100 (CET) From: Hauke Mehrtens To: john@phrozen.org, ralf@linux-mips.org Cc: linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 1/2] bcma: add gpio_to_irq again Date: Wed, 12 Dec 2012 02:17:10 +0100 Message-Id: <1355275031-19297-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35254 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1358 Lines: 41 The old code had support for gpio_to_irq, but the new code did not provide this function, but returned -ENXIO all the time. This patch adds the missing function. Signed-off-by: Hauke Mehrtens --- drivers/bcma/driver_gpio.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/bcma/driver_gpio.c b/drivers/bcma/driver_gpio.c index 9a6f585..212fda6 100644 --- a/drivers/bcma/driver_gpio.c +++ b/drivers/bcma/driver_gpio.c @@ -73,6 +73,16 @@ static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio) bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); } +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) +{ + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); + + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) + return bcma_core_mips_irq(cc->core) + 2; + else + return -EINVAL; +} + int bcma_gpio_init(struct bcma_drv_cc *cc) { struct gpio_chip *chip = &cc->gpio; @@ -85,6 +95,7 @@ int bcma_gpio_init(struct bcma_drv_cc *cc) chip->set = bcma_gpio_set_value; chip->direction_input = bcma_gpio_direction_input; chip->direction_output = bcma_gpio_direction_output; + chip->to_irq = bcma_gpio_to_irq; chip->ngpio = 16; /* There is just one SoC in one device and its GPIO addresses should be * deterministic to address them more easily. The other buses could get -- 1.7.10.4 From rientjes@google.com Wed Dec 12 04:07:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 04:07:24 +0100 (CET) Received: from mail-pb0-f50.google.com ([209.85.160.50]:46906 "EHLO mail-pb0-f50.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822197Ab2LLDHX0HAE3 (ORCPT ); Wed, 12 Dec 2012 04:07:23 +0100 Received: by mail-pb0-f50.google.com with SMTP id wz7so134581pbc.23 for ; Tue, 11 Dec 2012 19:07:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:x-x-sender:to:cc:subject:in-reply-to:message-id :references:user-agent:mime-version:content-type; bh=AXcc5Eq99161lzFJvTaCxrnO6e8wTJzfXq9SVlSWDck=; b=S3m8NfFNAR+SUOCm7Rnv2DPzXbPO6dkbMPeWgOfe12eDLZt73tjMf7osyknmncn72u XaE9F72soe3SkTE11zpGW6NZqCowRBCJ8GEkQyo4+16yCVD+yFDxVxPKwM/rSomEI0VA ksS/r+HA2YvoaK5JqNILeubEchIVvowDJNTnmo8KSZ+Ss8gpArlJgxJYOSFVCP5O4gxS RSIErUSuGRqc2VXc0PqcLk8SSIWWR1KbfIMe1Pb4gzoEL1ICuIPSavI7vIeljDra/NeH 14ifT/iXx33BlN2eMEFv9AgEFWINf5mkWcl+HN7jAsuLdyFUjSVZbtK8EDENQhWLbTea C1tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:x-x-sender:to:cc:subject:in-reply-to:message-id :references:user-agent:mime-version:content-type:x-gm-message-state; bh=AXcc5Eq99161lzFJvTaCxrnO6e8wTJzfXq9SVlSWDck=; b=iL4AN0TcXUqo66dVmgLsUXpJRRgXAvf2dcYTYvoSZGEiuqPdsSPMgk6vM9Yyzz9Qh/ 3hc3vL/v6fEOH/JHTwYxHL0wZ8deWvBZ8U4sOUUBhNrUKuV7+0cuvlG8j3g23X1NlhYE voUgo2jMNRa/MbMpeI+aYYggfHNoqzkOZqYKfefmwIzAjSVv6Sgbpo8lNxwpPB/KfLsw 2w9xze9f2gJkjpFvVNFhnA97kg5QEqdsiOhY22nERiVTvguhe8gzWG0wIODicAbh7kDp jZK9M4af1Ht8SWoccZnHH1mkSD2y7/18Phls0JVCl5zcL07mGN8ilYLowsAMw8cyJZuH PF7w== Received: by 10.66.88.198 with SMTP id bi6mr1307299pab.54.1355281636043; Tue, 11 Dec 2012 19:07:16 -0800 (PST) Received: from [2620:0:1008:1101:be30:5bff:fed8:5e64] ([2620:0:1008:1101:be30:5bff:fed8:5e64]) by mx.google.com with ESMTPS id o5sm1059149pay.5.2012.12.11.19.07.14 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 11 Dec 2012 19:07:15 -0800 (PST) Date: Tue, 11 Dec 2012 19:07:14 -0800 (PST) From: David Rientjes X-X-Sender: rientjes@chino.kir.corp.google.com To: "Kirill A. Shutemov" cc: Andrew Morton , linux-mm@kvack.org, Arnd Bergmann , linux-arch@vger.kernel.org, linux-s390@vger.kernel.org, Martin Schwidefsky , Heiko Carstens , linux-mips@linux-mips.org, Ralf Baechle , John Crispin Subject: Re: [PATCH, RESEND] asm-generic, mm: pgtable: consolidate zero page helpers In-Reply-To: <1354881215-26257-1-git-send-email-kirill.shutemov@linux.intel.com> Message-ID: References: <1354881215-26257-1-git-send-email-kirill.shutemov@linux.intel.com> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Gm-Message-State: ALoCoQm8Z9ciarVszOTVfJau6SGwPkGGVVmQAl1Ul/hRQEja+GcrU8eZ0HK1qVWaUo2jF8zdp0Kq6tTt+GN4MjSA3GJwUvQ/o5HXdj/cUmOC6a8IwhFm+dTodiLQye7H/JT0upPNaH0ZBN0UZZNULNJHDJhE5AIW1n1138RY0+aFMILJW8YYeNR7wtofCJpAr4LY2LKexwp1QLk7LwjoR/HABF//2fPa+g== X-archive-position: 35255 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rientjes@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 528 Lines: 14 On Fri, 7 Dec 2012, Kirill A. Shutemov wrote: > From: "Kirill A. Shutemov" > > We have two different implementation of is_zero_pfn() and > my_zero_pfn() helpers: for architectures with and without zero page > coloring. > > Let's consolidate them in . > What's the benefit from doing this other than generalizing some per-arch code? It simply adds on more layer of redirection to try to find the implementation that matters for the architecture you're hacking on. From florian@openwrt.org Wed Dec 12 10:15:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 10:15:50 +0100 (CET) Received: from mail-la0-f49.google.com ([209.85.215.49]:47904 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6828015Ab2LLJPtWRjLL (ORCPT ); Wed, 12 Dec 2012 10:15:49 +0100 Received: by mail-la0-f49.google.com with SMTP id r15so353705lag.36 for ; Wed, 12 Dec 2012 01:15:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=QF2kaAKw4I4Zcb4sewnWvmYfYvZJh+U1DwryLc6DHcA=; b=o4eYlR+hUqQKbx0kJk2eyCMqgrLKFhVXn2s8YWuSXNyZYrrYxBHREv113itbRXLh3p 4nAt/orjH4f1cJyJ/CLZ+MPeFqTTdELigfsUuXfQpYZGHBiRoy+g8j7evtv8HapiMbZw 6fgR7wgnRpxA1D/wu2KhW2z8liu/7WYX5CE1vuCBauoH496jXhgEiLtFqX2p7LECuYfk cScIyQyjeuuKGPhoXo6y9f7ewZVMYrBjGaVtuEPRWvnKJsL0brgOaRSvw9xUVy14jcFu JHUB3mSSc0MWUoZOD72hSCi/fAMCjSiB4SM/a1PwMzm35g3V+/3cc0sg+DSM2Dy81nYS Q3Fw== Received: by 10.152.108.42 with SMTP id hh10mr329703lab.4.1355303743736; Wed, 12 Dec 2012 01:15:43 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id v7sm9246637lbj.13.2012.12.12.01.15.42 (version=SSLv3 cipher=OTHER); Wed, 12 Dec 2012 01:15:43 -0800 (PST) Message-ID: <50C84AC3.9020809@openwrt.org> Date: Wed, 12 Dec 2012 10:13:39 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Hauke Mehrtens CC: john@phrozen.org, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: BCM47XX: fix compile error in wgt634u.c References: <1355274612-19167-1-git-send-email-hauke@hauke-m.de> In-Reply-To: <1355274612-19167-1-git-send-email-hauke@hauke-m.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35256 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2480 Lines: 60 Hello Hauke, Le 12/12/12 02:10, Hauke Mehrtens a écrit : > After the new GPIO handling for the bcm47xx target was introduced > wgt634u.c was not changed. > This patch fixes the following compile error: > > arch/mips/bcm47xx/wgt634u.c: In function ‘gpio_interrupt’: > arch/mips/bcm47xx/wgt634u.c:119:2: error: implicit declaration of function ‘gpio_polarity’ [-Werror=implicit-function-declaration] > arch/mips/bcm47xx/wgt634u.c: In function ‘wgt634u_init’: > arch/mips/bcm47xx/wgt634u.c:153:4: error: implicit declaration of function ‘gpio_intmask’ [-Werror=implicit-function-declaration] Thanks for fixing this. We should probably remove this wgt634u file some day or the other as it was an ad-hoc hack for this single device while we actually need a general solution for all BCM47xx boards out there. > > Reported-by: Ralf Baechle > Signed-off-by: Hauke Mehrtens > --- > arch/mips/bcm47xx/wgt634u.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > I am planing to remove this entire file, but I haven't come up with > code adding support for most of the boards found in the wild. > > diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c > index e9f9ec8..6c28f6d 100644 > --- a/arch/mips/bcm47xx/wgt634u.c > +++ b/arch/mips/bcm47xx/wgt634u.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -116,7 +117,8 @@ static irqreturn_t gpio_interrupt(int irq, void *ignored) > > /* Interrupt are level triggered, revert the interrupt polarity > to clear the interrupt. */ > - gpio_polarity(WGT634U_GPIO_RESET, state); > + ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << WGT634U_GPIO_RESET, > + state ? 1 << WGT634U_GPIO_RESET : 0); > > if (!state) { > printk(KERN_INFO "Reset button pressed"); > @@ -150,7 +152,9 @@ static int __init wgt634u_init(void) > gpio_interrupt, IRQF_SHARED, > "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) { > gpio_direction_input(WGT634U_GPIO_RESET); > - gpio_intmask(WGT634U_GPIO_RESET, 1); > + ssb_gpio_intmask(&bcm47xx_bus.ssb, > + 1 << WGT634U_GPIO_RESET, > + 1 << WGT634U_GPIO_RESET); > ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco, > SSB_CHIPCO_IRQ_GPIO, > SSB_CHIPCO_IRQ_GPIO); > From kirill.shutemov@linux.intel.com Wed Dec 12 11:54:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 11:54:23 +0100 (CET) Received: from mga11.intel.com ([192.55.52.93]:4084 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6828015Ab2LLKyVhElkJ (ORCPT ); Wed, 12 Dec 2012 11:54:21 +0100 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 12 Dec 2012 02:54:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,265,1355126400"; d="asc'?scan'208";a="261054906" Received: from blue.fi.intel.com ([10.237.72.156]) by fmsmga001.fm.intel.com with ESMTP; 12 Dec 2012 02:54:10 -0800 Received: by blue.fi.intel.com (Postfix, from userid 1000) id 828A2E0073; Wed, 12 Dec 2012 12:55:38 +0200 (EET) Date: Wed, 12 Dec 2012 12:55:38 +0200 From: "Kirill A. Shutemov" To: David Rientjes Cc: Andrew Morton , linux-mm@kvack.org, Arnd Bergmann , linux-arch@vger.kernel.org, linux-s390@vger.kernel.org, Martin Schwidefsky , Heiko Carstens , linux-mips@linux-mips.org, Ralf Baechle , John Crispin Subject: Re: [PATCH, RESEND] asm-generic, mm: pgtable: consolidate zero page helpers Message-ID: <20121212105538.GA14208@otc-wbsnb-06> References: <1354881215-26257-1-git-send-email-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="+QahgC5+KEYLbs62" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35257 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kirill.shutemov@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1989 Lines: 54 --+QahgC5+KEYLbs62 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Dec 11, 2012 at 07:07:14PM -0800, David Rientjes wrote: > On Fri, 7 Dec 2012, Kirill A. Shutemov wrote: >=20 > > From: "Kirill A. Shutemov" > >=20 > > We have two different implementation of is_zero_pfn() and > > my_zero_pfn() helpers: for architectures with and without zero page > > coloring. > >=20 > > Let's consolidate them in . > >=20 >=20 > What's the benefit from doing this other than generalizing some per-arch= =20 > code? It simply adds on more layer of redirection to try to find the=20 > implementation that matters for the architecture you're hacking on. The idea of asm-generic is consolidation arch code which can be re-used for different arches. It also makes support of new arches easier. Do you think have copy of the same code here and there is any better? --=20 Kirill A. Shutemov --+QahgC5+KEYLbs62 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBAgAGBQJQyGKqAAoJEAd+omnVudOMyuEQAMemWRvnFt+7wByWD1jXWC2Z nUe8yPig5B3W4uawzQNJXj7PS9xr+xHCi52KlJT5TLnpPAih8ozor0Ohj+hxWBG0 OssHOzZhk6z+/IEG1DB8UDOmVUK9z3k17yfqsZkx+YB9F/x5tSug1Qt5AHGYvzt8 LXYbtVBx5CJm21TlnnOfx7woy21Q6CgAWhA+wBm+MiUbTN1btI8xmapBAuzrE+vh 1EIFdZe+7uWJOqHNadmVhjFvhF/Bym9z3dY7+hCc6dKvqPVOm2Bd1KJ5Pw3kgXls m1d2Z6LEdC7k7z1ZtU1T+mUSVSJbEMCc3F9x7FcP24sw/9zYWNX0zG6t2Iz0Mr5N AQ7uZxWIn9OdEhmViJyoqHDUNBIP+k+fg5M57ZsgB42BR4orJvRgCEtV2Byts+sN kn0AqJHU2n7v60liv/mzeKKK9z/c+Kjeg3Tp6vRSg7jSjl1Akk9M4urtuu9fFEBw bNS0IsIdjMwMF5DVXJGR5fCW8wu4r20VvRv8ISjGTo+g7FngSphafmwEq5Fl0/Hh 2c0sZ+j9fpuuvwzzYBUPdulXji8frkHZ4WxMGJ1DINTq6kARaaxGkNFUS1IeteCG Wpyj+chEnkL+1UwLLdrfGz7gbO/+fmeiuTOAnbS2qOe5zcRD8pcTCBhQ4W/IQXcG 5L9+tvjncCAEktFUZWvH =6aAs -----END PGP SIGNATURE----- --+QahgC5+KEYLbs62-- From florian@openwrt.org Wed Dec 12 15:26:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 15:26:23 +0100 (CET) Received: from mail-la0-f49.google.com ([209.85.215.49]:63976 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823690Ab2LLO0WNsL0N (ORCPT ); Wed, 12 Dec 2012 15:26:22 +0100 Received: by mail-la0-f49.google.com with SMTP id r15so654213lag.36 for ; Wed, 12 Dec 2012 06:26:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=BWC70ruUfUEo9agIGAATFfwpkH7zOrtLKKd5qdd5hMI=; b=myXHd0WwSTrK//ANhC+hGCWevPPkkzZAV9Cor8Sa8G/3BnZfuwsJUBaU860/XhAI2M 7ceBIb+yFOJd0Bjk2CUjufeYe68JmSIDlHZTkZ/Vz7g+YdPJF+9anbqRPFAjmaJLCA2V nCT3vWlEZJ3WLc9AybX35LJfSSTEq0QKj5+diS6dx7xsikB3w3k10Gnws74WY98U7A0w El0o7wVciMVxLQo3w2IPX2Il+QjyFoc5lb9be3ChMIME+a8LJ92NVnwYlHMXwTvaLxRp ePQbb34dKi9HciElzvWc2GsNDGv3KbtJZd3MwZxq/nPgiOqcsn2YT25XVrSQLqT7xdFc lz2Q== Received: by 10.152.135.139 with SMTP id ps11mr1215913lab.29.1355322376483; Wed, 12 Dec 2012 06:26:16 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id u9sm10787664lbf.5.2012.12.12.06.26.15 (version=SSLv3 cipher=OTHER); Wed, 12 Dec 2012 06:26:16 -0800 (PST) Message-ID: <50C8938C.8020705@openwrt.org> Date: Wed, 12 Dec 2012 15:24:12 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] MIPS: dsp: Add assembler support for DSP ASEs. References: <1354855981-28392-1-git-send-email-sjhill@mips.com> In-Reply-To: <1354855981-28392-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35258 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2105 Lines: 73 Hi Steven, Le 12/07/12 05:53, Steven J. Hill a écrit : > From: "Steven J. Hill" > > Newer toolchains support the DSP and DSP Rev2 instructions. This patch > performs a check for that support and adds compiler and assembler > flags for only the files that need use those instructions. > > Signed-off-by: Steven J. Hill > --- > arch/mips/include/asm/mipsregs.h | 53 ++++++++++++++++++++++++++------------ > arch/mips/kernel/Makefile | 24 +++++++++++++++++ > 2 files changed, 60 insertions(+), 17 deletions(-) > > --- a/arch/mips/kernel/Makefile > +++ b/arch/mips/kernel/Makefile > @@ -99,4 +99,28 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o > > obj-$(CONFIG_JUMP_LABEL) += jump_label.o > > +ifeq ($(CONFIG_CPU_MIPS32), y) > +# > +# Check if assembler supports DSP ASE > +# > +ifeq ($(call cc-option-yn,-mdsp), y) > +CFLAGS_signal.o = -mdsp -DHAVE_AS_DSP > +CFLAGS_signal32.o = -mdsp -DHAVE_AS_DSP > +CFLAGS_process.o = -mdsp -DHAVE_AS_DSP > +CFLAGS_branch.o = -mdsp -DHAVE_AS_DSP > +CFLAGS_ptrace.o = -mdsp -DHAVE_AS_DSP > +endif > + > +# > +# Check if assembler supports DSP ASE Rev2 > +# > +ifeq ($(call cc-option-yn,-mdsp2), y) > +CFLAGS_signal.o = -mdsp2 -DHAVE_AS_DSP > +CFLAGS_signal32.o = -mdsp2 -DHAVE_AS_DSP > +CFLAGS_process.o = -mdsp2 -DHAVE_AS_DSP > +CFLAGS_branch.o = -mdsp2 -DHAVE_AS_DSP > +CFLAGS_ptrace.o = -mdsp2 -DHAVE_AS_DSP Should not this be -mdspr2 here? My GCC man page suggests that. By the way, should not we also check that we are building for a MIPS32_R2 CPU when checking for -mdsp2? > +endif > +endif > + I would simplify this like this: ifeq ($(CONFIG_CPU_MIPS32),y) CFLAGS_DSP = -DHAVE_AS_DSP ifeq ($(call cc-option-yn,-mdsp),y) CFLAGS_DSP += -mdsp endif ifeq ($(call cc-option-yn,-mdsp2),y) CFLAGS-DSP += -mdsp2 endif CFLAGS_signal.o = $(CFLAGS_DSP) ... CFLAGS_ptrace.o = $(CFLAGS_DSP) endif such that the day you can take advantage of a third DSP flavor it's only 3 lines worth of Makefile to get it used, and you only have one place where you need to change CFLAGS. -- Florian From florian@openwrt.org Wed Dec 12 15:28:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 15:28:20 +0100 (CET) Received: from mail-lb0-f177.google.com ([209.85.217.177]:47264 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823690Ab2LLO2UCT1Tn (ORCPT ); Wed, 12 Dec 2012 15:28:20 +0100 Received: by mail-lb0-f177.google.com with SMTP id n10so687229lbo.36 for ; Wed, 12 Dec 2012 06:28:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=ZO80q6H/TycvM7quSLIZGrZ8Az43BzdUC+OnBkV56Fg=; b=jeb+8Rer72WLHklfLTnfoG+zXJq5As2QJVH4T8MgrpdmksgmSWbrG7f1/YERZcxUk0 U6JWvheA2WOe7CMKsXQkDfR6Bl2V/UE0ivTtTMqmTkKoeQXzjPVOFMGxrxwOxzuOAgPR WoOhlZ7yYxK3nDcW+A6FrxjC7VdSFpNW+EHcG1wUtsgvT2Kt+dKSJYPdMN2gg6nJOJv5 mrHHoXgUt23GVFxfV6qKCwt1kt3kJY4xTHQsGywh48VYedc++9bNQklEJbk3pFh/r0M0 xWT2oLzVwdfIPzIFvTRMwO61Wjxhl8f57jeCw/evEE0hmXQY3bQjfXZnMGW6rohWdJEE +RFQ== Received: by 10.112.23.234 with SMTP id p10mr535181lbf.35.1355322494212; Wed, 12 Dec 2012 06:28:14 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id pg5sm9306249lab.6.2012.12.12.06.28.13 (version=SSLv3 cipher=OTHER); Wed, 12 Dec 2012 06:28:13 -0800 (PST) Message-ID: <50C89401.70705@openwrt.org> Date: Wed, 12 Dec 2012 15:26:09 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] MIPS: Make CP0 config registers readable via sysfs. References: <1354858280-29576-1-git-send-email-sjhill@mips.com> In-Reply-To: <1354858280-29576-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35259 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1216 Lines: 44 Hello Steven, Le 12/07/12 06:31, Steven J. Hill a écrit : [snip] > + > +#define __BUILD_CP0_SYSFS(reg) \ > +static DEFINE_PER_CPU(unsigned int, cpu_config##reg); \ > +static ssize_t show_config##reg(struct device *dev, \ > + struct device_attribute *attr, char *buf) \ > +{ \ > + struct cpu *cpu = container_of(dev, struct cpu, dev); \ > + int n = snprintf(buf, PAGE_SIZE-2, "%x\n", \ > + per_cpu(cpu_config##reg, cpu->dev.id)); \ > + return n; \ > +} \ > +static DEVICE_ATTR(config##reg, 0444, show_config##reg, NULL); > + > +__BUILD_CP0_SYSFS(0) > +__BUILD_CP0_SYSFS(1) > +__BUILD_CP0_SYSFS(2) > +__BUILD_CP0_SYSFS(3) > +__BUILD_CP0_SYSFS(4) > +__BUILD_CP0_SYSFS(5) > +__BUILD_CP0_SYSFS(6) > +__BUILD_CP0_SYSFS(7) > + > +static void read_c0_registers(void *arg) > +{ > + struct device *dev = get_cpu_device(smp_processor_id()); > + struct cpu *cpu; > + int ok; > + > + if (dev != NULL) { > + cpu = container_of(dev, struct cpu, dev); > + per_cpu(cpu_config0, cpu->dev.id) = read_c0_config(); > + device_create_file(dev, &dev_attr_config0); > + ok = per_cpu(cpu_config0, cpu->dev.id) & MIPS_CONF_M; > + } else Is there any reason you are not using a macro here too? -- Florian From florian@openwrt.org Wed Dec 12 15:31:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 15:31:50 +0100 (CET) Received: from mail-la0-f49.google.com ([209.85.215.49]:40677 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823690Ab2LLObuP71QP (ORCPT ); Wed, 12 Dec 2012 15:31:50 +0100 Received: by mail-la0-f49.google.com with SMTP id r15so660471lag.36 for ; Wed, 12 Dec 2012 06:31:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=L2ALDhU5foDbrLvL5LCUIbcMqDf5lZAe2Fk2Ul1YaeA=; b=S/PKhJYJNwFRTRYadm/ajD8QRySJJT3yU+ECi47XRMCXOKRuS6mkVVJfKhOUxXjXY+ wrjFeoh/Nr96pNCv4YeXv9Lf8otuoOXJ2DZOfpuNykjCPPCCuh5zKbi8UwuMXjbuIvue jeuYaj6kA70P/hdm3i0JH/VXf1yMAPOlJGSwPk4mLcM+9BnZP6KJqS3pKLFGku6CYvrF I4o/Z+I4rk1WTcedkc73PwOnQWDtHfYUjFaqBZd7B5dFGNi72dJoReo/AykftF4UxYRQ aDk2srF7tWqvhH492+FfVRSCcm34iOcdi/9W+R5FreLAeKcCx+LqOW9ThikrwYUr1BXk C7xA== Received: by 10.152.108.48 with SMTP id hh16mr1225514lab.25.1355322704645; Wed, 12 Dec 2012 06:31:44 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id v6sm10790757lbf.11.2012.12.12.06.31.43 (version=SSLv3 cipher=OTHER); Wed, 12 Dec 2012 06:31:44 -0800 (PST) Message-ID: <50C894D4.4090008@openwrt.org> Date: Wed, 12 Dec 2012 15:29:40 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] OF: MIPS: sead3: Implement OF support. References: <1354857297-28863-1-git-send-email-sjhill@mips.com> In-Reply-To: <1354857297-28863-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35260 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 700 Lines: 35 Hello Steven, Le 12/07/12 06:14, Steven J. Hill a écrit : [snip] > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "mips,sead-3"; > + > + cpus { > + cpu@0 { > + compatible = "mips,mips14Kc,mips14KEc"; > + }; You probably want this the other way around: mips14KEc,mips14Kc,mips you should always have the left-most string being the most descriptive about the hardware and the last one being the less descriptive and thus less "specializing" in order to be backward compatible. > + }; > + > + chosen { > + bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3"; > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x0 0x08000000>; > + }; > +}; > From lars@metafoo.de Wed Dec 12 15:45:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 15:45:11 +0100 (CET) Received: from smtp-out-249.synserver.de ([212.40.185.249]:1300 "EHLO smtp-out-249.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825735Ab2LLOpKonFCo (ORCPT ); Wed, 12 Dec 2012 15:45:10 +0100 Received: (qmail 29988 invoked by uid 0); 12 Dec 2012 14:45:05 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@metafoo.de X-SynServer-PPID: 29923 Received: from p4fe627b7.dip.t-dialin.net (HELO ?192.168.0.176?) [79.230.39.183] by 217.119.54.96 with AES256-SHA encrypted SMTP; 12 Dec 2012 14:45:04 -0000 Message-ID: <50C89870.5000704@metafoo.de> Date: Wed, 12 Dec 2012 15:45:04 +0100 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.10) Gecko/20121027 Icedove/10.0.10 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] MIPS: Make CP0 config registers readable via sysfs. References: <1354858280-29576-1-git-send-email-sjhill@mips.com> In-Reply-To: <1354858280-29576-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35261 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 433 Lines: 17 On 12/07/2012 06:31 AM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Allow reading of CP0 config registers via sysfs for each core > in the system. Maybe a stupid question, but why? > The registers will show up in sysfs at the path: > > /sys/devices/system/cpu/cpuX/configX > > Only CP0 config registers 0 through 7 are currently supported. > > Signed-off-by: Steven J. Hill [...] From hauke@hauke-m.de Wed Dec 12 15:46:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 15:46:51 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:39229 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825730Ab2LLOqrJbd6P (ORCPT ); Wed, 12 Dec 2012 15:46:47 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 9EB468F65; Wed, 12 Dec 2012 15:46:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id R7pWmUGRIu8K; Wed, 12 Dec 2012 15:46:33 +0100 (CET) Received: from [IPv6:2001:470:1f0b:447:8dd6:f11a:ffd3:5c8c] (unknown [IPv6:2001:470:1f0b:447:8dd6:f11a:ffd3:5c8c]) by hauke-m.de (Postfix) with ESMTPSA id 0DFB78F64; Wed, 12 Dec 2012 15:46:32 +0100 (CET) Message-ID: <50C898C4.4040609@hauke-m.de> Date: Wed, 12 Dec 2012 15:46:28 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Florian Fainelli CC: john@phrozen.org, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: BCM47XX: fix compile error in wgt634u.c References: <1355274612-19167-1-git-send-email-hauke@hauke-m.de> <50C84AC3.9020809@openwrt.org> In-Reply-To: <50C84AC3.9020809@openwrt.org> X-Enigmail-Version: 1.4.6 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 35262 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1556 Lines: 35 On 12/12/2012 10:13 AM, Florian Fainelli wrote: > Hello Hauke, > > Le 12/12/12 02:10, Hauke Mehrtens a écrit : >> After the new GPIO handling for the bcm47xx target was introduced >> wgt634u.c was not changed. >> This patch fixes the following compile error: >> >> arch/mips/bcm47xx/wgt634u.c: In function ‘gpio_interrupt’: >> arch/mips/bcm47xx/wgt634u.c:119:2: error: implicit declaration of >> function ‘gpio_polarity’ [-Werror=implicit-function-declaration] >> arch/mips/bcm47xx/wgt634u.c: In function ‘wgt634u_init’: >> arch/mips/bcm47xx/wgt634u.c:153:4: error: implicit declaration of >> function ‘gpio_intmask’ [-Werror=implicit-function-declaration] > > Thanks for fixing this. We should probably remove this wgt634u file some > day or the other as it was an ad-hoc hack for this single device while > we actually need a general solution for all BCM47xx boards out there. > Yes I also want to get rid of this file. Currently OpenWrt uses its own detection and gpio/led/button configure code [0], but this doe not look nice to me. I saw Jonas RFC patch for device tree integration into bcm63xx [1] and thought about doing something similar for bcm47xx. Initially device tree would be used for mapping gpios to leds and buttons. I haven't read much about DT, but it looks nice. Is it possible to detect devices by some arbitrary nvram settings like it is done in diag.c? Hauke [0]: https://dev.openwrt.org/browser/trunk/package/broadcom-diag/src/diag.c [1]: http://www.linux-mips.org/archives/linux-mips/2012-11/msg00092.html From lars@metafoo.de Wed Dec 12 15:53:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 15:53:28 +0100 (CET) Received: from smtp-out-249.synserver.de ([212.40.185.249]:1080 "EHLO smtp-out-249.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825730Ab2LLOx2FJbuq (ORCPT ); Wed, 12 Dec 2012 15:53:28 +0100 Received: (qmail 26908 invoked by uid 0); 12 Dec 2012 14:53:26 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@metafoo.de X-SynServer-PPID: 26804 Received: from p4fe627b7.dip.t-dialin.net (HELO ?192.168.0.176?) [79.230.39.183] by 217.119.54.87 with AES256-SHA encrypted SMTP; 12 Dec 2012 14:53:26 -0000 Message-ID: <50C89A6C.705@metafoo.de> Date: Wed, 12 Dec 2012 15:53:32 +0100 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.10) Gecko/20121027 Icedove/10.0.10 MIME-Version: 1.0 To: Florian Fainelli CC: "Steven J. Hill" , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] OF: MIPS: sead3: Implement OF support. References: <1354857297-28863-1-git-send-email-sjhill@mips.com> <50C894D4.4090008@openwrt.org> In-Reply-To: <50C894D4.4090008@openwrt.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 35263 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1288 Lines: 51 On 12/12/2012 03:29 PM, Florian Fainelli wrote: > Hello Steven, > > Le 12/07/12 06:14, Steven J. Hill a écrit : > [snip] > >> +/ { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = "mips,sead-3"; >> + >> + cpus { >> + cpu@0 { >> + compatible = "mips,mips14Kc,mips14KEc"; >> + }; > > You probably want this the other way around: > > mips14KEc,mips14Kc,mips > > you should always have the left-most string being the most descriptive about > the hardware and the last one being the less descriptive and thus less > "specializing" in order to be backward compatible. This is one compatible string though, what you describe is for when use multiple compatible string. E.g. compatible = "mips14KEc", "mips14Kc", "mips"; The "mips" in Stevens patch is probably the vendor prefix. Maybe a more correct compatible would be. compatible = "mips,mips14KEc", "mips,mips14Kc"; But in anyway the patch should also add documentation under Documentation/devicetree/bindings describing the binding. > >> + }; >> + >> + chosen { >> + bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3"; >> + }; >> + >> + memory { >> + device_type = "memory"; >> + reg = <0x0 0x08000000>; >> + }; >> +}; >> > From ralf@linux-mips.org Wed Dec 12 15:55:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 15:55:52 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:60230 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6825716Ab2LLOzsSnwmE (ORCPT ); Wed, 12 Dec 2012 15:55:48 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qBCEtlWP005814; Wed, 12 Dec 2012 15:55:47 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qBCEtjNp005813; Wed, 12 Dec 2012 15:55:45 +0100 Date: Wed, 12 Dec 2012 15:55:45 +0100 From: Ralf Baechle To: Lars-Peter Clausen Cc: Florian Fainelli , "Steven J. Hill" , linux-mips@linux-mips.org Subject: Re: [PATCH] OF: MIPS: sead3: Implement OF support. Message-ID: <20121212145545.GC11791@linux-mips.org> References: <1354857297-28863-1-git-send-email-sjhill@mips.com> <50C894D4.4090008@openwrt.org> <50C89A6C.705@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50C89A6C.705@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35264 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 481 Lines: 13 On Wed, Dec 12, 2012 at 03:53:32PM +0100, Lars-Peter Clausen wrote: > This is one compatible string though, what you describe is for when use > multiple compatible string. E.g. > compatible = "mips14KEc", "mips14Kc", "mips"; > > The "mips" in Stevens patch is probably the vendor prefix. Maybe a more > correct compatible would be. How about using something like mti (for MIPS Technologies, Inc.) instead of MIPS to differenciate the architecture from the company name? Ralf From florian@openwrt.org Wed Dec 12 15:58:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 15:58:55 +0100 (CET) Received: from mail-la0-f49.google.com ([209.85.215.49]:59815 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823128Ab2LLO6yR-s3A (ORCPT ); Wed, 12 Dec 2012 15:58:54 +0100 Received: by mail-la0-f49.google.com with SMTP id r15so691340lag.36 for ; Wed, 12 Dec 2012 06:58:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=BrdTQJz6fgVJLsVXw4sLcITUwP+9RBYNq4X7KTnIur4=; b=vAu+cDGxfxs1zpNnIf3HxsnMhSqMWUNecTkVVsScTHvzNz6TPFFlCL8iATvd+TxV+C THz9NDoOfYTGDsnL+TTseIhSz9v0syv0qa0+tx7SDHGAZ164qzDxX9TSRtlxy8kEeSB0 hh1lMclEYuXLiq7Jlpl1qrddNhSVL9tvPrHfMsYnDLOeWNm3RfHneWCfBGa4/yCNNKDS 2qKPz5zKKjCUQRZs5xIz1bduOUz4UMQXSLJokWArw7P7vtY1qYMuyZs4zFbp03bJjGBj acDL3SLJLX1nC+p6d+CHdmJM4cG7CMMjorYiYYEqSsN1ZcCXJ1fXgFKL02kdytwQfbNd OGOw== Received: by 10.112.103.202 with SMTP id fy10mr562164lbb.13.1355324328489; Wed, 12 Dec 2012 06:58:48 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id fe4sm4786613lbb.1.2012.12.12.06.58.47 (version=SSLv3 cipher=OTHER); Wed, 12 Dec 2012 06:58:47 -0800 (PST) Message-ID: <50C89B2C.1070903@openwrt.org> Date: Wed, 12 Dec 2012 15:56:44 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Lars-Peter Clausen CC: "Steven J. Hill" , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] OF: MIPS: sead3: Implement OF support. References: <1354857297-28863-1-git-send-email-sjhill@mips.com> <50C894D4.4090008@openwrt.org> <50C89A6C.705@metafoo.de> In-Reply-To: <50C89A6C.705@metafoo.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35265 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1289 Lines: 42 Le 12/12/12 15:53, Lars-Peter Clausen a écrit : > On 12/12/2012 03:29 PM, Florian Fainelli wrote: >> Hello Steven, >> >> Le 12/07/12 06:14, Steven J. Hill a écrit : >> [snip] >> >>> +/ { >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + compatible = "mips,sead-3"; >>> + >>> + cpus { >>> + cpu@0 { >>> + compatible = "mips,mips14Kc,mips14KEc"; >>> + }; >> You probably want this the other way around: >> >> mips14KEc,mips14Kc,mips >> >> you should always have the left-most string being the most descriptive about >> the hardware and the last one being the less descriptive and thus less >> "specializing" in order to be backward compatible. > This is one compatible string though, what you describe is for when use > multiple compatible string. E.g. > compatible = "mips14KEc", "mips14Kc", "mips"; > > The "mips" in Stevens patch is probably the vendor prefix. Maybe a more > correct compatible would be. > > compatible = "mips,mips14KEc", "mips,mips14Kc"; Right, this should be the proper compatible string. Steven's patch does not make any use of this compatible string right now anyway. > > But in anyway the patch should also add documentation under > Documentation/devicetree/bindings describing the binding. > Obviously -- Florian From florian@openwrt.org Wed Dec 12 16:04:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 16:04:14 +0100 (CET) Received: from mail-la0-f49.google.com ([209.85.215.49]:41500 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825653Ab2LLPEJiSfUW (ORCPT ); Wed, 12 Dec 2012 16:04:09 +0100 Received: by mail-la0-f49.google.com with SMTP id r15so698359lag.36 for ; Wed, 12 Dec 2012 07:04:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=UhJPmKxXUfPQv8cRkaK6ZaWphfGH1Z0vKVeUBUwUw/Q=; b=z75k6nBsXv3L0gInj0WiZpONVYw2xF6jAQdzeCf7EfLlkR7fb7p7Tk6np4kwgeC6W9 eRMXeBhW628WpxKSVBEJah7+yTDMPNmGoXHjHj8FofnqwKTAZQTCVLHg5pOKbbaUwZO4 a9GIWd3DM9JS3tfLHzFo0/K6TrlP85h2OA7PEFuFs+2DP29TDBX6VMVtyQb1eSEpJnm6 kHS43cugQcRSYyHz6T3uIfHBHovBTVVCyhUcjcvApdSuR7rLZBDun4VU3nF2wULzXRuo Nt4M2ZcqOcRyUzH2uhGcxoZxkAr6O9CwdbwwYPVZ/jSBViwuFVEsZEAnLW8qhEgzHZLY wmvQ== Received: by 10.112.25.193 with SMTP id e1mr583947lbg.94.1355324644017; Wed, 12 Dec 2012 07:04:04 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id v7sm9716867lbj.13.2012.12.12.07.04.02 (version=SSLv3 cipher=OTHER); Wed, 12 Dec 2012 07:04:03 -0800 (PST) Message-ID: <50C89C67.7040908@openwrt.org> Date: Wed, 12 Dec 2012 16:01:59 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Ralf Baechle CC: Lars-Peter Clausen , "Steven J. Hill" , linux-mips@linux-mips.org Subject: Re: [PATCH] OF: MIPS: sead3: Implement OF support. References: <1354857297-28863-1-git-send-email-sjhill@mips.com> <50C894D4.4090008@openwrt.org> <50C89A6C.705@metafoo.de> <20121212145545.GC11791@linux-mips.org> In-Reply-To: <20121212145545.GC11791@linux-mips.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35266 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 730 Lines: 17 Le 12/12/12 15:55, Ralf Baechle a écrit : > On Wed, Dec 12, 2012 at 03:53:32PM +0100, Lars-Peter Clausen wrote: > >> This is one compatible string though, what you describe is for when use >> multiple compatible string. E.g. >> compatible = "mips14KEc", "mips14Kc", "mips"; >> >> The "mips" in Stevens patch is probably the vendor prefix. Maybe a more >> correct compatible would be. > How about using something like mti (for MIPS Technologies, Inc.) instead > of MIPS to differenciate the architecture from the company name? The convention for vendor prefixes is to use the stock exchange prefix, giving us "mips". The same problem exist for ARM Ltd. vs architecture and they use "arm" as a prefix unconditionaly. -- Florian From ralf@linux-mips.org Wed Dec 12 16:12:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 16:12:06 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:60742 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6823126Ab2LLPMFsK0lW (ORCPT ); Wed, 12 Dec 2012 16:12:05 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qBCFC5AP006931; Wed, 12 Dec 2012 16:12:05 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qBCFC4l6006930; Wed, 12 Dec 2012 16:12:04 +0100 Date: Wed, 12 Dec 2012 16:12:04 +0100 From: Ralf Baechle To: Florian Fainelli Cc: Lars-Peter Clausen , "Steven J. Hill" , linux-mips@linux-mips.org Subject: Re: [PATCH] OF: MIPS: sead3: Implement OF support. Message-ID: <20121212151204.GD11791@linux-mips.org> References: <1354857297-28863-1-git-send-email-sjhill@mips.com> <50C894D4.4090008@openwrt.org> <50C89A6C.705@metafoo.de> <20121212145545.GC11791@linux-mips.org> <50C89C67.7040908@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50C89C67.7040908@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35267 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 393 Lines: 11 On Wed, Dec 12, 2012 at 04:01:59PM +0100, Florian Fainelli wrote: > The convention for vendor prefixes is to use the stock exchange > prefix, giving us "mips". The same problem exist for ARM Ltd. vs > architecture and they use "arm" as a prefix unconditionaly. ARM is traded at LSE as ARM but on Nasdaq as ARMH. Pick one ;) Conventions are made to be violated for good reasons ... Ralf From florian@openwrt.org Wed Dec 12 16:17:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 16:17:45 +0100 (CET) Received: from mail-lb0-f177.google.com ([209.85.217.177]:34881 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823126Ab2LLPRof7aVO (ORCPT ); Wed, 12 Dec 2012 16:17:44 +0100 Received: by mail-lb0-f177.google.com with SMTP id n10so743600lbo.36 for ; Wed, 12 Dec 2012 07:17:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=qPW7EssFAccBBgr1jC27oIkIQWglovQhi/S0FGj5Dgc=; b=X7t/obbnbKcakW6fB7TS3OCRGnyfFeXaleP76JLzOFc8scaAewaRPLWnZXOz9fp51H LOdUnqUm1qntVbX6vhuX0VvJnzj1SWwBhXjBsH2Q3ojlLdQAtq5xNzN4OA7O7my1ejGK odLIkQ9zEp+FqJ9N6CfwEx0IimAm7CJQr7qLB/RMfckDB7CQ3WggR3d4kBzTcv8WHxmw utb0a61tO4A2UDRz9nY1RBVbPxUWRvfaDDCYyy6XpAmzcflZpoQTY9lDn4Fpvpq0RF7c unZmrZwx4r2r9LZu9L7e2DOt60sAyp6gnZ2nii0Fzm/+OCrgdgex78qyRMB/y4Buuo4e PwUg== Received: by 10.112.45.232 with SMTP id q8mr603765lbm.23.1355325458925; Wed, 12 Dec 2012 07:17:38 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id pg5sm9366346lab.6.2012.12.12.07.17.37 (version=SSLv3 cipher=OTHER); Wed, 12 Dec 2012 07:17:38 -0800 (PST) Message-ID: <50C89F96.7010605@openwrt.org> Date: Wed, 12 Dec 2012 16:15:34 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Ralf Baechle CC: Lars-Peter Clausen , "Steven J. Hill" , linux-mips@linux-mips.org Subject: Re: [PATCH] OF: MIPS: sead3: Implement OF support. References: <1354857297-28863-1-git-send-email-sjhill@mips.com> <50C894D4.4090008@openwrt.org> <50C89A6C.705@metafoo.de> <20121212145545.GC11791@linux-mips.org> <50C89C67.7040908@openwrt.org> <20121212151204.GD11791@linux-mips.org> In-Reply-To: <20121212151204.GD11791@linux-mips.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35268 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 596 Lines: 14 Le 12/12/12 16:12, Ralf Baechle a écrit : > On Wed, Dec 12, 2012 at 04:01:59PM +0100, Florian Fainelli wrote: > >> The convention for vendor prefixes is to use the stock exchange >> prefix, giving us "mips". The same problem exist for ARM Ltd. vs >> architecture and they use "arm" as a prefix unconditionaly. > ARM is traded at LSE as ARM but on Nasdaq as ARMH. Pick one ;) > > Conventions are made to be violated for good reasons ... As I looked into Documentation/device-tree/bindings/vendor-prefixes.txt I found quite some good counter examples as well, so let's go for "mti". -- Florian From sjhill@mips.com Wed Dec 12 17:45:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 17:57:51 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:44609 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823668Ab2LLQpdQrdFY convert rfc822-to-8bit (ORCPT ); Wed, 12 Dec 2012 17:45:33 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qBCGjPo9007815; Wed, 12 Dec 2012 08:45:25 -0800 X-WSS-ID: 0MEXFVP-01-17B-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.67]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 26838364636; Wed, 12 Dec 2012 08:45:24 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([fe80::2897:a30d:a923:303%16]) with mapi id 14.01.0270.001; Wed, 12 Dec 2012 08:45:21 -0800 From: "Hill, Steven" To: Florian Fainelli CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: RE: [PATCH] MIPS: Make CP0 config registers readable via sysfs. Thread-Topic: [PATCH] MIPS: Make CP0 config registers readable via sysfs. Thread-Index: AQHN1DwdFeowWwCT60yFwo2HgIhlxJgVxuWA//+glV4= Date: Wed, 12 Dec 2012 16:45:20 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AA787@exchdb03.mips.com> References: <1354858280-29576-1-git-send-email-sjhill@mips.com>,<50C89401.70705@openwrt.org> In-Reply-To: <50C89401.70705@openwrt.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: mFQmxRa3Uy4dygvk5+9FNg== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35269 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 75 Lines: 1 By golly you're right! I can use a macro for the other code block. Thanks. From sjhill@mips.com Wed Dec 12 17:44:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 17:58:19 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:44605 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823668Ab2LLQohku-3m convert rfc822-to-8bit (ORCPT ); Wed, 12 Dec 2012 17:44:37 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qBCGiTHF007797; Wed, 12 Dec 2012 08:44:29 -0800 X-WSS-ID: 0MEXFU1-01-17A-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.67]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 210E8364636; Wed, 12 Dec 2012 08:44:25 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([fe80::2897:a30d:a923:303%16]) with mapi id 14.01.0270.001; Wed, 12 Dec 2012 08:44:20 -0800 From: "Hill, Steven" To: Lars-Peter Clausen CC: "linux-mips@linux-mips.org" Subject: RE: [PATCH] MIPS: Make CP0 config registers readable via sysfs. Thread-Topic: [PATCH] MIPS: Make CP0 config registers readable via sysfs. Thread-Index: AQHN1DwdFeowWwCT60yFwo2HgIhlxJgVzC4A//+Y9N8= Date: Wed, 12 Dec 2012 16:44:19 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AA779@exchdb03.mips.com> References: <1354858280-29576-1-git-send-email-sjhill@mips.com>,<50C89870.5000704@metafoo.de> In-Reply-To: <50C89870.5000704@metafoo.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: mtBau5Behgb/BpTq54FqTw== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35270 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 395 Lines: 5 Lars, This patch was requested by our DSP/Codec group to help with selecting the best user-space codecs at runtime. Simply reading /proc/cpuinfo was insufficient. I posted this patch more for feedback and interest with minimal expectations that it would make it upstream. This patch will always be in our supported branches, but I will defer to everyone else on its worth for upstream. -Steve From florian@openwrt.org Wed Dec 12 18:05:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 18:05:28 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:33041 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823128Ab2LLRF0wcno1 (ORCPT ); Wed, 12 Dec 2012 18:05:26 +0100 Received: by mail-bk0-f49.google.com with SMTP id jm19so510621bkc.36 for ; Wed, 12 Dec 2012 09:05:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=hF//RoxMDe9Bi4Ock0FHe2sWkSIdkQMHSJJbGxnsm30=; b=rkbTcAqFelQyewGTgFZ077NWM9PDiYY3QTvPUdPwE2pabIef+JT/ehI9WoJARfep3G jbm4oHd9nk7gBJ1sePFQQofp2M4Gy4Sw8Eyy5UXRa0gtN/MuoX6EJ/JTjkhf3GK7ItjV yrBOYjwD7kQz5nthzW4CNsL1ee2W94bcYY1gtU3Xi6V4P95KAniML5zh/PPNsssZ4p2D G3ZGDXi+6K1gqmWXs9qXnB5IGmPGOJc5ID5z/SV76r4l0Lb+D+XAAzvqEDKK7YBDAflT 850UJik4ToOhLrsX8M/gF9M515qWI+jlMbYYHGMuJWVmbWKQL4JGLZiuomgzGupfKm75 mNgA== Received: by 10.204.8.136 with SMTP id h8mr876497bkh.62.1355331921406; Wed, 12 Dec 2012 09:05:21 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id o9sm21070412bko.15.2012.12.12.09.05.20 (version=SSLv3 cipher=OTHER); Wed, 12 Dec 2012 09:05:20 -0800 (PST) Message-ID: <50C8B8D4.6070305@openwrt.org> Date: Wed, 12 Dec 2012 18:03:16 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Hill, Steven" CC: Lars-Peter Clausen , "linux-mips@linux-mips.org" Subject: Re: [PATCH] MIPS: Make CP0 config registers readable via sysfs. References: <1354858280-29576-1-git-send-email-sjhill@mips.com>,<50C89870.5000704@metafoo.de> <31E06A9FC96CEC488B43B19E2957C1B801146AA779@exchdb03.mips.com> In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B801146AA779@exchdb03.mips.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35271 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 689 Lines: 12 Le 12/12/12 17:44, Hill, Steven a écrit : > Lars, > > This patch was requested by our DSP/Codec group to help with selecting the best user-space codecs at runtime. Simply reading /proc/cpuinfo was insufficient. I posted this patch more for feedback and interest with minimal expectations that it would make it upstream. This patch will always be in our supported branches, but I will defer to everyone else on its worth for upstream. How do they actually make their choices? Is it just about advertising dsp vs. dspr2 to user-space? Have you looked into modifying the ELF platform via set_elf_platform() to help these binaries with identify the underlying platform/kernel? -- Florian From lars@metafoo.de Wed Dec 12 19:49:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 19:49:22 +0100 (CET) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:35404 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823690Ab2LLStREs9tN (ORCPT ); Wed, 12 Dec 2012 19:49:17 +0100 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 1C0B3A98; Wed, 12 Dec 2012 19:49:11 +0100 (CET) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id bpiphb2w9jGz; Wed, 12 Dec 2012 19:49:10 +0100 (CET) Received: from [192.168.178.21] (ppp-188-174-172-163.dynamic.mnet-online.de [188.174.172.163]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 425A6A97; Wed, 12 Dec 2012 19:49:09 +0100 (CET) Message-ID: <50C8D1D4.5050200@metafoo.de> Date: Wed, 12 Dec 2012 19:49:56 +0100 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20121027 Icedove/3.0.11 MIME-Version: 1.0 To: "Hill, Steven" CC: "linux-mips@linux-mips.org" Subject: Re: [PATCH] MIPS: Make CP0 config registers readable via sysfs. References: <1354858280-29576-1-git-send-email-sjhill@mips.com>,<50C89870.5000704@metafoo.de> <31E06A9FC96CEC488B43B19E2957C1B801146AA779@exchdb03.mips.com> In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B801146AA779@exchdb03.mips.com> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35272 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 896 Lines: 16 On 12/12/2012 05:44 PM, Hill, Steven wrote: > Lars, > > This patch was requested by our DSP/Codec group to help with selecting the best user-space codecs at runtime. Simply reading /proc/cpuinfo was insufficient. I posted this patch more for feedback and interest with minimal expectations that it would make it upstream. This patch will always be in our supported branches, but I will defer to everyone else on its worth for upstream. > > -Steve Well if it is something that is useful it makes sense to upstream it, especially if you are developing applications. Many people before you have learned the hard way that stashing stuff away in their private branches was not the best idea. If you are smart you are going to avoid that. It may not be the best solution though to just dump all the cp register to userspace. As Florian suggested there might be a smarter way to solve this. - Lars From ddaney.cavm@gmail.com Wed Dec 12 20:09:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 20:09:02 +0100 (CET) Received: from mail-pa0-f49.google.com ([209.85.220.49]:45723 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817207Ab2LLTJBrXtbT (ORCPT ); Wed, 12 Dec 2012 20:09:01 +0100 Received: by mail-pa0-f49.google.com with SMTP id bi1so817769pad.36 for ; Wed, 12 Dec 2012 11:08:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=EXeJQ9F3o9y9sAk8Qu4H1r35WCcRfqv0552iyFhwZqQ=; b=fiV7s61uAP/jZhKv4/+1lv150JLWGXIde+eiEVrRExqUx8NAGk/n4uJ3MDyd72uUUB zla5wC20K5wu2x+y+UZyKBxtzwYZ/zE0ATQTP3fv7hkOsL+9ZbTdGf5l8ksYxSbfRT5M nTWYgRdoJYIJ4GBWVDuoVFVY/7cE0UFa55Tc3C/5hRJLGBWzVXUU24US5JBY4zD+/uos bWyUgXWej+ZkJvsG272km3eXbKGvD1dUfK+GQyQ8D07d39AhIdNJ6QpuKwQCeICO0QMn lfmvLaDMrLjwGtY3AcmCogr4uYuxvijN1juum4A8EwL+CJkuyz33uhp7CW47PE4IO4Qd Qpiw== Received: by 10.66.90.1 with SMTP id bs1mr5041374pab.19.1355339334799; Wed, 12 Dec 2012 11:08:54 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ip8sm16086127pbc.36.2012.12.12.11.08.53 (version=SSLv3 cipher=OTHER); Wed, 12 Dec 2012 11:08:53 -0800 (PST) Message-ID: <50C8D644.9060103@gmail.com> Date: Wed, 12 Dec 2012 11:08:52 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Lars-Peter Clausen , "Hill, Steven" , Ralf Baechle CC: "linux-mips@linux-mips.org" Subject: Re: [PATCH] MIPS: Make CP0 config registers readable via sysfs. References: <1354858280-29576-1-git-send-email-sjhill@mips.com>,<50C89870.5000704@metafoo.de> <31E06A9FC96CEC488B43B19E2957C1B801146AA779@exchdb03.mips.com> <50C8D1D4.5050200@metafoo.de> In-Reply-To: <50C8D1D4.5050200@metafoo.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35273 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1528 Lines: 31 On 12/12/2012 10:49 AM, Lars-Peter Clausen wrote: > On 12/12/2012 05:44 PM, Hill, Steven wrote: >> Lars, >> >> This patch was requested by our DSP/Codec group to help with selecting the best user-space codecs at runtime. Simply reading /proc/cpuinfo was insufficient. I posted this patch more for feedback and interest with minimal expectations that it would make it upstream. This patch will always be in our supported branches, but I will defer to everyone else on its worth for upstream. >> >> -Steve > > Well if it is something that is useful it makes sense to upstream it, > especially if you are developing applications. Many people before you have > learned the hard way that stashing stuff away in their private branches was not > the best idea. If you are smart you are going to avoid that. > > It may not be the best solution though to just dump all the cp register to > userspace. As Florian suggested there might be a smarter way to solve this. If you want to have glibc's ld.so automatically select optimal libraries for a given platform, then the elf_platform is the way to do it. However I don't think this is necessarily the case here. elf_platform cannot easily handle a bunch of orthogonal capabilities. So I am in favor of the principle of this patch. There should be a per CPU file (probably in /sys/devices/system/cpu/cpuXX) with the CP0_Config values. One question I have is: Should it be a single file with one row for each implemented Config register, or one file per register? David Daney From manuel.lauss@gmail.com Wed Dec 12 20:15:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 20:15:40 +0100 (CET) Received: from mail-oa0-f49.google.com ([209.85.219.49]:40766 "EHLO mail-oa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817207Ab2LLTPjSsjll (ORCPT ); Wed, 12 Dec 2012 20:15:39 +0100 Received: by mail-oa0-f49.google.com with SMTP id l10so1167000oag.36 for ; Wed, 12 Dec 2012 11:15:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=TnqBGculqCCGGk4KBeU39Ppu/SnnRf1SLescYWAOj7I=; b=Uqrci1kOkTaBApSil5vdx8+689N4pA2b5s/F5bl652E/2X7s1i5Dna879HrsqU9QWo RCiZhpcZnytdZHstutfgS4k+a5QX3ZmcG9JbspzlnZg73Tq+BLb4H8exBqr+lvWEtr08 x55NjXvmyyapcpZeQnEnW2lz5C+SYkDAT3tYFdSgoCScPVjeW1YmIIKjrQU0jMAdTLKQ U6qc48aLabwYMmIbL2utEsLT4IC608sWieHQcmsUAxwv/7AIzpQtDpwOJ0uHH/KzC3mB WCr41bQD+k8Pjbc8dGyW8q1H4w35inDJE+xdHsxOyYB2nYQVpGuXnjykqxmYOuS7iwnR JWdg== Received: by 10.182.141.70 with SMTP id rm6mr1022915obb.59.1355339732755; Wed, 12 Dec 2012 11:15:32 -0800 (PST) MIME-Version: 1.0 Received: by 10.60.95.129 with HTTP; Wed, 12 Dec 2012 11:14:52 -0800 (PST) In-Reply-To: <50C8D644.9060103@gmail.com> References: <1354858280-29576-1-git-send-email-sjhill@mips.com> <50C89870.5000704@metafoo.de> <31E06A9FC96CEC488B43B19E2957C1B801146AA779@exchdb03.mips.com> <50C8D1D4.5050200@metafoo.de> <50C8D644.9060103@gmail.com> From: Manuel Lauss Date: Wed, 12 Dec 2012 20:14:52 +0100 Message-ID: Subject: Re: [PATCH] MIPS: Make CP0 config registers readable via sysfs. To: David Daney Cc: Lars-Peter Clausen , "Hill, Steven" , Ralf Baechle , "linux-mips@linux-mips.org" Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35274 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1873 Lines: 50 On Wed, Dec 12, 2012 at 8:08 PM, David Daney wrote: > On 12/12/2012 10:49 AM, Lars-Peter Clausen wrote: >> >> On 12/12/2012 05:44 PM, Hill, Steven wrote: >>> >>> Lars, >>> >>> This patch was requested by our DSP/Codec group to help with selecting >>> the best user-space codecs at runtime. Simply reading /proc/cpuinfo was >>> insufficient. I posted this patch more for feedback and interest with >>> minimal expectations that it would make it upstream. This patch will always >>> be in our supported branches, but I will defer to everyone else on its worth >>> for upstream. >>> >>> -Steve >> >> >> Well if it is something that is useful it makes sense to upstream it, >> especially if you are developing applications. Many people before you have >> learned the hard way that stashing stuff away in their private branches >> was not >> the best idea. If you are smart you are going to avoid that. >> >> It may not be the best solution though to just dump all the cp register to >> userspace. As Florian suggested there might be a smarter way to solve >> this. > > > > If you want to have glibc's ld.so automatically select optimal libraries for > a given platform, then the elf_platform is the way to do it. > > However I don't think this is necessarily the case here. elf_platform > cannot easily handle a bunch of orthogonal capabilities. So I am in favor > of the principle of this patch. > > There should be a per CPU file (probably in /sys/devices/system/cpu/cpuXX) > with the CP0_Config values. > > One question I have is: Should it be a single file with one row for each > implemented Config register, or one file per register? I'm all for the one-file-per-register approach. I find it easier to just read the right register instead of having to find out how many rows to read to get the value I'm looking for. Thanks! Manuel From wim@iguana.be Wed Dec 12 22:00:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 22:00:58 +0100 (CET) Received: from ns1.pc-advies.be ([83.149.101.17]:36102 "EHLO spo001.leaseweb.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6825653Ab2LLVA5jKW96 (ORCPT ); Wed, 12 Dec 2012 22:00:57 +0100 Received: from wimvs by spo001.leaseweb.com with local (Exim 4.50) id 1TitPV-0008Al-2v; Wed, 12 Dec 2012 22:00:09 +0100 Date: Wed, 12 Dec 2012 22:00:09 +0100 From: Wim Van Sebroeck To: Hauke Mehrtens Cc: linville@tuxdriver.com, linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, zajec5@gmail.com, linux-mips@linux-mips.org Subject: Re: [PATCH v2 00/15] watchdog/bcm47xx/bcma/ssb: add support for SoCs with PMU Message-ID: <20121212210009.GB31388@spo001.leaseweb.com> References: <1353975925-32056-1-git-send-email-hauke@hauke-m.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1353975925-32056-1-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.4.1i X-archive-position: 35275 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 285 Lines: 10 Hi Hauke, > @Wim Could you give me an ACK on the "watchdog: bcm47xx_wdt.c:" patches > so that John could take them trough the wireless-testing tree, or > provide me with some feedback on what I should change. I'll take a look at it and come back on it. Kind regards, Wim. From wim@iguana.be Wed Dec 12 22:38:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 22:38:01 +0100 (CET) Received: from ns1.pc-advies.be ([83.149.101.17]:36141 "EHLO spo001.leaseweb.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6825730Ab2LLViBMwwED (ORCPT ); Wed, 12 Dec 2012 22:38:01 +0100 Received: from wimvs by spo001.leaseweb.com with local (Exim 4.50) id 1Tiu01-0008Tj-Tf; Wed, 12 Dec 2012 22:37:53 +0100 Date: Wed, 12 Dec 2012 22:37:53 +0100 From: Wim Van Sebroeck To: =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= Cc: Hauke Mehrtens , linville@tuxdriver.com, linux-wireless@vger.kernel.org, linux-watchdog@vger.kernel.org, castet.matthieu@free.fr, biblbroks@sezampro.rs, m@bues.ch, linux-mips@linux-mips.org Subject: Re: [PATCH v2 00/15] watchdog/bcm47xx/bcma/ssb: add support for SoCs with PMU Message-ID: <20121212213753.GC31853@spo001.leaseweb.com> References: <1353975925-32056-1-git-send-email-hauke@hauke-m.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i X-archive-position: 35276 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 711 Lines: 22 Hi, > > @Wim Could you give me an ACK on the "watchdog: bcm47xx_wdt.c:" patches > > so that John could take them trough the wireless-testing tree, or > > provide me with some feedback on what I should change. > > Hi Wim, > > Have you got a chance to look at that patches? > > I've some additional bcma changes I wish to submit on top of this :) Sorry, but family health issues have distracted me from kernel stuff the last months. Things are better now. Concerning these patches: The correct decision has been taken to split this allready up into the bcma/ssb patches and do the watchdog patches later on. I will check the watchdog part and react on it as soon as possible. Kind regards, Wim. From rientjes@google.com Wed Dec 12 23:55:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Dec 2012 23:55:07 +0100 (CET) Received: from mail-pa0-f49.google.com ([209.85.220.49]:42128 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831627Ab2LLWzFusmx0 (ORCPT ); Wed, 12 Dec 2012 23:55:05 +0100 Received: by mail-pa0-f49.google.com with SMTP id bi1so948777pad.36 for ; Wed, 12 Dec 2012 14:54:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:x-x-sender:to:cc:subject:in-reply-to:message-id :references:user-agent:mime-version:content-type; bh=05+xC4fgB6q12pou/KeBZJUaZRI19bHQ4h7zg86XZ/Q=; b=jaXxxHKtcWHNODDn+0qAT+oKB3ptWEM88mymZquMWmHrY2KzJeBzSztGr73GGjgl1v 8ATpnsftrFJHUK4JfE98oBf598bvl0+c9SDh4qi05a0quLJ/lQRJ5Ap+5zK3gnQDWJwf Ql0LDd6XgctRDsogyD4v1beaB3Wv3EFuAT14P7VEHK69tCsr94PBb2+QkMPYuXupGu5B 1pJqNw0Mxkcw157zqtB3SlSqLmfPejsfCYuHY3UY4p5LpCS/m2KaCfP1Tvl2aSsN78/U SC/RTM6dqIdF+bWFwWqu8JINNy2C8UB8fV3uvCmpt6puUf8lWRPGAiQgzJIug6x0vtlY Qvzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:x-x-sender:to:cc:subject:in-reply-to:message-id :references:user-agent:mime-version:content-type:x-gm-message-state; bh=05+xC4fgB6q12pou/KeBZJUaZRI19bHQ4h7zg86XZ/Q=; b=PWVhZZmksaSViZQS4pt9YQQ50otV5iJpP0yaFHcZ+osT1hq02FMlRcr8UF5o1dBB6i jydyX0zJWtGVWCmDT2dIrk6t1ByX2AV74K6082mZrTF29JOO/P5QHNCfhN838w+As4BV nCdwn8lSLPSkSBlGmYydaEPKQxiCrhHMoEPwYc4P5KeE3XLMhde931Xz9yXoalBigbzM RYvmb3SwZGo863ILJ51Yvy/h6ayThRfe1D93M6511aaTB5hAJOCqTwLbTKTjcB/qJGcX 0HJsfgVfQJOPZbpHWYtLrvOXTrQorqBxIWnipPEvpwFJjs2X7jGl2PJVl+F1P4iIVd+H SAWw== Received: by 10.68.230.135 with SMTP id sy7mr6851311pbc.76.1355352897459; Wed, 12 Dec 2012 14:54:57 -0800 (PST) Received: from [2620:0:1008:1101:be30:5bff:fed8:5e64] ([2620:0:1008:1101:be30:5bff:fed8:5e64]) by mx.google.com with ESMTPS id pl10sm5570717pbc.60.2012.12.12.14.54.56 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 12 Dec 2012 14:54:56 -0800 (PST) Date: Wed, 12 Dec 2012 14:54:55 -0800 (PST) From: David Rientjes X-X-Sender: rientjes@chino.kir.corp.google.com To: "Kirill A. Shutemov" cc: Andrew Morton , linux-mm@kvack.org, Arnd Bergmann , linux-arch@vger.kernel.org, linux-s390@vger.kernel.org, Martin Schwidefsky , Heiko Carstens , linux-mips@linux-mips.org, Ralf Baechle , John Crispin Subject: Re: [PATCH, RESEND] asm-generic, mm: pgtable: consolidate zero page helpers In-Reply-To: <20121212105538.GA14208@otc-wbsnb-06> Message-ID: References: <1354881215-26257-1-git-send-email-kirill.shutemov@linux.intel.com> <20121212105538.GA14208@otc-wbsnb-06> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Gm-Message-State: ALoCoQnkre78oUxp73D0SbOFdaZSqKo5T6w6CFvvUxBJ1ETnRSrzPYcxzoDuHikqHVeyyYvkIrJjSKfxw+PeEFvFpsmi3i2NbT6mmTmuSYABlzQqJTyc6WAdeC94vjmjhVg48rHRej8RW6oESKvJz6nwpjr6cAMxrwISg+uPWNjKHCVdNEcWwyfkH5FKYjRFOCeL0Wu24VbdtvfyR5PZx4vyZYZzxtF8Jw== X-archive-position: 35277 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rientjes@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 756 Lines: 15 On Wed, 12 Dec 2012, Kirill A. Shutemov wrote: > > What's the benefit from doing this other than generalizing some per-arch > > code? It simply adds on more layer of redirection to try to find the > > implementation that matters for the architecture you're hacking on. > > The idea of asm-generic is consolidation arch code which can be re-used > for different arches. It also makes support of new arches easier. > Yeah, but you're moving is_zero_pfn() unnecessarily into a header file when it is only used mm/memory.c and it adds a __HAVE_* definition that we always try to reduce (both __HAVE and __ARCH definitions are frowned upon). I don't think it's much of a win to obfuscate the code because mips and s390 implement colored zero pages. From sjhill@mips.com Thu Dec 13 09:47:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Dec 2012 09:47:56 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:58333 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823911Ab2LMIrzVjRQm (ORCPT ); Thu, 13 Dec 2012 09:47:55 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tj4Rz-0004iA-1I; Thu, 13 Dec 2012 02:47:27 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2] MIPS: Make CP0 config registers readable via sysfs. Date: Thu, 13 Dec 2012 02:47:21 -0600 Message-Id: <1355388441-6762-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35278 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3891 Lines: 130 From: "Steven J. Hill" Allow reading of CP0 config registers via sysfs for each core in the system. The registers will show up in sysfs at the path: /sys/devices/system/cpu/cpuX/configX Only CP0 config registers 0 through 7 are currently supported. Signed-off-by: Steven J. Hill --- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/sysfs.c | 93 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 arch/mips/kernel/sysfs.c diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cc5eec6..0c3eb97 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o +obj-y += sysfs.o ifeq ($(CONFIG_CPU_MIPS32), y) # diff --git a/arch/mips/kernel/sysfs.c b/arch/mips/kernel/sysfs.c new file mode 100644 index 0000000..a64f559 --- /dev/null +++ b/arch/mips/kernel/sysfs.c @@ -0,0 +1,93 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include + +#include + + +#define __BUILD_CP0_SYSFS(reg) \ +static DEFINE_PER_CPU(unsigned int, cpu_config##reg); \ +static ssize_t show_config##reg(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct cpu *cpu = container_of(dev, struct cpu, dev); \ + int n = snprintf(buf, PAGE_SIZE-2, "%x\n", \ + per_cpu(cpu_config##reg, cpu->dev.id)); \ + return n; \ +} \ +static DEVICE_ATTR(config##reg, 0444, show_config##reg, NULL); + +__BUILD_CP0_SYSFS(0) +__BUILD_CP0_SYSFS(1) +__BUILD_CP0_SYSFS(2) +__BUILD_CP0_SYSFS(3) +__BUILD_CP0_SYSFS(4) +__BUILD_CP0_SYSFS(5) +__BUILD_CP0_SYSFS(6) +__BUILD_CP0_SYSFS(7) + +static void read_c0_registers(void *arg) +{ + struct device *dev = get_cpu_device(smp_processor_id()); + struct cpu *cpu; + int ok; + + if (dev != NULL) { + cpu = container_of(dev, struct cpu, dev); + per_cpu(cpu_config0, cpu->dev.id) = read_c0_config(); + device_create_file(dev, &dev_attr_config0); + ok = per_cpu(cpu_config0, cpu->dev.id) & MIPS_CONF_M; + } else + return; + + if (ok) { + per_cpu(cpu_config1, cpu->dev.id) = read_c0_config1(); + device_create_file(dev, &dev_attr_config1); + ok = per_cpu(cpu_config1, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config2, cpu->dev.id) = read_c0_config2(); + device_create_file(dev, &dev_attr_config2); + ok = per_cpu(cpu_config2, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config3, cpu->dev.id) = read_c0_config3(); + device_create_file(dev, &dev_attr_config3); + ok = per_cpu(cpu_config3, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config4, cpu->dev.id) = read_c0_config4(); + device_create_file(dev, &dev_attr_config4); + ok = per_cpu(cpu_config4, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config5, cpu->dev.id) = read_c0_config5(); + device_create_file(dev, &dev_attr_config5); + ok = per_cpu(cpu_config5, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config6, cpu->dev.id) = read_c0_config6(); + device_create_file(dev, &dev_attr_config6); + ok = per_cpu(cpu_config6, cpu->dev.id) & MIPS_CONF_M; + } + if (ok) { + per_cpu(cpu_config7, cpu->dev.id) = read_c0_config7(); + device_create_file(dev, &dev_attr_config7); + ok = per_cpu(cpu_config7, cpu->dev.id) & MIPS_CONF_M; + } +} + +static int __init mips_sysfs_registers(void) +{ + on_each_cpu(read_c0_registers, NULL, 1); + return 0; +} +late_initcall(mips_sysfs_registers); -- 1.7.9.5 From sjhill@mips.com Thu Dec 13 09:53:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Dec 2012 09:53:59 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:58347 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824762Ab2LMIx6ZduUe (ORCPT ); Thu, 13 Dec 2012 09:53:58 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tj4Y9-0004iP-AN; Thu, 13 Dec 2012 02:53:49 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v3] MIPS: Make CP0 config registers readable via sysfs. Date: Thu, 13 Dec 2012 02:53:44 -0600 Message-Id: <1355388824-7655-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35279 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2781 Lines: 105 From: "Steven J. Hill" Allow reading of CP0 config registers via sysfs for each core in the system. The registers will show up in sysfs at the path: /sys/devices/system/cpu/cpuX/configX Only CP0 config registers 0 through 7 are currently supported. Signed-off-by: Steven J. Hill --- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/sysfs.c | 68 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/mips/kernel/sysfs.c diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cc5eec6..0c3eb97 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o +obj-y += sysfs.o ifeq ($(CONFIG_CPU_MIPS32), y) # diff --git a/arch/mips/kernel/sysfs.c b/arch/mips/kernel/sysfs.c new file mode 100644 index 0000000..4f26349 --- /dev/null +++ b/arch/mips/kernel/sysfs.c @@ -0,0 +1,68 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include + +#include + +/* Convenience macro */ +#define read_c0_config0() read_c0_config() + +#define __BUILD_CP0_SYSFS(reg) \ +static ssize_t show_config##reg(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + int n = snprintf(buf, PAGE_SIZE-2, "%x\n", \ + read_c0_config##reg()); \ + return n; \ +} \ +static DEVICE_ATTR(config##reg, 0444, show_config##reg, NULL); + +__BUILD_CP0_SYSFS(0) +__BUILD_CP0_SYSFS(1) +__BUILD_CP0_SYSFS(2) +__BUILD_CP0_SYSFS(3) +__BUILD_CP0_SYSFS(4) +__BUILD_CP0_SYSFS(5) +__BUILD_CP0_SYSFS(6) +__BUILD_CP0_SYSFS(7) + +#define __CHECK_CONFIG_EXIST(reg) \ +if (ok) { \ + device_create_file(dev, &dev_attr_config##reg); \ + ok = read_c0_config##reg() & MIPS_CONF_M; \ +} + +static void read_c0_registers(void *arg) +{ + struct device *dev = get_cpu_device(smp_processor_id()); + int ok = 1; + + __CHECK_CONFIG_EXIST(0); + __CHECK_CONFIG_EXIST(1); + __CHECK_CONFIG_EXIST(2); + __CHECK_CONFIG_EXIST(3); + __CHECK_CONFIG_EXIST(4); + __CHECK_CONFIG_EXIST(5); + __CHECK_CONFIG_EXIST(6); + __CHECK_CONFIG_EXIST(7); +} + +static int __init mips_sysfs_registers(void) +{ + /* Not CPU hotplug safe. */ +#ifndef CONFIG_HOTPLUG_CPU + on_each_cpu(read_c0_registers, NULL, 1); + return 0; +#else + return 1; +#endif +} +late_initcall(mips_sysfs_registers); -- 1.7.9.5 From ddaney.cavm@gmail.com Thu Dec 13 18:50:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Dec 2012 18:50:47 +0100 (CET) Received: from mail-pb0-f49.google.com ([209.85.160.49]:38678 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6829639Ab2LMRuqbgXYd (ORCPT ); Thu, 13 Dec 2012 18:50:46 +0100 Received: by mail-pb0-f49.google.com with SMTP id un15so1580553pbc.36 for ; Thu, 13 Dec 2012 09:50:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=8EUKjPEp7H85h7TebDxRVFo41uzkYa96DTz1osn0w5U=; b=RpjVO4QaXxyve2Y6xJmpVcr5hw3E0rtfXHZeF7/+wfEI7ygf7Tovst7Mixsysa5nBs grDbPOintr4e8K1hSpe4UOWPZCxHUUq1yO90qjb0hkqSpSu+tlTEJ9zWGjO+wThEBmgs IWP4Za0DwmgV8AnQfXcdyeBn3+upsjVDZoAriLoMELh3pYmrvBeIJQlraVsZjV3g9ifA nA20sm2rZt/ByA0DKQQbtgLr3jbBPDka0aQNEEfqlNuhRS1HLtw76MQLjhjm2hEtuwZ9 vpzQNetXqGrhqbWvP2fTTaGftvayLF7JvtbYu4Tl+Yn5WYZvAFuStdx+JWo8Ksf/QV2V 278Q== Received: by 10.69.0.10 with SMTP id au10mr7836862pbd.18.1355421039606; Thu, 13 Dec 2012 09:50:39 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id yi9sm1366181pbc.39.2012.12.13.09.50.36 (version=SSLv3 cipher=OTHER); Thu, 13 Dec 2012 09:50:36 -0800 (PST) Message-ID: <50CA156B.6000002@gmail.com> Date: Thu, 13 Dec 2012 09:50:35 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Steven J. Hill" , ralf@linux-mips.org CC: linux-mips@linux-mips.org Subject: Re: [PATCH v3] MIPS: Make CP0 config registers readable via sysfs. References: <1355388824-7655-1-git-send-email-sjhill@mips.com> In-Reply-To: <1355388824-7655-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35282 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2387 Lines: 84 On 12/13/2012 12:53 AM, Steven J. Hill wrote: > From: "Steven J. Hill" > Thanks Steven, > Allow reading of CP0 config registers via sysfs for each core > in the system. The registers will show up in sysfs at the path: > > /sys/devices/system/cpu/cpuX/configX > > Only CP0 config registers 0 through 7 are currently supported. That's not really a limitation, as those are the only ones that exist. > > Signed-off-by: Steven J. Hill One small change below, but otherwise, Acked-by: David Daney > --- > arch/mips/kernel/Makefile | 1 + > arch/mips/kernel/sysfs.c | 68 +++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 69 insertions(+) > create mode 100644 arch/mips/kernel/sysfs.c > > diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile > index cc5eec6..0c3eb97 100644 > --- a/arch/mips/kernel/Makefile > +++ b/arch/mips/kernel/Makefile > @@ -97,6 +97,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o > obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o > > obj-$(CONFIG_JUMP_LABEL) += jump_label.o > +obj-y += sysfs.o > > ifeq ($(CONFIG_CPU_MIPS32), y) > # > diff --git a/arch/mips/kernel/sysfs.c b/arch/mips/kernel/sysfs.c > new file mode 100644 > index 0000000..4f26349 > --- /dev/null > +++ b/arch/mips/kernel/sysfs.c > @@ -0,0 +1,68 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. > + */ > +#include > +#include > +#include > +#include > + > +#include > + > +/* Convenience macro */ > +#define read_c0_config0() read_c0_config() > + > +#define __BUILD_CP0_SYSFS(reg) \ > +static ssize_t show_config##reg(struct device *dev, \ > + struct device_attribute *attr, char *buf) \ > +{ \ > + int n = snprintf(buf, PAGE_SIZE-2, "%x\n", \ > + read_c0_config##reg()); \ > + return n; \ > +} \ > +static DEVICE_ATTR(config##reg, 0444, show_config##reg, NULL); s/0444/S_IRUGO/ [...] > +late_initcall(mips_sysfs_registers); > Why late_initcall? I don't really have an objection, but unless there is a good reason, why not device_initcall? From sjhill@mips.com Thu Dec 13 23:15:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Dec 2012 23:15:54 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:59654 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823110Ab2LMWPwx33lo (ORCPT ); Thu, 13 Dec 2012 23:15:52 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TjH3o-0005Th-AF; Thu, 13 Dec 2012 16:15:20 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs. Date: Thu, 13 Dec 2012 16:15:15 -0600 Message-Id: <1355436915-24381-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35283 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3942 Lines: 155 From: "Steven J. Hill" Allow reading of CP0 config registers via sysfs for each core in the system. The registers will show up in sysfs at the path: /sys/devices/system/cpu/cpuX/configX Hotplugging of CPUs is also supported. Signed-off-by: Steven J. Hill --- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/sysfs.c | 118 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 arch/mips/kernel/sysfs.c diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cc5eec6..0c3eb97 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o +obj-y += sysfs.o ifeq ($(CONFIG_CPU_MIPS32), y) # diff --git a/arch/mips/kernel/sysfs.c b/arch/mips/kernel/sysfs.c new file mode 100644 index 0000000..1c02471 --- /dev/null +++ b/arch/mips/kernel/sysfs.c @@ -0,0 +1,118 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define read_c0_config0() read_c0_config() + +#define __BUILD_CP0_SYSFS(reg) \ +static ssize_t show_config##reg(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + int n = snprintf(buf, PAGE_SIZE-2, "%x\n", \ + read_c0_config##reg()); \ + return n; \ +} \ +static DEVICE_ATTR(config##reg, S_IRUGO, show_config##reg, NULL); + +__BUILD_CP0_SYSFS(0) +__BUILD_CP0_SYSFS(1) +__BUILD_CP0_SYSFS(2) +__BUILD_CP0_SYSFS(3) +__BUILD_CP0_SYSFS(4) +__BUILD_CP0_SYSFS(5) +__BUILD_CP0_SYSFS(6) +__BUILD_CP0_SYSFS(7) + +static DEFINE_PER_CPU(unsigned int, nregs); + +#define __CREATE_CONFIG_ENTRY(reg) \ +if (ok) { \ + device_create_file(dev, &dev_attr_config##reg); \ + ok = read_c0_config##reg() & MIPS_CONF_M; \ + per_cpu(nregs, cpu)++; \ +} + +#define __DELETE_CONFIG_ENTRY(reg) \ +if (reg < per_cpu(nregs, cpu)) \ + device_remove_file(dev, &dev_attr_config##reg); + +static void create_cp0_entries(unsigned int cpu) +{ + struct device *dev = get_cpu_device(cpu); + int ok = 1; + + per_cpu(nregs, cpu) = 0; + __CREATE_CONFIG_ENTRY(0); + __CREATE_CONFIG_ENTRY(1); + __CREATE_CONFIG_ENTRY(2); + __CREATE_CONFIG_ENTRY(3); + __CREATE_CONFIG_ENTRY(4); + __CREATE_CONFIG_ENTRY(5); + __CREATE_CONFIG_ENTRY(6); + __CREATE_CONFIG_ENTRY(7); +} + +#ifdef CONFIG_HOTPLUG_CPU +static void delete_cp0_entries(unsigned int cpu) +{ + struct device *dev = get_cpu_device(cpu); + + __DELETE_CONFIG_ENTRY(0); + __DELETE_CONFIG_ENTRY(1); + __DELETE_CONFIG_ENTRY(2); + __DELETE_CONFIG_ENTRY(3); + __DELETE_CONFIG_ENTRY(4); + __DELETE_CONFIG_ENTRY(5); + __DELETE_CONFIG_ENTRY(6); + __DELETE_CONFIG_ENTRY(7); +} +#endif + +static int __cpuinit sysfs_cpu_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + unsigned int cpu = (unsigned int)(long)hcpu; + + switch (action) { + case CPU_ONLINE: + case CPU_ONLINE_FROZEN: + create_cp0_entries(cpu); + break; +#ifdef CONFIG_HOTPLUG_CPU + case CPU_DEAD: + case CPU_DEAD_FROZEN: + delete_cp0_entries(cpu); + break; +#endif + } + return NOTIFY_OK; +} + +static struct notifier_block __cpuinitdata sysfs_cpu_nb = { + .notifier_call = sysfs_cpu_notify, +}; + +static int __init sysfs_mips_config_registers(void) +{ + int i; + + for_each_online_cpu(i) + create_cp0_entries(i); + register_cpu_notifier(&sysfs_cpu_nb); + return 0; +} +subsys_initcall(sysfs_mips_config_registers); -- 1.7.9.5 From macro@linux-mips.org Fri Dec 14 00:27:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Dec 2012 00:27:34 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:52033 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823110Ab2LMX1dd2Qh- (ORCPT ); Fri, 14 Dec 2012 00:27:33 +0100 Date: Thu, 13 Dec 2012 23:27:33 +0000 (GMT) From: "Maciej W. Rozycki" To: "Steven J. Hill" cc: linux-mips@linux-mips.org, Ralf Baechle Subject: Re: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs. In-Reply-To: <1355436915-24381-1-git-send-email-sjhill@mips.com> Message-ID: References: <1355436915-24381-1-git-send-email-sjhill@mips.com> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 35284 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 413 Lines: 12 On Thu, 13 Dec 2012, Steven J. Hill wrote: > Allow reading of CP0 config registers via sysfs for each core > in the system. The registers will show up in sysfs at the path: > > /sys/devices/system/cpu/cpuX/configX You're exporting privileged context outside the kernel -- have all the security implications been considered? At the very least I don't think these files should be word-readable. Maciej From ddaney.cavm@gmail.com Fri Dec 14 00:39:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Dec 2012 00:39:08 +0100 (CET) Received: from mail-da0-f49.google.com ([209.85.210.49]:33125 "EHLO mail-da0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6829678Ab2LMXjHdsbdz (ORCPT ); Fri, 14 Dec 2012 00:39:07 +0100 Received: by mail-da0-f49.google.com with SMTP id v40so1018150dad.36 for ; Thu, 13 Dec 2012 15:39:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=VTABqe3S7OO3Ep3/PurOxZNtPmjmh2USs6RfbyoMKeU=; b=gd0l1yStgBASdBpIkGL+f/nUUzFVW5TsV3mrR/pqTGHH54GTtoxJbsGipYKVujXDg3 XLBY0ulfrhUquhUFSgpPyuckTef3hNfssMj1VX3NVOw1bLKzicE9ufv2lsPDHowEHIEh qWSCVW4LrBebkY3bpJ7/pvRFnqQylcYAJXW4HG/Z1atCQSilIvYTx8MFxKw0CRe6RKNF T+Tbk2JkPM0Y7LderZxNT+h5HYDk+lbXdeATWFskpBSRvi40uzRhXTsi01eHBYdKxrO/ puagHbyJ5snv1YFkjk8kKYed0z1TM86Va5RUDMH7cvfCxQu218wfi7ho+KciKpK+h6mf v1IQ== Received: by 10.66.90.72 with SMTP id bu8mr10548439pab.69.1355441940381; Thu, 13 Dec 2012 15:39:00 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id k4sm2022252paz.26.2012.12.13.15.38.59 (version=SSLv3 cipher=OTHER); Thu, 13 Dec 2012 15:38:59 -0800 (PST) Message-ID: <50CA6712.1060809@gmail.com> Date: Thu, 13 Dec 2012 15:38:58 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: "Steven J. Hill" , linux-mips@linux-mips.org, Ralf Baechle Subject: Re: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs. References: <1355436915-24381-1-git-send-email-sjhill@mips.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35285 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 994 Lines: 32 On 12/13/2012 03:27 PM, Maciej W. Rozycki wrote: > On Thu, 13 Dec 2012, Steven J. Hill wrote: > >> Allow reading of CP0 config registers via sysfs for each core >> in the system. The registers will show up in sysfs at the path: >> >> /sys/devices/system/cpu/cpuX/configX > > You're exporting privileged context outside the kernel -- have all the > security implications been considered? Can you give an example of what would be risky? > At the very least I don't think > these files should be word-readable. > According to Steven's earlier comments, all he really cares about are the ASEs implemented. We have a patch (that I will send soon) that exports the Cache configurations via the same method that x86 Cache information is reported, so that part of the config register information would be reported separately. The rest of the CP0_ConfigX bits really report things that are only useful to privileged mode software, so perhaps they shouldn't be reported. David Daney From sjhill@mips.com Fri Dec 14 06:03:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Dec 2012 06:03:13 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:46322 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816743Ab2LNFDMk-vWM convert rfc822-to-8bit (ORCPT ); Fri, 14 Dec 2012 06:03:12 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qBE534Fp016489; Thu, 13 Dec 2012 21:03:04 -0800 X-WSS-ID: 0MF08P4-01-2AY-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2A72D36465D; Thu, 13 Dec 2012 21:03:03 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.01.0270.001; Thu, 13 Dec 2012 21:03:00 -0800 From: "Hill, Steven" To: Florian Fainelli , Lars-Peter Clausen CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: RE: [PATCH] OF: MIPS: sead3: Implement OF support. Thread-Topic: [PATCH] OF: MIPS: sead3: Implement OF support. Thread-Index: AQHN1DnSWGjTUvhf40CMe1gF/gDbQ5gVx+UAgAAGqwCAAADlAIAB+Dr+ Date: Fri, 14 Dec 2012 05:02:58 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AB302@exchdb03.mips.com> References: <1354857297-28863-1-git-send-email-sjhill@mips.com> <50C894D4.4090008@openwrt.org> <50C89A6C.705@metafoo.de>,<50C89B2C.1070903@openwrt.org> In-Reply-To: <50C89B2C.1070903@openwrt.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: 1eWDm6UTv4bHtGJs39amCg== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35286 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 283 Lines: 5 > > But in anyway the patch should also add documentation under > Documentation/devicetree/bindings describing the binding. > There is not much in the SEAD-3 .dts file and I see zero documentation for Lantiq or Netlogic. I am skipping adding anything in the Documentation directory. From sjhill@mips.com Fri Dec 14 06:56:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Dec 2012 06:56:12 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:60225 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816743Ab2LNF4LBbPcs (ORCPT ); Fri, 14 Dec 2012 06:56:11 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TjOFe-0005jC-SD; Thu, 13 Dec 2012 23:56:02 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2] OF: MIPS: sead3: Implement OF support. Date: Thu, 13 Dec 2012 23:55:58 -0600 Message-Id: <1355464558-11787-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35287 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8747 Lines: 318 From: "Steven J. Hill" Activate USE_OF for SEAD-3 platform. Add basic DTS file and convert memory detection and reservations to use OF. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 1 + arch/mips/include/asm/mips-boards/prom.h | 2 + arch/mips/mti-sead3/Makefile | 14 ++- arch/mips/mti-sead3/sead3-init.c | 5 +- arch/mips/mti-sead3/sead3-memory.c | 138 ------------------------------ arch/mips/mti-sead3/sead3-setup.c | 31 +++++++ arch/mips/mti-sead3/sead3.dts | 26 ++++++ 7 files changed, 76 insertions(+), 141 deletions(-) delete mode 100644 arch/mips/mti-sead3/sead3-memory.c create mode 100644 arch/mips/mti-sead3/sead3.dts diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 92d9a3c..8cb3c6e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -354,6 +354,7 @@ config MIPS_SEAD3 select USB_ARCH_HAS_EHCI select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO + select USE_OF help This enables support for the MIPS Technologies SEAD3 evaluation board. diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h index a9db576..2d427aa 100644 --- a/arch/mips/include/asm/mips-boards/prom.h +++ b/arch/mips/include/asm/mips-boards/prom.h @@ -44,4 +44,6 @@ struct prom_pmemblock { unsigned int type; /* free or prom memory */ }; +extern struct boot_param_header __dtb_start; + #endif /* !(_MIPS_PROM_H) */ diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile index 626afea..e2ace8a 100644 --- a/arch/mips/mti-sead3/Makefile +++ b/arch/mips/mti-sead3/Makefile @@ -5,10 +5,12 @@ # Copyright (C) 2008 Wind River Systems, Inc. # written by Ralf Baechle # +# Copyright (C) 2012 MIPS Technoligies, Inc. All rights reserved. +# Steven J. Hill +# obj-y := sead3-lcd.o sead3-cmdline.o \ sead3-display.o sead3-init.o sead3-int.o \ - sead3-mtd.o sead3-net.o \ - sead3-memory.o sead3-platform.o \ + sead3-mtd.o sead3-net.o sead3-platform.o \ sead3-reset.o sead3-setup.o sead3-time.o obj-y += sead3-i2c-dev.o sead3-i2c.o \ @@ -17,3 +19,11 @@ obj-y += sead3-i2c-dev.o sead3-i2c.o \ obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o + +DTS_FILES = sead3.dts +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) + +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) + +$(obj)/%.dtb: $(obj)/%.dts FORCE + $(call if_changed_dep,dtc) diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c index 802fce2..6939254 100644 --- a/arch/mips/mti-sead3/sead3-init.c +++ b/arch/mips/mti-sead3/sead3-init.c @@ -125,7 +125,6 @@ void __init prom_init(void) board_ejtag_handler_setup = mips_ejtag_setup; prom_init_cmdline(); - prom_meminit(); #ifdef CONFIG_EARLY_PRINTK if ((strstr(prom_getcmdline(), "console=ttyS0")) != NULL) prom_init_early_console(0); @@ -137,3 +136,7 @@ void __init prom_init(void) strcat(prom_getcmdline(), " console=ttyS0,38400n8r"); #endif } + +void prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/mti-sead3/sead3-memory.c b/arch/mips/mti-sead3/sead3-memory.c deleted file mode 100644 index da92441..0000000 --- a/arch/mips/mti-sead3/sead3-memory.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. - */ -#include - -#include -#include -#include - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; - -static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -/* determined physical memory size, not overridden by command line args */ -unsigned long physical_memsize = 0L; - -struct prom_pmemblock * __init prom_getmdesc(void) -{ - char *memsize_str, *ptr; - unsigned int memsize; - static char cmdline[COMMAND_LINE_SIZE] __initdata; - long val; - int tmp; - - /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - pr_warn("memsize not set in boot prom, set to default 32Mb\n"); - physical_memsize = 0x02000000; - } else { - tmp = kstrtol(memsize_str, 0, &val); - physical_memsize = (unsigned long)val; - } - -#ifdef CONFIG_CPU_BIG_ENDIAN - /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last - word of physical memory */ - physical_memsize -= PAGE_SIZE; -#endif - - /* Check the command line for a memsize directive that overrides - the physical/default amount */ - strcpy(cmdline, arcs_cmdline); - ptr = strstr(cmdline, "memsize="); - if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) - ptr = strstr(ptr, " memsize="); - - if (ptr) - memsize = memparse(ptr + 8, &ptr); - else - memsize = physical_memsize; - - memset(mdesc, 0, sizeof(mdesc)); - - mdesc[0].type = yamon_dontuse; - mdesc[0].base = 0x00000000; - mdesc[0].size = 0x00001000; - - mdesc[1].type = yamon_prom; - mdesc[1].base = 0x00001000; - mdesc[1].size = 0x000ef000; - - /* - * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the - * south bridge and PCI access always forwarded to the ISA Bus and - * BIOSCS# is always generated. - * This mean that this area can't be used as DMA memory for PCI - * devices. - */ - mdesc[2].type = yamon_dontuse; - mdesc[2].base = 0x000f0000; - mdesc[2].size = 0x00010000; - - mdesc[3].type = yamon_dontuse; - mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - - mdesc[3].base; - - mdesc[4].type = yamon_free; - mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); - mdesc[4].size = memsize - mdesc[4].base; - - return &mdesc[0]; -} - -static int __init prom_memtype_classify(unsigned int type) -{ - switch (type) { - case yamon_free: - return BOOT_MEM_RAM; - case yamon_prom: - return BOOT_MEM_ROM_DATA; - default: - return BOOT_MEM_RESERVED; - } -} - -void __init prom_meminit(void) -{ - struct prom_pmemblock *p; - - p = prom_getmdesc(); - - while (p->size) { - long type; - unsigned long base, size; - - type = prom_memtype_classify(p->type); - base = p->base; - size = p->size; - - add_memory_region(base, size, type); - p++; - } -} - -void __init prom_free_prom_memory(void) -{ - unsigned long addr; - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c index 8ad46ad..83faf68 100644 --- a/arch/mips/mti-sead3/sead3-setup.c +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -6,6 +6,11 @@ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include +#include +#include +#include + +#include int coherentio; /* 0 => no DMA cache coherency (may be set by user) */ int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */ @@ -17,4 +22,30 @@ const char *get_system_type(void) void __init plat_mem_setup(void) { + extern struct boot_param_header __dtb_start; + + /* + * Load the builtin devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + __dt_setup_arch(&__dtb_start); +} + +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); + + /* free the space reserved for the dt blob */ + free_bootmem(base, size); } diff --git a/arch/mips/mti-sead3/sead3.dts b/arch/mips/mti-sead3/sead3.dts new file mode 100644 index 0000000..658f437 --- /dev/null +++ b/arch/mips/mti-sead3/sead3.dts @@ -0,0 +1,26 @@ +/dts-v1/; + +/memreserve/ 0x00000000 0x00001000; // reserved +/memreserve/ 0x00001000 0x000ef000; // ROM data +/memreserve/ 0x000f0000 0x004cc000; // reserved + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mti,sead-3"; + + cpus { + cpu@0 { + compatible = "mti,mips14KEc", "mti,mips14Kc"; + }; + }; + + chosen { + bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; -- 1.7.9.5 From john@phrozen.org Fri Dec 14 08:06:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Dec 2012 08:06:50 +0100 (CET) Received: from nbd.name ([46.4.11.11]:48936 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6820610Ab2LNHGtK9QUF (ORCPT ); Fri, 14 Dec 2012 08:06:49 +0100 Message-ID: <50CACF97.5020402@phrozen.org> Date: Fri, 14 Dec 2012 08:04:55 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH v2] OF: MIPS: sead3: Implement OF support. References: <1355464558-11787-1-git-send-email-sjhill@mips.com> In-Reply-To: <1355464558-11787-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35288 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 940 Lines: 27 On 14/12/12 06:55, Steven J. Hill wrote: > From: "Steven J. Hill" > > Activate USE_OF for SEAD-3 platform. Add basic DTS file and convert > memory detection and reservations to use OF. > > Signed-off-by: Steven J. Hill > --- > arch/mips/Kconfig | 1 + > arch/mips/include/asm/mips-boards/prom.h | 2 + > arch/mips/mti-sead3/Makefile | 14 ++- > arch/mips/mti-sead3/sead3-init.c | 5 +- > arch/mips/mti-sead3/sead3-memory.c | 138 ------------------------------ > arch/mips/mti-sead3/sead3-setup.c | 31 +++++++ > arch/mips/mti-sead3/sead3.dts | 26 ++++++ > 7 files changed, 76 insertions(+), 141 deletions(-) > delete mode 100644 arch/mips/mti-sead3/sead3-memory.c > create mode 100644 arch/mips/mti-sead3/sead3.dts > Hi Steven, this patch still has the 2 problems i mentioned in the V1 inside it. John From sjhill@mips.com Fri Dec 14 23:14:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Dec 2012 23:14:54 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:33270 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823017Ab2LNWOuEzWbj (ORCPT ); Fri, 14 Dec 2012 23:14:50 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TjdWj-0006XV-8Z; Fri, 14 Dec 2012 16:14:41 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v3] OF: MIPS: sead3: Implement OF support. Date: Fri, 14 Dec 2012 16:14:36 -0600 Message-Id: <1355523276-2989-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35289 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8561 Lines: 311 From: "Steven J. Hill" Activate USE_OF for SEAD-3 platform. Add basic DTS file and convert memory detection and reservations to use OF. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 1 + arch/mips/include/asm/mips-boards/prom.h | 2 + arch/mips/mti-sead3/Makefile | 10 ++- arch/mips/mti-sead3/sead3-init.c | 5 +- arch/mips/mti-sead3/sead3-memory.c | 138 ------------------------------ arch/mips/mti-sead3/sead3-setup.c | 28 ++++++ arch/mips/mti-sead3/sead3.dts | 26 ++++++ 7 files changed, 69 insertions(+), 141 deletions(-) delete mode 100644 arch/mips/mti-sead3/sead3-memory.c create mode 100644 arch/mips/mti-sead3/sead3.dts diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 8fa6d7c..8bb9518 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -356,6 +356,7 @@ config MIPS_SEAD3 select USB_ARCH_HAS_EHCI select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO + select USE_OF help This enables support for the MIPS Technologies SEAD3 evaluation board. diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h index a9db576..2d427aa 100644 --- a/arch/mips/include/asm/mips-boards/prom.h +++ b/arch/mips/include/asm/mips-boards/prom.h @@ -44,4 +44,6 @@ struct prom_pmemblock { unsigned int type; /* free or prom memory */ }; +extern struct boot_param_header __dtb_start; + #endif /* !(_MIPS_PROM_H) */ diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile index 626afea..10ec701 100644 --- a/arch/mips/mti-sead3/Makefile +++ b/arch/mips/mti-sead3/Makefile @@ -5,10 +5,12 @@ # Copyright (C) 2008 Wind River Systems, Inc. # written by Ralf Baechle # +# Copyright (C) 2012 MIPS Technoligies, Inc. All rights reserved. +# Steven J. Hill +# obj-y := sead3-lcd.o sead3-cmdline.o \ sead3-display.o sead3-init.o sead3-int.o \ - sead3-mtd.o sead3-net.o \ - sead3-memory.o sead3-platform.o \ + sead3-mtd.o sead3-net.o sead3-platform.o \ sead3-reset.o sead3-setup.o sead3-time.o obj-y += sead3-i2c-dev.o sead3-i2c.o \ @@ -17,3 +19,7 @@ obj-y += sead3-i2c-dev.o sead3-i2c.o \ obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o +obj-$(CONFIG_OF) += sead3.dtb.o + +$(obj)/%.dtb: $(obj)/%.dts + $(call if_changed,dtc) diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c index 802fce2..6939254 100644 --- a/arch/mips/mti-sead3/sead3-init.c +++ b/arch/mips/mti-sead3/sead3-init.c @@ -125,7 +125,6 @@ void __init prom_init(void) board_ejtag_handler_setup = mips_ejtag_setup; prom_init_cmdline(); - prom_meminit(); #ifdef CONFIG_EARLY_PRINTK if ((strstr(prom_getcmdline(), "console=ttyS0")) != NULL) prom_init_early_console(0); @@ -137,3 +136,7 @@ void __init prom_init(void) strcat(prom_getcmdline(), " console=ttyS0,38400n8r"); #endif } + +void prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/mti-sead3/sead3-memory.c b/arch/mips/mti-sead3/sead3-memory.c deleted file mode 100644 index da92441..0000000 --- a/arch/mips/mti-sead3/sead3-memory.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. - */ -#include - -#include -#include -#include - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; - -static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -/* determined physical memory size, not overridden by command line args */ -unsigned long physical_memsize = 0L; - -struct prom_pmemblock * __init prom_getmdesc(void) -{ - char *memsize_str, *ptr; - unsigned int memsize; - static char cmdline[COMMAND_LINE_SIZE] __initdata; - long val; - int tmp; - - /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - pr_warn("memsize not set in boot prom, set to default 32Mb\n"); - physical_memsize = 0x02000000; - } else { - tmp = kstrtol(memsize_str, 0, &val); - physical_memsize = (unsigned long)val; - } - -#ifdef CONFIG_CPU_BIG_ENDIAN - /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last - word of physical memory */ - physical_memsize -= PAGE_SIZE; -#endif - - /* Check the command line for a memsize directive that overrides - the physical/default amount */ - strcpy(cmdline, arcs_cmdline); - ptr = strstr(cmdline, "memsize="); - if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) - ptr = strstr(ptr, " memsize="); - - if (ptr) - memsize = memparse(ptr + 8, &ptr); - else - memsize = physical_memsize; - - memset(mdesc, 0, sizeof(mdesc)); - - mdesc[0].type = yamon_dontuse; - mdesc[0].base = 0x00000000; - mdesc[0].size = 0x00001000; - - mdesc[1].type = yamon_prom; - mdesc[1].base = 0x00001000; - mdesc[1].size = 0x000ef000; - - /* - * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the - * south bridge and PCI access always forwarded to the ISA Bus and - * BIOSCS# is always generated. - * This mean that this area can't be used as DMA memory for PCI - * devices. - */ - mdesc[2].type = yamon_dontuse; - mdesc[2].base = 0x000f0000; - mdesc[2].size = 0x00010000; - - mdesc[3].type = yamon_dontuse; - mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - - mdesc[3].base; - - mdesc[4].type = yamon_free; - mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); - mdesc[4].size = memsize - mdesc[4].base; - - return &mdesc[0]; -} - -static int __init prom_memtype_classify(unsigned int type) -{ - switch (type) { - case yamon_free: - return BOOT_MEM_RAM; - case yamon_prom: - return BOOT_MEM_ROM_DATA; - default: - return BOOT_MEM_RESERVED; - } -} - -void __init prom_meminit(void) -{ - struct prom_pmemblock *p; - - p = prom_getmdesc(); - - while (p->size) { - long type; - unsigned long base, size; - - type = prom_memtype_classify(p->type); - base = p->base; - size = p->size; - - add_memory_region(base, size, type); - p++; - } -} - -void __init prom_free_prom_memory(void) -{ - unsigned long addr; - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c index 8ad46ad..af8903d 100644 --- a/arch/mips/mti-sead3/sead3-setup.c +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -6,6 +6,11 @@ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include +#include +#include +#include + +#include int coherentio; /* 0 => no DMA cache coherency (may be set by user) */ int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */ @@ -17,4 +22,27 @@ const char *get_system_type(void) void __init plat_mem_setup(void) { + extern struct boot_param_header __dtb_start; + + /* + * Load the builtin devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + __dt_setup_arch(&__dtb_start); +} + +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); } diff --git a/arch/mips/mti-sead3/sead3.dts b/arch/mips/mti-sead3/sead3.dts new file mode 100644 index 0000000..658f437 --- /dev/null +++ b/arch/mips/mti-sead3/sead3.dts @@ -0,0 +1,26 @@ +/dts-v1/; + +/memreserve/ 0x00000000 0x00001000; // reserved +/memreserve/ 0x00001000 0x000ef000; // ROM data +/memreserve/ 0x000f0000 0x004cc000; // reserved + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mti,sead-3"; + + cpus { + cpu@0 { + compatible = "mti,mips14KEc", "mti,mips14Kc"; + }; + }; + + chosen { + bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; -- 1.7.9.5 From sjhill@mips.com Sat Dec 15 06:06:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 15 Dec 2012 06:06:22 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:33791 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816206Ab2LOFGVHarlN (ORCPT ); Sat, 15 Dec 2012 06:06:21 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Tjjwz-0006mh-Er; Fri, 14 Dec 2012 23:06:13 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2] MIPS: dsp: Add assembler support for DSP ASEs. Date: Fri, 14 Dec 2012 23:06:07 -0600 Message-Id: <1355547967-13779-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35290 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3626 Lines: 135 From: "Steven J. Hill" Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mipsregs.h | 53 ++++++++++++++++++++++++++------------ arch/mips/kernel/Makefile | 27 +++++++++++++++++++ 2 files changed, 63 insertions(+), 17 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index a9ed612..0960d68 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1155,36 +1155,26 @@ do { \ : "=r" (__res)); \ __res;}) +#ifdef HAVE_AS_DSP #define rddsp(mask) \ ({ \ - unsigned int __res; \ + unsigned int __dspctl; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ + " rddsp %0, %x1 \n" \ + : "=r" (__dspctl) \ : "i" (mask)); \ - __res; \ + __dspctl; \ }) #define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ - " .set pop \n" \ - : \ + " wrdsp %0, %x1 \n" \ + : \ : "r" (val), "i" (mask)); \ } while (0) -#if 0 /* Need DSP ASE capable assembler ... */ #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) @@ -1207,6 +1197,35 @@ do { \ #else +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ + " .set pop \n" \ + : \ + : "r" (val), "i" (mask)); \ +} while (0) + #define mfhi0() \ ({ \ unsigned long __treg; \ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 33a96a9..c3c8cba 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -98,4 +98,31 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o +# +# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only +# +ifeq ($(CONFIG_CPU_MIPSR2), y) +CFLAGS_DSP = -DHAVE_AS_DSP + +# +# Check if assembler supports DSP ASE +# +ifeq ($(call cc-option-yn,-mdsp), y) +CFLAGS_DSP += -mdsp +endif + +# +# Check if assembler supports DSP ASE Rev2 +# +ifeq ($(call cc-option-yn,-mdspr2), y) +CFLAGS_DSP += -mdspr2 +endif + +CFLAGS_signal.o = $(CFLAGS_DSP) +CFLAGS_signal32.o = $(CFLAGS_DSP) +CFLAGS_process.o = $(CFLAGS_DSP) +CFLAGS_branch.o = $(CFLAGS_DSP) +CFLAGS_ptrace.o = $(CFLAGS_DSP) +endif + CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) -- 1.7.9.5 From sjhill@mips.com Sat Dec 15 06:10:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 15 Dec 2012 06:10:26 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:47452 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816206Ab2LOFKVAX5b8 convert rfc822-to-8bit (ORCPT ); Sat, 15 Dec 2012 06:10:21 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qBF5ACR0006690; Fri, 14 Dec 2012 21:10:12 -0800 X-WSS-ID: 0MF23OX-01-2RQ-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2882336465D; Fri, 14 Dec 2012 21:10:09 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.01.0270.001; Fri, 14 Dec 2012 21:10:06 -0800 From: "Hill, Steven" To: Florian Fainelli CC: "linux-mips@linux-mips.org" Subject: RE: [PATCH] MIPS: dsp: Add assembler support for DSP ASEs. Thread-Topic: [PATCH] MIPS: dsp: Add assembler support for DSP ASEs. Thread-Index: AQHN1DbCEutikq7i/UCxLXUHzYmgqZgVxmQAgAOVCZc= Date: Sat, 15 Dec 2012 05:10:05 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AB429@exchdb03.mips.com> References: <1354855981-28392-1-git-send-email-sjhill@mips.com>,<50C8938C.8020705@openwrt.org> In-Reply-To: <50C8938C.8020705@openwrt.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: 2PYP6mgVtyrb/8rE9O0mAQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35291 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1157 Lines: 41 >> +ifeq ($(call cc-option-yn,-mdsp2), y) >> +CFLAGS_signal.o = -mdsp2 -DHAVE_AS_DSP >> +CFLAGS_signal32.o = -mdsp2 -DHAVE_AS_DSP >> +CFLAGS_process.o = -mdsp2 -DHAVE_AS_DSP >> +CFLAGS_branch.o = -mdsp2 -DHAVE_AS_DSP >> +CFLAGS_ptrace.o = -mdsp2 -DHAVE_AS_DSP > > Should not this be -mdspr2 here? My GCC man page suggests that. > Yes, corrected this. > By the way, should not we also check that we are building for a > MIPS32_R2 CPU when checking for -mdsp2? > Yes, fixed this also. > I would simplify this like this: > > ifeq ($(CONFIG_CPU_MIPS32),y) > CFLAGS_DSP = -DHAVE_AS_DSP > ifeq ($(call cc-option-yn,-mdsp),y) > CFLAGS_DSP += -mdsp > endif > ifeq ($(call cc-option-yn,-mdsp2),y) > CFLAGS-DSP += -mdsp2 >endif > > CFLAGS_signal.o = $(CFLAGS_DSP) > ... > CFLAGS_ptrace.o = $(CFLAGS_DSP) > endif > > such that the day you can take advantage of a third DSP flavor it's only > 3 lines worth of Makefile to get it used, and you only have one place > where you need to change CFLAGS. > Good idea, fixed. I have posted a new patch for review. -Steve From sjhill@mips.com Sat Dec 15 06:16:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 15 Dec 2012 06:16:32 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:54456 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816206Ab2LOFQPtpCFI convert rfc822-to-8bit (ORCPT ); Sat, 15 Dec 2012 06:16:15 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qBF5G9N8006772; Fri, 14 Dec 2012 21:16:09 -0800 X-WSS-ID: 0MF23YR-01-2RR-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.67]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 220D736465A; Fri, 14 Dec 2012 21:16:02 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([fe80::2897:a30d:a923:303%16]) with mapi id 14.01.0270.001; Fri, 14 Dec 2012 21:15:58 -0800 From: "Hill, Steven" To: "ralf@linux-mips.org" , Kevin Cernekee CC: "linux-mips@linux-mips.org" , "Kevin D. Kissell" Subject: RE: [PATCH v99,01/13] MIPS: microMIPS: Add support for microMIPS instructions. Thread-Topic: [PATCH v99,01/13] MIPS: microMIPS: Add support for microMIPS instructions. Thread-Index: AQHN1DiHCvL61O110EKCn4uZDGaFTZgNfKEAgAB++gCAC2ENog== Date: Sat, 15 Dec 2012 05:15:56 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AB43B@exchdb03.mips.com> References: <1354856737-28678-1-git-send-email-sjhill@mips.com> <1354856737-28678-2-git-send-email-sjhill@mips.com> ,<20121207152438.GC25923@linux-mips.org> In-Reply-To: <20121207152438.GC25923@linux-mips.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: 7o0zcoJgP0DjKlARO/J+Jg== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35292 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1097 Lines: 19 >> The microMIPS patch nearly quadruples the number of instruction >> formats in the mips_instruction union, so it might be worth >> considering questions like: >> >> 1) Is this the optimal way to represent this information, or have we >> reached a point where it is worth adding more complex "infrastructure" >> that would support a more compact instruction definition format? >> >> 2) Is there a better way to handle the LE/BE bitfield problem, than to >> duplicate each of the 28+ structs? > > Something based on #defines, for example. Back in the dark ages I > figured bitfields would be nicer way to represent instruction formats. > Against the warning words of I think Kevin Kissel I went for the bitfields > and this would be a good opportunity to change direction. > Oh sure, why not. I mean I've only rewritten this patch at least 10 times. What's one more time? :) If one or all of you would expound on what your design ideas are, that would be great. Again, not to sound like a scratched CD, but I am still shooting for this code to get into 3.9, so please reply soon. Thanks. -Steve From jogo@openwrt.org Sun Dec 16 12:42:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Dec 2012 12:42:30 +0100 (CET) Received: from mail.nanl.de ([217.115.11.12]:58265 "EHLO mail.nanl.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823018Ab2LPLm3w4ZAB (ORCPT ); Sun, 16 Dec 2012 12:42:29 +0100 Received: from mail-oa0-f49.google.com (mail-oa0-f49.google.com [209.85.219.49]) by mail.nanl.de (Postfix) with ESMTPSA id B97EE40572; Sun, 16 Dec 2012 11:41:49 +0000 (UTC) Received: by mail-oa0-f49.google.com with SMTP id l10so5108719oag.36 for ; Sun, 16 Dec 2012 03:42:25 -0800 (PST) Received: by 10.60.0.165 with SMTP id 5mr9214289oef.128.1355658145159; Sun, 16 Dec 2012 03:42:25 -0800 (PST) MIME-Version: 1.0 Received: by 10.76.28.70 with HTTP; Sun, 16 Dec 2012 03:42:05 -0800 (PST) In-Reply-To: <1355547967-13779-1-git-send-email-sjhill@mips.com> References: <1355547967-13779-1-git-send-email-sjhill@mips.com> From: Jonas Gorski Date: Sun, 16 Dec 2012 12:42:05 +0100 Message-ID: Subject: Re: [PATCH v2] MIPS: dsp: Add assembler support for DSP ASEs. To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 35295 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jogo@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 625 Lines: 21 On 15 December 2012 06:06, Steven J. Hill wrote: > (snip) > diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile > index 33a96a9..c3c8cba 100644 > --- a/arch/mips/kernel/Makefile > +++ b/arch/mips/kernel/Makefile > @@ -98,4 +98,31 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o > > obj-$(CONFIG_JUMP_LABEL) += jump_label.o > > +# > +# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only > +# > +ifeq ($(CONFIG_CPU_MIPSR2), y) > +CFLAGS_DSP = -DHAVE_AS_DSP 24K (non-E) is MIPS32r2, but not not implement any DSP ASEs, is this a problem here? Jonas From manuel.lauss@gmail.com Sun Dec 16 20:41:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Dec 2012 20:41:49 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:44580 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823059Ab2LPTlry0hwJ (ORCPT ); Sun, 16 Dec 2012 20:41:47 +0100 Received: by mail-bk0-f49.google.com with SMTP id jm19so2353786bkc.36 for ; Sun, 16 Dec 2012 11:41:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=gBlJZw82KRibjIa9dMuttcVeP6JODlfrzAPmbcwhwtE=; b=SSULHaDmsbKqhjBK8jYV8hfoBusXDbnJPeH0DmJgngzr87OGxeKeVYIUYEZHOGFjRQ hdl+he6l0Vn8QBGs7RD7aSpdeo/pvMel/UdNnnFr9tZ7zZkkW1idZgo+Ur51nhhmSv2N 4qglPJMutX3D4kQgtbfCN4gClOiDPZFgpaYdBUks9SjCFkHWTZXPWwe75Q1n5awIYC4H 6/OrLst6aNOEKkanCsp9QXHYt7WPJa9AX22AnXHwJ3JxKdkJBQWwRPU+0c4FECj+Op3d MXLCncHh8ckZEDGxhoNevQn1ttJizbys8d3shg+tdE20RgvuHjVenS8Jht/DjGleTSk3 U/cQ== Received: by 10.204.151.21 with SMTP id a21mr5141023bkw.124.1355686902381; Sun, 16 Dec 2012 11:41:42 -0800 (PST) Received: from flagship.roarinelk.net (188-22-154-9.adsl.highway.telekom.at. [188.22.154.9]) by mx.google.com with ESMTPS id v8sm7861031bku.6.2012.12.16.11.41.40 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 16 Dec 2012 11:41:41 -0800 (PST) From: Manuel Lauss To: Ralf Baechle , Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: make 32kHz and r4k timer coexist peacefully Date: Sun, 16 Dec 2012 20:41:36 +0100 Message-Id: <1355686896-26001-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.8.0.2 X-archive-position: 35297 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2812 Lines: 85 From: Manuel Lauss Now that the r4k timer is registered no matter what, bump the rating of the Alchemy 32kHz timer so that it gets used when it is working, and fall back on the r4k when it isn't. This fixes a timer-related hang on platform with a working 32kHz timer (the better rated c0 timer stops while executing 'wait' leading to (almost) eternal sleep) and an oops on boot on platforms without a working 32kHz timer (due to double registration of the r4k timer). Signed-off-by: Manuel Lauss --- For what is to become 3.8. This is a quick fix; it's far less invasive than my preferred solution: having each platform register the r4k clocksource explicitly. It should be enough until Alchemy variants with speeds >= 1.3GHz appear (which is very unlikely). arch/mips/alchemy/common/time.c | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index a7193ae..12589d0 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -53,7 +53,7 @@ static struct clocksource au1x_counter1_clocksource = { .read = au1x_counter1_read, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .rating = 100, + .rating = 1500, }; static int au1x_rtcmatch2_set_next_event(unsigned long delta, @@ -84,7 +84,7 @@ static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id) static struct clock_event_device au1x_rtcmatch2_clockdev = { .name = "rtcmatch2", .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 100, + .rating = 1500, .set_next_event = au1x_rtcmatch2_set_next_event, .set_mode = au1x_rtcmatch2_set_mode, .cpumask = cpu_all_mask, @@ -158,20 +158,6 @@ cntr_err: return -1; } -static void __init alchemy_setup_c0timer(void) -{ - /* - * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this - * function is called. Because the Alchemy counters are unusable - * the C0 timekeeping code is installed and use of the 'wait' - * instruction must be prohibited, which is done most easily by - * assigning NULL to cpu_wait. - */ - cpu_wait = NULL; - r4k_clockevent_init(); - init_r4k_clocksource(); -} - static int alchemy_m2inttab[] __initdata = { AU1000_RTC_MATCH2_INT, AU1500_RTC_MATCH2_INT, @@ -183,11 +169,8 @@ static int alchemy_m2inttab[] __initdata = { void __init plat_time_init(void) { - int t; - - t = alchemy_get_cputype(); - if (t == ALCHEMY_CPU_UNKNOWN) - alchemy_setup_c0timer(); - else if (alchemy_time_init(alchemy_m2inttab[t])) - alchemy_setup_c0timer(); + int t = alchemy_get_cputype(); + if ((t == ALCHEMY_CPU_UNKNOWN) || + (alchemy_time_init(alchemy_m2inttab[t]))) + cpu_wait = NULL; /* wait doesn't work with r4k timer */ } -- 1.8.0.2 From sshtylyov@mvista.com Sun Dec 16 21:17:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Dec 2012 21:17:44 +0100 (CET) Received: from mail-lb0-f177.google.com ([209.85.217.177]:59820 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823043Ab2LPURmJm4-8 (ORCPT ); Sun, 16 Dec 2012 21:17:42 +0100 Received: by mail-lb0-f177.google.com with SMTP id n10so4107894lbo.36 for ; Sun, 16 Dec 2012 12:17:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=MP+T3n1RgdaQNYwDZnCwawtsqMJUhnlvyQnhBIKxbXI=; b=USB0WNyuGoZ8N9Hpe0GLZRIBlfdJKebPrCON4YSmEbGFGoKypO0zSrcJK4QM+1kEZ+ TZjeSiKMojO+mwqxxRaKppjKjtst7NWNo20A/yR2J9H5DCzhed5hI+PhGknFbZLqW8EF tO7eS2Z8B/rp+lXTYU1HNEAGvY2ByJcOxqqVKYK/fSE8eTGua021XU2cSxiziGr6XC4f 5EwvjQl7ZpNpLxvCKt6HBpPDIQF7wV6RgGzwi04cyj7rlZW/1xz1eHhHFlOLAoJf130k frbZBC7Nt8GTI9gyrjHSBn+TlB5Pz5Z0X2sRkdv7osC3SACwrJviqxsvrlmBLeRo1Qvt 8fgw== Received: by 10.152.46.161 with SMTP id w1mr8904068lam.27.1355689056381; Sun, 16 Dec 2012 12:17:36 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-89-229.pppoe.mtu-net.ru. [91.79.89.229]) by mx.google.com with ESMTPS id pw17sm4039964lab.5.2012.12.16.12.17.34 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 16 Dec 2012 12:17:35 -0800 (PST) Message-ID: <50CE2C65.6020805@mvista.com> Date: Mon, 17 Dec 2012 00:17:41 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Manuel Lauss CC: Ralf Baechle , Linux-MIPS Subject: Re: [PATCH] MIPS: Alchemy: make 32kHz and r4k timer coexist peacefully References: <1355686896-26001-1-git-send-email-manuel.lauss@googlemail.com> In-Reply-To: <1355686896-26001-1-git-send-email-manuel.lauss@googlemail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlVkkcIL1dO4HVQ8wCly0HbOUf3AN9uU+WNjzTHIJhjcI3D1AutHPvXId42xJICQZdOCeOa X-archive-position: 35298 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1801 Lines: 54 Hello. On 16-12-2012 23:41, Manuel Lauss wrote: > From: Manuel Lauss > Now that the r4k timer is registered no matter what, bump the rating of > the Alchemy 32kHz timer so that it gets used when it is working, > and fall back on the r4k when it isn't. > This fixes a timer-related hang on platform with a working 32kHz timer > (the better rated c0 timer stops while executing 'wait' leading to (almost) > eternal sleep) and an oops on boot on platforms without a working 32kHz timer > (due to double registration of the r4k timer). > Signed-off-by: Manuel Lauss > --- > For what is to become 3.8. > This is a quick fix; it's far less invasive than my preferred solution: > having each platform register the r4k clocksource explicitly. > It should be enough until Alchemy variants with speeds >= 1.3GHz appear > (which is very unlikely). > arch/mips/alchemy/common/time.c | 29 ++++++----------------------- > 1 file changed, 6 insertions(+), 23 deletions(-) > diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c > index a7193ae..12589d0 100644 > --- a/arch/mips/alchemy/common/time.c > +++ b/arch/mips/alchemy/common/time.c [...] > @@ -183,11 +169,8 @@ static int alchemy_m2inttab[] __initdata = { > > void __init plat_time_init(void) > { > - int t; > - > - t = alchemy_get_cputype(); > - if (t == ALCHEMY_CPU_UNKNOWN) > - alchemy_setup_c0timer(); > - else if (alchemy_time_init(alchemy_m2inttab[t])) > - alchemy_setup_c0timer(); > + int t = alchemy_get_cputype(); Could you please keep the coding style and insert empty line here? > + if ((t == ALCHEMY_CPU_UNKNOWN) || > + (alchemy_time_init(alchemy_m2inttab[t]))) Useless parens around == and especially around function call. WBR, Sergei From manuel.lauss@gmail.com Mon Dec 17 08:14:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Dec 2012 08:14:20 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:35914 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816900Ab2LQHOTFHVZD (ORCPT ); Mon, 17 Dec 2012 08:14:19 +0100 Received: by mail-bk0-f49.google.com with SMTP id jm19so2462281bkc.36 for ; Sun, 16 Dec 2012 23:14:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=iO6xG+psKnJMxYSfQTrK9dy3/w2pnIx5NwyLEm7/nsE=; b=tOMpTMoHmQxb5RrfhyyvsEXsh+USinSzLB0ezo/M/kavUz6gHgnuHeArsEUq6v3LxN jnA7yhrbjzdVuDDVjoCJb0aRn7HjSKQZeF/4u/4FWwcEhiXkIeCJDevENK0g+wvKHsed SXy+WeoQ6u/JwvoYGsKTPJ3BxLsqkh+F4PPQKmWMPX9IsyM5ZXLAjp+XKISdzVIIF6Pl 1ggH48PS4Zjc7xf1nA2IZgRSgQDOPoA7u5TXPk1cf8nWUKScO0Gkkp2UgyoCyCf5+BG7 1k6u4QcJjtou3uudhxlHfTw4JlRvfZo0a6gIaCAioe2wPRaeOhdM+WPNu6iZO10FD/Yg rp3A== Received: by 10.204.149.149 with SMTP id t21mr5382838bkv.85.1355728453634; Sun, 16 Dec 2012 23:14:13 -0800 (PST) Received: from flagship.roarinelk.net (178-191-3-232.adsl.highway.telekom.at. [178.191.3.232]) by mx.google.com with ESMTPS id 18sm8349777bkv.0.2012.12.16.23.14.11 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 16 Dec 2012 23:14:12 -0800 (PST) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH v2] MIPS: Alchemy: make 32kHz and r4k timer coexist peacefully Date: Mon, 17 Dec 2012 08:14:08 +0100 Message-Id: <1355728448-24220-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.8.0.2 X-archive-position: 35299 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2720 Lines: 81 Now that the r4k timer is registered no matter what, bump the rating of the Alchemy 32kHz timer so that it gets used when it is working, and fall back on the r4k when it isn't. This fixes a timer-related hang on platform with a working 32kHz timer (the better rated c0 timer stops while executing 'wait' leading to (almost) eternal sleep) and an oops on boot on platforms without a working 32kHz timer (due to double registration of the r4k timer). Signed-off-by: Manuel Lauss --- v2: address Sergey's comments. On top of Linus' latest -git. This is a quick fix, it's far less invasive than my preferred solution: having each platform register the r4k clocksource explicitly. It should be enough until Alchemy variants with speeds >= 1.3GHz appear (which I believe is _very_ unlikely). arch/mips/alchemy/common/time.c | 25 +++++-------------------- 1 file changed, 5 insertions(+), 20 deletions(-) diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index a7193ae..b67930d 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -53,7 +53,7 @@ static struct clocksource au1x_counter1_clocksource = { .read = au1x_counter1_read, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .rating = 100, + .rating = 1500, }; static int au1x_rtcmatch2_set_next_event(unsigned long delta, @@ -84,7 +84,7 @@ static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id) static struct clock_event_device au1x_rtcmatch2_clockdev = { .name = "rtcmatch2", .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 100, + .rating = 1500, .set_next_event = au1x_rtcmatch2_set_next_event, .set_mode = au1x_rtcmatch2_set_mode, .cpumask = cpu_all_mask, @@ -158,20 +158,6 @@ cntr_err: return -1; } -static void __init alchemy_setup_c0timer(void) -{ - /* - * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this - * function is called. Because the Alchemy counters are unusable - * the C0 timekeeping code is installed and use of the 'wait' - * instruction must be prohibited, which is done most easily by - * assigning NULL to cpu_wait. - */ - cpu_wait = NULL; - r4k_clockevent_init(); - init_r4k_clocksource(); -} - static int alchemy_m2inttab[] __initdata = { AU1000_RTC_MATCH2_INT, AU1500_RTC_MATCH2_INT, @@ -186,8 +172,7 @@ void __init plat_time_init(void) int t; t = alchemy_get_cputype(); - if (t == ALCHEMY_CPU_UNKNOWN) - alchemy_setup_c0timer(); - else if (alchemy_time_init(alchemy_m2inttab[t])) - alchemy_setup_c0timer(); + if (t == ALCHEMY_CPU_UNKNOWN || + alchemy_time_init(alchemy_m2inttab[t])) + cpu_wait = NULL; /* wait doesn't work with r4k timer */ } -- 1.8.0.2 From manuel.lauss@gmail.com Mon Dec 17 08:22:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Dec 2012 08:22:02 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:52241 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816668Ab2LQHWBSNrzz (ORCPT ); Mon, 17 Dec 2012 08:22:01 +0100 Received: by mail-bk0-f49.google.com with SMTP id jm19so2464483bkc.36 for ; Sun, 16 Dec 2012 23:21:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=OWmsNDNVI1yp0W7eeM4QJRQOOfNWza4xKRiOMbM2Tl0=; b=ElBM3erYm7/G7ODnGKmMzzKMAF/FXDydvtCm72jmfqhe2kPZ5WbjXEJhuXkdRcr64I zM/Vw7NiFc9fdkf58NpU1M0RB0sRDiKW6cEj5qZp7/v5v7PfT20EGFBqtdt+rb9mFjoD 88YY5nNLp5gjWjZlYweTkv0FZ2e1BsdpixUIWptwQsPmH0cbpDO17JTjKziYM7yaxSz0 SVPp+EC7x8iv7tqJ7HDEMRe8q9dYShm2739JvSNU2qtYVn1kA0nnXUP15imLyjh2bvRl YdXn5XC6si32Gq19ao228NKFiWxbEx/OqlhtbkZ/yIvETtvKYP+EDBg9T53N+sLoSlce KRJA== Received: by 10.204.147.207 with SMTP id m15mr5407875bkv.54.1355728915947; Sun, 16 Dec 2012 23:21:55 -0800 (PST) Received: from flagship.roarinelk.net (178-191-3-232.adsl.highway.telekom.at. [178.191.3.232]) by mx.google.com with ESMTPS id d16sm8364392bkw.2.2012.12.16.23.21.54 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 16 Dec 2012 23:21:55 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: John Crispin , Ralf Baechle , Manuel Lauss , Zi Shen Lim , Jayachandran C Subject: [PATCH] MIPS: perf: fix build failure in XLP perf support. Date: Mon, 17 Dec 2012 08:21:46 +0100 Message-Id: <1355728906-24370-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.8.0.2 X-archive-position: 35300 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3713 Lines: 111 Commit 4be3d2f3966b9f010bb997dcab25e7af489a841e ("MIPS: perf: Add XLP support for hardware perf.") added UNSUPPORTED_PERF_EVENT_ID which was removed a while back. Cc: Zi Shen Lim Cc: Jayachandran C Signed-off-by: Manuel Lauss --- Against Linus' latest -git. That's also where the commit-id is from. arch/mips/kernel/perf_event_mipsxx.c | 38 ------------------------------------ 1 file changed, 38 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index b14c14d..51aa6a4 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -847,7 +847,6 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */ [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */ - [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, }; /* 24K/34K/1004K cores can share the same cache event map. */ @@ -1115,24 +1114,12 @@ static const struct mips_perf_event xlp_cache_map [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */ [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */ }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(L1I)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(LL)] = { [C(OP_READ)] = { @@ -1143,10 +1130,6 @@ static const struct mips_perf_event xlp_cache_map [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */ [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */ }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(DTLB)] = { /* @@ -1154,46 +1137,25 @@ static const struct mips_perf_event xlp_cache_map * read and write. */ [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(ITLB)] = { [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(BPU)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x25, CNTR_ALL }, }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, -}, }; #ifdef CONFIG_MIPS_MT_SMP -- 1.8.0.2 From manuel.lauss@gmail.com Mon Dec 17 08:26:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Dec 2012 08:26:30 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:61799 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816671Ab2LQH03uWmQr (ORCPT ); Mon, 17 Dec 2012 08:26:29 +0100 Received: by mail-bk0-f49.google.com with SMTP id jm19so2465762bkc.36 for ; Sun, 16 Dec 2012 23:26:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=ItrBgqnjIyPlHpvNnhMCeNerYfVRaHaSgaydA8+Hj4I=; b=Q6EcymrKnlEfVJfUJSsFqB+w1d2jU85IEr+oFNqqe7PGvhcihR6bAwqURq+kJe0wf9 oTfjQ1uhoeqXicOxwsBkurIzGTTn6Gg6Vj6tRXdueIAfsmfd9xASgONc0SurwobdVsR/ G+8mCnvkJFwptr6oVfT/leCGmH+YsVr0wAlkOfUj3s33W5viQsW19zIlcNtjx9va3hT6 vIatobzHZag+vKz5dp5XaKmuz+S4ksxn17ZlqaNoyzEqdTiUBEnjxBLyD6DnBUxXLlU8 p0z5PKz031LCMHqzIZFQKpFw1PSfrGG/2DONyKmQT4gbyjfe36XiQu3LkLXnIc7/YTo/ gNRQ== Received: by 10.204.146.6 with SMTP id f6mr5373172bkv.69.1355729184487; Sun, 16 Dec 2012 23:26:24 -0800 (PST) Received: from flagship.roarinelk.net (178-191-3-232.adsl.highway.telekom.at. [178.191.3.232]) by mx.google.com with ESMTPS id i20sm8369277bkw.5.2012.12.16.23.26.22 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 16 Dec 2012 23:26:23 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: John Crispin , Ralf Baechle , Manuel Lauss , Zi Shen Lim , Jayachandran C Subject: [PATCH v2] MIPS: perf: fix build failure in XLP perf support. Date: Mon, 17 Dec 2012 08:26:19 +0100 Message-Id: <1355729179-5442-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.8.0.2 X-archive-position: 35301 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3773 Lines: 112 Commit 4be3d2f3966b9f010bb997dcab25e7af489a841e ("MIPS: perf: Add XLP support for hardware perf.") added UNSUPPORTED_PERF_EVENT_ID which was removed a while back. Cc: Zi Shen Lim Cc: Jayachandran C Signed-off-by: Manuel Lauss --- v2: one escaped me and I left the array in a bad state. Now fixed and compile tested! Against Linus' latest -git. That's also where the commit-id is from. arch/mips/kernel/perf_event_mipsxx.c | 38 ------------------------------------ 1 file changed, 38 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index b14c14d..d9c81c5 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -847,7 +847,6 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */ [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */ - [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, }; /* 24K/34K/1004K cores can share the same cache event map. */ @@ -1115,24 +1114,12 @@ static const struct mips_perf_event xlp_cache_map [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */ [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */ }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(L1I)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(LL)] = { [C(OP_READ)] = { @@ -1143,10 +1130,6 @@ static const struct mips_perf_event xlp_cache_map [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */ [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */ }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(DTLB)] = { /* @@ -1154,45 +1137,24 @@ static const struct mips_perf_event xlp_cache_map * read and write. */ [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(ITLB)] = { [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(BPU)] = { [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x25, CNTR_ALL }, }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, }; -- 1.8.0.2 From florian@openwrt.org Mon Dec 17 10:49:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Dec 2012 10:49:10 +0100 (CET) Received: from mail-lb0-f177.google.com ([209.85.217.177]:45734 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816900Ab2LQJtGS4WbI (ORCPT ); Mon, 17 Dec 2012 10:49:06 +0100 Received: by mail-lb0-f177.google.com with SMTP id n10so4458522lbo.36 for ; Mon, 17 Dec 2012 01:49:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=4sDQm90M4KUZLH0sfmPHwP26kGvgPKATh8ItJ/Eep9g=; b=xDi7mrbfaPem6lQ0dMzyT1BCE+zOwrsLiGfUEVHe7jnWreh6tZpixnVMwaEN/N1xLC eapG0Y8buuzbLP3jzkPaEyydcYI1L8l0uL3U6ZKRtInIcldEMw4D4j2srVStUAoiAb2q zSAcOJGjC7zPj+ayOliVA0LJ6Bz8znv7eQMrNmvqiMKMnI4F+YL0pJfhTYtxwaK+f1vF GSYDPS3Lj0B2H/PRjPnif1kM7R37rjI0GHZwLHADrNKz88BDKqSAmby99PBb297KNP1i QGVZgBUXbg/nRGZ7NCLWJrtnLys9/V6hdiTTNN9MQdy7W3r3pCf79MOe5lqlyIsKUC0l 93Xg== Received: by 10.152.114.66 with SMTP id je2mr10207088lab.40.1355737740350; Mon, 17 Dec 2012 01:49:00 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id n7sm4664496lbg.3.2012.12.17.01.48.59 (version=SSLv3 cipher=OTHER); Mon, 17 Dec 2012 01:48:59 -0800 (PST) Message-ID: <50CEEA0B.6030606@openwrt.org> Date: Mon, 17 Dec 2012 10:46:51 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Jonas Gorski CC: "Steven J. Hill" , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2] MIPS: dsp: Add assembler support for DSP ASEs. References: <1355547967-13779-1-git-send-email-sjhill@mips.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35302 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 897 Lines: 25 Le 12/16/12 12:42, Jonas Gorski a écrit : > On 15 December 2012 06:06, Steven J. Hill wrote: >> (snip) >> diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile >> index 33a96a9..c3c8cba 100644 >> --- a/arch/mips/kernel/Makefile >> +++ b/arch/mips/kernel/Makefile >> @@ -98,4 +98,31 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o >> >> obj-$(CONFIG_JUMP_LABEL) += jump_label.o >> >> +# >> +# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only >> +# >> +ifeq ($(CONFIG_CPU_MIPSR2), y) >> +CFLAGS_DSP = -DHAVE_AS_DSP > > 24K (non-E) is MIPS32r2, but not not implement any DSP ASEs, is this a > problem here? I do not think it is, all code-paths making use of the rddsp() wrdsp() macros are checking cpu_has_dsp() so we should be pretty safe here. It might be worth adding this comment to the Makefile though. -- Florian From jchandra@broadcom.com Mon Dec 17 13:46:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Dec 2012 13:46:35 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:4613 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823021Ab2LQMqaYmi0t (ORCPT ); Mon, 17 Dec 2012 13:46:30 +0100 Received: from [10.9.200.133] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 17 Dec 2012 04:41:24 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Mon, 17 Dec 2012 04:45:32 -0800 Received: from jayachandranc.netlogicmicro.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 283F940FE4; Mon, 17 Dec 2012 04:45:47 -0800 (PST) Date: Mon, 17 Dec 2012 18:16:11 +0530 From: "Jayachandran C." To: "Manuel Lauss" cc: Linux-MIPS , "John Crispin" , "Ralf Baechle" , "Zi Shen Lim" Subject: Re: [PATCH v2] MIPS: perf: fix build failure in XLP perf support. Message-ID: <20121217124610.GA30888@jayachandranc.netlogicmicro.com> References: <1355729179-5442-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 In-Reply-To: <1355729179-5442-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-WSS-ID: 7CD1CD7E39W12673483-15-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit X-archive-position: 35303 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 866 Lines: 24 On Mon, Dec 17, 2012 at 08:26:19AM +0100, Manuel Lauss wrote: > Commit 4be3d2f3966b9f010bb997dcab25e7af489a841e ("MIPS: perf: Add > XLP support for hardware perf.") added UNSUPPORTED_PERF_EVENT_ID > which was removed a while back. > > Cc: Zi Shen Lim > Cc: Jayachandran C > Signed-off-by: Manuel Lauss > --- > v2: one escaped me and I left the array in a bad state. Now fixed and compile tested! > > Against Linus' latest -git. That's also where the commit-id is from. > > arch/mips/kernel/perf_event_mipsxx.c | 38 ------------------------------------ > 1 file changed, 38 deletions(-) > Acked-by: Jayachandran C Thanks for fixing this up, I did not notice the perf change [c5600b] which went into 3.7 when submitting the patch. Sorry for the breakage. JC. From jchandra@broadcom.com Tue Dec 18 10:50:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Dec 2012 10:50:04 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:1721 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822190Ab2LRJuBK8vXX (ORCPT ); Tue, 18 Dec 2012 10:50:01 +0100 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 18 Dec 2012 01:46:45 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 18 Dec 2012 01:49:22 -0800 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id EB66A40FE4; Tue, 18 Dec 2012 01:49:37 -0800 (PST) From: "Jayachandran C" To: "Steven J . Hill" , ralf@linux-mips.org cc: "Jayachandran C" , linux-mips@linux-mips.org Subject: [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." Date: Tue, 18 Dec 2012 15:20:03 +0530 Message-ID: <1355824203-18912-1-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-WSS-ID: 7CCEE40F3R022890145-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35304 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1689 Lines: 50 This reverts commit ff401e52100dcdc85e572d1ad376d3307b3fe28e. The commit causes a boot-time crash on Netlogic XLP boards. The crash is caused by the second part of the patch that changes build_get_ptep(), which seems to break mips64 TLB handling on r2 platforms. Signed-off-by: Jayachandran C --- arch/mips/mm/tlbex.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index e085e15..1a17a9b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -976,13 +976,6 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) #endif uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); - - if (cpu_has_mips_r2) { - uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT)); - uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT)); - return; - } - uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -1018,15 +1011,6 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { - if (cpu_has_mips_r2) { - /* PTE ptr offset is obtained from BadVAddr */ - UASM_i_MFC0(p, tmp, C0_BADVADDR); - UASM_i_LW(p, ptr, 0, ptr); - uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1); - uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1); - return; - } - /* * Bug workaround for the Nevada. It seems as if under certain * circumstances the move from cp0_context might produce a -- 1.7.9.5 From ralf@linux-mips.org Tue Dec 18 11:41:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Dec 2012 11:41:26 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37555 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6822190Ab2LRKlUc1Wc1 (ORCPT ); Tue, 18 Dec 2012 11:41:20 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qBIAfH37029004; Tue, 18 Dec 2012 11:41:17 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qBIAfEHa029003; Tue, 18 Dec 2012 11:41:14 +0100 Date: Tue, 18 Dec 2012 11:41:14 +0100 From: Ralf Baechle To: Alan Cox , linux-serial@vger.kernel.org Cc: linux-mips@linux-mips.org Subject: [PATCH] SERIAL: Remove RM9000 series serial driver. Message-ID: <20121218104114.GA28910@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35305 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4418 Lines: 145 Now that support for RM9000 and platforms based on it has been removed, remove the serial driver for it as well. It's really only been a quirk for an almost 8250 compatible UART anyway. Signed-off-by: Ralf Baechle drivers/tty/serial/8250/8250.c | 70 +---------------------------------------- drivers/tty/serial/8250/Kconfig | 9 ------ include/linux/serial_core.h | 1 - 3 files changed, 1 insertion(+), 79 deletions(-) diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c index 3ba4234..33711f5 100644 --- a/drivers/tty/serial/8250/8250.c +++ b/drivers/tty/serial/8250/8250.c @@ -239,13 +239,6 @@ static const struct serial8250_config uart_config[] = { .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, }, - [PORT_RM9000] = { - .name = "RM9000", - .fifo_size = 16, - .tx_loadsz = 16, - .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, - .flags = UART_CAP_FIFO, - }, [PORT_OCTEON] = { .name = "OCTEON", .fifo_size = 64, @@ -354,56 +347,6 @@ static void au_serial_dl_write(struct uart_8250_port *up, int value) #endif -#ifdef CONFIG_SERIAL_8250_RM9K - -static const u8 - regmap_in[8] = { - [UART_RX] = 0x00, - [UART_IER] = 0x0c, - [UART_IIR] = 0x14, - [UART_LCR] = 0x1c, - [UART_MCR] = 0x20, - [UART_LSR] = 0x24, - [UART_MSR] = 0x28, - [UART_SCR] = 0x2c - }, - regmap_out[8] = { - [UART_TX] = 0x04, - [UART_IER] = 0x0c, - [UART_FCR] = 0x18, - [UART_LCR] = 0x1c, - [UART_MCR] = 0x20, - [UART_LSR] = 0x24, - [UART_MSR] = 0x28, - [UART_SCR] = 0x2c - }; - -static unsigned int rm9k_serial_in(struct uart_port *p, int offset) -{ - offset = regmap_in[offset] << p->regshift; - return readl(p->membase + offset); -} - -static void rm9k_serial_out(struct uart_port *p, int offset, int value) -{ - offset = regmap_out[offset] << p->regshift; - writel(value, p->membase + offset); -} - -static int rm9k_serial_dl_read(struct uart_8250_port *up) -{ - return ((__raw_readl(up->port.membase + 0x10) << 8) | - (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff; -} - -static void rm9k_serial_dl_write(struct uart_8250_port *up, int value) -{ - __raw_writel(value, up->port.membase + 0x08); - __raw_writel(value >> 8, up->port.membase + 0x10); -} - -#endif - static unsigned int hub6_serial_in(struct uart_port *p, int offset) { offset = offset << p->regshift; @@ -480,15 +423,6 @@ static void set_io_from_upio(struct uart_port *p) p->serial_out = mem32_serial_out; break; -#ifdef CONFIG_SERIAL_8250_RM9K - case UPIO_RM9000: - p->serial_in = rm9k_serial_in; - p->serial_out = rm9k_serial_out; - up->dl_read = rm9k_serial_dl_read; - up->dl_write = rm9k_serial_dl_write; - break; -#endif - #ifdef CONFIG_MIPS_ALCHEMY case UPIO_AU: p->serial_in = au_serial_in; @@ -1294,9 +1228,7 @@ static void serial8250_start_tx(struct uart_port *port) unsigned char lsr; lsr = serial_in(up, UART_LSR); up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; - if ((port->type == PORT_RM9000) ? - (lsr & UART_LSR_THRE) : - (lsr & UART_LSR_TEMT)) + if (lsr & UART_LSR_TEMT) serial8250_tx_chars(up); } } diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index f3d283f..700fe12 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -249,15 +249,6 @@ config SERIAL_8250_ACORN system, say Y to this option. The driver can handle 1, 2, or 3 port cards. If unsure, say N. -config SERIAL_8250_RM9K - bool "Support for MIPS RM9xxx integrated serial port" - depends on SERIAL_8250 != n && SERIAL_RM9000 - select SERIAL_8250_SHARE_IRQ - help - Selecting this option will add support for the integrated serial - port hardware found on MIPS RM9122 and similar processors. - If unsure, say N. - config SERIAL_8250_FSL bool depends on SERIAL_8250_CONSOLE && PPC_UDBG_16550 diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 3c43022..3ba8e91 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -134,7 +134,6 @@ struct uart_port { #define UPIO_MEM32 (3) #define UPIO_AU (4) /* Au1x00 type IO */ #define UPIO_TSI (5) /* Tsi108/109 type IO */ -#define UPIO_RM9000 (6) /* RM9000 type IO */ unsigned int read_status_mask; /* driver specific */ unsigned int ignore_status_mask; /* driver specific */ From khali@linux-fr.org Tue Dec 18 13:08:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Dec 2012 13:08:37 +0100 (CET) Received: from zoneX.GCU-Squad.org ([194.213.125.0]:6834 "EHLO services.gcu-squad.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824761Ab2LRMIcUqxMw (ORCPT ); Tue, 18 Dec 2012 13:08:32 +0100 Received: from jdelvare.pck.nerim.net ([62.212.121.182] helo=endymion.delvare) by services.gcu-squad.org (GCU Mailer Daemon) with esmtpsa id 1TkvyG-0006jc-Pw (TLSv1:AES128-SHA:128) (envelope-from ) ; Tue, 18 Dec 2012 13:08:28 +0100 Date: Tue, 18 Dec 2012 13:08:23 +0100 From: Jean Delvare To: "Maciej W. Rozycki" , Matt Turner Cc: linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20121218130823.183a0322@endymion.delvare> In-Reply-To: References: <1313710991-3596-1-git-send-email-mattst88@gmail.com> <20110903103036.161616a5@endymion.delvare> <20111031105354.4b888e44@endymion.delvare> <20120110153834.531664db@endymion.delvare> <20120331082346.26cc95cb@endymion.delvare> X-Mailer: Claws Mail 3.7.10 (GTK+ 2.24.7; x86_64-suse-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 35306 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khali@linux-fr.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 597 Lines: 17 On Thu, 19 Jul 2012 22:01:08 +0100 (BST), Maciej W. Rozycki wrote: > On Sat, 30 Jun 2012, Matt Turner wrote: > > > I'm not going to have time to do this. :( > > > > I had another look at the code, and I'm not sure I really understand > > it well enough to address your concerns. > > I'll try then, as soon as I can. I'm giving up on this one, sorry. I've been waiting for an update for over a year, this is simply too much. I just don't get why this patch was ever submitted if there was no intent to actually get it included. This has been a waste of many people's time :( -- Jean Delvare From blogic@openwrt.org Tue Dec 18 13:11:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Dec 2012 13:11:41 +0100 (CET) Received: from nbd.name ([46.4.11.11]:37607 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823031Ab2LRMLkChIO- (ORCPT ); Tue, 18 Dec 2012 13:11:40 +0100 Message-ID: <50D05D02.1090405@openwrt.org> Date: Tue, 18 Dec 2012 13:09:38 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: Manuel Lauss CC: Linux-MIPS , Ralf Baechle , Zi Shen Lim , Jayachandran C Subject: Re: [PATCH v2] MIPS: perf: fix build failure in XLP perf support. References: <1355729179-5442-1-git-send-email-manuel.lauss@gmail.com> In-Reply-To: <1355729179-5442-1-git-send-email-manuel.lauss@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35307 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 464 Lines: 18 On 17/12/12 08:26, Manuel Lauss wrote: > Commit 4be3d2f3966b9f010bb997dcab25e7af489a841e ("MIPS: perf: Add > XLP support for hardware perf.") added UNSUPPORTED_PERF_EVENT_ID > which was removed a while back. > > Cc: Zi Shen Lim > Cc: Jayachandran C > Signed-off-by: Manuel Lauss > --- > Hi, my bad, this commit clashed with on in Ralf's tree... Acked-by: John Crispin ); Tue, 18 Dec 2012 19:27:31 +0100 Received: by mail-pb0-f54.google.com with SMTP id wz12so629353pbc.41 for ; Tue, 18 Dec 2012 10:27:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=aDsi/h8kZtCk7CsUzkeu4CUYxin+i3YM9zjP/O/udGM=; b=BUTH9R/uWU7qAJwg3ldHQl2wXPMSlSbQVKars+bE3hs+xROZSe9RBmRTrNMpPKhCUt 0FBRM1GXlPJNhU4K33p1bj76L/3sEir4h2PjUpWXosIGVYGkBmZNVZToUynh0MeTVZBu vPJESKba9CRqY/QC1liycpWl2H5iT6VgpJjQaj5db5HxcfbGQ0pDG7IUWD6cDDLh6xjr xoU8S71HliKmSWGMFL3a3e3EFBnORe967CIcgLSJgOl40370rBe/P345RmfUMxOgE3P/ oCqQYIQ+U+Nj9iYM0PzxN/cNdzbVQ28lqaD+dlC0BRWwpyW85XpUshNRgVmwYIdXpfpV 5LoA== X-Received: by 10.66.86.71 with SMTP id n7mr8903135paz.77.1355855244271; Tue, 18 Dec 2012 10:27:24 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ai8sm1547777pbd.14.2012.12.18.10.27.21 (version=SSLv3 cipher=OTHER); Tue, 18 Dec 2012 10:27:22 -0800 (PST) Message-ID: <50D0B588.2070906@gmail.com> Date: Tue, 18 Dec 2012 10:27:20 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Jayachandran C , ralf@linux-mips.org CC: "Steven J . Hill" , linux-mips@linux-mips.org Subject: Re: [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." References: <1355824203-18912-1-git-send-email-jchandra@broadcom.com> In-Reply-To: <1355824203-18912-1-git-send-email-jchandra@broadcom.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35308 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1984 Lines: 57 On 12/18/2012 01:50 AM, Jayachandran C wrote: > This reverts commit ff401e52100dcdc85e572d1ad376d3307b3fe28e. > > The commit causes a boot-time crash on Netlogic XLP boards. The > crash is caused by the second part of the patch that changes > build_get_ptep(), which seems to break mips64 TLB handling on r2 > platforms. > > Signed-off-by: Jayachandran C Acked-by: David Daney The offending patch is incorrect and should be reverted. It uses EXT and INS on 64-bit values. David Daney > --- > arch/mips/mm/tlbex.c | 16 ---------------- > 1 file changed, 16 deletions(-) > > diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c > index e085e15..1a17a9b 100644 > --- a/arch/mips/mm/tlbex.c > +++ b/arch/mips/mm/tlbex.c > @@ -976,13 +976,6 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) > #endif > uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ > uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); > - > - if (cpu_has_mips_r2) { > - uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT)); > - uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT)); > - return; > - } > - > uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ > uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); > uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ > @@ -1018,15 +1011,6 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) > > static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) > { > - if (cpu_has_mips_r2) { > - /* PTE ptr offset is obtained from BadVAddr */ > - UASM_i_MFC0(p, tmp, C0_BADVADDR); > - UASM_i_LW(p, ptr, 0, ptr); > - uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1); > - uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1); > - return; > - } > - > /* > * Bug workaround for the Nevada. It seems as if under certain > * circumstances the move from cp0_context might produce a > From sjhill@mips.com Tue Dec 18 19:39:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Dec 2012 19:39:34 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:51561 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817293Ab2LRSjdK8WDy convert rfc822-to-8bit (ORCPT ); Tue, 18 Dec 2012 19:39:33 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qBIIdPTv011295; Tue, 18 Dec 2012 10:39:25 -0800 X-WSS-ID: 0MF8P5O-01-06C-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.84]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2962D364669; Tue, 18 Dec 2012 10:39:24 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.02.0247.003; Tue, 18 Dec 2012 10:39:24 -0800 From: "Hill, Steven" To: David Daney , Jayachandran C , "ralf@linux-mips.org" CC: "linux-mips@linux-mips.org" Subject: RE: [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." Thread-Topic: [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." Thread-Index: AQHN3QUIS1qOm5BxXUKcek/ScPwLU5gfZrMA//98wuU= Date: Tue, 18 Dec 2012 18:39:23 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AB823@exchdb03.mips.com> References: <1355824203-18912-1-git-send-email-jchandra@broadcom.com>,<50D0B588.2070906@gmail.com> In-Reply-To: <50D0B588.2070906@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.4.41] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: aQhcYonXhPxqYobTiKZC9g== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35309 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 125 Lines: 3 I would ask that we hold off on the revert patch as I will have the 64-bit fix today in the next 2 hours. Thank you. -Steve From sjhill@mips.com Wed Dec 19 06:18:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 19 Dec 2012 06:18:53 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:39397 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822664Ab2LSFSs5Amzg (ORCPT ); Wed, 19 Dec 2012 06:18:48 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id qBJ5Id3q023289; Tue, 18 Dec 2012 21:18:39 -0800 X-WSS-ID: 0MF9IR0-01-0GB-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.67]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2ED2D36465A; Tue, 18 Dec 2012 21:18:36 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([fe80::2897:a30d:a923:303%16]) with mapi id 14.01.0270.001; Tue, 18 Dec 2012 21:18:35 -0800 From: "Hill, Steven" To: Jayachandran C , "ralf@linux-mips.org" CC: "linux-mips@linux-mips.org" Subject: RE: [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." Thread-Topic: [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." Thread-Index: AQHN3QUIS1qOm5BxXUKcek/ScPwLU5gflgVP Date: Wed, 19 Dec 2012 05:18:35 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146AB865@exchdb03.mips.com> References: <1355824203-18912-1-git-send-email-jchandra@broadcom.com> In-Reply-To: <1355824203-18912-1-git-send-email-jchandra@broadcom.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: Ch8NKIBZiKAadUBu4WQ7jw== Content-Type: multipart/mixed; boundary="_002_31E06A9FC96CEC488B43B19E2957C1B801146AB865exchdb03mipsc_" MIME-Version: 1.0 X-archive-position: 35310 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6676 Lines: 99 --_002_31E06A9FC96CEC488B43B19E2957C1B801146AB865exchdb03mipsc_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable JC,=0A= =0A= Can you try to apply this patch on top of the "MIPS: Optimise TLB handlers = for MIPS32/64 R2 cores." patch and let me know of the results. Thanks.=0A= =0A= -Steve= --_002_31E06A9FC96CEC488B43B19E2957C1B801146AB865exchdb03mipsc_ Content-Type: text/x-patch; name="fix-optimise-tlb-for-mips64r2.patch" Content-Description: fix-optimise-tlb-for-mips64r2.patch Content-Disposition: attachment; filename="fix-optimise-tlb-for-mips64r2.patch"; size=4333; creation-date="Wed, 19 Dec 2012 05:16:58 GMT"; modification-date="Wed, 19 Dec 2012 05:16:58 GMT" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2FyY2gvbWlwcy9pbmNsdWRlL2FzbS9pbnN0LmggYi9hcmNoL21pcHMvaW5j bHVkZS9hc20vaW5zdC5oCmluZGV4IDUzNTQyZTNjLi43NjFmYTE4IDEwMDY0NAotLS0gYS9hcmNo L21pcHMvaW5jbHVkZS9hc20vaW5zdC5oCisrKyBiL2FyY2gvbWlwcy9pbmNsdWRlL2FzbS9pbnN0 LmgKQEAgLTg5Myw3ICs4OTMsNyBAQCBlbnVtIG1tX21ham9yX29wIHsKIAltbV9wb29sMzJiX29w LCBtbV9wb29sMTZiX29wLCBtbV9saHUxNl9vcCwgbW1fYW5kaTE2X29wLAogCW1tX2FkZGl1MzJf b3AsIG1tX2xodTMyX29wLCBtbV9zaDMyX29wLCBtbV9saDMyX29wLAogCW1tX3Bvb2wzMmlfb3As IG1tX3Bvb2wxNmNfb3AsIG1tX2x3c3AxNl9vcCwgbW1fcG9vbDE2ZF9vcCwKLQltbV9vcmkzMl9v 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IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Wed, 19 Dec 2012 01:01:41 -0800 Received: from jayachandranc.netlogicmicro.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2C48340FE6; Wed, 19 Dec 2012 01:01:56 -0800 (PST) Date: Wed, 19 Dec 2012 14:32:29 +0530 From: "Jayachandran C." To: "Hill, Steven" cc: "ralf@linux-mips.org" , "linux-mips@linux-mips.org" Subject: Re: [PATCH] Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." Message-ID: <20121219090228.GC3423@jayachandranc.netlogicmicro.com> References: <1355824203-18912-1-git-send-email-jchandra@broadcom.com> <31E06A9FC96CEC488B43B19E2957C1B801146AB865@exchdb03.mips.com> MIME-Version: 1.0 In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B801146AB865@exchdb03.mips.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-WSS-ID: 7CCF5E7D3R023714115-11-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit X-archive-position: 35311 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 499 Lines: 14 On Wed, Dec 19, 2012 at 05:18:35AM +0000, Hill, Steven wrote: > JC, > > Can you try to apply this patch on top of the "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." patch and let me know of the results. Thanks. This changes does not fix the issue. The patch did not apply cleanly since it had micro-mips changes that is not in the linux-mips tree, so I had to do some of the changes manually. I'll send you a dump of the old and new TLB handlers so that you can debug this further. JC. From aaro.koskinen@iki.fi Sat Dec 22 13:28:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 22 Dec 2012 13:28:06 +0100 (CET) Received: from filtteri6.pp.htv.fi ([213.243.153.189]:60332 "EHLO filtteri6.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823098Ab2LVM2DVLKUr (ORCPT ); Sat, 22 Dec 2012 13:28:03 +0100 Received: from localhost (localhost [127.0.0.1]) by filtteri6.pp.htv.fi (Postfix) with ESMTP id 45A8956E72F; Sat, 22 Dec 2012 14:28:02 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp4.welho.com ([213.243.153.38]) by localhost (filtteri6.pp.htv.fi [213.243.153.189]) (amavisd-new, port 10024) with ESMTP id XwfwLSeH1c6o; Sat, 22 Dec 2012 14:28:01 +0200 (EET) Received: from musicnaut.iki.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp4.welho.com (Postfix) with SMTP id 2780A5BC005; Sat, 22 Dec 2012 14:28:00 +0200 (EET) Received: by musicnaut.iki.fi (sSMTP sendmail emulation); Sat, 22 Dec 2012 14:27:57 +0200 Date: Sat, 22 Dec 2012 14:27:57 +0200 From: Aaro Koskinen To: "Kirill A. Shutemov" , linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: linux-mips@linux-mips.org Subject: 3.8-rc1 build failure with MIPS/SPARSEMEM Message-ID: <20121222122757.GB6847@blackmetal.musicnaut.iki.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35312 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 43200 Lines: 1712 Hi, It looks like commit 816422ad76474fed8052b6f7b905a054d082e59a (asm-generic, mm: pgtable: consolidate zero page helpers) broke MIPS/SPARSEMEM build in 3.8-rc1: CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h Checking missing-syscalls for N32 CC arch/mips/kernel/asm-offsets.s In file included from /home/aaro/git/linux/arch/mips/include/asm/pgtable.h:388:0, from include/linux/mm.h:44, from arch/mips/kernel/asm-offsets.c:14: include/asm-generic/pgtable.h: In function 'my_zero_pfn': include/asm-generic/pgtable.h:462:9: error: implicit declaration of function 'page_to_section' [-Werror=implicit-function-declaration] In file included from arch/mips/kernel/asm-offsets.c:14:0: include/linux/mm.h: At top level: include/linux/mm.h:708:29: error: conflicting types for 'page_to_section' In file included from /home/aaro/git/linux/arch/mips/include/asm/pgtable.h:388:0, from include/linux/mm.h:44, from arch/mips/kernel/asm-offsets.c:14: include/asm-generic/pgtable.h:462:9: note: previous implicit declaration of 'page_to_section' was here cc1: some warnings being treated as errors make[1]: *** [arch/mips/kernel/asm-offsets.s] Error 1 make: *** [archprepare] Error 2 Reverting the patch helps. My test config is below, A. # # Automatically generated file; DO NOT EDIT. # Linux/mips 3.8.0-rc1 Kernel Configuration # CONFIG_MIPS=y # # Machine selection # # CONFIG_MIPS_ALCHEMY is not set # CONFIG_AR7 is not set # CONFIG_ATH79 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MACH_JZ4740 is not set # CONFIG_LANTIQ is not set # CONFIG_LASAT is not set CONFIG_MACH_LOONGSON=y # CONFIG_MACH_LOONGSON1 is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD3 is not set # CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set # CONFIG_NXP_STB220 is not set # CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_MACH_TX39XX is not set # CONFIG_MACH_TX49XX is not set # CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set # CONFIG_NLM_XLR_BOARD is not set # CONFIG_NLM_XLP_BOARD is not set # CONFIG_ALCHEMY_GPIO_INDIRECT is not set # CONFIG_LEMOTE_FULOONG2E is not set CONFIG_LEMOTE_MACH2F=y CONFIG_CS5536=y CONFIG_CS5536_MFGPT=y CONFIG_LOONGSON_SUSPEND=y CONFIG_LOONGSON_UART_BASE=y CONFIG_LOONGSON_MC146818=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_DMA_NONCOHERENT=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_SYS_HAS_EARLY_PRINTK=y CONFIG_I8259=y # CONFIG_MIPS_MACHINE is not set # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y CONFIG_ISA_DMA_API=y CONFIG_GENERIC_GPIO=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_HUGETLBFS=y # CONFIG_MIPS_HUGE_TLB_SUPPORT is not set CONFIG_IRQ_CPU=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # CONFIG_CPU_LOONGSON2F=y CONFIG_CPU_NOP_WORKAROUNDS=y CONFIG_CPU_JUMP_WORKAROUNDS=y CONFIG_CPU_LOONGSON2F_WORKAROUNDS=y CONFIG_SYS_SUPPORTS_ZBOOT=y CONFIG_CPU_LOONGSON2=y CONFIG_SYS_HAS_CPU_LOONGSON2F=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_CPUFREQ=y CONFIG_CPU_SUPPORTS_ADDRWINCFG=y CONFIG_CPU_SUPPORTS_HUGEPAGES=y CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED=y # # Kernel type # # CONFIG_32BIT is not set CONFIG_64BIT=y CONFIG_PAGE_SIZE_16KB=y # CONFIG_PAGE_SIZE_64KB is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_BOARD_SCACHE=y CONFIG_CPU_GENERIC_DUMP_TLB=y CONFIG_CPU_R4K_FPU=y CONFIG_CPU_R4K_CACHE_TLB=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_CPU_HAS_WB=y CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_STATIC=y CONFIG_HAVE_MEMBLOCK=y CONFIG_HAVE_MEMBLOCK_NODE_MAP=y CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_COMPACTION=y CONFIG_MIGRATION=y CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # CONFIG_TRANSPARENT_HUGEPAGE is not set CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_NEED_PER_CPU_KM=y # CONFIG_CLEANCACHE is not set # CONFIG_FRONTSWAP is not set # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set CONFIG_HZ_250=y # CONFIG_HZ_256 is not set # CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_HZ=250 # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y CONFIG_KEXEC=y # CONFIG_CRASH_DUMP is not set # CONFIG_SECCOMP is not set CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_HAVE_IRQ_WORK=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_EXTABLE_SORT=y # # General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_CROSS_COMPILE="" CONFIG_LOCALVERSION="-lemote" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_LZO=y # CONFIG_KERNEL_GZIP is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_LZMA=y # CONFIG_KERNEL_LZO is not set CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_FHANDLE is not set # CONFIG_AUDIT is not set CONFIG_HAVE_GENERIC_HARDIRQS=y # # IRQ subsystem # CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CMOS_UPDATE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y # CONFIG_TASKSTATS is not set # # RCU Subsystem # CONFIG_TINY_PREEMPT_RCU=y CONFIG_PREEMPT_RCU=y # CONFIG_TREE_RCU_TRACE is not set # CONFIG_RCU_BOOST is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=15 # CONFIG_CGROUPS is not set # CONFIG_CHECKPOINT_RESTORE is not set # CONFIG_NAMESPACES is not set CONFIG_UIDGID_CONVERTED=y # CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_RD_GZIP is not set # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set # CONFIG_RD_XZ is not set # CONFIG_RD_LZO is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_PROFILING=y CONFIG_OPROFILE=m CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_HAVE_SYSCALL_WRAPPERS=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_HAVE_CLK=y CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_MODULES_USE_ELF_REL=y # # GCOV-based kernel profiling # CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set CONFIG_BLOCK=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSGLIB is not set # CONFIG_BLK_DEV_INTEGRITY is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_FREEZER=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set # CONFIG_PCI_STUB is not set # CONFIG_PCI_IOV is not set # CONFIG_PCI_PRI is not set # CONFIG_PCI_PASID is not set # CONFIG_PCIEPORTBUS is not set CONFIG_ISA=y CONFIG_MMU=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_RAPIDIO is not set # # Executable file formats # CONFIG_BINFMT_ELF=y CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y # CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_COREDUMP=y CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y CONFIG_BINFMT_ELF32=y # # Power management options # CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y CONFIG_PM_STD_PARTITION="/dev/hda3" CONFIG_PM_SLEEP=y # CONFIG_PM_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM_RUNTIME=y CONFIG_PM=y # CONFIG_PM_DEBUG is not set CONFIG_PM_CLK=y CONFIG_MIPS_EXTERNAL_TIMER=y CONFIG_MIPS_CPUFREQ=y # # CPU Frequency scaling # # # CPU Frequency scaling # CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_TABLE=y # CONFIG_CPU_FREQ_STAT is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_GOV_USERSPACE is not set CONFIG_CPU_FREQ_GOV_ONDEMAND=y # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set # # CPUFreq processor drivers # CONFIG_LOONGSON2_CPUFREQ=y CONFIG_NET=y # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y # CONFIG_UNIX_DIAG is not set # CONFIG_XFRM_USER is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set # CONFIG_IP_PNP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE_DEMUX is not set # CONFIG_ARPD is not set # CONFIG_SYN_COOKIES is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETWORK_PHY_TIMESTAMPING is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_L2TP is not set # CONFIG_BRIDGE is not set CONFIG_HAVE_NET_DSA=y # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set # CONFIG_BATMAN_ADV is not set # CONFIG_OPENVSWITCH is not set CONFIG_BQL=y # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set # CONFIG_WIRELESS is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set # CONFIG_NFC is not set # # Device Drivers # # # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y # CONFIG_DEVTMPFS_MOUNT is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_GENERIC_CPU_DEVICES is not set # CONFIG_DMA_SHARED_BUFFER is not set # # Bus devices # # CONFIG_CONNECTOR is not set # CONFIG_MTD is not set # CONFIG_PARPORT is not set # CONFIG_PNP is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_XD is not set # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_NVME is not set # CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set # CONFIG_BLK_DEV_RBD is not set # # Misc devices # # CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_ATMEL_PWM is not set # CONFIG_PHANTOM is not set # CONFIG_INTEL_MID_PTI is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set # CONFIG_PCH_PHUB is not set # CONFIG_C2PORT is not set # # EEPROM support # # CONFIG_EEPROM_93CX6 is not set # CONFIG_CB710_CORE is not set # # Texas Instruments shared transport line discipline # # CONFIG_TI_ST is not set # # Altera FPGA firmware download module # CONFIG_HAVE_IDE=y CONFIG_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_XFER_MODE=y CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set CONFIG_IDE_GD=y CONFIG_IDE_GD_ATA=y # CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set CONFIG_IDE_TASK_IOCTL=y CONFIG_IDE_PROC_FS=y # # IDE chipset support/bugfixes # # CONFIG_IDE_GENERIC is not set # CONFIG_BLK_DEV_PLATFORM is not set CONFIG_BLK_DEV_IDEDMA_SFF=y # # PCI IDE chipsets support # CONFIG_BLK_DEV_IDEPCI=y # CONFIG_IDEPCI_PCIBUS_ORDER is not set # CONFIG_BLK_DEV_GENERIC is not set # CONFIG_BLK_DEV_OPTI621 is not set CONFIG_BLK_DEV_IDEDMA_PCI=y # CONFIG_BLK_DEV_AEC62XX is not set # CONFIG_BLK_DEV_ALI15X3 is not set CONFIG_BLK_DEV_AMD74XX=y # CONFIG_BLK_DEV_CMD64X is not set # CONFIG_BLK_DEV_TRIFLEX is not set # CONFIG_BLK_DEV_CS5520 is not set # CONFIG_BLK_DEV_CS5530 is not set # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_JMICRON is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set # CONFIG_BLK_DEV_IT8172 is not set # CONFIG_BLK_DEV_IT8213 is not set # CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set # CONFIG_BLK_DEV_SVWKS is not set # CONFIG_BLK_DEV_SIIMAGE is not set # CONFIG_BLK_DEV_SLC90E66 is not set # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set # CONFIG_BLK_DEV_TC86C001 is not set # # Other IDE chipsets support # # # Note: most of these also require special kernel boot parameters # # CONFIG_BLK_DEV_4DRIVES is not set # CONFIG_BLK_DEV_ALI14XX is not set # CONFIG_BLK_DEV_DTC2278 is not set # CONFIG_BLK_DEV_HT6560B is not set # CONFIG_BLK_DEV_QD65XX is not set # CONFIG_BLK_DEV_UMC8672 is not set CONFIG_BLK_DEV_IDEDMA=y # # SCSI device support # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set # # SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # # CONFIG_FIREWIRE is not set # CONFIG_FIREWIRE_NOSY is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set CONFIG_MII=y # CONFIG_NET_TEAM is not set # CONFIG_MACVLAN is not set # CONFIG_VXLAN is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set # CONFIG_ARCNET is not set # # CAIF transport drivers # # # Distributed Switch Architecture drivers # # CONFIG_NET_DSA_MV88E6XXX is not set # CONFIG_NET_DSA_MV88E6060 is not set # CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set # CONFIG_NET_DSA_MV88E6131 is not set # CONFIG_NET_DSA_MV88E6123_61_65 is not set CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_ADAPTEC is not set # CONFIG_NET_VENDOR_ALTEON is not set # CONFIG_NET_VENDOR_AMD is not set # CONFIG_NET_VENDOR_ATHEROS is not set CONFIG_NET_CADENCE=y # CONFIG_ARM_AT91_ETHER is not set # CONFIG_MACB is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_CALXEDA_XGMAC is not set # CONFIG_NET_VENDOR_CHELSIO is not set # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_CISCO is not set # CONFIG_DM9000 is not set # CONFIG_DNET is not set # CONFIG_NET_VENDOR_DEC is not set # CONFIG_NET_VENDOR_DLINK is not set # CONFIG_NET_VENDOR_EMULEX is not set # CONFIG_NET_VENDOR_EXAR is not set # CONFIG_NET_VENDOR_FUJITSU is not set # CONFIG_NET_VENDOR_HP is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_IP1000 is not set # CONFIG_JME is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MYRI is not set # CONFIG_FEALNX is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NVIDIA is not set # CONFIG_NET_VENDOR_OKI is not set # CONFIG_ETHOC is not set # CONFIG_NET_PACKET_ENGINE is not set # CONFIG_NET_VENDOR_QLOGIC is not set # CONFIG_NET_VENDOR_RACAL is not set CONFIG_NET_VENDOR_REALTEK=y # CONFIG_8139CP is not set # CONFIG_8139TOO is not set CONFIG_R8169=y # CONFIG_NET_VENDOR_RDC is not set # CONFIG_NET_VENDOR_SEEQ is not set # CONFIG_NET_VENDOR_SILAN is not set # CONFIG_NET_VENDOR_SIS is not set # CONFIG_SFC is not set # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_SUN is not set # CONFIG_NET_VENDOR_TEHUTI is not set # CONFIG_NET_VENDOR_TI is not set # CONFIG_NET_VENDOR_TOSHIBA is not set # CONFIG_NET_VENDOR_VIA is not set CONFIG_NET_VENDOR_WIZNET=y # CONFIG_WIZNET_W5100 is not set # CONFIG_WIZNET_W5300 is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PHYLIB is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # # USB Network Adapters # # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set # CONFIG_USB_IPHETH is not set # CONFIG_WLAN is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers # # CONFIG_WAN is not set # CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # # Input device support # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set # CONFIG_INPUT_SPARSEKMAP is not set # CONFIG_INPUT_MATRIXKMAP is not set # # Userland interfaces # # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set # # Hardware I/O ports # # CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 CONFIG_SERIAL_NONSTANDARD=y # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_SYNCLINK is not set # CONFIG_SYNCLINKMP is not set # CONFIG_SYNCLINK_GT is not set # CONFIG_NOZOMI is not set # CONFIG_ISI is not set # CONFIG_N_HDLC is not set # CONFIG_N_GSM is not set # CONFIG_TRACE_SINK is not set CONFIG_DEVKMEM=y # CONFIG_STALDRV is not set # # Serial drivers # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_SERIAL_8250_PCI is not set CONFIG_SERIAL_8250_NR_UARTS=16 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_FOURPORT=y # CONFIG_SERIAL_8250_ACCENT is not set # CONFIG_SERIAL_8250_BOCA is not set # CONFIG_SERIAL_8250_EXAR_ST16C554 is not set # CONFIG_SERIAL_8250_HUB6 is not set # CONFIG_SERIAL_8250_SHARE_IRQ is not set # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set # # Non-8250 serial port support # # CONFIG_SERIAL_MFD_HSU is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_TIMBERDALE is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_PCH_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_TTY_PRINTK is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_HW_RANDOM_ATMEL is not set # CONFIG_HW_RANDOM_EXYNOS is not set CONFIG_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_I2C is not set # CONFIG_SPI is not set # CONFIG_HSI is not set # # PPS support # # CONFIG_PPS is not set # # PPS generators support # # # PTP clock support # # CONFIG_PTP_1588_CLOCK is not set # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # # CONFIG_PTP_1588_CLOCK_PCH is not set CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set # CONFIG_GPIO_SYSFS is not set # # Memory mapped GPIO drivers: # # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_TS5500 is not set # CONFIG_GPIO_VX855 is not set # # I2C GPIO expanders: # # # PCI GPIO expanders: # # CONFIG_GPIO_BT8XX is not set # CONFIG_GPIO_AMD8111 is not set # CONFIG_GPIO_ML_IOH is not set # CONFIG_GPIO_RDC321X is not set # # SPI GPIO expanders: # # # AC97 GPIO expanders: # # # MODULbus GPIO expanders: # # # USB GPIO expanders: # # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_POWER_AVS is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # # CONFIG_SSB is not set CONFIG_BCMA_POSSIBLE=y # # Broadcom specific AMBA # # CONFIG_BCMA is not set # # Multifunction device drivers # # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_RTSX_PCI is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_TIMBERDALE is not set # CONFIG_LPC_SCH is not set # CONFIG_LPC_ICH is not set # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_VX855 is not set # CONFIG_MFD_VIPERBOARD is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # # CONFIG_VGA_ARB is not set # CONFIG_DRM is not set # CONFIG_STUB_POULSBO is not set # CONFIG_VGASTATE is not set CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y # CONFIG_FB_DDC is not set CONFIG_FB_BOOT_VESA_SUPPORT=y CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set # CONFIG_FB_SYS_FILLRECT is not set # CONFIG_FB_SYS_COPYAREA is not set # CONFIG_FB_SYS_IMAGEBLIT is not set # CONFIG_FB_FOREIGN_ENDIAN is not set # CONFIG_FB_SYS_FOPS is not set # CONFIG_FB_WMT_GE_ROPS is not set # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_I740 is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON is not set # CONFIG_FB_ATY128 is not set # CONFIG_FB_ATY is not set # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set CONFIG_FB_SIS=y CONFIG_FB_SIS_300=y CONFIG_FB_SIS_315=y # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set # CONFIG_FB_VT8623 is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set # CONFIG_FB_SMSCUFX is not set # CONFIG_FB_UDL is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set # CONFIG_FB_AUO_K190X is not set # CONFIG_EXYNOS_VIDEO is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_LOGO=y CONFIG_LOGO_LINUX_MONO=y # CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_LOGO_LINUX_CLUT224 is not set # CONFIG_SOUND is not set # # HID support # CONFIG_HID=y # CONFIG_HIDRAW is not set # CONFIG_UHID is not set CONFIG_HID_GENERIC=y # # Special HID drivers # # CONFIG_HID_A4TECH is not set # CONFIG_HID_ACRUX is not set # CONFIG_HID_APPLE is not set # CONFIG_HID_AUREAL is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set # CONFIG_HID_CYPRESS is not set # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EMS_FF is not set # CONFIG_HID_EZKEY is not set # CONFIG_HID_HOLTEK is not set # CONFIG_HID_KEYTOUCH is not set # CONFIG_HID_KYE is not set # CONFIG_HID_UCLOGIC is not set # CONFIG_HID_WALTOP is not set # CONFIG_HID_GYRATION is not set # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LENOVO_TPKBD is not set # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set # CONFIG_HID_MULTITOUCH is not set # CONFIG_HID_NTRIG is not set # CONFIG_HID_ORTEK is not set # CONFIG_HID_PANTHERLORD is not set # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set # CONFIG_HID_SAMSUNG is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SPEEDLINK is not set # CONFIG_HID_SUNPLUS is not set # CONFIG_HID_GREENASIA is not set # CONFIG_HID_SMARTJOYPLUS is not set # CONFIG_HID_TIVO is not set # CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set # CONFIG_HID_ZEROPLUS is not set # CONFIG_HID_ZYDACRON is not set # CONFIG_HID_SENSOR_HUB is not set # # USB HID support # CONFIG_USB_HID=y # CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB_ARCH_HAS_XHCI=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_SUSPEND is not set CONFIG_USB_OTG_WHITELIST=y # CONFIG_USB_OTG_BLACKLIST_HUB is not set # CONFIG_USB_MON is not set # CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_XHCI_HCD is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_PCI=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_HCD_PLATFORM is not set # CONFIG_USB_EHCI_HCD_PLATFORM is not set # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_CHIPIDEA is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set # CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_REALTEK is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_STORAGE_ENE_UB6250 is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # # USB port drivers # # CONFIG_USB_SERIAL is not set # # USB Miscellaneous drivers # # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_YUREX is not set # CONFIG_USB_EZUSB_FX2 is not set # # USB Physical Layer drivers # # CONFIG_USB_RCAR_PHY is not set # CONFIG_USB_GADGET is not set # # OTG and related infrastructure # # CONFIG_USB_GPIO_VBUS is not set # CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # # Virtio drivers # # CONFIG_VIRTIO_PCI is not set # CONFIG_VIRTIO_MMIO is not set # # Microsoft Hyper-V guest support # # CONFIG_STAGING is not set # # Hardware Spinlock drivers # # CONFIG_IOMMU_SUPPORT is not set # # Remoteproc drivers (EXPERIMENTAL) # # CONFIG_STE_MODEM_RPROC is not set # # Rpmsg drivers (EXPERIMENTAL) # # CONFIG_VIRT_DRIVERS is not set # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set # CONFIG_IIO is not set # CONFIG_VME_BUS is not set # CONFIG_PWM is not set # CONFIG_IPACK_BUS is not set # # Firmware Drivers # # CONFIG_FIRMWARE_MEMMAP is not set # # File systems # # CONFIG_EXT2_FS is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y # CONFIG_EXT4_FS is not set # CONFIG_EXT4_FS_POSIX_ACL is not set # CONFIG_EXT4_FS_SECURITY is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set # CONFIG_QUOTACTL is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set # # Caches # # CONFIG_FSCACHE is not set # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # # CONFIG_MSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLBFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set # CONFIG_MISC_FILESYSTEMS is not set # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" # CONFIG_NLS_CODEPAGE_437 is not set # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_852 is not set # CONFIG_NLS_CODEPAGE_855 is not set # CONFIG_NLS_CODEPAGE_857 is not set # CONFIG_NLS_CODEPAGE_860 is not set # CONFIG_NLS_CODEPAGE_861 is not set # CONFIG_NLS_CODEPAGE_862 is not set # CONFIG_NLS_CODEPAGE_863 is not set # CONFIG_NLS_CODEPAGE_864 is not set # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set # CONFIG_NLS_CODEPAGE_869 is not set # CONFIG_NLS_CODEPAGE_936 is not set # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set # CONFIG_NLS_CODEPAGE_949 is not set # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_ASCII is not set # CONFIG_NLS_ISO8859_1 is not set # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_5 is not set # CONFIG_NLS_ISO8859_6 is not set # CONFIG_NLS_ISO8859_7 is not set # CONFIG_NLS_ISO8859_9 is not set # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set # CONFIG_NLS_ISO8859_15 is not set # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_MAC_ROMAN is not set # CONFIG_NLS_MAC_CELTIC is not set # CONFIG_NLS_MAC_CENTEURO is not set # CONFIG_NLS_MAC_CROATIAN is not set # CONFIG_NLS_MAC_CYRILLIC is not set # CONFIG_NLS_MAC_GAELIC is not set # CONFIG_NLS_MAC_GREEK is not set # CONFIG_NLS_MAC_ICELAND is not set # CONFIG_NLS_MAC_INUIT is not set # CONFIG_NLS_MAC_ROMANIAN is not set # CONFIG_NLS_MAC_TURKISH is not set # CONFIG_NLS_UTF8 is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_PRINTK_TIME=y CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set # CONFIG_LOCKUP_DETECTOR is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_LOCK_ALLOC is not set # CONFIG_PROVE_LOCKING is not set # CONFIG_PROVE_RCU_DELAY is not set # CONFIG_SPARSE_RCU_POINTER is not set # CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_ATOMIC_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_KOBJECT is not set # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_TEST_LIST_SORT is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_DEBUG_CREDENTIALS is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_TRACE is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_RBTREE_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set # CONFIG_TEST_KSTRTOX is not set CONFIG_EARLY_PRINTK=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyS0,115200 console=tty" CONFIG_CMDLINE_OVERRIDE=y # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_RUNTIME_DEBUG is not set # CONFIG_DEBUG_ZBOOT is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_RNG=m CONFIG_CRYPTO_RNG2=m # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_MANAGER2 is not set # CONFIG_CRYPTO_USER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set # # Authenticated Encryption with Associated Data # # CONFIG_CRYPTO_CCM is not set # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_SEQIV is not set # # Block modes # # CONFIG_CRYPTO_CBC is not set # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set # CONFIG_CRYPTO_ECB is not set # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # # Hash modes # # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_VMAC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set # CONFIG_CRYPTO_MD5 is not set # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # # Ciphers # CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # # Compression # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # # Random Number Generation # CONFIG_CRYPTO_ANSI_CPRNG=m # CONFIG_CRYPTO_USER_API_HASH is not set # CONFIG_CRYPTO_USER_API_SKCIPHER is not set CONFIG_CRYPTO_HW=y # CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IO=y CONFIG_PERCPU_RWSEM=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set # CONFIG_CRC8 is not set CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y # CONFIG_XZ_DEC is not set # CONFIG_XZ_DEC_BCJ is not set CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_DQL=y CONFIG_NLATTR=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y # CONFIG_AVERAGE is not set # CONFIG_CORDIC is not set # CONFIG_DDR is not set From kirill.shutemov@linux.intel.com Sat Dec 22 14:09:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 22 Dec 2012 14:09:53 +0100 (CET) Received: from mga03.intel.com ([143.182.124.21]:49730 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823098Ab2LVNJwJwPKV (ORCPT ); Sat, 22 Dec 2012 14:09:52 +0100 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 22 Dec 2012 05:09:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,336,1355126400"; d="asc'?scan'208";a="235561035" Received: from blue.fi.intel.com ([10.237.72.156]) by azsmga001.ch.intel.com with ESMTP; 22 Dec 2012 05:09:36 -0800 Received: by blue.fi.intel.com (Postfix, from userid 1000) id 18EA8E0073; Sat, 22 Dec 2012 15:10:23 +0200 (EET) Date: Sat, 22 Dec 2012 15:10:23 +0200 From: "Kirill A. Shutemov" To: Aaro Koskinen Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-mips@linux-mips.org Subject: Re: 3.8-rc1 build failure with MIPS/SPARSEMEM Message-ID: <20121222131022.GA16364@otc-wbsnb-06> References: <20121222122757.GB6847@blackmetal.musicnaut.iki.fi> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="a8Wt8u1KmwUX3Y2C" Content-Disposition: inline In-Reply-To: <20121222122757.GB6847@blackmetal.musicnaut.iki.fi> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35313 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kirill.shutemov@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1460 Lines: 44 --a8Wt8u1KmwUX3Y2C Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Dec 22, 2012 at 02:27:57PM +0200, Aaro Koskinen wrote: > Hi, >=20 > It looks like commit 816422ad76474fed8052b6f7b905a054d082e59a > (asm-generic, mm: pgtable: consolidate zero page helpers) broke > MIPS/SPARSEMEM build in 3.8-rc1: Could you try this: http://permalink.gmane.org/gmane.linux.kernel/1410981 ? --=20 Kirill A. Shutemov --a8Wt8u1KmwUX3Y2C Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBAgAGBQJQ1bE+AAoJEAd+omnVudOMApcP/1uIiUWCXP8Lym3KcmCKmK1j pqU/ALq5X8t6SAcZTOMF7xroFabeSGZ5mXTWFJ26fgMY95LkddsFzcvO1zgl5BFp OBkT4shs/M/cDvEcetOO0lBExAkKngOXQGd8ZATMIlXaIyZ03dJ3m/A0chsfRdwE COPgc5ixTTwGEhAcMy1r6MBokO+pFc8ODlUGWNHOvgsW4/YKwjgzGZ1rT6vtv0rN ah7cWeJ5PTD1HupHZSOh1P91pGwQbV1TWML+hEEJlbeLxFW47yx9vNkdjwoi1kvm PSjHZOs1SeMQxpGP9icE/ZH1tnCeQoyIk8SD90xusV+5YRktPw8BTpdErLT7z03P ebAKfQgixSMhEawHSe9wW6DMSRt5+IFTZlz0lYrHSfSVb2k0SbyN2oFepmih0q98 tBI8I63QpqlVlYrAFktURnNg794sWXNtsxJ4yaXBwrw5CfxFM3YalPHJOmPgB/QX MiMBKkMVmFh+2P+Imf3w/oMqDJcg5vNjjoGG75LoIn1LnZELmc1IDoe+igof1Uac sr7SkycpcSBshtggTvxvxO5EEgmZqNck+t4ixwQKbYOnge7SBNPzqZaa9XePeiyU 574fk+hUnQSjk1WpWzaKPmvuLnNibF6WMSBYMjbeg0sbdNLOpf0ZTp1bH5WLbmfO nVYpX2z0UbR/s6MCw/vD =FFgu -----END PGP SIGNATURE----- --a8Wt8u1KmwUX3Y2C-- From aaro.koskinen@iki.fi Sat Dec 22 14:31:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 22 Dec 2012 14:31:48 +0100 (CET) Received: from filtteri6.pp.htv.fi ([213.243.153.189]:49945 "EHLO filtteri6.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823113Ab2LVNbrmu39A (ORCPT ); Sat, 22 Dec 2012 14:31:47 +0100 Received: from localhost (localhost [127.0.0.1]) by filtteri6.pp.htv.fi (Postfix) with ESMTP id 19D9256E7DF; Sat, 22 Dec 2012 15:31:47 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp5.welho.com ([213.243.153.39]) by localhost (filtteri6.pp.htv.fi [213.243.153.189]) (amavisd-new, port 10024) with ESMTP id AxQN2NjjUBP7; Sat, 22 Dec 2012 15:31:46 +0200 (EET) Received: from musicnaut.iki.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp5.welho.com (Postfix) with SMTP id AFB955BC004; Sat, 22 Dec 2012 15:31:45 +0200 (EET) Received: by musicnaut.iki.fi (sSMTP sendmail emulation); Sat, 22 Dec 2012 15:31:45 +0200 Date: Sat, 22 Dec 2012 15:31:45 +0200 From: Aaro Koskinen To: "Kirill A. Shutemov" Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-mips@linux-mips.org Subject: Re: 3.8-rc1 build failure with MIPS/SPARSEMEM Message-ID: <20121222133145.GC6847@blackmetal.musicnaut.iki.fi> References: <20121222122757.GB6847@blackmetal.musicnaut.iki.fi> <20121222131022.GA16364@otc-wbsnb-06> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20121222131022.GA16364@otc-wbsnb-06> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35314 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 681 Lines: 22 Hi, On Sat, Dec 22, 2012 at 03:10:23PM +0200, Kirill A. Shutemov wrote: > On Sat, Dec 22, 2012 at 02:27:57PM +0200, Aaro Koskinen wrote: > > It looks like commit 816422ad76474fed8052b6f7b905a054d082e59a > > (asm-generic, mm: pgtable: consolidate zero page helpers) broke > > MIPS/SPARSEMEM build in 3.8-rc1: > > Could you try this: > > http://permalink.gmane.org/gmane.linux.kernel/1410981 It's not helping. And if you look at the error, it shows linux/mm.h is already there? [...] In file included from /home/aaro/git/linux/arch/mips/include/asm/pgtable.h:388:0, from include/linux/mm.h:44, from arch/mips/kernel/asm-offsets.c:14: [...] A. From mcdonald.shane@gmail.com Mon Dec 24 05:06:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Dec 2012 05:06:38 +0100 (CET) Received: from mail-ia0-f180.google.com ([209.85.210.180]:41264 "EHLO mail-ia0-f180.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817286Ab2LXEGhhQwNE (ORCPT ); Mon, 24 Dec 2012 05:06:37 +0100 Received: by mail-ia0-f180.google.com with SMTP id t4so5718482iag.11 for ; Sun, 23 Dec 2012 20:06:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:date:message-id:to:subject:from; bh=0ATmrfeqXoZIuXtfnoLS/iOn19EdagiWg5Of0lr66H4=; b=dwulcPWBh1L+dgynVr05gIHE7+1ALsNlKHhI9Oz0uzZcW/3UF805k3qHd0qqHJvGOy 8VlGwTCkTqVSm2Qh5OyF/2sW2meGz1TNo4Nwg76BGasU7BpEP0Pqzz5KB5t8GCADRMyk EMpn86WlkSX+ChUxv3doHkvowysnzYuskCfiQCOGstpy9DsVpvcb2kK43SF4eysFVWZT DbuhuZYMPQxU6jDWhMVwFHr9OccdmOZQpFrSydYJ5DFu2r0otUDH/+qT6X8w9nnCH6mr d2l6s6/Ii8eGX/j5ObGWwOqxjG5/MAl/u92uMTFsDmaA8lzq7bGG/mGtHN2OMFfCc+6G qZyg== X-Received: by 10.50.41.165 with SMTP id g5mr19347011igl.66.1356321990861; Sun, 23 Dec 2012 20:06:30 -0800 (PST) Received: from localhost ([207.47.250.72]) by mx.google.com with ESMTPS id pr7sm21624102igc.16.2012.12.23.20.06.28 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 23 Dec 2012 20:06:29 -0800 (PST) Received: from shane by localhost with local (Exim 4.72) (envelope-from ) id 1TmzJ4-0003mm-3H; Sun, 23 Dec 2012 22:06:26 -0600 Date: Sun, 23 Dec 2012 22:06:26 -0600 Message-Id: To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: MIPS: MSP71xx: Indicate new location of source files in Platform file From: Shane McDonald X-archive-position: 35316 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 920 Lines: 27 The source files for the MSP71xx support code have been moved in commit 13a347ef60c68e490809dad8fcf79c25eabc4d58, "MIPS: MSP71xx: Move code." Update the Platform file to indicate the new location. Signed-off-by: Shane McDonald --- arch/mips/pmcs-msp71xx/Platform | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/pmcs-msp71xx/Platform b/arch/mips/pmcs-msp71xx/Platform index 17299f9..9a86e29 100644 --- a/arch/mips/pmcs-msp71xx/Platform +++ b/arch/mips/pmcs-msp71xx/Platform @@ -1,7 +1,7 @@ # # PMC-Sierra MSP SOCs # -platform-$(CONFIG_PMC_MSP) += pmc-sierra/ -cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/pmc-sierra \ +platform-$(CONFIG_PMC_MSP) += pmcs-msp71xx/ +cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \ -mno-branch-likely load-$(CONFIG_PMC_MSP) += 0xffffffff80100000 -- 1.7.2.5 From mcdonald.shane@gmail.com Mon Dec 24 05:53:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Dec 2012 05:54:06 +0100 (CET) Received: from mail-ie0-f176.google.com ([209.85.223.176]:51330 "EHLO mail-ie0-f176.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816206Ab2LXExwv87kw (ORCPT ); Mon, 24 Dec 2012 05:53:52 +0100 Received: by mail-ie0-f176.google.com with SMTP id 13so8498323iea.21 for ; Sun, 23 Dec 2012 20:53:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:date:message-id:to:subject:from; bh=X9AXdVSmABDtc0n03rBwou9MqqdNKH7WBkMjytvZ/kE=; b=h3xujLDgCvInN9Q6hxDujHXaMKeNF9Qc7LeRHgfqW1OXNo26tSxJtr4Vc7ZEi/nQfw D6smjBy7fr1S6K7KPxzWSgKXd7zht04JQ36ZQcQMZZOypSCmjWZuLu08q4MNJRZmonRg d9gi2r5RmPf7zCNsyGIaSsztw7IjY+LlzJ0qmXs6aaQH2DGEUT/Z75Fgd/Uxkyu7dpR9 Qq3eaf4cs79bChC+V+rCgghPL996xSR2qLDAliPt75efTmQJxnLYKeALYQ+E3XFg7GhW 6r/GYzLkqtIz5diRsab/HaaO9zvJ3IjRXohr3wKDQsUIqzn1nDhCEtJgSZWtWUoooB9W GUfw== X-Received: by 10.50.150.167 with SMTP id uj7mr19567328igb.33.1356324825635; Sun, 23 Dec 2012 20:53:45 -0800 (PST) Received: from localhost ([207.47.250.72]) by mx.google.com with ESMTPS id ex10sm16149421igc.15.2012.12.23.20.53.40 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 23 Dec 2012 20:53:44 -0800 (PST) Received: from shane by localhost with local (Exim 4.72) (envelope-from ) id 1Tn02j-0003nm-Hh; Sun, 23 Dec 2012 22:53:37 -0600 Date: Sun, 23 Dec 2012 22:53:37 -0600 Message-Id: To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH] MIPS: MSP71xx: Move include files From: Shane McDonald X-archive-position: 35317 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 174627 Lines: 4605 Now that Yosemite's gone we can move the MSP71xx include files one level up. Signed-off-by: Shane McDonald --- .../asm/mach-pmcs-msp71xx/cpu-feature-overrides.h | 22 + arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h | 46 ++ .../include/asm/mach-pmcs-msp71xx/msp_cic_int.h | 151 +++++ .../asm/mach-pmcs-msp71xx/msp_gpio_macros.h | 343 ++++++++++ arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h | 43 ++ arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h | 205 ++++++ arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h | 171 +++++ .../include/asm/mach-pmcs-msp71xx/msp_regops.h | 236 +++++++ arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h | 664 ++++++++++++++++++++ .../include/asm/mach-pmcs-msp71xx/msp_slp_int.h | 141 +++++ arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h | 144 +++++ arch/mips/include/asm/mach-pmcs-msp71xx/war.h | 29 + .../asm/pmc-sierra/msp71xx/cpu-feature-overrides.h | 22 - arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h | 46 -- .../include/asm/pmc-sierra/msp71xx/msp_cic_int.h | 151 ----- .../asm/pmc-sierra/msp71xx/msp_gpio_macros.h | 343 ---------- arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h | 43 -- arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h | 205 ------ .../mips/include/asm/pmc-sierra/msp71xx/msp_prom.h | 171 ----- .../include/asm/pmc-sierra/msp71xx/msp_regops.h | 236 ------- .../mips/include/asm/pmc-sierra/msp71xx/msp_regs.h | 664 -------------------- .../include/asm/pmc-sierra/msp71xx/msp_slp_int.h | 141 ----- arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h | 144 ----- arch/mips/include/asm/pmc-sierra/msp71xx/war.h | 29 - arch/mips/pmcs-msp71xx/Platform | 2 +- 25 files changed, 2196 insertions(+), 2196 deletions(-) create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/msp_gpio_macros.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/msp_slp_int.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h create mode 100644 arch/mips/include/asm/mach-pmcs-msp71xx/war.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h delete mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/war.h diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-pmcs-msp71xx/cpu-feature-overrides.h new file mode 100644 index 0000000..016fa94 --- /dev/null +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/cpu-feature-overrides.h @@ -0,0 +1,22 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_mips16 1 +#define cpu_has_dsp 1 +/* #define cpu_has_dsp2 ??? - do runtime detection */ +#define cpu_has_mipsmt 1 +#define cpu_has_fpu 0 + +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#endif /* __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h b/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h new file mode 100644 index 0000000..ebdbab9 --- /dev/null +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h @@ -0,0 +1,46 @@ +/* + * include/asm-mips/pmc-sierra/msp71xx/gpio.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * @author Patrick Glass + */ + +#ifndef __PMC_MSP71XX_GPIO_H +#define __PMC_MSP71XX_GPIO_H + +/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */ +#define ARCH_NR_GPIOS (28 + (3 * 8)) + +/* new generic GPIO API - see Documentation/gpio.txt */ +#include + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep + +/* Setup calls for the gpio and gpio extended */ +extern void msp71xx_init_gpio(void); +extern void msp71xx_init_gpio_extended(void); +extern int msp71xx_set_output_drive(unsigned gpio, int value); + +/* Custom output drive functionss */ +static inline int gpio_set_output_drive(unsigned gpio, int value) +{ + return msp71xx_set_output_drive(gpio, value); +} + +/* IRQ's are not supported for gpio lines */ +static inline int gpio_to_irq(unsigned gpio) +{ + return -EINVAL; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return -EINVAL; +} + +#endif /* __PMC_MSP71XX_GPIO_H */ diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h new file mode 100644 index 0000000..c84bcf9 --- /dev/null +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h @@ -0,0 +1,151 @@ +/* + * Defines for the MSP interrupt controller. + * + * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. + * Author: Carsten Langgaard, carstenl@mips.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + */ + +#ifndef _MSP_CIC_INT_H +#define _MSP_CIC_INT_H + +/* + * The PMC-Sierra CIC interrupts are all centrally managed by the + * CIC sub-system. + * We attempt to keep the interrupt numbers as consistent as possible + * across all of the MSP devices, but some differences will creep in ... + * The interrupts which are directly forwarded to the MIPS core interrupts + * are assigned interrupts in the range 0-7, interrupts cascaded through + * the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4 + * (MSP_INT_CIC). Currently we don't really distinguish between VPE1 + * and VPE0 (or thread contexts for that matter). Will have to fix. + * The PER interrupts are assigned interrupts in the range 40-71. +*/ + + +/* + * IRQs directly forwarded to the CPU + */ +#define MSP_MIPS_INTBASE 0 +#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ +#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ +#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ +#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ +#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */ +#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */ +#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */ +#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */ + +/* + * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) + * These defines should be tied to the register definitions for the CIC + * interrupt routine. For now, just use hard-coded values. + */ +#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8) +#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0) + /* External interrupt 0 */ +#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1) + /* External interrupt 1 */ +#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2) + /* External interrupt 2 */ +#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3) + /* External interrupt 3 */ +#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4) + /* CPU interface interrupt */ +#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5) + /* External interrupt 4 */ +#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6) + /* Cascaded IRQ for USB */ +#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7) + /* Sec engine mailbox IRQ */ +#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8) + /* External interrupt 5 */ +#define MSP_INT_TDM (MSP_CIC_INTBASE + 9) + /* TDM interrupt */ +#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10) + /* Cascaded IRQ for MAC 0 */ +#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11) + /* Cascaded IRQ for MAC 1 */ +#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12) + /* Cascaded IRQ for sec engine */ +#define MSP_INT_PER (MSP_CIC_INTBASE + 13) + /* Peripheral interrupt */ +#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14) + /* SLP timer 0 */ +#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15) + /* SLP timer 1 */ +#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16) + /* SLP timer 2 */ +#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17) + /* VPE0 MIPS timer */ +#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18) + /* Block Copy */ +#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19) + /* UART 0 */ +#define MSP_INT_PCI (MSP_CIC_INTBASE + 20) + /* PCI subsystem */ +#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21) + /* External interrupt 5 */ +#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22) + /* PCI Message Signal */ +#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23) + /* Cascaded ADSL2+ SAR IRQ */ +#define MSP_INT_DSL (MSP_CIC_INTBASE + 24) + /* ADSL2+ IRQ */ +#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25) + /* SLP error condition */ +#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26) + /* VPE1 MIPS timer */ +#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27) + /* VPE0 Performance counter */ +#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28) + /* VPE1 Performance counter */ +#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29) + /* External interrupt 5 */ +#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30) + /* VPE0 Software interrupt */ +#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31) + /* VPE0 Software interrupt */ + +/* + * IRQs cascaded on CIC PER interrupt (MSP_INT_PER) + */ +#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32) +/* Reserved 0-1 */ +#define MSP_INT_UART1 (MSP_PER_INTBASE + 2) + /* UART 1 */ +/* Reserved 3-5 */ +#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) + /* 2-wire */ +#define MSP_INT_TM0 (MSP_PER_INTBASE + 7) + /* Peripheral timer block out 0 */ +#define MSP_INT_TM1 (MSP_PER_INTBASE + 8) + /* Peripheral timer block out 1 */ +/* Reserved 9 */ +#define MSP_INT_SPRX (MSP_PER_INTBASE + 10) + /* SPI RX complete */ +#define MSP_INT_SPTX (MSP_PER_INTBASE + 11) + /* SPI TX complete */ +#define MSP_INT_GPIO (MSP_PER_INTBASE + 12) + /* GPIO */ +#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) + /* Peripheral error */ +/* Reserved 14-31 */ + +#endif /* !_MSP_CIC_INT_H */ diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_gpio_macros.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_gpio_macros.h new file mode 100644 index 0000000..156f320 --- /dev/null +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_gpio_macros.h @@ -0,0 +1,343 @@ +/* + * + * Macros for external SMP-safe access to the PMC MSP71xx reference + * board GPIO pins + * + * Copyright 2010 PMC-Sierra, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MSP_GPIO_MACROS_H__ +#define __MSP_GPIO_MACROS_H__ + +#include +#include + +#ifdef CONFIG_PMC_MSP7120_GW +#define MSP_NUM_GPIOS 20 +#else +#define MSP_NUM_GPIOS 28 +#endif + +/* -- GPIO Enumerations -- */ +enum msp_gpio_data { + MSP_GPIO_LO = 0, + MSP_GPIO_HI = 1, + MSP_GPIO_NONE, /* Special - Means pin is out of range */ + MSP_GPIO_TOGGLE, /* Special - Sets pin to opposite */ +}; + +enum msp_gpio_mode { + MSP_GPIO_INPUT = 0x0, + /* MSP_GPIO_ INTERRUPT = 0x1, Not supported yet */ + MSP_GPIO_UART_INPUT = 0x2, /* Only GPIO 4 or 5 */ + MSP_GPIO_OUTPUT = 0x8, + MSP_GPIO_UART_OUTPUT = 0x9, /* Only GPIO 2 or 3 */ + MSP_GPIO_PERIF_TIMERA = 0x9, /* Only GPIO 0 or 1 */ + MSP_GPIO_PERIF_TIMERB = 0xa, /* Only GPIO 0 or 1 */ + MSP_GPIO_UNKNOWN = 0xb, /* No such GPIO or mode */ +}; + +/* -- Static Tables -- */ + +/* Maps pins to data register */ +static volatile u32 * const MSP_GPIO_DATA_REGISTER[] = { + /* GPIO 0 and 1 on the first register */ + GPIO_DATA1_REG, GPIO_DATA1_REG, + /* GPIO 2, 3, 4, and 5 on the second register */ + GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG, + /* GPIO 6, 7, 8, and 9 on the third register */ + GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG, + /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */ + GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG, + GPIO_DATA4_REG, GPIO_DATA4_REG, + /* GPIO 16 - 23 on the first strange EXTENDED register */ + EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, + EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, + EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, + /* GPIO 24 - 27 on the second strange EXTENDED register */ + EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, + EXTENDED_GPIO2_REG, +}; + +/* Maps pins to mode register */ +static volatile u32 * const MSP_GPIO_MODE_REGISTER[] = { + /* GPIO 0 and 1 on the first register */ + GPIO_CFG1_REG, GPIO_CFG1_REG, + /* GPIO 2, 3, 4, and 5 on the second register */ + GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG, + /* GPIO 6, 7, 8, and 9 on the third register */ + GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG, + /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */ + GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG, + GPIO_CFG4_REG, GPIO_CFG4_REG, + /* GPIO 16 - 23 on the first strange EXTENDED regis