From dhillf@gmail.com Sat Sep 1 17:01:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Sep 2012 17:01:25 +0200 (CEST) Received: from mail-vc0-f177.google.com ([209.85.220.177]:53916 "EHLO mail-vc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903297Ab2IAPBS (ORCPT ); Sat, 1 Sep 2012 17:01:18 +0200 Received: by vcbfl15 with SMTP id fl15so4526389vcb.36 for ; Sat, 01 Sep 2012 08:01:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=r0OZiZ0zzPsK9c0N9CexNfLBdMDybaQwdYOZBEHUTjI=; b=vuk/HxXIuDo3AZngAm4HjbBaVpDA2D48hGF8ib0r46J2ELq+F8QbIvq2I0aC7sqkbb 8/vSYooc2QdmPAFIVf98g+L2sKWQJ5oaU8RgXSVrTqxea42/KRCWpDIsqKrjykIT466m TwJYhWWLGTlh1tKxvaoEvb/XkKvjManHSb42yiJzvhFOmevy2lKgh4ULHYSgyhBNUxZg RFskidxejfXfeMeA8pHEp+9fw06ccB5VOCo10MuX2lUKqgtLyAgUeHYxZ3TL72jxPOXZ zteBNqq5VF+1dtaiajUDIqBoh0PnpLYbHEFUOspDHhY7kdVmrbohcPhbJ3ZP13CI87cV xQKg== MIME-Version: 1.0 Received: by 10.52.70.46 with SMTP id j14mr6391340vdu.42.1346511672850; Sat, 01 Sep 2012 08:01:12 -0700 (PDT) Received: by 10.220.96.148 with HTTP; Sat, 1 Sep 2012 08:01:12 -0700 (PDT) Date: Sat, 1 Sep 2012 23:01:12 +0800 Message-ID: Subject: [patch] MIPS: align address to HPAGE_SIZE when updating mmu for thp From: Hillf Danton To: Ralf Baechle , Hillf Danton , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 34393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 604 Lines: 18 Make certain that we are always handling head page in all cases if address is aligned to HPAGE_SIZE. Signed-off-by: Hillf Danton --- --- a/arch/mips/include/asm/pgtable.h Sat Sep 1 22:27:12 2012 +++ b/arch/mips/include/asm/pgtable.h Sat Sep 1 22:38:02 2012 @@ -546,7 +546,7 @@ static inline pmd_t pmdp_get_and_clear(s static inline void update_mmu_thp(struct vm_area_struct *vma, unsigned long addr, pmd_t *pmdp) { - update_mmu_cache(vma, addr, (pte_t *)pmdp); + update_mmu_cache(vma, addr & HPAGE_PMD_MASK, (pte_t *)pmdp); } #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ -- From juhosg@openwrt.org Sat Sep 1 18:46:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Sep 2012 18:46:22 +0200 (CEST) Received: from arrakis.dune.hu ([78.24.191.176]:46516 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903298Ab2IAQqQ (ORCPT ); Sat, 1 Sep 2012 18:46:16 +0200 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 5CFE323C0094; Sat, 1 Sep 2012 18:46:14 +0200 (CEST) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos , , "[3.5+]"@arrakis.dune.hu Subject: [PATCH] MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x Date: Sat, 1 Sep 2012 18:46:00 +0200 Message-Id: <1346517960-13537-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 34394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 1649 Lines: 48 The current dividers in the code are wrong and this leads to broken CPU frequency calculation on boards where the fractional part is used. For example, if the SoC is running from a 40MHz reference clock, refdiv=1, nint=14, outdiv=0 and nfrac=31 the real frequency is 579.375MHz but the current code calculates 569.687MHz instead. Because the system time is indirectly related to the CPU frequency the broken computation causes drift in the system time. The correct divider is 2^6 for the CPU PLL and 2^10 for the DDR PLL. Use the correct values to fix the issue. Cc: [3.5+] Signed-off-by: Gabor Juhos --- arch/mips/ath79/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index b91ad3e..d272857 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -189,7 +189,7 @@ static void __init ar934x_clocks_init(void) AR934X_PLL_CPU_CONFIG_NFRAC_MASK; cpu_pll = nint * ath79_ref_clk.rate / ref_div; - cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); + cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); cpu_pll /= (1 << out_div); pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); @@ -203,7 +203,7 @@ static void __init ar934x_clocks_init(void) AR934X_PLL_DDR_CONFIG_NFRAC_MASK; ddr_pll = nint * ath79_ref_clk.rate / ref_div; - ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); + ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); ddr_pll /= (1 << out_div); clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); -- 1.7.10 From thierry.reding@avionic-design.de Sun Sep 2 11:52:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 11:52:50 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:58650 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901165Ab2IBJwm (ORCPT ); Sun, 2 Sep 2012 11:52:42 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu0) with ESMTP (Nemesis) id 0M3O8y-1TPumw1gTQ-00r1Ts; Sun, 02 Sep 2012 11:52:34 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id A27752A28305; Sun, 2 Sep 2012 11:52:33 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id twrgXeIIwXVe; Sun, 2 Sep 2012 11:52:32 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 449E22A282EC; Sun, 2 Sep 2012 11:52:32 +0200 (CEST) From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: [PATCH 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Date: Sun, 2 Sep 2012 11:52:27 +0200 Message-Id: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 X-Provags-ID: V02:K0:Y4bA/5CKk5Dd3Ey41RPM6LHj6BDA9/gLkEb5dPTFqcQ jKzCCtGMrlx3LCpv+OXBJeeH9pe/i+4x3KT6XSDn7mjEPLv7+C mKaJIakaY8igAFOgWbzM8vCYP/kWgeYdXpDa5EhquVni1bCRlA cOb1TwTqmMERzjaNX7s2VvGXbVr7q0KEYSkoXCiPxVXgQKXPi9 FycTfEQvcFmLzWOCeoQSvCMrSarkZynsqsyM4/9gmVm97lSSp1 8yyxeITSLSHYbTx07XD1VKsAjYBgSGaa5xOJR7POSt2XKgtm+o phXjq0b/eDilil8g/9TqQdQCcZ90tAW0mw+vELxrYYmBRZIFIg LpY5TvfgONTPu80IXYYqbUzNyFj+rgwl2puDMoswjAP0ND23Cc iw0c3yTf4OKZvU34oN+CXqjN1oTxyd2Ym1odlyGWfJFS1YToxq m9PWz X-archive-position: 34395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1869 Lines: 45 Hi, This small series fixes a build error due to a circular header dependency, exports the timer API so it can be used outside of the arch/mips/jz4740 tree and finally moves and converts the JZ4740 PWM driver to the PWM framework. Note that I don't have any hardware to test this on, so I had to rely on compile tests only. Patches 1 and 2 should probably go through the MIPS tree, while I can take patch 3 through the PWM tree. It touches a couple of files in arch/mips but the changes are unlikely to cause conflicts. Thierry Thierry Reding (3): MIPS: JZ4740: Break circular header dependency MIPS: JZ4740: Export timer API pwm: Add Ingenic JZ4740 support arch/mips/include/asm/mach-jz4740/irq.h | 5 + arch/mips/include/asm/mach-jz4740/platform.h | 1 + arch/mips/include/asm/mach-jz4740/timer.h | 35 +++++ arch/mips/jz4740/Kconfig | 3 - arch/mips/jz4740/Makefile | 2 +- arch/mips/jz4740/board-qi_lb60.c | 3 +- arch/mips/jz4740/irq.h | 23 --- arch/mips/jz4740/platform.c | 6 + arch/mips/jz4740/pwm.c | 177 ----------------------- arch/mips/jz4740/time.c | 2 +- arch/mips/jz4740/timer.c | 128 +++++++++++++++-- arch/mips/jz4740/timer.h | 136 ------------------ drivers/pwm/Kconfig | 12 +- drivers/pwm/Makefile | 1 + drivers/pwm/core.c | 2 +- drivers/pwm/pwm-jz4740.c | 205 +++++++++++++++++++++++++++ 16 files changed, 386 insertions(+), 355 deletions(-) delete mode 100644 arch/mips/jz4740/irq.h delete mode 100644 arch/mips/jz4740/pwm.c delete mode 100644 arch/mips/jz4740/timer.h create mode 100644 drivers/pwm/pwm-jz4740.c -- 1.7.12 From thierry.reding@avionic-design.de Sun Sep 2 11:52:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 11:53:13 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.10]:60400 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1902756Ab2IBJwp (ORCPT ); Sun, 2 Sep 2012 11:52:45 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu4) with ESMTP (Nemesis) id 0Lmjnc-1Tp9Jf1inM-00h2Sm; Sun, 02 Sep 2012 11:52:35 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id A47142A2830D; Sun, 2 Sep 2012 11:52:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mO5Bq1cTshNG; Sun, 2 Sep 2012 11:52:33 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 0FBD92A282FD; Sun, 2 Sep 2012 11:52:33 +0200 (CEST) From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: [PATCH 1/3] MIPS: JZ4740: Break circular header dependency Date: Sun, 2 Sep 2012 11:52:28 +0200 Message-Id: <1346579550-5990-2-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:vBTpCUbdjb+f0tX8mbylDajFjasL5SP7lFS8D7fTp8A xkkgOQ4NkkdLi8RuGGLR6YMji/Q1OUQSR18/SJYAq5K4TB+WUR FuxTDs6Hq3/AplT9DS0o+hx5oCwcRyQumyYmn52pQdGesOjaUM 6fsYDpQRSRYFhm84p7C0x3DMWBm6DxeWmdtdbG+GWLeEHGf8sI IqrwE9AVrbFxIuv38JDM1+YW3euR5q7kCWrWgYzqQznZDPzQ3E WLWv/9AEBOURjrvdr+PY3BKogyxnjIiBPqVDz50mwOlFDcvkKU gPzCHCqU0rExQCwACgeyPYcQDbfT+LhEyaM3/Vjn8+wth0bEqO a7RG4EJbhNf/MuIfNg8zzRO3S3XtotnYMfPK1fFU0UjP5MORMi FdxXEq9WSJqjCAWZlNb7wWYnmoSoRbKPf6/5vvJXfCU7IQUBm+ YLAM8 X-archive-position: 34396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2009 Lines: 60 When including irq.h, arch/mips/jz4740/irq.h will be selected as the first candidate. This header does not include the proper definitions (most notably NR_IRQS) required by subsequent headers. To solve this arch/mips/jz4740/irq.h can be deleted and its contents can be moved into arch/mips/include/asm/mach-jz4740/irq.h, which will then be correctly included. Signed-off-by: Thierry Reding --- arch/mips/include/asm/mach-jz4740/irq.h | 5 +++++ arch/mips/jz4740/irq.h | 23 ----------------------- 2 files changed, 5 insertions(+), 23 deletions(-) delete mode 100644 arch/mips/jz4740/irq.h diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h index 5ad1a9c..aa6fd90 100644 --- a/arch/mips/include/asm/mach-jz4740/irq.h +++ b/arch/mips/include/asm/mach-jz4740/irq.h @@ -54,4 +54,9 @@ #define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6) +struct irq_data; + +extern void jz4740_irq_suspend(struct irq_data *data); +extern void jz4740_irq_resume(struct irq_data *data); + #endif diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h deleted file mode 100644 index f75e39d..0000000 --- a/arch/mips/jz4740/irq.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __MIPS_JZ4740_IRQ_H__ -#define __MIPS_JZ4740_IRQ_H__ - -#include - -extern void jz4740_irq_suspend(struct irq_data *data); -extern void jz4740_irq_resume(struct irq_data *data); - -#endif -- 1.7.12 From thierry.reding@avionic-design.de Sun Sep 2 11:52:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 11:53:40 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.10]:55118 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903298Ab2IBJwp (ORCPT ); Sun, 2 Sep 2012 11:52:45 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap4) with ESMTP (Nemesis) id 0LoIBN-1TnmP71OgL-00gDOg; Sun, 02 Sep 2012 11:52:36 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id BBBAD2A282FF; Sun, 2 Sep 2012 11:52:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id W0sqK1nlLjpH; Sun, 2 Sep 2012 11:52:34 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id D95852A282EC; Sun, 2 Sep 2012 11:52:33 +0200 (CEST) From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: [PATCH 2/3] MIPS: JZ4740: Export timer API Date: Sun, 2 Sep 2012 11:52:29 +0200 Message-Id: <1346579550-5990-3-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:yIT9Euq0LRTENHP/24JAnfVRb8OgF9DD7mmhmYK4ivS LA3pgCoiOcI755OtpSe8bbQo2tJmrAYrcdlEFnuwbGduH7qER6 Tu23atrdwBdnbq0qQJ9hxvdyvt/M7o0JizkwgJfRNhYC+634F6 z0ebtpWR+P0lP10N/I0pCG6/U4fNYsGreBTatwNJ8mWCYIg19q vyyD5aePD+OlpRMlPJMUwtqJJcUv59ZAdpZOQgCJXJr9Lf6iMD PSGyI4skWF+SeUHdtawfvDGm32a688r+eU59/l3+8vR0SCxxPb x5rrJ2UAC/chfYMiu3dR3jaVazlWAsvd0DznEabmdeb3Dijoje j2VriXuimU7GacyEcQCrbyIgOHUw9SifjkVoM5qxgDNpoe86xN ynp4WGNYQysiPomK/uhZgTiq8BEl0e4iV5VIPaavE/3Lu3T4Z5 hNaVc X-archive-position: 34397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 11734 Lines: 364 This is a prerequisite for allowing the PWM driver to be converted to the PWM framework. Signed-off-by: Thierry Reding --- arch/mips/include/asm/mach-jz4740/timer.h | 35 ++++++++ arch/mips/jz4740/time.c | 2 +- arch/mips/jz4740/timer.c | 128 +++++++++++++++++++++++++--- arch/mips/jz4740/timer.h | 136 ------------------------------ 4 files changed, 153 insertions(+), 148 deletions(-) delete mode 100644 arch/mips/jz4740/timer.h diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h index 9baa03c..9e41d0e 100644 --- a/arch/mips/include/asm/mach-jz4740/timer.h +++ b/arch/mips/include/asm/mach-jz4740/timer.h @@ -16,6 +16,41 @@ #ifndef __ASM_MACH_JZ4740_TIMER #define __ASM_MACH_JZ4740_TIMER +#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9) +#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8) +#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7) +#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c +#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3 +#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3) +#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3) +#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3) +#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3) +#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3) +#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3) + +#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET) + +#define JZ_TIMER_CTRL_SRC_EXT BIT(2) +#define JZ_TIMER_CTRL_SRC_RTC BIT(1) +#define JZ_TIMER_CTRL_SRC_PCLK BIT(0) + +void __init jz4740_timer_init(void); + +void jz4740_timer_stop(unsigned int timer); +void jz4740_timer_start(unsigned int timer); +bool jz4740_timer_is_enabled(unsigned int timer); +void jz4740_timer_enable(unsigned int timer); +void jz4740_timer_disable(unsigned int timer); +void jz4740_timer_set_period(unsigned int timer, uint16_t period); +void jz4740_timer_set_duty(unsigned int timer, uint16_t duty); +void jz4740_timer_set_count(unsigned int timer, uint16_t count); +uint16_t jz4740_timer_get_count(unsigned int timer); +void jz4740_timer_ack_full(unsigned int timer); +void jz4740_timer_irq_full_enable(unsigned int timer); +void jz4740_timer_irq_full_disable(unsigned int timer); +uint16_t jz4740_timer_get_ctrl(unsigned int timer); +void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl); + void jz4740_timer_enable_watchdog(void); void jz4740_timer_disable_watchdog(void); diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c index f83c2dd..39bb4bb 100644 --- a/arch/mips/jz4740/time.c +++ b/arch/mips/jz4740/time.c @@ -20,10 +20,10 @@ #include #include +#include #include #include "clock.h" -#include "timer.h" #define TIMER_CLOCKEVENT 0 #define TIMER_CLOCKSOURCE 1 diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c index 654d5c3..79c4354 100644 --- a/arch/mips/jz4740/timer.c +++ b/arch/mips/jz4740/timer.c @@ -21,19 +21,28 @@ #include -void __iomem *jz4740_timer_base; +#define JZ_REG_TIMER_STOP 0x0C +#define JZ_REG_TIMER_STOP_SET 0x1C +#define JZ_REG_TIMER_STOP_CLEAR 0x2C +#define JZ_REG_TIMER_ENABLE 0x00 +#define JZ_REG_TIMER_ENABLE_SET 0x04 +#define JZ_REG_TIMER_ENABLE_CLEAR 0x08 +#define JZ_REG_TIMER_FLAG 0x10 +#define JZ_REG_TIMER_FLAG_SET 0x14 +#define JZ_REG_TIMER_FLAG_CLEAR 0x18 +#define JZ_REG_TIMER_MASK 0x20 +#define JZ_REG_TIMER_MASK_SET 0x24 +#define JZ_REG_TIMER_MASK_CLEAR 0x28 -void jz4740_timer_enable_watchdog(void) -{ - writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); -} -EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog); +#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30) +#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34) +#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38) +#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C) -void jz4740_timer_disable_watchdog(void) -{ - writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); -} -EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog); +#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10) +#define JZ_TIMER_IRQ_FULL(x) BIT(x) + +void __iomem *jz4740_timer_base; void __init jz4740_timer_init(void) { @@ -48,3 +57,100 @@ void __init jz4740_timer_init(void) /* Timer irqs are unmasked by default, mask them */ writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET); } + +void jz4740_timer_stop(unsigned int timer) +{ + writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); +} +EXPORT_SYMBOL_GPL(jz4740_timer_stop); + +void jz4740_timer_start(unsigned int timer) +{ + writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); +} +EXPORT_SYMBOL_GPL(jz4740_timer_start); + +bool jz4740_timer_is_enabled(unsigned int timer) +{ + return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer); +} +EXPORT_SYMBOL_GPL(jz4740_timer_is_enabled); + +void jz4740_timer_enable(unsigned int timer) +{ + writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); +} +EXPORT_SYMBOL_GPL(jz4740_timer_enable); + +void jz4740_timer_disable(unsigned int timer) +{ + writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); +} +EXPORT_SYMBOL_GPL(jz4740_timer_disable); + +void jz4740_timer_set_period(unsigned int timer, uint16_t period) +{ + writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer)); +} +EXPORT_SYMBOL_GPL(jz4740_timer_set_period); + +void jz4740_timer_set_duty(unsigned int timer, uint16_t duty) +{ + writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer)); +} +EXPORT_SYMBOL_GPL(jz4740_timer_set_duty); + +void jz4740_timer_set_count(unsigned int timer, uint16_t count) +{ + writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); +} +EXPORT_SYMBOL_GPL(jz4740_timer_set_count); + +uint16_t jz4740_timer_get_count(unsigned int timer) +{ + return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); +} +EXPORT_SYMBOL_GPL(jz4740_timer_get_count); + +void jz4740_timer_ack_full(unsigned int timer) +{ + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); +} +EXPORT_SYMBOL_GPL(jz4740_timer_ack_full); + +void jz4740_timer_irq_full_enable(unsigned int timer) +{ + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); +} +EXPORT_SYMBOL_GPL(jz4740_timer_irq_full_enable); + +void jz4740_timer_irq_full_disable(unsigned int timer) +{ + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); +} +EXPORT_SYMBOL_GPL(jz4740_timer_irq_full_disable); + +void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl) +{ + writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); +} +EXPORT_SYMBOL_GPL(jz4740_timer_set_ctrl); + +uint16_t jz4740_timer_get_ctrl(unsigned int timer) +{ + return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); +} +EXPORT_SYMBOL_GPL(jz4740_timer_get_ctrl); + +void jz4740_timer_enable_watchdog(void) +{ + writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); +} +EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog); + +void jz4740_timer_disable_watchdog(void) +{ + writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); +} +EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog); diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h deleted file mode 100644 index fca3994..0000000 --- a/arch/mips/jz4740/timer.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen - * JZ4740 platform timer support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __MIPS_JZ4740_TIMER_H__ -#define __MIPS_JZ4740_TIMER_H__ - -#include -#include - -#define JZ_REG_TIMER_STOP 0x0C -#define JZ_REG_TIMER_STOP_SET 0x1C -#define JZ_REG_TIMER_STOP_CLEAR 0x2C -#define JZ_REG_TIMER_ENABLE 0x00 -#define JZ_REG_TIMER_ENABLE_SET 0x04 -#define JZ_REG_TIMER_ENABLE_CLEAR 0x08 -#define JZ_REG_TIMER_FLAG 0x10 -#define JZ_REG_TIMER_FLAG_SET 0x14 -#define JZ_REG_TIMER_FLAG_CLEAR 0x18 -#define JZ_REG_TIMER_MASK 0x20 -#define JZ_REG_TIMER_MASK_SET 0x24 -#define JZ_REG_TIMER_MASK_CLEAR 0x28 - -#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30) -#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34) -#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38) -#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C) - -#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10) -#define JZ_TIMER_IRQ_FULL(x) BIT(x) - -#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9) -#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8) -#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7) -#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c -#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3 -#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3) -#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3) -#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3) -#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3) -#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3) -#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3) - -#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET) - -#define JZ_TIMER_CTRL_SRC_EXT BIT(2) -#define JZ_TIMER_CTRL_SRC_RTC BIT(1) -#define JZ_TIMER_CTRL_SRC_PCLK BIT(0) - -extern void __iomem *jz4740_timer_base; -void __init jz4740_timer_init(void); - -static inline void jz4740_timer_stop(unsigned int timer) -{ - writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); -} - -static inline void jz4740_timer_start(unsigned int timer) -{ - writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); -} - -static inline bool jz4740_timer_is_enabled(unsigned int timer) -{ - return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer); -} - -static inline void jz4740_timer_enable(unsigned int timer) -{ - writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); -} - -static inline void jz4740_timer_disable(unsigned int timer) -{ - writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); -} - - -static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period) -{ - writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer)); -} - -static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty) -{ - writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer)); -} - -static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count) -{ - writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); -} - -static inline uint16_t jz4740_timer_get_count(unsigned int timer) -{ - return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); -} - -static inline void jz4740_timer_ack_full(unsigned int timer) -{ - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); -} - -static inline void jz4740_timer_irq_full_enable(unsigned int timer) -{ - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); -} - -static inline void jz4740_timer_irq_full_disable(unsigned int timer) -{ - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); -} - -static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl) -{ - writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); -} - -static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer) -{ - return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); -} - -#endif -- 1.7.12 From thierry.reding@avionic-design.de Sun Sep 2 11:52:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 11:54:04 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:59850 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903299Ab2IBJwu (ORCPT ); Sun, 2 Sep 2012 11:52:50 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu1) with ESMTP (Nemesis) id 0M1kaM-1TRYgZ2Z1G-00t9Ay; Sun, 02 Sep 2012 11:52:38 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 0CCC92A282EC; Sun, 2 Sep 2012 11:52:37 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lrDrBLmxKMpg; Sun, 2 Sep 2012 11:52:35 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 913AA2A2830C; Sun, 2 Sep 2012 11:52:34 +0200 (CEST) From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: [PATCH 3/3] pwm: Add Ingenic JZ4740 support Date: Sun, 2 Sep 2012 11:52:30 +0200 Message-Id: <1346579550-5990-4-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:O7bbH0d1TwMcIYzGjRDKZ0FYrCcqa7qpanbgUXKjkSM KCtQ+LPjkVVzTEdCL3vMrnx801ZTpDwguOkRrYDs62anNd7oM2 vQg2QPEHnAyiphQPqCc2rXgaiRCFVyQLi//QledAvTQva+dhtp vQDyYwIAxH2L90RX2CLUbavdRIRBMxxaz3Kjq/YPZl3Iqv6J6h +v0Y0FMxQPy1yXbZlqzuL76kdg0TUu7miAsMiC+Nbv7mQZ7O9L Fncu3LnevUmXvZtBFBj3HWEdkDrPYDilKtbEEcJQCK3PGlmmuH aHt5SgnZkY+exbyV7uUd83Cs09I57wIzLQHJPUOKNw/dxYR/78 3a4tT/eAQdhZsDh+VB7Kb2gBYmtWPbTldojvEX+is1+LI8KRdz wgxqDsPYdbfUbJvbUKr22LFx7ayo4LboF288AQQlnzQdcmszti 6pL4S X-archive-position: 34398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13847 Lines: 541 This commit moves the driver to drivers/pwm and converts it to the new PWM framework. Signed-off-by: Thierry Reding --- arch/mips/include/asm/mach-jz4740/platform.h | 1 + arch/mips/jz4740/Kconfig | 3 - arch/mips/jz4740/Makefile | 2 +- arch/mips/jz4740/board-qi_lb60.c | 3 +- arch/mips/jz4740/platform.c | 6 + arch/mips/jz4740/pwm.c | 177 ----------------------- drivers/pwm/Kconfig | 12 +- drivers/pwm/Makefile | 1 + drivers/pwm/core.c | 2 +- drivers/pwm/pwm-jz4740.c | 205 +++++++++++++++++++++++++++ 10 files changed, 228 insertions(+), 184 deletions(-) delete mode 100644 arch/mips/jz4740/pwm.c create mode 100644 drivers/pwm/pwm-jz4740.c diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h index 564ab81..163e81d 100644 --- a/arch/mips/include/asm/mach-jz4740/platform.h +++ b/arch/mips/include/asm/mach-jz4740/platform.h @@ -31,6 +31,7 @@ extern struct platform_device jz4740_pcm_device; extern struct platform_device jz4740_codec_device; extern struct platform_device jz4740_adc_device; extern struct platform_device jz4740_wdt_device; +extern struct platform_device jz4740_pwm_device; void jz4740_serial_device_register(void); diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig index 3e7141f..4689030 100644 --- a/arch/mips/jz4740/Kconfig +++ b/arch/mips/jz4740/Kconfig @@ -7,6 +7,3 @@ config JZ4740_QI_LB60 bool "Qi Hardware Ben NanoNote" endchoice - -config HAVE_PWM - bool diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile index e44abea..63bad0e 100644 --- a/arch/mips/jz4740/Makefile +++ b/arch/mips/jz4740/Makefile @@ -5,7 +5,7 @@ # Object file lists. obj-y += prom.o irq.o time.o reset.o setup.o dma.o \ - gpio.o clock.o platform.o timer.o pwm.o serial.o + gpio.o clock.o platform.o timer.o serial.o obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 9a3d9de..405382c 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -394,7 +394,7 @@ static struct platform_device qi_lb60_pwm_beeper = { .name = "pwm-beeper", .id = -1, .dev = { - .platform_data = (void *)4, + .platform_data = (void *)2, }, }; @@ -437,6 +437,7 @@ static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_codec_device, &jz4740_rtc_device, &jz4740_adc_device, + &jz4740_pwm_device, &qi_lb60_gpio_keys, &qi_lb60_pwm_beeper, &qi_lb60_charger_device, diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c index e342ed4..6d14dcd 100644 --- a/arch/mips/jz4740/platform.c +++ b/arch/mips/jz4740/platform.c @@ -323,3 +323,9 @@ struct platform_device jz4740_wdt_device = { .num_resources = ARRAY_SIZE(jz4740_wdt_resources), .resource = jz4740_wdt_resources, }; + +/* PWM */ +struct platform_device jz4740_pwm_device = { + .name = "jz4740-pwm", + .id = -1, +}; diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c deleted file mode 100644 index a26a6fa..0000000 --- a/arch/mips/jz4740/pwm.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen - * JZ4740 platform PWM support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include - -#include -#include -#include -#include - -#include -#include "timer.h" - -static struct clk *jz4740_pwm_clk; - -DEFINE_MUTEX(jz4740_pwm_mutex); - -struct pwm_device { - unsigned int id; - unsigned int gpio; - bool used; -}; - -static struct pwm_device jz4740_pwm_list[] = { - { 2, JZ_GPIO_PWM2, false }, - { 3, JZ_GPIO_PWM3, false }, - { 4, JZ_GPIO_PWM4, false }, - { 5, JZ_GPIO_PWM5, false }, - { 6, JZ_GPIO_PWM6, false }, - { 7, JZ_GPIO_PWM7, false }, -}; - -struct pwm_device *pwm_request(int id, const char *label) -{ - int ret = 0; - struct pwm_device *pwm; - - if (id < 2 || id > 7 || !jz4740_pwm_clk) - return ERR_PTR(-ENODEV); - - mutex_lock(&jz4740_pwm_mutex); - - pwm = &jz4740_pwm_list[id - 2]; - if (pwm->used) - ret = -EBUSY; - else - pwm->used = true; - - mutex_unlock(&jz4740_pwm_mutex); - - if (ret) - return ERR_PTR(ret); - - ret = gpio_request(pwm->gpio, label); - - if (ret) { - printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret); - pwm->used = false; - return ERR_PTR(ret); - } - - jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM); - - jz4740_timer_start(id); - - return pwm; -} - -void pwm_free(struct pwm_device *pwm) -{ - pwm_disable(pwm); - jz4740_timer_set_ctrl(pwm->id, 0); - - jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE); - gpio_free(pwm->gpio); - - jz4740_timer_stop(pwm->id); - - pwm->used = false; -} - -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) -{ - unsigned long long tmp; - unsigned long period, duty; - unsigned int prescaler = 0; - unsigned int id = pwm->id; - uint16_t ctrl; - bool is_enabled; - - if (duty_ns < 0 || duty_ns > period_ns) - return -EINVAL; - - tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns; - do_div(tmp, 1000000000); - period = tmp; - - while (period > 0xffff && prescaler < 6) { - period >>= 2; - ++prescaler; - } - - if (prescaler == 6) - return -EINVAL; - - tmp = (unsigned long long)period * duty_ns; - do_div(tmp, period_ns); - duty = period - tmp; - - if (duty >= period) - duty = period - 1; - - is_enabled = jz4740_timer_is_enabled(id); - if (is_enabled) - pwm_disable(pwm); - - jz4740_timer_set_count(id, 0); - jz4740_timer_set_duty(id, duty); - jz4740_timer_set_period(id, period); - - ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | - JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; - - jz4740_timer_set_ctrl(id, ctrl); - - if (is_enabled) - pwm_enable(pwm); - - return 0; -} - -int pwm_enable(struct pwm_device *pwm) -{ - uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); - - ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; - jz4740_timer_set_ctrl(pwm->id, ctrl); - jz4740_timer_enable(pwm->id); - - return 0; -} - -void pwm_disable(struct pwm_device *pwm) -{ - uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); - - ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; - jz4740_timer_disable(pwm->id); - jz4740_timer_set_ctrl(pwm->id, ctrl); -} - -static int __init jz4740_pwm_init(void) -{ - int ret = 0; - - jz4740_pwm_clk = clk_get(NULL, "ext"); - - if (IS_ERR(jz4740_pwm_clk)) { - ret = PTR_ERR(jz4740_pwm_clk); - jz4740_pwm_clk = NULL; - } - - return ret; -} -subsys_initcall(jz4740_pwm_init); diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 90c5c73..5c663df 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -1,6 +1,6 @@ menuconfig PWM bool "Pulse-Width Modulation (PWM) Support" - depends on !MACH_JZ4740 && !PUV3_PWM + depends on !PUV3_PWM help Generic Pulse-Width Modulation (PWM) support. @@ -47,6 +47,16 @@ config PWM_IMX To compile this driver as a module, choose M here: the module will be called pwm-imx. +config PWM_JZ4740 + tristate "Ingenic JZ4740 PWM support" + depends on MACH_JZ4740 + help + Generic PWM framework driver for Ingenic JZ4740 based + machines. + + To compile this driver as a module, choose M here: the module + will be called pwm-jz4740. + config PWM_LPC32XX tristate "LPC32XX PWM support" depends on ARCH_LPC32XX diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index e4b2c89..a1d6169 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_PWM) += core.o obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o +obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 92b1782..f5acdaa 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -371,7 +371,7 @@ EXPORT_SYMBOL_GPL(pwm_free); */ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { - if (!pwm || period_ns == 0 || duty_ns > period_ns) + if (!pwm || duty_ns < 0 || period_ns <= 0 || duty_ns > period_ns) return -EINVAL; return pwm->chip->ops->config(pwm->chip, pwm, duty_ns, period_ns); diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c new file mode 100644 index 0000000..db29b37 --- /dev/null +++ b/drivers/pwm/pwm-jz4740.c @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen + * JZ4740 platform PWM support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define NUM_PWM 6 + +static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = { + JZ_GPIO_PWM2, + JZ_GPIO_PWM3, + JZ_GPIO_PWM4, + JZ_GPIO_PWM5, + JZ_GPIO_PWM6, + JZ_GPIO_PWM7, +}; + +struct jz4740_pwm_chip { + struct pwm_chip chip; + struct clk *clk; +}; + +static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip) +{ + return container_of(chip, struct jz4740_pwm_chip, chip); +} + +static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; + int ret; + + ret = gpio_request(gpio, pwm->label); + + if (ret) { + printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret); + return ret; + } + + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_PWM); + + jz4740_timer_start(pwm->hwpwm); + + return 0; +} + +static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; + + jz4740_timer_set_ctrl(pwm->hwpwm, 0); + + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE); + gpio_free(gpio); + + jz4740_timer_stop(pwm->hwpwm); +} + +static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip); + unsigned long long tmp; + unsigned long period, duty; + unsigned int prescaler = 0; + uint16_t ctrl; + bool is_enabled; + + tmp = (unsigned long long)clk_get_rate(jz4740->clk) * period_ns; + do_div(tmp, 1000000000); + period = tmp; + + while (period > 0xffff && prescaler < 6) { + period >>= 2; + ++prescaler; + } + + if (prescaler == 6) + return -EINVAL; + + tmp = (unsigned long long)period * duty_ns; + do_div(tmp, period_ns); + duty = period - tmp; + + if (duty >= period) + duty = period - 1; + + is_enabled = jz4740_timer_is_enabled(pwm->hwpwm); + if (is_enabled) + pwm_disable(pwm); + + jz4740_timer_set_count(pwm->hwpwm, 0); + jz4740_timer_set_duty(pwm->hwpwm, duty); + jz4740_timer_set_period(pwm->hwpwm, period); + + ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | + JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; + + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); + + if (is_enabled) + pwm_enable(pwm); + + return 0; +} + +static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm); + + ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); + jz4740_timer_enable(pwm->hwpwm); + + return 0; +} + +static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); + + ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; + jz4740_timer_disable(pwm->hwpwm); + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); +} + +static const struct pwm_ops jz4740_pwm_ops = { + .request = jz4740_pwm_request, + .free = jz4740_pwm_free, + .config = jz4740_pwm_config, + .enable = jz4740_pwm_enable, + .disable = jz4740_pwm_disable, +}; + +static int jz4740_pwm_probe(struct platform_device *pdev) +{ + struct jz4740_pwm_chip *jz4740; + int ret = 0; + + jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL); + if (!jz4740) + return -ENOMEM; + + jz4740->clk = clk_get(NULL, "ext"); + if (IS_ERR(jz4740->clk)) + return PTR_ERR(jz4740->clk); + + jz4740->chip.dev = &pdev->dev; + jz4740->chip.ops = &jz4740_pwm_ops; + jz4740->chip.npwm = NUM_PWM; + jz4740->chip.base = -1; + + ret = pwmchip_add(&jz4740->chip); + if (ret < 0) { + clk_put(jz4740->clk); + return ret; + } + + platform_set_drvdata(pdev, jz4740); + + return 0; +} + +static int jz4740_pwm_remove(struct platform_device *pdev) +{ + struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&jz4740->chip); + if (ret < 0) + return ret; + + clk_put(jz4740->clk); + + return 0; +} + +static struct platform_driver jz4740_pwm_driver = { + .driver = { + .name = "jz4740-pwm", + }, + .probe = jz4740_pwm_probe, + .remove = jz4740_pwm_remove, +}; +module_platform_driver(jz4740_pwm_driver); -- 1.7.12 From maarten@treewalker.org Sun Sep 2 15:31:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 15:31:13 +0200 (CEST) Received: from smtp-vbr16.xs4all.nl ([194.109.24.36]:1598 "EHLO smtp-vbr16.xs4all.nl" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901165Ab2IBNbH (ORCPT ); Sun, 2 Sep 2012 15:31:07 +0200 Received: from starbug-2.trinair2002 (dhcp-089-098-069-120.chello.nl [89.98.69.120]) (authenticated bits=0) by smtp-vbr16.xs4all.nl (8.13.8/8.13.8) with ESMTP id q82DUExZ081653; Sun, 2 Sep 2012 15:30:14 +0200 (CEST) (envelope-from maarten@treewalker.org) Received: from hyperion.localnet (hyperion.trinair2002 [192.168.0.43]) by starbug-2.trinair2002 (Postfix) with ESMTP id 7CF822BA1C; Sun, 2 Sep 2012 15:30:14 +0200 (CEST) From: Maarten ter Huurne To: Thierry Reding Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen Subject: Re: [PATCH 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Date: Sun, 02 Sep 2012 15:25:55 +0200 Message-ID: <1890769.KjIbOv8Xbz@hyperion> User-Agent: KMail/4.9 (Linux/3.1.10-1.16-desktop; KDE/4.9.0; x86_64; ; ) In-Reply-To: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="nextPart1496028.RW5dUh1a0f" Content-Transfer-Encoding: 7Bit X-Virus-Scanned: by XS4ALL Virus Scanner X-archive-position: 34399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maarten@treewalker.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2887 Lines: 81 This is a multi-part message in MIME format. --nextPart1496028.RW5dUh1a0f Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" On Sunday 02 September 2012 11:52:27 Thierry Reding wrote: > This small series fixes a build error due to a circular header > dependency, exports the timer API so it can be used outside of > the arch/mips/jz4740 tree and finally moves and converts the > JZ4740 PWM driver to the PWM framework. > > Note that I don't have any hardware to test this on, so I had to > rely on compile tests only. Patches 1 and 2 should probably go > through the MIPS tree, while I can take patch 3 through the PWM > tree. It touches a couple of files in arch/mips but the changes > are unlikely to cause conflicts. Exporting the hardware outputs PWM2-7 as index 0-5 in the PWM core is rather confusing. I discussed with Lars on IRC and it's probably better to expose PWM0-7 through the API, but refuse to hand out PWM0 and PWM1 when requested, since their associated timers are in use by the system. I attached a diff that illustrates this approach. Note that if this approach is taken, the beeper ID in board-qi_lb60.c should be changed back from 2 to 4, since the beeper is attached to PWM4. I tested the "for-next" branch on the Dingoo A320 with the pwm-backlight driver. It didn't work at first, because the PWM number and the timer number didn't align: I requested PWM number 5 to get PWM7 and the GPIO of PWM7 was used, but with timer 5 instead of timer 7, resulting in a dark screen. However, it works fine after adding PWM0/1 as described above. If other people want to test on real hardware, you can find the code in branch jz-3.6-rc2-pwm in the qi-kernel repository. Unfortunately our web interface for git is still broken, but the repo itself is fine. git://projects.qi-hardware.com/qi-kernel.git Bye, Maarten --nextPart1496028.RW5dUh1a0f Content-Disposition: inline; filename="jz4740-pwm-all-8.diff" Content-Transfer-Encoding: 7Bit Content-Type: text/x-patch; charset="UTF-8"; name="jz4740-pwm-all-8.diff" diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c index db29b37..554e414 100644 --- a/drivers/pwm/pwm-jz4740.c +++ b/drivers/pwm/pwm-jz4740.c @@ -24,9 +24,11 @@ #include #include -#define NUM_PWM 6 +#define NUM_PWM 8 static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = { + JZ_GPIO_PWM0, + JZ_GPIO_PWM1, JZ_GPIO_PWM2, JZ_GPIO_PWM3, JZ_GPIO_PWM4, @@ -50,6 +52,13 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; int ret; + /* + * Timer 0 and 1 are used for system tasks, so they are unavailable + * for use as PWMs. + */ + if (pwm->hwpwm < 2) + return -EBUSY; + ret = gpio_request(gpio, pwm->label); if (ret) { --nextPart1496028.RW5dUh1a0f-- From lars@metafoo.de Sun Sep 2 16:44:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 16:44:42 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:64956 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901165Ab2IBOoe (ORCPT ); Sun, 2 Sep 2012 16:44:34 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 51ECA781; Sun, 2 Sep 2012 16:44:28 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id QBMhoc9GL2Kr; Sun, 2 Sep 2012 16:44:27 +0200 (CEST) Received: from [192.168.178.21] (ppp-88-217-76-199.dynamic.mnet-online.de [88.217.76.199]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 13824780; Sun, 2 Sep 2012 16:44:05 +0200 (CEST) Message-ID: <504370BF.6090702@metafoo.de> Date: Sun, 02 Sep 2012 16:44:15 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20120724 Icedove/3.0.11 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 3/3] pwm: Add Ingenic JZ4740 support References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-4-git-send-email-thierry.reding@avionic-design.de> In-Reply-To: <1346579550-5990-4-git-send-email-thierry.reding@avionic-design.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6784 Lines: 260 On 09/02/2012 11:52 AM, Thierry Reding wrote: > This commit moves the driver to drivers/pwm and converts it to the new > PWM framework. > Thanks for taking care of this, some comments inline. [...] > diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c > index 92b1782..f5acdaa 100644 > --- a/drivers/pwm/core.c > +++ b/drivers/pwm/core.c > @@ -371,7 +371,7 @@ EXPORT_SYMBOL_GPL(pwm_free); > */ > int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > { > - if (!pwm || period_ns == 0 || duty_ns > period_ns) > + if (!pwm || duty_ns < 0 || period_ns <= 0 || duty_ns > period_ns) > return -EINVAL; > This change seems to be unrelated. > return pwm->chip->ops->config(pwm->chip, pwm, duty_ns, period_ns); > diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c > new file mode 100644 > index 0000000..db29b37 > --- /dev/null > +++ b/drivers/pwm/pwm-jz4740.c > @@ -0,0 +1,205 @@ > +/* > + * Copyright (C) 2010, Lars-Peter Clausen > + * JZ4740 platform PWM support > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include #include > + > +#define NUM_PWM 6 > + > +static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = { As mth said, it would be better to have JZ_GPIO_PWM0 and here as well and set NUM_PWM to 8. Right now we are using the timers associated to PWM channel 0 and 1 as system timers. But there might be devices where this is not possible, e.g. because the PWM is actually connected to something. Also this fixes the of by two for the hwpwm id. > + JZ_GPIO_PWM2, > + JZ_GPIO_PWM3, > + JZ_GPIO_PWM4, > + JZ_GPIO_PWM5, > + JZ_GPIO_PWM6, > + JZ_GPIO_PWM7, > +}; > + > +struct jz4740_pwm_chip { > + struct pwm_chip chip; > + struct clk *clk; > +}; > + > +static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip) > +{ > + return container_of(chip, struct jz4740_pwm_chip, chip); > +} > + > +static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) > +{ > + unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; > + int ret; > + > + ret = gpio_request(gpio, pwm->label); > + > + if (ret) { > + printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret); dev_err(chip->dev, .... > + return ret; > + } > + > + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_PWM); > + > + jz4740_timer_start(pwm->hwpwm); > + > + return 0; > +} > + > +static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) > +{ > + unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; > + > + jz4740_timer_set_ctrl(pwm->hwpwm, 0); > + > + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE); > + gpio_free(gpio); > + > + jz4740_timer_stop(pwm->hwpwm); > +} > + > +static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, > + int duty_ns, int period_ns) > +{ > + struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip); > + unsigned long long tmp; > + unsigned long period, duty; > + unsigned int prescaler = 0; > + uint16_t ctrl; > + bool is_enabled; > + > + tmp = (unsigned long long)clk_get_rate(jz4740->clk) * period_ns; > + do_div(tmp, 1000000000); > + period = tmp; > + > + while (period > 0xffff && prescaler < 6) { > + period >>= 2; > + ++prescaler; > + } > + > + if (prescaler == 6) > + return -EINVAL; > + > + tmp = (unsigned long long)period * duty_ns; > + do_div(tmp, period_ns); > + duty = period - tmp; > + > + if (duty >= period) > + duty = period - 1; > + > + is_enabled = jz4740_timer_is_enabled(pwm->hwpwm); > + if (is_enabled) > + pwm_disable(pwm); I think this should be jz4740_pwm_disable > + > + jz4740_timer_set_count(pwm->hwpwm, 0); > + jz4740_timer_set_duty(pwm->hwpwm, duty); > + jz4740_timer_set_period(pwm->hwpwm, period); > + > + ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | > + JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; > + > + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); > + > + if (is_enabled) > + pwm_enable(pwm); and jz4740_pwm_enable here. > + > + return 0; > +} > + > + > +static const struct pwm_ops jz4740_pwm_ops = { > + .request = jz4740_pwm_request, > + .free = jz4740_pwm_free, > + .config = jz4740_pwm_config, > + .enable = jz4740_pwm_enable, > + .disable = jz4740_pwm_disable, .owner = THIS_MODULE, > +}; > + > +static int jz4740_pwm_probe(struct platform_device *pdev) __devinit > +{ > + struct jz4740_pwm_chip *jz4740; > + int ret = 0; The '= 0' is not really necessary since it will be overwritten anyway. > + > + jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL); > + if (!jz4740) > + return -ENOMEM; > + > + jz4740->clk = clk_get(NULL, "ext"); > + if (IS_ERR(jz4740->clk)) > + return PTR_ERR(jz4740->clk); > + > + jz4740->chip.dev = &pdev->dev; > + jz4740->chip.ops = &jz4740_pwm_ops; > + jz4740->chip.npwm = NUM_PWM; > + jz4740->chip.base = -1; > + > + ret = pwmchip_add(&jz4740->chip); > + if (ret < 0) { > + clk_put(jz4740->clk); > + return ret; > + } > + > + platform_set_drvdata(pdev, jz4740); > + > + return 0; > +} > + > +static int jz4740_pwm_remove(struct platform_device *pdev) __devexit > +{ > + struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev); > + int ret; > + > + ret = pwmchip_remove(&jz4740->chip); > + if (ret < 0) > + return ret; remove is not really allowed to fail, the return value is never really tested and the device is removed nevertheless. But this seems to be a problem with the PWM API. It should be possible to remove a PWM chip even if it is currently in use and after a PWM chip has been removed all calls to a pwm_device of that chip it should return an error. This will require reference counting for the pwm_device struct though. E.g. by adding a 'struct device' to it. > + > + clk_put(jz4740->clk); > + > + return 0; > +} > + > +static struct platform_driver jz4740_pwm_driver = { > + .driver = { > + .name = "jz4740-pwm", .owner = THIS_MODULE, > + }, > + .probe = jz4740_pwm_probe, > + .remove = jz4740_pwm_remove, .remove = __devexit_p(jz4740_pwm_remove), > +}; > +module_platform_driver(jz4740_pwm_driver); MODULE_LICENSE(...), MODULE_AUTHOR(...), MODULE_DESCRIPTION(...), MODULE_ALIAS(...) From lars@metafoo.de Sun Sep 2 16:45:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 16:45:49 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:65029 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901165Ab2IBOpj (ORCPT ); Sun, 2 Sep 2012 16:45:39 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 6BAC6785; Sun, 2 Sep 2012 16:45:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id Mk6WHxkH4Kix; Sun, 2 Sep 2012 16:45:33 +0200 (CEST) Received: from [192.168.178.21] (ppp-88-217-76-199.dynamic.mnet-online.de [88.217.76.199]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id A2D06784; Sun, 2 Sep 2012 16:45:32 +0200 (CEST) Message-ID: <50437117.8000700@metafoo.de> Date: Sun, 02 Sep 2012 16:45:43 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20120724 Icedove/3.0.11 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 2/3] MIPS: JZ4740: Export timer API References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-3-git-send-email-thierry.reding@avionic-design.de> In-Reply-To: <1346579550-5990-3-git-send-email-thierry.reding@avionic-design.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 12602 Lines: 367 On 09/02/2012 11:52 AM, Thierry Reding wrote: > This is a prerequisite for allowing the PWM driver to be converted to > the PWM framework. > > Signed-off-by: Thierry Reding I'd prefer to keep the timer functions inline, some of them are called quite often in the system clock code. > --- > arch/mips/include/asm/mach-jz4740/timer.h | 35 ++++++++ > arch/mips/jz4740/time.c | 2 +- > arch/mips/jz4740/timer.c | 128 +++++++++++++++++++++++++--- > arch/mips/jz4740/timer.h | 136 ------------------------------ > 4 files changed, 153 insertions(+), 148 deletions(-) > delete mode 100644 arch/mips/jz4740/timer.h > > diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h > index 9baa03c..9e41d0e 100644 > --- a/arch/mips/include/asm/mach-jz4740/timer.h > +++ b/arch/mips/include/asm/mach-jz4740/timer.h > @@ -16,6 +16,41 @@ > #ifndef __ASM_MACH_JZ4740_TIMER > #define __ASM_MACH_JZ4740_TIMER > > +#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9) > +#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8) > +#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7) > +#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c > +#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3 > +#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3) > +#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3) > +#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3) > +#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3) > +#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3) > +#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3) > + > +#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET) > + > +#define JZ_TIMER_CTRL_SRC_EXT BIT(2) > +#define JZ_TIMER_CTRL_SRC_RTC BIT(1) > +#define JZ_TIMER_CTRL_SRC_PCLK BIT(0) > + > +void __init jz4740_timer_init(void); > + > +void jz4740_timer_stop(unsigned int timer); > +void jz4740_timer_start(unsigned int timer); > +bool jz4740_timer_is_enabled(unsigned int timer); > +void jz4740_timer_enable(unsigned int timer); > +void jz4740_timer_disable(unsigned int timer); > +void jz4740_timer_set_period(unsigned int timer, uint16_t period); > +void jz4740_timer_set_duty(unsigned int timer, uint16_t duty); > +void jz4740_timer_set_count(unsigned int timer, uint16_t count); > +uint16_t jz4740_timer_get_count(unsigned int timer); > +void jz4740_timer_ack_full(unsigned int timer); > +void jz4740_timer_irq_full_enable(unsigned int timer); > +void jz4740_timer_irq_full_disable(unsigned int timer); > +uint16_t jz4740_timer_get_ctrl(unsigned int timer); > +void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl); > + > void jz4740_timer_enable_watchdog(void); > void jz4740_timer_disable_watchdog(void); > > diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c > index f83c2dd..39bb4bb 100644 > --- a/arch/mips/jz4740/time.c > +++ b/arch/mips/jz4740/time.c > @@ -20,10 +20,10 @@ > #include > > #include > +#include > #include > > #include "clock.h" > -#include "timer.h" > > #define TIMER_CLOCKEVENT 0 > #define TIMER_CLOCKSOURCE 1 > diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c > index 654d5c3..79c4354 100644 > --- a/arch/mips/jz4740/timer.c > +++ b/arch/mips/jz4740/timer.c > @@ -21,19 +21,28 @@ > > #include > > -void __iomem *jz4740_timer_base; > +#define JZ_REG_TIMER_STOP 0x0C > +#define JZ_REG_TIMER_STOP_SET 0x1C > +#define JZ_REG_TIMER_STOP_CLEAR 0x2C > +#define JZ_REG_TIMER_ENABLE 0x00 > +#define JZ_REG_TIMER_ENABLE_SET 0x04 > +#define JZ_REG_TIMER_ENABLE_CLEAR 0x08 > +#define JZ_REG_TIMER_FLAG 0x10 > +#define JZ_REG_TIMER_FLAG_SET 0x14 > +#define JZ_REG_TIMER_FLAG_CLEAR 0x18 > +#define JZ_REG_TIMER_MASK 0x20 > +#define JZ_REG_TIMER_MASK_SET 0x24 > +#define JZ_REG_TIMER_MASK_CLEAR 0x28 > > -void jz4740_timer_enable_watchdog(void) > -{ > - writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); > -} > -EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog); > +#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30) > +#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34) > +#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38) > +#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C) > > -void jz4740_timer_disable_watchdog(void) > -{ > - writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); > -} > -EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog); > +#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10) > +#define JZ_TIMER_IRQ_FULL(x) BIT(x) > + > +void __iomem *jz4740_timer_base; > > void __init jz4740_timer_init(void) > { > @@ -48,3 +57,100 @@ void __init jz4740_timer_init(void) > /* Timer irqs are unmasked by default, mask them */ > writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET); > } > + > +void jz4740_timer_stop(unsigned int timer) > +{ > + writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_stop); > + > +void jz4740_timer_start(unsigned int timer) > +{ > + writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_start); > + > +bool jz4740_timer_is_enabled(unsigned int timer) > +{ > + return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_is_enabled); > + > +void jz4740_timer_enable(unsigned int timer) > +{ > + writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_enable); > + > +void jz4740_timer_disable(unsigned int timer) > +{ > + writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_disable); > + > +void jz4740_timer_set_period(unsigned int timer, uint16_t period) > +{ > + writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer)); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_set_period); > + > +void jz4740_timer_set_duty(unsigned int timer, uint16_t duty) > +{ > + writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer)); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_set_duty); > + > +void jz4740_timer_set_count(unsigned int timer, uint16_t count) > +{ > + writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_set_count); > + > +uint16_t jz4740_timer_get_count(unsigned int timer) > +{ > + return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_get_count); > + > +void jz4740_timer_ack_full(unsigned int timer) > +{ > + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_ack_full); > + > +void jz4740_timer_irq_full_enable(unsigned int timer) > +{ > + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); > + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_irq_full_enable); > + > +void jz4740_timer_irq_full_disable(unsigned int timer) > +{ > + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_irq_full_disable); > + > +void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl) > +{ > + writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_set_ctrl); > + > +uint16_t jz4740_timer_get_ctrl(unsigned int timer) > +{ > + return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_get_ctrl); > + > +void jz4740_timer_enable_watchdog(void) > +{ > + writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog); > + > +void jz4740_timer_disable_watchdog(void) > +{ > + writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); > +} > +EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog); > diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h > deleted file mode 100644 > index fca3994..0000000 > --- a/arch/mips/jz4740/timer.h > +++ /dev/null > @@ -1,136 +0,0 @@ > -/* > - * Copyright (C) 2010, Lars-Peter Clausen > - * JZ4740 platform timer support > - * > - * This program is free software; you can redistribute it and/or modify it > - * under the terms of the GNU General Public License as published by the > - * Free Software Foundation; either version 2 of the License, or (at your > - * option) any later version. > - * > - * You should have received a copy of the GNU General Public License along > - * with this program; if not, write to the Free Software Foundation, Inc., > - * 675 Mass Ave, Cambridge, MA 02139, USA. > - * > - */ > - > -#ifndef __MIPS_JZ4740_TIMER_H__ > -#define __MIPS_JZ4740_TIMER_H__ > - > -#include > -#include > - > -#define JZ_REG_TIMER_STOP 0x0C > -#define JZ_REG_TIMER_STOP_SET 0x1C > -#define JZ_REG_TIMER_STOP_CLEAR 0x2C > -#define JZ_REG_TIMER_ENABLE 0x00 > -#define JZ_REG_TIMER_ENABLE_SET 0x04 > -#define JZ_REG_TIMER_ENABLE_CLEAR 0x08 > -#define JZ_REG_TIMER_FLAG 0x10 > -#define JZ_REG_TIMER_FLAG_SET 0x14 > -#define JZ_REG_TIMER_FLAG_CLEAR 0x18 > -#define JZ_REG_TIMER_MASK 0x20 > -#define JZ_REG_TIMER_MASK_SET 0x24 > -#define JZ_REG_TIMER_MASK_CLEAR 0x28 > - > -#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30) > -#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34) > -#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38) > -#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C) > - > -#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10) > -#define JZ_TIMER_IRQ_FULL(x) BIT(x) > - > -#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9) > -#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8) > -#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7) > -#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c > -#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3 > -#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3) > -#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3) > -#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3) > -#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3) > -#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3) > -#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3) > - > -#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET) > - > -#define JZ_TIMER_CTRL_SRC_EXT BIT(2) > -#define JZ_TIMER_CTRL_SRC_RTC BIT(1) > -#define JZ_TIMER_CTRL_SRC_PCLK BIT(0) > - > -extern void __iomem *jz4740_timer_base; > -void __init jz4740_timer_init(void); > - > -static inline void jz4740_timer_stop(unsigned int timer) > -{ > - writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); > -} > - > -static inline void jz4740_timer_start(unsigned int timer) > -{ > - writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); > -} > - > -static inline bool jz4740_timer_is_enabled(unsigned int timer) > -{ > - return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer); > -} > - > -static inline void jz4740_timer_enable(unsigned int timer) > -{ > - writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); > -} > - > -static inline void jz4740_timer_disable(unsigned int timer) > -{ > - writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); > -} > - > - > -static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period) > -{ > - writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer)); > -} > - > -static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty) > -{ > - writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer)); > -} > - > -static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count) > -{ > - writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); > -} > - > -static inline uint16_t jz4740_timer_get_count(unsigned int timer) > -{ > - return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); > -} > - > -static inline void jz4740_timer_ack_full(unsigned int timer) > -{ > - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); > -} > - > -static inline void jz4740_timer_irq_full_enable(unsigned int timer) > -{ > - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); > - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); > -} > - > -static inline void jz4740_timer_irq_full_disable(unsigned int timer) > -{ > - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); > -} > - > -static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl) > -{ > - writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); > -} > - > -static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer) > -{ > - return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); > -} > - > -#endif From lars@metafoo.de Sun Sep 2 16:48:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 16:48:50 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:65210 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901165Ab2IBOsm (ORCPT ); Sun, 2 Sep 2012 16:48:42 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 676FC78D; Sun, 2 Sep 2012 16:48:37 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id LddwGxuBLPtn; Sun, 2 Sep 2012 16:48:36 +0200 (CEST) Received: from [192.168.178.21] (ppp-88-217-76-199.dynamic.mnet-online.de [88.217.76.199]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 2733C78C; Sun, 2 Sep 2012 16:48:36 +0200 (CEST) Message-ID: <504371CE.2040707@metafoo.de> Date: Sun, 02 Sep 2012 16:48:46 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20120724 Icedove/3.0.11 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 1/3] MIPS: JZ4740: Break circular header dependency References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-2-git-send-email-thierry.reding@avionic-design.de> In-Reply-To: <1346579550-5990-2-git-send-email-thierry.reding@avionic-design.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34402 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2332 Lines: 64 On 09/02/2012 11:52 AM, Thierry Reding wrote: > When including irq.h, arch/mips/jz4740/irq.h will be selected as the > first candidate. This header does not include the proper definitions > (most notably NR_IRQS) required by subsequent headers. To solve this > arch/mips/jz4740/irq.h can be deleted and its contents can be moved > into arch/mips/include/asm/mach-jz4740/irq.h, which will then be > correctly included. > Where exactly did you have this problem? arch/mips/jz4740/ should not be in the include path, so "#include " should not cause arch/mips/jz4740/irq.h to be included. > Signed-off-by: Thierry Reding > --- > arch/mips/include/asm/mach-jz4740/irq.h | 5 +++++ > arch/mips/jz4740/irq.h | 23 ----------------------- > 2 files changed, 5 insertions(+), 23 deletions(-) > delete mode 100644 arch/mips/jz4740/irq.h > > diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h > index 5ad1a9c..aa6fd90 100644 > --- a/arch/mips/include/asm/mach-jz4740/irq.h > +++ b/arch/mips/include/asm/mach-jz4740/irq.h > @@ -54,4 +54,9 @@ > > #define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6) > > +struct irq_data; > + > +extern void jz4740_irq_suspend(struct irq_data *data); > +extern void jz4740_irq_resume(struct irq_data *data); > + > #endif > diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h > deleted file mode 100644 > index f75e39d..0000000 > --- a/arch/mips/jz4740/irq.h > +++ /dev/null > @@ -1,23 +0,0 @@ > -/* > - * Copyright (C) 2010, Lars-Peter Clausen > - * > - * This program is free software; you can redistribute it and/or modify it > - * under the terms of the GNU General Public License as published by the > - * Free Software Foundation; either version 2 of the License, or (at your > - * option) any later version. > - * > - * You should have received a copy of the GNU General Public License along > - * with this program; if not, write to the Free Software Foundation, Inc., > - * 675 Mass Ave, Cambridge, MA 02139, USA. > - * > - */ > - > -#ifndef __MIPS_JZ4740_IRQ_H__ > -#define __MIPS_JZ4740_IRQ_H__ > - > -#include > - > -extern void jz4740_irq_suspend(struct irq_data *data); > -extern void jz4740_irq_resume(struct irq_data *data); > - > -#endif From thierry.reding@avionic-design.de Sun Sep 2 21:17:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 21:17:08 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.8]:50391 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903298Ab2IBTRD (ORCPT ); Sun, 2 Sep 2012 21:17:03 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap0) with ESMTP (Nemesis) id 0MeMRD-1SxayM0xlH-00QDZe; Sun, 02 Sep 2012 21:16:57 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 9A4C12A282FD; Sun, 2 Sep 2012 21:16:56 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ytCkLN-pdj8Z; Sun, 2 Sep 2012 21:16:55 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id A8CF62A281A5; Sun, 2 Sep 2012 21:16:55 +0200 (CEST) Date: Sun, 2 Sep 2012 21:16:55 +0200 From: Thierry Reding To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 1/3] MIPS: JZ4740: Break circular header dependency Message-ID: <20120902191654.GA10843@avionic-0098.mockup.avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-2-git-send-email-thierry.reding@avionic-design.de> <504371CE.2040707@metafoo.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="RnlQjJ0d97Da+TV1" Content-Disposition: inline In-Reply-To: <504371CE.2040707@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:M79KQ3CeD1etoFC2kJLOrKUcF/Rzo7i6QvpLH/qh8dB qmaJhYUSDjyJr8r9rA01/Vcj2kB3pM33dFF4QjQJH2qYisrrFY KAZ51mRjP0JBhy0I5OilQsVU0dRbSTHQp85tu31qFXjBxnxYck xlte7LSR9bA93WaLs43Z72+YTXoJWEAC25FHscZs7uCbz9OGTh LGsw/sRGO64eXYbfF/+izvZ589Pw4JU7GcSmCgAHomhDHpyOyS GwN5JtC0Fpj36Za3h01sEWlJp0AgSC8NmJfrl0Wi6/cMu8nAnS WpCbgSueNJUJ/Z6wXBP8dkeE5408g7cJtWnUqDYGshMLhAA5q5 8SiG16mSlwE/jvdca6SVPn+Vlw2PKDdsFTKKSLBhfBBsRZ35Fm l0ZKzDW+VcAwKM//aiOOFKQZ0LpP8UbXXkiRNsguhcGCJvSR/k cSWWz X-archive-position: 34403 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2211 Lines: 55 --RnlQjJ0d97Da+TV1 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Sep 02, 2012 at 04:48:46PM +0200, Lars-Peter Clausen wrote: > On 09/02/2012 11:52 AM, Thierry Reding wrote: > > When including irq.h, arch/mips/jz4740/irq.h will be selected as the > > first candidate. This header does not include the proper definitions > > (most notably NR_IRQS) required by subsequent headers. To solve this > > arch/mips/jz4740/irq.h can be deleted and its contents can be moved > > into arch/mips/include/asm/mach-jz4740/irq.h, which will then be > > correctly included. > >=20 >=20 > Where exactly did you have this problem? arch/mips/jz4740/ should not be = in the > include path, so "#include " should not cause arch/mips/jz4740/irq= =2Eh to > be included. While compile-testing I did make ARCH=3Dmips menuconfig and selected JZ4740 plus the new PWM driver option, then ran make ARCH=3Dmips. That showed errors like struct irq_data not being declared or NR_IRQS not being defined. Maybe I was just using a very strange configuration. I tested this with 3.6-rc3 and linux-next, both had this problem. Neither of them had a default configuration for JZ4740, so maybe I'm just missing a configuration option. Thierry --RnlQjJ0d97Da+TV1 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQQ7CmAAoJEN0jrNd/PrOh47kP/04b7XC/q2SxL4vlrrgWejnx kVv1iMLZaEKM3N3LTGiOJ/ZUR5i9lWdaXG6ra7PQmalZVQXrcZYEuD1Jn1MIwj96 pCUWrbqj7S55sfQe5H3Mq2qweAt885wMFouHVbjRdt51IVl8upOlPIx/B+vJLjGi G47f5/NumPaNX84iTn/7IjWwBwmRaqkJRMOrsLFET7SITK4RaFvc0iF2gIQZRfO8 7QIq6ncv0vwxMFSUPpZYRnmM4h3MUI1Mupmw4s9MyISAL73AVWIwKyT6RUyirSSP pvW6l0/UZadtQFADzjToT8SjI2Co9GPQq0Vp60FjegC+9iwgzcmt8cAADLJ5aicv YB3/FO1c5cheISzn5N4iUwvmS8WC8S+MSU4stoyBEmFmY/eVWAeQZ2M76vQTzkpM K5ZFPHiQ7vvtnabb/1qL8DOedjsCH3MJXgRhMb5RMFPx5/jFBFI7FX3nFzbzU6s6 YtM76cvkK9VyXUBTmRi7M/NQkWdFov3ttYyINfFy1lFte3Dc9RLITfo8pe/Fz8MY dWtQO7PJwj4Di1QOAg54MdmZ8OF74x+WWvK0PFE5S6kPiU6W7cxYifwSW5wxh4Tp GUgBFfla72+EipQPqlpkwD7YGpNmtvCYYGuiaTbCjFPOPPhaUL0FNNwcLn/eGuIQ Tf3MbWs3CGZXysXsxxEA =rDF/ -----END PGP SIGNATURE----- --RnlQjJ0d97Da+TV1-- From thierry.reding@avionic-design.de Sun Sep 2 21:28:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 21:28:07 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:55000 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903298Ab2IBT2D (ORCPT ); Sun, 2 Sep 2012 21:28:03 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0MKMb4-1T8o4D3KFi-001utf; Sun, 02 Sep 2012 21:27:56 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 38D022A282FD; Sun, 2 Sep 2012 21:27:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OXJZJOtXMseP; Sun, 2 Sep 2012 21:27:53 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id A3CED2A281A5; Sun, 2 Sep 2012 21:27:53 +0200 (CEST) Date: Sun, 2 Sep 2012 21:27:53 +0200 From: Thierry Reding To: Maarten ter Huurne Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen Subject: Re: [PATCH 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Message-ID: <20120902192752.GA10930@avionic-0098.mockup.avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1890769.KjIbOv8Xbz@hyperion> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="n8g4imXOkfNTN/H1" Content-Disposition: inline In-Reply-To: <1890769.KjIbOv8Xbz@hyperion> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:dgNimggAZ/nVAOd0sKtFYtOuGdOXRt0vh+QKn+jnmVn pNmDgofn87qH/t/lsX/6t/DjRdg7HvENMRLEEBpkdvhK6sRnsO mQz0CAHRZycvws3TnSoYxvZpavopTQ3yOBYVtqgEo1mCEVzYyc EoOLgKW2w++KSwckn+/bT/qdJg+GVFK7T4KP4+9C8eebcwlJCv ueU8h7wLFXF7p+WC6YDw+l1KFi3eW2Z0PqPRL2R6r3fiWzAp2N E4MIv9VekvlxtQq+p6UiuBcWt56G00dS65ThW+o9OgbqKCipGi N101S9dSPd3QsPqCk/Cj4KBA0zqaGm0t54SIq7RLo0aAM+5cQq +Tcynyo6qU29V12W1aDoRGbsU9KSSemXSxRwa4pqDsLxCjzzcI FNju8O4+8Ng1DZeNtSq6Aef7s0fBG+FD+g= X-archive-position: 34404 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4355 Lines: 122 --n8g4imXOkfNTN/H1 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Sep 02, 2012 at 03:25:55PM +0200, Maarten ter Huurne wrote: > On Sunday 02 September 2012 11:52:27 Thierry Reding wrote: >=20 > > This small series fixes a build error due to a circular header > > dependency, exports the timer API so it can be used outside of > > the arch/mips/jz4740 tree and finally moves and converts the > > JZ4740 PWM driver to the PWM framework. > >=20 > > Note that I don't have any hardware to test this on, so I had to > > rely on compile tests only. Patches 1 and 2 should probably go > > through the MIPS tree, while I can take patch 3 through the PWM > > tree. It touches a couple of files in arch/mips but the changes > > are unlikely to cause conflicts. >=20 > Exporting the hardware outputs PWM2-7 as index 0-5 in the PWM core is rat= her=20 > confusing. I discussed with Lars on IRC and it's probably better to expos= e=20 > PWM0-7 through the API, but refuse to hand out PWM0 and PWM1 when request= ed,=20 > since their associated timers are in use by the system. I attached a diff= =20 > that illustrates this approach. >=20 > Note that if this approach is taken, the beeper ID in board-qi_lb60.c sho= uld=20 > be changed back from 2 to 4, since the beeper is attached to PWM4. >=20 > I tested the "for-next" branch on the Dingoo A320 with the pwm-backlight= =20 > driver. It didn't work at first, because the PWM number and the timer num= ber=20 > didn't align: I requested PWM number 5 to get PWM7 and the GPIO of PWM7 w= as=20 > used, but with timer 5 instead of timer 7, resulting in a dark screen.=20 > However, it works fine after adding PWM0/1 as described above. I haven't seen any usage of the pwm-backlight driver in mainline. I assume this is only present in some downstream repository? > If other people want to test on real hardware, you can find the code in= =20 > branch jz-3.6-rc2-pwm in the qi-kernel repository. Unfortunately our web= =20 > interface for git is still broken, but the repo itself is fine. > git://projects.qi-hardware.com/qi-kernel.git >=20 > Bye, > Maarten > diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c > index db29b37..554e414 100644 > --- a/drivers/pwm/pwm-jz4740.c > +++ b/drivers/pwm/pwm-jz4740.c > @@ -24,9 +24,11 @@ > #include > #include > =20 > -#define NUM_PWM 6 > +#define NUM_PWM 8 > =20 > static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] =3D { > + JZ_GPIO_PWM0, > + JZ_GPIO_PWM1, > JZ_GPIO_PWM2, > JZ_GPIO_PWM3, > JZ_GPIO_PWM4, > @@ -50,6 +52,13 @@ static int jz4740_pwm_request(struct pwm_chip *chip, s= truct pwm_device *pwm) > unsigned int gpio =3D jz4740_pwm_gpio_list[pwm->hwpwm]; > int ret; > =20 > + /* > + * Timer 0 and 1 are used for system tasks, so they are unavailable > + * for use as PWMs. > + */ > + if (pwm->hwpwm < 2) > + return -EBUSY; > + > ret =3D gpio_request(gpio, pwm->label); > =20 > if (ret) { An alternative approach would be to change pwm_chip.base from -1 (dynamically allocated) to 2, which would leave 0 and 1 unavailable. That should at least solve the problem that you had regarding the GPIO and timer mismatch. But the above also sounds sensible, and since both you and Lars agree that this is the better option, I can squash these changes into my patch with your permission. Thierry --n8g4imXOkfNTN/H1 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQQ7M4AAoJEN0jrNd/PrOhCE8QAMIDtLnVUn8z+sH+ybggaN6m QACwD4L+el+pXo0qFWQNKX5hrd5otSmHIVduRdZmUsD8k3G503jP3NQzJ5wUxyXl PTtfSf6rifk82R0BFSNCOwqo7yiv4oWwdOmZC87W1tGHHW3QaN9zRaf4o9rHcHOj wsSCqIY3KKvfWHrYkx+45XF4UmvES8UpMdio6nETDsp4+WOIzDzqh2JNGFAcmqkF kSEVwITKW1UKEW+JUY7JCcGZ0CMQvrk9r2tefrucis03zX+qWZM3d6PJ+ItAbt9U qc7ML6y33FItdQMnAqX/gaYD8WlqQPh7Lk2CcxKFJuVr/DQhvCB4sWnvj7jOOoIi qvhdhejBaMN1SR95Evm7myzLnYply6RNXMwWv+RAwIdcvgCkK7luVcJ0N7mWK55H c2fOus+eCEsrE5plIUvA8nrvIyD6Sqfe8ybu0ziBi1WYZWnpdoMSNfUVBq1zSz4e LKJBxZUMp/91CS/Q+MAVLGzRpz22eoGCc4EbDOHkz4fGWqToNBPXKJ/dazJdPJvh 1zsxAMOZADNKl3+1/bH1nGCo2EhD8Tp0SlA/FRpp+ApBfQfyXNkYGEEBm3AuR2BT xhZ4U8pV6GlGcJmEICtF2MiHTzk1goI70e21GPpf+H+NQyc/73d0XsEcHT0D/K55 gWXr/To/HbvzIS3d5M5B =EIhv -----END PGP SIGNATURE----- --n8g4imXOkfNTN/H1-- From thierry.reding@avionic-design.de Sun Sep 2 21:59:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 21:59:36 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:52192 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903298Ab2IBT73 (ORCPT ); Sun, 2 Sep 2012 21:59:29 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu1) with ESMTP (Nemesis) id 0Lx3Ub-1TerCr38av-017DAg; Sun, 02 Sep 2012 21:59:21 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 2B9DC2A282FD; Sun, 2 Sep 2012 21:59:20 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZWVSEbkBu9Sl; Sun, 2 Sep 2012 21:59:18 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 4095E2A281A5; Sun, 2 Sep 2012 21:59:18 +0200 (CEST) Date: Sun, 2 Sep 2012 21:59:17 +0200 From: Thierry Reding To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 3/3] pwm: Add Ingenic JZ4740 support Message-ID: <20120902195917.GB10930@avionic-0098.mockup.avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-4-git-send-email-thierry.reding@avionic-design.de> <504370BF.6090702@metafoo.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="dc+cDN39EJAMEtIO" Content-Disposition: inline In-Reply-To: <504370BF.6090702@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:PnTmiHAzihGawP3wR8kWu0bPTPilCuLUqbUVl0/GwvS 9d8mIm5WUQXtd3LOJxAWkknNpbnJRnbr2VYpSAo7UNdFRSIkid /F3XWdEppoPqP0uggjkqbY2GxkGsvT6YlqaZoLILFZrVQap74X muxPA1Du99LupIGtu14lA539FoswtLGnGLXXG4uUC4lcI4WXzC iHJUzqVV7fdMnYSE1M9qXIAseMB64xe59A0x40J+f11QsfrNe3 S7E5BrPcf+SA7quJtrMj78UwaG7s3DbW6v+o5T46AX8AO7bQDu Ka0nW2MeYnEw+z7D5BDXQiPDdTL098jyoBBtKvveiEaiVCnaJF xAQAnVKJMNUacG+JN+BtiYzDZ2MxzibhqnC3sjzLkmvr9Rcz5F +NbQNgow878lWWap9SHxT8JOhQKSR04/aY= X-archive-position: 34405 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6857 Lines: 235 --dc+cDN39EJAMEtIO Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Sep 02, 2012 at 04:44:15PM +0200, Lars-Peter Clausen wrote: > On 09/02/2012 11:52 AM, Thierry Reding wrote: > > diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c > > index 92b1782..f5acdaa 100644 > > --- a/drivers/pwm/core.c > > +++ b/drivers/pwm/core.c > > @@ -371,7 +371,7 @@ EXPORT_SYMBOL_GPL(pwm_free); > > */ > > int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > > { > > - if (!pwm || period_ns =3D=3D 0 || duty_ns > period_ns) > > + if (!pwm || duty_ns < 0 || period_ns <=3D 0 || duty_ns > period_ns) > > return -EINVAL; > > =20 >=20 > This change seems to be unrelated. Yes, that slipped in by mistake. That was supposed to go into a separate patch so that the .config of each driver doesn't have to repeat these checks. > > return pwm->chip->ops->config(pwm->chip, pwm, duty_ns, period_ns); > > diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c > > new file mode 100644 > > index 0000000..db29b37 > > --- /dev/null > > +++ b/drivers/pwm/pwm-jz4740.c > > @@ -0,0 +1,205 @@ > > +/* > > + * Copyright (C) 2010, Lars-Peter Clausen > > + * JZ4740 platform PWM support > > + * > > + * This program is free software; you can redistribute it and/or modi= fy it > > + * under the terms of the GNU General Public License as published b= y the > > + * Free Software Foundation; either version 2 of the License, or (at= your > > + * option) any later version. > > + * > > + * You should have received a copy of the GNU General Public License = along > > + * with this program; if not, write to the Free Software Foundation, = Inc., > > + * 675 Mass Ave, Cambridge, MA 02139, USA. > > + * > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > +#include >=20 > #include >=20 > > + > > +#define NUM_PWM 6 > > + > > +static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] =3D { >=20 > As mth said, it would be better to have JZ_GPIO_PWM0 and here as well and= set > NUM_PWM to 8. Right now we are using the timers associated to PWM channel= 0 and > 1 as system timers. But there might be devices where this is not possible= , e.g. > because the PWM is actually connected to something. Also this fixes the o= f by > two for the hwpwm id. Okay. I was actually planning on doing some cleanup in a follow-up patch and try to limit actual changes in this patch to what is required by the conversion. However if Maarten and you both are okay with it I can make these additional changes while at it. > > + if (ret) { > > + printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret); >=20 > dev_err(chip->dev, .... Okay. > > + is_enabled =3D jz4740_timer_is_enabled(pwm->hwpwm); > > + if (is_enabled) > > + pwm_disable(pwm); >=20 > I think this should be jz4740_pwm_disable >=20 > > + > > + jz4740_timer_set_count(pwm->hwpwm, 0); > > + jz4740_timer_set_duty(pwm->hwpwm, duty); > > + jz4740_timer_set_period(pwm->hwpwm, period); > > + > > + ctrl =3D JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | > > + JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; > > + > > + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); > > + > > + if (is_enabled) > > + pwm_enable(pwm); >=20 > and jz4740_pwm_enable here. I wonder if this is actually required here. Can the timer really not be reprogrammed while enabled? > > + > > + return 0; > > +} > > + >=20 > > + > > +static const struct pwm_ops jz4740_pwm_ops =3D { > > + .request =3D jz4740_pwm_request, > > + .free =3D jz4740_pwm_free, > > + .config =3D jz4740_pwm_config, > > + .enable =3D jz4740_pwm_enable, > > + .disable =3D jz4740_pwm_disable, >=20 > .owner =3D THIS_MODULE, Yes, I forgot that one. > > +}; > > + > > +static int jz4740_pwm_probe(struct platform_device *pdev) > __devinit Yes, I'll add that. > > +{ > > + struct jz4740_pwm_chip *jz4740; > > + int ret =3D 0; >=20 > The '=3D 0' is not really necessary since it will be overwritten anyway. Right, I'll drop it. > > +static int jz4740_pwm_remove(struct platform_device *pdev) > __devexit Can do. > > +{ > > + struct jz4740_pwm_chip *jz4740 =3D platform_get_drvdata(pdev); > > + int ret; > > + > > + ret =3D pwmchip_remove(&jz4740->chip); > > + if (ret < 0) > > + return ret; >=20 > remove is not really allowed to fail, the return value is never really te= sted > and the device is removed nevertheless. But this seems to be a problem wi= th the > PWM API. It should be possible to remove a PWM chip even if it is current= ly in > use and after a PWM chip has been removed all calls to a pwm_device of th= at > chip it should return an error. This will require reference counting for = the > pwm_device struct though. E.g. by adding a 'struct device' to it. I beg to differ. It shouldn't be possible to remove a PWM chip that provides requested PWM devices. All other drivers do the same here. > > + > > + clk_put(jz4740->clk); > > + > > + return 0; > > +} > > + > > +static struct platform_driver jz4740_pwm_driver =3D { > > + .driver =3D { > > + .name =3D "jz4740-pwm", >=20 > .owner =3D THIS_MODULE, There are a number of other drivers where this is missing. I'll make a note to add it to those as well. > > + }, > > + .probe =3D jz4740_pwm_probe, > > + .remove =3D jz4740_pwm_remove, >=20 > .remove =3D __devexit_p(jz4740_pwm_remove), Yes. >=20 > > +}; > > +module_platform_driver(jz4740_pwm_driver); >=20 > MODULE_LICENSE(...), MODULE_AUTHOR(...), MODULE_DESCRIPTION(...), MODULE_= ALIAS(...) Those weren't present previously. I suppose they should be "GPL", you, "Ingenic JZ4740 PWM driver" and "platform:jz4740-pwm", respectively? Thierry --dc+cDN39EJAMEtIO Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQQ7qVAAoJEN0jrNd/PrOhDG4P/igXgZNIdiGYvb5vkxCiwaL6 qtnc9r4I+lv4j9LjS1QMz/wTkQ6jw3inPqlLt0hYZ2PX9a+fSeevzaMRDscqnk/W yqRA1cHAKa+SDRI0gf/G73tZ8tX7Ntxl9i8/hiSvHk0ohzTNJNRM35e1EBhPb5bt wNSa5p/nH01ZeRM3CHpmfItOFGDF4WBpjzrniY967ZvnPU4bSoLozhGUwroEMlfW eBJagUVQz5lscZL41szSY11mCzPWvYORMWz6YDfem21DQ/OLR6ZVdu6cgpxE1Bj/ Mu/cnQ/FVABxubzxVEaasTFmWfRflCXOEJm3L5zDcBJqVCvCzokeKm5NPFQS3zWQ XUQ+tcec1zH5T9Xmq//flqYDn+8fme09dAEBUTqri6zKnxkVUGOUzp0AHXv4iYVF J9O8BgPkhA0+zk68hIJ7q5blVqnSFTtZk5mxJ10sI5/d5T7kRgNnRZ7tS6AwErpP AIH8GmCC86XURsdSYlWwy07rhWzKp/+u03JWvQrD+uRZQoBOrm7jVxaA3LX5+J0A YUpyCGNP5h9Jd/s/kAvEIEbByiSikibnzx7CII0i4HTmxodocVbPUD5rHI8NMIgs ErKoZTcdBFxzyTr2f+QBRbZBe/z95Orj070R+KL0G7J6Z2igpR7ZZWXLnZabE9ZB QQ7RUtbt80cY4aP+fP2z =XQVe -----END PGP SIGNATURE----- --dc+cDN39EJAMEtIO-- From thierry.reding@avionic-design.de Sun Sep 2 22:21:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 22:21:42 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.10]:56038 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903298Ab2IBUVg (ORCPT ); Sun, 2 Sep 2012 22:21:36 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu3) with ESMTP (Nemesis) id 0M0XGM-1TSX2v3tja-00usJK; Sun, 02 Sep 2012 22:21:28 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 35C682A282FF; Sun, 2 Sep 2012 22:21:27 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VetcsFmHd-VH; Sun, 2 Sep 2012 22:21:25 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 684022A281A5; Sun, 2 Sep 2012 22:21:25 +0200 (CEST) Date: Sun, 2 Sep 2012 22:21:24 +0200 From: Thierry Reding To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 2/3] MIPS: JZ4740: Export timer API Message-ID: <20120902202124.GA21635@avionic-0098.mockup.avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-3-git-send-email-thierry.reding@avionic-design.de> <50437117.8000700@metafoo.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="4Ckj6UjgE2iN1+kY" Content-Disposition: inline In-Reply-To: <50437117.8000700@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:Lsn7QrQZlRfOtc4MZYuacR9C1PNcxaPad9pAFM5RS7o TqYXfEYcyIjhMDaLUq/W62J/76luUhB1bvM2ESY37hcx9yU3sn OPQTJZa88oQqSKdogfPqKXuyxuPav8Kr7ZLiBiz+hECSxGd9Lf YAF5vQMcggw1H8ykDnIVDDBR9RbyEBMip2oXTkWRTreEST+tpi Mcyv70WoJkcRAeQgHc/cpHXxY3NKbz5Q7wrMbob3xDBD2Cs27V gHBJ80i0QKCFazGsJ71IynAr31lZjlc5Ub9aWJZchyRZQpE1CM rEmJBFQAbHzHhZgIuiECl+0qHPQO9XeUtg4SXpjIPT3nfT3KF1 42d5cH9h5TUspfaUaB0IDymfWrJwop7dcxfPkmHFrf5e403Cwu VigStsoz0XHag+rFQUop/PtiM9D4WrotXI= X-archive-position: 34406 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1721 Lines: 46 --4Ckj6UjgE2iN1+kY Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Sep 02, 2012 at 04:45:43PM +0200, Lars-Peter Clausen wrote: > On 09/02/2012 11:52 AM, Thierry Reding wrote: > > This is a prerequisite for allowing the PWM driver to be converted to > > the PWM framework. > >=20 > > Signed-off-by: Thierry Reding >=20 > I'd prefer to keep the timer functions inline, some of them are called qu= ite > often in the system clock code. I've opted for this variant because it better hides the register values. If the functions are inlined it also means the complete register definitions need to go into timer.h. If you don't think that's an issue, I can update the patch accordingly. Thierry --4Ckj6UjgE2iN1+kY Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQQ7/EAAoJEN0jrNd/PrOhOicP/3Bl1HCJf7GLPkSzeCpoQFNA pDjyGpKgQn68wn+QNV53GlRwk9KheahF+MJ35tPYJrMuV/lv+A/zDjaE4gKM9hEZ 0BRNer/A+JRRE5JXt9cDEv5XBt8HRLOesfTHIt3gB0Wu5ohQInqmOs2sSTznq6IZ LCQTgjuKFfCGQVV9eVvc1P4BZLDJiAbBuYwSdK1amW0lNUWjiZeT3I2/s4s950xF Nn18ByEcnnxSIg1HdbqPu+db+OYnvTk8iC2KYnIL2TO4evtx5LFMm3qELNjj+bEs go6CLnSgJruRPnLRaP5Iibj2cn4AsBY+4+BOq3aWP9RNZBCoCk4m8ff8m5iUbARy 1BZEMb0IPmkK1cfqPnU7kK73rTsFE/ZDPJe7ZHJQ+OXXZ46MOxWdb97O8cfn7j1o QjCk9S6KF0yAxiuJQfLTzSu7h6qboceR4+hwdGXazHWuKt6Sxl6KqsTo2H1SYInv rrr5Pfn9TICQpYGpMPdA3dO4cSneSzC9hoos68mTHgB18E0wTbmcrd+YvMnoJSNu FME9UEJMU+6WrVgGHV79YQ2rBF30qqeXVIV411Qy1EyE50XlTvp79YfnJb5+Qjsn x4habdpkr+0BbLw+o5DFpob7Xelq34TVETUTD+POAvycVpdxghWR2xajbl7MukFg B8cZa7pRCQiXVyKOrPyR =BD1p -----END PGP SIGNATURE----- --4Ckj6UjgE2iN1+kY-- From lars@metafoo.de Sun Sep 2 22:22:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 22:22:53 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:57651 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903299Ab2IBUWr (ORCPT ); Sun, 2 Sep 2012 22:22:47 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 7CE08FA3; Sun, 2 Sep 2012 22:22:37 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 3nDQm1eJTp0w; Sun, 2 Sep 2012 22:22:36 +0200 (CEST) Received: from [192.168.178.21] (ppp-88-217-76-199.dynamic.mnet-online.de [88.217.76.199]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 14AF5F9B; Sun, 2 Sep 2012 22:22:18 +0200 (CEST) Message-ID: <5043C005.8060907@metafoo.de> Date: Sun, 02 Sep 2012 22:22:29 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20120724 Icedove/3.0.11 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 3/3] pwm: Add Ingenic JZ4740 support References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-4-git-send-email-thierry.reding@avionic-design.de> <504370BF.6090702@metafoo.de> <20120902195917.GB10930@avionic-0098.mockup.avionic-design.de> In-Reply-To: <20120902195917.GB10930@avionic-0098.mockup.avionic-design.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34407 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2536 Lines: 67 On 09/02/2012 09:59 PM, Thierry Reding wrote: >>> + is_enabled = jz4740_timer_is_enabled(pwm->hwpwm); >>> + if (is_enabled) >>> + pwm_disable(pwm); >> >> I think this should be jz4740_pwm_disable >> >>> + >>> + jz4740_timer_set_count(pwm->hwpwm, 0); >>> + jz4740_timer_set_duty(pwm->hwpwm, duty); >>> + jz4740_timer_set_period(pwm->hwpwm, period); >>> + >>> + ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | >>> + JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; >>> + >>> + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); >>> + >>> + if (is_enabled) >>> + pwm_enable(pwm); >> >> and jz4740_pwm_enable here. > > I wonder if this is actually required here. Can the timer really not be > reprogrammed while enabled? > It can, but we've observed this to cause permanent glitches until the timer is reprogrammed again. >>> +{ >>> + struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev); >>> + int ret; >>> + >>> + ret = pwmchip_remove(&jz4740->chip); >>> + if (ret < 0) >>> + return ret; >> >> remove is not really allowed to fail, the return value is never really tested >> and the device is removed nevertheless. But this seems to be a problem with the >> PWM API. It should be possible to remove a PWM chip even if it is currently in >> use and after a PWM chip has been removed all calls to a pwm_device of that >> chip it should return an error. This will require reference counting for the >> pwm_device struct though. E.g. by adding a 'struct device' to it. > > I beg to differ. It shouldn't be possible to remove a PWM chip that > provides requested PWM devices. All other drivers do the same here. Part of the Linux device driver model is that that a device may appear or disappear at any given time (if the kernel has been compiled with CONFIG_HOTPLUG). So you can't prevent removal. The fact that the remove callback function return an int is kind of misleading and should probably be fixed at some point. The return value is never checked and the device will be removed nevertheless. So the PWM subsystem must cope with the case where the PWM chip is removed while some of its pwm_devices are still in use. [...] >> >>> +}; >>> +module_platform_driver(jz4740_pwm_driver); >> >> MODULE_LICENSE(...), MODULE_AUTHOR(...), MODULE_DESCRIPTION(...), MODULE_ALIAS(...) > > Those weren't present previously. I suppose they should be "GPL", you, > "Ingenic JZ4740 PWM driver" and "platform:jz4740-pwm", respectively? Yes, sounds good. The old code couldn't be build as a module, so these were not necessary previously. From lars@metafoo.de Sun Sep 2 22:27:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 22:27:40 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:57942 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903298Ab2IBU1e (ORCPT ); Sun, 2 Sep 2012 22:27:34 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id E0231FBE; Sun, 2 Sep 2012 22:27:28 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id Ho4kJNmqDFy1; Sun, 2 Sep 2012 22:27:28 +0200 (CEST) Received: from [192.168.178.21] (ppp-88-217-76-199.dynamic.mnet-online.de [88.217.76.199]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id BE907FBD; Sun, 2 Sep 2012 22:27:27 +0200 (CEST) Message-ID: <5043C139.2010700@metafoo.de> Date: Sun, 02 Sep 2012 22:27:37 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20120724 Icedove/3.0.11 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 2/3] MIPS: JZ4740: Export timer API References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-3-git-send-email-thierry.reding@avionic-design.de> <50437117.8000700@metafoo.de> <20120902202124.GA21635@avionic-0098.mockup.avionic-design.de> In-Reply-To: <20120902202124.GA21635@avionic-0098.mockup.avionic-design.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34408 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 849 Lines: 21 On 09/02/2012 10:21 PM, Thierry Reding wrote: > On Sun, Sep 02, 2012 at 04:45:43PM +0200, Lars-Peter Clausen wrote: >> On 09/02/2012 11:52 AM, Thierry Reding wrote: >>> This is a prerequisite for allowing the PWM driver to be converted to >>> the PWM framework. >>> >>> Signed-off-by: Thierry Reding >> >> I'd prefer to keep the timer functions inline, some of them are called quite >> often in the system clock code. > > I've opted for this variant because it better hides the register values. > If the functions are inlined it also means the complete register > definitions need to go into timer.h. If you don't think that's an issue, > I can update the patch accordingly. > It's not pretty, but it should be ok. Having a single global function for each and every register access is kind of ugly too. - Lars From thierry.reding@avionic-design.de Sun Sep 2 22:37:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 22:37:37 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.10]:61075 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903298Ab2IBUha (ORCPT ); Sun, 2 Sep 2012 22:37:30 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap3) with ESMTP (Nemesis) id 0LtWNA-1TZbPc4AFw-010yBN; Sun, 02 Sep 2012 22:37:25 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 66B0D2A282FF; Sun, 2 Sep 2012 22:37:24 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OSxNO4+ENm2G; Sun, 2 Sep 2012 22:37:23 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 03E602A281A5; Sun, 2 Sep 2012 22:37:22 +0200 (CEST) Date: Sun, 2 Sep 2012 22:37:22 +0200 From: Thierry Reding To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 3/3] pwm: Add Ingenic JZ4740 support Message-ID: <20120902203722.GB21635@avionic-0098.mockup.avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-4-git-send-email-thierry.reding@avionic-design.de> <504370BF.6090702@metafoo.de> <20120902195917.GB10930@avionic-0098.mockup.avionic-design.de> <5043C005.8060907@metafoo.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="NDin8bjvE/0mNLFQ" Content-Disposition: inline In-Reply-To: <5043C005.8060907@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:SudN5a3td9UblLE96xwNPwHEutfAsj2xYqyS/CAFkMN 73hOWvKj+5Kcsg8j1EqCM3FVdY16fSsKiGFKiZeykbbLVOgE61 a4DParbi1BF2vSArlDbeUAT+pQtL3rpuxSOfuCuAa5krcLfzJg I+VJi+jLOltYR23KlAMnSa6pl+nupWovkeA1CNKRSqDNQrQUpY zm4CGXczAv23PsV4cJYNzUStNWc9bDFbRbOOVVltXDAd9Fx7Xz gpOOOgEkoxMI6WlH7mdQ98W+QY9ce8xEfLsSfLV6csCne9rL/3 QNMp8t6WDq5GrdMZAMNgjrVehRjmoO61QezUun8GX4buKSg3L/ poQJDEJnfQjfcqsLxwHakPs77PpOxxidC0/L/G6oE55pRkzDeJ iAe/1Hq8+UXaWwr7ceEOplA0CF7PHsjwgQC3hCTR7N+Eh3LjYA vCbN/ X-archive-position: 34409 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4115 Lines: 110 --NDin8bjvE/0mNLFQ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Sep 02, 2012 at 10:22:29PM +0200, Lars-Peter Clausen wrote: > On 09/02/2012 09:59 PM, Thierry Reding wrote: > >>> + is_enabled =3D jz4740_timer_is_enabled(pwm->hwpwm); > >>> + if (is_enabled) > >>> + pwm_disable(pwm); > >> > >> I think this should be jz4740_pwm_disable > >> > >>> + > >>> + jz4740_timer_set_count(pwm->hwpwm, 0); > >>> + jz4740_timer_set_duty(pwm->hwpwm, duty); > >>> + jz4740_timer_set_period(pwm->hwpwm, period); > >>> + > >>> + ctrl =3D JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT= | > >>> + JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; > >>> + > >>> + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); > >>> + > >>> + if (is_enabled) > >>> + pwm_enable(pwm); > >> > >> and jz4740_pwm_enable here. > >=20 > > I wonder if this is actually required here. Can the timer really not be > > reprogrammed while enabled? > > >=20 > It can, but we've observed this to cause permanent glitches until the tim= er is > reprogrammed again. Okay. I've changed this to use jz4740_pwm_{enable,disable}() instead. > >>> +{ > >>> + struct jz4740_pwm_chip *jz4740 =3D platform_get_drvdata(pdev); > >>> + int ret; > >>> + > >>> + ret =3D pwmchip_remove(&jz4740->chip); > >>> + if (ret < 0) > >>> + return ret; > >> > >> remove is not really allowed to fail, the return value is never really= tested > >> and the device is removed nevertheless. But this seems to be a problem= with the > >> PWM API. It should be possible to remove a PWM chip even if it is curr= ently in > >> use and after a PWM chip has been removed all calls to a pwm_device of= that > >> chip it should return an error. This will require reference counting f= or the > >> pwm_device struct though. E.g. by adding a 'struct device' to it. > >=20 > > I beg to differ. It shouldn't be possible to remove a PWM chip that > > provides requested PWM devices. All other drivers do the same here. >=20 > Part of the Linux device driver model is that that a device may appear or > disappear at any given time (if the kernel has been compiled with > CONFIG_HOTPLUG). So you can't prevent removal. The fact that the remove > callback function return an int is kind of misleading and should probably= be > fixed at some point. The return value is never checked and the device wil= l be > removed nevertheless. So the PWM subsystem must cope with the case where = the > PWM chip is removed while some of its pwm_devices are still in use. I thought I had seen this work. But looking at the code, you're right. Perhaps what I saw was caused by the reference counting done on the pwm_ops structure. At least that keeps the module from being unloaded if there are still any requested PWM devices, but it won't help if the device suddenly goes away. I wonder if that's a realistic use-case, though, at least for platform devices. I currently can't run any tests because I don't have any hardware available. I'll need to take another look when I'm back at work next week and think of a way to solve this. Adding some reference counting as you suggested earlier may be the only way. Thierry --NDin8bjvE/0mNLFQ Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQQ8OCAAoJEN0jrNd/PrOhLdIQAJBjhBAuvLgaIR7M2Im0Up5C v+mUCGpF+cRzies9nxi255SuZTX7UnNnBvkJ2O0LAMJycfawGxZbl3sUdDD4MWFU VJdAgSMP1hHBizNdE1rATSV7saKo7bqOZdmOoooCRmVOobjLkVD1qvOk4IxY2vYd 0Z59wM4ZQOCq/PGuUgMCAA2FjGOPP4C6rghBQSQlxNbO8bAJjHAAOuUUbaAmclJQ triXc/Anc3pM5md/GdMkp0egB6wqdX2FGAgMNN7BsSkEEN9knZEcuducJnwT2ifY OSVVD1gchCKAOLtY3AVIoB5WIkU4mLn91AOek6uoUNDeP8PJnGOPpjuVW7tBvlHn xjOlrUId5rYSUAjBAg3gH8hzPMClQYZh+53rm6ZAY9crW76yV4roTilYqMsbdVFL 75G7FQ6Mdbm6jnB7+uO3tzizxSb3Rixvu5SiHZDqhT6WaSgkf1urAkCjxOUmsfAF aaJm9Csl4+FWe+UJAnHLCazENyVrPVM2Keqlk51J4R6q4J6qsWk57BBPSeR9DQFQ 17+sJF+d9TShrXhPbrzxkw5zdfMbV3CJ8jcJ36MQk23MVtJ7awLsi5CyOzy6zzLU D9wkgEA99n2mom8YeU6Fjn84kbhRzriU3uxuYdl7wC9PQqvQU6ndDTjUZG3JERzW upBchj7N+Y5AvIeqzRAf =ERXA -----END PGP SIGNATURE----- --NDin8bjvE/0mNLFQ-- From thierry.reding@avionic-design.de Sun Sep 2 22:46:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 22:46:48 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.10]:62475 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903298Ab2IBUql (ORCPT ); Sun, 2 Sep 2012 22:46:41 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap0) with ESMTP (Nemesis) id 0MKKU2-1T8p1e1LRm-001eOo; Sun, 02 Sep 2012 22:46:28 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id A827F2A282FF; Sun, 2 Sep 2012 22:46:27 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qdN7B+usgmFY; Sun, 2 Sep 2012 22:46:25 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 44B042A281A5; Sun, 2 Sep 2012 22:46:25 +0200 (CEST) Date: Sun, 2 Sep 2012 22:46:24 +0200 From: Thierry Reding To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH 2/3] MIPS: JZ4740: Export timer API Message-ID: <20120902204624.GC21635@avionic-0098.mockup.avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1346579550-5990-3-git-send-email-thierry.reding@avionic-design.de> <50437117.8000700@metafoo.de> <20120902202124.GA21635@avionic-0098.mockup.avionic-design.de> <5043C139.2010700@metafoo.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Fig2xvG2VGoz8o/s" Content-Disposition: inline In-Reply-To: <5043C139.2010700@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:57/T1gPWzzr1/CoW8o5/G+57k2wz3faaVfTNA3CP/FC Pkdaq2pTSXRlkfO45pgrXaIQ6wK+5SXN7EeForI0NpDZY4l2d6 jvDtyVB7ISc2lllOg/iQLrCSgbscfJvCR5CA1+rACjs9I/IVhY GRCZr8OsxcvMDj8J2sEvKQ77C6PgWvIAv7f1C8pdQ+gTgzwoDK x/l8YMYrMWaxX2X2A0SMzEis0iVahyitWVyLAP7ycJwps8c6Zq VFY+SZDsnlzQ3CHp+BCxACXtpI+fo84rwNYhuPjLwW/C4HNOof I47KFBLmjP/ChscQ4r1TYVBd5V9Kz1lCxVw5kQavTo2zRAsz1C GzwfSylEMfK71PX1RD82psyIp1dceRMn+TxDjfXFr3JhPPVU6u F6AnENONWxXJIgBDlbnSzNziioJLQQ/95gPX7VRNAeQDmAgj/T ry4Vc X-archive-position: 34410 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2286 Lines: 58 --Fig2xvG2VGoz8o/s Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Sep 02, 2012 at 10:27:37PM +0200, Lars-Peter Clausen wrote: > On 09/02/2012 10:21 PM, Thierry Reding wrote: > > On Sun, Sep 02, 2012 at 04:45:43PM +0200, Lars-Peter Clausen wrote: > >> On 09/02/2012 11:52 AM, Thierry Reding wrote: > >>> This is a prerequisite for allowing the PWM driver to be converted to > >>> the PWM framework. > >>> > >>> Signed-off-by: Thierry Reding > >> > >> I'd prefer to keep the timer functions inline, some of them are called= quite > >> often in the system clock code. > >=20 > > I've opted for this variant because it better hides the register values. > > If the functions are inlined it also means the complete register > > definitions need to go into timer.h. If you don't think that's an issue, > > I can update the patch accordingly. > >=20 >=20 > It's not pretty, but it should be ok. Having a single global function for= each > and every register access is kind of ugly too. Okay, I'll update the patch accordingly. I probably won't get around to it until later this week because I won't have access to a computer for a few days but I'll be back at work on September 10 and should be able to send the next version of this series out then. Thierry --Fig2xvG2VGoz8o/s Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQQ8WgAAoJEN0jrNd/PrOhm+EP/0Adl62IwELOR83e+uqIEADM +aLp3NHggdPe77rf/Tjn6zooAS7aPFnsqpave99BP8f5SzzbPI3i5GQRUVwA6TdP n+ivzgX5R8ml/5XqYtvX3y086c+1/1axvnj6D6FqJ/v/SN10I9GioiPMFtYwcK/S RfMvnlltpfcmO/ysvbXODnmlWEHb6oOUnzfVfQpd6SvCGQbJTeVMCZuNw5hMHKbs gg5SC/tDmsfrIqj7xuoXj9n9Ct+MH64hv8V5rDOmPqXM3RYG4XWX1d0nIYP1RCIi pijBA3q7jTlOrV7pHV+F0os15U/AagXlFZIRJAbcCuiNgIMd4FKqgM3AwHV+bhgT JzmTaEyS5F34keMbY/4qnn5B/cFRhHDURg5z9Yo7mDnkYjWbOifj15cgjYZHZEZe YAqhmhLm71IQRmrqTc81QZpigwttlHzG46DsJoUyvuxabMIHRZKMo2vlTydbbp5r bpqu3xF8jJkauORIKXNvKaeX9zfpFKOy4QRnCYSpFczMjNeYc+E9iPNBVuNHCYy5 L68uIK88nzFikNRoEStJdHUKsu9W9H9QDBPrnzIMbgqOJp1ab/i8QW59sRm4dPf+ jSXpiV/3JJX9JBGiCKq8lOxZzm+Xlg7QZbfooCvmzxyQWrrD8kl79sqtTNaYxTn9 uyrYOCe0nDpcxMOunq0F =TXny -----END PGP SIGNATURE----- --Fig2xvG2VGoz8o/s-- From maarten@treewalker.org Sun Sep 2 23:39:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Sep 2012 23:39:48 +0200 (CEST) Received: from smtp-vbr4.xs4all.nl ([194.109.24.24]:4573 "EHLO smtp-vbr4.xs4all.nl" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903299Ab2IBVjl (ORCPT ); Sun, 2 Sep 2012 23:39:41 +0200 Received: from starbug-2.trinair2002 (dhcp-089-098-069-120.chello.nl [89.98.69.120]) (authenticated bits=0) by smtp-vbr4.xs4all.nl (8.13.8/8.13.8) with ESMTP id q82LcqwS052519; Sun, 2 Sep 2012 23:38:52 +0200 (CEST) (envelope-from maarten@treewalker.org) Received: from hyperion.localnet (hyperion.trinair2002 [192.168.0.43]) by starbug-2.trinair2002 (Postfix) with ESMTP id A8FA0401E7; Sun, 2 Sep 2012 23:38:51 +0200 (CEST) From: Maarten ter Huurne To: Thierry Reding Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen Subject: Re: [PATCH 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Date: Sun, 02 Sep 2012 23:34:32 +0200 Message-ID: <1494411.dJ2nCQkPX8@hyperion> User-Agent: KMail/4.9 (Linux/3.1.10-1.16-desktop; KDE/4.9.0; x86_64; ; ) In-Reply-To: <20120902192752.GA10930@avionic-0098.mockup.avionic-design.de> References: <1346579550-5990-1-git-send-email-thierry.reding@avionic-design.de> <1890769.KjIbOv8Xbz@hyperion> <20120902192752.GA10930@avionic-0098.mockup.avionic-design.de> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Virus-Scanned: by XS4ALL Virus Scanner X-archive-position: 34411 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maarten@treewalker.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2045 Lines: 48 On Sunday 02 September 2012 21:27:53 Thierry Reding wrote: > On Sun, Sep 02, 2012 at 03:25:55PM +0200, Maarten ter Huurne wrote: > > I tested the "for-next" branch on the Dingoo A320 with the pwm-backlight > > driver. It didn't work at first, because the PWM number and the timer > > number didn't align: I requested PWM number 5 to get PWM7 and the GPIO > > of PWM7 was used, but with timer 5 instead of timer 7, resulting in a > > dark screen. However, it works fine after adding PWM0/1 as described > > above. > > I haven't seen any usage of the pwm-backlight driver in mainline. I > assume this is only present in some downstream repository? Yes, the Dingoo A320 support is currently only available in the qi-kernel repository. We have some essential drivers (the SLCD framebuffer driver in particular) that are in their current state just too ugly to submit to mainline. > > If other people want to test on real hardware, you can find the code in > > branch jz-3.6-rc2-pwm in the qi-kernel repository. Unfortunately our web > > interface for git is still broken, but the repo itself is fine. > > > > git://projects.qi-hardware.com/qi-kernel.git This is where you can find the code. The relevant configs are qi_lb60_defconfig and a320_defconfig. > An alternative approach would be to change pwm_chip.base from -1 > (dynamically allocated) to 2, which would leave 0 and 1 unavailable. > That should at least solve the problem that you had regarding the GPIO > and timer mismatch. That could work, but the hardware does have PWM0 and PWM1, which are just not available in our kernel, so adding them in busy state would better describe real situation. Maybe at some point we'll have a generic timer framework as well and then having PWM0/1 defined but not requestable because the timers are busy would be a natural fit. > But the above also sounds sensible, and since both you and Lars agree > that this is the better option, I can squash these changes into my patch > with your permission. Yes, please do. Bye, Maarten From zajec5@gmail.com Mon Sep 3 21:15:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Sep 2012 21:16:03 +0200 (CEST) Received: from mail-we0-f177.google.com ([74.125.82.177]:41582 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903345Ab2ICTPu convert rfc822-to-8bit (ORCPT ); Mon, 3 Sep 2012 21:15:50 +0200 Received: by weyr3 with SMTP id r3so3195103wey.36 for ; Mon, 03 Sep 2012 12:15:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=9zi9DPWS4MkL+lX8mG4g1bHR3Y2ZqNFSnF3Jdunm9Lg=; b=YLpN5z2Rd86PDfqk658IU0RPvfjz3Pn6RM12lkVvpg1P8zyXYX488VYZvvGzFLWs5t YAo/ulbLm/qccqV0+oh8Eu4Q08YEk+kkKos2zWyXlf3OSctxyS3JEXVP+UT1VVU/Ovli qexjHIm/nS/FBIBLUpX4nybZYmdP37WridajsSDWZajEDpHUU0DGn+o8+PKN8bsyzeCJ Iqd/nFWaA3blgUhal9iohgWKKz6pqU+HHHw3105GRrnb8IfWnhVqXqRhrubiMMPKBxmF aTRWzDtm9eQm92y0SNKslbZYGm15cbAbYEJPE57D1rUtElPeF9vCmto4Zlaz0AUOukFJ 2MCg== MIME-Version: 1.0 Received: by 10.216.23.202 with SMTP id v52mr10089113wev.32.1346699744878; Mon, 03 Sep 2012 12:15:44 -0700 (PDT) Received: by 10.216.169.136 with HTTP; Mon, 3 Sep 2012 12:15:44 -0700 (PDT) In-Reply-To: <1346427485-12801-3-git-send-email-hauke@hauke-m.de> References: <1346427485-12801-1-git-send-email-hauke@hauke-m.de> <1346427485-12801-3-git-send-email-hauke@hauke-m.de> Date: Mon, 3 Sep 2012 21:15:44 +0200 Message-ID: Subject: Re: [PATCH v3 2/3] bcma: add GPIO driver for SoCs From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: Hauke Mehrtens Cc: ralf@linux-mips.org, john@phrozen.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, florian@openwrt.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 34412 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zajec5@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 503 Lines: 20 2012/8/31 Hauke Mehrtens : > +u32 bcma_gpio_in(struct bcma_bus *bus, u32 mask) > +{ > + unsigned long flags; > + u32 res = 0; > + > + spin_lock_irqsave(&bus->gpio_lock, flags); > + res = bcma_chipco_gpio_in(&bus->drv_cc, mask); > + spin_unlock_irqrestore(&bus->gpio_lock, flags); > + > + return res; > +} > +EXPORT_SYMBOL(bcma_gpio_in); Could we put here direct ops on ChipCommon regs and drop GPIO functions from driver_chipcommon.c? -- RafaÅ‚ From jim2101024@gmail.com Mon Sep 3 23:53:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Sep 2012 23:53:16 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:3191 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903348Ab2ICVxH (ORCPT ); Mon, 3 Sep 2012 23:53:07 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 03 Sep 2012 14:51:21 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Mon, 3 Sep 2012 14:52:44 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id CE7059F9F5; Mon, 3 Sep 2012 14:52:43 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com, "Jim Quinlan" Subject: [PATCH V3 2/2] MIPS: make funcs preempt-safe for non-mipsr2 cpus Date: Mon, 3 Sep 2012 17:52:17 -0400 Message-ID: <1346709137-3448-2-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1346709137-3448-1-git-send-email-jim2101024@gmail.com> References: <1346709137-3448-1-git-send-email-jim2101024@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C5BF9D33NK22813710-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34413 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 11289 Lines: 404 For non MIPSr2 processors, such as the BMIPS 5000, calls to arch_local_irq_disable() and others may be preempted, and in doing so a stale value may be restored to c0_status. This fix disables preemption for such processors prior to the call and enables it after the call. Those functions that needed this fix have been "outlined" to mips-atomic.c, as they are no longer good candidates for inlining. This bug was observed in a BMIPS 5000, occuring once every few hours in a continuous reboot test. It was traced to the write_lock_irq() function which was being invoked in release_task() in exit.c. By placing a number of "nops" inbetween the mfc0/mtc0 pair in arch_local_irq_disable(), which is called by write_lock_irq(), we were able to greatly increase the occurance of this bug. Similarly, the application of this commit silenced the bug. Signed-off-by: Jim Quinlan --- arch/mips/include/asm/irqflags.h | 92 +++++--------------- arch/mips/lib/Makefile | 3 +- arch/mips/lib/mips-atomic.c | 179 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 202 insertions(+), 72 deletions(-) create mode 100644 arch/mips/lib/mips-atomic.c diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h index 309cbcd..9174d88 100644 --- a/arch/mips/include/asm/irqflags.h +++ b/arch/mips/include/asm/irqflags.h @@ -16,6 +16,15 @@ #include #include +#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MT_SMTC) +/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */ +extern void arch_local_irq_disable(void); +extern unsigned long arch_local_irq_save(void); +extern void arch_local_irq_restore(unsigned long flags); +extern void __arch_local_irq_restore(unsigned long flags); +#endif + + __asm__( " .macro arch_local_irq_enable \n" " .set push \n" @@ -57,42 +66,12 @@ static inline void arch_local_irq_enable(void) } -/* - * For cli() we have to insert nops to make sure that the new value - * has actually arrived in the status register before the end of this - * macro. - * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs - * no nops at all. - */ -/* - * For TX49, operating only IE bit is not enough. - * - * If mfc0 $12 follows store and the mfc0 is last instruction of a - * page and fetching the next instruction causes TLB miss, the result - * of the mfc0 might wrongly contain EXL bit. - * - * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 - * - * Workaround: mask EXL bit of the result or place a nop before mfc0. - */ +#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MT_SMTC) __asm__( " .macro arch_local_irq_disable\n" " .set push \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 \n" - " ori $1, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) " di \n" -#else - " mfc0 $1,$12 \n" - " ori $1,0x1f \n" - " xori $1,0x1f \n" - " .set noreorder \n" - " mtc0 $1,$12 \n" -#endif " irq_disable_hazard \n" " .set pop \n" " .endm \n"); @@ -105,6 +84,8 @@ static inline void arch_local_irq_disable(void) : /* no inputs */ : "memory"); } +#endif + __asm__( " .macro arch_local_save_flags flags \n" @@ -125,27 +106,15 @@ static inline unsigned long arch_local_save_flags(void) return flags; } + +#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MT_SMTC) __asm__( " .macro arch_local_irq_save result \n" " .set push \n" " .set reorder \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\result, $2, 1 \n" - " ori $1, \\result, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" - " andi \\result, \\result, 0x400 \n" -#elif defined(CONFIG_CPU_MIPSR2) " di \\result \n" " andi \\result, 1 \n" -#else - " mfc0 \\result, $12 \n" - " ori $1, \\result, 0x1f \n" - " xori $1, 0x1f \n" - " .set noreorder \n" - " mtc0 $1, $12 \n" -#endif " irq_disable_hazard \n" " .set pop \n" " .endm \n"); @@ -159,20 +128,16 @@ static inline unsigned long arch_local_irq_save(void) : "memory"); return flags; } +#endif + +#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MT_SMTC) __asm__( " .macro arch_local_irq_restore flags \n" " .set push \n" " .set noreorder \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - "mfc0 $1, $2, 1 \n" - "andi \\flags, 0x400 \n" - "ori $1, 0x400 \n" - "xori $1, 0x400 \n" - "or \\flags, $1 \n" - "mtc0 \\flags, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) +#if defined(CONFIG_IRQ_CPU) /* * Slow, but doesn't suffer from a relatively unlikely race * condition we're having since days 1. @@ -181,20 +146,13 @@ __asm__( " di \n" " ei \n" "1: \n" -#elif defined(CONFIG_CPU_MIPSR2) +#else /* * Fast, dangerous. Life is fun, life is good. */ " mfc0 $1, $12 \n" " ins $1, \\flags, 0, 1 \n" " mtc0 $1, $12 \n" -#else - " mfc0 $1, $12 \n" - " andi \\flags, 1 \n" - " ori $1, 0x1f \n" - " xori $1, 0x1f \n" - " or \\flags, $1 \n" - " mtc0 \\flags, $12 \n" #endif " irq_disable_hazard \n" " .set pop \n" @@ -205,16 +163,6 @@ static inline void arch_local_irq_restore(unsigned long flags) { unsigned long __tmp1; -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC kernel needs to do a software replay of queued - * IPIs, at the cost of branch and call overhead on each - * local_irq_restore() - */ - if (unlikely(!(flags & 0x0400))) - smtc_ipi_replay(); -#endif - __asm__ __volatile__( "arch_local_irq_restore\t%0" : "=r" (__tmp1) @@ -232,6 +180,8 @@ static inline void __arch_local_irq_restore(unsigned long flags) : "0" (flags) : "memory"); } +#endif + static inline int arch_irqs_disabled_flags(unsigned long flags) { diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index a7b8937..eeddc58 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -3,7 +3,8 @@ # lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ - strlen_user.o strncpy_user.o strnlen_user.o uncached.o + mips-atomic.o strlen_user.o strncpy_user.o \ + strnlen_user.o uncached.o obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c new file mode 100644 index 0000000..546eb25 --- /dev/null +++ b/arch/mips/lib/mips-atomic.c @@ -0,0 +1,179 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#include +#include +#include +#include + +#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) + +#if defined(CONFIG_PREEMPT) +#define arch_local_preempt_enable() preempt_enable() +#define arch_local_preempt_disable() preempt_disable() +#else +#define arch_local_preempt_enable() +#define arch_local_preempt_disable() +#endif + + +/* + * For cli() we have to insert nops to make sure that the new value + * has actually arrived in the status register before the end of this + * macro. + * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs + * no nops at all. + */ +/* + * For TX49, operating only IE bit is not enough. + * + * If mfc0 $12 follows store and the mfc0 is last instruction of a + * page and fetching the next instruction causes TLB miss, the result + * of the mfc0 might wrongly contain EXL bit. + * + * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 + * + * Workaround: mask EXL bit of the result or place a nop before mfc0. + */ +__asm__( + " .macro arch_local_irq_disable\n" + " .set push \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 $1, $2, 1 \n" + " ori $1, 0x400 \n" + " .set noreorder \n" + " mtc0 $1, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) + /* see irqflags.h for inline function */ +#else + " mfc0 $1,$12 \n" + " ori $1,0x1f \n" + " xori $1,0x1f \n" + " .set noreorder \n" + " mtc0 $1,$12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +void arch_local_irq_disable(void) +{ + arch_local_preempt_disable(); + __asm__ __volatile__( + "arch_local_irq_disable" + : /* no outputs */ + : /* no inputs */ + : "memory"); + arch_local_preempt_enable(); +} + + +__asm__( + " .macro arch_local_irq_save result \n" + " .set push \n" + " .set reorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 \\result, $2, 1 \n" + " ori $1, \\result, 0x400 \n" + " .set noreorder \n" + " mtc0 $1, $2, 1 \n" + " andi \\result, \\result, 0x400 \n" +#elif defined(CONFIG_CPU_MIPSR2) + /* see irqflags.h for inline function */ +#else + " mfc0 \\result, $12 \n" + " ori $1, \\result, 0x1f \n" + " xori $1, 0x1f \n" + " .set noreorder \n" + " mtc0 $1, $12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + arch_local_preempt_disable(); + asm volatile("arch_local_irq_save\t%0" + : "=r" (flags) + : /* no inputs */ + : "memory"); + arch_local_preempt_enable(); + return flags; +} + + +__asm__( + " .macro arch_local_irq_restore flags \n" + " .set push \n" + " .set noreorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + "mfc0 $1, $2, 1 \n" + "andi \\flags, 0x400 \n" + "ori $1, 0x400 \n" + "xori $1, 0x400 \n" + "or \\flags, $1 \n" + "mtc0 \\flags, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) + /* see irqflags.h for inline function */ +#elif defined(CONFIG_CPU_MIPSR2) + /* see irqflags.h for inline function */ +#else + " mfc0 $1, $12 \n" + " andi \\flags, 1 \n" + " ori $1, 0x1f \n" + " xori $1, 0x1f \n" + " or \\flags, $1 \n" + " mtc0 \\flags, $12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +void arch_local_irq_restore(unsigned long flags) +{ + unsigned long __tmp1; + +#ifdef CONFIG_MIPS_MT_SMTC + /* + * SMTC kernel needs to do a software replay of queued + * IPIs, at the cost of branch and call overhead on each + * local_irq_restore() + */ + if (unlikely(!(flags & 0x0400))) + smtc_ipi_replay(); +#endif + arch_local_preempt_disable(); + __asm__ __volatile__( + "arch_local_irq_restore\t%0" + : "=r" (__tmp1) + : "0" (flags) + : "memory"); + arch_local_preempt_enable(); +} + +void __arch_local_irq_restore(unsigned long flags) +{ + unsigned long __tmp1; + + arch_local_preempt_disable(); + __asm__ __volatile__( + "arch_local_irq_restore\t%0" + : "=r" (__tmp1) + : "0" (flags) + : "memory"); + arch_local_preempt_enable(); +} + +#endif /* !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) */ -- 1.7.6 From jim2101024@gmail.com Mon Sep 3 23:53:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Sep 2012 23:53:46 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:3191 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903351Ab2ICVxY (ORCPT ); Mon, 3 Sep 2012 23:53:24 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 03 Sep 2012 14:51:20 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Mon, 3 Sep 2012 14:52:43 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id EC4E69F9F5; Mon, 3 Sep 2012 14:52:42 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com, "Jim Quinlan" Subject: [PATCH V3 1/2] MIPS: Remove irqflags.h dependency from bitops.h Date: Mon, 3 Sep 2012 17:52:16 -0400 Message-ID: <1346709137-3448-1-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: References: MIME-Version: 1.0 X-WSS-ID: 7C5BF9D23NK22813709-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34414 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10589 Lines: 409 The "else clause" of most functions in bitops.h invoked raw_local_irq_{save,restore}() and so had a dependency on irqflags.h. This fix moves said code to bitops.c, removing the dependency. Signed-off-by: Jim Quinlan --- arch/mips/include/asm/bitops.h | 114 +++++++------------------ arch/mips/include/asm/io.h | 1 + arch/mips/lib/Makefile | 2 +- arch/mips/lib/bitops.c | 180 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 214 insertions(+), 83 deletions(-) create mode 100644 arch/mips/lib/bitops.c diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 82ad35c..9fd0b1d 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -14,7 +14,6 @@ #endif #include -#include #include #include #include /* sigh ... */ @@ -44,6 +43,24 @@ #define smp_mb__before_clear_bit() smp_mb__before_llsc() #define smp_mb__after_clear_bit() smp_llsc_mb() + +/* + * These are the "slower" versions of the functions and are in bitops.c. + * These functions call raw_local_irq_{save,restore}(). + */ +extern void atomic_set_bit(unsigned long nr, volatile unsigned long *addr); +extern void atomic_clear_bit(unsigned long nr, volatile unsigned long *addr); +extern void atomic_change_bit(unsigned long nr, volatile unsigned long *addr); +extern int atomic_test_and_set_bit(unsigned long nr, + volatile unsigned long *addr); +extern int atomic_test_and_set_bit_lock(unsigned long nr, + volatile unsigned long *addr); +extern int atomic_test_and_clear_bit(unsigned long nr, + volatile unsigned long *addr); +extern int atomic_test_and_change_bit(unsigned long nr, + volatile unsigned long *addr); + + /* * set_bit - Atomically set a bit in memory * @nr: the bit to set @@ -92,17 +109,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) : "=&r" (temp), "+m" (*m) : "ir" (1UL << bit)); } while (unlikely(!temp)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a |= mask; - raw_local_irq_restore(flags); - } + } else + atomic_set_bit(nr, addr); } /* @@ -153,17 +161,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) : "=&r" (temp), "+m" (*m) : "ir" (~(1UL << bit))); } while (unlikely(!temp)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a &= ~mask; - raw_local_irq_restore(flags); - } + } else + atomic_clear_bit(nr, addr); } /* @@ -220,17 +219,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) : "=&r" (temp), "+m" (*m) : "ir" (1UL << bit)); } while (unlikely(!temp)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a ^= mask; - raw_local_irq_restore(flags); - } + } else + atomic_change_bit(nr, addr); } /* @@ -281,18 +271,8 @@ static inline int test_and_set_bit(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a |= mask; - raw_local_irq_restore(flags); - } + } else + res = atomic_test_and_set_bit(nr, addr); smp_llsc_mb(); @@ -345,18 +325,8 @@ static inline int test_and_set_bit_lock(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a |= mask; - raw_local_irq_restore(flags); - } + } else + res = atomic_test_and_set_bit_lock(nr, addr); smp_llsc_mb(); @@ -428,18 +398,8 @@ static inline int test_and_clear_bit(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a &= ~mask; - raw_local_irq_restore(flags); - } + } else + res = atomic_test_and_clear_bit(nr, addr); smp_llsc_mb(); @@ -494,18 +454,8 @@ static inline int test_and_change_bit(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a ^= mask; - raw_local_irq_restore(flags); - } + } else + res = atomic_test_and_change_bit(nr, addr); smp_llsc_mb(); diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 29d9c23..ff2e034 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index c4a82e8..a7b8937 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o delay.o memcpy.o memset.o \ +lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ strlen_user.o strncpy_user.o strnlen_user.o uncached.o obj-y += iomap.o diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c new file mode 100644 index 0000000..6562ab2 --- /dev/null +++ b/arch/mips/lib/bitops.c @@ -0,0 +1,180 @@ + +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org) + * Copyright (c) 1999, 2000 Silicon Graphics, Inc. + */ + +#include + +#if _MIPS_SZLONG == 32 +#define SZLONG_LOG 5 +#define SZLONG_MASK 31UL +#elif _MIPS_SZLONG == 64 +#define SZLONG_MASK 63UL +#define SZLONG_LOG 6 +#endif + + +/* + * atomic_set_bit - Atomically set a bit in memory. This is called by + * if set_bit() if it cannot find a faster solution. + * @nr: the bit to set + * @addr: the address to start counting from + */ +void atomic_set_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned short bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + *a |= mask; + raw_local_irq_restore(flags); +} + + +/* + * atomic_clear_bit - Clears a bit in memory. This is called by clear_bit() if + * it cannot find a faster solution. + * @nr: Bit to clear + * @addr: Address to start counting from + */ +void atomic_clear_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned short bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + *a &= ~mask; + raw_local_irq_restore(flags); +} + + +/* + * atomic_change_bit - Toggle a bit in memory. This is called by change_bit() + * if it cannot find a faster solution. + * @nr: Bit to change + * @addr: Address to start counting from + */ +void atomic_change_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned short bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + *a ^= mask; + raw_local_irq_restore(flags); +} + + +/* + * atomic_test_and_set_bit - Set a bit and return its old value. This is + * called by test_and_set_bit() if it cannot find a faster solution. + * @nr: Bit to set + * @addr: Address to count from + */ +int atomic_test_and_set_bit(unsigned long nr, + volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned short bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a |= mask; + raw_local_irq_restore(flags); + return res; +} + + +/* + * atomic_test_and_set_bit_lock - Set a bit and return its old value. This is + * called by test_and_set_bit_lock() if it cannot find a faster solution. + * @nr: Bit to set + * @addr: Address to count from + */ +int atomic_test_and_set_bit_lock(unsigned long nr, + volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned short bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a |= mask; + raw_local_irq_restore(flags); + return res; +} + + +/* + * atomic_test_and_clear_bit - Clear a bit and return its old value. This is + * called by test_and_clear_bit() if it cannot find a faster solution. + * @nr: Bit to clear + * @addr: Address to count from + */ +int atomic_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned short bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a &= ~mask; + raw_local_irq_restore(flags); + return res; +} + + +/* + * atomic_test_and_change_bit - Change a bit and return its old value. This is + * called by test_and_change_bit() if it cannot find a faster solution. + * @nr: Bit to change + * @addr: Address to count from + */ +int atomic_test_and_change_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned short bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a ^= mask; + raw_local_irq_restore(flags); + return res; +} -- 1.7.6 From ddaney.cavm@gmail.com Tue Sep 4 19:30:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Sep 2012 19:30:31 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:53532 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903381Ab2IDRaX (ORCPT ); Tue, 4 Sep 2012 19:30:23 +0200 Received: by pbbrq8 with SMTP id rq8so10274491pbb.36 for ; Tue, 04 Sep 2012 10:30:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=ttf0tJ5HhyKcV6Ci+IX3SCERhB9/TzVi7Ul/2Y9LYvo=; b=dNXzJShYl9rDQDCeuinqcKn1bPQTX6kEmAeuzt3IWVTNoF1wHtdVJgPKDtdQySRt6f zqVurVJPyk8u6K3Nxi5JS4inOWBHnmkl3JxiOX3NoatU5UAv91C2kzuWSzysEWm/Ss1L +XLsmSZb+Q6qO+VqD3KKHJqak69oCX0ylFIGOM6tbyVTWHTa2oyun0fzF38JHLB9+i1t 8YDYIwqwpktdWLwcOtK8iSlIggnTec3Mnv5I2xWA0LbDTcM+6/ra38eyGKmHP525FG/d ieGBnomcUvSg51RSn1EeclCilezrO1f3tJfvWlmWRv6hB/r3nNpmJsN4mx6qkYZMSYzj wh9g== Received: by 10.68.221.225 with SMTP id qh1mr47981575pbc.50.1346779816977; Tue, 04 Sep 2012 10:30:16 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id tt6sm10205620pbc.51.2012.09.04.10.30.14 (version=SSLv3 cipher=OTHER); Tue, 04 Sep 2012 10:30:15 -0700 (PDT) Message-ID: <50463AA5.1000506@gmail.com> Date: Tue, 04 Sep 2012 10:30:13 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: Jim Quinlan CC: ralf@linux-mips.org, linux-mips@linux-mips.org, cernekee@gmail.com Subject: Re: [PATCH V3 1/2] MIPS: Remove irqflags.h dependency from bitops.h References: <1346709137-3448-1-git-send-email-jim2101024@gmail.com> In-Reply-To: <1346709137-3448-1-git-send-email-jim2101024@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34415 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3979 Lines: 127 On 09/03/2012 02:52 PM, Jim Quinlan wrote: > The "else clause" of most functions in bitops.h invoked > raw_local_irq_{save,restore}() and so had a dependency on irqflags.h. This > fix moves said code to bitops.c, removing the dependency. > > Signed-off-by: Jim Quinlan This is much better I think. Now only a few very minor things I would change... > --- > arch/mips/include/asm/bitops.h | 114 +++++++------------------ > arch/mips/include/asm/io.h | 1 + > arch/mips/lib/Makefile | 2 +- > arch/mips/lib/bitops.c | 180 ++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 214 insertions(+), 83 deletions(-) > create mode 100644 arch/mips/lib/bitops.c > > diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h > index 82ad35c..9fd0b1d 100644 > --- a/arch/mips/include/asm/bitops.h > +++ b/arch/mips/include/asm/bitops.h > @@ -14,7 +14,6 @@ > #endif > > #include > -#include > #include > #include > #include /* sigh ... */ > @@ -44,6 +43,24 @@ > #define smp_mb__before_clear_bit() smp_mb__before_llsc() > #define smp_mb__after_clear_bit() smp_llsc_mb() > > + > +/* > + * These are the "slower" versions of the functions and are in bitops.c. > + * These functions call raw_local_irq_{save,restore}(). > + */ > +extern void atomic_set_bit(unsigned long nr, volatile unsigned long *addr); > +extern void atomic_clear_bit(unsigned long nr, volatile unsigned long *addr); > +extern void atomic_change_bit(unsigned long nr, volatile unsigned long *addr); > +extern int atomic_test_and_set_bit(unsigned long nr, > + volatile unsigned long *addr); > +extern int atomic_test_and_set_bit_lock(unsigned long nr, > + volatile unsigned long *addr); > +extern int atomic_test_and_clear_bit(unsigned long nr, > + volatile unsigned long *addr); > +extern int atomic_test_and_change_bit(unsigned long nr, > + volatile unsigned long *addr); > + No 'extern' needed. These shouldn't be directly called from user code. I would suggest renaming the functions to something like: __mips_set_bit(); [...] > diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c > new file mode 100644 > index 0000000..6562ab2 > --- /dev/null > +++ b/arch/mips/lib/bitops.c > @@ -0,0 +1,180 @@ > + > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org) > + * Copyright (c) 1999, 2000 Silicon Graphics, Inc. > + */ > + > +#include > + > +#if _MIPS_SZLONG == 32 > +#define SZLONG_LOG 5 > +#define SZLONG_MASK 31UL > +#elif _MIPS_SZLONG == 64 > +#define SZLONG_MASK 63UL > +#define SZLONG_LOG 6 > +#endif > + There has to be a cleaner way to do this... Perhaps: #define SZLONG_LOG (ilog2(sizeof(unsigned long)) + 3) #define SZLONG_MASK ((1 << SZLONG_LOG) - 1) > + > +/* > + * atomic_set_bit - Atomically set a bit in memory. This is called by > + * if set_bit() if it cannot find a faster solution. > + * @nr: the bit to set > + * @addr: the address to start counting from > + */ > +void atomic_set_bit(unsigned long nr, volatile unsigned long *addr) > +{ > + volatile unsigned long *a = addr; > + unsigned short bit = nr & SZLONG_MASK; just make bit type 'int'. In some cases forcing a narrower type than necessary requires the compiler to emit extra code. I am not sure if it would here, but why use a type other than int unless absolutely necessary? > + unsigned long mask; > + unsigned long flags; > + > + a += nr >> SZLONG_LOG; > + mask = 1UL << bit; > + raw_local_irq_save(flags); > + *a |= mask; > + raw_local_irq_restore(flags); > +} All these must be EXPORT_SYMBOL(), so the bitop intrinsics can be used from modules. From ddaney.cavm@gmail.com Tue Sep 4 19:36:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Sep 2012 19:36:56 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:58730 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903381Ab2IDRgs (ORCPT ); Tue, 4 Sep 2012 19:36:48 +0200 Received: by pbbrq8 with SMTP id rq8so10283121pbb.36 for ; Tue, 04 Sep 2012 10:36:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=BcoBhfFlmUgtgJ1tv1OGK1FxRin17phIJVebDkyOOg8=; b=Jqpy1MdkLtNSzVgY5AiOIvwZXqA72e+dxvHagHgO6z0ZG9LelMc1b3DazHNTJ1gxDO bvfuksqnA6qYPKHXxr3GroHa/q39rBSdNRZU/ZgJ5PKVi8f5veATYiOnXuBF+aU1hCwJ yaXlT+FqmDrGiKDtu9IidlHxbTLclZwgmi/mTml3r8PebyrGVnIZZ/vv9L5yNdGoks9B PIz8VXItagDaVH/pxYDxvqWnJbfHMZSjtKc6rMCeAGxHXwIQzSETdxihPensBfIuTLlX MPbmjRbXvNePhhYt185id3H0wDAa/ShBChGUm8nnWklB8FGzLZmSvBCi0nvsu2Zqb4wW wxaw== Received: by 10.68.242.42 with SMTP id wn10mr36815992pbc.105.1346780201768; Tue, 04 Sep 2012 10:36:41 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id uj3sm12616798pbc.39.2012.09.04.10.36.40 (version=SSLv3 cipher=OTHER); Tue, 04 Sep 2012 10:36:41 -0700 (PDT) Message-ID: <50463C27.9070201@gmail.com> Date: Tue, 04 Sep 2012 10:36:39 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: Jim Quinlan CC: ralf@linux-mips.org, linux-mips@linux-mips.org, cernekee@gmail.com Subject: Re: [PATCH V3 2/2] MIPS: make funcs preempt-safe for non-mipsr2 cpus References: <1346709137-3448-1-git-send-email-jim2101024@gmail.com> <1346709137-3448-2-git-send-email-jim2101024@gmail.com> In-Reply-To: <1346709137-3448-2-git-send-email-jim2101024@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34416 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3608 Lines: 110 On 09/03/2012 02:52 PM, Jim Quinlan wrote: > For non MIPSr2 processors, such as the BMIPS 5000, calls to > arch_local_irq_disable() and others may be preempted, and in doing > so a stale value may be restored to c0_status. This fix disables > preemption for such processors prior to the call and enables it > after the call. > > Those functions that needed this fix have been "outlined" to > mips-atomic.c, as they are no longer good candidates for inlining. > > This bug was observed in a BMIPS 5000, occuring once every few hours > in a continuous reboot test. It was traced to the write_lock_irq() > function which was being invoked in release_task() in exit.c. > By placing a number of "nops" inbetween the mfc0/mtc0 pair in > arch_local_irq_disable(), which is called by write_lock_irq(), we > were able to greatly increase the occurance of this bug. Similarly, > the application of this commit silenced the bug. > > Signed-off-by: Jim Quinlan This one seems better too... [...] > diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c > new file mode 100644 > index 0000000..546eb25 > --- /dev/null > +++ b/arch/mips/lib/mips-atomic.c > @@ -0,0 +1,179 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle > + * Copyright (C) 1996 by Paul M. Antoine > + * Copyright (C) 1999 Silicon Graphics > + * Copyright (C) 2000 MIPS Technologies, Inc. > + */ > +#include > +#include > +#include > +#include > + > +#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) > + > +#if defined(CONFIG_PREEMPT) > +#define arch_local_preempt_enable() preempt_enable() > +#define arch_local_preempt_disable() preempt_disable() > +#else > +#define arch_local_preempt_enable() > +#define arch_local_preempt_disable() > +#endif > + > + > +/* > + * For cli() we have to insert nops to make sure that the new value > + * has actually arrived in the status register before the end of this > + * macro. > + * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs > + * no nops at all. > + */ > +/* > + * For TX49, operating only IE bit is not enough. > + * > + * If mfc0 $12 follows store and the mfc0 is last instruction of a > + * page and fetching the next instruction causes TLB miss, the result > + * of the mfc0 might wrongly contain EXL bit. > + * > + * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 > + * > + * Workaround: mask EXL bit of the result or place a nop before mfc0. > + */ > +__asm__( > + " .macro arch_local_irq_disable\n" > + " .set push \n" > + " .set noat \n" > +#ifdef CONFIG_MIPS_MT_SMTC > + " mfc0 $1, $2, 1 \n" > + " ori $1, 0x400 \n" > + " .set noreorder \n" > + " mtc0 $1, $2, 1 \n" > +#elif defined(CONFIG_CPU_MIPSR2) > + /* see irqflags.h for inline function */ > +#else > + " mfc0 $1,$12 \n" > + " ori $1,0x1f \n" > + " xori $1,0x1f \n" > + " .set noreorder \n" > + " mtc0 $1,$12 \n" > +#endif > + " irq_disable_hazard \n" > + " .set pop \n" > + " .endm \n"); > + > +void arch_local_irq_disable(void) > +{ > + arch_local_preempt_disable(); > + __asm__ __volatile__( > + "arch_local_irq_disable" > + : /* no outputs */ > + : /* no inputs */ > + : "memory"); > + arch_local_preempt_enable(); > +} I think this function must be EXPORT_SYMBOL() too. David Daney From benh@kernel.crashing.org Wed Sep 5 04:04:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 04:04:25 +0200 (CEST) Received: from gate.crashing.org ([63.228.1.57]:55341 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903392Ab2IECEM (ORCPT ); Wed, 5 Sep 2012 04:04:12 +0200 Received: from [127.0.0.1] (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id q8523iQ0003954; Tue, 4 Sep 2012 21:03:45 -0500 Message-ID: <1346810624.2257.22.camel@pasglop> Subject: Re: [PATCH] clk: Make the generic clock API available by default From: Benjamin Herrenschmidt To: Mark Brown Cc: Arnd Bergmann , Russell King , Haavard Skinnemoen , Hans-Christian Egtvedt , Ralf Baechle , Paul Mackerras , Guan Xuetao , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org Date: Wed, 05 Sep 2012 12:03:44 +1000 In-Reply-To: <1346186104-4083-1-git-send-email-broonie@opensource.wolfsonmicro.com> References: <1346186104-4083-1-git-send-email-broonie@opensource.wolfsonmicro.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit Mime-Version: 1.0 X-archive-position: 34417 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: benh@kernel.crashing.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 766 Lines: 23 On Tue, 2012-08-28 at 13:35 -0700, Mark Brown wrote: > Rather than requiring platforms to select the generic clock API to make > it available make the API available as a user selectable option unless the > user either selects HAVE_CUSTOM_CLK (if they have their own implementation) > or selects COMMON_CLK (if they depend on the generic implementation). > > All current architectures that HAVE_CLK but don't use the common clock > framework have selects of HAVE_CUSTOM_CLK added. > > This allows drivers to use the generic API on platforms which have no need > for the clock API at platform level. > > Signed-off-by: Mark Brown > --- For powerpc: Acked-by: Benjamin Herrenschmidt Cheers, Ben. From sjhill@mips.com Wed Sep 5 22:28:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 22:28:19 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:56491 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903404Ab2IEU2L (ORCPT ); Wed, 5 Sep 2012 22:28:11 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1T9MCh-0004QI-Ve; Wed, 05 Sep 2012 15:28:03 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 0/4] Add RI and XI bits to MIPS base architecture. Date: Wed, 5 Sep 2012 15:27:54 -0500 Message-Id: <1346876878-25965-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 34418 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1327 Lines: 30 From: "Steven J. Hill" Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI) and Execute Inhibit (XI) page protection. SmartMIPS cores will not notice any change in functionality. Signed-off-by: Steven J. Hill Steven J. Hill (4): MIPS: Add base architecture support for RI and XI. MIPS: Remove kernel_uses_smartmips_rixi use from arch/mips/mm. MIPS: Remove kernel_uses_smartmips_rixi from page table bits. MIPS: Remove kernel_uses_smartmips_rixi macro definition. arch/mips/include/asm/cpu-features.h | 7 ++++-- arch/mips/include/asm/cpu.h | 2 ++ .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 -- arch/mips/include/asm/mipsregs.h | 1 + arch/mips/include/asm/pgtable-bits.h | 24 ++++++++++++-------- arch/mips/include/asm/pgtable.h | 12 +++++----- arch/mips/kernel/cpu-probe.c | 12 +++++++++- arch/mips/mm/cache.c | 2 +- arch/mips/mm/fault.c | 4 +++- arch/mips/mm/tlb-r4k.c | 7 ++++-- arch/mips/mm/tlbex.c | 14 ++++++------ 11 files changed, 55 insertions(+), 32 deletions(-) -- 1.7.9.5 From sjhill@mips.com Wed Sep 5 22:28:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 22:28:42 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:56493 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903405Ab2IEU2N (ORCPT ); Wed, 5 Sep 2012 22:28:13 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1T9MCl-0004QI-7w; Wed, 05 Sep 2012 15:28:07 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 1/4] MIPS: Add base architecture support for RI and XI. Date: Wed, 5 Sep 2012 15:27:55 -0500 Message-Id: <1346876878-25965-2-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1346876878-25965-1-git-send-email-sjhill@mips.com> References: <1346876878-25965-1-git-send-email-sjhill@mips.com> X-archive-position: 34419 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3150 Lines: 85 From: "Steven J. Hill" Originally both Read Inhibit (RI) and Execute Inhibit (XI) were supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) Architecture now defines an optional feature to implement these TLB bits separately. Support for one or both features can be checked by looking at the Config3.RXI bit. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu-features.h | 6 ++++++ arch/mips/include/asm/cpu.h | 2 ++ arch/mips/include/asm/mipsregs.h | 1 + arch/mips/kernel/cpu-probe.c | 12 +++++++++++- 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 080edd8..c78a77b 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -98,6 +98,12 @@ #ifndef kernel_uses_smartmips_rixi #define kernel_uses_smartmips_rixi 0 #endif +#ifndef cpu_has_ri +#define cpu_has_ri (cpu_data[0].options & MIPS_CPU_RI) +#endif +#ifndef cpu_has_xi +#define cpu_has_xi (cpu_data[0].options & MIPS_CPU_XI) +#endif #ifndef cpu_has_mmips #define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 4889fae..1b928ed 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -323,6 +323,8 @@ enum cpu_type_enum { #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ #define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ +#define MIPS_CPU_RI 0x02000000 /* CPU has TLB Read Inhibit */ +#define MIPS_CPU_XI 0x04000000 /* CPU has TLB Execute Inhibit */ /* * CPU ASE encodings diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index cdb9c87..19430fb 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -591,6 +591,7 @@ #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) +#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 009fc13..e85d732 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -422,8 +422,18 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) config3 = read_c0_config3(); - if (config3 & MIPS_CONF3_SM) + if (config3 & MIPS_CONF3_SM) { c->ases |= MIPS_ASE_SMARTMIPS; + c->options |= MIPS_CPU_RI; + c->options |= MIPS_CPU_XI; + } + if (config3 & MIPS_CONF3_RXI) { + write_c0_pagegrain(read_c0_pagegrain() | PG_RIE | PG_XIE); + if (read_c0_pagegrain() & PG_RIE) + c->options |= MIPS_CPU_RI; + if (read_c0_pagegrain() & PG_XIE) + c->options |= MIPS_CPU_XI; + } if (config3 & MIPS_CONF3_DSP) c->ases |= MIPS_ASE_DSP; if (config3 & MIPS_CONF3_DSP2P) -- 1.7.9.5 From sjhill@mips.com Wed Sep 5 22:28:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 22:29:08 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:56494 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903407Ab2IEU2O (ORCPT ); Wed, 5 Sep 2012 22:28:14 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1T9MCm-0004QI-0x; Wed, 05 Sep 2012 15:28:08 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 2/4] MIPS: Remove kernel_uses_smartmips_rixi use from arch/mips/mm. Date: Wed, 5 Sep 2012 15:27:56 -0500 Message-Id: <1346876878-25965-3-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1346876878-25965-1-git-send-email-sjhill@mips.com> References: <1346876878-25965-1-git-send-email-sjhill@mips.com> X-archive-position: 34420 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5124 Lines: 140 From: "Steven J. Hill" Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files in the 'arch/mips/mm' subsystem. Signed-off-by: Steven J. Hill --- arch/mips/mm/cache.c | 2 +- arch/mips/mm/fault.c | 4 +++- arch/mips/mm/tlb-r4k.c | 7 +++++-- arch/mips/mm/tlbex.c | 14 +++++++------- 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index ff910a1..b478c51 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -183,7 +183,7 @@ EXPORT_SYMBOL(_page_cachable_default); static inline void setup_protection_map(void) { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index c14f6df..153aeee 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -114,7 +114,7 @@ good_area: if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_xi) { if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) { #if 0 pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] XI violation\n", @@ -125,6 +125,8 @@ good_area: #endif goto bad_area; } + } + else if (cpu_has_ri) { if (!(vma->vm_flags & VM_READ)) { #if 0 pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] RI violation\n", diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index d2572cb..df894f8 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -401,12 +401,15 @@ void __cpuinit tlb_init(void) current_cpu_type() == CPU_R14000) write_c0_framemask(0); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { + u32 pg; + /* * Enable the no read, no exec bits, and enable large virtual * address. */ - u32 pg = PG_RIE | PG_XIE; + pg = (cpu_has_ri ? PG_RIE : 0); + pg |= (cpu_has_xi ? PG_XIE : 0); #ifdef CONFIG_64BIT pg |= PG_ELPA; #endif diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index e565d45..90c86ee 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -601,7 +601,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, unsigned int reg) { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); } else { @@ -1021,7 +1021,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, if (cpu_has_64bits) { uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); @@ -1048,7 +1048,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ if (r45k_bvahwbug()) build_tlb_probe_entry(p); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); @@ -1214,7 +1214,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, UASM_i_LW(p, even, 0, ptr); /* get even pte */ UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ } - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC)); uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC)); uasm_i_drotr(p, even, even, @@ -1576,7 +1576,7 @@ build_pte_present(u32 **p, struct uasm_reloc **r, { int t = scratch >= 0 ? scratch : pte; - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { if (use_bbit_insns()) { uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); uasm_i_nop(p); @@ -1906,7 +1906,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) if (m4kc_tlbp_war()) build_tlb_probe_entry(&p); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. @@ -1960,7 +1960,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); build_tlb_probe_entry(&p); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. -- 1.7.9.5 From sjhill@mips.com Wed Sep 5 22:28:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 22:29:36 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:56497 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903408Ab2IEU2O (ORCPT ); Wed, 5 Sep 2012 22:28:14 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1T9MCm-0004QI-GA; Wed, 05 Sep 2012 15:28:08 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 3/4] MIPS: Remove kernel_uses_smartmips_rixi from page table bits. Date: Wed, 5 Sep 2012 15:27:57 -0500 Message-Id: <1346876878-25965-4-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1346876878-25965-1-git-send-email-sjhill@mips.com> References: <1346876878-25965-1-git-send-email-sjhill@mips.com> X-archive-position: 34421 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5333 Lines: 118 From: "Steven J. Hill" Remove usage of the 'kernel_uses_smartmips_rixi' macro from all the page table bit definitions in 'arch/mips/include/asm' directory. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/pgtable-bits.h | 24 ++++++++++++++---------- arch/mips/include/asm/pgtable.h | 12 ++++++------ 2 files changed, 20 insertions(+), 16 deletions(-) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index e9fe7e9..c266cba 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -79,9 +79,9 @@ /* implemented in software */ #define _PAGE_PRESENT_SHIFT (0) #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) -/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */ -#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) -#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; }) +/* implemented in software, should be unused if cpu_has_ri. */ +#define _PAGE_READ_SHIFT (cpu_has_ri ? _PAGE_PRESENT_SHIFT + 1: _PAGE_PRESENT_SHIFT) +#define _PAGE_READ ({if (!cpu_has_ri) BUG(); 1 << _PAGE_READ_SHIFT; }) /* implemented in software */ #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) @@ -104,12 +104,12 @@ #endif /* Page cannot be executed */ -#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) -#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) +#define _PAGE_NO_EXEC_SHIFT (cpu_has_xi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) +#define _PAGE_NO_EXEC ({if (!cpu_has_xi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) /* Page cannot be read */ -#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) -#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) +#define _PAGE_NO_READ_SHIFT (cpu_has_ri ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) +#define _PAGE_NO_READ ({if (!cpu_has_ri) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) @@ -155,20 +155,24 @@ */ static inline uint64_t pte_to_entrylo(unsigned long pte_val) { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri | cpu_has_xi) { + unsigned long rixi; int sa; #ifdef CONFIG_32BIT sa = 31 - _PAGE_NO_READ_SHIFT; #else sa = 63 - _PAGE_NO_READ_SHIFT; #endif + rixi = ((cpu_has_ri ? _PAGE_NO_READ : 0) | + (cpu_has_xi ? _PAGE_NO_EXEC : 0)); + /* * C has no way to express that this is a DSRL * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily * in the fast path this is done in assembly */ return (pte_val >> _PAGE_GLOBAL_SHIFT) | - ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); + ((pte_val & rixi) << sa); } return pte_val >> _PAGE_GLOBAL_SHIFT; @@ -220,7 +224,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #endif -#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ)) +#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_ri ? 0 : _PAGE_READ)) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index b2202a6..748aa6a 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -22,15 +22,15 @@ struct mm_struct; struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_ri ? 0 : _PAGE_READ) | \ _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ - (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_COPY __pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | \ + (cpu_has_xi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | \ _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ +#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | _PAGE_WRITE | \ _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) @@ -299,7 +299,7 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; - if (kernel_uses_smartmips_rixi) { + if (cpu_has_ri) { if (!(pte_val(pte) & _PAGE_NO_READ)) pte_val(pte) |= _PAGE_SILENT_READ; } else { -- 1.7.9.5 From sjhill@mips.com Wed Sep 5 22:28:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 22:29:59 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:56499 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903410Ab2IEU2P (ORCPT ); Wed, 5 Sep 2012 22:28:15 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1T9MCn-0004QI-29; Wed, 05 Sep 2012 15:28:09 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 4/4] MIPS: Remove kernel_uses_smartmips_rixi macro definition. Date: Wed, 5 Sep 2012 15:27:58 -0500 Message-Id: <1346876878-25965-5-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1346876878-25965-1-git-send-email-sjhill@mips.com> References: <1346876878-25965-1-git-send-email-sjhill@mips.com> X-archive-position: 34422 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1456 Lines: 41 From: "Steven J. Hill" Remove the 'kernel_uses_smartmips_rixi' macro definitions from the architecture header files. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu-features.h | 3 --- .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 -- 2 files changed, 5 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index c78a77b..7452d78 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -95,9 +95,6 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif -#ifndef kernel_uses_smartmips_rixi -#define kernel_uses_smartmips_rixi 0 -#endif #ifndef cpu_has_ri #define cpu_has_ri (cpu_data[0].options & MIPS_CPU_RI) #endif diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index a58addb..971bdc2 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -58,8 +58,6 @@ #define cpu_has_veic 0 #define cpu_hwrena_impl_bits 0xc0000000 -#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) - #define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1 #define spin_lock_prefetch(x) prefetch(x) -- 1.7.9.5 From ddaney.cavm@gmail.com Wed Sep 5 22:48:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 22:48:48 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:44188 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903404Ab2IEUsm (ORCPT ); Wed, 5 Sep 2012 22:48:42 +0200 Received: by dajq27 with SMTP id q27so611590daj.36 for ; Wed, 05 Sep 2012 13:48:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=1PbUfoENGIwd0SofdNoQtEwzY3evpqLfU+Qx6Qypgjw=; b=yN4dHj86acMK332Zeq7WWrDhSgs12N2QUs33KER3OqcSO8JJgDGdE/9Dc9qq6x8D0S t8mwIqLg5CZSWTsV6v3q4sa5mFCBFzQf5g7UbRvYOckEjtJOwt9V7XYS9ekDjLy9DCE8 AHUROamE7KJY//ovJZC5bsaX5toOEHDhGAzB/GvoTWJ+cQGyzCUKox+wpkrpWqd8B97X E7iaA8dD2r8KnVPS1hjTJVj6KSDDYsl/1D5Af09xkfnVHOavdT1SKogNzP7kSa6WpdkL BtjDi5AcCNrptNTC+1Exu8OwU5SLL4jxaVmNi3eb1nII7vEpSmxmGOPDTfFnUrzeLtGQ pm0Q== Received: by 10.66.79.38 with SMTP id g6mr51376857pax.40.1346878115978; Wed, 05 Sep 2012 13:48:35 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id y11sm113427pbv.66.2012.09.05.13.48.33 (version=SSLv3 cipher=OTHER); Wed, 05 Sep 2012 13:48:34 -0700 (PDT) Message-ID: <5047BAA0.1010602@gmail.com> Date: Wed, 05 Sep 2012 13:48:32 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: "Steven J. Hill" , ralf@linux-mips.org CC: linux-mips@linux-mips.org Subject: Re: [PATCH 1/4] MIPS: Add base architecture support for RI and XI. References: <1346876878-25965-1-git-send-email-sjhill@mips.com> <1346876878-25965-2-git-send-email-sjhill@mips.com> In-Reply-To: <1346876878-25965-2-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34423 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3662 Lines: 98 On 09/05/2012 01:27 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Originally both Read Inhibit (RI) and Execute Inhibit (XI) were > supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) > Architecture now defines an optional feature to implement these > TLB bits separately. Support for one or both features can be > checked by looking at the Config3.RXI bit. > > Signed-off-by: Steven J. Hill This particular patch seems fine. Acked-by: David Daney However in order not to break things there has to be a follow-on patch that is applied before any of the subsequent patches that sets cpu_has_ri and cpu_has_xi to the proper values for OCTEON. David Daney > --- > arch/mips/include/asm/cpu-features.h | 6 ++++++ > arch/mips/include/asm/cpu.h | 2 ++ > arch/mips/include/asm/mipsregs.h | 1 + > arch/mips/kernel/cpu-probe.c | 12 +++++++++++- > 4 files changed, 20 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h > index 080edd8..c78a77b 100644 > --- a/arch/mips/include/asm/cpu-features.h > +++ b/arch/mips/include/asm/cpu-features.h > @@ -98,6 +98,12 @@ > #ifndef kernel_uses_smartmips_rixi > #define kernel_uses_smartmips_rixi 0 > #endif > +#ifndef cpu_has_ri > +#define cpu_has_ri (cpu_data[0].options & MIPS_CPU_RI) > +#endif > +#ifndef cpu_has_xi > +#define cpu_has_xi (cpu_data[0].options & MIPS_CPU_XI) > +#endif > #ifndef cpu_has_mmips > #define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) > #endif > diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h > index 4889fae..1b928ed 100644 > --- a/arch/mips/include/asm/cpu.h > +++ b/arch/mips/include/asm/cpu.h > @@ -323,6 +323,8 @@ enum cpu_type_enum { > #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ > #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ > #define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ > +#define MIPS_CPU_RI 0x02000000 /* CPU has TLB Read Inhibit */ > +#define MIPS_CPU_XI 0x04000000 /* CPU has TLB Execute Inhibit */ > > /* > * CPU ASE encodings > diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h > index cdb9c87..19430fb 100644 > --- a/arch/mips/include/asm/mipsregs.h > +++ b/arch/mips/include/asm/mipsregs.h > @@ -591,6 +591,7 @@ > #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) > #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) > #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) > +#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) > #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) > #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) > #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index 009fc13..e85d732 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -422,8 +422,18 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) > > config3 = read_c0_config3(); > > - if (config3 & MIPS_CONF3_SM) > + if (config3 & MIPS_CONF3_SM) { > c->ases |= MIPS_ASE_SMARTMIPS; > + c->options |= MIPS_CPU_RI; > + c->options |= MIPS_CPU_XI; > + } > + if (config3 & MIPS_CONF3_RXI) { > + write_c0_pagegrain(read_c0_pagegrain() | PG_RIE | PG_XIE); > + if (read_c0_pagegrain() & PG_RIE) > + c->options |= MIPS_CPU_RI; > + if (read_c0_pagegrain() & PG_XIE) > + c->options |= MIPS_CPU_XI; > + } > if (config3 & MIPS_CONF3_DSP) > c->ases |= MIPS_ASE_DSP; > if (config3 & MIPS_CONF3_DSP2P) > From ddaney.cavm@gmail.com Wed Sep 5 23:11:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 23:11:42 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:39599 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903404Ab2IEVLg (ORCPT ); Wed, 5 Sep 2012 23:11:36 +0200 Received: by pbbrq8 with SMTP id rq8so1582762pbb.36 for ; Wed, 05 Sep 2012 14:11:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=24EXvvZ5ufYlRcNR0i5pAw348K2IR8fKHL/CFSCFQEo=; b=kuQO+pvVBoc5rG87zSOU/yuib9lO9/BmYIs8YNxhCx62A20mY4Y0WwWS9Hvt4LVGKU HVfnq9di7vsw6Pazkn8RTxau4d+Yno3pKTDnSs3mHyrbxHqP7jrnTNfJ8smYDCL37426 h4C4OZXljwJ3ZM6MLxnW7shcB+cA6BeMrp63EwhAGpMy5JGXf7NedRxRWsEaD0moHGsN C7Ss/GZVokRmyi/s0z6oMtKfwOJB4r+SPRWOFFBxNn8gjlmE+RF5iNkvpurcOFaNEnRV txIvaYMKvQRWMY/CemGmb8V0ryclfhWRu6cOrs7GROh9Hfz+KiHHYq1mdsrALvfSagoP 7ROw== Received: by 10.68.225.196 with SMTP id rm4mr565942pbc.131.1346879489642; Wed, 05 Sep 2012 14:11:29 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id sr3sm149382pbc.44.2012.09.05.14.11.27 (version=SSLv3 cipher=OTHER); Wed, 05 Sep 2012 14:11:28 -0700 (PDT) Message-ID: <5047BFFE.1070109@gmail.com> Date: Wed, 05 Sep 2012 14:11:26 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: "Steven J. Hill" , ralf@linux-mips.org CC: linux-mips@linux-mips.org Subject: Re: [PATCH 2/4] MIPS: Remove kernel_uses_smartmips_rixi use from arch/mips/mm. References: <1346876878-25965-1-git-send-email-sjhill@mips.com> <1346876878-25965-3-git-send-email-sjhill@mips.com> In-Reply-To: <1346876878-25965-3-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34424 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3495 Lines: 87 On 09/05/2012 01:27 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files > in the 'arch/mips/mm' subsystem. > > diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c > index e565d45..90c86ee 100644 > --- a/arch/mips/mm/tlbex.c > +++ b/arch/mips/mm/tlbex.c > @@ -601,7 +601,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, > static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, > unsigned int reg) > { > - if (kernel_uses_smartmips_rixi) { > + if (cpu_has_ri | cpu_has_xi) { > UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); > UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); Patch is out of date. This will not apply against mips-for-linux-next. > } else { > @@ -1021,7 +1021,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, > if (cpu_has_64bits) { > uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ > uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ > - if (kernel_uses_smartmips_rixi) { > + if (cpu_has_ri | cpu_has_xi) { > UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); > UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); > UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); > @@ -1048,7 +1048,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, > UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ > if (r45k_bvahwbug()) > build_tlb_probe_entry(p); > - if (kernel_uses_smartmips_rixi) { > + if (cpu_has_ri | cpu_has_xi) { > UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); > UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); > UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); > @@ -1214,7 +1214,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, > UASM_i_LW(p, even, 0, ptr); /* get even pte */ > UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ > } > - if (kernel_uses_smartmips_rixi) { > + if (cpu_has_ri | cpu_has_xi) { > uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC)); > uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC)); > uasm_i_drotr(p, even, even, > @@ -1576,7 +1576,7 @@ build_pte_present(u32 **p, struct uasm_reloc **r, > { > int t = scratch >= 0 ? scratch : pte; > > - if (kernel_uses_smartmips_rixi) { > + if (cpu_has_ri | cpu_has_xi) { > if (use_bbit_insns()) { > uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); > uasm_i_nop(p); > @@ -1906,7 +1906,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) > if (m4kc_tlbp_war()) > build_tlb_probe_entry(&p); > > - if (kernel_uses_smartmips_rixi) { > + if (cpu_has_ri | cpu_has_xi) { These bits should be made conditional on the value of PageGrain[IEC]. Also when PageGrain[IEC] is set you would have to install the proper exception handlers for TLBRI and TLBXI ExecCodes. > /* > * If the page is not _PAGE_VALID, RI or XI could not > * have triggered it. Skip the expensive test.. > @@ -1960,7 +1960,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) > build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); > build_tlb_probe_entry(&p); > > - if (kernel_uses_smartmips_rixi) { > + if (cpu_has_ri | cpu_has_xi) { > /* > * If the page is not _PAGE_VALID, RI or XI could not > * have triggered it. Skip the expensive test.. > From ddaney.cavm@gmail.com Wed Sep 5 23:16:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 23:16:45 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:62288 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903404Ab2IEVQi (ORCPT ); Wed, 5 Sep 2012 23:16:38 +0200 Received: by dajq27 with SMTP id q27so626477daj.36 for ; Wed, 05 Sep 2012 14:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=n2eRk8HJy2h72mDlo+FubrdGL0u0T85eA3044U9Jq6Q=; b=pKh8x5anbWiNzLcx9ExV41bhagc2k6DESwk8OTKWWbXRQaQEHmQHM4oa/1tkzdN8O/ OL10yR3BkseEQ3Kt7CXgr4kxkTlXjR9b7stK2vCG0/wOeUuTzLdLUStVu1859Cq8Z7X/ ahoFG91AhQ9AMoByR74NCweMN7hMAldd824GmPXUyPc6olgJlyi/I7a6KhpGUlIOfNHH Rpxudte1gpciLBLqN4w+vkZumbY+xjGeG9iqG1jihivDC5Qk+Lwch0ekc3GiN+ih8alz Yb0VgTauuPOiRjd8fPBmlNZ0mU+ZMv9ZXvBkLGX1ufRWHo6G8yEj+NPe+YiOz2ODDxgX 6JJA== Received: by 10.66.76.106 with SMTP id j10mr51420087paw.51.1346879791280; Wed, 05 Sep 2012 14:16:31 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id kt2sm149300pbc.73.2012.09.05.14.16.29 (version=SSLv3 cipher=OTHER); Wed, 05 Sep 2012 14:16:30 -0700 (PDT) Message-ID: <5047C12B.9030002@gmail.com> Date: Wed, 05 Sep 2012 14:16:27 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 3/4] MIPS: Remove kernel_uses_smartmips_rixi from page table bits. References: <1346876878-25965-1-git-send-email-sjhill@mips.com> <1346876878-25965-4-git-send-email-sjhill@mips.com> In-Reply-To: <1346876878-25965-4-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34425 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5849 Lines: 126 On 09/05/2012 01:27 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Remove usage of the 'kernel_uses_smartmips_rixi' macro from all the > page table bit definitions in 'arch/mips/include/asm' directory. > > Signed-off-by: Steven J. Hill > --- > arch/mips/include/asm/pgtable-bits.h | 24 ++++++++++++++---------- > arch/mips/include/asm/pgtable.h | 12 ++++++------ > 2 files changed, 20 insertions(+), 16 deletions(-) > > diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h > index e9fe7e9..c266cba 100644 > --- a/arch/mips/include/asm/pgtable-bits.h > +++ b/arch/mips/include/asm/pgtable-bits.h > @@ -79,9 +79,9 @@ > /* implemented in software */ > #define _PAGE_PRESENT_SHIFT (0) > #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) > -/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */ > -#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) > -#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; }) > +/* implemented in software, should be unused if cpu_has_ri. */ > +#define _PAGE_READ_SHIFT (cpu_has_ri ? _PAGE_PRESENT_SHIFT + 1: _PAGE_PRESENT_SHIFT) As per IRC discussion, it would be nice if the shift value were not dependent on runtime values (cpu_has_ri) See this thread for ideas about this: http://www.linux-mips.org/archives/linux-mips/2011-04/msg00102.html > +#define _PAGE_READ ({if (!cpu_has_ri) BUG(); 1 << _PAGE_READ_SHIFT; }) > /* implemented in software */ > #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) > #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) > @@ -104,12 +104,12 @@ > #endif > > /* Page cannot be executed */ > -#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) > -#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) > +#define _PAGE_NO_EXEC_SHIFT (cpu_has_xi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) > +#define _PAGE_NO_EXEC ({if (!cpu_has_xi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) > > /* Page cannot be read */ > -#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) > -#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) > +#define _PAGE_NO_READ_SHIFT (cpu_has_ri ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) > +#define _PAGE_NO_READ ({if (!cpu_has_ri) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) > > #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) > #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) > @@ -155,20 +155,24 @@ > */ > static inline uint64_t pte_to_entrylo(unsigned long pte_val) > { > - if (kernel_uses_smartmips_rixi) { > + if (cpu_has_ri | cpu_has_xi) { > + unsigned long rixi; > int sa; > #ifdef CONFIG_32BIT > sa = 31 - _PAGE_NO_READ_SHIFT; > #else > sa = 63 - _PAGE_NO_READ_SHIFT; > #endif > + rixi = ((cpu_has_ri ? _PAGE_NO_READ : 0) | > + (cpu_has_xi ? _PAGE_NO_EXEC : 0)); > + > /* > * C has no way to express that this is a DSRL > * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily > * in the fast path this is done in assembly > */ > return (pte_val >> _PAGE_GLOBAL_SHIFT) | > - ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); > + ((pte_val & rixi) << sa); > } > > return pte_val >> _PAGE_GLOBAL_SHIFT; > @@ -220,7 +224,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) > > #endif > > -#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ)) > +#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_ri ? 0 : _PAGE_READ)) > #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) > > #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) > diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h > index b2202a6..748aa6a 100644 > --- a/arch/mips/include/asm/pgtable.h > +++ b/arch/mips/include/asm/pgtable.h > @@ -22,15 +22,15 @@ struct mm_struct; > struct vm_area_struct; > > #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) > -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ > +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_ri ? 0 : _PAGE_READ) | \ > _page_cachable_default) > -#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ > - (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) > -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ > +#define PAGE_COPY __pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | \ > + (cpu_has_xi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) > +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | \ > _page_cachable_default) > #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ > _PAGE_GLOBAL | _page_cachable_default) > -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ > +#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | _PAGE_WRITE | \ > _page_cachable_default) > #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ > __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) > @@ -299,7 +299,7 @@ static inline pte_t pte_mkdirty(pte_t pte) > static inline pte_t pte_mkyoung(pte_t pte) > { > pte_val(pte) |= _PAGE_ACCESSED; > - if (kernel_uses_smartmips_rixi) { > + if (cpu_has_ri) { > if (!(pte_val(pte) & _PAGE_NO_READ)) > pte_val(pte) |= _PAGE_SILENT_READ; > } else { > From ddaney.cavm@gmail.com Wed Sep 5 23:22:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 23:22:25 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:60035 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903404Ab2IEVWU (ORCPT ); Wed, 5 Sep 2012 23:22:20 +0200 Received: by pbbrq8 with SMTP id rq8so1594905pbb.36 for ; Wed, 05 Sep 2012 14:22:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=W2rVSZPlvP+2xOBQJm83D3E0BWQpoZ4cGB3zci18QaA=; b=JHB6aZNsiP5004ojuLLB7oYY1plwuiOgLZC/Y2e59AWMuaINxv1hljW1MVQupz5pY7 NB4irb1g+t0XT7QKw0WWuSi9xX1L8pXjx3hsPpnAYksgSI7MTkuEOYTWJifjQGIUS46+ sKk7NX32JKTli0Mnkg8vlNaIq8zzCPKF4EPr21eZ5d9qquhdTvAJN6mdVDoI/Gq1sI3U iz8P167jaR6JdD2cFFjqFdDJjOd+U+C6PxBE4ObLnntL3BUGA3GX/N9XRhhReTYDpNB9 q8jpE5SK4JKy2H6NSBEIpVD46paqCTTSHOPlX1DTDsHsVE7bXFxF/GEWmZWFmb2fzF0x nAmA== Received: by 10.66.76.106 with SMTP id j10mr51447795paw.51.1346880133586; Wed, 05 Sep 2012 14:22:13 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id uj3sm171742pbc.39.2012.09.05.14.22.11 (version=SSLv3 cipher=OTHER); Wed, 05 Sep 2012 14:22:12 -0700 (PDT) Message-ID: <5047C27E.7070007@gmail.com> Date: Wed, 05 Sep 2012 14:22:06 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: "Steven J. Hill" , ralf@linux-mips.org CC: linux-mips@linux-mips.org Subject: Re: [PATCH 4/4] MIPS: Remove kernel_uses_smartmips_rixi macro definition. References: <1346876878-25965-1-git-send-email-sjhill@mips.com> <1346876878-25965-5-git-send-email-sjhill@mips.com> In-Reply-To: <1346876878-25965-5-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34426 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1860 Lines: 51 On 09/05/2012 01:27 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Remove the 'kernel_uses_smartmips_rixi' macro definitions from > the architecture header files. > > Signed-off-by: Steven J. Hill > --- > arch/mips/include/asm/cpu-features.h | 3 --- > .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 -- > 2 files changed, 5 deletions(-) > > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h > index c78a77b..7452d78 100644 > --- a/arch/mips/include/asm/cpu-features.h > +++ b/arch/mips/include/asm/cpu-features.h > @@ -95,9 +95,6 @@ > #ifndef cpu_has_smartmips > #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) > #endif > -#ifndef kernel_uses_smartmips_rixi > -#define kernel_uses_smartmips_rixi 0 As I said in the other message, you will want to have the replacement for this instance of kernel_uses_smartmips_rixi in place before you do the other conversions. That said, at the end of the patch set, this does need to go, so something like this will be needed. David Daney > -#endif > #ifndef cpu_has_ri > #define cpu_has_ri (cpu_data[0].options & MIPS_CPU_RI) > #endif > diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h > index a58addb..971bdc2 100644 > --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h > +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h > @@ -58,8 +58,6 @@ > #define cpu_has_veic 0 > #define cpu_hwrena_impl_bits 0xc0000000 > > -#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) > - > #define ARCH_HAS_IRQ_PER_CPU 1 > #define ARCH_HAS_SPINLOCK_PREFETCH 1 > #define spin_lock_prefetch(x) prefetch(x) > From ddaney.cavm@gmail.com Wed Sep 5 23:51:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Sep 2012 23:51:50 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:42192 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903404Ab2IEVvp (ORCPT ); Wed, 5 Sep 2012 23:51:45 +0200 Received: by pbbrq8 with SMTP id rq8so1627462pbb.36 for ; Wed, 05 Sep 2012 14:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=xzFpxcv0mcXc6mAa+y/4HofLC97W9dKVxv/o2UBqnOI=; b=ipPpLYcWVP/23bK8P+H1Mfr40+Jyp07vQmHK5GThwWwKtKuAUJNz6JxmkFkj8WvdSo pvj+ABtGdvl4ZFKYBy4PLnMZcaavWCL+uERVlK12gW3B9CDSq1k5IvbbYDPLIP2UUisJ n95u7EBQurGF1aYy1RrA34JpNJ1gFcBWveUr7z6ghyXhNuSi8pKXP7qHO/yxStSbKNo6 7HSlMXef89mDbdj6nwd6ruhAxzVzZ1vrM03SvokGbTTj3avL6NIwE6NjGGJ1BsJ7WNRi 1C9rJoKx8FOGYO5d7Ec+6aIymlZXGEdRQZRVrEedRvALIa8QpmOrHPw+bfXPNRl7W5kO q07w== Received: by 10.68.224.161 with SMTP id rd1mr782764pbc.133.1346881898161; Wed, 05 Sep 2012 14:51:38 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ou6sm222687pbc.9.2012.09.05.14.51.36 (version=SSLv3 cipher=OTHER); Wed, 05 Sep 2012 14:51:37 -0700 (PDT) Message-ID: <5047C967.2010709@gmail.com> Date: Wed, 05 Sep 2012 14:51:35 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: "Steven J. Hill" , ralf@linux-mips.org CC: linux-mips@linux-mips.org Subject: Re: [PATCH 1/4] MIPS: Add base architecture support for RI and XI. References: <1346876878-25965-1-git-send-email-sjhill@mips.com> <1346876878-25965-2-git-send-email-sjhill@mips.com> <5047BAA0.1010602@gmail.com> In-Reply-To: <5047BAA0.1010602@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34427 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4513 Lines: 127 On 09/05/2012 01:48 PM, David Daney wrote: > On 09/05/2012 01:27 PM, Steven J. Hill wrote: >> From: "Steven J. Hill" >> >> Originally both Read Inhibit (RI) and Execute Inhibit (XI) were >> supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) >> Architecture now defines an optional feature to implement these >> TLB bits separately. Support for one or both features can be >> checked by looking at the Config3.RXI bit. >> >> Signed-off-by: Steven J. Hill > > This particular patch seems fine. > > Acked-by: David Daney Sorry, I changed my mind. NAK. > > > However in order not to break things there has to be a follow-on patch > that is applied before any of the subsequent patches that sets > cpu_has_ri and cpu_has_xi to the proper values for OCTEON. > > David Daney > > >> --- >> arch/mips/include/asm/cpu-features.h | 6 ++++++ >> arch/mips/include/asm/cpu.h | 2 ++ >> arch/mips/include/asm/mipsregs.h | 1 + >> arch/mips/kernel/cpu-probe.c | 12 +++++++++++- >> 4 files changed, 20 insertions(+), 1 deletion(-) >> >> diff --git a/arch/mips/include/asm/cpu-features.h >> b/arch/mips/include/asm/cpu-features.h >> index 080edd8..c78a77b 100644 >> --- a/arch/mips/include/asm/cpu-features.h >> +++ b/arch/mips/include/asm/cpu-features.h >> @@ -98,6 +98,12 @@ >> #ifndef kernel_uses_smartmips_rixi >> #define kernel_uses_smartmips_rixi 0 >> #endif >> +#ifndef cpu_has_ri >> +#define cpu_has_ri (cpu_data[0].options & MIPS_CPU_RI) >> +#endif >> +#ifndef cpu_has_xi >> +#define cpu_has_xi (cpu_data[0].options & MIPS_CPU_XI) Nobody in their right mind would implement only one of RI or XI. So splitting this feature into two parts just adds complication with no benefit. Unless you have evidence that there is actual silicon that only implements one of the two, there is no reason to split this, and to way to test it. You can just keep kernel_uses_smartmips_rixi, and the rest of the patch set is mostly unneeded. >> +#endif >> #ifndef cpu_has_mmips >> #define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) >> #endif >> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h >> index 4889fae..1b928ed 100644 >> --- a/arch/mips/include/asm/cpu.h >> +++ b/arch/mips/include/asm/cpu.h >> @@ -323,6 +323,8 @@ enum cpu_type_enum { >> #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 >> external interrupt controller mode */ >> #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ >> #define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS >> capability */ >> +#define MIPS_CPU_RI 0x02000000 /* CPU has TLB Read Inhibit */ >> +#define MIPS_CPU_XI 0x04000000 /* CPU has TLB Execute Inhibit */ ... and only one new bit needed here. ... >> >> /* >> * CPU ASE encodings >> diff --git a/arch/mips/include/asm/mipsregs.h >> b/arch/mips/include/asm/mipsregs.h >> index cdb9c87..19430fb 100644 >> --- a/arch/mips/include/asm/mipsregs.h >> +++ b/arch/mips/include/asm/mipsregs.h >> @@ -591,6 +591,7 @@ >> #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) >> #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) >> #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) >> +#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) >> #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) >> #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) >> #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) >> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c >> index 009fc13..e85d732 100644 >> --- a/arch/mips/kernel/cpu-probe.c >> +++ b/arch/mips/kernel/cpu-probe.c >> @@ -422,8 +422,18 @@ static inline unsigned int decode_config3(struct >> cpuinfo_mips *c) >> >> config3 = read_c0_config3(); >> >> - if (config3 & MIPS_CONF3_SM) >> + if (config3 & MIPS_CONF3_SM) { >> c->ases |= MIPS_ASE_SMARTMIPS; >> + c->options |= MIPS_CPU_RI; >> + c->options |= MIPS_CPU_XI; >> + } >> + if (config3 & MIPS_CONF3_RXI) { >> + write_c0_pagegrain(read_c0_pagegrain() | PG_RIE | PG_XIE); >> + if (read_c0_pagegrain() & PG_RIE) >> + c->options |= MIPS_CPU_RI; >> + if (read_c0_pagegrain() & PG_XIE) >> + c->options |= MIPS_CPU_XI; >> + } ... and this bit becomes a little simpler. >> if (config3 & MIPS_CONF3_DSP) >> c->ases |= MIPS_ASE_DSP; >> if (config3 & MIPS_CONF3_DSP2P) >> > From jim2101024@gmail.com Thu Sep 6 00:33:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 00:33:12 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:1988 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903405Ab2IEWdF (ORCPT ); Thu, 6 Sep 2012 00:33:05 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 05 Sep 2012 15:31:27 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Wed, 5 Sep 2012 15:32:52 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 84F9F9F9F5; Wed, 5 Sep 2012 15:32:51 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com, "Jim Quinlan" Subject: [PATCH V4 1/3] MIPS: bitops.h: change use of 'unsigned short' to 'int' Date: Wed, 5 Sep 2012 18:32:45 -0400 Message-ID: <1346884367-6906-2-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1346884367-6906-1-git-send-email-jim2101024@gmail.com> References: <1346884367-6906-1-git-send-email-jim2101024@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C590D353NK23809176-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34428 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2602 Lines: 76 Signed-off-by: Jim Quinlan --- arch/mips/include/asm/bitops.h | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 82ad35c..455664c 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -57,7 +57,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long temp; if (kernel_uses_llsc && R10000_LLSC_WAR) { @@ -118,7 +118,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long temp; if (kernel_uses_llsc && R10000_LLSC_WAR) { @@ -191,7 +191,7 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad */ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; if (kernel_uses_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); @@ -244,7 +244,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long res; smp_mb__before_llsc(); @@ -310,7 +310,7 @@ static inline int test_and_set_bit(unsigned long nr, static inline int test_and_set_bit_lock(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long res; if (kernel_uses_llsc && R10000_LLSC_WAR) { @@ -373,7 +373,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long res; smp_mb__before_llsc(); @@ -457,7 +457,7 @@ static inline int test_and_clear_bit(unsigned long nr, static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long res; smp_mb__before_llsc(); -- 1.7.6 From jim2101024@gmail.com Thu Sep 6 00:33:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 00:33:37 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:1990 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903404Ab2IEWdI (ORCPT ); Thu, 6 Sep 2012 00:33:08 +0200 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 05 Sep 2012 15:31:28 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Wed, 5 Sep 2012 15:32:16 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 647A59F9F5; Wed, 5 Sep 2012 15:32:52 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com, "Jim Quinlan" Subject: [PATCH V4 2/3] MIPS: Remove irqflags.h dependency from bitops.h Date: Wed, 5 Sep 2012 18:32:46 -0400 Message-ID: <1346884367-6906-3-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1346884367-6906-1-git-send-email-jim2101024@gmail.com> References: <1346884367-6906-1-git-send-email-jim2101024@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C590D4A3NK23809179-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34429 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10680 Lines: 409 The "else clause" of most functions in bitops.h invoked raw_local_irq_{save,restore}() and in doing so had a dependency on irqflags.h. This fix moves said code to bitops.c, removing the dependency. Signed-off-by: Jim Quinlan --- arch/mips/include/asm/bitops.h | 114 +++++++------------------ arch/mips/include/asm/io.h | 1 + arch/mips/lib/Makefile | 2 +- arch/mips/lib/bitops.c | 179 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 213 insertions(+), 83 deletions(-) create mode 100644 arch/mips/lib/bitops.c diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 455664c..46ac73a 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -14,7 +14,6 @@ #endif #include -#include #include #include #include /* sigh ... */ @@ -44,6 +43,24 @@ #define smp_mb__before_clear_bit() smp_mb__before_llsc() #define smp_mb__after_clear_bit() smp_llsc_mb() + +/* + * These are the "slower" versions of the functions and are in bitops.c. + * These functions call raw_local_irq_{save,restore}(). + */ +void __mips_set_bit(unsigned long nr, volatile unsigned long *addr); +void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr); +void __mips_change_bit(unsigned long nr, volatile unsigned long *addr); +int __mips_test_and_set_bit(unsigned long nr, + volatile unsigned long *addr); +int __mips_test_and_set_bit_lock(unsigned long nr, + volatile unsigned long *addr); +int __mips_test_and_clear_bit(unsigned long nr, + volatile unsigned long *addr); +int __mips_test_and_change_bit(unsigned long nr, + volatile unsigned long *addr); + + /* * set_bit - Atomically set a bit in memory * @nr: the bit to set @@ -92,17 +109,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) : "=&r" (temp), "+m" (*m) : "ir" (1UL << bit)); } while (unlikely(!temp)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a |= mask; - raw_local_irq_restore(flags); - } + } else + __mips_set_bit(nr, addr); } /* @@ -153,17 +161,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) : "=&r" (temp), "+m" (*m) : "ir" (~(1UL << bit))); } while (unlikely(!temp)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a &= ~mask; - raw_local_irq_restore(flags); - } + } else + __mips_clear_bit(nr, addr); } /* @@ -220,17 +219,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) : "=&r" (temp), "+m" (*m) : "ir" (1UL << bit)); } while (unlikely(!temp)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a ^= mask; - raw_local_irq_restore(flags); - } + } else + __mips_change_bit(nr, addr); } /* @@ -281,18 +271,8 @@ static inline int test_and_set_bit(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a |= mask; - raw_local_irq_restore(flags); - } + } else + res = __mips_test_and_set_bit(nr, addr); smp_llsc_mb(); @@ -345,18 +325,8 @@ static inline int test_and_set_bit_lock(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a |= mask; - raw_local_irq_restore(flags); - } + } else + res = __mips_test_and_set_bit_lock(nr, addr); smp_llsc_mb(); @@ -428,18 +398,8 @@ static inline int test_and_clear_bit(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a &= ~mask; - raw_local_irq_restore(flags); - } + } else + res = __mips_test_and_clear_bit(nr, addr); smp_llsc_mb(); @@ -494,18 +454,8 @@ static inline int test_and_change_bit(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a ^= mask; - raw_local_irq_restore(flags); - } + } else + res = __mips_test_and_change_bit(nr, addr); smp_llsc_mb(); diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 29d9c23..ff2e034 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index c4a82e8..a7b8937 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o delay.o memcpy.o memset.o \ +lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ strlen_user.o strncpy_user.o strnlen_user.o uncached.o obj-y += iomap.o diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c new file mode 100644 index 0000000..239a9c9 --- /dev/null +++ b/arch/mips/lib/bitops.c @@ -0,0 +1,179 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org) + * Copyright (c) 1999, 2000 Silicon Graphics, Inc. + */ +#include +#include +#include + + +/** + * __mips_set_bit - Atomically set a bit in memory. This is called by + * set_bit() if it cannot find a faster solution. + * @nr: the bit to set + * @addr: the address to start counting from + */ +void __mips_set_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + *a |= mask; + raw_local_irq_restore(flags); +} +EXPORT_SYMBOL(__mips_set_bit); + + +/** + * __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if + * it cannot find a faster solution. + * @nr: Bit to clear + * @addr: Address to start counting from + */ +void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + *a &= ~mask; + raw_local_irq_restore(flags); +} +EXPORT_SYMBOL(__mips_clear_bit); + + +/** + * __mips_change_bit - Toggle a bit in memory. This is called by change_bit() + * if it cannot find a faster solution. + * @nr: Bit to change + * @addr: Address to start counting from + */ +void __mips_change_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + *a ^= mask; + raw_local_irq_restore(flags); +} +EXPORT_SYMBOL(__mips_change_bit); + + +/** + * __mips_test_and_set_bit - Set a bit and return its old value. This is + * called by test_and_set_bit() if it cannot find a faster solution. + * @nr: Bit to set + * @addr: Address to count from + */ +int __mips_test_and_set_bit(unsigned long nr, + volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a |= mask; + raw_local_irq_restore(flags); + return res; +} +EXPORT_SYMBOL(__mips_test_and_set_bit); + + +/** + * __mips_test_and_set_bit_lock - Set a bit and return its old value. This is + * called by test_and_set_bit_lock() if it cannot find a faster solution. + * @nr: Bit to set + * @addr: Address to count from + */ +int __mips_test_and_set_bit_lock(unsigned long nr, + volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a |= mask; + raw_local_irq_restore(flags); + return res; +} +EXPORT_SYMBOL(__mips_test_and_set_bit_lock); + + +/** + * __mips_test_and_clear_bit - Clear a bit and return its old value. This is + * called by test_and_clear_bit() if it cannot find a faster solution. + * @nr: Bit to clear + * @addr: Address to count from + */ +int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a &= ~mask; + raw_local_irq_restore(flags); + return res; +} +EXPORT_SYMBOL(__mips_test_and_clear_bit); + + +/** + * __mips_test_and_change_bit - Change a bit and return its old value. This is + * called by test_and_change_bit() if it cannot find a faster solution. + * @nr: Bit to change + * @addr: Address to count from + */ +int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a ^= mask; + raw_local_irq_restore(flags); + return res; +} +EXPORT_SYMBOL(__mips_test_and_change_bit); -- 1.7.6 From jim2101024@gmail.com Thu Sep 6 00:33:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 00:34:01 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:1809 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903407Ab2IEWdI (ORCPT ); Thu, 6 Sep 2012 00:33:08 +0200 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 05 Sep 2012 15:31:26 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Wed, 5 Sep 2012 15:32:14 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id C0D459F9F6; Wed, 5 Sep 2012 15:32:50 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com Subject: [PATCH V4 0/3] MIPS: make funcs preempt-safe for non-mipsr2 cpus Date: Wed, 5 Sep 2012 18:32:44 -0400 Message-ID: <1346884367-6906-1-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 MIME-Version: 1.0 X-WSS-ID: 7C590D343NK23809173-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34430 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 977 Lines: 25 This is V4 of my submission. Here is a list of requested changes: o Extra commit was added for changing an unsigned short to an int. o Use of EXTERN_SYMBOL was added to mips-atomic.c and bitops.c, as well as the removal of 'extern' in the functions' declarations. o Name of funcs changed from atomic_xxx to __mips_xxx in bitops.c. o The function comments in bitops.c were tweaked to please scripts/kernel-doc. Here is a list of requested changes that were not done (and why): o Suggested optimization of _MIPS_SZLONG and others was not needed as mips-atomic.c now includes . o Suggested fixes to please checkpatch.pl for whitespace before newlines in asm strings was attempted but the result made the assembly code look more cluttered => no change made. These were unrequested changes: o Changed order of func listings in irqflags.h so that only one #ifdef/#endif pair was needed instead of three. Jim Quinlan From jim2101024@gmail.com Thu Sep 6 00:33:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 00:34:27 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:4746 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903408Ab2IEWdL (ORCPT ); Thu, 6 Sep 2012 00:33:11 +0200 Received: from [10.9.200.131] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 05 Sep 2012 15:31:58 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Wed, 5 Sep 2012 15:32:53 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 3B1D49F9F5; Wed, 5 Sep 2012 15:32:53 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com, "Jim Quinlan" Subject: [PATCH V4 3/3] MIPS: make funcs preempt-safe for non-mipsr2 cpus Date: Wed, 5 Sep 2012 18:32:47 -0400 Message-ID: <1346884367-6906-4-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1346884367-6906-1-git-send-email-jim2101024@gmail.com> References: <1346884367-6906-1-git-send-email-jim2101024@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C590D543MK28706377-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34431 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13564 Lines: 512 For non MIPSr2 processors, such as the BMIPS 5000, calls to arch_local_irq_disable() and others may be preempted, and in doing so a stale value may be restored to c0_status. This fix disables preemption for such processors prior to the call and enables it after the call. Those functions that needed this fix have been "outlined" to mips-atomic.c, as they are no longer good candidates for inlining. This bug was observed in a BMIPS 5000, occuring once every few hours in a continuous reboot test. It was traced to the write_lock_irq() function which was being invoked in release_task() in exit.c. By placing a number of "nops" inbetween the mfc0/mtc0 pair in arch_local_irq_disable(), which is called by write_lock_irq(), we were able to greatly increase the occurance of this bug. Similarly, the application of this commit silenced the bug. Signed-off-by: Jim Quinlan --- arch/mips/include/asm/irqflags.h | 207 ++++++++++++++------------------------ arch/mips/lib/Makefile | 3 +- arch/mips/lib/mips-atomic.c | 176 ++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+), 133 deletions(-) create mode 100644 arch/mips/lib/mips-atomic.c diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h index 309cbcd..9f3384c 100644 --- a/arch/mips/include/asm/irqflags.h +++ b/arch/mips/include/asm/irqflags.h @@ -16,83 +16,13 @@ #include #include -__asm__( - " .macro arch_local_irq_enable \n" - " .set push \n" - " .set reorder \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n" - " ori $1, 0x400 \n" - " xori $1, 0x400 \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) - " ei \n" -#else - " mfc0 $1,$12 \n" - " ori $1,0x1f \n" - " xori $1,0x1e \n" - " mtc0 $1,$12 \n" -#endif - " irq_enable_hazard \n" - " .set pop \n" - " .endm"); +#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) -extern void smtc_ipi_replay(void); - -static inline void arch_local_irq_enable(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC kernel needs to do a software replay of queued - * IPIs, at the cost of call overhead on each local_irq_enable() - */ - smtc_ipi_replay(); -#endif - __asm__ __volatile__( - "arch_local_irq_enable" - : /* no outputs */ - : /* no inputs */ - : "memory"); -} - - -/* - * For cli() we have to insert nops to make sure that the new value - * has actually arrived in the status register before the end of this - * macro. - * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs - * no nops at all. - */ -/* - * For TX49, operating only IE bit is not enough. - * - * If mfc0 $12 follows store and the mfc0 is last instruction of a - * page and fetching the next instruction causes TLB miss, the result - * of the mfc0 might wrongly contain EXL bit. - * - * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 - * - * Workaround: mask EXL bit of the result or place a nop before mfc0. - */ __asm__( " .macro arch_local_irq_disable\n" " .set push \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 \n" - " ori $1, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) " di \n" -#else - " mfc0 $1,$12 \n" - " ori $1,0x1f \n" - " xori $1,0x1f \n" - " .set noreorder \n" - " mtc0 $1,$12 \n" -#endif " irq_disable_hazard \n" " .set pop \n" " .endm \n"); @@ -106,46 +36,14 @@ static inline void arch_local_irq_disable(void) : "memory"); } -__asm__( - " .macro arch_local_save_flags flags \n" - " .set push \n" - " .set reorder \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\flags, $2, 1 \n" -#else - " mfc0 \\flags, $12 \n" -#endif - " .set pop \n" - " .endm \n"); - -static inline unsigned long arch_local_save_flags(void) -{ - unsigned long flags; - asm volatile("arch_local_save_flags %0" : "=r" (flags)); - return flags; -} __asm__( " .macro arch_local_irq_save result \n" " .set push \n" " .set reorder \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\result, $2, 1 \n" - " ori $1, \\result, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" - " andi \\result, \\result, 0x400 \n" -#elif defined(CONFIG_CPU_MIPSR2) " di \\result \n" " andi \\result, 1 \n" -#else - " mfc0 \\result, $12 \n" - " ori $1, \\result, 0x1f \n" - " xori $1, 0x1f \n" - " .set noreorder \n" - " mtc0 $1, $12 \n" -#endif " irq_disable_hazard \n" " .set pop \n" " .endm \n"); @@ -160,61 +58,37 @@ static inline unsigned long arch_local_irq_save(void) return flags; } + __asm__( " .macro arch_local_irq_restore flags \n" " .set push \n" " .set noreorder \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - "mfc0 $1, $2, 1 \n" - "andi \\flags, 0x400 \n" - "ori $1, 0x400 \n" - "xori $1, 0x400 \n" - "or \\flags, $1 \n" - "mtc0 \\flags, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) +#if defined(CONFIG_IRQ_CPU) /* * Slow, but doesn't suffer from a relatively unlikely race * condition we're having since days 1. */ " beqz \\flags, 1f \n" - " di \n" + " di \n" " ei \n" "1: \n" -#elif defined(CONFIG_CPU_MIPSR2) +#else /* * Fast, dangerous. Life is fun, life is good. */ " mfc0 $1, $12 \n" " ins $1, \\flags, 0, 1 \n" " mtc0 $1, $12 \n" -#else - " mfc0 $1, $12 \n" - " andi \\flags, 1 \n" - " ori $1, 0x1f \n" - " xori $1, 0x1f \n" - " or \\flags, $1 \n" - " mtc0 \\flags, $12 \n" #endif " irq_disable_hazard \n" " .set pop \n" " .endm \n"); - static inline void arch_local_irq_restore(unsigned long flags) { unsigned long __tmp1; -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC kernel needs to do a software replay of queued - * IPIs, at the cost of branch and call overhead on each - * local_irq_restore() - */ - if (unlikely(!(flags & 0x0400))) - smtc_ipi_replay(); -#endif - __asm__ __volatile__( "arch_local_irq_restore\t%0" : "=r" (__tmp1) @@ -232,6 +106,75 @@ static inline void __arch_local_irq_restore(unsigned long flags) : "0" (flags) : "memory"); } +#else +/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */ +void arch_local_irq_disable(void); +unsigned long arch_local_irq_save(void); +void arch_local_irq_restore(unsigned long flags); +void __arch_local_irq_restore(unsigned long flags); +#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */ + + +__asm__( + " .macro arch_local_irq_enable \n" + " .set push \n" + " .set reorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n" + " ori $1, 0x400 \n" + " xori $1, 0x400 \n" + " mtc0 $1, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) + " ei \n" +#else + " mfc0 $1,$12 \n" + " ori $1,0x1f \n" + " xori $1,0x1e \n" + " mtc0 $1,$12 \n" +#endif + " irq_enable_hazard \n" + " .set pop \n" + " .endm"); + +extern void smtc_ipi_replay(void); + +static inline void arch_local_irq_enable(void) +{ +#ifdef CONFIG_MIPS_MT_SMTC + /* + * SMTC kernel needs to do a software replay of queued + * IPIs, at the cost of call overhead on each local_irq_enable() + */ + smtc_ipi_replay(); +#endif + __asm__ __volatile__( + "arch_local_irq_enable" + : /* no outputs */ + : /* no inputs */ + : "memory"); +} + + +__asm__( + " .macro arch_local_save_flags flags \n" + " .set push \n" + " .set reorder \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 \\flags, $2, 1 \n" +#else + " mfc0 \\flags, $12 \n" +#endif + " .set pop \n" + " .endm \n"); + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("arch_local_save_flags %0" : "=r" (flags)); + return flags; +} + static inline int arch_irqs_disabled_flags(unsigned long flags) { @@ -245,7 +188,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) #endif } -#endif +#endif /* #ifndef __ASSEMBLY__ */ /* * Do the CPU's IRQ-state tracing from assembly code. diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index a7b8937..eeddc58 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -3,7 +3,8 @@ # lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ - strlen_user.o strncpy_user.o strnlen_user.o uncached.o + mips-atomic.o strlen_user.o strncpy_user.o \ + strnlen_user.o uncached.o obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c new file mode 100644 index 0000000..e091430 --- /dev/null +++ b/arch/mips/lib/mips-atomic.c @@ -0,0 +1,176 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#include +#include +#include +#include +#include + +#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) + +/* + * For cli() we have to insert nops to make sure that the new value + * has actually arrived in the status register before the end of this + * macro. + * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs + * no nops at all. + */ +/* + * For TX49, operating only IE bit is not enough. + * + * If mfc0 $12 follows store and the mfc0 is last instruction of a + * page and fetching the next instruction causes TLB miss, the result + * of the mfc0 might wrongly contain EXL bit. + * + * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 + * + * Workaround: mask EXL bit of the result or place a nop before mfc0. + */ +__asm__( + " .macro arch_local_irq_disable\n" + " .set push \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 $1, $2, 1 \n" + " ori $1, 0x400 \n" + " .set noreorder \n" + " mtc0 $1, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) + /* see irqflags.h for inline function */ +#else + " mfc0 $1,$12 \n" + " ori $1,0x1f \n" + " xori $1,0x1f \n" + " .set noreorder \n" + " mtc0 $1,$12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +void arch_local_irq_disable(void) +{ + preempt_disable(); + __asm__ __volatile__( + "arch_local_irq_disable" + : /* no outputs */ + : /* no inputs */ + : "memory"); + preempt_enable(); +} +EXPORT_SYMBOL(arch_local_irq_disable); + + +__asm__( + " .macro arch_local_irq_save result \n" + " .set push \n" + " .set reorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 \\result, $2, 1 \n" + " ori $1, \\result, 0x400 \n" + " .set noreorder \n" + " mtc0 $1, $2, 1 \n" + " andi \\result, \\result, 0x400 \n" +#elif defined(CONFIG_CPU_MIPSR2) + /* see irqflags.h for inline function */ +#else + " mfc0 \\result, $12 \n" + " ori $1, \\result, 0x1f \n" + " xori $1, 0x1f \n" + " .set noreorder \n" + " mtc0 $1, $12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + preempt_disable(); + asm volatile("arch_local_irq_save\t%0" + : "=r" (flags) + : /* no inputs */ + : "memory"); + preempt_enable(); + return flags; +} +EXPORT_SYMBOL(arch_local_irq_save); + + +__asm__( + " .macro arch_local_irq_restore flags \n" + " .set push \n" + " .set noreorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + "mfc0 $1, $2, 1 \n" + "andi \\flags, 0x400 \n" + "ori $1, 0x400 \n" + "xori $1, 0x400 \n" + "or \\flags, $1 \n" + "mtc0 \\flags, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) + /* see irqflags.h for inline function */ +#elif defined(CONFIG_CPU_MIPSR2) + /* see irqflags.h for inline function */ +#else + " mfc0 $1, $12 \n" + " andi \\flags, 1 \n" + " ori $1, 0x1f \n" + " xori $1, 0x1f \n" + " or \\flags, $1 \n" + " mtc0 \\flags, $12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +void arch_local_irq_restore(unsigned long flags) +{ + unsigned long __tmp1; + +#ifdef CONFIG_MIPS_MT_SMTC + /* + * SMTC kernel needs to do a software replay of queued + * IPIs, at the cost of branch and call overhead on each + * local_irq_restore() + */ + if (unlikely(!(flags & 0x0400))) + smtc_ipi_replay(); +#endif + preempt_disable(); + __asm__ __volatile__( + "arch_local_irq_restore\t%0" + : "=r" (__tmp1) + : "0" (flags) + : "memory"); + preempt_enable(); +} +EXPORT_SYMBOL(arch_local_irq_restore); + + +void __arch_local_irq_restore(unsigned long flags) +{ + unsigned long __tmp1; + + preempt_disable(); + __asm__ __volatile__( + "arch_local_irq_restore\t%0" + : "=r" (__tmp1) + : "0" (flags) + : "memory"); + preempt_enable(); +} +EXPORT_SYMBOL(__arch_local_irq_restore); + +#endif /* !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) */ -- 1.7.6 From cernekee@gmail.com Thu Sep 6 01:30:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 01:30:35 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:42860 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903404Ab2IEXa3 (ORCPT ); Thu, 6 Sep 2012 01:30:29 +0200 Received: by eaai12 with SMTP id i12so355130eaa.36 for ; Wed, 05 Sep 2012 16:30:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=WzschZMRJzE+KaP51EZSOHk6yptNVSVM/LYEEmupikc=; b=qkQwFxdvGuE3nDpY1QjRa0K0yYIQwG1jj3WvmiGlTi2xNkUoxOgSd+pIJojT1DwoxI m4W/87R50sFjZfY9RiBdRmTbYlxZa/1Uu2urxJCmhA1LGoixUS4fXC/TfGFsKpDBdKX5 3qULmYxmFz//Tdztr9KQefepITuYfNwFHYfst0Vtx53DKdINr0jrCPHh4xyf2FX0oRhG UedrBlrBa4D9Z8lrCrnVrP/MCds3Snjty2jRXA0RRjX9RNWcvf/eQo2kOeNnjgROuJyF B7dRhZBJoimaPpuCuv6zdnLD3dWIF5c3R8sHTF1FKP2Vxj0hS//x/o9gJV0wF2HFurNJ mKiQ== MIME-Version: 1.0 Received: by 10.14.202.66 with SMTP id c42mr179156eeo.35.1346887824305; Wed, 05 Sep 2012 16:30:24 -0700 (PDT) Received: by 10.14.179.71 with HTTP; Wed, 5 Sep 2012 16:30:24 -0700 (PDT) In-Reply-To: <5047C967.2010709@gmail.com> References: <1346876878-25965-1-git-send-email-sjhill@mips.com> <1346876878-25965-2-git-send-email-sjhill@mips.com> <5047BAA0.1010602@gmail.com> <5047C967.2010709@gmail.com> Date: Wed, 5 Sep 2012 16:30:24 -0700 Message-ID: Subject: Re: [PATCH 1/4] MIPS: Add base architecture support for RI and XI. From: Kevin Cernekee To: David Daney Cc: "Steven J. Hill" , ralf@linux-mips.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 34432 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 641 Lines: 13 On Wed, Sep 5, 2012 at 2:51 PM, David Daney wrote: > Nobody in their right mind would implement only one of RI or XI. So > splitting this feature into two parts just adds complication with no > benefit. Unless you have evidence that there is actual silicon that only > implements one of the two, there is no reason to split this, and to way to > test it. > > You can just keep kernel_uses_smartmips_rixi, and the rest of the patch set > is mostly unneeded. Recent BMIPS4380/BMIPS5000 cores support the XI bit, and ignore the RI bit. AFAICT it is safe to just use kernel_uses_smartmips_rixi=1 on these processors. From ddaney.cavm@gmail.com Thu Sep 6 01:45:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 01:45:25 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:63329 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903407Ab2IEXpW (ORCPT ); Thu, 6 Sep 2012 01:45:22 +0200 Received: by pbbrq8 with SMTP id rq8so1742550pbb.36 for ; Wed, 05 Sep 2012 16:45:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=OxhiQPJa/Hq9bcj5s9ZhwdF/9lzpCPLfeNrQvQz04pE=; b=0BQwBCOJy66MsyV2QIjL2G9Q+V7Y6Idn/kC+YnvonyQzL6XXFIWdnBn+1jv2UMcjrY 0tOXBBkAnhCmzStjCLACq2Hb2VolF43d7SUab0g+4L+cnxGDCO78UDv2kHLIsqBy+USR LBUAzvO39sWdSraBi5fy351NMUK9jP1GLRKuhqODoKy/AOgzHPPP8aTLrd96dCkAOOw5 25ZhS3iAXVxjJS/NSKit28mp/Zltv9klau9VtxnBaM0Kp4sEL/u5YScQErdaDu+O461l EWatulXcCWZS3TXQ89ZCX6fIHeI9u7a12KVtc6gWa6mwr1S1YvVEt2A8LlJfzApTBzPs 6J3A== Received: by 10.66.84.130 with SMTP id z2mr285052pay.77.1346888715356; Wed, 05 Sep 2012 16:45:15 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ty1sm376267pbc.76.2012.09.05.16.45.13 (version=SSLv3 cipher=OTHER); Wed, 05 Sep 2012 16:45:14 -0700 (PDT) Message-ID: <5047E408.4060009@gmail.com> Date: Wed, 05 Sep 2012 16:45:12 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: Jim Quinlan , ralf@linux-mips.org CC: linux-mips@linux-mips.org, cernekee@gmail.com Subject: Re: [PATCH V4 0/3] MIPS: make funcs preempt-safe for non-mipsr2 cpus References: <1346884367-6906-1-git-send-email-jim2101024@gmail.com> In-Reply-To: <1346884367-6906-1-git-send-email-jim2101024@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34433 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1194 Lines: 33 On 09/05/2012 03:32 PM, Jim Quinlan wrote: > This is V4 of my submission. Here is a list of requested changes: > > o Extra commit was added for changing an unsigned short to an int. > o Use of EXTERN_SYMBOL was added to mips-atomic.c and bitops.c, > as well as the removal of 'extern' in the functions' declarations. > o Name of funcs changed from atomic_xxx to __mips_xxx in bitops.c. > o The function comments in bitops.c were tweaked to please > scripts/kernel-doc. > > Here is a list of requested changes that were not done (and why): > > o Suggested optimization of _MIPS_SZLONG and others was not needed > as mips-atomic.c now includes . > o Suggested fixes to please checkpatch.pl for whitespace before > newlines in asm strings was attempted but the result made the > assembly code look more cluttered => no change made. > > These were unrequested changes: > o Changed order of func listings in irqflags.h so that only one > #ifdef/#endif pair was needed instead of three. > > Jim Quinlan > FWIW: I haven't tested these, but... Acked-by: David Daney Thanks for your patience, David Daney From ralf@linux-mips.org Thu Sep 6 16:08:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 16:08:54 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:52325 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903491Ab2IFOIp (ORCPT ); Thu, 6 Sep 2012 16:08:45 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q86E8i8a003430 for ; Thu, 6 Sep 2012 16:08:44 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q86E8hEi003429 for linux-mips@linux-mips.org; Thu, 6 Sep 2012 16:08:43 +0200 Date: Thu, 6 Sep 2012 16:08:43 +0200 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Warning of gcc bugs affecting kernel builds Message-ID: <20120906140843.GA17068@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34434 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 341 Lines: 10 There are two gcc bugs which are having serious impact on the kernel. http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54369 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54494 Afaics the first one affects SPARC and MIPS in versions 4.5 ... 4.7.1 while the second one affects all architectures but is specific to gcc 4.7.0 and 4.7.1. Ralf From jim2101024@gmail.com Thu Sep 6 17:37:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 17:37:25 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2026 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903444Ab2IFPhO (ORCPT ); Thu, 6 Sep 2012 17:37:14 +0200 Received: from [10.9.200.133] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Thu, 06 Sep 2012 08:34:49 -0700 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Thu, 6 Sep 2012 08:36:23 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 7C57E9F9F6; Thu, 6 Sep 2012 08:36:59 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com, "Jim Quinlan" Subject: [PATCH V5 1/3] MIPS: bitops.h: change use of 'unsigned short' to 'int' Date: Thu, 6 Sep 2012 11:36:54 -0400 Message-ID: <1346945816-13984-2-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1346945816-13984-1-git-send-email-jim2101024@gmail.com> References: <1346945816-13984-1-git-send-email-jim2101024@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C561D1349827917988-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34435 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2602 Lines: 76 Signed-off-by: Jim Quinlan --- arch/mips/include/asm/bitops.h | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 82ad35c..455664c 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -57,7 +57,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long temp; if (kernel_uses_llsc && R10000_LLSC_WAR) { @@ -118,7 +118,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long temp; if (kernel_uses_llsc && R10000_LLSC_WAR) { @@ -191,7 +191,7 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad */ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; if (kernel_uses_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); @@ -244,7 +244,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long res; smp_mb__before_llsc(); @@ -310,7 +310,7 @@ static inline int test_and_set_bit(unsigned long nr, static inline int test_and_set_bit_lock(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long res; if (kernel_uses_llsc && R10000_LLSC_WAR) { @@ -373,7 +373,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long res; smp_mb__before_llsc(); @@ -457,7 +457,7 @@ static inline int test_and_clear_bit(unsigned long nr, static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned short bit = nr & SZLONG_MASK; + int bit = nr & SZLONG_MASK; unsigned long res; smp_mb__before_llsc(); -- 1.7.6 From jim2101024@gmail.com Thu Sep 6 17:37:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 17:37:52 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2115 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903440Ab2IFPhO (ORCPT ); Thu, 6 Sep 2012 17:37:14 +0200 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Thu, 06 Sep 2012 08:35:34 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Thu, 6 Sep 2012 08:36:22 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id D11EE9F9F7; Thu, 6 Sep 2012 08:36:58 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com Subject: [PATCH V5 0/3] Make funcs preempt safe for non-mipsr2 cpus Date: Thu, 6 Sep 2012 11:36:53 -0400 Message-ID: <1346945816-13984-1-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 MIME-Version: 1.0 X-WSS-ID: 7C561D4C3NK24161106-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34436 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 231 Lines: 7 This is the same as V4 except for a one line change in cvmx-l2c.c in PATCH 2/3 for sucessful compilation on cavium-octeon. Other configurations that were tested include: bcm47xx, bcm63xx, bigsur, cobalt, malta, and yosemite. From jim2101024@gmail.com Thu Sep 6 17:37:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 17:38:19 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:3538 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903449Ab2IFPhU (ORCPT ); Thu, 6 Sep 2012 17:37:20 +0200 Received: from [10.9.200.131] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Thu, 06 Sep 2012 08:36:05 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Thu, 6 Sep 2012 08:37:01 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 6AD379F9F8; Thu, 6 Sep 2012 08:37:00 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com, "Jim Quinlan" Subject: [PATCH V5 2/3] MIPS: Remove irqflags.h dependency from bitops.h Date: Thu, 6 Sep 2012 11:36:55 -0400 Message-ID: <1346945816-13984-3-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1346945816-13984-1-git-send-email-jim2101024@gmail.com> References: <1346945816-13984-1-git-send-email-jim2101024@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C561D6F3MK29068685-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34437 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 11206 Lines: 422 The "else clause" of most functions in bitops.h invoked raw_local_irq_{save,restore}() and in doing so had a dependency on irqflags.h. This fix moves said code to bitops.c, removing the dependency. Signed-off-by: Jim Quinlan --- arch/mips/cavium-octeon/executive/cvmx-l2c.c | 1 + arch/mips/include/asm/bitops.h | 114 +++++------------ arch/mips/include/asm/io.h | 1 + arch/mips/lib/Makefile | 2 +- arch/mips/lib/bitops.c | 179 ++++++++++++++++++++++++++ 5 files changed, 214 insertions(+), 83 deletions(-) create mode 100644 arch/mips/lib/bitops.c diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c index d38246e..9f883bf 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c @@ -30,6 +30,7 @@ * measurement, and debugging facilities. */ +#include #include #include #include diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 455664c..46ac73a 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -14,7 +14,6 @@ #endif #include -#include #include #include #include /* sigh ... */ @@ -44,6 +43,24 @@ #define smp_mb__before_clear_bit() smp_mb__before_llsc() #define smp_mb__after_clear_bit() smp_llsc_mb() + +/* + * These are the "slower" versions of the functions and are in bitops.c. + * These functions call raw_local_irq_{save,restore}(). + */ +void __mips_set_bit(unsigned long nr, volatile unsigned long *addr); +void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr); +void __mips_change_bit(unsigned long nr, volatile unsigned long *addr); +int __mips_test_and_set_bit(unsigned long nr, + volatile unsigned long *addr); +int __mips_test_and_set_bit_lock(unsigned long nr, + volatile unsigned long *addr); +int __mips_test_and_clear_bit(unsigned long nr, + volatile unsigned long *addr); +int __mips_test_and_change_bit(unsigned long nr, + volatile unsigned long *addr); + + /* * set_bit - Atomically set a bit in memory * @nr: the bit to set @@ -92,17 +109,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) : "=&r" (temp), "+m" (*m) : "ir" (1UL << bit)); } while (unlikely(!temp)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a |= mask; - raw_local_irq_restore(flags); - } + } else + __mips_set_bit(nr, addr); } /* @@ -153,17 +161,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) : "=&r" (temp), "+m" (*m) : "ir" (~(1UL << bit))); } while (unlikely(!temp)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a &= ~mask; - raw_local_irq_restore(flags); - } + } else + __mips_clear_bit(nr, addr); } /* @@ -220,17 +219,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) : "=&r" (temp), "+m" (*m) : "ir" (1UL << bit)); } while (unlikely(!temp)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a ^= mask; - raw_local_irq_restore(flags); - } + } else + __mips_change_bit(nr, addr); } /* @@ -281,18 +271,8 @@ static inline int test_and_set_bit(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a |= mask; - raw_local_irq_restore(flags); - } + } else + res = __mips_test_and_set_bit(nr, addr); smp_llsc_mb(); @@ -345,18 +325,8 @@ static inline int test_and_set_bit_lock(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a |= mask; - raw_local_irq_restore(flags); - } + } else + res = __mips_test_and_set_bit_lock(nr, addr); smp_llsc_mb(); @@ -428,18 +398,8 @@ static inline int test_and_clear_bit(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a &= ~mask; - raw_local_irq_restore(flags); - } + } else + res = __mips_test_and_clear_bit(nr, addr); smp_llsc_mb(); @@ -494,18 +454,8 @@ static inline int test_and_change_bit(unsigned long nr, } while (unlikely(!res)); res = temp & (1UL << bit); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a ^= mask; - raw_local_irq_restore(flags); - } + } else + res = __mips_test_and_change_bit(nr, addr); smp_llsc_mb(); diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 29d9c23..ff2e034 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index c4a82e8..a7b8937 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o delay.o memcpy.o memset.o \ +lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ strlen_user.o strncpy_user.o strnlen_user.o uncached.o obj-y += iomap.o diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c new file mode 100644 index 0000000..239a9c9 --- /dev/null +++ b/arch/mips/lib/bitops.c @@ -0,0 +1,179 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org) + * Copyright (c) 1999, 2000 Silicon Graphics, Inc. + */ +#include +#include +#include + + +/** + * __mips_set_bit - Atomically set a bit in memory. This is called by + * set_bit() if it cannot find a faster solution. + * @nr: the bit to set + * @addr: the address to start counting from + */ +void __mips_set_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + *a |= mask; + raw_local_irq_restore(flags); +} +EXPORT_SYMBOL(__mips_set_bit); + + +/** + * __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if + * it cannot find a faster solution. + * @nr: Bit to clear + * @addr: Address to start counting from + */ +void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + *a &= ~mask; + raw_local_irq_restore(flags); +} +EXPORT_SYMBOL(__mips_clear_bit); + + +/** + * __mips_change_bit - Toggle a bit in memory. This is called by change_bit() + * if it cannot find a faster solution. + * @nr: Bit to change + * @addr: Address to start counting from + */ +void __mips_change_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + *a ^= mask; + raw_local_irq_restore(flags); +} +EXPORT_SYMBOL(__mips_change_bit); + + +/** + * __mips_test_and_set_bit - Set a bit and return its old value. This is + * called by test_and_set_bit() if it cannot find a faster solution. + * @nr: Bit to set + * @addr: Address to count from + */ +int __mips_test_and_set_bit(unsigned long nr, + volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a |= mask; + raw_local_irq_restore(flags); + return res; +} +EXPORT_SYMBOL(__mips_test_and_set_bit); + + +/** + * __mips_test_and_set_bit_lock - Set a bit and return its old value. This is + * called by test_and_set_bit_lock() if it cannot find a faster solution. + * @nr: Bit to set + * @addr: Address to count from + */ +int __mips_test_and_set_bit_lock(unsigned long nr, + volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a |= mask; + raw_local_irq_restore(flags); + return res; +} +EXPORT_SYMBOL(__mips_test_and_set_bit_lock); + + +/** + * __mips_test_and_clear_bit - Clear a bit and return its old value. This is + * called by test_and_clear_bit() if it cannot find a faster solution. + * @nr: Bit to clear + * @addr: Address to count from + */ +int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a &= ~mask; + raw_local_irq_restore(flags); + return res; +} +EXPORT_SYMBOL(__mips_test_and_clear_bit); + + +/** + * __mips_test_and_change_bit - Change a bit and return its old value. This is + * called by test_and_change_bit() if it cannot find a faster solution. + * @nr: Bit to change + * @addr: Address to count from + */ +int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr; + unsigned bit = nr & SZLONG_MASK; + unsigned long mask; + unsigned long flags; + unsigned long res; + + a += nr >> SZLONG_LOG; + mask = 1UL << bit; + raw_local_irq_save(flags); + res = (mask & *a); + *a ^= mask; + raw_local_irq_restore(flags); + return res; +} +EXPORT_SYMBOL(__mips_test_and_change_bit); -- 1.7.6 From jim2101024@gmail.com Thu Sep 6 17:37:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 17:38:50 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:3539 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903458Ab2IFPh0 (ORCPT ); Thu, 6 Sep 2012 17:37:26 +0200 Received: from [10.9.200.131] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Thu, 06 Sep 2012 08:36:06 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Thu, 6 Sep 2012 08:37:02 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 525E69F9F8; Thu, 6 Sep 2012 08:37:01 -0700 (PDT) From: "Jim Quinlan" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: ddaney.cavm@gmail.com, cernekee@gmail.com, "Jim Quinlan" Subject: [PATCH V5 3/3] MIPS: make funcs preempt-safe for non-mipsr2 cpus Date: Thu, 6 Sep 2012 11:36:56 -0400 Message-ID: <1346945816-13984-4-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1346945816-13984-1-git-send-email-jim2101024@gmail.com> References: <1346945816-13984-1-git-send-email-jim2101024@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C561D6C3MK29068693-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 34438 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jim2101024@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13564 Lines: 512 For non MIPSr2 processors, such as the BMIPS 5000, calls to arch_local_irq_disable() and others may be preempted, and in doing so a stale value may be restored to c0_status. This fix disables preemption for such processors prior to the call and enables it after the call. Those functions that needed this fix have been "outlined" to mips-atomic.c, as they are no longer good candidates for inlining. This bug was observed in a BMIPS 5000, occuring once every few hours in a continuous reboot test. It was traced to the write_lock_irq() function which was being invoked in release_task() in exit.c. By placing a number of "nops" inbetween the mfc0/mtc0 pair in arch_local_irq_disable(), which is called by write_lock_irq(), we were able to greatly increase the occurance of this bug. Similarly, the application of this commit silenced the bug. Signed-off-by: Jim Quinlan --- arch/mips/include/asm/irqflags.h | 207 ++++++++++++++------------------------ arch/mips/lib/Makefile | 3 +- arch/mips/lib/mips-atomic.c | 176 ++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+), 133 deletions(-) create mode 100644 arch/mips/lib/mips-atomic.c diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h index 309cbcd..9f3384c 100644 --- a/arch/mips/include/asm/irqflags.h +++ b/arch/mips/include/asm/irqflags.h @@ -16,83 +16,13 @@ #include #include -__asm__( - " .macro arch_local_irq_enable \n" - " .set push \n" - " .set reorder \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n" - " ori $1, 0x400 \n" - " xori $1, 0x400 \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) - " ei \n" -#else - " mfc0 $1,$12 \n" - " ori $1,0x1f \n" - " xori $1,0x1e \n" - " mtc0 $1,$12 \n" -#endif - " irq_enable_hazard \n" - " .set pop \n" - " .endm"); +#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) -extern void smtc_ipi_replay(void); - -static inline void arch_local_irq_enable(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC kernel needs to do a software replay of queued - * IPIs, at the cost of call overhead on each local_irq_enable() - */ - smtc_ipi_replay(); -#endif - __asm__ __volatile__( - "arch_local_irq_enable" - : /* no outputs */ - : /* no inputs */ - : "memory"); -} - - -/* - * For cli() we have to insert nops to make sure that the new value - * has actually arrived in the status register before the end of this - * macro. - * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs - * no nops at all. - */ -/* - * For TX49, operating only IE bit is not enough. - * - * If mfc0 $12 follows store and the mfc0 is last instruction of a - * page and fetching the next instruction causes TLB miss, the result - * of the mfc0 might wrongly contain EXL bit. - * - * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 - * - * Workaround: mask EXL bit of the result or place a nop before mfc0. - */ __asm__( " .macro arch_local_irq_disable\n" " .set push \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 \n" - " ori $1, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) " di \n" -#else - " mfc0 $1,$12 \n" - " ori $1,0x1f \n" - " xori $1,0x1f \n" - " .set noreorder \n" - " mtc0 $1,$12 \n" -#endif " irq_disable_hazard \n" " .set pop \n" " .endm \n"); @@ -106,46 +36,14 @@ static inline void arch_local_irq_disable(void) : "memory"); } -__asm__( - " .macro arch_local_save_flags flags \n" - " .set push \n" - " .set reorder \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\flags, $2, 1 \n" -#else - " mfc0 \\flags, $12 \n" -#endif - " .set pop \n" - " .endm \n"); - -static inline unsigned long arch_local_save_flags(void) -{ - unsigned long flags; - asm volatile("arch_local_save_flags %0" : "=r" (flags)); - return flags; -} __asm__( " .macro arch_local_irq_save result \n" " .set push \n" " .set reorder \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\result, $2, 1 \n" - " ori $1, \\result, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" - " andi \\result, \\result, 0x400 \n" -#elif defined(CONFIG_CPU_MIPSR2) " di \\result \n" " andi \\result, 1 \n" -#else - " mfc0 \\result, $12 \n" - " ori $1, \\result, 0x1f \n" - " xori $1, 0x1f \n" - " .set noreorder \n" - " mtc0 $1, $12 \n" -#endif " irq_disable_hazard \n" " .set pop \n" " .endm \n"); @@ -160,61 +58,37 @@ static inline unsigned long arch_local_irq_save(void) return flags; } + __asm__( " .macro arch_local_irq_restore flags \n" " .set push \n" " .set noreorder \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - "mfc0 $1, $2, 1 \n" - "andi \\flags, 0x400 \n" - "ori $1, 0x400 \n" - "xori $1, 0x400 \n" - "or \\flags, $1 \n" - "mtc0 \\flags, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) +#if defined(CONFIG_IRQ_CPU) /* * Slow, but doesn't suffer from a relatively unlikely race * condition we're having since days 1. */ " beqz \\flags, 1f \n" - " di \n" + " di \n" " ei \n" "1: \n" -#elif defined(CONFIG_CPU_MIPSR2) +#else /* * Fast, dangerous. Life is fun, life is good. */ " mfc0 $1, $12 \n" " ins $1, \\flags, 0, 1 \n" " mtc0 $1, $12 \n" -#else - " mfc0 $1, $12 \n" - " andi \\flags, 1 \n" - " ori $1, 0x1f \n" - " xori $1, 0x1f \n" - " or \\flags, $1 \n" - " mtc0 \\flags, $12 \n" #endif " irq_disable_hazard \n" " .set pop \n" " .endm \n"); - static inline void arch_local_irq_restore(unsigned long flags) { unsigned long __tmp1; -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC kernel needs to do a software replay of queued - * IPIs, at the cost of branch and call overhead on each - * local_irq_restore() - */ - if (unlikely(!(flags & 0x0400))) - smtc_ipi_replay(); -#endif - __asm__ __volatile__( "arch_local_irq_restore\t%0" : "=r" (__tmp1) @@ -232,6 +106,75 @@ static inline void __arch_local_irq_restore(unsigned long flags) : "0" (flags) : "memory"); } +#else +/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */ +void arch_local_irq_disable(void); +unsigned long arch_local_irq_save(void); +void arch_local_irq_restore(unsigned long flags); +void __arch_local_irq_restore(unsigned long flags); +#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */ + + +__asm__( + " .macro arch_local_irq_enable \n" + " .set push \n" + " .set reorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n" + " ori $1, 0x400 \n" + " xori $1, 0x400 \n" + " mtc0 $1, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) + " ei \n" +#else + " mfc0 $1,$12 \n" + " ori $1,0x1f \n" + " xori $1,0x1e \n" + " mtc0 $1,$12 \n" +#endif + " irq_enable_hazard \n" + " .set pop \n" + " .endm"); + +extern void smtc_ipi_replay(void); + +static inline void arch_local_irq_enable(void) +{ +#ifdef CONFIG_MIPS_MT_SMTC + /* + * SMTC kernel needs to do a software replay of queued + * IPIs, at the cost of call overhead on each local_irq_enable() + */ + smtc_ipi_replay(); +#endif + __asm__ __volatile__( + "arch_local_irq_enable" + : /* no outputs */ + : /* no inputs */ + : "memory"); +} + + +__asm__( + " .macro arch_local_save_flags flags \n" + " .set push \n" + " .set reorder \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 \\flags, $2, 1 \n" +#else + " mfc0 \\flags, $12 \n" +#endif + " .set pop \n" + " .endm \n"); + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("arch_local_save_flags %0" : "=r" (flags)); + return flags; +} + static inline int arch_irqs_disabled_flags(unsigned long flags) { @@ -245,7 +188,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) #endif } -#endif +#endif /* #ifndef __ASSEMBLY__ */ /* * Do the CPU's IRQ-state tracing from assembly code. diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index a7b8937..eeddc58 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -3,7 +3,8 @@ # lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ - strlen_user.o strncpy_user.o strnlen_user.o uncached.o + mips-atomic.o strlen_user.o strncpy_user.o \ + strnlen_user.o uncached.o obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c new file mode 100644 index 0000000..e091430 --- /dev/null +++ b/arch/mips/lib/mips-atomic.c @@ -0,0 +1,176 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#include +#include +#include +#include +#include + +#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) + +/* + * For cli() we have to insert nops to make sure that the new value + * has actually arrived in the status register before the end of this + * macro. + * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs + * no nops at all. + */ +/* + * For TX49, operating only IE bit is not enough. + * + * If mfc0 $12 follows store and the mfc0 is last instruction of a + * page and fetching the next instruction causes TLB miss, the result + * of the mfc0 might wrongly contain EXL bit. + * + * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 + * + * Workaround: mask EXL bit of the result or place a nop before mfc0. + */ +__asm__( + " .macro arch_local_irq_disable\n" + " .set push \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 $1, $2, 1 \n" + " ori $1, 0x400 \n" + " .set noreorder \n" + " mtc0 $1, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) + /* see irqflags.h for inline function */ +#else + " mfc0 $1,$12 \n" + " ori $1,0x1f \n" + " xori $1,0x1f \n" + " .set noreorder \n" + " mtc0 $1,$12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +void arch_local_irq_disable(void) +{ + preempt_disable(); + __asm__ __volatile__( + "arch_local_irq_disable" + : /* no outputs */ + : /* no inputs */ + : "memory"); + preempt_enable(); +} +EXPORT_SYMBOL(arch_local_irq_disable); + + +__asm__( + " .macro arch_local_irq_save result \n" + " .set push \n" + " .set reorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 \\result, $2, 1 \n" + " ori $1, \\result, 0x400 \n" + " .set noreorder \n" + " mtc0 $1, $2, 1 \n" + " andi \\result, \\result, 0x400 \n" +#elif defined(CONFIG_CPU_MIPSR2) + /* see irqflags.h for inline function */ +#else + " mfc0 \\result, $12 \n" + " ori $1, \\result, 0x1f \n" + " xori $1, 0x1f \n" + " .set noreorder \n" + " mtc0 $1, $12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + preempt_disable(); + asm volatile("arch_local_irq_save\t%0" + : "=r" (flags) + : /* no inputs */ + : "memory"); + preempt_enable(); + return flags; +} +EXPORT_SYMBOL(arch_local_irq_save); + + +__asm__( + " .macro arch_local_irq_restore flags \n" + " .set push \n" + " .set noreorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + "mfc0 $1, $2, 1 \n" + "andi \\flags, 0x400 \n" + "ori $1, 0x400 \n" + "xori $1, 0x400 \n" + "or \\flags, $1 \n" + "mtc0 \\flags, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) + /* see irqflags.h for inline function */ +#elif defined(CONFIG_CPU_MIPSR2) + /* see irqflags.h for inline function */ +#else + " mfc0 $1, $12 \n" + " andi \\flags, 1 \n" + " ori $1, 0x1f \n" + " xori $1, 0x1f \n" + " or \\flags, $1 \n" + " mtc0 \\flags, $12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +void arch_local_irq_restore(unsigned long flags) +{ + unsigned long __tmp1; + +#ifdef CONFIG_MIPS_MT_SMTC + /* + * SMTC kernel needs to do a software replay of queued + * IPIs, at the cost of branch and call overhead on each + * local_irq_restore() + */ + if (unlikely(!(flags & 0x0400))) + smtc_ipi_replay(); +#endif + preempt_disable(); + __asm__ __volatile__( + "arch_local_irq_restore\t%0" + : "=r" (__tmp1) + : "0" (flags) + : "memory"); + preempt_enable(); +} +EXPORT_SYMBOL(arch_local_irq_restore); + + +void __arch_local_irq_restore(unsigned long flags) +{ + unsigned long __tmp1; + + preempt_disable(); + __asm__ __volatile__( + "arch_local_irq_restore\t%0" + : "=r" (__tmp1) + : "0" (flags) + : "memory"); + preempt_enable(); +} +EXPORT_SYMBOL(__arch_local_irq_restore); + +#endif /* !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) */ -- 1.7.6 From mturquette@ti.com Thu Sep 6 19:13:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Sep 2012 19:13:15 +0200 (CEST) Received: from na3sys009aog103.obsmtp.com ([74.125.149.71]:50171 "EHLO na3sys009aog103.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903465Ab2IFRNK (ORCPT ); Thu, 6 Sep 2012 19:13:10 +0200 Received: from mail-ie0-f177.google.com ([209.85.223.177]) (using TLSv1) by na3sys009aob103.postini.com ([74.125.148.12]) with SMTP ID DSNKUEjZpAWQbsLU9J3fv3n28hA5U6YwOcwd@postini.com; Thu, 06 Sep 2012 10:13:09 PDT Received: by ieje10 with SMTP id e10so3590755iej.36 for ; Thu, 06 Sep 2012 10:13:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=5ClK+hX6l1HeNUgLO+VPyPp9s7jRkbXGdBmmBY3h6Ls=; b=hpAY6jgMKeVPVeETHwCuqiVL7j2ENpbclvtr5NRhJS7IMinfjuvuegH00HCLO87QRa 0vwUWQmpJ1KmrHvpTptA5l9jPqNAERlZD9e+tCcBvx4dFVCFspVcsbSkH8lH6eKld4z8 ijoLGcpm8hvEvN8wTerPl4jBbSb2jGXVlTDgdJDx4SfefS9v6xePxw0QPnUPGMTcqciw h2ZytGCG9DVSEme0MgidS2LzMaEjctwMkRj996OSS03VZWFTJ5YFPez8Nz8FfLCmrMeK 8RTJK6AW+Mqo0RF4h6LNLYRi2a1WfjcCASCKkYrOPEcYG4rN4E/YM4pgd775ESwGesfx IJ4w== Received: by 10.42.39.197 with SMTP id i5mr3292039ice.27.1346951587596; Thu, 06 Sep 2012 10:13:07 -0700 (PDT) MIME-Version: 1.0 Received: by 10.50.220.163 with HTTP; Thu, 6 Sep 2012 10:12:47 -0700 (PDT) In-Reply-To: References: <1345287301-18165-1-git-send-email-keguang.zhang@gmail.com> From: "Turquette, Mike" Date: Thu, 6 Sep 2012 10:12:47 -0700 Message-ID: Subject: Re: [PATCH] clk: add Loongson1B clock support To: Kelvin Cheung Cc: Belisko Marek , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Russell King Content-Type: text/plain; charset=ISO-8859-1 X-Gm-Message-State: ALoCoQmau7qU8/bzdgxPN0dlVN9BDxpbigeEI+x0qKU7sTFJkZw7/PTpbEeu+3TYX6soeEPMYxA+ X-archive-position: 34439 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mturquette@ti.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6356 Lines: 200 On Sat, Aug 18, 2012 at 4:54 AM, Kelvin Cheung wrote: > > 2012/8/18 Belisko Marek >> >> On Sat, Aug 18, 2012 at 12:55 PM, Kelvin Cheung wrote: >> > This adds clock support to Loongson1B SoC using the common clock >> > infrastructure. >> > >> > Signed-off-by: Kelvin Cheung >> > --- >> > drivers/clk/Makefile | 1 + >> > drivers/clk/clk-ls1x.c | 108 ++++++++++++++++++++++++++++++++++++++++++++++++ >> > 2 files changed, 109 insertions(+), 0 deletions(-) >> > create mode 100644 drivers/clk/clk-ls1x.c >> > >> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile >> > index 5869ea3..018ec57 100644 >> > --- a/drivers/clk/Makefile >> > +++ b/drivers/clk/Makefile >> > @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ >> > obj-$(CONFIG_PLAT_SPEAR) += spear/ >> > obj-$(CONFIG_ARCH_U300) += clk-u300.o >> > obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/ >> > +obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o >> > >> > # Chip specific >> > obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o >> > diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c >> > new file mode 100644 >> > index 0000000..0aadf9d >> > --- /dev/null >> > +++ b/drivers/clk/clk-ls1x.c >> > @@ -0,0 +1,108 @@ >> > +/* >> > + * Copyright (c) 2012 Zhang, Keguang >> > + * >> > + * This program is free software; you can redistribute it and/or modify it >> > + * under the terms of the GNU General Public License as published by the >> > + * Free Software Foundation; either version 2 of the License, or (at your >> > + * option) any later version. >> > + */ >> > + >> > +#include >> > +#include >> > +#include >> > +#include >> > +#include >> > +#include >> > + >> > +#include >> > + >> > +#define OSC 33 >> > + >> > +static DEFINE_SPINLOCK(_lock); >> > + >> > +int ls1x_pll_clk_enable(struct clk_hw *hw) >> ^^^^static > > > OK, will do. > Thanks! > Hi Kelvin, I've already taken the above patch for loongson1b common clk support into clk-next. Can you submit a fixup patch and I'll just apply the fix to the tip of the branch. I'm trying to avoid rebases this late in the cycle. Thanks, Mike >> >> > +{ >> > + return 0; >> > +} >> > + >> > +void ls1x_pll_clk_disable(struct clk_hw *hw) >> ^^^^ also static >> > +{ >> > +} >> > + >> > +static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, >> > + unsigned long parent_rate) >> > +{ >> > + u32 pll, rate; >> > + >> > + pll = __raw_readl(LS1X_CLK_PLL_FREQ); >> > + rate = ((12 + (pll & 0x3f)) * 1000000) + >> > + ((((pll >> 8) & 0x3ff) * 1000000) >> 10); >> > + rate *= OSC; >> > + rate >>= 1; >> > + >> > + return rate; >> > +} >> > + >> > +static const struct clk_ops ls1x_pll_clk_ops = { >> > + .enable = ls1x_pll_clk_enable, >> > + .disable = ls1x_pll_clk_disable, >> > + .recalc_rate = ls1x_pll_recalc_rate, >> > +}; >> > + >> > +static struct clk * __init clk_register_pll(struct device *dev, >> > + const char *name, const char *parent_name, unsigned long flags) >> > +{ >> > + struct clk_hw *hw; >> > + struct clk *clk; >> > + struct clk_init_data init; >> > + >> > + /* allocate the divider */ >> > + hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL); >> > + if (!hw) { >> > + pr_err("%s: could not allocate clk_hw\n", __func__); >> > + return ERR_PTR(-ENOMEM); >> > + } >> > + >> > + init.name = name; >> > + init.ops = &ls1x_pll_clk_ops; >> > + init.flags = flags | CLK_IS_BASIC; >> > + init.parent_names = (parent_name ? &parent_name : NULL); >> > + init.num_parents = (parent_name ? 1 : 0); >> > + hw->init = &init; >> > + >> > + /* register the clock */ >> > + clk = clk_register(dev, hw); >> > + >> > + if (IS_ERR(clk)) >> > + kfree(hw); >> > + >> > + return clk; >> > +} >> > + >> > +void __init ls1x_clk_init(void) >> > +{ >> > + struct clk *clk; >> > + >> > + clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT); >> > + clk_prepare_enable(clk); >> > + >> > + clk = clk_register_divider(NULL, "cpu_clk", "pll_clk", >> > + CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT, >> > + DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); >> > + clk_prepare_enable(clk); >> > + clk_register_clkdev(clk, "cpu", NULL); >> > + >> > + clk = clk_register_divider(NULL, "ddr_clk", "pll_clk", >> > + CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT, >> > + DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); >> > + clk_prepare_enable(clk); >> > + clk_register_clkdev(clk, "ddr", NULL); >> > + clk_register_clkdev(clk, "stmmaceth", NULL); >> > + >> > + clk = clk_register_divider(NULL, "dc_clk", "pll_clk", >> > + CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT, >> > + DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); >> > + clk_prepare_enable(clk); >> > + clk_register_clkdev(clk, "dc", NULL); >> > + clk_register_clkdev(clk, "serial8250", NULL); >> > +} >> > -- >> > 1.7.1 >> > >> > -- >> > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in >> > the body of a message to majordomo@vger.kernel.org >> > More majordomo info at http://vger.kernel.org/majordomo-info.html >> > Please read the FAQ at http://www.tux.org/lkml/ >> >> cheers, >> >> marek >> >> -- >> as simple and primitive as possible >> ------------------------------------------------- >> Marek Belisko - OPEN-NANDRA >> Freelance Developer >> >> Ruska Nova Ves 219 | Presov, 08005 Slovak Republic >> Tel: +421 915 052 184 >> skype: marekwhite >> twitter: #opennandra >> web: http://open-nandra.com > > > > > -- > Best Regards! > Kelvin > > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > From ckhardin@exablox.com Fri Sep 7 00:35:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Sep 2012 00:35:13 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:45222 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903465Ab2IFWfH (ORCPT ); Fri, 7 Sep 2012 00:35:07 +0200 Received: by pbbrq8 with SMTP id rq8so3220935pbb.36 for ; Thu, 06 Sep 2012 15:35:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=oN1kcIxsdNp4Fri7MdRop0Fv9zzILV8i4SUGcrSoOYk=; b=PBVP4FpkEzk0ysZHjYO9wYFr/jR8V7xX+vtKaQl/TN05SbZAk6zBR1OXBVU+zavmdy Nk7I3yWxfH10gw5Jf1CDtE8023krt3una+d7fbawD+G6eDM9NnvosyqaSBQ+uk9oQ1PB ZFkPvBElpTAJIr+Zt++4ZGmXD4eXsBxrBTqQmM1D61oyG8EW3VXM803KDALWufUl8/8X 8frIMNe14ACYtzs2Yf2peyc0tfY/hsAwC1PnlM26W1puyi5juzYEIeJNZlmw7NpZC44R jNwDcb64mZIto9i/WF2cPsAoi/OozeDLBJmuqvFZzr+5blbpEY96wtAsemNL0KgxpeLO jEjw== Received: by 10.68.201.104 with SMTP id jz8mr6737845pbc.141.1346970900423; Thu, 06 Sep 2012 15:35:00 -0700 (PDT) Received: from localhost.localdomain (50-76-62-73-ip-static.hfc.comcastbusiness.net. [50.76.62.73]) by mx.google.com with ESMTPS id hc10sm2051739pbc.21.2012.09.06.15.34.59 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Sep 2012 15:34:59 -0700 (PDT) From: Charles Hardin To: linux-mips@linux-mips.org Cc: Ralf Baechle , David Daney , Jeremy Fitzhardinge , Charles Hardin Subject: [PATCH] mips/octeon: 16-Bit NOR flash was not being detected during boot Date: Wed, 5 Sep 2012 06:54:53 -0700 Message-Id: <1346853293-9166-1-git-send-email-ckhardin@exablox.com> X-Mailer: git-send-email 1.7.9.1 X-Gm-Message-State: ALoCoQmmtUIDztQGz5+0xzk2EoxNesJ8AtHon2ZBIgEe43Y8Brmiifj7nZFST0jxNDHeCkkNOdlk X-archive-position: 34440 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ckhardin@exablox.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1184 Lines: 32 The cavium code assumed that all NOR on the boot bus was an 8-bit NOR part and hardcoded the bankwidth. The simple solution was to add the code that queries the configuration register for the width of the bus that has been hardware strapped to the Cavium. This allows both 8-bit and 16-bit parts to be discovered during boot. Signed-off-by: Charles Hardin diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c index e44a55b..9e46976 100644 --- a/arch/mips/cavium-octeon/flash_setup.c +++ b/arch/mips/cavium-octeon/flash_setup.c @@ -51,7 +51,17 @@ static int __init flash_init(void) flash_map.name = "phys_mapped_flash"; flash_map.phys = region_cfg.s.base << 16; flash_map.size = 0x1fc00000 - flash_map.phys; - flash_map.bankwidth = 1; + switch (region_cfg.s.width) { + default: + case 0: + /* 8-bit bus */ + flash_map.bankwidth = 1; + break; + case 1: + /* 16-bit bus */ + flash_map.bankwidth = 2; + break; + } flash_map.virt = ioremap(flash_map.phys, flash_map.size); pr_notice("Bootbus flash: Setting flash for %luMB flash at " "0x%08llx\n", flash_map.size >> 20, flash_map.phys); From ddaney.cavm@gmail.com Fri Sep 7 19:57:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Sep 2012 19:57:55 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:51497 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903249Ab2IGR5p (ORCPT ); Fri, 7 Sep 2012 19:57:45 +0200 Received: by pbbrq8 with SMTP id rq8so4472358pbb.36 for ; Fri, 07 Sep 2012 10:57:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=m+oCvsuokBD9Qfz63z0Itd5eKEjREZTff9BEbKI/V4c=; b=cbwj9CcChdteR2iqLDLjqVu8jRVp+LF78ON/SRdM61w6/2CkR1U9RzSsJrOGyvGvVf L/nME21bPBj1E8WborSr6jCbnjPCxrU/5DkCvrhXc8G120CJHF9aTj9wgpqir8icK0o7 0R3FoJNZ+3O01ex8XqdnknppXtmHrKiOoS3pAUyz2UgDT1BSUo5VbfMu5dVvohzA4m00 MozVsy7DYsedT9h2I8A1xCarR2osGDH281GQR+r50YAyYfOebkTSFeZvH46uzHyYV1uG DSK2m+GH3mPJcvGTzB0qLJa6yG8nUHcoZ+R9rGlaEO8j5kX8YQloEiSUyilCvdbThZbs Pesg== Received: by 10.68.226.195 with SMTP id ru3mr10534306pbc.149.1347040658711; Fri, 07 Sep 2012 10:57:38 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id or1sm3505021pbb.10.2012.09.07.10.57.36 (version=SSLv3 cipher=OTHER); Fri, 07 Sep 2012 10:57:37 -0700 (PDT) Message-ID: <504A358F.50904@gmail.com> Date: Fri, 07 Sep 2012 10:57:35 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: Charles Hardin CC: linux-mips@linux-mips.org, Ralf Baechle , David Daney , Jeremy Fitzhardinge Subject: Re: [PATCH] mips/octeon: 16-Bit NOR flash was not being detected during boot References: <1346853293-9166-1-git-send-email-ckhardin@exablox.com> In-Reply-To: <1346853293-9166-1-git-send-email-ckhardin@exablox.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34441 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1313 Lines: 42 On 09/05/2012 06:54 AM, Charles Hardin wrote: > The cavium code assumed that all NOR on the boot bus was > an 8-bit NOR part and hardcoded the bankwidth. The simple > solution was to add the code that queries the configuration > register for the width of the bus that has been hardware strapped > to the Cavium. This allows both 8-bit and 16-bit parts to be > discovered during boot. > > Signed-off-by: Charles Hardin > > diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c > index e44a55b..9e46976 100644 > --- a/arch/mips/cavium-octeon/flash_setup.c > +++ b/arch/mips/cavium-octeon/flash_setup.c > @@ -51,7 +51,17 @@ static int __init flash_init(void) > flash_map.name = "phys_mapped_flash"; > flash_map.phys = region_cfg.s.base << 16; > flash_map.size = 0x1fc00000 - flash_map.phys; > - flash_map.bankwidth = 1; > + switch (region_cfg.s.width) { > + default: > + case 0: > + /* 8-bit bus */ > + flash_map.bankwidth = 1; > + break; > + case 1: > + /* 16-bit bus */ > + flash_map.bankwidth = 2; > + break; > + } A slightly less verbose version of this would be: - flash_map.bankwidth = 1; + flash_map.bankwidth = region_cfg.s.width + 1; Can you test that instead? If it works, Acked-by me. David Daney From ckhardin@exablox.com Fri Sep 7 23:21:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Sep 2012 23:22:01 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:36464 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903438Ab2IGVVy (ORCPT ); Fri, 7 Sep 2012 23:21:54 +0200 Received: by pbbrq8 with SMTP id rq8so196063pbb.36 for ; Fri, 07 Sep 2012 14:21:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=9gyWPalzI7zkVcaOtmp0vfvBzTT5542/KgbuYdIeQHc=; b=N2qhoJ+OLN9TCLcr04/VQY9wHu4mntSUWU464hxyYjVBsbNXXWuRwIzgo3zMKr356y fYc6bewiQT2KFDuaK2xyj7HqXKxvlHNvwZY+wiMalN4cNLG1kF2KjxVqevLhC94xLLGf J7Oq7sGk1kLrs8o+dE5yBWz10tcyx1AbMXUOoOFXKaiEsfsExECURVqwR6U6SCZR49Z9 rtODA9D6DbqA3nZYisTFOtWz/l5YdyL9BC95CYNfqbq0lRq7VL4QLL+Se9gh8+ZD8EeI 2Fhk5usFN1wBjy0S9dcJYy7YRc0ZMe7sdrHRntBACDexD40NQjbEC3GLnWQjevDfKcrf 2x0Q== Received: by 10.68.211.105 with SMTP id nb9mr11680388pbc.67.1347052907335; Fri, 07 Sep 2012 14:21:47 -0700 (PDT) Received: from localhost.localdomain (50-76-62-73-ip-static.hfc.comcastbusiness.net. [50.76.62.73]) by mx.google.com with ESMTPS id to6sm3793135pbc.12.2012.09.07.14.21.45 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 07 Sep 2012 14:21:46 -0700 (PDT) From: Charles Hardin To: linux-mips@linux-mips.org Cc: Ralf Baechle , David Daney , Jeremy Fitzhardinge , Charles Hardin Subject: [PATCH] mips/octeon: 16-Bit NOR flash was not being detected during boot Date: Wed, 5 Sep 2012 13:19:48 -0700 Message-Id: <1346876388-25839-1-git-send-email-ckhardin@exablox.com> X-Mailer: git-send-email 1.7.9.1 X-Gm-Message-State: ALoCoQmn0BwqYR7S51FD7gq8a3+JJrAHJ6QcTS1f6SI2b5+PmIAJhDrMc5G2vz2iP7zxU8a+4FyB X-archive-position: 34442 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ckhardin@exablox.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1135 Lines: 24 The cavium code assumed that all NOR on the boot bus was an 8-bit NOR part and hardcoded the bankwidth. The simple solution was to add the code that queries the configuration register for the width of the bus that has been hardware strapped to the Cavium. This allows both 8-bit and 16-bit parts to be discovered during boot. Acked-by: David Daney Signed-off-by: Charles Hardin diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c index e44a55b..237e5b1 100644 --- a/arch/mips/cavium-octeon/flash_setup.c +++ b/arch/mips/cavium-octeon/flash_setup.c @@ -51,7 +51,8 @@ static int __init flash_init(void) flash_map.name = "phys_mapped_flash"; flash_map.phys = region_cfg.s.base << 16; flash_map.size = 0x1fc00000 - flash_map.phys; - flash_map.bankwidth = 1; + /* 8-bit bus (0 + 1) or 16-bit bus (1 + 1) */ + flash_map.bankwidth = region_cfg.s.width + 1; flash_map.virt = ioremap(flash_map.phys, flash_map.size); pr_notice("Bootbus flash: Setting flash for %luMB flash at " "0x%08llx\n", flash_map.size >> 20, flash_map.phys); From juhosg@openwrt.org Sat Sep 8 14:02:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Sep 2012 14:02:49 +0200 (CEST) Received: from arrakis.dune.hu ([78.24.191.176]:57346 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903258Ab2IHMCl (ORCPT ); Sat, 8 Sep 2012 14:02:41 +0200 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 1070A23C0088; Sat, 8 Sep 2012 14:02:37 +0200 (CEST) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos , Subject: [PATCH] MIPS: ath79: fix CPU/DDR frequency calculation for SRIF PLLs Date: Sat, 8 Sep 2012 14:02:21 +0200 Message-Id: <1347105741-23091-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 34443 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 6959 Lines: 207 Besides the CPU and DDR PLLs, the CPU and DDR frequencies can be derived from other PLLs in the SRIF block on the AR934x SoCs. The current code does not checks if the SRIF PLLs are used and this can lead to incorrectly calculated CPU/DDR frequencies. Fix it by calculating the frequencies from SRIF PLLs if those are used on a given board. Cc: Signed-off-by: Gabor Juhos --- This depends on the following patch: 'MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x' https://patchwork.linux-mips.org/patch/4305/ arch/mips/ath79/clock.c | 109 ++++++++++++++++++------ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 23 +++++ 2 files changed, 104 insertions(+), 28 deletions(-) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index d272857..579f452 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -17,6 +17,8 @@ #include #include +#include + #include #include #include "common.h" @@ -166,11 +168,34 @@ static void __init ar933x_clocks_init(void) ath79_uart_clk.rate = ath79_ref_clk.rate; } +static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, + u32 frac, u32 out_div) +{ + u64 t; + u32 ret; + + t = ath79_ref_clk.rate; + t *= nint; + do_div(t, ref_div); + ret = t; + + t = ath79_ref_clk.rate; + t *= nfrac; + do_div(t, ref_div * frac); + ret += t; + + ret /= (1 << out_div); + return ret; +} + static void __init ar934x_clocks_init(void) { - u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; + u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; u32 cpu_pll, ddr_pll; u32 bootstrap; + void __iomem *dpll_base; + + dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE); bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) @@ -178,33 +203,59 @@ static void __init ar934x_clocks_init(void) else ath79_ref_clk.rate = 25 * 1000 * 1000; - pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); - out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & - AR934X_PLL_CPU_CONFIG_REFDIV_MASK; - nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & - AR934X_PLL_CPU_CONFIG_NINT_MASK; - frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & - AR934X_PLL_CPU_CONFIG_NFRAC_MASK; - - cpu_pll = nint * ath79_ref_clk.rate / ref_div; - cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); - cpu_pll /= (1 << out_div); - - pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); - out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & - AR934X_PLL_DDR_CONFIG_REFDIV_MASK; - nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & - AR934X_PLL_DDR_CONFIG_NINT_MASK; - frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & - AR934X_PLL_DDR_CONFIG_NFRAC_MASK; - - ddr_pll = nint * ath79_ref_clk.rate / ref_div; - ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); - ddr_pll /= (1 << out_div); + pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); + if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { + out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & + AR934X_SRIF_DPLL2_OUTDIV_MASK; + pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); + nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & + AR934X_SRIF_DPLL1_NINT_MASK; + nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; + ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & + AR934X_SRIF_DPLL1_REFDIV_MASK; + frac = 1 << 18; + } else { + pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); + out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; + ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_REFDIV_MASK; + nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & + AR934X_PLL_CPU_CONFIG_NINT_MASK; + nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_CPU_CONFIG_NFRAC_MASK; + frac = 1 << 6; + } + + cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, + nfrac, frac, out_div); + + pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); + if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { + out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & + AR934X_SRIF_DPLL2_OUTDIV_MASK; + pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); + nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & + AR934X_SRIF_DPLL1_NINT_MASK; + nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; + ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & + AR934X_SRIF_DPLL1_REFDIV_MASK; + frac = 1 << 18; + } else { + pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); + out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; + ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_REFDIV_MASK; + nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & + AR934X_PLL_DDR_CONFIG_NINT_MASK; + nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_DDR_CONFIG_NFRAC_MASK; + frac = 1 << 10; + } + + ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, + nfrac, frac, out_div); clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); @@ -240,6 +291,8 @@ static void __init ar934x_clocks_init(void) ath79_wdt_clk.rate = ath79_ref_clk.rate; ath79_uart_clk.rate = ath79_ref_clk.rate; + + iounmap(dpll_base); } void __init ath79_clocks_init(void) diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 3ccae12..a5e0f17 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -65,6 +65,8 @@ #define AR934X_WMAC_SIZE 0x20000 #define AR934X_EHCI_BASE 0x1b000000 #define AR934X_EHCI_SIZE 0x200 +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 /* * DDR_CTRL block @@ -406,4 +408,25 @@ #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_COUNT 23 +/* + * SRIF block + */ +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 + +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + #endif /* __ASM_MACH_AR71XX_REGS_H */ -- 1.7.10 From macro@linux-mips.org Sat Sep 8 21:28:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Sep 2012 21:28:31 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:45557 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903261Ab2IHT21 (ORCPT ); Sat, 8 Sep 2012 21:28:27 +0200 Date: Sat, 8 Sep 2012 20:28:26 +0100 (BST) From: "Maciej W. Rozycki" To: linux-mips@linux-mips.org Subject: Re: MIPS: Fix build error with modern GCC for non-Cavium. In-Reply-To: Message-ID: References: User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 34444 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 351 Lines: 10 On Tue, 4 Sep 2012, linux-mips@linux-mips.org wrote: > An empty default block is not allowed so add a ; as empty statement to > make gcc happy. A dummy "break" is the usual solution though. I don't think GCC ever complains if it sees it unreachable after a "return" -- in a sense it is just as unreachable as this null instruction is. Maciej From hauke@hauke-m.de Sun Sep 9 17:22:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 09 Sep 2012 17:22:18 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:33170 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903205Ab2IIPWN (ORCPT ); Sun, 9 Sep 2012 17:22:13 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 192088880; Sun, 9 Sep 2012 17:22:11 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aB-ZH3eDWthP; Sun, 9 Sep 2012 17:22:07 +0200 (CEST) Received: from [192.168.178.21] (dyndsl-085-016-153-152.ewe-ip-backbone.de [85.16.153.152]) by hauke-m.de (Postfix) with ESMTPSA id 87FFF87B9; Sun, 9 Sep 2012 17:22:07 +0200 (CEST) Message-ID: <504CB41E.6070201@hauke-m.de> Date: Sun, 09 Sep 2012 17:22:06 +0200 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120827 Thunderbird/15.0 MIME-Version: 1.0 To: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= CC: ralf@linux-mips.org, john@phrozen.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, florian@openwrt.org Subject: Re: [PATCH v3 2/3] bcma: add GPIO driver for SoCs References: <1346427485-12801-1-git-send-email-hauke@hauke-m.de> <1346427485-12801-3-git-send-email-hauke@hauke-m.de> In-Reply-To: X-Enigmail-Version: 1.4.4 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 34445 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1020 Lines: 29 On 09/03/2012 09:15 PM, RafaÅ‚ MiÅ‚ecki wrote: > 2012/8/31 Hauke Mehrtens : >> +u32 bcma_gpio_in(struct bcma_bus *bus, u32 mask) >> +{ >> + unsigned long flags; >> + u32 res = 0; >> + >> + spin_lock_irqsave(&bus->gpio_lock, flags); >> + res = bcma_chipco_gpio_in(&bus->drv_cc, mask); >> + spin_unlock_irqrestore(&bus->gpio_lock, flags); >> + >> + return res; >> +} >> +EXPORT_SYMBOL(bcma_gpio_in); > > > Could we put here direct ops on ChipCommon regs and drop GPIO > functions from driver_chipcommon.c? So you mean that all accesses to the gpio registers are locked, also when b43 or bcma accesses them? If so, I will change my patch and test it on my devices. I am currently not at my development machine and do not have the test devices here, but I will see if I find some time on Tuesday when I am home again. So bcma_chipco_gpio_XXX() should not be exported in the way it is done now any more and all accesses to the gpio registers should be locked. Hauke From dalias@aerifal.cx Sun Sep 9 21:27:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 09 Sep 2012 21:27:25 +0200 (CEST) Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:52733 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903266Ab2IIT1V (ORCPT ); Sun, 9 Sep 2012 21:27:21 +0200 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1TAnCq-0003wj-00 for linux-mips@linux-mips.org; Sun, 09 Sep 2012 19:30:08 +0000 Date: Sun, 9 Sep 2012 15:30:08 -0400 To: linux-mips@linux-mips.org Subject: Is r25 saved across syscalls? Message-ID: <20120909193008.GA15157@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) From: Rich Felker X-archive-position: 34446 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dalias@aerifal.cx Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 439 Lines: 10 Hi all, The kernel syscall entry/exit code seems to always save and restore r25. Is this stable/documented behavior I can rely on? If there's a reason it _needs_ to be preserved, knowing that would help convince me it's safe to assume it will always be done. The intended usage is to be able to make syscalls (where the syscall # is not a constant that could be loaded with lwi) without a stack frame, as in "move $2,$25 ; syscall". Rich From thierry.reding@avionic-design.de Mon Sep 10 14:05:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 14:05:44 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.8]:63314 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903446Ab2IJMFg (ORCPT ); Mon, 10 Sep 2012 14:05:36 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0MDCvo-1TKxqh2Qiy-00Gq18; Mon, 10 Sep 2012 14:05:23 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id E262B2A282E2; Mon, 10 Sep 2012 14:05:22 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ziUt81VE2jDh; Mon, 10 Sep 2012 14:05:21 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id B0A5D2A28267; Mon, 10 Sep 2012 14:05:21 +0200 (CEST) From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: [PATCH v2 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Date: Mon, 10 Sep 2012 14:05:16 +0200 Message-Id: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 X-Provags-ID: V02:K0:n+yP6mng7YgOvO61oGfh2jjrxo260QIM+tPDlygG/98 J67g1c5PE5Msj1DDC976bof1oI7FQ2UXb4WFDo1FUkukY0KI1Q In0cvla3RbhQVcy7yTXpeRbiOn6+ou5DK7QuncEpdn6+OxLhy9 CMBhu3l4AJQCI7sVHBmXmqXstKsDtEXCtDQzmMKg8OgNvqds/S w8jM8bk0ai26JWcsT9Kjhr4z/vpeBaL1WpLUtdxbxDcmaQNCPa AJ5be4EPcUbuW1X5zDW2fa2XLHAaVOW57mRbxeTFKFyLm50/md AZcwiusW6IYlUawCUCYM3EX/+3sX1R8P+szHBSFK6UnBhneFXW flchSr83+qGQjA0dEkNt9xFAnEy1rSKzaf4EABE405n0xM0Gd5 Ox53IgzlbKYyeW347QPgrV0sLNkXJQiZII9l18RgZ5iwI5wmTU AE81H X-archive-position: 34447 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1804 Lines: 44 Hi, This small series fixes a build error due to a circular header dependency, exports the timer API so it can be used outside of the arch/mips/jz4740 tree and finally moves and converts the JZ4740 PWM driver to the PWM framework. Note that I don't have any hardware to test this on, so I had to rely on compile tests only. Patches 1 and 2 should probably go through the MIPS tree, while I can take patch 3 through the PWM tree. It touches a couple of files in arch/mips but the changes are unlikely to cause conflicts. Thierry Thierry Reding (3): MIPS: JZ4740: Break circular header dependency MIPS: JZ4740: Export timer API pwm: Add Ingenic JZ4740 support arch/mips/include/asm/mach-jz4740/irq.h | 5 + arch/mips/include/asm/mach-jz4740/platform.h | 1 + arch/mips/include/asm/mach-jz4740/timer.h | 113 ++++++++++++++ arch/mips/jz4740/Kconfig | 3 - arch/mips/jz4740/Makefile | 2 +- arch/mips/jz4740/board-qi_lb60.c | 1 + arch/mips/jz4740/irq.h | 23 --- arch/mips/jz4740/platform.c | 6 + arch/mips/jz4740/pwm.c | 177 --------------------- arch/mips/jz4740/time.c | 2 +- arch/mips/jz4740/timer.c | 4 +- arch/mips/jz4740/timer.h | 136 ----------------- drivers/pwm/Kconfig | 12 +- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-jz4740.c | 221 +++++++++++++++++++++++++++ 15 files changed, 363 insertions(+), 344 deletions(-) delete mode 100644 arch/mips/jz4740/irq.h delete mode 100644 arch/mips/jz4740/pwm.c delete mode 100644 arch/mips/jz4740/timer.h create mode 100644 drivers/pwm/pwm-jz4740.c -- 1.7.12 From thierry.reding@avionic-design.de Mon Sep 10 14:05:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 14:06:09 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.171]:56762 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903463Ab2IJMFh (ORCPT ); Mon, 10 Sep 2012 14:05:37 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap3) with ESMTP (Nemesis) id 0M7Jry-1TWGI62NMs-00x4G0; Mon, 10 Sep 2012 14:05:25 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id E27752A282E6; Mon, 10 Sep 2012 14:05:23 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Qvw6QJoCXljX; Mon, 10 Sep 2012 14:05:22 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id A32242A282DF; Mon, 10 Sep 2012 14:05:22 +0200 (CEST) From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: [PATCH v2 1/3] MIPS: JZ4740: Break circular header dependency Date: Mon, 10 Sep 2012 14:05:17 +0200 Message-Id: <1347278719-15276-2-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:P1KBcgsyvYL/mcNyro9+r0jLVESETgYND9K42T3JfZi rG+CQtCz7KRGoqQBjlIDfQLgm23QPqrphcRIdRaYdzKF81xd5r KUTJ6SRtsHvWzG8SJ1nlZtRgMR+gbwXZ/U9F+9GLiUh7cQa2XA 1d1lUNhGk6uxuIw3qFU/wnNwTtaOEbHYlCUwGHty2lfNmhaceh CwOLEU1KunxjKJ3mKE0sSBgmnRvLzWlbV1zdpmeHdAE6TWBWqB m7RSYON7Qlhr/XNLcEiZBuOv0Z4NDHJY8V7QjqI3M44vRHWEsG pKWpjAHddgQrVnmROz0E/AXLoQnDR59bl4i5DdBgE3kM56EXkl cBBBGSVym7fVXVPFoCtMRzbjapHoq/LMHBSF242p5WdGu25mED nleqXJ/B2BpK8s2rSyS+RDqZHhDWqYR+zwhZo/P/511Os1hX8f m9ws0 X-archive-position: 34448 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2009 Lines: 60 When including irq.h, arch/mips/jz4740/irq.h will be selected as the first candidate. This header does not include the proper definitions (most notably NR_IRQS) required by subsequent headers. To solve this arch/mips/jz4740/irq.h can be deleted and its contents can be moved into arch/mips/include/asm/mach-jz4740/irq.h, which will then be correctly included. Signed-off-by: Thierry Reding --- arch/mips/include/asm/mach-jz4740/irq.h | 5 +++++ arch/mips/jz4740/irq.h | 23 ----------------------- 2 files changed, 5 insertions(+), 23 deletions(-) delete mode 100644 arch/mips/jz4740/irq.h diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h index 5ad1a9c..aa6fd90 100644 --- a/arch/mips/include/asm/mach-jz4740/irq.h +++ b/arch/mips/include/asm/mach-jz4740/irq.h @@ -54,4 +54,9 @@ #define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6) +struct irq_data; + +extern void jz4740_irq_suspend(struct irq_data *data); +extern void jz4740_irq_resume(struct irq_data *data); + #endif diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h deleted file mode 100644 index f75e39d..0000000 --- a/arch/mips/jz4740/irq.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __MIPS_JZ4740_IRQ_H__ -#define __MIPS_JZ4740_IRQ_H__ - -#include - -extern void jz4740_irq_suspend(struct irq_data *data); -extern void jz4740_irq_resume(struct irq_data *data); - -#endif -- 1.7.12 From thierry.reding@avionic-design.de Mon Sep 10 14:05:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 14:06:34 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.171]:57433 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903465Ab2IJMFh (ORCPT ); Mon, 10 Sep 2012 14:05:37 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu4) with ESMTP (Nemesis) id 0MHehs-1T7kQE0Z24-003JxE; Mon, 10 Sep 2012 14:05:26 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 8141B2A282E2; Mon, 10 Sep 2012 14:05:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id X84wXyEjWn-q; Mon, 10 Sep 2012 14:05:23 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 6FF8C2A28267; Mon, 10 Sep 2012 14:05:23 +0200 (CEST) From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: [PATCH v2 2/3] MIPS: JZ4740: Export timer API Date: Mon, 10 Sep 2012 14:05:18 +0200 Message-Id: <1347278719-15276-3-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:HQ89UM4vFbH2Mb7WTNYLn94RU111ke8VAlGJeLwYy1A HDLbkna6zgd8geFxobggXvqFidt+54Hzcg19hdGhRirLfNh+AI rMvPE+f+CaTKJBb/zck+rWumuTsnE9H3v4eAh9UhiRPVROpd8L F/MdeCecsjROl1YaF/vpHpsIDkdP3nCGf7lgSIDz2/I9MHy9WV Sxb3f+utrNuXlFGsSeVGQsqh74/Xjipc6jUYq9lHnBr+wG0YvA vcyUf5S+/cwzJPY8z+LCiICeQEYP/vOo8FvTLvLO1tFGLrIx87 7bzPOwV+DPDclPu/R5pySW1RxF4R4w39lvZb3ma4DnMFIhQzaA yu2wq+he09XcKY7kfKKMli2SPQ8lwG20FhcqZitAnTu8MziX/5 hranEOFcmK8Iuj4ij5kRVJNjzxHmxnxE6xxQeJKn560M9LnimB JjYwI X-archive-position: 34449 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 9967 Lines: 319 This is a prerequisite for allowing the PWM driver to be converted to the PWM framework. Signed-off-by: Thierry Reding --- Changes in v2: - keep timer API as static inline, move it to public header instead arch/mips/include/asm/mach-jz4740/timer.h | 113 +++++++++++++++++++++++++ arch/mips/jz4740/time.c | 2 +- arch/mips/jz4740/timer.c | 4 +- arch/mips/jz4740/timer.h | 136 ------------------------------ 4 files changed, 116 insertions(+), 139 deletions(-) delete mode 100644 arch/mips/jz4740/timer.h diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h index 9baa03c..a7759fb 100644 --- a/arch/mips/include/asm/mach-jz4740/timer.h +++ b/arch/mips/include/asm/mach-jz4740/timer.h @@ -16,7 +16,120 @@ #ifndef __ASM_MACH_JZ4740_TIMER #define __ASM_MACH_JZ4740_TIMER +#define JZ_REG_TIMER_STOP 0x0C +#define JZ_REG_TIMER_STOP_SET 0x1C +#define JZ_REG_TIMER_STOP_CLEAR 0x2C +#define JZ_REG_TIMER_ENABLE 0x00 +#define JZ_REG_TIMER_ENABLE_SET 0x04 +#define JZ_REG_TIMER_ENABLE_CLEAR 0x08 +#define JZ_REG_TIMER_FLAG 0x10 +#define JZ_REG_TIMER_FLAG_SET 0x14 +#define JZ_REG_TIMER_FLAG_CLEAR 0x18 +#define JZ_REG_TIMER_MASK 0x20 +#define JZ_REG_TIMER_MASK_SET 0x24 +#define JZ_REG_TIMER_MASK_CLEAR 0x28 + +#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30) +#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34) +#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38) +#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C) + +#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10) +#define JZ_TIMER_IRQ_FULL(x) BIT(x) + +#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9) +#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8) +#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7) +#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c +#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3 +#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3) +#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3) +#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3) +#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3) +#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3) +#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3) + +#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET) + +#define JZ_TIMER_CTRL_SRC_EXT BIT(2) +#define JZ_TIMER_CTRL_SRC_RTC BIT(1) +#define JZ_TIMER_CTRL_SRC_PCLK BIT(0) + +extern void __iomem *jz4740_timer_base; +void __init jz4740_timer_init(void); + void jz4740_timer_enable_watchdog(void); void jz4740_timer_disable_watchdog(void); +static inline void jz4740_timer_stop(unsigned int timer) +{ + writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); +} + +static inline void jz4740_timer_start(unsigned int timer) +{ + writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); +} + +static inline bool jz4740_timer_is_enabled(unsigned int timer) +{ + return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer); +} + +static inline void jz4740_timer_enable(unsigned int timer) +{ + writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); +} + +static inline void jz4740_timer_disable(unsigned int timer) +{ + writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); +} + +static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period) +{ + writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer)); +} + +static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty) +{ + writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer)); +} + +static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count) +{ + writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); +} + +static inline uint16_t jz4740_timer_get_count(unsigned int timer) +{ + return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); +} + +static inline void jz4740_timer_ack_full(unsigned int timer) +{ + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); +} + +static inline void jz4740_timer_irq_full_enable(unsigned int timer) +{ + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); +} + +static inline void jz4740_timer_irq_full_disable(unsigned int timer) +{ + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); +} + +static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl) +{ + writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); +} + +static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer) +{ + return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); +} + #endif diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c index f83c2dd..39bb4bb 100644 --- a/arch/mips/jz4740/time.c +++ b/arch/mips/jz4740/time.c @@ -20,10 +20,10 @@ #include #include +#include #include #include "clock.h" -#include "timer.h" #define TIMER_CLOCKEVENT 0 #define TIMER_CLOCKSOURCE 1 diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c index 654d5c3..22f11d7 100644 --- a/arch/mips/jz4740/timer.c +++ b/arch/mips/jz4740/timer.c @@ -17,11 +17,11 @@ #include #include -#include "timer.h" - #include +#include void __iomem *jz4740_timer_base; +EXPORT_SYMBOL_GPL(jz4740_timer_base); void jz4740_timer_enable_watchdog(void) { diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h deleted file mode 100644 index fca3994..0000000 --- a/arch/mips/jz4740/timer.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen - * JZ4740 platform timer support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __MIPS_JZ4740_TIMER_H__ -#define __MIPS_JZ4740_TIMER_H__ - -#include -#include - -#define JZ_REG_TIMER_STOP 0x0C -#define JZ_REG_TIMER_STOP_SET 0x1C -#define JZ_REG_TIMER_STOP_CLEAR 0x2C -#define JZ_REG_TIMER_ENABLE 0x00 -#define JZ_REG_TIMER_ENABLE_SET 0x04 -#define JZ_REG_TIMER_ENABLE_CLEAR 0x08 -#define JZ_REG_TIMER_FLAG 0x10 -#define JZ_REG_TIMER_FLAG_SET 0x14 -#define JZ_REG_TIMER_FLAG_CLEAR 0x18 -#define JZ_REG_TIMER_MASK 0x20 -#define JZ_REG_TIMER_MASK_SET 0x24 -#define JZ_REG_TIMER_MASK_CLEAR 0x28 - -#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30) -#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34) -#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38) -#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C) - -#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10) -#define JZ_TIMER_IRQ_FULL(x) BIT(x) - -#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9) -#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8) -#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7) -#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c -#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3 -#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3) -#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3) -#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3) -#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3) -#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3) -#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3) - -#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET) - -#define JZ_TIMER_CTRL_SRC_EXT BIT(2) -#define JZ_TIMER_CTRL_SRC_RTC BIT(1) -#define JZ_TIMER_CTRL_SRC_PCLK BIT(0) - -extern void __iomem *jz4740_timer_base; -void __init jz4740_timer_init(void); - -static inline void jz4740_timer_stop(unsigned int timer) -{ - writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); -} - -static inline void jz4740_timer_start(unsigned int timer) -{ - writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); -} - -static inline bool jz4740_timer_is_enabled(unsigned int timer) -{ - return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer); -} - -static inline void jz4740_timer_enable(unsigned int timer) -{ - writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); -} - -static inline void jz4740_timer_disable(unsigned int timer) -{ - writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); -} - - -static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period) -{ - writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer)); -} - -static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty) -{ - writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer)); -} - -static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count) -{ - writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); -} - -static inline uint16_t jz4740_timer_get_count(unsigned int timer) -{ - return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); -} - -static inline void jz4740_timer_ack_full(unsigned int timer) -{ - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); -} - -static inline void jz4740_timer_irq_full_enable(unsigned int timer) -{ - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); -} - -static inline void jz4740_timer_irq_full_disable(unsigned int timer) -{ - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); -} - -static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl) -{ - writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); -} - -static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer) -{ - return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); -} - -#endif -- 1.7.12 From thierry.reding@avionic-design.de Mon Sep 10 14:05:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 14:07:02 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.171]:53876 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903467Ab2IJMFm (ORCPT ); Mon, 10 Sep 2012 14:05:42 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0Mao5W-1SrjTG1rhK-00KhcH; Mon, 10 Sep 2012 14:05:28 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id C396A2A28267; Mon, 10 Sep 2012 14:05:27 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XGs+E21HWE61; Mon, 10 Sep 2012 14:05:24 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 3292B2A282DF; Mon, 10 Sep 2012 14:05:24 +0200 (CEST) From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: [PATCH v2 3/3] pwm: Add Ingenic JZ4740 support Date: Mon, 10 Sep 2012 14:05:19 +0200 Message-Id: <1347278719-15276-4-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:uKUgEID/Ix1bZoNHsIy0m2Rvmq6uGYdLYyVtS42fKP6 B89MC2Rf5J9rlsxnWbJ5Aw0kIIvJsqYVfC6ra5iMVSW935Ginj P5o+LvRPhmFfX/hGXH/0peTbZ2IzOu+VB1q63e4bWLwEGMXnsn umh7KBiVdZ73UJDXGhrR4fuHr6DzTeiuFQXaEb4rrFV4YgNXXR aVsMdmYvownCTLWTItAtF8td/5NPXfVR4rk4w4SeGO72HtYzAq PUhL+buMgEPy89avmJzBzn00RXprfhv8jf0BrmuMz3nJWqgiKq gL4pvygxTYdReizJypSVnWygxgmXQUG9Uy3KWc3a7bWgAuVgIZ jByLfzYlcpZGH47yaJEp1r+Cefwy6mNAHOGgbyN/GKZc0thXKj EXj+0MqIgj6n4Mre+EhaFKF8Hs3MLDFp4HPI7P+leNCN+5IA03 sjL4a X-archive-position: 34450 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 14216 Lines: 548 This commit moves the driver to drivers/pwm and converts it to the new PWM framework. Signed-off-by: Thierry Reding --- Changes in v2: - remove PWM core hunk that slipped in by mistake - change pwm-beeper platform data back to 4 - refer to timer.h by full path - register PWMs 0 and 1 but reserve them for system tasks - replace printk by dev_err now that a proper device is available - use jz4740_pwm_{enable,disable}() instead of pwm_{enable,disable}() internally - make THIS_MODULE the owner of jz4740_pwm_ops and jz4740_pwm_driver - add __devinit and __devexit annotations to jz4740_pwm_probe() and jz4740_pwm_remove() respectively - add MODULE_AUTHOR(), MODULE_DESCRIPTION(), MODULE_ALIAS() and MODULE_LICENSE() arch/mips/include/asm/mach-jz4740/platform.h | 1 + arch/mips/jz4740/Kconfig | 3 - arch/mips/jz4740/Makefile | 2 +- arch/mips/jz4740/board-qi_lb60.c | 1 + arch/mips/jz4740/platform.c | 6 + arch/mips/jz4740/pwm.c | 177 --------------------- drivers/pwm/Kconfig | 12 +- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-jz4740.c | 221 +++++++++++++++++++++++++++ 9 files changed, 242 insertions(+), 182 deletions(-) delete mode 100644 arch/mips/jz4740/pwm.c create mode 100644 drivers/pwm/pwm-jz4740.c diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h index 564ab81..163e81d 100644 --- a/arch/mips/include/asm/mach-jz4740/platform.h +++ b/arch/mips/include/asm/mach-jz4740/platform.h @@ -31,6 +31,7 @@ extern struct platform_device jz4740_pcm_device; extern struct platform_device jz4740_codec_device; extern struct platform_device jz4740_adc_device; extern struct platform_device jz4740_wdt_device; +extern struct platform_device jz4740_pwm_device; void jz4740_serial_device_register(void); diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig index 3e7141f..4689030 100644 --- a/arch/mips/jz4740/Kconfig +++ b/arch/mips/jz4740/Kconfig @@ -7,6 +7,3 @@ config JZ4740_QI_LB60 bool "Qi Hardware Ben NanoNote" endchoice - -config HAVE_PWM - bool diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile index e44abea..63bad0e 100644 --- a/arch/mips/jz4740/Makefile +++ b/arch/mips/jz4740/Makefile @@ -5,7 +5,7 @@ # Object file lists. obj-y += prom.o irq.o time.o reset.o setup.o dma.o \ - gpio.o clock.o platform.o timer.o pwm.o serial.o + gpio.o clock.o platform.o timer.o serial.o obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 9a3d9de..43d964d 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -437,6 +437,7 @@ static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_codec_device, &jz4740_rtc_device, &jz4740_adc_device, + &jz4740_pwm_device, &qi_lb60_gpio_keys, &qi_lb60_pwm_beeper, &qi_lb60_charger_device, diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c index e342ed4..6d14dcd 100644 --- a/arch/mips/jz4740/platform.c +++ b/arch/mips/jz4740/platform.c @@ -323,3 +323,9 @@ struct platform_device jz4740_wdt_device = { .num_resources = ARRAY_SIZE(jz4740_wdt_resources), .resource = jz4740_wdt_resources, }; + +/* PWM */ +struct platform_device jz4740_pwm_device = { + .name = "jz4740-pwm", + .id = -1, +}; diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c deleted file mode 100644 index a26a6fa..0000000 --- a/arch/mips/jz4740/pwm.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen - * JZ4740 platform PWM support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include - -#include -#include -#include -#include - -#include -#include "timer.h" - -static struct clk *jz4740_pwm_clk; - -DEFINE_MUTEX(jz4740_pwm_mutex); - -struct pwm_device { - unsigned int id; - unsigned int gpio; - bool used; -}; - -static struct pwm_device jz4740_pwm_list[] = { - { 2, JZ_GPIO_PWM2, false }, - { 3, JZ_GPIO_PWM3, false }, - { 4, JZ_GPIO_PWM4, false }, - { 5, JZ_GPIO_PWM5, false }, - { 6, JZ_GPIO_PWM6, false }, - { 7, JZ_GPIO_PWM7, false }, -}; - -struct pwm_device *pwm_request(int id, const char *label) -{ - int ret = 0; - struct pwm_device *pwm; - - if (id < 2 || id > 7 || !jz4740_pwm_clk) - return ERR_PTR(-ENODEV); - - mutex_lock(&jz4740_pwm_mutex); - - pwm = &jz4740_pwm_list[id - 2]; - if (pwm->used) - ret = -EBUSY; - else - pwm->used = true; - - mutex_unlock(&jz4740_pwm_mutex); - - if (ret) - return ERR_PTR(ret); - - ret = gpio_request(pwm->gpio, label); - - if (ret) { - printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret); - pwm->used = false; - return ERR_PTR(ret); - } - - jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM); - - jz4740_timer_start(id); - - return pwm; -} - -void pwm_free(struct pwm_device *pwm) -{ - pwm_disable(pwm); - jz4740_timer_set_ctrl(pwm->id, 0); - - jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE); - gpio_free(pwm->gpio); - - jz4740_timer_stop(pwm->id); - - pwm->used = false; -} - -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) -{ - unsigned long long tmp; - unsigned long period, duty; - unsigned int prescaler = 0; - unsigned int id = pwm->id; - uint16_t ctrl; - bool is_enabled; - - if (duty_ns < 0 || duty_ns > period_ns) - return -EINVAL; - - tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns; - do_div(tmp, 1000000000); - period = tmp; - - while (period > 0xffff && prescaler < 6) { - period >>= 2; - ++prescaler; - } - - if (prescaler == 6) - return -EINVAL; - - tmp = (unsigned long long)period * duty_ns; - do_div(tmp, period_ns); - duty = period - tmp; - - if (duty >= period) - duty = period - 1; - - is_enabled = jz4740_timer_is_enabled(id); - if (is_enabled) - pwm_disable(pwm); - - jz4740_timer_set_count(id, 0); - jz4740_timer_set_duty(id, duty); - jz4740_timer_set_period(id, period); - - ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | - JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; - - jz4740_timer_set_ctrl(id, ctrl); - - if (is_enabled) - pwm_enable(pwm); - - return 0; -} - -int pwm_enable(struct pwm_device *pwm) -{ - uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); - - ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; - jz4740_timer_set_ctrl(pwm->id, ctrl); - jz4740_timer_enable(pwm->id); - - return 0; -} - -void pwm_disable(struct pwm_device *pwm) -{ - uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); - - ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; - jz4740_timer_disable(pwm->id); - jz4740_timer_set_ctrl(pwm->id, ctrl); -} - -static int __init jz4740_pwm_init(void) -{ - int ret = 0; - - jz4740_pwm_clk = clk_get(NULL, "ext"); - - if (IS_ERR(jz4740_pwm_clk)) { - ret = PTR_ERR(jz4740_pwm_clk); - jz4740_pwm_clk = NULL; - } - - return ret; -} -subsys_initcall(jz4740_pwm_init); diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 90c5c73..5c663df 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -1,6 +1,6 @@ menuconfig PWM bool "Pulse-Width Modulation (PWM) Support" - depends on !MACH_JZ4740 && !PUV3_PWM + depends on !PUV3_PWM help Generic Pulse-Width Modulation (PWM) support. @@ -47,6 +47,16 @@ config PWM_IMX To compile this driver as a module, choose M here: the module will be called pwm-imx. +config PWM_JZ4740 + tristate "Ingenic JZ4740 PWM support" + depends on MACH_JZ4740 + help + Generic PWM framework driver for Ingenic JZ4740 based + machines. + + To compile this driver as a module, choose M here: the module + will be called pwm-jz4740. + config PWM_LPC32XX tristate "LPC32XX PWM support" depends on ARCH_LPC32XX diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index e4b2c89..a1d6169 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_PWM) += core.o obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o +obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c new file mode 100644 index 0000000..10250fc --- /dev/null +++ b/drivers/pwm/pwm-jz4740.c @@ -0,0 +1,221 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen + * JZ4740 platform PWM support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define NUM_PWM 8 + +static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = { + JZ_GPIO_PWM0, + JZ_GPIO_PWM1, + JZ_GPIO_PWM2, + JZ_GPIO_PWM3, + JZ_GPIO_PWM4, + JZ_GPIO_PWM5, + JZ_GPIO_PWM6, + JZ_GPIO_PWM7, +}; + +struct jz4740_pwm_chip { + struct pwm_chip chip; + struct clk *clk; +}; + +static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip) +{ + return container_of(chip, struct jz4740_pwm_chip, chip); +} + +static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; + int ret; + + /* + * Timers 0 and 1 are used for system tasks, so they are unavailable + * for use as PWMs. + */ + if (pwm->hwpwm < 2) + return -EBUSY; + + ret = gpio_request(gpio, pwm->label); + if (ret) { + dev_err(chip->dev, "Failed to request GPIO#%u for PWM: %d\n", + gpio, ret); + return ret; + } + + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_PWM); + + jz4740_timer_start(pwm->hwpwm); + + return 0; +} + +static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; + + jz4740_timer_set_ctrl(pwm->hwpwm, 0); + + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE); + gpio_free(gpio); + + jz4740_timer_stop(pwm->hwpwm); +} + +static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm); + + ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); + jz4740_timer_enable(pwm->hwpwm); + + return 0; +} + +static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); + + ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; + jz4740_timer_disable(pwm->hwpwm); + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); +} + +static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip); + unsigned long long tmp; + unsigned long period, duty; + unsigned int prescaler = 0; + uint16_t ctrl; + bool is_enabled; + + tmp = (unsigned long long)clk_get_rate(jz4740->clk) * period_ns; + do_div(tmp, 1000000000); + period = tmp; + + while (period > 0xffff && prescaler < 6) { + period >>= 2; + ++prescaler; + } + + if (prescaler == 6) + return -EINVAL; + + tmp = (unsigned long long)period * duty_ns; + do_div(tmp, period_ns); + duty = period - tmp; + + if (duty >= period) + duty = period - 1; + + is_enabled = jz4740_timer_is_enabled(pwm->hwpwm); + if (is_enabled) + jz4740_pwm_disable(chip, pwm); + + jz4740_timer_set_count(pwm->hwpwm, 0); + jz4740_timer_set_duty(pwm->hwpwm, duty); + jz4740_timer_set_period(pwm->hwpwm, period); + + ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | + JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; + + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); + + if (is_enabled) + jz4740_pwm_enable(chip, pwm); + + return 0; +} + +static const struct pwm_ops jz4740_pwm_ops = { + .request = jz4740_pwm_request, + .free = jz4740_pwm_free, + .config = jz4740_pwm_config, + .enable = jz4740_pwm_enable, + .disable = jz4740_pwm_disable, + .owner = THIS_MODULE, +}; + +static int __devinit jz4740_pwm_probe(struct platform_device *pdev) +{ + struct jz4740_pwm_chip *jz4740; + int ret; + + jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL); + if (!jz4740) + return -ENOMEM; + + jz4740->clk = clk_get(NULL, "ext"); + if (IS_ERR(jz4740->clk)) + return PTR_ERR(jz4740->clk); + + jz4740->chip.dev = &pdev->dev; + jz4740->chip.ops = &jz4740_pwm_ops; + jz4740->chip.npwm = NUM_PWM; + jz4740->chip.base = -1; + + ret = pwmchip_add(&jz4740->chip); + if (ret < 0) { + clk_put(jz4740->clk); + return ret; + } + + platform_set_drvdata(pdev, jz4740); + + return 0; +} + +static int __devexit jz4740_pwm_remove(struct platform_device *pdev) +{ + struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&jz4740->chip); + if (ret < 0) + return ret; + + clk_put(jz4740->clk); + + return 0; +} + +static struct platform_driver jz4740_pwm_driver = { + .driver = { + .name = "jz4740-pwm", + .owner = THIS_MODULE, + }, + .probe = jz4740_pwm_probe, + .remove = __devexit_p(jz4740_pwm_remove), +}; +module_platform_driver(jz4740_pwm_driver); + +MODULE_AUTHOR("Lars-Peter Clausen "); +MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver"); +MODULE_ALIAS("platform:jz4740-pwm"); +MODULE_LICENSE("GPL"); -- 1.7.12 From lars@metafoo.de Mon Sep 10 17:20:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 17:20:12 +0200 (CEST) Received: from smtp-out-024.synserver.de ([212.40.185.24]:1127 "EHLO smtp-out-024.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903466Ab2IJPUI (ORCPT ); Mon, 10 Sep 2012 17:20:08 +0200 Received: (qmail 29459 invoked by uid 0); 10 Sep 2012 15:19:58 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@metafoo.de X-SynServer-PPID: 29378 Received: from p5491fbb6.dip.t-dialin.net (HELO ?192.168.0.176?) [84.145.251.182] by 217.119.54.87 with AES256-SHA encrypted SMTP; 10 Sep 2012 15:19:58 -0000 Message-ID: <504E0542.8020309@metafoo.de> Date: Mon, 10 Sep 2012 17:20:34 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.6esrpre) Gecko/20120817 Icedove/10.0.6 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH v2 0/3] MIPS: JZ4740: Move PWM driver to PWM framework References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> In-Reply-To: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34451 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2392 Lines: 58 On 09/10/2012 02:05 PM, Thierry Reding wrote: > Hi, > I think v2 looks, good. Will give it some testing later. > This small series fixes a build error due to a circular header > dependency, exports the timer API so it can be used outside of > the arch/mips/jz4740 tree and finally moves and converts the > JZ4740 PWM driver to the PWM framework. > > Note that I don't have any hardware to test this on, so I had to > rely on compile tests only. Patches 1 and 2 should probably go > through the MIPS tree, while I can take patch 3 through the PWM > tree. It touches a couple of files in arch/mips but the changes > are unlikely to cause conflicts. Patch 2 and 3 should probably go through the same tree since patch 3 depends on patch 2. I'd like to see them both go through the PWM tree. Patch 1 should go through the MIPS tree, but I still can't see why the issue should occur nor does it happen for anybody else except for you. Instead of moving the content over to the public irq.h I'd rather like to see the private irq.h being renamed. Thanks, - Lars > > Thierry > > Thierry Reding (3): > MIPS: JZ4740: Break circular header dependency > MIPS: JZ4740: Export timer API > pwm: Add Ingenic JZ4740 support > > arch/mips/include/asm/mach-jz4740/irq.h | 5 + > arch/mips/include/asm/mach-jz4740/platform.h | 1 + > arch/mips/include/asm/mach-jz4740/timer.h | 113 ++++++++++++++ > arch/mips/jz4740/Kconfig | 3 - > arch/mips/jz4740/Makefile | 2 +- > arch/mips/jz4740/board-qi_lb60.c | 1 + > arch/mips/jz4740/irq.h | 23 --- > arch/mips/jz4740/platform.c | 6 + > arch/mips/jz4740/pwm.c | 177 --------------------- > arch/mips/jz4740/time.c | 2 +- > arch/mips/jz4740/timer.c | 4 +- > arch/mips/jz4740/timer.h | 136 ----------------- > drivers/pwm/Kconfig | 12 +- > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-jz4740.c | 221 +++++++++++++++++++++++++++ > 15 files changed, 363 insertions(+), 344 deletions(-) > delete mode 100644 arch/mips/jz4740/irq.h > delete mode 100644 arch/mips/jz4740/pwm.c > delete mode 100644 arch/mips/jz4740/timer.h > create mode 100644 drivers/pwm/pwm-jz4740.c > From ralf@linux-mips.org Mon Sep 10 19:08:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 19:08:41 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:38805 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903468Ab2IJRId (ORCPT ); Mon, 10 Sep 2012 19:08:33 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8AH8W1h013802; Mon, 10 Sep 2012 19:08:32 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8AH8UvH013801; Mon, 10 Sep 2012 19:08:30 +0200 Date: Mon, 10 Sep 2012 19:08:30 +0200 From: Ralf Baechle To: Rich Felker Cc: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? Message-ID: <20120910170830.GB24448@linux-mips.org> References: <20120909193008.GA15157@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120909193008.GA15157@brightrain.aerifal.cx> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34452 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 781 Lines: 17 On Sun, Sep 09, 2012 at 03:30:08PM -0400, Rich Felker wrote: > The kernel syscall entry/exit code seems to always save and restore > r25. Is this stable/documented behavior I can rely on? If there's a > reason it _needs_ to be preserved, knowing that would help convince me > it's safe to assume it will always be done. The intended usage is to > be able to make syscalls (where the syscall # is not a constant that > could be loaded with lwi) without a stack frame, as in "move $2,$25 ; > syscall". The basic design idea is that syscalls use a calling convention similar to subroutine calls. $25 is $t9, so a temp register which is callee saved. So if the kernel is saving $t9 and you've been relying on that, consider yourself lucky - there's not guarantee for that. Ralf From ralf@linux-mips.org Mon Sep 10 19:11:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 19:12:04 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:38817 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903468Ab2IJRL6 (ORCPT ); Mon, 10 Sep 2012 19:11:58 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8AHBvYg014081; Mon, 10 Sep 2012 19:11:57 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8AHBvfM014080; Mon, 10 Sep 2012 19:11:57 +0200 Date: Mon, 10 Sep 2012 19:11:57 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@linux-mips.org Subject: Re: MIPS: Fix build error with modern GCC for non-Cavium. Message-ID: <20120910171157.GC24448@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34453 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 589 Lines: 14 On Sat, Sep 08, 2012 at 08:28:26PM +0100, Maciej W. Rozycki wrote: > > An empty default block is not allowed so add a ; as empty statement to > > make gcc happy. > > A dummy "break" is the usual solution though. I don't think GCC ever > complains if it sees it unreachable after a "return" -- in a sense it is > just as unreachable as this null instruction is. I wasn't overly picky. Whatever gets the stuff to build correctly. I'm doing one final round of test builds over all -stable branches before dropping most of them like radioctive rocks. But more on that later. Ralf From dalias@aerifal.cx Mon Sep 10 19:19:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 19:20:02 +0200 (CEST) Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:39328 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903469Ab2IJRT6 (ORCPT ); Mon, 10 Sep 2012 19:19:58 +0200 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1TB7hC-0005TT-00 for linux-mips@linux-mips.org; Mon, 10 Sep 2012 17:22:50 +0000 Date: Mon, 10 Sep 2012 13:22:50 -0400 To: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? Message-ID: <20120910172248.GN27715@brightrain.aerifal.cx> References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120910170830.GB24448@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) From: Rich Felker X-archive-position: 34454 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dalias@aerifal.cx Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1729 Lines: 33 On Mon, Sep 10, 2012 at 07:08:30PM +0200, Ralf Baechle wrote: > On Sun, Sep 09, 2012 at 03:30:08PM -0400, Rich Felker wrote: > > > The kernel syscall entry/exit code seems to always save and restore > > r25. Is this stable/documented behavior I can rely on? If there's a > > reason it _needs_ to be preserved, knowing that would help convince me > > it's safe to assume it will always be done. The intended usage is to > > be able to make syscalls (where the syscall # is not a constant that > > could be loaded with lwi) without a stack frame, as in "move $2,$25 ; > > syscall". > > The basic design idea is that syscalls use a calling convention similar > to subroutine calls. $25 is $t9, so a temp register which is callee saved. > > So if the kernel is saving $t9 and you've been relying on that, consider > yourself lucky - there's not guarantee for that. Is there any documentation of what the kernel does guarantee? All existing syscall-making code I've seen depends at least on r4-r7 not being clobbered when a signal interrupts a syscall and sets it up for restart (since the arguments still need to be there when it's restarted), and seems to also depend on r4-r6 not being clobbered when the syscall successfully returns (since they're not listed in the clobber list, e.g. in uClibc's inline syscall asm). These are requirements beyond the normal function call convention (which does not require the callee preserve the values of r4-r7). As for my problem, I can use r7 as the temp ("move $2,$7 ; syscall") for syscalls with 3 or fewer args, but for the 4-arg syscall, $7 is occupied by an argument, and I'd need to spill the syscall number to the stack to be able to restore it if $25 is not available... Rich From thierry.reding@avionic-design.de Mon Sep 10 19:31:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 19:31:18 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.186]:60426 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903469Ab2IJRbL (ORCPT ); Mon, 10 Sep 2012 19:31:11 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap4) with ESMTP (Nemesis) id 0LfBVo-1TvS0I2aTo-00olkH; Mon, 10 Sep 2012 19:30:58 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 045E02A282F4; Mon, 10 Sep 2012 19:30:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RmwHvdBI+ORH; Mon, 10 Sep 2012 19:30:57 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 03A0A2A28295; Mon, 10 Sep 2012 19:30:56 +0200 (CEST) Date: Mon, 10 Sep 2012 19:30:56 +0200 From: Thierry Reding To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH v2 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Message-ID: <20120910173056.GA31611@avionic-0098.mockup.avionic-design.de> References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> <504E0542.8020309@metafoo.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="M9NhX3UHpAaciwkO" Content-Disposition: inline In-Reply-To: <504E0542.8020309@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:j+SZqMo+4tu8auhFQAWVbVDyMzIr5zhpulQT4J4rUYl 9b3+yNfw4j8lQc/Quejgps51f26mutUFc+5ZboaCSEQzgWR0j3 WCkCf9WuCtYqj/8QFU/1yT70PSjkPyb2uWxK5MaIXCCI0yDIh1 DgvszMW/Pp9CH5y13HyzG9Gf68nWe0lOdEJmPoY+s15ATT+ka+ IFMLs1YIvhQqMDVxOin6Ig0snaB6Lg/Ay/kXz2B6lulMRV8bBu jnqiL9C3jXEWITfjxqdlBTzFUzFqiNTOG6HEEkKxgoCAUwOxak Zxg8I/V/G4MePzSMXw90K3+iCMVfyxZIF+LBe4i5h0/gtoYFP+ KbelZmr/VjjEXuNZi298tNwelXHbMgqpAzquA5jWraKybuEhzn Te/Vl7SgY4HtHWELIf9QLEOUJbmHFYdGBxk5o6NblbSIhZKifg PYNVU X-archive-position: 34455 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2472 Lines: 66 --M9NhX3UHpAaciwkO Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Sep 10, 2012 at 05:20:34PM +0200, Lars-Peter Clausen wrote: > On 09/10/2012 02:05 PM, Thierry Reding wrote: > > Hi, > >=20 >=20 > I think v2 looks, good. Will give it some testing later. >=20 > > This small series fixes a build error due to a circular header > > dependency, exports the timer API so it can be used outside of > > the arch/mips/jz4740 tree and finally moves and converts the > > JZ4740 PWM driver to the PWM framework. > >=20 > > Note that I don't have any hardware to test this on, so I had to > > rely on compile tests only. Patches 1 and 2 should probably go > > through the MIPS tree, while I can take patch 3 through the PWM > > tree. It touches a couple of files in arch/mips but the changes > > are unlikely to cause conflicts. >=20 > Patch 2 and 3 should probably go through the same tree since patch 3 depe= nds > on patch 2. I'd like to see them both go through the PWM tree. That's fine with me. I'll probably need an Acked-by from Ralf just to be safe. > Patch 1 should go through the MIPS tree, but I still can't see why the is= sue > should occur nor does it happen for anybody else except for you. Instead = of > moving the content over to the public irq.h I'd rather like to see the > private irq.h being renamed. If we can solve this some other way I'm all for it. Maybe you can share the defconfig or .config that you use so I can test under the same conditions. Thierry --M9NhX3UHpAaciwkO Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQTiPQAAoJEN0jrNd/PrOhiAMQALvMtvosXECK2p3pb2bfBOtw NLKDadGL0SzXtBthxEI86edd6Px51aE7n1pmSa9p64ph1RqJXrD2/yl5E+FdmUFK csqn76lN7p/TM9uHj7pizVENTxKaDCVJmEpZz5zgTMEOnSURw6LWhv8xr1tmlFwz 4FBpY2PQwCcqtfFN3YNU0CQycD3QxxVi46aMydflRjnfLa3TAIGsGYXQFO3XC1Ut B18hksX5J0Lo0i5w76APoRN5HtEy3JA7uDxW3WUMVzwCUR/H+w4CQmqklYcr+WjB QExWiexGLT5R7MF+PP2kBk6+YWbJIOO6z9CgFDmTHHxPVNpa9/yBmUHvXtrTKWdl VwMWRIun6h+/U2lApUDqGznO3By8o1tspOT/aDqqgWn4IaFesDSIv19AifePnAbv AfXZ8TOrGL33xK5LpbcVlarfGQz7RqXMP9XGwnckOxrd5z44mlSzOjrBV6MV95eS DgpTSHSjQwVqVR4CGN9QkEfrgyPMMH7QPPf6mYWFeeY/OeIqyDYYMT7MM4EGBAQL 52ogcaEQQapiGv7MztTX4+haSSN/nSx3SZMedK+MdH1j+2uckYHUgSOLK5bdI2LE inqvcRx0pFCW5Y/K6jOL/4MaWIJWR/8h6LuLXkLoi4Hth4f7iFT3gDeQm7KBSKK4 hZGXJy4zQgeglCRy3gko =ND9B -----END PGP SIGNATURE----- --M9NhX3UHpAaciwkO-- From ddaney.cavm@gmail.com Mon Sep 10 20:05:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 20:05:13 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:57281 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903466Ab2IJSFF (ORCPT ); Mon, 10 Sep 2012 20:05:05 +0200 Received: by pbbrq8 with SMTP id rq8so3024140pbb.36 for ; Mon, 10 Sep 2012 11:04:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=EX57iYaZsxkx6zesvcJPdvD8OFOwy8yP9r5YUnzXNQw=; b=Ngi5kcqWdPs7t43yuHUQ9879hKttKcxtx6UBIkYfL3c+mFqhS9TjB9FendH1OrhURD 7iVFt0rWM8o0HIeoHuGoP6grbA5lDKei/QlotSQIVNGgsOrd5gvrdubOMICEezGOGXRb h1Ih4NjsAXJ/H08l9Uxi4jGGc+KCwSrAnsX8Wbx2i6NR2AX5ZDeLWdfR5pHTsvV7QQsL oUxhuMbJSbKR4yLTXn/fGlPk0feaiio+ciZJTDpFi+C2VQxElaBrnGcy6kktru0VgkHx o3mAaEerLbSeJF5aF2jR8HTBRGyt1pzMuR7Hec2zanpRjIkiZynunw4DUtuB1n0Bo8kO 0Osw== Received: by 10.68.129.73 with SMTP id nu9mr7013787pbb.59.1347300298283; Mon, 10 Sep 2012 11:04:58 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id uu10sm8424328pbc.2.2012.09.10.11.04.56 (version=SSLv3 cipher=OTHER); Mon, 10 Sep 2012 11:04:57 -0700 (PDT) Message-ID: <504E2BC7.7000108@gmail.com> Date: Mon, 10 Sep 2012 11:04:55 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: Rich Felker CC: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> <20120910172248.GN27715@brightrain.aerifal.cx> In-Reply-To: <20120910172248.GN27715@brightrain.aerifal.cx> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34456 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2103 Lines: 52 On 09/10/2012 10:22 AM, Rich Felker wrote: > On Mon, Sep 10, 2012 at 07:08:30PM +0200, Ralf Baechle wrote: >> On Sun, Sep 09, 2012 at 03:30:08PM -0400, Rich Felker wrote: >> >>> The kernel syscall entry/exit code seems to always save and restore >>> r25. Is this stable/documented behavior I can rely on? If there's a >>> reason it _needs_ to be preserved, knowing that would help convince me >>> it's safe to assume it will always be done. The intended usage is to >>> be able to make syscalls (where the syscall # is not a constant that >>> could be loaded with lwi) without a stack frame, as in "move $2,$25 ; >>> syscall". >> >> The basic design idea is that syscalls use a calling convention similar >> to subroutine calls. $25 is $t9, so a temp register which is callee saved. >> >> So if the kernel is saving $t9 and you've been relying on that, consider >> yourself lucky - there's not guarantee for that. > > Is there any documentation of what the kernel does guarantee? Not really. The glibc souces can be used as the canonical implementation as we cannot break it. glibc assumes $25 is clobbered. > All > existing syscall-making code I've seen depends at least on r4-r7 not > being clobbered when a signal interrupts a syscall This is an internal kernel implementation detail. Relying on it in userspace is probably not a good idea. > and sets it up for > restart (since the arguments still need to be there when it's > restarted), and seems to also depend on r4-r6 not being clobbered when > the syscall successfully returns (since they're not listed in the > clobber list, e.g. in uClibc's inline syscall asm). Some versions of uClibc's inline syscall asm are buggy. So they cannot be used as an indication of what is supported. > These are > requirements beyond the normal function call convention (which does > not require the callee preserve the values of r4-r7). I would assume these are clobbered (from glibc sources ports/sysdeps/unix/sysv/linux/mips/mips64/n64/sysdep.h): "$1", "$3", "$10", "$11", "$12", "$13", "$14", "$15", "$24", "$25", "hi", "lo" David Daney From dalias@aerifal.cx Mon Sep 10 20:34:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 20:34:32 +0200 (CEST) Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:58677 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903468Ab2IJSe2 (ORCPT ); Mon, 10 Sep 2012 20:34:28 +0200 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1TB8rI-0005cS-00 for linux-mips@linux-mips.org; Mon, 10 Sep 2012 18:37:20 +0000 Date: Mon, 10 Sep 2012 14:37:20 -0400 To: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? Message-ID: <20120910183720.GO27715@brightrain.aerifal.cx> References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> <20120910172248.GN27715@brightrain.aerifal.cx> <504E2BC7.7000108@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <504E2BC7.7000108@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) From: Rich Felker X-archive-position: 34457 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dalias@aerifal.cx Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 3300 Lines: 76 On Mon, Sep 10, 2012 at 11:04:55AM -0700, David Daney wrote: > On 09/10/2012 10:22 AM, Rich Felker wrote: > >On Mon, Sep 10, 2012 at 07:08:30PM +0200, Ralf Baechle wrote: > >>On Sun, Sep 09, 2012 at 03:30:08PM -0400, Rich Felker wrote: > >> > >>>The kernel syscall entry/exit code seems to always save and restore > >>>r25. Is this stable/documented behavior I can rely on? If there's a > >>>reason it _needs_ to be preserved, knowing that would help convince me > >>>it's safe to assume it will always be done. The intended usage is to > >>>be able to make syscalls (where the syscall # is not a constant that > >>>could be loaded with lwi) without a stack frame, as in "move $2,$25 ; > >>>syscall". > >> > >>The basic design idea is that syscalls use a calling convention similar > >>to subroutine calls. $25 is $t9, so a temp register which is callee saved. > >> > >>So if the kernel is saving $t9 and you've been relying on that, consider > >>yourself lucky - there's not guarantee for that. > > > >Is there any documentation of what the kernel does guarantee? > > Not really. The glibc souces can be used as the canonical > implementation as we cannot break it. glibc assumes $25 is > clobbered. OK. > >All > >existing syscall-making code I've seen depends at least on r4-r7 not > >being clobbered when a signal interrupts a syscall > > This is an internal kernel implementation detail. Relying on it in > userspace is probably not a good idea. When a restartable system call is interrupted by a signal, the kernel must arrange for it to restart after the signal handler returns. While some other obscure variants with trampolines are conceivable, the canonical way to do this is to set PC back to the syscall instruction with all the relevant registers preserved. MIPS is a bit peculiar in that the kernel sets PC back to the _previous_ instruction and requires that instruction to reload $2. This requirement is part of the syscall ABI in that failure of the application to properly reload $2 in this slot will cause unpredictable behavior when a syscall needs to be resumed after a signal. While I asked about preserving $25 in general, my actual concern is about the syscall restarting situation. I don't care if the value of $25 (or $7 in my alternate version) is lost once the syscall returns; I only care that the value is still there if the kernel decides to point PC back at the instruction before syscall in order to implement restarting. > >and sets it up for > >restart (since the arguments still need to be there when it's > >restarted), and seems to also depend on r4-r6 not being clobbered when > >the syscall successfully returns (since they're not listed in the > >clobber list, e.g. in uClibc's inline syscall asm). > > Some versions of uClibc's inline syscall asm are buggy. So they > cannot be used as an indication of what is supported. The code I'm looking at seems to match what you cited from glibc. > >These are > >requirements beyond the normal function call convention (which does > >not require the callee preserve the values of r4-r7). > > I would assume these are clobbered (from glibc sources > ports/sysdeps/unix/sysv/linux/mips/mips64/n64/sysdep.h): > > "$1", "$3", "$10", "$11", "$12", "$13", "$14", "$15", "$24", "$25", > "hi", "lo" OK. Rich From lars@metafoo.de Mon Sep 10 23:52:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Sep 2012 23:52:22 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:58743 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903485Ab2IJVwK (ORCPT ); Mon, 10 Sep 2012 23:52:10 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id C4403EBF; Mon, 10 Sep 2012 23:52:04 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id VtApCmXLYk0N; Mon, 10 Sep 2012 23:52:04 +0200 (CEST) Received: from [192.168.178.21] (ppp-93-104-171-183.dynamic.mnet-online.de [93.104.171.183]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 78B4CEBC; Mon, 10 Sep 2012 23:51:37 +0200 (CEST) Message-ID: <504E60F4.9010309@metafoo.de> Date: Mon, 10 Sep 2012 23:51:48 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20120724 Icedove/3.0.11 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH v2 3/3] pwm: Add Ingenic JZ4740 support References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> <1347278719-15276-4-git-send-email-thierry.reding@avionic-design.de> In-Reply-To: <1347278719-15276-4-git-send-email-thierry.reding@avionic-design.de> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34458 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 15767 Lines: 560 On 09/10/2012 02:05 PM, Thierry Reding wrote: > This commit moves the driver to drivers/pwm and converts it to the new > PWM framework. > > Signed-off-by: Thierry Reding Seems to work, thanks a lot. This one and patch 2: Acked-by: Lars-Peter Clausen Tested-by: Lars-Peter Clausen But I noticed a different problem. Some drivers using the pwm API depend on HAVE_PWM (e.g. the pwm beeper driver), but the generic PWM framework does not select HAVE_PWM, so I couldn't select the pwm beeper driver. Imo the generic PWM framework should select HAVE_PWM - Lars > --- > Changes in v2: > - remove PWM core hunk that slipped in by mistake > - change pwm-beeper platform data back to 4 > - refer to timer.h by full path > - register PWMs 0 and 1 but reserve them for system tasks > - replace printk by dev_err now that a proper device is available > - use jz4740_pwm_{enable,disable}() instead of pwm_{enable,disable}() > internally > - make THIS_MODULE the owner of jz4740_pwm_ops and jz4740_pwm_driver > - add __devinit and __devexit annotations to jz4740_pwm_probe() and > jz4740_pwm_remove() respectively > - add MODULE_AUTHOR(), MODULE_DESCRIPTION(), MODULE_ALIAS() and > MODULE_LICENSE() > > arch/mips/include/asm/mach-jz4740/platform.h | 1 + > arch/mips/jz4740/Kconfig | 3 - > arch/mips/jz4740/Makefile | 2 +- > arch/mips/jz4740/board-qi_lb60.c | 1 + > arch/mips/jz4740/platform.c | 6 + > arch/mips/jz4740/pwm.c | 177 --------------------- > drivers/pwm/Kconfig | 12 +- > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-jz4740.c | 221 +++++++++++++++++++++++++++ > 9 files changed, 242 insertions(+), 182 deletions(-) > delete mode 100644 arch/mips/jz4740/pwm.c > create mode 100644 drivers/pwm/pwm-jz4740.c > > diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h > index 564ab81..163e81d 100644 > --- a/arch/mips/include/asm/mach-jz4740/platform.h > +++ b/arch/mips/include/asm/mach-jz4740/platform.h > @@ -31,6 +31,7 @@ extern struct platform_device jz4740_pcm_device; > extern struct platform_device jz4740_codec_device; > extern struct platform_device jz4740_adc_device; > extern struct platform_device jz4740_wdt_device; > +extern struct platform_device jz4740_pwm_device; > > void jz4740_serial_device_register(void); > > diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig > index 3e7141f..4689030 100644 > --- a/arch/mips/jz4740/Kconfig > +++ b/arch/mips/jz4740/Kconfig > @@ -7,6 +7,3 @@ config JZ4740_QI_LB60 > bool "Qi Hardware Ben NanoNote" > > endchoice > - > -config HAVE_PWM > - bool > diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile > index e44abea..63bad0e 100644 > --- a/arch/mips/jz4740/Makefile > +++ b/arch/mips/jz4740/Makefile > @@ -5,7 +5,7 @@ > # Object file lists. > > obj-y += prom.o irq.o time.o reset.o setup.o dma.o \ > - gpio.o clock.o platform.o timer.o pwm.o serial.o > + gpio.o clock.o platform.o timer.o serial.o > > obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o > > diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c > index 9a3d9de..43d964d 100644 > --- a/arch/mips/jz4740/board-qi_lb60.c > +++ b/arch/mips/jz4740/board-qi_lb60.c > @@ -437,6 +437,7 @@ static struct platform_device *jz_platform_devices[] __initdata = { > &jz4740_codec_device, > &jz4740_rtc_device, > &jz4740_adc_device, > + &jz4740_pwm_device, > &qi_lb60_gpio_keys, > &qi_lb60_pwm_beeper, > &qi_lb60_charger_device, > diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c > index e342ed4..6d14dcd 100644 > --- a/arch/mips/jz4740/platform.c > +++ b/arch/mips/jz4740/platform.c > @@ -323,3 +323,9 @@ struct platform_device jz4740_wdt_device = { > .num_resources = ARRAY_SIZE(jz4740_wdt_resources), > .resource = jz4740_wdt_resources, > }; > + > +/* PWM */ > +struct platform_device jz4740_pwm_device = { > + .name = "jz4740-pwm", > + .id = -1, > +}; > diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c > deleted file mode 100644 > index a26a6fa..0000000 > --- a/arch/mips/jz4740/pwm.c > +++ /dev/null > @@ -1,177 +0,0 @@ > -/* > - * Copyright (C) 2010, Lars-Peter Clausen > - * JZ4740 platform PWM support > - * > - * This program is free software; you can redistribute it and/or modify it > - * under the terms of the GNU General Public License as published by the > - * Free Software Foundation; either version 2 of the License, or (at your > - * option) any later version. > - * > - * You should have received a copy of the GNU General Public License along > - * with this program; if not, write to the Free Software Foundation, Inc., > - * 675 Mass Ave, Cambridge, MA 02139, USA. > - * > - */ > - > -#include > - > -#include > -#include > -#include > -#include > - > -#include > -#include "timer.h" > - > -static struct clk *jz4740_pwm_clk; > - > -DEFINE_MUTEX(jz4740_pwm_mutex); > - > -struct pwm_device { > - unsigned int id; > - unsigned int gpio; > - bool used; > -}; > - > -static struct pwm_device jz4740_pwm_list[] = { > - { 2, JZ_GPIO_PWM2, false }, > - { 3, JZ_GPIO_PWM3, false }, > - { 4, JZ_GPIO_PWM4, false }, > - { 5, JZ_GPIO_PWM5, false }, > - { 6, JZ_GPIO_PWM6, false }, > - { 7, JZ_GPIO_PWM7, false }, > -}; > - > -struct pwm_device *pwm_request(int id, const char *label) > -{ > - int ret = 0; > - struct pwm_device *pwm; > - > - if (id < 2 || id > 7 || !jz4740_pwm_clk) > - return ERR_PTR(-ENODEV); > - > - mutex_lock(&jz4740_pwm_mutex); > - > - pwm = &jz4740_pwm_list[id - 2]; > - if (pwm->used) > - ret = -EBUSY; > - else > - pwm->used = true; > - > - mutex_unlock(&jz4740_pwm_mutex); > - > - if (ret) > - return ERR_PTR(ret); > - > - ret = gpio_request(pwm->gpio, label); > - > - if (ret) { > - printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret); > - pwm->used = false; > - return ERR_PTR(ret); > - } > - > - jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM); > - > - jz4740_timer_start(id); > - > - return pwm; > -} > - > -void pwm_free(struct pwm_device *pwm) > -{ > - pwm_disable(pwm); > - jz4740_timer_set_ctrl(pwm->id, 0); > - > - jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE); > - gpio_free(pwm->gpio); > - > - jz4740_timer_stop(pwm->id); > - > - pwm->used = false; > -} > - > -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > -{ > - unsigned long long tmp; > - unsigned long period, duty; > - unsigned int prescaler = 0; > - unsigned int id = pwm->id; > - uint16_t ctrl; > - bool is_enabled; > - > - if (duty_ns < 0 || duty_ns > period_ns) > - return -EINVAL; > - > - tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns; > - do_div(tmp, 1000000000); > - period = tmp; > - > - while (period > 0xffff && prescaler < 6) { > - period >>= 2; > - ++prescaler; > - } > - > - if (prescaler == 6) > - return -EINVAL; > - > - tmp = (unsigned long long)period * duty_ns; > - do_div(tmp, period_ns); > - duty = period - tmp; > - > - if (duty >= period) > - duty = period - 1; > - > - is_enabled = jz4740_timer_is_enabled(id); > - if (is_enabled) > - pwm_disable(pwm); > - > - jz4740_timer_set_count(id, 0); > - jz4740_timer_set_duty(id, duty); > - jz4740_timer_set_period(id, period); > - > - ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | > - JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; > - > - jz4740_timer_set_ctrl(id, ctrl); > - > - if (is_enabled) > - pwm_enable(pwm); > - > - return 0; > -} > - > -int pwm_enable(struct pwm_device *pwm) > -{ > - uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); > - > - ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; > - jz4740_timer_set_ctrl(pwm->id, ctrl); > - jz4740_timer_enable(pwm->id); > - > - return 0; > -} > - > -void pwm_disable(struct pwm_device *pwm) > -{ > - uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); > - > - ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; > - jz4740_timer_disable(pwm->id); > - jz4740_timer_set_ctrl(pwm->id, ctrl); > -} > - > -static int __init jz4740_pwm_init(void) > -{ > - int ret = 0; > - > - jz4740_pwm_clk = clk_get(NULL, "ext"); > - > - if (IS_ERR(jz4740_pwm_clk)) { > - ret = PTR_ERR(jz4740_pwm_clk); > - jz4740_pwm_clk = NULL; > - } > - > - return ret; > -} > -subsys_initcall(jz4740_pwm_init); > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 90c5c73..5c663df 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -1,6 +1,6 @@ > menuconfig PWM > bool "Pulse-Width Modulation (PWM) Support" > - depends on !MACH_JZ4740 && !PUV3_PWM > + depends on !PUV3_PWM > help > Generic Pulse-Width Modulation (PWM) support. > > @@ -47,6 +47,16 @@ config PWM_IMX > To compile this driver as a module, choose M here: the module > will be called pwm-imx. > > +config PWM_JZ4740 > + tristate "Ingenic JZ4740 PWM support" > + depends on MACH_JZ4740 > + help > + Generic PWM framework driver for Ingenic JZ4740 based > + machines. > + > + To compile this driver as a module, choose M here: the module > + will be called pwm-jz4740. > + > config PWM_LPC32XX > tristate "LPC32XX PWM support" > depends on ARCH_LPC32XX > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index e4b2c89..a1d6169 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -1,6 +1,7 @@ > obj-$(CONFIG_PWM) += core.o > obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o > obj-$(CONFIG_PWM_IMX) += pwm-imx.o > +obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o > obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o > obj-$(CONFIG_PWM_MXS) += pwm-mxs.o > obj-$(CONFIG_PWM_PXA) += pwm-pxa.o > diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c > new file mode 100644 > index 0000000..10250fc > --- /dev/null > +++ b/drivers/pwm/pwm-jz4740.c > @@ -0,0 +1,221 @@ > +/* > + * Copyright (C) 2010, Lars-Peter Clausen > + * JZ4740 platform PWM support > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +#define NUM_PWM 8 > + > +static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = { > + JZ_GPIO_PWM0, > + JZ_GPIO_PWM1, > + JZ_GPIO_PWM2, > + JZ_GPIO_PWM3, > + JZ_GPIO_PWM4, > + JZ_GPIO_PWM5, > + JZ_GPIO_PWM6, > + JZ_GPIO_PWM7, > +}; > + > +struct jz4740_pwm_chip { > + struct pwm_chip chip; > + struct clk *clk; > +}; > + > +static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip) > +{ > + return container_of(chip, struct jz4740_pwm_chip, chip); > +} > + > +static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) > +{ > + unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; > + int ret; > + > + /* > + * Timers 0 and 1 are used for system tasks, so they are unavailable > + * for use as PWMs. > + */ > + if (pwm->hwpwm < 2) > + return -EBUSY; > + > + ret = gpio_request(gpio, pwm->label); > + if (ret) { > + dev_err(chip->dev, "Failed to request GPIO#%u for PWM: %d\n", > + gpio, ret); > + return ret; > + } > + > + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_PWM); > + > + jz4740_timer_start(pwm->hwpwm); > + > + return 0; > +} > + > +static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) > +{ > + unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; > + > + jz4740_timer_set_ctrl(pwm->hwpwm, 0); > + > + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE); > + gpio_free(gpio); > + > + jz4740_timer_stop(pwm->hwpwm); > +} > + > +static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) > +{ > + uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm); > + > + ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; > + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); > + jz4740_timer_enable(pwm->hwpwm); > + > + return 0; > +} > + > +static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) > +{ > + uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); > + > + ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; > + jz4740_timer_disable(pwm->hwpwm); > + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); > +} > + > +static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, > + int duty_ns, int period_ns) > +{ > + struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip); > + unsigned long long tmp; > + unsigned long period, duty; > + unsigned int prescaler = 0; > + uint16_t ctrl; > + bool is_enabled; > + > + tmp = (unsigned long long)clk_get_rate(jz4740->clk) * period_ns; > + do_div(tmp, 1000000000); > + period = tmp; > + > + while (period > 0xffff && prescaler < 6) { > + period >>= 2; > + ++prescaler; > + } > + > + if (prescaler == 6) > + return -EINVAL; > + > + tmp = (unsigned long long)period * duty_ns; > + do_div(tmp, period_ns); > + duty = period - tmp; > + > + if (duty >= period) > + duty = period - 1; > + > + is_enabled = jz4740_timer_is_enabled(pwm->hwpwm); > + if (is_enabled) > + jz4740_pwm_disable(chip, pwm); > + > + jz4740_timer_set_count(pwm->hwpwm, 0); > + jz4740_timer_set_duty(pwm->hwpwm, duty); > + jz4740_timer_set_period(pwm->hwpwm, period); > + > + ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | > + JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; > + > + jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); > + > + if (is_enabled) > + jz4740_pwm_enable(chip, pwm); > + > + return 0; > +} > + > +static const struct pwm_ops jz4740_pwm_ops = { > + .request = jz4740_pwm_request, > + .free = jz4740_pwm_free, > + .config = jz4740_pwm_config, > + .enable = jz4740_pwm_enable, > + .disable = jz4740_pwm_disable, > + .owner = THIS_MODULE, > +}; > + > +static int __devinit jz4740_pwm_probe(struct platform_device *pdev) > +{ > + struct jz4740_pwm_chip *jz4740; > + int ret; > + > + jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL); > + if (!jz4740) > + return -ENOMEM; > + > + jz4740->clk = clk_get(NULL, "ext"); > + if (IS_ERR(jz4740->clk)) > + return PTR_ERR(jz4740->clk); > + > + jz4740->chip.dev = &pdev->dev; > + jz4740->chip.ops = &jz4740_pwm_ops; > + jz4740->chip.npwm = NUM_PWM; > + jz4740->chip.base = -1; > + > + ret = pwmchip_add(&jz4740->chip); > + if (ret < 0) { > + clk_put(jz4740->clk); > + return ret; > + } > + > + platform_set_drvdata(pdev, jz4740); > + > + return 0; > +} > + > +static int __devexit jz4740_pwm_remove(struct platform_device *pdev) > +{ > + struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev); > + int ret; > + > + ret = pwmchip_remove(&jz4740->chip); > + if (ret < 0) > + return ret; > + > + clk_put(jz4740->clk); > + > + return 0; > +} > + > +static struct platform_driver jz4740_pwm_driver = { > + .driver = { > + .name = "jz4740-pwm", > + .owner = THIS_MODULE, > + }, > + .probe = jz4740_pwm_probe, > + .remove = __devexit_p(jz4740_pwm_remove), > +}; > +module_platform_driver(jz4740_pwm_driver); > + > +MODULE_AUTHOR("Lars-Peter Clausen "); > +MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver"); > +MODULE_ALIAS("platform:jz4740-pwm"); > +MODULE_LICENSE("GPL"); From macro@linux-mips.org Tue Sep 11 02:29:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 02:29:58 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:37920 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903487Ab2IKA3w (ORCPT ); Tue, 11 Sep 2012 02:29:52 +0200 Date: Tue, 11 Sep 2012 01:29:52 +0100 (BST) From: "Maciej W. Rozycki" To: Rich Felker , Ralf Baechle cc: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? In-Reply-To: <20120910172248.GN27715@brightrain.aerifal.cx> Message-ID: References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> <20120910172248.GN27715@brightrain.aerifal.cx> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 34459 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1008 Lines: 22 On Mon, 10 Sep 2012, Rich Felker wrote: > As for my problem, I can use r7 as the temp ("move $2,$7 ; syscall") > for syscalls with 3 or fewer args, but for the 4-arg syscall, $7 is > occupied by an argument, and I'd need to spill the syscall number to > the stack to be able to restore it if $25 is not available... If performance or some other factors require you to avoid spilling the syscall number to the stack or other readily-accessible (e.g. GP-relative) memory and the number is not a constant you could load with LI, then you can always store it in a call-saved register, one of $s0-$s8, that are guaranteed by the syscall ABI to be preserved across. Relying on any call-clobbered registers, including $7 to be preserved across a syscall is risky, to say the least, as this is not guaranteed by the syscall ABI. I do wonder however why we have these instructions to save/restore $25 in SAVE_SOME/RESTORE_SOME. This dates back to 2.4 at the very least. Ralf, any insights? Maciej From kevink@paralogos.com Tue Sep 11 03:04:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 03:04:48 +0200 (CEST) Received: from gateway09.websitewelcome.com ([67.18.39.12]:50216 "EHLO gateway09.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903487Ab2IKBEo (ORCPT ); Tue, 11 Sep 2012 03:04:44 +0200 Received: by gateway09.websitewelcome.com (Postfix, from userid 507) id 8EEC9D6ECAB5; Mon, 10 Sep 2012 20:04:41 -0500 (CDT) Received: from gator750.hostgator.com (gator750.hostgator.com [174.132.194.2]) by gateway09.websitewelcome.com (Postfix) with ESMTP id 81F26D6ECA94 for ; Mon, 10 Sep 2012 20:04:41 -0500 (CDT) Received: from [216.239.45.4] (port=7415 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.77) (envelope-from ) id 1TBEu9-0002Oh-6l for linux-mips@linux-mips.org; Mon, 10 Sep 2012 20:04:41 -0500 Message-ID: <504E8E27.5030904@paralogos.com> Date: Mon, 10 Sep 2012 18:04:39 -0700 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120827 Thunderbird/15.0 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> <20120910172248.GN27715@brightrain.aerifal.cx> In-Reply-To: X-Enigmail-Version: 1.4.4 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-BWhitelist: no X-Source: X-Source-Args: X-Source-Dir: X-Source-Sender: (kkissell.mtv.corp.google.com) [216.239.45.4]:7415 X-Source-Auth: kevink@kevink.net X-Email-Count: 1 X-Source-Cap: a2tpc3NlbGw7a2tpc3NlbGw7Z2F0b3I3NTAuaG9zdGdhdG9yLmNvbQ== X-archive-position: 34460 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 317 Lines: 9 On 09/10/2012 05:29 PM, Maciej W. Rozycki wrote: > I do wonder however why we have these instructions to save/restore $25 > in SAVE_SOME/RESTORE_SOME. This dates back to 2.4 at the very least. > Ralf, any insights? Hi, guys. Maybe the fact that it's used for dispatching PIC calls has something to do with it? /K. From ddaney.cavm@gmail.com Tue Sep 11 03:28:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 03:28:10 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:39299 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903487Ab2IKB2F (ORCPT ); Tue, 11 Sep 2012 03:28:05 +0200 Received: by pbbrq8 with SMTP id rq8so80753pbb.36 for ; Mon, 10 Sep 2012 18:27:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=p4PjrGXx3lKLKp2kQnzLpCiIVrj9McRvZZ4761IaWAQ=; b=ucoG0MgH+9kaDRxQSpCOmglFe+uxWtSiMJ9FaJFL5iDrzJ3SfHyIO+6b8XaqnZ+KNv dmjlrgWnH8URWtNYXPXWsskei8jeV1W0/uMW1beTarcYkuW3IEaGyjfn53+ow5quBkUm R77RY5rFkaffAEpfrjexBFGKeZWp6WyGH6/+//Ki5N2k5nkFliTX+kKcSYwzLvHUIOzL Cta6pPKxhFdPpR7PkXHdQp3MUO87gsyWNBQP5Ay21X11oCJvd7TqBMXwQjg85fbKhSPL ehE3GbkPM734PdHeS5fkexap6cGCYg5oFH6fWR7i+Up+VSjKROT+YGOc9rby/AYGwL1B diWw== Received: by 10.66.89.37 with SMTP id bl5mr24563085pab.55.1347326878848; Mon, 10 Sep 2012 18:27:58 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id qf4sm8973626pbc.1.2012.09.10.18.27.55 (version=SSLv3 cipher=OTHER); Mon, 10 Sep 2012 18:27:56 -0700 (PDT) Message-ID: <504E939B.5060209@gmail.com> Date: Mon, 10 Sep 2012 18:27:55 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: "Kevin D. Kissell" CC: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> <20120910172248.GN27715@brightrain.aerifal.cx> <504E8E27.5030904@paralogos.com> In-Reply-To: <504E8E27.5030904@paralogos.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34461 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 758 Lines: 26 On 09/10/2012 06:04 PM, Kevin D. Kissell wrote: > On 09/10/2012 05:29 PM, Maciej W. Rozycki wrote: >> I do wonder however why we have these instructions to save/restore $25 >> in SAVE_SOME/RESTORE_SOME. This dates back to 2.4 at the very least. >> Ralf, any insights? > Hi, guys. Maybe the fact that it's used for dispatching PIC calls has > something to do with it? > I don't think so. It is call clobbered in all Linux ABIs. So there is never a need to save it. It even has the pseudonym of $t9 indicating that it will get clobbered. The other call clobbered registers that happen to be saved are for the nefarious uses of the kernel itself (a0..a6 for system call restarting), I think this is just left over cruft. David Daney > /K. > > > > From dalias@aerifal.cx Tue Sep 11 04:25:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 04:25:52 +0200 (CEST) Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:51211 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901165Ab2IKCZr (ORCPT ); Tue, 11 Sep 2012 04:25:47 +0200 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1TBGDQ-0006UC-00 for linux-mips@linux-mips.org; Tue, 11 Sep 2012 02:28:40 +0000 Date: Mon, 10 Sep 2012 22:28:40 -0400 To: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? Message-ID: <20120911022840.GP27715@brightrain.aerifal.cx> References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> <20120910172248.GN27715@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) From: Rich Felker X-archive-position: 34462 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dalias@aerifal.cx Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2396 Lines: 50 On Tue, Sep 11, 2012 at 01:29:52AM +0100, Maciej W. Rozycki wrote: > On Mon, 10 Sep 2012, Rich Felker wrote: > > > As for my problem, I can use r7 as the temp ("move $2,$7 ; syscall") > > for syscalls with 3 or fewer args, but for the 4-arg syscall, $7 is > > occupied by an argument, and I'd need to spill the syscall number to > > the stack to be able to restore it if $25 is not available... > > If performance or some other factors require you to avoid spilling the > syscall number to the stack or other readily-accessible (e.g. GP-relative) > memory and the number is not a constant you could load with LI, then you > can always store it in a call-saved register, one of $s0-$s8, that are > guaranteed by the syscall ABI to be preserved across. That's not possible; you'd need to save the old contents of that register somewhere else, and that requires spilling it to the stack. > Relying on any call-clobbered registers, including $7 to be preserved > across a syscall is risky, to say the least, as this is not guaranteed by > the syscall ABI. Relying on them being preserved upon return from the syscall is "unsafe", I agree. In reality, r4-r6 are preserved, and r7 is clobbered with the syscall error flag. But there's no fundamental reason r4-r6 have to be preserved in this case. On the other hand, relying on them being preserved when the kernel resets PC to the instruction before the syscall instruction in order to restart as syscall after a signal interrupts it is completely safe. If it didn't restore them, the restarted syscall would be executed with the wrong arguments. Of course the kernel design could change to point PC at the syscall instruction rather than the previous instruction, and arrange for the registers (including $2) to all have their correct values for the syscall, and then the issue would become irrelevant because the instruction "move $2,$7" would not be executed again on restart. > I do wonder however why we have these instructions to > save/restore $25 in SAVE_SOME/RESTORE_SOME. This dates back to 2.4 at the > very least. > > Ralf, any insights? I would be interested in knowing too. It goes back further than 2.4. It seems 2.0 saved and restored ALL registers, and 2.2 dropped it down to the current set. This past change is why I'm hesitant to rely on behavior that's not either documented or fundamentally required. Rich From thierry.reding@avionic-design.de Tue Sep 11 07:02:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 07:02:37 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.10]:62442 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901165Ab2IKFC3 (ORCPT ); Tue, 11 Sep 2012 07:02:29 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap1) with ESMTP (Nemesis) id 0M34gJ-1TRJSo3mPH-00sCro; Tue, 11 Sep 2012 07:02:18 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 2D4452A282DE; Tue, 11 Sep 2012 07:02:17 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AWE1yohhOmSg; Tue, 11 Sep 2012 07:02:15 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 3F4CB2A280F5; Tue, 11 Sep 2012 07:02:15 +0200 (CEST) Date: Tue, 11 Sep 2012 07:02:11 +0200 From: Thierry Reding To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH v2 3/3] pwm: Add Ingenic JZ4740 support Message-ID: <20120911050211.GA23771@avionic-0098.mockup.avionic-design.de> References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> <1347278719-15276-4-git-send-email-thierry.reding@avionic-design.de> <504E60F4.9010309@metafoo.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="5vNYLRcllDrimb99" Content-Disposition: inline In-Reply-To: <504E60F4.9010309@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:7ul+BrP8/wvk6OrYOTddx8xmo41Rh5GiacLv3LzLEQJ sSqMEFnnBjI0YhoFwoV9fH3TFbfEQNC9WRfcU6Hol1j1KlvN7A CNudZbMpA4kdXWyzijNcWz2gLaMRXyHro6i0yI538FpdHG3Ym6 u1wXGdMUwpMVnHs1kgaaOKjvCu+R3UDquk90JbrLV9qhBm7BOe SnDj1fv3aqQf5/YlcE/B9Z1OM+DmoyPQFlvlkeomIds3dOXn6e hfxkK4ZY9POqDzMTmnHc0vW/p0emeGTgSuK1sKL0/C2tWrCeDQ JLdW4YwJB+L7uLYbTydLLF9ctjCWgSeDwtKrSbG9/kA0RMuCL1 oHU1cPPXub3CkA+HRyhPVCpx5qtDn/1+5Yhs0k0bF0TlWvOy4u F/5Qdwb053ZBP6CitOCiQ4wZjPgKUO7E2JHevxm+36chCTcHr5 GtVPS X-archive-position: 34463 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2450 Lines: 62 --5vNYLRcllDrimb99 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Sep 10, 2012 at 11:51:48PM +0200, Lars-Peter Clausen wrote: > On 09/10/2012 02:05 PM, Thierry Reding wrote: > > This commit moves the driver to drivers/pwm and converts it to the new > > PWM framework. > >=20 > > Signed-off-by: Thierry Reding >=20 > Seems to work, thanks a lot. This one and patch 2: >=20 > Acked-by: Lars-Peter Clausen > Tested-by: Lars-Peter Clausen >=20 > But I noticed a different problem. Some drivers using the pwm API depend = on > HAVE_PWM (e.g. the pwm beeper driver), but the generic PWM framework does= not > select HAVE_PWM, so I couldn't select the pwm beeper driver. Imo the gene= ric > PWM framework should select HAVE_PWM Does it also work if you add || PWM to the PWM beeper driver's depends? I thought I had done something similar for pwm-backlight, but looking at the logs I didn't. The reason was that it also uses the new APIs introduced by the PWM subsystem. For pwm-beeper the situation is different because it only uses the legacy API and therefore can work with both the legacy and new frameworks. I think selecting HAVE_PWM won't work properly because it isn't provided by all architectures. So you might end up with PWM enabled on PowerPC, which doesn't define HAVE_PWM and will probably give you Kconfig warnings and will still not let you select pwm-beeper. Thierry --5vNYLRcllDrimb99 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQTsXTAAoJEN0jrNd/PrOhZi4P/R390gRh2p7kvHME3Zk2amYN FEOVvtlGpvOrIZE8rUhOX3gkdQNScNrVPDfru2ZH8r0DMzIGAhE3LV5O/HxKa8yg eNREkWzlEIGtgS61SGnqjnuDzC1FHMlT0/qDV6/4IT+3H4rPaSHvM5+8g/wwrmVX 3jqC3QDxHNi5SVGTzZUv4cYG5IFPOzV7oN339CAF6+3dTxHKfSHWgVxetUppyblz yQQ6NnLj24fI7s77f7ri8It6lZyEes/3fjY/XjLcMTdXJ/gOIVYq+kqeJYAECvkM gzFC/Rc0Wgtuqzaez3pE6i/+4ef8Gl5GXLv4GbgADDlJqKe8Vs7iARm9bdMpOiYx e8JLMqn5ivZDWIr2igRKQZsv3eFx1HHxyKJpAJhSR1MtBemGYmp5A052chjxvnQn n/LxblyknDSdDM0jq2sjjNDxnQ4W7A3x0vaeKlrkRq0Ku61zlSYpo7AovqXI4n1s GlRJYyEx+ZOqGsGbWlvtRVD1+0vLPRLUBkYCqgsyECPNVeAJdV/MwKCIlYfdXrAI XbZbLvlUkuR8FSOIYP7AV3tIQwXPdvIO4qCIkeL7l1eTf3UAk6M5SbC9Lia4CeBZ KWUkBP65ourncCuIdNvqOGsdbTBRPbtrjyQSlgrqn5MQZYDz7jH6EqJ8X6qIFNQe zJ4DZj4o+jlQlY0Ax52f =qAec -----END PGP SIGNATURE----- --5vNYLRcllDrimb99-- From ralf@linux-mips.org Tue Sep 11 10:12:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 10:13:07 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:44691 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903303Ab2IKIM7 (ORCPT ); Tue, 11 Sep 2012 10:12:59 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8B8Cv8m018844; Tue, 11 Sep 2012 10:12:57 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8B8Cuur018843; Tue, 11 Sep 2012 10:12:56 +0200 Date: Tue, 11 Sep 2012 10:12:56 +0200 From: Ralf Baechle To: Rich Felker Cc: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? Message-ID: <20120911081256.GD24448@linux-mips.org> References: <20120909193008.GA15157@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120909193008.GA15157@brightrain.aerifal.cx> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34464 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 845 Lines: 21 On Sun, Sep 09, 2012 at 03:30:08PM -0400, Rich Felker wrote: > Hi all, > The kernel syscall entry/exit code seems to always save and restore > r25. Is this stable/documented behavior I can rely on? If there's a > reason it _needs_ to be preserved, knowing that would help convince me > it's safe to assume it will always be done. The intended usage is to > be able to make syscalls (where the syscall # is not a constant that > could be loaded with lwi) without a stack frame, as in "move $2,$25 ; > syscall". Since there is no place where the syscall interface is documented other than in the code itself, I've written a new wiki article http://www.linux-mips.org/wiki/Syscall as start. It's still lacking on the more obscure points but it at least should have have answered your question, had it already existed when you asked. Ralf From ralf@linux-mips.org Tue Sep 11 10:48:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 10:48:11 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:45126 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903304Ab2IKIsG (ORCPT ); Tue, 11 Sep 2012 10:48:06 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8B8m4hp021507; Tue, 11 Sep 2012 10:48:04 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8B8m4po021506; Tue, 11 Sep 2012 10:48:04 +0200 Date: Tue, 11 Sep 2012 10:48:04 +0200 From: Ralf Baechle To: Rich Felker Cc: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? Message-ID: <20120911084804.GE24448@linux-mips.org> References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> <20120910172248.GN27715@brightrain.aerifal.cx> <504E2BC7.7000108@gmail.com> <20120910183720.GO27715@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120910183720.GO27715@brightrain.aerifal.cx> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34465 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2503 Lines: 56 On Mon, Sep 10, 2012 at 02:37:20PM -0400, Rich Felker wrote: > When a restartable system call is interrupted by a signal, the kernel > must arrange for it to restart after the signal handler returns. > While some other obscure variants with trampolines are conceivable, > the canonical way to do this is to set PC back to the syscall > instruction with all the relevant registers preserved. MIPS is a bit > peculiar in that the kernel sets PC back to the _previous_ instruction > and requires that instruction to reload $2. This requirement is part > of the syscall ABI in that failure of the application to properly > reload $2 in this slot will cause unpredictable behavior when a > syscall needs to be resumed after a signal. > > While I asked about preserving $25 in general, my actual concern is > about the syscall restarting situation. I don't care if the value of > $25 (or $7 in my alternate version) is lost once the syscall returns; > I only care that the value is still there if the kernel decides to > point PC back at the instruction before syscall in order to implement > restarting. Yes. The kernel keeps a backup copy of $a3 around and uses it to restore the old content of $a3 before returning to userland, even in old kernels. A recent signal.c contains: if (regs->regs[2] == ERESTART_RESTARTBLOCK) { regs->regs[2] = current->thread.abi->restart; regs->regs[7] = regs->regs[26]; regs->cp0_epc -= 4; } Note that c0_epc is made to point back to the SYSCALL instruction, not the one preceeding the SYSCALL instructions since 8f5a00eb4 [MIPS: Sanitize restart logics] which went in for 2.6.36. Relying on userland to reload $v0 was something ugly that Linux inherited from god knows where and I'm happy to have gotten rid of that. > The code I'm looking at seems to match what you cited from glibc. > > > >These are > > >requirements beyond the normal function call convention (which does > > >not require the callee preserve the values of r4-r7). > > > > I would assume these are clobbered (from glibc sources > > ports/sysdeps/unix/sysv/linux/mips/mips64/n64/sysdep.h): > > > > "$1", "$3", "$10", "$11", "$12", "$13", "$14", "$15", "$24", "$25", > > "hi", "lo" Which is correct but also means that the _syscallX() macros that were in up to 2.6.19 were broken; the were lacking clobbers for $25, $hi and $lo. Unfortunately these macros were copied into many libraries and applications. Ralf From ralf@linux-mips.org Tue Sep 11 10:58:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 10:58:35 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:56222 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903305Ab2IKI62 (ORCPT ); Tue, 11 Sep 2012 10:58:28 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8B8wREK022300; Tue, 11 Sep 2012 10:58:27 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8B8wRqr022299; Tue, 11 Sep 2012 10:58:27 +0200 Date: Tue, 11 Sep 2012 10:58:27 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: Rich Felker , linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? Message-ID: <20120911085827.GF24448@linux-mips.org> References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> <20120910172248.GN27715@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34466 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 699 Lines: 16 On Tue, Sep 11, 2012 at 01:29:52AM +0100, Maciej W. Rozycki wrote: > Relying on any call-clobbered registers, including $7 to be preserved > across a syscall is risky, to say the least, as this is not guaranteed by > the syscall ABI. I do wonder however why we have these instructions to > save/restore $25 in SAVE_SOME/RESTORE_SOME. This dates back to 2.4 at the > very least. > > Ralf, any insights? It dates back to the initial commit in 36ea5120 from March 27, 1998 for 2.1.90 when for the sake of better lmbench syscall latency numbers I had introduced the concept of partial saving of a register frame. I think it should rather have been in SAVE_TEMP/RESTORE_TEMP instead. Ralf From dalias@aerifal.cx Tue Sep 11 15:29:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 15:29:57 +0200 (CEST) Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:36919 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903487Ab2IKN3t (ORCPT ); Tue, 11 Sep 2012 15:29:49 +0200 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1TBQa3-00079E-00 for linux-mips@linux-mips.org; Tue, 11 Sep 2012 13:32:43 +0000 Date: Tue, 11 Sep 2012 09:32:43 -0400 To: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? Message-ID: <20120911133243.GR27715@brightrain.aerifal.cx> References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120910170830.GB24448@linux-mips.org> <20120910172248.GN27715@brightrain.aerifal.cx> <504E2BC7.7000108@gmail.com> <20120910183720.GO27715@brightrain.aerifal.cx> <20120911084804.GE24448@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120911084804.GE24448@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) From: Rich Felker X-archive-position: 34467 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dalias@aerifal.cx Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1922 Lines: 42 On Tue, Sep 11, 2012 at 10:48:04AM +0200, Ralf Baechle wrote: > Note that c0_epc is made to point back to the SYSCALL instruction, > not the one preceeding the SYSCALL instructions since 8f5a00eb4 [MIPS: > Sanitize restart logics] which went in for 2.6.36. > > Relying on userland to reload $v0 was something ugly that Linux inherited > from god knows where and I'm happy to have gotten rid of that. So basically my whole question/concern is irrelevant to anything but pre-2.6.36 kernels, and all of those preserve $25, so it would have been safe to keep using $25. Thankfully I already found another solution using an "ir" constraint and "addu $2,$0,%2"; this assembles to "li" whenever the compiler can do constant propagation, and if CP fails or the syscall number is not constant, it allocates a register (either an unused argument register or a call-preserved register since all the others are already in the clobberlist or used as inputs). > > The code I'm looking at seems to match what you cited from glibc. > > > > > >These are > > > >requirements beyond the normal function call convention (which does > > > >not require the callee preserve the values of r4-r7). > > > > > > I would assume these are clobbered (from glibc sources > > > ports/sysdeps/unix/sysv/linux/mips/mips64/n64/sysdep.h): > > > > > > "$1", "$3", "$10", "$11", "$12", "$13", "$14", "$15", "$24", "$25", > > > "hi", "lo" > > Which is correct but also means that the _syscallX() macros that were in > up to 2.6.19 were broken; the were lacking clobbers for > $25, $hi and $lo. Unfortunately these macros were copied into many > libraries and applications. I don't think the compiler will try to cache anything in $25 itself anyway. Normally it seems to only get used for its role in the function call ABI. But yes, in theory this is rather problematic, moreso that my issue of using $25 to restore $2 on restart. Rich From dalias@aerifal.cx Tue Sep 11 15:42:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 15:42:14 +0200 (CEST) Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:52723 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903494Ab2IKNmE (ORCPT ); Tue, 11 Sep 2012 15:42:04 +0200 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1TBQlv-0007AB-00 for linux-mips@linux-mips.org; Tue, 11 Sep 2012 13:44:59 +0000 Date: Tue, 11 Sep 2012 09:44:59 -0400 To: linux-mips@linux-mips.org Subject: Re: Is r25 saved across syscalls? Message-ID: <20120911134459.GS27715@brightrain.aerifal.cx> References: <20120909193008.GA15157@brightrain.aerifal.cx> <20120911081256.GD24448@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120911081256.GD24448@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) From: Rich Felker X-archive-position: 34468 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dalias@aerifal.cx Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2799 Lines: 62 On Tue, Sep 11, 2012 at 10:12:56AM +0200, Ralf Baechle wrote: > On Sun, Sep 09, 2012 at 03:30:08PM -0400, Rich Felker wrote: > > > Hi all, > > The kernel syscall entry/exit code seems to always save and restore > > r25. Is this stable/documented behavior I can rely on? If there's a > > reason it _needs_ to be preserved, knowing that would help convince me > > it's safe to assume it will always be done. The intended usage is to > > be able to make syscalls (where the syscall # is not a constant that > > could be loaded with lwi) without a stack frame, as in "move $2,$25 ; > > syscall". > > Since there is no place where the syscall interface is documented other > than in the code itself, I've written a new wiki article > > http://www.linux-mips.org/wiki/Syscall > > as start. It's still lacking on the more obscure points but it at least > should have have answered your question, had it already existed when you > asked. Thanks! Some comments... In the table, $a0 ... $a2/$a7 except $a3 is unclear. Do you mean to say $a0 ... $a2 on o32 and also $a4 ... $a7 on all other ABIs? If so I think it would make sense to put those ranges as separate lines in the table, so it's clear that the second group are not preserved on o32 (if they were, they would also have solved my problem). As for $a3 4th syscall argument $a3 set to 0/1 for success/error Does the kernel guarantee 0/1, or is it 0/nonzero? This could matter to asm programmers using the syscall ABI who want to do bit twiddling. Syscall restarting is a special case where $v0, $v1 and $a3 will stay unmodified. Even the program counter will stay unmodified so the same syscall will be executed again. This is something that does not matter to application programmers but may become visible in debuggers. Syscall restarting is something that is used internally by the kernel, for example when during a large read(2) syscall the kernel receives a signal. The way syscall restarting works does matter to userspace, although only to very low-level code. In musl (http://www.etalabs.net/musl), the syscall routine for cancellation-point syscalls uses labels in the asm before checking the cancellation flag and immediately after the syscall instruction so that the signal handler that processes thread cancellation can examine the saved program counter in the ucontext_t it receives and determine whether the interrupted code is at a cancellable syscall or not, with no race conditions. The glibc/NPTL approach of wrapping a plain syscall with code to change to async cancellation mode and back has extremely dangerous race conditions, and my approach in musl of examining the program counter and comparing it against asm labels is the only solution I've seen that's race-free. Rich From hauke@hauke-m.de Tue Sep 11 17:15:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 17:15:35 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:38209 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903500Ab2IKPP2 (ORCPT ); Tue, 11 Sep 2012 17:15:28 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 20E098F62; Tue, 11 Sep 2012 17:15:22 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id l4Db6bGKhtG0; Tue, 11 Sep 2012 17:15:17 +0200 (CEST) Received: from hauke.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id C0F7587B9; Tue, 11 Sep 2012 17:15:16 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org, john@phrozen.org Cc: linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, florian@openwrt.org, zajec5@gmail.com, Hauke Mehrtens Subject: [PATCH v4 0/3] MIPS: BCM47xx: use gpiolib Date: Tue, 11 Sep 2012 17:15:07 +0200 Message-Id: <1347376511-20953-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 34469 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1381 Lines: 38 The original code implemented the GPIO interface itself and this caused some problems. With this patch gpiolib is used. This is based on mips/master. This should go through linux-mips, John W. Linville approved that for the bcma and ssb changes normally maintained in wireless-testing. v4: - remove extra BCMA_DRIVER_GPIO option and inline the spinlocks in bcma/driver_chipcommon.c. v3: - add missing break after setting bcm47xx_gpio_count in bcm47xx_gpio_init() v2: - use use gpio_chip.to_irq() instead of directly declare gpio_to_irq Hauke Mehrtens (3): ssb: add function to return number of gpio lines bcma: add GPIO driver for SoCs MIPS: BCM47xx: rewrite GPIO handling and use gpiolib arch/mips/Kconfig | 2 +- arch/mips/bcm47xx/gpio.c | 212 ++++++++++++++++++++------ arch/mips/bcm47xx/setup.c | 2 + arch/mips/bcm47xx/wgt634u.c | 7 + arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 2 + arch/mips/include/asm/mach-bcm47xx/gpio.h | 148 +++--------------- drivers/bcma/driver_chipcommon.c | 61 +++++++- drivers/ssb/embedded.c | 12 ++ include/linux/bcma/bcma_driver_chipcommon.h | 24 ++- include/linux/ssb/ssb_embedded.h | 4 + 10 files changed, 287 insertions(+), 187 deletions(-) -- 1.7.9.5 From hauke@hauke-m.de Tue Sep 11 17:15:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 17:16:01 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:38221 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903498Ab2IKPP3 (ORCPT ); Tue, 11 Sep 2012 17:15:29 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id B51E087B9; Tue, 11 Sep 2012 17:15:23 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6zrKAiLuDJt8; Tue, 11 Sep 2012 17:15:18 +0200 (CEST) Received: from hauke.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id B96F08880; Tue, 11 Sep 2012 17:15:17 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org, john@phrozen.org Cc: linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, florian@openwrt.org, zajec5@gmail.com, Hauke Mehrtens , Michael Buesch Subject: [PATCH v4 1/3] ssb: add function to return number of gpio lines Date: Tue, 11 Sep 2012 17:15:08 +0200 Message-Id: <1347376511-20953-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1347376511-20953-1-git-send-email-hauke@hauke-m.de> References: <1347376511-20953-1-git-send-email-hauke@hauke-m.de> X-archive-position: 34470 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1723 Lines: 54 CC: Michael Buesch Signed-off-by: Hauke Mehrtens --- drivers/ssb/embedded.c | 12 ++++++++++++ include/linux/ssb/ssb_embedded.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/ssb/embedded.c b/drivers/ssb/embedded.c index 9ef124f..078007c 100644 --- a/drivers/ssb/embedded.c +++ b/drivers/ssb/embedded.c @@ -136,6 +136,18 @@ u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value) } EXPORT_SYMBOL(ssb_gpio_polarity); +int ssb_gpio_count(struct ssb_bus *bus) +{ + if (ssb_chipco_available(&bus->chipco)) + return SSB_GPIO_CHIPCO_LINES; + else if (ssb_extif_available(&bus->extif)) + return SSB_GPIO_EXTIF_LINES; + else + SSB_WARN_ON(1); + return 0; +} +EXPORT_SYMBOL(ssb_gpio_count); + #ifdef CONFIG_SSB_DRIVER_GIGE static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data) { diff --git a/include/linux/ssb/ssb_embedded.h b/include/linux/ssb/ssb_embedded.h index 8d8dedf..f1618d2 100644 --- a/include/linux/ssb/ssb_embedded.h +++ b/include/linux/ssb/ssb_embedded.h @@ -7,6 +7,9 @@ extern int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks); +#define SSB_GPIO_EXTIF_LINES 5 +#define SSB_GPIO_CHIPCO_LINES 16 + /* Generic GPIO API */ u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask); u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value); @@ -14,5 +17,6 @@ u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value); u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value); u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value); u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value); +int ssb_gpio_count(struct ssb_bus *bus); #endif /* LINUX_SSB_EMBEDDED_H_ */ -- 1.7.9.5 From hauke@hauke-m.de Tue Sep 11 17:15:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 17:16:28 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:38228 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903502Ab2IKPPj (ORCPT ); Tue, 11 Sep 2012 17:15:39 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id EFB988880; Tue, 11 Sep 2012 17:15:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BqQLDx7ABtGp; Tue, 11 Sep 2012 17:15:22 +0200 (CEST) Received: from hauke.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id BB9298E1C; Tue, 11 Sep 2012 17:15:18 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org, john@phrozen.org Cc: linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, florian@openwrt.org, zajec5@gmail.com, Hauke Mehrtens Subject: [PATCH v4 2/3] bcma: add GPIO driver for SoCs Date: Tue, 11 Sep 2012 17:15:09 +0200 Message-Id: <1347376511-20953-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1347376511-20953-1-git-send-email-hauke@hauke-m.de> References: <1347376511-20953-1-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 34471 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5247 Lines: 158 The GPIOs are access through some registers in the chip common core. We need locking around these GPIO accesses, all GPIOs are accessed through the same registers and parallel writes will cause problems. CC: RafaÅ‚ MiÅ‚ecki Signed-off-by: Hauke Mehrtens --- drivers/bcma/driver_chipcommon.c | 61 ++++++++++++++++++++++++--- include/linux/bcma/bcma_driver_chipcommon.h | 24 ++++++++--- 2 files changed, 73 insertions(+), 12 deletions(-) diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c index a4c3ebc..7a7baf1 100644 --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c @@ -57,6 +57,8 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } + spin_lock_init(&cc->gpio_lock); + cc->setup_done = true; } @@ -79,34 +81,81 @@ u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) { - return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_in); u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_intmask); u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_polarity); #ifdef CONFIG_BCMA_DRIVER_MIPS void bcma_chipco_serial_init(struct bcma_drv_cc *cc) diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h index d323a4b..7054d0d 100644 --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h @@ -454,6 +454,9 @@ struct bcma_drv_cc { int nr_serial_ports; struct bcma_serial_port serial_ports[4]; #endif /* CONFIG_BCMA_DRIVER_MIPS */ + + /* Lock for GPIO register access. */ + spinlock_t gpio_lock; }; /* Register access */ @@ -483,13 +486,22 @@ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); +#define BCMA_CC_GPIO_LINES 16 + /* Chipcommon GPIO pin access. */ -u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); -u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); -u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); -u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); -u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); -u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); +extern u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); +extern u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); +extern u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); +extern u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, + u32 value); +extern u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, + u32 value); +extern u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, + u32 value); +static inline int bcma_chipco_gpio_count(void) +{ + return BCMA_CC_GPIO_LINES; +} /* PMU support */ extern void bcma_pmu_init(struct bcma_drv_cc *cc); -- 1.7.9.5 From hauke@hauke-m.de Tue Sep 11 17:15:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 17:16:54 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:38238 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903504Ab2IKPPo (ORCPT ); Tue, 11 Sep 2012 17:15:44 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 8960A8F63; Tue, 11 Sep 2012 17:15:38 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CwUbiEJLxQAX; Tue, 11 Sep 2012 17:15:24 +0200 (CEST) Received: from hauke.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 623A28F61; Tue, 11 Sep 2012 17:15:20 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org, john@phrozen.org Cc: linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, florian@openwrt.org, zajec5@gmail.com, Hauke Mehrtens Subject: [PATCH v4 3/3] MIPS: BCM47xx: rewrite GPIO handling and use gpiolib Date: Tue, 11 Sep 2012 17:15:10 +0200 Message-Id: <1347376511-20953-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1347376511-20953-1-git-send-email-hauke@hauke-m.de> References: <1347376511-20953-1-git-send-email-hauke@hauke-m.de> X-archive-position: 34472 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 14562 Lines: 528 The original implementation implemented functions like gpio_request() itself, but it missed some new functions added to the GPIO interface. This caused compile problems for some drivers using some of the special request methods which where not implemented. Now it uses gpiolib and this implements all the request methods needed. The raw GPIO register access methods like bcm47xx_gpio_in() are exported, because some special drivers for this target, not yet in mainline, need them. Signed-off-by: Hauke Mehrtens --- arch/mips/Kconfig | 2 +- arch/mips/bcm47xx/gpio.c | 212 ++++++++++++++++++++------ arch/mips/bcm47xx/setup.c | 2 + arch/mips/bcm47xx/wgt634u.c | 7 + arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 2 + arch/mips/include/asm/mach-bcm47xx/gpio.h | 148 +++--------------- 6 files changed, 198 insertions(+), 175 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index faf6528..fa171a3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -101,6 +101,7 @@ config ATH79 config BCM47XX bool "Broadcom BCM47XX based boards" + select ARCH_REQUIRE_GPIOLIB select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT @@ -108,7 +109,6 @@ config BCM47XX select IRQ_CPU select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_GPIO select SYS_HAS_EARLY_PRINTK select CFE help diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c index 5ebdf62..415cc38 100644 --- a/arch/mips/bcm47xx/gpio.c +++ b/arch/mips/bcm47xx/gpio.c @@ -4,83 +4,154 @@ * for more details. * * Copyright (C) 2007 Aurelien Jarno + * Copyright (C) 2012 Hauke Mehrtens + * + * Parts of this file are based on Atheros AR71XX/AR724X/AR913X GPIO */ #include +#include #include -#include -#include -#include -#include +#include +#include + +#include -#if (BCM47XX_CHIPCO_GPIO_LINES > BCM47XX_EXTIF_GPIO_LINES) -static DECLARE_BITMAP(gpio_in_use, BCM47XX_CHIPCO_GPIO_LINES); -#else -static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES); -#endif -int gpio_request(unsigned gpio, const char *tag) +static unsigned long bcm47xx_gpio_count; + +/* low level BCM47xx gpio api */ +u32 bcm47xx_gpio_in(u32 mask) { switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: - if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && - ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) - return -EINVAL; - - if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && - ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) - return -EINVAL; - - if (test_and_set_bit(gpio, gpio_in_use)) - return -EBUSY; - - return 0; + return ssb_gpio_in(&bcm47xx_bus.ssb, mask); #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: - if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) - return -EINVAL; - - if (test_and_set_bit(gpio, gpio_in_use)) - return -EBUSY; + return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, mask); +#endif + } + return -EINVAL; +} +EXPORT_SYMBOL(bcm47xx_gpio_in); - return 0; +u32 bcm47xx_gpio_out(u32 mask, u32 value) +{ + switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value); +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask, + value); #endif } return -EINVAL; } -EXPORT_SYMBOL(gpio_request); +EXPORT_SYMBOL(bcm47xx_gpio_out); -void gpio_free(unsigned gpio) +u32 bcm47xx_gpio_outen(u32 mask, u32 value) { switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: - if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && - ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) - return; + return ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value); +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + return bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, + mask, value); +#endif + } + return -EINVAL; +} +EXPORT_SYMBOL(bcm47xx_gpio_outen); - if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && - ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) - return; +u32 bcm47xx_gpio_control(u32 mask, u32 value) +{ + switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value); +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc, + mask, value); +#endif + } + return -EINVAL; +} +EXPORT_SYMBOL(bcm47xx_gpio_control); - clear_bit(gpio, gpio_in_use); - return; +u32 bcm47xx_gpio_intmask(u32 mask, u32 value) +{ + switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value); #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: - if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) - return; + return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, + mask, value); +#endif + } + return -EINVAL; +} +EXPORT_SYMBOL(bcm47xx_gpio_intmask); - clear_bit(gpio, gpio_in_use); - return; +u32 bcm47xx_gpio_polarity(u32 mask, u32 value) +{ + switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value); +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, + mask, value); #endif } + return -EINVAL; +} +EXPORT_SYMBOL(bcm47xx_gpio_polarity); + + +static int bcm47xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio) +{ + return bcm47xx_gpio_in(1 << gpio); +} + +static void bcm47xx_gpio_set_value(struct gpio_chip *chip, + unsigned gpio, int value) +{ + bcm47xx_gpio_out(1 << gpio, value ? 1 << gpio : 0); +} + +static int bcm47xx_gpio_direction_input(struct gpio_chip *chip, + unsigned gpio) +{ + bcm47xx_gpio_outen(1 << gpio, 0); + return 0; +} + +static int bcm47xx_gpio_direction_output(struct gpio_chip *chip, + unsigned gpio, int value) +{ + /* first set the gpio out value */ + bcm47xx_gpio_out(1 << gpio, value ? 1 << gpio : 0); + /* then set the gpio mode */ + bcm47xx_gpio_outen(1 << gpio, 1 << gpio); + return 0; } -EXPORT_SYMBOL(gpio_free); -int gpio_to_irq(unsigned gpio) +static int bcm47xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) { switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB @@ -99,4 +170,55 @@ int gpio_to_irq(unsigned gpio) } return -EINVAL; } -EXPORT_SYMBOL_GPL(gpio_to_irq); + +static struct gpio_chip bcm47xx_gpio_chip = { + .label = "bcm47xx", + .get = bcm47xx_gpio_get_value, + .set = bcm47xx_gpio_set_value, + .direction_input = bcm47xx_gpio_direction_input, + .direction_output = bcm47xx_gpio_direction_output, + .to_irq = bcm47xx_gpio_to_irq, + .base = 0, +}; + +void __init bcm47xx_gpio_init(void) +{ + int err; + + switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + bcm47xx_gpio_count = ssb_gpio_count(&bcm47xx_bus.ssb); + break; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcm47xx_gpio_count = bcma_chipco_gpio_count(); + break; +#endif + } + + bcm47xx_gpio_chip.ngpio = bcm47xx_gpio_count; + + err = gpiochip_add(&bcm47xx_gpio_chip); + if (err) + panic("cannot add BCM47xx GPIO chip, error=%d", err); +} + +int gpio_get_value(unsigned gpio) +{ + if (gpio < bcm47xx_gpio_count) + return bcm47xx_gpio_in(1 << gpio); + + return __gpio_get_value(gpio); +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned gpio, int value) +{ + if (gpio < bcm47xx_gpio_count) + bcm47xx_gpio_out(1 << gpio, value ? 1 << gpio : 0); + else + __gpio_set_value(gpio, value); +} +EXPORT_SYMBOL(gpio_set_value); diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 95bf4d7..2936532 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -220,6 +220,8 @@ void __init plat_mem_setup(void) _machine_restart = bcm47xx_machine_restart; _machine_halt = bcm47xx_machine_halt; pm_power_off = bcm47xx_machine_halt; + + bcm47xx_gpio_init(); } static int __init bcm47xx_register_bus_complete(void) diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c index e9f9ec8..fd1066e 100644 --- a/arch/mips/bcm47xx/wgt634u.c +++ b/arch/mips/bcm47xx/wgt634u.c @@ -133,6 +133,7 @@ static int __init wgt634u_init(void) * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx. */ u8 *et0mac; + int err; if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB) return -ENODEV; @@ -146,6 +147,12 @@ static int __init wgt634u_init(void) printk(KERN_INFO "WGT634U machine detected.\n"); + err = gpio_request(WGT634U_GPIO_RESET, "reset-buton"); + if (err) { + printk(KERN_INFO "Can not register gpio for reset button\n"); + return 0; + } + if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET), gpio_interrupt, IRQF_SHARED, "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) { diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h index 26fdaf4..1bd5560 100644 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h @@ -56,4 +56,6 @@ void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo, const char *prefix); #endif +void bcm47xx_gpio_init(void); + #endif /* __ASM_BCM47XX_H */ diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h index 2ef17e8..27a5632 100644 --- a/arch/mips/include/asm/mach-bcm47xx/gpio.h +++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h @@ -4,152 +4,42 @@ * for more details. * * Copyright (C) 2007 Aurelien Jarno + * Copyright (C) 2012 Hauke Mehrtens */ #ifndef __BCM47XX_GPIO_H #define __BCM47XX_GPIO_H -#include -#include -#include +#define ARCH_NR_GPIOS 64 +#include -#define BCM47XX_EXTIF_GPIO_LINES 5 -#define BCM47XX_CHIPCO_GPIO_LINES 16 +/* low level BCM47xx gpio api */ +u32 bcm47xx_gpio_in(u32 mask); +u32 bcm47xx_gpio_out(u32 mask, u32 value); +u32 bcm47xx_gpio_outen(u32 mask, u32 value); +u32 bcm47xx_gpio_control(u32 mask, u32 value); +u32 bcm47xx_gpio_intmask(u32 mask, u32 value); +u32 bcm47xx_gpio_polarity(u32 mask, u32 value); -extern int gpio_request(unsigned gpio, const char *label); -extern void gpio_free(unsigned gpio); -extern int gpio_to_irq(unsigned gpio); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); -static inline int gpio_get_value(unsigned gpio) +static inline void gpio_intmask(unsigned gpio, int value) { - switch (bcm47xx_bus_type) { -#ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio); -#endif -#ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: - return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, - 1 << gpio); -#endif - } - return -EINVAL; -} - -#define gpio_get_value_cansleep gpio_get_value - -static inline void gpio_set_value(unsigned gpio, int value) -{ - switch (bcm47xx_bus_type) { -#ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio, - value ? 1 << gpio : 0); - return; -#endif -#ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: - bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, - value ? 1 << gpio : 0); - return; -#endif - } -} - -#define gpio_set_value_cansleep gpio_set_value - -static inline int gpio_cansleep(unsigned gpio) -{ - return 0; -} - -static inline int gpio_is_valid(unsigned gpio) -{ - return gpio < (BCM47XX_EXTIF_GPIO_LINES + BCM47XX_CHIPCO_GPIO_LINES); -} - - -static inline int gpio_direction_input(unsigned gpio) -{ - switch (bcm47xx_bus_type) { -#ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0); - return 0; -#endif -#ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: - bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, - 0); - return 0; -#endif - } - return -EINVAL; + bcm47xx_gpio_intmask(1 << gpio, value ? 1 << gpio : 0); } -static inline int gpio_direction_output(unsigned gpio, int value) +static inline void gpio_polarity(unsigned gpio, int value) { - switch (bcm47xx_bus_type) { -#ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - /* first set the gpio out value */ - ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio, - value ? 1 << gpio : 0); - /* then set the gpio mode */ - ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio); - return 0; -#endif -#ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: - /* first set the gpio out value */ - bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, - value ? 1 << gpio : 0); - /* then set the gpio mode */ - bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, - 1 << gpio); - return 0; -#endif - } - return -EINVAL; -} - -static inline int gpio_intmask(unsigned gpio, int value) -{ - switch (bcm47xx_bus_type) { -#ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio, - value ? 1 << gpio : 0); - return 0; -#endif -#ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: - bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, - 1 << gpio, value ? 1 << gpio : 0); - return 0; -#endif - } - return -EINVAL; + bcm47xx_gpio_polarity(1 << gpio, value ? 1 << gpio : 0); } -static inline int gpio_polarity(unsigned gpio, int value) +static inline int irq_to_gpio(int gpio) { - switch (bcm47xx_bus_type) { -#ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio, - value ? 1 << gpio : 0); - return 0; -#endif -#ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: - bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, - 1 << gpio, value ? 1 << gpio : 0); - return 0; -#endif - } return -EINVAL; } +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq #endif /* __BCM47XX_GPIO_H */ -- 1.7.9.5 From lars@metafoo.de Tue Sep 11 19:54:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 19:54:30 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:37798 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903302Ab2IKRyX (ORCPT ); Tue, 11 Sep 2012 19:54:23 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 9C19984E; Tue, 11 Sep 2012 19:54:16 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id z+VbseKDISjf; Tue, 11 Sep 2012 19:54:16 +0200 (CEST) Received: from [192.168.178.21] (ppp-188-174-8-103.dynamic.mnet-online.de [188.174.8.103]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 4259184B; Tue, 11 Sep 2012 19:54:04 +0200 (CEST) Message-ID: <504F7AC8.6070405@metafoo.de> Date: Tue, 11 Sep 2012 19:54:16 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20120724 Icedove/3.0.11 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH v2 3/3] pwm: Add Ingenic JZ4740 support References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> <1347278719-15276-4-git-send-email-thierry.reding@avionic-design.de> <504E60F4.9010309@metafoo.de> <20120911050211.GA23771@avionic-0098.mockup.avionic-design.de> In-Reply-To: <20120911050211.GA23771@avionic-0098.mockup.avionic-design.de> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34473 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1055 Lines: 25 On 09/11/2012 07:02 AM, Thierry Reding wrote: > On Mon, Sep 10, 2012 at 11:51:48PM +0200, Lars-Peter Clausen wrote: >> On 09/10/2012 02:05 PM, Thierry Reding wrote: >>> This commit moves the driver to drivers/pwm and converts it to the new >>> PWM framework. >>> >>> Signed-off-by: Thierry Reding >> >> Seems to work, thanks a lot. This one and patch 2: >> >> Acked-by: Lars-Peter Clausen >> Tested-by: Lars-Peter Clausen >> >> But I noticed a different problem. Some drivers using the pwm API depend on >> HAVE_PWM (e.g. the pwm beeper driver), but the generic PWM framework does not >> select HAVE_PWM, so I couldn't select the pwm beeper driver. Imo the generic >> PWM framework should select HAVE_PWM > > Does it also work if you add || PWM to the PWM beeper driver's depends? Should work, but to select HAVE_PWM would in my opinion have been cleaner. But since the custom implementations of the PWM API should be gone soon anyway it probably does not matter that much. - Lars From lars@metafoo.de Tue Sep 11 19:56:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Sep 2012 19:56:27 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:38034 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903488Ab2IKR4X (ORCPT ); Tue, 11 Sep 2012 19:56:23 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 70E2985D; Tue, 11 Sep 2012 19:56:18 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id gcJYvVfP6mTm; Tue, 11 Sep 2012 19:56:17 +0200 (CEST) Received: from [192.168.178.21] (ppp-188-174-8-103.dynamic.mnet-online.de [188.174.8.103]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 4795785C; Tue, 11 Sep 2012 19:56:17 +0200 (CEST) Message-ID: <504F7B4D.3030602@metafoo.de> Date: Tue, 11 Sep 2012 19:56:29 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20120724 Icedove/3.0.11 MIME-Version: 1.0 To: Thierry Reding CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH v2 0/3] MIPS: JZ4740: Move PWM driver to PWM framework References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> <504E0542.8020309@metafoo.de> <20120910173056.GA31611@avionic-0098.mockup.avionic-design.de> In-Reply-To: <20120910173056.GA31611@avionic-0098.mockup.avionic-design.de> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34474 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 779 Lines: 24 On 09/10/2012 07:30 PM, Thierry Reding wrote: > On Mon, Sep 10, 2012 at 05:20:34PM +0200, Lars-Peter Clausen wrote: >> On 09/10/2012 02:05 PM, Thierry Reding wrote: >>> Hi, >>> >> >> [...] > >> Patch 1 should go through the MIPS tree, but I still can't see why the issue >> should occur nor does it happen for anybody else except for you. Instead of >> moving the content over to the public irq.h I'd rather like to see the >> private irq.h being renamed. > > If we can solve this some other way I'm all for it. Maybe you can share > the defconfig or .config that you use so I can test under the same > conditions. > > Thierry This is the config I'm using: http://projects.qi-hardware.com/index.php/p/qi-kernel/source/tree/jz-3.4/arch/mips/configs/qi_lb60_defconfig - Lars From kirill.shutemov@linux.intel.com Wed Sep 12 12:09:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 12:09:34 +0200 (CEST) Received: from mga03.intel.com ([143.182.124.21]:13805 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903325Ab2ILKJ3 (ORCPT ); Wed, 12 Sep 2012 12:09:29 +0200 Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga101.ch.intel.com with ESMTP; 12 Sep 2012 03:09:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.80,408,1344236400"; d="asc'?scan'208";a="144142806" Received: from blue.fi.intel.com ([10.237.72.50]) by AZSMGA002.ch.intel.com with ESMTP; 12 Sep 2012 03:09:15 -0700 Received: by blue.fi.intel.com (Postfix, from userid 1000) id ABE50E0073; Wed, 12 Sep 2012 13:09:41 +0300 (EEST) Date: Wed, 12 Sep 2012 13:09:41 +0300 From: "Kirill A. Shutemov" To: linux-mm@kvack.org Cc: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Andi Kleen , Tim Chen , Alex Shi , Jan Beulich , Robert Richter , Andy Lutomirski , Andrew Morton , Andrea Arcangeli , Johannes Weiner , Hugh Dickins , KAMEZAWA Hiroyuki , Mel Gorman , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org Subject: Re: [PATCH v4 0/8] Avoid cache trashing on clearing huge/gigantic page Message-ID: <20120912100941.GA26582@otc-wbsnb-06> References: <1345470757-12005-1-git-send-email-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="9amGYk9869ThD9tj" Content-Disposition: inline In-Reply-To: <1345470757-12005-1-git-send-email-kirill.shutemov@linux.intel.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34475 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kirill.shutemov@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1162 Lines: 36 --9amGYk9869ThD9tj Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, Any feedback? --=20 Kirill A. Shutemov --9amGYk9869ThD9tj Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBAgAGBQJQUF9lAAoJEAd+omnVudOMqvgP/A9oBD+NU+NuFlm6b32IkUIR 2jlEFuSzAp3dAS+aQWVcjLz88pNu7ZjD2m9dTWwVr03UKSlfc/UUcHctWmjrhj+B trkuGQ7qVadFTaunqj1z1NZGCrXwGTdw2f+soGtJ+cmwmOqxrqyDJlbJyyOfpiJe iYyOU522V7Rc/cnyjY+OxOkaHDBy3RIpo6DhVpSC4Ws6wH6bkuiM2ZYAx+fiRDnj Ii60Iel88rjQ0uSeTQ+Jznu16czL4q4bRB9IeT24jUQRgTp7kYKNyjzgy4/zrjOL Dlkck9VihPQhZ3QxAjqcxQQCwclB0GctZDFUIrP97+REFlvd3u7yVzgxpeVuqtsz K6aXJDcPqfTGyEe0OgOGVb+M6ylvIvsXjNXkym85PTCZNnw9smem1S2HY5689bH+ ELP9ruYagr1yb+LTX3CQmFuvmoCyuzES/tgw97AJbFP3prkt0K44WhBsJCaflJjl efJg6qWTwTrIK8hq0ulcWnwa2oi9zbNwV2SVgDdVQmOfwtzKAp69ijF0Rd4lwpZf 47ch8oZDVcn8Fv2nhv9FrFr8JiAZ07eIwzeAGiSfpIRpcKXoKUp8y950i++mlxNq xoGPDY1odKCKoVsbwYtW/E9l/tmUhTljqExfn9pzcHqMz4YUMGob7xnZOP0ljY5y ikNOztWkQPhLD2Cj1nLx =p8ME -----END PGP SIGNATURE----- --9amGYk9869ThD9tj-- From thierry.reding@avionic-design.de Wed Sep 12 17:02:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 17:02:31 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:63015 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903347Ab2ILPCZ (ORCPT ); Wed, 12 Sep 2012 17:02:25 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu3) with ESMTP (Nemesis) id 0MITil-1TFwmu0ZEV-0049Fn; Wed, 12 Sep 2012 17:02:15 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 710B72A28318; Wed, 12 Sep 2012 17:02:14 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7L1C-Zr5Ezaa; Wed, 12 Sep 2012 17:02:12 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id B9A722A2830F; Wed, 12 Sep 2012 17:02:11 +0200 (CEST) Date: Wed, 12 Sep 2012 17:02:10 +0200 From: Thierry Reding To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Maarten ter Huurne Subject: Re: [PATCH v2 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Message-ID: <20120912150210.GA20961@avionic-0098.mockup.avionic-design.de> References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> <504E0542.8020309@metafoo.de> <20120910173056.GA31611@avionic-0098.mockup.avionic-design.de> <504F7B4D.3030602@metafoo.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="ZGiS0Q5IWpPtfppv" Content-Disposition: inline In-Reply-To: <504F7B4D.3030602@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:+RgVVIBL7qWruvdn/em8uZQcQo6zGZLlZIB7AeqE8Aq E1YwlznOeyS9TBRrckMempIamMGmmdBHIba5cyRoSfhzg9Mhu7 mfxFBsZPqkJOEJeQeB6IEIhOlSi9Mi7B2Bgi2mKdS93VSc2eeJ TPIyXhwHxgVdimGZ8l2BEwIHUO9euySuHh7Wwswz3oQb1f1Mk0 l8V1cN4G7Nyl1eKR6wdw0HAAKMijRq00Jfra3xywxPkH/MxJkA 6A/4WlnFuoETSoDpOQjnDVA8aG3af2N1kvKS0YC0tmpugu1Bzs 3dWFBm1t4pieDvz469QDCTGmZMpDq/289/uQ5atJQOARFA9MUh eFNSIqdwYXOOnaiB0ITFJN73xrdocTKWtO/YqnCmxq4VYlGsXJ /k23aDGapXxPmdR2FmKL2J6VekiD9oEeb4= X-archive-position: 34476 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 12577 Lines: 259 --ZGiS0Q5IWpPtfppv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Sep 11, 2012 at 07:56:29PM +0200, Lars-Peter Clausen wrote: > On 09/10/2012 07:30 PM, Thierry Reding wrote: > > On Mon, Sep 10, 2012 at 05:20:34PM +0200, Lars-Peter Clausen wrote: > >> On 09/10/2012 02:05 PM, Thierry Reding wrote: > >>> Hi, > >>> > >> > >> [...] > >=20 > >> Patch 1 should go through the MIPS tree, but I still can't see why the= issue > >> should occur nor does it happen for anybody else except for you. Inste= ad of > >> moving the content over to the public irq.h I'd rather like to see the > >> private irq.h being renamed. > >=20 > > If we can solve this some other way I'm all for it. Maybe you can share > > the defconfig or .config that you use so I can test under the same > > conditions. > >=20 > > Thierry >=20 > This is the config I'm using: > http://projects.qi-hardware.com/index.php/p/qi-kernel/source/tree/jz-3.4/= arch/mips/configs/qi_lb60_defconfig I can still reproduce the error with that configuration. Perhaps related to the toolchain? I use a vanilla gcc 4.7.1 cross-compiler. This is all on top of Linux v3.6-rc2. Here's the complete error message: $ nice make ARCH=3Dmips CROSS_COMPILE=3D/home/thierry.reding/pbs-stage1/bin= /mips-linux-gnu- O=3Dbuild/jz4740 Using /home/thierry.reding/src/kernel/linux-pwm.git as source for kernel GEN /home/thierry.reding/src/kernel/linux-pwm.git/build/jz4740/Makefi= le CHK include/linux/version.h CHK include/generated/utsrelease.h CALL /home/thierry.reding/src/kernel/linux-pwm.git/scripts/checksyscal= ls.sh CHK include/generated/compile.h CC arch/mips/jz4740/irq.o In file included from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/irq.h:18:0, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/irq.h:27, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /asm-generic/hardirq.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/hardirq.h:16, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/hardirq.h:7, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/interrupt.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/jz4740/irq.c:19: /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:20:39:= error: 'struct irq_data' declared inside parameter list [-Werror] /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:20:39:= error: its scope is only this definition or declaration, which is probably= not what you want [-Werror] /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:21:38:= error: 'struct irq_data' declared inside parameter list [-Werror] In file included from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/irq.h:356:0, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /asm-generic/hardirq.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/hardirq.h:16, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/hardirq.h:7, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/interrupt.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/jz4740/irq.c:19: /home/thierry.reding/src/kernel/linux-pwm.git/include/linux/irqdesc.h:75:33= : error: 'NR_IRQS' undeclared here (not in a function) /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c: In fu= nction 'jz4740_cascade': /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:49:39:= error: 'JZ4740_IRQ_BASE' undeclared (first use in this function) /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:49:39:= note: each undeclared identifier is reported only once for each function i= t appears in /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c: At to= p level: /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:62:6: = error: conflicting types for 'jz4740_irq_suspend' In file included from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/irq.h:18:0, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/irq.h:27, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /asm-generic/hardirq.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/hardirq.h:16, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/hardirq.h:7, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/interrupt.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/jz4740/irq.c:19: /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:20:13:= note: previous declaration of 'jz4740_irq_suspend' was here /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:68:6: = error: conflicting types for 'jz4740_irq_resume' In file included from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/irq.h:18:0, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/irq.h:27, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /asm-generic/hardirq.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/hardirq.h:16, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/hardirq.h:7, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/interrupt.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/jz4740/irq.c:19: /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:21:13:= note: previous declaration of 'jz4740_irq_resume' was here /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c: In fu= nction 'arch_init_irq': /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:91:41:= error: 'JZ4740_IRQ_BASE' undeclared (first use in this function) cc1: all warnings being treated as errors make[3]: *** [arch/mips/jz4740/irq.o] Error 1 make[2]: *** [arch/mips/jz4740] Error 2 make[1]: *** [arch/mips] Error 2 make: *** [sub-make] Error 2 Using /home/thierry.reding/src/kernel/linux-pwm.git as source for kernel GEN /home/thierry.reding/src/kernel/linux-pwm.git/build/jz4740/Makefi= le CHK include/linux/version.h CHK include/generated/utsrelease.h CALL /home/thierry.reding/src/kernel/linux-pwm.git/scripts/checksyscal= ls.sh CHK include/generated/compile.h CC arch/mips/jz4740/irq.o In file included from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/irq.h:18:0, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/irq.h:27, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /asm-generic/hardirq.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/hardirq.h:16, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/hardirq.h:7, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/interrupt.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/jz4740/irq.c:19: /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:20:39:= error: 'struct irq_data' declared inside parameter list [-Werror] /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:20:39:= error: its scope is only this definition or declaration, which is probably= not what you want [-Werror] /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:21:38:= error: 'struct irq_data' declared inside parameter list [-Werror] In file included from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/irq.h:356:0, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /asm-generic/hardirq.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/hardirq.h:16, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/hardirq.h:7, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/interrupt.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/jz4740/irq.c:19: /home/thierry.reding/src/kernel/linux-pwm.git/include/linux/irqdesc.h:75:33= : error: 'NR_IRQS' undeclared here (not in a function) /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c: In fu= nction 'jz4740_cascade': /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:49:39:= error: 'JZ4740_IRQ_BASE' undeclared (first use in this function) /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:49:39:= note: each undeclared identifier is reported only once for each function i= t appears in /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c: At to= p level: /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:62:6: = error: conflicting types for 'jz4740_irq_suspend' In file included from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/irq.h:18:0, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/irq.h:27, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /asm-generic/hardirq.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/hardirq.h:16, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/hardirq.h:7, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/interrupt.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/jz4740/irq.c:19: /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:20:13:= note: previous declaration of 'jz4740_irq_suspend' was here /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:68:6: = error: conflicting types for 'jz4740_irq_resume' In file included from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/irq.h:18:0, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/irq.h:27, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /asm-generic/hardirq.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/include/asm/hardirq.h:16, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/hardirq.h:7, from /home/thierry.reding/src/kernel/linux-pwm.git/include= /linux/interrupt.h:12, from /home/thierry.reding/src/kernel/linux-pwm.git/arch/mi= ps/jz4740/irq.c:19: /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.h:21:13:= note: previous declaration of 'jz4740_irq_resume' was here /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c: In fu= nction 'arch_init_irq': /home/thierry.reding/src/kernel/linux-pwm.git/arch/mips/jz4740/irq.c:91:41:= error: 'JZ4740_IRQ_BASE' undeclared (first use in this function) cc1: all warnings being treated as errors make[3]: *** [arch/mips/jz4740/irq.o] Error 1 make[2]: *** [arch/mips/jz4740] Error 2 make[1]: *** [arch/mips] Error 2 make: *** [sub-make] Error 2 --ZGiS0Q5IWpPtfppv Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQUKPyAAoJEN0jrNd/PrOhUJwP/1dIPL5IM60pGY/bOYYQ9Jff FK/Y8wiQjTfYFvdO7qlM5bzfAbifb0KeHNGVgk+Qyxj80EF3kK3finWCR2MdYKN7 55fXKYDVbpeAcHQ1OAAN5i2fYhiCcs/uw0xXCqDw4miHoCo9BHPsHAX3/UdC4ILW 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arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q8CG5dLL029773; Wed, 12 Sep 2012 11:05:39 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8CG5dix029882; Wed, 12 Sep 2012 11:05:39 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Wed, 12 Sep 2012 11:05:39 -0500 Received: from ares-ubuntu.am.dhcp.ti.com (ares-ubuntu.am.dhcp.ti.com [158.218.103.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8CG5dki023284; Wed, 12 Sep 2012 11:05:39 -0500 Received: from a0875269 by ares-ubuntu.am.dhcp.ti.com with local (Exim 4.76) (envelope-from ) id 1TBpRa-0001qg-S0; Wed, 12 Sep 2012 12:05:38 -0400 From: Cyril Chemparathy To: , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Cyril Chemparathy Subject: [PATCH] of: specify initrd location using 64-bit Date: Wed, 12 Sep 2012 12:05:37 -0400 Message-ID: <1347465937-7056-1-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 34477 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cyril@ti.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6041 Lines: 166 On some PAE architectures, the entire range of physical memory could reside outside the 32-bit limit. These systems need the ability to specify the initrd location using 64-bit numbers. This patch globally modifies the early_init_dt_setup_initrd_arch() function to use 64-bit numbers instead of the current unsigned long. --- arch/arm/mm/init.c | 2 +- arch/c6x/kernel/devicetree.c | 3 +-- arch/microblaze/kernel/prom.c | 3 +-- arch/mips/kernel/prom.c | 3 +-- arch/openrisc/kernel/prom.c | 3 +-- arch/powerpc/kernel/prom.c | 3 +-- arch/x86/kernel/devicetree.c | 3 +-- drivers/of/fdt.c | 10 ++++++---- include/linux/of_fdt.h | 3 +-- 9 files changed, 14 insertions(+), 19 deletions(-) diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index ad722f1..579792c 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -76,7 +76,7 @@ static int __init parse_tag_initrd2(const struct tag *tag) __tagtable(ATAG_INITRD2, parse_tag_initrd2); #ifdef CONFIG_OF_FLATTREE -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { phys_initrd_start = start; phys_initrd_size = end - start; diff --git a/arch/c6x/kernel/devicetree.c b/arch/c6x/kernel/devicetree.c index bdb56f0..287d0e6 100644 --- a/arch/c6x/kernel/devicetree.c +++ b/arch/c6x/kernel/devicetree.c @@ -33,8 +33,7 @@ void __init early_init_devtree(void *params) #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c index 4a764cc..cecd42c 100644 --- a/arch/microblaze/kernel/prom.c +++ b/arch/microblaze/kernel/prom.c @@ -136,8 +136,7 @@ void __init early_init_devtree(void *params) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 028f6f8..e37e0dc 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -41,8 +41,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/openrisc/kernel/prom.c b/arch/openrisc/kernel/prom.c index 5869e3f..150215a 100644 --- a/arch/openrisc/kernel/prom.c +++ b/arch/openrisc/kernel/prom.c @@ -96,8 +96,7 @@ void __init early_init_devtree(void *params) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 37725e8..ac15f63 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -549,8 +549,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index b158152..2fbad6b 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -52,8 +52,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 91a375f..2ff8b7a 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -554,7 +554,8 @@ int __init of_flat_dt_match(unsigned long node, const char *const *compat) */ void __init early_init_dt_check_for_initrd(unsigned long node) { - unsigned long start, end, len; + u64 start, end; + unsigned long len; __be32 *prop; pr_debug("Looking for initrd properties... "); @@ -562,15 +563,16 @@ void __init early_init_dt_check_for_initrd(unsigned long node) prop = of_get_flat_dt_prop(node, "linux,initrd-start", &len); if (!prop) return; - start = of_read_ulong(prop, len/4); + start = of_read_number(prop, len/4); prop = of_get_flat_dt_prop(node, "linux,initrd-end", &len); if (!prop) return; - end = of_read_ulong(prop, len/4); + end = of_read_number(prop, len/4); early_init_dt_setup_initrd_arch(start, end); - pr_debug("initrd_start=0x%lx initrd_end=0x%lx\n", start, end); + pr_debug("initrd_start=0x%llx initrd_end=0x%llx\n", + (unsigned long long)start, (unsigned long long)end); } #else inline void early_init_dt_check_for_initrd(unsigned long node) diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h index ed136ad..4a17939 100644 --- a/include/linux/of_fdt.h +++ b/include/linux/of_fdt.h @@ -106,8 +106,7 @@ extern u64 dt_mem_next_cell(int s, __be32 **cellp); * physical addresses. */ #ifdef CONFIG_BLK_DEV_INITRD -extern void early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end); +extern void early_init_dt_setup_initrd_arch(u64 start, u64 end); #endif /* Early flat tree scan hooks */ -- 1.7.9.5 From geert@linux-m68k.org Wed Sep 12 18:16:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 18:16:23 +0200 (CEST) Received: from mail-vc0-f177.google.com ([209.85.220.177]:35557 "EHLO mail-vc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903340Ab2ILQQP (ORCPT ); Wed, 12 Sep 2012 18:16:15 +0200 Received: by vcbgb22 with SMTP id gb22so2407795vcb.36 for ; Wed, 12 Sep 2012 09:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=oXDpucRhCkwlYX1m+Tfy470zElP33reNOq0fAHcyB8k=; b=g1FRBVjZDL/oF12R5x1rkHYe3sFS09CQBZiXjBZIt603SM3VNIFkvOmwSfDaTjd0GI QKMqFshtlOIlQTxAoDha3Ny/v2r8JmPMLZLhvz2EmXNkrCJeh10GamazqT0nX+rmreoC GyQlo7G9KOvFXZD4HYrLrlD6zVEMCncjJ24gAbF5N3v6WiCE9BU5u5OUIjErDk/W4/rs D+rNd/WA8q9Ci2Sl4w7h2bEdL4FIIdoSfxDKjzA1+CuxH5SenE/F7/b4xpeDtnkkaQDN PH/nuZrgRyaC7UEnzNbpFAjuAr2UDRwBubH3Bi5Z5VCCJjpK8BCixL6fLJBI2PYJTlkX 4DMA== MIME-Version: 1.0 Received: by 10.52.18.244 with SMTP id z20mr23359837vdd.85.1347466569443; Wed, 12 Sep 2012 09:16:09 -0700 (PDT) Received: by 10.220.50.135 with HTTP; Wed, 12 Sep 2012 09:16:09 -0700 (PDT) In-Reply-To: <1347465937-7056-1-git-send-email-cyril@ti.com> References: <1347465937-7056-1-git-send-email-cyril@ti.com> Date: Wed, 12 Sep 2012 18:16:09 +0200 X-Google-Sender-Auth: wGlSj2Ng-D3KFipHiLmHQ-ErF5w Message-ID: Subject: Re: [PATCH] of: specify initrd location using 64-bit From: Geert Uytterhoeven To: Cyril Chemparathy Cc: devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux@openrisc.net, linuxppc-dev@lists.ozlabs.org, microblaze-uclinux@itee.uq.edu.au, a-jacquiot@ti.com, arnd@arndb.de, benh@kernel.crashing.org, bigeasy@linutronix.de, blogic@openwrt.org, david.daney@cavium.com, dhowells@redhat.com, grant.likely@secretlab.ca, hpa@zytor.com, jonas@southpole.se, linus.walleij@linaro.org, linux@arm.linux.org.uk, m.szyprowski@samsung.com, mahesh@linux.vnet.ibm.com, mingo@redhat.com, monstr@monstr.eu, msalter@redhat.com, nico@linaro.org, paul.gortmaker@windriver.com, paulus@samba.org, ralf@linux-mips.org, rob.herring@calxeda.com, suzuki@in.ibm.com, tglx@linutronix.de, tj@kernel.org, x86@kernel.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 34478 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 928 Lines: 23 On Wed, Sep 12, 2012 at 6:05 PM, Cyril Chemparathy wrote: > On some PAE architectures, the entire range of physical memory could reside > outside the 32-bit limit. These systems need the ability to specify the > initrd location using 64-bit numbers. > > This patch globally modifies the early_init_dt_setup_initrd_arch() function to > use 64-bit numbers instead of the current unsigned long. > -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) Why not phys_addr_t? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From sjhill@mips.com Wed Sep 12 19:02:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 19:02:13 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:33960 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903346Ab2ILRCF (ORCPT ); Wed, 12 Sep 2012 19:02:05 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TBqK7-0003K9-Jf; Wed, 12 Sep 2012 12:01:59 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 1/2] MIPS: Add base architecture support for RI and XI. Date: Wed, 12 Sep 2012 12:01:48 -0500 Message-Id: <1347469309-11468-2-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1347469309-11468-1-git-send-email-sjhill@mips.com> References: <1347469309-11468-1-git-send-email-sjhill@mips.com> X-archive-position: 34479 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2808 Lines: 75 From: "Steven J. Hill" Originally both Read Inhibit (RI) and Execute Inhibit (XI) were supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) Architecture now defines an optional feature to implement these TLB bits separately. Support for one or both features can be checked by looking at the Config3.RXI bit. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu-features.h | 3 +++ arch/mips/include/asm/cpu.h | 1 + arch/mips/include/asm/mipsregs.h | 1 + arch/mips/kernel/cpu-probe.c | 6 +++++- 4 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index bba9398..232cb1e 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -95,6 +95,9 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif +#ifndef cpu_has_rixi +#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +#endif #ifndef kernel_uses_smartmips_rixi #define kernel_uses_smartmips_rixi 0 #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 4889fae..f3150f6 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -323,6 +323,7 @@ enum cpu_type_enum { #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ #define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ +#define MIPS_CPU_RIXI 0x02000000 /* CPU has TLB Read/eXec Inhibit */ /* * CPU ASE encodings diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index cdb9c87..19430fb 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -591,6 +591,7 @@ #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) +#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 009fc13..b63732c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -422,8 +422,12 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) config3 = read_c0_config3(); - if (config3 & MIPS_CONF3_SM) + if (config3 & MIPS_CONF3_SM) { c->ases |= MIPS_ASE_SMARTMIPS; + c->options |= MIPS_CPU_RIXI; + } + if (config3 & MIPS_CONF3_RXI) + c->options |= MIPS_CPU_RIXI; if (config3 & MIPS_CONF3_DSP) c->ases |= MIPS_ASE_DSP; if (config3 & MIPS_CONF3_DSP2P) -- 1.7.9.5 From sjhill@mips.com Wed Sep 12 19:02:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 19:02:39 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:33958 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903349Ab2ILRCG (ORCPT ); Wed, 12 Sep 2012 19:02:06 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TBqK6-0003K9-1C; Wed, 12 Sep 2012 12:01:58 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 0/2] Add RI and XI bits to MIPS base architecture. Date: Wed, 12 Sep 2012 12:01:47 -0500 Message-Id: <1347469309-11468-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 34480 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1259 Lines: 30 From: "Steven J. Hill" Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI) and Execute Inhibit (XI) page protection. SmartMIPS cores will not notice any change in functionality. This patchset obsoletes the previous patchset with four commits. Signed-off-by: Steven J. Hill Steven J. Hill (2): MIPS: Add base architecture support for RI and XI. MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. arch/mips/include/asm/cpu-features.h | 4 ++-- arch/mips/include/asm/cpu.h | 1 + .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 +- arch/mips/include/asm/mipsregs.h | 1 + arch/mips/include/asm/pgtable-bits.h | 18 +++++++++--------- arch/mips/include/asm/pgtable.h | 12 ++++++------ arch/mips/kernel/cpu-probe.c | 6 +++++- arch/mips/mm/cache.c | 2 +- arch/mips/mm/fault.c | 2 +- arch/mips/mm/tlb-r4k.c | 2 +- arch/mips/mm/tlbex.c | 14 +++++++------- 11 files changed, 35 insertions(+), 29 deletions(-) -- 1.7.9.5 From sjhill@mips.com Wed Sep 12 19:02:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 19:03:06 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:33962 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903350Ab2ILRCG (ORCPT ); Wed, 12 Sep 2012 19:02:06 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TBqK8-0003K9-GJ; Wed, 12 Sep 2012 12:02:00 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH 2/2] MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. Date: Wed, 12 Sep 2012 12:01:49 -0500 Message-Id: <1347469309-11468-3-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1347469309-11468-1-git-send-email-sjhill@mips.com> References: <1347469309-11468-1-git-send-email-sjhill@mips.com> X-archive-position: 34481 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10574 Lines: 239 From: "Steven J. Hill" Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files and use new 'cpu_has_rixi' instead. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu-features.h | 3 --- .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 +- arch/mips/include/asm/pgtable-bits.h | 18 +++++++++--------- arch/mips/include/asm/pgtable.h | 12 ++++++------ arch/mips/mm/cache.c | 2 +- arch/mips/mm/fault.c | 2 +- arch/mips/mm/tlb-r4k.c | 2 +- arch/mips/mm/tlbex.c | 14 +++++++------- 8 files changed, 26 insertions(+), 29 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 232cb1e..5a65870 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -98,9 +98,6 @@ #ifndef cpu_has_rixi #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) #endif -#ifndef kernel_uses_smartmips_rixi -#define kernel_uses_smartmips_rixi 0 -#endif #ifndef cpu_has_mmips #define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) #endif diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index a58addb..375ad0c 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -58,7 +58,7 @@ #define cpu_has_veic 0 #define cpu_hwrena_impl_bits 0xc0000000 -#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) +#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) #define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1 diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index e9fe7e9..2f99313 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -79,9 +79,9 @@ /* implemented in software */ #define _PAGE_PRESENT_SHIFT (0) #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) -/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */ -#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) -#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; }) +/* implemented in software, should be unused if cpu_has_rixi. */ +#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ ({if (cpu_has_rixi) BUG(); 1 << _PAGE_READ_SHIFT; }) /* implemented in software */ #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) @@ -104,12 +104,12 @@ #endif /* Page cannot be executed */ -#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) -#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) +#define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) +#define _PAGE_NO_EXEC ({if (!cpu_has_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) /* Page cannot be read */ -#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) -#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) +#define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) +#define _PAGE_NO_READ ({if (!cpu_has_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) @@ -155,7 +155,7 @@ */ static inline uint64_t pte_to_entrylo(unsigned long pte_val) { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { int sa; #ifdef CONFIG_32BIT sa = 31 - _PAGE_NO_READ_SHIFT; @@ -220,7 +220,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #endif -#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ)) +#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index b2202a6..c02158b 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -22,15 +22,15 @@ struct mm_struct; struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ - (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_COPY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ + (cpu_has_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ +#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) @@ -299,7 +299,7 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { if (!(pte_val(pte) & _PAGE_NO_READ)) pte_val(pte) |= _PAGE_SILENT_READ; } else { diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index ff910a1..d449d9a 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -183,7 +183,7 @@ EXPORT_SYMBOL(_page_cachable_default); static inline void setup_protection_map(void) { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index c14f6df..7a19957 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -114,7 +114,7 @@ good_area: if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) { #if 0 pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] XI violation\n", diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index d2572cb..87b9cfc 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -401,7 +401,7 @@ void __cpuinit tlb_init(void) current_cpu_type() == CPU_R14000) write_c0_framemask(0); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { /* * Enable the no read, no exec bits, and enable large virtual * address. diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 202908e..542dae1 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -601,7 +601,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, unsigned int reg) { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); } else { @@ -1021,7 +1021,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, if (cpu_has_64bits) { uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); @@ -1048,7 +1048,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ if (r45k_bvahwbug()) build_tlb_probe_entry(p); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); @@ -1214,7 +1214,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, UASM_i_LW(p, even, 0, ptr); /* get even pte */ UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ } - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC)); uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC)); uasm_i_drotr(p, even, even, @@ -1576,7 +1576,7 @@ build_pte_present(u32 **p, struct uasm_reloc **r, { int t = scratch >= 0 ? scratch : pte; - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { if (use_bbit_insns()) { uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); uasm_i_nop(p); @@ -1906,7 +1906,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) if (m4kc_tlbp_war()) build_tlb_probe_entry(&p); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. @@ -1960,7 +1960,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); build_tlb_probe_entry(&p); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. -- 1.7.9.5 From ddaney.cavm@gmail.com Wed Sep 12 19:47:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 19:47:40 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:61459 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903340Ab2ILRre (ORCPT ); Wed, 12 Sep 2012 19:47:34 +0200 Received: by pbbrq8 with SMTP id rq8so2801931pbb.36 for ; Wed, 12 Sep 2012 10:47:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=qkCcQGO3p2TVTvWfJKYhqNdRHh8A4tx7QyEIYSBv6wI=; b=d+puFmdSpQ8qCxMGg3AG+WlUPwCzhJPnBKzQ7MjXDpjkxT7EBuk6LHcp+o+1M3fQEZ 9w1i4X30JMhPzV93EhQ7jclJd1wzZdzYj66U7IgvLTNLqgKuzFofsJ0h0aCN/lGtn8FQ JUSMWcc+9/TT9HnWZbDNEw5hhO+2DdWK7LxA4z/ZXYhe81kSDPfXjtZ7hq5yveQ3utjL d5X721R1lsfeX03lnxZTo/9NZtwJJZN1mH+8IZ6qzaCNtHOaSKU6nEorwyBVYPDYlshs ScQkDPUDMtdtuFcFQefOX+HjMUOn71TfSvy5ZwNaVA4R1tIKn9NlOSXABFoGp+0TkzHX GTWw== Received: by 10.66.76.165 with SMTP id l5mr32535439paw.79.1347472047910; Wed, 12 Sep 2012 10:47:27 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ka4sm11714859pbc.61.2012.09.12.10.47.25 (version=SSLv3 cipher=OTHER); Wed, 12 Sep 2012 10:47:26 -0700 (PDT) Message-ID: <5050CAAC.1090600@gmail.com> Date: Wed, 12 Sep 2012 10:47:24 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: "Steven J. Hill" , ralf@linux-mips.org CC: linux-mips@linux-mips.org Subject: Re: [PATCH 0/2] Add RI and XI bits to MIPS base architecture. References: <1347469309-11468-1-git-send-email-sjhill@mips.com> In-Reply-To: <1347469309-11468-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34482 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1457 Lines: 35 On 09/12/2012 10:01 AM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI) > and Execute Inhibit (XI) page protection. SmartMIPS cores will not > notice any change in functionality. > > This patchset obsoletes the previous patchset with four commits. > > Signed-off-by: Steven J. Hill FWIW: I haven't tested it, but the entire set ... Acked-by: David Daney > > Steven J. Hill (2): > MIPS: Add base architecture support for RI and XI. > MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. > > arch/mips/include/asm/cpu-features.h | 4 ++-- > arch/mips/include/asm/cpu.h | 1 + > .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 +- > arch/mips/include/asm/mipsregs.h | 1 + > arch/mips/include/asm/pgtable-bits.h | 18 +++++++++--------- > arch/mips/include/asm/pgtable.h | 12 ++++++------ > arch/mips/kernel/cpu-probe.c | 6 +++++- > arch/mips/mm/cache.c | 2 +- > arch/mips/mm/fault.c | 2 +- > arch/mips/mm/tlb-r4k.c | 2 +- > arch/mips/mm/tlbex.c | 14 +++++++------- > 11 files changed, 35 insertions(+), 29 deletions(-) > From cyril@ti.com Wed Sep 12 20:03:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 20:03:31 +0200 (CEST) Received: from bear.ext.ti.com ([192.94.94.41]:51376 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903340Ab2ILSDU (ORCPT ); Wed, 12 Sep 2012 20:03:20 +0200 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q8CI2Zvf021542; Wed, 12 Sep 2012 13:02:35 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8CI2ZS9023276; Wed, 12 Sep 2012 13:02:35 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Wed, 12 Sep 2012 13:02:35 -0500 Received: from [158.218.103.130] (gtla0875269.am.dhcp.ti.com [158.218.103.130]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8CI2RDL032273; Wed, 12 Sep 2012 13:02:28 -0500 Message-ID: <5050CE33.9060909@ti.com> Date: Wed, 12 Sep 2012 14:02:27 -0400 From: Cyril Chemparathy User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:15.0) Gecko/20120824 Thunderbird/15.0 MIME-Version: 1.0 To: Geert Uytterhoeven CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH] of: specify initrd location using 64-bit References: <1347465937-7056-1-git-send-email-cyril@ti.com> In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34483 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cyril@ti.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1160 Lines: 33 On 9/12/2012 12:16 PM, Geert Uytterhoeven wrote: > On Wed, Sep 12, 2012 at 6:05 PM, Cyril Chemparathy wrote: >> On some PAE architectures, the entire range of physical memory could reside >> outside the 32-bit limit. These systems need the ability to specify the >> initrd location using 64-bit numbers. >> >> This patch globally modifies the early_init_dt_setup_initrd_arch() function to >> use 64-bit numbers instead of the current unsigned long. > >> -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) >> +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > > Why not phys_addr_t? > The rest of the memory specific bits of the device-tree code use u64 for addresses, and I kept it the same for consistency. > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds > -- Thanks - Cyril From bigeasy@linutronix.de Wed Sep 12 22:00:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 22:00:12 +0200 (CEST) Received: from www.linutronix.de ([62.245.132.108]:58828 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903340Ab2ILUAF (ORCPT ); Wed, 12 Sep 2012 22:00:05 +0200 Received: from localhost ([127.0.0.1]) by Galois.linutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1TBt4y-0000Uj-On; Wed, 12 Sep 2012 21:58:32 +0200 Message-ID: <5050E965.5080405@linutronix.de> Date: Wed, 12 Sep 2012 21:58:29 +0200 From: Sebastian Andrzej Siewior User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.6esrpre) Gecko/20120817 Icedove/10.0.6 MIME-Version: 1.0 To: Cyril Chemparathy CC: Geert Uytterhoeven , devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux@openrisc.net, linuxppc-dev@lists.ozlabs.org, microblaze-uclinux@itee.uq.edu.au, a-jacquiot@ti.com, arnd@arndb.de, benh@kernel.crashing.org, blogic@openwrt.org, david.daney@cavium.com, dhowells@redhat.com, grant.likely@secretlab.ca, hpa@zytor.com, jonas@southpole.se, linus.walleij@linaro.org, linux@arm.linux.org.uk, m.szyprowski@samsung.com, mahesh@linux.vnet.ibm.com, mingo@redhat.com, monstr@monstr.eu, msalter@redhat.com, nico@linaro.org, paul.gortmaker@windriver.com, paulus@samba.org, ralf@linux-mips.org, rob.herring@calxeda.com, suzuki@in.ibm.com, tglx@linutronix.de, tj@kernel.org, x86@kernel.org Subject: Re: [PATCH] of: specify initrd location using 64-bit References: <1347465937-7056-1-git-send-email-cyril@ti.com> <5050CE33.9060909@ti.com> In-Reply-To: <5050CE33.9060909@ti.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 X-archive-position: 34484 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bigeasy@linutronix.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 459 Lines: 15 On 09/12/2012 08:02 PM, Cyril Chemparathy wrote: >>> -void __init early_init_dt_setup_initrd_arch(unsigned long start, >>> unsigned long end) >>> +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) >> >> Why not phys_addr_t? >> > > The rest of the memory specific bits of the device-tree code use u64 for > addresses, and I kept it the same for consistency. Geert is right here. If it is a physical address, it should be phys_addr_t. Sebastian From robherring2@gmail.com Wed Sep 12 22:23:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 22:23:45 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:37793 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903346Ab2ILUXi (ORCPT ); Wed, 12 Sep 2012 22:23:38 +0200 Received: by obbta17 with SMTP id ta17so3443552obb.36 for ; Wed, 12 Sep 2012 13:23:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=LAg63+2yvHZORhQUOjlpS9uYpijGQI3981O7/ek8vtU=; b=mZdJncWwtBCqrZrCwf0s2J9jsW4/PPa2jyHorSjFZV5bpOLUvnBomwlJfr5o7Li/S0 pKsMRT2O6bGD82cMJEEzr3u4tGPpnc7XlflmBK1JD8a4zvo2RrHuQSU7RP8/XPQprquz 9R8sW2zBe/6jJDAmLzAtLRRsE72GrsffPUPxWJqj52S2tXSbQlihKZETWhjVZ4tLe0b5 vqwm8AXkiFtUl1s7/wJO5qFRtHMpH0H0qFk5YJf2fkxRNW2r01BGY4Lhacl4YDxEgplb bCH++pl03l3sc+aF8SjqQ7o40EuXVJLyxrXU0qV3sWXcMN/1rFfXjz76MEgLUWviwInC S7fg== Received: by 10.60.171.138 with SMTP id au10mr24825772oec.39.1347481411344; Wed, 12 Sep 2012 13:23:31 -0700 (PDT) Received: from [10.10.10.90] ([173.226.190.126]) by mx.google.com with ESMTPS id 2sm21227455obi.20.2012.09.12.13.23.28 (version=SSLv3 cipher=OTHER); Wed, 12 Sep 2012 13:23:30 -0700 (PDT) Message-ID: <5050EF3F.6030003@gmail.com> Date: Wed, 12 Sep 2012 15:23:27 -0500 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Cyril Chemparathy CC: devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux@openrisc.net, linuxppc-dev@lists.ozlabs.org, microblaze-uclinux@itee.uq.edu.au, x86@kernel.org, david.daney@cavium.com, benh@kernel.crashing.org, bigeasy@linutronix.de, grant.likely@secretlab.ca, paul.gortmaker@windriver.com, paulus@samba.org, hpa@zytor.com, m.szyprowski@samsung.com, jonas@southpole.se, linux@arm.linux.org.uk, nico@linaro.org, a-jacquiot@ti.com, mingo@redhat.com, suzuki@in.ibm.com, mahesh@linux.vnet.ibm.com, linus.walleij@linaro.org, arnd@arndb.de, msalter@redhat.com, rob.herring@calxeda.com, tglx@linutronix.de, blogic@openwrt.org, dhowells@redhat.com, monstr@monstr.eu, ralf@linux-mips.org, tj@kernel.org Subject: Re: [PATCH] of: specify initrd location using 64-bit References: <1347465937-7056-1-git-send-email-cyril@ti.com> In-Reply-To: <1347465937-7056-1-git-send-email-cyril@ti.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34485 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6541 Lines: 175 On 09/12/2012 11:05 AM, Cyril Chemparathy wrote: > On some PAE architectures, the entire range of physical memory could reside > outside the 32-bit limit. These systems need the ability to specify the > initrd location using 64-bit numbers. > > This patch globally modifies the early_init_dt_setup_initrd_arch() function to > use 64-bit numbers instead of the current unsigned long. S-o-B? > --- > arch/arm/mm/init.c | 2 +- > arch/c6x/kernel/devicetree.c | 3 +-- > arch/microblaze/kernel/prom.c | 3 +-- > arch/mips/kernel/prom.c | 3 +-- > arch/openrisc/kernel/prom.c | 3 +-- > arch/powerpc/kernel/prom.c | 3 +-- > arch/x86/kernel/devicetree.c | 3 +-- > drivers/of/fdt.c | 10 ++++++---- > include/linux/of_fdt.h | 3 +-- > 9 files changed, 14 insertions(+), 19 deletions(-) > > diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c > index ad722f1..579792c 100644 > --- a/arch/arm/mm/init.c > +++ b/arch/arm/mm/init.c > @@ -76,7 +76,7 @@ static int __init parse_tag_initrd2(const struct tag *tag) > __tagtable(ATAG_INITRD2, parse_tag_initrd2); > > #ifdef CONFIG_OF_FLATTREE > -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) phys_initrd_start/size need to change too. Not sure about similar things on other arches. Does u-boot need similar fixes? > { > phys_initrd_start = start; > phys_initrd_size = end - start; > diff --git a/arch/c6x/kernel/devicetree.c b/arch/c6x/kernel/devicetree.c > index bdb56f0..287d0e6 100644 > --- a/arch/c6x/kernel/devicetree.c > +++ b/arch/c6x/kernel/devicetree.c > @@ -33,8 +33,7 @@ void __init early_init_devtree(void *params) > > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c > index 4a764cc..cecd42c 100644 > --- a/arch/microblaze/kernel/prom.c > +++ b/arch/microblaze/kernel/prom.c > @@ -136,8 +136,7 @@ void __init early_init_devtree(void *params) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c > index 028f6f8..e37e0dc 100644 > --- a/arch/mips/kernel/prom.c > +++ b/arch/mips/kernel/prom.c > @@ -41,8 +41,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/openrisc/kernel/prom.c b/arch/openrisc/kernel/prom.c > index 5869e3f..150215a 100644 > --- a/arch/openrisc/kernel/prom.c > +++ b/arch/openrisc/kernel/prom.c > @@ -96,8 +96,7 @@ void __init early_init_devtree(void *params) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c > index 37725e8..ac15f63 100644 > --- a/arch/powerpc/kernel/prom.c > +++ b/arch/powerpc/kernel/prom.c > @@ -549,8 +549,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c > index b158152..2fbad6b 100644 > --- a/arch/x86/kernel/devicetree.c > +++ b/arch/x86/kernel/devicetree.c > @@ -52,8 +52,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c > index 91a375f..2ff8b7a 100644 > --- a/drivers/of/fdt.c > +++ b/drivers/of/fdt.c > @@ -554,7 +554,8 @@ int __init of_flat_dt_match(unsigned long node, const char *const *compat) > */ > void __init early_init_dt_check_for_initrd(unsigned long node) > { > - unsigned long start, end, len; > + u64 start, end; > + unsigned long len; > __be32 *prop; > > pr_debug("Looking for initrd properties... "); > @@ -562,15 +563,16 @@ void __init early_init_dt_check_for_initrd(unsigned long node) > prop = of_get_flat_dt_prop(node, "linux,initrd-start", &len); > if (!prop) > return; > - start = of_read_ulong(prop, len/4); > + start = of_read_number(prop, len/4); > > prop = of_get_flat_dt_prop(node, "linux,initrd-end", &len); > if (!prop) > return; > - end = of_read_ulong(prop, len/4); > + end = of_read_number(prop, len/4); > > early_init_dt_setup_initrd_arch(start, end); > - pr_debug("initrd_start=0x%lx initrd_end=0x%lx\n", start, end); > + pr_debug("initrd_start=0x%llx initrd_end=0x%llx\n", > + (unsigned long long)start, (unsigned long long)end); > } > #else > inline void early_init_dt_check_for_initrd(unsigned long node) > diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h > index ed136ad..4a17939 100644 > --- a/include/linux/of_fdt.h > +++ b/include/linux/of_fdt.h > @@ -106,8 +106,7 @@ extern u64 dt_mem_next_cell(int s, __be32 **cellp); > * physical addresses. > */ > #ifdef CONFIG_BLK_DEV_INITRD > -extern void early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end); > +extern void early_init_dt_setup_initrd_arch(u64 start, u64 end); > #endif > > /* Early flat tree scan hooks */ > From nicolas.pitre@linaro.org Wed Sep 12 22:31:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 22:31:42 +0200 (CEST) Received: from mail-qa0-f49.google.com ([209.85.216.49]:56318 "EHLO mail-qa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903348Ab2ILUbi (ORCPT ); Wed, 12 Sep 2012 22:31:38 +0200 Received: by qafk1 with SMTP id k1so1417399qaf.15 for ; Wed, 12 Sep 2012 13:31:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:in-reply-to:message-id:references :user-agent:mime-version:content-type:x-gm-message-state; bh=4bXrofJBvKD27Thx87qmEQ7uxo2cJaabolvZNLZypjQ=; b=awlzqzcB02rlBn3JqComf8hBzs4VnpiB9hS0HuZFKnhPdGvskWSzTjpU2L5FjTSHgg 82fma0NI9PEG/q/oBpTcs+b7ir9FYWCcK36++aQsa+pfJVbggafOfwV3tq1bQUk2iPFU +7T8d3k40HNcsqladnJKjcK5tqVAsb24sA7XOmba9tVA9vEQTQFcd6W7z8O7+kzCmnJ1 1PVpzXhyIrxKdMPd9TwDbOgLZmzFsBbCZwPi9NApFi7dBesyqDfu1zpTYzsDiSp6EtaZ KhJQD6T/dWT3crDPVnOoWVg0b8DWLuXUW+RtgHw6tQIweU3kbMxzF1eqWPzMfxf35JSH L1YQ== Received: by 10.224.214.67 with SMTP id gz3mr698356qab.70.1347481892171; Wed, 12 Sep 2012 13:31:32 -0700 (PDT) Received: from xanadu.home (modemcable149.196-201-24.mc.videotron.ca. [24.201.196.149]) by mx.google.com with ESMTPS id a13sm11255754qad.18.2012.09.12.13.31.30 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 12 Sep 2012 13:31:31 -0700 (PDT) Date: Wed, 12 Sep 2012 16:31:29 -0400 (EDT) From: Nicolas Pitre To: Rob Herring cc: Cyril Chemparathy , devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux@openrisc.net, linuxppc-dev@lists.ozlabs.org, microblaze-uclinux@itee.uq.edu.au, x86@kernel.org, david.daney@cavium.com, benh@kernel.crashing.org, bigeasy@linutronix.de, grant.likely@secretlab.ca, paul.gortmaker@windriver.com, paulus@samba.org, hpa@zytor.com, m.szyprowski@samsung.com, jonas@southpole.se, linux@arm.linux.org.uk, a-jacquiot@ti.com, mingo@redhat.com, suzuki@in.ibm.com, mahesh@linux.vnet.ibm.com, linus.walleij@linaro.org, arnd@arndb.de, msalter@redhat.com, rob.herring@calxeda.com, tglx@linutronix.de, blogic@openwrt.org, dhowells@redhat.com, monstr@monstr.eu, ralf@linux-mips.org, tj@kernel.org Subject: Re: [PATCH] of: specify initrd location using 64-bit In-Reply-To: <5050EF3F.6030003@gmail.com> Message-ID: References: <1347465937-7056-1-git-send-email-cyril@ti.com> <5050EF3F.6030003@gmail.com> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Gm-Message-State: ALoCoQnekanbUMWQw6esCiKCfk07hXJe9kdlUWp666woH7Lrg4upM3HSkdk2b/wZDoiJZJJ8rMA0 X-archive-position: 34486 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nicolas.pitre@linaro.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1534 Lines: 42 On Wed, 12 Sep 2012, Rob Herring wrote: > On 09/12/2012 11:05 AM, Cyril Chemparathy wrote: > > On some PAE architectures, the entire range of physical memory could reside > > outside the 32-bit limit. These systems need the ability to specify the > > initrd location using 64-bit numbers. > > > > This patch globally modifies the early_init_dt_setup_initrd_arch() function to > > use 64-bit numbers instead of the current unsigned long. > > S-o-B? > > > --- > > arch/arm/mm/init.c | 2 +- > > arch/c6x/kernel/devicetree.c | 3 +-- > > arch/microblaze/kernel/prom.c | 3 +-- > > arch/mips/kernel/prom.c | 3 +-- > > arch/openrisc/kernel/prom.c | 3 +-- > > arch/powerpc/kernel/prom.c | 3 +-- > > arch/x86/kernel/devicetree.c | 3 +-- > > drivers/of/fdt.c | 10 ++++++---- > > include/linux/of_fdt.h | 3 +-- > > 9 files changed, 14 insertions(+), 19 deletions(-) > > > > diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c > > index ad722f1..579792c 100644 > > --- a/arch/arm/mm/init.c > > +++ b/arch/arm/mm/init.c > > @@ -76,7 +76,7 @@ static int __init parse_tag_initrd2(const struct tag *tag) > > __tagtable(ATAG_INITRD2, parse_tag_initrd2); > > > > #ifdef CONFIG_OF_FLATTREE > > -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) > > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > > phys_initrd_start/size need to change too. Not sure about similar things > on other arches. size ? Nicolas From robherring2@gmail.com Wed Sep 12 22:56:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Sep 2012 22:56:39 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:34009 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903508Ab2ILU4f (ORCPT ); Wed, 12 Sep 2012 22:56:35 +0200 Received: by obbta17 with SMTP id ta17so3496745obb.36 for ; Wed, 12 Sep 2012 13:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=qRRupGy+jLT3bdqbyn8e1tMDubc+EYbZLTVrVRmvZnw=; b=JChgIHL/IWqc3fX6MN40C73H2X+CFAyXwKFhePLSWFVfIpNKAHcleZchTwy5e5iH6p WjZnYnnr00+VF+CQddicX1e9srJ+DreJqqRPmE6T1QQKsSc9uaeg1p80GZ1aggYUBlKg DuFc3eTcZgPQMivbskhGW9k91o62NmNG0+Jn7YDm/n9aolvPo/Kb+SSW94Zz0hX4Dz9h C9a0AZUl8ir62/UoALcPUQPi2g34hz7mXp2l4tDNK1OOBYTpOCukQac4DULWVZxdXv9d Xpb5dg2rjHbFgXNvzhkIo9AfCcRMlzyKdY6eYjHizfJoH7jVi+GidYBHuhGuXtUoyCni qNew== Received: by 10.60.30.201 with SMTP id u9mr24274025oeh.51.1347483388460; Wed, 12 Sep 2012 13:56:28 -0700 (PDT) Received: from [10.10.10.90] ([173.226.190.126]) by mx.google.com with ESMTPS id ea6sm21321394obc.9.2012.09.12.13.56.25 (version=SSLv3 cipher=OTHER); Wed, 12 Sep 2012 13:56:27 -0700 (PDT) Message-ID: <5050F6F8.6000008@gmail.com> Date: Wed, 12 Sep 2012 15:56:24 -0500 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Nicolas Pitre CC: Cyril Chemparathy , devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux@openrisc.net, linuxppc-dev@lists.ozlabs.org, microblaze-uclinux@itee.uq.edu.au, x86@kernel.org, david.daney@cavium.com, benh@kernel.crashing.org, bigeasy@linutronix.de, grant.likely@secretlab.ca, paul.gortmaker@windriver.com, paulus@samba.org, hpa@zytor.com, m.szyprowski@samsung.com, jonas@southpole.se, linux@arm.linux.org.uk, a-jacquiot@ti.com, mingo@redhat.com, suzuki@in.ibm.com, mahesh@linux.vnet.ibm.com, linus.walleij@linaro.org, arnd@arndb.de, msalter@redhat.com, rob.herring@calxeda.com, tglx@linutronix.de, blogic@openwrt.org, dhowells@redhat.com, monstr@monstr.eu, ralf@linux-mips.org, tj@kernel.org Subject: Re: [PATCH] of: specify initrd location using 64-bit References: <1347465937-7056-1-git-send-email-cyril@ti.com> <5050EF3F.6030003@gmail.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34487 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1776 Lines: 47 On 09/12/2012 03:31 PM, Nicolas Pitre wrote: > On Wed, 12 Sep 2012, Rob Herring wrote: > >> On 09/12/2012 11:05 AM, Cyril Chemparathy wrote: >>> On some PAE architectures, the entire range of physical memory could reside >>> outside the 32-bit limit. These systems need the ability to specify the >>> initrd location using 64-bit numbers. >>> >>> This patch globally modifies the early_init_dt_setup_initrd_arch() function to >>> use 64-bit numbers instead of the current unsigned long. >> >> S-o-B? >> >>> --- >>> arch/arm/mm/init.c | 2 +- >>> arch/c6x/kernel/devicetree.c | 3 +-- >>> arch/microblaze/kernel/prom.c | 3 +-- >>> arch/mips/kernel/prom.c | 3 +-- >>> arch/openrisc/kernel/prom.c | 3 +-- >>> arch/powerpc/kernel/prom.c | 3 +-- >>> arch/x86/kernel/devicetree.c | 3 +-- >>> drivers/of/fdt.c | 10 ++++++---- >>> include/linux/of_fdt.h | 3 +-- >>> 9 files changed, 14 insertions(+), 19 deletions(-) >>> >>> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c >>> index ad722f1..579792c 100644 >>> --- a/arch/arm/mm/init.c >>> +++ b/arch/arm/mm/init.c >>> @@ -76,7 +76,7 @@ static int __init parse_tag_initrd2(const struct tag *tag) >>> __tagtable(ATAG_INITRD2, parse_tag_initrd2); >>> >>> #ifdef CONFIG_OF_FLATTREE >>> -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) >>> +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) >> >> phys_initrd_start/size need to change too. Not sure about similar things >> on other arches. > > size ? phys_initrd_size. Arguably, we'll never have a >4GB initrd with a PAE system or perhaps run into other issues first (like space to decompress it), but technically the DTS could specify one. Rob From robherring2@gmail.com Thu Sep 13 00:08:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Sep 2012 00:08:47 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:41592 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903351Ab2ILWIk (ORCPT ); Thu, 13 Sep 2012 00:08:40 +0200 Received: by obbta17 with SMTP id ta17so3601656obb.36 for ; Wed, 12 Sep 2012 15:08:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=QQ0noX15Z5BL3V3kLW6FG8GbGxnVnZVlNfZYaapKMjY=; b=bRMOccOwj9JDNzoG7X7DPaR6WkdITRz10oOshhzppzvnMi6tHXxTaHD60gndFb5SIP X1sGIgCiwFSmCzXSlGgZZhDia93m1DIOJ1e5V7yTmW57AKLFI5xyeg74fn97NJk2mxCY OSrE3uQOEC01VKeez3Aojf43Thmi27uG2Bht1cNfrMdU1lA0PFTG7J6D7nA9i8RDijUx 4jSynL2UsxKWp7t9QnReFx8HWTp3C5ddog8AFOpRi7SKiCGJYUBrDWmv95zhGj+ytCCG xXXLQakySWlKF0uL71C6PlRuirciUEBNIlDY4/fICV8ElYjXbG/6/Er2TCl8rF1gajQs XFJQ== Received: by 10.60.170.47 with SMTP id aj15mr1657oec.29.1347487714394; Wed, 12 Sep 2012 15:08:34 -0700 (PDT) Received: from [10.10.10.90] ([173.226.190.126]) by mx.google.com with ESMTPS id th3sm21504107obb.6.2012.09.12.15.08.32 (version=SSLv3 cipher=OTHER); Wed, 12 Sep 2012 15:08:33 -0700 (PDT) Message-ID: <505107DF.5020105@gmail.com> Date: Wed, 12 Sep 2012 17:08:31 -0500 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Sebastian Andrzej Siewior CC: Cyril Chemparathy , linux-mips@linux-mips.org, x86@kernel.org, a-jacquiot@ti.com, mahesh@linux.vnet.ibm.com, linus.walleij@linaro.org, grant.likely@secretlab.ca, paul.gortmaker@windriver.com, paulus@samba.org, hpa@zytor.com, m.szyprowski@samsung.com, jonas@southpole.se, linux@arm.linux.org.uk, linux-c6x-dev@linux-c6x.org, nico@linaro.org, david.daney@cavium.com, mingo@redhat.com, Geert Uytterhoeven , benh@kernel.crashing.org, suzuki@in.ibm.com, linux@openrisc.net, arnd@arndb.de, microblaze-uclinux@itee.uq.edu.au, devicetree-discuss@lists.ozlabs.org, msalter@redhat.com, rob.herring@calxeda.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, blogic@openwrt.org, dhowells@redhat.com, monstr@monstr.eu, linux-kernel@vger.kernel.org, ralf@linux-mips.org, tj@kernel.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] of: specify initrd location using 64-bit References: <1347465937-7056-1-git-send-email-cyril@ti.com> <5050CE33.9060909@ti.com> <5050E965.5080405@linutronix.de> In-Reply-To: <5050E965.5080405@linutronix.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34488 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 957 Lines: 26 On 09/12/2012 02:58 PM, Sebastian Andrzej Siewior wrote: > On 09/12/2012 08:02 PM, Cyril Chemparathy wrote: >>>> -void __init early_init_dt_setup_initrd_arch(unsigned long start, >>>> unsigned long end) >>>> +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) >>> >>> Why not phys_addr_t? >>> >> >> The rest of the memory specific bits of the device-tree code use u64 for >> addresses, and I kept it the same for consistency. > > Geert is right here. If it is a physical address, it should be > phys_addr_t. While generally true, for the DT specific code I think it should be a fixed u64. The size of the address is defined by the FDT, not the kernel. It is very likely we could have a FDT that specifies addresses in 64-bit values, but then we boot a kernel is compiled for !LPAE. phys_addr_t is currently sized based on LPAE setting. Also, this is how the memory and reserved nodes are handled currently, so we should be consistent. Rob From gregkh@linuxfoundation.org Thu Sep 13 01:30:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Sep 2012 01:30:41 +0200 (CEST) Received: from mail-oa0-f49.google.com ([209.85.219.49]:36385 "EHLO mail-oa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903509Ab2ILXah (ORCPT ); Thu, 13 Sep 2012 01:30:37 +0200 Received: by oagh1 with SMTP id h1so1475100oag.36 for ; Wed, 12 Sep 2012 16:30:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :user-agent:x-gm-message-state; bh=vQ39qJL+h6bbvFbm66yuvK+8ljwMYCb/tvFJISbeKDU=; b=f3arxAw+rVx9nRJNU688H01HNG0EHx7mMLsg7OoNdqwldmrTP8Xp7TceId0Z973RVm FvjGjU2BYHrZstMvbYWfGTGE8hbT8wGdwk7+HL1w//T+66yJDr/KLBjx1UQjaBO+SIX/ WJX8gJDlv3K3M5ggwjdNPWnXQ9EvYXLkiQvwzMGsku6rM1MdXdJ9pSAZwG20GCEb6m5w do5R3MY3cm6X9E+ieBcnb1OHmJbRzZvr+/Bl5oIcE70Xoa6R3iUxSRBKn72fOXO/uJer 0vd4TF9p89AlNSYTXAfhNIjRs5+zob6cc707VRIVczLZ9QWxyUexpTRFa2Mk6xkah3dS SOfg== Received: by 10.60.25.129 with SMTP id c1mr126314oeg.36.1347492631227; Wed, 12 Sep 2012 16:30:31 -0700 (PDT) Received: from localhost (c-67-168-183-230.hsd1.wa.comcast.net. [67.168.183.230]) by mx.google.com with ESMTPS id 2sm21739513obi.20.2012.09.12.16.30.27 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 12 Sep 2012 16:30:29 -0700 (PDT) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Greg KH , Gabor Juhos , Ralf Baechle , linux-mips@linux-mips.org Subject: [ 017/108] MIPS: pci-ar724x: avoid data bus error due to a missing PCIe module Date: Wed, 12 Sep 2012 16:28:15 -0700 Message-Id: <20120912232452.346902780@linuxfoundation.org> X-Mailer: git-send-email 1.7.10.1.362.g242cab3 In-Reply-To: <20120912232450.500619493@linuxfoundation.org> References: <20120912232816.GA1655@kroah.com> <20120912232450.500619493@linuxfoundation.org> User-Agent: quilt/0.60-2.1.2 X-Gm-Message-State: ALoCoQkQFT7zXfmAlDdnO2vSRgvVud2LxuegwF89sKEJGbzINcyJl6+6Csa9zJIrer08HhRSrDEg X-archive-position: 34489 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2415 Lines: 89 From: Greg KH 3.5-stable review patch. If anyone has any objections, please let me know. ------------------ From: Gabor Juhos commit a1dca315ce3f78347bca8ce8befe3cc71ae63b7e upstream. If the controller has no PCIe module attached, accessing of the device configuration space causes a data bus error. Avoid this by checking the status of the PCIe link in advance, and indicate an error if the link is down. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4293/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/pci/pci-ar724x.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -23,9 +23,12 @@ #define AR724X_PCI_MEM_BASE 0x10000000 #define AR724X_PCI_MEM_SIZE 0x08000000 +#define AR724X_PCI_REG_RESET 0x18 #define AR724X_PCI_REG_INT_STATUS 0x4c #define AR724X_PCI_REG_INT_MASK 0x50 +#define AR724X_PCI_RESET_LINK_UP BIT(0) + #define AR724X_PCI_INT_DEV0 BIT(14) #define AR724X_PCI_IRQ_COUNT 1 @@ -38,6 +41,15 @@ static void __iomem *ar724x_pci_ctrl_bas static u32 ar724x_pci_bar0_value; static bool ar724x_pci_bar0_is_cached; +static bool ar724x_pci_link_up; + +static inline bool ar724x_pci_check_link(void) +{ + u32 reset; + + reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET); + return reset & AR724X_PCI_RESET_LINK_UP; +} static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t *value) @@ -46,6 +58,9 @@ static int ar724x_pci_read(struct pci_bu void __iomem *base; u32 data; + if (!ar724x_pci_link_up) + return PCIBIOS_DEVICE_NOT_FOUND; + if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; @@ -96,6 +111,9 @@ static int ar724x_pci_write(struct pci_b u32 data; int s; + if (!ar724x_pci_link_up) + return PCIBIOS_DEVICE_NOT_FOUND; + if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; @@ -280,6 +298,10 @@ int __init ar724x_pcibios_init(int irq) if (ar724x_pci_ctrl_base == NULL) goto err_unmap_devcfg; + ar724x_pci_link_up = ar724x_pci_check_link(); + if (!ar724x_pci_link_up) + pr_warn("ar724x: PCIe link is down\n"); + ar724x_pci_irq_init(irq); register_pci_controller(&ar724x_pci_controller); From cyril@ti.com Thu Sep 13 01:47:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Sep 2012 01:47:38 +0200 (CEST) Received: from devils.ext.ti.com ([198.47.26.153]:49657 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903508Ab2ILXrd (ORCPT ); Thu, 13 Sep 2012 01:47:33 +0200 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q8CNk0r8005534; Wed, 12 Sep 2012 18:46:00 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8CNk0Zs001064; Wed, 12 Sep 2012 18:46:00 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Wed, 12 Sep 2012 18:45:59 -0500 Received: from [158.218.103.130] (gtla0875269.am.dhcp.ti.com [158.218.103.130]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8CNjwdB007123; Wed, 12 Sep 2012 18:45:58 -0500 Message-ID: <50511EB5.800@ti.com> Date: Wed, 12 Sep 2012 19:45:57 -0400 From: Cyril Chemparathy User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:15.0) Gecko/20120907 Thunderbird/15.0.1 MIME-Version: 1.0 To: Rob Herring CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH] of: specify initrd location using 64-bit References: <1347465937-7056-1-git-send-email-cyril@ti.com> <5050EF3F.6030003@gmail.com> In-Reply-To: <5050EF3F.6030003@gmail.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34490 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cyril@ti.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1240 Lines: 42 On 9/12/2012 4:23 PM, Rob Herring wrote: > On 09/12/2012 11:05 AM, Cyril Chemparathy wrote: >> On some PAE architectures, the entire range of physical memory could reside >> outside the 32-bit limit. These systems need the ability to specify the >> initrd location using 64-bit numbers. >> >> This patch globally modifies the early_init_dt_setup_initrd_arch() function to >> use 64-bit numbers instead of the current unsigned long. > > S-o-B? > Sorry about that, will include in v2. [...] >> --- a/arch/arm/mm/init.c >> +++ b/arch/arm/mm/init.c >> @@ -76,7 +76,7 @@ static int __init parse_tag_initrd2(const struct tag *tag) >> __tagtable(ATAG_INITRD2, parse_tag_initrd2); >> >> #ifdef CONFIG_OF_FLATTREE >> -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) >> +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > > phys_initrd_start/size need to change too. Not sure about similar things > on other arches. > I've fixed phys_initrd_start (not size) in another patch, please see [1]. > Does u-boot need similar fixes? > We aren't there yet :-) We are currently running this platform without u-boot. [1] http://permalink.gmane.org/gmane.linux.kernel/1356713 -- Thanks - Cyril From bigeasy@linutronix.de Thu Sep 13 08:48:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Sep 2012 08:48:12 +0200 (CEST) Received: from www.linutronix.de ([62.245.132.108]:60940 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1902243Ab2IMGsD (ORCPT ); Thu, 13 Sep 2012 08:48:03 +0200 Received: from localhost ([127.0.0.1]) by Galois.linutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1TC3Ce-0005AW-GH; Thu, 13 Sep 2012 08:47:08 +0200 Message-ID: <5051816A.3050705@linutronix.de> Date: Thu, 13 Sep 2012 08:47:06 +0200 From: Sebastian Andrzej Siewior User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.6esrpre) Gecko/20120817 Icedove/10.0.6 MIME-Version: 1.0 To: Rob Herring CC: Cyril Chemparathy , linux-mips@linux-mips.org, x86@kernel.org, a-jacquiot@ti.com, mahesh@linux.vnet.ibm.com, linus.walleij@linaro.org, grant.likely@secretlab.ca, paul.gortmaker@windriver.com, paulus@samba.org, hpa@zytor.com, m.szyprowski@samsung.com, jonas@southpole.se, linux@arm.linux.org.uk, linux-c6x-dev@linux-c6x.org, nico@linaro.org, david.daney@cavium.com, mingo@redhat.com, Geert Uytterhoeven , benh@kernel.crashing.org, suzuki@in.ibm.com, linux@openrisc.net, arnd@arndb.de, microblaze-uclinux@itee.uq.edu.au, devicetree-discuss@lists.ozlabs.org, msalter@redhat.com, rob.herring@calxeda.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, blogic@openwrt.org, dhowells@redhat.com, monstr@monstr.eu, linux-kernel@vger.kernel.org, ralf@linux-mips.org, tj@kernel.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] of: specify initrd location using 64-bit References: <1347465937-7056-1-git-send-email-cyril@ti.com> <5050CE33.9060909@ti.com> <5050E965.5080405@linutronix.de> <505107DF.5020105@gmail.com> In-Reply-To: <505107DF.5020105@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 X-archive-position: 34491 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bigeasy@linutronix.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 665 Lines: 19 On 09/13/2012 12:08 AM, Rob Herring wrote: >> Geert is right here. If it is a physical address, it should be >> phys_addr_t. > > While generally true, for the DT specific code I think it should be a > fixed u64. The size of the address is defined by the FDT, not the > kernel. It is very likely we could have a FDT that specifies addresses > in 64-bit values, but then we boot a kernel is compiled for !LPAE. > phys_addr_t is currently sized based on LPAE setting. If your kernel is 32bit without PAE and your DTB address is >32ibt than you can't handle it. If you don't notice this in your dt code than you remap the wrong memory ioremap(). > > Rob > Sebastian From blogic@openwrt.org Thu Sep 13 10:26:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Sep 2012 10:27:01 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:55415 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903354Ab2IMI0y (ORCPT ); Thu, 13 Sep 2012 10:26:54 +0200 Message-ID: <50519848.6050901@openwrt.org> Date: Thu, 13 Sep 2012 10:24:40 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.6esrpre) Gecko/20120817 Icedove/10.0.6 MIME-Version: 1.0 To: akpm@linux-foundation.org CC: richard -rw- weinberger , Tracey Dent , linux-kernel@vger.kernel.org, Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [PATCH 1/1] Arch: mips: Delete Makefile.rej References: <1347490239-1351-1-git-send-email-tdent48227@gmail.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 34492 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 493 Lines: 16 On 13/09/12 01:15, richard -rw- weinberger wrote: > On Thu, Sep 13, 2012 at 12:50 AM, Tracey Dent wrote: >> Makefile.rej should not be there. That was introduced >> in commit 3fa68afc3d774bab1e91cbb3a3cdd1e36068ee95 . > Linus' tree does not contain such a commit id. > Hi, my bad .. its in linux-next (3fa68afc3d774bab1e91cbb3a3cdd1e36068ee95) and comes from the upstream-sfr tree on linux-mips.org i will talk to Ralf and fix it inside the lmo tree. Thanks, John From manuel.lauss@gmail.com Thu Sep 13 17:44:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Sep 2012 17:45:03 +0200 (CEST) Received: from mail-wg0-f43.google.com ([74.125.82.43]:51741 "EHLO mail-wg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903369Ab2IMPov (ORCPT ); Thu, 13 Sep 2012 17:44:51 +0200 Received: by wgbdr1 with SMTP id dr1so2126911wgb.24 for ; Thu, 13 Sep 2012 08:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=SiCPNJYzAtSfPQqJQv3IXDx/7CG6fZ2f2c4gufImy64=; b=rw6fd4oXfCU6Oh/UrYARwImVxKuQJQ3EoDRtBUMxEQn82pCAM1k0Z4L7yHVpcrT1z6 GQsKD5k/sA3LsT/01rUFq09dQBx6KsTbpnF/ybIWBKacilD8+zgXq2Sc+YxPyVnmXpsG ZY4BNFeX6odkgjeDnuTtBYAIS7rZWEneUYxPRTaKW+rvSZGR/tMtBMOFDhhHjI5Q6kOs Yc1wzoA/1IqZ/SZwROoWu0oFMJFtTd3dmhKJlBf1Nz7BtO27fOgnT70S9ThnJ3cLKy2m +Nu0Lih0c0BIFGo8bUCyW7OsNlKOTAW+Sx0yOtFtZuPJ9XDPbfUaEJuVzACVimknv/48 Ao1Q== Received: by 10.217.2.146 with SMTP id p18mr1494293wes.224.1347551086382; Thu, 13 Sep 2012 08:44:46 -0700 (PDT) Received: from flagship.roarinelk.net (188-22-148-144.adsl.highway.telekom.at. [188.22.148.144]) by mx.google.com with ESMTPS id dp8sm21220239wib.3.2012.09.13.08.44.42 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 13 Sep 2012 08:44:44 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: single kernel for DB1200/1300/1550 Date: Thu, 13 Sep 2012 17:44:39 +0200 Message-Id: <1347551079-20965-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.12 X-archive-position: 34493 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 44199 Lines: 1724 Combine support for the DB1200/PB1200, DB1300 and DB1550 boards into a single kernel image. defconfig-generated image verified on DB1200, DB1300 and DB1550. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/Kconfig | 22 +- arch/mips/alchemy/Platform | 22 +- arch/mips/alchemy/devboards/Makefile | 4 +- arch/mips/alchemy/devboards/db1200.c | 37 +-- arch/mips/alchemy/devboards/db1235.c | 84 ++++++ arch/mips/alchemy/devboards/db1300.c | 12 +- arch/mips/alchemy/devboards/db1550.c | 15 +- arch/mips/alchemy/devboards/platform.c | 9 +- arch/mips/boot/compressed/uart-alchemy.c | 4 - arch/mips/configs/db1200_defconfig | 170 ------------ arch/mips/configs/db1235_defconfig | 434 +++++++++++++++++++++++++++++++ arch/mips/configs/db1300_defconfig | 391 ---------------------------- arch/mips/configs/db1550_defconfig | 285 -------------------- 13 files changed, 548 insertions(+), 941 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1235.c delete mode 100644 arch/mips/configs/db1200_defconfig create mode 100644 arch/mips/configs/db1235_defconfig delete mode 100644 arch/mips/configs/db1300_defconfig delete mode 100644 arch/mips/configs/db1550_defconfig diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 0faaab2..b4929b9 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -36,25 +36,9 @@ config MIPS_DB1000 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_DB1200 - bool "Alchemy DB1200/PB1200 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_COHERENT - select MIPS_DISABLE_OBSOLETE_IDE - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - -config MIPS_DB1300 - bool "NetLogic DB1300 board" - select ALCHEMY_GPIOINT_AU1300 - select DMA_COHERENT - select MIPS_DISABLE_OBSOLETE_IDE - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - -config MIPS_DB1550 - bool "Alchemy DB1550 board" - select ALCHEMY_GPIOINT_AU1000 +config MIPS_DB1235 + bool "Alchemy DB1200/PB1200/DB1300/DB1550 boards" + select ARCH_REQUIRE_GPIOLIB select HW_HAS_PCI select DMA_COHERENT select MIPS_DISABLE_OBSOLETE_IDE diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 7956274..942c580 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -30,25 +30,11 @@ cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 # -# AMD Alchemy Db1550 eval board +# AMD Alchemy Db1200/Pb1200/Db1550/Db1300 eval boards # -platform-$(CONFIG_MIPS_DB1550) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 - -# -# AMD Alchemy Db1200/Pb1200 eval boards -# -platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 - -# -# NetLogic DBAu1300 development platform -# -platform-$(CONFIG_MIPS_DB1300) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 +platform-$(CONFIG_MIPS_DB1235) += alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1235) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1235) += 0xffffffff80100000 # # 4G-Systems MTX-1 "MeshCube" wireless router diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index c9e747d..f8a9624 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -8,6 +8,4 @@ obj-$(CONFIG_MIPS_PB1100) += pb1100.o obj-$(CONFIG_MIPS_PB1500) += pb1500.o obj-$(CONFIG_MIPS_PB1550) += pb1550.o obj-$(CONFIG_MIPS_DB1000) += db1000.o -obj-$(CONFIG_MIPS_DB1200) += db1200.o -obj-$(CONFIG_MIPS_DB1300) += db1300.o -obj-$(CONFIG_MIPS_DB1550) += db1550.o +obj-$(CONFIG_MIPS_DB1235) += db1235.o db1200.o db1300.o db1550.o diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c index bf22484..299b7d2 100644 --- a/arch/mips/alchemy/devboards/db1200.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -45,25 +45,9 @@ #include "platform.h" -static const char *board_type_str(void) -{ - switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { - case BCSR_WHOAMI_PB1200_DDR1: - case BCSR_WHOAMI_PB1200_DDR2: - return "PB1200"; - case BCSR_WHOAMI_DB1200: - return "DB1200"; - default: - return "(unknown)"; - } -} +const char *get_system_type(void); -const char *get_system_type(void) -{ - return board_type_str(); -} - -static int __init detect_board(void) +static int __init db1200_detect_board(void) { int bid; @@ -96,19 +80,17 @@ static int __init detect_board(void) return 1; /* it's neither */ } -void __init board_setup(void) +int __init db1200_board_setup(void) { unsigned long freq0, clksrc, div, pfc; unsigned short whoami; - if (detect_board()) { - printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n"); - return; - } + if (db1200_detect_board()) + return -ENODEV; whoami = bcsr_read(BCSR_WHOAMI); printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" - " Board-ID %d Daughtercard ID %d\n", board_type_str(), + " Board-ID %d Daughtercard ID %d\n", get_system_type(), (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); /* SMBus/SPI on PSC0, Audio on PSC1 */ @@ -138,6 +120,8 @@ void __init board_setup(void) clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC); wmb(); + + return 0; } /******************************************************************************/ @@ -796,7 +780,7 @@ static int __init pb1200_res_fixup(void) return 0; } -static int __init db1200_dev_init(void) +int __init db1200_dev_setup(void) { unsigned long pfc; unsigned short sw; @@ -846,7 +830,7 @@ static int __init db1200_dev_init(void) gpio_request(215, "otg-vbus"); gpio_direction_output(215, 1); - printk(KERN_INFO "%s device configuration:\n", board_type_str()); + printk(KERN_INFO "%s device configuration:\n", get_system_type()); sw = bcsr_read(BCSR_SWITCHES); if (sw & BCSR_SWITCHES_DIP_8) { @@ -922,4 +906,3 @@ static int __init db1200_dev_init(void) return 0; } -device_initcall(db1200_dev_init); diff --git a/arch/mips/alchemy/devboards/db1235.c b/arch/mips/alchemy/devboards/db1235.c new file mode 100644 index 0000000..15003eb --- /dev/null +++ b/arch/mips/alchemy/devboards/db1235.c @@ -0,0 +1,84 @@ +/* + * DB1200/PB1200 / DB1550 / DB1300 board support. + * + * These 4 boards can reliably be supported in a single kernel image. + */ + +#include +#include + +int __init db1200_board_setup(void); +int __init db1200_dev_setup(void); +int __init db1300_board_setup(void); +int __init db1300_dev_setup(void); +int __init db1550_board_setup(void); +int __init db1550_dev_setup(void); +int __init db1550_pci_setup(void); + +static const char *board_type_str(void) +{ + switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { + case BCSR_WHOAMI_PB1200_DDR1: + case BCSR_WHOAMI_PB1200_DDR2: + return "PB1200"; + case BCSR_WHOAMI_DB1200: + return "DB1200"; + case BCSR_WHOAMI_DB1300: + return "DB1300"; + case BCSR_WHOAMI_DB1550: + return "DB1550"; + default: + return "(unknown)"; + } +} + +const char *get_system_type(void) +{ + return board_type_str(); +} + +void __init board_setup(void) +{ + int ret; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1550: + ret = db1550_board_setup(); + break; + case ALCHEMY_CPU_AU1200: + ret = db1200_board_setup(); + break; + case ALCHEMY_CPU_AU1300: + ret = db1300_board_setup(); + break; + default: + pr_err("unsupported CPU on board\n"); + ret = -ENODEV; + } + if (ret) + panic("cannot initialize board support\n"); +} + +int __init db1235_arch_init(void) +{ + if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1550) + return db1550_pci_setup(); + return 0; +} +arch_initcall(db1235_arch_init); + +int __init db1235_dev_init(void) +{ + switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { + case BCSR_WHOAMI_PB1200_DDR1: + case BCSR_WHOAMI_PB1200_DDR2: + case BCSR_WHOAMI_DB1200: + return db1200_dev_setup(); + case BCSR_WHOAMI_DB1300: + return db1300_dev_setup(); + case BCSR_WHOAMI_DB1550: + return db1550_dev_setup(); + } + return 0; +} +device_initcall(db1235_dev_init); diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index c56e024..cdf37cb 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -110,11 +110,6 @@ static void __init db1300_gpio_config(void) au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); } -char *get_system_type(void) -{ - return "DB1300"; -} - /**********************************************************************/ static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, @@ -701,7 +696,7 @@ static struct platform_device *db1300_dev[] __initdata = { &db1300_sndi2s_dev, }; -static int __init db1300_device_init(void) +int __init db1300_dev_setup(void) { int swapped, cpldirq; @@ -758,10 +753,9 @@ static int __init db1300_device_init(void) return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); } -device_initcall(db1300_device_init); -void __init board_setup(void) +int __init db1300_board_setup(void) { unsigned short whoami; @@ -779,4 +773,6 @@ void __init board_setup(void) alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); + + return 0; } diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c index 9eb7906..7664beed 100644 --- a/arch/mips/alchemy/devboards/db1550.c +++ b/arch/mips/alchemy/devboards/db1550.c @@ -26,12 +26,6 @@ #include #include "platform.h" - -const char *get_system_type(void) -{ - return "DB1550"; -} - static void __init db1550_hw_setup(void) { void __iomem *base; @@ -61,7 +55,7 @@ static void __init db1550_hw_setup(void) alchemy_gpio_direction_output(202, 0); /* green led on */ } -void __init board_setup(void) +int __init db1550_board_setup(void) { unsigned short whoami; @@ -74,6 +68,7 @@ void __init board_setup(void) (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); db1550_hw_setup(); + return 0; } /*****************************************************************************/ @@ -430,13 +425,12 @@ static struct platform_device *db1550_devs[] __initdata = { }; /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ -static int __init db1550_pci_init(void) +int __init db1550_pci_setup(void) { return platform_device_register(&db1550_pci_host_dev); } -arch_initcall(db1550_pci_init); -static int __init db1550_dev_init(void) +int __init db1550_dev_setup(void) { int swapped; @@ -492,4 +486,3 @@ static int __init db1550_dev_init(void) return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs)); } -device_initcall(db1550_dev_init); diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c index f39042e..8df86eb 100644 --- a/arch/mips/alchemy/devboards/platform.c +++ b/arch/mips/alchemy/devboards/platform.c @@ -36,11 +36,10 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { -#ifdef CONFIG_MIPS_DB1300 - alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); -#else - alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); -#endif + if (alchemy_get_cputype() == ALCHEMY_CPU_AU1300) + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); + else + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); } diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c index 3112df8..4bee55b9 100644 --- a/arch/mips/boot/compressed/uart-alchemy.c +++ b/arch/mips/boot/compressed/uart-alchemy.c @@ -2,9 +2,5 @@ void putc(char c) { -#ifdef CONFIG_MIPS_DB1300 - alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); -#else alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); -#endif } diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig deleted file mode 100644 index 1f69249..0000000 --- a/arch/mips/configs/db1200_defconfig +++ /dev/null @@ -1,170 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_DB1200=y -CONFIG_KSM=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1200" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_UB=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_BLK_DEV_IDECD=y -CONFIG_IDE_TASK_IOCTL=y -# CONFIG_IDE_PROC_FS is not set -CONFIG_BLK_DEV_IDE_AU1XXX=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=2 -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_AU1550=y -CONFIG_SPI=y -CONFIG_SPI_AU1550=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_SENSORS_ADM1025=y -CONFIG_SENSORS_LM70=y -CONFIG_FB=y -CONFIG_FB_AU1200=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_8x16=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_MIPS is not set -# CONFIG_SND_USB is not set -# CONFIG_SND_PCMCIA is not set -CONFIG_SND_SOC=y -CONFIG_SND_SOC_AU1XPSC=y -CONFIG_SND_SOC_DB1200=y -CONFIG_HIDRAW=y -CONFIG_USB_HIDDEV=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_OHCI_HCD=y -CONFIG_MMC=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_MMC_AU1X=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=y -CONFIG_VFAT_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_EFI_PARTITION=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyS0,115200" -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/arch/mips/configs/db1235_defconfig b/arch/mips/configs/db1235_defconfig new file mode 100644 index 0000000..c48998f --- /dev/null +++ b/arch/mips/configs/db1235_defconfig @@ -0,0 +1,434 @@ +CONFIG_MIPS_ALCHEMY=y +CONFIG_MIPS_DB1235=y +CONFIG_COMPACTION=y +CONFIG_KSM=y +CONFIG_HZ_100=y +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="-db1235" +CONFIG_KERNEL_LZMA=y +CONFIG_DEFAULT_HOSTNAME="db1235" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_FHANDLE=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_AUDIT=y +CONFIG_AUDIT_LOGINUID_IMMUTABLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NAMESPACES=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_JUMP_LABEL=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_LDM_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_PCI=y +CONFIG_PCCARD=y +CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_XFRM_USER=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IPGRE=y +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_UDP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=y +CONFIG_TCP_CONG_HYBLA=y +CONFIG_TCP_CONG_SCALABLE=y +CONFIG_TCP_CONG_LP=y +CONFIG_TCP_CONG_VENO=y +CONFIG_TCP_CONG_YEAH=y +CONFIG_TCP_CONG_ILLINOIS=y +CONFIG_DEFAULT_HYBLA=y +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_QUEUE_CT=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_HMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_LED=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TEE=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CLUSTER=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_CPU=y +CONFIG_NETFILTER_XT_MATCH_DCCP=y +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_NFACCT=y +CONFIG_NETFILTER_XT_MATCH_OSF=y +CONFIG_NETFILTER_XT_MATCH_OWNER=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_RATEEST=y +CONFIG_NETFILTER_XT_MATCH_REALM=y +CONFIG_NETFILTER_XT_MATCH_RECENT=y +CONFIG_NETFILTER_XT_MATCH_SCTP=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_CLUSTERIP=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_EUI64=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_TARGET_HL=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_802_3=y +CONFIG_BRIDGE_EBT_AMONG=y +CONFIG_BRIDGE_EBT_ARP=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_IP6=y +CONFIG_BRIDGE_EBT_LIMIT=y +CONFIG_BRIDGE_EBT_MARK=y +CONFIG_BRIDGE_EBT_PKTTYPE=y +CONFIG_BRIDGE_EBT_STP=y +CONFIG_BRIDGE_EBT_VLAN=y +CONFIG_BRIDGE_EBT_ARPREPLY=y +CONFIG_BRIDGE_EBT_DNAT=y +CONFIG_BRIDGE_EBT_MARK_T=y +CONFIG_BRIDGE_EBT_REDIRECT=y +CONFIG_BRIDGE_EBT_SNAT=y +CONFIG_BRIDGE_EBT_LOG=y +CONFIG_BRIDGE_EBT_NFLOG=y +CONFIG_L2TP=y +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_LLC2=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_HFSC=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_RED=y +CONFIG_NET_SCH_SFB=y +CONFIG_NET_SCH_SFQ=y +CONFIG_NET_SCH_TEQL=y +CONFIG_NET_SCH_TBF=y +CONFIG_NET_SCH_GRED=y +CONFIG_NET_SCH_DSMARK=y +CONFIG_NET_SCH_NETEM=y +CONFIG_NET_SCH_DRR=y +CONFIG_NET_SCH_MQPRIO=y +CONFIG_NET_SCH_CHOKE=y +CONFIG_NET_SCH_QFQ=y +CONFIG_NET_SCH_CODEL=y +CONFIG_NET_SCH_FQ_CODEL=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_SCH_PLUG=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_TCINDEX=y +CONFIG_NET_CLS_ROUTE4=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=y +CONFIG_NET_CLS_RSVP6=y +CONFIG_NET_CLS_FLOW=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_NET_ACT_NAT=y +CONFIG_NET_ACT_PEDIT=y +CONFIG_NET_ACT_SIMP=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_NET_ACT_CSUM=y +CONFIG_NET_CLS_IND=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y +CONFIG_CFG80211=y +CONFIG_CFG80211_CERTIFICATION_ONUS=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE_AU1XXX=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_ATA=y +CONFIG_PATA_HPT37X=y +CONFIG_PATA_PCMCIA=y +CONFIG_PATA_PLATFORM=y +CONFIG_NETDEVICES=y +CONFIG_MIPS_AU1X00_ENET=y +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_AMD_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_RT2X00=y +CONFIG_RT73USB=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_WM97XX=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_TTY_PRINTK=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_AU1550=y +CONFIG_SPI=y +CONFIG_SPI_AU1550=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_ADM1025=y +CONFIG_SENSORS_LM70=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_DB1200=y +CONFIG_HIDRAW=y +CONFIG_UHID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_AU1X=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AU1XXX=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_XFS_FS=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_CMODE_FAVOURLZO=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_VMAC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_FCRYPT=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_SALSA20=y +CONFIG_CRYPTO_SEED=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ZLIB=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig deleted file mode 100644 index 3590ab5..0000000 --- a/arch/mips/configs/db1300_defconfig +++ /dev/null @@ -1,391 +0,0 @@ -CONFIG_MIPS=y -CONFIG_MIPS_ALCHEMY=y -CONFIG_ALCHEMY_GPIOINT_AU1300=y -CONFIG_MIPS_DB1300=y -CONFIG_SOC_AU1300=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -CONFIG_CEVT_R4K_LIB=y -CONFIG_CSRC_R4K_LIB=y -CONFIG_DMA_COHERENT=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y -CONFIG_GENERIC_GPIO=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_CPU_MIPS32_R1=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPSR1=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_32BIT=y -CONFIG_PAGE_SIZE_4KB=y -CONFIG_FORCE_MAX_ZONEORDER=11 -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -CONFIG_64BIT_PHYS_ADDR=y -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_COMPACTION=y -CONFIG_MIGRATION=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NEED_PER_CPU_KM=y -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_HZ_100=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=100 -CONFIG_PREEMPT_NONE=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y -CONFIG_HAVE_IRQ_WORK=y -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_CROSS_COMPILE="" -CONFIG_LOCALVERSION="-db1300" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_KERNEL_LZMA=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -CONFIG_FHANDLE=y -CONFIG_HAVE_GENERIC_HARDIRQS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=19 -CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_IPC_NS=y -CONFIG_USER_NS=y -CONFIG_PID_NS=y -CONFIG_NET_NS=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EXPERT=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_EMBEDDED=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_SLAB=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_DMA_ATTRS=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -CONFIG_IOSCHED_NOOP=y -CONFIG_DEFAULT_NOOP=y -CONFIG_DEFAULT_IOSCHED="noop" -# CONFIG_UNINLINE_SPIN_UNLOCK is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -CONFIG_INLINE_READ_UNLOCK=y -CONFIG_INLINE_READ_UNLOCK_IRQ=y -CONFIG_INLINE_WRITE_UNLOCK=y -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -CONFIG_MMU=y -CONFIG_PCCARD=y -CONFIG_PCMCIA=y -CONFIG_PCMCIA_LOAD_CIS=y -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_BINFMT_ELF=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_TRAD_SIGNALS=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_INET_TUNNEL=y -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_IPV6=y -CONFIG_INET6_XFRM_MODE_TRANSPORT=y -CONFIG_INET6_XFRM_MODE_TUNNEL=y -CONFIG_INET6_XFRM_MODE_BEET=y -CONFIG_IPV6_SIT=y -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_IDS=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_BLK_DEV=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_UB=y -CONFIG_HAVE_IDE=y -CONFIG_IDE=y -CONFIG_IDE_GD=y -CONFIG_IDE_GD_ATA=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_IDE_TASK_IOCTL=y -CONFIG_IDE_PROC_FS=y -CONFIG_BLK_DEV_PLATFORM=y -CONFIG_SCSI_MOD=y -CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_PHYLIB=y -CONFIG_SMSC_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_WM97XX=y -CONFIG_TOUCHSCREEN_WM9712=y -CONFIG_TOUCHSCREEN_WM9713=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=y -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_UNIX98_PTYS=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_SMBUS=y -CONFIG_I2C_AU1550=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_AU1550=y -CONFIG_SPI_BITBANG=y -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -CONFIG_HWMON=y -CONFIG_HWMON_VID=y -CONFIG_SENSORS_ADM1025=y -CONFIG_FB=y -CONFIG_FB_AU1200=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_ACORN_8x8=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -CONFIG_SND_HRTIMER=y -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_VERBOSE_PROCFS=y -CONFIG_SND_VERBOSE_PRINTK=y -CONFIG_SND_VMASTER=y -CONFIG_SND_AC97_CODEC=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_CACHE_LZO=y -CONFIG_SND_SOC_AC97_BUS=y -CONFIG_SND_SOC_AU1XPSC=y -CONFIG_SND_SOC_AU1XPSC_I2S=y -CONFIG_SND_SOC_AU1XPSC_AC97=y -CONFIG_SND_SOC_DB1300=y -CONFIG_SND_SOC_I2C_AND_SPI=y -CONFIG_SND_SOC_WM8731=y -CONFIG_SND_SOC_WM9712=y -CONFIG_AC97_BUS=y -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -CONFIG_HIDRAW=y -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -CONFIG_RTC_INTF_DEV_UIE_EMUL=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -CONFIG_FS_POSIX_ACL=y -CONFIG_EXPORTFS=y -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_GENERIC_ACL=y -CONFIG_FAT_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TMPFS_XATTR=y -CONFIG_MISC_FILESYSTEMS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -CONFIG_JFFS2_RUBIN=y -CONFIG_JFFS2_CMODE_PRIORITY=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_PRINTK_TIME=y -CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACING_SUPPORT=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_EARLY_PRINTK=y -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="video=au1200fb:panel:bs console=tty console=ttyS2,115200" -CONFIG_DEBUG_ZBOOT=y -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_CRYPTO=y -CONFIG_BITREVERSE=y -CONFIG_CRC32=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_XZ_DEC=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y -CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig deleted file mode 100644 index 36cda27..0000000 --- a/arch/mips/configs/db1550_defconfig +++ /dev/null @@ -1,285 +0,0 @@ -CONFIG_MIPS=y -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_DB1550=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -CONFIG_GENERIC_GPIO=y -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -CONFIG_HZ=100 -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="-db1550" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_KERNEL_LZMA=y -CONFIG_DEFAULT_HOSTNAME="db1550" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -CONFIG_FHANDLE=y -CONFIG_AUDIT=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=18 -CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_IPC_NS=y -CONFIG_USER_NS=y -CONFIG_PID_NS=y -CONFIG_NET_NS=y -CONFIG_EXPERT=y -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_EMBEDDED=y -CONFIG_PCI_QUIRKS=y -CONFIG_SLAB=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_IOSCHED_NOOP=y -CONFIG_DEFAULT_NOOP=y -CONFIG_DEFAULT_IOSCHED="noop" -CONFIG_PCI=y -CONFIG_PCCARD=y -CONFIG_PCMCIA=y -CONFIG_PCMCIA_LOAD_CIS=y -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_BINFMT_ELF=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_BINFMT_MISC=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_PM_SLEEP=y -CONFIG_PM_RUNTIME=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_INET_TUNNEL=y -CONFIG_INET_LRO=y -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_IPV6=y -CONFIG_INET6_XFRM_MODE_TRANSPORT=y -CONFIG_INET6_XFRM_MODE_TUNNEL=y -CONFIG_INET6_XFRM_MODE_BEET=y -CONFIG_IPV6_SIT=y -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_DNS_RESOLVER=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_MTD=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_IDS=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_MISC_DEVICES=y -CONFIG_EEPROM_AT24=y -CONFIG_SCSI_MOD=y -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_ATA=y -CONFIG_ATA_SFF=y -CONFIG_ATA_BMDMA=y -CONFIG_PATA_HPT37X=y -CONFIG_PATA_PCMCIA=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_PHYLIB=y -CONFIG_NET_ETHERNET=y -CONFIG_MIPS_AU1X00_ENET=y -CONFIG_NET_PCMCIA=y -CONFIG_PCMCIA_3C589=y -CONFIG_PCMCIA_PCNET=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_DEVPTS_MULTIPLE_INSTANCES=y -CONFIG_DEVKMEM=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_DEVPORT=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_AU1550=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_AU1550=y -CONFIG_SPI_BITBANG=y -CONFIG_HWMON=y -CONFIG_SENSORS_ADM1025=y -CONFIG_SENSORS_LM70=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -CONFIG_SND_VMASTER=y -CONFIG_SND_AC97_CODEC=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_AC97_BUS=y -CONFIG_SND_SOC_AU1XPSC=y -CONFIG_SND_SOC_AU1XPSC_I2S=y -CONFIG_SND_SOC_AU1XPSC_AC97=y -CONFIG_SND_SOC_DB1200=y -CONFIG_SND_SOC_I2C_AND_SPI=y -CONFIG_SND_SOC_AC97_CODEC=y -CONFIG_SND_SOC_WM8731=y -CONFIG_SND_SOC_WM9712=y -CONFIG_AC97_BUS=y -CONFIG_USB=y -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_USE_FOR_EXT23=y -CONFIG_EXT4_FS_XATTR=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_JBD2=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_EXPORTFS=y -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=y -CONFIG_MISC_FILESYSTEMS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -CONFIG_JFFS2_RUBIN=y -CONFIG_JFFS2_CMODE_PRIORITY=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_ZLIB=y -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_PNFS_FILE_LAYOUT=y -CONFIG_PNFS_BLOCK=y -CONFIG_ROOT_NFS=y -CONFIG_NFS_USE_KERNEL_DNS=y -CONFIG_NFS_USE_NEW_IDMAPPER=y -CONFIG_NFSD=y -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_SUNRPC_BACKCHANNEL=y -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 -CONFIG_FRAME_WARN=1024 -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="noirqdebug console=ttyS0,115200 root=/dev/sda1 rootfstype=ext4" -CONFIG_KEYS=y -CONFIG_SECURITYFS=y -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_BITREVERSE=y -CONFIG_CRC16=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_AUDIT_GENERIC=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_BCH=y -CONFIG_NLATTR=y -- 1.7.12 From macro@codesourcery.com Thu Sep 13 22:23:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Sep 2012 22:23:55 +0200 (CEST) Received: from relay1.mentorg.com ([192.94.38.131]:36455 "EHLO relay1.mentorg.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903378Ab2IMUXp (ORCPT ); Thu, 13 Sep 2012 22:23:45 +0200 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1TCFwn-0006fK-Tp from Maciej_Rozycki@mentor.com ; Thu, 13 Sep 2012 13:23:37 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 13 Sep 2012 13:23:37 -0700 Received: from [172.30.7.121] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Thu, 13 Sep 2012 21:23:35 +0100 Date: Thu, 13 Sep 2012 21:23:25 +0100 From: "Maciej W. Rozycki" To: CC: Ralf Baechle Subject: [PATCH] Malta: Remove RTC Data Mode bootstrap breakage Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-OriginalArrivalTime: 13 Sep 2012 20:23:37.0786 (UTC) FILETIME=[A82499A0:01CD91ED] X-archive-position: 34494 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@codesourcery.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 1865 Lines: 46 YAMON requires and enforces the RTC Data Mode (Register B, DM bit) to binary, that is the bit is set every time the board goes through the firmware bootstrap sequence. Likewise its calendar manipulation commands interpret or set the RTC registers unconditionally as binary, never actually checking what the value of the DM bit is, under the (correct) assumption that it has been previously set, to indicate the binary mode. A change to Linux a while ago however introduced a platform-specific tweak that clears that bit and therefore forces the data mode to BCD. This causes clock corruption and misinterpretation that has to be fixed up by user-mode tools in system startup scripts as the initial clock is often incorrect according to the BCD interpretation forced. This change removes the hack; a comment included refers to alarm code, but even if it was broken at one point by requiring the BCD mode, it should have been trivially corrected and even if not, given how rarely the alarm feature is used, that was not really a reasonable justification to break the system clock that is indeed used by virtually everything. And either way the alarm code has been since fixed anyway. Signed-off-by: Maciej W. Rozycki --- Please apply -- this ends a long battle trying to track down where the annoying clock corruption has come from. Maciej linux-malta-rtc.diff diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c index 4c35301..80562b8 100644 --- a/arch/mips/mti-malta/malta-platform.c +++ b/arch/mips/mti-malta/malta-platform.c @@ -138,11 +138,6 @@ static int __init malta_add_devices(void) if (err) return err; - /* - * Set RTC to BCD mode to support current alarm code. - */ - CMOS_WRITE(CMOS_READ(RTC_CONTROL) & ~RTC_DM_BINARY, RTC_CONTROL); - return 0; } From robherring2@gmail.com Thu Sep 13 23:03:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Sep 2012 23:03:04 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:37187 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903378Ab2IMVDA (ORCPT ); Thu, 13 Sep 2012 23:03:00 +0200 Received: by obbta17 with SMTP id ta17so5477458obb.36 for ; Thu, 13 Sep 2012 14:02:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=UNpuo3wZgbfCHiGgUVSRyXc93sb+xRVJqxG9ogQd5BQ=; b=TRKxmPbvmPOqA6YmmXJgKiImJTk1szN08aOOIxokTJfOPJR9ViRzB1mr5minZ8Y/yZ KIdtsxywn2o8pCPID1FLGRuLnlIJOnMGubEtsdrVGpyGuLKYZM76xDQAWj0scmbPu2cs bmHzVR3sbVQ0hYpVAjm1sH6ck85mih9tDxeQVZTZZpjUXECuFR1o+hsv9CWqFXoYc2vb 2xNe2qf6hkAsNNXAClKs1Zyp3D5iF4XiH41TMVAprlvlEoMkaVDv5bdnsmlm/2AbbnG0 acKvLswaSjS67hGRTjTLOoHk9SnL5bv9jNPK9kCm/v70VWQ2RELtcVirLSHpUD41i4Bv 6erw== Received: by 10.60.154.198 with SMTP id vq6mr721272oeb.20.1347570173648; Thu, 13 Sep 2012 14:02:53 -0700 (PDT) Received: from [10.10.10.90] ([173.226.190.126]) by mx.google.com with ESMTPS id l10sm20414669oeb.13.2012.09.13.14.02.50 (version=SSLv3 cipher=OTHER); Thu, 13 Sep 2012 14:02:52 -0700 (PDT) Message-ID: <505249F9.7050201@gmail.com> Date: Thu, 13 Sep 2012 16:02:49 -0500 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Sebastian Andrzej Siewior CC: Cyril Chemparathy , linux-mips@linux-mips.org, x86@kernel.org, a-jacquiot@ti.com, mahesh@linux.vnet.ibm.com, linus.walleij@linaro.org, grant.likely@secretlab.ca, paul.gortmaker@windriver.com, paulus@samba.org, hpa@zytor.com, m.szyprowski@samsung.com, jonas@southpole.se, linux@arm.linux.org.uk, linux-c6x-dev@linux-c6x.org, nico@linaro.org, david.daney@cavium.com, mingo@redhat.com, Geert Uytterhoeven , benh@kernel.crashing.org, suzuki@in.ibm.com, linux@openrisc.net, arnd@arndb.de, microblaze-uclinux@itee.uq.edu.au, devicetree-discuss@lists.ozlabs.org, msalter@redhat.com, rob.herring@calxeda.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, blogic@openwrt.org, dhowells@redhat.com, monstr@monstr.eu, linux-kernel@vger.kernel.org, ralf@linux-mips.org, tj@kernel.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] of: specify initrd location using 64-bit References: <1347465937-7056-1-git-send-email-cyril@ti.com> <5050CE33.9060909@ti.com> <5050E965.5080405@linutronix.de> <505107DF.5020105@gmail.com> <5051816A.3050705@linutronix.de> In-Reply-To: <5051816A.3050705@linutronix.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34495 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1266 Lines: 27 On 09/13/2012 01:47 AM, Sebastian Andrzej Siewior wrote: > On 09/13/2012 12:08 AM, Rob Herring wrote: >>> Geert is right here. If it is a physical address, it should be >>> phys_addr_t. >> >> While generally true, for the DT specific code I think it should be a >> fixed u64. The size of the address is defined by the FDT, not the >> kernel. It is very likely we could have a FDT that specifies addresses >> in 64-bit values, but then we boot a kernel is compiled for !LPAE. >> phys_addr_t is currently sized based on LPAE setting. > > If your kernel is 32bit without PAE and your DTB address is >32ibt than > you can't handle it. If you don't notice this in your dt code than you > remap the wrong memory ioremap(). The size of the initrd fields are set by #address-cells properties and determined when you create the dtb. The address to load the initrd is decided by the bootloader/user and set at that point later in time. The dtb should not be tied to the kernel you are booting. Obviously, if you want to boot a non-PAE kernel, everything has to be placed at <4GB. I can boot i386 and i386-pae kernels on an i386-pae machines. I expect to generally be able to do that on ARM. Perhaps some SOCs like this one will not allow that, it is not always true. Rob From akpm@linux-foundation.org Fri Sep 14 01:05:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 01:05:20 +0200 (CEST) Received: from mail.linuxfoundation.org ([140.211.169.12]:34724 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903384Ab2IMXFQ (ORCPT ); Fri, 14 Sep 2012 01:05:16 +0200 Received: from akpm.mtv.corp.google.com (216-239-45-4.google.com [216.239.45.4]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id C8D9D9E3; Thu, 13 Sep 2012 23:05:07 +0000 (UTC) Date: Thu, 13 Sep 2012 16:05:06 -0700 From: Andrew Morton To: "Kirill A. Shutemov" Cc: linux-mm@kvack.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Andi Kleen , Tim Chen , Alex Shi , Jan Beulich , Robert Richter , Andy Lutomirski , Andrea Arcangeli , Johannes Weiner , Hugh Dickins , KAMEZAWA Hiroyuki , Mel Gorman , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org Subject: Re: [PATCH v4 0/8] Avoid cache trashing on clearing huge/gigantic page Message-Id: <20120913160506.d394392a.akpm@linux-foundation.org> In-Reply-To: <1345470757-12005-1-git-send-email-kirill.shutemov@linux.intel.com> References: <1345470757-12005-1-git-send-email-kirill.shutemov@linux.intel.com> X-Mailer: Sylpheed 3.0.2 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 34496 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 933 Lines: 19 On Mon, 20 Aug 2012 16:52:29 +0300 "Kirill A. Shutemov" wrote: > Clearing a 2MB huge page will typically blow away several levels of CPU > caches. To avoid this only cache clear the 4K area around the fault > address and use a cache avoiding clears for the rest of the 2MB area. > > This patchset implements cache avoiding version of clear_page only for > x86. If an architecture wants to provide cache avoiding version of > clear_page it should to define ARCH_HAS_USER_NOCACHE to 1 and implement > clear_page_nocache() and clear_user_highpage_nocache(). Patchset looks nice to me, but the changelogs are terribly short of performance measurements. For this sort of change I do think it is important that pretty exhaustive testing be performed, and that the results (or a readable summary of them) be shown. And that testing should be designed to probe for slowdowns, not just the speedups! From ralf@linux-mips.org Fri Sep 14 01:08:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 01:08:06 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:56569 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903386Ab2IMXIC (ORCPT ); Fri, 14 Sep 2012 01:08:02 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8DN80rB004540; Fri, 14 Sep 2012 01:08:00 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8DN80nA004539; Fri, 14 Sep 2012 01:08:00 +0200 Date: Fri, 14 Sep 2012 01:08:00 +0200 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH] MIPS: Alchemy: single kernel for DB1200/1300/1550 Message-ID: <20120913230800.GC19592@linux-mips.org> References: <1347551079-20965-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1347551079-20965-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34497 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 320 Lines: 12 On Thu, Sep 13, 2012 at 05:44:39PM +0200, Manuel Lauss wrote: > Combine support for the DB1200/PB1200, DB1300 and DB1550 boards into > a single kernel image. > > defconfig-generated image verified on DB1200, DB1300 and DB1550. Thanks, queued. What's the hardware difference between DB1200 and PB1200 boards? Ralf From manuel.lauss@gmail.com Fri Sep 14 14:47:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 14:47:30 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:34379 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903385Ab2INMrW (ORCPT ); Fri, 14 Sep 2012 14:47:22 +0200 Received: by bkcji2 with SMTP id ji2so1202202bkc.36 for ; Fri, 14 Sep 2012 05:47:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=AlNzf0c6jXpZEfFmsz6a5hMkpV4IAiry7rNXoT8d1wE=; b=h5lCeEOfGkcZ4/+ReFjqQVnYy2mwiTrlG7KveTHi4+I+G4qBOFROQ6XvGA9AOMwYyT 3fHMCF+6vemM5lTe+NfoHOJRjAevw7N9iJWqthKHR8UeEKTe5E94VRVriukxygXeBFfr IGVkW2c3ELcD3/kcG6+nHqNAnntwrMgu9BnBphf80pQfddsSVDZm3P+c/yS6UPSKxtyK P3Fktpcu1Uwk4k7kaiAiHVkaHC0ClxrQ1q4bGwJ566aLvVGgOqlgbe/sCiSfjzOX9bvD t3+d3LxngxlijIyuPxlTpFWGRqQjfSCwBk8bdB8bdxGHmDfXjMe9YroD4dw7X4IQQeTc Yhkw== Received: by 10.204.8.65 with SMTP id g1mr1088826bkg.50.1347626836703; Fri, 14 Sep 2012 05:47:16 -0700 (PDT) Received: from flagship.roarinelk.net (188-22-1-39.adsl.highway.telekom.at. [188.22.1.39]) by mx.google.com with ESMTPS id t23sm1040667bks.4.2012.09.14.05.47.14 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 14 Sep 2012 05:47:15 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: merge PB1550 support into DB1550 code Date: Fri, 14 Sep 2012 14:47:10 +0200 Message-Id: <1347626830-15237-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.12 X-archive-position: 34499 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 23846 Lines: 791 The PB1550 is more or less a DB1550 without the PCI IDE controller, a more complicated (read: configurable) Flash setup and some other minor changes. Like the DB1550 it can be automatically detected by reading the CPLD ID register bits. This patch adds PB1550 detection and setup to the DB1550 code. Signed-off-by: Manuel Lauss --- Tested only on the DB1550 since I don't have and don't know anyone with a PB1550. Applies on top of the previos db1200/1300/1550 merge patch. arch/mips/alchemy/Kconfig | 11 +- arch/mips/alchemy/devboards/Makefile | 1 - arch/mips/alchemy/devboards/db1235.c | 16 ++- arch/mips/alchemy/devboards/db1550.c | 181 +++++++++++++++++++++----- arch/mips/alchemy/devboards/pb1550.c | 244 ----------------------------------- arch/mips/configs/pb1550_defconfig | 145 --------------------- 6 files changed, 161 insertions(+), 437 deletions(-) delete mode 100644 arch/mips/alchemy/devboards/pb1550.c delete mode 100644 arch/mips/configs/pb1550_defconfig diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index b4929b9..6eb66a9 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -37,7 +37,7 @@ config MIPS_DB1000 select SYS_HAS_EARLY_PRINTK config MIPS_DB1235 - bool "Alchemy DB1200/PB1200/DB1300/DB1550 boards" + bool "Alchemy DB1200/PB1200/DB1300/DB1550/PB1550 boards" select ARCH_REQUIRE_GPIOLIB select HW_HAS_PCI select DMA_COHERENT @@ -62,15 +62,6 @@ config MIPS_PB1500 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_PB1550 - bool "Alchemy PB1550 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI - select MIPS_DISABLE_OBSOLETE_IDE - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_XXS1500 bool "MyCable XXS1500 board" select DMA_NONCOHERENT diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index f8a9624..fad8a99 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -6,6 +6,5 @@ obj-y += bcsr.o platform.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MIPS_PB1100) += pb1100.o obj-$(CONFIG_MIPS_PB1500) += pb1500.o -obj-$(CONFIG_MIPS_PB1550) += pb1550.o obj-$(CONFIG_MIPS_DB1000) += db1000.o obj-$(CONFIG_MIPS_DB1235) += db1235.o db1200.o db1300.o db1550.o diff --git a/arch/mips/alchemy/devboards/db1235.c b/arch/mips/alchemy/devboards/db1235.c index 15003eb..c76a90f 100644 --- a/arch/mips/alchemy/devboards/db1235.c +++ b/arch/mips/alchemy/devboards/db1235.c @@ -13,7 +13,7 @@ int __init db1300_board_setup(void); int __init db1300_dev_setup(void); int __init db1550_board_setup(void); int __init db1550_dev_setup(void); -int __init db1550_pci_setup(void); +int __init db1550_pci_setup(int); static const char *board_type_str(void) { @@ -27,6 +27,9 @@ static const char *board_type_str(void) return "DB1300"; case BCSR_WHOAMI_DB1550: return "DB1550"; + case BCSR_WHOAMI_PB1550_SDR: + case BCSR_WHOAMI_PB1550_DDR: + return "PB1550"; default: return "(unknown)"; } @@ -61,8 +64,13 @@ void __init board_setup(void) int __init db1235_arch_init(void) { - if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1550) - return db1550_pci_setup(); + int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + if (id == BCSR_WHOAMI_DB1550) + return db1550_pci_setup(0); + else if ((id == BCSR_WHOAMI_PB1550_SDR) || + (id == BCSR_WHOAMI_PB1550_DDR)) + return db1550_pci_setup(1); + return 0; } arch_initcall(db1235_arch_init); @@ -77,6 +85,8 @@ int __init db1235_dev_init(void) case BCSR_WHOAMI_DB1300: return db1300_dev_setup(); case BCSR_WHOAMI_DB1550: + case BCSR_WHOAMI_PB1550_SDR: + case BCSR_WHOAMI_PB1550_DDR: return db1550_dev_setup(); } return 0; diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c index 7664beed..5a9ae60 100644 --- a/arch/mips/alchemy/devboards/db1550.c +++ b/arch/mips/alchemy/devboards/db1550.c @@ -1,5 +1,5 @@ /* - * Alchemy Db1550 board support + * Alchemy Db1550/Pb1550 board support * * (c) 2011 Manuel Lauss */ @@ -17,11 +17,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include "platform.h" @@ -30,15 +32,14 @@ static void __init db1550_hw_setup(void) { void __iomem *base; - alchemy_gpio_direction_output(203, 0); /* red led on */ - /* complete SPI setup: link psc0_intclk to a 48MHz source, - * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) + * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) as well as PSC1_SYNC + * for AC97 on PB1550. */ base = (void __iomem *)SYS_CLKSRC; __raw_writel(__raw_readl(base) | 0x000001e0, base); base = (void __iomem *)SYS_PINFUNC; - __raw_writel(__raw_readl(base) | 1, base); + __raw_writel(__raw_readl(base) | 1 | SYS_PF_PSC1_S1, base); wmb(); /* reset the AC97 codec now, the reset time in the psc-ac97 driver @@ -51,8 +52,6 @@ static void __init db1550_hw_setup(void) wmb(); __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); wmb(); - - alchemy_gpio_direction_output(202, 0); /* green led on */ } int __init db1550_board_setup(void) @@ -62,9 +61,14 @@ int __init db1550_board_setup(void) bcsr_init(DB1550_BCSR_PHYS_ADDR, DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS); - whoami = bcsr_read(BCSR_WHOAMI); - printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d" - " Board-ID %d Daughtercard ID %d\n", + whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */ + if ((BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_SDR) || + (BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_DDR)) + bcsr_init(PB1550_BCSR_PHYS_ADDR, + PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); + + pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \ + "Daughtercard ID %d\n", get_system_type(), (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); db1550_hw_setup(); @@ -189,6 +193,39 @@ static struct platform_device db1550_nand_dev = { } }; +static struct au1550nd_platdata pb1550_nand_pd = { + .parts = db1550_nand_parts, + .num_parts = ARRAY_SIZE(db1550_nand_parts), + .devwidth = 0, /* x8 NAND default, needs fixing up */ +}; + +static struct platform_device pb1550_nand_dev = { + .name = "au1550-nand", + .id = -1, + .resource = db1550_nand_res, + .num_resources = ARRAY_SIZE(db1550_nand_res), + .dev = { + .platform_data = &pb1550_nand_pd, + }, +}; + +static void __init pb1550_nand_setup(void) +{ + int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | + ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); + + gpio_direction_input(206); /* de-assert NAND CS# */ + switch (boot_swapboot) { + case 0: case 2: case 8: case 0xC: case 0xD: + /* x16 NAND Flash */ + pb1550_nand_pd.devwidth = 1; + /* fallthrough */ + case 1: case 3: case 9: case 0xE: case 0xF: + /* x8 NAND, already set up */ + platform_device_register(&pb1550_nand_dev); + } +} + /**********************************************************************/ static struct resource au1550_psc0_res[] = { @@ -389,6 +426,29 @@ static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) return -1; } +static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) { + switch (pin) { + case 1: return AU1500_PCI_INTB; + case 2: return AU1500_PCI_INTC; + case 3: return AU1500_PCI_INTD; + case 4: return AU1500_PCI_INTA; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + static struct resource alchemy_pci_host_res[] = { [0] = { .start = AU1500_PCI_PHYS_ADDR, @@ -412,7 +472,6 @@ static struct platform_device db1550_pci_host_dev = { /**********************************************************************/ static struct platform_device *db1550_devs[] __initdata = { - &db1550_nand_dev, &db1550_i2c_dev, &db1550_ac97_dev, &db1550_spi_dev, @@ -425,14 +484,16 @@ static struct platform_device *db1550_devs[] __initdata = { }; /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ -int __init db1550_pci_setup(void) +int __init db1550_pci_setup(int id) { + if (id) + db1550_pci_pd.board_map_irq = pb1550_map_pci_irq; return platform_device_register(&db1550_pci_host_dev); } -int __init db1550_dev_setup(void) +static void __init db1550_devices(void) { - int swapped; + alchemy_gpio_direction_output(203, 0); /* red led on */ irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */ irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */ @@ -441,6 +502,75 @@ int __init db1550_dev_setup(void) irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */ irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1550_GPIO3_INT, AU1550_GPIO0_INT, + /*AU1550_GPIO21_INT*/0, 0, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + AU1550_GPIO5_INT, AU1550_GPIO1_INT, + /*AU1550_GPIO22_INT*/0, 0, 1); + + platform_device_register(&db1550_nand_dev); + + alchemy_gpio_direction_output(202, 0); /* green led on */ +} + +static void __init pb1550_devices(void) +{ + irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH); + + /* enable both PCMCIA card irqs in the shared line */ + alchemy_gpio2_enable_int(201); /* socket 0 card irq */ + alchemy_gpio2_enable_int(202); /* socket 1 card irq */ + + /* Pb1550, like all others, also has statuschange irqs; however they're + * wired up on one of the Au1550's shared GPIO201_205 line, which also + * services the PCMCIA card interrupts. So we ignore statuschange and + * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia + * drivers are used to shared irqs and b) statuschange isn't really use- + * ful anyway. + */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, + AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); + + pb1550_nand_setup(); +} + +int __init db1550_dev_setup(void) +{ + int swapped, id; + + id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550); + i2c_register_board_info(0, db1550_i2c_devs, ARRAY_SIZE(db1550_i2c_devs)); spi_register_board_info(db1550_spi_devs, @@ -461,27 +591,10 @@ int __init db1550_dev_setup(void) (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1550_GPIO3_INT, AU1550_GPIO0_INT, - /*AU1550_GPIO21_INT*/0, 0, 0); - - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, - AU1550_GPIO5_INT, AU1550_GPIO1_INT, - /*AU1550_GPIO22_INT*/0, 0, 1); + id ? pb1550_devices() : db1550_devices(); - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; + swapped = bcsr_read(BCSR_STATUS) & + (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT); db1x_register_norflash(128 << 20, 4, swapped); return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs)); diff --git a/arch/mips/alchemy/devboards/pb1550.c b/arch/mips/alchemy/devboards/pb1550.c deleted file mode 100644 index b37e7de..0000000 --- a/arch/mips/alchemy/devboards/pb1550.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Pb1550 board support. - * - * Copyright (C) 2009-2011 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "platform.h" - -const char *get_system_type(void) -{ - return "PB1550"; -} - -void __init board_setup(void) -{ - u32 pin_func; - - bcsr_init(PB1550_BCSR_PHYS_ADDR, - PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); - - alchemy_gpio2_enable(); - - /* - * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, - * but it is board specific code, so put it here. - */ - pin_func = au_readl(SYS_PINFUNC); - au_sync(); - pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; - au_writel(pin_func, SYS_PINFUNC); - - bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ - - printk(KERN_INFO "AMD Alchemy Pb1550 Board\n"); -} - -/******************************************************************************/ - -static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 12) || (slot > 13) || pin == 0) - return -1; - if (slot == 12) { - switch (pin) { - case 1: return AU1500_PCI_INTB; - case 2: return AU1500_PCI_INTC; - case 3: return AU1500_PCI_INTD; - case 4: return AU1500_PCI_INTA; - } - } - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - case 3: return AU1500_PCI_INTC; - case 4: return AU1500_PCI_INTD; - } - } - return -1; -} - -static struct resource alchemy_pci_host_res[] = { - [0] = { - .start = AU1500_PCI_PHYS_ADDR, - .end = AU1500_PCI_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct alchemy_pci_platdata pb1550_pci_pd = { - .board_map_irq = pb1550_map_pci_irq, -}; - -static struct platform_device pb1550_pci_host = { - .dev.platform_data = &pb1550_pci_pd, - .name = "alchemy-pci", - .id = 0, - .num_resources = ARRAY_SIZE(alchemy_pci_host_res), - .resource = alchemy_pci_host_res, -}; - -static struct resource au1550_psc2_res[] = { - [0] = { - .start = AU1550_PSC2_PHYS_ADDR, - .end = AU1550_PSC2_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1550_PSC2_INT, - .end = AU1550_PSC2_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1550_DSCR_CMD0_PSC2_TX, - .end = AU1550_DSCR_CMD0_PSC2_TX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1550_DSCR_CMD0_PSC2_RX, - .end = AU1550_DSCR_CMD0_PSC2_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device pb1550_i2c_dev = { - .name = "au1xpsc_smbus", - .id = 0, /* bus number */ - .num_resources = ARRAY_SIZE(au1550_psc2_res), - .resource = au1550_psc2_res, -}; - -static struct mtd_partition pb1550_nand_parts[] = { - [0] = { - .name = "NAND FS 0", - .offset = 0, - .size = 8 * 1024 * 1024, - }, - [1] = { - .name = "NAND FS 1", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct au1550nd_platdata pb1550_nand_pd = { - .parts = pb1550_nand_parts, - .num_parts = ARRAY_SIZE(pb1550_nand_parts), - .devwidth = 0, /* x8 NAND default, needs fixing up */ -}; - -static struct resource pb1550_nand_res[] = { - [0] = { - .start = 0x20000000, - .end = 0x20000fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device pb1550_nand_dev = { - .name = "au1550-nand", - .id = -1, - .resource = pb1550_nand_res, - .num_resources = ARRAY_SIZE(pb1550_nand_res), - .dev = { - .platform_data = &pb1550_nand_pd, - }, -}; - -static void __init pb1550_nand_setup(void) -{ - int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | - ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); - - switch (boot_swapboot) { - case 0: - case 2: - case 8: - case 0xC: - case 0xD: - /* x16 NAND Flash */ - pb1550_nand_pd.devwidth = 1; - /* fallthrough */ - case 1: - case 9: - case 3: - case 0xE: - case 0xF: - /* x8 NAND, already set up */ - platform_device_register(&pb1550_nand_dev); - } -} - -static int __init pb1550_dev_init(void) -{ - int swapped; - - irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); - - /* enable both PCMCIA card irqs in the shared line */ - alchemy_gpio2_enable_int(201); - alchemy_gpio2_enable_int(202); - - /* Pb1550, like all others, also has statuschange irqs; however they're - * wired up on one of the Au1550's shared GPIO201_205 line, which also - * services the PCMCIA card interrupts. So we ignore statuschange and - * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia - * drivers are used to shared irqs and b) statuschange isn't really use- - * ful anyway. - */ - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0); - - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, - AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); - - /* NAND setup */ - gpio_direction_input(206); /* GPIO206 high */ - pb1550_nand_setup(); - - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; - db1x_register_norflash(128 * 1024 * 1024, 4, swapped); - platform_device_register(&pb1550_pci_host); - platform_device_register(&pb1550_i2c_dev); - - return 0; -} -arch_initcall(pb1550_dev_init); diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig deleted file mode 100644 index e83d649..0000000 --- a/arch/mips/configs/pb1550_defconfig +++ /dev/null @@ -1,145 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_PB1550=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-pb1550" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCI=y -CONFIG_PCCARD=y -# CONFIG_CARDBUS is not set -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_AU1550=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_UB=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -CONFIG_BLK_DEV_HPT366=y -CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_PCI is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_AU1550=y -# CONFIG_HWMON is not set -# CONFIG_VGA_ARB is not set -CONFIG_HIDRAW=y -CONFIG_USB_HIDDEV=y -CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=y -CONFIG_VFAT_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y -- 1.7.12 From ralf@linux-mips.org Fri Sep 14 16:37:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 16:37:19 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:51765 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903385Ab2INOhP (ORCPT ); Fri, 14 Sep 2012 16:37:15 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8EEbDEo018860; Fri, 14 Sep 2012 16:37:13 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8EEbCus018859; Fri, 14 Sep 2012 16:37:12 +0200 Date: Fri, 14 Sep 2012 16:37:12 +0200 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH] MIPS: Alchemy: merge PB1550 support into DB1550 code Message-ID: <20120914143712.GD19592@linux-mips.org> References: <1347626830-15237-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1347626830-15237-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34500 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 24 Lines: 3 Thanks, queued. Ralf From ralf@linux-mips.org Fri Sep 14 18:07:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 18:07:08 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:53125 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903404Ab2INQHE (ORCPT ); Fri, 14 Sep 2012 18:07:04 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8EG728K025960; Fri, 14 Sep 2012 18:07:02 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8EG715D025931; Fri, 14 Sep 2012 18:07:01 +0200 Date: Fri, 14 Sep 2012 18:07:00 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Malta: Remove RTC Data Mode bootstrap breakage Message-ID: <20120914160700.GE19592@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34501 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 25 Lines: 3 Thanks, applied! Ralf From manuel.lauss@gmail.com Fri Sep 14 18:25:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 18:25:23 +0200 (CEST) Received: from mail-wi0-f171.google.com ([209.85.212.171]:46099 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903394Ab2INQZQ (ORCPT ); Fri, 14 Sep 2012 18:25:16 +0200 Received: by wibhq4 with SMTP id hq4so19033wib.6 for ; Fri, 14 Sep 2012 09:25:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=wzZw1N3vqswxXuaGugxfYyIIUEr5FEKJFmQL8e30IHE=; b=jlanGWmKY5v5cOjZ64TfxiACxKogDjbNk+OTmUVkOwiYAh/HBZHqw8wpawSda5mAsB 4CmMK36E9zgwzBM54LlZDNEPNlTn8YpALtJM+YWt+QgdtYXTNoMvFXGeDLPrgTJOHald 2VcLh/RQiVRG9drSFA6yKUZ7D6r4e62mkcURuOYXoc9o2EW3y6dxQdtvcyyklH3MxCq8 ZGW0kQrJlxqkB+X0f3IvkFJ7LrA/zYWvBe0vVL+XPsBOJsB5MNkmcuYYryc4xCLEmBA9 Qg9lxifb2Q6rvOmpmBs2C3blDEL2kiIx8Y9xvXckI+E7/f15YAC+T8rr9f+1jueFEBtN hXLg== Received: by 10.216.245.135 with SMTP id o7mr1715231wer.40.1347639911432; Fri, 14 Sep 2012 09:25:11 -0700 (PDT) Received: from flagship.roarinelk.net (188-22-1-39.adsl.highway.telekom.at. [188.22.1.39]) by mx.google.com with ESMTPS id el6sm19572631wib.8.2012.09.14.09.25.09 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 14 Sep 2012 09:25:10 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: merge PB1100/1500 support into DB1000 code. Date: Fri, 14 Sep 2012 18:25:00 +0200 Message-Id: <1347639900-3734-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.12 X-archive-position: 34502 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 29395 Lines: 973 The PB1100/1500 are similar to their DB-cousins but with a few more devices on the bus. This patch adds PB1100/1500 support to the existing DB1100/1500 code. Signed-off-by: Manuel Lauss --- Tested only on DB1100 and DB1500 as I don't have any PB1xxx boards. I didn't copy the custom board config from the PB1x sources since newer versions of YAMON already take care of it. I figure the code was added since the original developers only had very early yamon code on their boards. Applies on top of the pb1550 merge patch. arch/mips/alchemy/Kconfig | 19 +-- arch/mips/alchemy/devboards/Makefile | 2 - arch/mips/alchemy/devboards/db1000.c | 120 ++++++++++++++----- arch/mips/alchemy/devboards/pb1100.c | 167 -------------------------- arch/mips/alchemy/devboards/pb1500.c | 198 ------------------------------- arch/mips/configs/pb1100_defconfig | 124 ------------------- arch/mips/configs/pb1500_defconfig | 141 ---------------------- arch/mips/include/asm/mach-db1x00/bcsr.h | 2 + 8 files changed, 95 insertions(+), 678 deletions(-) delete mode 100644 arch/mips/alchemy/devboards/pb1100.c delete mode 100644 arch/mips/alchemy/devboards/pb1500.c delete mode 100644 arch/mips/configs/pb1100_defconfig delete mode 100644 arch/mips/configs/pb1500_defconfig diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 6eb66a9..c8862bd 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -27,7 +27,7 @@ config MIPS_MTX1 select SYS_HAS_EARLY_PRINTK config MIPS_DB1000 - bool "Alchemy DB1000/DB1500/DB1100 boards" + bool "Alchemy DB1000/DB1500/DB1100 PB1500/1100 boards" select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI @@ -45,23 +45,6 @@ config MIPS_DB1235 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_PB1100 - bool "Alchemy PB1100 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI - select SWAP_IO_SPACE - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - -config MIPS_PB1500 - bool "Alchemy PB1500 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_XXS1500 bool "MyCable XXS1500 board" select DMA_NONCOHERENT diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index fad8a99..15bf730 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -4,7 +4,5 @@ obj-y += bcsr.o platform.o obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_MIPS_PB1100) += pb1100.o -obj-$(CONFIG_MIPS_PB1500) += pb1500.o obj-$(CONFIG_MIPS_DB1000) += db1000.o obj-$(CONFIG_MIPS_DB1235) += db1235.o db1200.o db1300.o db1550.o diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c index 1b81dbf..8187845 100644 --- a/arch/mips/alchemy/devboards/db1000.c +++ b/arch/mips/alchemy/devboards/db1000.c @@ -1,5 +1,5 @@ /* - * DBAu1000/1500/1100 board support + * DBAu1000/1500/1100 PBAu1100/1500 board support * * Copyright 2000, 2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. @@ -52,6 +52,11 @@ static const char *board_type_str(void) return "DB1500"; case BCSR_WHOAMI_DB1100: return "DB1100"; + case BCSR_WHOAMI_PB1500: + case BCSR_WHOAMI_PB1500R2: + return "PB1500"; + case BCSR_WHOAMI_PB1100: + return "PB1100"; default: return "(unknown)"; } @@ -111,7 +116,9 @@ static struct platform_device db1500_pci_host_dev = { static int __init db1500_pci_init(void) { - if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1500) + int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + if ((id == BCSR_WHOAMI_DB1500) || (id == BCSR_WHOAMI_PB1500) || + (id == BCSR_WHOAMI_PB1500R2)) return platform_device_register(&db1500_pci_host_dev); return 0; } @@ -199,27 +206,37 @@ static irqreturn_t db1100_mmc_cd(int irq, void *ptr) static int db1100_mmc_cd_setup(void *mmc_host, int en) { - int ret = 0; + int ret = 0, irq; + + if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) + irq = AU1100_GPIO19_INT; + else + irq = AU1100_GPIO14_INT; /* PB1100 SD0 CD# */ if (en) { - irq_set_irq_type(AU1100_GPIO19_INT, IRQ_TYPE_EDGE_BOTH); - ret = request_irq(AU1100_GPIO19_INT, db1100_mmc_cd, 0, + irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH); + ret = request_irq(irq, db1100_mmc_cd, 0, "sd0_cd", mmc_host); } else - free_irq(AU1100_GPIO19_INT, mmc_host); + free_irq(irq, mmc_host); return ret; } static int db1100_mmc1_cd_setup(void *mmc_host, int en) { - int ret = 0; + int ret = 0, irq; + + if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) + irq = AU1100_GPIO20_INT; + else + irq = AU1100_GPIO15_INT; /* PB1100 SD1 CD# */ if (en) { - irq_set_irq_type(AU1100_GPIO20_INT, IRQ_TYPE_EDGE_BOTH); - ret = request_irq(AU1100_GPIO20_INT, db1100_mmc_cd, 0, + irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH); + ret = request_irq(irq, db1100_mmc_cd, 0, "sd1_cd", mmc_host); } else - free_irq(AU1100_GPIO20_INT, mmc_host); + free_irq(irq, mmc_host); return ret; } @@ -236,11 +253,18 @@ static int db1100_mmc_card_inserted(void *mmc_host) static void db1100_mmc_set_power(void *mmc_host, int state) { + int bit; + + if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) + bit = BCSR_BOARD_SD0PWR; + else + bit = BCSR_BOARD_PB1100_SD0PWR; + if (state) { - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); + bcsr_mod(BCSR_BOARD, 0, bit); msleep(400); /* stabilization time */ } else - bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); + bcsr_mod(BCSR_BOARD, bit, 0); } static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b) @@ -267,11 +291,18 @@ static int db1100_mmc1_card_inserted(void *mmc_host) static void db1100_mmc1_set_power(void *mmc_host, int state) { + int bit; + + if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) + bit = BCSR_BOARD_SD1PWR; + else + bit = BCSR_BOARD_PB1100_SD1PWR; + if (state) { - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); + bcsr_mod(BCSR_BOARD, 0, bit); msleep(400); /* stabilization time */ } else - bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); + bcsr_mod(BCSR_BOARD, bit, 0); } static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b) @@ -480,13 +511,12 @@ static struct platform_device *db1100_devs[] = { &db1100_mmc0_dev, &db1100_mmc1_dev, &db1000_irda_dev, - &db1100_spi_dev, }; static int __init db1000_dev_init(void) { int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); - int c0, c1, d0, d1, s0, s1; + int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1; unsigned long pfc; if (board == BCSR_WHOAMI_DB1500) { @@ -522,6 +552,7 @@ static int __init db1000_dev_init(void) ARRAY_SIZE(db1100_spi_info)); platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); + platform_device_register(&db1100_spi_dev); } else if (board == BCSR_WHOAMI_DB1000) { c0 = AU1000_GPIO2_INT; c1 = AU1000_GPIO5_INT; @@ -530,15 +561,42 @@ static int __init db1000_dev_init(void) s0 = AU1000_GPIO1_INT; s1 = AU1000_GPIO4_INT; platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs)); + } else if ((board == BCSR_WHOAMI_PB1500) || + (board == BCSR_WHOAMI_PB1500R2)) { + c0 = AU1500_GPIO203_INT; + d0 = AU1500_GPIO201_INT; + s0 = AU1500_GPIO202_INT; + twosocks = 0; + flashsize = 64; + /* RTC and daughtercard irqs */ + irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW); + /* EPSON S1D13806 0x1b000000 + * SRAM 1MB/2MB 0x1a000000 + * DS1693 RTC 0x0c000000 + */ + } else if (board == BCSR_WHOAMI_PB1100) { + c0 = AU1100_GPIO11_INT; + d0 = AU1100_GPIO9_INT; + s0 = AU1100_GPIO10_INT; + twosocks = 0; + flashsize = 64; + /* pendown, rtc, daughtercard irqs */ + irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW); + /* EPSON S1D13806 0x1b000000 + * SRAM 1MB/2MB 0x1a000000 + * DiskOnChip 0x0d000000 + * DS1693 RTC 0x0c000000 + */ + platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); } else return 0; /* unknown board, no further dev setup to do */ irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH); - irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH); irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW); db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR, @@ -549,17 +607,23 @@ static int __init db1000_dev_init(void) AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, c0, d0, /*s0*/0, 0, 0); - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, - c1, d1, /*s1*/0, 0, 1); + if (twosocks) { + irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + c1, d1, /*s1*/0, 0, 1); + } platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); - db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED); + db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED); return 0; } device_initcall(db1000_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1100.c b/arch/mips/alchemy/devboards/pb1100.c deleted file mode 100644 index 78c77a4..0000000 --- a/arch/mips/alchemy/devboards/pb1100.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Pb1100 board platform device registration - * - * Copyright (C) 2009 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "platform.h" - -const char *get_system_type(void) -{ - return "PB1100"; -} - -void __init board_setup(void) -{ - volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; - - bcsr_init(DB1000_BCSR_PHYS_ADDR, - DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); - - /* Set AUX clock to 12 MHz * 8 = 96 MHz */ - au_writel(8, SYS_AUXPLL); - alchemy_gpio1_input_enable(); - udelay(100); - -#if IS_ENABLED(CONFIG_USB_OHCI_HCD) - { - u32 pin_func, sys_freqctrl, sys_clksrc; - - /* Configure pins GPIO[14:9] as GPIO */ - pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; - - /* Zero and disable FREQ2 */ - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* Zero and disable USBH/USBD/IrDA clock */ - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK); - au_writel(sys_clksrc, SYS_CLKSRC); - - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK); - - /* FREQ2 = aux / 2 = 48 MHz */ - sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | - SYS_FC_FE2 | SYS_FC_FS2; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* - * Route 48 MHz FREQ2 into USBH/USBD/IrDA - */ - sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT; - au_writel(sys_clksrc, SYS_CLKSRC); - - /* Setup the static bus controller */ - au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ - au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ - au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ - - /* - * Get USB Functionality pin state (device vs host drive pins). - */ - pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB; - /* 2nd USB port is USB host. */ - pin_func |= SYS_PF_USB; - au_writel(pin_func, SYS_PINFUNC); - } -#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */ - - /* Enable sys bus clock divider when IDLE state or no bus activity. */ - au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); - - /* Enable the RTC if not already enabled. */ - if (!(readb(base + 0x28) & 0x20)) { - writeb(readb(base + 0x28) | 0x20, base + 0x28); - au_sync(); - } - /* Put the clock in BCD mode. */ - if (readb(base + 0x2C) & 0x4) { /* reg B */ - writeb(readb(base + 0x2c) & ~0x4, base + 0x2c); - au_sync(); - } -} - -/******************************************************************************/ - -static struct resource au1100_lcd_resources[] = { - [0] = { - .start = AU1100_LCD_PHYS_ADDR, - .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1100_LCD_INT, - .end = AU1100_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1100_lcd_device = { - .name = "au1100-lcd", - .id = 0, - .dev = { - .dma_mask = &au1100_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1100_lcd_resources), - .resource = au1100_lcd_resources, -}; - -static int __init pb1100_dev_init(void) -{ - int swapped; - - irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ - irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ - irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ - irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ - - /* PCMCIA. single socket, identical to Pb1500 */ - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */ - /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ - - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; - db1x_register_norflash(64 * 1024 * 1024, 4, swapped); - platform_device_register(&au1100_lcd_device); - - return 0; -} -device_initcall(pb1100_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1500.c b/arch/mips/alchemy/devboards/pb1500.c deleted file mode 100644 index 232fee9..0000000 --- a/arch/mips/alchemy/devboards/pb1500.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Pb1500 board support. - * - * Copyright (C) 2009 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "platform.h" - -const char *get_system_type(void) -{ - return "PB1500"; -} - -void __init board_setup(void) -{ - u32 pin_func; - u32 sys_freqctrl, sys_clksrc; - - bcsr_init(DB1000_BCSR_PHYS_ADDR, - DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); - - sys_clksrc = sys_freqctrl = pin_func = 0; - /* Set AUX clock to 12 MHz * 8 = 96 MHz */ - au_writel(8, SYS_AUXPLL); - alchemy_gpio1_input_enable(); - udelay(100); - - /* GPIO201 is input for PCMCIA card detect */ - /* GPIO203 is input for PCMCIA interrupt request */ - alchemy_gpio_direction_input(201); - alchemy_gpio_direction_input(203); - -#if IS_ENABLED(CONFIG_USB_OHCI_HCD) - - /* Zero and disable FREQ2 */ - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* zero and disable USBH/USBD clocks */ - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | - SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); - au_writel(sys_clksrc, SYS_CLKSRC); - - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | - SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); - - /* FREQ2 = aux/2 = 48 MHz */ - sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* - * Route 48MHz FREQ2 into USB Host and/or Device - */ - sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT; - au_writel(sys_clksrc, SYS_CLKSRC); - - pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB; - /* 2nd USB port is USB host */ - pin_func |= SYS_PF_USB; - au_writel(pin_func, SYS_PINFUNC); -#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */ - -#ifdef CONFIG_PCI - { - void __iomem *base = - (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR); - /* Setup PCI bus controller */ - __raw_writel(0x00003fff, base + PCI_REG_CMEM); - __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV); - __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL); - __raw_writel(0x02a00356, base + PCI_REG_STATCMD); - __raw_writel(0x00003c04, base + PCI_REG_PARAM); - __raw_writel(0x00000008, base + PCI_REG_MBAR); - wmb(); - } -#endif - - /* Enable sys bus clock divider when IDLE state or no bus activity. */ - au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); - - /* Enable the RTC if not already enabled */ - if (!(au_readl(0xac000028) & 0x20)) { - printk(KERN_INFO "enabling clock ...\n"); - au_writel((au_readl(0xac000028) | 0x20), 0xac000028); - } - /* Put the clock in BCD mode */ - if (au_readl(0xac00002c) & 0x4) { /* reg B */ - au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c); - au_sync(); - } -} - -/******************************************************************************/ - -static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 12) || (slot > 13) || pin == 0) - return -1; - if (slot == 12) - return (pin == 1) ? AU1500_PCI_INTA : 0xff; - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - case 3: return AU1500_PCI_INTC; - case 4: return AU1500_PCI_INTD; - } - } - return -1; -} - -static struct resource alchemy_pci_host_res[] = { - [0] = { - .start = AU1500_PCI_PHYS_ADDR, - .end = AU1500_PCI_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct alchemy_pci_platdata pb1500_pci_pd = { - .board_map_irq = pb1500_map_pci_irq, - .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | - PCI_CONFIG_CH | -#if defined(__MIPSEB__) - PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, -#else - 0, -#endif -}; - -static struct platform_device pb1500_pci_host = { - .dev.platform_data = &pb1500_pci_pd, - .name = "alchemy-pci", - .id = 0, - .num_resources = ARRAY_SIZE(alchemy_pci_host_res), - .resource = alchemy_pci_host_res, -}; - -static int __init pb1500_dev_init(void) -{ - int swapped; - - irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ - irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); - irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); - - /* PCMCIA. single socket, identical to Pb1100 */ - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */ - /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ - - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; - db1x_register_norflash(64 * 1024 * 1024, 4, swapped); - platform_device_register(&pb1500_pci_host); - - return 0; -} -arch_initcall(pb1500_dev_init); diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig deleted file mode 100644 index 75eb1b1..0000000 --- a/arch/mips/configs/pb1100_defconfig +++ /dev/null @@ -1,124 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_PB1100=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-pb1100" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_UB=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_IDE_TASK_IOCTL=y -# CONFIG_IDE_PROC_FS is not set -CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -CONFIG_HIDRAW=y -CONFIG_USB_HIDDEV=y -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -# CONFIG_JFFS2_FS_POSIX_ACL is not set -# CONFIG_JFFS2_FS_SECURITY is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig deleted file mode 100644 index fa00487..0000000 --- a/arch/mips/configs/pb1500_defconfig +++ /dev/null @@ -1,141 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_PB1500=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-pb1500" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCI=y -CONFIG_PCCARD=y -# CONFIG_CARDBUS is not set -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_UB=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_BLK_DEV_IDECD=y -CONFIG_IDE_TASK_IOCTL=y -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -CONFIG_BLK_DEV_HPT366=y -CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_PCI is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_ARB is not set -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y -CONFIG_FB_S1D13XXX=y -CONFIG_USB_HIDDEV=y -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_OTG_WHITELIST=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=y -CONFIG_VFAT_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index bb9fc23..16f1cf5 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -162,6 +162,8 @@ enum bcsr_whoami_boards { #define BCSR_BOARD_PCIEXTARB 0x0200 #define BCSR_BOARD_GPIO200RST 0x0400 #define BCSR_BOARD_PCICLKOUT 0x0800 +#define BCSR_BOARD_PB1100_SD0PWR 0x0400 +#define BCSR_BOARD_PB1100_SD1PWR 0x0800 #define BCSR_BOARD_PCICFG 0x1000 #define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */ #define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ -- 1.7.12 From mingo@kernel.org Fri Sep 14 07:52:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 07:52:25 +0200 (CEST) Received: from mail-wi0-f171.google.com ([209.85.212.171]:40373 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org 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[46.107.194.141]) by mx.google.com with ESMTPS id t8sm17198353wiy.3.2012.09.13.22.52.12 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 13 Sep 2012 22:52:13 -0700 (PDT) Date: Fri, 14 Sep 2012 07:52:10 +0200 From: Ingo Molnar To: Andrew Morton Cc: "Kirill A. Shutemov" , linux-mm@kvack.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Andi Kleen , Tim Chen , Alex Shi , Jan Beulich , Robert Richter , Andy Lutomirski , Andrea Arcangeli , Johannes Weiner , Hugh Dickins , KAMEZAWA Hiroyuki , Mel Gorman , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org Subject: Re: [PATCH v4 0/8] Avoid cache trashing on clearing huge/gigantic page Message-ID: <20120914055210.GC9043@gmail.com> References: <1345470757-12005-1-git-send-email-kirill.shutemov@linux.intel.com> <20120913160506.d394392a.akpm@linux-foundation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120913160506.d394392a.akpm@linux-foundation.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34498 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@kernel.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2559 Lines: 60 * Andrew Morton wrote: > On Mon, 20 Aug 2012 16:52:29 +0300 > "Kirill A. Shutemov" wrote: > > > Clearing a 2MB huge page will typically blow away several levels of CPU > > caches. To avoid this only cache clear the 4K area around the fault > > address and use a cache avoiding clears for the rest of the 2MB area. > > > > This patchset implements cache avoiding version of clear_page only for > > x86. If an architecture wants to provide cache avoiding version of > > clear_page it should to define ARCH_HAS_USER_NOCACHE to 1 and implement > > clear_page_nocache() and clear_user_highpage_nocache(). > > Patchset looks nice to me, but the changelogs are terribly > short of performance measurements. For this sort of change I > do think it is important that pretty exhaustive testing be > performed, and that the results (or a readable summary of > them) be shown. And that testing should be designed to probe > for slowdowns, not just the speedups! That is my general impression as well. Firstly, doing before/after "perf stat --repeat 3 ..." runs showing a statistically significant effect on a workload that is expected to win from this, and on a workload expected to be hurting from this would go a long way towards convincing me. Secondly, if you can find some user-space simulation of the intended positive (and negative) effects then a 'perf bench' testcase designed to show weakness of any such approach, running the very kernel assembly code in user-space would also be rather useful. See: comet:~/tip> git grep x86 tools/perf/bench/ | grep inclu tools/perf/bench/mem-memcpy-arch.h:#include "mem-memcpy-x86-64-asm-def.h" tools/perf/bench/mem-memcpy-x86-64-asm.S:#include "../../../arch/x86/lib/memcpy_64.S" tools/perf/bench/mem-memcpy.c:#include "mem-memcpy-x86-64-asm-def.h" tools/perf/bench/mem-memset-arch.h:#include "mem-memset-x86-64-asm-def.h" tools/perf/bench/mem-memset-x86-64-asm.S:#include "../../../arch/x86/lib/memset_64.S" tools/perf/bench/mem-memset.c:#include "mem-memset-x86-64-asm-def.h" that code uses the kernel-side assembly code and runs it in user-space. Although obviously clearing pages on page faults needs some care to properly simulate in user-space. Without repeatable hard numbers such code just gets into the kernel and bitrots there as new CPU generations come in - a few years down the line the original decisions often degrade to pure noise. We've been there, we've done that, we don't want to repeat it. Thanks, Ingo From ralf@linux-mips.org Fri Sep 14 20:24:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 20:24:12 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:39352 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903385Ab2INSYJ (ORCPT ); Fri, 14 Sep 2012 20:24:09 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8EIO7Lr004099; Fri, 14 Sep 2012 20:24:07 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8EIO6Jg004098; Fri, 14 Sep 2012 20:24:06 +0200 Date: Fri, 14 Sep 2012 20:24:06 +0200 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH] MIPS: Alchemy: merge PB1100/1500 support into DB1000 code. Message-ID: <20120914182406.GF19592@linux-mips.org> References: <1347639900-3734-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1347639900-3734-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34503 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 89 Lines: 5 Thanks, queued. I love this patch series. So many fewer defconfigs to test :-) Ralf From manuel.lauss@gmail.com Fri Sep 14 20:28:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 20:28:17 +0200 (CEST) Received: from mail-gh0-f177.google.com ([209.85.160.177]:45393 "EHLO mail-gh0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903385Ab2INS2L (ORCPT ); Fri, 14 Sep 2012 20:28:11 +0200 Received: by ghbf20 with SMTP id f20so204708ghb.36 for ; Fri, 14 Sep 2012 11:28:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=TO7CHP86HVRKKc7jS5h6wLqka9+Nb33RJAGJnDHWznM=; b=yfaPJBMoJyTtHIiFRgpSfFxOq2esEthaXLVwfTAZch6XHM6MS57hC2gWcjIqW6/CU9 Urj+/3yRFVdhK5a2M5HBuzSM7vfajKmFxY5vvtttVwqU6/t3fZZhjm+GeZPBhLoF/q2S cbacGzXemH91vlLKxL3LPBIeVUpbjLjZ9nXmzFc+3xSIHwT4jN4m6DNem/I9G8kkEsGy s52YL6ufx5C2GDwG1bHlataf7MWspnCmbzctM6l0TR0DvYk/cf9dlzAoyfzE8SP6wEqq 0T2meoYEXpe3R+Beg04i5TEoS43N8fjXakOn3X+I0Qko3c+T6wp90MZGE1HCDJPGy9bf /1/w== Received: by 10.236.189.38 with SMTP id b26mr4619519yhn.85.1347647284849; Fri, 14 Sep 2012 11:28:04 -0700 (PDT) MIME-Version: 1.0 Received: by 10.236.176.229 with HTTP; Fri, 14 Sep 2012 11:27:24 -0700 (PDT) In-Reply-To: <20120914182406.GF19592@linux-mips.org> References: <1347639900-3734-1-git-send-email-manuel.lauss@gmail.com> <20120914182406.GF19592@linux-mips.org> From: Manuel Lauss Date: Fri, 14 Sep 2012 20:27:24 +0200 Message-ID: Subject: Re: [PATCH] MIPS: Alchemy: merge PB1100/1500 support into DB1000 code. To: Ralf Baechle Cc: Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 34504 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 218 Lines: 8 On Fri, Sep 14, 2012 at 8:24 PM, Ralf Baechle wrote: > Thanks, queued. > > I love this patch series. So many fewer defconfigs to test :-) Thank you, that was one of my main motivations. Manuel From thierry.reding@avionic-design.de Fri Sep 14 22:44:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 22:44:54 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.186]:54658 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903396Ab2INUoq (ORCPT ); Fri, 14 Sep 2012 22:44:46 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu4) with ESMTP (Nemesis) id 0LqacI-1TgiRT3o7m-00eIGv; Fri, 14 Sep 2012 22:44:23 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 03F682A28267; Fri, 14 Sep 2012 22:44:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NDZPIag+jTVf; Fri, 14 Sep 2012 22:44:18 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 7C0042A282F5; Fri, 14 Sep 2012 22:44:18 +0200 (CEST) From: Thierry Reding To: Bjorn Helgaas Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 2/2] PCI: Provide a default pcibios_update_irq() Date: Fri, 14 Sep 2012 22:44:16 +0200 Message-Id: <1347655456-2542-2-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> References: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:FkHMxROCDl7QuCFbIQo5dMmgHPcuYz7TikXf1v5r3Vi 7Pv3j6uY6QsZq6XTzw7z8LW2Cr7WAAcFunGfc7mXzPcdSOPLzp 0JzLXecVDUToOZn8BziwbCyulB8CA6zlmKRS0Clv2mjwI1f3dv RNotsm3INA/iPHXpBdzrm0D6ba0UdS/Yt5P2ldmApD9imjpFKx W+eN/s3oxKxc5DAers4loaFUu4rzSJ99Yd9bodxtW5rxoGXFHk pY7SjIjUFTFOHSx3pyvuaBUyknKzLp6LPV9Mn8VH564iNmgWR2 qPXCWlfRWYlwf0ljENR6+i1udztM8kSFZZ4Mhcbk+AMgRp50T8 dJuwnlEkk0eGNKyyyLCYoW7y4OiQY8//zWVj5djCoIMmgefG6M dtbFlj/tONxEkrIXf9oaLy5ST5P04CJYoQdrg6FixbL5EoidM/ JhHRw X-archive-position: 34505 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8963 Lines: 289 Most architectures implement this in exactly the same way. Instead of having each architecture duplicate this function, provide a single implementation in the core and make it a weak symbol so that it can be overridden on architectures where it is required. Signed-off-by: Thierry Reding --- Note: ARM and Unicore32 did use a debug_pci variable to check whether or not to output a debug message in pcibios_update_irq(). SPARC/LEON checks for CONFIG_PCI_DEBUG instead. I've adopted the SPARC variant in this patch. I assumed that in the interest of unification this would be a good compromise. If not, please let me know. Also, SPARC64 had an empty pcibios_update_irq(). I've opted to drop it in favour of the default implementation, which just writes a single byte in the device's configuration space. I assumed that this should still work but perhaps was just not used on SPARC64. If this is known to break SPARC64 I can keep the noop implementation. arch/alpha/kernel/pci.c | 6 ------ arch/arm/kernel/bios32.c | 9 --------- arch/ia64/pci/pci.c | 8 -------- arch/m68k/kernel/pcibios.c | 5 ----- arch/mips/pci/pci.c | 6 ------ arch/sh/drivers/pci/pci.c | 5 ----- arch/sparc/kernel/leon_pci.c | 9 --------- arch/sparc/kernel/pci.c | 4 ---- arch/tile/kernel/pci.c | 8 -------- arch/tile/kernel/pci_gx.c | 8 -------- arch/unicore32/kernel/pci.c | 8 -------- arch/x86/pci/visws.c | 5 ----- arch/xtensa/kernel/pci.c | 8 -------- drivers/pci/setup-irq.c | 8 ++++++++ 14 files changed, 8 insertions(+), 89 deletions(-) diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c index 6192b35..ef75714 100644 --- a/arch/alpha/kernel/pci.c +++ b/arch/alpha/kernel/pci.c @@ -256,12 +256,6 @@ pcibios_fixup_bus(struct pci_bus *bus) } } -void __devinit -pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - int pcibios_enable_device(struct pci_dev *dev, int mask) { diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 2b2f25e..9cf16b8 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -270,15 +270,6 @@ static void __devinit pci_fixup_it8152(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); - - -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) -{ - if (debug_pci) - printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev)); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - /* * If the bus contains any of these devices, then we must not turn on * parity checking of any kind. Currently this is CyberPro 20x0 only. diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c index 81acc7a..a7ebe94 100644 --- a/arch/ia64/pci/pci.c +++ b/arch/ia64/pci/pci.c @@ -461,14 +461,6 @@ void pcibios_set_master (struct pci_dev *dev) /* No special bus mastering setup handling */ } -void __devinit -pcibios_update_irq (struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); - - /* ??? FIXME -- record old value for shutdown. */ -} - int pcibios_enable_device (struct pci_dev *dev, int mask) { diff --git a/arch/m68k/kernel/pcibios.c b/arch/m68k/kernel/pcibios.c index b2988aa..73fa0b5 100644 --- a/arch/m68k/kernel/pcibios.c +++ b/arch/m68k/kernel/pcibios.c @@ -87,11 +87,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return 0; } -void pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - void __devinit pcibios_fixup_bus(struct pci_bus *bus) { struct pci_dev *dev; diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index af3dc05..04e35bc 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -313,12 +313,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) } } -void __devinit -pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - #ifdef CONFIG_HOTPLUG EXPORT_SYMBOL(PCIBIOS_MIN_IO); EXPORT_SYMBOL(PCIBIOS_MIN_MEM); diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index d16fabe..a7e078f 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -192,11 +192,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pci_enable_resources(dev, mask); } -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - static void __init pcibios_bus_report_status_early(struct pci_channel *hose, int top_bus, int current_bus, diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c index 21dcda7..fc05211 100644 --- a/arch/sparc/kernel/leon_pci.c +++ b/arch/sparc/kernel/leon_pci.c @@ -102,15 +102,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pci_enable_resources(dev, mask); } -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) -{ -#ifdef CONFIG_PCI_DEBUG - printk(KERN_DEBUG "LEONPCI: Assigning IRQ %02d to %s\n", irq, - pci_name(dev)); -#endif - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - /* in/out routines taken from pcic.c * * This probably belongs here rather than ioport.c because diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index 065b88c..acc8c83 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c @@ -622,10 +622,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *pbus) { } -void pcibios_update_irq(struct pci_dev *pdev, int irq) -{ -} - resource_size_t pcibios_align_resource(void *data, const struct resource *res, resource_size_t size, resource_size_t align) { diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index 33c1086..dbdab34 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -404,14 +404,6 @@ void pcibios_set_master(struct pci_dev *dev) } /* - * This is called from the generic Linux layer. - */ -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - -/* * Enable memory and/or address decoding, as appropriate, for the * device described by the 'dev' struct. * diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index 0e213e3..2ba6d05 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c @@ -1034,14 +1034,6 @@ char __devinit *pcibios_setup(char *str) } /* - * This is called from the generic Linux layer. - */ -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - -/* * Enable memory address decoding, as appropriate, for the * device described by the 'dev' struct. The I/O decoding * is disabled, though the TILE-Gx supports I/O addressing. diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c index 46cb6c9..b0056f6 100644 --- a/arch/unicore32/kernel/pci.c +++ b/arch/unicore32/kernel/pci.c @@ -154,14 +154,6 @@ void __init puv3_pci_adjust_zones(unsigned long *zone_size, zhole_size[0] = 0; } -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) -{ - if (debug_pci) - printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", - irq, pci_name(dev)); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - /* * If the bus contains any of these devices, then we must not turn on * parity checking of any kind. diff --git a/arch/x86/pci/visws.c b/arch/x86/pci/visws.c index 15bdfbf..3e6d2a6 100644 --- a/arch/x86/pci/visws.c +++ b/arch/x86/pci/visws.c @@ -62,11 +62,6 @@ out: return irq; } -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - int __init pci_visws_init(void) { pcibios_enable_irq = &pci_visws_enable_irq; diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c index efc3369..54354de 100644 --- a/arch/xtensa/kernel/pci.c +++ b/arch/xtensa/kernel/pci.c @@ -210,14 +210,6 @@ void pcibios_set_master(struct pci_dev *dev) /* No special bus mastering setup handling */ } -/* the next one is stolen from the alpha port... */ - -void __devinit -pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - int pcibios_enable_device(struct pci_dev *dev, int mask) { u16 cmd, old_cmd; diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c index f0bcd56..2d39268 100644 --- a/drivers/pci/setup-irq.c +++ b/drivers/pci/setup-irq.c @@ -17,6 +17,14 @@ #include #include +void __devinit __weak pcibios_update_irq(struct pci_dev *dev, int irq) +{ +#ifdef CONFIG_PCI_DEBUG + printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", irq, + pci_name(dev)); +#endif + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); +} static void __devinit pdev_fixup_irq(struct pci_dev *dev, -- 1.7.12 From thierry.reding@avionic-design.de Fri Sep 14 22:45:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 22:45:15 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:52360 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903398Ab2INUpE (ORCPT ); Fri, 14 Sep 2012 22:45:04 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap3) with ESMTP (Nemesis) id 0MEWGP-1TIyOz1EbJ-00Fhy5; Fri, 14 Sep 2012 22:44:21 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 065972A28302; Fri, 14 Sep 2012 22:44:19 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MvSH9u6EVoyS; Fri, 14 Sep 2012 22:44:17 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 2E0F92A28267; Fri, 14 Sep 2012 22:44:17 +0200 (CEST) From: Thierry Reding To: Bjorn Helgaas Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 1/2] PCI: Annotate pci_fixup_irqs with __devinit Date: Fri, 14 Sep 2012 22:44:15 +0200 Message-Id: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 X-Provags-ID: V02:K0:Nom7qgQWtfUTmgDSmVNYlmmvP9AxgzwH/qrwOy7eCMz patGWO1MF3YdfI0U6+I20HshBj73o08NLfjOhLOZF6OYJkflk2 42y+hd/25nIP+6K3/YROuzb5xFlOeXsUEVmlHdPpGyG7M7EIJu R5qG+Ri5cXdRiYMcLXqHRljqpottpzl4LL1dJWtYeGB6FJ0wsF UItkdTl0SPIMC6Pwq1C0a7OJKkXufei6XKpZc6hDfNsmBERfRy FaqxiCgx8ud7GlKEiPVMLCt0Gp3Ap9+M73Oa9Nmhv/X4W5PHJk /JcZTM7ywLVAwgRvy5cCM2h9n6HaOnWmR4rNTBEZYVJpurQy7j hL7szTDcDTp5JgX2CDK50J7R+kgG78RZEWWLS7n0mMJYl6EoAh 1nkMHQRPdyfq79Q0NQ7GHuWCj/Ioel0Imsa9ZF/8cLlDtsTr+O CqWKh X-archive-position: 34506 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3367 Lines: 109 In order to keep pci_fixup_irqs() around after init (e.g. for hotplug), mark it __devinit instead of __init. This requires the same change for the implementation of the pcibios_update_irq() function on all architectures. Signed-off-by: Thierry Reding --- Note: Ideally these annotations should go away completely in order to be independent of the HOTPLUG symbol. However, there is work underway to get rid of HOTPLUG altogether, so I've kept the __devinit for now. arch/alpha/kernel/pci.c | 2 +- arch/mips/pci/pci.c | 2 +- arch/sh/drivers/pci/pci.c | 2 +- arch/x86/pci/visws.c | 2 +- arch/xtensa/kernel/pci.c | 2 +- drivers/pci/setup-irq.c | 4 ++-- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c index 9816d5a..6192b35 100644 --- a/arch/alpha/kernel/pci.c +++ b/arch/alpha/kernel/pci.c @@ -256,7 +256,7 @@ pcibios_fixup_bus(struct pci_bus *bus) } } -void __init +void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 6903568..af3dc05 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -313,7 +313,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) } } -void __init +void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index 40db2d0..d16fabe 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -192,7 +192,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pci_enable_resources(dev, mask); } -void __init pcibios_update_irq(struct pci_dev *dev, int irq) +void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } diff --git a/arch/x86/pci/visws.c b/arch/x86/pci/visws.c index 6f2f8ee..15bdfbf 100644 --- a/arch/x86/pci/visws.c +++ b/arch/x86/pci/visws.c @@ -62,7 +62,7 @@ out: return irq; } -void __init pcibios_update_irq(struct pci_dev *dev, int irq) +void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c index 69759e9..efc3369 100644 --- a/arch/xtensa/kernel/pci.c +++ b/arch/xtensa/kernel/pci.c @@ -212,7 +212,7 @@ void pcibios_set_master(struct pci_dev *dev) /* the next one is stolen from the alpha port... */ -void __init +void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c index eb219a1..f0bcd56 100644 --- a/drivers/pci/setup-irq.c +++ b/drivers/pci/setup-irq.c @@ -18,7 +18,7 @@ #include -static void __init +static void __devinit pdev_fixup_irq(struct pci_dev *dev, u8 (*swizzle)(struct pci_dev *, u8 *), int (*map_irq)(const struct pci_dev *, u8, u8)) @@ -54,7 +54,7 @@ pdev_fixup_irq(struct pci_dev *dev, pcibios_update_irq(dev, irq); } -void __init +void __devinit pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *), int (*map_irq)(const struct pci_dev *, u8, u8)) { -- 1.7.12 From bhelgaas@google.com Fri Sep 14 22:53:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Sep 2012 22:53:44 +0200 (CEST) Received: from mail-iy0-f177.google.com ([209.85.210.177]:36007 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903399Ab2INUxi (ORCPT ); Fri, 14 Sep 2012 22:53:38 +0200 Received: by iaai1 with SMTP id i1so3845783iaa.36 for ; Fri, 14 Sep 2012 13:53:31 -0700 (PDT) DKIM-Signature: v=1; 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Fri, 14 Sep 2012 13:53:31 -0700 (PDT) Received: by 10.50.236.100 with SMTP id ut4mr81520igc.34.1347656011573; Fri, 14 Sep 2012 13:53:31 -0700 (PDT) MIME-Version: 1.0 Received: by 10.64.73.167 with HTTP; Fri, 14 Sep 2012 13:53:11 -0700 (PDT) In-Reply-To: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> References: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> From: Bjorn Helgaas Date: Fri, 14 Sep 2012 14:53:11 -0600 Message-ID: Subject: Re: [PATCH 1/2] PCI: Annotate pci_fixup_irqs with __devinit To: Thierry Reding Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org, Greg Kroah-Hartman Content-Type: text/plain; charset=ISO-8859-1 X-System-Of-Record: true X-Gm-Message-State: ALoCoQmwZDivv2jY9dckFnAXletLKKdCpId0kmPphvJpVuDrb72u6CKJmP004Sw88gR6R/VpVZ9WYwSWMA4zT2o2CDfEsHlBcjd5hMX/fy26IvbYOZwPbjA5eNv0PAZ7GttjMpty5N1JgPQxH4DSh8AgKcb+DlycW+dBcw3dSZVJ6LIF7QMrhUMWJOMdbce6fb4VtoFCE1VEAXSuUNzw1IaM3ljEQfHeiA== X-archive-position: 34507 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3743 Lines: 113 +cc Greg KH On Fri, Sep 14, 2012 at 2:44 PM, Thierry Reding wrote: > In order to keep pci_fixup_irqs() around after init (e.g. for hotplug), > mark it __devinit instead of __init. This requires the same change for > the implementation of the pcibios_update_irq() function on all > architectures. > > Signed-off-by: Thierry Reding > --- > Note: Ideally these annotations should go away completely in order to > be independent of the HOTPLUG symbol. However, there is work underway > to get rid of HOTPLUG altogether, so I've kept the __devinit for now. > > arch/alpha/kernel/pci.c | 2 +- > arch/mips/pci/pci.c | 2 +- > arch/sh/drivers/pci/pci.c | 2 +- > arch/x86/pci/visws.c | 2 +- > arch/xtensa/kernel/pci.c | 2 +- > drivers/pci/setup-irq.c | 4 ++-- > 6 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c > index 9816d5a..6192b35 100644 > --- a/arch/alpha/kernel/pci.c > +++ b/arch/alpha/kernel/pci.c > @@ -256,7 +256,7 @@ pcibios_fixup_bus(struct pci_bus *bus) > } > } > > -void __init > +void __devinit > pcibios_update_irq(struct pci_dev *dev, int irq) > { > pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); > diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c > index 6903568..af3dc05 100644 > --- a/arch/mips/pci/pci.c > +++ b/arch/mips/pci/pci.c > @@ -313,7 +313,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) > } > } > > -void __init > +void __devinit > pcibios_update_irq(struct pci_dev *dev, int irq) > { > pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); > diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c > index 40db2d0..d16fabe 100644 > --- a/arch/sh/drivers/pci/pci.c > +++ b/arch/sh/drivers/pci/pci.c > @@ -192,7 +192,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) > return pci_enable_resources(dev, mask); > } > > -void __init pcibios_update_irq(struct pci_dev *dev, int irq) > +void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) > { > pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); > } > diff --git a/arch/x86/pci/visws.c b/arch/x86/pci/visws.c > index 6f2f8ee..15bdfbf 100644 > --- a/arch/x86/pci/visws.c > +++ b/arch/x86/pci/visws.c > @@ -62,7 +62,7 @@ out: > return irq; > } > > -void __init pcibios_update_irq(struct pci_dev *dev, int irq) > +void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) > { > pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); > } > diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c > index 69759e9..efc3369 100644 > --- a/arch/xtensa/kernel/pci.c > +++ b/arch/xtensa/kernel/pci.c > @@ -212,7 +212,7 @@ void pcibios_set_master(struct pci_dev *dev) > > /* the next one is stolen from the alpha port... */ > > -void __init > +void __devinit > pcibios_update_irq(struct pci_dev *dev, int irq) > { > pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); > diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c > index eb219a1..f0bcd56 100644 > --- a/drivers/pci/setup-irq.c > +++ b/drivers/pci/setup-irq.c > @@ -18,7 +18,7 @@ > #include > > > -static void __init > +static void __devinit > pdev_fixup_irq(struct pci_dev *dev, > u8 (*swizzle)(struct pci_dev *, u8 *), > int (*map_irq)(const struct pci_dev *, u8, u8)) > @@ -54,7 +54,7 @@ pdev_fixup_irq(struct pci_dev *dev, > pcibios_update_irq(dev, irq); > } > > -void __init > +void __devinit > pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *), > int (*map_irq)(const struct pci_dev *, u8, u8)) > { > -- > 1.7.12 > From gregkh@linuxfoundation.org Sat Sep 15 00:35:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 15 Sep 2012 00:35:47 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:54742 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903400Ab2INWfn (ORCPT ); Sat, 15 Sep 2012 00:35:43 +0200 Received: by dajq27 with SMTP id q27so1422327daj.36 for ; Fri, 14 Sep 2012 15:35:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=QQPqKVcFXiZQc9S7EC9X4a9KvEqgrapKZDAnkrz3wmg=; b=O9fCQhWUrtYZDEoE44sk0kprzB4HWoGHZ51K5R/WGJzprxT7TDlHfaJCfhejLjLqQd 5HIwcILkPLp5CcDqgX61LpXHqz64S/u6NC8PjT3D34z11Mfd3jUJ8zkrIslC939xVGDr uuCoULiRfa+Yhq6jwAawYnDSgzUSshQTPIDek92TSa12zNLxwxku73qlYtjQinYS/7oF 9oAyo8Z9WguGdZQ+ej/j2wO8NNZJ/IFq39hQCCpNjtgSeuCUZBF2NIHI1ibDG+tMLp/n 7uZ2dfwnUmZru1yAHHz70CBibFEIiqB5Sau5JnczQOjmmBEnsEg89wZchEt9X4aBxpRT GHiA== Received: by 10.68.242.164 with SMTP id wr4mr7073308pbc.41.1347662136386; Fri, 14 Sep 2012 15:35:36 -0700 (PDT) Received: from localhost (c-67-168-183-230.hsd1.wa.comcast.net. [67.168.183.230]) by mx.google.com with ESMTPS id ho7sm1707972pbc.3.2012.09.14.15.35.32 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 14 Sep 2012 15:35:35 -0700 (PDT) Date: Fri, 14 Sep 2012 15:35:31 -0700 From: Greg Kroah-Hartman To: Bjorn Helgaas Cc: Thierry Reding , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH 1/2] PCI: Annotate pci_fixup_irqs with __devinit Message-ID: <20120914223531.GA8771@kroah.com> References: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQmrqfD/EuigwgrftzoBa6Tumut7fZw8UJMz8rhk+URe2mpxU3wNyfBlSboNZ8ZVHUxzr7wz X-archive-position: 34508 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 989 Lines: 24 On Fri, Sep 14, 2012 at 02:53:11PM -0600, Bjorn Helgaas wrote: > +cc Greg KH > > On Fri, Sep 14, 2012 at 2:44 PM, Thierry Reding > wrote: > > In order to keep pci_fixup_irqs() around after init (e.g. for hotplug), > > mark it __devinit instead of __init. This requires the same change for > > the implementation of the pcibios_update_irq() function on all > > architectures. > > > > Signed-off-by: Thierry Reding > > --- > > Note: Ideally these annotations should go away completely in order to > > be independent of the HOTPLUG symbol. However, there is work underway > > to get rid of HOTPLUG altogether, so I've kept the __devinit for now. No, just take away the __init marking completly. For 3.7, CONFIG_HOTPLUG will always be enabled, making it be the same thing. That way this saves me the time and energy from deleting the __devinit markings when I get to that point in the patch series :) thanks, greg k-h From geert@linux-m68k.org Sat Sep 15 09:32:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 15 Sep 2012 09:32:24 +0200 (CEST) Received: from mail-vc0-f177.google.com ([209.85.220.177]:32916 "EHLO mail-vc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903234Ab2IOHcR (ORCPT ); Sat, 15 Sep 2012 09:32:17 +0200 Received: by vcbgb22 with SMTP id gb22so6047036vcb.36 for ; Sat, 15 Sep 2012 00:32:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=oKUjMbnOdMtqIHRgQqgb+0OJdvE9f4xQvLSj2N0dESk=; b=S6vCHoTLecI450CYovV8Z5ztOqEWmWJLeaWwNzYfRwEpMhQnIrFhwChcSlAXSUQdWU Lz23tMClZxbIc2eJgyncGe4rTmzMQnan4kjMCWPDB4kH8y36rvg1l7gWX1fYoBW4A5W5 yzzcBxyY+hg7iJXLa0HJ1pMaeAy9DdQy5MvpPRDD8nIPc39I4LO6BXJ/cMhONcHiUIPU uUFmLIRpJJEpQFXJh7d+l9ARBUwnFAd7hVo9oBv5uDaO6XoHSR9/2mhS4ppFStoZ8ZNc 4XOT1X39HM/9ZLd1Nw0MJKLEJld5+rVdkN1U+xzqf6JXp5y0tcWUIlyg3TCqy/7KzktG VSXw== MIME-Version: 1.0 Received: by 10.58.164.8 with SMTP id ym8mr4359961veb.39.1347694330690; Sat, 15 Sep 2012 00:32:10 -0700 (PDT) Received: by 10.220.50.135 with HTTP; Sat, 15 Sep 2012 00:32:10 -0700 (PDT) In-Reply-To: <1347655456-2542-2-git-send-email-thierry.reding@avionic-design.de> References: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> <1347655456-2542-2-git-send-email-thierry.reding@avionic-design.de> Date: Sat, 15 Sep 2012 09:32:10 +0200 X-Google-Sender-Auth: CKlwSCtI1vW5-tlPeb5XFNsfC2c Message-ID: Subject: Re: [PATCH 2/2] PCI: Provide a default pcibios_update_irq() From: Geert Uytterhoeven To: Thierry Reding Cc: Bjorn Helgaas , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 34509 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 904 Lines: 31 On Fri, Sep 14, 2012 at 10:44 PM, Thierry Reding wrote: > --- a/drivers/pci/setup-irq.c > +++ b/drivers/pci/setup-irq.c > @@ -17,6 +17,14 @@ > #include > #include > > +void __devinit __weak pcibios_update_irq(struct pci_dev *dev, int irq) > +{ > +#ifdef CONFIG_PCI_DEBUG > + printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", irq, > + pci_name(dev)); pr_debug()? Or even better, dev_dbg()? > +#endif > + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); > +} Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From thierry.reding@avionic-design.de Sat Sep 15 09:54:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 15 Sep 2012 09:54:13 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.9]:49343 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903239Ab2IOHyE (ORCPT ); Sat, 15 Sep 2012 09:54:04 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0MBG3l-1TKjfJ3xDh-009wBL; Sat, 15 Sep 2012 09:53:05 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 0BF6F2A282D4; Sat, 15 Sep 2012 09:53:04 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GD-fCSsbMocr; Sat, 15 Sep 2012 09:53:03 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 716852A2818B; Sat, 15 Sep 2012 09:53:02 +0200 (CEST) Date: Sat, 15 Sep 2012 09:53:01 +0200 From: Thierry Reding To: Geert Uytterhoeven Cc: Bjorn Helgaas , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH 2/2] PCI: Provide a default pcibios_update_irq() Message-ID: <20120915075301.GA31044@avionic-0098.mockup.avionic-design.de> References: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> <1347655456-2542-2-git-send-email-thierry.reding@avionic-design.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="9jxsPFA5p3P2qPhR" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:+WM1IBlhxGXCa1U3T21B9tS4Ln9hnPL8z3edAljLR97 tGcJzIAXzo25dc89sm6KU/20G61r+KrsRgf7uZs956M5WNoaHe XdBo8Ro5FYrhv3FesDimr5qug4tVoTZBUidqs5iJIhdN8Gnki1 qjO4pXEiQ1rbkme7N5abi5Ce2p8Ru0N6cy4DFmwO1BEl3TH7LI l2jvH9UGSyOAdqRktKaMgK2kZs4w+1fmIAU6Uyfh+RywkBwUIn dnBqxWeWJ1MLJp+l1vdumWXHWze52MXfxAfsDy7H5hWqueCYYS wVGCttukaG2Q1e1jbAP4PQ/hpemaKywICjltOnFNWaIWHekbGc p0lFWRObMT6lbiBlfi5Rh2R5XQ90QA+QOFLC0oekzp87SWtWaV 9oa4hp4ICwAqeFWQwywIE0odZpLep5oEP0= X-archive-position: 34510 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1833 Lines: 52 --9jxsPFA5p3P2qPhR Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Sep 15, 2012 at 09:32:10AM +0200, Geert Uytterhoeven wrote: > On Fri, Sep 14, 2012 at 10:44 PM, Thierry Reding > wrote: > > --- a/drivers/pci/setup-irq.c > > +++ b/drivers/pci/setup-irq.c > > @@ -17,6 +17,14 @@ > > #include > > #include > > > > +void __devinit __weak pcibios_update_irq(struct pci_dev *dev, int irq) > > +{ > > +#ifdef CONFIG_PCI_DEBUG > > + printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", irq, > > + pci_name(dev)); >=20 > pr_debug()? > Or even better, dev_dbg()? The problem with pr_debug() and dev_dbg() is that they will be compiled out if DEBUG is not defined. Perhaps we should pass -DDEBUG if PCI_DEBUG is configured and make this dev_dbg()? Thierry --9jxsPFA5p3P2qPhR Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQVDPdAAoJEN0jrNd/PrOhyIYP/Ru7vr3AxNAHfW1yg4IPxgM0 HlExgyk6vrHq2RxLK1h714L7sqYK3Gn7AQcXUa8sCHhTqJ7v/nmfnguP9m4K/QJO SnC+nG4VgwIn7aZHevaupjVcHWXGtL1aR7zUWb7LzqDq+bKYHxpXAz2p8bCzotJG nZd2OyMdbjVLnONcjdSpbVNHRvKe7UoS4R9I2PvciJI/oUYlV03aMXYpRxujxnIY DbLxoyCCLsBphYBDx9IvQCFFpBaXqgTVa9PWQ1MlytfuEWoLr6nOVD01bgMizOGS Ry1Wbs3YAVHjFN/68iLZGjZCz9ODft2MYpw47akDX2InilvlPUH3GZZ4bu+31tP1 bd2M4ZCNAC8EK/UPxAxcyMFhqJ688qpHhDXsPDX349lYdo2SjG90/5CMl6cYL1Xv Hd/1Uygl+Mmw9oPNX/hpozAJeKvT9P8VqGunn0uabdBxl+4Uo6ucauWRs2V0DY+z eEX1mVwYSddgcLt9LCU45Io03p3M6W2CRIOwG9beckMj00c07riHX4w6z/OhIsF5 /rhDGvqTr9LHs8L45SzqygsuVWGZiGAryRsHDdXxj2yS+yT1HCDjFboPwsgx6K9P IcUekJYFy1RxEB7YzK8oyfl7EhigIQAzdyhqL/QgjhtTla6vG7cXcgMYJgXhRtBG qq23DlFKzpQ/g5tsIqjp =aCDh -----END PGP SIGNATURE----- --9jxsPFA5p3P2qPhR-- From thierry.reding@avionic-design.de Sat Sep 15 09:58:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 15 Sep 2012 09:58:48 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:61374 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903236Ab2IOH6l (ORCPT ); Sat, 15 Sep 2012 09:58:41 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu3) with ESMTP (Nemesis) id 0LblNw-1TtmyH06hY-00jHxy; Sat, 15 Sep 2012 09:57:42 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 221E92A282D4; Sat, 15 Sep 2012 09:57:40 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FU1EKzGoIfCK; Sat, 15 Sep 2012 09:57:38 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 6AB292A2818B; Sat, 15 Sep 2012 09:57:38 +0200 (CEST) Date: Sat, 15 Sep 2012 09:57:37 +0200 From: Thierry Reding To: Greg Kroah-Hartman Cc: Bjorn Helgaas , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH 1/2] PCI: Annotate pci_fixup_irqs with __devinit Message-ID: <20120915075737.GA31258@avionic-0098.mockup.avionic-design.de> References: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> <20120914223531.GA8771@kroah.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="+QahgC5+KEYLbs62" Content-Disposition: inline In-Reply-To: <20120914223531.GA8771@kroah.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:z4ZB6PdzY1xIrstHENAfrYAdSCRjDWPVsvDoaG48yS0 fhZjf4y14sTuedXfjMjHO9Rp0+V92pmUySAI+BVBgGfMziR0o1 lsfIEbEz9mdKlEhQFCi5/YIK0rlCS3A1Auy9J2Nnp1kDmOoQ4n nRNGQg+2jjj5/4fYQMjNJ6vxePoIV+yJhsCc5Dxm5r4Nc2owtJ SVsnWx3pffGLEdB28fD0gRsReX4YhzbX6DCdn/VmLnYmPeNVh2 bjaUXD2z87r1ie3+GeBhOHyu8HFqc8i9nz4C/GrUZE3AtLQXlG lyN4VWby/me/rvw8lM7J2XH1dLLKBjFDyYPCJ9n5y9QfgfDyJA 3VhLtlmvCQuCjRZZ12596QBc6uB2k5jm+SjdjoP2axtAtled4b deJqhKxirkoSs8yO/QpqAHq4IT0OzUsH7M= X-archive-position: 34511 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2234 Lines: 56 --+QahgC5+KEYLbs62 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 14, 2012 at 03:35:31PM -0700, Greg Kroah-Hartman wrote: > On Fri, Sep 14, 2012 at 02:53:11PM -0600, Bjorn Helgaas wrote: > > +cc Greg KH > >=20 > > On Fri, Sep 14, 2012 at 2:44 PM, Thierry Reding > > wrote: > > > In order to keep pci_fixup_irqs() around after init (e.g. for hotplug= ), > > > mark it __devinit instead of __init. This requires the same change for > > > the implementation of the pcibios_update_irq() function on all > > > architectures. > > > > > > Signed-off-by: Thierry Reding > > > --- > > > Note: Ideally these annotations should go away completely in order to > > > be independent of the HOTPLUG symbol. However, there is work underway > > > to get rid of HOTPLUG altogether, so I've kept the __devinit for now. >=20 > No, just take away the __init marking completly. For 3.7, > CONFIG_HOTPLUG will always be enabled, making it be the same thing. > That way this saves me the time and energy from deleting the __devinit > markings when I get to that point in the patch series :) Done. I'll give other people some time to comment before sending the updated series. Thierry --+QahgC5+KEYLbs62 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQVDTxAAoJEN0jrNd/PrOhY84P/1V6CjM7bTnYamaHDOKyZQUc IyLN3mZRN6AbMMO8awcN6B4BDXuB6ua8nN7ozdlqRnFSUgSXVwWwrezZnrpc+Sws yO4Axr8IOBxpG2IDX+d2bGWRV5W34kzty5WsZhlPEJxOBSQH0MiNJCgTojSIIf5n 9a6+7fF5qsSamGnmtWKwe01nwvlAsJg0i3sxyguWlFuBqd1IyQMCptCWsSBzMQVc 1EeCDtWdLTKzxNHhkl97rWcQYi3ov8LTK76zUutTSDlpc2+HhX0nu73Tz34fLs9m k4Z1mw2VLHRUorvFCptwhvB72LR2hssTZxGDt3xbPLERUECtV3wwpFTDT8J4jZj0 bzHCpbfj11K1Y7/Ku/1FBWBXjFPh1+YS0lA39V00WnHBx9Xv2DX6Ytm8FwGCtqEN wfV+VGyR+tvIWI6oA8vIgc/1xuMuDlrK4Ldn2uwZBHZfq28ghCiKFHasHA5RW+D/ kTA2p4Yvuujuvh6PbsvJv2h4A9Sudko6rzwlclnv7OGxsxCa624yF8YN+rqLVU9C 7Sq/vSCmpj1E3AQ9TKcnYyFYP1sUsc9BnslLNEHNly+MFRJoAMOAx3M6s/30vRJp FKyDyeWTzkjnlCYDiH/ebSQRk1tO9h6HJXnzrAAU55iJYHDxCGQ15I2emj8v/bqT 3iUVzezeZpRhZ0IPIxbq =Q8MZ -----END PGP SIGNATURE----- --+QahgC5+KEYLbs62-- From bhelgaas@google.com Sun Sep 16 00:22:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Sep 2012 00:22:44 +0200 (CEST) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:38713 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903239Ab2IOWWh (ORCPT ); Sun, 16 Sep 2012 00:22:37 +0200 Received: by lagu2 with SMTP id u2so3384018lag.36 for ; Sat, 15 Sep 2012 15:22:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-system-of-record; bh=5Wt5qkgo+oOBcu3h8EKDod3tPReHpckJ7yb6KaH2bgU=; b=JH7+btohi/2TyfzE5GKoDZF0YVfcFBB2RpB3XPn3CtutcjQnFTCIhYoMw2QgPcEYmU uHi2yIVa3Pzr6M0BZU8tpg9tBs4Slywcvy/LVCyHi2VmODhZW1hvaBJ1oWH0xyRkAELj HPRtdqZdCRyPTgo3znsEnOnavedOc6yzfESLyKTt/MKH0q3eo4m6bqbsVzRgYeinkUjH HrER5rBXWi01UJOqP1/6SiwIzpXTMPsXeHCmjckFVxP1HE18gMsVc1Q9IcjI9fmlVBiB yZf3Hff8M9qtSSMZC7l3zHs3YegSGqh/7JIEAjnjdC7/Okj0BUzWnwfQstuJz7PehNDD ZsZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-system-of-record:x-gm-message-state; bh=5Wt5qkgo+oOBcu3h8EKDod3tPReHpckJ7yb6KaH2bgU=; b=MV/3pNm0fHG2y2ALeFSLCqZaOxp5TW2+BOwMgSBkXcQ8uya+Xui3tzaNFyideoa0XI p5rBKnDN0eyNH2vfE9kFOTwc95otbg549km4A58HVrZR6VpQuMKai9bbCtUUsf3ptsLg G1FZ6FriYbac6EkbD5uGrJC3klgiaBVjFQlvyZtDLQRAzZrrYFu2gClh1Uuunv7ajetJ 6cSkrrfSbm1dRUXRig9bMARPHvppLSif/yd7sJlfcuYw6+X1WxECE0kxO8oh4wps7k0Q 2vBou0nB44dZIpKR1OJ/8t4Ha3P9ekYdGv8TGOBwZHE89V1pfT5A1y1I89yEdehZ6EsJ vcog== Received: by 10.152.114.3 with SMTP id jc3mr6171158lab.11.1347747751566; Sat, 15 Sep 2012 15:22:31 -0700 (PDT) Received: by 10.152.114.3 with SMTP id jc3mr6171113lab.11.1347747751398; Sat, 15 Sep 2012 15:22:31 -0700 (PDT) MIME-Version: 1.0 Received: by 10.112.132.73 with HTTP; Sat, 15 Sep 2012 15:22:11 -0700 (PDT) In-Reply-To: <20120915075301.GA31044@avionic-0098.mockup.avionic-design.de> References: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> <1347655456-2542-2-git-send-email-thierry.reding@avionic-design.de> <20120915075301.GA31044@avionic-0098.mockup.avionic-design.de> From: Bjorn Helgaas Date: Sat, 15 Sep 2012 16:22:11 -0600 Message-ID: Subject: Re: [PATCH 2/2] PCI: Provide a default pcibios_update_irq() To: Thierry Reding Cc: Geert Uytterhoeven , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-System-Of-Record: true X-Gm-Message-State: ALoCoQnbIur6eyJqKOpVuVPerbGLVOZB7tYTmNts9eFDFSIRIoNPd2L39kej7qqdMvuB0lb/+YXGfyvkSQqN9ak12oc/UFh1Baf6azjHinm7AIeYz4fFLRCUgAu2YiNBf/xbTlwHAjT7bkv59glJHM5lCD4zM+8qQ/WSOmbh8DgV+ANPBp/ZhC66DgD9juDB7GU8ZXRgW3aGph/KvNFuhHBJFmFu5dWHMQ== X-archive-position: 34512 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 881 Lines: 23 On Sat, Sep 15, 2012 at 1:53 AM, Thierry Reding wrote: > On Sat, Sep 15, 2012 at 09:32:10AM +0200, Geert Uytterhoeven wrote: >> On Fri, Sep 14, 2012 at 10:44 PM, Thierry Reding >> wrote: >> > --- a/drivers/pci/setup-irq.c >> > +++ b/drivers/pci/setup-irq.c >> > @@ -17,6 +17,14 @@ >> > #include >> > #include >> > >> > +void __devinit __weak pcibios_update_irq(struct pci_dev *dev, int irq) >> > +{ >> > +#ifdef CONFIG_PCI_DEBUG >> > + printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", irq, >> > + pci_name(dev)); >> >> pr_debug()? >> Or even better, dev_dbg()? > > The problem with pr_debug() and dev_dbg() is that they will be compiled > out if DEBUG is not defined. Perhaps we should pass -DDEBUG if PCI_DEBUG > is configured and make this dev_dbg()? From bhelgaas@google.com Sun Sep 16 00:23:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Sep 2012 00:24:04 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:60846 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903402Ab2IOWX7 (ORCPT ); Sun, 16 Sep 2012 00:23:59 +0200 Received: by lbbgf7 with SMTP id gf7so3441653lbb.36 for ; Sat, 15 Sep 2012 15:23:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-system-of-record; bh=+x9faSjHzvy5gI7XXn/+Hp3u80GFlk6pZyOTpUMa1Fw=; b=fAv7jg8WyuhcZQN33zmYFyA2eoP6tZCh72JRjWAiNmHMI5Qewe55BC6v0HySdgbWgW AvyqmZhb/ll2JQm+cVTTqzvfKd2NavmwP25eyK6Rp5BpebFfAPUHAkIZgqF4vYh1u2WD bvg19nr/9uI16wknCpCMtjJZBwSGMhmzjc+fNe98aay48PCYlMrC+uXcRqkwzQKYJ3D/ Puk7GQl8JSlmMQyDH0qdLA2rrhDYDhU6NSVOQ3bceH+KJiht/lr23ub5GQVKNY2ZNh3W gtidxVaNskgh98ZT6AsJ256O9naVtRd7VhWUfqqfnN5xsIkKp2by/VdW9ZplU03lDxNE OapQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-system-of-record:x-gm-message-state; bh=+x9faSjHzvy5gI7XXn/+Hp3u80GFlk6pZyOTpUMa1Fw=; b=BT7+U3d8+NCC3sYShxbCNHuAfB0jyUgK6l9rUhCXukgOEs75xW+pX4DjYZJDXekxIV fFHyMMw686rAL4ekv+KnzvL4kfJR0TJiy3t9N7QpXrIH7p08G02n2wmpn0Mhg+cKEXW7 J9IKxS028DXFP5kvaW8fCjUMoOrMdCb1HgDGtuOw/iEpbCgMIfn18CwzrU+PqzvFKxZT Yv0/MzpUuQ4mH0x1pGPeI+Ym1ZnWSQ4X1X6AglI0uEVWF47Kc5HeW9WzSeGj7rUl6iAg FffExh/jCJ+3dxmDWfyusQJbBHTnQ7BBLbe/fscaxgVujP0L3CmlVptYzYt3n7JydhF0 FQug== Received: by 10.112.26.106 with SMTP id k10mr2521823lbg.100.1347747833588; Sat, 15 Sep 2012 15:23:53 -0700 (PDT) Received: by 10.112.26.106 with SMTP id k10mr2521780lbg.100.1347747833420; Sat, 15 Sep 2012 15:23:53 -0700 (PDT) MIME-Version: 1.0 Received: by 10.112.132.73 with HTTP; Sat, 15 Sep 2012 15:23:33 -0700 (PDT) In-Reply-To: <20120915075301.GA31044@avionic-0098.mockup.avionic-design.de> References: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> <1347655456-2542-2-git-send-email-thierry.reding@avionic-design.de> <20120915075301.GA31044@avionic-0098.mockup.avionic-design.de> From: Bjorn Helgaas Date: Sat, 15 Sep 2012 16:23:33 -0600 Message-ID: Subject: Re: [PATCH 2/2] PCI: Provide a default pcibios_update_irq() To: Thierry Reding Cc: Geert Uytterhoeven , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-System-Of-Record: true X-Gm-Message-State: ALoCoQkj7OFNqjL/srkpisa8dn4WkNfvdBwlIJmfuFB+QgdHM4p43bD15UY2EalD/lNxNY3d4SGgLCThLX1F4RP2G8uUCSdthW6u3jBebXPymsyZ9tfupweiGB6kyw//mKntoOS7HAn2bT1e7G4poFB0l8qQcJIT81eUhlFyx5OL7v7GSp4N7y5UZlMzxrFIbxgnqOiZwJ/M6XZnSTCTBbTU4P2+Eq7UKw== X-archive-position: 34513 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1055 Lines: 31 On Sat, Sep 15, 2012 at 1:53 AM, Thierry Reding wrote: > On Sat, Sep 15, 2012 at 09:32:10AM +0200, Geert Uytterhoeven wrote: >> On Fri, Sep 14, 2012 at 10:44 PM, Thierry Reding >> wrote: >> > --- a/drivers/pci/setup-irq.c >> > +++ b/drivers/pci/setup-irq.c >> > @@ -17,6 +17,14 @@ >> > #include >> > #include >> > >> > +void __devinit __weak pcibios_update_irq(struct pci_dev *dev, int irq) >> > +{ >> > +#ifdef CONFIG_PCI_DEBUG >> > + printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", irq, >> > + pci_name(dev)); >> >> pr_debug()? >> Or even better, dev_dbg()? > > The problem with pr_debug() and dev_dbg() is that they will be compiled > out if DEBUG is not defined. Perhaps we should pass -DDEBUG if PCI_DEBUG > is configured and make this dev_dbg()? Sorry, fat-fingered the previous empty response. We already have this in drivers/pci/Makefile: ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG so dev_dbg() should be perfect. From macro@linux-mips.org Sun Sep 16 00:42:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Sep 2012 00:42:30 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:52574 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903239Ab2IOWmX (ORCPT ); Sun, 16 Sep 2012 00:42:23 +0200 Date: Sat, 15 Sep 2012 23:42:23 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: linux-mips@linux-mips.org Subject: Re: MIPS: Fix build error with modern GCC for non-Cavium. In-Reply-To: <20120910171157.GC24448@linux-mips.org> Message-ID: References: <20120910171157.GC24448@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 34514 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Status: RO Content-Length: 866 Lines: 18 On Mon, 10 Sep 2012, Ralf Baechle wrote: > > A dummy "break" is the usual solution though. I don't think GCC ever > > complains if it sees it unreachable after a "return" -- in a sense it is > > just as unreachable as this null instruction is. > > I wasn't overly picky. Whatever gets the stuff to build correctly. I'm > doing one final round of test builds over all -stable branches before > dropping most of them like radioctive rocks. But more on that later. Yeah, sure -- I just noted this is not breaking a new ground really. There was a time GCC used to support genuinely empty switch cases and that was removed at one point for better ISO C compliance. There was a rush fixing code all over the place at that point, including some "proper" GNU software such as I reckon bison, and the common approach taken was that I referred to. Maciej From tdent48227@gmail.com Sun Sep 16 05:34:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Sep 2012 05:34:16 +0200 (CEST) Received: from mail-we0-f177.google.com ([74.125.82.177]:52596 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901346Ab2IPDeI (ORCPT ); Sun, 16 Sep 2012 05:34:08 +0200 Received: by weyr3 with SMTP id r3so3331133wey.36 for ; Sat, 15 Sep 2012 20:34:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=rcjemwNKPbaqscMW//HK/vQZjM6O5+pnlTVp0RrZz4A=; b=dVBrDJXktYSjHL71Zgxilpjmj/darLjN+WtPc2xG9IKSJc4CuoycbLcnrmTelNhcLY pY0g4uKuHd7oaGmdUXlywTVe73cDUNo/XaCcQduXKfqwxtocedzds77TOYX1Oy7UABZE K6rkP5FQnCQi6lUPgzk8ERVZfXzzs/Rn48SA/nMsP+8ilCpyqBGIpjq9Alk30x2kqd+d 4ids3h19AMmmn9WCp853NZeARyWKdsoY3E+3hzqsY6Mc3M8GxpzlSoVGWuIU8Hk5+AR4 sU2mkJkCpb14j92RTaLGO8UjBzuyB1K6Vh2uNu8zgebN9KEg8wIIt25HTqQ9WJNQeaTE 4MIw== MIME-Version: 1.0 Received: by 10.180.106.97 with SMTP id gt1mr7716094wib.5.1347766443321; Sat, 15 Sep 2012 20:34:03 -0700 (PDT) Received: by 10.216.121.210 with HTTP; Sat, 15 Sep 2012 20:34:03 -0700 (PDT) In-Reply-To: <50519848.6050901@openwrt.org> References: <1347490239-1351-1-git-send-email-tdent48227@gmail.com> <50519848.6050901@openwrt.org> Date: Sat, 15 Sep 2012 23:34:03 -0400 Message-ID: Subject: Re: [PATCH 1/1] Arch: mips: Delete Makefile.rej From: Tracey Dent To: John Crispin Cc: akpm@linux-foundation.org, richard -rw- weinberger , linux-kernel@vger.kernel.org, Ralf Baechle , "linux-mips@linux-mips.org" Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 34515 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tdent48227@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 613 Lines: 25 On 9/13/12, John Crispin wrote: > On 13/09/12 01:15, richard -rw- weinberger wrote: >> On Thu, Sep 13, 2012 at 12:50 AM, Tracey Dent >> wrote: >>> Makefile.rej should not be there. That was introduced >>> in commit 3fa68afc3d774bab1e91cbb3a3cdd1e36068ee95 . >> Linus' tree does not contain such a commit id. >> Your right but its in linux-next > > Hi, > > my bad .. its in linux-next (3fa68afc3d774bab1e91cbb3a3cdd1e36068ee95) > and comes from the upstream-sfr tree on linux-mips.org > > i will talk to Ralf and fix it inside the lmo tree. Okay > > Thanks, > John > From thierry.reding@avionic-design.de Sun Sep 16 08:51:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Sep 2012 08:51:56 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.186]:64040 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901346Ab2IPGvu (ORCPT ); Sun, 16 Sep 2012 08:51:50 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap4) with ESMTP (Nemesis) id 0M6lyG-1TPHj42unc-00wW7k; Sun, 16 Sep 2012 08:50:43 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id B6EC82A282EA; Sun, 16 Sep 2012 08:50:41 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QiYHvGJzmAsz; Sun, 16 Sep 2012 08:50:39 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 739812A280C0; Sun, 16 Sep 2012 08:50:39 +0200 (CEST) Date: Sun, 16 Sep 2012 08:50:38 +0200 From: Thierry Reding To: Bjorn Helgaas Cc: Geert Uytterhoeven , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH 2/2] PCI: Provide a default pcibios_update_irq() Message-ID: <20120916065038.GB11030@avionic-0098.mockup.avionic-design.de> References: <1347655456-2542-1-git-send-email-thierry.reding@avionic-design.de> <1347655456-2542-2-git-send-email-thierry.reding@avionic-design.de> <20120915075301.GA31044@avionic-0098.mockup.avionic-design.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="8GpibOaaTibBMecb" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:EkMl3hHk5YfsOSdCevVlgtpPEoeHE8N0MWpcfsVR7t6 0M+LIsicD2sFuhx4GLfzcGs0GW/HfNHC/ePGpoIHsCjyKZGnTw d++nxw9/G3YqJ8V3WEc38bHzwrT4o8eOZst5uretJf/w2JGvIM Q43CvklyK4HD75jmiBYss4rZufeupfvQQ8HNM29PG/2AeaxQgs dSZ2hQdvxkLs5Gcqce4iXCogwg4dGRwP3QjmodI7lzl9k1NvBW Je0U/I45FV5Oo3GV/OsEEWoshN44OjQVwJIhRfhuiCh0U8RL19 fDo1sr5G2v1kDETH1bMZSMAXNhTaWxKPpTALAYkYck+zZOclhC VPyd7m7+4p4/kpw3kzPAc/VrPklL0Sj1Q4KkMYldYLKvNffqas cNKAI//TEIjg5vt83u96RBzzAR7wThmhqZxR0L3gX3PyNd/F6l r5l8u X-archive-position: 34516 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2382 Lines: 67 --8GpibOaaTibBMecb Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Sep 15, 2012 at 04:23:33PM -0600, Bjorn Helgaas wrote: > On Sat, Sep 15, 2012 at 1:53 AM, Thierry Reding > wrote: > > On Sat, Sep 15, 2012 at 09:32:10AM +0200, Geert Uytterhoeven wrote: > >> On Fri, Sep 14, 2012 at 10:44 PM, Thierry Reding > >> wrote: > >> > --- a/drivers/pci/setup-irq.c > >> > +++ b/drivers/pci/setup-irq.c > >> > @@ -17,6 +17,14 @@ > >> > #include > >> > #include > >> > > >> > +void __devinit __weak pcibios_update_irq(struct pci_dev *dev, int i= rq) > >> > +{ > >> > +#ifdef CONFIG_PCI_DEBUG > >> > + printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", irq, > >> > + pci_name(dev)); > >> > >> pr_debug()? > >> Or even better, dev_dbg()? > > > > The problem with pr_debug() and dev_dbg() is that they will be compiled > > out if DEBUG is not defined. Perhaps we should pass -DDEBUG if PCI_DEBUG > > is configured and make this dev_dbg()? >=20 > Sorry, fat-fingered the previous empty response. >=20 > We already have this in drivers/pci/Makefile: >=20 > ccflags-$(CONFIG_PCI_DEBUG) :=3D -DDEBUG >=20 > so dev_dbg() should be perfect. Yeah, this occurred to me as well and I was just about to look it up when I read your response. I'll make it dev_dbg() then. Thierry --8GpibOaaTibBMecb Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQVXa+AAoJEN0jrNd/PrOh00IQAJSTG1Ukqu3ay8m7AznzjD2Y eRN6wDO0Pd37qkHr46rMO2UVPCavDFnoS6gsGhuTzdQgIOnVO9NKGUPm71xAhBnt Yq+rYhg8i2cHNjZVKy8Kn5EY0Ly8k0yunH1KFMEodzeS2ZU/wrHSJZmkyKIUzMdN AdMoFV81Q7So+JEdG1zIaM1hsDl3t18gt+9SlRSJZ6T4kXlv0j1pD9Jy2d0OC7bx Yu8DDnNI33FIcZQnHsO50okCU0o4SqZHFmL/xm4Aa3JiQ5H4gMKiCYNXvFQ5M/gr jU+cj0P1WdIPQVof9uie8TCiPCtNEJMbUQsgbhQuFf6eEefuUIbqkfETjmY8rNk9 NoNp1anLNxxxp2L17e8dN9VTJgNUi+lrpvcG6gqVBs7rE9ruo/6NVnFHwUUHd3Q3 o9ivpbuYPfJCRSW1r+TbE74iVQdg7jKO+p1cIZjMQOcv9B88M8KJaS60wpgxn9S+ f/eLoMlUK2wIbP3Zj4MR3DIorUOTyi7f14+J448Y5D9Ci86QU/+4bmMexqEVxsRS Un+iARiZQlrWnmVjva4iG8g2mOxcmDPzHSlcE9+uIIdNdPCUWusrt81PAyIjTlUX xo2R3G3LIVA4lfOiUSdQB2RYPmQHAXW/Tul5aBvXk11jsl0BN1Hbk2qO4641Puej LLzcEjPu0384yupX0hSL =/+fm -----END PGP SIGNATURE----- --8GpibOaaTibBMecb-- From hauke@hauke-m.de Sun Sep 16 16:48:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Sep 2012 16:48:47 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:46459 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903241Ab2IPOso (ORCPT ); Sun, 16 Sep 2012 16:48:44 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 8E4B88E1C; Sun, 16 Sep 2012 16:48:43 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IAKcFK4e-Woz; Sun, 16 Sep 2012 16:48:40 +0200 (CEST) Received: from hauke.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id C817E87B9; Sun, 16 Sep 2012 16:48:39 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org, john@phrozen.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 1/2] MIPS: BCM47XX: select BOOT_RAW Date: Sun, 16 Sep 2012 16:48:34 +0200 Message-Id: <1347806915-25132-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 34517 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 725 Lines: 25 All the boot loaders I have seen are booting the kernel in raw mode by default. CFE seams to support elf kernel images too, but the default case is raw for the devices I know of. Select this option to make the kernel boot on most of the devices with the default options. Signed-off-by: Hauke Mehrtens --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fa171a3..564a06f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -102,6 +102,7 @@ config ATH79 config BCM47XX bool "Broadcom BCM47XX based boards" select ARCH_REQUIRE_GPIOLIB + select BOOT_RAW select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT -- 1.7.9.5 From hauke@hauke-m.de Sun Sep 16 16:48:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Sep 2012 16:49:12 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:46462 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903242Ab2IPOso (ORCPT ); Sun, 16 Sep 2012 16:48:44 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 2238E87B9; Sun, 16 Sep 2012 16:48:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AjfuMfz-vWit; Sun, 16 Sep 2012 16:48:40 +0200 (CEST) Received: from hauke.lan (unknown [134.102.133.158]) by hauke-m.de (Postfix) with ESMTPSA id 188088880; Sun, 16 Sep 2012 16:48:40 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org, john@phrozen.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 2/2] MIPS BCM47XX: select NO_EXCEPT_FILL Date: Sun, 16 Sep 2012 16:48:35 +0200 Message-Id: <1347806915-25132-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1347806915-25132-1-git-send-email-hauke@hauke-m.de> References: <1347806915-25132-1-git-send-email-hauke@hauke-m.de> X-archive-position: 34518 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 634 Lines: 24 The kernel is loaded to 0x80001000 so there is some space left for the exception handlers and the kernel do not have to reserve some extra space for them. Signed-off-by: Hauke Mehrtens --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 564a06f..e372fe3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -108,6 +108,7 @@ config BCM47XX select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU + select NO_EXCEPT_FILL select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -- 1.7.9.5 From cernekee@gmail.com Sun Sep 16 17:38:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Sep 2012 17:38:40 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:62413 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903052Ab2IPPid (ORCPT ); Sun, 16 Sep 2012 17:38:33 +0200 Received: by eaai12 with SMTP id i12so2046096eaa.36 for ; Sun, 16 Sep 2012 08:38:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=htV8wC9q/4GjeN07lmsoUzdY0tQUFc2M1i88ToaEvEY=; b=q+C3Zaf8Am+6vgi9GEaL08Y7ni0K0cTgBInV0nlgwgBMa8iWM1wx5iNiuytpTVrdW7 29SCNr2GpPH6SJKjafP4ueFdwcLYVXonc1aAB9Pk3RA9cuT3vbMXa5VKNYWChhdWn8c7 qIYMD3C05UdrgAwLZ6aQHG/bqebC9ciTe4J73l02ZTqjy6UjJ/BkaQMsZaFOc9eam0xe +Zpi0SAEQz2PkosLCZ3UXdFWfNwicIEht2/Be1R33A7HuELGP0nQGcQn2kC8UPQ3FXuN d2LyiSojxRsPgPXcqhUhGiWaNWjfat96E4WAUX0lPCdFic5xWCmRbZE5PTZvipQRYeuV c+JQ== MIME-Version: 1.0 Received: by 10.14.173.9 with SMTP id u9mr10543738eel.8.1347809908368; Sun, 16 Sep 2012 08:38:28 -0700 (PDT) Received: by 10.14.179.71 with HTTP; Sun, 16 Sep 2012 08:38:28 -0700 (PDT) In-Reply-To: <1347806915-25132-1-git-send-email-hauke@hauke-m.de> References: <1347806915-25132-1-git-send-email-hauke@hauke-m.de> Date: Sun, 16 Sep 2012 08:38:28 -0700 Message-ID: Subject: Re: [PATCH 1/2] MIPS: BCM47XX: select BOOT_RAW From: Kevin Cernekee To: ralf@linux-mips.org, Hauke Mehrtens Cc: john@phrozen.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 34519 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 665 Lines: 15 On Sun, Sep 16, 2012 at 7:48 AM, Hauke Mehrtens wrote: > All the boot loaders I have seen are booting the kernel in raw mode by > default. CFE seams to support elf kernel images too, but the default Nitpick: "seems" > case is raw for the devices I know of. Select this option to make the > kernel boot on most of the devices with the default options. CONFIG_BOOT_RAW only adds about 8 bytes to the kernel image. Since early 2008 it's just been implemented as a single jump instruction, and it's harmless on platforms that don't need it. Do you think it is worthwhile to delete the Kconfig option, and enable BOOT_RAW behavior on all builds? From thierry.reding@avionic-design.de Mon Sep 17 13:23:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Sep 2012 13:24:03 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:64590 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903256Ab2IQLXy (ORCPT ); Mon, 17 Sep 2012 13:23:54 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu4) with ESMTP (Nemesis) id 0Ln0mX-1TjLSh1cfV-00hJbE; Mon, 17 Sep 2012 13:22:59 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 6A0412A282F7; Mon, 17 Sep 2012 13:22:57 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7VWzLCc5bZ-r; Mon, 17 Sep 2012 13:22:55 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 68D9E2A2817A; Mon, 17 Sep 2012 13:22:55 +0200 (CEST) From: Thierry Reding To: Bjorn Helgaas Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , Greg Kroah-Hartman , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 1/2] PCI: Keep pci_fixup_irqs() around after init Date: Mon, 17 Sep 2012 13:22:53 +0200 Message-Id: <1347880974-13615-1-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 X-Provags-ID: V02:K0:UNn0Y9Uxpibd86Z8HLmLW1v1HhxUZwWTQQydDy8lfMW RPzJEAlPkuH/B384PhRysvdLiElSbxmn3chQ6bs2amUuGMdMjG sho+YaOZXH5/F87wiJT5Om3fGGEWd5/Zrj5lM+98XEf1BZEHMs 2gUZSZlSn1giVHfmSrjAzBODog/uS+PmQWTe++rqUwcEZgoc6c ngDyo0LlTCzHdkFjCPspIbadCUj3Y4udWy+I7k7L0LI30vwUBZ Ufb6mqb87nKvFYN70okAnoNwKw9ixkWV7AA4tLTakR7FjpnOCq uRypqZONIM4KYXgu4iacR1xBJuQhK6Fu8a9GxLWfMfE+nkHCqY AmqgtDhyGle3koRwVvdb2d8CgZ87oJbB4V9tkKHUECGhnY9wxR Q5qA/X5/g7QJqq/BaORdmmKVB0vzbddkNQTOgawD0sKo1mUudn 2gfXz X-archive-position: 34520 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6249 Lines: 193 Remove the __init annotations in order to keep pci_fixup_irqs() around after init (e.g. for hotplug). This requires the same change for the implementation of pcibios_update_irq() on all architectures. While at it, all __devinit annotations are removed as well, since they will be useless now that HOTPLUG is always on. Signed-off-by: Thierry Reding --- Changes in v2: - remove __init and __devinit annotations altogether arch/alpha/kernel/pci.c | 2 +- arch/arm/kernel/bios32.c | 2 +- arch/ia64/pci/pci.c | 2 +- arch/mips/pci/pci.c | 2 +- arch/sh/drivers/pci/pci.c | 2 +- arch/sparc/kernel/leon_pci.c | 2 +- arch/tile/kernel/pci.c | 2 +- arch/tile/kernel/pci_gx.c | 2 +- arch/unicore32/kernel/pci.c | 2 +- arch/x86/pci/visws.c | 2 +- arch/xtensa/kernel/pci.c | 2 +- drivers/pci/setup-irq.c | 4 ++-- 12 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c index 9816d5a..920392f 100644 --- a/arch/alpha/kernel/pci.c +++ b/arch/alpha/kernel/pci.c @@ -256,7 +256,7 @@ pcibios_fixup_bus(struct pci_bus *bus) } } -void __init +void pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 2b2f25e..0174fe6 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -272,7 +272,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) +void pcibios_update_irq(struct pci_dev *dev, int irq) { if (debug_pci) printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev)); diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c index 81acc7a..27db6a8 100644 --- a/arch/ia64/pci/pci.c +++ b/arch/ia64/pci/pci.c @@ -461,7 +461,7 @@ void pcibios_set_master (struct pci_dev *dev) /* No special bus mastering setup handling */ } -void __devinit +void pcibios_update_irq (struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 6903568..64f0419 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -313,7 +313,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) } } -void __init +void pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index 40db2d0..1bd3e08 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -192,7 +192,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pci_enable_resources(dev, mask); } -void __init pcibios_update_irq(struct pci_dev *dev, int irq) +void pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c index 21dcda7..404621b 100644 --- a/arch/sparc/kernel/leon_pci.c +++ b/arch/sparc/kernel/leon_pci.c @@ -102,7 +102,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pci_enable_resources(dev, mask); } -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) +void pcibios_update_irq(struct pci_dev *dev, int irq) { #ifdef CONFIG_PCI_DEBUG printk(KERN_DEBUG "LEONPCI: Assigning IRQ %02d to %s\n", irq, diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index 33c1086..6245bba 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -406,7 +406,7 @@ void pcibios_set_master(struct pci_dev *dev) /* * This is called from the generic Linux layer. */ -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) +void pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index 0e213e3..5faad0b 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c @@ -1036,7 +1036,7 @@ char __devinit *pcibios_setup(char *str) /* * This is called from the generic Linux layer. */ -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) +void pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c index 46cb6c9..c07ecc5 100644 --- a/arch/unicore32/kernel/pci.c +++ b/arch/unicore32/kernel/pci.c @@ -154,7 +154,7 @@ void __init puv3_pci_adjust_zones(unsigned long *zone_size, zhole_size[0] = 0; } -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) +void pcibios_update_irq(struct pci_dev *dev, int irq) { if (debug_pci) printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", diff --git a/arch/x86/pci/visws.c b/arch/x86/pci/visws.c index 6f2f8ee..9d736e7 100644 --- a/arch/x86/pci/visws.c +++ b/arch/x86/pci/visws.c @@ -62,7 +62,7 @@ out: return irq; } -void __init pcibios_update_irq(struct pci_dev *dev, int irq) +void pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c index 69759e9..6f9b40c 100644 --- a/arch/xtensa/kernel/pci.c +++ b/arch/xtensa/kernel/pci.c @@ -212,7 +212,7 @@ void pcibios_set_master(struct pci_dev *dev) /* the next one is stolen from the alpha port... */ -void __init +void pcibios_update_irq(struct pci_dev *dev, int irq) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c index eb219a1..270ae7b 100644 --- a/drivers/pci/setup-irq.c +++ b/drivers/pci/setup-irq.c @@ -18,7 +18,7 @@ #include -static void __init +static void pdev_fixup_irq(struct pci_dev *dev, u8 (*swizzle)(struct pci_dev *, u8 *), int (*map_irq)(const struct pci_dev *, u8, u8)) @@ -54,7 +54,7 @@ pdev_fixup_irq(struct pci_dev *dev, pcibios_update_irq(dev, irq); } -void __init +void pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *), int (*map_irq)(const struct pci_dev *, u8, u8)) { -- 1.7.12 From thierry.reding@avionic-design.de Mon Sep 17 13:23:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Sep 2012 13:24:29 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:60065 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903258Ab2IQLX7 (ORCPT ); Mon, 17 Sep 2012 13:23:59 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu3) with ESMTP (Nemesis) id 0Mfeu7-1St1ku2MbT-00P5p2; Mon, 17 Sep 2012 13:23:01 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 888252A2817A; Mon, 17 Sep 2012 13:22:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HQ5iAL5Yv9T4; Mon, 17 Sep 2012 13:22:56 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 8405D2A282AA; Mon, 17 Sep 2012 13:22:56 +0200 (CEST) From: Thierry Reding To: Bjorn Helgaas Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , Greg Kroah-Hartman , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 2/2] PCI: Provide a default pcibios_update_irq() Date: Mon, 17 Sep 2012 13:22:54 +0200 Message-Id: <1347880974-13615-2-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347880974-13615-1-git-send-email-thierry.reding@avionic-design.de> References: <1347880974-13615-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:NUiyNRXCLpLU54zzRebEnGKZG334sFWr2heirloIyGn Iu/D32iAzingKJNjwkboqkHyLx/q4UjhwRLei8PZhxVnSa7mdR FIhVLgLooTM9240izmpG034vA3w6HQDtmWqUfZ2k7St4EZh4BN cBxDyWAGjWlzuFDG5hp6ifHvwly5juS7NuJQQB9oVGMFt4abFb 6eExTi2vbZfVxqTRFhdO1lXq2JohO62n80Njb59PxNRcM7mzeg 6FjJpjGwe3dtUVGouJuhy6lvZldEmmXLbs5xb/38ctNzy//vyh nnji7uK1UxT9aQaIro5x9FwGsC9UogE60IfU6wkaa2sWOf57AA eA9VfG72wLOYte1Jj9evl3eMIb62x9/jfF2ba4n8ipPJ47GteN U/Mtm37aLQyy5jlKghZFhfA0vDm95eFVoLaRYx6G1gN9j2B0PY LvvlU X-archive-position: 34521 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8823 Lines: 290 Most architectures implement this in exactly the same way. Instead of having each architecture duplicate this function, provide a single implementation in the core and make it a weak symbol so that it can be overridden on architectures where it is required. Signed-off-by: Thierry Reding --- Note: ARM and Unicore32 did use a debug_pci variable to check whether or not to output a debug message in pcibios_update_irq(). SPARC/LEON checks for CONFIG_PCI_DEBUG instead. I've adopted the SPARC variant in this patch. I assumed that in the interest of unification this would be a good compromise. If not, please let me know. Also, SPARC64 had an empty pcibios_update_irq(). I've opted to drop it in favour of the default implementation, which just writes a single byte in the device's configuration space. I assumed that this should still work but perhaps was just not used on SPARC64. If this is known to break SPARC64 I can keep the noop implementation. Changes in v2: - drop __devinit annotation - use dev_dbg() arch/alpha/kernel/pci.c | 6 ------ arch/arm/kernel/bios32.c | 9 --------- arch/ia64/pci/pci.c | 8 -------- arch/m68k/kernel/pcibios.c | 5 ----- arch/mips/pci/pci.c | 6 ------ arch/sh/drivers/pci/pci.c | 5 ----- arch/sparc/kernel/leon_pci.c | 9 --------- arch/sparc/kernel/pci.c | 4 ---- arch/tile/kernel/pci.c | 8 -------- arch/tile/kernel/pci_gx.c | 8 -------- arch/unicore32/kernel/pci.c | 8 -------- arch/x86/pci/visws.c | 5 ----- arch/xtensa/kernel/pci.c | 8 -------- drivers/pci/setup-irq.c | 5 +++++ 14 files changed, 5 insertions(+), 89 deletions(-) diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c index 920392f..ef75714 100644 --- a/arch/alpha/kernel/pci.c +++ b/arch/alpha/kernel/pci.c @@ -256,12 +256,6 @@ pcibios_fixup_bus(struct pci_bus *bus) } } -void -pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - int pcibios_enable_device(struct pci_dev *dev, int mask) { diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 0174fe6..9cf16b8 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -270,15 +270,6 @@ static void __devinit pci_fixup_it8152(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); - - -void pcibios_update_irq(struct pci_dev *dev, int irq) -{ - if (debug_pci) - printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev)); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - /* * If the bus contains any of these devices, then we must not turn on * parity checking of any kind. Currently this is CyberPro 20x0 only. diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c index 27db6a8..a7ebe94 100644 --- a/arch/ia64/pci/pci.c +++ b/arch/ia64/pci/pci.c @@ -461,14 +461,6 @@ void pcibios_set_master (struct pci_dev *dev) /* No special bus mastering setup handling */ } -void -pcibios_update_irq (struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); - - /* ??? FIXME -- record old value for shutdown. */ -} - int pcibios_enable_device (struct pci_dev *dev, int mask) { diff --git a/arch/m68k/kernel/pcibios.c b/arch/m68k/kernel/pcibios.c index b2988aa..73fa0b5 100644 --- a/arch/m68k/kernel/pcibios.c +++ b/arch/m68k/kernel/pcibios.c @@ -87,11 +87,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return 0; } -void pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - void __devinit pcibios_fixup_bus(struct pci_bus *bus) { struct pci_dev *dev; diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 64f0419..04e35bc 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -313,12 +313,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) } } -void -pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - #ifdef CONFIG_HOTPLUG EXPORT_SYMBOL(PCIBIOS_MIN_IO); EXPORT_SYMBOL(PCIBIOS_MIN_MEM); diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index 1bd3e08..a7e078f 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -192,11 +192,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pci_enable_resources(dev, mask); } -void pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - static void __init pcibios_bus_report_status_early(struct pci_channel *hose, int top_bus, int current_bus, diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c index 404621b..fc05211 100644 --- a/arch/sparc/kernel/leon_pci.c +++ b/arch/sparc/kernel/leon_pci.c @@ -102,15 +102,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pci_enable_resources(dev, mask); } -void pcibios_update_irq(struct pci_dev *dev, int irq) -{ -#ifdef CONFIG_PCI_DEBUG - printk(KERN_DEBUG "LEONPCI: Assigning IRQ %02d to %s\n", irq, - pci_name(dev)); -#endif - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - /* in/out routines taken from pcic.c * * This probably belongs here rather than ioport.c because diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index 065b88c..acc8c83 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c @@ -622,10 +622,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *pbus) { } -void pcibios_update_irq(struct pci_dev *pdev, int irq) -{ -} - resource_size_t pcibios_align_resource(void *data, const struct resource *res, resource_size_t size, resource_size_t align) { diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index 6245bba..dbdab34 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -404,14 +404,6 @@ void pcibios_set_master(struct pci_dev *dev) } /* - * This is called from the generic Linux layer. - */ -void pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - -/* * Enable memory and/or address decoding, as appropriate, for the * device described by the 'dev' struct. * diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index 5faad0b..2ba6d05 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c @@ -1034,14 +1034,6 @@ char __devinit *pcibios_setup(char *str) } /* - * This is called from the generic Linux layer. - */ -void pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - -/* * Enable memory address decoding, as appropriate, for the * device described by the 'dev' struct. The I/O decoding * is disabled, though the TILE-Gx supports I/O addressing. diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c index c07ecc5..b0056f6 100644 --- a/arch/unicore32/kernel/pci.c +++ b/arch/unicore32/kernel/pci.c @@ -154,14 +154,6 @@ void __init puv3_pci_adjust_zones(unsigned long *zone_size, zhole_size[0] = 0; } -void pcibios_update_irq(struct pci_dev *dev, int irq) -{ - if (debug_pci) - printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", - irq, pci_name(dev)); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - /* * If the bus contains any of these devices, then we must not turn on * parity checking of any kind. diff --git a/arch/x86/pci/visws.c b/arch/x86/pci/visws.c index 9d736e7..3e6d2a6 100644 --- a/arch/x86/pci/visws.c +++ b/arch/x86/pci/visws.c @@ -62,11 +62,6 @@ out: return irq; } -void pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - int __init pci_visws_init(void) { pcibios_enable_irq = &pci_visws_enable_irq; diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c index 6f9b40c..54354de 100644 --- a/arch/xtensa/kernel/pci.c +++ b/arch/xtensa/kernel/pci.c @@ -210,14 +210,6 @@ void pcibios_set_master(struct pci_dev *dev) /* No special bus mastering setup handling */ } -/* the next one is stolen from the alpha port... */ - -void -pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - int pcibios_enable_device(struct pci_dev *dev, int mask) { u16 cmd, old_cmd; diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c index 270ae7b..3d61ce3 100644 --- a/drivers/pci/setup-irq.c +++ b/drivers/pci/setup-irq.c @@ -17,6 +17,11 @@ #include #include +void __weak pcibios_update_irq(struct pci_dev *dev, int irq) +{ + dev_dbg(&dev->dev, "Assigning IRQ %02d\n", irq); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); +} static void pdev_fixup_irq(struct pci_dev *dev, -- 1.7.12 From gregkh@linuxfoundation.org Mon Sep 17 13:34:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Sep 2012 13:34:41 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:40831 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903258Ab2IQLef (ORCPT ); Mon, 17 Sep 2012 13:34:35 +0200 Received: by dajq27 with SMTP id q27so2899847daj.36 for ; Mon, 17 Sep 2012 04:34:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=Jb90C30WpfPy43Af+wGr+Cqydq32MkjWJVv+/wuHIV8=; b=DLwVMFcaccX5kf+4/CL95yySE/zTb2YpYJcqIWfj8HqzYqwjCD8yafF9WKGfZpF3hL bXCOywzsGj2HzZsFHS1/JXIU/N2oUu678PmYmBcR/lC1YmzyNh2liwR3YrtyTtprWRJN CM3WZLbOQ2tkkPHcoVZZgBX0RapI4146Z552K/4LrApEdZ8169uti17FbDbC3f3SvSmO 1xEXNw0XUDrFOnzKlUPID49LYxHhlQBHF9CktCszbiE9+g5hWGkEHe/aiJMoESivL4qI Bt98bbLWl4S7JBAi9fHuPhtH62uULPzlRCukEjiqNKbc8WQuG9aUIl4kLyuNSFc1oR37 hBaw== Received: by 10.66.88.198 with SMTP id bi6mr19927640pab.23.1347881668748; Mon, 17 Sep 2012 04:34:28 -0700 (PDT) Received: from localhost (c-67-168-183-230.hsd1.wa.comcast.net. [67.168.183.230]) by mx.google.com with ESMTPS id gf3sm6785549pbc.74.2012.09.17.04.34.24 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 17 Sep 2012 04:34:26 -0700 (PDT) Date: Mon, 17 Sep 2012 04:34:23 -0700 From: Greg Kroah-Hartman To: Thierry Reding Cc: Bjorn Helgaas , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v2 1/2] PCI: Keep pci_fixup_irqs() around after init Message-ID: <20120917113423.GA28759@kroah.com> References: <1347880974-13615-1-git-send-email-thierry.reding@avionic-design.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1347880974-13615-1-git-send-email-thierry.reding@avionic-design.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQnmW780MY8DYW7Z84Wqv+puoeJN2wlxalQCfm3Cn/gaacjE7xQH4A4FKHA8IXZfkS3xR3vE X-archive-position: 34522 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 600 Lines: 13 On Mon, Sep 17, 2012 at 01:22:53PM +0200, Thierry Reding wrote: > Remove the __init annotations in order to keep pci_fixup_irqs() around > after init (e.g. for hotplug). This requires the same change for the > implementation of pcibios_update_irq() on all architectures. While at > it, all __devinit annotations are removed as well, since they will be > useless now that HOTPLUG is always on. > > Signed-off-by: Thierry Reding > --- > Changes in v2: > - remove __init and __devinit annotations altogether Acked-by: Greg Kroah-Hartman From geert@linux-m68k.org Mon Sep 17 22:20:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Sep 2012 22:20:31 +0200 (CEST) Received: from juliette.telenet-ops.be ([195.130.137.74]:49198 "EHLO juliette.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903405Ab2IQUUX (ORCPT ); Mon, 17 Sep 2012 22:20:23 +0200 Received: from ayla.of.borg ([84.193.72.141]) by juliette.telenet-ops.be with bizsmtp id 0LLM1k00z32ts5g06LLM38; Mon, 17 Sep 2012 22:20:22 +0200 Received: from geert by ayla.of.borg with local (Exim 4.71) (envelope-from ) id 1TDhnp-0002u9-Nu; Mon, 17 Sep 2012 22:20:21 +0200 From: Geert Uytterhoeven To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-next@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH -next] MIPS: ptrace: Add missing #include Date: Mon, 17 Sep 2012 22:20:16 +0200 Message-Id: <1347913216-11140-1-git-send-email-geert@linux-m68k.org> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 34523 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Status: RO X-Status: A Content-Length: 769 Lines: 26 arch/mips/kernel/ptrace.c: In function ‘syscall_trace_enter’: arch/mips/kernel/ptrace.c:664: error: implicit declaration of function ‘__syscall_get_arch’ make[2]: *** [arch/mips/kernel/ptrace.o] Error 1 Signed-off-by: Geert Uytterhoeven --- E.g. http://kisskb.ellerman.id.au/kisskb/buildresult/7223557/ arch/mips/kernel/ptrace.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 94fd0f4..cc7c44f 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -40,6 +40,7 @@ #include #include #include +#include /* * Called by kernel/ptrace.c when detaching.. -- 1.7.0.4 From jonas.gorski@gmail.com Tue Sep 18 11:29:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Sep 2012 11:29:49 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:58921 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903269Ab2IRJ3k (ORCPT ); Tue, 18 Sep 2012 11:29:40 +0200 Received: by bkcji2 with SMTP id ji2so3082621bkc.36 for ; Tue, 18 Sep 2012 02:29:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=xI/qCL12pns6tTxYIHcox1v2nAhdHt1YUOmhHgaLGnM=; b=WLtjJi3GjMX3z3we8viOc/kl+gkJK5gurIJHX4P+8nmyOKXnVjOQGAIKc065p56nm5 ED1YML9MPBvxOeWTxwCyt8kHkhnPlXVLzIRWNI37ZPD2hSGvk60g4mY5D+HlE80c9dP4 9OQ+08ncmYgdk9DPMxv6zeqrjQdQ0Wr3I+8CslJ02KPINuXCWtF3TAEzwiLeFEVLL0nN SZT01XMA/CZpDEIizDsn9wUnRDVV3x7sbswEarvxot3YgW79ODhAi5L/83Q2sHpt3Kml 012kpHEZN8Kn36iP816ppi4uRlPHe5j2LVM4Ik6c/hawRiFYuImg8DQ2EJ78UnG1pIqO DCqQ== Received: by 10.204.128.214 with SMTP id l22mr5303445bks.86.1347960575001; Tue, 18 Sep 2012 02:29:35 -0700 (PDT) Received: from ixxyvirt.lan (dslb-088-073-033-117.pools.arcor-ip.net. [88.73.33.117]) by mx.google.com with ESMTPS id g6sm7212223bkg.2.2012.09.18.02.29.33 (version=SSLv3 cipher=OTHER); Tue, 18 Sep 2012 02:29:34 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH] MIPS: hide USE_OF Date: Tue, 18 Sep 2012 11:28:54 +0200 Message-Id: <1347960534-5760-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 34524 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Status: RO X-Status: A Content-Length: 1179 Lines: 42 b01da9f1 ("MIPS: Prune some target specific code out of prom.c") removed the generic implementation of device_tree_init, breaking the kernel build when manually selecting USE_OF. Hide the config symbol so it can't be selected acidentially anymore. Signed-off-by: Jonas Gorski --- There are two alternatives I have thought of: a) Make HAVE_OF depend on an additional config symbol selected by targets supporting OF. and b) create a weak implementation of device_tree_init. Both depend on the assumption that there are/will be targets that support booting with and without OF, but I don't know if anyone really wants that. arch/mips/Kconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 678931c..529fb19 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2408,12 +2408,10 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. config USE_OF - bool "Flattened Device Tree support" + bool select OF select OF_EARLY_FLATTREE select IRQ_DOMAIN - help - Include support for flattened device tree machine descriptions. endmenu -- 1.7.10.4 From jonas.gorski@gmail.com Tue Sep 18 11:32:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Sep 2012 11:32:45 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:45014 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903269Ab2IRJcj (ORCPT ); Tue, 18 Sep 2012 11:32:39 +0200 Received: by bkcji2 with SMTP id ji2so3084709bkc.36 for ; Tue, 18 Sep 2012 02:32:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=xOJ01fU+gbK14LkFXPDF1yr2ooHTvaimcs86LIDLOCU=; b=Ft997d4YXubzpMl6mPyLv5Er0idbAqxWuDjVrgRfXP3x3AD/qUDx+Huub0ACug5RwX sjYNOnxBzhqHQhdzg+JzzwT+phnqSZDCbIXTQy+Y8+WTxYQNbfPL7SAPgaFGp5u8SQ58 4Dy1sXPz4r6QXcHD+SbTD+yRO2vYZhl1WmV0u1BmTO9vY2S1tE3qHm8mNGAQ34ReSHC9 mjJ28IMcuQbo7tHnSuGKsmNznhdIAA6c2LSdv9EZkc3RE1cMCjaSCMelEYEO6UOAm5AZ A7XxhVQRPwQJOlprKN7eJWNFYF0WsZeHA7Te93wnl0XX/rnh5HY6edKCFlDWl2j8ZN9L KUNg== Received: by 10.204.152.146 with SMTP id g18mr1617386bkw.73.1347960754297; Tue, 18 Sep 2012 02:32:34 -0700 (PDT) Received: from ixxyvirt.lan (dslb-088-073-033-117.pools.arcor-ip.net. [88.73.33.117]) by mx.google.com with ESMTPS id a17sm4084298bkw.5.2012.09.18.02.32.32 (version=SSLv3 cipher=OTHER); Tue, 18 Sep 2012 02:32:33 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli Subject: [PATCH] MIPS: BCM63XX: properly handle mac address octet overflow Date: Tue, 18 Sep 2012 11:32:08 +0200 Message-Id: <1347960728-5884-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 34525 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Status: RO Content-Length: 1802 Lines: 65 While calculating the mac address the pointer for the current octet was never reset back to the least significant one after being decremented because of an octet overflow. This resulted in the code continuing to increment at the current octet, potentially generating duplicate or invalid mac addresses. As a second issue the pointer was allowed to advance up to the most significant octet, modifying the OUI, and potentially changing the type of mac address. Rewrite the code so it resets the pointer to the least significant in each outer loop step, and bails out when the least significant octet of the OUI is reached. Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/boards/board_bcm963xx.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index ea4ea77..f0fcec6 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -720,7 +720,7 @@ const char *board_get_name(void) */ static int board_get_mac_address(u8 *mac) { - u8 *p; + u8 *oui; int count; if (mac_addr_used >= nvram.mac_addr_count) { @@ -729,21 +729,23 @@ static int board_get_mac_address(u8 *mac) } memcpy(mac, nvram.mac_addr_base, ETH_ALEN); - p = mac + ETH_ALEN - 1; + oui = mac + ETH_ALEN/2 - 1; count = mac_addr_used; while (count--) { + p = mac + ETH_ALEN - 1; + do { (*p)++; if (*p != 0) break; p--; - } while (p != mac); - } + } while (p != oui); - if (p == mac) { - printk(KERN_ERR PFX "unable to fetch mac address\n"); - return -ENODEV; + if (p == oui) { + printk(KERN_ERR PFX "unable to fetch mac address\n"); + return -ENODEV; + } } mac_addr_used++; -- 1.7.10.4 From sshtylyov@mvista.com Tue Sep 18 13:53:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Sep 2012 13:53:20 +0200 (CEST) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:48191 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903421Ab2IRLxI (ORCPT ); Tue, 18 Sep 2012 13:53:08 +0200 Received: by lagu2 with SMTP id u2so4782094lag.36 for ; Tue, 18 Sep 2012 04:53:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=BwIBRmozRA46Z/CJu0PALTbW0qRyHmO4otM3q4cmvyQ=; b=c36cjZ5/BRICMZYJm9wnYJKMM4feUz8lf3dEFFp/FBevBMveITj+3DHG6m+uGs0Ktc S9TSvLQqezPmnaUc+w/G0Ci1MpGadozPIdt30Yy0u+iHFrKtJY77TEXcaj8rLVTU1YCZ Y91skgvawIzmGIxuUp2R7bbWcyjilPs2fddIPnv7eJ+k6PYK2DTR8ZDAKsfLQJjSAUbV ye0DZCHs2NbNF5TeST1sZxRWzYEKr6H0P22IoJwI2AG+DnxgQVaIc+nLYGTmph4U4O9I dBeh/5AE5/jNF3BnCl12XjoUXMGIUo4hma5tBpecDbX2fDxzsImGuoSYHCBg3kfFdsp9 mM+w== Received: by 10.152.104.77 with SMTP id gc13mr12471677lab.31.1347969182141; Tue, 18 Sep 2012 04:53:02 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-85-75.pppoe.mtu-net.ru. [91.79.85.75]) by mx.google.com with ESMTPS id o7sm3321938lbg.4.2012.09.18.04.52.57 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Sep 2012 04:53:00 -0700 (PDT) Message-ID: <50586059.4090407@mvista.com> Date: Tue, 18 Sep 2012 15:51:53 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:15.0) Gecko/20120907 Thunderbird/15.0.1 MIME-Version: 1.0 To: Jonas Gorski CC: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli Subject: Re: [PATCH] MIPS: BCM63XX: properly handle mac address octet overflow References: <1347960728-5884-1-git-send-email-jonas.gorski@gmail.com> In-Reply-To: <1347960728-5884-1-git-send-email-jonas.gorski@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlYZCdXJiZEKRYkHTUU8drpONkaq1UZXW71a3x2feINBp/7Em4NlrXrfgy5WNnC9scQm75W X-archive-position: 34526 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1660 Lines: 51 Hello. On 18-09-2012 13:32, Jonas Gorski wrote: > While calculating the mac address the pointer for the current octet was > never reset back to the least significant one after being decremented > because of an octet overflow. This resulted in the code continuing to > increment at the current octet, potentially generating duplicate or > invalid mac addresses. > As a second issue the pointer was allowed to advance up to the most > significant octet, modifying the OUI, and potentially changing the type > of mac address. > Rewrite the code so it resets the pointer to the least significant > in each outer loop step, and bails out when the least significant octet > of the OUI is reached. > Signed-off-by: Jonas Gorski > --- > arch/mips/bcm63xx/boards/board_bcm963xx.c | 16 +++++++++------- > 1 file changed, 9 insertions(+), 7 deletions(-) > diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c > index ea4ea77..f0fcec6 100644 > --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c > +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c > @@ -720,7 +720,7 @@ const char *board_get_name(void) > */ > static int board_get_mac_address(u8 *mac) > { > - u8 *p; > + u8 *oui; > int count; > > if (mac_addr_used >= nvram.mac_addr_count) { > @@ -729,21 +729,23 @@ static int board_get_mac_address(u8 *mac) > } > > memcpy(mac, nvram.mac_addr_base, ETH_ALEN); > - p = mac + ETH_ALEN - 1; > + oui = mac + ETH_ALEN/2 - 1; > count = mac_addr_used; > > while (count--) { > + p = mac + ETH_ALEN - 1; But didn't you remove 'p' above? Did you compile this? WBR, Sergei From jonas.gorski@gmail.com Tue Sep 18 13:57:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Sep 2012 13:57:26 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:58859 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903421Ab2IRL5P (ORCPT ); Tue, 18 Sep 2012 13:57:15 +0200 Received: by obbta17 with SMTP id ta17so10782819obb.36 for ; Tue, 18 Sep 2012 04:57:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=0OEpOmu3yaVExx2aeDaMuVbQmZgW01kxQlMbD+o6R+I=; b=DLhT8or5prEJ0TFmLrRE5aZP1YVb+OOuLGHgk5NzvxaVq/zQDN8Nh9sibm6fLzhSHl kiN8sVrKXDN2a85Y3jMFXaxMJsCRTFqJXL/dLwhkycHUo+W7FEwdQi8XC8b0FTeDFSGe ifKLJOK//YnVOh3Nd4uETNWwTAu9yAkZJHRdIwX5Q5NAd3Yx37JT2tfgk2fjd7LRGZes x+tP0/S/K/p+2n7icCDMd/ai7c7DBHzP6NYyAhIDE6Y8on1WvmzgHJZ2J2Mit/vNzpeT hjlSvv8Cqp8g+QIz7GlT50bvzdbDoAimq6nI69M3cCq14TrHbp14t4sc5D8TojGf1cv8 omLg== Received: by 10.182.119.72 with SMTP id ks8mr14894972obb.10.1347969429124; Tue, 18 Sep 2012 04:57:09 -0700 (PDT) MIME-Version: 1.0 Received: by 10.76.3.15 with HTTP; Tue, 18 Sep 2012 04:56:49 -0700 (PDT) In-Reply-To: <50586059.4090407@mvista.com> References: <1347960728-5884-1-git-send-email-jonas.gorski@gmail.com> <50586059.4090407@mvista.com> From: Jonas Gorski Date: Tue, 18 Sep 2012 13:56:49 +0200 Message-ID: Subject: Re: [PATCH] MIPS: BCM63XX: properly handle mac address octet overflow To: Sergei Shtylyov Cc: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli Content-Type: text/plain; charset=UTF-8 X-archive-position: 34527 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1979 Lines: 61 On 18 September 2012 13:51, Sergei Shtylyov wrote: > Hello. > > > On 18-09-2012 13:32, Jonas Gorski wrote: > >> While calculating the mac address the pointer for the current octet was >> never reset back to the least significant one after being decremented >> because of an octet overflow. This resulted in the code continuing to >> increment at the current octet, potentially generating duplicate or >> invalid mac addresses. > > >> As a second issue the pointer was allowed to advance up to the most >> significant octet, modifying the OUI, and potentially changing the type >> of mac address. > > >> Rewrite the code so it resets the pointer to the least significant >> in each outer loop step, and bails out when the least significant octet >> of the OUI is reached. > > >> Signed-off-by: Jonas Gorski >> --- >> arch/mips/bcm63xx/boards/board_bcm963xx.c | 16 +++++++++------- >> 1 file changed, 9 insertions(+), 7 deletions(-) > > >> diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c >> b/arch/mips/bcm63xx/boards/board_bcm963xx.c >> index ea4ea77..f0fcec6 100644 >> --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c >> +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c >> @@ -720,7 +720,7 @@ const char *board_get_name(void) >> */ >> static int board_get_mac_address(u8 *mac) >> { >> - u8 *p; >> + u8 *oui; >> int count; >> >> if (mac_addr_used >= nvram.mac_addr_count) { >> @@ -729,21 +729,23 @@ static int board_get_mac_address(u8 *mac) >> } >> >> memcpy(mac, nvram.mac_addr_base, ETH_ALEN); >> - p = mac + ETH_ALEN - 1; >> + oui = mac + ETH_ALEN/2 - 1; >> count = mac_addr_used; >> >> while (count--) { >> + p = mac + ETH_ALEN - 1; > > > But didn't you remove 'p' above? Did you compile this? Argh. Yes, but the wrong version (my "user space" one to test it). Let me try that again ... . Thanks for catching it. Jonas From jonas.gorski@gmail.com Tue Sep 18 14:09:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Sep 2012 14:09:29 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:42609 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903421Ab2IRMJV (ORCPT ); Tue, 18 Sep 2012 14:09:21 +0200 Received: by bkcji2 with SMTP id ji2so3178708bkc.36 for ; Tue, 18 Sep 2012 05:09:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=EceTQEuvVbbTpm/sLkVxFQtHLPfI5GLD7CtbRzW/7Qw=; b=dFN1r0JV5GUZ2a+E/P6fIbZGmXu29kIPZ9GRrooV1ts6LQ3t4d73709RO0PL439DhT KiWq392fKuwNC3IJOVTkFKwnZk7fPJOW3uI55Z0FyLJW4bfcPnt3LASJ7JdcJAm50dzV ao5rGOORyOWb3fDu6YuIzw+MRB2sfH/nj/mwkAQqu194F9tb1j21iF7cXbSbYwK28mf3 1/EpanIGUdYOPTiyjKI7TWLKnXlcUub/qLkD0ysuVcrX4YUOCBf/HQCTU6fwTqAPOPlo VYgmIGgvocwLC3jDSe8CFohAkEhvtSlPZIFaT0BA95UieIyRIRPlPlY9KovlP8sIqqzw +ITA== Received: by 10.204.152.75 with SMTP id f11mr5791218bkw.83.1347970156505; Tue, 18 Sep 2012 05:09:16 -0700 (PDT) Received: from ixxyvirt.lan (p50811FD1.dip.t-dialin.net. [80.129.31.209]) by mx.google.com with ESMTPS id t23sm7663426bks.4.2012.09.18.05.09.14 (version=SSLv3 cipher=OTHER); Tue, 18 Sep 2012 05:09:15 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Sergei Shtylyov Subject: [PATCH V2] MIPS: BCM63XX: properly handle mac address octet overflow Date: Tue, 18 Sep 2012 14:09:08 +0200 Message-Id: <1347970148-17804-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1347960728-5884-1-git-send-email-jonas.gorski@gmail.com> References: <1347960728-5884-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 34528 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Status: RO X-Status: A Content-Length: 1879 Lines: 68 While calculating the mac address the pointer for the current octet was never reset back to the least significant one after being decremented because of an octet overflow. This resulted in the code continuing to increment at the current octet, potentially generating duplicate or invalid mac addresses. As a second issue the pointer was allowed to advance up to the most significant octet, modifying the OUI, and potentially changing the type of mac address. Rewrite the code so it resets the pointer to the least significant in each outer loop step, and bails out when the least significant octet of the OUI is reached. Signed-off-by: Jonas Gorski --- V1 -> V2: add a missing variable declaration breaking the compilation. arch/mips/bcm63xx/boards/board_bcm963xx.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index ea4ea77..442ba96 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -720,7 +720,7 @@ const char *board_get_name(void) */ static int board_get_mac_address(u8 *mac) { - u8 *p; + u8 *oui; int count; if (mac_addr_used >= nvram.mac_addr_count) { @@ -729,21 +729,23 @@ static int board_get_mac_address(u8 *mac) } memcpy(mac, nvram.mac_addr_base, ETH_ALEN); - p = mac + ETH_ALEN - 1; + oui = mac + ETH_ALEN/2 - 1; count = mac_addr_used; while (count--) { + u8 *p = mac + ETH_ALEN - 1; + do { (*p)++; if (*p != 0) break; p--; - } while (p != mac); - } + } while (p != oui); - if (p == mac) { - printk(KERN_ERR PFX "unable to fetch mac address\n"); - return -ENODEV; + if (p == oui) { + printk(KERN_ERR PFX "unable to fetch mac address\n"); + return -ENODEV; + } } mac_addr_used++; -- 1.7.10.4 From ralf@linux-mips.org Wed Sep 19 15:36:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 19 Sep 2012 15:36:37 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:57188 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903293Ab2ISNgb (ORCPT ); Wed, 19 Sep 2012 15:36:31 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8JDaSCi008559; Wed, 19 Sep 2012 15:36:28 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8JDaRZX008558; Wed, 19 Sep 2012 15:36:27 +0200 Date: Wed, 19 Sep 2012 15:36:27 +0200 From: Ralf Baechle To: Jonas Gorski Cc: linux-mips@linux-mips.org, David Daney Subject: Re: [PATCH] MIPS: hide USE_OF Message-ID: <20120919133627.GG19592@linux-mips.org> References: <1347960534-5760-1-git-send-email-jonas.gorski@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1347960534-5760-1-git-send-email-jonas.gorski@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34529 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 430 Lines: 12 On Tue, Sep 18, 2012 at 11:28:54AM +0200, Jonas Gorski wrote: > b01da9f1 ("MIPS: Prune some target specific code out of prom.c") removed > the generic implementation of device_tree_init, breaking the kernel > build when manually selecting USE_OF. > > Hide the config symbol so it can't be selected acidentially anymore. I'm inclined to accept this patch but would like to wait for a little longer for others' opinions. Ralf From ola.liljedahl@gmail.com Wed Sep 19 16:55:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 19 Sep 2012 16:55:14 +0200 (CEST) Received: from plane.gmane.org ([80.91.229.3]:37709 "EHLO plane.gmane.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903291Ab2ISOzC (ORCPT ); Wed, 19 Sep 2012 16:55:02 +0200 Received: from list by plane.gmane.org with local (Exim 4.69) (envelope-from ) id 1TELg8-0007e7-Gd for linux-mips@linux-mips.org; Wed, 19 Sep 2012 16:55:04 +0200 Received: from sestofw01.enea.se ([192.36.1.252]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 19 Sep 2012 16:55:04 +0200 Received: from ola.liljedahl by sestofw01.enea.se with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 19 Sep 2012 16:55:04 +0200 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Ola Liljedahl Subject: Re: [PATCH 1/1] Pendantic stack backtrace code Date: Wed, 19 Sep 2012 14:52:02 +0000 (UTC) Message-ID: References: <20110706233614.GA19332@dvomlehn-lnx2.corp.sa.net> <20110802155759.GA891@linux-mips.org> <20110805020242.GA23916@dvomlehn-lnx2.corp.sa.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: usenet@ger.gmane.org X-Gmane-NNTP-Posting-Host: sea.gmane.org User-Agent: Loom/3.14 (http://gmane.org/) X-Loom-IP: 192.36.1.252 (Mozilla/5.0 (Windows NT 5.1; rv:15.0) Gecko/20100101 Firefox/15.0) X-archive-position: 34530 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ola.liljedahl@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 821 Lines: 16 I have also written a back-trace utility for MIPS, for Enea's "OSE" realtime OS. Again, it was the sentences in "See MIPS Run" which inspired me (well the whole book is full of inspiration, a great read). My twist to the solution is that my design always scans instructions in the *forward* direction (from the specified PC), trying to find the end of the function. In the process of doing so, unconditional jumps are followed and conditional branches are followed both ways. There is however no support for tracing over signal handlers since in the OSE error handler, we will get the user space register dump for most exceptions and can start back-tracing there. The code is available here: https://dl.dropbox.com/u/45566557/mips_backtrace.c Improvement suggestions and other comments are welcome. -- Ola Liljedahl From bhelgaas@google.com Wed Sep 19 18:57:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 19 Sep 2012 18:57:48 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:35432 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903296Ab2ISQ5l (ORCPT ); Wed, 19 Sep 2012 18:57:41 +0200 Received: by lbbgf7 with SMTP id gf7so1202826lbb.36 for ; Wed, 19 Sep 2012 09:57:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-system-of-record; bh=NcZkJLhJEkiZyo9XfUYupBdttT84j2In1pupDVmRMdw=; b=TJxBD1qLVax9WdsnmW86fjX0IGjGyeexW5CsJ/MCwAadbHkfkTvcHO+Vho00nue8nU 6h+5Z+XNGVqE75Lbc5pZLWxX0LdH/taziXW5WTragdMqDU55KA6coULtO+nhfL674M8u 2iS+p6nNx+vQ25senO33DlUi/smWJxri5hpvgguesXb9ZaBgpeMNd1FItrNDl3ZdyrlZ ZlqZfwpq9IB1pyGgQuZ8G4+xXEdHyV/h0WuhRA6W2mqgXLcTGpUGXlegbahO30G/0T+M 4ZGJ6Uh4qb8RAWX6mHu8vH8WnmFK0lSwj1H9RsPYRnlfDUztCXVTjnqtQKSjtV6Cu45J Mh3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-system-of-record:x-gm-message-state; bh=NcZkJLhJEkiZyo9XfUYupBdttT84j2In1pupDVmRMdw=; b=UAELFLgC/K8dz+trKL6v8A/GF+tR8T6t9N4fysJPcaWDs7h+c3tOYoexUkskXk+ALo 5CHAYu85z3xvsvbg9AbcrAOV4OdHqCiy5Pto1HJOI+NrpQaIN36cOj+fKzF5LHQCwRC+ tKjJUc/bb7tbHBRAsB1+RrJDktW150iFUmJg2xPVYi2xfaZUr4VsuSuj45QIsjGqzfAY WaHbhdPj7K2KG2PAAOcQ1t4YxhEPWCodfJ5d8BSD7YqZNgD7hxiKdhpMMWltBz2bHRef NP+3ZXX7SqD/YeNcE+0/r9B5qOSfFNyQyBTfKd52MkYurZ3m7kRZH+5rrrhRzCVsSZRq SoeA== Received: by 10.112.85.226 with SMTP id k2mr28081lbz.70.1348073855434; Wed, 19 Sep 2012 09:57:35 -0700 (PDT) Received: by 10.112.85.226 with SMTP id k2mr28022lbz.70.1348073855220; Wed, 19 Sep 2012 09:57:35 -0700 (PDT) MIME-Version: 1.0 Received: by 10.112.132.73 with HTTP; Wed, 19 Sep 2012 09:57:15 -0700 (PDT) In-Reply-To: <20120917113423.GA28759@kroah.com> References: <1347880974-13615-1-git-send-email-thierry.reding@avionic-design.de> <20120917113423.GA28759@kroah.com> From: Bjorn Helgaas Date: Wed, 19 Sep 2012 10:57:15 -0600 Message-ID: Subject: Re: [PATCH v2 1/2] PCI: Keep pci_fixup_irqs() around after init To: Greg Kroah-Hartman Cc: Thierry Reding , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-System-Of-Record: true X-Gm-Message-State: ALoCoQl/rysIUhuLKeNJyXCPb2iaGf1ItXAGLI5Q9XItqaoNRDOJkK0tDQiU1B6NaUwFID1BTdIT0jkQ7cpZc2cm5HtAq2D8JB2S8PtCj1/Us9CZwUeqYRWxz4hH9B4/j3FvNUsFDnMz4s5ejiE7cxRA9+iBZwvQ6yX06qy9slGay2GdIKlxUthM6nLCkI0Lv3XxV3oaiXnjEDdWKeg37kkwz4yBwkw9Hg== X-archive-position: 34531 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 775 Lines: 19 On Mon, Sep 17, 2012 at 5:34 AM, Greg Kroah-Hartman wrote: > On Mon, Sep 17, 2012 at 01:22:53PM +0200, Thierry Reding wrote: >> Remove the __init annotations in order to keep pci_fixup_irqs() around >> after init (e.g. for hotplug). This requires the same change for the >> implementation of pcibios_update_irq() on all architectures. While at >> it, all __devinit annotations are removed as well, since they will be >> useless now that HOTPLUG is always on. >> >> Signed-off-by: Thierry Reding >> --- >> Changes in v2: >> - remove __init and __devinit annotations altogether > > Acked-by: Greg Kroah-Hartman I applied these (both 1/2 and 2/2) to my "next" branch. Thanks! Bjorn From sfr@canb.auug.org.au Thu Sep 20 00:38:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 20 Sep 2012 00:38:22 +0200 (CEST) Received: from haggis.pcug.org.au ([203.10.76.10]:58298 "EHLO members.tip.net.au" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903294Ab2ISWiO (ORCPT ); Thu, 20 Sep 2012 00:38:14 +0200 Received: from canb.auug.org.au (unknown [IPv6:2402:b800:7003:7010:223:14ff:fe30:c8e4]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by members.tip.net.au (Postfix) with ESMTPSA id 4E50316411E; Thu, 20 Sep 2012 08:37:47 +1000 (EST) Date: Thu, 20 Sep 2012 08:37:31 +1000 From: Stephen Rothwell To: Thierry Reding Cc: Bjorn Helgaas , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , Greg Kroah-Hartman , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v2 2/2] PCI: Provide a default pcibios_update_irq() Message-Id: <20120920083731.b99255eb8fdeea908d34ed2f@canb.auug.org.au> In-Reply-To: <1347880974-13615-2-git-send-email-thierry.reding@avionic-design.de> References: <1347880974-13615-1-git-send-email-thierry.reding@avionic-design.de> <1347880974-13615-2-git-send-email-thierry.reding@avionic-design.de> X-Mailer: Sylpheed 3.2.0 (GTK+ 2.24.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg="PGP-SHA256"; boundary="Signature=_Thu__20_Sep_2012_08_37_31_+1000_w3NxfdoHc7EAjbxm" X-archive-position: 34532 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sfr@canb.auug.org.au Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2054 Lines: 58 --Signature=_Thu__20_Sep_2012_08_37_31_+1000_w3NxfdoHc7EAjbxm Content-Type: text/plain; charset=US-ASCII Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Mon, 17 Sep 2012 13:22:54 +0200 Thierry Reding wrote: > > diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c > index 270ae7b..3d61ce3 100644 > --- a/drivers/pci/setup-irq.c > +++ b/drivers/pci/setup-irq.c > @@ -17,6 +17,11 @@ > #include > #include > =20 > +void __weak pcibios_update_irq(struct pci_dev *dev, int irq) > +{ > + dev_dbg(&dev->dev, "Assigning IRQ %02d\n", irq); > + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); > +} > =20 > static void > pdev_fixup_irq(struct pci_dev *dev, Didn't we have a problem with some compiler versions when the weak definition was in the same file as the call (there is a call to this function in drivers/pci/setup-irq.c)? --=20 Cheers, Stephen Rothwell sfr@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ --Signature=_Thu__20_Sep_2012_08_37_31_+1000_w3NxfdoHc7EAjbxm Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBCAAGBQJQWkkrAAoJEECxmPOUX5FEW9wP/RZUlNoHKF/hdMIqgBXmqu9j ziwT/7xAnOx2PyPXzlr360bi/PMcjIv3oqf4DHv1tBxYe7tzxS9j1M2Moq8UHiWW 1wOj+EXsgex73bIKtudojQojTpY9lZML9cdD5ki6zxvIEZTynAH4dSdomk2knPxw er3HuNnawQIA4iad+FF4IFp9ojKsduCCRHEGzgC0sfLm1zT/pKgT/jQjZYjdWtKy cTujkETaHoMG6rZdnUwmmZryGHWtPUAlWVyg9BDebJfIL32zzU66lQlpIFREyTnI zmOrfeJ4Ypw/B0NRUvEMQbUZJtRk7L/ovddItq9NNWHgYn5pznuJOlTaPQb9owOd i4oOZguBUyIQL92SrzMMXjxkx5RaBf8dtgGwvdvvCGv5F48Cnr3eCbQN5YQL08xQ fek/sjc5izX0MbNjKYw4twCrOwYVpd6Hj7W8L0lhZ0NgFZIoXQi8zTmEjDtf5cHw heVKZnH2zdtboYaiIB6utdl1/20mrq6YUd4yuQxwGpc9LveCkPxpPZ1fwTYJj6Fq sjabH0KJVKmHTKr3LJg6xFKNh98p+Z3PlVAz4Ac6JTfCWLroBb9df9XAbHZ5kUZd Q8RvTloTEYY6hiYKVUn7QF6iO7fUxYuY8/7s8HBhGEyJrwCrVJTpFCOgm7ySBwO5 fqCAlk6bhtq1THZ3WZZh =VZA6 -----END PGP SIGNATURE----- --Signature=_Thu__20_Sep_2012_08_37_31_+1000_w3NxfdoHc7EAjbxm-- From bhelgaas@google.com Fri Sep 21 05:19:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 21 Sep 2012 05:20:01 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:47439 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903318Ab2IUDT5 (ORCPT ); Fri, 21 Sep 2012 05:19:57 +0200 Received: by lbbgf7 with SMTP id gf7so3253981lbb.36 for ; Thu, 20 Sep 2012 20:19:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-system-of-record; bh=Rtw/GkRDlF7fki5PjlDcM6jPF9f0BbRmFMmdNfrs20k=; b=RMOxlJ35LjtETIc2eAIf5cUH41K9yX+YZWyguFHI+Ja1FHr63nesPrT0pUhXqqXBX7 8TV0rMd5R9NA3LsMsmqmjviuadijPg3BJI3n8R5dRJSb8w8dBKAczghZTs+XgkB2Oqnb bAveLvYXu/oYwJi7fa+TMx20Gk+iuv3JpVOQkaX2T8atBH37OwKyl3K8WzOmmMX+Kfw0 E92hJgn5jLAd0Q3JnsnXo68W791Husi1OvnenBKacuw8vgivfOSuUEPtoJeFdl++z7LV 7huHBKlURmJGBjIqL1cU6SMpD3gC+nyGVw7TdTeWKbAx72ivHB1g2WX99YwcBFXfuikJ w8cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-system-of-record:x-gm-message-state; bh=Rtw/GkRDlF7fki5PjlDcM6jPF9f0BbRmFMmdNfrs20k=; b=YHHGfuUwSedGa2XomtzBGx2SvLDOZ6QVXIRYfMnzPrwJ9AS8CT4CNTVMKuCDUwc5+X Q67leLgllZu3orBjS8x4ctUHmEq3GHSmJHq7vSnu3tk/vJHaMuSgn5uKCZOA2refevfq 8Ay7kkso4X/3xkFNj1whrfRYfa65uGtApHF4in0JrjSRU4jONyaYgkslWhm4hgHTuaHe Zh+y+LIV+qKwJ+82AElJjWSkJxaSKVTIhh3HOvVDgbTqEU1Hjyuc6bh8OGaCr/qiqB4v mLoSn+E+BZA0fZpF3QL/UZGX2TZm2s4MmNmerc/a1KthVZHvh79vgkeOVYfmCvH7oHvg sq2g== Received: by 10.152.114.3 with SMTP id jc3mr3154370lab.11.1348197590589; Thu, 20 Sep 2012 20:19:50 -0700 (PDT) Received: by 10.152.114.3 with SMTP id jc3mr3154333lab.11.1348197590451; Thu, 20 Sep 2012 20:19:50 -0700 (PDT) MIME-Version: 1.0 Received: by 10.112.132.73 with HTTP; Thu, 20 Sep 2012 20:19:30 -0700 (PDT) In-Reply-To: <20120920083731.b99255eb8fdeea908d34ed2f@canb.auug.org.au> References: <1347880974-13615-1-git-send-email-thierry.reding@avionic-design.de> <1347880974-13615-2-git-send-email-thierry.reding@avionic-design.de> <20120920083731.b99255eb8fdeea908d34ed2f@canb.auug.org.au> From: Bjorn Helgaas Date: Thu, 20 Sep 2012 21:19:30 -0600 Message-ID: Subject: Re: [PATCH v2 2/2] PCI: Provide a default pcibios_update_irq() To: Stephen Rothwell Cc: Thierry Reding , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , Greg Kroah-Hartman , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-System-Of-Record: true X-Gm-Message-State: ALoCoQl3qJUaL4zconefUv2Av5jGDQmdUb53MkboklHy99Sey/WSO+uWpc+RoIKEbNqLJ1AGHpBPDIW1zuPMIXK9pduEqVmEOHXcyNIckwGwYdvBnTh2R+agtpjX2TfrPWyEJQJJPJZEcp9NkLF/F+Lzg1EMKxRlCGs+lGw0nFIDbMWtyrMQjRLT1xvLRIyBLcCQU8xRvrYCh8nuGVPG/njhIBmoq+rKIg== X-archive-position: 34533 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 987 Lines: 28 On Wed, Sep 19, 2012 at 4:37 PM, Stephen Rothwell wrote: > Hi, > > On Mon, 17 Sep 2012 13:22:54 +0200 Thierry Reding wrote: >> >> diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c >> index 270ae7b..3d61ce3 100644 >> --- a/drivers/pci/setup-irq.c >> +++ b/drivers/pci/setup-irq.c >> @@ -17,6 +17,11 @@ >> #include >> #include >> >> +void __weak pcibios_update_irq(struct pci_dev *dev, int irq) >> +{ >> + dev_dbg(&dev->dev, "Assigning IRQ %02d\n", irq); >> + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); >> +} >> >> static void >> pdev_fixup_irq(struct pci_dev *dev, > > Didn't we have a problem with some compiler versions when the weak > definition was in the same file as the call (there is a call to this > function in drivers/pci/setup-irq.c)? There was such a bug, but as far as I know, we aren't worrying about it anymore: https://lkml.org/lkml/2011/7/4/9 From sfr@canb.auug.org.au Fri Sep 21 05:31:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 21 Sep 2012 05:31:34 +0200 (CEST) Received: from haggis.pcug.org.au ([203.10.76.10]:37476 "EHLO members.tip.net.au" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903318Ab2IUDb1 (ORCPT ); Fri, 21 Sep 2012 05:31:27 +0200 Received: from canb.auug.org.au (ibmaus65.lnk.telstra.net [165.228.126.9]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by members.tip.net.au (Postfix) with ESMTPSA id 23AA01640F3; Fri, 21 Sep 2012 13:30:57 +1000 (EST) Date: Fri, 21 Sep 2012 13:30:53 +1000 From: Stephen Rothwell To: Bjorn Helgaas Cc: Thierry Reding , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , "David S. Miller" , Chris Metcalf , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Chris Zankel , Greg Ungerer , Greg Kroah-Hartman , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v2 2/2] PCI: Provide a default pcibios_update_irq() Message-Id: <20120921133053.7d92b41c54d3400e952ee8ff@canb.auug.org.au> In-Reply-To: References: <1347880974-13615-1-git-send-email-thierry.reding@avionic-design.de> <1347880974-13615-2-git-send-email-thierry.reding@avionic-design.de> <20120920083731.b99255eb8fdeea908d34ed2f@canb.auug.org.au> X-Mailer: Sylpheed 3.2.0 (GTK+ 2.24.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg="PGP-SHA256"; boundary="Signature=_Fri__21_Sep_2012_13_30_53_+1000_6fJdZvf2GVz=KRck" X-archive-position: 34534 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sfr@canb.auug.org.au Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1757 Lines: 47 --Signature=_Fri__21_Sep_2012_13_30_53_+1000_6fJdZvf2GVz=KRck Content-Type: text/plain; charset=US-ASCII Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Bjorn, On Thu, 20 Sep 2012 21:19:30 -0600 Bjorn Helgaas wrot= e: > > On Wed, Sep 19, 2012 at 4:37 PM, Stephen Rothwell = wrote: > > > > Didn't we have a problem with some compiler versions when the weak > > definition was in the same file as the call (there is a call to this > > function in drivers/pci/setup-irq.c)? >=20 > There was such a bug, but as far as I know, we aren't worrying about > it anymore: https://lkml.org/lkml/2011/7/4/9 OK, thanks. --=20 Cheers, Stephen Rothwell sfr@canb.auug.org.au --Signature=_Fri__21_Sep_2012_13_30_53_+1000_6fJdZvf2GVz=KRck Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBCAAGBQJQW99tAAoJEECxmPOUX5FEL/YP+wX8jDRVY59Nu8INBHtW97vi Id5MzR7NZqIMFLsX4TTasMY3zXmh7QthaRgHeLCRpeApLuai3q7jPO9mh1N5Liij ipemFO+d4Z+SODfvdaWFxzAdvb3OHBZ2Bj2fUX9reeJoqLx6rRNkhOIXapx8gjFT G6Zpv5G6UC6oCJwQwO+v1zIuPA5Z6MN3PRhShM6bTvRguXeih+Ur+67XRtDDKORi KngGhWpc0ieTooaQEfdlJ5eztlk8qphp3lM6ehdXTPzdl9azRM0oj5Lvn7T9pauj 2zNJ5JEZj1hFHQPfjxurrx1h6b+duoZ9E3IN2mHM+DpOHltfxSnar8Pv0nJsq9yS sqrxuIomZggUNi68h+bebrd+76Na6u9FAq0DOnZas+kxWYDmw6Pf+DjAOylBLEyr qitrPDoJONCJzjFbklyvdIhvoHmp0HLssku9uuocz6AWJ4oXwTiOLGC1RfYLJmpA qtKjPRUkvSMGGXh7wbSJu1B9/Z0e7hdKspggv5nzYnkJB0lDYaQcl5/0f5S6Yy34 clbH1xdUT2YnW6T8wfNUAvMf3bexzVCy6IGxU9gidfYcQMcbv+Fzpp1HNtsnQX+R W9otg+HJxouJ69+UpBMUWeS6pc0voZdT/GDEpxbN3u9P8e8Y46OJZfEwOGIgrjUP flkeljYJMKmwjZ/bAfRA =292X -----END PGP SIGNATURE----- --Signature=_Fri__21_Sep_2012_13_30_53_+1000_6fJdZvf2GVz=KRck-- From thierry.reding@avionic-design.de Sat Sep 22 09:41:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 22 Sep 2012 09:42:03 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.10]:61839 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903341Ab2IVHl6 (ORCPT ); Sat, 22 Sep 2012 09:41:58 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu1) with ESMTP (Nemesis) id 0Mg2HB-1SruCf3v6L-00NOet; Sat, 22 Sep 2012 09:41:49 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 51B4D2A282EB; Sat, 22 Sep 2012 09:41:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q5hKc3KW-Nux; Sat, 22 Sep 2012 09:41:46 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 51D272A2819B; Sat, 22 Sep 2012 09:41:46 +0200 (CEST) Date: Sat, 22 Sep 2012 09:41:45 +0200 From: Thierry Reding To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: Re: [PATCH v2 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Message-ID: <20120922074144.GC2538@avionic-0098.mockup.avionic-design.de> References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="QRj9sO5tAVLaXnSD" Content-Disposition: inline In-Reply-To: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:HKIQIIVHcPi0JX5bfrEeMQ+21+7wk9Pn68zVzqA42LU +9T+tYBrj3lZi/Wdw5v8OTh1L+6XGVTySSWoHVpDB40sZYR3hz f2TCYCZ+UDNIbFNLSMOOblrPBxdeySH3QfGkZ8hySlll97mWiX /LYLz1cQoyAQHPP/V2zZfhG1dQNZ62Tos/KENkcT04I42ALzTx td1RCeOB7RCEGb965CO72honskelPzj2ns/bfKvz1N5W4l8hfU sUJSkkoZynSSqlELo8GWFCwAWlmtS9oDcSJA7D7eokIfm7rChp jSH4WrJyneTxeyKDdOMPfjYD0SNnTdMEK8oKRxtpUkymkGqnE+ sWBJJRjYzM1lZ1EYZ8oaGepmZ4odrrhtFOtbYhcurqG48ZdVQb MjEUydxmBV3AJ0lBtb9xqTf7EmGrmBivq0= X-archive-position: 34535 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 3707 Lines: 88 --QRj9sO5tAVLaXnSD Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Sep 10, 2012 at 02:05:16PM +0200, Thierry Reding wrote: > Hi, >=20 > This small series fixes a build error due to a circular header > dependency, exports the timer API so it can be used outside of > the arch/mips/jz4740 tree and finally moves and converts the > JZ4740 PWM driver to the PWM framework. >=20 > Note that I don't have any hardware to test this on, so I had to > rely on compile tests only. Patches 1 and 2 should probably go > through the MIPS tree, while I can take patch 3 through the PWM > tree. It touches a couple of files in arch/mips but the changes > are unlikely to cause conflicts. >=20 > Thierry >=20 > Thierry Reding (3): > MIPS: JZ4740: Break circular header dependency > MIPS: JZ4740: Export timer API > pwm: Add Ingenic JZ4740 support >=20 > arch/mips/include/asm/mach-jz4740/irq.h | 5 + > arch/mips/include/asm/mach-jz4740/platform.h | 1 + > arch/mips/include/asm/mach-jz4740/timer.h | 113 ++++++++++++++ > arch/mips/jz4740/Kconfig | 3 - > arch/mips/jz4740/Makefile | 2 +- > arch/mips/jz4740/board-qi_lb60.c | 1 + > arch/mips/jz4740/irq.h | 23 --- > arch/mips/jz4740/platform.c | 6 + > arch/mips/jz4740/pwm.c | 177 --------------------- > arch/mips/jz4740/time.c | 2 +- > arch/mips/jz4740/timer.c | 4 +- > arch/mips/jz4740/timer.h | 136 ----------------- > drivers/pwm/Kconfig | 12 +- > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-jz4740.c | 221 +++++++++++++++++++++= ++++++ > 15 files changed, 363 insertions(+), 344 deletions(-) > delete mode 100644 arch/mips/jz4740/irq.h > delete mode 100644 arch/mips/jz4740/pwm.c > delete mode 100644 arch/mips/jz4740/timer.h > create mode 100644 drivers/pwm/pwm-jz4740.c Hi Ralf, Have you had a chance to look at this? It is the last remaining PWM driver that isn't moved to the PWM framework yet. All the others are either in linux-next already and queued for 3.7 or have recently got Acked-by the respective maintainers (Unicore32). Patches 2 and 3 were already acked and tested by Lars-Peter who did the initial porting. Patch 1 can probably be dropped since I seem to be the only one running into that issue. I really want to take this in for 3.7 so I can use the 3.7 cycle to transition from the legacy API to the new API and possibly even get rid of the legacy parts altogether. However I don't want to do this without the Acked-by from the MIPS maintainer. Thierry --QRj9sO5tAVLaXnSD Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQXWu4AAoJEN0jrNd/PrOhLDIP/iv28ONKXxxVsKa4449otNeV u28SXWhBbmqtIonkcLCiuiWV2/WbmQeZ6QvvhKKmXDIVdLtNGnBQXnoLJyjokIjf 1Bq4mkFsJ021ltuHqfd8qyt80UMu2kYaxwXxPN+/H40vqeIb9UfQaE7XtV7y9/ho C7Jy4erKpLMpS5oWBZ151q8GpojczA0MC+OsTg0KlrphF3cSZOBeHouQwZ9anaOt aHttqo8zFQq5brXwVLdhhPOlJY3AOb3vEG3P9TUfXY/6uDQVnPKDs0Wpg/UDwS1X z/4U35MOQijMi22C0ajXs50jgfHqwV16Br/JQW+MckBxyeAxaOu1VHfZ+2bjzAYJ AJTdbWDmSzwSnamwUpf8UgR9v8IXDEuk8WcRsrNRAosy2F2EKO6JRhVtRqdS2nUo X1d4vSuxCPyyQQpDIN8tQK4rKsTsFwED6/RDFJHY2FCrpjtPvbGXYMxsL5Urwee+ /KKVIo4cBAHm/zrWra7Dhg06x45JuEquPOjbS+H+bpLdyeGtw+SL7t4UCWFNZ5fK Z5H37MtO8Rk38kcZls+ltbEsVpVZxV7cr7YS6Uw/8aDLpHx1M9DiFowaVspWU2vb hKk0dSL6zKqLAXFAb4ykPLOprEbUthjen2/5NrAu0hQyE+/xTEtQKW0a7ACR6vvW 4LPRc7GPkewsiujUXJtp =PsHc -----END PGP SIGNATURE----- --QRj9sO5tAVLaXnSD-- From ralf@linux-mips.org Sun Sep 23 15:56:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 23 Sep 2012 15:56:49 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:42599 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903360Ab2IWN4o (ORCPT ); Sun, 23 Sep 2012 15:56:44 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8NDufa6021491; Sun, 23 Sep 2012 15:56:41 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8NDuZP1021490; Sun, 23 Sep 2012 15:56:35 +0200 Date: Sun, 23 Sep 2012 15:56:35 +0200 From: Ralf Baechle To: Thierry Reding , Michal Marek , linux-kbuild@vger.kernel.org Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: Re: [PATCH v2 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Message-ID: <20120923135635.GB13842@linux-mips.org> References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> <20120922074144.GC2538@avionic-0098.mockup.avionic-design.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20120922074144.GC2538@avionic-0098.mockup.avionic-design.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34536 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5424 Lines: 74 On Sat, Sep 22, 2012 at 09:41:45AM +0200, Thierry Reding wrote: > Have you had a chance to look at this? It is the last remaining PWM > driver that isn't moved to the PWM framework yet. All the others are > either in linux-next already and queued for 3.7 or have recently got > Acked-by the respective maintainers (Unicore32). Patches 2 and 3 were > already acked and tested by Lars-Peter who did the initial porting. > Patch 1 can probably be dropped since I seem to be the only one running > into that issue. > > I really want to take this in for 3.7 so I can use the 3.7 cycle to > transition from the legacy API to the new API and possibly even get rid > of the legacy parts altogether. However I don't want to do this without > the Acked-by from the MIPS maintainer. Acked-by: Ralf Baechle for 2/3 and 3/3. I now can reproduce the build error that 1/3 is supposed to fix. The issue is not as first suspected an odd bug in just your compiler. The tree (I was testing on today's -next) is building fine when compiling in-tree but fails out of tree: CC arch/mips/jz4740/irq.o In file included from /home/ralf/src/linux/linux-jz4740/arch/mips/include/asm/irq.h:18:0, from /home/ralf/src/linux/linux-jz4740/include/linux/irq.h:27, from /home/ralf/src/linux/linux-jz4740/include/asm-generic/hardirq.h:12, from /home/ralf/src/linux/linux-jz4740/arch/mips/include/asm/hardirq.h:16, from /home/ralf/src/linux/linux-jz4740/include/linux/hardirq.h:7, from /home/ralf/src/linux/linux-jz4740/include/linux/interrupt.h:12, from /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:19: /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:20:39: error: ‘struct irq_data’ declared inside parameter list [-Werror] /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:20:39: error: its scope is only this definition or declaration, which is probably not what you want [-Werror] /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:21:38: error: ‘struct irq_data’ declared inside parameter list [-Werror] In file included from /home/ralf/src/linux/linux-jz4740/include/linux/irq.h:356:0, from /home/ralf/src/linux/linux-jz4740/include/asm-generic/hardirq.h:12, from /home/ralf/src/linux/linux-jz4740/arch/mips/include/asm/hardirq.h:16, from /home/ralf/src/linux/linux-jz4740/include/linux/hardirq.h:7, from /home/ralf/src/linux/linux-jz4740/include/linux/interrupt.h:12, from /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:19: /home/ralf/src/linux/linux-jz4740/include/linux/irqdesc.h:73:33: error: ‘NR_IRQS’ undeclared here (not in a function) /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c: In function ‘jz4740_cascade’: /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:49:39: error: ‘JZ4740_IRQ_BASE’ undeclared (first use in this function) /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:49:39: note: each undeclared identifier is reported only once for each function it appears in /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c: At top level: /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:62:6: error: conflicting types for ‘jz4740_irq_suspend’ In file included from /home/ralf/src/linux/linux-jz4740/arch/mips/include/asm/irq.h:18:0, from /home/ralf/src/linux/linux-jz4740/include/linux/irq.h:27, from /home/ralf/src/linux/linux-jz4740/include/asm-generic/hardirq.h:12, from /home/ralf/src/linux/linux-jz4740/arch/mips/include/asm/hardirq.h:16, from /home/ralf/src/linux/linux-jz4740/include/linux/hardirq.h:7, from /home/ralf/src/linux/linux-jz4740/include/linux/interrupt.h:12, from /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:19: /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:20:13: note: previous declaration of ‘jz4740_irq_suspend’ was here /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:68:6: error: conflicting types for ‘jz4740_irq_resume’ In file included from /home/ralf/src/linux/linux-jz4740/arch/mips/include/asm/irq.h:18:0, from /home/ralf/src/linux/linux-jz4740/include/linux/irq.h:27, from /home/ralf/src/linux/linux-jz4740/include/asm-generic/hardirq.h:12, from /home/ralf/src/linux/linux-jz4740/arch/mips/include/asm/hardirq.h:16, from /home/ralf/src/linux/linux-jz4740/include/linux/hardirq.h:7, from /home/ralf/src/linux/linux-jz4740/include/linux/interrupt.h:12, from /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:19: /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:21:13: note: previous declaration of ‘jz4740_irq_resume’ was here /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c: In function ‘arch_init_irq’: /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:91:41: error: ‘JZ4740_IRQ_BASE’ undeclared (first use in this function) Which (while your patch is probably fine, I haven't tested) this seems to be a build system issue, so should be preferably be fixed there. Marek, the whole email exchange is archived at http://www.linux-mips.org/archives/linux-mips/2012-09/threads.html Ralf From thierry.reding@avionic-design.de Sun Sep 23 19:12:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 23 Sep 2012 19:12:58 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.9]:51333 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903359Ab2IWRMv (ORCPT ); Sun, 23 Sep 2012 19:12:51 +0200 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu3) with ESMTP (Nemesis) id 0Lv4go-1TfmeD3hHm-00zh2Y; Sun, 23 Sep 2012 19:12:40 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 3F5332A28305; Sun, 23 Sep 2012 19:12:39 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id C7jiKGJnV+qy; Sun, 23 Sep 2012 19:12:37 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 558CC2A2829D; Sun, 23 Sep 2012 19:12:37 +0200 (CEST) Date: Sun, 23 Sep 2012 19:12:36 +0200 From: Thierry Reding To: Ralf Baechle Cc: Michal Marek , linux-kbuild@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Antony Pavlov , Lars-Peter Clausen , Maarten ter Huurne Subject: Re: [PATCH v2 0/3] MIPS: JZ4740: Move PWM driver to PWM framework Message-ID: <20120923171236.GA1219@avionic-0098.mockup.avionic-design.de> References: <1347278719-15276-1-git-send-email-thierry.reding@avionic-design.de> <20120922074144.GC2538@avionic-0098.mockup.avionic-design.de> <20120923135635.GB13842@linux-mips.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="BOKacYhQ+x31HxR3" Content-Disposition: inline In-Reply-To: <20120923135635.GB13842@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-Provags-ID: V02:K0:42eL0QZmasXQEOhS5q0hpnw0br6uR+qnrEBPslPeZ7w 8OZ6xSzhXOzNo+pEbTs7ivT0iwqdzxsTD1TJknfeHNI0A0bXaH KWuxMTGELzZREWlIqnIx2gwB8+Ll9QUfxvuSI6hS8N+0dh/a2t RDkQpJviOCn+1OuHeNWrTL4ebCrkYKngcWYlX/m4ZEvKTQ8n/0 XLDHjzQ9xmWNYNvLTgV9AFoZE2p+K5hlyVKFV0CSlfiUH0ldtR zYcV2ib1tf9eNDEyhrryikMwPO0WUBSveij/cNipxYwT3Jf0PJ 069ViGH6OXZmd7GrRplxwydE+RX2BjJsb1Lm0nABKKZABEIq1z vKftzDZ85dZyIGTn78WpjwejTt3y7arQmzk9gQ29xzO18jlSsT 7LggpzAbXOU0MMlrZj9s5byZbCmJAd84sI= X-archive-position: 34537 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@avionic-design.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7191 Lines: 155 --BOKacYhQ+x31HxR3 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Sep 23, 2012 at 03:56:35PM +0200, Ralf Baechle wrote: > On Sat, Sep 22, 2012 at 09:41:45AM +0200, Thierry Reding wrote: >=20 > > Have you had a chance to look at this? It is the last remaining PWM > > driver that isn't moved to the PWM framework yet. All the others are > > either in linux-next already and queued for 3.7 or have recently got > > Acked-by the respective maintainers (Unicore32). Patches 2 and 3 were > > already acked and tested by Lars-Peter who did the initial porting. > > Patch 1 can probably be dropped since I seem to be the only one running > > into that issue. > >=20 > > I really want to take this in for 3.7 so I can use the 3.7 cycle to > > transition from the legacy API to the new API and possibly even get rid > > of the legacy parts altogether. However I don't want to do this without > > the Acked-by from the MIPS maintainer. >=20 > Acked-by: Ralf Baechle >=20 > for 2/3 and 3/3. Alright, thanks. I'll take those through the PWM tree. > I now can reproduce the build error that 1/3 is supposed to fix. The iss= ue > is not as first suspected an odd bug in just your compiler. The tree > (I was testing on today's -next) is building fine when compiling in-tree > but fails out of tree: Okay, that makes sense. I rarely if even build in-tree nowadays. > CC arch/mips/jz4740/irq.o > In file included from /home/ralf/src/linux/linux-jz4740/arch/mips/include= /asm/irq.h:18:0, > from /home/ralf/src/linux/linux-jz4740/include/linux/irq= =2Eh:27, > from /home/ralf/src/linux/linux-jz4740/include/asm-gener= ic/hardirq.h:12, > from /home/ralf/src/linux/linux-jz4740/arch/mips/include= /asm/hardirq.h:16, > from /home/ralf/src/linux/linux-jz4740/include/linux/har= dirq.h:7, > from /home/ralf/src/linux/linux-jz4740/include/linux/int= errupt.h:12, > from /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/= irq.c:19: > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:20:39: error: = =E2=80=98struct irq_data=E2=80=99 declared inside parameter list [-Werror] > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:20:39: error: it= s scope is only this definition or declaration, which is probably not what = you want [-Werror] > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:21:38: error: = =E2=80=98struct irq_data=E2=80=99 declared inside parameter list [-Werror] > In file included from /home/ralf/src/linux/linux-jz4740/include/linux/irq= =2Eh:356:0, > from /home/ralf/src/linux/linux-jz4740/include/asm-gener= ic/hardirq.h:12, > from /home/ralf/src/linux/linux-jz4740/arch/mips/include= /asm/hardirq.h:16, > from /home/ralf/src/linux/linux-jz4740/include/linux/har= dirq.h:7, > from /home/ralf/src/linux/linux-jz4740/include/linux/int= errupt.h:12, > from /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/= irq.c:19: > /home/ralf/src/linux/linux-jz4740/include/linux/irqdesc.h:73:33: error: = =E2=80=98NR_IRQS=E2=80=99 undeclared here (not in a function) > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c: In function =E2= =80=98jz4740_cascade=E2=80=99: > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:49:39: error: = =E2=80=98JZ4740_IRQ_BASE=E2=80=99 undeclared (first use in this function) > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:49:39: note: eac= h undeclared identifier is reported only once for each function it appears = in > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c: At top level: > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:62:6: error: con= flicting types for =E2=80=98jz4740_irq_suspend=E2=80=99 > In file included from /home/ralf/src/linux/linux-jz4740/arch/mips/include= /asm/irq.h:18:0, > from /home/ralf/src/linux/linux-jz4740/include/linux/irq= =2Eh:27, > from /home/ralf/src/linux/linux-jz4740/include/asm-gener= ic/hardirq.h:12, > from /home/ralf/src/linux/linux-jz4740/arch/mips/include= /asm/hardirq.h:16, > from /home/ralf/src/linux/linux-jz4740/include/linux/har= dirq.h:7, > from /home/ralf/src/linux/linux-jz4740/include/linux/int= errupt.h:12, > from /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/= irq.c:19: > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:20:13: note: pre= vious declaration of =E2=80=98jz4740_irq_suspend=E2=80=99 was here > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:68:6: error: con= flicting types for =E2=80=98jz4740_irq_resume=E2=80=99 > In file included from /home/ralf/src/linux/linux-jz4740/arch/mips/include= /asm/irq.h:18:0, > from /home/ralf/src/linux/linux-jz4740/include/linux/irq= =2Eh:27, > from /home/ralf/src/linux/linux-jz4740/include/asm-gener= ic/hardirq.h:12, > from /home/ralf/src/linux/linux-jz4740/arch/mips/include= /asm/hardirq.h:16, > from /home/ralf/src/linux/linux-jz4740/include/linux/har= dirq.h:7, > from /home/ralf/src/linux/linux-jz4740/include/linux/int= errupt.h:12, > from /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/= irq.c:19: > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.h:21:13: note: pre= vious declaration of =E2=80=98jz4740_irq_resume=E2=80=99 was here > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c: In function =E2= =80=98arch_init_irq=E2=80=99: > /home/ralf/src/linux/linux-jz4740/arch/mips/jz4740/irq.c:91:41: error: = =E2=80=98JZ4740_IRQ_BASE=E2=80=99 undeclared (first use in this function) >=20 > Which (while your patch is probably fine, I haven't tested) this seems to > be a build system issue, so should be preferably be fixed there. >=20 > Marek, the whole email exchange is archived at > http://www.linux-mips.org/archives/linux-mips/2012-09/threads.html Okay. I think I mentioned in the commit message for patch 1 that the include order seems to cause this. Maybe it's just a matter of rearranging those. Thierry --BOKacYhQ+x31HxR3 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAEBAgAGBQJQX0MEAAoJEN0jrNd/PrOh8QgP/085xg8zk4F13Gb9g4ur5lxY WkQmcdPjpdVbKAGsZIlNdM0gnONQlqeTX0DgqmKX1uqQBQRtaVHRDHIz6PnwnN8s NkBa1U63ffljEVfh4p05XXfTZUCRFUH2I24KTNZeirEIBwcsKictjALf0pJDLwtJ jlkcOk/P869DxQeQuGLrqBqb+RWAlCyGYAj/ZG0jUMLsD74yo8MZqMbGxV/hROGM ZfAB9TILAk9i46YAxrH+VdUxPcX+Piws01IcnV9jwcafg93gVA63XEua62oqLbw6 S8hwqNq5VLwjSMLqYrUTmXtCRFhxClMLpyAZ6YuT6IAsFApTLhQWG2LfDEQ6Tlmn VBS35MWiV3QaIY30ze0JrCbJE0WaSu9TtoUrYN4AMR7syK7LTfaA99F78nXKiRaw pup6zSD1rpT76zSPBfqyLGrzDS9Ma0RTO2xsgID7l0T6F1P2yiApOdE8/iHQEARD dhUvebODim2iAaaJaEVwm+fFErhHLTDqoeEVxUCnkDv4fghvhkhGHblrXG0vxcoV xXYrDB4F5QFv00+5fx2BtA/UFCvrapFwvaxwAewgqD4fqDNfW9089AV5Yu7QgVii eljnNr3WQtj/Fac/DijBmhKpLCKjOoIjy5R4UsD5yTMjsLrUKmYW5AlAmay6JiWA hnyERLjdjWyRtznTwR1D =urqc -----END PGP SIGNATURE----- --BOKacYhQ+x31HxR3-- From ralf@linux-mips.org Sun Sep 23 19:24:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 23 Sep 2012 19:25:00 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:40657 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903362Ab2IWRY4 (ORCPT ); Sun, 23 Sep 2012 19:24:56 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8NHOrNP005586; Sun, 23 Sep 2012 19:24:53 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8NHOqjO005585; Sun, 23 Sep 2012 19:24:52 +0200 Date: Sun, 23 Sep 2012 19:24:52 +0200 From: Ralf Baechle To: Jonas Gorski Cc: linux-mips@linux-mips.org, David Daney Subject: Re: [PATCH] MIPS: hide USE_OF Message-ID: <20120923172452.GC13842@linux-mips.org> References: <1347960534-5760-1-git-send-email-jonas.gorski@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1347960534-5760-1-git-send-email-jonas.gorski@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34538 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Status: RO Content-Length: 275 Lines: 9 On Tue, Sep 18, 2012 at 11:28:54AM +0200, Jonas Gorski wrote: > b01da9f1 ("MIPS: Prune some target specific code out of prom.c") removed > the generic implementation of device_tree_init, breaking the kernel > build when manually selecting USE_OF. Applied. Thanks, Ralf From ralf@linux-mips.org Sun Sep 23 19:35:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 23 Sep 2012 19:35:05 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:34075 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903360Ab2IWRfB (ORCPT ); Sun, 23 Sep 2012 19:35:01 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8NHYwYn006370; Sun, 23 Sep 2012 19:34:58 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8NHYu98006369; Sun, 23 Sep 2012 19:34:56 +0200 Date: Sun, 23 Sep 2012 19:34:56 +0200 From: Ralf Baechle To: Jonas Gorski Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Sergei Shtylyov Subject: Re: [PATCH V2] MIPS: BCM63XX: properly handle mac address octet overflow Message-ID: <20120923173455.GD13842@linux-mips.org> References: <1347960728-5884-1-git-send-email-jonas.gorski@gmail.com> <1347970148-17804-1-git-send-email-jonas.gorski@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1347970148-17804-1-git-send-email-jonas.gorski@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34539 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 26 Lines: 3 Applied. Thanks, Ralf From ralf@linux-mips.org Sun Sep 23 19:36:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 23 Sep 2012 19:36:16 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:34083 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903360Ab2IWRgM (ORCPT ); Sun, 23 Sep 2012 19:36:12 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8NHaAmd006495; Sun, 23 Sep 2012 19:36:10 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8NHa9D2006494; Sun, 23 Sep 2012 19:36:09 +0200 Date: Sun, 23 Sep 2012 19:36:09 +0200 From: Ralf Baechle To: Geert Uytterhoeven Cc: linux-mips@linux-mips.org, linux-next@vger.kernel.org Subject: Re: [PATCH -next] MIPS: ptrace: Add missing #include Message-ID: <20120923173609.GE13842@linux-mips.org> References: <1347913216-11140-1-git-send-email-geert@linux-m68k.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1347913216-11140-1-git-send-email-geert@linux-m68k.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34540 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 424 Lines: 10 On Mon, Sep 17, 2012 at 10:20:16PM +0200, Geert Uytterhoeven wrote: > arch/mips/kernel/ptrace.c: In function ‘syscall_trace_enter’: > arch/mips/kernel/ptrace.c:664: error: implicit declaration of function ‘__syscall_get_arch’ > make[2]: *** [arch/mips/kernel/ptrace.o] Error 1 Thanks, I already had fixed that in the linux-trace tree; the latest version just had not yet propagated yet to the other trees. Ralf From ralf@linux-mips.org Sun Sep 23 19:42:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 23 Sep 2012 19:42:32 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:36536 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903365Ab2IWRm3 (ORCPT ); Sun, 23 Sep 2012 19:42:29 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8NHgS8d006995; Sun, 23 Sep 2012 19:42:28 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8NHgSHq006994; Sun, 23 Sep 2012 19:42:28 +0200 Date: Sun, 23 Sep 2012 19:42:28 +0200 From: Ralf Baechle To: Gabor Juhos Cc: linux-mips@linux-mips.org, stable@vger.kernel.org Subject: Re: [PATCH] MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x Message-ID: <20120923174228.GF13842@linux-mips.org> References: <1346517960-13537-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1346517960-13537-1-git-send-email-juhosg@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34541 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 25 Lines: 3 Thanks, applied. Ralf From ralf@linux-mips.org Sun Sep 23 19:48:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 23 Sep 2012 19:48:56 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:54403 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903365Ab2IWRsw (ORCPT ); Sun, 23 Sep 2012 19:48:52 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q8NHmqtB007486; Sun, 23 Sep 2012 19:48:52 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q8NHmpAb007485; Sun, 23 Sep 2012 19:48:51 +0200 Date: Sun, 23 Sep 2012 19:48:51 +0200 From: Ralf Baechle To: Gabor Juhos Cc: linux-mips@linux-mips.org, stable@vger.kernel.org Subject: Re: [PATCH] MIPS: ath79: fix CPU/DDR frequency calculation for SRIF PLLs Message-ID: <20120923174851.GG13842@linux-mips.org> References: <1347105741-23091-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1347105741-23091-1-git-send-email-juhosg@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34542 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 401 Lines: 17 On Sat, Sep 08, 2012 at 02:02:21PM +0200, Gabor Juhos wrote: Applied but I had to fix a conflict: @@ -65,6 +65,8 @@ #define AR934X_WMAC_SIZE 0x20000 #define AR934X_EHCI_BASE 0x1b000000 #define AR934X_EHCI_SIZE 0x200 +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 /* * DDR_CTRL block The EHCI lines don't exist yet. Seems harmless though. Ralf From juhosg@openwrt.org Mon Sep 24 09:26:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Sep 2012 09:26:58 +0200 (CEST) Received: from arrakis.dune.hu ([78.24.191.176]:52090 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903373Ab2IXH0w (ORCPT ); Mon, 24 Sep 2012 09:26:52 +0200 X-Virus-Scanned: at arrakis.dune.hu Received: from [192.168.254.50] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 7B52223C00B5; Mon, 24 Sep 2012 09:26:46 +0200 (CEST) Message-ID: <50600B35.3050101@openwrt.org> Date: Mon, 24 Sep 2012 09:26:45 +0200 From: Gabor Juhos MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org, stable@vger.kernel.org Subject: Re: [PATCH] MIPS: ath79: fix CPU/DDR frequency calculation for SRIF PLLs References: <1347105741-23091-1-git-send-email-juhosg@openwrt.org> <20120923174851.GG13842@linux-mips.org> In-Reply-To: <20120923174851.GG13842@linux-mips.org> X-Enigmail-Version: 1.4.4 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 34543 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1202 Lines: 38 2012.09.23. 19:48 keltezéssel, Ralf Baechle írta: > On Sat, Sep 08, 2012 at 02:02:21PM +0200, Gabor Juhos wrote: > > Applied but I had to fix a conflict: > > @@ -65,6 +65,8 @@ > #define AR934X_WMAC_SIZE 0x20000 > #define AR934X_EHCI_BASE 0x1b000000 > #define AR934X_EHCI_SIZE 0x200 > +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) > +#define AR934X_SRIF_SIZE 0x1000 > > /* > * DDR_CTRL block > > The EHCI lines don't exist yet. Seems harmless though. Hm, I'm sure that the line was present a few days ago. It has been added by the following commit: commit 00ffed582fe8a3f7556593c0e8baaf3da3df85b0 Author: Gabor Juhos Date: Sat Aug 4 15:03:56 2012 +0000 MIPS: ath79: add USB platform setup code for AR934X Signed-off-by: Gabor Juhos Patchwork: http://patchwork.linux-mips.org/patch/4172/ Signed-off-by: John Crispin However I don't see that commit in the 'mips-for-linux-next' branch of the 'upstream-sfr.git' tree anymore. Also these changes are missing: MIPS: ath79: register USB host controller on the DB120 board MIPS: ath79: use a helper function for USB resource initialization -Gabor From sjhill@mips.com Mon Sep 24 16:47:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Sep 2012 16:47:42 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:37699 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903394Ab2IXOre (ORCPT ); Mon, 24 Sep 2012 16:47:34 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TG9wR-0007fD-5S; Mon, 24 Sep 2012 09:47:23 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, netdev@vger.kernel.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] net: mipsnet: Remove the MIPSsim Ethernet driver. Date: Mon, 24 Sep 2012 09:47:16 -0500 Message-Id: <1348498036-30257-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 34544 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10674 Lines: 399 From: "Steven J. Hill" The MIPSsim platform is no longer supported or used. This patch deletes the Ethernet driver. Signed-off-by: Steven J. Hill --- drivers/net/ethernet/Kconfig | 9 -- drivers/net/ethernet/Makefile | 1 - drivers/net/ethernet/mipsnet.c | 345 ---------------------------------------- 3 files changed, 355 deletions(-) delete mode 100644 drivers/net/ethernet/mipsnet.c diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index e507b78..9ce995b 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -89,15 +89,6 @@ source "drivers/net/ethernet/marvell/Kconfig" source "drivers/net/ethernet/mellanox/Kconfig" source "drivers/net/ethernet/micrel/Kconfig" source "drivers/net/ethernet/microchip/Kconfig" - -config MIPS_SIM_NET - tristate "MIPS simulator Network device" - depends on MIPS_SIM - ---help--- - The MIPSNET device is a simple Ethernet network device which is - emulated by the MIPS Simulator. - If you are not using a MIPSsim or are unsure, say N. - source "drivers/net/ethernet/myricom/Kconfig" config FEALNX diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index d1c7a11..9acd1d7 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -40,7 +40,6 @@ obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ obj-$(CONFIG_NET_VENDOR_MICROCHIP) += microchip/ -obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/ obj-$(CONFIG_FEALNX) += fealnx.o obj-$(CONFIG_NET_VENDOR_NATSEMI) += natsemi/ diff --git a/drivers/net/ethernet/mipsnet.c b/drivers/net/ethernet/mipsnet.c deleted file mode 100644 index db5285b..0000000 --- a/drivers/net/ethernet/mipsnet.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MIPSNET_VERSION "2007-11-17" - -/* - * Net status/control block as seen by sw in the core. - */ -struct mipsnet_regs { - /* - * Device info for probing, reads as MIPSNET%d where %d is some - * form of version. - */ - u64 devId; /*0x00 */ - - /* - * read only busy flag. - * Set and cleared by the Net Device to indicate that an rx or a tx - * is in progress. - */ - u32 busy; /*0x08 */ - - /* - * Set by the Net Device. - * The device will set it once data has been received. - * The value is the number of bytes that should be read from - * rxDataBuffer. The value will decrease till 0 until all the data - * from rxDataBuffer has been read. - */ - u32 rxDataCount; /*0x0c */ -#define MIPSNET_MAX_RXTX_DATACOUNT (1 << 16) - - /* - * Settable from the MIPS core, cleared by the Net Device. - * The core should set the number of bytes it wants to send, - * then it should write those bytes of data to txDataBuffer. - * The device will clear txDataCount has been processed (not - * necessarily sent). - */ - u32 txDataCount; /*0x10 */ - - /* - * Interrupt control - * - * Used to clear the interrupted generated by this dev. - * Write a 1 to clear the interrupt. (except bit31). - * - * Bit0 is set if it was a tx-done interrupt. - * Bit1 is set when new rx-data is available. - * Until this bit is cleared there will be no other RXs. - * - * Bit31 is used for testing, it clears after a read. - * Writing 1 to this bit will cause an interrupt to be generated. - * To clear the test interrupt, write 0 to this register. - */ - u32 interruptControl; /*0x14 */ -#define MIPSNET_INTCTL_TXDONE (1u << 0) -#define MIPSNET_INTCTL_RXDONE (1u << 1) -#define MIPSNET_INTCTL_TESTBIT (1u << 31) - - /* - * Readonly core-specific interrupt info for the device to signal - * the core. The meaning of the contents of this field might change. - */ - /* XXX: the whole memIntf interrupt scheme is messy: the device - * should have no control what so ever of what VPE/register set is - * being used. - * The MemIntf should only expose interrupt lines, and something in - * the config should be responsible for the line<->core/vpe bindings. - */ - u32 interruptInfo; /*0x18 */ - - /* - * This is where the received data is read out. - * There is more data to read until rxDataReady is 0. - * Only 1 byte at this regs offset is used. - */ - u32 rxDataBuffer; /*0x1c */ - - /* - * This is where the data to transmit is written. - * Data should be written for the amount specified in the - * txDataCount register. - * Only 1 byte at this regs offset is used. - */ - u32 txDataBuffer; /*0x20 */ -}; - -#define regaddr(dev, field) \ - (dev->base_addr + offsetof(struct mipsnet_regs, field)) - -static char mipsnet_string[] = "mipsnet"; - -/* - * Copy data from the MIPSNET rx data port - */ -static int ioiocpy_frommipsnet(struct net_device *dev, unsigned char *kdata, - int len) -{ - for (; len > 0; len--, kdata++) - *kdata = inb(regaddr(dev, rxDataBuffer)); - - return inl(regaddr(dev, rxDataCount)); -} - -static inline void mipsnet_put_todevice(struct net_device *dev, - struct sk_buff *skb) -{ - int count_to_go = skb->len; - char *buf_ptr = skb->data; - - outl(skb->len, regaddr(dev, txDataCount)); - - for (; count_to_go; buf_ptr++, count_to_go--) - outb(*buf_ptr, regaddr(dev, txDataBuffer)); - - dev->stats.tx_packets++; - dev->stats.tx_bytes += skb->len; - - dev_kfree_skb(skb); -} - -static int mipsnet_xmit(struct sk_buff *skb, struct net_device *dev) -{ - /* - * Only one packet at a time. Once TXDONE interrupt is serviced, the - * queue will be restarted. - */ - netif_stop_queue(dev); - mipsnet_put_todevice(dev, skb); - - return NETDEV_TX_OK; -} - -static inline ssize_t mipsnet_get_fromdev(struct net_device *dev, size_t len) -{ - struct sk_buff *skb; - - if (!len) - return len; - - skb = netdev_alloc_skb(dev, len + NET_IP_ALIGN); - if (!skb) { - dev->stats.rx_dropped++; - return -ENOMEM; - } - - skb_reserve(skb, NET_IP_ALIGN); - if (ioiocpy_frommipsnet(dev, skb_put(skb, len), len)) - return -EFAULT; - - skb->protocol = eth_type_trans(skb, dev); - skb->ip_summed = CHECKSUM_UNNECESSARY; - - netif_rx(skb); - - dev->stats.rx_packets++; - dev->stats.rx_bytes += len; - - return len; -} - -static irqreturn_t mipsnet_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - u32 int_flags; - irqreturn_t ret = IRQ_NONE; - - if (irq != dev->irq) - goto out_badirq; - - /* TESTBIT is cleared on read. */ - int_flags = inl(regaddr(dev, interruptControl)); - if (int_flags & MIPSNET_INTCTL_TESTBIT) { - /* TESTBIT takes effect after a write with 0. */ - outl(0, regaddr(dev, interruptControl)); - ret = IRQ_HANDLED; - } else if (int_flags & MIPSNET_INTCTL_TXDONE) { - /* Only one packet at a time, we are done. */ - dev->stats.tx_packets++; - netif_wake_queue(dev); - outl(MIPSNET_INTCTL_TXDONE, - regaddr(dev, interruptControl)); - ret = IRQ_HANDLED; - } else if (int_flags & MIPSNET_INTCTL_RXDONE) { - mipsnet_get_fromdev(dev, inl(regaddr(dev, rxDataCount))); - outl(MIPSNET_INTCTL_RXDONE, regaddr(dev, interruptControl)); - ret = IRQ_HANDLED; - } - return ret; - -out_badirq: - printk(KERN_INFO "%s: %s(): irq %d for unknown device\n", - dev->name, __func__, irq); - return ret; -} - -static int mipsnet_open(struct net_device *dev) -{ - int err; - - err = request_irq(dev->irq, mipsnet_interrupt, - IRQF_SHARED, dev->name, (void *) dev); - if (err) { - release_region(dev->base_addr, sizeof(struct mipsnet_regs)); - return err; - } - - netif_start_queue(dev); - - /* test interrupt handler */ - outl(MIPSNET_INTCTL_TESTBIT, regaddr(dev, interruptControl)); - - return 0; -} - -static int mipsnet_close(struct net_device *dev) -{ - netif_stop_queue(dev); - free_irq(dev->irq, dev); - return 0; -} - -static void mipsnet_set_mclist(struct net_device *dev) -{ -} - -static const struct net_device_ops mipsnet_netdev_ops = { - .ndo_open = mipsnet_open, - .ndo_stop = mipsnet_close, - .ndo_start_xmit = mipsnet_xmit, - .ndo_set_rx_mode = mipsnet_set_mclist, - .ndo_change_mtu = eth_change_mtu, - .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, -}; - -static int __devinit mipsnet_probe(struct platform_device *dev) -{ - struct net_device *netdev; - int err; - - netdev = alloc_etherdev(0); - if (!netdev) { - err = -ENOMEM; - goto out; - } - - platform_set_drvdata(dev, netdev); - - netdev->netdev_ops = &mipsnet_netdev_ops; - - /* - * TODO: probe for these or load them from PARAM - */ - netdev->base_addr = 0x4200; - netdev->irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB0 + - inl(regaddr(netdev, interruptInfo)); - - /* Get the io region now, get irq on open() */ - if (!request_region(netdev->base_addr, sizeof(struct mipsnet_regs), - "mipsnet")) { - err = -EBUSY; - goto out_free_netdev; - } - - /* - * Lacking any better mechanism to allocate a MAC address we use a - * random one ... - */ - eth_hw_addr_random(netdev); - - err = register_netdev(netdev); - if (err) { - printk(KERN_ERR "MIPSNet: failed to register netdev.\n"); - goto out_free_region; - } - - return 0; - -out_free_region: - release_region(netdev->base_addr, sizeof(struct mipsnet_regs)); - -out_free_netdev: - free_netdev(netdev); - -out: - return err; -} - -static int __devexit mipsnet_device_remove(struct platform_device *device) -{ - struct net_device *dev = platform_get_drvdata(device); - - unregister_netdev(dev); - release_region(dev->base_addr, sizeof(struct mipsnet_regs)); - free_netdev(dev); - platform_set_drvdata(device, NULL); - - return 0; -} - -static struct platform_driver mipsnet_driver = { - .driver = { - .name = mipsnet_string, - .owner = THIS_MODULE, - }, - .probe = mipsnet_probe, - .remove = __devexit_p(mipsnet_device_remove), -}; - -static int __init mipsnet_init_module(void) -{ - int err; - - printk(KERN_INFO "MIPSNet Ethernet driver. Version: %s. " - "(c)2005 MIPS Technologies, Inc.\n", MIPSNET_VERSION); - - err = platform_driver_register(&mipsnet_driver); - if (err) - printk(KERN_ERR "Driver registration failed\n"); - - return err; -} - -static void __exit mipsnet_exit_module(void) -{ - platform_driver_unregister(&mipsnet_driver); -} - -module_init(mipsnet_init_module); -module_exit(mipsnet_exit_module); -- 1.7.9.5 From sjhill@mips.com Mon Sep 24 16:49:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Sep 2012 16:49:16 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:37709 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903398Ab2IXOtF (ORCPT ); Mon, 24 Sep 2012 16:49:05 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TG9xy-0007fV-Nn; Mon, 24 Sep 2012 09:48:58 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: MIPSsim: Remove the MIPSsim platform. Date: Mon, 24 Sep 2012 09:48:53 -0500 Message-Id: <1348498133-30328-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 34545 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 23015 Lines: 863 From: "Steven J. Hill" The MIPSsim platform is no longer supported or used. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 19 ----- arch/mips/configs/mipssim_defconfig | 64 --------------- arch/mips/include/asm/mips-boards/simint.h | 31 -------- arch/mips/mipssim/Makefile | 23 ------ arch/mips/mipssim/Platform | 6 -- arch/mips/mipssim/sim_console.c | 40 ---------- arch/mips/mipssim/sim_int.c | 87 --------------------- arch/mips/mipssim/sim_mem.c | 115 --------------------------- arch/mips/mipssim/sim_platform.c | 35 --------- arch/mips/mipssim/sim_setup.c | 99 ----------------------- arch/mips/mipssim/sim_smtc.c | 116 --------------------------- arch/mips/mipssim/sim_time.c | 117 ---------------------------- 12 files changed, 752 deletions(-) delete mode 100644 arch/mips/configs/mipssim_defconfig delete mode 100644 arch/mips/include/asm/mips-boards/simint.h delete mode 100644 arch/mips/mipssim/Makefile delete mode 100644 arch/mips/mipssim/Platform delete mode 100644 arch/mips/mipssim/sim_console.c delete mode 100644 arch/mips/mipssim/sim_int.c delete mode 100644 arch/mips/mipssim/sim_mem.c delete mode 100644 arch/mips/mipssim/sim_platform.c delete mode 100644 arch/mips/mipssim/sim_setup.c delete mode 100644 arch/mips/mipssim/sim_smtc.c delete mode 100644 arch/mips/mipssim/sim_time.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6e52408..f989b0c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -350,25 +350,6 @@ config MIPS_SEAD3 This enables support for the MIPS Technologies SEAD3 evaluation board. -config MIPS_SIM - bool 'MIPS simulator (MIPSsim)' - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select SYS_HAS_EARLY_PRINTK - select IRQ_CPU - select BOOT_RAW - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_MULTITHREADING - select SYS_SUPPORTS_LITTLE_ENDIAN - help - This option enables support for MIPS Technologies MIPSsim software - emulator. - config NEC_MARKEINS bool "NEC EMMA2RH Mark-eins board" select SOC_EMMA2RH diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig deleted file mode 100644 index b5ad738..0000000 --- a/arch/mips/configs/mipssim_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_MIPS_SIM=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -# CONFIG_MISC_DEVICES is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_MIPS_SIM_NET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_ROMFS_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_INFO=y -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp" -# CONFIG_CRC32 is not set diff --git a/arch/mips/include/asm/mips-boards/simint.h b/arch/mips/include/asm/mips-boards/simint.h deleted file mode 100644 index 8ef6db7..0000000 --- a/arch/mips/include/asm/mips-boards/simint.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef _MIPS_SIMINT_H -#define _MIPS_SIMINT_H - -#include - -#define SIM_INT_BASE 0 -#define MIPSCPU_INT_MB0 2 -#define MIPS_CPU_TIMER_IRQ 7 - - -#define MSC01E_INT_BASE 64 - -#define MSC01E_INT_CPUCTR 11 - -#endif diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile deleted file mode 100644 index 01410a3..0000000 --- a/arch/mips/mipssim/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. -# Copyright (C) 2007 MIPS Technologies, Inc. -# written by Ralf Baechle (ralf@linux-mips.org) -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# - -obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o - -obj-$(CONFIG_EARLY_PRINTK) += sim_console.o -obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o diff --git a/arch/mips/mipssim/Platform b/arch/mips/mipssim/Platform deleted file mode 100644 index 3df60b8a..0000000 --- a/arch/mips/mipssim/Platform +++ /dev/null @@ -1,6 +0,0 @@ -# -# MIPS SIM -# -platform-$(CONFIG_MIPS_SIM) += mipssim/ -cflags-$(CONFIG_MIPS_SIM) += -I$(srctree)/arch/mips/include/asm/mach-mipssim -load-$(CONFIG_MIPS_SIM) += 0x80100000 diff --git a/arch/mips/mipssim/sim_console.c b/arch/mips/mipssim/sim_console.c deleted file mode 100644 index a2f4167..0000000 --- a/arch/mips/mipssim/sim_console.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2007 MIPS Technologies, Inc. - * written by Ralf Baechle - */ -#include -#include -#include - -static inline unsigned int serial_in(int offset) -{ - return inb(0x3f8 + offset); -} - -static inline void serial_out(int offset, int value) -{ - outb(value, 0x3f8 + offset); -} - -void __init prom_putchar(char c) -{ - while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(UART_TX, c); -} diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c deleted file mode 100644 index 5c779be..0000000 --- a/arch/mips/mipssim/sim_int.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ -#include -#include -#include -#include -#include -#include - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = s0 & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0x8000; - t0 = t0 < 1; - /* t0 = t0 << 2; */ - a0 = a0 - t0; - /* s0 = s0 << t0; */ - - return a0; -#endif -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq > 0) - do_IRQ(MIPS_CPU_IRQ_BASE + irq); - else - spurious_interrupt(); -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(); -} diff --git a/arch/mips/mipssim/sim_mem.c b/arch/mips/mipssim/sim_mem.c deleted file mode 100644 index 953d836..0000000 --- a/arch/mips/mipssim/sim_mem.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ -#include -#include -#include -#include - -#include -#include -#include - -#include - -/*#define DEBUG*/ - -enum simmem_memtypes { - simmem_reserved = 0, - simmem_free, -}; -struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -#ifdef DEBUG -static char *mtypes[3] = { - "SIM reserved memory", - "SIM free memory", -}; -#endif - -struct prom_pmemblock * __init prom_getmdesc(void) -{ - unsigned int memsize; - - memsize = 0x02000000; - pr_info("Setting default memory size 0x%08x\n", memsize); - - memset(mdesc, 0, sizeof(mdesc)); - - mdesc[0].type = simmem_reserved; - mdesc[0].base = 0x00000000; - mdesc[0].size = 0x00001000; - - mdesc[1].type = simmem_free; - mdesc[1].base = 0x00001000; - mdesc[1].size = 0x000ff000; - - mdesc[2].type = simmem_reserved; - mdesc[2].base = 0x00100000; - mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base; - - mdesc[3].type = simmem_free; - mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end)); - mdesc[3].size = memsize - mdesc[3].base; - - return &mdesc[0]; -} - -static int __init prom_memtype_classify(unsigned int type) -{ - switch (type) { - case simmem_free: - return BOOT_MEM_RAM; - case simmem_reserved: - default: - return BOOT_MEM_RESERVED; - } -} - -void __init prom_meminit(void) -{ - struct prom_pmemblock *p; - - p = prom_getmdesc(); - - while (p->size) { - long type; - unsigned long base, size; - - type = prom_memtype_classify(p->type); - base = p->base; - size = p->size; - - add_memory_region(base, size, type); - p++; - } -} - -void __init prom_free_prom_memory(void) -{ - int i; - unsigned long addr; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/mipssim/sim_platform.c b/arch/mips/mipssim/sim_platform.c deleted file mode 100644 index 53210a8..0000000 --- a/arch/mips/mipssim/sim_platform.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 by Ralf Baechle (ralf@linux-mips.org) - */ -#include -#include -#include -#include - -static char mipsnet_string[] = "mipsnet"; - -static struct platform_device eth1_device = { - .name = mipsnet_string, - .id = 0, -}; - -/* - * Create a platform device for the GPI port that receives the - * image data from the embedded camera. - */ -static int __init mipsnet_devinit(void) -{ - int err; - - err = platform_device_register(ð1_device); - if (err) - printk(KERN_ERR "%s: registration failed\n", mipsnet_string); - - return err; -} - -device_initcall(mipsnet_devinit); diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c deleted file mode 100644 index 256e0cd..0000000 --- a/arch/mips/mipssim/sim_setup.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -static void __init serial_init(void); -unsigned int _isbonito; - -const char *get_system_type(void) -{ - return "MIPSsim"; -} - -void __init plat_mem_setup(void) -{ - set_io_port_base(0xbfd00000); - - serial_init(); -} - -extern struct plat_smp_ops ssmtc_smp_ops; - -void __init prom_init(void) -{ - set_io_port_base(0xbfd00000); - - prom_meminit(); - - if (cpu_has_mipsmt) { - if (!register_vsmp_smp_ops()) - return; - -#ifdef CONFIG_MIPS_MT_SMTC - register_smp_ops(&ssmtc_smp_ops); - return; -#endif - } - - register_up_smp_ops(); -} - -static void __init serial_init(void) -{ -#ifdef CONFIG_SERIAL_8250 - struct uart_port s; - - memset(&s, 0, sizeof(s)); - - s.iobase = 0x3f8; - - /* hardware int 4 - the serial int, is CPU int 6 - but poll for now */ - s.irq = 0; - s.uartclk = 1843200; - s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - s.iotype = UPIO_PORT; - s.regshift = 0; - s.timeout = 4; - - if (early_serial_setup(&s) != 0) { - printk(KERN_ERR "Serial setup failed!\n"); - } - -#endif -} diff --git a/arch/mips/mipssim/sim_smtc.c b/arch/mips/mipssim/sim_smtc.c deleted file mode 100644 index 3c104ab..0000000 --- a/arch/mips/mipssim/sim_smtc.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ -/* - * Simulator Platform-specific hooks for SMTC operation - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* VPE/SMP Prototype implements platform interfaces directly */ - -/* - * Cause the specified action to be performed on a targeted "CPU" - */ - -static void ssmtc_send_ipi_single(int cpu, unsigned int action) -{ - smtc_send_ipi(cpu, LINUX_SMP_IPI, action); - /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ -} - -static inline void ssmtc_send_ipi_mask(const struct cpumask *mask, - unsigned int action) -{ - unsigned int i; - - for_each_cpu(i, mask) - ssmtc_send_ipi_single(i, action); -} - -/* - * Post-config but pre-boot cleanup entry point - */ -static void __cpuinit ssmtc_init_secondary(void) -{ - smtc_init_secondary(); -} - -/* - * SMP initialization finalization entry point - */ -static void __cpuinit ssmtc_smp_finish(void) -{ - smtc_smp_finish(); -} - -/* - * Hook for after all CPUs are online - */ -static void ssmtc_cpus_done(void) -{ -} - -/* - * Platform "CPU" startup hook - */ -static void __cpuinit ssmtc_boot_secondary(int cpu, struct task_struct *idle) -{ - smtc_boot_secondary(cpu, idle); -} - -static void __init ssmtc_smp_setup(void) -{ - if (read_c0_config3() & (1 << 2)) - mipsmt_build_cpu_map(0); -} - -/* - * Platform SMP pre-initialization - */ -static void ssmtc_prepare_cpus(unsigned int max_cpus) -{ - /* - * As noted above, we can assume a single CPU for now - * but it may be multithreaded. - */ - - if (read_c0_config3() & (1 << 2)) { - mipsmt_prepare_cpus(); - } -} - -struct plat_smp_ops ssmtc_smp_ops = { - .send_ipi_single = ssmtc_send_ipi_single, - .send_ipi_mask = ssmtc_send_ipi_mask, - .init_secondary = ssmtc_init_secondary, - .smp_finish = ssmtc_smp_finish, - .cpus_done = ssmtc_cpus_done, - .boot_secondary = ssmtc_boot_secondary, - .smp_setup = ssmtc_smp_setup, - .prepare_cpus = ssmtc_prepare_cpus, -}; diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c deleted file mode 100644 index 77bad3c..0000000 --- a/arch/mips/mipssim/sim_time.c +++ /dev/null @@ -1,117 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - - -unsigned long cpu_khz; - -/* - * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect - */ -static unsigned int __init estimate_cpu_frequency(void) -{ - unsigned int prid = read_c0_prid() & 0xffff00; - unsigned int count; - -#if 1 - /* - * hardwire the board frequency to 12MHz. - */ - - if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || - (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) - count = 12000000; - else - count = 6000000; -#else - unsigned int flags; - - local_irq_save(flags); - - /* Start counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - /* Start r4k counter. */ - write_c0_count(0); - - /* Read counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - count = read_c0_count(); - - /* restore interrupts */ - local_irq_restore(flags); -#endif - - mips_hpt_frequency = count; - - if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && - (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) - count *= 2; - - count += 5000; /* round */ - count -= count%10000; - - return count; -} - -static int mips_cpu_timer_irq; - -static void mips_timer_dispatch(void) -{ - do_IRQ(mips_cpu_timer_irq); -} - - -unsigned __cpuinit get_c0_compare_int(void) -{ -#ifdef MSC01E_INT_BASE - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); - mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; - - return mips_cpu_timer_irq; - } -#endif - if (cpu_has_vint) - set_vi_handler(cp0_compare_irq, mips_timer_dispatch); - mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; - - return mips_cpu_timer_irq; -} - -void __init plat_time_init(void) -{ - unsigned int est_freq; - - /* Set Data mode - binary. */ - CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - - est_freq = estimate_cpu_frequency(); - - printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, - (est_freq % 1000000) * 100 / 1000000); - - cpu_khz = est_freq / 1000; -} -- 1.7.9.5 From ddaney.cavm@gmail.com Mon Sep 24 20:23:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Sep 2012 20:23:56 +0200 (CEST) Received: from mail-pa0-f49.google.com ([209.85.220.49]:35521 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903439Ab2IXSXu (ORCPT ); Mon, 24 Sep 2012 20:23:50 +0200 Received: by padbi5 with SMTP id bi5so1656739pad.36 for ; Mon, 24 Sep 2012 11:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=DZlv4501ZD/mVzPylBgmcikrAMI+bbLtQ+j9+Y51m94=; b=MFBvozTcuR7hW9OvX0MZq2yZ8KBOXWvzJ+xNOGwoRLUtdEpHLcNjb0P5uzQl9NYi8p 5RocUsP6/9Kq+znJlbELTBW3Xlbw5KPIZpDNh7oZLdIMyCSLeze/S72EHMFTPW/mwk/x 9Zsi7x7lVO/xu5iONPLDZptQaEcfvT9bVEfzAb321XE9A2/9bNAZk1mU4oDnITBPcvfh uVqDfOR5EFBHaF2CzIeSZFfO0WXsxBffnjjL44F+5y2lq6vBrPEk9DGs+kYcYU5ia29F 3ZuKNqXTXdXzG4flY2z/z6395f2l7Q9OCCHvE43MTu84AhRHYsoxmO3elfmVJ0z0c1Wz Vrjw== Received: by 10.68.190.197 with SMTP id gs5mr39595457pbc.124.1348511023601; Mon, 24 Sep 2012 11:23:43 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ky6sm5223472pbc.18.2012.09.24.11.23.41 (version=SSLv3 cipher=OTHER); Mon, 24 Sep 2012 11:23:42 -0700 (PDT) Message-ID: <5060A52C.1050504@gmail.com> Date: Mon, 24 Sep 2012 11:23:40 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0 MIME-Version: 1.0 To: Ralf Baechle CC: Geert Uytterhoeven , linux-mips@linux-mips.org, linux-next@vger.kernel.org Subject: Re: [PATCH -next] MIPS: ptrace: Add missing #include References: <1347913216-11140-1-git-send-email-geert@linux-m68k.org> <20120923173609.GE13842@linux-mips.org> In-Reply-To: <20120923173609.GE13842@linux-mips.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 34546 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 621 Lines: 16 On 09/23/2012 10:36 AM, Ralf Baechle wrote: > On Mon, Sep 17, 2012 at 10:20:16PM +0200, Geert Uytterhoeven wrote: > >> arch/mips/kernel/ptrace.c: In function ‘syscall_trace_enter’: >> arch/mips/kernel/ptrace.c:664: error: implicit declaration of function ‘__syscall_get_arch’ >> make[2]: *** [arch/mips/kernel/ptrace.o] Error 1 > > Thanks, I already had fixed that in the linux-trace tree; the latest > version just had not yet propagated yet to the other trees. > It is still not on mips-for-linux-next. Perhaps we should arrange for it to be there, so that the actual propagation may commence. David Daney From davem@davemloft.net Mon Sep 24 22:41:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Sep 2012 22:41:43 +0200 (CEST) Received: from shards.monkeyblade.net ([149.20.54.216]:51816 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903439Ab2IXUlh (ORCPT ); Mon, 24 Sep 2012 22:41:37 +0200 Received: from localhost (nat-pool-rdu.redhat.com [66.187.233.202]) by shards.monkeyblade.net (Postfix) with ESMTPSA id 9A1C9584CEA; Mon, 24 Sep 2012 13:41:34 -0700 (PDT) Date: Mon, 24 Sep 2012 16:41:30 -0400 (EDT) Message-Id: <20120924.164130.1073842749430205590.davem@davemloft.net> To: sjhill@mips.com Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, ralf@linux-mips.org Subject: Re: [PATCH] net: mipsnet: Remove the MIPSsim Ethernet driver. From: David Miller In-Reply-To: <1348498036-30257-1-git-send-email-sjhill@mips.com> References: <1348498036-30257-1-git-send-email-sjhill@mips.com> X-Mailer: Mew version 6.5 on Emacs 24.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-archive-position: 34547 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 314 Lines: 11 From: "Steven J. Hill" Date: Mon, 24 Sep 2012 09:47:16 -0500 > From: "Steven J. Hill" > > The MIPSsim platform is no longer supported or used. This patch > deletes the Ethernet driver. > > Signed-off-by: Steven J. Hill I'll apply this to net-next, thanks. From ralf@linux-mips.org Tue Sep 25 12:33:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue,