From sshtylyov@mvista.com Sat Jun 30 22:06:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 30 Jun 2012 22:07:05 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:47267 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903540Ab2F3UG5 (ORCPT ); Sat, 30 Jun 2012 22:06:57 +0200 Received: by lbbgg6 with SMTP id gg6so6147372lbb.36 for ; Sat, 30 Jun 2012 13:06:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=OWV4hlFooLXfnovwkdvsgH8QFVwSr8XAEhy93ctP7Vc=; b=Oe/7lgr8aarp0KF8CEOcZGzWEXSLF/y1K1A1d2VMX6QK5oSzaXSgKWlhEmVpZfIEgK QnqIsudKlldEW2ijaS3ZMuepOc+79VtwrGxK71Xr1NVfp+tDTuYmraYTbQepR6A/iiME jpEV2ad3bSphGIRFws4J+UXDts3IYSzxAUxaVYW36Q1bZqS8YP7Fyri1Ob4b9aQzd5gM C6NSqCjWXGfM0lepNSNisk/w08RYQ+Bqzdmzw3w/3i1ZdEOOha9dxE/2fpCDxiLhIDBq wS88GRIEcOxY4kTVfLZBfEP69U69oaa8Nnp9tYP1dvnjKSXOLgSf/aAQV2BT9a0CD7yo 5prA== Received: by 10.112.36.195 with SMTP id s3mr3411816lbj.42.1341086811095; Sat, 30 Jun 2012 13:06:51 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-87-54.pppoe.mtu-net.ru. [91.79.87.54]) by mx.google.com with ESMTPS id fy10sm13036560lab.0.2012.06.30.13.06.49 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 30 Jun 2012 13:06:50 -0700 (PDT) Message-ID: <4FEF5C29.50107@mvista.com> Date: Sun, 01 Jul 2012 00:06:01 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v4,04/10] Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler. References: <1340994924-3922-1-git-send-email-sjhill@mips.com> In-Reply-To: <1340994924-3922-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQknMtsYlrZA8SIQluJT/UcsYvFIYxj1Y6lJ/SDlA2rIpnFK3McCuz2JQ+3cJOiZgP2Tms3g X-archive-position: 33872 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 817 Lines: 38 Hello. On 29-06-2012 22:35, Steven J. Hill wrote: > From: "Steven J. Hill" > Signed-off-by: Steven J. Hill [...] > diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c > index 5fa1851..663b6b1 100644 > --- a/arch/mips/mm/uasm.c > +++ b/arch/mips/mm/uasm.c [...] > @@ -343,6 +345,13 @@ Ip_u2u1msbu3(op) \ > } \ > UASM_EXPORT_SYMBOL(uasm_i##op); > > +#define I_u2u1mmsbu3(op) \ > +Ip_u2u1msbu3(op) \ > +{ \ > + build_insn(buf, insn##op, b, a, d-1, c); \ > +} \ > +UASM_EXPORT_SYMBOL(uasm_i##op); > + > #define I_u1u2(op) \ > Ip_u1u2(op) \ > { \ > @@ -396,6 +405,8 @@ I_u2u1u3(_drotr) > I_u2u1u3(_drotr32) > I_u3u1u2(_dsubu) > I_0(_eret) > +I_u2u1mmsbu3(_ext) > +I_u2u1msbu3(_ins) Not I_u2u1mmsbu3()? WBR, Sergei From srivatsa.bhat@linux.vnet.ibm.com Fri Jun 1 11:13:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Jun 2012 11:13:39 +0200 (CEST) Received: from e28smtp02.in.ibm.com ([122.248.162.2]:45503 "EHLO e28smtp02.in.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903605Ab2FAJN3 (ORCPT ); Fri, 1 Jun 2012 11:13:29 +0200 Received: from /spool/local by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 1 Jun 2012 14:43:21 +0530 Received: from d28relay03.in.ibm.com (9.184.220.60) by e28smtp02.in.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 1 Jun 2012 14:43:18 +0530 Received: from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63]) by d28relay03.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q519DHGn55443464; Fri, 1 Jun 2012 14:43:17 +0530 Received: from d28av01.in.ibm.com (loopback [127.0.0.1]) by d28av01.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q51Egpu6026697; Fri, 1 Jun 2012 20:12:53 +0530 Received: from srivatsabhat.in.ibm.com (srivatsabhat.in.ibm.com [9.124.35.113]) by d28av01.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q51EgoMF026615; Fri, 1 Jun 2012 20:12:50 +0530 From: "Srivatsa S. Bhat" Subject: [PATCH 10/27] mips, smpboot: Use generic SMP booting infrastructure To: tglx@linutronix.de, peterz@infradead.org, paulmck@linux.vnet.ibm.com Cc: rusty@rustcorp.com.au, mingo@kernel.org, yong.zhang0@gmail.com, akpm@linux-foundation.org, vatsa@linux.vnet.ibm.com, rjw@sisk.pl, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, srivatsa.bhat@linux.vnet.ibm.com, nikunj@linux.vnet.ibm.com, Ralf Baechle , Andrew Morton , Eric Dumazet , Mike Frysinger , David Howells , Arun Sharma , Thomas Gleixner , Rusty Russell , linux-mips@linux-mips.org Date: Fri, 01 Jun 2012 14:42:32 +0530 Message-ID: <20120601091226.31979.62223.stgit@srivatsabhat.in.ibm.com> In-Reply-To: <20120601090952.31979.24799.stgit@srivatsabhat.in.ibm.com> References: <20120601090952.31979.24799.stgit@srivatsabhat.in.ibm.com> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit x-cbid: 12060109-5816-0000-0000-000002F5CFC1 X-archive-position: 33503 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: srivatsa.bhat@linux.vnet.ibm.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4473 Lines: 153 Convert mips to use the generic framework to boot secondary CPUs. Notes: 1. The boot processor was setting the secondary cpu in cpu_online_mask! Instead, leave it up to the secondary cpu (... and it will be done by the generic code now). 2. Make the boot cpu wait for the secondary cpu to be set in cpu_online_mask before returning. 3. Don't enable interrupts in cmp_smp_finish() and vsmp_smp_finish(). Do it much later, in generic code. 4. In synchronise_count_slave(), use local_save_flags() instead of local_irq_save() because irqs are still disabled. Cc: Ralf Baechle Cc: Andrew Morton Cc: Eric Dumazet Cc: Mike Frysinger Cc: David Howells Cc: Arun Sharma Cc: Thomas Gleixner Cc: Rusty Russell Cc: linux-mips@linux-mips.org Signed-off-by: Srivatsa S. Bhat --- arch/mips/kernel/smp-cmp.c | 8 ++++---- arch/mips/kernel/smp-mt.c | 2 -- arch/mips/kernel/smp.c | 23 +++++++++++++++-------- arch/mips/kernel/sync-r4k.c | 3 ++- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index e7e03ec..7ecd6db 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -108,7 +108,9 @@ static void cmp_init_secondary(void) static void cmp_smp_finish(void) { - pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__); + unsigned int cpu = smp_processor_id(); + + pr_debug("SMPCMP: CPU%d: %s\n", cpu, __func__); /* CDFIXME: remove this? */ write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); @@ -116,10 +118,8 @@ static void cmp_smp_finish(void) #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ if (cpu_has_fpu) - cpu_set(smp_processor_id(), mt_fpu_cpumask); + cpumask_set_cpu(cpu, &mt_fpu_cpumask); #endif /* CONFIG_MIPS_MT_FPAFF */ - - local_irq_enable(); } static void cmp_cpus_done(void) diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ff17868..25f7b09 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -171,8 +171,6 @@ static void __cpuinit vsmp_smp_finish(void) if (cpu_has_fpu) cpu_set(smp_processor_id(), mt_fpu_cpumask); #endif /* CONFIG_MIPS_MT_FPAFF */ - - local_irq_enable(); } static void vsmp_cpus_done(void) diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 71a95f5..4453d4d 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -98,8 +99,11 @@ __cpuinit void register_smp_ops(struct plat_smp_ops *ops) */ asmlinkage __cpuinit void start_secondary(void) { - unsigned int cpu; + smpboot_start_secondary(NULL); +} +void __cpuinit __cpu_pre_starting(void *unused) +{ #ifdef CONFIG_MIPS_MT_SMTC /* Only do cpu_probe for first TC of CPU */ if ((read_c0_tcbind() & TCBIND_CURTC) == 0) @@ -116,20 +120,22 @@ asmlinkage __cpuinit void start_secondary(void) */ calibrate_delay(); - preempt_disable(); - cpu = smp_processor_id(); - cpu_data[cpu].udelay_val = loops_per_jiffy; + cpu_data[smp_processor_id()].udelay_val = loops_per_jiffy; +} - notify_cpu_starting(cpu); +void __cpuinit __cpu_pre_online(void *unused) +{ + unsigned int cpu = smp_processor_id(); mp_ops->smp_finish(); set_cpu_sibling_map(cpu); cpu_set(cpu, cpu_callin_map); +} +void __cpuinit __cpu_post_online(void *unused) +{ synchronise_count_slave(); - - cpu_idle(); } /* @@ -196,7 +202,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) while (!cpu_isset(cpu, cpu_callin_map)) udelay(100); - set_cpu_online(cpu, true); + while (!cpu_online(cpu)) + udelay(100); return 0; } diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c index 99f913c..7f43069 100644 --- a/arch/mips/kernel/sync-r4k.c +++ b/arch/mips/kernel/sync-r4k.c @@ -46,7 +46,8 @@ void __cpuinit synchronise_count_master(void) printk(KERN_INFO "Synchronize counters across %u CPUs: ", num_online_cpus()); - local_irq_save(flags); + /* IRQs are already disabled. So just save the flags */ + local_save_flags(flags); /* * Notify the slaves that it's time to start From srivatsa.bhat@linux.vnet.ibm.com Fri Jun 1 12:48:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Jun 2012 12:48:15 +0200 (CEST) Received: from e23smtp09.au.ibm.com ([202.81.31.142]:41979 "EHLO e23smtp09.au.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903607Ab2FAKsK (ORCPT ); Fri, 1 Jun 2012 12:48:10 +0200 Received: from /spool/local by e23smtp09.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 1 Jun 2012 11:15:10 +1000 Received: from d23relay05.au.ibm.com (202.81.31.247) by e23smtp09.au.ibm.com (202.81.31.206) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 1 Jun 2012 11:14:43 +1000 Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay05.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q5194Zl541746644; Fri, 1 Jun 2012 19:05:27 +1000 Received: from d23av03.au.ibm.com (loopback [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q519BWts003283; Fri, 1 Jun 2012 19:11:33 +1000 Received: from srivatsabhat.in.ibm.com (srivatsabhat.in.ibm.com [9.124.35.113]) by d23av03.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q519BPe7003154; Fri, 1 Jun 2012 19:11:25 +1000 From: "Srivatsa S. Bhat" Subject: [PATCH 03/27] smpboot: Define and use cpu_state per-cpu variable in generic code To: tglx@linutronix.de, peterz@infradead.org, paulmck@linux.vnet.ibm.com Cc: rusty@rustcorp.com.au, mingo@kernel.org, yong.zhang0@gmail.com, akpm@linux-foundation.org, vatsa@linux.vnet.ibm.com, rjw@sisk.pl, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, srivatsa.bhat@linux.vnet.ibm.com, nikunj@linux.vnet.ibm.com, Tony Luck , Fenghua Yu , Ralf Baechle , Benjamin Herrenschmidt , Paul Mundt , Chris Metcalf , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Konrad Rzeszutek Wilk , Jeremy Fitzhardinge , Peter Zijlstra , Andrew Morton , Mike Frysinger , Yong Zhang , Venkatesh Pallipadi , Suresh Siddha , linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, xen-devel@lists.xensource.com, virtualization@lists.linux-foundation.org Date: Fri, 01 Jun 2012 14:40:44 +0530 Message-ID: <20120601091038.31979.67878.stgit@srivatsabhat.in.ibm.com> In-Reply-To: <20120601090952.31979.24799.stgit@srivatsabhat.in.ibm.com> References: <20120601090952.31979.24799.stgit@srivatsabhat.in.ibm.com> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit x-cbid: 12060101-3568-0000-0000-000001E92C27 X-archive-position: 33504 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: srivatsa.bhat@linux.vnet.ibm.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8088 Lines: 277 The per-cpu variable cpu_state is used in x86 and also used in other architectures, to track the state of the cpu during bringup and hotplug. Pull it out into generic code. Cc: Tony Luck Cc: Fenghua Yu Cc: Ralf Baechle Cc: Benjamin Herrenschmidt Cc: Paul Mundt Cc: Chris Metcalf Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: Konrad Rzeszutek Wilk Cc: Jeremy Fitzhardinge Cc: Peter Zijlstra Cc: Andrew Morton Cc: Mike Frysinger Cc: Yong Zhang Cc: Venkatesh Pallipadi Cc: Suresh Siddha Cc: linux-ia64@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-sh@vger.kernel.org Cc: xen-devel@lists.xensource.com Cc: virtualization@lists.linux-foundation.org Signed-off-by: Srivatsa S. Bhat --- arch/ia64/include/asm/cpu.h | 2 -- arch/ia64/kernel/process.c | 1 + arch/ia64/kernel/smpboot.c | 6 +----- arch/mips/cavium-octeon/smp.c | 4 +--- arch/powerpc/kernel/smp.c | 6 +----- arch/sh/include/asm/smp.h | 2 -- arch/sh/kernel/smp.c | 4 +--- arch/tile/kernel/smpboot.c | 4 +--- arch/x86/include/asm/cpu.h | 2 -- arch/x86/kernel/smpboot.c | 4 +--- arch/x86/xen/smp.c | 1 + include/linux/smpboot.h | 1 + kernel/smpboot.c | 4 ++++ 13 files changed, 13 insertions(+), 28 deletions(-) diff --git a/arch/ia64/include/asm/cpu.h b/arch/ia64/include/asm/cpu.h index fcca30b..1c3acac 100644 --- a/arch/ia64/include/asm/cpu.h +++ b/arch/ia64/include/asm/cpu.h @@ -12,8 +12,6 @@ struct ia64_cpu { DECLARE_PER_CPU(struct ia64_cpu, cpu_devices); -DECLARE_PER_CPU(int, cpu_state); - #ifdef CONFIG_HOTPLUG_CPU extern int arch_register_cpu(int num); extern void arch_unregister_cpu(int); diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c index 5e0e86d..32566c7 100644 --- a/arch/ia64/kernel/process.c +++ b/arch/ia64/kernel/process.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c index 963d2db..df00a3c 100644 --- a/arch/ia64/kernel/smpboot.c +++ b/arch/ia64/kernel/smpboot.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include @@ -111,11 +112,6 @@ extern unsigned long ia64_iobase; struct task_struct *task_for_booting_cpu; -/* - * State for each CPU - */ -DEFINE_PER_CPU(int, cpu_state); - cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned; EXPORT_SYMBOL(cpu_core_map); DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map); diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 97e7ce9..93cd4b0 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -252,9 +253,6 @@ static void octeon_cpus_done(void) #ifdef CONFIG_HOTPLUG_CPU -/* State of each CPU. */ -DEFINE_PER_CPU(int, cpu_state); - extern void fixup_irqs(void); static DEFINE_SPINLOCK(smp_reserve_lock); diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index e1417c4..1928058a 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -57,11 +58,6 @@ #define DBG(fmt...) #endif -#ifdef CONFIG_HOTPLUG_CPU -/* State of each CPU during hotplug phases */ -static DEFINE_PER_CPU(int, cpu_state) = { 0 }; -#endif - struct thread_info *secondary_ti; DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); diff --git a/arch/sh/include/asm/smp.h b/arch/sh/include/asm/smp.h index 78b0d0f4..bda041e 100644 --- a/arch/sh/include/asm/smp.h +++ b/arch/sh/include/asm/smp.h @@ -31,8 +31,6 @@ enum { SMP_MSG_NR, /* must be last */ }; -DECLARE_PER_CPU(int, cpu_state); - void smp_message_recv(unsigned int msg); void smp_timer_broadcast(const struct cpumask *mask); diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c index b86e9ca..8e0fde0 100644 --- a/arch/sh/kernel/smp.c +++ b/arch/sh/kernel/smp.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -34,9 +35,6 @@ int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ struct plat_smp_ops *mp_ops = NULL; -/* State of each CPU */ -DEFINE_PER_CPU(int, cpu_state) = { 0 }; - void __cpuinit register_smp_ops(struct plat_smp_ops *ops) { if (mp_ops) diff --git a/arch/tile/kernel/smpboot.c b/arch/tile/kernel/smpboot.c index e686c5a..24a9c06 100644 --- a/arch/tile/kernel/smpboot.c +++ b/arch/tile/kernel/smpboot.c @@ -25,13 +25,11 @@ #include #include #include +#include #include #include #include -/* State of each CPU. */ -static DEFINE_PER_CPU(int, cpu_state) = { 0 }; - /* The messaging code jumps to this pointer during boot-up */ unsigned long start_cpu_function_addr; diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 4564c8e..2d0b239 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -30,8 +30,6 @@ extern int arch_register_cpu(int num); extern void arch_unregister_cpu(int); #endif -DECLARE_PER_CPU(int, cpu_state); - int mwait_usable(const struct cpuinfo_x86 *); #endif /* _ASM_X86_CPU_H */ diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index bfbe30e..269bc1f 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include @@ -73,9 +74,6 @@ #include #include -/* State of each CPU */ -DEFINE_PER_CPU(int, cpu_state) = { 0 }; - #ifdef CONFIG_HOTPLUG_CPU /* * We need this for trampoline_base protection from concurrent accesses when diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c index 2ef5948..09a7199 100644 --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include diff --git a/include/linux/smpboot.h b/include/linux/smpboot.h index 63bbedd..834d90c 100644 --- a/include/linux/smpboot.h +++ b/include/linux/smpboot.h @@ -5,6 +5,7 @@ #ifndef SMPBOOT_H #define SMPBOOT_H +DECLARE_PER_CPU(int, cpu_state); extern void smpboot_start_secondary(void *arg); #endif diff --git a/kernel/smpboot.c b/kernel/smpboot.c index 5ae1805..0df43b0 100644 --- a/kernel/smpboot.c +++ b/kernel/smpboot.c @@ -67,6 +67,8 @@ void __init idle_threads_init(void) } #endif +/* State of each CPU during bringup/teardown */ +DEFINE_PER_CPU(int, cpu_state) = { 0 }; /* Implement the following functions in your architecture, as appropriate. */ @@ -141,6 +143,8 @@ void __cpuinit smpboot_start_secondary(void *arg) set_cpu_online(cpu, true); arch_vector_unlock(); + per_cpu(cpu_state, cpu) = CPU_ONLINE; + __cpu_post_online(arg); /* Enable local interrupts now */ From ddaney.cavm@gmail.com Fri Jun 1 18:59:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Jun 2012 18:59:25 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:55388 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903608Ab2FAQ7S (ORCPT ); Fri, 1 Jun 2012 18:59:18 +0200 Received: by pbbrq13 with SMTP id rq13so3532389pbb.36 for ; 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[64.2.3.195]) by mx.google.com with ESMTPS id ua6sm3303728pbc.20.2012.06.01.09.59.08 (version=SSLv3 cipher=OTHER); Fri, 01 Jun 2012 09:59:09 -0700 (PDT) Message-ID: <4FC8F4DB.2070906@gmail.com> Date: Fri, 01 Jun 2012 09:59:07 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: "Srivatsa S. Bhat" CC: tglx@linutronix.de, peterz@infradead.org, paulmck@linux.vnet.ibm.com, rusty@rustcorp.com.au, mingo@kernel.org, yong.zhang0@gmail.com, akpm@linux-foundation.org, vatsa@linux.vnet.ibm.com, rjw@sisk.pl, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, nikunj@linux.vnet.ibm.com, Tony Luck , Fenghua Yu , Ralf Baechle , Benjamin Herrenschmidt , Paul Mundt , Chris Metcalf , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Konrad Rzeszutek Wilk , Jeremy Fitzhardinge , Peter Zijlstra , Mike Frysinger , Venkatesh Pallipadi , Suresh Siddha , linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, xen-devel@lists.xensource.com, virtualization@lists.linux-foundation.org Subject: Re: [PATCH 03/27] smpboot: Define and use cpu_state per-cpu variable in generic code References: <20120601090952.31979.24799.stgit@srivatsabhat.in.ibm.com> <20120601091038.31979.67878.stgit@srivatsabhat.in.ibm.com> In-Reply-To: <20120601091038.31979.67878.stgit@srivatsabhat.in.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 33505 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2639 Lines: 77 On 06/01/2012 02:10 AM, Srivatsa S. Bhat wrote: > The per-cpu variable cpu_state is used in x86 and also used in other > architectures, to track the state of the cpu during bringup and hotplug. > Pull it out into generic code. > > Cc: Tony Luck > Cc: Fenghua Yu > Cc: Ralf Baechle > Cc: Benjamin Herrenschmidt > Cc: Paul Mundt > Cc: Chris Metcalf > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: "H. Peter Anvin" > Cc: x86@kernel.org > Cc: Konrad Rzeszutek Wilk > Cc: Jeremy Fitzhardinge > Cc: Peter Zijlstra > Cc: Andrew Morton > Cc: Mike Frysinger > Cc: Yong Zhang > Cc: Venkatesh Pallipadi > Cc: Suresh Siddha > Cc: linux-ia64@vger.kernel.org > Cc: linux-mips@linux-mips.org > Cc: linuxppc-dev@lists.ozlabs.org > Cc: linux-sh@vger.kernel.org > Cc: xen-devel@lists.xensource.com > Cc: virtualization@lists.linux-foundation.org > Signed-off-by: Srivatsa S. Bhat > --- > > arch/ia64/include/asm/cpu.h | 2 -- > arch/ia64/kernel/process.c | 1 + > arch/ia64/kernel/smpboot.c | 6 +----- > arch/mips/cavium-octeon/smp.c | 4 +--- > arch/powerpc/kernel/smp.c | 6 +----- > arch/sh/include/asm/smp.h | 2 -- > arch/sh/kernel/smp.c | 4 +--- > arch/tile/kernel/smpboot.c | 4 +--- > arch/x86/include/asm/cpu.h | 2 -- > arch/x86/kernel/smpboot.c | 4 +--- > arch/x86/xen/smp.c | 1 + > include/linux/smpboot.h | 1 + > kernel/smpboot.c | 4 ++++ > 13 files changed, 13 insertions(+), 28 deletions(-) > [...] > diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c > index 97e7ce9..93cd4b0 100644 > --- a/arch/mips/cavium-octeon/smp.c > +++ b/arch/mips/cavium-octeon/smp.c > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -252,9 +253,6 @@ static void octeon_cpus_done(void) > > #ifdef CONFIG_HOTPLUG_CPU > > -/* State of each CPU. */ > -DEFINE_PER_CPU(int, cpu_state); > - > extern void fixup_irqs(void); > > static DEFINE_SPINLOCK(smp_reserve_lock); The Octeon bit: Acked-by: David Daney FWIW, the rest looks good too. From ralf@linux-mips.org Fri Jun 1 19:30:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Jun 2012 19:30:18 +0200 (CEST) Received: from h9.dl5rb.org.uk ([81.2.74.9]:36446 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903608Ab2FARaN (ORCPT ); Fri, 1 Jun 2012 19:30:13 +0200 Received: from h5.dl5rb.org.uk (h5.dl5rb.org.uk [127.0.0.1]) by h5.dl5rb.org.uk (8.14.5/8.14.3) with ESMTP id q51HUC9P019914 for ; Fri, 1 Jun 2012 18:30:12 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.5/8.14.5/Submit) id q51HUBaT019913 for linux-mips@linux-mips.org; Fri, 1 Jun 2012 18:30:11 +0100 Date: Fri, 1 Jun 2012 18:30:11 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Submitting patches, patchwork Message-ID: <20120601173010.GG7881@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33506 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1909 Lines: 41 As some of you have noticed I've barely merged any patches or answered emails in the past few months for personal reasons and I'm just digging myself out from the resulting skyhigh mountain of backlog I'm burried under. Many of the patches didn't get the Linus mandated soak time in linux-next much will missed the 3.5 merge window. I've worked through some of the backlog earlier this week as usual sorting everything into fixes and small bits that can go to Linus as after 3.5-rc1 will be released and the bigger, more dangerous bits that will need to soak until the merge window for 3.6 opens. This was harder by some folks resubmitting their patches, sometimes even several times unchanged from earlier submissions. I also still have thousands of unread emails. If you haven't received an answer yet, please don't take it personal. Patch submissions that were sent to linux-mips@linux-mips.org will automatically have been sucked up by patchworks. This is _the_ reason why you really want to cc the mailing list on all patch submissions. Feel free to cc to my personal address though. As long as a patch is still listed in patchwork there is no need to resubmit. But if you resubmit, please mark older versions of your patches as superseded. All this is reuired is a patchwork account. If you don't have one already creating one at http://patchwork.linux-mips.org/ will only take a minute. A single account can also handle submissions from multiple email addresses, for example from your work and a gmail address. Having patchwork know which email addresses belong to the same person helps when searching for submissions from a single person that is is going to make my life a tad easier. One last request - take care of your password for patchwork. It seems there is no facility for a user to change his own password, so only a patchwork sysadmin can replace it when it's lost. Ralf From yong.zhang0@gmail.com Sun Jun 3 10:25:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Jun 2012 10:25:44 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:62994 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903616Ab2FCIZj (ORCPT ); Sun, 3 Jun 2012 10:25:39 +0200 Received: by pbbrq13 with SMTP id rq13so5197462pbb.36 for ; Sun, 03 Jun 2012 01:25:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=J/uBad80stU0KPfYA0lW8I/VP6BYA0dr19dGkNJmjlQ=; b=Ro4Vh/IUY39fjjv896HT4kMCtl9fp5GZsQk7p/nGgjBI9gsM2uxHukLaFBAj0pS+I4 dRUi6R/haK3FBWPSuYMFFjWU/MLc68v2/UZ1Q/5HoBbtA+0qBQ+a1TnXME2bud8GAHLT 3lhfZBcG9FdP3egT/iBmtKw6Gfno16B9KWpiVj9QirszqAGjULHGK7h0mpoJkN7McqPH avQuhsTHd6FX0vCPFV6A+sFFvCyALbIkq5wQZlN0DMiS4S5j78F75aa6XTdQcqTTayBj uitB1js91N6dNPlCPmTf+XU1uQsvyWVB6x3lgBTdiJFsJv+UJMKfoAinaaj7kOLoW3w+ JxqA== Received: by 10.68.232.103 with SMTP id tn7mr27131837pbc.86.1338711931773; Sun, 03 Jun 2012 01:25:31 -0700 (PDT) Received: from localhost ([221.223.120.44]) by mx.google.com with ESMTPS id io2sm8904976pbc.24.2012.06.03.01.25.16 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 03 Jun 2012 01:25:29 -0700 (PDT) Date: Sun, 3 Jun 2012 16:25:07 +0800 From: Yong Zhang To: "Srivatsa S. Bhat" Cc: tglx@linutronix.de, peterz@infradead.org, paulmck@linux.vnet.ibm.com, rusty@rustcorp.com.au, mingo@kernel.org, akpm@linux-foundation.org, vatsa@linux.vnet.ibm.com, rjw@sisk.pl, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, nikunj@linux.vnet.ibm.com, Ralf Baechle , Eric Dumazet , Mike Frysinger , David Howells , Arun Sharma , linux-mips@linux-mips.org Subject: Re: [PATCH 10/27] mips, smpboot: Use generic SMP booting infrastructure Message-ID: <20120603082507.GA16829@zhy> Reply-To: Yong Zhang References: <20120601090952.31979.24799.stgit@srivatsabhat.in.ibm.com> <20120601091226.31979.62223.stgit@srivatsabhat.in.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20120601091226.31979.62223.stgit@srivatsabhat.in.ibm.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 33507 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang0@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5326 Lines: 171 On Fri, Jun 01, 2012 at 02:42:32PM +0530, Srivatsa S. Bhat wrote: > Convert mips to use the generic framework to boot secondary CPUs. > > Notes: > 1. The boot processor was setting the secondary cpu in cpu_online_mask! > Instead, leave it up to the secondary cpu (... and it will be done by the > generic code now). > > 2. Make the boot cpu wait for the secondary cpu to be set in cpu_online_mask > before returning. We don't need to wait for both cpu_callin_map (The code above yours) any more. > > 3. Don't enable interrupts in cmp_smp_finish() and vsmp_smp_finish(). > Do it much later, in generic code. Hmmm... the bad thing is that some board enable irq more early than ->smp_finish(), I have sent patches for that (by moving irq enable to smp_finish() and delaying smp_finish()). Please check patch#0001~patch#0004 in http://marc.info/?l=linux-mips&m=133758022710973&w=2 > > 4. In synchronise_count_slave(), use local_save_flags() instead of > local_irq_save() because irqs are still disabled. We can just remove local_irq_save()/local_irq_restore() like: http://marc.info/?l=linux-mips&m=133758046211043&w=2 Thanks, Yong > > Cc: Ralf Baechle > Cc: Andrew Morton > Cc: Eric Dumazet > Cc: Mike Frysinger > Cc: David Howells > Cc: Arun Sharma > Cc: Thomas Gleixner > Cc: Rusty Russell > Cc: linux-mips@linux-mips.org > Signed-off-by: Srivatsa S. Bhat > --- > > arch/mips/kernel/smp-cmp.c | 8 ++++---- > arch/mips/kernel/smp-mt.c | 2 -- > arch/mips/kernel/smp.c | 23 +++++++++++++++-------- > arch/mips/kernel/sync-r4k.c | 3 ++- > 4 files changed, 21 insertions(+), 15 deletions(-) > > diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c > index e7e03ec..7ecd6db 100644 > --- a/arch/mips/kernel/smp-cmp.c > +++ b/arch/mips/kernel/smp-cmp.c > @@ -108,7 +108,9 @@ static void cmp_init_secondary(void) > > static void cmp_smp_finish(void) > { > - pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__); > + unsigned int cpu = smp_processor_id(); > + > + pr_debug("SMPCMP: CPU%d: %s\n", cpu, __func__); > > /* CDFIXME: remove this? */ > write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); > @@ -116,10 +118,8 @@ static void cmp_smp_finish(void) > #ifdef CONFIG_MIPS_MT_FPAFF > /* If we have an FPU, enroll ourselves in the FPU-full mask */ > if (cpu_has_fpu) > - cpu_set(smp_processor_id(), mt_fpu_cpumask); > + cpumask_set_cpu(cpu, &mt_fpu_cpumask); > #endif /* CONFIG_MIPS_MT_FPAFF */ > - > - local_irq_enable(); > } > > static void cmp_cpus_done(void) > diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c > index ff17868..25f7b09 100644 > --- a/arch/mips/kernel/smp-mt.c > +++ b/arch/mips/kernel/smp-mt.c > @@ -171,8 +171,6 @@ static void __cpuinit vsmp_smp_finish(void) > if (cpu_has_fpu) > cpu_set(smp_processor_id(), mt_fpu_cpumask); > #endif /* CONFIG_MIPS_MT_FPAFF */ > - > - local_irq_enable(); > } > > static void vsmp_cpus_done(void) > diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c > index 71a95f5..4453d4d 100644 > --- a/arch/mips/kernel/smp.c > +++ b/arch/mips/kernel/smp.c > @@ -33,6 +33,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -98,8 +99,11 @@ __cpuinit void register_smp_ops(struct plat_smp_ops *ops) > */ > asmlinkage __cpuinit void start_secondary(void) > { > - unsigned int cpu; > + smpboot_start_secondary(NULL); > +} > > +void __cpuinit __cpu_pre_starting(void *unused) > +{ > #ifdef CONFIG_MIPS_MT_SMTC > /* Only do cpu_probe for first TC of CPU */ > if ((read_c0_tcbind() & TCBIND_CURTC) == 0) > @@ -116,20 +120,22 @@ asmlinkage __cpuinit void start_secondary(void) > */ > > calibrate_delay(); > - preempt_disable(); > - cpu = smp_processor_id(); > - cpu_data[cpu].udelay_val = loops_per_jiffy; > + cpu_data[smp_processor_id()].udelay_val = loops_per_jiffy; > +} > > - notify_cpu_starting(cpu); > +void __cpuinit __cpu_pre_online(void *unused) > +{ > + unsigned int cpu = smp_processor_id(); > > mp_ops->smp_finish(); > set_cpu_sibling_map(cpu); > > cpu_set(cpu, cpu_callin_map); > +} > > +void __cpuinit __cpu_post_online(void *unused) > +{ > synchronise_count_slave(); > - > - cpu_idle(); > } > > /* > @@ -196,7 +202,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) > while (!cpu_isset(cpu, cpu_callin_map)) > udelay(100); > > - set_cpu_online(cpu, true); > + while (!cpu_online(cpu)) > + udelay(100); > > return 0; > } > diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c > index 99f913c..7f43069 100644 > --- a/arch/mips/kernel/sync-r4k.c > +++ b/arch/mips/kernel/sync-r4k.c > @@ -46,7 +46,8 @@ void __cpuinit synchronise_count_master(void) > printk(KERN_INFO "Synchronize counters across %u CPUs: ", > num_online_cpus()); > > - local_irq_save(flags); > + /* IRQs are already disabled. So just save the flags */ > + local_save_flags(flags); > > /* > * Notify the slaves that it's time to start From srivatsa.bhat@linux.vnet.ibm.com Sun Jun 3 13:49:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Jun 2012 13:49:25 +0200 (CEST) Received: from e28smtp01.in.ibm.com ([122.248.162.1]:57793 "EHLO e28smtp01.in.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903618Ab2FCLtR (ORCPT ); Sun, 3 Jun 2012 13:49:17 +0200 Received: from /spool/local by e28smtp01.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 3 Jun 2012 17:19:09 +0530 Received: from d28relay03.in.ibm.com (9.184.220.60) by e28smtp01.in.ibm.com (192.168.1.131) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Sun, 3 Jun 2012 17:19:05 +0530 Received: from d28av04.in.ibm.com (d28av04.in.ibm.com [9.184.220.66]) by d28relay03.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q53Bn5mH11206926; Sun, 3 Jun 2012 17:19:05 +0530 Received: from d28av04.in.ibm.com (loopback [127.0.0.1]) by d28av04.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q53HIpos001301; Mon, 4 Jun 2012 03:18:52 +1000 Received: from [9.79.225.40] ([9.79.225.40]) by d28av04.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q53HIlbZ001138; Mon, 4 Jun 2012 03:18:48 +1000 Message-ID: <4FCB4F00.8080202@linux.vnet.ibm.com> Date: Sun, 03 Jun 2012 17:18:16 +0530 From: "Srivatsa S. Bhat" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:12.0) Gecko/20120424 Thunderbird/12.0 MIME-Version: 1.0 To: Yong Zhang CC: tglx@linutronix.de, peterz@infradead.org, paulmck@linux.vnet.ibm.com, rusty@rustcorp.com.au, mingo@kernel.org, akpm@linux-foundation.org, vatsa@linux.vnet.ibm.com, rjw@sisk.pl, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, nikunj@linux.vnet.ibm.com, Ralf Baechle , Eric Dumazet , Mike Frysinger , David Howells , Arun Sharma , linux-mips@linux-mips.org Subject: Re: [PATCH 10/27] mips, smpboot: Use generic SMP booting infrastructure References: <20120601090952.31979.24799.stgit@srivatsabhat.in.ibm.com> <20120601091226.31979.62223.stgit@srivatsabhat.in.ibm.com> <20120603082507.GA16829@zhy> In-Reply-To: <20120603082507.GA16829@zhy> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit x-cbid: 12060311-4790-0000-0000-0000030FA1A4 X-archive-position: 33508 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: srivatsa.bhat@linux.vnet.ibm.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1999 Lines: 58 On 06/03/2012 01:55 PM, Yong Zhang wrote: > On Fri, Jun 01, 2012 at 02:42:32PM +0530, Srivatsa S. Bhat wrote: >> Convert mips to use the generic framework to boot secondary CPUs. >> >> Notes: >> 1. The boot processor was setting the secondary cpu in cpu_online_mask! >> Instead, leave it up to the secondary cpu (... and it will be done by the >> generic code now). >> >> 2. Make the boot cpu wait for the secondary cpu to be set in cpu_online_mask >> before returning. > > We don't need to wait for both cpu_callin_map (The code above yours) > any more. Yes, I noticed that while writing the patch. But then, I thought of cleaning up the hundreds of callin/callout/commenced maps in various architectures and bringing them out into core code in a later series, and clean this up at that time.. I didn't want to do too many invasive changes all at one-shot. But I guess for this particular case of mips, I can get rid of the wait for cpu_callin_map in this patchset itself. I'll update this patch with that change. Thanks! > >> >> 3. Don't enable interrupts in cmp_smp_finish() and vsmp_smp_finish(). >> Do it much later, in generic code. > > Hmmm... the bad thing is that some board enable irq more early than > ->smp_finish(), I have sent patches for that (by moving irq enable > to smp_finish() and delaying smp_finish()). > Please check patch#0001~patch#0004 in > http://marc.info/?l=linux-mips&m=133758022710973&w=2 > >> >> 4. In synchronise_count_slave(), use local_save_flags() instead of >> local_irq_save() because irqs are still disabled. > > We can just remove local_irq_save()/local_irq_restore() like: > http://marc.info/?l=linux-mips&m=133758046211043&w=2 > So what is the status of those patches? Has anyone picked them up? I could rebase this patch on top of yours, or better yet, if your patches haven't been picked up yet, I could include them in this patchset itself to avoid too many dependencies on external patches. What do you say? Regards, Srivatsa S. Bhat From yong.zhang0@gmail.com Mon Jun 4 04:17:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Jun 2012 04:17:58 +0200 (CEST) Received: from mail-wi0-f171.google.com ([209.85.212.171]:55902 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903617Ab2FDCRy (ORCPT ); Mon, 4 Jun 2012 04:17:54 +0200 Received: by wibhm14 with SMTP id hm14so2104748wib.6 for ; Sun, 03 Jun 2012 19:17:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=kzvaYxuJPMN1bPhqJlosFC1b15P1eydXXGWWeqlcfmo=; b=ijL6vdCCB69iQB185wQ+PqtuYq2TCvQqVa+Wti/kzRj3tnJY6QvmMGwyoRSMKBeoaM uoaJRirOV2aij4lxzokHIYm3kdzMM/wSXUEDaVbFFIr3zUXj7F/so58mGo0AYLhyyu6Y elNdYoWYDJiq7lSHTpUzvzg9eWaosrFhskb80lkvEtgdTpfXfL/4FqC18Ypk0mgM3PdY aVfq6KCsBeacOfcI2bL1a4miCq26J2+67zaIhSgoXQ211PXyyGxNak2BYkZcf+zzbKhv ztOAVzZvfZD82NJ356SOw+ChD0dT29YW8TaedJ0T3H1N8uExnhGJffen3WA8HXbsWMRX 5JPg== Received: by 10.216.202.160 with SMTP id d32mr6679026weo.147.1338776268645; Sun, 03 Jun 2012 19:17:48 -0700 (PDT) Received: from localhost ([61.148.56.138]) by mx.google.com with ESMTPS id bn9sm16974537wib.5.2012.06.03.19.17.28 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 03 Jun 2012 19:17:45 -0700 (PDT) Date: Mon, 4 Jun 2012 10:17:17 +0800 From: Yong Zhang To: "Srivatsa S. Bhat" Cc: tglx@linutronix.de, peterz@infradead.org, paulmck@linux.vnet.ibm.com, rusty@rustcorp.com.au, mingo@kernel.org, akpm@linux-foundation.org, vatsa@linux.vnet.ibm.com, rjw@sisk.pl, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, nikunj@linux.vnet.ibm.com, Ralf Baechle , Eric Dumazet , Mike Frysinger , David Howells , Arun Sharma , linux-mips@linux-mips.org Subject: Re: [PATCH 10/27] mips, smpboot: Use generic SMP booting infrastructure Message-ID: <20120604021717.GA26319@zhy> Reply-To: Yong Zhang References: <20120601090952.31979.24799.stgit@srivatsabhat.in.ibm.com> <20120601091226.31979.62223.stgit@srivatsabhat.in.ibm.com> <20120603082507.GA16829@zhy> <4FCB4F00.8080202@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <4FCB4F00.8080202@linux.vnet.ibm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33509 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang0@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 970 Lines: 27 On Sun, Jun 03, 2012 at 05:18:16PM +0530, Srivatsa S. Bhat wrote: > Yes, I noticed that while writing the patch. But then, I thought of cleaning > up the hundreds of callin/callout/commenced maps in various architectures and > bringing them out into core code in a later series, and clean this up at that time.. > I didn't want to do too many invasive changes all at one-shot. OK. > But I guess for this particular case of mips, I can get rid of the wait for > cpu_callin_map in this patchset itself. I'll update this patch with that change. :-) > So what is the status of those patches? Has anyone picked them up? > > I could rebase this patch on top of yours, or better yet, if your > patches haven't been picked up yet, I could include them in this > patchset itself to avoid too many dependencies on external patches. > > What do you say? Ralf has pushed it to http://git.linux-mips.org/?p=ralf/linux.git;a=summary I guess you can see it soon. Thanks, Yong From ddaney.cavm@gmail.com Mon Jun 4 23:10:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Jun 2012 23:10:31 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:38979 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903665Ab2FDVKF (ORCPT ); Mon, 4 Jun 2012 23:10:05 +0200 Received: by dadm1 with SMTP id m1so6925575dad.36 for ; Mon, 04 Jun 2012 14:09:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=+97HaSBKoV7yMXZjC4kjeltIoRADADEYTJ7Ww31XfLc=; b=c7lSzhcIR0ybDSD8jvH+GVAtoKKDDf7CGSm3BcGc64NjwGDSLHTkbl/GqZ/Y1tO0Z9 HLkUyAaBKg7fBBvZa6aw/RezOuPXz4X9YfjbcksOK1QSzjzEk4T9hvo21co8SdP2Cyyy a6tN9fkwuAqch+tmWzNOWKcE0nQDkuDDEtm4L9slYYMMqdZj5Rz6l+Vy3BhKdwV54g0j EBwC4h/BBVpDJjKcsVo0tXoNKeZMiFddWoftkslwcGwrqSdEfPMq9hjdcENGYsYW66wb 31OZsVVxHKk5wOLoRk/+CjrGIN2BtR2d8EQzaZ0c9Ff4ojwWN0gqymJRXJ0rBU0ky96q x7gg== Received: by 10.68.193.233 with SMTP id hr9mr42694291pbc.99.1338844198280; Mon, 04 Jun 2012 14:09:58 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id jv6sm14462854pbc.40.2012.06.04.14.09.56 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 04 Jun 2012 14:09:57 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q54L9tN5019833; Mon, 4 Jun 2012 14:09:55 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q54L9sJ2019831; Mon, 4 Jun 2012 14:09:54 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: OCTEON: Remove some unused files. Date: Mon, 4 Jun 2012 14:09:53 -0700 Message-Id: <1338844193-19800-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33510 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 17268 Lines: 540 From: David Daney These FPA related files are not used anywhere in the kernel. Remove them. Signed-off-by: David Daney --- arch/mips/cavium-octeon/executive/cvmx-fpa.c | 183 --------------- .../mips/cavium-octeon/executive/cvmx-helper-fpa.c | 243 -------------------- arch/mips/include/asm/octeon/cvmx-helper-fpa.h | 64 ----- arch/mips/include/asm/octeon/cvmx-helper.h | 2 - 4 files changed, 0 insertions(+), 492 deletions(-) delete mode 100644 arch/mips/cavium-octeon/executive/cvmx-fpa.c delete mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c delete mode 100644 arch/mips/include/asm/octeon/cvmx-helper-fpa.h diff --git a/arch/mips/cavium-octeon/executive/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c deleted file mode 100644 index ad44b8b..0000000 --- a/arch/mips/cavium-octeon/executive/cvmx-fpa.c +++ /dev/null @@ -1,183 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Support library for the hardware Free Pool Allocator. - * - * - */ - -#include "cvmx-config.h" -#include "cvmx.h" -#include "cvmx-fpa.h" -#include "cvmx-ipd.h" - -/** - * Current state of all the pools. Use access functions - * instead of using it directly. - */ -CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; - -/** - * Setup a FPA pool to control a new block of memory. The - * buffer pointer must be a physical address. - * - * @pool: Pool to initialize - * 0 <= pool < 8 - * @name: Constant character string to name this pool. - * String is not copied. - * @buffer: Pointer to the block of memory to use. This must be - * accessible by all processors and external hardware. - * @block_size: Size for each block controlled by the FPA - * @num_blocks: Number of blocks - * - * Returns 0 on Success, - * -1 on failure - */ -int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, - uint64_t block_size, uint64_t num_blocks) -{ - char *ptr; - if (!buffer) { - cvmx_dprintf - ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n"); - return -1; - } - if (pool >= CVMX_FPA_NUM_POOLS) { - cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n"); - return -1; - } - - if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) { - cvmx_dprintf - ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n"); - return -1; - } - - if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) { - cvmx_dprintf - ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n"); - return -1; - } - - cvmx_fpa_pool_info[pool].name = name; - cvmx_fpa_pool_info[pool].size = block_size; - cvmx_fpa_pool_info[pool].starting_element_count = num_blocks; - cvmx_fpa_pool_info[pool].base = buffer; - - ptr = (char *)buffer; - while (num_blocks--) { - cvmx_fpa_free(ptr, pool, 0); - ptr += block_size; - } - return 0; -} - -/** - * Shutdown a Memory pool and validate that it had all of - * the buffers originally placed in it. - * - * @pool: Pool to shutdown - * Returns Zero on success - * - Positive is count of missing buffers - * - Negative is too many buffers or corrupted pointers - */ -uint64_t cvmx_fpa_shutdown_pool(uint64_t pool) -{ - uint64_t errors = 0; - uint64_t count = 0; - uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base); - uint64_t finish = - base + - cvmx_fpa_pool_info[pool].size * - cvmx_fpa_pool_info[pool].starting_element_count; - void *ptr; - uint64_t address; - - count = 0; - do { - ptr = cvmx_fpa_alloc(pool); - if (ptr) - address = cvmx_ptr_to_phys(ptr); - else - address = 0; - if (address) { - if ((address >= base) && (address < finish) && - (((address - - base) % cvmx_fpa_pool_info[pool].size) == 0)) { - count++; - } else { - cvmx_dprintf - ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n", - (unsigned long long)address, - cvmx_fpa_pool_info[pool].name, (int)pool); - errors++; - } - } - } while (address); - -#ifdef CVMX_ENABLE_PKO_FUNCTIONS - if (pool == 0) - cvmx_ipd_free_ptr(); -#endif - - if (errors) { - cvmx_dprintf - ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n", - cvmx_fpa_pool_info[pool].name, (int)pool, - (unsigned long long)base, (unsigned long long)finish, - (unsigned long long)cvmx_fpa_pool_info[pool].size); - return -errors; - } else - return 0; -} - -uint64_t cvmx_fpa_get_block_size(uint64_t pool) -{ - switch (pool) { - case 0: - return CVMX_FPA_POOL_0_SIZE; - case 1: - return CVMX_FPA_POOL_1_SIZE; - case 2: - return CVMX_FPA_POOL_2_SIZE; - case 3: - return CVMX_FPA_POOL_3_SIZE; - case 4: - return CVMX_FPA_POOL_4_SIZE; - case 5: - return CVMX_FPA_POOL_5_SIZE; - case 6: - return CVMX_FPA_POOL_6_SIZE; - case 7: - return CVMX_FPA_POOL_7_SIZE; - default: - return 0; - } -} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c deleted file mode 100644 index c239e5f..0000000 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c +++ /dev/null @@ -1,243 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Helper functions for FPA setup. - * - */ -#include "executive-config.h" -#include "cvmx-config.h" -#include "cvmx.h" -#include "cvmx-bootmem.h" -#include "cvmx-fpa.h" -#include "cvmx-helper-fpa.h" - -/** - * Allocate memory for and initialize a single FPA pool. - * - * @pool: Pool to initialize - * @buffer_size: Size of buffers to allocate in bytes - * @buffers: Number of buffers to put in the pool. Zero is allowed - * @name: String name of the pool for debugging purposes - * Returns Zero on success, non-zero on failure - */ -static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size, - uint64_t buffers, const char *name) -{ - uint64_t current_num; - void *memory; - uint64_t align = CVMX_CACHE_LINE_SIZE; - - /* - * Align the allocation so that power of 2 size buffers are - * naturally aligned. - */ - while (align < buffer_size) - align = align << 1; - - if (buffers == 0) - return 0; - - current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool)); - if (current_num) { - cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. " - "Skipping setup.\n", - pool, name, (unsigned long long)current_num); - return 0; - } - - memory = cvmx_bootmem_alloc(buffer_size * buffers, align); - if (memory == NULL) { - cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n", - pool, name); - return -1; - } - cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers); - return 0; -} - -/** - * Allocate memory and initialize the FPA pools using memory - * from cvmx-bootmem. Specifying zero for the number of - * buffers will cause that FPA pool to not be setup. This is - * useful if you aren't using some of the hardware and want - * to save memory. Use cvmx_helper_initialize_fpa instead of - * this function directly. - * - * @pip_pool: Should always be CVMX_FPA_PACKET_POOL - * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE - * @pip_buffers: - * Number of packet buffers. - * @wqe_pool: Should always be CVMX_FPA_WQE_POOL - * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE - * @wqe_entries: - * Number of work queue entries - * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL - * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - * @pko_buffers: - * PKO Command buffers. You should at minimum have two per - * each PKO queue. - * @tim_pool: Should always be CVMX_FPA_TIMER_POOL - * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE - * @tim_buffers: - * TIM ring buffer command queues. At least two per timer bucket - * is recommened. - * @dfa_pool: Should always be CVMX_FPA_DFA_POOL - * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE - * @dfa_buffers: - * DFA command buffer. A relatively small (32 for example) - * number should work. - * Returns Zero on success, non-zero if out of memory - */ -static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size, - int pip_buffers, int wqe_pool, - int wqe_size, int wqe_entries, - int pko_pool, int pko_size, - int pko_buffers, int tim_pool, - int tim_size, int tim_buffers, - int dfa_pool, int dfa_size, - int dfa_buffers) -{ - int status; - - cvmx_fpa_enable(); - - if ((pip_buffers > 0) && (pip_buffers <= 64)) - cvmx_dprintf - ("Warning: %d packet buffers may not be enough for hardware" - " prefetch. 65 or more is recommended.\n", pip_buffers); - - if (pip_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size, - pip_buffers, - "Packet Buffers"); - if (status) - return status; - } - - if (wqe_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size, - wqe_entries, - "Work Queue Entries"); - if (status) - return status; - } - - if (pko_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size, - pko_buffers, - "PKO Command Buffers"); - if (status) - return status; - } - - if (tim_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size, - tim_buffers, - "TIM Command Buffers"); - if (status) - return status; - } - - if (dfa_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size, - dfa_buffers, - "DFA Command Buffers"); - if (status) - return status; - } - - return 0; -} - -/** - * Allocate memory and initialize the FPA pools using memory - * from cvmx-bootmem. Sizes of each element in the pools is - * controlled by the cvmx-config.h header file. Specifying - * zero for any parameter will cause that FPA pool to not be - * setup. This is useful if you aren't using some of the - * hardware and want to save memory. - * - * @packet_buffers: - * Number of packet buffers to allocate - * @work_queue_entries: - * Number of work queue entries - * @pko_buffers: - * PKO Command buffers. You should at minimum have two per - * each PKO queue. - * @tim_buffers: - * TIM ring buffer command queues. At least two per timer bucket - * is recommened. - * @dfa_buffers: - * DFA command buffer. A relatively small (32 for example) - * number should work. - * Returns Zero on success, non-zero if out of memory - */ -int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries, - int pko_buffers, int tim_buffers, - int dfa_buffers) -{ -#ifndef CVMX_FPA_PACKET_POOL -#define CVMX_FPA_PACKET_POOL -1 -#define CVMX_FPA_PACKET_POOL_SIZE 0 -#endif -#ifndef CVMX_FPA_WQE_POOL -#define CVMX_FPA_WQE_POOL -1 -#define CVMX_FPA_WQE_POOL_SIZE 0 -#endif -#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL -#define CVMX_FPA_OUTPUT_BUFFER_POOL -1 -#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0 -#endif -#ifndef CVMX_FPA_TIMER_POOL -#define CVMX_FPA_TIMER_POOL -1 -#define CVMX_FPA_TIMER_POOL_SIZE 0 -#endif -#ifndef CVMX_FPA_DFA_POOL -#define CVMX_FPA_DFA_POOL -1 -#define CVMX_FPA_DFA_POOL_SIZE 0 -#endif - return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL, - CVMX_FPA_PACKET_POOL_SIZE, - packet_buffers, CVMX_FPA_WQE_POOL, - CVMX_FPA_WQE_POOL_SIZE, - work_queue_entries, - CVMX_FPA_OUTPUT_BUFFER_POOL, - CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, - pko_buffers, CVMX_FPA_TIMER_POOL, - CVMX_FPA_TIMER_POOL_SIZE, - tim_buffers, CVMX_FPA_DFA_POOL, - CVMX_FPA_DFA_POOL_SIZE, - dfa_buffers); -} diff --git a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h deleted file mode 100644 index 5ff8c93..0000000 --- a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h +++ /dev/null @@ -1,64 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Helper functions for FPA setup. - * - */ -#ifndef __CVMX_HELPER_H_FPA__ -#define __CVMX_HELPER_H_FPA__ - -/** - * Allocate memory and initialize the FPA pools using memory - * from cvmx-bootmem. Sizes of each element in the pools is - * controlled by the cvmx-config.h header file. Specifying - * zero for any parameter will cause that FPA pool to not be - * setup. This is useful if you aren't using some of the - * hardware and want to save memory. - * - * @packet_buffers: - * Number of packet buffers to allocate - * @work_queue_entries: - * Number of work queue entries - * @pko_buffers: - * PKO Command buffers. You should at minimum have two per - * each PKO queue. - * @tim_buffers: - * TIM ring buffer command queues. At least two per timer bucket - * is recommened. - * @dfa_buffers: - * DFA command buffer. A relatively small (32 for example) - * number should work. - * Returns Zero on success, non-zero if out of memory - */ -extern int cvmx_helper_initialize_fpa(int packet_buffers, - int work_queue_entries, int pko_buffers, - int tim_buffers, int dfa_buffers); - -#endif /* __CVMX_HELPER_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h index 3169cd7..0ac6b9f 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper.h +++ b/arch/mips/include/asm/octeon/cvmx-helper.h @@ -61,8 +61,6 @@ typedef union { } s; } cvmx_helper_link_info_t; -#include "cvmx-helper-fpa.h" - #include #include "cvmx-helper-loop.h" #include "cvmx-helper-npi.h" -- 1.7.2.3 From florian@openwrt.org Tue Jun 5 11:57:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 11:57:51 +0200 (CEST) Received: from mail-ee0-f49.google.com ([74.125.83.49]:38714 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903703Ab2FEJ5r (ORCPT ); Tue, 5 Jun 2012 11:57:47 +0200 Received: by eekd17 with SMTP id d17so2500809eek.36 for ; Tue, 05 Jun 2012 02:57:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:user-agent:in-reply-to :references:mime-version:content-transfer-encoding:content-type; bh=7B1oJytCIBqJiDjZAVKybQ58dY7YTtqzU5yfDDT1OsA=; b=Sa55akxv/WAvigo+l3ik6yf95xcKhceetxw4GsBNIErGpTPwv/AdhlzuiWFIJ/mmMU bVvwlEUWFgphTa5L4hAw8nQgsbeDqpXK9zt88a5mYTu3f2uAL3Z7qwsHyzl+hyblwaFn wAwH2XbJ7KIj4yXlhTjqvk/QMhJCGPufgPB9d10XPs2nkEs5M2eEF54U51XyjJ4PVM/P P27yB19H+bDnK5WhkeoNOFSicBn+qqqOc1eySFwH9wbnUUMmDQhJX84NfiaLIravFwTW W/E+6ZuAcIs/r5B2ShQXA5GO1gF2w6vRR0LEHXwwLpdVOe5fN5fv253lAD8cciTlIFc1 H7BA== Received: by 10.14.96.8 with SMTP id q8mr6188823eef.203.1338890261416; Tue, 05 Jun 2012 02:57:41 -0700 (PDT) Received: from flexo.localnet ([2a01:e34:ec0d:4090:daa:5a0b:38c8:54be]) by mx.google.com with ESMTPS id p41sm4140997eef.5.2012.06.05.02.57.37 (version=SSLv3 cipher=OTHER); Tue, 05 Jun 2012 02:57:37 -0700 (PDT) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] MIPS: BCM63XX: be consistent in clock bits enable naming Date: Tue, 05 Jun 2012 11:55:26 +0200 Message-ID: <1470070.RaZQ4a8ogE@flexo> User-Agent: KMail/4.8.3 (Linux/3.2.0-24-generic; KDE/4.8.3; x86_64; ; ) In-Reply-To: <1328018888-5533-3-git-send-email-florian@openwrt.org> References: <1328018888-5533-1-git-send-email-florian@openwrt.org> <1328018888-5533-3-git-send-email-florian@openwrt.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-archive-position: 33511 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4109 Lines: 115 Hi Ralf, On Tuesday 31 January 2012 15:08:08 Florian Fainelli wrote: > Remove the _CLK suffix from the BCM6368 clock bits definitions to be > consistent with what is already present. > > Signed-off-by: Florian Fainelli This patch is a prerequisite for BCM63xx's SPI support, and should be applied to your master tree in order to fix the following build failure, the patch applies cleanly to your master tree. arch/mips/bcm63xx/clk.c: In function 'spi_set': arch/mips/bcm63xx/clk.c:188:10: error: 'CKCTL_6368_SPI_EN' undeclared (first use in this function) arch/mips/bcm63xx/clk.c:188:10: note: each undeclared identifier is reported only once for each function it appears in make[2]: *** [arch/mips/bcm63xx/clk.o] Error 1 Thanks! > --- > arch/mips/bcm63xx/clk.c | 6 ++-- > arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 36 ++++++++++---------- > 2 files changed, 21 insertions(+), 21 deletions(-) > > diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c > index 9d57c71..8d2ea22 100644 > --- a/arch/mips/bcm63xx/clk.c > +++ b/arch/mips/bcm63xx/clk.c > @@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk, int enable) > { > if (!BCMCPU_IS_6368()) > return; > - bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN | > + bcm_hwclock_set(CKCTL_6368_ROBOSW_EN | > CKCTL_6368_SWPKT_USB_EN | > CKCTL_6368_SWPKT_SAR_EN, enable); > if (enable) { > @@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, int enable) > if (BCMCPU_IS_6348()) > bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); > else if (BCMCPU_IS_6368()) > - bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable); > + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); > } > > static struct clk clk_usbh = { > @@ -199,7 +199,7 @@ static void xtm_set(struct clk *clk, int enable) > if (!BCMCPU_IS_6368()) > return; > > - bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN | > + bcm_hwclock_set(CKCTL_6368_SAR_EN | > CKCTL_6368_SWPKT_SAR_EN, enable); > > if (enable) { > diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h > index 94d4faa..6ddd081 100644 > --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h > +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h > @@ -90,29 +90,29 @@ > #define CKCTL_6368_PHYMIPS_EN (1 << 6) > #define CKCTL_6368_SWPKT_USB_EN (1 << 7) > #define CKCTL_6368_SWPKT_SAR_EN (1 << 8) > -#define CKCTL_6368_SPI_CLK_EN (1 << 9) > -#define CKCTL_6368_USBD_CLK_EN (1 << 10) > -#define CKCTL_6368_SAR_CLK_EN (1 << 11) > -#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12) > -#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13) > -#define CKCTL_6368_PCM_CLK_EN (1 << 14) > -#define CKCTL_6368_USBH_CLK_EN (1 << 15) > +#define CKCTL_6368_SPI_EN (1 << 9) > +#define CKCTL_6368_USBD_EN (1 << 10) > +#define CKCTL_6368_SAR_EN (1 << 11) > +#define CKCTL_6368_ROBOSW_EN (1 << 12) > +#define CKCTL_6368_UTOPIA_EN (1 << 13) > +#define CKCTL_6368_PCM_EN (1 << 14) > +#define CKCTL_6368_USBH_EN (1 << 15) > #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) > -#define CKCTL_6368_NAND_CLK_EN (1 << 17) > -#define CKCTL_6368_IPSEC_CLK_EN (1 << 17) > +#define CKCTL_6368_NAND_EN (1 << 17) > +#define CKCTL_6368_IPSEC_EN (1 << 17) > > #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ > CKCTL_6368_SWPKT_SAR_EN | \ > - CKCTL_6368_SPI_CLK_EN | \ > - CKCTL_6368_USBD_CLK_EN | \ > - CKCTL_6368_SAR_CLK_EN | \ > - CKCTL_6368_ROBOSW_CLK_EN | \ > - CKCTL_6368_UTOPIA_CLK_EN | \ > - CKCTL_6368_PCM_CLK_EN | \ > - CKCTL_6368_USBH_CLK_EN | \ > + CKCTL_6368_SPI_EN | \ > + CKCTL_6368_USBD_EN | \ > + CKCTL_6368_SAR_EN | \ > + CKCTL_6368_ROBOSW_EN | \ > + CKCTL_6368_UTOPIA_EN | \ > + CKCTL_6368_PCM_EN | \ > + CKCTL_6368_USBH_EN | \ > CKCTL_6368_DISABLE_GLESS_EN | \ > - CKCTL_6368_NAND_CLK_EN | \ > - CKCTL_6368_IPSEC_CLK_EN) > + CKCTL_6368_NAND_EN | \ > + CKCTL_6368_IPSEC_EN) > > /* System PLL Control register */ > #define PERF_SYS_PLL_CTL_REG 0x8 > -- > 1.7.5.4 > From jfaulkne@ccs.neu.edu Tue Jun 5 21:00:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 21:00:58 +0200 (CEST) Received: from amber.ccs.neu.edu ([129.10.116.51]:41472 "EHLO amber.ccs.neu.edu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903721Ab2FETAu (ORCPT ); Tue, 5 Jun 2012 21:00:50 +0200 Received: from alumni-linux.ccs.neu.edu ([129.10.116.115]) by amber.ccs.neu.edu with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1Sbyzo-0003Z9-0J for linux-mips@linux-mips.org; Tue, 05 Jun 2012 15:00:48 -0400 Received: from jfaulkne by alumni-linux.ccs.neu.edu with local (Exim 4.69) (envelope-from ) id 1Sbyzn-0001kg-UG for linux-mips@linux-mips.org; Tue, 05 Jun 2012 15:00:47 -0400 Date: Tue, 5 Jun 2012 15:00:47 -0400 From: Jim Faulkner To: linux-mips@linux-mips.org Subject: booting linux-3.3 or linux 3.4 on an SGI O2? Message-ID: <20120605190047.GA6263@alumni-linux.ccs.neu.edu> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="J2SCkAp4GZ/dPZZf" Content-Disposition: inline X-archive-position: 33512 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jfaulkne@ccs.neu.edu Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 46993 Lines: 1908 --J2SCkAp4GZ/dPZZf Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Hi all, I haven't been able to boot any kernels after linux 3.2 on my SGI O2. I've tried linux-3.3.5 and linux-3.4.0, but neither would boot. Unfortunately I don't have further information such as a kernel panic, since I don't get any video output after the kernel is loaded. I've attached my linux-3.4 .config. Anybody know what patches I might need to get the latest kernels booting on this system? --J2SCkAp4GZ/dPZZf Content-Type: text/plain; charset=utf-8 Content-Disposition: attachment; filename="sgi_o2_linux_3.4.config" # # Automatically generated file; DO NOT EDIT. # Linux/mips 3.4.0 Kernel Configuration # CONFIG_MIPS=y # # Machine selection # # CONFIG_MIPS_ALCHEMY is not set # CONFIG_AR7 is not set # CONFIG_ATH79 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MACH_JZ4740 is not set # CONFIG_LANTIQ is not set # CONFIG_LASAT is not set # CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set # CONFIG_NXP_STB220 is not set # CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set CONFIG_SGI_IP32=y # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_MACH_TX39XX is not set # CONFIG_MACH_TX49XX is not set # CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set # CONFIG_NLM_XLR_BOARD is not set # CONFIG_NLM_XLP_BOARD is not set # CONFIG_ALCHEMY_GPIO_INDIRECT is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_ARC=y CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y CONFIG_CSRC_R4K_LIB=y CONFIG_CSRC_R4K=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_DMA_NONCOHERENT=y CONFIG_NEED_DMA_MAP_STATE=y # CONFIG_MIPS_MACHINE is not set # CONFIG_NO_IOPORT is not set CONFIG_CPU_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_ARC32=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 CONFIG_ARC_MEMORY=y CONFIG_ARC_PROMLIB=y # # CPU selection # # CONFIG_CPU_R4X00 is not set CONFIG_CPU_R5000=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_RM7000 is not set CONFIG_SYS_HAS_CPU_R5000=y CONFIG_SYS_HAS_CPU_NEVADA=y CONFIG_SYS_HAS_CPU_RM7000=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y # # Kernel type # # CONFIG_32BIT is not set CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_BOARD_SCACHE=y CONFIG_R5000_CPU_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_CPU_HAS_SYNC=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_HAVE_MEMBLOCK=y CONFIG_HAVE_MEMBLOCK_NODE_MAP=y CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_COMPACTION is not set CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_NEED_PER_CPU_KM=y CONFIG_CLEANCACHE=y CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_HZ_48=y # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_256 is not set # CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_HZ=48 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set CONFIG_SECCOMP=y CONFIG_USE_OF=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_HAVE_IRQ_WORK=y # # General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_CROSS_COMPILE="" CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y # CONFIG_FHANDLE is not set # CONFIG_TASKSTATS is not set CONFIG_AUDIT=y # CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set CONFIG_HAVE_GENERIC_HARDIRQS=y # # IRQ subsystem # CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y # # RCU Subsystem # CONFIG_TINY_RCU=y # CONFIG_PREEMPT_RCU is not set # CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 # CONFIG_CGROUPS is not set # CONFIG_CHECKPOINT_RESTORE is not set CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_IPC_NS is not set # CONFIG_USER_NS is not set # CONFIG_PID_NS is not set # CONFIG_NET_NS is not set # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y # CONFIG_EXPERT is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # # CONFIG_PERF_EVENTS is not set # CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_COMPAT_BRK is not set # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y CONFIG_HAVE_SYSCALL_WRAPPERS=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y # # GCOV-based kernel profiling # CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y # # Partition Types # CONFIG_PARTITION_ADVANCED=y # CONFIG_ACORN_PARTITION is not set CONFIG_OSF_PARTITION=y # CONFIG_AMIGA_PARTITION is not set # CONFIG_ATARI_PARTITION is not set CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y CONFIG_BSD_DISKLABEL=y # CONFIG_MINIX_SUBPARTITION is not set CONFIG_SOLARIS_X86_PARTITION=y # CONFIG_UNIXWARE_DISKLABEL is not set CONFIG_LDM_PARTITION=y # CONFIG_LDM_DEBUG is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set CONFIG_SUN_PARTITION=y # CONFIG_KARMA_PARTITION is not set CONFIG_EFI_PARTITION=y # CONFIG_SYSV68_PARTITION is not set CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_DEADLINE=m CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_INLINE_SPIN_TRYLOCK is not set # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK is not set # CONFIG_INLINE_SPIN_LOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK_IRQ is not set # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set # CONFIG_INLINE_SPIN_UNLOCK_BH is not set CONFIG_INLINE_SPIN_UNLOCK_IRQ=y # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set # CONFIG_INLINE_READ_TRYLOCK is not set # CONFIG_INLINE_READ_LOCK is not set # CONFIG_INLINE_READ_LOCK_BH is not set # CONFIG_INLINE_READ_LOCK_IRQ is not set # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set CONFIG_INLINE_READ_UNLOCK=y # CONFIG_INLINE_READ_UNLOCK_BH is not set CONFIG_INLINE_READ_UNLOCK_IRQ=y # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set # CONFIG_INLINE_WRITE_TRYLOCK is not set # CONFIG_INLINE_WRITE_LOCK is not set # CONFIG_INLINE_WRITE_LOCK_BH is not set # CONFIG_INLINE_WRITE_LOCK_IRQ is not set # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set CONFIG_INLINE_WRITE_UNLOCK=y # CONFIG_INLINE_WRITE_UNLOCK_BH is not set CONFIG_INLINE_WRITE_UNLOCK_IRQ=y # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set # CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set # CONFIG_PCI_STUB is not set # CONFIG_PCI_IOV is not set # CONFIG_PCI_PRI is not set # CONFIG_PCI_PASID is not set CONFIG_MMU=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_RAPIDIO is not set # # Executable file formats # CONFIG_BINFMT_ELF=y CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y CONFIG_BINFMT_ELF32=y # # Power management options # CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_SUSPEND is not set # CONFIG_HIBERNATION is not set CONFIG_PM_RUNTIME=y CONFIG_PM=y # CONFIG_PM_DEBUG is not set CONFIG_NET=y # # Networking options # CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_UNIX_DIAG=m CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=m # CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set CONFIG_IP_ADVANCED_ROUTER=y # CONFIG_IP_FIB_TRIE_STATS is not set # CONFIG_IP_MULTIPLE_TABLES is not set # CONFIG_IP_ROUTE_MULTIPATH is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_ROUTE_CLASSID=y # CONFIG_IP_PNP is not set CONFIG_NET_IPIP=m CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m # CONFIG_ARPD is not set CONFIG_SYN_COOKIES=y CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_TUNNEL=m CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m CONFIG_INET_LRO=m CONFIG_INET_DIAG=m CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m CONFIG_INET6_XFRM_TUNNEL=m CONFIG_INET6_TUNNEL=m CONFIG_INET6_XFRM_MODE_TRANSPORT=m CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m CONFIG_IPV6_SIT=m # CONFIG_IPV6_SIT_6RD is not set CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m # CONFIG_IPV6_MULTIPLE_TABLES is not set # CONFIG_IPV6_MROUTE is not set # CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=y # # Core Netfilter Configuration # CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_NETLINK_ACCT=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CONNTRACK_TIMEOUT=y CONFIG_NF_CONNTRACK_TIMESTAMP=y CONFIG_NF_CT_PROTO_DCCP=m CONFIG_NF_CT_PROTO_GRE=m CONFIG_NF_CT_PROTO_SCTP=m CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_BROADCAST=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m CONFIG_NF_CT_NETLINK_TIMEOUT=m CONFIG_NETFILTER_TPROXY=m CONFIG_NETFILTER_XTABLES=m # # Xtables combined modules # CONFIG_NETFILTER_XT_MARK=m CONFIG_NETFILTER_XT_CONNMARK=m CONFIG_NETFILTER_XT_SET=m # # Xtables targets # CONFIG_NETFILTER_XT_TARGET_AUDIT=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_HL=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m # # Xtables matches # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_CPU=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ECN=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_HL=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_NFACCT=m CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m CONFIG_IP_SET=m CONFIG_IP_SET_MAX=256 CONFIG_IP_SET_BITMAP_IP=m CONFIG_IP_SET_BITMAP_IPMAC=m CONFIG_IP_SET_BITMAP_PORT=m CONFIG_IP_SET_HASH_IP=m CONFIG_IP_SET_HASH_IPPORT=m CONFIG_IP_SET_HASH_IPPORTIP=m CONFIG_IP_SET_HASH_IPPORTNET=m CONFIG_IP_SET_HASH_NET=m CONFIG_IP_SET_HASH_NETPORT=m CONFIG_IP_SET_HASH_NETIFACE=m CONFIG_IP_SET_LIST_SET=m # CONFIG_IP_VS is not set # # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m # CONFIG_NF_CONNTRACK_PROC_COMPAT is not set # CONFIG_IP_NF_QUEUE is not set CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_DCCP=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m CONFIG_NF_NAT_PROTO_SCTP=m CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_IRC=m CONFIG_NF_NAT_TFTP=m CONFIG_NF_NAT_AMANDA=m CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # # IPv6: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV6=m CONFIG_NF_CONNTRACK_IPV6=m # CONFIG_IP6_NF_QUEUE is not set CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_SECURITY=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m CONFIG_BRIDGE_EBT_IP=m CONFIG_BRIDGE_EBT_IP6=m CONFIG_BRIDGE_EBT_LIMIT=m CONFIG_BRIDGE_EBT_MARK=m CONFIG_BRIDGE_EBT_PKTTYPE=m CONFIG_BRIDGE_EBT_STP=m CONFIG_BRIDGE_EBT_VLAN=m CONFIG_BRIDGE_EBT_ARPREPLY=m CONFIG_BRIDGE_EBT_DNAT=m CONFIG_BRIDGE_EBT_MARK_T=m CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m CONFIG_BRIDGE_EBT_NFLOG=m # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_L2TP is not set CONFIG_STP=m CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_DECNET is not set CONFIG_LLC=m # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y # CONFIG_BATMAN_ADV is not set # CONFIG_OPENVSWITCH is not set CONFIG_BQL=y # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set # CONFIG_WIRELESS is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set # CONFIG_NFC is not set # # Device Drivers # # # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_FW_LOADER=y # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_GENERIC_CPU_DEVICES is not set # CONFIG_DMA_SHARED_BUFFER is not set CONFIG_CONNECTOR=m # CONFIG_MTD is not set CONFIG_DTC=y CONFIG_OF=y # # Device Tree and Open Firmware support # CONFIG_PROC_DEVICETREE=y # CONFIG_OF_SELFTEST is not set CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_DEVICE=y CONFIG_OF_NET=y CONFIG_OF_MDIO=m CONFIG_OF_PCI=y CONFIG_OF_PCI_IRQ=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_NVME is not set # CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set # CONFIG_BLK_DEV_RBD is not set # # Misc devices # # CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_PHANTOM is not set # CONFIG_INTEL_MID_PTI is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set # CONFIG_PCH_PHUB is not set # CONFIG_C2PORT is not set # # EEPROM support # # CONFIG_EEPROM_93CX6 is not set # CONFIG_CB710_CORE is not set # # Texas Instruments shared transport line discipline # # # Altera FPGA firmware download module # CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # # SCSI device support # CONFIG_SCSI_MOD=y CONFIG_RAID_ATTRS=m CONFIG_SCSI=y CONFIG_SCSI_DMA=y CONFIG_SCSI_TGT=m # CONFIG_SCSI_NETLINK is not set # CONFIG_SCSI_PROC_FS is not set # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m # CONFIG_CHR_DEV_OSST is not set CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_FC_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=m # CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=m # CONFIG_ISCSI_BOOT_SYSFS is not set # CONFIG_SCSI_CXGB3_ISCSI is not set # CONFIG_SCSI_CXGB4_ISCSI is not set # CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_SCSI_BNX2X_FCOE is not set # CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_HPSA is not set # CONFIG_SCSI_3W_9XXX is not set # CONFIG_SCSI_3W_SAS is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set CONFIG_SCSI_AIC7XXX=y CONFIG_AIC7XXX_CMDS_PER_DEVICE=253 CONFIG_AIC7XXX_RESET_DELAY_MS=12000 # CONFIG_AIC7XXX_BUILD_FIRMWARE is not set # CONFIG_AIC7XXX_DEBUG_ENABLE is not set CONFIG_AIC7XXX_DEBUG_MASK=0 # CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set # CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_MVUMI is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_MPT2SAS is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_HPTIOP is not set # CONFIG_LIBFC is not set # CONFIG_LIBFCOE is not set # CONFIG_FCOE is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_QLOGIC_1280 is not set # CONFIG_SCSI_QLA_FC is not set # CONFIG_SCSI_QLA_ISCSI is not set # CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set # CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_BFA_FC is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=m # CONFIG_MD_LINEAR is not set CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m # CONFIG_MD_RAID10 is not set CONFIG_MD_RAID456=m # CONFIG_MD_MULTIPATH is not set # CONFIG_MD_FAULTY is not set CONFIG_BLK_DEV_DM=m # CONFIG_DM_DEBUG is not set CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m # CONFIG_DM_THIN_PROVISIONING is not set CONFIG_DM_MIRROR=m CONFIG_DM_RAID=m # CONFIG_DM_LOG_USERSPACE is not set CONFIG_DM_ZERO=m # CONFIG_DM_MULTIPATH is not set # CONFIG_DM_DELAY is not set CONFIG_DM_UEVENT=y # CONFIG_DM_FLAKEY is not set # CONFIG_DM_VERITY is not set # CONFIG_TARGET_CORE is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # # CONFIG_FIREWIRE is not set # CONFIG_FIREWIRE_NOSY is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y CONFIG_NET_CORE=y CONFIG_BONDING=m # CONFIG_DUMMY is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set CONFIG_MII=m CONFIG_NET_TEAM=m CONFIG_NET_TEAM_MODE_ROUNDROBIN=m CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m CONFIG_MACVLAN=m CONFIG_MACVTAP=m # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set CONFIG_TUN=m CONFIG_VETH=m # CONFIG_ARCNET is not set # # CAIF transport drivers # CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_ADAPTEC is not set # CONFIG_NET_VENDOR_ALTEON is not set # CONFIG_NET_VENDOR_AMD is not set # CONFIG_NET_VENDOR_ATHEROS is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_CALXEDA_XGMAC is not set # CONFIG_NET_VENDOR_CHELSIO is not set # CONFIG_NET_VENDOR_CISCO is not set # CONFIG_DM9000 is not set # CONFIG_DNET is not set # CONFIG_NET_VENDOR_DEC is not set # CONFIG_NET_VENDOR_DLINK is not set # CONFIG_NET_VENDOR_EMULEX is not set # CONFIG_NET_VENDOR_EXAR is not set # CONFIG_NET_VENDOR_HP is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_IP1000 is not set # CONFIG_JME is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MYRI is not set # CONFIG_FEALNX is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NVIDIA is not set # CONFIG_NET_VENDOR_OKI is not set # CONFIG_ETHOC is not set # CONFIG_NET_PACKET_ENGINE is not set # CONFIG_NET_VENDOR_QLOGIC is not set # CONFIG_NET_VENDOR_REALTEK is not set # CONFIG_NET_VENDOR_RDC is not set # CONFIG_NET_VENDOR_SEEQ is not set # CONFIG_NET_VENDOR_SILAN is not set # CONFIG_NET_VENDOR_SIS is not set # CONFIG_SFC is not set CONFIG_NET_VENDOR_SGI=y CONFIG_SGI_O2MACE_ETH=y # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_SUN is not set # CONFIG_NET_VENDOR_TEHUTI is not set # CONFIG_NET_VENDOR_TI is not set # CONFIG_NET_VENDOR_TOSHIBA is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set CONFIG_PHYLIB=m # # MII PHY device drivers # CONFIG_AMD_PHY=m CONFIG_MARVELL_PHY=m CONFIG_DAVICOM_PHY=m CONFIG_QSEMI_PHY=m CONFIG_LXT_PHY=m CONFIG_CICADA_PHY=m CONFIG_VITESSE_PHY=m CONFIG_SMSC_PHY=m CONFIG_BROADCOM_PHY=m CONFIG_ICPLUS_PHY=m CONFIG_REALTEK_PHY=m CONFIG_NATIONAL_PHY=m CONFIG_STE10XP=m CONFIG_LSI_ET1011C_PHY=m CONFIG_MICREL_PHY=m CONFIG_MDIO_BITBANG=m CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_DEFLATE=m CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m # CONFIG_PPP_MULTILINK is not set CONFIG_PPPOE=m CONFIG_PPTP=m CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m # CONFIG_SLIP is not set CONFIG_SLHC=m # CONFIG_TR is not set # CONFIG_WLAN is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers # # CONFIG_WAN is not set # CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # # Input device support # CONFIG_INPUT=y CONFIG_INPUT_FF_MEMLESS=m CONFIG_INPUT_POLLDEV=y CONFIG_INPUT_SPARSEKMAP=m # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=m # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_OMAP4 is not set # CONFIG_KEYBOARD_XTKBD is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_SENTELIC is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set CONFIG_INPUT_UINPUT=m CONFIG_INPUT_SGI_BTNS=y # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_CMA3000 is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_I8042=y CONFIG_SERIO_SERPORT=m # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_MACEPS2=y CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_SERIO_PS2MULT is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set # CONFIG_N_GSM is not set # CONFIG_TRACE_SINK is not set # CONFIG_DEVKMEM is not set # # Serial drivers # CONFIG_SERIAL_8250=m CONFIG_SERIAL_8250_PCI=m CONFIG_SERIAL_8250_NR_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 # CONFIG_SERIAL_8250_EXTENDED is not set # CONFIG_SERIAL_8250_DW is not set # # Non-8250 serial port support # # CONFIG_SERIAL_MFD_HSU is not set CONFIG_SERIAL_CORE=m # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set # CONFIG_SERIAL_TIMBERDALE is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_PCH_UART is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=m CONFIG_HW_RANDOM_TIMERIOMEM=m # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_RAMOOPS is not set # CONFIG_I2C is not set # CONFIG_SPI is not set # CONFIG_HSI is not set # # PPS support # # CONFIG_PPS is not set # # PPS generators support # # # PTP clock support # # # Enable Device Drivers -> PPS to see the PTP clock options. # # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # # CONFIG_SSB is not set CONFIG_BCMA_POSSIBLE=y # # Broadcom specific AMBA # # CONFIG_BCMA is not set # # Multifunction device drivers # CONFIG_MFD_CORE=m # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set # CONFIG_ABX500_CORE is not set CONFIG_LPC_SCH=m # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_VX855 is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=1 # CONFIG_DRM is not set # CONFIG_STUB_POULSBO is not set # CONFIG_VGASTATE is not set CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_FB=y CONFIG_FIRMWARE_EDID=y # CONFIG_FB_DDC is not set # CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set # CONFIG_FB_SYS_FILLRECT is not set # CONFIG_FB_SYS_COPYAREA is not set # CONFIG_FB_SYS_IMAGEBLIT is not set # CONFIG_FB_FOREIGN_ENDIAN is not set # CONFIG_FB_SYS_FOPS is not set # CONFIG_FB_WMT_GE_ROPS is not set # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set # # Frame buffer hardware drivers # # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set # CONFIG_FB_UVESA is not set CONFIG_FB_GBE=y CONFIG_FB_GBE_MEM=4 # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_I740 is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON is not set # CONFIG_FB_ATY128 is not set # CONFIG_FB_ATY is not set # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set # CONFIG_FB_VT8623 is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set # CONFIG_FB_TMIO is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set # CONFIG_EXYNOS_VIDEO is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=m CONFIG_LCD_PLATFORM=m CONFIG_BACKLIGHT_CLASS_DEVICE=m CONFIG_BACKLIGHT_GENERIC=m # # Console display driver support # CONFIG_VGA_CONSOLE=y CONFIG_VGACON_SOFT_SCROLLBACK=y CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set CONFIG_FONTS=y # CONFIG_FONT_8x8 is not set CONFIG_FONT_8x16=y # CONFIG_FONT_6x11 is not set # CONFIG_FONT_7x14 is not set # CONFIG_FONT_PEARL_8x8 is not set # CONFIG_FONT_ACORN_8x8 is not set # CONFIG_FONT_MINI_4x6 is not set # CONFIG_FONT_SUN8x16 is not set # CONFIG_FONT_SUN12x22 is not set # CONFIG_FONT_10x18 is not set CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_LOGO_LINUX_CLUT224 is not set CONFIG_LOGO_SGI_CLUT224=y # CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB_ARCH_HAS_XHCI=y # CONFIG_USB_SUPPORT is not set # CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m # # LED drivers # # CONFIG_LEDS_OT200 is not set CONFIG_LEDS_TRIGGERS=y # # LED Triggers # CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m CONFIG_LEDS_TRIGGER_BACKLIGHT=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m # # iptables trigger is under Netfilter config (LED target) # # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set # CONFIG_RTC_DEBUG is not set # # RTC interfaces # CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set # CONFIG_RTC_DRV_TEST is not set # # SPI RTC drivers # # # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=m CONFIG_RTC_DRV_DS1286=m CONFIG_RTC_DRV_DS1511=m CONFIG_RTC_DRV_DS1553=m CONFIG_RTC_DRV_DS1742=m CONFIG_RTC_DRV_STK17TA8=m CONFIG_RTC_DRV_M48T86=m CONFIG_RTC_DRV_M48T35=m CONFIG_RTC_DRV_M48T59=m CONFIG_RTC_DRV_MSM6242=m CONFIG_RTC_DRV_BQ4802=m CONFIG_RTC_DRV_RP5C01=m CONFIG_RTC_DRV_V3020=m # # on-CPU RTC drivers # CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set # # DMA Devices # CONFIG_TIMB_DMA=m CONFIG_DMA_ENGINE=y # # DMA Clients # CONFIG_NET_DMA=y # CONFIG_ASYNC_TX_DMA is not set # CONFIG_DMATEST is not set # CONFIG_AUXDISPLAY is not set CONFIG_UIO=m # CONFIG_UIO_CIF is not set # CONFIG_UIO_PDRV is not set # CONFIG_UIO_PDRV_GENIRQ is not set # CONFIG_UIO_AEC is not set # CONFIG_UIO_SERCOS3 is not set # CONFIG_UIO_PCI_GENERIC is not set # CONFIG_UIO_NETX is not set # # Virtio drivers # # CONFIG_VIRTIO_PCI is not set # CONFIG_VIRTIO_BALLOON is not set # CONFIG_VIRTIO_MMIO is not set # # Microsoft Hyper-V guest support # # CONFIG_STAGING is not set # # Hardware Spinlock drivers # CONFIG_IOMMU_SUPPORT=y # # Remoteproc drivers (EXPERIMENTAL) # # # Rpmsg drivers (EXPERIMENTAL) # # CONFIG_VIRT_DRIVERS is not set # CONFIG_PM_DEVFREQ is not set # # File systems # CONFIG_EXT2_FS=m # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=m # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set CONFIG_EXT4_FS=y # CONFIG_EXT4_FS_XATTR is not set # CONFIG_EXT4_DEBUG is not set CONFIG_JBD=m CONFIG_JBD2=y CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set # CONFIG_REISERFS_FS_XATTR is not set CONFIG_JFS_FS=m # CONFIG_JFS_POSIX_ACL is not set # CONFIG_JFS_SECURITY is not set # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set # CONFIG_XFS_RT is not set # CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_BTRFS_FS=m # CONFIG_BTRFS_FS_POSIX_ACL is not set # CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_NILFS2_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=m CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y # CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set # CONFIG_QUOTA is not set # CONFIG_QUOTACTL is not set CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m CONFIG_CUSE=m CONFIG_GENERIC_ACL=y # # Caches # CONFIG_FSCACHE=m # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set # CONFIG_FSCACHE_OBJECT_LIST is not set CONFIG_CACHEFILES=m # CONFIG_CACHEFILES_DEBUG is not set # CONFIG_CACHEFILES_HISTOGRAM is not set # # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=m CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m CONFIG_UDF_NLS=y # # DOS/FAT/NT Filesystems # CONFIG_FAT_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y # CONFIG_HUGETLB_PAGE is not set CONFIG_CONFIGFS_FS=m CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set CONFIG_EFS_FS=y # CONFIG_LOGFS is not set # CONFIG_CRAMFS is not set # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_MINIX_FS_NATIVE_ENDIAN is not set # CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_PSTORE is not set # CONFIG_SYSV_FS is not set CONFIG_UFS_FS=m # CONFIG_UFS_FS_WRITE is not set # CONFIG_UFS_DEBUG is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y # CONFIG_NFS_V4_1 is not set CONFIG_NFS_FSCACHE=y # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y # CONFIG_NFSD_V3_ACL is not set CONFIG_NFSD_V4=y # CONFIG_NFSD_FAULT_INJECTION is not set CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set CONFIG_CIFS=m # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_UPCALL is not set CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y # CONFIG_CIFS_DEBUG2 is not set # CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_CIFS_FSCACHE is not set # CONFIG_CIFS_ACL is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=m CONFIG_NLS_DEFAULT="utf-8" CONFIG_NLS_CODEPAGE_437=m # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_852 is not set # CONFIG_NLS_CODEPAGE_855 is not set # CONFIG_NLS_CODEPAGE_857 is not set # CONFIG_NLS_CODEPAGE_860 is not set # CONFIG_NLS_CODEPAGE_861 is not set # CONFIG_NLS_CODEPAGE_862 is not set # CONFIG_NLS_CODEPAGE_863 is not set # CONFIG_NLS_CODEPAGE_864 is not set # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set # CONFIG_NLS_CODEPAGE_869 is not set # CONFIG_NLS_CODEPAGE_936 is not set # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set # CONFIG_NLS_CODEPAGE_949 is not set # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set CONFIG_NLS_ASCII=m CONFIG_NLS_ISO8859_1=m # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_5 is not set # CONFIG_NLS_ISO8859_6 is not set # CONFIG_NLS_ISO8859_7 is not set # CONFIG_NLS_ISO8859_9 is not set # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set CONFIG_NLS_ISO8859_15=m # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set CONFIG_NLS_UTF8=m # CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_PRINTK_TIME=y CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 # CONFIG_ENABLE_WARN_DEPRECATED is not set CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_MAGIC_SYSRQ is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set # CONFIG_LOCKUP_DETECTOR is not set # CONFIG_HARDLOCKUP_DETECTOR is not set # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set CONFIG_TIMER_STATS=y # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_LOCK_ALLOC is not set # CONFIG_PROVE_LOCKING is not set # CONFIG_SPARSE_RCU_POINTER is not set # CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_ATOMIC_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_KOBJECT is not set # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_TEST_LIST_SORT is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_DEBUG_CREDENTIALS is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_TRACE is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_ASYNC_RAID6_TEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_CMDLINE_BOOL is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_RUNTIME_DEBUG is not set # # Security options # CONFIG_KEYS=y CONFIG_ENCRYPTED_KEYS=m # CONFIG_KEYS_DEBUG_PROC_KEYS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set CONFIG_SECURITY_NETWORK=y # CONFIG_SECURITY_NETWORK_XFRM is not set # CONFIG_SECURITY_PATH is not set # CONFIG_SECURITY_SELINUX is not set # CONFIG_SECURITY_TOMOYO is not set # CONFIG_SECURITY_APPARMOR is not set # CONFIG_SECURITY_YAMA is not set # CONFIG_IMA is not set # CONFIG_EVM is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_DEFAULT_SECURITY="" CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m CONFIG_ASYNC_MEMCPY=m CONFIG_ASYNC_XOR=m CONFIG_ASYNC_PQ=m CONFIG_ASYNC_RAID6_RECOV=m CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=m CONFIG_CRYPTO_ALGAPI2=m CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_AEAD2=m CONFIG_CRYPTO_BLKCIPHER=m CONFIG_CRYPTO_BLKCIPHER2=m CONFIG_CRYPTO_HASH=m CONFIG_CRYPTO_HASH2=m CONFIG_CRYPTO_RNG=m CONFIG_CRYPTO_RNG2=m CONFIG_CRYPTO_PCOMP=m CONFIG_CRYPTO_PCOMP2=m CONFIG_CRYPTO_MANAGER=m CONFIG_CRYPTO_MANAGER2=m CONFIG_CRYPTO_USER=m # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set CONFIG_CRYPTO_GF128MUL=m # CONFIG_CRYPTO_NULL is not set CONFIG_CRYPTO_WORKQUEUE=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=m # CONFIG_CRYPTO_TEST is not set # # Authenticated Encryption with Associated Data # CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=m CONFIG_CRYPTO_SEQIV=m # # Block modes # CONFIG_CRYPTO_CBC=m CONFIG_CRYPTO_CTR=m CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m # # Hash modes # CONFIG_CRYPTO_HMAC=m CONFIG_CRYPTO_XCBC=m CONFIG_CRYPTO_VMAC=m # # Digest # CONFIG_CRYPTO_CRC32C=m CONFIG_CRYPTO_GHASH=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m # # Ciphers # CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_BLOWFISH_COMMON=m CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_SALSA20=m CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_TWOFISH_COMMON=m # # Compression # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # # Random Number Generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_USER_API=m CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set # CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_RAID6_PQ=m CONFIG_BITREVERSE=y CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IO=y CONFIG_CRC_CCITT=m CONFIG_CRC16=y CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=m CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set CONFIG_CRC7=m CONFIG_LIBCRC32C=m CONFIG_CRC8=m CONFIG_AUDIT_GENERIC=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m CONFIG_LZO_COMPRESS=m CONFIG_LZO_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_IA64=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_SPARC=y CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_DQL=y CONFIG_NLATTR=y CONFIG_AVERAGE=y CONFIG_CORDIC=m --J2SCkAp4GZ/dPZZf-- From david.daney@cavium.com Tue Jun 5 21:08:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 21:08:51 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:18254 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903720Ab2FETIr (ORCPT ); Tue, 5 Jun 2012 21:08:47 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 05 Jun 2012 12:10:39 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 5 Jun 2012 12:08:44 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 5 Jun 2012 12:08:43 -0700 Message-ID: <4FCE593B.10808@cavium.com> Date: Tue, 05 Jun 2012 12:08:43 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Jim Faulkner CC: linux-mips@linux-mips.org Subject: Re: booting linux-3.3 or linux 3.4 on an SGI O2? References: <20120605190047.GA6263@alumni-linux.ccs.neu.edu> In-Reply-To: <20120605190047.GA6263@alumni-linux.ccs.neu.edu> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Jun 2012 19:08:43.0931 (UTC) FILETIME=[A049BEB0:01CD434E] X-archive-position: 33513 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 608 Lines: 15 On 06/05/2012 12:00 PM, Jim Faulkner wrote: > Hi all, I haven't been able to boot any kernels after linux 3.2 on my > SGI O2. I've tried linux-3.3.5 and linux-3.4.0, but neither would boot. > Unfortunately I don't have further information such as a kernel panic, > since I don't get any video output after the kernel is loaded. I've > attached my linux-3.4 .config. Anybody know what patches I might need > to get the latest kernels booting on this system? > I have had problems as well. Someone should configure a serial console and early printk to see if they can see what is happening. David Daney From sjhill@mips.com Tue Jun 5 23:19:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:20:25 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43432 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2FEVT4 (ORCPT ); Tue, 5 Jun 2012 23:19:56 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AL-000824-Kz; Tue, 05 Jun 2012 16:19:49 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 01/35] MIPS: Add environment variable processing code to firmware library. Date: Tue, 5 Jun 2012 16:19:05 -0500 Message-Id: <1338931179-9611-2-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33514 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4084 Lines: 170 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/fw/lib/Makefile | 2 + arch/mips/fw/lib/cmdline.c | 86 +++++++++++++++++++++++++++++++++++++++++ arch/mips/include/asm/fw/fw.h | 47 ++++++++++++++++++++++ 3 files changed, 135 insertions(+) create mode 100644 arch/mips/fw/lib/cmdline.c create mode 100644 arch/mips/include/asm/fw/fw.h diff --git a/arch/mips/fw/lib/Makefile b/arch/mips/fw/lib/Makefile index 84befc9..5291505 100644 --- a/arch/mips/fw/lib/Makefile +++ b/arch/mips/fw/lib/Makefile @@ -2,4 +2,6 @@ # Makefile for generic prom monitor library routines under Linux. # +lib-y += cmdline.o + lib-$(CONFIG_64BIT) += call_o32.o diff --git a/arch/mips/fw/lib/cmdline.c b/arch/mips/fw/lib/cmdline.c new file mode 100644 index 0000000..b05b8130 --- /dev/null +++ b/arch/mips/fw/lib/cmdline.c @@ -0,0 +1,86 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include + +int fw_argc; +int *_fw_argv; +int *_fw_envp; + +void __init fw_init_cmdline(void) +{ + int i; + + fw_argc = (fw_arg0 & 0x0000ffff); + _fw_argv = (int *)fw_arg1; + _fw_envp = (int *)fw_arg2; + + for (i = 1; i < fw_argc; i++) { + strlcat(arcs_cmdline, fw_argv(i), COMMAND_LINE_SIZE); + if (i < (fw_argc - 1)) + strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); + } +} + +char * __init fw_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +char *fw_getenv(char *envname) +{ + char *result = NULL; + + if (_fw_envp != NULL) { + /* + * Return a pointer to the given environment variable. + * YAMON uses "name", "value" pairs, while U-Boot uses + * "name=value". + */ + int i, yamon, index = 0; + + yamon = (strchr(fw_envp(index), '=') == NULL); + i = strlen(envname); + + while (fw_envp(index)) { + if (strncmp(envname, fw_envp(index), i) == 0) { + if (yamon) { + result = fw_envp(index + 1); + break; + } else if (fw_envp(index)[i] == '=') { + result = (fw_envp(index + 1) + i); + break; + } + } + + /* Increment array index. */ + if (yamon) + index += 2; + else + index += 1; + } + } + + return result; +} + +unsigned long fw_getenvl(char *envname) +{ + unsigned long envl = 0UL; + char *str; + long val; + int tmp; + + str = fw_getenv(envname); + if (str) { + tmp = kstrtol(str, 0, &val); + envl = (unsigned long)val; + } + + return envl; +} diff --git a/arch/mips/include/asm/fw/fw.h b/arch/mips/include/asm/fw/fw.h new file mode 100644 index 0000000..d6c50a7 --- /dev/null +++ b/arch/mips/include/asm/fw/fw.h @@ -0,0 +1,47 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. + */ +#ifndef __ASM_FW_H_ +#define __ASM_FW_H_ + +#include /* For cleaner code... */ + +enum fw_memtypes { + fw_dontuse, + fw_code, + fw_free, +}; + +typedef struct { + unsigned long base; /* Within KSEG0 */ + unsigned int size; /* bytes */ + enum fw_memtypes type; /* fw_memtypes */ +} fw_memblock_t; + +/* Maximum number of memory block descriptors. */ +#define FW_MAX_MEMBLOCKS 32 + +extern int fw_argc; +extern int *_fw_argv; +extern int *_fw_envp; + +/* + * Most firmware like YAMON, PMON, etc. pass arguments and environment + * variables as 32-bit pointers. These take care of sign extension. + */ +#define fw_argv(index) ((char *)(long)_fw_argv[(index)]) +#define fw_envp(index) ((char *)(long)_fw_envp[(index)]) + +extern void fw_init_cmdline(void); +extern char *fw_getcmdline(void); +extern fw_memblock_t *fw_getmdesc(void); +extern void fw_meminit(void); +extern char *fw_getenv(char *name); +extern unsigned long fw_getenvl(char *name); +extern void fw_init_early_console(char port); + +#endif /* __ASM_FW_H_ */ -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:19:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:20:51 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43433 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903720Ab2FEVT4 (ORCPT ); Tue, 5 Jun 2012 23:19:56 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AM-000824-5p; Tue, 05 Jun 2012 16:19:50 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 02/35] MIPS: Alchemy: Cleanup firmware support for Alchemy platforms. Date: Tue, 5 Jun 2012 16:19:06 -0500 Message-Id: <1338931179-9611-3-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33515 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 11197 Lines: 380 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/alchemy/board-gpr.c | 22 +++++-------- arch/mips/alchemy/board-mtx1.c | 22 +++++-------- arch/mips/alchemy/board-xxs1500.c | 21 +++++------- arch/mips/alchemy/common/platform.c | 3 +- arch/mips/alchemy/common/prom.c | 42 ++---------------------- arch/mips/alchemy/devboards/db1000.c | 1 - arch/mips/alchemy/devboards/db1300.c | 1 - arch/mips/alchemy/devboards/db1550.c | 1 - arch/mips/alchemy/devboards/pb1100.c | 1 - arch/mips/alchemy/devboards/pb1500.c | 1 - arch/mips/alchemy/devboards/prom.c | 19 ++++------- arch/mips/include/asm/mach-au1x00/au1xxx_eth.h | 1 + arch/mips/include/asm/mach-au1x00/prom.h | 12 ------- drivers/net/ethernet/amd/au1000_eth.c | 1 - 14 files changed, 35 insertions(+), 113 deletions(-) delete mode 100644 arch/mips/include/asm/mach-au1x00/prom.h diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c index ba32590..1139173 100644 --- a/arch/mips/alchemy/board-gpr.c +++ b/arch/mips/alchemy/board-gpr.c @@ -30,10 +30,10 @@ #include #include #include -#include + #include +#include #include -#include const char *get_system_type(void) { @@ -42,21 +42,15 @@ const char *get_system_type(void) void __init prom_init(void) { - unsigned char *memsize_str; - unsigned long memsize; + unsigned long physical_memsize; - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; + fw_init_cmdline(); - prom_init_cmdline(); + physical_memsize = fw_getenvl("memsize"); + if (!physical_memsize) + physical_memsize = 0x04000000; - memsize_str = prom_getenv("memsize"); - if (!memsize_str) - memsize = 0x04000000; - else - strict_strtoul(memsize_str, 0, &memsize); - add_memory_region(0, memsize, BOOT_MEM_RAM); + add_memory_region(0, physical_memsize, BOOT_MEM_RAM); } void prom_putchar(unsigned char c) diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c index 295f1a9..7d1ea7a 100644 --- a/arch/mips/alchemy/board-mtx1.c +++ b/arch/mips/alchemy/board-mtx1.c @@ -29,11 +29,11 @@ #include #include #include -#include + #include +#include #include #include -#include const char *get_system_type(void) { @@ -42,21 +42,15 @@ const char *get_system_type(void) void __init prom_init(void) { - unsigned char *memsize_str; - unsigned long memsize; + unsigned long physical_memsize; - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; + fw_init_cmdline(); - prom_init_cmdline(); + physical_memsize = fw_getenvl("memsize"); + if (!physical_memsize) + physical_memsize = 0x04000000; - memsize_str = prom_getenv("memsize"); - if (!memsize_str) - memsize = 0x04000000; - else - strict_strtoul(memsize_str, 0, &memsize); - add_memory_region(0, memsize, BOOT_MEM_RAM); + add_memory_region(0, physical_memsize, BOOT_MEM_RAM); } void prom_putchar(unsigned char c) diff --git a/arch/mips/alchemy/board-xxs1500.c b/arch/mips/alchemy/board-xxs1500.c index bd55136..0469f1c 100644 --- a/arch/mips/alchemy/board-xxs1500.c +++ b/arch/mips/alchemy/board-xxs1500.c @@ -27,10 +27,10 @@ #include #include #include -#include + #include +#include #include -#include const char *get_system_type(void) { @@ -39,20 +39,15 @@ const char *get_system_type(void) void __init prom_init(void) { - unsigned char *memsize_str; - unsigned long memsize; - - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; + unsigned long physical_memsize; - prom_init_cmdline(); + fw_init_cmdline(); - memsize_str = prom_getenv("memsize"); - if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) - memsize = 0x04000000; + physical_memsize = fw_getenvl("memsize"); + if (!physical_memsize) + physical_memsize = 0x04000000; - add_memory_region(0, memsize, BOOT_MEM_RAM); + add_memory_region(0, physical_memsize, BOOT_MEM_RAM); } void prom_putchar(unsigned char c) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 95cb911..2c5c014 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -18,13 +18,12 @@ #include #include +#include #include #include #include #include -#include - static void alchemy_8250_pm(struct uart_port *port, unsigned int state, unsigned int old_state) { diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c index 5340210..a67012d 100644 --- a/arch/mips/alchemy/common/prom.c +++ b/arch/mips/alchemy/common/prom.c @@ -37,45 +37,7 @@ #include #include -#include - -int prom_argc; -char **prom_argv; -char **prom_envp; - -void __init prom_init_cmdline(void) -{ - int i; - - for (i = 1; i < prom_argc; i++) { - strlcat(arcs_cmdline, prom_argv[i], COMMAND_LINE_SIZE); - if (i < (prom_argc - 1)) - strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); - } -} - -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - * YAMON uses "name", "value" pairs, while U-Boot uses "name=value". - */ - - char **env = prom_envp; - int i = strlen(envname); - int yamon = (*env && strchr(*env, '=') == NULL); - - while (*env) { - if (yamon) { - if (strcmp(envname, *env++) == 0) - return *env; - } else if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=') - return *env + i + 1; - env++; - } - - return NULL; -} +#include static inline unsigned char str2hexnum(unsigned char c) { @@ -109,7 +71,7 @@ int __init prom_get_ethernet_addr(char *ethernet_addr) char *ethaddr_str; /* Check the environment variables first */ - ethaddr_str = prom_getenv("ethaddr"); + ethaddr_str = fw_getenv("ethaddr"); if (!ethaddr_str) { /* Check command line */ ethaddr_str = strstr(arcs_cmdline, "ethaddr="); diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c index 1b81dbf..53ff8a4 100644 --- a/arch/mips/alchemy/devboards/db1000.c +++ b/arch/mips/alchemy/devboards/db1000.c @@ -36,7 +36,6 @@ #include #include #include -#include #include "platform.h" #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index c56e024..8073c86 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -28,7 +28,6 @@ #include #include #include -#include #include "platform.h" diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c index 9eb7906..7d72509 100644 --- a/arch/mips/alchemy/devboards/db1550.c +++ b/arch/mips/alchemy/devboards/db1550.c @@ -23,7 +23,6 @@ #include #include #include -#include #include "platform.h" diff --git a/arch/mips/alchemy/devboards/pb1100.c b/arch/mips/alchemy/devboards/pb1100.c index cff50d0..a9d8904 100644 --- a/arch/mips/alchemy/devboards/pb1100.c +++ b/arch/mips/alchemy/devboards/pb1100.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "platform.h" const char *get_system_type(void) diff --git a/arch/mips/alchemy/devboards/pb1500.c b/arch/mips/alchemy/devboards/pb1500.c index e7b807b..36e1853 100644 --- a/arch/mips/alchemy/devboards/pb1500.c +++ b/arch/mips/alchemy/devboards/pb1500.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "platform.h" const char *get_system_type(void) diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index 93a2210..59af1d4 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -29,9 +29,8 @@ #include #include -#include +#include #include -#include #if defined(CONFIG_MIPS_DB1000) || \ defined(CONFIG_MIPS_PB1100) || \ @@ -44,19 +43,15 @@ void __init prom_init(void) { - unsigned char *memsize_str; - unsigned long memsize; + unsigned long physical_memsize; - prom_argc = (int)fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; + fw_init_cmdline(); - prom_init_cmdline(); - memsize_str = prom_getenv("memsize"); - if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) - memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE; + physical_memsize = fw_getenvl("memsize"); + if (!physical_memsize) + physical_memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE; - add_memory_region(0, memsize, BOOT_MEM_RAM); + add_memory_region(0, physical_memsize, BOOT_MEM_RAM); } void prom_putchar(unsigned char c) diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h index 49dc8d9..3f22d5a 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h @@ -14,5 +14,6 @@ struct au1000_eth_platform_data { void __init au1xxx_override_eth_cfg(unsigned port, struct au1000_eth_platform_data *eth_data); +int __init prom_get_ethernet_addr(char *ethernet_addr); #endif /* __AU1X00_ETH_DATA_H */ diff --git a/arch/mips/include/asm/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h deleted file mode 100644 index 4c0e09c..0000000 --- a/arch/mips/include/asm/mach-au1x00/prom.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __AU1X00_PROM_H -#define __AU1X00_PROM_H - -extern int prom_argc; -extern char **prom_argv; -extern char **prom_envp; - -extern void prom_init_cmdline(void); -extern char *prom_getenv(char *envname); -extern int prom_get_ethernet_addr(char *ethernet_addr); - -#endif diff --git a/drivers/net/ethernet/amd/au1000_eth.c b/drivers/net/ethernet/amd/au1000_eth.c index 397596b..200ccc2 100644 --- a/drivers/net/ethernet/amd/au1000_eth.c +++ b/drivers/net/ethernet/amd/au1000_eth.c @@ -67,7 +67,6 @@ #include #include -#include #include "au1000_eth.h" -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:19:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:21:13 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43430 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903721Ab2FEVT4 (ORCPT ); Tue, 5 Jun 2012 23:19:56 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AJ-000824-D6; Tue, 05 Jun 2012 16:19:47 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 00/35] Cleanup firmware support across multiple platforms. Date: Tue, 5 Jun 2012 16:19:04 -0500 Message-Id: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 X-archive-position: 33516 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7612 Lines: 128 From: "Steven J. Hill" The firmware/bootloader support code has been duplicated across a lot of platforms and continues to self-replicate. These patches move the support code into the common 'arch/mips/fw/lib' directory. All affected platforms have been built and produce a linked kernel. Any files that were modified also had their headers cleaned up and the checkpatch script ran on them. Steven J. Hill (35): MIPS: Add environment variable processing code to firmware library. MIPS: Alchemy: Cleanup firmware support for Alchemy platforms. MIPS: Alchemy: Cleanup files effected by firmware changes. MIPS: AR7: Cleanup firmware support for the AR7 platform. MIPS: AR7: Cleanup files effected by firmware changes. MIPS: ath79: Cleanup firmware support for the ath79 platform. MIPS: ath79: Cleanup files effected by firmware changes. MIPS: Cobalt: Cleanup firmware support for the Cobalt platform. MIPS: Cobalt: Cleanup files effected by firmware changes. MIPS: Emma: Cleanup firmware support for the Emma platform. MIPS: Emma: Cleanup files effected by firmware changes. MIPS: jz4740: Cleanup firmware support for the JZ4740 platform. MIPS: jz4740: Cleanup files effected by firmware changes. MIPS: lantiq: Cleanup firmware support for the lantiq platform. MIPS: lantiq: Cleanup files effected by firmware changes. MIPS: Lasat: Cleanup firmware support for the Lasat platform. MIPS: Lasat: Cleanup files effected by firmware changes. MIPS: Loongson: Cleanup firmware support for the Loongson platform. MIPS: Loongson: Cleanup files effected by firmware changes. MIPS: Malta: Cleanup firmware support for the Malta platform. MIPS: Malta: Cleanup files effected by firmware changes. MIPS: Netlogic: Cleanup firmware support for the XLR platform. MIPS: Netlogic: Cleanup files effected by firmware changes. MIPS: MSP71xx, Yosemite: Cleanup firmware support for PMC platforms. MIPS: MSP71xx, Yosemite: Cleanup files effected by firmware changes. MIPS: PNX83xx, PNX8550: Cleanup firmware support for PNX platforms. MIPS: PNX83xx, PNX8550: Cleanup files effected by firmware changes. MIPS: PowerTV: Cleanup firmware support for PowerTV platform. MIPS: PowerTV: Cleanup files effected by firmware changes. MIPS: RB532: Cleanup firmware support for RB532 platform. MIPS: RB532: Cleanup files effected by firmware changes. MIPS: txx9: Cleanup firmware support for txx9 platforms. MIPS: txx9: Cleanup files effected by firmware changes. MIPS: vr41xx: Cleanup firmware support for vr41xx platforms. MIPS: vr41xx: Cleanup files effected by firmware changes. arch/mips/alchemy/board-gpr.c | 48 ++--- arch/mips/alchemy/board-mtx1.c | 48 ++--- arch/mips/alchemy/board-xxs1500.c | 45 ++--- arch/mips/alchemy/common/platform.c | 30 +-- arch/mips/alchemy/common/prom.c | 79 ++------ arch/mips/alchemy/devboards/db1000.c | 1 - arch/mips/alchemy/devboards/db1300.c | 1 - arch/mips/alchemy/devboards/db1550.c | 1 - arch/mips/alchemy/devboards/pb1100.c | 1 - arch/mips/alchemy/devboards/pb1500.c | 1 - arch/mips/alchemy/devboards/prom.c | 54 ++--- arch/mips/ar7/memory.c | 22 +-- arch/mips/ar7/platform.c | 63 +++--- arch/mips/ar7/prom.c | 62 ++---- arch/mips/ar7/setup.c | 26 +-- arch/mips/ath79/prom.c | 33 +--- arch/mips/cobalt/setup.c | 42 ++-- arch/mips/emma/common/prom.c | 44 +---- arch/mips/fw/lib/Makefile | 2 + arch/mips/fw/lib/cmdline.c | 86 ++++++++ arch/mips/include/asm/fw/fw.h | 47 +++++ arch/mips/include/asm/mach-ar7/prom.h | 25 --- arch/mips/include/asm/mach-au1x00/au1xxx_eth.h | 1 + arch/mips/include/asm/mach-au1x00/prom.h | 12 -- arch/mips/include/asm/mach-loongson/loongson.h | 54 ++--- arch/mips/include/asm/mips-boards/generic.h | 30 +-- arch/mips/include/asm/mips-boards/prom.h | 47 ----- .../mips/include/asm/pmc-sierra/msp71xx/msp_prom.h | 52 +---- arch/mips/include/asm/txx9/generic.h | 1 - arch/mips/jz4740/prom.c | 50 ++--- arch/mips/lantiq/prom.c | 32 +-- arch/mips/lasat/prom.c | 24 +-- arch/mips/loongson/common/Makefile | 2 +- arch/mips/loongson/common/cmdline.c | 48 ----- arch/mips/loongson/common/env.c | 40 ++-- arch/mips/loongson/common/init.c | 16 +- arch/mips/mti-malta/Makefile | 2 +- arch/mips/mti-malta/malta-cmdline.c | 59 ------ arch/mips/mti-malta/malta-display.c | 40 ++-- arch/mips/mti-malta/malta-init.c | 157 +++------------ arch/mips/mti-malta/malta-memory.c | 108 ++++------ arch/mips/mti-malta/malta-setup.c | 59 ++---- arch/mips/mti-malta/malta-time.c | 65 ++---- arch/mips/netlogic/xlr/setup.c | 82 ++------ arch/mips/pmc-sierra/msp71xx/msp_prom.c | 207 +++++--------------- arch/mips/pmc-sierra/msp71xx/msp_serial.c | 69 +++---- arch/mips/pmc-sierra/msp71xx/msp_setup.c | 43 ++-- arch/mips/pmc-sierra/msp71xx/msp_time.c | 75 ++----- arch/mips/pmc-sierra/msp71xx/msp_usb.c | 45 ++--- arch/mips/pmc-sierra/yosemite/prom.c | 46 ++--- arch/mips/pnx833x/common/Makefile | 2 +- arch/mips/pnx833x/common/prom.c | 64 ------ arch/mips/pnx833x/common/setup.c | 39 ++-- arch/mips/pnx833x/stb22x/board.c | 70 +++---- arch/mips/pnx8550/common/Makefile | 2 +- arch/mips/pnx8550/common/prom.c | 128 ------------ arch/mips/pnx8550/common/setup.c | 69 +++---- arch/mips/pnx8550/jbs/init.c | 45 +---- arch/mips/pnx8550/stb810/prom_init.c | 36 +--- arch/mips/powertv/asic/asic_int.c | 45 ++--- arch/mips/powertv/init.c | 81 ++------ arch/mips/powertv/memory.c | 39 ++-- arch/mips/powertv/powertv_setup.c | 29 +-- arch/mips/rb532/prom.c | 69 +++---- arch/mips/txx9/generic/setup.c | 85 ++------ arch/mips/vr41xx/common/init.c | 41 +--- drivers/mtd/maps/pmcmsp-flash.c | 58 ++---- drivers/net/ethernet/amd/au1000_eth.c | 1 - 68 files changed, 890 insertions(+), 2240 deletions(-) create mode 100644 arch/mips/fw/lib/cmdline.c create mode 100644 arch/mips/include/asm/fw/fw.h delete mode 100644 arch/mips/include/asm/mach-ar7/prom.h delete mode 100644 arch/mips/include/asm/mach-au1x00/prom.h delete mode 100644 arch/mips/include/asm/mips-boards/prom.h delete mode 100644 arch/mips/loongson/common/cmdline.c delete mode 100644 arch/mips/mti-malta/malta-cmdline.c delete mode 100644 arch/mips/pnx833x/common/prom.c delete mode 100644 arch/mips/pnx8550/common/prom.c -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:19:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:21:38 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43436 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903723Ab2FEVT5 (ORCPT ); Tue, 5 Jun 2012 23:19:57 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AM-000824-Jk; Tue, 05 Jun 2012 16:19:50 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 03/35] MIPS: Alchemy: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:07 -0500 Message-Id: <1338931179-9611-4-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33517 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 15057 Lines: 375 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/alchemy/board-gpr.c | 26 +++++++----------------- arch/mips/alchemy/board-mtx1.c | 26 +++++++----------------- arch/mips/alchemy/board-xxs1500.c | 24 ++++++----------------- arch/mips/alchemy/common/platform.c | 27 +++++++++++++------------ arch/mips/alchemy/common/prom.c | 37 +++++++++-------------------------- arch/mips/alchemy/devboards/prom.c | 35 ++++++++------------------------- 6 files changed, 51 insertions(+), 124 deletions(-) diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c index 1139173..8ad454a 100644 --- a/arch/mips/alchemy/board-gpr.c +++ b/arch/mips/alchemy/board-gpr.c @@ -1,27 +1,15 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * GPR board platform device registration (Au1550) * * Copyright (C) 2010 Wolfgang Grandegger - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include -#include #include -#include #include #include #include @@ -65,7 +53,7 @@ static void gpr_reset(char *c) alchemy_gpio_direction_output(5, 0); /* trigger watchdog to reset board in 200ms */ - printk(KERN_EMERG "Triggering watchdog soft reset...\n"); + pr_emerg("Triggering watchdog soft reset...\n"); raw_local_irq_disable(); alchemy_gpio_direction_output(1, 0); udelay(1); @@ -82,7 +70,7 @@ static void gpr_power_off(void) void __init board_setup(void) { - printk(KERN_INFO "Trapeze ITS GPR board\n"); + pr_info("Trapeze ITS GPR board\n"); pm_power_off = gpr_power_off; _machine_halt = gpr_power_off; diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c index 7d1ea7a..6d5e56c 100644 --- a/arch/mips/alchemy/board-mtx1.c +++ b/arch/mips/alchemy/board-mtx1.c @@ -1,26 +1,14 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * MTX-1 platform devices registration (Au1500) * * Copyright (C) 2007-2009, Florian Fainelli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - -#include #include -#include #include #include #include @@ -98,7 +86,7 @@ void __init board_setup(void) _machine_halt = mtx1_power_off; _machine_restart = mtx1_reset; - printk(KERN_INFO "4G Systems MTX-1 Board\n"); + pr_info("4G Systems MTX-1 Board\n"); } /******************************************************************************/ @@ -296,7 +284,7 @@ static int __init mtx1_register_devices(void) rc = gpio_request(mtx1_gpio_button[0].gpio, mtx1_gpio_button[0].desc); if (rc < 0) { - printk(KERN_INFO "mtx1: failed to request %d\n", + pr_info("mtx1: failed to request %d\n", mtx1_gpio_button[0].gpio); goto out; } diff --git a/arch/mips/alchemy/board-xxs1500.c b/arch/mips/alchemy/board-xxs1500.c index 0469f1c..e7a3745 100644 --- a/arch/mips/alchemy/board-xxs1500.c +++ b/arch/mips/alchemy/board-xxs1500.c @@ -1,25 +1,13 @@ /* - * BRIEF MODULE DESCRIPTION - * MyCable XXS1500 board support + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright 2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. + * MyCable XXS1500 board support * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Copyright 2003, 2008 MontaVista Software Inc. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include #include #include diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 2c5c014..6a870a9 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -1,4 +1,8 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Platform device support for Au1x00 SoCs. * * Copyright 2004, Matt Porter @@ -6,11 +10,8 @@ * (C) Copyright Embedded Alley Solutions, Inc 2005 * Author: Pantelis Antoniou * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include #include #include @@ -103,7 +104,7 @@ static void __init alchemy_setup_uarts(int ctype) ports = kzalloc(s * (c + 1), GFP_KERNEL); if (!ports) { - printk(KERN_INFO "Alchemy: no memory for UART data\n"); + pr_info("Alchemy: no memory for UART data\n"); return; } memcpy(ports, au1x00_uart_data[ctype], s * c); @@ -113,7 +114,7 @@ static void __init alchemy_setup_uarts(int ctype) for (s = 0; s < c; s++) ports[s].uartclk = uartclk; if (platform_device_register(&au1xx0_uart_device)) - printk(KERN_INFO "Alchemy: failed to register UARTs\n"); + pr_info("Alchemy: failed to register UARTs\n"); } @@ -173,7 +174,7 @@ static void __init alchemy_setup_usb(int ctype) pdev->dev.dma_mask = &alchemy_ohci_dmamask; if (platform_device_register(pdev)) - printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); + pr_info("Alchemy USB: cannot add OHCI0\n"); /* setup EHCI0: Au1200/Au1300 */ @@ -192,7 +193,7 @@ static void __init alchemy_setup_usb(int ctype) pdev->dev.dma_mask = &alchemy_ehci_dmamask; if (platform_device_register(pdev)) - printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); + pr_info("Alchemy USB: cannot add EHCI0\n"); } /* Au1300: OHCI1 */ @@ -211,7 +212,7 @@ static void __init alchemy_setup_usb(int ctype) pdev->dev.dma_mask = &alchemy_ohci_dmamask; if (platform_device_register(pdev)) - printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n"); + pr_info("Alchemy USB: cannot add OHCI1\n"); } } @@ -335,7 +336,7 @@ static void __init alchemy_setup_macs(int ctype) macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); if (!macres) { - printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n"); + pr_info("Alchemy: no memory for MAC0 resources\n"); return; } memcpy(macres, au1xxx_eth0_resources[ctype], @@ -348,7 +349,7 @@ static void __init alchemy_setup_macs(int ctype) ret = platform_device_register(&au1xxx_eth0_device); if (ret) - printk(KERN_INFO "Alchemy: failed to register MAC0\n"); + pr_info("Alchemy: failed to register MAC0\n"); /* Handle 2nd MAC */ @@ -357,7 +358,7 @@ static void __init alchemy_setup_macs(int ctype) macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); if (!macres) { - printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n"); + pr_info("Alchemy: no memory for MAC1 resources\n"); return; } memcpy(macres, au1xxx_eth1_resources[ctype], @@ -372,7 +373,7 @@ static void __init alchemy_setup_macs(int ctype) if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) { ret = platform_device_register(&au1xxx_eth1_device); if (ret) - printk(KERN_INFO "Alchemy: failed to register MAC1\n"); + pr_info("Alchemy: failed to register MAC1\n"); } } diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c index a67012d..57e754d 100644 --- a/arch/mips/alchemy/common/prom.c +++ b/arch/mips/alchemy/common/prom.c @@ -1,38 +1,19 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * BRIEF MODULE DESCRIPTION - * PROM library initialisation code, supports YAMON and U-Boot. + * PROM library initialisation code, supports YAMON and U-Boot. This file + * was derived from Carsten Langgaard's arch/mips/mips-boards/xx files. * * Copyright 2000-2001, 2006, 2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/xx files. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ - #include #include #include diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index 59af1d4..a48f9ae 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -1,40 +1,21 @@ /* - * Common code used by all Alchemy develboards. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Extracted from files which had this to say: + * Common code used by all Alchemy development boards. + * GPR board platform device registration (Au1550) * * Copyright 2000, 2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved */ - -#include -#include #include #include -#if defined(CONFIG_MIPS_DB1000) || \ - defined(CONFIG_MIPS_PB1100) || \ - defined(CONFIG_MIPS_PB1500) +#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_PB1100) || \ + defined(CONFIG_MIPS_PB1500) #define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 #else /* Au1550/Au1200-based develboards */ -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:19:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:22:06 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43437 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903724Ab2FEVT5 (ORCPT ); Tue, 5 Jun 2012 23:19:57 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AN-000824-2c; Tue, 05 Jun 2012 16:19:51 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 04/35] MIPS: AR7: Cleanup firmware support for the AR7 platform. Date: Tue, 5 Jun 2012 16:19:08 -0500 Message-Id: <1338931179-9611-5-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33518 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5711 Lines: 209 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/ar7/memory.c | 3 +-- arch/mips/ar7/platform.c | 10 ++++----- arch/mips/ar7/prom.c | 40 ++++++++------------------------- arch/mips/ar7/setup.c | 4 ++-- arch/mips/include/asm/mach-ar7/prom.h | 25 --------------------- 5 files changed, 17 insertions(+), 65 deletions(-) delete mode 100644 arch/mips/include/asm/mach-ar7/prom.h diff --git a/arch/mips/ar7/memory.c b/arch/mips/ar7/memory.c index 28abfee..3d7133d 100644 --- a/arch/mips/ar7/memory.c +++ b/arch/mips/ar7/memory.c @@ -30,7 +30,6 @@ #include #include -#include static int __init memsize(void) { @@ -57,7 +56,7 @@ static int __init memsize(void) return size; } -void __init prom_meminit(void) +void __init fw_meminit(void) { unsigned long pages; diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 1a24d31..284b86a 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -38,9 +38,9 @@ #include #include +#include #include #include -#include /***************************************************************************** * VLYNQ Bus @@ -297,10 +297,10 @@ static void __init cpmac_get_mac(int instance, unsigned char *dev_addr) char name[5], *mac; sprintf(name, "mac%c", 'a' + instance); - mac = prom_getenv(name); + mac = fw_getenv(name); if (!mac && instance) { sprintf(name, "mac%c", 'a'); - mac = prom_getenv(name); + mac = fw_getenv(name); } if (mac) { @@ -514,8 +514,8 @@ static void __init detect_leds(void) ar7_led_data.leds = default_leds; /* FIXME: the whole thing is unreliable */ - prid = prom_getenv("ProductID"); - usb_prod = prom_getenv("usb_prod"); + prid = fw_getenv("ProductID"); + usb_prod = fw_getenv("usb_prod"); /* If we can't get the product id from PROM, use the default LEDs */ if (!prid) diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c index a23adc4..9e5699a 100644 --- a/arch/mips/ar7/prom.c +++ b/arch/mips/ar7/prom.c @@ -24,10 +24,9 @@ #include #include #include -#include +#include #include -#include #define MAX_ENTRY 80 @@ -38,29 +37,6 @@ struct env_var { static struct env_var adam2_env[MAX_ENTRY]; -char *prom_getenv(const char *name) -{ - int i; - - for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++) - if (!strcmp(name, adam2_env[i].name)) - return adam2_env[i].value; - - return NULL; -} -EXPORT_SYMBOL(prom_getenv); - -static void __init ar7_init_cmdline(int argc, char *argv[]) -{ - int i; - - for (i = 1; i < argc; i++) { - strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE); - if (i < (argc - 1)) - strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); - } -} - struct psbl_rec { u32 psbl_size; u32 env_base; @@ -199,17 +175,19 @@ static void __init console_config(void) { #ifdef CONFIG_SERIAL_8250_CONSOLE char console_string[40]; - int baud = 0; + long val; + int tmp, baud = 0; char parity = '\0', bits = '\0', flow = '\0'; - char *s, *p; + char *s; if (strstr(arcs_cmdline, "console=")) return; - s = prom_getenv("modetty0"); + s = fw_getenv("modetty0"); if (s) { - baud = simple_strtoul(s, &p, 10); - s = p; + tmp = kstrtol(s, 0, &val); + baud = (int)val; + while (*s++ != ','); if (*s == ',') s++; if (*s) @@ -243,7 +221,7 @@ static void __init console_config(void) void __init prom_init(void) { - ar7_init_cmdline(fw_arg0, (char **)fw_arg1); + fw_init_cmdline(); ar7_init_env((struct env_var *)fw_arg2); console_config(); diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c index 9a357ff..ec318bb 100644 --- a/arch/mips/ar7/setup.c +++ b/arch/mips/ar7/setup.c @@ -21,8 +21,8 @@ #include #include +#include #include -#include #include static void ar7_machine_restart(char *command) @@ -99,7 +99,7 @@ void __init plat_mem_setup(void) panic("Can't remap IO base!"); set_io_port_base(io_base); - prom_meminit(); + fw_meminit(); printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n", get_system_type(), ar7_chip_id(), ar7_chip_rev()); diff --git a/arch/mips/include/asm/mach-ar7/prom.h b/arch/mips/include/asm/mach-ar7/prom.h deleted file mode 100644 index 088f61f..0000000 --- a/arch/mips/include/asm/mach-ar7/prom.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2006, 2007 Florian Fainelli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PROM_H__ -#define __PROM_H__ - -extern char *prom_getenv(const char *name); -extern void prom_meminit(void); - -#endif /* __PROM_H__ */ -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:19:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:22:32 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43441 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903725Ab2FEVT5 (ORCPT ); Tue, 5 Jun 2012 23:19:57 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AN-000824-JJ; Tue, 05 Jun 2012 16:19:51 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 05/35] MIPS: AR7: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:09 -0500 Message-Id: <1338931179-9611-6-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33519 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 9479 Lines: 244 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/ar7/memory.c | 19 +++++------------ arch/mips/ar7/platform.c | 53 ++++++++++++++++++---------------------------- arch/mips/ar7/prom.c | 22 ++++++------------- arch/mips/ar7/setup.c | 22 ++++++------------- 4 files changed, 39 insertions(+), 77 deletions(-) diff --git a/arch/mips/ar7/memory.c b/arch/mips/ar7/memory.c index 3d7133d..f3009a8 100644 --- a/arch/mips/ar7/memory.c +++ b/arch/mips/ar7/memory.c @@ -1,20 +1,11 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright (C) 2007 Felix Fietkau * Copyright (C) 2007 Eugene Konev - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include #include diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 284b86a..921e42c 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -1,22 +1,12 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright (C) 2006,2007 Felix Fietkau * Copyright (C) 2006,2007 Eugene Konev - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include #include #include @@ -308,8 +298,7 @@ static void __init cpmac_get_mac(int instance, unsigned char *dev_addr) &dev_addr[0], &dev_addr[1], &dev_addr[2], &dev_addr[3], &dev_addr[4], &dev_addr[5]) != 6) { - pr_warning("cannot parse mac address, " - "using random address\n"); + pr_warn("cannot parse mac address, using random address\n"); random_ether_addr(dev_addr); } } else @@ -489,11 +478,11 @@ static struct gpio_led gt701_leds[] = { .active_low = 1, .default_trigger = "default-on", }, - { - .name = "ethernet", - .gpio = 10, - .active_low = 1, - }, + { + .name = "ethernet", + .gpio = 10, + .active_low = 1, + }, }; static struct gpio_led_platform_data ar7_led_data; @@ -662,7 +651,7 @@ static int __init ar7_register_devices(void) res = platform_device_register(&physmap_flash); if (res) - pr_warning("unable to register physmap-flash: %d\n", res); + pr_warn("unable to register physmap-flash: %d\n", res); if (ar7_is_titan()) titan_fixup_devices(); @@ -670,13 +659,13 @@ static int __init ar7_register_devices(void) ar7_device_disable(vlynq_low_data.reset_bit); res = platform_device_register(&vlynq_low); if (res) - pr_warning("unable to register vlynq-low: %d\n", res); + pr_warn("unable to register vlynq-low: %d\n", res); if (ar7_has_high_vlynq()) { ar7_device_disable(vlynq_high_data.reset_bit); res = platform_device_register(&vlynq_high); if (res) - pr_warning("unable to register vlynq-high: %d\n", res); + pr_warn("unable to register vlynq-high: %d\n", res); } if (ar7_has_high_cpmac()) { @@ -686,9 +675,9 @@ static int __init ar7_register_devices(void) res = platform_device_register(&cpmac_high); if (res) - pr_warning("unable to register cpmac-high: %d\n", res); + pr_warn("unable to register cpmac-high: %d\n", res); } else - pr_warning("unable to add cpmac-high phy: %d\n", res); + pr_warn("unable to add cpmac-high phy: %d\n", res); } else cpmac_low_data.phy_mask = 0xffffffff; @@ -697,18 +686,18 @@ static int __init ar7_register_devices(void) cpmac_get_mac(0, cpmac_low_data.dev_addr); res = platform_device_register(&cpmac_low); if (res) - pr_warning("unable to register cpmac-low: %d\n", res); + pr_warn("unable to register cpmac-low: %d\n", res); } else - pr_warning("unable to add cpmac-low phy: %d\n", res); + pr_warn("unable to add cpmac-low phy: %d\n", res); detect_leds(); res = platform_device_register(&ar7_gpio_leds); if (res) - pr_warning("unable to register leds: %d\n", res); + pr_warn("unable to register leds: %d\n", res); res = platform_device_register(&ar7_udc); if (res) - pr_warning("unable to register usb slave: %d\n", res); + pr_warn("unable to register usb slave: %d\n", res); /* Register watchdog only if enabled in hardware */ bootcr = ioremap_nocache(AR7_REGS_DCL, 4); @@ -723,7 +712,7 @@ static int __init ar7_register_devices(void) ar7_wdt_res.end = ar7_wdt_res.start + 0x20; res = platform_device_register(&ar7_wdt); if (res) - pr_warning("unable to register watchdog: %d\n", res); + pr_warn("unable to register watchdog: %d\n", res); } return 0; diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c index 9e5699a..64ef6de 100644 --- a/arch/mips/ar7/prom.c +++ b/arch/mips/ar7/prom.c @@ -1,21 +1,11 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Putting things on the screen/serial line using YAMONs facilities. + * Carsten Langgaard, carstenl@mips.com + * Steven J. Hill, sjhill@mips.com + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. All rights reserved. */ #include #include diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c index ec318bb..0195cf1 100644 --- a/arch/mips/ar7/setup.c +++ b/arch/mips/ar7/setup.c @@ -1,19 +1,11 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * Carsten Langgaard, carstenl@mips.com + * Steven J. Hill, sjhill@mips.com + * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. */ #include #include @@ -101,6 +93,6 @@ void __init plat_mem_setup(void) fw_meminit(); - printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n", + pr_info("%s, ID: 0x%04x, Revision: 0x%02x\n", get_system_type(), ar7_chip_id(), ar7_chip_rev()); } -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:19:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:22:56 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43442 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903726Ab2FEVT6 (ORCPT ); Tue, 5 Jun 2012 23:19:58 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AO-000824-3o; Tue, 05 Jun 2012 16:19:52 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 06/35] MIPS: ath79: Cleanup firmware support for the ath79 platform. Date: Tue, 5 Jun 2012 16:19:10 -0500 Message-Id: <1338931179-9611-7-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33520 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1137 Lines: 50 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/ath79/prom.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c index e9cbd7c..adbe614 100644 --- a/arch/mips/ath79/prom.c +++ b/arch/mips/ath79/prom.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include "common.h" @@ -32,23 +32,11 @@ static inline int is_valid_ram_addr(void *addr) return 0; } -static __init void ath79_prom_init_cmdline(int argc, char **argv) -{ - int i; - - if (!is_valid_ram_addr(argv)) - return; - - for (i = 0; i < argc; i++) - if (is_valid_ram_addr(argv[i])) { - strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); - strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); - } -} - void __init prom_init(void) { - ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1); + if (!is_valid_ram_addr((int *)fw_arg1)) + return; + fw_init_cmdline(); } void __init prom_free_prom_memory(void) -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:19:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:23:23 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43444 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903727Ab2FEVT6 (ORCPT ); Tue, 5 Jun 2012 23:19:58 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AO-000824-Lx; Tue, 05 Jun 2012 16:19:52 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 07/35] MIPS: ath79: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:11 -0500 Message-Id: <1338931179-9611-8-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33521 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1261 Lines: 41 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/ath79/prom.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c index adbe614..9ead18a 100644 --- a/arch/mips/ath79/prom.c +++ b/arch/mips/ath79/prom.c @@ -1,18 +1,15 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Atheros AR71XX/AR724X/AR913X specific prom routines * * Copyright (C) 2008-2010 Gabor Juhos * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - -#include -#include #include -#include #include #include -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:19:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:23:46 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43446 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903728Ab2FEVT7 (ORCPT ); Tue, 5 Jun 2012 23:19:59 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AP-000824-5U; Tue, 05 Jun 2012 16:19:53 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 08/35] MIPS: Cobalt: Cleanup firmware support for the Cobalt platform. Date: Tue, 5 Jun 2012 16:19:12 -0500 Message-Id: <1338931179-9611-9-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33522 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1141 Lines: 49 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/cobalt/setup.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index ec3b2c4..3fdd449 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -15,9 +15,9 @@ #include #include -#include #include #include +#include #include @@ -97,21 +97,9 @@ void __init plat_mem_setup(void) void __init prom_init(void) { - unsigned long memsz; - int argc, i; - char **argv; + fw_init_cmdline(); - memsz = fw_arg0 & 0x7fff0000; - argc = fw_arg0 & 0x0000ffff; - argv = (char **)fw_arg1; - - for (i = 1; i < argc; i++) { - strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE); - if (i < (argc - 1)) - strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); - } - - add_memory_region(0x0, memsz, BOOT_MEM_RAM); + add_memory_region(0x0, (fw_arg0 & 0x7fff0000), BOOT_MEM_RAM); } void __init prom_free_prom_memory(void) -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:19:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:24:07 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43449 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903737Ab2FEVT7 (ORCPT ); Tue, 5 Jun 2012 23:19:59 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AP-000824-Kz; Tue, 05 Jun 2012 16:19:53 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 09/35] MIPS: Cobalt: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:13 -0500 Message-Id: <1338931179-9611-10-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33523 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1954 Lines: 66 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/cobalt/setup.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index 3fdd449..2565965 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -1,12 +1,13 @@ /* - * Setup pointers to hardware dependent routines. - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * + * Setup pointers to hardware dependent routines. + * * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. * */ #include @@ -27,14 +28,14 @@ extern void cobalt_machine_halt(void); const char *get_system_type(void) { switch (cobalt_board_id) { - case COBALT_BRD_ID_QUBE1: - return "Cobalt Qube"; - case COBALT_BRD_ID_RAQ1: - return "Cobalt RaQ"; - case COBALT_BRD_ID_QUBE2: - return "Cobalt Qube2"; - case COBALT_BRD_ID_RAQ2: - return "Cobalt RaQ2"; + case COBALT_BRD_ID_QUBE1: + return "Cobalt Qube"; + case COBALT_BRD_ID_RAQ1: + return "Cobalt RaQ"; + case COBALT_BRD_ID_QUBE2: + return "Cobalt Qube2"; + case COBALT_BRD_ID_RAQ2: + return "Cobalt RaQ2"; } return "MIPS Cobalt"; } @@ -86,7 +87,8 @@ void __init plat_mem_setup(void) /* These resources have been reserved by VIA SuperI/O chip. */ for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) - request_resource(&ioport_resource, cobalt_reserved_resources + i); + request_resource(&ioport_resource, + cobalt_reserved_resources + i); } /* -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:49:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:49:36 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43544 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903720Ab2FEVta (ORCPT ); Tue, 5 Jun 2012 23:49:30 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1Ab-000824-Mu; Tue, 05 Jun 2012 16:20:05 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 34/35] MIPS: vr41xx: Cleanup firmware support for vr41xx platforms. Date: Tue, 5 Jun 2012 16:19:38 -0500 Message-Id: <1338931179-9611-35-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33524 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 997 Lines: 43 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/vr41xx/common/init.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c index 2391632..a2fa7f0 100644 --- a/arch/mips/vr41xx/common/init.c +++ b/arch/mips/vr41xx/common/init.c @@ -22,8 +22,8 @@ #include #include -#include #include +#include #include #include @@ -59,17 +59,7 @@ void __init plat_mem_setup(void) void __init prom_init(void) { - int argc, i; - char **argv; - - argc = fw_arg0; - argv = (char **)fw_arg1; - - for (i = 1; i < argc; i++) { - strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE); - if (i < (argc - 1)) - strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); - } + fw_init_cmdline(); } void __init prom_free_prom_memory(void) -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:49:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:50:02 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43545 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2FEVtm (ORCPT ); Tue, 5 Jun 2012 23:49:42 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AU-000824-EC; Tue, 05 Jun 2012 16:19:58 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 19/35] MIPS: Loongson: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:23 -0500 Message-Id: <1338931179-9611-20-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33525 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7514 Lines: 178 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mach-loongson/loongson.h | 51 ++++++++++++------------ arch/mips/loongson/common/env.c | 9 +++-- arch/mips/loongson/common/init.c | 10 ++--- 3 files changed, 36 insertions(+), 34 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index b19c5b4..57537e6 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -1,11 +1,12 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #ifndef __ASM_MACH_LOONGSON_LOONGSON_H @@ -80,13 +81,13 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_BOOT_BASE 0x1fc00000 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */ -#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) -#define LOONGSON_REG_BASE 0x1fe00000 -#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ +#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) +#define LOONGSON_REG_BASE 0x1fe00000 +#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) -#define LOONGSON_LIO1_BASE 0x1ff00000 -#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ +#define LOONGSON_LIO1_BASE 0x1ff00000 +#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ #define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1) #define LOONGSON_PCILO0_BASE 0x10000000 @@ -113,13 +114,13 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x)) #define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00) #define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04) -#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) +#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) #define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c) -#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) -#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) -#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) -#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) -#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) +#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) +#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) +#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) +#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) +#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) #define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30) #define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c) @@ -130,7 +131,7 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_PCICMD_MABORT_CLR 0x20000000 #define LOONGSON_PCICMD_MTABORT_CLR 0x10000000 #define LOONGSON_PCICMD_TABORT_CLR 0x08000000 -#define LOONGSON_PCICMD_MPERR_CLR 0x01000000 +#define LOONGSON_PCICMD_MPERR_CLR 0x01000000 #define LOONGSON_PCICMD_PERRRESPEN 0x00000040 #define LOONGSON_PCICMD_ASTEPEN 0x00000080 #define LOONGSON_PCICMD_SERREN 0x00000100 @@ -171,25 +172,25 @@ static inline void do_perfcnt_IRQ(void) /* GPIO Regs - r/w */ -#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) +#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) #define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20) /* ICU Configuration Regs - r/w */ #define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) -#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) +#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) #define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) /* ICU Enable Regs - IntEn & IntISR are r/o. */ -#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) -#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) +#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) +#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) #define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) #define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) /* ICU */ #define LOONGSON_ICU_MBOXES 0x0000000f -#define LOONGSON_ICU_MBOXES_SHIFT 0 +#define LOONGSON_ICU_MBOXES_SHIFT 0 #define LOONGSON_ICU_DMARDY 0x00000010 #define LOONGSON_ICU_DMAEMPTY 0x00000020 #define LOONGSON_ICU_COPYRDY 0x00000040 @@ -210,10 +211,10 @@ static inline void do_perfcnt_IRQ(void) /* PCI prefetch window base & mask */ -#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) -#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) -#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) -#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) +#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) +#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) +#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) +#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) /* PCI_Hit*_Sel_* */ diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c index 681690a..b2cd683 100644 --- a/arch/mips/loongson/common/env.c +++ b/arch/mips/loongson/common/env.c @@ -1,4 +1,8 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Based on Ocelot Linux port, which is * Copyright 2001 MontaVista Software Inc. * Author: jsun@mvista.com or jsun@junsun.net @@ -12,10 +16,7 @@ * Copyright (C) 2009 Lemote Inc. * Author: Wu Zhangjin, wuzhangjin@gmail.com * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c index a40ab27..818ace6 100644 --- a/arch/mips/loongson/common/init.c +++ b/arch/mips/loongson/common/init.c @@ -1,13 +1,13 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright (C) 2009 Lemote Inc. * Author: Wu Zhangjin, wuzhangjin@gmail.com * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include #include -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:49:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:50:25 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43547 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903723Ab2FEVts (ORCPT ); Tue, 5 Jun 2012 23:49:48 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1Ac-000824-Om; Tue, 05 Jun 2012 16:20:06 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 35/35] MIPS: vr41xx: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:39 -0500 Message-Id: <1338931179-9611-36-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33526 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2037 Lines: 54 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/vr41xx/common/init.c | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c index a2fa7f0..783b7f8 100644 --- a/arch/mips/vr41xx/common/init.c +++ b/arch/mips/vr41xx/common/init.c @@ -1,30 +1,15 @@ /* - * init.c, Common initialization routines for NEC VR4100 series. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright (C) 2003-2009 Yoichi Yuasa + * init.c, Common initialization routines for NEC VR4100 series. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * Copyright (C) 2003-2009 Yoichi Yuasa + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ -#include -#include -#include -#include - #include #include -#include #include #define IO_MEM_RESOURCE_START 0UL -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:49:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:50:50 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43550 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903720Ab2FEVt7 (ORCPT ); Tue, 5 Jun 2012 23:49:59 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AR-000824-2z; Tue, 05 Jun 2012 16:19:55 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 12/35] MIPS: jz4740: Cleanup firmware support for the JZ4740 platform. Date: Tue, 5 Jun 2012 16:19:16 -0500 Message-Id: <1338931179-9611-13-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33527 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1023 Lines: 50 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/jz4740/prom.c | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c index 4a70407..c5071ab 100644 --- a/arch/mips/jz4740/prom.c +++ b/arch/mips/jz4740/prom.c @@ -20,33 +20,12 @@ #include -#include +#include #include -static __init void jz4740_init_cmdline(int argc, char *argv[]) -{ - unsigned int count = COMMAND_LINE_SIZE - 1; - int i; - char *dst = &(arcs_cmdline[0]); - char *src; - - for (i = 1; i < argc && count; ++i) { - src = argv[i]; - while (*src && count) { - *dst++ = *src++; - --count; - } - *dst++ = ' '; - } - if (i > 1) - --dst; - - *dst = 0; -} - void __init prom_init(void) { - jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1); + fw_init_cmdline(); mips_machtype = MACH_INGENIC_JZ4740; } -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:50:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:51:16 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43555 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903726Ab2FEVuJ (ORCPT ); Tue, 5 Jun 2012 23:50:09 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AW-000824-Sj; Tue, 05 Jun 2012 16:20:00 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 24/35] MIPS: MSP71xx, Yosemite: Cleanup firmware support for PMC platforms. Date: Tue, 5 Jun 2012 16:19:28 -0500 Message-Id: <1338931179-9611-25-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33528 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 17094 Lines: 605 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- .../mips/include/asm/pmc-sierra/msp71xx/msp_prom.h | 25 ---- arch/mips/pmc-sierra/msp71xx/msp_prom.c | 130 +++++++------------- arch/mips/pmc-sierra/msp71xx/msp_serial.c | 9 +- arch/mips/pmc-sierra/msp71xx/msp_setup.c | 10 +- arch/mips/pmc-sierra/msp71xx/msp_time.c | 26 ++-- arch/mips/pmc-sierra/msp71xx/msp_usb.c | 17 +-- arch/mips/pmc-sierra/yosemite/prom.c | 32 +---- drivers/mtd/maps/pmcmsp-flash.c | 9 +- 8 files changed, 73 insertions(+), 185 deletions(-) diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h index 786d82d..b8c34ff 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h @@ -118,13 +118,9 @@ #define ZSP_DUET 'D' /* one DUET zsp engine */ #define ZSP_TRIAD 'T' /* two TRIAD zsp engines */ -extern char *prom_getenv(char *name); -extern void prom_init_cmdline(void); -extern void prom_meminit(void); extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); -extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr); extern unsigned long get_deviceid(void); extern char identify_enet(unsigned long interface_num); extern char identify_enetTxD(unsigned long interface_num); @@ -147,25 +143,4 @@ extern unsigned long identify_revision(void); printk(_f, ## x); \ } while (0) -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */ - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; - -struct prom_pmemblock { - unsigned long base; /* Within KSEG0. */ - unsigned int size; /* In bytes. */ - unsigned int type; /* free or prom memory */ -}; - -extern int prom_argc; -extern char **prom_argv; -extern char **prom_envp; -extern int *prom_vec; -extern struct prom_pmemblock *prom_getmdesc(void); - #endif /* !_ASM_MSP_PROM_H */ diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c index db00deb..885256f 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_prom.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c @@ -43,23 +43,18 @@ #include #include -#include #include #include +#include #include #include -/* global PROM environment variables and pointers */ -int prom_argc; -char **prom_argv, **prom_envp; -int *prom_vec; - -/* debug flag */ -int init_debug = 1; +/* Global PROM vector */ +int *fw_vec; /* memory blocks */ -struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; +fw_memblock_t mdesc[7]; /* default feature sets */ static char msp_default_features[] = @@ -141,7 +136,7 @@ int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr) { char *ethaddr_str; - ethaddr_str = prom_getenv(ethaddr_name); + ethaddr_str = fw_getenv(ethaddr_name); if (!ethaddr_str) { printk(KERN_WARNING "%s not set in boot prom\n", ethaddr_name); return -1; @@ -168,7 +163,7 @@ EXPORT_SYMBOL(get_ethernet_addr); static char *get_features(void) { - char *feature = prom_getenv(FEATURES); + char *feature = fw_getenv(FEATURES); if (feature == NULL) { /* default features based on MACHINE_TYPE */ @@ -193,7 +188,7 @@ static char test_feature(char c) unsigned long get_deviceid(void) { - char *deviceid = prom_getenv(DEVICEID); + char *deviceid = fw_getenv(DEVICEID); if (deviceid == NULL) return *DEV_ID_REG; @@ -281,72 +276,30 @@ unsigned long identify_revision(void) } EXPORT_SYMBOL(identify_revision); -/* PROM environment functions */ -char *prom_getenv(char *env_name) -{ - /* - * Return a pointer to the given environment variable. prom_envp - * points to a null terminated array of pointers to variables. - * Environment variables are stored in the form of "memsize=64" - */ - - char **var = prom_envp; - int i = strlen(env_name); - - while (*var) { - if (strncmp(env_name, *var, i) == 0) { - return (*var + strlen(env_name) + 1); - } - var++; - } - - return NULL; -} - -/* PROM commandline functions */ -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while (actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; -} - /* memory allocation functions */ -static int __init prom_memtype_classify(unsigned int type) +static int __init fw_memtype_classify(unsigned int type) { switch (type) { - case yamon_free: + case fw_free: return BOOT_MEM_RAM; - case yamon_prom: + case fw_code: return BOOT_MEM_ROM_DATA; default: return BOOT_MEM_RESERVED; } } -void __init prom_meminit(void) +void __init fw_meminit(void) { - struct prom_pmemblock *p; + fw_memblock_t *p; - p = prom_getmdesc(); + p = fw_getmdesc(); while (p->size) { long type; unsigned long base, size; - type = prom_memtype_classify(p->type); + type = fw_memtype_classify(p->type); base = p->base; size = p->size; @@ -369,43 +322,43 @@ void __init prom_free_prom_memory(void) * preserve environment variables and command line from pmon/bbload * first preserve the command line */ - for (argc = 0; argc < prom_argc; argc++) { - len += sizeof(char *); /* length of pointer */ - len += strlen(prom_argv[argc]) + 1; /* length of string */ + for (argc = 0; argc < fw_argc; argc++) { + len += sizeof(int *); /* length of pointer */ + len += strlen(fw_argv(argc)) + 1; /* length of string */ } len += sizeof(char *); /* plus length of null pointer */ argv = kmalloc(len, GFP_KERNEL); - ptr = (char *) &argv[prom_argc + 1]; /* strings follow array */ + ptr = (char *) &argv[fw_argc + 1]; /* strings follow array */ - for (argc = 0; argc < prom_argc; argc++) { + for (argc = 0; argc < fw_argc; argc++) { argv[argc] = ptr; - strcpy(ptr, prom_argv[argc]); - ptr += strlen(prom_argv[argc]) + 1; + strcpy(ptr, fw_argv(argc)); + ptr += strlen(fw_argv(argc)) + 1; } - argv[prom_argc] = NULL; /* end array with null pointer */ - prom_argv = argv; + argv[fw_argc] = NULL; /* end array with null pointer */ + _fw_argv = (int *)argv; /* next preserve the environment variables */ len = 0; i = 0; - for (envp = prom_envp; *envp != NULL; envp++) { + while (fw_envp(i) != NULL) { + len += sizeof(int *); /* length of pointer */ + len += strlen(fw_envp(i)) + 1; /* length of string */ i++; /* count number of environment variables */ - len += sizeof(char *); /* length of pointer */ - len += strlen(*envp) + 1; /* length of string */ } len += sizeof(char *); /* plus length of null pointer */ envp = kmalloc(len, GFP_KERNEL); - ptr = (char *) &envp[i+1]; + ptr = (char *) &envp[i + 1]; for (argc = 0; argc < i; argc++) { envp[argc] = ptr; - strcpy(ptr, prom_envp[argc]); - ptr += strlen(prom_envp[argc]) + 1; + strcpy(ptr, fw_envp(argc)); + ptr += strlen(fw_envp(argc)) + 1; } envp[i] = NULL; /* end array with null pointer */ - prom_envp = envp; + _fw_envp = (int *)envp; for (i = 0; i < boot_mem_map.nr_map; i++) { if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) @@ -417,22 +370,23 @@ void __init prom_free_prom_memory(void) } } -struct prom_pmemblock *__init prom_getmdesc(void) +fw_memblock_t *__init fw_getmdesc(void) { static char memsz_env[] __initdata = "memsize"; static char heaptop_env[] __initdata = "heaptop"; char *str; unsigned int memsize; unsigned int heaptop; - int i; + int i, tmp; + long val; - str = prom_getenv(memsz_env); + str = fw_getenv(memsz_env); if (!str) { - ppfinit("memsize not set in boot prom, " - "set to default (32Mb)\n"); + ppfinit("memsize not set in firmware, set to default (32Mb)\n"); memsize = 0x02000000; } else { - memsize = simple_strtol(str, NULL, 0); + tmp = kstrtol(str, 0, &val); + memsize = (unsigned int)val; if (memsize == 0) { /* if memsize is a bad size, use reasonable default */ @@ -443,16 +397,18 @@ struct prom_pmemblock *__init prom_getmdesc(void) memsize = CPHYSADDR(memsize); } - str = prom_getenv(heaptop_env); + str = fw_getenv(heaptop_env); if (!str) { heaptop = CPHYSADDR((u32)&_text); ppfinit("heaptop not set in boot prom, " "set to default 0x%08x\n", heaptop); } else { - heaptop = simple_strtol(str, NULL, 16); + tmp = kstrtol(str, 16, &val); + heaptop = (unsigned int)val; if (heaptop == 0) { /* heaptop conversion bad, might have 0xValue */ - heaptop = simple_strtol(str, NULL, 0); + tmp = kstrtol(str, 0, &val); + heaptop = (unsigned int)val; if (heaptop == 0) { /* heaptop still bad, use reasonable default */ @@ -495,7 +451,7 @@ struct prom_pmemblock *__init prom_getmdesc(void) /* Remainder of RAM -- under memsize */ i++; /* 5 */ - mdesc[i].type = yamon_free; + mdesc[i].type = fw_free; mdesc[i].base = mdesc[i-1].base + mdesc[i-1].size; mdesc[i].size = memsize - mdesc[i].base; diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c index a1c7c7d..7080bce 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c @@ -29,12 +29,13 @@ #include #include -#include #include #include #include #include +#include + #include #include #include @@ -90,16 +91,14 @@ static int msp_serial_handle_irq(struct uart_port *p) void __init msp_serial_setup(void) { - char *s; - char *endp; struct uart_port up; unsigned int uartclk; memset(&up, 0, sizeof(up)); /* Check if clock was specified in environment */ - s = prom_getenv("uartfreqhz"); - if(!(s && *s && (uartclk = simple_strtoul(s, &endp, 10)) && *endp == 0)) + uartclk = (unsigned int) fw_getenvl("uartfreqhz"); + if (uartclk == 0) uartclk = MSP_BASE_BAUD; ppfinit("UART clock set to %d\n", uartclk); diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index 7a834b2..6fa0d76 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -10,12 +10,12 @@ * option) any later version. */ -#include #include #include #include #include #include +#include #include #include @@ -154,10 +154,6 @@ void __init prom_init(void) unsigned long family; unsigned long revision; - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; - /* * Someday we can use this with PMON2000 to get a * platform call prom routines for output etc. without @@ -213,9 +209,9 @@ void __init prom_init(void) break; } - prom_init_cmdline(); + fw_init_cmdline(); - prom_meminit(); + fw_meminit(); /* * Sub-system setup follows. diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index 8b42f30..d76cbdb 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -32,8 +32,8 @@ #include #include #include +#include -#include #include #include @@ -45,26 +45,16 @@ static int tim_installed; void __init plat_time_init(void) { - char *endp, *s; - unsigned long cpu_rate = 0; + unsigned long cpu_rate; - if (cpu_rate == 0) { - s = prom_getenv("clkfreqhz"); - cpu_rate = simple_strtoul(s, &endp, 10); - if (endp != NULL && *endp != 0) { - printk(KERN_ERR - "Clock rate in Hz parse error: %s\n", s); - cpu_rate = 0; - } - } + cpu_rate = fw_getenvl("clkfreqhz"); + if (cpu_rate == 0) + printk(KERN_ERR "Clock rate in Hz parse error: %s\n", s); if (cpu_rate == 0) { - s = prom_getenv("clkfreq"); - cpu_rate = 1000 * simple_strtoul(s, &endp, 10); - if (endp != NULL && *endp != 0) { - printk(KERN_ERR - "Clock rate in MHz parse error: %s\n", s); - cpu_rate = 0; + cpu_rate = 1000 * fw_getenvl("clkfreq"); + if (cpu_rate == 0) + printk(KERN_ERR "Clock rate in MHz parse error: %s\n", s); } } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c index 9a1aef8..ee4ed9b 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c @@ -30,6 +30,7 @@ #include #include +#include #include #include @@ -201,26 +202,20 @@ static struct mspusb_device msp_usbdev1_device = { static int __init msp_usb_setup(void) { - char *strp; - char envstr[32]; struct platform_device *msp_devs[NUM_USB_DEVS]; + char *strp; unsigned int val; - /* construct environment name usbmode */ - /* set usbmode as pmon environment var */ + /* set default host mode */ + val = 1; + /* * Could this perhaps be integrated into the "features" env var? * Use the features key "U", and follow with "H" for host-mode, * "D" for device-mode. If it works for Ethernet, why not USB... * -- hammtrev, 2007/03/22 */ - snprintf((char *)&envstr[0], sizeof(envstr), "usbmode"); - - /* set default host mode */ - val = 1; - - /* get environment string */ - strp = prom_getenv((char *)&envstr[0]); + strp = fw_getenv("usbmode"); if (strp) { /* compare string */ if (!strcmp(strp, "device")) diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c index 6a2754c..b4ce648 100644 --- a/arch/mips/pmc-sierra/yosemite/prom.c +++ b/arch/mips/pmc-sierra/yosemite/prom.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #ifdef CONFIG_SMP @@ -85,11 +85,7 @@ extern struct plat_smp_ops yos_smp_ops; */ void __init prom_init(void) { - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; struct callvectors *cv = (struct callvectors *) fw_arg3; - int i = 0; /* Callbacks for halt, restart */ _machine_restart = (void (*)(char *)) prom_exit; @@ -97,36 +93,16 @@ void __init prom_init(void) pm_power_off = prom_halt; debug_vectors = cv; - arcs_cmdline[0] = '\0'; - /* Get the boot parameters */ - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i]) + 1 >= - sizeof(arcs_cmdline)) - break; - - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } + fw_init_cmdline(); #ifdef CONFIG_SERIAL_8250_CONSOLE if ((strstr(arcs_cmdline, "console=ttyS")) == NULL) strcat(arcs_cmdline, "console=ttyS0,115200"); #endif - while (*env) { - if (strncmp("ocd_base", *env, strlen("ocd_base")) == 0) - yosemite_base = - simple_strtol(*env + strlen("ocd_base="), NULL, - 16); - - if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) - cpu_clock_freq = - simple_strtol(*env + strlen("cpuclock="), NULL, - 10); - - env++; - } + yosemite_base = fw_getenvl("ocd_base"); + cpu_clock_freq = fw_getenvl("cpuclock"); prom_grab_secondary(); diff --git a/drivers/mtd/maps/pmcmsp-flash.c b/drivers/mtd/maps/pmcmsp-flash.c index 744ca5c..c19d9e4 100644 --- a/drivers/mtd/maps/pmcmsp-flash.c +++ b/drivers/mtd/maps/pmcmsp-flash.c @@ -37,6 +37,7 @@ #include #include +#include #include #include @@ -67,7 +68,7 @@ static int __init init_msp_flash(void) } /* examine the prom environment for flash devices */ - for (fcnt = 0; (env = prom_getenv(flash_name)); fcnt++) + for (fcnt = 0; (env = fw_getenv(flash_name)); fcnt++) flash_name[5] = '0' + fcnt + 1; if (fcnt < 1) @@ -92,7 +93,7 @@ static int __init init_msp_flash(void) /* examine the prom environment for flash partititions */ part_name[5] = '0' + i; part_name[7] = '0'; - for (pcnt = 0; (env = prom_getenv(part_name)); pcnt++) + for (pcnt = 0; (env = fw_getenv(part_name)); pcnt++) part_name[7] = '0' + pcnt + 1; if (pcnt == 0) { @@ -108,7 +109,7 @@ static int __init init_msp_flash(void) /* now initialize the devices proper */ flash_name[5] = '0' + i; - env = prom_getenv(flash_name); + env = fw_getenv(flash_name); if (sscanf(env, "%x:%x", &addr, &size) < 2) { ret = -ENXIO; @@ -152,7 +153,7 @@ static int __init init_msp_flash(void) part_name[5] = '0' + i; part_name[7] = '0' + j; - env = prom_getenv(part_name); + env = fw_getenv(part_name); if (sscanf(env, "%x:%x:%n", &offset, &size, &coff) < 2) { -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:50:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:51:40 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43556 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2FEVuU (ORCPT ); Tue, 5 Jun 2012 23:50:20 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AR-000824-Hb; Tue, 05 Jun 2012 16:19:55 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 13/35] MIPS: jz4740: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:17 -0500 Message-Id: <1338931179-9611-14-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33529 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1862 Lines: 58 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/jz4740/prom.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c index c5071ab..ea86605 100644 --- a/arch/mips/jz4740/prom.c +++ b/arch/mips/jz4740/prom.c @@ -1,23 +1,14 @@ /* - * Copyright (C) 2010, Lars-Peter Clausen - * JZ4740 SoC prom code + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * JZ4740 SoC prom code * + * Copyright (C) 2010, Lars-Peter Clausen + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include -#include -#include -#include - #include #include @@ -33,7 +24,9 @@ void __init prom_free_prom_memory(void) { } -#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2))) +#define UART_REG(_reg) \ + ((volatile void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + \ + (_reg << 2))) void prom_putchar(char c) { -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:50:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:52:07 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43558 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903737Ab2FEVua (ORCPT ); Tue, 5 Jun 2012 23:50:30 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1Aa-000824-NU; Tue, 05 Jun 2012 16:20:04 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 32/35] MIPS: txx9: Cleanup firmware support for txx9 platforms. Date: Tue, 5 Jun 2012 16:19:36 -0500 Message-Id: <1338931179-9611-33-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33530 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3191 Lines: 122 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/txx9/generic.h | 1 - arch/mips/txx9/generic/setup.c | 56 ++-------------------------------- 2 files changed, 3 insertions(+), 54 deletions(-) diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h index 64887d3..4127a38 100644 --- a/arch/mips/include/asm/txx9/generic.h +++ b/arch/mips/include/asm/txx9/generic.h @@ -42,7 +42,6 @@ struct txx9_board_vec { }; extern struct txx9_board_vec *txx9_board_vec; extern int (*txx9_irq_dispatch)(int pending); -const char *prom_getenv(const char *name); void txx9_wdt_init(unsigned long base); void txx9_wdt_now(unsigned long base); void txx9_spi_init(int busid, unsigned long base, int irq); diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index ae77a79..8a053d6 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -25,11 +25,11 @@ #include #include #include -#include #include #include #include #include +#include #include #include #include @@ -157,39 +157,6 @@ static struct txx9_board_vec *__init find_board_byname(const char *name) return NULL; } -static void __init prom_init_cmdline(void) -{ - int argc; - int *argv32; - int i; /* Always ignore the "-c" at argv[0] */ - - if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { - /* - * argc is not a valid number, or argv32 is not a valid - * pointer - */ - argc = 0; - argv32 = NULL; - } else { - argc = (int)fw_arg0; - argv32 = (int *)fw_arg1; - } - - arcs_cmdline[0] = '\0'; - - for (i = 1; i < argc; i++) { - char *str = (char *)(long)argv32[i]; - if (i != 1) - strcat(arcs_cmdline, " "); - if (strchr(str, ' ')) { - strcat(arcs_cmdline, "\""); - strcat(arcs_cmdline, str); - strcat(arcs_cmdline, "\""); - } else - strcat(arcs_cmdline, str); - } -} - static int txx9_ic_disable __initdata; static int txx9_dc_disable __initdata; @@ -341,7 +308,7 @@ static void __init select_board(void) if (txx9_board_vec) return; /* next, determine by "board" envvar */ - envstr = prom_getenv("board"); + envstr = fw_getenv("board"); if (envstr) { txx9_board_vec = find_board_byname(envstr); if (txx9_board_vec) @@ -378,7 +345,7 @@ static void __init select_board(void) void __init prom_init(void) { - prom_init_cmdline(); + fw_init_cmdline(); preprocess_cmdline(); select_board(); @@ -401,23 +368,6 @@ const char *get_system_type(void) return txx9_system_type; } -const char *__init prom_getenv(const char *name) -{ - const s32 *str; - - if (fw_arg2 < CKSEG0) - return NULL; - - str = (const s32 *)fw_arg2; - /* YAMON style ("name", "value" pairs) */ - while (str[0] && str[1]) { - if (!strcmp((const char *)(unsigned long)str[0], name)) - return (const char *)(unsigned long)str[1]; - str += 2; - } - return NULL; -} - static void __noreturn txx9_machine_halt(void) { local_irq_disable(); -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:50:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:52:30 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43560 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903743Ab2FEVug (ORCPT ); Tue, 5 Jun 2012 23:50:36 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AV-000824-Ty; Tue, 05 Jun 2012 16:19:59 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 22/35] MIPS: Netlogic: Cleanup firmware support for the XLR platform. Date: Tue, 5 Jun 2012 16:19:26 -0500 Message-Id: <1338931179-9611-23-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33531 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2574 Lines: 98 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/netlogic/xlr/setup.c | 47 +++++++++------------------------------- 1 file changed, 10 insertions(+), 37 deletions(-) diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index c9d066d..113a402 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -38,7 +38,7 @@ #include #include -#include +#include #include #include @@ -113,45 +113,21 @@ void __init prom_free_prom_memory(void) /* Nothing yet */ } -static void __init build_arcs_cmdline(int *argv) +static void __init build_arcs_cmdline(void) { - int i, remain, len; - char *arg; - - remain = sizeof(arcs_cmdline) - 1; - arcs_cmdline[0] = '\0'; - for (i = 0; argv[i] != 0; i++) { - arg = (char *)(long)argv[i]; - len = strlen(arg); - if (len + 1 > remain) - break; - strcat(arcs_cmdline, arg); - strcat(arcs_cmdline, " "); - remain -= len + 1; - } + fw_init_cmdline(); /* Add the default options here */ - if ((strstr(arcs_cmdline, "console=")) == NULL) { - arg = "console=ttyS0,38400 "; - len = strlen(arg); - if (len > remain) - goto fail; - strcat(arcs_cmdline, arg); - remain -= len; + if ((strstr(fw_getcmdline(), "console=")) == NULL) { + strlcat(fw_getcmdline(), "console=ttyS0,38400 ", + COMMAND_LINE_SIZE); } #ifdef CONFIG_BLK_DEV_INITRD - if ((strstr(arcs_cmdline, "rdinit=")) == NULL) { - arg = "rdinit=/sbin/init "; - len = strlen(arg); - if (len > remain) - goto fail; - strcat(arcs_cmdline, arg); - remain -= len; + if ((strstr(fw_getcmdline(), "rdinit=")) == NULL) { + strlcat(fw_getcmdline(), "rdinit=/sbin/init ", + COMMAND_LINE_SIZE); } #endif - return; -fail: - panic("Cannot add %s, command line too big!", arg); } static void prom_add_memory(void) @@ -178,19 +154,16 @@ static void prom_add_memory(void) void __init prom_init(void) { - int *argv, *envp; /* passed as 32 bit ptrs */ struct psb_info *prom_infop; /* truncate to 32 bit and sign extend all args */ - argv = (int *)(long)(int)fw_arg1; - envp = (int *)(long)(int)fw_arg2; prom_infop = (struct psb_info *)(long)(int)fw_arg3; nlm_prom_info = *prom_infop; nlm_pic_base = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET); nlm_early_serial_setup(); - build_arcs_cmdline(argv); + build_arcs_cmdline(); nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); prom_add_memory(); -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:50:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:52:59 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43562 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903723Ab2FEVuo (ORCPT ); Tue, 5 Jun 2012 23:50:44 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AV-000824-E8; Tue, 05 Jun 2012 16:19:59 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 21/35] MIPS: Malta: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:25 -0500 Message-Id: <1338931179-9611-22-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33532 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 18756 Lines: 555 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mips-boards/generic.h | 21 ++---- arch/mips/mti-malta/malta-display.c | 39 ++++------ arch/mips/mti-malta/malta-init.c | 108 +++++++-------------------- arch/mips/mti-malta/malta-memory.c | 34 +++------ arch/mips/mti-malta/malta-setup.c | 52 +++++-------- arch/mips/mti-malta/malta-time.c | 64 ++++++---------- 6 files changed, 98 insertions(+), 220 deletions(-) diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index cf20a30..d99f5b6 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -1,21 +1,14 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive * for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * * Defines of the MIPS boards specific address-MAP, registers, etc. + * + * Copyright (C) 2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ #ifndef __ASM_MIPS_BOARDS_GENERIC_H #define __ASM_MIPS_BOARDS_GENERIC_H diff --git a/arch/mips/mti-malta/malta-display.c b/arch/mips/mti-malta/malta-display.c index 2a0057c..04826d7 100644 --- a/arch/mips/mti-malta/malta-display.c +++ b/arch/mips/mti-malta/malta-display.c @@ -1,26 +1,19 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Display routines for display messages in MIPS boards ascii display. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ - #include #include -#include +#include + #include extern const char display_string[]; @@ -29,17 +22,17 @@ static unsigned int max_display_count; void mips_display_message(const char *str) { - static unsigned int __iomem *display = NULL; + static unsigned int __iomem *display; int i; if (unlikely(display == NULL)) display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int)); - for (i = 0; i <= 14; i=i+2) { - if (*str) - __raw_writel(*str++, display + i); - else - __raw_writel(' ', display + i); + for (i = 0; i <= 14; i += 2) { + if (*str) + __raw_writel(*str++, display + i); + else + __raw_writel(' ', display + i); } } diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 9844f31..8e7dfcd 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -1,40 +1,22 @@ /* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * PROM library initialisation code. + * + * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * Steven J. Hill */ -#include -#include -#include - -#include -#include #include #include #include - #include #include #include -#include -#include - #include extern void mips_display_message(const char *str); @@ -52,52 +34,6 @@ unsigned long _pcictrl_gt64120; /* MIPS System controller register base */ unsigned long _pcictrl_msc; -static inline unsigned char str2hexnum(unsigned char c) -{ - if (c >= '0' && c <= '9') - return c - '0'; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return 0; /* foo */ -} - -static inline void str2eaddr(unsigned char *ea, unsigned char *str) -{ - int i; - - for (i = 0; i < 6; i++) { - unsigned char num; - - if((*str == '.') || (*str == ':')) - str++; - num = str2hexnum(*str++) << 4; - num |= (str2hexnum(*str++)); - ea[i] = num; - } -} - -int get_ethernet_addr(char *ethernet_addr) -{ - char *ethaddr_str; - - ethaddr_str = prom_getenv("ethaddr"); - if (!ethaddr_str) { - printk("ethaddr not set in boot prom\n"); - return -1; - } - str2eaddr(ethernet_addr, ethaddr_str); - - if (init_debug > 1) { - int i; - printk("get_ethernet_addr: "); - for (i=0; i<5; i++) - printk("%02x:", (unsigned char)*(ethernet_addr+i)); - printk("%02x\n", *(ethernet_addr+i)); - } - - return 0; -} - #ifdef CONFIG_SERIAL_8250_CONSOLE static void __init console_config(void) { @@ -111,12 +47,18 @@ static void __init console_config(void) if (s) { while (*s >= '0' && *s <= '9') baud = baud*10 + *s++ - '0'; - if (*s == ',') s++; - if (*s) parity = *s++; - if (*s == ',') s++; - if (*s) bits = *s++; - if (*s == ',') s++; - if (*s == 'h') flow = 'r'; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; } if (baud == 0) baud = 38400; @@ -126,7 +68,8 @@ static void __init console_config(void) bits = '8'; if (flow == '\0') flow = 'r'; - sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, + parity, bits, flow); strcat(fw_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } @@ -270,7 +213,7 @@ void __init prom_init(void) case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); - mips_pci_controller: +mips_pci_controller: mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); @@ -312,14 +255,13 @@ void __init prom_init(void) default: /* Unknown system controller */ mips_display_message("SC Error"); - while (1); /* We die here... */ + while (1); /* We die here... */ } board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; fw_init_cmdline(); fw_meminit(); - #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index cddcd46..4cdcc88 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -1,30 +1,19 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * PROM library functions for acquiring/using memory descriptors given to * us from the YAMON. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ -#include -#include #include -#include -#include -#include +#include #include #include @@ -92,7 +81,8 @@ fw_memblock_t * __init fw_getmdesc(void) mdesc[3].type = fw_dontuse; mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - + mdesc[3].base; mdesc[4].type = fw_free; mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); @@ -128,7 +118,7 @@ void __init fw_meminit(void) size = p->size; add_memory_region(base, size, type); - p++; + p++; } } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 08cdf8f..f50f053 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -1,39 +1,22 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2008 Dmitri Vorobiev - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. + * Copyright (C) 2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * Copyright (C) 2008 Dmitri Vorobiev */ -#include -#include -#include -#include -#include #include #include -#include -#include -#include -#include -#include #include #include -#ifdef CONFIG_VT -#include -#endif +#include +#include extern void malta_be_init(void); extern int malta_be_handler(struct pt_regs *regs, int is_fixup); @@ -117,13 +100,12 @@ static void __init pci_clock_check(void) char *argptr = fw_getcmdline(); if (pciclock != 33 && !strstr(argptr, "idebus=")) { - printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " - "setting idebus\n", pciclock); + pr_warn("WARNING: PCI clock is %dMHz, setting idebus\n", + pciclock); argptr += strlen(argptr); sprintf(argptr, " idebus=%d", pciclock); if (pciclock < 20 || pciclock > 66) - printk(KERN_WARNING "WARNING: IDE timing " - "calculations will be incorrect\n"); + pr_warn("WARNING: IDE timing calculations will be incorrect\n"); } } #endif @@ -155,14 +137,14 @@ static void __init bonito_quirks_setup(void) argptr = fw_getcmdline(); if (strstr(argptr, "debug")) { BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; - printk(KERN_INFO "Enabled Bonito debug mode\n"); + pr_info("Enabled Bonito debug mode\n"); } else BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; #ifdef CONFIG_DMA_COHERENT if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; - printk(KERN_INFO "Enabled Bonito CPU coherency\n"); + pr_info("Enabled Bonito CPU coherency\n"); argptr = fw_getcmdline(); if (strstr(argptr, "iobcuncached")) { @@ -170,13 +152,13 @@ static void __init bonito_quirks_setup(void) BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Disabled Bonito IOBC coherency\n"); + pr_info("Disabled Bonito IOBC coherency\n"); } else { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG |= (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Enabled Bonito IOBC coherency\n"); + pr_info("Enabled Bonito IOBC coherency\n"); } } else panic("Hardware DMA cache coherency not supported"); diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 8a5d589..4574730 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -1,47 +1,21 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Setting up the clock on the MIPS boards. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ - -#include #include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include + #include #include #include -#include - #include - #include unsigned long cpu_khz; @@ -74,15 +48,19 @@ static unsigned int __init estimate_cpu_frequency(void) local_irq_save(flags); /* Start counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + while (CMOS_READ(RTC_REG_A) & RTC_UIP) + ; + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)) + ; /* Start r4k counter. */ start = read_c0_count(); /* Read counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + while (CMOS_READ(RTC_REG_A) & RTC_UIP) + ; + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)) + ; count = read_c0_count() - start; @@ -145,15 +123,15 @@ void __init plat_time_init(void) { unsigned int est_freq; - /* Set Data mode - binary. */ - CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); + /* Set Data mode - binary. */ + CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); est_freq = estimate_cpu_frequency(); - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + pr_info("CPU frequency %d.%02d MHz\n", est_freq/1000000, (est_freq%1000000)*100/1000000); - cpu_khz = est_freq / 1000; + cpu_khz = est_freq / 1000; mips_scroll_message(); #ifdef CONFIG_I8253 /* Only Malta has a PIT */ -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:50:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:53:27 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43564 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903738Ab2FEVuv (ORCPT ); Tue, 5 Jun 2012 23:50:51 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AX-000824-R2; Tue, 05 Jun 2012 16:20:01 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 26/35] MIPS: PNX83xx, PNX8550: Cleanup firmware support for PNX platforms. Date: Tue, 5 Jun 2012 16:19:30 -0500 Message-Id: <1338931179-9611-27-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33533 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10744 Lines: 411 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/pnx833x/common/Makefile | 2 +- arch/mips/pnx833x/common/prom.c | 64 ----------------- arch/mips/pnx833x/common/setup.c | 4 ++ arch/mips/pnx833x/stb22x/board.c | 25 ++----- arch/mips/pnx8550/common/Makefile | 2 +- arch/mips/pnx8550/common/prom.c | 128 ---------------------------------- arch/mips/pnx8550/common/setup.c | 7 +- arch/mips/pnx8550/jbs/init.c | 9 +-- arch/mips/pnx8550/stb810/prom_init.c | 13 +--- 9 files changed, 21 insertions(+), 233 deletions(-) delete mode 100644 arch/mips/pnx833x/common/prom.c delete mode 100644 arch/mips/pnx8550/common/prom.c diff --git a/arch/mips/pnx833x/common/Makefile b/arch/mips/pnx833x/common/Makefile index 1a46dd2..abda463 100644 --- a/arch/mips/pnx833x/common/Makefile +++ b/arch/mips/pnx833x/common/Makefile @@ -1 +1 @@ -obj-y := interrupts.o platform.o prom.o setup.o reset.o +obj-y := interrupts.o platform.o setup.o reset.o diff --git a/arch/mips/pnx833x/common/prom.c b/arch/mips/pnx833x/common/prom.c deleted file mode 100644 index 29969f9..0000000 --- a/arch/mips/pnx833x/common/prom.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * prom.c: - * - * Copyright 2008 NXP Semiconductors - * Chris Steel - * Daniel Laird - * - * Based on software written by: - * Nikita Youshchenko , based on PNX8550 code. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -void __init prom_init_cmdline(void) -{ - int argc = fw_arg0; - char **argv = (char **)fw_arg1; - char *c = &(arcs_cmdline[0]); - int i; - - for (i = 1; i < argc; i++) { - strcpy(c, argv[i]); - c += strlen(argv[i]); - if (i < argc-1) - *c++ = ' '; - } - *c = 0; -} - -char __init *prom_getenv(char *envname) -{ - extern char **prom_envp; - char **env = prom_envp; - int i; - - i = strlen(envname); - - while (*env) { - if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=') - return *env + i + 1; - env++; - } - - return 0; -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/pnx833x/common/setup.c b/arch/mips/pnx833x/common/setup.c index e51fbc4..3ea4926 100644 --- a/arch/mips/pnx833x/common/setup.c +++ b/arch/mips/pnx833x/common/setup.c @@ -36,6 +36,10 @@ extern void pnx833x_machine_restart(char *); extern void pnx833x_machine_halt(void); extern void pnx833x_machine_power_off(void); +void __init prom_free_prom_memory(void) +{ +} + int __init plat_mem_setup(void) { /* fake pci bus to avoid bounce buffers */ diff --git a/arch/mips/pnx833x/stb22x/board.c b/arch/mips/pnx833x/stb22x/board.c index 644eb7c..cdf1a3b 100644 --- a/arch/mips/pnx833x/stb22x/board.c +++ b/arch/mips/pnx833x/stb22x/board.c @@ -23,8 +23,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include #include +#include #include #include @@ -38,34 +38,23 @@ #define PNX8335_DEBUG6 0x4418 #define PNX8335_DEBUG7 0x441c -int prom_argc; -char **prom_argv, **prom_envp; - -extern void prom_init_cmdline(void); -extern char *prom_getenv(char *envname); - const char *get_system_type(void) { return "NXP STB22x"; } -static inline unsigned long env_or_default(char *env, unsigned long dfl) -{ - char *str = prom_getenv(env); - return str ? simple_strtol(str, 0, 0) : dfl; -} - void __init prom_init(void) { unsigned long memsize; - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; + fw_init_cmdline(); - prom_init_cmdline(); + memsize = fw_getenvl("memsize"); + if (!memsize) { + pr_warn("memsize not set by firmware, setting to 32MB\n"); + memsize = 0x02000000; + } - memsize = env_or_default("memsize", 0x02000000); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/arch/mips/pnx8550/common/Makefile b/arch/mips/pnx8550/common/Makefile index f8ce695..32f5399 100644 --- a/arch/mips/pnx8550/common/Makefile +++ b/arch/mips/pnx8550/common/Makefile @@ -22,5 +22,5 @@ # under Linux. # -obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o +obj-y := setup.o int.o reset.o time.o proc.o platform.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/pnx8550/common/prom.c b/arch/mips/pnx8550/common/prom.c deleted file mode 100644 index 49639e8..0000000 --- a/arch/mips/pnx8550/common/prom.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * - * Per Hallsmark, per.hallsmark@mvista.com - * - * Based on jmr3927/common/prom.c - * - * 2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include - -#include -#include - -/* #define DEBUG_CMDLINE */ - -extern int prom_argc; -extern char **prom_argv, **prom_envp; - -typedef struct -{ - char *name; -/* char *val; */ -}t_env_var; - - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - int i; - - arcs_cmdline[0] = '\0'; - for (i = 0; i < prom_argc; i++) { - strcat(arcs_cmdline, prom_argv[i]); - strcat(arcs_cmdline, " "); - } -} - -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - * Environment variables are stored in the form of "memsize=64". - */ - - t_env_var *env = (t_env_var *)prom_envp; - int i; - - i = strlen(envname); - - while(env->name) { - if(strncmp(envname, env->name, i) == 0) { - return(env->name + strlen(envname) + 1); - } - env++; - } - return(NULL); -} - -inline unsigned char str2hexnum(unsigned char c) -{ - if(c >= '0' && c <= '9') - return c - '0'; - if(c >= 'a' && c <= 'f') - return c - 'a' + 10; - if(c >= 'A' && c <= 'F') - return c - 'A' + 10; - return 0; /* foo */ -} - -inline void str2eaddr(unsigned char *ea, unsigned char *str) -{ - int i; - - for(i = 0; i < 6; i++) { - unsigned char num; - - if((*str == '.') || (*str == ':')) - str++; - num = str2hexnum(*str++) << 4; - num |= (str2hexnum(*str++)); - ea[i] = num; - } -} - -int get_ethernet_addr(char *ethernet_addr) -{ - char *ethaddr_str; - - ethaddr_str = prom_getenv("ethaddr"); - if (!ethaddr_str) { - printk("ethaddr not set in boot prom\n"); - return -1; - } - str2eaddr(ethernet_addr, ethaddr_str); - return 0; -} - -void __init prom_free_prom_memory(void) -{ -} - -extern int pnx8550_console_port; - -/* used by early printk */ -void prom_putchar(char c) -{ - if (pnx8550_console_port != -1) { - /* Wait until FIFO not full */ - while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) >= 16) - ; - /* Send one char */ - ip3106_fifo(UART_BASE, pnx8550_console_port) = c; - } -} - -EXPORT_SYMBOL(get_ethernet_addr); -EXPORT_SYMBOL(str2eaddr); diff --git a/arch/mips/pnx8550/common/setup.c b/arch/mips/pnx8550/common/setup.c index fccd6b0..b8ae54c 100644 --- a/arch/mips/pnx8550/common/setup.c +++ b/arch/mips/pnx8550/common/setup.c @@ -28,10 +28,10 @@ #include #include -#include #include #include #include +#include #include #include @@ -46,7 +46,6 @@ extern void pnx8550_machine_restart(char *); extern void pnx8550_machine_halt(void); extern struct resource ioport_resource; extern struct resource iomem_resource; -extern char *prom_getcmdline(void); struct resource standard_io_resources[] = { { @@ -128,8 +127,8 @@ void __init plat_mem_setup(void) (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT), PNX8550_GPIO_MC1); - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "console=ttyS")) != NULL) { + argptr = strstr(fw_getcmdline(), "console=ttyS"); + if (argptr != NULL) { argptr += strlen("console=ttyS"); pnx8550_console_port = *argptr == '0' ? 0 : 1; diff --git a/arch/mips/pnx8550/jbs/init.c b/arch/mips/pnx8550/jbs/init.c index d59b4a4..e682446 100644 --- a/arch/mips/pnx8550/jbs/init.c +++ b/arch/mips/pnx8550/jbs/init.c @@ -29,15 +29,10 @@ #include #include #include -#include +#include #include #include -int prom_argc; -char **prom_argv, **prom_envp; -extern void __init prom_init_cmdline(void); -extern char *prom_getenv(char *envname); - const char *get_system_type(void) { return "NXP PNX8550/JBS"; @@ -47,6 +42,8 @@ void __init prom_init(void) { unsigned long memsize; + fw_init_cmdline(); + //memsize = 0x02800000; /* Trimedia uses memory above */ memsize = 0x08000000; /* Trimedia uses memory above */ add_memory_region(0, memsize, BOOT_MEM_RAM); diff --git a/arch/mips/pnx8550/stb810/prom_init.c b/arch/mips/pnx8550/stb810/prom_init.c index ca7f4ad..cb1b052 100644 --- a/arch/mips/pnx8550/stb810/prom_init.c +++ b/arch/mips/pnx8550/stb810/prom_init.c @@ -17,15 +17,10 @@ #include #include #include -#include +#include #include #include -int prom_argc; -char **prom_argv, **prom_envp; -extern void __init prom_init_cmdline(void); -extern char *prom_getenv(char *envname); - const char *get_system_type(void) { return "NXP PNX8950/STB810"; @@ -35,11 +30,7 @@ void __init prom_init(void) { unsigned long memsize; - prom_argc = (int) fw_arg0; - prom_argv = (char **) fw_arg1; - prom_envp = (char **) fw_arg2; - - prom_init_cmdline(); + fw_init_cmdline(); memsize = 0x08000000; /* Trimedia uses memory above */ add_memory_region(0, memsize, BOOT_MEM_RAM); -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:51:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:53:51 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43567 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903739Ab2FEVvC (ORCPT ); Tue, 5 Jun 2012 23:51:02 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AU-000824-VE; Tue, 05 Jun 2012 16:19:58 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 20/35] MIPS: Malta: Cleanup firmware support for the Malta platform. Date: Tue, 5 Jun 2012 16:19:24 -0500 Message-Id: <1338931179-9611-21-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33534 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 14920 Lines: 506 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mips-boards/generic.h | 9 +--- arch/mips/include/asm/mips-boards/prom.h | 47 ----------------- arch/mips/mti-malta/Makefile | 2 +- arch/mips/mti-malta/malta-cmdline.c | 59 --------------------- arch/mips/mti-malta/malta-display.c | 1 - arch/mips/mti-malta/malta-init.c | 51 +++--------------- arch/mips/mti-malta/malta-memory.c | 76 ++++++++------------------- arch/mips/mti-malta/malta-setup.c | 9 ++-- arch/mips/mti-malta/malta-time.c | 1 - 9 files changed, 38 insertions(+), 217 deletions(-) delete mode 100644 arch/mips/include/asm/mips-boards/prom.h delete mode 100644 arch/mips/mti-malta/malta-cmdline.c diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index 6e23ceb..cf20a30 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -30,13 +30,6 @@ #define ASCII_DISPLAY_WORD_BASE 0x1f000410 #define ASCII_DISPLAY_POS_BASE 0x1f000418 - -/* - * Yamon Prom print address. - */ -#define YAMON_PROM_PRINT_ADDR 0x1fc00504 - - /* * Reset register. */ @@ -93,4 +86,6 @@ extern void mips_pcibios_init(void); #define mips_pcibios_init() do { } while (0) #endif +extern void mips_scroll_message(void); + #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h deleted file mode 100644 index a9db576..0000000 --- a/arch/mips/include/asm/mips-boards/prom.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * MIPS boards bootprom interface for the Linux kernel. - * - */ - -#ifndef _MIPS_PROM_H -#define _MIPS_PROM_H - -extern char *prom_getcmdline(void); -extern char *prom_getenv(char *name); -extern void prom_init_cmdline(void); -extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); -extern void mips_display_message(const char *str); -extern void mips_display_word(unsigned int num); -extern void mips_scroll_message(void); -extern int get_ethernet_addr(char *ethernet_addr); - -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - unsigned long base; /* Within KSEG0. */ - unsigned int size; /* In bytes. */ - unsigned int type; /* free or prom memory */ -}; - -#endif /* !(_MIPS_PROM_H) */ diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile index 6079ef3..8d64bd4 100644 --- a/arch/mips/mti-malta/Makefile +++ b/arch/mips/mti-malta/Makefile @@ -5,7 +5,7 @@ # Copyright (C) 2008 Wind River Systems, Inc. # written by Ralf Baechle # -obj-y := malta-amon.o malta-cmdline.o \ +obj-y := malta-amon.o \ malta-display.o malta-init.o malta-int.o \ malta-memory.o malta-platform.o \ malta-reset.o malta-setup.o malta-time.o diff --git a/arch/mips/mti-malta/malta-cmdline.c b/arch/mips/mti-malta/malta-cmdline.c deleted file mode 100644 index 1871c30..0000000 --- a/arch/mips/mti-malta/malta-cmdline.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Kernel command line creation using the prom monitor (YAMON) argc/argv. - */ -#include -#include - -#include - -extern int prom_argc; -extern int *_prom_argv; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension. - */ -#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv(actr)); - cp += strlen(prom_argv(actr)); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) { - /* get rid of trailing space */ - --cp; - *cp = '\0'; - } -} diff --git a/arch/mips/mti-malta/malta-display.c b/arch/mips/mti-malta/malta-display.c index 7c8828f..2a0057c 100644 --- a/arch/mips/mti-malta/malta-display.c +++ b/arch/mips/mti-malta/malta-display.c @@ -22,7 +22,6 @@ #include #include #include -#include extern const char display_string[]; static unsigned int display_count; diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 27a6cdb..9844f31 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -23,31 +23,21 @@ #include #include -#include #include #include #include #include #include +#include #include -#include #include #include #include #include -int prom_argc; -int *_prom_argv, *_prom_envp; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension, if running in 64-bit mode. - */ -#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) - -int init_debug; +extern void mips_display_message(const char *str); static int mips_revision_corid; int mips_revision_sconid; @@ -62,28 +52,6 @@ unsigned long _pcictrl_gt64120; /* MIPS System controller register base */ unsigned long _pcictrl_msc; -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - * In 64-bit mode: we're using 64-bit pointers, but all pointers - * in the PROM structures are only 32-bit, so we need some - * workarounds, if we are running in 64-bit mode. - */ - int i, index=0; - - i = strlen(envname); - - while (prom_envp(index)) { - if(strncmp(envname, prom_envp(index), i) == 0) { - return(prom_envp(index+1)); - } - index += 2; - } - - return NULL; -} - static inline unsigned char str2hexnum(unsigned char c) { if (c >= '0' && c <= '9') @@ -138,8 +106,8 @@ static void __init console_config(void) char parity = '\0', bits = '\0', flow = '\0'; char *s; - if ((strstr(prom_getcmdline(), "console=")) == NULL) { - s = prom_getenv("modetty0"); + if ((strstr(fw_getcmdline(), "console=")) == NULL) { + s = fw_getenv("modetty0"); if (s) { while (*s >= '0' && *s <= '9') baud = baud*10 + *s++ - '0'; @@ -159,7 +127,7 @@ static void __init console_config(void) if (flow == '\0') flow = 'r'; sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); - strcat(prom_getcmdline(), console_string); + strcat(fw_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } } @@ -193,10 +161,6 @@ extern struct plat_smp_ops msmtc_smp_ops; void __init prom_init(void) { - prom_argc = fw_arg0; - _prom_argv = (int *) fw_arg1; - _prom_envp = (int *) fw_arg2; - mips_display_message("LINUX"); /* @@ -353,8 +317,9 @@ void __init prom_init(void) board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; - prom_init_cmdline(); - prom_meminit(); + fw_init_cmdline(); + fw_meminit(); + #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index a96d281..cddcd46 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -24,50 +24,31 @@ #include #include -#include #include #include +#include -#include - -/*#define DEBUG*/ - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; -static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -#ifdef DEBUG -static char *mtypes[3] = { - "Dont use memory", - "YAMON PROM memory", - "Free memory", -}; -#endif +static fw_memblock_t mdesc[FW_MAX_MEMBLOCKS]; /* determined physical memory size, not overridden by command line args */ unsigned long physical_memsize = 0L; -static struct prom_pmemblock * __init prom_getmdesc(void) +fw_memblock_t * __init fw_getmdesc(void) { - char *memsize_str; + char *memsize_str, *ptr; unsigned int memsize; - char *ptr; static char cmdline[COMMAND_LINE_SIZE] __initdata; + long val; + int tmp; /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); + memsize_str = fw_getenv("memsize"); if (!memsize_str) { - printk(KERN_WARNING - "memsize not set in boot prom, set to default (32Mb)\n"); + pr_warn("memsize not set in YAMON, set to default (32Mb)\n"); physical_memsize = 0x02000000; } else { -#ifdef DEBUG - pr_debug("prom_memsize = %s\n", memsize_str); -#endif - physical_memsize = simple_strtol(memsize_str, NULL, 0); + tmp = kstrtol(memsize_str, 0, &val); + physical_memsize = (unsigned long)val; } #ifdef CONFIG_CPU_BIG_ENDIAN @@ -90,11 +71,11 @@ static struct prom_pmemblock * __init prom_getmdesc(void) memset(mdesc, 0, sizeof(mdesc)); - mdesc[0].type = yamon_dontuse; + mdesc[0].type = fw_dontuse; mdesc[0].base = 0x00000000; mdesc[0].size = 0x00001000; - mdesc[1].type = yamon_prom; + mdesc[1].type = fw_code; mdesc[1].base = 0x00001000; mdesc[1].size = 0x000ef000; @@ -105,55 +86,44 @@ static struct prom_pmemblock * __init prom_getmdesc(void) * This mean that this area can't be used as DMA memory for PCI * devices. */ - mdesc[2].type = yamon_dontuse; + mdesc[2].type = fw_dontuse; mdesc[2].base = 0x000f0000; mdesc[2].size = 0x00010000; - mdesc[3].type = yamon_dontuse; + mdesc[3].type = fw_dontuse; mdesc[3].base = 0x00100000; mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; - mdesc[4].type = yamon_free; + mdesc[4].type = fw_free; mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); mdesc[4].size = memsize - mdesc[4].base; return &mdesc[0]; } -static int __init prom_memtype_classify(unsigned int type) +static int __init fw_memtype_classify(unsigned int type) { switch (type) { - case yamon_free: + case fw_free: return BOOT_MEM_RAM; - case yamon_prom: + case fw_code: return BOOT_MEM_ROM_DATA; default: return BOOT_MEM_RESERVED; } } -void __init prom_meminit(void) +void __init fw_meminit(void) { - struct prom_pmemblock *p; + fw_memblock_t *p; -#ifdef DEBUG - pr_debug("YAMON MEMORY DESCRIPTOR dump:\n"); - p = prom_getmdesc(); - while (p->size) { - int i = 0; - pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", - i, p, p->base, p->size, mtypes[p->type]); - p++; - i++; - } -#endif - p = prom_getmdesc(); + p = fw_getmdesc(); while (p->size) { long type; unsigned long base, size; - type = prom_memtype_classify(p->type); + type = fw_memtype_classify(p->type); base = p->base; size = p->size; @@ -172,7 +142,7 @@ void __init prom_free_prom_memory(void) continue; addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", + free_init_pages("YAMON memory", addr, addr + boot_mem_map.map[i].size); } } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 2e28f65..08cdf8f 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -25,9 +25,8 @@ #include #include -#include +#include #include -#include #include #include #include @@ -115,7 +114,7 @@ static void __init pci_clock_check(void) 33, 20, 25, 30, 12, 16, 37, 10 }; int pciclock = pciclocks[jmpr]; - char *argptr = prom_getcmdline(); + char *argptr = fw_getcmdline(); if (pciclock != 33 && !strstr(argptr, "idebus=")) { printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " @@ -153,7 +152,7 @@ static void __init bonito_quirks_setup(void) { char *argptr; - argptr = prom_getcmdline(); + argptr = fw_getcmdline(); if (strstr(argptr, "debug")) { BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; printk(KERN_INFO "Enabled Bonito debug mode\n"); @@ -165,7 +164,7 @@ static void __init bonito_quirks_setup(void) BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; printk(KERN_INFO "Enabled Bonito CPU coherency\n"); - argptr = prom_getcmdline(); + argptr = fw_getcmdline(); if (strstr(argptr, "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 115f5bc..8a5d589 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -41,7 +41,6 @@ #include #include -#include #include -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:51:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:54:16 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43571 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903720Ab2FEVvM (ORCPT ); Tue, 5 Jun 2012 23:51:12 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AQ-000824-4X; Tue, 05 Jun 2012 16:19:54 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 10/35] MIPS: Emma: Cleanup firmware support for the Emma platform. Date: Tue, 5 Jun 2012 16:19:14 -0500 Message-Id: <1338931179-9611-11-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33535 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1252 Lines: 47 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/emma/common/prom.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/arch/mips/emma/common/prom.c b/arch/mips/emma/common/prom.c index cae4225..5228584 100644 --- a/arch/mips/emma/common/prom.c +++ b/arch/mips/emma/common/prom.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include const char *get_system_type(void) @@ -40,22 +40,7 @@ const char *get_system_type(void) /* [jsun@junsun.net] PMON passes arguments in C main() style */ void __init prom_init(void) { - int argc = fw_arg0; - char **arg = (char **)fw_arg1; - int i; - - /* if user passes kernel args, ignore the default one */ - if (argc > 1) - arcs_cmdline[0] = '\0'; - - /* arg[0] is "g", the rest is boot parameters */ - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i]) + 1 - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } + fw_init_cmdline(); #ifdef CONFIG_NEC_MARKEINS add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:51:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:54:38 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43573 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903751Ab2FEVv0 (ORCPT ); Tue, 5 Jun 2012 23:51:26 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AQ-000824-JN; Tue, 05 Jun 2012 16:19:54 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 11/35] MIPS: Emma: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:15 -0500 Message-Id: <1338931179-9611-12-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33536 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1942 Lines: 49 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/emma/common/prom.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/arch/mips/emma/common/prom.c b/arch/mips/emma/common/prom.c index 5228584..9a70c4e 100644 --- a/arch/mips/emma/common/prom.c +++ b/arch/mips/emma/common/prom.c @@ -1,23 +1,14 @@ /* - * Copyright (C) NEC Electronics Corporation 2004-2006 + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * This file is based on the arch/mips/ddb5xxx/common/prom.c + * This is based on the arch/mips/ddb5xxx/common/prom.c file. + * GPR board platform device registration (Au1550) * - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * Copyright 2001 MontaVista Software Inc. + * Copyright (C) NEC Electronics Corporation 2004-2006 + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include #include -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:51:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:55:03 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43576 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903744Ab2FEVvd (ORCPT ); Tue, 5 Jun 2012 23:51:33 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AT-000824-Ua; Tue, 05 Jun 2012 16:19:57 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 18/35] MIPS: Loongson: Cleanup firmware support for the Loongson platform. Date: Tue, 5 Jun 2012 16:19:22 -0500 Message-Id: <1338931179-9611-19-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33537 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5442 Lines: 175 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mach-loongson/loongson.h | 3 +- arch/mips/loongson/common/Makefile | 2 +- arch/mips/loongson/common/cmdline.c | 48 ------------------------ arch/mips/loongson/common/env.c | 31 ++++----------- arch/mips/loongson/common/init.c | 6 ++- 5 files changed, 13 insertions(+), 77 deletions(-) delete mode 100644 arch/mips/loongson/common/cmdline.c diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 1e29b9d..b19c5b4 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -28,9 +28,8 @@ extern unsigned long memsize, highmemsize; /* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); -extern void __init prom_init_cmdline(void); extern void __init prom_init_machtype(void); -extern void __init prom_init_env(void); +extern void __init fw_init_env(void); #ifdef CONFIG_LOONGSON_UART_BASE extern unsigned long _loongson_uart_base, loongson_uart_base; extern void prom_init_loongson_uart_base(void); diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index e526488..5267e33 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -2,7 +2,7 @@ # Makefile for loongson based machines. # -obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ +obj-y += setup.o init.o env.o time.o reset.o irq.o \ pci.o bonito-irq.o mem.o machtype.o platform.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c deleted file mode 100644 index 353e1d2..0000000 --- a/arch/mips/loongson/common/cmdline.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2003 ICT CAS - * Author: Michael Guo - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (C) 2009 Lemote Inc. - * Author: Wu Zhangjin, wuzhangjin@gmail.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -void __init prom_init_cmdline(void) -{ - int prom_argc; - /* pmon passes arguments in 32bit pointers */ - int *_prom_argv; - int i; - long l; - - /* firmware arguments are initialized in head.S */ - prom_argc = fw_arg0; - _prom_argv = (int *)fw_arg1; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < prom_argc; i++) { - l = (long)_prom_argv[i]; - if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ((char *)l)); - strcat(arcs_cmdline, " "); - } - - prom_init_machtype(); -} diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c index d93830a..681690a 100644 --- a/arch/mips/loongson/common/env.c +++ b/arch/mips/loongson/common/env.c @@ -19,7 +19,7 @@ */ #include -#include +#include #include @@ -27,34 +27,17 @@ unsigned long cpu_clock_freq; EXPORT_SYMBOL(cpu_clock_freq); unsigned long memsize, highmemsize; -#define parse_even_earlier(res, option, p) \ -do { \ - unsigned int tmp __maybe_unused; \ - \ - if (strncmp(option, (char *)p, strlen(option)) == 0) \ - tmp = strict_strtol((char *)p + strlen(option"="), 10, &res); \ -} while (0) - -void __init prom_init_env(void) +void __init fw_init_env(void) { - /* pmon passes arguments in 32bit pointers */ - int *_prom_envp; + /* PMON passes arguments in 32bit pointers */ unsigned long bus_clock; unsigned int processor_id; - long l; - /* firmware arguments are initialized in head.S */ - _prom_envp = (int *)fw_arg2; + bus_clock = fw_getenvl("busclock"); + cpu_clock_freq = fw_getenvl("cpuclock"); + memsize = fw_getenvl("memsize"); + highmemsize = fw_getenvl("highmemsize"); - l = (long)*_prom_envp; - while (l != 0) { - parse_even_earlier(bus_clock, "busclock", l); - parse_even_earlier(cpu_clock_freq, "cpuclock", l); - parse_even_earlier(memsize, "memsize", l); - parse_even_earlier(highmemsize, "highmemsize", l); - _prom_envp++; - l = (long)*_prom_envp; - } if (memsize == 0) memsize = 256; if (bus_clock == 0) diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c index 19d3415..a40ab27 100644 --- a/arch/mips/loongson/common/init.c +++ b/arch/mips/loongson/common/init.c @@ -10,6 +10,8 @@ #include +#include + #include /* Loongson CPU address windows config space base address */ @@ -26,8 +28,8 @@ void __init prom_init(void) ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE); #endif - prom_init_cmdline(); - prom_init_env(); + fw_init_cmdline(); + fw_init_env(); prom_init_memory(); /*init the uart base address */ -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:51:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:55:25 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43578 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903741Ab2FEVvl (ORCPT ); Tue, 5 Jun 2012 23:51:41 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AZ-000824-PQ; Tue, 05 Jun 2012 16:20:03 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 30/35] MIPS: RB532: Cleanup firmware support for RB532 platform. Date: Tue, 5 Jun 2012 16:19:34 -0500 Message-Id: <1338931179-9611-31-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33538 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2293 Lines: 87 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/rb532/prom.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c index d7c26d0..54f5399 100644 --- a/arch/mips/rb532/prom.c +++ b/arch/mips/rb532/prom.c @@ -33,7 +33,7 @@ #include #include -#include +#include #include #include @@ -62,41 +62,40 @@ static inline int match_tag(char *arg, const char *tag) static inline unsigned long tag2ul(char *arg, const char *tag) { char *num; + long val; + int tmp; num = arg + strlen(tag); - return simple_strtoul(num, 0, 10); + tmp = kstrtol(num, 0, &val); + return (unsigned long)val; } void __init prom_setup_cmdline(void) { static char cmd_line[COMMAND_LINE_SIZE] __initdata; char *cp, *board; - int prom_argc; - char **prom_argv, **prom_envp; int i; - prom_argc = fw_arg0; - prom_argv = (char **) fw_arg1; - prom_envp = (char **) fw_arg2; + fw_init_cmdline(); cp = cmd_line; /* Note: it is common that parameters start * at argv[1] and not argv[0], * however, our elf loader starts at [0] */ - for (i = 0; i < prom_argc; i++) { - if (match_tag(prom_argv[i], FREQ_TAG)) { - idt_cpu_freq = tag2ul(prom_argv[i], FREQ_TAG); + for (i = 0; i < fw_argc; i++) { + if (match_tag(fw_argv(i), FREQ_TAG)) { + idt_cpu_freq = tag2ul(fw_argv(i), FREQ_TAG); continue; } #ifdef IGNORE_CMDLINE_MEM /* parses out the "mem=xx" arg */ - if (match_tag(prom_argv[i], MEM_TAG)) + if (match_tag(fw_argv(i), MEM_TAG)) continue; #endif if (i > 0) *(cp++) = ' '; - if (match_tag(prom_argv[i], BOARD_TAG)) { - board = prom_argv[i] + strlen(BOARD_TAG); + if (match_tag(fw_argv(i), BOARD_TAG)) { + board = fw_argv(i) + strlen(BOARD_TAG); if (match_tag(board, BOARD_RB532A)) mips_machtype = MACH_MIKROTIK_RB532A; @@ -104,8 +103,8 @@ void __init prom_setup_cmdline(void) mips_machtype = MACH_MIKROTIK_RB532; } - strcpy(cp, prom_argv[i]); - cp += strlen(prom_argv[i]); + strcpy(cp, fw_argv(i)); + cp += strlen(fw_argv(i)); } *(cp++) = ' '; -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:51:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:55:51 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43579 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903747Ab2FEVvr (ORCPT ); Tue, 5 Jun 2012 23:51:47 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AY-000824-Au; Tue, 05 Jun 2012 16:20:02 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 27/35] MIPS: PNX83xx, PNX8550: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:31 -0500 Message-Id: <1338931179-9611-28-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33539 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 12010 Lines: 335 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/pnx833x/common/setup.c | 35 ++++++------------- arch/mips/pnx833x/stb22x/board.c | 45 ++++++++++-------------- arch/mips/pnx8550/common/setup.c | 62 +++++++++++++++------------------- arch/mips/pnx8550/jbs/init.c | 38 ++++----------------- arch/mips/pnx8550/stb810/prom_init.c | 25 +++++--------- 5 files changed, 71 insertions(+), 134 deletions(-) diff --git a/arch/mips/pnx833x/common/setup.c b/arch/mips/pnx833x/common/setup.c index 3ea4926..f744b80 100644 --- a/arch/mips/pnx833x/common/setup.c +++ b/arch/mips/pnx833x/common/setup.c @@ -1,33 +1,20 @@ /* - * setup.c: Setup PNX833X Soc. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright 2008 NXP Semiconductors - * Chris Steel - * Daniel Laird + * Setup PNX833X SOC. Based on software written by + * Nikita Youshchenko from PNX8550 code. * - * Based on software written by: - * Nikita Youshchenko , based on PNX8550 code. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * Copyright 2008 NXP Semiconductors + * Authors: Chris Steel + * Daniel Laird + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ -#include -#include -#include -#include #include + #include + #include #include diff --git a/arch/mips/pnx833x/stb22x/board.c b/arch/mips/pnx833x/stb22x/board.c index cdf1a3b..80e12ee 100644 --- a/arch/mips/pnx833x/stb22x/board.c +++ b/arch/mips/pnx833x/stb22x/board.c @@ -1,31 +1,20 @@ /* - * board.c: STB225 board support. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright 2008 NXP Semiconductors - * Chris Steel - * Daniel Laird + * STB225 board support based on software written by + * Nikita Youshchenko from PNX8550 code. * - * Based on software written by: - * Nikita Youshchenko , based on PNX8550 code. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * Copyright 2008 NXP Semiconductors + * Authors: Chris Steel + * Daniel Laird + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ -#include -#include +#include + #include -#include + #include /* endianess twiddlers */ @@ -94,9 +83,6 @@ void __init pnx833x_board_setup(void) PNX833X_MIU_SEL0_TIMING = 0x50003081; PNX833X_MIU_SEL1_TIMING = 0x50003081; - /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ - pnx833x_gpio_select_function_alt(0); - /* Setup GPIO 04 to input NAND read/busy signal */ pnx833x_gpio_select_function_io(4); pnx833x_gpio_select_input(4); @@ -115,8 +101,11 @@ void __init pnx833x_board_setup(void) PNX833X_MIU_SEL1 = 1; PNX833X_MIU_SEL0_TIMING = 0x6A08D082; PNX833X_MIU_SEL1_TIMING = 0x6A08D082; +#endif - /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ + /* + * Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, + * so does not need this) + */ pnx833x_gpio_select_function_alt(0); -#endif } diff --git a/arch/mips/pnx8550/common/setup.c b/arch/mips/pnx8550/common/setup.c index b8ae54c..abe585e 100644 --- a/arch/mips/pnx8550/common/setup.c +++ b/arch/mips/pnx8550/common/setup.c @@ -1,45 +1,21 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * 2.6 port, Embedded Alley Solutions, Inc + * Setup based on Per Hallsmark, per.hallsmark@mvista.com * - * Based on Per Hallsmark, per.hallsmark@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * Copyright 2005 Embedded Alley Solutions, Inc + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ -#include -#include -#include -#include -#include -#include -#include #include -#include -#include -#include -#include #include #include -#include -#include #include -#include #include #include -#include extern void __init board_setup(void); extern void pnx8550_machine_restart(char *); @@ -89,16 +65,34 @@ unsigned long get_system_mem_size(void) int pnx8550_console_port = -1; +/* used by early printk */ +void prom_putchar(char c) +{ + if (pnx8550_console_port != -1) { + /* Wait until FIFO not full */ + while (((ip3106_fifo(UART_BASE, pnx8550_console_port) & + PNX8XXX_UART_FIFO_TXFIFO) >> 16) >= 16) + ; + + /* Send one char */ + ip3106_fifo(UART_BASE, pnx8550_console_port) = c; + } +} + +void __init prom_free_prom_memory(void) +{ +} + void __init plat_mem_setup(void) { int i; - char* argptr; + char *argptr; board_setup(); /* board specific setup */ - _machine_restart = pnx8550_machine_restart; - _machine_halt = pnx8550_machine_halt; - pm_power_off = pnx8550_machine_halt; + _machine_restart = pnx8550_machine_restart; + _machine_halt = pnx8550_machine_halt; + pm_power_off = pnx8550_machine_halt; /* Clear the Global 2 Register, PCI Inta Output Enable Registers Bit 1:Enable DAC Powerdown diff --git a/arch/mips/pnx8550/jbs/init.c b/arch/mips/pnx8550/jbs/init.c index e682446..cc69bac 100644 --- a/arch/mips/pnx8550/jbs/init.c +++ b/arch/mips/pnx8550/jbs/init.c @@ -1,37 +1,14 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright 2005 Embedded Alley Solutions, Inc - * source@embeddedalley.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * Copyright 2005 Embedded Alley Solutions, Inc + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - -#include -#include -#include #include -#include + #include -#include -#include const char *get_system_type(void) { @@ -44,7 +21,6 @@ void __init prom_init(void) fw_init_cmdline(); - //memsize = 0x02800000; /* Trimedia uses memory above */ - memsize = 0x08000000; /* Trimedia uses memory above */ + memsize = 0x08000000; /* Trimedia uses memory above */ add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/arch/mips/pnx8550/stb810/prom_init.c b/arch/mips/pnx8550/stb810/prom_init.c index cb1b052..58d2765 100644 --- a/arch/mips/pnx8550/stb810/prom_init.c +++ b/arch/mips/pnx8550/stb810/prom_init.c @@ -1,25 +1,16 @@ /* - * STB810 specific prom routines + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Author: MontaVista Software, Inc. - * source@mvista.com + * STB810 specific prom routines. * - * Copyright 2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Copyright 2005 MontaVista Software Inc. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - -#include -#include -#include #include -#include + #include -#include -#include const char *get_system_type(void) { @@ -32,6 +23,6 @@ void __init prom_init(void) fw_init_cmdline(); - memsize = 0x08000000; /* Trimedia uses memory above */ + memsize = 0x08000000; /* Trimedia uses memory above */ add_memory_region(0, memsize, BOOT_MEM_RAM); } -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:51:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:56:13 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43583 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903746Ab2FEVvz (ORCPT ); Tue, 5 Jun 2012 23:51:55 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AS-000824-1Y; Tue, 05 Jun 2012 16:19:56 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 14/35] MIPS: lantiq: Cleanup firmware support for the lantiq platform. Date: Tue, 5 Jun 2012 16:19:18 -0500 Message-Id: <1338931179-9611-15-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33540 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1395 Lines: 59 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/lantiq/prom.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index d185e84..aa9da9e 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -9,9 +9,9 @@ #include #include #include -#include #include +#include #include #include "prom.h" @@ -36,24 +36,6 @@ void prom_free_prom_memory(void) { } -static void __init prom_init_cmdline(void) -{ - int argc = fw_arg0; - char **argv = (char **) KSEG1ADDR(fw_arg1); - int i; - - arcs_cmdline[0] = '\0'; - - for (i = 0; i < argc; i++) { - char *p = (char *) KSEG1ADDR(argv[i]); - - if (CPHYSADDR(p) && *p) { - strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); - strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); - } - } -} - void __init plat_mem_setup(void) { ioport_resource.start = IOPORT_RESOURCE_START; @@ -78,7 +60,7 @@ void __init prom_init(void) soc_info.name, soc_info.rev_type); soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; pr_info("SoC: %s\n", soc_info.sys_type); - prom_init_cmdline(); + fw_init_cmdline(); #if defined(CONFIG_MIPS_MT_SMP) if (register_vsmp_smp_ops()) -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:52:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:56:38 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43584 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903745Ab2FEVwB (ORCPT ); Tue, 5 Jun 2012 23:52:01 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1Aa-000824-84; Tue, 05 Jun 2012 16:20:04 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 31/35] MIPS: RB532: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:35 -0500 Message-Id: <1338931179-9611-32-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33541 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2623 Lines: 74 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/rb532/prom.c | 40 +++++++++++----------------------------- 1 file changed, 11 insertions(+), 29 deletions(-) diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c index 54f5399..5bddd0b 100644 --- a/arch/mips/rb532/prom.c +++ b/arch/mips/rb532/prom.c @@ -1,37 +1,19 @@ /* - * RouterBoard 500 specific prom routines + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright (C) 2003, Peter Sadik - * Copyright (C) 2005-2006, P.Christeas - * Copyright (C) 2007, Gabor Juhos - * Felix Fietkau - * Florian Fainelli - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the - * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. + * RouterBoard 500 specific prom routines * + * Copyright (C) 2003, Peter Sadik + * Copyright (C) 2005-2006, P.Christeas + * Copyright (C) 2007, Gabor Juhos + * Felix Fietkau + * Florian Fainelli + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - -#include -#include #include #include -#include -#include -#include -#include #include #include @@ -129,7 +111,7 @@ void __init prom_init(void) ddr_reg[0].end - ddr_reg[0].start); if (!ddr) { - printk(KERN_ERR "Unable to remap DDR register\n"); + pr_err("Unable to remap DDR register\n"); return; } -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:52:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:57:02 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43588 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903753Ab2FEVwK (ORCPT ); Tue, 5 Jun 2012 23:52:10 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1Ab-000824-6m; Tue, 05 Jun 2012 16:20:05 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 33/35] MIPS: txx9: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:37 -0500 Message-Id: <1338931179-9611-34-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33542 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2002 Lines: 64 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/txx9/generic/setup.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 8a053d6..00fc82b 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -1,34 +1,29 @@ /* - * Based on linux/arch/mips/txx9/rbtx4938/setup.c, - * and RBTX49xx patch from CELF patch archive. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c and RBTX49xx patch + * from CELF patch archive. * * 2003-2005 (c) MontaVista Software, Inc. * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ -#include -#include -#include -#include #include #include -#include -#include +#include #include +#include #include -#include #include -#include -#include -#include -#include -#include +#include + #include #include #include +#include #include #include #include -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:52:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:57:26 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43591 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903757Ab2FEVwQ (ORCPT ); Tue, 5 Jun 2012 23:52:16 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AS-000824-He; Tue, 05 Jun 2012 16:19:56 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 15/35] MIPS: lantiq: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:19 -0500 Message-Id: <1338931179-9611-16-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33543 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1159 Lines: 38 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/lantiq/prom.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index aa9da9e..56470c6 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -1,15 +1,15 @@ /* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Copyright (C) 2010 John Crispin + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include #include #include -#include +#include #include #include -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:52:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:57:54 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43593 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903759Ab2FEVwX (ORCPT ); Tue, 5 Jun 2012 23:52:23 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AX-000824-CB; Tue, 05 Jun 2012 16:20:01 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 25/35] MIPS: MSP71xx, Yosemite: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:29 -0500 Message-Id: <1338931179-9611-26-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33544 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 24162 Lines: 644 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- .../mips/include/asm/pmc-sierra/msp71xx/msp_prom.h | 27 ++----- arch/mips/pmc-sierra/msp71xx/msp_prom.c | 79 +++----------------- arch/mips/pmc-sierra/msp71xx/msp_serial.c | 60 +++++---------- arch/mips/pmc-sierra/msp71xx/msp_setup.c | 33 ++++---- arch/mips/pmc-sierra/msp71xx/msp_time.c | 53 ++++--------- arch/mips/pmc-sierra/msp71xx/msp_usb.c | 28 ++----- arch/mips/pmc-sierra/yosemite/prom.c | 14 ++-- drivers/mtd/maps/pmcmsp-flash.c | 49 ++++-------- 8 files changed, 98 insertions(+), 245 deletions(-) diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h index b8c34ff..ceacb7e 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h @@ -1,25 +1,14 @@ /* - * MIPS boards bootprom interface for the Linux kernel. - * - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Author: Carsten Langgaard, carstenl@mips.com - * - * ######################################################################## + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * MIPS boards bootprom interface for the Linux kernel. * - * ######################################################################## + * Copyright (C) 2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ #ifndef _ASM_MSP_PROM_H diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c index 885256f..39eddff 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_prom.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c @@ -1,42 +1,18 @@ /* - * BRIEF MODULE DESCRIPTION - * PROM library initialisation code, assuming a version of - * pmon is the boot code. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * PROM library initialisation code, assuming a version of PMON is + * the boot code. * * Copyright 2000,2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/xx files. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Pete Popov or * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include -#include -#include #include #include #include @@ -58,11 +34,9 @@ fw_memblock_t mdesc[7]; /* default feature sets */ static char msp_default_features[] = -#if defined(CONFIG_PMC_MSP4200_EVAL) \ - || defined(CONFIG_PMC_MSP4200_GW) +#if defined(CONFIG_PMC_MSP4200_EVAL) || defined(CONFIG_PMC_MSP4200_GW) "ERER"; -#elif defined(CONFIG_PMC_MSP7120_EVAL) \ - || defined(CONFIG_PMC_MSP7120_GW) +#elif defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) "EMEMSP"; #elif defined(CONFIG_PMC_MSP7120_FPGA) "EMEM"; @@ -132,35 +106,6 @@ const char *get_system_type(void) #endif } -int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr) -{ - char *ethaddr_str; - - ethaddr_str = fw_getenv(ethaddr_name); - if (!ethaddr_str) { - printk(KERN_WARNING "%s not set in boot prom\n", ethaddr_name); - return -1; - } - - if (str2eaddr(ethernet_addr, ethaddr_str) == -1) { - printk(KERN_WARNING "%s badly formatted-<%s>\n", - ethaddr_name, ethaddr_str); - return -1; - } - - if (init_debug > 1) { - int i; - printk(KERN_DEBUG "get_ethernet_addr: for %s ", ethaddr_name); - for (i = 0; i < 5; i++) - printk(KERN_DEBUG "%02x:", - (unsigned char)*(ethernet_addr+i)); - printk(KERN_DEBUG "%02x\n", *(ethernet_addr+i)); - } - - return 0; -} -EXPORT_SYMBOL(get_ethernet_addr); - static char *get_features(void) { char *feature = fw_getenv(FEATURES); @@ -400,8 +345,8 @@ fw_memblock_t *__init fw_getmdesc(void) str = fw_getenv(heaptop_env); if (!str) { heaptop = CPHYSADDR((u32)&_text); - ppfinit("heaptop not set in boot prom, " - "set to default 0x%08x\n", heaptop); + ppfinit("heaptop not set in boot prom, set to default 0x%08x\n", + heaptop); } else { tmp = kstrtol(str, 16, &val); heaptop = (unsigned int)val; diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c index 7080bce..041b53b 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c @@ -1,37 +1,15 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * The setup file for serial related hardware on PMC-Sierra MSP processors. * * Copyright 2005 PMC-Sierra, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - -#include -#include -#include #include - -#include -#include -#include +#include #include #include @@ -127,25 +105,25 @@ void __init msp_serial_setup(void) /* Initialize the second serial port, if one exists */ switch (mips_machtype) { - case MACH_MSP4200_EVAL: - case MACH_MSP4200_GW: - case MACH_MSP4200_FPGA: - case MACH_MSP7120_EVAL: - case MACH_MSP7120_GW: - case MACH_MSP7120_FPGA: - /* Enable UART1 on MSP4200 and MSP7120 */ - *GPIO_CFG2_REG = 0x00002299; - break; - - default: - return; /* No second serial port, good-bye. */ + case MACH_MSP4200_EVAL: + case MACH_MSP4200_GW: + case MACH_MSP4200_FPGA: + case MACH_MSP7120_EVAL: + case MACH_MSP7120_GW: + case MACH_MSP7120_FPGA: + /* Enable UART1 on MSP4200 and MSP7120 */ + *GPIO_CFG2_REG = 0x00002299; + break; + + default: + return; /* No second serial port, good-bye. */ } up.mapbase = MSP_UART1_BASE; up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN); up.irq = MSP_INT_UART1; up.line = 1; - up.private_data = (void*)UART1_STATUS_REG; + up.private_data = (void *)UART1_STATUS_REG; if (early_serial_setup(&up)) { kfree(up.private_data); pr_err("Early serial init of port 1 failed\n"); diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index 6fa0d76..c3adca6 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -1,15 +1,15 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * The generic setup file for PMC-Sierra MSP processors * * Copyright 2005-2007 PMC-Sierra, Inc, * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include #include #include @@ -28,9 +28,8 @@ extern void msp_serial_setup(void); extern void pmctwiled_setup(void); -#if defined(CONFIG_PMC_MSP7120_EVAL) || \ - defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_FPGA) +#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ + defined(CONFIG_PMC_MSP7120_FPGA) /* * Performs the reset for MSP7120-based boards */ @@ -77,7 +76,8 @@ void msp7120_reset(void) */ /* Wait a bit for the DDRC to settle */ - for (i = 0; i < 100000000; i++); + for (i = 0; i < 100000000; i++) + ; #if defined(CONFIG_PMC_MSP7120_GW) /* @@ -107,11 +107,10 @@ void msp7120_reset(void) void msp_restart(char *command) { - printk(KERN_WARNING "Now rebooting .......\n"); + pr_warn("Now rebooting .......\n"); -#if defined(CONFIG_PMC_MSP7120_EVAL) || \ - defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_FPGA) +#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ + defined(CONFIG_PMC_MSP7120_FPGA) msp7120_reset(); #else /* No chip-specific reset code, just jump to the ROM reset vector */ @@ -120,13 +119,17 @@ void msp_restart(char *command) flush_cache_all(); write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); + __asm__ __volatile__ ( + " jr %0 \n" + : + : "r" (0xbfc00000) + ); #endif } void msp_halt(void) { - printk(KERN_WARNING "\n** You can safely turn off the power\n"); + pr_warn("\n** You can safely turn off the power\n"); while (1) /* If possible call official function to get CPU WARs */ if (cpu_wait) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index d76cbdb..e24c1c5 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -1,41 +1,21 @@ /* - * Setting up the clock on MSP SOCs. No RTC typically. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * Setting up the clock on MSP SOCs. No RTC typically. * - * ######################################################################## + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill */ - -#include -#include -#include -#include -#include -#include - #include #include #include #include #include -#include #define get_current_vpe() \ ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) @@ -49,33 +29,30 @@ void __init plat_time_init(void) cpu_rate = fw_getenvl("clkfreqhz"); if (cpu_rate == 0) - printk(KERN_ERR "Clock rate in Hz parse error: %s\n", s); + pr_err("Clock rate in Hz parse error\n"); if (cpu_rate == 0) { cpu_rate = 1000 * fw_getenvl("clkfreq"); if (cpu_rate == 0) - printk(KERN_ERR "Clock rate in MHz parse error: %s\n", s); - } + pr_err("Clock rate in MHz parse error\n"); } if (cpu_rate == 0) { -#if defined(CONFIG_PMC_MSP7120_EVAL) \ - || defined(CONFIG_PMC_MSP7120_GW) +#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) cpu_rate = 400000000; #elif defined(CONFIG_PMC_MSP7120_FPGA) cpu_rate = 25000000; #else cpu_rate = 150000000; #endif - printk(KERN_ERR - "Failed to determine CPU clock rate, " - "assuming %ld hz ...\n", cpu_rate); + pr_err("Failed to determine CPU clock rate, assuming %ld Hz\n", + cpu_rate); } - printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate); + pr_warn("Clock rate set to %ld\n", cpu_rate); /* timer frequency is 1/2 clock rate */ - mips_hpt_frequency = cpu_rate/2; + mips_hpt_frequency = (cpu_rate / 2); } unsigned int __cpuinit get_c0_compare_int(void) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c index ee4ed9b..3ba9da0 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c @@ -1,35 +1,17 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * The setup file for USB related hardware on PMC-Sierra MSP processors. * * Copyright 2006 PMC-Sierra, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) -#include -#include #include -#include #include #include diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c index b4ce648..945911d 100644 --- a/arch/mips/pmc-sierra/yosemite/prom.c +++ b/arch/mips/pmc-sierra/yosemite/prom.c @@ -1,12 +1,12 @@ /* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Copyright (C) 2003, 2004 PMC-Sierra Inc. * Author: Manish Lachwani (lachwani@pmc-sierra.com) * Copyright (C) 2004 Ralf Baechle + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include #include @@ -14,8 +14,8 @@ #include #include #include +#include -#include #include #include #include @@ -52,7 +52,7 @@ static void prom_cpu0_exit(void *arg) mdelay(100 + (1000 / 16)); /* if the watchdog fails for some reason, let people know */ - printk(KERN_NOTICE "Watchdog reset failed\n"); + pr_notice("Watchdog reset failed\n"); } /* @@ -73,7 +73,7 @@ static void prom_exit(void) */ static void prom_halt(void) { - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + pr_notice("\n** You can safely turn off the power\n"); while (1) __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0"); } diff --git a/drivers/mtd/maps/pmcmsp-flash.c b/drivers/mtd/maps/pmcmsp-flash.c index c19d9e4..896a76c 100644 --- a/drivers/mtd/maps/pmcmsp-flash.c +++ b/drivers/mtd/maps/pmcmsp-flash.c @@ -1,42 +1,25 @@ /* - * Mapping of a custom board with both AMD CFI and JEDEC flash in partitions. - * Config with both CFI and JEDEC device support. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Basically physmap.c with the addition of partitions and - * an array of mapping info to accommodate more than one flash type per board. + * Mapping of a custom board with both AMD CFI and JEDEC flash in partitions. + * Config with both CFI and JEDEC device support. Basically physmap.c with + * the addition of partitions and an array of mapping info to accommodate more + * than one flash type per board. * * Copyright 2005-2007 PMC-Sierra, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include #include #include #include +#include #include #include #include -#include #include #include @@ -48,8 +31,6 @@ static struct mtd_partition **msp_parts; static struct map_info *msp_maps; static int fcnt; -#define DEBUG_MARKER printk(KERN_NOTICE "%s[%d]\n", __func__, __LINE__) - static int __init init_msp_flash(void) { int i, j, ret = -ENOMEM; @@ -63,7 +44,7 @@ static int __init init_msp_flash(void) /* If ELB is disabled by "ful-mux" mode, we can't get at flash */ if ((*DEV_ID_REG & DEV_ID_SINGLE_PC) && (*ELB_1PC_EN_REG & SINGLE_PCCARD)) { - printk(KERN_NOTICE "Single PC Card mode: no flash access\n"); + pr_notice("Single PC Card mode: no flash access\n"); return -ENXIO; } @@ -74,7 +55,7 @@ static int __init init_msp_flash(void) if (fcnt < 1) return -ENXIO; - printk(KERN_NOTICE "Found %d PMC flash devices\n", fcnt); + pr_notice("Found %d PMC flash devices\n", fcnt); msp_flash = kmalloc(fcnt * sizeof(struct map_info *), GFP_KERNEL); if (!msp_flash) @@ -97,8 +78,7 @@ static int __init init_msp_flash(void) part_name[7] = '0' + pcnt + 1; if (pcnt == 0) { - printk(KERN_NOTICE "Skipping flash device %d " - "(no partitions defined)\n", i); + pr_notice("Skipping flash device %d (no partitions defined)\n", i); continue; } @@ -118,8 +98,7 @@ static int __init init_msp_flash(void) } addr = CPHYSADDR(addr); - printk(KERN_NOTICE - "MSP flash device \"%s\": 0x%08x at 0x%08x\n", + pr_notice("MSP flash device \"%s\": 0x%08x at 0x%08x\n", flash_name, size, addr); /* This must matchs the actual size of the flash chip */ msp_maps[i].size = size; @@ -176,7 +155,7 @@ static int __init init_msp_flash(void) msp_flash[i]->owner = THIS_MODULE; mtd_device_register(msp_flash[i], msp_parts[i], pcnt); } else { - printk(KERN_ERR "map probe failed for flash\n"); + pr_err("map probe failed for flash\n"); ret = -ENXIO; kfree(msp_maps[i].name); iounmap(msp_maps[i].virt); -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:52:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:58:18 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43595 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903737Ab2FEVw3 (ORCPT ); Tue, 5 Jun 2012 23:52:29 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AW-000824-ES; Tue, 05 Jun 2012 16:20:00 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 23/35] MIPS: Netlogic: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:27 -0500 Message-Id: <1338931179-9611-24-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33545 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2561 Lines: 60 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/netlogic/xlr/setup.c | 35 +++++------------------------------ 1 file changed, 5 insertions(+), 30 deletions(-) diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index 113a402..324c071 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -1,37 +1,12 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ - #include #include #include -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:52:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:58:44 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43597 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903748Ab2FEVwg (ORCPT ); Tue, 5 Jun 2012 23:52:36 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AY-000824-Qi; Tue, 05 Jun 2012 16:20:02 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 28/35] MIPS: PowerTV: Cleanup firmware support for PowerTV platform. Date: Tue, 5 Jun 2012 16:19:32 -0500 Message-Id: <1338931179-9611-29-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33546 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4709 Lines: 170 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/powertv/asic/asic_int.c | 1 - arch/mips/powertv/init.c | 54 +++---------------------------------- arch/mips/powertv/memory.c | 13 +++------ arch/mips/powertv/powertv_setup.c | 2 -- 4 files changed, 7 insertions(+), 63 deletions(-) diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c index 99d82e1..8728c3b 100644 --- a/arch/mips/powertv/asic/asic_int.c +++ b/arch/mips/powertv/asic/asic_int.c @@ -35,7 +35,6 @@ #include #include #include -#include #include diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c index 1cf5abb..14cdf19 100644 --- a/arch/mips/powertv/init.c +++ b/arch/mips/powertv/init.c @@ -23,52 +23,15 @@ #include #include #include - -#include #include + #include #include - -#include -#include +#include #include -static int *_prom_envp; unsigned long _prom_memsize; -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension, if running in 64-bit mode. - */ -#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) - -char *prom_getenv(char *envname) -{ - char *result = NULL; - - if (_prom_envp != NULL) { - /* - * Return a pointer to the given environment variable. - * In 64-bit mode: we're using 64-bit pointers, but all pointers - * in the PROM structures are only 32-bit, so we need some - * workarounds, if we are running in 64-bit mode. - */ - int i, index = 0; - - i = strlen(envname); - - while (prom_envp(index)) { - if (strncmp(envname, prom_envp(index), i) == 0) { - result = prom_envp(index + 1); - break; - } - index += 2; - } - } - - return result; -} - /* TODO: Verify on linux-mips mailing list that the following two */ /* functions are correct */ /* TODO: Copy NMI and EJTAG exception vectors to memory from the */ @@ -105,24 +68,15 @@ static void __init mips_ejtag_setup(void) void __init prom_init(void) { - int prom_argc; - char *prom_argv; - - prom_argc = fw_arg0; - prom_argv = (char *) fw_arg1; - _prom_envp = (int *) fw_arg2; _prom_memsize = (unsigned long) fw_arg3; board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; - if (prom_argc == 1) { - strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); - strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE); - } + fw_init_cmdline(); configure_platform(); - prom_meminit(); + fw_meminit(); #ifndef CONFIG_BOOTLOADER_DRIVER pr_info("\nBootloader driver isn't loaded...\n"); diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c index fb3d296..56f0193 100644 --- a/arch/mips/powertv/memory.c +++ b/arch/mips/powertv/memory.c @@ -28,8 +28,8 @@ #include #include #include +#include -#include #include #include @@ -163,7 +163,6 @@ static phys_addr_t get_memsize(void) { static char cmdline[COMMAND_LINE_SIZE] __initdata; phys_addr_t memsize = 0; - char *memsize_str; char *ptr; /* Check the command line first for a memsize directive */ @@ -176,13 +175,7 @@ static phys_addr_t get_memsize(void) memsize = memparse(ptr + 8, &ptr); } else { /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - - if (memsize_str != NULL) { - pr_info("prom memsize = %s\n", memsize_str); - memsize = simple_strtol(memsize_str, NULL, 0); - } - + memsize = (phys_addr_t) fw_getenvl("memsize"); if (memsize == 0) { if (_prom_memsize != 0) { memsize = _prom_memsize; @@ -332,7 +325,7 @@ static __init void register_address_space(phys_addr_t memsize) } } -void __init prom_meminit(void) +void __init fw_meminit(void) { ptv_memsize = get_memsize(); register_address_space(ptv_memsize); diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c index 3933c37..55a3fc5 100644 --- a/arch/mips/powertv/powertv_setup.c +++ b/arch/mips/powertv/powertv_setup.c @@ -30,8 +30,6 @@ #include #include -#include -#include #include #include #include -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:52:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:59:08 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43598 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903764Ab2FEVwm (ORCPT ); Tue, 5 Jun 2012 23:52:42 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AZ-000824-9w; Tue, 05 Jun 2012 16:20:03 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 29/35] MIPS: PowerTV: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:33 -0500 Message-Id: <1338931179-9611-30-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33547 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8292 Lines: 209 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/powertv/asic/asic_int.c | 44 ++++++++++--------------------------- arch/mips/powertv/init.c | 27 +++++++++-------------- arch/mips/powertv/memory.c | 26 +++++++++------------- arch/mips/powertv/powertv_setup.c | 27 +++++++++-------------- 4 files changed, 42 insertions(+), 82 deletions(-) diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c index 8728c3b..3cd9f65 100644 --- a/arch/mips/powertv/asic/asic_int.c +++ b/arch/mips/powertv/asic/asic_int.c @@ -1,27 +1,20 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. - * Copyright (C) 2001 Ralf Baechle - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. + * Routines for generic manipulation of the interrupts found on the PowerTV + * platform. The interrupt controller is located in the South Bridge a PIIX4 + * device with two internal 82C95 interrupt controllers. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * Copyright (C) 2000,2001,2004,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill * - * Routines for generic manipulation of the interrupts found on the PowerTV - * platform. + * Copyright (C) 2001 Ralf Baechle * - * The interrupt controller is located in the South Bridge a PIIX4 device - * with two internal 82C95 interrupt controllers. + * Portions copyright (C) 2009 Cisco Systems, Inc. */ #include #include @@ -68,19 +61,6 @@ static void asic_irqdispatch(void) do_IRQ(irq); } -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - /* * Version of ffs that only looks at bits 12..15. */ diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c index 14cdf19..d9be671 100644 --- a/arch/mips/powertv/init.c +++ b/arch/mips/powertv/init.c @@ -1,24 +1,17 @@ /* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. + * PROM library initialisation code. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * Steven J. Hill * - * PROM library initialisation code. + * Portions copyright (C) 2009 Cisco Systems, Inc. */ #include #include diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c index 56f0193..be70d51 100644 --- a/arch/mips/powertv/memory.c +++ b/arch/mips/powertv/memory.c @@ -1,23 +1,17 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Apparently originally from arch/mips/malta-memory.c. Modified to work * with the PowerTV bootloader. + * + * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill + * + * Portions copyright (C) 2009 Cisco Systems, Inc. */ #include #include diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c index 55a3fc5..beec158 100644 --- a/arch/mips/powertv/powertv_setup.c +++ b/arch/mips/powertv/powertv_setup.c @@ -1,20 +1,14 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. + * Copyright (C) 2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Steven J. Hill * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * Portions copyright (C) 2009 Cisco Systems, Inc. */ #include #include @@ -197,8 +191,7 @@ static int panic_handler(struct notifier_block *notifier_block, my_regs.cp0_status = read_c0_status(); } - pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " - "zzzz... \n"); + pr_crit("I'm feeling a bit sleepy. Perhaps a nap would...zzzz...\n"); return NOTIFY_DONE; } @@ -295,7 +288,7 @@ void platform_random_ether_addr(u8 addr[ETH_ALEN]) const unsigned char mac_addr_locally_managed = (1 << 1); if (!have_rfmac) { - pr_warning("rfmac not available on command line; " + pr_warn("rfmac not available on command line; " "generating random MAC address\n"); random_ether_addr(addr); } -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:52:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:59:30 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43600 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2FEVws (ORCPT ); Tue, 5 Jun 2012 23:52:48 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AT-000824-Fl; Tue, 05 Jun 2012 16:19:57 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 17/35] MIPS: Lasat: Cleanup files effected by firmware changes. Date: Tue, 5 Jun 2012 16:19:21 -0500 Message-Id: <1338931179-9611-18-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33548 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1646 Lines: 63 From: "Steven J. Hill" Make headers consistent across the files and make changes based on running the checkpatch script. Signed-off-by: Steven J. Hill --- arch/mips/lasat/prom.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c index 8bd3994..0091351 100644 --- a/arch/mips/lasat/prom.c +++ b/arch/mips/lasat/prom.c @@ -2,19 +2,18 @@ * PROM interface routines. */ #include -#include #include #include -#include #include #include #include +#include + #include #include -#include +#include #include "at93c.h" -#include #include "prom.h" #define RESET_VECTOR 0xbfc00000 @@ -58,7 +57,7 @@ static void setup_prom_vectors(void) __prom_putc = (void *)PROM_PUTC_ADDR; prom_monitor = (void *)PROM_MONITOR_ADDR; } - printk(KERN_DEBUG "prom vectors set up\n"); + pr_debug("prom vectors set up\n"); } static struct at93c_defs at93c_defs[N_MACHTYPES] = { @@ -84,11 +83,11 @@ void __init prom_init(void) setup_prom_vectors(); if (IS_LASAT_200()) { - printk(KERN_INFO "LASAT 200 board\n"); + pr_info("LASAT 200 board\n"); lasat_ndelay_divider = LASAT_200_DIVIDER; at93c = &at93c_defs[1]; } else { - printk(KERN_INFO "LASAT 100 board\n"); + pr_info("LASAT 100 board\n"); lasat_ndelay_divider = LASAT_100_DIVIDER; at93c = &at93c_defs[0]; } -- 1.7.10.3 From sjhill@mips.com Tue Jun 5 23:52:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Jun 2012 23:59:52 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:43602 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903743Ab2FEVwy (ORCPT ); Tue, 5 Jun 2012 23:52:54 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sc1AT-000824-0a; Tue, 05 Jun 2012 16:19:57 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 16/35] MIPS: Lasat: Cleanup firmware support for the Lasat platform. Date: Tue, 5 Jun 2012 16:19:20 -0500 Message-Id: <1338931179-9611-17-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-archive-position: 33549 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1105 Lines: 46 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/lasat/prom.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c index 20fde19..8bd3994 100644 --- a/arch/mips/lasat/prom.c +++ b/arch/mips/lasat/prom.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include @@ -81,9 +81,6 @@ static struct at93c_defs at93c_defs[N_MACHTYPES] = { void __init prom_init(void) { - int argc = fw_arg0; - char **argv = (char **) fw_arg1; - setup_prom_vectors(); if (IS_LASAT_200()) { @@ -98,11 +95,7 @@ void __init prom_init(void) lasat_init_board_info(); /* Read info from EEPROM */ - /* Get the command line */ - if (argc > 0) { - strncpy(arcs_cmdline, argv[0], COMMAND_LINE_SIZE-1); - arcs_cmdline[COMMAND_LINE_SIZE-1] = '\0'; - } + fw_init_cmdline(); /* Set the I/O base address */ set_io_port_base(KSEG1); -- 1.7.10.3 From yuasa@linux-mips.org Wed Jun 6 04:09:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 04:09:42 +0200 (CEST) Received: from mail-wg0-f43.google.com ([74.125.82.43]:37901 "EHLO mail-wg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901351Ab2FFCJg convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 04:09:36 +0200 Received: by wgbdr1 with SMTP id dr1so5236838wgb.24 for ; Tue, 05 Jun 2012 19:09:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=cPZ151Y6aGK5cKhj70/fonGE6C4r0st8Ka/c2P9f+dY=; b=WwTxHrZXCinEONce5uopVB0ExwajYiHyztQgmpY20VNvtptJ08LDeWMBSoXygmWvd8 y72YRQ66OAqCRYSgLGdCzVhgcLK9GWce3Cb7VcTICNy3aNWyRsyANIzIEnu0L+M3Wvrx 7cOPk+Fq8sz5b1Y0f1t+N4P6Rtc+YOWBWEoMQUBFtgdqsVYrn0EGvR5PFZ2Piwrn/uLA R+GwIgp91xU7WXMvIw0/bKgz9/xHVXLm6l5x5zuT1GxFIkHZIDPrfug4YqBQwrbEfHVF ACkmNVSpPLub1m+Pyg1eVuGxP/7D78q95tKFGAm7Jb5fdD/MbLGouBxTyYYUSleAIm9n Ql2g== MIME-Version: 1.0 Received: by 10.216.218.77 with SMTP id j55mr14586963wep.179.1338948570421; Tue, 05 Jun 2012 19:09:30 -0700 (PDT) Received: by 10.180.84.136 with HTTP; Tue, 5 Jun 2012 19:09:30 -0700 (PDT) In-Reply-To: <1338931179-9611-10-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-10-git-send-email-sjhill@mips.com> Date: Wed, 6 Jun 2012 11:09:30 +0900 X-Google-Sender-Auth: TATboqki2c51xhnUkc_XQmH6Q7E Message-ID: Subject: Re: [PATCH 09/35] MIPS: Cobalt: Cleanup files effected by firmware changes. From: Yuasa Yoichi To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 33550 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 398 Lines: 16 Hi, 2012/6/6 Steven J. Hill : > From: "Steven J. Hill" > > Make headers consistent across the files and make changes based on > running the checkpatch script. > > Signed-off-by: Steven J. Hill > --- >  arch/mips/cobalt/setup.c |   24 +++++++++++++----------- >  1 file changed, 13 insertions(+), 11 deletions(-) Do we really need it ? Yoichi From yuasa@linux-mips.org Wed Jun 6 04:14:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 04:14:51 +0200 (CEST) Received: from mail-wi0-f169.google.com ([209.85.212.169]:60812 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901351Ab2FFCOo convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 04:14:44 +0200 Received: by wibhn14 with SMTP id hn14so3649240wib.0 for ; Tue, 05 Jun 2012 19:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=WunF15KMlx/ITZq0G/k0BxX3A3ypS3lK4JFSKmc7jVI=; b=eHjZ+5DGg/7dKxuP4ktlgTH4KnPO/Au0BcMtU4XSa3OLtK8kthS2u+hif3F/mlS2TS vEZi/FfXtFNXg4egTPunS69JoTDyqfSFACYJaLYu6ptfd0ir/2Rzh4zlaxR+UiRMARG2 lkpmV7UYqNEQjq6+77+lLxMxprHJPKheCrq2JgGCWsG0u9yQ8g24Oo2GijhiRJJoVsQ/ ofC48OM+WBE4pbQW8yGKcV/2dM4P70IjStUEmTNWyME0B3d4ZG4DCzk2VKuY9e3HL2tG BblN67aTUiLsWKDlJZsSvh5xP3FEpwue2CqN6hPCI8S2+2mvMKHmI+4bSshMqbQyjdV3 ypKg== MIME-Version: 1.0 Received: by 10.216.213.79 with SMTP id z57mr15490279weo.27.1338948879127; Tue, 05 Jun 2012 19:14:39 -0700 (PDT) Received: by 10.180.84.136 with HTTP; Tue, 5 Jun 2012 19:14:39 -0700 (PDT) In-Reply-To: <1338931179-9611-36-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-36-git-send-email-sjhill@mips.com> Date: Wed, 6 Jun 2012 11:14:39 +0900 X-Google-Sender-Auth: JpJgQ4iHuymhbnkdBDYZiR5f3_o Message-ID: Subject: Re: [PATCH 35/35] MIPS: vr41xx: Cleanup files effected by firmware changes. From: Yuasa Yoichi To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 33551 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2083 Lines: 52 Hi, 2012/6/6 Steven J. Hill : > From: "Steven J. Hill" > > Make headers consistent across the files and make changes based on > running the checkpatch script. > > Signed-off-by: Steven J. Hill > --- >  arch/mips/vr41xx/common/init.c |   27 ++++++--------------------- >  1 file changed, 6 insertions(+), 21 deletions(-) > > diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c > index a2fa7f0..783b7f8 100644 > --- a/arch/mips/vr41xx/common/init.c > +++ b/arch/mips/vr41xx/common/init.c > @@ -1,30 +1,15 @@ >  /* > - *  init.c, Common initialization routines for NEC VR4100 series. > + * This file is subject to the terms and conditions of the GNU General Public > + * License.  See the file "COPYING" in the main directory of this archive > + * for more details. >  * > - *  Copyright (C) 2003-2009  Yoichi Yuasa > + * init.c, Common initialization routines for NEC VR4100 series. >  * > - *  This program is free software; you can redistribute it and/or modify > - *  it under the terms of the GNU General Public License as published by > - *  the Free Software Foundation; either version 2 of the License, or > - *  (at your option) any later version. > - * > - *  This program is distributed in the hope that it will be useful, > - *  but WITHOUT ANY WARRANTY; without even the implied warranty of > - *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the > - *  GNU General Public License for more details. > - * > - *  You should have received a copy of the GNU General Public License > - *  along with this program; if not, write to the Free Software > - *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA > + * Copyright (C) 2003-2009  Yoichi Yuasa > + * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved. >  */ > -#include > -#include ... > -#include These are required include files. Please remove only and Yoichi From sjhill@mips.com Wed Jun 6 04:18:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 04:18:26 +0200 (CEST) Received: from dns0.mips.com ([12.201.5.70]:35384 "EHLO dns0.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901351Ab2FFCSW convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 04:18:22 +0200 Received: from exchdb01.mips.com (exchhub01.mips.com [192.168.36.84]) by dns0.mips.com (8.13.8/8.13.8) with ESMTP id q562IFZo032542; Tue, 5 Jun 2012 19:18:15 -0700 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.01.0270.001; Tue, 5 Jun 2012 19:18:11 -0700 From: "Hill, Steven" To: Yuasa Yoichi CC: "linux-mips@linux-mips.org" Subject: RE: [PATCH 35/35] MIPS: vr41xx: Cleanup files effected by firmware changes. Thread-Topic: [PATCH 35/35] MIPS: vr41xx: Cleanup files effected by firmware changes. Thread-Index: AQHNQ2Uqk3LPmJqjHket7SHElRInu5btAs+A//+K8wc= Date: Wed, 6 Jun 2012 02:18:11 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146957B7@exchdb03.mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-36-git-send-email-sjhill@mips.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: DyBfI2dQs/j8YioUYJQPww== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 33552 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 224 Lines: 5 Yoichi, How are those include files required? I built a complete vr41xx kernel and that file did not produce any errors when being compiled with those headers removed. Did you try building a kernel with this patch? -Steve From yuasa@linux-mips.org Wed Jun 6 04:20:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 04:20:25 +0200 (CEST) Received: from mail-wg0-f43.google.com ([74.125.82.43]:42426 "EHLO mail-wg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901351Ab2FFCUS convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 04:20:18 +0200 Received: by wgbdr1 with SMTP id dr1so5241285wgb.24 for ; Tue, 05 Jun 2012 19:20:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=dtG6V1RJWsv91sD9+jC5WnDiHgcCe1TzoXpfq9AEGcA=; b=OvbS9w6SZq06WMtgdgmzrBoMGn1gYRU2uxKfEHS0kGVXiZvgII7P4e538w/8n5jbAX 2BOo6iiNBsW8YqSa0IMKp6v/XBb5bXm4FskPwBx3hVxI6y/C7EP72TAXP1Zto1B3Ae2D dLcCtgVBUNdwcdGY8OIA1RpMU/LKLxExmsCiX3IPeHkeMxxbnwNSMQCu6AA2lmAL22HR BwRmpE+DzSgfXv4qFLRTJ5dPGzxqoz7mMU470UUsTiwtZ8mHbsTcU2rJpWqOQT7CafBw 3677e13NS5g1yalbsgo6336WS8Q8VW0aki454VL8bxN1nHCo0VxCAc6D02is1h+fxxGa Th1Q== MIME-Version: 1.0 Received: by 10.216.212.157 with SMTP id y29mr15971709weo.146.1338949213227; Tue, 05 Jun 2012 19:20:13 -0700 (PDT) Received: by 10.180.84.136 with HTTP; Tue, 5 Jun 2012 19:20:13 -0700 (PDT) In-Reply-To: <1338931179-9611-35-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-35-git-send-email-sjhill@mips.com> Date: Wed, 6 Jun 2012 11:20:13 +0900 X-Google-Sender-Auth: EHGpRQIJemgdm3-A_cJT27sZIzg Message-ID: Subject: Re: [PATCH 34/35] MIPS: vr41xx: Cleanup firmware support for vr41xx platforms. From: Yuasa Yoichi To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 33553 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 578 Lines: 21 Hi, 2012/6/6 Steven J. Hill : > From: "Steven J. Hill" > > Signed-off-by: Steven J. Hill > --- >  arch/mips/vr41xx/common/init.c |   14 ++------------ >  1 file changed, 2 insertions(+), 12 deletions(-) > > diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c > index 2391632..a2fa7f0 100644 > --- a/arch/mips/vr41xx/common/init.c > +++ b/arch/mips/vr41xx/common/init.c > @@ -22,8 +22,8 @@ >  #include >  #include You can remove #include too. Yoichi From sjhill@mips.com Wed Jun 6 04:22:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 04:22:22 +0200 (CEST) Received: from dns0.mips.com ([12.201.5.70]:57909 "EHLO dns0.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901351Ab2FFCWT convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 04:22:19 +0200 Received: from exchdb01.mips.com (exchdb01.mips.com [192.168.36.67]) by dns0.mips.com (8.13.8/8.13.8) with ESMTP id q562MCB8032582; Tue, 5 Jun 2012 19:22:12 -0700 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([fe80::2897:a30d:a923:303%16]) with mapi id 14.01.0270.001; Tue, 5 Jun 2012 19:22:09 -0700 From: "Hill, Steven" To: Yuasa Yoichi CC: "linux-mips@linux-mips.org" Subject: RE: [PATCH 09/35] MIPS: Cobalt: Cleanup files effected by firmware changes. Thread-Topic: [PATCH 09/35] MIPS: Cobalt: Cleanup files effected by firmware changes. Thread-Index: AQHNQ2D2ambDCIYiNUKR2DJq4zDrnJbtAWcA//+NObs= Date: Wed, 6 Jun 2012 02:22:08 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146957C3@exchdb03.mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-10-git-send-email-sjhill@mips.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: Ve/n9ajk6SnD6jTjSc3jXQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 33554 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 229 Lines: 5 Yoichi, True, I added 2 additional lines. One to conform to the coding standard and another to add in our copyright line because I changed the file. If it really bothers you and others, I can certainly revert the patch. -Steve From sjhill@mips.com Wed Jun 6 04:28:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 04:28:05 +0200 (CEST) Received: from dns0.mips.com ([12.201.5.70]:48733 "EHLO dns0.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901351Ab2FFC2C convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 04:28:02 +0200 Received: from exchdb01.mips.com (exchhub01.mips.com [192.168.36.84]) by dns0.mips.com (8.13.8/8.13.8) with ESMTP id q562RtaL032653; Tue, 5 Jun 2012 19:27:55 -0700 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.01.0270.001; Tue, 5 Jun 2012 19:27:50 -0700 From: "Hill, Steven" To: Yuasa Yoichi CC: "linux-mips@linux-mips.org" Subject: RE: [PATCH 34/35] MIPS: vr41xx: Cleanup firmware support for vr41xx platforms. Thread-Topic: [PATCH 34/35] MIPS: vr41xx: Cleanup firmware support for vr41xx platforms. Thread-Index: AQHNQ2Ub+Ldobfs4Uk2rWbUNQNAysZbtBF2A//+MqCU= Date: Wed, 6 Jun 2012 02:27:50 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146957D8@exchdb03.mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-35-git-send-email-sjhill@mips.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: k4FWQwNYB5Vee//+8YVtbw== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 33555 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 58 Lines: 5 Yoichi, I did remove it in the next patch 35/35. -Steve From yuasa@linux-mips.org Wed Jun 6 04:33:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 04:33:14 +0200 (CEST) Received: from mail-wg0-f43.google.com ([74.125.82.43]:39013 "EHLO mail-wg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901351Ab2FFCdL (ORCPT ); Wed, 6 Jun 2012 04:33:11 +0200 Received: by wgbdr1 with SMTP id dr1so5246522wgb.24 for ; Tue, 05 Jun 2012 19:33:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=mdkszLX0jj4uK5iK73p6QNdRYR4Os8+enC2iyULn2/k=; b=oTeqEwHbxnhlg8Hkbh7mWngi264LiJ4g6SXjivYYRckxqY6l2fIKj6tt8CsN1pL7NZ 8AeJn2fbogkt1tHhC3pWtLIwDs4Y21PbZmCPHgwyPbQQ8nwvKboRN8iGE/QCGN9dSatg 1DEqWpnndLcWJYNE1o9iWVWFHgtVYBkxYbrW0HUYkz0DGLIvjbobeT9uzZfCh96ORFig fiuxmn9fplkaiS4dCPYc8PgVXn8uILQkHQUvqE9z5aAX/cfQrj9vSa4rCFeoMPHxUbyW lteJ3rCkOTtMFOqfrfK1gz5fdqojtcuZg+uettdb1gFu9WGj0sxDmhARmOGDHz85bMQo BcqQ== MIME-Version: 1.0 Received: by 10.216.212.157 with SMTP id y29mr15999186weo.146.1338949986083; Tue, 05 Jun 2012 19:33:06 -0700 (PDT) Received: by 10.180.84.136 with HTTP; Tue, 5 Jun 2012 19:33:06 -0700 (PDT) In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B801146957B7@exchdb03.mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-36-git-send-email-sjhill@mips.com> <31E06A9FC96CEC488B43B19E2957C1B801146957B7@exchdb03.mips.com> Date: Wed, 6 Jun 2012 11:33:06 +0900 X-Google-Sender-Auth: bKczRV8FOpPgO6eBhWvSubEv-NQ Message-ID: Subject: Re: [PATCH 35/35] MIPS: vr41xx: Cleanup files effected by firmware changes. From: Yuasa Yoichi To: "Hill, Steven" Cc: "linux-mips@linux-mips.org" Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33556 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 418 Lines: 13 Hi, 2012/6/6 Hill, Steven : > Yoichi, > > How are those include files required? I built a complete vr41xx kernel and that file did not produce any errors when being compiled with those headers removed. Did you try building a kernel with this patch? > It is not only build problem. We would like to include and explicitly because of __init and iomem_resource. Yoichi From yuasa@linux-mips.org Wed Jun 6 04:36:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 04:36:50 +0200 (CEST) Received: from mail-wi0-f171.google.com ([209.85.212.171]:59557 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903640Ab2FFCgq (ORCPT ); Wed, 6 Jun 2012 04:36:46 +0200 Received: by wibhm14 with SMTP id hm14so4028230wib.6 for ; Tue, 05 Jun 2012 19:36:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=4xLRDYfoPJsrC0hp2IIA3x8X9sqxQ584pIXGycviNC8=; b=px1IoiKnAH8umOKj/LY1IC1AT0NgoP7kFMPR7MaCW8VYfkjQA3oETeWcVBfXEswwdg 4A2bpvFTBslPe8YnJ5hq/1HVALpTfo30Sli0NloORjOyrK3i2gaLby7dw14i21NXJkjC bGphE+p2OpGhUSy/WcfNi9qYOYcMdj5OOEftSkAOVXcekTyBpfQRmriK81Tm+eM/VcRH FNGJYv7p+XOGyWO+v8HpOjSYHIikUKNHPZETCEjd/FLW8xhMCpOzPyCDIK/blFrvaVNj RyDkDwyF+nt6EQdv8FqAcH/PysdImQXQ9p9DBNiGXQtWCEDpDOuN/bmhKdbgEI1G/rdG AYPg== MIME-Version: 1.0 Received: by 10.216.205.5 with SMTP id i5mr15340976weo.6.1338950201270; Tue, 05 Jun 2012 19:36:41 -0700 (PDT) Received: by 10.180.84.136 with HTTP; Tue, 5 Jun 2012 19:36:41 -0700 (PDT) In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B801146957D8@exchdb03.mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-35-git-send-email-sjhill@mips.com> <31E06A9FC96CEC488B43B19E2957C1B801146957D8@exchdb03.mips.com> Date: Wed, 6 Jun 2012 11:36:41 +0900 X-Google-Sender-Auth: kePwLLzUUcCOAPnQywpN9B0xPTs Message-ID: Subject: Re: [PATCH 34/35] MIPS: vr41xx: Cleanup firmware support for vr41xx platforms. From: Yuasa Yoichi To: "Hill, Steven" Cc: "linux-mips@linux-mips.org" Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33557 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 159 Lines: 13 Hi, 2012/6/6 Hill, Steven : > Yoichi, > > I did remove it in the next patch 35/35. > Please include in the related change. Thanks, Yoichi From KHarken@bluevalleyk12.org Wed Jun 6 07:25:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 07:25:31 +0200 (CEST) Received: from tx2outboundsmtppool2.messaging.microsoft.com ([65.55.83.132]:34681 "EHLO TX2EHSNDR001.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1901761Ab2FFFZY convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 07:25:24 +0200 Received: from tx2outboundpool.messaging.microsoft.com (10.9.14.236) by TX2EHSNDR001.bigfish.com (10.9.40.50) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 6 Jun 2012 05:24:34 +0000 Received: from mail185-tx2-R.bigfish.com (10.9.14.244) by TX2EHSOBE005.bigfish.com (10.9.40.25) with Microsoft SMTP Server id 14.1.225.23; Wed, 6 Jun 2012 05:24:34 +0000 Received: from mail185-tx2 (localhost [127.0.0.1]) by mail185-tx2-R.bigfish.com (Postfix) with ESMTP id 70EEB2601B8; Wed, 6 Jun 2012 05:24:33 +0000 (UTC) X-Forefront-Antispam-Report: CIP:204.52.179.108;KIP:(null);UIP:(null);IPV:NLI;H:VM235401.bluevalleyk12.org;RD:vm235401.bluevalleyk12.org;EFVD:NLI X-BigFish: VPS47(zzd334imcc19imzz1202hzz8275bhz2fh2a8h668h839hd25hf0aha02m) X-FB-OUTBOUND-SPAM: yes X-SpamScore: 47 Received-SPF: pass (mail185-tx2: domain of bluevalleyk12.org designates 204.52.179.108 as permitted sender) client-ip=204.52.179.108; envelope-from=KHarken@bluevalleyk12.org; helo=VM235401.bluevalleyk12.org ;alleyk12.org ; Received: from mail185-tx2 (localhost.localdomain [127.0.0.1]) by mail185-tx2 (MessageSwitch) id 1338960272415128_11261; Wed, 6 Jun 2012 05:24:32 +0000 (UTC) Received: from TX2EHSMHS020.bigfish.com (unknown [10.9.14.236]) by mail185-tx2.bigfish.com (Postfix) with ESMTP id D449536005B; Wed, 6 Jun 2012 05:24:31 +0000 (UTC) Received: from VM235401.bluevalleyk12.org (204.52.179.108) by TX2EHSMHS020.bigfish.com (10.9.99.120) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 6 Jun 2012 05:24:31 +0000 Received: from VM235301.EMP.BV (10.106.97.45) by VM235401.bluevalleyk12.org (172.16.6.108) with Microsoft SMTP Server (TLS) id 8.2.234.1; Wed, 6 Jun 2012 00:25:42 -0500 Received: from VM235101.EMP.BV ([fe80::e4e7:5029:b4df:caff]) by VM235301.EMP.BV ([fe80::f02a:26fb:6a0f:eb97%11]) with mapi; Wed, 6 Jun 2012 00:25:13 -0500 From: "Harken, Karel" Date: Wed, 6 Jun 2012 00:25:12 -0500 Subject: Thread-Index: AQHNQ6S/ueiOHzJ3hkGLH+e6ZfxBbw== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7BIT MIME-Version: 1.0 To: Undisclosed recipients:; X-FOPE-CRA-Verdict: 204.52.179.108$multicare.org%14251%4%bluevalleyk12.org%False%False%0$ou.edu%0%1%bluevalleyk12.org%False%False%0$pa.press.net%0%1%bluevalleyk12.org%False%False%0$nmsu.edu%0%1%bluevalleyk12.org%False%False%0$memphis.edu%0%1%bluevalleyk12.org%False%False%0$ Reply-To: X-OriginatorOrg: bluevalleyk12.org X-archive-position: 33558 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: KHarken@bluevalleyk12.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 979 Lines: 8 My wife Violet and I Allen Large won $11.3 million in a lottery 6-49 in July and we have decided to donate the sum of $500,000.00 USD to you,as part of our charity project to improve the lot of 10 lucky individuals all over the world from our $11.3 million Jackpot Lottery winning fund. Contact us via our personal email for details: a_v.large@hotmail.com --------------- Blue Valley Schools - Education Beyond Expectations --------------- This e-mail (including any attachments) is confidential and intended solely for the use of the intended recipient. Any review, reliance, disclosure, copying, dissemination or distribution by others or forwarding without express permission is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. Further, the sender accepts no responsibility for any damage caused by any virus, spyware, malware, or other malicious code transmitted by this e-mail. From john@phrozen.org Wed Jun 6 07:39:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 07:39:27 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:53122 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901761Ab2FFFjX (ORCPT ); Wed, 6 Jun 2012 07:39:23 +0200 Message-ID: <4FCEECE8.8010901@phrozen.org> Date: Wed, 06 Jun 2012 07:38:48 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH 15/35] MIPS: lantiq: Cleanup files effected by firmware changes. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-16-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-16-git-send-email-sjhill@mips.com> X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33559 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1564 Lines: 55 On 05/06/12 23:19, Steven J. Hill wrote: > From: "Steven J. Hill" > > Make headers consistent across the files and make changes based on > running the checkpatch script. i dont see any checkpatch related changes > > Signed-off-by: Steven J. Hill > --- > arch/mips/lantiq/prom.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c > index aa9da9e..56470c6 100644 > --- a/arch/mips/lantiq/prom.c > +++ b/arch/mips/lantiq/prom.c > @@ -1,15 +1,15 @@ > /* > - * This program is free software; you can redistribute it and/or modify it > - * under the terms of the GNU General Public License version 2 as published > - * by the Free Software Foundation. > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > * The change in License is not related to the Subject / commit message. Why do you change the license in the first place ? the code was GPLv2 and after your change it only GPL ? NAK on this one ... > * Copyright (C) 2010 John Crispin > + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. Does a include fixup justify a Copyright holder change ? > */ > - > #include > #include > #include > -#include > +#include > > #include > #include From info@westernunion.com Wed Jun 6 08:41:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 08:41:07 +0200 (CEST) Received: from out-62.smtp.ucla.edu ([169.232.46.172]:50894 "EHLO out-62.smtp.ucla.edu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903649Ab2FFGlD convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 08:41:03 +0200 Received: from smtp-12.smtp.ucla.edu (smtp-12.smtp.ucla.edu [169.232.46.245]) by out-62.smtp.ucla.edu with ESMTP id q566cEi1027613; Tue, 05 Jun 2012 23:38:18 -0700 Received: from mail.ucla.edu (m5.mail.ucla.edu [128.97.27.133]) by smtp-12.smtp.ucla.edu (8.14.3/8.14.3) with ESMTP id q566cEi1027613; Tue, 5 Jun 2012 23:38:14 -0700 Received: from [10.18.33.34] (173.234.157.202.rdns.ubiquityservers.com [173.234.157.202] (may be forged)) (user=dharmon mech=LOGIN bits=0) by mail.ucla.edu (8.14.3/8.14.3/Debian-9.4) with ESMTP id q566bpcb013598 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 5 Jun 2012 23:38:09 -0700 Message-Id: <201206060638.q566bpcb013598@mail.ucla.edu> Content-Type: text/plain; charset=US-ASCII MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Description: Mail message body Subject: Hello To: Recipients From: "western union" Date: Wed, 06 Jun 2012 07:38:07 +0100 Reply-To: w.union1@rogers.com X-Probable-Spam: no X-Scanned-By: smtp.ucla.edu on 169.232.46.245 X-archive-position: 33560 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: info@westernunion.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 348 Lines: 5 We wish to inform you that We have sent $5000.00 USD already ,that was given to you by the European Union, as we are mandated to send you the total sum of 1,000,000,00 USD through Western Union.send name,address, phone number.Processing your first payment of 5,000 USD. Sign, Barr. Roland Owen (Payment Officer) Phone Number: Tel +(44) 7417556070 From alex.shi@intel.com Wed Jun 6 08:54:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 08:54:57 +0200 (CEST) Received: from mga11.intel.com ([192.55.52.93]:47370 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2FFGyw (ORCPT ); Wed, 6 Jun 2012 08:54:52 +0200 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 05 Jun 2012 23:54:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="175368209" Received: from debian.sh.intel.com ([10.239.13.3]) by fmsmga002.fm.intel.com with ESMTP; 05 Jun 2012 23:54:39 -0700 From: Alex Shi To: a.p.zijlstra@chello.nl Cc: anton@samba.org, benh@kernel.crashing.org, cmetcalf@tilera.com, dhowells@redhat.com, davem@davemloft.net, fenghua.yu@intel.com, hpa@zytor.com, ink@jurassic.park.msu.ru, linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, mattst88@gmail.com, paulus@samba.org, lethal@linux-sh.org, ralf@linux-mips.org, rth@twiddle.net, sparclinux@vger.kernel.org, tony.luck@intel.com, x86@kernel.org, sivanich@sgi.com, greg.pearson@hp.com, kamezawa.hiroyu@jp.fujitsu.com, bob.picco@oracle.com, chris.mason@oracle.com, torvalds@linux-foundation.org, akpm@linux-foundation.org, mingo@kernel.org, pjt@google.com, tglx@linutronix.de, seto.hidetoshi@jp.fujitsu.com, ak@linux.intel.com, arjan.van.de.ven@intel.com Subject: [RFC PATCH] sched/numa: do load balance between remote nodes Date: Wed, 6 Jun 2012 14:52:51 +0800 Message-Id: <1338965571-9812-1-git-send-email-alex.shi@intel.com> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 33561 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex.shi@intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1289 Lines: 35 commit cb83b629b remove the NODE sched domain and check if the node distance in SLIT table is farther than REMOTE_DISTANCE, if so, it will lose the load balance chance at exec/fork/wake_affine points. But actually, even the node distance is farther than REMOTE_DISTANCE, Modern CPUs also has QPI like connections, that make memory access is not too slow between nodes. So above losing on NUMA machine make a huge performance regression on benchmark: hackbench, tbench, netperf and oltp etc. This patch will recover the scheduler behavior to old mode on all my Intel platforms: NHM EP/EX, WSM EP, SNB EP/EP4S, and so remove the perfromance regressions. (all of them just has 2 kinds distance, 10 21) Signed-off-by: Alex Shi --- kernel/sched/core.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 39eb601..b2ee41a 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -6286,7 +6286,7 @@ static int sched_domains_curr_level; static inline int sd_local_flags(int level) { - if (sched_domains_numa_distance[level] > REMOTE_DISTANCE) + if (sched_domains_numa_distance[level] > RECLAIM_DISTANCE) return 0; return SD_BALANCE_EXEC | SD_BALANCE_FORK | SD_WAKE_AFFINE; -- 1.7.5.4 From c.jayachandran@gmail.com Wed Jun 6 10:42:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 10:42:39 +0200 (CEST) Received: from mail-wg0-f43.google.com ([74.125.82.43]:37421 "EHLO mail-wg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903643Ab2FFImf convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 10:42:35 +0200 Received: by wgbdr1 with SMTP id dr1so5461947wgb.24 for ; Wed, 06 Jun 2012 01:42:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=RO2+4VCm8Jy9LlRVXIy1XN4+6oJISVASfEE8jxtx8u4=; b=NHJb8olNtT0G4MGQYu8ppEl7qArfsLSx4uxcCvlfP2oThBB45knpsD7EVckVksdIc9 zCdMOXY28RmVf30fi3SFlbj2PByKo3FRtwtaRmthnFhza3wocs0CGAt7W9hrA/1oOHNq pFzvkNb/xkXFWaiPOEnMwLOoaO0+VvLe9KrJ+8LEhTQXy52oiNbYnEdFzmHKjiCRhpMr 5T4dnC+urN9AZtnQcUT8ETDAinaCjTU24FNgd+PsIA4IonywbMvhYieHuP5NBvU3OQCq KYAGBVyKuykO2jbi9SXyuq24RoqPOmww6caXuhLDTAfes8x4Yb+1AgmOt/SrbpRgty+k MiXQ== MIME-Version: 1.0 Received: by 10.216.218.138 with SMTP id k10mr16991750wep.222.1338972150164; Wed, 06 Jun 2012 01:42:30 -0700 (PDT) Received: by 10.216.152.33 with HTTP; Wed, 6 Jun 2012 01:42:30 -0700 (PDT) In-Reply-To: <1338931179-9611-24-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-24-git-send-email-sjhill@mips.com> Date: Wed, 6 Jun 2012 14:12:30 +0530 Message-ID: Subject: Re: [PATCH 23/35] MIPS: Netlogic: Cleanup files effected by firmware changes. From: "Jayachandran C." To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 33562 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: c.jayachandran@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1443 Lines: 39 On Wed, Jun 6, 2012 at 2:49 AM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Make headers consistent across the files and make changes based on > running the checkpatch script. > > Signed-off-by: Steven J. Hill > --- >  arch/mips/netlogic/xlr/setup.c |   35 +++++------------------------------ >  1 file changed, 5 insertions(+), 30 deletions(-) > > diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c > index 113a402..324c071 100644 > --- a/arch/mips/netlogic/xlr/setup.c > +++ b/arch/mips/netlogic/xlr/setup.c > @@ -1,37 +1,12 @@ >  /* > + * This file is subject to the terms and conditions of the GNU General Public > + * License.  See the file "COPYING" in the main directory of this archive > + * for more details. > + * >  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights >  * reserved. > - * > - * This software is available to you under a choice of one of two > - * licenses.  You may choose to be licensed under the terms of the GNU > - * General Public License (GPL) Version 2, available from the file > - * COPYING in the main directory of this source tree, or the NetLogic > - * license below: > - * [....] > - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved. >  */ Can you drop this? This patch changes the existing license on the file. Thanks, JC. From a.p.zijlstra@chello.nl Wed Jun 6 11:02:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 11:02:11 +0200 (CEST) Received: from merlin.infradead.org ([205.233.59.134]:54479 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2FFJCB convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 11:02:01 +0200 Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1ScC7b-0006JF-Kj; Wed, 06 Jun 2012 09:01:43 +0000 Received: from dhcp-089-099-019-018.chello.nl ([89.99.19.18] helo=twins) by canuck.infradead.org with esmtpsa (Exim 4.76 #1 (Red Hat Linux)) id 1ScC7a-00083k-MZ; Wed, 06 Jun 2012 09:01:43 +0000 Received: by twins (Postfix, from userid 1000) id 8D8C88028D56; Wed, 6 Jun 2012 11:01:35 +0200 (CEST) Message-ID: <1338973295.2749.81.camel@twins> Subject: Re: [RFC PATCH] sched/numa: do load balance between remote nodes From: Peter Zijlstra To: Alex Shi Cc: anton@samba.org, benh@kernel.crashing.org, cmetcalf@tilera.com, dhowells@redhat.com, davem@davemloft.net, fenghua.yu@intel.com, hpa@zytor.com, ink@jurassic.park.msu.ru, linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, mattst88@gmail.com, paulus@samba.org, lethal@linux-sh.org, ralf@linux-mips.org, rth@twiddle.net, sparclinux@vger.kernel.org, tony.luck@intel.com, x86@kernel.org, sivanich@sgi.com, greg.pearson@hp.com, kamezawa.hiroyu@jp.fujitsu.com, bob.picco@oracle.com, chris.mason@oracle.com, torvalds@linux-foundation.org, akpm@linux-foundation.org, mingo@kernel.org, pjt@google.com, tglx@linutronix.de, seto.hidetoshi@jp.fujitsu.com, ak@linux.intel.com, arjan.van.de.ven@intel.com Date: Wed, 06 Jun 2012 11:01:35 +0200 In-Reply-To: <1338965571-9812-1-git-send-email-alex.shi@intel.com> References: <1338965571-9812-1-git-send-email-alex.shi@intel.com> Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7BIT X-Mailer: Evolution 3.2.2- Mime-Version: 1.0 X-archive-position: 33563 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: a.p.zijlstra@chello.nl Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 393 Lines: 11 On Wed, 2012-06-06 at 14:52 +0800, Alex Shi wrote: > - if (sched_domains_numa_distance[level] > REMOTE_DISTANCE) > + if (sched_domains_numa_distance[level] > RECLAIM_DISTANCE) I actually considered this.. I just felt a little uneasy re-purposing the RECLAIM_DISTANCE for this, but I guess its all the same anyway. Both mean expensive-away-distance. So I've taken this. thanks! From sshtylyov@mvista.com Wed Jun 6 12:53:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 12:53:55 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:43316 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903701Ab2FFKxs (ORCPT ); Wed, 6 Jun 2012 12:53:48 +0200 Received: by lbbgg6 with SMTP id gg6so5571848lbb.36 for ; Wed, 06 Jun 2012 03:53:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=JRMtM/xQ9SjDwq/z3PCRH9ufA39d3vEDy7KviIycajs=; b=GWmWDdo0EHDRpCS44NNwZe5zXp186FWReWj7NK3ZAdsTZGZXsVrv8ABW2FOe/acv3c XuJpkAW4+dPPel29+DECNTFOwdT8xRY31LNlslEWiy+vIBjOQroMFH02cU5QuKbcw1eb 61mzfmYjDrmmBBeJznEb4am6Cjp5ZZp+VQeacx7TkOoh3WCyMXSYxYhRXgnsfHkm2tI3 7rOAAuDnx/he0AERmgx4humS8CL2jMWK9b67HQw27dC54in7813Y+WcjHc6vQQSk/XA+ 434bb7i+lnOLLfVuqjUzMb5so+S+qtApZTgSLIQXdvvFUIhBsa1hVDkh7qGN6VEpAHY8 /MQA== Received: by 10.112.25.106 with SMTP id b10mr9656161lbg.36.1338980021871; Wed, 06 Jun 2012 03:53:41 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-86-181.pppoe.mtu-net.ru. [91.79.86.181]) by mx.google.com with ESMTPS id hm7sm2270479lab.12.2012.06.06.03.53.36 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 03:53:40 -0700 (PDT) Message-ID: <4FCF3694.206@mvista.com> Date: Wed, 06 Jun 2012 14:53:08 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: Alex Shi CC: a.p.zijlstra@chello.nl, anton@samba.org, benh@kernel.crashing.org, cmetcalf@tilera.com, dhowells@redhat.com, davem@davemloft.net, fenghua.yu@intel.com, hpa@zytor.com, ink@jurassic.park.msu.ru, linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, mattst88@gmail.com, paulus@samba.org, lethal@linux-sh.org, ralf@linux-mips.org, rth@twiddle.net, sparclinux@vger.kernel.org, tony.luck@intel.com, x86@kernel.org, sivanich@sgi.com, greg.pearson@hp.com, kamezawa.hiroyu@jp.fujitsu.com, bob.picco@oracle.com, chris.mason@oracle.com, torvalds@linux-foundation.org, akpm@linux-foundation.org, mingo@kernel.org, pjt@google.com, tglx@linutronix.de, seto.hidetoshi@jp.fujitsu.com, ak@linux.intel.com, arjan.van.de.ven@intel.com Subject: Re: [RFC PATCH] sched/numa: do load balance between remote nodes References: <1338965571-9812-1-git-send-email-alex.shi@intel.com> In-Reply-To: <1338965571-9812-1-git-send-email-alex.shi@intel.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQngGdQ8DF+gcqoXhZYntN02t0UbITXR4tQ/dd8f8MOjt7R2UOE8qIm3bTgMvw99RGv9rQna X-archive-position: 33564 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 919 Lines: 28 Hello. On 06-06-2012 10:52, Alex Shi wrote: > commit cb83b629b Please also specify that commit's summary in parens. > remove the NODE sched domain and check if the node > distance in SLIT table is farther than REMOTE_DISTANCE, if so, it will > lose the load balance chance at exec/fork/wake_affine points. > But actually, even the node distance is farther than REMOTE_DISTANCE, > Modern CPUs also has QPI like connections, that make memory access is "Is" not needed here. > not too slow between nodes. So above losing on NUMA machine make a > huge performance regression on benchmark: hackbench, tbench, netperf > and oltp etc. > This patch will recover the scheduler behavior to old mode on all my > Intel platforms: NHM EP/EX, WSM EP, SNB EP/EP4S, and so remove the > perfromance regressions. (all of them just has 2 kinds distance, 10 21) > Signed-off-by: Alex Shi WBR, Sergei From sshtylyov@mvista.com Wed Jun 6 13:16:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 13:16:44 +0200 (CEST) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:55576 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903701Ab2FFLQh (ORCPT ); Wed, 6 Jun 2012 13:16:37 +0200 Received: by laap9 with SMTP id p9so5416610laa.36 for ; Wed, 06 Jun 2012 04:16:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=sFmgQBUHXrJpgpC3G8PWO8FDqDIWGA2PHVlbjHauysc=; b=QDF6zGd1HQuLmalFavrQDLXpbA7c6RDX1d7A0fYpZN36K8moxrVghRxABdjgnegU/b lAued9MeByfZ3WeONV9ZCbepYtMphL2siQhEljOUGyIqXhnqjnApuxwzMYJN/mcAW8Cl AY92cTDkwBBLOnwR/zgVngqn6YQs3KnRV1E9oRTIfIq+qc/LRZoP/xl+DBy8qIr4Bum6 XApmjMEjDRk5ZVQvKkDI0BQT+Cn1qS6KXdgB4JmJg1gUJ8IZMrmfR8uIrk+H0r4eqNQq /fM9rPMX6ugyGoLHWaXGEEx1MbEI01Oyzjs1zmPLFBOEXjZaZFJTLpXl2fgpIgZT/KMh zE4Q== Received: by 10.112.42.66 with SMTP id m2mr9781104lbl.46.1338981392207; Wed, 06 Jun 2012 04:16:32 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-86-181.pppoe.mtu-net.ru. [91.79.86.181]) by mx.google.com with ESMTPS id hg4sm2354681lab.11.2012.06.06.04.16.29 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 04:16:30 -0700 (PDT) Message-ID: <4FCF3BF0.8070405@mvista.com> Date: Wed, 06 Jun 2012 15:16:00 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 07/35] MIPS: ath79: Cleanup files effected by firmware changes. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-8-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-8-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQmy+1Ice67bCCo/veZ6KDN0T1IGAhf8iD69avMjrc0yDdd+JAr49xoY/AS2SSXEw6fledQS X-archive-position: 33565 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1548 Lines: 48 Hello. On 06-06-2012 1:19, Steven J. Hill wrote: > From: "Steven J. Hill" > Make headers consistent across the files and make changes based on > running the checkpatch script. > Signed-off-by: Steven J. Hill > --- > arch/mips/ath79/prom.c | 13 +++++-------- > 1 file changed, 5 insertions(+), 8 deletions(-) > > diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c > index adbe614..9ead18a 100644 > --- a/arch/mips/ath79/prom.c > +++ b/arch/mips/ath79/prom.c > @@ -1,18 +1,15 @@ > /* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * Why move/change this text at all? > * Atheros AR71XX/AR724X/AR913X specific prom routines > * > * Copyright (C) 2008-2010 Gabor Juhos > * Copyright (C) 2008 Imre Kaloz > - * > - * This program is free software; you can redistribute it and/or modify it > - * under the terms of the GNU General Public License version 2 as published > - * by the Free Software Foundation. > + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. > */ > - > -#include > -#include > #include > -#include Removing a few #include's doesn't justify copyrighting the file. You generally need to do some substantial change (some people say about 1/3) to the file to claim the copyright. WBR, Sergei From sshtylyov@mvista.com Wed Jun 6 13:30:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 13:30:39 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:48857 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903701Ab2FFLaZ (ORCPT ); Wed, 6 Jun 2012 13:30:25 +0200 Received: by lbbgg6 with SMTP id gg6so5595463lbb.36 for ; Wed, 06 Jun 2012 04:30:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=hjMUFcH82isCIfSMV0byNX+bLNYsf/wry2UDjS/Je/k=; b=a7Ke3Sc9RMBDbPE8fgqG1xj6jHhbLVDgb2t9W/86sidx0kcQdVoEVUbkK7R0YSPRdl 5xsjVUeCBhiqhNZFk0K4WnSoU7L7ARNZ+mMcrVaCDxaN//r6MZJVJMgwK/MyqEBiJzUm 4ZEWCfrw48fAjf2Xnz7HDqA0/Dfd152vBPIaqsUl/uEd4hfzDrgM6szeN0AMdm3NRtST eguG8bO9tZhdAeCtCW26iuWXPtgWxCzBVU8YJl8X1ZYhQQ/v08lZNlGFlSuvt+UVGnMj BFpkqZoB0saE0vxS6zkV1X20jS1S/x5sK2HUryH1hY1N/NBI+T0xVuvEy6rfip73BEjo tqXg== Received: by 10.112.36.195 with SMTP id s3mr9698482lbj.42.1338982218500; Wed, 06 Jun 2012 04:30:18 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-86-181.pppoe.mtu-net.ru. [91.79.86.181]) by mx.google.com with ESMTPS id hm7sm2401053lab.12.2012.06.06.04.30.16 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 04:30:16 -0700 (PDT) Message-ID: <4FCF3F2B.1090908@mvista.com> Date: Wed, 06 Jun 2012 15:29:47 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 11/35] MIPS: Emma: Cleanup files effected by firmware changes. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-12-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-12-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlOzZrthcueGV/rh1nU+qxbg7i0n0dS/GHug63LC1izag6/l5+PeKhWiIVFBiUA0C0Dgl/x X-archive-position: 33566 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2149 Lines: 53 Hello. On 06-06-2012 1:19, Steven J. Hill wrote: > From: "Steven J. Hill" > Make headers consistent across the files and make changes based on > running the checkpatch script. I don't see any checkpatch.pl-related changes. > Signed-off-by: Steven J. Hill > --- > arch/mips/emma/common/prom.c | 25 ++++++++----------------- > 1 file changed, 8 insertions(+), 17 deletions(-) > diff --git a/arch/mips/emma/common/prom.c b/arch/mips/emma/common/prom.c > index 5228584..9a70c4e 100644 > --- a/arch/mips/emma/common/prom.c > +++ b/arch/mips/emma/common/prom.c > @@ -1,23 +1,14 @@ > /* > - * Copyright (C) NEC Electronics Corporation 2004-2006 > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > * > - * This file is based on the arch/mips/ddb5xxx/common/prom.c > + * This is based on the arch/mips/ddb5xxx/common/prom.c file. > + * GPR board platform device registration (Au1550) > * > - * Copyright 2001 MontaVista Software Inc. > - * > - * This program is free software; you can redistribute it and/or modify > - * it under the terms of the GNU General Public License as published by > - * the Free Software Foundation; either version 2 of the License, or > - * (at your option) any later version. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, write to the Free Software > - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + * Copyright 2001 MontaVista Software Inc. > + * Copyright (C) NEC Electronics Corporation 2004-2006 > + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. Reshuffling the header again hardly qualifies for adding a copyright. WBR, Sergei From sshtylyov@mvista.com Wed Jun 6 13:38:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 13:39:00 +0200 (CEST) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:44072 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2FFLix (ORCPT ); Wed, 6 Jun 2012 13:38:53 +0200 Received: by laap9 with SMTP id p9so5431394laa.36 for ; Wed, 06 Jun 2012 04:38:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=echVHvWgnlwZVC3szW0NdIatkZFHnnb6bvVPbWSD050=; b=A8Skxntx00QwhJzY1Zht2emH/JN8Urx1CuHxF08fVj4CA8DF0ybwBx+lN3dLxjKOlM y8QNDobADECMJZw6O/0qB/+xfJHRat/fadCaSaZ5zS0j10THiGFbRqieDQlWp0V8l1oh 8AHJWMiKxDnQVf5BhKK03o3AP0qNK+zuA4q08dyOIFCKwY9mGqzhh7k/pRxBJgFnQkwz CgPgFgMkJEYWUfJT6N1YRoDaVHkIcY1YQPD+qGlhp3UstWh9C1oiZYspqIvuBAYGxThK +K3ANHKPi+BXNs/clXIdauy3F7G5CpDZd5hj2N5kEv7Gi2KjnEq9u5iAlWZ76S28L+vi D3JA== Received: by 10.112.43.67 with SMTP id u3mr9765833lbl.16.1338982728117; Wed, 06 Jun 2012 04:38:48 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-86-181.pppoe.mtu-net.ru. [91.79.86.181]) by mx.google.com with ESMTPS id hz16sm2441386lab.6.2012.06.06.04.38.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 04:38:47 -0700 (PDT) Message-ID: <4FCF4129.2010308@mvista.com> Date: Wed, 06 Jun 2012 15:38:17 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 13/35] MIPS: jz4740: Cleanup files effected by firmware changes. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-14-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-14-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlh3uqdiKw/6Cz8+P2ZDXCa6iuXnslJlfXK1XhPZsEj34Qz5mU1cQUv757SWgRNG26OGxSk X-archive-position: 33567 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1863 Lines: 52 Hello. On 06-06-2012 1:19, Steven J. Hill wrote: > From: "Steven J. Hill" > Make headers consistent across the files and make changes based on > running the checkpatch script. > Signed-off-by: Steven J. Hill > --- > arch/mips/jz4740/prom.c | 25 +++++++++---------------- > 1 file changed, 9 insertions(+), 16 deletions(-) > diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c > index c5071ab..ea86605 100644 > --- a/arch/mips/jz4740/prom.c > +++ b/arch/mips/jz4740/prom.c > @@ -1,23 +1,14 @@ > /* > - * Copyright (C) 2010, Lars-Peter Clausen > - * JZ4740 SoC prom code > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > * > - * This program is free software; you can redistribute it and/or modify it > - * under the terms of the GNU General Public License as published by the > - * Free Software Foundation; either version 2 of the License, or (at your > - * option) any later version. > - * > - * You should have received a copy of the GNU General Public License along > - * with this program; if not, write to the Free Software Foundation, Inc., > - * 675 Mass Ave, Cambridge, MA 02139, USA. > + * JZ4740 SoC prom code > * > + * Copyright (C) 2010, Lars-Peter Clausen > + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. > */ > - > #include > -#include > -#include This header is needed explicitly because '__init' qualifier is used. Documentation/SubmitChecklist says: 1: If you use a facility then #include the file that defines/declares that facility. Don't depend on other header files pulling in ones that you use. WBR, Sergei From sshtylyov@mvista.com Wed Jun 6 13:54:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 13:54:44 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:55874 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903702Ab2FFLyh (ORCPT ); Wed, 6 Jun 2012 13:54:37 +0200 Received: by lbbgg6 with SMTP id gg6so5611777lbb.36 for ; Wed, 06 Jun 2012 04:54:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=9gwX2NkMYw24RdHTGsTPs/SkkfiONXisE8ioSbU1rMo=; b=ENQgS2ldI/Hbi88EqOQ/s6s6VHBVSXuusQhd3WmmD2SJgvWLXCtNo1OZbkEUTlwo83 4nE7LSR/cY34RKF0409lq7D7tUmiEjD6BQRm/5kKCoct3/ho35tre7tT6aXdmodiNmWR QWYI443mHQrghfifTyhdMRXPruvqA4a7zi2dn5GCvn4ZtfHjJlhz0v6tVwOtGyKG4Db6 oIpjsZPiU2zdDRV6ybsJmTbKVtyi0VmHHEt1QFSq/mDdSFpqcnL4UPWlp+qV3cEVJ/eg l68rGHAuNTNpNdY0HffhRdR++zuZOJp9visxFSgcme/+OoDu3ISecMP19s5Yb4A2IcC0 Y0zA== Received: by 10.112.36.130 with SMTP id q2mr9628303lbj.44.1338983672336; Wed, 06 Jun 2012 04:54:32 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-86-181.pppoe.mtu-net.ru. [91.79.86.181]) by mx.google.com with ESMTPS id s3sm984939lbk.11.2012.06.06.04.54.30 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 04:54:31 -0700 (PDT) Message-ID: <4FCF44D9.1020407@mvista.com> Date: Wed, 06 Jun 2012 15:54:01 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 17/35] MIPS: Lasat: Cleanup files effected by firmware changes. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-18-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-18-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQl+u/oeor1+4oqkfzSwp1VA98dOMnEm21A/pToFIWG2ZeJ27OpNsrJPNAQEQbVzor09Vln3 X-archive-position: 33568 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1228 Lines: 46 Hello. On 06-06-2012 1:19, Steven J. Hill wrote: > From: "Steven J. Hill" > Make headers consistent across the files It's the case where you don't do it (forgot? :-). > and make changes based on running the checkpatch script. > Signed-off-by: Steven J. Hill > --- > arch/mips/lasat/prom.c | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) > > diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c > index 8bd3994..0091351 100644 > --- a/arch/mips/lasat/prom.c > +++ b/arch/mips/lasat/prom.c > @@ -2,19 +2,18 @@ > * PROM interface routines. > */ > #include > -#include No, it should be left intact because '__init' is used. > #include > #include > -#include Doesn't the code use printk()? > @@ -58,7 +57,7 @@ static void setup_prom_vectors(void) > __prom_putc = (void *)PROM_PUTC_ADDR; > prom_monitor = (void *)PROM_MONITOR_ADDR; > } > - printk(KERN_DEBUG "prom vectors set up\n"); > + pr_debug("prom vectors set up\n"); Changes behavior: now you need to #define DEBUG at the start of file for anything to be printed here. WBR, Sergei From sshtylyov@mvista.com Wed Jun 6 14:00:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 14:00:48 +0200 (CEST) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:52714 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2FFMAi (ORCPT ); Wed, 6 Jun 2012 14:00:38 +0200 Received: by laap9 with SMTP id p9so5445843laa.36 for ; Wed, 06 Jun 2012 05:00:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=k0kNoxVdlgyIFS6sUzcZc810q/vU4ZpqhukRrjGLqe0=; b=ZhAKxiRwklLp2mX8poDfSLK01BJ9t8N3POgGm8xRVre+jFsPh5ikDtHC1acrPORHg2 sGVIDioQ2pdAwaJ7e8YEyVXavyYi6al6KSxCpcBK0fBNtKbrZOWn3ccWqsgXtGhIbpgY BtudnW0TUX4nLogIvRnnIEJvxr5MokKiXSZBJHc0PR0UNliFGF/fjhHTOmiuKc+E0A/c 6djgQvPbjantbaGIguCo6LdejPVH15uFcAazgIWmOyR5pHQ77sjqwcjWbX4Z9IJwCosD zNaG+jkDjCa7hWyT99MdFdTnVIffcWjSqAkUCRyfz6mlqWk7Z7Gyo/EWdzC31AgzjmUB XJLg== Received: by 10.112.83.169 with SMTP id r9mr9657841lby.66.1338984032864; Wed, 06 Jun 2012 05:00:32 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-86-181.pppoe.mtu-net.ru. [91.79.86.181]) by mx.google.com with ESMTPS id ta2sm2502470lab.15.2012.06.06.05.00.30 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 05:00:31 -0700 (PDT) Message-ID: <4FCF4641.2060906@mvista.com> Date: Wed, 06 Jun 2012 16:00:01 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 23/35] MIPS: Netlogic: Cleanup files effected by firmware changes. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-24-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-24-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQmuT2w3zAj58ufWx2VHV4r7mgZIaoiOZ2VgbmxuHuaQ4EdBuvL8+ZPIpf6jfIHadc/Ho+0n X-archive-position: 33569 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2799 Lines: 65 Hello. On 06-06-2012 1:19, Steven J. Hill wrote: > From: "Steven J. Hill" > Make headers consistent across the files and make changes based on > running the checkpatch script. I don't see any checkpatch.pl induced changes. > Signed-off-by: Steven J. Hill > --- > arch/mips/netlogic/xlr/setup.c | 35 +++++------------------------------ > 1 file changed, 5 insertions(+), 30 deletions(-) > > diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c > index 113a402..324c071 100644 > --- a/arch/mips/netlogic/xlr/setup.c > +++ b/arch/mips/netlogic/xlr/setup.c > @@ -1,37 +1,12 @@ > /* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * You removed the NetLogic license. > * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights > * reserved. > - * > - * This software is available to you under a choice of one of two > - * licenses. You may choose to be licensed under the terms of the GNU > - * General Public License (GPL) Version 2, available from the file > - * COPYING in the main directory of this source tree, or the NetLogic > - * license below: > - * > - * Redistribution and use in source and binary forms, with or without > - * modification, are permitted provided that the following conditions > - * are met: > - * > - * 1. Redistributions of source code must retain the above copyright > - * notice, this list of conditions and the following disclaimer. > - * 2. Redistributions in binary form must reproduce the above copyright > - * notice, this list of conditions and the following disclaimer in > - * the documentation and/or other materials provided with the > - * distribution. > - * > - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR > - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED > - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE > - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE > - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR > - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, > - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE > - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN > - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. Reshuffling the header is not really a good reason for adding your copyright. WBR, Sergei From lars@metafoo.de Wed Jun 6 14:10:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 14:10:27 +0200 (CEST) Received: from smtp-out-134.synserver.de ([212.40.185.134]:1110 "EHLO smtp-out-123.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903702Ab2FFMKX (ORCPT ); Wed, 6 Jun 2012 14:10:23 +0200 Received: (qmail 14120 invoked by uid 0); 6 Jun 2012 12:10:13 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@metafoo.de X-SynServer-PPID: 14017 Received: from p5491e52a.dip.t-dialin.net (HELO ?192.168.0.176?) [84.145.229.42] by 217.119.54.77 with AES256-SHA encrypted SMTP; 6 Jun 2012 12:10:12 -0000 Message-ID: <4FCF4973.8090907@metafoo.de> Date: Wed, 06 Jun 2012 14:13:39 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.4) Gecko/20120510 Icedove/10.0.4 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 12/35] MIPS: jz4740: Cleanup firmware support for the JZ4740 platform. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-13-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-13-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33570 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1199 Lines: 52 On 06/05/2012 11:19 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Signed-off-by: Steven J. Hill Acked-by: Lars-Peter Clausen > --- > arch/mips/jz4740/prom.c | 25 ++----------------------- > 1 file changed, 2 insertions(+), 23 deletions(-) > > diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c > index 4a70407..c5071ab 100644 > --- a/arch/mips/jz4740/prom.c > +++ b/arch/mips/jz4740/prom.c > @@ -20,33 +20,12 @@ > > #include > > -#include > +#include > #include > > -static __init void jz4740_init_cmdline(int argc, char *argv[]) > -{ > - unsigned int count = COMMAND_LINE_SIZE - 1; > - int i; > - char *dst = &(arcs_cmdline[0]); > - char *src; > - > - for (i = 1; i < argc && count; ++i) { > - src = argv[i]; > - while (*src && count) { > - *dst++ = *src++; > - --count; > - } > - *dst++ = ' '; > - } > - if (i > 1) > - --dst; > - > - *dst = 0; > -} > - > void __init prom_init(void) > { > - jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1); > + fw_init_cmdline(); > mips_machtype = MACH_INGENIC_JZ4740; > } > From florian@openwrt.org Wed Jun 6 14:18:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 14:19:02 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:41098 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903702Ab2FFMS4 (ORCPT ); Wed, 6 Jun 2012 14:18:56 +0200 Received: by eaaf11 with SMTP id f11so2596690eaa.36 for ; Wed, 06 Jun 2012 05:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:user-agent:in-reply-to :references:mime-version:content-transfer-encoding:content-type; bh=35Jv+ojJ3S6a5u+sSR+3ZGDqBmTQhAXuqvw73DEqe1w=; b=cuez03qQ9bnQlmQlnzyfXqH+rxvTQqMZ3MdQEJHGOuZ0r27lZjKEnao/oM5jHW+4tu NEfMox3rgL5ew2XUi4tJFdFqmU7Y/6x8snM9G3fCYItc3+tsEM9gy0dQGgrc8qMyt+Pt cYU/AeoNUwjro+N3KVves4izyEFH/SWa/6ESEv/vjQWfN8SuS+MG7Vax0S99qhDIBVMq 7U0F9wha4poPQZqmJ3o1jy2MPssZ33T9m/NbdbEZ70ow66xgtA6uCz2yz8AMDtHfZ6rI eGwoWg411HedSKscCOWsiMRKjH+TgL2R3aP34USs+0yowbxUMBQ956hSQenKHd4En8J2 F6mw== Received: by 10.14.119.6 with SMTP id m6mr10666121eeh.165.1338985130768; Wed, 06 Jun 2012 05:18:50 -0700 (PDT) Received: from flexo.localnet ([2a01:e34:ec0d:4090:7dc0:e3ad:a3a1:b40c]) by mx.google.com with ESMTPS id f16sm5848565eec.2.2012.06.06.05.18.48 (version=SSLv3 cipher=OTHER); Wed, 06 Jun 2012 05:18:48 -0700 (PDT) From: Florian Fainelli To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: Re: [PATCH 00/35] Cleanup firmware support across multiple platforms. Date: Wed, 06 Jun 2012 14:16:36 +0200 Message-ID: <7001181.e1a1v1VHCx@flexo> User-Agent: KMail/4.8.3 (Linux/3.2.0-24-generic; KDE/4.8.3; x86_64; ; ) In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-archive-position: 33571 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8146 Lines: 140 Hi Steven, On Tuesday 05 June 2012 16:19:04 Steven J. Hill wrote: > From: "Steven J. Hill" > > The firmware/bootloader support code has been duplicated across a lot > of platforms and continues to self-replicate. These patches move the > support code into the common 'arch/mips/fw/lib' directory. All affected > platforms have been built and produce a linked kernel. Any files that > were modified also had their headers cleaned up and the checkpatch > script ran on them. The rationale for your patches look good to me, as well as the impressive diffstat. You seem to be mixing fixes with cleanups however. Otherwise, for the AR7 and RB532 bits, you have my ack. > > Steven J. Hill (35): > MIPS: Add environment variable processing code to firmware library. > MIPS: Alchemy: Cleanup firmware support for Alchemy platforms. > MIPS: Alchemy: Cleanup files effected by firmware changes. > MIPS: AR7: Cleanup firmware support for the AR7 platform. > MIPS: AR7: Cleanup files effected by firmware changes. > MIPS: ath79: Cleanup firmware support for the ath79 platform. > MIPS: ath79: Cleanup files effected by firmware changes. > MIPS: Cobalt: Cleanup firmware support for the Cobalt platform. > MIPS: Cobalt: Cleanup files effected by firmware changes. > MIPS: Emma: Cleanup firmware support for the Emma platform. > MIPS: Emma: Cleanup files effected by firmware changes. > MIPS: jz4740: Cleanup firmware support for the JZ4740 platform. > MIPS: jz4740: Cleanup files effected by firmware changes. > MIPS: lantiq: Cleanup firmware support for the lantiq platform. > MIPS: lantiq: Cleanup files effected by firmware changes. > MIPS: Lasat: Cleanup firmware support for the Lasat platform. > MIPS: Lasat: Cleanup files effected by firmware changes. > MIPS: Loongson: Cleanup firmware support for the Loongson platform. > MIPS: Loongson: Cleanup files effected by firmware changes. > MIPS: Malta: Cleanup firmware support for the Malta platform. > MIPS: Malta: Cleanup files effected by firmware changes. > MIPS: Netlogic: Cleanup firmware support for the XLR platform. > MIPS: Netlogic: Cleanup files effected by firmware changes. > MIPS: MSP71xx, Yosemite: Cleanup firmware support for PMC platforms. > MIPS: MSP71xx, Yosemite: Cleanup files effected by firmware changes. > MIPS: PNX83xx, PNX8550: Cleanup firmware support for PNX platforms. > MIPS: PNX83xx, PNX8550: Cleanup files effected by firmware changes. > MIPS: PowerTV: Cleanup firmware support for PowerTV platform. > MIPS: PowerTV: Cleanup files effected by firmware changes. > MIPS: RB532: Cleanup firmware support for RB532 platform. > MIPS: RB532: Cleanup files effected by firmware changes. > MIPS: txx9: Cleanup firmware support for txx9 platforms. > MIPS: txx9: Cleanup files effected by firmware changes. > MIPS: vr41xx: Cleanup firmware support for vr41xx platforms. > MIPS: vr41xx: Cleanup files effected by firmware changes. > > arch/mips/alchemy/board-gpr.c | 48 ++--- > arch/mips/alchemy/board-mtx1.c | 48 ++--- > arch/mips/alchemy/board-xxs1500.c | 45 ++--- > arch/mips/alchemy/common/platform.c | 30 +-- > arch/mips/alchemy/common/prom.c | 79 ++------ > arch/mips/alchemy/devboards/db1000.c | 1 - > arch/mips/alchemy/devboards/db1300.c | 1 - > arch/mips/alchemy/devboards/db1550.c | 1 - > arch/mips/alchemy/devboards/pb1100.c | 1 - > arch/mips/alchemy/devboards/pb1500.c | 1 - > arch/mips/alchemy/devboards/prom.c | 54 ++--- > arch/mips/ar7/memory.c | 22 +-- > arch/mips/ar7/platform.c | 63 +++--- > arch/mips/ar7/prom.c | 62 ++---- > arch/mips/ar7/setup.c | 26 +-- > arch/mips/ath79/prom.c | 33 +--- > arch/mips/cobalt/setup.c | 42 ++-- > arch/mips/emma/common/prom.c | 44 +---- > arch/mips/fw/lib/Makefile | 2 + > arch/mips/fw/lib/cmdline.c | 86 ++++++++ > arch/mips/include/asm/fw/fw.h | 47 +++++ > arch/mips/include/asm/mach-ar7/prom.h | 25 --- > arch/mips/include/asm/mach-au1x00/au1xxx_eth.h | 1 + > arch/mips/include/asm/mach-au1x00/prom.h | 12 -- > arch/mips/include/asm/mach-loongson/loongson.h | 54 ++--- > arch/mips/include/asm/mips-boards/generic.h | 30 +-- > arch/mips/include/asm/mips-boards/prom.h | 47 ----- > .../mips/include/asm/pmc-sierra/msp71xx/msp_prom.h | 52 +---- > arch/mips/include/asm/txx9/generic.h | 1 - > arch/mips/jz4740/prom.c | 50 ++--- > arch/mips/lantiq/prom.c | 32 +-- > arch/mips/lasat/prom.c | 24 +-- > arch/mips/loongson/common/Makefile | 2 +- > arch/mips/loongson/common/cmdline.c | 48 ----- > arch/mips/loongson/common/env.c | 40 ++-- > arch/mips/loongson/common/init.c | 16 +- > arch/mips/mti-malta/Makefile | 2 +- > arch/mips/mti-malta/malta-cmdline.c | 59 ------ > arch/mips/mti-malta/malta-display.c | 40 ++-- > arch/mips/mti-malta/malta-init.c | 157 +++------------ > arch/mips/mti-malta/malta-memory.c | 108 ++++------ > arch/mips/mti-malta/malta-setup.c | 59 ++---- > arch/mips/mti-malta/malta-time.c | 65 ++---- > arch/mips/netlogic/xlr/setup.c | 82 ++------ > arch/mips/pmc-sierra/msp71xx/msp_prom.c | 207 +++++--------------- > arch/mips/pmc-sierra/msp71xx/msp_serial.c | 69 +++---- > arch/mips/pmc-sierra/msp71xx/msp_setup.c | 43 ++-- > arch/mips/pmc-sierra/msp71xx/msp_time.c | 75 ++----- > arch/mips/pmc-sierra/msp71xx/msp_usb.c | 45 ++--- > arch/mips/pmc-sierra/yosemite/prom.c | 46 ++--- > arch/mips/pnx833x/common/Makefile | 2 +- > arch/mips/pnx833x/common/prom.c | 64 ------ > arch/mips/pnx833x/common/setup.c | 39 ++-- > arch/mips/pnx833x/stb22x/board.c | 70 +++---- > arch/mips/pnx8550/common/Makefile | 2 +- > arch/mips/pnx8550/common/prom.c | 128 ------------ > arch/mips/pnx8550/common/setup.c | 69 +++---- > arch/mips/pnx8550/jbs/init.c | 45 +---- > arch/mips/pnx8550/stb810/prom_init.c | 36 +--- > arch/mips/powertv/asic/asic_int.c | 45 ++--- > arch/mips/powertv/init.c | 81 ++------ > arch/mips/powertv/memory.c | 39 ++-- > arch/mips/powertv/powertv_setup.c | 29 +-- > arch/mips/rb532/prom.c | 69 +++---- > arch/mips/txx9/generic/setup.c | 85 ++------ > arch/mips/vr41xx/common/init.c | 41 +--- > drivers/mtd/maps/pmcmsp-flash.c | 58 ++---- > drivers/net/ethernet/amd/au1000_eth.c | 1 - > 68 files changed, 890 insertions(+), 2240 deletions(-) > create mode 100644 arch/mips/fw/lib/cmdline.c > create mode 100644 arch/mips/include/asm/fw/fw.h > delete mode 100644 arch/mips/include/asm/mach-ar7/prom.h > delete mode 100644 arch/mips/include/asm/mach-au1x00/prom.h > delete mode 100644 arch/mips/include/asm/mips-boards/prom.h > delete mode 100644 arch/mips/loongson/common/cmdline.c > delete mode 100644 arch/mips/mti-malta/malta-cmdline.c > delete mode 100644 arch/mips/pnx833x/common/prom.c > delete mode 100644 arch/mips/pnx8550/common/prom.c > > -- > 1.7.10.3 > > -- Florian From lars@metafoo.de Wed Jun 6 14:22:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 14:22:19 +0200 (CEST) Received: from smtp-out-134.synserver.de ([212.40.185.134]:1053 "EHLO smtp-out-123.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903708Ab2FFMWN (ORCPT ); Wed, 6 Jun 2012 14:22:13 +0200 Received: (qmail 19790 invoked by uid 0); 6 Jun 2012 12:15:31 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@metafoo.de X-SynServer-PPID: 18612 Received: from p5491e52a.dip.t-dialin.net (HELO ?192.168.0.176?) [84.145.229.42] by 217.119.54.77 with AES256-SHA encrypted SMTP; 6 Jun 2012 12:15:31 -0000 Message-ID: <4FCF4A99.7090501@metafoo.de> Date: Wed, 06 Jun 2012 14:18:33 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.4) Gecko/20120510 Icedove/10.0.4 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 13/35] MIPS: jz4740: Cleanup files effected by firmware changes. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-14-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-14-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33572 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2220 Lines: 69 On 06/05/2012 11:19 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Make headers consistent across the files and make changes based on > running the checkpatch script. Why is the cleanup not in the inital patch? > > Signed-off-by: Steven J. Hill > --- > arch/mips/jz4740/prom.c | 25 +++++++++---------------- > 1 file changed, 9 insertions(+), 16 deletions(-) > > diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c > index c5071ab..ea86605 100644 > --- a/arch/mips/jz4740/prom.c > +++ b/arch/mips/jz4740/prom.c > @@ -1,23 +1,14 @@ > /* > - * Copyright (C) 2010, Lars-Peter Clausen > - * JZ4740 SoC prom code > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > * > - * This program is free software; you can redistribute it and/or modify it > - * under the terms of the GNU General Public License as published by the > - * Free Software Foundation; either version 2 of the License, or (at your > - * option) any later version. > - * > - * You should have received a copy of the GNU General Public License along > - * with this program; if not, write to the Free Software Foundation, Inc., > - * 675 Mass Ave, Cambridge, MA 02139, USA. > + * JZ4740 SoC prom code > * > + * Copyright (C) 2010, Lars-Peter Clausen > + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. > */ Please don't randomly change the license of files. > - > #include > -#include > -#include > -#include > - Why can't this be in the previous patch which removed the custom fw args parser? > #include > > #include > @@ -33,7 +24,9 @@ void __init prom_free_prom_memory(void) > { > } > > -#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2))) > +#define UART_REG(_reg) \ > + ((volatile void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + \ > + (_reg << 2))) > Why did you add volatile here? > void prom_putchar(char c) > { From juhosg@openwrt.org Wed Jun 6 15:04:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 15:04:49 +0200 (CEST) Received: from arrakis.dune.hu ([78.24.191.176]:36571 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2FFNEn (ORCPT ); Wed, 6 Jun 2012 15:04:43 +0200 X-Virus-Scanned: at arrakis.dune.hu Received: from [192.168.254.129] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id AFB8A23C007C; Wed, 6 Jun 2012 15:04:37 +0200 (CEST) Message-ID: <4FCF5565.2040909@openwrt.org> Date: Wed, 06 Jun 2012 15:04:37 +0200 From: Gabor Juhos MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 06/35] MIPS: ath79: Cleanup firmware support for the ath79 platform. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-7-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-7-git-send-email-sjhill@mips.com> X-Enigmail-Version: 1.4.1 Content-Type: text/plain; charset=ISO-8859-2 Content-Transfer-Encoding: 8bit X-archive-position: 33573 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1646 Lines: 61 Hi Steven, 2012.06.05. 23:19 keltezéssel, Steven J. Hill írta: > From: "Steven J. Hill" > > Signed-off-by: Steven J. Hill > --- > arch/mips/ath79/prom.c | 20 ++++---------------- > 1 file changed, 4 insertions(+), 16 deletions(-) > > diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c > index e9cbd7c..adbe614 100644 > --- a/arch/mips/ath79/prom.c > +++ b/arch/mips/ath79/prom.c > @@ -14,7 +14,7 @@ > #include > #include > > -#include > +#include > #include > > #include "common.h" > @@ -32,23 +32,11 @@ static inline int is_valid_ram_addr(void *addr) > return 0; > } > > -static __init void ath79_prom_init_cmdline(int argc, char **argv) > -{ > - int i; > - > - if (!is_valid_ram_addr(argv)) > - return; > - > - for (i = 0; i < argc; i++) > - if (is_valid_ram_addr(argv[i])) { Please don't remove this validation. The Atheros AR7xxx/AR9xxx based boards are using various bootloaders. Some of them puts insane values in argv, and this validation ensures that the kernel will not crash with them. > - strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); > - strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); > - } > -} > - > void __init prom_init(void) > { > - ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1); > + if (!is_valid_ram_addr((int *)fw_arg1)) The 'is_valid_ram_addr' function requires a 'void *' argument, so it would be more precise to use that instead of 'int *' in the cast. > + return; > + fw_init_cmdline(); > } > > void __init prom_free_prom_memory(void) -Gabor From geert@linux-m68k.org Wed Jun 6 15:27:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 15:27:42 +0200 (CEST) Received: from mail-yw0-f49.google.com ([209.85.213.49]:35854 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2FFN1g convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 15:27:36 +0200 Received: by yhjj52 with SMTP id j52so5336359yhj.36 for ; Wed, 06 Jun 2012 06:27:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=474hVnNMj6QmIQKH9a/maAI24fzXcAeTTtuMI9498OE=; b=hyqzNgkOxwyLX/kAH9X5a8OPOst6Dfq+6F0Ylb/UVCGoQtgMtlUHmg622VwMoC8Mlv ULN78Qdp7B6fjkdBoq8aWltgKcbX/ocUqxOHDz2LUyViE0q/dlk7+2Be90lO6qqwVCfq Yc6x1StTncrR/gbHM74rDmREhzFsbvbgJPBH4sMqWVNrza61JeOgKCNLADwml9NADbws a/D3C8nM4M0WTjUZtvFg9HIbAE4PP+tT7baLOqoVs3imsAWf1jH/rVv6Wld76fSm4T86 aeodJhOzCrF/SQ/MdOwXAnziiC8UwqEls1b7+xojFseSd1V5HxBW5/AB1mRAQqf1je4L kZQQ== MIME-Version: 1.0 Received: by 10.50.100.169 with SMTP id ez9mr6438841igb.44.1338989249668; Wed, 06 Jun 2012 06:27:29 -0700 (PDT) Received: by 10.231.135.1 with HTTP; Wed, 6 Jun 2012 06:27:29 -0700 (PDT) In-Reply-To: <1338931179-9611-33-git-send-email-sjhill@mips.com> References: <1338931179-9611-1-git-send-email-sjhill@mips.com> <1338931179-9611-33-git-send-email-sjhill@mips.com> Date: Wed, 6 Jun 2012 15:27:29 +0200 X-Google-Sender-Auth: S9DR8d6KEfEvYToEnNqw4Y_0s_I Message-ID: Subject: Re: [PATCH 32/35] MIPS: txx9: Cleanup firmware support for txx9 platforms. From: Geert Uytterhoeven To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 33574 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2129 Lines: 65 Hi Steven, On Tue, Jun 5, 2012 at 11:19 PM, Steven J. Hill wrote: > --- a/arch/mips/txx9/generic/setup.c > +++ b/arch/mips/txx9/generic/setup.c > @@ -25,11 +25,11 @@ >  #include >  #include >  #include > -#include >  #include >  #include >  #include >  #include > +#include >  #include >  #include >  #include > @@ -157,39 +157,6 @@ static struct txx9_board_vec *__init find_board_byname(const char *name) >        return NULL; >  } > > -static void __init prom_init_cmdline(void) > -{ > -       int argc; > -       int *argv32; > -       int i;                  /* Always ignore the "-c" at argv[0] */ > - > -       if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { > -               /* > -                * argc is not a valid number, or argv32 is not a valid > -                * pointer > -                */ > -               argc = 0; > -               argv32 = NULL; > -       } else { > -               argc = (int)fw_arg0; > -               argv32 = (int *)fw_arg1; > -       } > - > @@ -378,7 +345,7 @@ static void __init select_board(void) > >  void __init prom_init(void) >  { > -       prom_init_cmdline(); > +       fw_init_cmdline(); This basically reverts commit 97b0511ce125b0cb95d73b198c1bdbb3cebc4de2 ("MIPS: TXx9: Make firmware parameter passing more robust"), so it's gonna die horribly on RBTX4927 with VxWorks bootloader. Can you add the checks to fw_init_cmdline()? I guess they don't harm on other boards anyway. Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.                                 -- Linus Torvalds From clouds.yan@gmail.com Wed Jun 6 16:17:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 16:17:04 +0200 (CEST) Received: from mail-wi0-f171.google.com ([209.85.212.171]:45163 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903709Ab2FFORA convert rfc822-to-8bit (ORCPT ); Wed, 6 Jun 2012 16:17:00 +0200 Received: by wibhm14 with SMTP id hm14so4513056wib.6 for ; Wed, 06 Jun 2012 07:16:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type :content-transfer-encoding; bh=F0GQkF328vovscqME/w+K3HSK/78VvCgkZAa2KZhIYg=; b=mo56qXmS/zPwI2XHXGw/tHahtZRvijhufqjrXGIBZiJQ2msNqS38M+Gd/jwo/EiMYL uT2ivy5gRmHymIX7F4kET7LM4W6xYGRhcFxoYGVCjUfu7lm1gRpVvWMgJaegSUhDrYoR 9tmSPY7uSE/XmPZtPW2YEBEx8UKSy1xxYAemXL+uln6agUszpe9mQ625qxPhI1ekWGKg O9ygl2pQAnaTXZM7ET+HBed2N6mcVxi6BOTD3oAaUfgJg4D9gaESaC3M7IsKYDL34ApC xSS6KBLw3fazSsHYi2yOlkJOmnUhaY7svQ7cMUaJxXwNNz5HJuhxzoCsVTog5Cf5T+Td mcNA== MIME-Version: 1.0 Received: by 10.216.198.1 with SMTP id u1mr17373729wen.92.1338992214659; Wed, 06 Jun 2012 07:16:54 -0700 (PDT) Received: by 10.194.1.100 with HTTP; Wed, 6 Jun 2012 07:16:54 -0700 (PDT) Date: Wed, 6 Jun 2012 22:16:54 +0800 Message-ID: Subject: Symbol address in instructions is different from that in symbol table From: yan yan To: linux-mips@linux-mips.org Content-Type: text/plain; charset=GB2312 Content-Transfer-Encoding: 8BIT X-archive-position: 33575 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: clouds.yan@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 372 Lines: 10 Hi, all: I'm new to mips.When I disassembled a linux vmlinux, I found variable address referenced in instructions have a constant difference 64K respect to that in symbol table. For example, instruction/s want to reference a variable and construct its address XXX3YYYY by lui and addui£¬but in system map, its address is actually XXX2YYYY. What happens? Thanks From ddaney.cavm@gmail.com Wed Jun 6 23:50:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Jun 2012 23:50:34 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:56016 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903712Ab2FFVu2 (ORCPT ); Wed, 6 Jun 2012 23:50:28 +0200 Received: by dadm1 with SMTP id m1so10111154dad.36 for ; Wed, 06 Jun 2012 14:50:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=wCTwCHyCXV0QncUkmP1/ohK9HAxV7rNc81EjmPAOxYA=; b=CpRtpx+e1n+oapskvNtfNT9GaYxzgkDXIMMB7aSrtmdGFGSaU8TAMAc7FPjCmVG78C 5a85QwH/KWcCkYb4eJdrD0InK2sN7nYUhloCZEnXagMKIJQl5V8ZyaEr013CK0aGQ8s2 U1rc+XAsFtcSIGZa049Kngg0V0exJLDzb84iFtgX5xYBedIqFvPnsUFEKoNGkWdXYwoa s6JVIn1j/zXnQTXw4FaKwEOSL7M3RSjFhXwqeDzjewN6MvH6XKa2Qh2Qwchz9N8F2VSD +ZffvdPiF0zhOWi4M3VnKiuBKshs1OKNGMXqZ3xdtw8aEwftIIA7S30sbdHdrScB5ooR yUVg== Received: by 10.68.197.198 with SMTP id iw6mr1420488pbc.36.1339019421830; Wed, 06 Jun 2012 14:50:21 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id vc6sm1665715pbc.6.2012.06.06.14.50.20 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 14:50:20 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56LoJ1i010778; Wed, 6 Jun 2012 14:50:19 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56LoInq010777; Wed, 6 Jun 2012 14:50:18 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Octeon: Implement Octeon specific __copy_user_inatomic Date: Wed, 6 Jun 2012 14:50:17 -0700 Message-Id: <1339019417-10745-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33576 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1758 Lines: 69 From: David Daney The generic version seems to prefetch past the end of memory. Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-memcpy.S | 16 ++++++++++++---- 1 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S index 88e0cdd..d55bd6a 100644 --- a/arch/mips/cavium-octeon/octeon-memcpy.S +++ b/arch/mips/cavium-octeon/octeon-memcpy.S @@ -164,6 +164,14 @@ .set noat /* + * t7 is used as a flag to note inatomic mode. + */ +LEAF(__copy_user_inatomic) + b __copy_user_common + li t7, 1 + END(__copy_user_inatomic) + +/* * A combined memcpy/__copy_user * __copy_user sets len to 0 for success; else to an upper bound of * the number of uncopied bytes. @@ -174,6 +182,8 @@ LEAF(memcpy) /* a0=dst a1=src a2=len */ move v0, dst /* return value */ __memcpy: FEXPORT(__copy_user) + li t7, 0 /* not inatomic */ +__copy_user_common: /* * Note: dst & src may be unaligned, len may be 0 * Temps @@ -412,7 +422,6 @@ l_exc_copy: * Assumes src < THREAD_BUADDR($28) */ LOAD t0, TI_TASK($28) - nop LOAD t0, THREAD_BUADDR(t0) 1: EXC( lb t1, 0(src), l_exc) @@ -422,10 +431,9 @@ EXC( lb t1, 0(src), l_exc) ADD dst, dst, 1 l_exc: LOAD t0, TI_TASK($28) - nop LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address - nop SUB len, AT, t0 # len number of uncopied bytes + bnez t7, 2f /* Skip the zeroing out part if inatomic */ /* * Here's where we rely on src and dst being incremented in tandem, * See (3) above. @@ -443,7 +451,7 @@ l_exc: ADD dst, dst, 1 bnez src, 1b SUB src, src, 1 - jr ra +2: jr ra nop -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:44:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:44:31 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:59893 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903712Ab2FFWoZ (ORCPT ); Thu, 7 Jun 2012 00:44:25 +0200 Received: by dadm1 with SMTP id m1so10165382dad.36 for ; Wed, 06 Jun 2012 15:44:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=NbJm++N3EOuWNKjGtDF80XLq5ym67GX8W7GS0kw8rmI=; b=u7Cs2Ip+Vwi4Il2yKkFL0MVZLl01FJVIlVjVoS9/1uD7ikv6Xpmzcd7JB1Rv/wUUSq brbtaopTafdAUJ7QOR0ZbLHd/BQMlgNSnG2+pmtULJbXPrMo6Fi5To0UxrtrqJ0pcFf1 fYU5GU7oMUBxoFtLHDEy6eh8fkoTw2NwLm9bK7QU2A69a+7yLs1aYVBbFrz4HzRHtzFE OQ/GOl6iiCRSOSikNMe0CY/KtKmbD9ta5iylHHWEAoyDQIGIyDIdKqQfdXcOa/2vzyAB a5J84G3LaPk2NyUVeD1Us4nMCPW6C2CxWyOcHqsUfZYzm5VjfXcWoZLRwhvc/M0sXhii IArA== Received: by 10.68.237.74 with SMTP id va10mr1969227pbc.46.1339022658675; Wed, 06 Jun 2012 15:44:18 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ve6sm1765119pbc.75.2012.06.06.15.44.17 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:44:17 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56MiGTu019896; Wed, 6 Jun 2012 15:44:16 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56MiGHr019894; Wed, 6 Jun 2012 15:44:16 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v2 0/3] MIPS: OCTEON: irq handling improvements. Date: Wed, 6 Jun 2012 15:44:12 -0700 Message-Id: <1339022655-19860-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33577 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 800 Lines: 30 From: David Daney v2: Small bug fix in the GPIO interrupt handling. Rebased. v1: These three patches are prerequisites for the follow-on device tree patches, although they don't touch or use any device tree functionality. 1/3: Handle GPIO interrupts and their triggering. 2/3: Remove a bunch of unused OCTEON_IRQ_ symbols. 3/3: Remove some duplicate definitions. David Daney (3): MIPS: Octeon: Add irq handlers for GPIO interrupts. MIPS: OCTEON: Remove unneeded OCTEON_IRQ_* defines. MIPS: OCTEON: Consolidate the edge and level irq_chip structures. arch/mips/cavium-octeon/octeon-irq.c | 184 ++++++++++++++--------- arch/mips/include/asm/mach-cavium-octeon/irq.h | 40 +----- 2 files changed, 114 insertions(+), 110 deletions(-) -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:44:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:44:57 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:35406 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903717Ab2FFWoZ (ORCPT ); Thu, 7 Jun 2012 00:44:25 +0200 Received: by dadm1 with SMTP id m1so10165393dad.36 for ; Wed, 06 Jun 2012 15:44:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=aMdfuud0U9TgoKaWBG/64MW5iD4pXPaZLtdIHnnXCJY=; b=vAfP8IoNaHazbsmDIBVZs/uuNNnlwZCF8H+etWAENkOggOsqDWFBa8Rnx3k34yNicC R4VOKKaaKMYf7+cp+WW6EtE6ETyUqH3GvbW/5cHbyf9r4nERP0PWO45AJ9hPL1zfQ9AG B7t3v4nowLtXviAHQs3h6exsnPlL9tV0MmR7RGKHlhBJkAIv/IO24qZguwXtaPqseBQE kMGOlVhm/PqYUuGZII98wOSanNgJUOMuiZogw2IjI9iO4aZEsQ0vFwxTPN8ZQevOwqUl 0+heML0SxU5wqzJXQbboqudfxdWIVGSYS6tZMliwy9qytmdW8/S4iEv2b3IKIyfvcoQu sJmw== Received: by 10.68.131.10 with SMTP id oi10mr982615pbb.122.1339022659105; Wed, 06 Jun 2012 15:44:19 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id of1sm1795059pbb.15.2012.06.06.15.44.17 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:44:17 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56MiGqt019904; Wed, 6 Jun 2012 15:44:16 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56MiGDo019903; Wed, 6 Jun 2012 15:44:16 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v2 2/3] MIPS: OCTEON: Remove unneeded OCTEON_IRQ_* defines. Date: Wed, 6 Jun 2012 15:44:14 -0700 Message-Id: <1339022655-19860-3-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339022655-19860-1-git-send-email-ddaney.cavm@gmail.com> References: <1339022655-19860-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33578 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6696 Lines: 144 From: David Daney The follow-on patch to add irq_domain support will be the supported method for using these irq lines, so get these defines out of the way in preperation for that. Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 43 ------------------------ arch/mips/include/asm/mach-cavium-octeon/irq.h | 40 +--------------------- 2 files changed, 2 insertions(+), 81 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 168b489..bccbda9 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -1045,23 +1045,11 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq); - - for (i = 0; i < 2; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq); - for (i = 0; i < 4; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); @@ -1072,37 +1060,6 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq); /* Enable the CIU lines */ set_c0_status(STATUSF_IP3 | STATUSF_IP2); diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 5b05f18..f9bfb63 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -41,56 +41,20 @@ enum octeon_irq { OCTEON_IRQ_TWSI, OCTEON_IRQ_TWSI2, OCTEON_IRQ_RML, - OCTEON_IRQ_TRACE0, - OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4, - OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5, - OCTEON_IRQ_KEY_ZERO, OCTEON_IRQ_TIMER0, OCTEON_IRQ_TIMER1, OCTEON_IRQ_TIMER2, OCTEON_IRQ_TIMER3, OCTEON_IRQ_USB0, OCTEON_IRQ_USB1, - OCTEON_IRQ_PCM, - OCTEON_IRQ_MPI, - OCTEON_IRQ_POWIQ, - OCTEON_IRQ_IPDPPTHR, OCTEON_IRQ_MII0, OCTEON_IRQ_MII1, OCTEON_IRQ_BOOTDMA, - - OCTEON_IRQ_NAND, - OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */ - OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */ - OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */ - OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */ - OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */ - OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */ - OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */ - OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */ - OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */ - OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */ - OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */ - OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */ - OCTEON_IRQ_DFA, /* Summary of DFA */ - OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */ - OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */ - OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */ - OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */ - OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5, - OCTEON_IRQ_PTP, - OCTEON_IRQ_PEM0, - OCTEON_IRQ_PEM1, - OCTEON_IRQ_SRIO0, - OCTEON_IRQ_SRIO1, - OCTEON_IRQ_LMC0, - OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */ - OCTEON_IRQ_RST, }; #ifdef CONFIG_PCI_MSI -/* 152 - 407 represent the MSI interrupts 0-255 */ -#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1) +/* 256 - 511 represent the MSI interrupts 0-255 */ +#define OCTEON_IRQ_MSI_BIT0 (256) #define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) #define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:44:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:45:22 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:43513 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903725Ab2FFWoZ (ORCPT ); Thu, 7 Jun 2012 00:44:25 +0200 Received: by dadm1 with SMTP id m1so10165404dad.36 for ; Wed, 06 Jun 2012 15:44:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Ni9N9RWe6Bj2pj6N64BiuJFd0BFAskmnAv+bPzlVOtA=; b=LwTvXlO7nPwcZW45vgtmo5pZbFs9QHuB7KjdNG9dPck9t3s5jfFg5OgNoZFmAHfpxm 37sx8sytKoNUpGVou1HqTNmGvumluG+NJj6T59XDgEWNQX9V+k2ufIPZW2U6wv4VDQtz AxTI3Twg73+1zC6P6hoAnWdRLCx2kHLYC4mPOfmegF/PJ52COwTRCl3N8ExIJ3uBwQWJ RBESakAi8tBUminuJCE2CIQo1PgJ9oXBb3xLtV98wjgH3CzwgMO6lHL6hbwUwzEOXxIV HhqO37KAyMttfv/43NW2O4YxfFk4JkbhYS7p8i0NMoLlQXbRquB3E84z/23h4V+60qJ/ as/Q== Received: by 10.68.231.10 with SMTP id tc10mr1111096pbc.107.1339022659423; Wed, 06 Jun 2012 15:44:19 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id pq1sm1799666pbb.5.2012.06.06.15.44.17 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:44:18 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56MiGFI019908; Wed, 6 Jun 2012 15:44:16 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56MiGbX019907; Wed, 6 Jun 2012 15:44:16 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v2 3/3] MIPS: OCTEON: Consolidate the edge and level irq_chip structures. Date: Wed, 6 Jun 2012 15:44:15 -0700 Message-Id: <1339022655-19860-4-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339022655-19860-1-git-send-email-ddaney.cavm@gmail.com> References: <1339022655-19860-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33579 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3576 Lines: 91 From: David Daney We can consolidate octeon_irq_chip_ciu_edge and octeon_irq_chip_ciu as they only differ in the .irq_ack element, and that is unused by the level handler. This gets rid of a bunch of duplicate definitions. Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 30 ++---------------------------- 1 files changed, 2 insertions(+), 28 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index bccbda9..fac22a8 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -729,18 +729,6 @@ static struct irq_chip octeon_irq_chip_ciu_v2 = { .name = "CIU", .irq_enable = octeon_irq_ciu_enable_v2, .irq_disable = octeon_irq_ciu_disable_all_v2, - .irq_mask = octeon_irq_ciu_disable_local_v2, - .irq_unmask = octeon_irq_ciu_enable_v2, -#ifdef CONFIG_SMP - .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, - .irq_cpu_offline = octeon_irq_cpu_offline_ciu, -#endif -}; - -static struct irq_chip octeon_irq_chip_ciu_edge_v2 = { - .name = "CIU-E", - .irq_enable = octeon_irq_ciu_enable_v2, - .irq_disable = octeon_irq_ciu_disable_all_v2, .irq_ack = octeon_irq_ciu_ack, .irq_mask = octeon_irq_ciu_disable_local_v2, .irq_unmask = octeon_irq_ciu_enable_v2, @@ -754,19 +742,8 @@ static struct irq_chip octeon_irq_chip_ciu = { .name = "CIU", .irq_enable = octeon_irq_ciu_enable, .irq_disable = octeon_irq_ciu_disable_all, - .irq_mask = octeon_irq_dummy_mask, -#ifdef CONFIG_SMP - .irq_set_affinity = octeon_irq_ciu_set_affinity, - .irq_cpu_offline = octeon_irq_cpu_offline_ciu, -#endif -}; - -static struct irq_chip octeon_irq_chip_ciu_edge = { - .name = "CIU-E", - .irq_enable = octeon_irq_ciu_enable, - .irq_disable = octeon_irq_ciu_disable_all, - .irq_mask = octeon_irq_dummy_mask, .irq_ack = octeon_irq_ciu_ack, + .irq_mask = octeon_irq_dummy_mask, #ifdef CONFIG_SMP .irq_set_affinity = octeon_irq_ciu_set_affinity, .irq_cpu_offline = octeon_irq_cpu_offline_ciu, @@ -993,7 +970,6 @@ static void __init octeon_irq_init_ciu(void) { unsigned int i; struct irq_chip *chip; - struct irq_chip *chip_edge; struct irq_chip *chip_mbox; struct irq_chip *chip_wd; struct irq_chip *chip_gpio; @@ -1008,7 +984,6 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_ip2 = octeon_irq_ip2_v2; octeon_irq_ip3 = octeon_irq_ip3_v2; chip = &octeon_irq_chip_ciu_v2; - chip_edge = &octeon_irq_chip_ciu_edge_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; chip_gpio = &octeon_irq_chip_ciu_gpio_v2; @@ -1016,7 +991,6 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_ip2 = octeon_irq_ip2_v1; octeon_irq_ip3 = octeon_irq_ip3_v1; chip = &octeon_irq_chip_ciu; - chip_edge = &octeon_irq_chip_ciu_edge; chip_mbox = &octeon_irq_chip_ciu_mbox; chip_wd = &octeon_irq_chip_ciu_wd; chip_gpio = &octeon_irq_chip_ciu_gpio; @@ -1046,7 +1020,7 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); for (i = 0; i < 4; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip, handle_edge_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:44:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:45:48 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:53937 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903726Ab2FFWo0 (ORCPT ); Thu, 7 Jun 2012 00:44:26 +0200 Received: by pbbrq13 with SMTP id rq13so164394pbb.36 for ; Wed, 06 Jun 2012 15:44:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=B3lNbz09Qm+Dzt0yZtBv15tFreeTjJuSb4tuQBZhpho=; b=fqDjhDYzNTWrjUrbTSB+5nYddpJ1DnvhZCtTOZF3FSiwEZA/IuQgDKbhn59y5FvCrq lcFIOlJEspsAf5JuttaDXiAwBHU0hIU+Y//eWuI/KNV+I/eDXvJZFA5m5oXq71wE8HpD nFadRYFS51xpweOWhije+WfY+qK5VbjKYIXcL1saq5eAvK9+SrVg8yzbM40645F7HhOJ OIyP6c264lpig56dLB6MK2Ljqe0SoIDgV1jjWhti7irIlzWQDhP5u9+VF/u33gcLBQxg SH3ZO297hMKQU5KAgSUdc4UNI/VsN8t+9AWhVSMKnPeuiFhgH+dDfyZPdJXh5XzGoJlm R1GA== Received: by 10.68.233.201 with SMTP id ty9mr2061778pbc.34.1339022659910; Wed, 06 Jun 2012 15:44:19 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ip5sm1797007pbc.3.2012.06.06.15.44.17 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:44:18 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56MiGhD019900; Wed, 6 Jun 2012 15:44:16 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56MiGLq019899; Wed, 6 Jun 2012 15:44:16 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v2 1/3] MIPS: Octeon: Add irq handlers for GPIO interrupts. Date: Wed, 6 Jun 2012 15:44:13 -0700 Message-Id: <1339022655-19860-2-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339022655-19860-1-git-send-email-ddaney.cavm@gmail.com> References: <1339022655-19860-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33580 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5243 Lines: 170 From: David Daney This is needed for follow-on on patches for Octeon to use the Device Tree to configure GPIO interrupts. Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 111 +++++++++++++++++++++++++++++++++- 1 files changed, 110 insertions(+), 1 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index ffd4ae6..168b489 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -505,6 +505,85 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) } } +static void octeon_irq_gpio_setup(struct irq_data *data) +{ + union cvmx_gpio_bit_cfgx cfg; + union octeon_ciu_chip_data cd; + u32 t = irqd_get_trigger_type(data); + + cd.p = irq_data_get_irq_chip_data(data); + + cfg.u64 = 0; + cfg.s.int_en = 1; + cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0; + cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0; + + /* 140 nS glitch filter*/ + cfg.s.fil_cnt = 7; + cfg.s.fil_sel = 3; + + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), cfg.u64); +} + +static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data) +{ + octeon_irq_gpio_setup(data); + octeon_irq_ciu_enable_v2(data); +} + +static void octeon_irq_ciu_enable_gpio(struct irq_data *data) +{ + octeon_irq_gpio_setup(data); + octeon_irq_ciu_enable(data); +} + +static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t) +{ + irqd_set_trigger_type(data, t); + octeon_irq_gpio_setup(data); + + return IRQ_SET_MASK_OK; +} + +static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data) +{ + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0); + + octeon_irq_ciu_disable_all_v2(data); +} + +static void octeon_irq_ciu_disable_gpio(struct irq_data *data) +{ + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0); + + octeon_irq_ciu_disable_all(data); +} + +static void octeon_irq_ciu_gpio_ack(struct irq_data *data) +{ + union octeon_ciu_chip_data cd; + u64 mask; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit - 16); + + cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); +} + +static void octeon_irq_handle_gpio(unsigned int irq, struct irq_desc *desc) +{ + if (irqd_get_trigger_type(irq_desc_get_irq_data(desc)) & IRQ_TYPE_EDGE_BOTH) + handle_edge_irq(irq, desc); + else + handle_level_irq(irq, desc); +} + #ifdef CONFIG_SMP static void octeon_irq_cpu_offline_ciu(struct irq_data *data) @@ -717,6 +796,33 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = { .flags = IRQCHIP_ONOFFLINE_ENABLED, }; +static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = { + .name = "CIU-GPIO", + .irq_enable = octeon_irq_ciu_enable_gpio_v2, + .irq_disable = octeon_irq_ciu_disable_gpio_v2, + .irq_ack = octeon_irq_ciu_gpio_ack, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_v2, + .irq_set_type = octeon_irq_ciu_gpio_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, +#endif + .flags = IRQCHIP_SET_TYPE_MASKED, +}; + +static struct irq_chip octeon_irq_chip_ciu_gpio = { + .name = "CIU-GPIO", + .irq_enable = octeon_irq_ciu_enable_gpio, + .irq_disable = octeon_irq_ciu_disable_gpio, + .irq_mask = octeon_irq_dummy_mask, + .irq_ack = octeon_irq_ciu_gpio_ack, + .irq_set_type = octeon_irq_ciu_gpio_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity, +#endif + .flags = IRQCHIP_SET_TYPE_MASKED, +}; + /* * Watchdog interrupts are special. They are associated with a single * core, so we hardwire the affinity to that core. @@ -890,6 +996,7 @@ static void __init octeon_irq_init_ciu(void) struct irq_chip *chip_edge; struct irq_chip *chip_mbox; struct irq_chip *chip_wd; + struct irq_chip *chip_gpio; octeon_irq_init_ciu_percpu(); octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; @@ -904,6 +1011,7 @@ static void __init octeon_irq_init_ciu(void) chip_edge = &octeon_irq_chip_ciu_edge_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; + chip_gpio = &octeon_irq_chip_ciu_gpio_v2; } else { octeon_irq_ip2 = octeon_irq_ip2_v1; octeon_irq_ip3 = octeon_irq_ip3_v1; @@ -911,6 +1019,7 @@ static void __init octeon_irq_init_ciu(void) chip_edge = &octeon_irq_chip_ciu_edge; chip_mbox = &octeon_irq_chip_ciu_mbox; chip_wd = &octeon_irq_chip_ciu_wd; + chip_gpio = &octeon_irq_chip_ciu_gpio; } octeon_irq_ip4 = octeon_irq_ip4_mask; @@ -921,7 +1030,7 @@ static void __init octeon_irq_init_ciu(void) for (i = 0; i < 16; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, octeon_irq_handle_gpio); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:49:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:49:47 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:59167 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903728Ab2FFWto (ORCPT ); Thu, 7 Jun 2012 00:49:44 +0200 Received: by pbbrq13 with SMTP id rq13so169458pbb.36 for ; Wed, 06 Jun 2012 15:49:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=IOU4RFEEnIcmQalIL9dorRZhREArPcJlD51IPsVbBUI=; b=OFndD+TfWxj1s9wXtMP2Tp8vXcX3xcsPDUFQMGEJA2j06tEhOOc5NUI9JPoYabcgVn r8A6lcETHZaS4+aX6Sm5ibWayy/PIf2UNsiL4TY1/d2sJZEXH/P4mnDa0mYb4irSrEdW E34vPFMAeB1qIHyN3T5QUgKQAOLFspdbo5Kc2etFPPmbhiCyONU+m+9MT9J1yUceLVd3 0p6oevPO/Cw4NiED4aDui0aTEd1PJCobBH5tldSXaGteMtYU0cJRPIi1ulnZqigmPkux 2zJ8reGxs+/gJRcSNTIFo03nzbsagivCiaTl6cXjcLPPU/guZkvDgO0+ddaRc3engyNM eOmw== Received: by 10.68.237.74 with SMTP id va10mr2014646pbc.46.1339022977287; Wed, 06 Jun 2012 15:49:37 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id rs3sm1794729pbc.47.2012.06.06.15.49.35 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:49:36 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56MnZfS020068; Wed, 6 Jun 2012 15:49:35 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56MnXxS020066; Wed, 6 Jun 2012 15:49:33 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v8 1/1] of/lib: Allow scripts/dtc/libfdt to be used from kernel code Date: Wed, 6 Jun 2012 15:49:32 -0700 Message-Id: <1339022972-20036-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33581 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5434 Lines: 187 From: David Daney libfdt is part of the device tree support in scripts/dtc/libfdt. For some platforms that use the Device Tree, we want to be able to edit the flattened device tree form. We don't want to burden kernel builds that do not require it, so we gate compilation of libfdt files with CONFIG_LIBFDT. So if it is needed, you need to do this in your Kconfig: select LIBFDT And in the Makefile of the code using libfdt something like: ccflags-y := -I$(src)/../../../scripts/dtc/libfdt Signed-off-by: David Daney --- This patch has been seen several times before as part of a larger patch set for my OCTEON Device Tree work. After further refinement to my patches that depend on core Device Tree functionality, this is the only remaining patch to the common 'core' code. Here is the history: v8: Rebased lib/Makefile to avoid merge conflict. v7: No changes other that to split from other, now unneeded, patches. v6: No changes other than to split these out of the MIPS/OCTEON patch set to allow them to be merged separately if desired. v5: Build libfdt in the lib directory instead of devices/of, and include all libfdt files. Changes to of_find_node_by_path() requested by Grant Likely. v4: No changes to these two patches. v3: libfdt building moved to devices/of/libfdt. Cleanup and style improvements as suggested by Grant Likely. v2: No changes to these two patches. There are a couple of possibility for merging this. 1) Via the Device Tree maintainers, thus blocking the follow-ons until it is merged. 2) Via Ralf's Linux/MIPS tree with the rest of the patches after Device Tree maintainer sign-off. include/linux/libfdt.h | 8 ++++++++ include/linux/libfdt_env.h | 13 +++++++++++++ lib/Kconfig | 6 ++++++ lib/Makefile | 5 +++++ lib/fdt.c | 2 ++ lib/fdt_ro.c | 2 ++ lib/fdt_rw.c | 2 ++ lib/fdt_strerror.c | 2 ++ lib/fdt_sw.c | 2 ++ lib/fdt_wip.c | 2 ++ 10 files changed, 44 insertions(+), 0 deletions(-) create mode 100644 include/linux/libfdt.h create mode 100644 include/linux/libfdt_env.h create mode 100644 lib/fdt.c create mode 100644 lib/fdt_ro.c create mode 100644 lib/fdt_rw.c create mode 100644 lib/fdt_strerror.c create mode 100644 lib/fdt_sw.c create mode 100644 lib/fdt_wip.c diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h new file mode 100644 index 0000000..4c0306c --- /dev/null +++ b/include/linux/libfdt.h @@ -0,0 +1,8 @@ +#ifndef _INCLUDE_LIBFDT_H_ +#define _INCLUDE_LIBFDT_H_ + +#include +#include "../../scripts/dtc/libfdt/fdt.h" +#include "../../scripts/dtc/libfdt/libfdt.h" + +#endif /* _INCLUDE_LIBFDT_H_ */ diff --git a/include/linux/libfdt_env.h b/include/linux/libfdt_env.h new file mode 100644 index 0000000..01508c7 --- /dev/null +++ b/include/linux/libfdt_env.h @@ -0,0 +1,13 @@ +#ifndef _LIBFDT_ENV_H +#define _LIBFDT_ENV_H + +#include + +#include + +#define fdt32_to_cpu(x) be32_to_cpu(x) +#define cpu_to_fdt32(x) cpu_to_be32(x) +#define fdt64_to_cpu(x) be64_to_cpu(x) +#define cpu_to_fdt64(x) cpu_to_be64(x) + +#endif /* _LIBFDT_ENV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index a9e1540..e091300 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -395,4 +395,10 @@ config SIGNATURE Digital signature verification. Currently only RSA is supported. Implementation is done using GnuPG MPI library +# +# libfdt files, only selected if needed. +# +config LIBFDT + bool + endmenu diff --git a/lib/Makefile b/lib/Makefile index 8c31a0c..2f2be5a 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -130,6 +130,11 @@ obj-$(CONFIG_GENERIC_STRNLEN_USER) += strnlen_user.o obj-$(CONFIG_STMP_DEVICE) += stmp_device.o +libfdt_files = fdt.o fdt_ro.o fdt_wip.o fdt_rw.o fdt_sw.o fdt_strerror.o +$(foreach file, $(libfdt_files), \ + $(eval CFLAGS_$(file) = -I$(src)/../scripts/dtc/libfdt)) +lib-$(CONFIG_LIBFDT) += $(libfdt_files) + hostprogs-y := gen_crc32table clean-files := crc32table.h diff --git a/lib/fdt.c b/lib/fdt.c new file mode 100644 index 0000000..97f2006 --- /dev/null +++ b/lib/fdt.c @@ -0,0 +1,2 @@ +#include +#include "../scripts/dtc/libfdt/fdt.c" diff --git a/lib/fdt_ro.c b/lib/fdt_ro.c new file mode 100644 index 0000000..f73c04e --- /dev/null +++ b/lib/fdt_ro.c @@ -0,0 +1,2 @@ +#include +#include "../scripts/dtc/libfdt/fdt_ro.c" diff --git a/lib/fdt_rw.c b/lib/fdt_rw.c new file mode 100644 index 0000000..0c1f0f4 --- /dev/null +++ b/lib/fdt_rw.c @@ -0,0 +1,2 @@ +#include +#include "../scripts/dtc/libfdt/fdt_rw.c" diff --git a/lib/fdt_strerror.c b/lib/fdt_strerror.c new file mode 100644 index 0000000..8713e3f --- /dev/null +++ b/lib/fdt_strerror.c @@ -0,0 +1,2 @@ +#include +#include "../scripts/dtc/libfdt/fdt_strerror.c" diff --git a/lib/fdt_sw.c b/lib/fdt_sw.c new file mode 100644 index 0000000..9ac7e50 --- /dev/null +++ b/lib/fdt_sw.c @@ -0,0 +1,2 @@ +#include +#include "../scripts/dtc/libfdt/fdt_sw.c" diff --git a/lib/fdt_wip.c b/lib/fdt_wip.c new file mode 100644 index 0000000..45b3fc3 --- /dev/null +++ b/lib/fdt_wip.c @@ -0,0 +1,2 @@ +#include +#include "../scripts/dtc/libfdt/fdt_wip.c" -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:57:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:57:57 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:33648 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903728Ab2FFW5y (ORCPT ); Thu, 7 Jun 2012 00:57:54 +0200 Received: by dadm1 with SMTP id m1so10178442dad.36 for ; Wed, 06 Jun 2012 15:57:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=OwcD34EqlI+208AmXHacsBRSi6Vy5vNGWUdbevOo95k=; b=qRtlnR3q1E6qMIb4cJ4ZlMlQFyIMZu3V5EsLj185IkB6u7K2t9wAgkS2lCveJyu4qq Ij4oNRU3VcHafFjhYBkmSnHdJlKg8B3nASqC1IdX0mHKTUfdUYauujE1JhDYL64Gcu3+ ewbojopmpm4VNNKj90SXiXmmZrgB2VMEyPYrUFu96Qf9oyPVxFhdXecCLcLkeLg3RhlG s4EZwgtWuoE3BoXaTL4piJBnITsG9xnbzZ5KGbwBVEiZUJVwU6imv6MYjGwk7+HTxdbI 5DKb2z802snEjFzFIsIFEqA3m8t4wox5S2oPNJc0oMGWoa4Pj9fUC+HBDKPFj+OcX6tX 6nGA== Received: by 10.68.217.40 with SMTP id ov8mr1051928pbc.131.1339023467190; Wed, 06 Jun 2012 15:57:47 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id to1sm1822044pbc.27.2012.06.06.15.57.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:57:46 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56Mviqm020307; Wed, 6 Jun 2012 15:57:44 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56MviMf020306; Wed, 6 Jun 2012 15:57:44 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v8 1/4] MIPS: Don't define early_init_devtree() and device_tree_init() in prom.c for CPU_CAVIUM_OCTEON Date: Wed, 6 Jun 2012 15:57:40 -0700 Message-Id: <1339023463-20267-2-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339023463-20267-1-git-send-email-ddaney.cavm@gmail.com> References: <1339023463-20267-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33582 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 915 Lines: 33 From: David Daney This code is not common enough to be in a shared file, so OCTEON defines it's own versions. When the last of this target specific code is moved out, we can remove all of this. Signed-off-by: David Daney --- arch/mips/kernel/prom.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index f11b2bb..fcb325e 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -60,6 +60,7 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start, } #endif +#ifndef CONFIG_CPU_CAVIUM_OCTEON void __init early_init_devtree(void *params) { /* Setup flat device-tree pointer */ @@ -108,3 +109,4 @@ void __init __dt_setup_arch(struct boot_param_header *bph) early_init_devtree(initial_boot_params); } +#endif /* !CONFIG_CPU_CAVIUM_OCTEON */ -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:57:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:58:24 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:61875 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903738Ab2FFW5y (ORCPT ); Thu, 7 Jun 2012 00:57:54 +0200 Received: by dadm1 with SMTP id m1so10178450dad.36 for ; Wed, 06 Jun 2012 15:57:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=CcRqbCk4LfhxfWew1yhuYkcEmGQKydJ8fb1L+euaDxY=; b=VJalov7/4B8JKG/EYxMIgIU7ZkiwgRzOwLU0AXLa38cj+GKoJJzpyr8YJscnzODq/w 1aA8LnYX2Z93w1+Bs3uiOynXHViCxYjQ62yW7IfytAfmpV5qA4ZcXjTTuSgaXW2V07kf xxIHxBB4/gbmFPfQ0zHV3ktiia7eMz2bJibfVRL3XR9gmYwtHE032l94LsY55Kkip2Ru gOLjTjn8vuMaBN8bm2FHgr1gJqayBmmB0pzAD5ok6Glcu7u0rfE0DgDuZLp3fdiLMUkM kr3RWDvoxR8ObAUmtFAidGNdo4Z96xARV9RhMGG7dIGml67txLBpV+Od/bv7ycttaiUW yqRw== Received: by 10.68.211.170 with SMTP id nd10mr1557509pbc.68.1339023467619; Wed, 06 Jun 2012 15:57:47 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id we10sm1826402pbc.13.2012.06.06.15.57.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:57:46 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56MvjdL020315; Wed, 6 Jun 2012 15:57:45 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56MvjVD020314; Wed, 6 Jun 2012 15:57:45 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v8 3/4] MIPS: Octeon: Initialize and fixup device tree. Date: Wed, 6 Jun 2012 15:57:42 -0700 Message-Id: <1339023463-20267-4-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339023463-20267-1-git-send-email-ddaney.cavm@gmail.com> References: <1339023463-20267-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33583 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 19340 Lines: 655 From: David Daney If a compiled in device tree template is used, trim out unwanted parts based on legacy platform probing. Signed-off-by: David Daney --- arch/mips/Kconfig | 2 + arch/mips/cavium-octeon/Makefile | 3 + arch/mips/cavium-octeon/octeon-platform.c | 523 ++++++++++++++++++++++++++++- arch/mips/cavium-octeon/setup.c | 45 +++ 4 files changed, 572 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6d7e9b0..5988137 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1434,6 +1434,8 @@ config CPU_CAVIUM_OCTEON select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES select ARCH_SPARSEMEM_ENABLE + select USE_OF + select LIBFDT help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 1e37522..bc96e29 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -9,6 +9,9 @@ # Copyright (C) 2005-2009 Cavium Networks # +CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt +CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt + obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o obj-y += dma-octeon.o flash_setup.o obj-y += octeon-memcpy.o diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index cd61d72..2754bc2 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004-2010 Cavium Networks + * Copyright (C) 2004-2011 Cavium Networks * Copyright (C) 2008 Wind River Systems */ @@ -13,10 +13,16 @@ #include #include #include +#include #include +#include +#include +#include #include #include +#include +#include static struct octeon_cf_data octeon_cf_data; @@ -440,6 +446,521 @@ device_initcall(octeon_ohci_device_init); #endif /* CONFIG_USB */ +static struct of_device_id __initdata octeon_ids[] = { + { .compatible = "simple-bus", }, + { .compatible = "cavium,octeon-6335-uctl", }, + { .compatible = "cavium,octeon-3860-bootbus", }, + { .compatible = "cavium,mdio-mux", }, + { .compatible = "gpio-leds", }, + {}, +}; + +static bool __init octeon_has_88e1145(void) +{ + return !OCTEON_IS_MODEL(OCTEON_CN52XX) && + !OCTEON_IS_MODEL(OCTEON_CN6XXX) && + !OCTEON_IS_MODEL(OCTEON_CN56XX); +} + +static void __init octeon_fdt_set_phy(int eth, int phy_addr) +{ + const __be32 *phy_handle; + const __be32 *alt_phy_handle; + const __be32 *reg; + u32 phandle; + int phy; + int alt_phy; + const char *p; + int current_len; + char new_name[20]; + + phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); + if (!phy_handle) + return; + + phandle = be32_to_cpup(phy_handle); + phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); + + alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); + if (alt_phy_handle) { + u32 alt_phandle = be32_to_cpup(alt_phy_handle); + alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); + } else { + alt_phy = -1; + } + + if (phy_addr < 0 || phy < 0) { + /* Delete the PHY things */ + fdt_nop_property(initial_boot_params, eth, "phy-handle"); + /* This one may fail */ + fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle"); + if (phy >= 0) + fdt_nop_node(initial_boot_params, phy); + if (alt_phy >= 0) + fdt_nop_node(initial_boot_params, alt_phy); + return; + } + + if (phy_addr >= 256 && alt_phy > 0) { + const struct fdt_property *phy_prop; + struct fdt_property *alt_prop; + u32 phy_handle_name; + + /* Use the alt phy node instead.*/ + phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL); + phy_handle_name = phy_prop->nameoff; + fdt_nop_node(initial_boot_params, phy); + fdt_nop_property(initial_boot_params, eth, "phy-handle"); + alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); + alt_prop->nameoff = phy_handle_name; + phy = alt_phy; + } + + phy_addr &= 0xff; + + if (octeon_has_88e1145()) { + fdt_nop_property(initial_boot_params, phy, "marvell,reg-init"); + memset(new_name, 0, sizeof(new_name)); + strcpy(new_name, "marvell,88e1145"); + p = fdt_getprop(initial_boot_params, phy, "compatible", + ¤t_len); + if (p && current_len >= strlen(new_name)) + fdt_setprop_inplace(initial_boot_params, phy, + "compatible", new_name, current_len); + } + + reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); + if (phy_addr == be32_to_cpup(reg)) + return; + + fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); + + snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr); + + p = fdt_get_name(initial_boot_params, phy, ¤t_len); + if (p && current_len == strlen(new_name)) + fdt_set_name(initial_boot_params, phy, new_name); + else + pr_err("Error: could not rename ethernet phy: <%s>", p); +} + +static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) +{ + u8 new_mac[6]; + u64 mac = *pmac; + int r; + + new_mac[0] = (mac >> 40) & 0xff; + new_mac[1] = (mac >> 32) & 0xff; + new_mac[2] = (mac >> 24) & 0xff; + new_mac[3] = (mac >> 16) & 0xff; + new_mac[4] = (mac >> 8) & 0xff; + new_mac[5] = mac & 0xff; + + r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", + new_mac, sizeof(new_mac)); + + if (r) { + pr_err("Setting \"local-mac-address\" failed %d", r); + return; + } + *pmac = mac + 1; +} + +static void __init octeon_fdt_rm_ethernet(int node) +{ + const __be32 *phy_handle; + + phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); + if (phy_handle) { + u32 ph = be32_to_cpup(phy_handle); + int p = fdt_node_offset_by_phandle(initial_boot_params, ph); + if (p >= 0) + fdt_nop_node(initial_boot_params, p); + } + fdt_nop_node(initial_boot_params, node); +} + +static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac) +{ + char name_buffer[20]; + int eth; + int phy_addr; + int ipd_port; + + snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); + eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); + if (eth < 0) + return; + if (p > max) { + pr_debug("Deleting port %x:%x\n", i, p); + octeon_fdt_rm_ethernet(eth); + return; + } + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + ipd_port = (0x100 * i) + (0x10 * p) + 0x800; + else + ipd_port = 16 * i + p; + + phy_addr = cvmx_helper_board_get_mii_address(ipd_port); + octeon_fdt_set_phy(eth, phy_addr); + octeon_fdt_set_mac_addr(eth, pmac); +} + +static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) +{ + char name_buffer[20]; + int iface; + int p; + int count; + + count = cvmx_helper_interface_enumerate(idx); + + snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); + iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); + if (iface < 0) + return; + + for (p = 0; p < 16; p++) + octeon_fdt_pip_port(iface, idx, p, count - 1, pmac); +} + +int __init octeon_prune_device_tree(void) +{ + int i, max_port, uart_mask; + const char *pip_path; + const char *alias_prop; + char name_buffer[20]; + int aliases; + u64 mac_addr_base; + + if (fdt_check_header(initial_boot_params)) + panic("Corrupt Device Tree."); + + aliases = fdt_path_offset(initial_boot_params, "/aliases"); + if (aliases < 0) { + pr_err("Error: No /aliases node in device tree."); + return -EINVAL; + } + + + mac_addr_base = + ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | + ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | + ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | + ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | + ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | + (octeon_bootinfo->mac_addr_base[5] & 0xffull); + + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) + max_port = 2; + else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) + max_port = 1; + else + max_port = 0; + + if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) + max_port = 0; + + for (i = 0; i < 2; i++) { + int mgmt; + snprintf(name_buffer, sizeof(name_buffer), + "mix%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + if (alias_prop) { + mgmt = fdt_path_offset(initial_boot_params, alias_prop); + if (mgmt < 0) + continue; + if (i >= max_port) { + pr_debug("Deleting mix%d\n", i); + octeon_fdt_rm_ethernet(mgmt); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } else { + int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); + octeon_fdt_set_phy(mgmt, phy_addr); + octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); + } + } + } + + pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); + if (pip_path) { + int pip = fdt_path_offset(initial_boot_params, pip_path); + if (pip >= 0) + for (i = 0; i <= 4; i++) + octeon_fdt_pip_iface(pip, i, &mac_addr_base); + } + + /* I2C */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN68XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 2; + else + max_port = 1; + + for (i = 0; i < 2; i++) { + int i2c; + snprintf(name_buffer, sizeof(name_buffer), + "twsi%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + i2c = fdt_path_offset(initial_boot_params, alias_prop); + if (i2c < 0) + continue; + if (i >= max_port) { + pr_debug("Deleting twsi%d\n", i); + fdt_nop_node(initial_boot_params, i2c); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + } + + /* SMI/MDIO */ + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + max_port = 4; + else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 2; + else + max_port = 1; + + for (i = 0; i < 2; i++) { + int i2c; + snprintf(name_buffer, sizeof(name_buffer), + "smi%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + i2c = fdt_path_offset(initial_boot_params, alias_prop); + if (i2c < 0) + continue; + if (i >= max_port) { + pr_debug("Deleting smi%d\n", i); + fdt_nop_node(initial_boot_params, i2c); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + } + + /* Serial */ + uart_mask = 3; + + /* Right now CN52XX is the only chip with a third uart */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) + uart_mask |= 4; /* uart2 */ + + for (i = 0; i < 3; i++) { + int uart; + snprintf(name_buffer, sizeof(name_buffer), + "uart%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + uart = fdt_path_offset(initial_boot_params, alias_prop); + if (uart_mask & (1 << i)) + continue; + pr_debug("Deleting uart%d\n", i); + fdt_nop_node(initial_boot_params, uart); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + + /* Compact Flash */ + alias_prop = fdt_getprop(initial_boot_params, aliases, + "cf0", NULL); + if (alias_prop) { + union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; + unsigned long base_ptr, region_base, region_size; + unsigned long region1_base = 0; + unsigned long region1_size = 0; + int cs, bootbus; + bool is_16bit = false; + bool is_true_ide = false; + __be32 new_reg[6]; + __be32 *ranges; + int len; + + int cf = fdt_path_offset(initial_boot_params, alias_prop); + base_ptr = 0; + if (octeon_bootinfo->major_version == 1 + && octeon_bootinfo->minor_version >= 1) { + if (octeon_bootinfo->compact_flash_common_base_addr) + base_ptr = octeon_bootinfo->compact_flash_common_base_addr; + } else { + base_ptr = 0x1d000800; + } + + if (!base_ptr) + goto no_cf; + + /* Find CS0 region. */ + for (cs = 0; cs < 8; cs++) { + mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); + region_base = mio_boot_reg_cfg.s.base << 16; + region_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (mio_boot_reg_cfg.s.en && base_ptr >= region_base + && base_ptr < region_base + region_size) { + is_16bit = mio_boot_reg_cfg.s.width; + break; + } + } + if (cs >= 7) { + /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ + goto no_cf; + } + + if (!(base_ptr & 0xfffful)) { + /* + * Boot loader signals availability of DMA (true_ide + * mode) by setting low order bits of base_ptr to + * zero. + */ + + /* Asume that CS1 immediately follows. */ + mio_boot_reg_cfg.u64 = + cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); + region1_base = mio_boot_reg_cfg.s.base << 16; + region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (!mio_boot_reg_cfg.s.en) + goto no_cf; + is_true_ide = true; + + } else { + fdt_nop_property(initial_boot_params, cf, "cavium,true-ide"); + fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); + if (!is_16bit) { + __be32 width = cpu_to_be32(8); + fdt_setprop_inplace(initial_boot_params, cf, + "cavium,bus-width", &width, sizeof(width)); + } + } + new_reg[0] = cpu_to_be32(cs); + new_reg[1] = cpu_to_be32(0); + new_reg[2] = cpu_to_be32(0x10000); + new_reg[3] = cpu_to_be32(cs + 1); + new_reg[4] = cpu_to_be32(0); + new_reg[5] = cpu_to_be32(0x10000); + fdt_setprop_inplace(initial_boot_params, cf, + "reg", new_reg, sizeof(new_reg)); + + bootbus = fdt_parent_offset(initial_boot_params, cf); + if (bootbus < 0) + goto no_cf; + ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); + if (!ranges || len < (5 * 8 * sizeof(__be32))) + goto no_cf; + + ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); + ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); + ranges[(cs * 5) + 4] = cpu_to_be32(region_size); + if (is_true_ide) { + cs++; + ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); + ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); + ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); + } + goto end_cf; +no_cf: + fdt_nop_node(initial_boot_params, cf); + +end_cf: + ; + } + + /* 8 char LED */ + alias_prop = fdt_getprop(initial_boot_params, aliases, + "led0", NULL); + if (alias_prop) { + union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; + unsigned long base_ptr, region_base, region_size; + int cs, bootbus; + __be32 new_reg[6]; + __be32 *ranges; + int len; + int led = fdt_path_offset(initial_boot_params, alias_prop); + + base_ptr = octeon_bootinfo->led_display_base_addr; + if (base_ptr == 0) + goto no_led; + /* Find CS0 region. */ + for (cs = 0; cs < 8; cs++) { + mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); + region_base = mio_boot_reg_cfg.s.base << 16; + region_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (mio_boot_reg_cfg.s.en && base_ptr >= region_base + && base_ptr < region_base + region_size) + break; + } + + if (cs > 7) + goto no_led; + + new_reg[0] = cpu_to_be32(cs); + new_reg[1] = cpu_to_be32(0x20); + new_reg[2] = cpu_to_be32(0x20); + new_reg[3] = cpu_to_be32(cs); + new_reg[4] = cpu_to_be32(0); + new_reg[5] = cpu_to_be32(0x20); + fdt_setprop_inplace(initial_boot_params, led, + "reg", new_reg, sizeof(new_reg)); + + bootbus = fdt_parent_offset(initial_boot_params, led); + if (bootbus < 0) + goto no_led; + ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); + if (!ranges || len < (5 * 8 * sizeof(__be32))) + goto no_led; + + ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); + ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); + ranges[(cs * 5) + 4] = cpu_to_be32(region_size); + goto end_led; + +no_led: + fdt_nop_node(initial_boot_params, led); +end_led: + ; + } + + /* OHCI/UHCI USB */ + alias_prop = fdt_getprop(initial_boot_params, aliases, + "uctl", NULL); + if (alias_prop) { + int uctl = fdt_path_offset(initial_boot_params, alias_prop); + + if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || + octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { + pr_debug("Deleting uctl\n"); + fdt_nop_node(initial_boot_params, uctl); + fdt_nop_property(initial_boot_params, aliases, "uctl"); + } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || + octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { + /* Missing "refclk-type" defaults to crystal. */ + fdt_nop_property(initial_boot_params, uctl, "refclk-type"); + } + } + + return 0; +} + +static int __init octeon_publish_devices(void) +{ + return of_platform_bus_probe(NULL, octeon_ids, NULL); +} +device_initcall(octeon_publish_devices); + MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Platform driver for Octeon SOC"); diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 260dc24..919b0fb 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #include #include @@ -775,3 +777,46 @@ void prom_free_prom_memory(void) } #endif } + +int octeon_prune_device_tree(void); + +extern const char __dtb_octeon_3xxx_begin; +extern const char __dtb_octeon_3xxx_end; +extern const char __dtb_octeon_68xx_begin; +extern const char __dtb_octeon_68xx_end; +void __init device_tree_init(void) +{ + int dt_size; + struct boot_param_header *fdt; + bool do_prune; + + if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { + fdt = phys_to_virt(octeon_bootinfo->fdt_addr); + if (fdt_check_header(fdt)) + panic("Corrupt Device Tree passed to kernel."); + dt_size = be32_to_cpu(fdt->totalsize); + do_prune = false; + } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { + fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin; + dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin; + do_prune = true; + } else { + fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin; + dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; + do_prune = true; + } + + /* Copy the default tree from init memory. */ + initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); + if (initial_boot_params == NULL) + panic("Could not allocate initial_boot_params\n"); + memcpy(initial_boot_params, fdt, dt_size); + + if (do_prune) { + octeon_prune_device_tree(); + pr_info("Using internal Device Tree.\n"); + } else { + pr_info("Using passed Device Tree.\n"); + } + unflatten_device_tree(); +} -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:57:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:58:46 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:49630 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903741Ab2FFW5z (ORCPT ); Thu, 7 Jun 2012 00:57:55 +0200 Received: by pbbrq13 with SMTP id rq13so177275pbb.36 for ; Wed, 06 Jun 2012 15:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=2HbZoVvOgJKs8AxX6Xf8NOyYAR+z/X4MTJbbucaeGQE=; b=0bsX0YYNdbwMA6ahHMnMSJYr27fgvbsRaZPIk7HP91GYbvrwWTqZC07QsFxO/I1U1M HOjSflGGk8CrJOLC+zoLKDHkURcNQeeUH3U+LI0fay5Py7hhF599WidalphTqPyt/P3d nb0X9Ad7lJ0JLo6EWfa051Eo1W7xWEYlBLlGuv/iYfYPmW6V6BBKFUPEcRpWfVGLo2ZR QwyV1fP8WmUE2kT3UKeoJzcsKlE/inFssg+94tFHwKK3G/8doOAKtVeKJPCR5VaMWt6u FgewfnHYNmEfPl1F7/68bb84o0/dt6XlxuhiN4EMQzHwaBJVCek8wXQTit10l7eP6S5e hsrg== Received: by 10.68.202.99 with SMTP id kh3mr869310pbc.157.1339023468373; Wed, 06 Jun 2012 15:57:48 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id gj8sm1816989pbc.39.2012.06.06.15.57.46 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:57:46 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56Mvi1A020303; Wed, 6 Jun 2012 15:57:44 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56Mvi4I020301; Wed, 6 Jun 2012 15:57:44 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v8 0/4] MIPS: OCTEON: Use Device Tree. Date: Wed, 6 Jun 2012 15:57:39 -0700 Message-Id: <1339023463-20267-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33584 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5312 Lines: 136 From: David Daney This code has now had extensive testing, it is running on more than 10 different boards and SOC combinations. The patches in this set are all in the arch/mips tree and should probably be merged by Ralf. They do depend on this libfdt patch: http://patchwork.linux-mips.org/patch/3933/ As well as thses MIPS patches: http://patchwork.linux-mips.org/patch/3932/ http://patchwork.linux-mips.org/patch/3930/ http://patchwork.linux-mips.org/patch/3931/ New in v8: o Reordered to maintain bisectability. o Rebased to avoid merge conflicts. New in v7: o irq_domain support revised based on feedback from Grant and Rob. New in v6: o Device Tree bindings updated based on feedback and more actual use. o Use of irq_domain support added to recent kernels. New in v5: o New irq triggering mode constants. o Boot protocol to pass flattened device tree from bootloader. This protocol may change based on attempts to arrive at a common protocol for all MIPS boards. New in v4: o Cleanup and error checking suggested by Sergei Shtylyov. o Use device tree passed by bootloader if present. New in v3: o More updates to device tree bindings, and perhaps more importantly descriptions/definitions of the bindings o Cleanup and style improvements as suggested by Grant Likley. o Omitted all the driver changes, as they are unchanged from the last set, and at this stage the patches are just an RFC. New in v2: o Changed many device tree bindings. They should be closer to the standard naming scheme now. o Editing of the template device tree is done in the flattened form using libfdt. o Standard platform driver functions used in preference to the of_platform variety. v1: Background: The Octeon family of SOCs has a variety of on-chip controllers for Ethernet, MDIO, I2C, and several other I/O devices. These chips are used on boards with a great variety of different configurations. To date, the configuration and bus topology information has been hard coded in the drivers and support code. To facilitate supporting new chips and boards, we are using the Device Tree to encode the configuration information. The migration from the legacy approach to the device tree is as follows: o A device tree template is statically linked into the kernel image. Based on SOC type and board type, legacy configuration probing code is used to prune and patch the device tree template. o New SOCs and boards will directly use a device tree passed by the bootloader. David Daney (4): MIPS: Don't define early_init_devtree() and device_tree_init() in prom.c for CPU_CAVIUM_OCTEON MIPS: Octeon: Add device tree source files. MIPS: Octeon: Initialize and fixup device tree. MIPS: Octeon: Setup irq_domains for interrupts. .../bindings/ata/cavium-compact-flash.txt | 30 + .../bindings/gpio/cavium-octeon-gpio.txt | 49 ++ .../devicetree/bindings/i2c/cavium-i2c.txt | 34 ++ .../devicetree/bindings/mips/cavium/bootbus.txt | 126 ++++ .../devicetree/bindings/mips/cavium/ciu.txt | 26 + .../devicetree/bindings/mips/cavium/ciu2.txt | 27 + .../devicetree/bindings/mips/cavium/dma-engine.txt | 21 + .../devicetree/bindings/mips/cavium/uctl.txt | 47 ++ .../devicetree/bindings/net/cavium-mdio.txt | 27 + .../devicetree/bindings/net/cavium-mix.txt | 40 ++ .../devicetree/bindings/net/cavium-pip.txt | 98 +++ .../devicetree/bindings/serial/cavium-uart.txt | 19 + arch/mips/Kconfig | 2 + arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 16 + arch/mips/cavium-octeon/octeon-irq.c | 215 +++++++- arch/mips/cavium-octeon/octeon-platform.c | 523 ++++++++++++++++- arch/mips/cavium-octeon/octeon_3xxx.dts | 571 ++++++++++++++++++ arch/mips/cavium-octeon/octeon_68xx.dts | 625 ++++++++++++++++++++ arch/mips/cavium-octeon/setup.c | 45 ++ arch/mips/kernel/prom.c | 2 + 21 files changed, 2535 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/cavium-compact-flash.txt create mode 100644 Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt create mode 100644 Documentation/devicetree/bindings/i2c/cavium-i2c.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/bootbus.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu2.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/dma-engine.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/uctl.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mdio.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mix.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-pip.txt create mode 100644 Documentation/devicetree/bindings/serial/cavium-uart.txt create mode 100644 arch/mips/cavium-octeon/.gitignore create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:57:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:59:09 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:50096 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903744Ab2FFW54 (ORCPT ); Thu, 7 Jun 2012 00:57:56 +0200 Received: by dadm1 with SMTP id m1so10178474dad.36 for ; Wed, 06 Jun 2012 15:57:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=QJD3UO2+TlZSHg0RowhGdcCa66/AWex3y+aCI5Sxu4k=; b=ZVlCcnvtc00UQFTiA8XFxNAocrMNWQ6YLHP2/5Mlu3fq8ld+JnU1EpKZQHNNl0d8FN EXTa49UsYCNrnWLSy5QDIPsbCeySsNzRs66JHf/tQBfeEtf8RymbZkp1iki/8tdFx4Ym m+02nGHCcsxFwqPlibqDBnZA7fHuufQ0ok4U5tF2gWFlXhK5D+GnfaSme9M2zrm8+0xD /cV+QLH1AW0gijINT2JGQ1/QFRBLIrvFOVrG/5fD3qZXClQ/Yxjp981cKV4wOnjI3mPv /vLN5ib77saUfETgllzxp39hu763Nqo+oZDvYLs9voKFCzvKb17OFz7Iq5743EO7S0eU 4vGA== Received: by 10.68.213.7 with SMTP id no7mr433808pbc.3.1339023469291; Wed, 06 Jun 2012 15:57:49 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id hc7sm1811658pbc.54.2012.06.06.15.57.46 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:57:46 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56Mvjlp020319; Wed, 6 Jun 2012 15:57:45 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56Mvjr9020318; Wed, 6 Jun 2012 15:57:45 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v8 4/4] MIPS: Octeon: Setup irq_domains for interrupts. Date: Wed, 6 Jun 2012 15:57:43 -0700 Message-Id: <1339023463-20267-5-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339023463-20267-1-git-send-email-ddaney.cavm@gmail.com> References: <1339023463-20267-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33585 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7993 Lines: 295 From: David Daney Create two domains. One for the GPIO lines, and the other for on-chip sources. Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 215 ++++++++++++++++++++++++++++++++-- 1 files changed, 206 insertions(+), 9 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index fac22a8..52610ce 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -3,14 +3,17 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks + * Copyright (C) 2004-2012 Cavium, Inc. */ #include +#include #include #include +#include #include #include +#include #include @@ -42,9 +45,9 @@ struct octeon_core_chip_data { static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; -static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, - struct irq_chip *chip, - irq_flow_handler_t handler) +static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, + struct irq_chip *chip, + irq_flow_handler_t handler) { union octeon_ciu_chip_data cd; @@ -847,6 +850,178 @@ static struct irq_chip octeon_irq_chip_ciu_wd = { .irq_mask = octeon_irq_dummy_mask, }; +static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit) +{ + bool edge = false; + + if (line == 0) + switch (bit) { + case 48 ... 49: /* GMX DRP */ + case 50: /* IPD_DRP */ + case 52 ... 55: /* Timers */ + case 58: /* MPI */ + edge = true; + break; + default: + break; + } + else /* line == 1 */ + switch (bit) { + case 47: /* PTP */ + edge = true; + break; + default: + break; + } + return edge; +} + +struct octeon_irq_gpio_domain_data { + unsigned int base_hwirq; +}; + +static int octeon_irq_gpio_xlat(struct irq_domain *d, + struct device_node *node, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + unsigned int type; + unsigned int pin; + unsigned int trigger; + struct octeon_irq_gpio_domain_data *gpiod; + + if (d->of_node != node) + return -EINVAL; + + if (intsize < 2) + return -EINVAL; + + pin = intspec[0]; + if (pin >= 16) + return -EINVAL; + + trigger = intspec[1]; + + switch (trigger) { + case 1: + type = IRQ_TYPE_EDGE_RISING; + break; + case 2: + type = IRQ_TYPE_EDGE_FALLING; + break; + case 4: + type = IRQ_TYPE_LEVEL_HIGH; + break; + case 8: + type = IRQ_TYPE_LEVEL_LOW; + break; + default: + pr_err("Error: (%s) Invalid irq trigger specification: %x\n", + node->name, + trigger); + type = IRQ_TYPE_LEVEL_LOW; + break; + } + *out_type = type; + gpiod = d->host_data; + *out_hwirq = gpiod->base_hwirq + pin; + + return 0; +} + +static int octeon_irq_ciu_xlat(struct irq_domain *d, + struct device_node *node, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + unsigned int ciu, bit; + + ciu = intspec[0]; + bit = intspec[1]; + + if (ciu > 1 || bit > 63) + return -EINVAL; + + /* These are the GPIO lines */ + if (ciu == 0 && bit >= 16 && bit < 32) + return -EINVAL; + + *out_hwirq = (ciu << 6) | bit; + *out_type = 0; + + return 0; +} + +static struct irq_chip *octeon_irq_ciu_chip; +static struct irq_chip *octeon_irq_gpio_chip; + +static bool octeon_irq_virq_in_range(unsigned int virq) +{ + /* We cannot let it overflow the mapping array. */ + if (virq < (1ul << 8 * sizeof(octeon_irq_ciu_to_irq[0][0]))) + return true; + + WARN_ONCE(true, "virq out of range %u.\n", virq); + return false; +} + +static int octeon_irq_ciu_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw) +{ + unsigned int line = hw >> 6; + unsigned int bit = hw & 63; + + if (!octeon_irq_virq_in_range(virq)) + return -EINVAL; + + if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) + return -EINVAL; + + if (octeon_irq_ciu_is_edge(line, bit)) + octeon_irq_set_ciu_mapping(virq, line, bit, + octeon_irq_ciu_chip, + handle_edge_irq); + else + octeon_irq_set_ciu_mapping(virq, line, bit, + octeon_irq_ciu_chip, + handle_level_irq); + + return 0; +} + +static int octeon_irq_gpio_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw) +{ + unsigned int line = hw >> 6; + unsigned int bit = hw & 63; + + if (!octeon_irq_virq_in_range(virq)) + return -EINVAL; + + if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) + return -EINVAL; + + octeon_irq_set_ciu_mapping(virq, line, bit, + octeon_irq_gpio_chip, + octeon_irq_handle_gpio); + + return 0; +} + +static struct irq_domain_ops octeon_irq_domain_ciu_ops = { + .map = octeon_irq_ciu_map, + .xlate = octeon_irq_ciu_xlat, +}; + +static struct irq_domain_ops octeon_irq_domain_gpio_ops = { + .map = octeon_irq_gpio_map, + .xlate = octeon_irq_gpio_xlat, +}; + static void octeon_irq_ip2_v1(void) { const unsigned long core_id = cvmx_get_core_num(); @@ -972,7 +1147,8 @@ static void __init octeon_irq_init_ciu(void) struct irq_chip *chip; struct irq_chip *chip_mbox; struct irq_chip *chip_wd; - struct irq_chip *chip_gpio; + struct device_node *gpio_node; + struct device_node *ciu_node; octeon_irq_init_ciu_percpu(); octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; @@ -986,15 +1162,16 @@ static void __init octeon_irq_init_ciu(void) chip = &octeon_irq_chip_ciu_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; - chip_gpio = &octeon_irq_chip_ciu_gpio_v2; + octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2; } else { octeon_irq_ip2 = octeon_irq_ip2_v1; octeon_irq_ip3 = octeon_irq_ip3_v1; chip = &octeon_irq_chip_ciu; chip_mbox = &octeon_irq_chip_ciu_mbox; chip_wd = &octeon_irq_chip_ciu_wd; - chip_gpio = &octeon_irq_chip_ciu_gpio; + octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio; } + octeon_irq_ciu_chip = chip; octeon_irq_ip4 = octeon_irq_ip4_mask; /* Mips internal */ @@ -1003,8 +1180,6 @@ static void __init octeon_irq_init_ciu(void) /* CIU_0 */ for (i = 0; i < 16; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); - for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, octeon_irq_handle_gpio); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); @@ -1035,6 +1210,28 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); + gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); + if (gpio_node) { + struct octeon_irq_gpio_domain_data *gpiod; + + gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL); + if (gpiod) { + /* gpio domain host_data is the base hwirq number. */ + gpiod->base_hwirq = 16; + irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod); + of_node_put(gpio_node); + } else + pr_warn("Cannot allocate memory for GPIO irq_domain.\n"); + } else + pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n"); + + ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); + if (ciu_node) { + irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); + of_node_put(ciu_node); + } else + pr_warn("Cannot find device node for cavium,octeon-3860-ciu.\n"); + /* Enable the CIU lines */ set_c0_status(STATUSF_IP3 | STATUSF_IP2); clear_c0_status(STATUSF_IP4); -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 00:57:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 00:59:38 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:40247 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903745Ab2FFW54 (ORCPT ); Thu, 7 Jun 2012 00:57:56 +0200 Received: by dadm1 with SMTP id m1so10178482dad.36 for ; Wed, 06 Jun 2012 15:57:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=uPLCGrsTmmuS/58/KgkC4AcJUGKcPlU2jtLEvMUsKjg=; b=YPd3mRt4RN+o4mB9pKxlgFg/RmWzPtYe+gEmTQfUK9ZJTYA9MJ53xyrlWQ92wqM4WK tC/rrqQN1+a7ocKDa9tFsY5MR09pB2L/gpr5VNu1epprAbplaTuFe5mSmhCUKCwYotgb Vtc5IRB/40dkrsBZYLbd5hrKj5ZbqKUbxRK502Mmw2yLNgfbmt+eY97dAj/xLSYfTgcs p3u7bCZfigvcMH8M7obRxHlucPq5OhpNt3sEseaK+Gce5WinySKK8s4f17EGHL+JCV3s EWv9JVOL6l1YTOj8dK7SwuR+QgUZFHn89qdphrU1pJdeeDzFkXLimbu+AdXMXd+meG83 EU0g== Received: by 10.68.203.7 with SMTP id km7mr2858424pbc.7.1339023469644; Wed, 06 Jun 2012 15:57:49 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ve6sm1798980pbc.75.2012.06.06.15.57.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 15:57:46 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56MvjSI020311; Wed, 6 Jun 2012 15:57:45 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56MviOQ020310; Wed, 6 Jun 2012 15:57:44 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v8 2/4] MIPS: Octeon: Add device tree source files. Date: Wed, 6 Jun 2012 15:57:41 -0700 Message-Id: <1339023463-20267-3-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339023463-20267-1-git-send-email-ddaney.cavm@gmail.com> References: <1339023463-20267-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33586 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 55655 Lines: 1905 From: David Daney The two device tree files octeon_3xxx.dts and octeon_68xx.dts are trimmed by code in a subsequent patch to reflect the hardware actually present on the board. To this end several properties that are not part of the declared bindings are added to aid in trimming off unwanted nodes. Since the device tree and the code that trims it are bound into the kernel binary, these 'marker' properties never escape into the wild, and are purely an implementation detail of the kernel early boot process. This is done for backwards compatibility with existing boards (identified by a board type enumeration value by their bootloaders). New boards will always pass a device tree from the bootloader, the built-in trees are ignored in this case. Signed-off-by: David Daney --- .../bindings/ata/cavium-compact-flash.txt | 30 + .../bindings/gpio/cavium-octeon-gpio.txt | 49 ++ .../devicetree/bindings/i2c/cavium-i2c.txt | 34 ++ .../devicetree/bindings/mips/cavium/bootbus.txt | 126 ++++ .../devicetree/bindings/mips/cavium/ciu.txt | 26 + .../devicetree/bindings/mips/cavium/ciu2.txt | 27 + .../devicetree/bindings/mips/cavium/dma-engine.txt | 21 + .../devicetree/bindings/mips/cavium/uctl.txt | 47 ++ .../devicetree/bindings/net/cavium-mdio.txt | 27 + .../devicetree/bindings/net/cavium-mix.txt | 40 ++ .../devicetree/bindings/net/cavium-pip.txt | 98 +++ .../devicetree/bindings/serial/cavium-uart.txt | 19 + arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 13 + arch/mips/cavium-octeon/octeon_3xxx.dts | 571 ++++++++++++++++++ arch/mips/cavium-octeon/octeon_68xx.dts | 625 ++++++++++++++++++++ 16 files changed, 1755 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/cavium-compact-flash.txt create mode 100644 Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt create mode 100644 Documentation/devicetree/bindings/i2c/cavium-i2c.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/bootbus.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu2.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/dma-engine.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/uctl.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mdio.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mix.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-pip.txt create mode 100644 Documentation/devicetree/bindings/serial/cavium-uart.txt create mode 100644 arch/mips/cavium-octeon/.gitignore create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt new file mode 100644 index 0000000..93986a5 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt @@ -0,0 +1,30 @@ +* Compact Flash + +The Cavium Compact Flash device is connected to the Octeon Boot Bus, +and is thus a child of the Boot Bus device. It can read and write +industry standard compact flash devices. + +Properties: +- compatible: "cavium,ebt3000-compact-flash"; + + Compatibility with many Cavium evaluation boards. + +- reg: The base address of the the CF chip select banks. Depending on + the device configuration, there may be one or two banks. + +- cavium,bus-width: The width of the connection to the CF devices. Valid + values are 8 and 16. + +- cavium,true-ide: Optional, if present the CF connection is in True IDE mode. + +- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected + to this device. + +Example: + compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt new file mode 100644 index 0000000..9d6dcd3 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt @@ -0,0 +1,49 @@ +* General Purpose Input Output (GPIO) bus. + +Properties: +- compatible: "cavium,octeon-3860-gpio" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the GPIO unit's register bank. + +- gpio-controller: This is a GPIO controller. + +- #gpio-cells: Must be <2>. The first cell is the GPIO pin. + +- interrupt-controller: The GPIO controller is also an interrupt + controller, many of its pins may be configured as an interrupt + source. + +- #interrupt-cells: Must be <2>. The first cell is the GPIO pin + connected to the interrupt source. The second cell is the interrupt + triggering protocol and may have one of four values: + 1 - edge triggered on the rising edge. + 2 - edge triggered on the falling edge + 4 - level triggered active high. + 8 - level triggered active low. + +- interrupts: Interrupt routing for each pin. + +Example: + + gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>, <0 17>, <0 18>, <0 19>, + <0 20>, <0 21>, <0 22>, <0 23>, + <0 24>, <0 25>, <0 26>, <0 27>, + <0 28>, <0 29>, <0 30>, <0 31>; + }; diff --git a/Documentation/devicetree/bindings/i2c/cavium-i2c.txt b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt new file mode 100644 index 0000000..dced82e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt @@ -0,0 +1,34 @@ +* Two Wire Serial Interface (TWSI) / I2C + +- compatible: "cavium,octeon-3860-twsi" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the TWSI/I2C bus controller register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. I2C addresses have no size component. + +- interrupts: A single interrupt specifier. + +- clock-frequency: The I2C bus clock rate in Hz. + +Example: + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt new file mode 100644 index 0000000..6581478 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt @@ -0,0 +1,126 @@ +* Boot Bus + +The Octeon Boot Bus is a configurable parallel bus with 8 chip +selects. Each chip select is independently configurable. + +Properties: +- compatible: "cavium,octeon-3860-bootbus" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the Boot Bus' register bank. + +- #address-cells: Must be <2>. The first cell is the chip select + within the bootbus. The second cell is the offset from the chip select. + +- #size-cells: Must be <1>. + +- ranges: There must be one one triplet of (child-bus-address, + parent-bus-address, length) for each active chip select. If the + length element for any triplet is zero, the chip select is disabled, + making it inactive. + +The configuration parameters for each chip select are stored in child +nodes. + +Configuration Properties: +- compatible: "cavium,octeon-3860-bootbus-config" + +- cavium,cs-index: A single cell indicating the chip select that + corresponds to this configuration. + +- cavium,t-adr: A cell specifying the ADR timing (in nS). + +- cavium,t-ce: A cell specifying the CE timing (in nS). + +- cavium,t-oe: A cell specifying the OE timing (in nS). + +- cavium,t-we: A cell specifying the WE timing (in nS). + +- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). + +- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). + +- cavium,t-pause: A cell specifying the PAUSE timing (in nS). + +- cavium,t-wait: A cell specifying the WAIT timing (in nS). + +- cavium,t-page: A cell specifying the PAGE timing (in nS). + +- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS). + +- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1 + = 2 bytes, 2 = 4 bytes, 3 = 8 bytes). + +- cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected. + +- cavium,page-mode: Optional. If present, page mode (PAGEM) is selected. + +- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of + the bus for this chip select. + +- cavium,ale-mode: Optional. If present, ALE mode is selected. + +- cavium,sam-mode: Optional. If present, SAM mode is selected. + +- cavium,or-mode: Optional. If present, OR mode is selected. + +Example: + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0x0 0x1d020000 0x10000>, + <5 0 0x0 0x1d040000 0x10000>, + <6 0 0x0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <20>; + cavium,t-ce = <60>; + cavium,t-oe = <60>; + cavium,t-we = <45>; + cavium,t-rd-hld = <35>; + cavium,t-wr-hld = <45>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <35>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + . + . + . + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <270>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <70>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + . + . + . + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt new file mode 100644 index 0000000..2c2d074 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu.txt @@ -0,0 +1,26 @@ +* Central Interrupt Unit + +Properties: +- compatible: "cavium,octeon-3860-ciu" + + Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is the bank within + the CIU and may have a value of 0 or 1. The second cell is the bit + within the bank and may have a value between 0 and 63. + +Example: + interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt new file mode 100644 index 0000000..0ec7ba8 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt @@ -0,0 +1,27 @@ +* Central Interrupt Unit + +Properties: +- compatible: "cavium,octeon-6880-ciu2" + + Compatibility with 68XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is the bank within + the CIU and may have a value between 0 and 63. The second cell is + the bit within the bank and may also have a value between 0 and 63. + +Example: + interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0..63) + * 2) Bit within the register (0..63) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt new file mode 100644 index 0000000..cb4291e --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt @@ -0,0 +1,21 @@ +* DMA Engine. + +The Octeon DMA Engine transfers between the Boot Bus and main memory. +The DMA Engine will be refered to by phandle by any device that is +connected to it. + +Properties: +- compatible: "cavium,octeon-5750-bootbus-dma" + + Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. + +- reg: The base address of the DMA Engine's register bank. + +- interrupts: A single interrupt specifier. + +Example: + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt new file mode 100644 index 0000000..5dabe02 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/uctl.txt @@ -0,0 +1,47 @@ +* UCTL USB controller glue + +Properties: +- compatible: "cavium,octeon-6335-uctl" + + Compatibility with all cn6XXX SOCs. + +- reg: The base address of the UCTL register bank. + +- #address-cells: Must be <2>. + +- #size-cells: Must be <2>. + +- ranges: Empty to signify direct mapping of the children. + +- refclk-frequency: A single cell containing the reference clock + frequency in Hz. + +- refclk-type: A string describing the reference clock connection + either "crystal" or "external". + +Example: + uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <24000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + }; + diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt new file mode 100644 index 0000000..04cb749 --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-mdio.txt @@ -0,0 +1,27 @@ +* System Management Interface (SMI) / MDIO + +Properties: +- compatible: "cavium,octeon-3860-mdio" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the MDIO bus controller register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. MDIO addresses have no size component. + +Typically an MDIO bus might have several children. + +Example: + mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + ethernet-phy@0 { + ... + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt new file mode 100644 index 0000000..e4f9d3c --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-mix.txt @@ -0,0 +1,40 @@ +* MIX Ethernet controller. + +Properties: +- compatible: "cavium,octeon-5750-mix" + + Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX + devices. + +- reg: The base addresses of four separate register banks. The first + bank contains the MIX registers. The second bank the corresponding + AGL registers. The third bank are the AGL registers shared by all + MIX devices present. The fourth bank is the AGL_PRT_CTL shared by + all MIX devices present. + +- cell-index: A single cell specifying which portion of the shared + register banks corresponds to this MIX device. + +- interrupts: Two interrupt specifiers. The first is the MIX + interrupt routing and the second the routing for the AGL interrupts. + +- mac-address: Optional, the MAC address to assign to the device. + +- local-mac-address: Optional, the MAC address to assign to the device + if mac-address is not specified. + +- phy-handle: Optional, a phandle for the PHY device connected to this device. + +Example: + ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 0f b7 10 63 54 ]; + phy-handle = <&phy1>; + }; + diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt new file mode 100644 index 0000000..d4c53ba --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-pip.txt @@ -0,0 +1,98 @@ +* PIP Ethernet nexus. + +The PIP Ethernet nexus can control several data packet input/output +devices. The devices have a two level grouping scheme. There may be +several interfaces, and each interface may have several ports. These +ports might be an individual Ethernet PHY. + + +Properties for the PIP nexus: +- compatible: "cavium,octeon-3860-pip" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the PIP's register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. + +Properties for PIP interfaces which is a child the PIP nexus: +- compatible: "cavium,octeon-3860-pip-interface" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The interface number. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. + +Properties for PIP port which is a child the PIP interface: +- compatible: "cavium,octeon-3860-pip-port" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The port number within the interface group. + +- mac-address: Optional, the MAC address to assign to the device. + +- local-mac-address: Optional, the MAC address to assign to the device + if mac-address is not specified. + +- phy-handle: Optional, a phandle for the PHY device connected to this device. + +Example: + + pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 60 ]; + phy-handle = <&phy2>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 61 ]; + phy-handle = <&phy3>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 62 ]; + phy-handle = <&phy4>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 63 ]; + phy-handle = <&phy5>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 64 ]; + phy-handle = <&phy6>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/serial/cavium-uart.txt b/Documentation/devicetree/bindings/serial/cavium-uart.txt new file mode 100644 index 0000000..87a6c37 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cavium-uart.txt @@ -0,0 +1,19 @@ +* Universal Asynchronous Receiver/Transmitter (UART) + +- compatible: "cavium,octeon-3860-uart" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the UART register bank. + +- interrupts: A single interrupt specifier. + +- current-speed: Optional, the current bit rate in bits per second. + +Example: + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + current-speed = <115200>; + interrupts = <0 35>; + }; diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore new file mode 100644 index 0000000..39c9686 --- /dev/null +++ b/arch/mips/cavium-octeon/.gitignore @@ -0,0 +1,2 @@ +*.dtb.S +*.dtb diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 19eb043..1e37522 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -15,3 +15,16 @@ obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o + +DTS_FILES = octeon_3xxx.dts octeon_68xx.dts +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) + +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) + +$(obj)/%.dtb: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) + +# Let's keep the .dtb files around in case we want to look at them. +.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES)) + +clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES)) diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts new file mode 100644 index 0000000..f28b2d0 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_3xxx.dts @@ -0,0 +1,571 @@ +/dts-v1/; +/* + * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + compatible = "cavium,octeon-3860"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu: interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>, <0 17>, <0 18>, <0 19>, + <0 20>, <0 21>, <0 22>, <0 23>, + <0 24>, <0 25>, <0 26>, <0 27>, + <0 28>, <0 29>, <0 30>, <0 31>; + }; + + smi0: mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + phy0: ethernet-phy@0 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + + phy6: ethernet-phy@6 { + reg = <6>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000001900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001900 0x0 0x40>; + + phy100: ethernet-phy@1 { + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy101: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy102: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy103: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupts = <0 62>, <1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + mix1: ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + cavium,alt-phy-handle = <&phy100>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + cavium,alt-phy-handle = <&phy101>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + cavium,alt-phy-handle = <&phy102>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy5>; + cavium,alt-phy-handle = <&phy103>; + }; + ethernet@4 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x4>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@5 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x5>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@6 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x6>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@7 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x7>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@8 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x8>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@9 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x9>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@a { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xa>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@b { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xb>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@c { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xc>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@d { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xd>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@e { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xe>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@f { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xf>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy6>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy7>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy8>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy9>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupts = <0 59>; + clock-frequency = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 34>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 35>; + }; + + uart2: serial@1180000000400 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000400 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <1 16>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0x0 0x1d020000 0x10000>, + <5 0 0x0 0x1d040000 0x10000>, + <6 0 0x0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <20>; + cavium,t-ce = <60>; + cavium,t-oe = <60>; + cavium,t-we = <45>; + cavium,t-rd-hld = <35>; + cavium,t-wr-hld = <45>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <35>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <320>; + cavium,t-ce = <320>; + cavium,t-oe = <320>; + cavium,t-we = <320>; + cavium,t-rd-hld = <320>; + cavium,t-wr-hld = <320>; + cavium,t-pause = <320>; + cavium,t-wait = <320>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@5 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <5>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <30>; + cavium,t-pause = <0>; + cavium,t-wait = <30>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <16>; + }; + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <270>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <70>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + led0: led-display@4,0 { + compatible = "avago,hdsp-253x"; + reg = <4 0x20 0x20>, <4 0 0x20>; + }; + + cf0: compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; + }; + + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; + dma1: dma-engine@1180000000108 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000108 0x0 0x8>; + interrupts = <0 63>; + }; + + uctl: uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <12000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + }; + }; + + aliases { + mix0 = &mix0; + mix1 = &mix1; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + twsi0 = &twsi0; + twsi1 = &twsi1; + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + flash0 = &flash0; + cf0 = &cf0; + uctl = &uctl; + led0 = &led0; + }; + }; diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts new file mode 100644 index 0000000..1839468 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_68xx.dts @@ -0,0 +1,625 @@ +/dts-v1/; +/* + * OCTEON 68XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + compatible = "cavium,octeon-6880"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu2>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu2: interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 7) + * 2) Bit within the register (0..63) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pins connect to 16 consecutive CUI bits */ + interrupts = <7 0>, <7 1>, <7 2>, <7 3>, + <7 4>, <7 5>, <7 6>, <7 7>, + <7 8>, <7 9>, <7 10>, <7 11>, + <7 12>, <7 13>, <7 14>, <7 15>; + }; + + smi0: mdio@1180000003800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003800 0x0 0x40>; + + phy0: ethernet-phy@6 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <6>; + }; + + phy1: ethernet-phy@1 { + cavium,qlm-trim = "4,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy2: ethernet-phy@2 { + cavium,qlm-trim = "4,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + cavium,qlm-trim = "4,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + cavium,qlm-trim = "4,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000003880 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003880 0x0 0x40>; + + phy41: ethernet-phy@1 { + cavium,qlm-trim = "0,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy42: ethernet-phy@2 { + cavium,qlm-trim = "0,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy43: ethernet-phy@3 { + cavium,qlm-trim = "0,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy44: ethernet-phy@4 { + cavium,qlm-trim = "0,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi2: mdio@1180000003900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003900 0x0 0x40>; + + phy21: ethernet-phy@1 { + cavium,qlm-trim = "2,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy22: ethernet-phy@2 { + cavium,qlm-trim = "2,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy23: ethernet-phy@3 { + cavium,qlm-trim = "2,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy24: ethernet-phy@4 { + cavium,qlm-trim = "2,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi3: mdio@1180000003980 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003980 0x0 0x40>; + + phy11: ethernet-phy@1 { + cavium,qlm-trim = "3,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy12: ethernet-phy@2 { + cavium,qlm-trim = "3,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy13: ethernet-phy@3 { + cavium,qlm-trim = "3,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy14: ethernet-phy@4 { + cavium,qlm-trim = "3,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupts = <6 40>, <6 32>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@4 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + }; + }; + + interface@3 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy11>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy12>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy13>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy14>; + }; + }; + + interface@2 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy21>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy22>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy23>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy24>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy41>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy42>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy43>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy44>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <3 32>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupts = <3 33>; + clock-frequency = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <3 36>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <3 37>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0 0x1d020000 0x10000>, + <5 0 0 0x1d040000 0x10000>, + <6 0 0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <10>; + cavium,t-ce = <50>; + cavium,t-oe = <50>; + cavium,t-we = <35>; + cavium,t-rd-hld = <25>; + cavium,t-wr-hld = <35>; + cavium,t-pause = <0>; + cavium,t-wait = <300>; + cavium,t-page = <25>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <320>; + cavium,t-ce = <320>; + cavium,t-oe = <320>; + cavium,t-we = <320>; + cavium,t-rd-hld = <320>; + cavium,t-wr-hld = <320>; + cavium,t-pause = <320>; + cavium,t-wait = <320>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@5 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <5>; + cavium,t-adr = <0>; + cavium,t-ce = <300>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <300>; + cavium,t-pause = <0>; + cavium,t-wait = <300>; + cavium,t-page = <310>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <16>; + }; + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <0>; + cavium,t-ce = <30>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <30>; + cavium,t-pause = <0>; + cavium,t-wait = <30>; + cavium,t-page = <310>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0 0x200000>; + read-only; + }; + partition@200000 { + label = "kernel"; + reg = <0x200000 0x200000>; + }; + partition@400000 { + label = "cramfs"; + reg = <0x400000 0x3fe000>; + }; + partition@7fe000 { + label = "environment"; + reg = <0x7fe000 0x2000>; + read-only; + }; + }; + + led0: led-display@4,0 { + compatible = "avago,hdsp-253x"; + reg = <4 0x20 0x20>, <4 0 0x20>; + }; + + compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; + }; + + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; + dma1: dma-engine@1180000000108 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000108 0x0 0x8>; + interrupts = <0 63>; + }; + + uctl: uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <12000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <3 44>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <3 44>; + big-endian-regs; + }; + }; + }; + + aliases { + mix0 = &mix0; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + smi2 = &smi2; + smi3 = &smi3; + twsi0 = &twsi0; + twsi1 = &twsi1; + uart0 = &uart0; + uart1 = &uart1; + uctl = &uctl; + led0 = &led0; + flash0 = &flash0; + }; + }; -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 01:28:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 01:28:50 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:61115 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903717Ab2FFX2p (ORCPT ); Thu, 7 Jun 2012 01:28:45 +0200 Received: by dadm1 with SMTP id m1so8178dad.36 for ; Wed, 06 Jun 2012 16:28:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=59jUNHwQc/1HmRo1xhil1isGb0YUokNwGXRjHCaRwQI=; b=lJ9sAF74qNwN15xFtkT8W8dioSOl9RAk/bapExbDDx1QVJhbUW3Ai06Fsw64tPTqCA w/0UYTsJfYgKezfIoOgBW/Add9DbtrzEBXGH94OBs5UMGc1tSOo8zj1HknfQyB6dP+I5 Evh06T2Uv2F4HMDUx/wH7FQonpL4BLd3Ekv8+gC2mFt0UWo/2LdYLJ76AqH9uLkCXMgu j+CjwLi7CpBxSRgt2Rqip7KM9xQ3JbFV8PEAlBjYDseDMUUysuWjIJL+FiNHBw35+qUL 1pnAPwvQh14+aM2QRsK388FtKQtgNUStMswRzOc7Hx27ZV5hEvY1rydiCyiSHQu1cRQI YBPw== Received: by 10.68.194.6 with SMTP id hs6mr1039326pbc.133.1339025319140; Wed, 06 Jun 2012 16:28:39 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id qn1sm1907792pbc.9.2012.06.06.16.28.37 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 16:28:38 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56NSaAd024254; Wed, 6 Jun 2012 16:28:36 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56NSZkj024252; Wed, 6 Jun 2012 16:28:35 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v3 0/5] MIPS: OCTEON: Convert some device to use Device Tree. Date: Wed, 6 Jun 2012 16:28:29 -0700 Message-Id: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33587 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2046 Lines: 59 From: David Daney This patch set depends on the previous set to add Device Tree to OCTEON. That set can be found among other places here: http://www.linux-mips.org/archives/linux-mips/2012-06/msg00081.html For v3: No functional changes, Added more Acked-bys, rebased to avoid merge conflicts. For v2: No functional changes, but minor clean-ups to use some new device tree helper functions. Some Acked-bys added. I am suggesting that all these go via Ralf's linux-mips.org tree as they depend on other patches in that tree. >From v1: The patches are for drivers scattered throughout the tree, but there is an order dependency as well as the dependency mentioned above, so it may be preferable to merge them all via Ralf's linux-mips.org tree rather that separately via the various device sub-system maintainers. The mdio-octeon.c and octeon_mgmt patches were already Acked-by davem. The i2c has been seen before, but to my knowledge was never acked. The octeon_ethernet patch is in staging and has also been seen before. The serial patch is new. David Daney (5): i2c: Convert i2c-octeon.c to use device tree. netdev: mdio-octeon.c: Convert to use device tree. netdev: octeon_mgmt: Convert to use device tree. staging: octeon_ethernet: Convert to use device tree. MIPS: Octeon: Use device tree to register serial ports. arch/mips/cavium-octeon/octeon-irq.c | 8 - arch/mips/cavium-octeon/octeon-platform.c | 176 ---------------- arch/mips/cavium-octeon/serial.c | 134 +++++-------- arch/mips/include/asm/octeon/octeon.h | 5 - drivers/i2c/busses/i2c-octeon.c | 92 +++++---- drivers/net/ethernet/octeon/octeon_mgmt.c | 312 +++++++++++++++++++---------- drivers/net/phy/mdio-octeon.c | 92 ++++++--- drivers/staging/octeon/ethernet-mdio.c | 28 ++-- drivers/staging/octeon/ethernet.c | 153 +++++++++----- drivers/staging/octeon/octeon-ethernet.h | 3 + 10 files changed, 484 insertions(+), 519 deletions(-) -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 01:28:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 01:29:14 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:37256 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903738Ab2FFX2q (ORCPT ); Thu, 7 Jun 2012 01:28:46 +0200 Received: by dadm1 with SMTP id m1so8201dad.36 for ; Wed, 06 Jun 2012 16:28:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=PoqGqfwVU98O82elsXuhXtWd7TtctXU61fRoNyGIDzE=; b=KtmIDljUGSJSkHyfv70tCfmM72myYlTzOOnoNANmVkwpvXgPBlSVgULLDJNOMjmtuN rM4lkN9VyuIi1ZEIrRLjJuOD18LcPbXKeQ/ALcmRMYQkSj00j/WxF3UwAuGoBUsotHpc BlJMtUBPpoGUbNGxs/V18MThG38qJW8bRnyqwPUyxivyto4NySilxYJR/e2GQagzuhZU eUBEKwbE+bLYk5vPxluW9Wyj9jWJHqYQsJDE3XVVxapbaniIXIn+pRTPIkOkRiDQfsgK II9Q8VsChN3fRAtqKGcyp25BwYemWMwuYD/4FJV7Zg5PbA8tEBDqHc9655JsBDj6nFDn /rSw== Received: by 10.68.236.129 with SMTP id uu1mr1645219pbc.77.1339025319984; Wed, 06 Jun 2012 16:28:39 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ol1sm1903962pbb.25.2012.06.06.16.28.37 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 16:28:38 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56NSbvq024262; Wed, 6 Jun 2012 16:28:37 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56NSbNs024261; Wed, 6 Jun 2012 16:28:37 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v3 2/5] netdev: mdio-octeon.c: Convert to use device tree. Date: Wed, 6 Jun 2012 16:28:31 -0700 Message-Id: <1339025314-24216-3-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> References: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33588 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7119 Lines: 258 From: David Daney Get the MDIO bus controller addresses from the device tree, small clean up in use of devm_* Remove, now unused, platform device setup code. Acked-by: David S. Miller Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-platform.c | 30 --------- drivers/net/phy/mdio-octeon.c | 92 ++++++++++++++++++----------- 2 files changed, 58 insertions(+), 64 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index f62a40f..66cabc2 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -168,36 +168,6 @@ out: } device_initcall(octeon_rng_device_init); -/* Octeon SMI/MDIO interface. */ -static int __init octeon_mdiobus_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - - if (octeon_is_simulation()) - return 0; /* No mdio in the simulator. */ - - /* The bus number is the platform_device id. */ - pd = platform_device_alloc("mdio-octeon", 0); - if (!pd) { - ret = -ENOMEM; - goto out; - } - - ret = platform_device_add(pd); - if (ret) - goto fail; - - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mdiobus_device_init); - /* Octeon mgmt port Ethernet interface. */ static int __init octeon_mgmt_device_init(void) { diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c index 826d961..d4015aa 100644 --- a/drivers/net/phy/mdio-octeon.c +++ b/drivers/net/phy/mdio-octeon.c @@ -3,14 +3,17 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2009 Cavium Networks + * Copyright (C) 2009,2011 Cavium, Inc. */ -#include -#include -#include #include +#include +#include +#include +#include +#include #include +#include #include #include @@ -18,9 +21,17 @@ #define DRV_VERSION "1.0" #define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver" +#define SMI_CMD 0x0 +#define SMI_WR_DAT 0x8 +#define SMI_RD_DAT 0x10 +#define SMI_CLK 0x18 +#define SMI_EN 0x20 + struct octeon_mdiobus { struct mii_bus *mii_bus; - int unit; + u64 register_base; + resource_size_t mdio_phys; + resource_size_t regsize; int phy_irq[PHY_MAX_ADDR]; }; @@ -35,15 +46,15 @@ static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum) smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); + cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - cvmx_wait(1000); - smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(p->unit)); + __delay(1000); + smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT); } while (smi_rd.s.pending && --timeout); if (smi_rd.s.val) @@ -62,21 +73,21 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, smi_wr.u64 = 0; smi_wr.s.dat = val; - cvmx_write_csr(CVMX_SMIX_WR_DAT(p->unit), smi_wr.u64); + cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64); smi_cmd.u64 = 0; smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); + cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - cvmx_wait(1000); - smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(p->unit)); + __delay(1000); + smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT); } while (smi_wr.s.pending && --timeout); if (timeout <= 0) @@ -88,38 +99,44 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) { struct octeon_mdiobus *bus; + struct resource *res_mem; union cvmx_smix_en smi_en; - int i; int err = -ENOENT; bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); if (!bus) return -ENOMEM; - /* The platform_device id is our unit number. */ - bus->unit = pdev->id; + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (res_mem == NULL) { + dev_err(&pdev->dev, "found no memory resource\n"); + err = -ENXIO; + goto fail; + } + bus->mdio_phys = res_mem->start; + bus->regsize = resource_size(res_mem); + if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize, + res_mem->name)) { + dev_err(&pdev->dev, "request_mem_region failed\n"); + goto fail; + } + bus->register_base = + (u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize); bus->mii_bus = mdiobus_alloc(); if (!bus->mii_bus) - goto err; + goto fail; smi_en.u64 = 0; smi_en.s.en = 1; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); - - /* - * Standard Octeon evaluation boards don't support phy - * interrupts, we need to poll. - */ - for (i = 0; i < PHY_MAX_ADDR; i++) - bus->phy_irq[i] = PHY_POLL; + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); bus->mii_bus->priv = bus; bus->mii_bus->irq = bus->phy_irq; bus->mii_bus->name = "mdio-octeon"; - snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", - bus->mii_bus->name, bus->unit); + snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base); bus->mii_bus->parent = &pdev->dev; bus->mii_bus->read = octeon_mdiobus_read; @@ -127,20 +144,18 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, bus); - err = mdiobus_register(bus->mii_bus); + err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node); if (err) - goto err_register; + goto fail_register; dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); return 0; -err_register: +fail_register: mdiobus_free(bus->mii_bus); - -err: - devm_kfree(&pdev->dev, bus); +fail: smi_en.u64 = 0; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); return err; } @@ -154,14 +169,23 @@ static int __devexit octeon_mdiobus_remove(struct platform_device *pdev) mdiobus_unregister(bus->mii_bus); mdiobus_free(bus->mii_bus); smi_en.u64 = 0; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); return 0; } +static struct of_device_id octeon_mdiobus_match[] = { + { + .compatible = "cavium,octeon-3860-mdio", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_mdiobus_match); + static struct platform_driver octeon_mdiobus_driver = { .driver = { .name = "mdio-octeon", .owner = THIS_MODULE, + .of_match_table = octeon_mdiobus_match, }, .probe = octeon_mdiobus_probe, .remove = __devexit_p(octeon_mdiobus_remove), -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 01:28:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 01:29:44 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:61250 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903741Ab2FFX2q (ORCPT ); Thu, 7 Jun 2012 01:28:46 +0200 Received: by dadm1 with SMTP id m1so8205dad.36 for ; Wed, 06 Jun 2012 16:28:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=ta9z0tVBR1c8phUfaoCNieFW4ziS1JCyvO1SNE+nylM=; b=CFS9vh44omq8zPfWBptr4TI+R+uudrmwXp1nQWoGvnWcVKgG8KXf4dqWq6kZ35AzCc dTIAI43cA8KYFWkaYy7+u+2zkLU+cyznndwHjmimB3O8fcUA547k8DYWr6vCr+/ULCtF bNOUIwDRFtVGiXNnI+LHkDMydrlzAe+eHK6cmgqUj9WDyIEOMUBoGFrxvF558zKBuFmv qLN9S76mCZZKhYIIGRiTtzWZJrtxiLlqdKvaA+094WStRfM2h9QeQnG2ycuLTib+1pRG 2zlBVpbtvHATDaqXW6exv61wTgY9VxM9dHt3T8vNaHynDjjibei3+Tj3JalCHCiXItF4 U+qA== Received: by 10.68.138.169 with SMTP id qr9mr1832072pbb.27.1339025319615; Wed, 06 Jun 2012 16:28:39 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id pe2sm1887602pbc.59.2012.06.06.16.28.37 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 16:28:38 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56NSbuV024258; Wed, 6 Jun 2012 16:28:37 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56NSbZA024257; Wed, 6 Jun 2012 16:28:37 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v3 1/5] i2c: Convert i2c-octeon.c to use device tree. Date: Wed, 6 Jun 2012 16:28:30 -0700 Message-Id: <1339025314-24216-2-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> References: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33589 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10827 Lines: 376 From: David Daney There are three parts to this: 1) Remove the definitions of OCTEON_IRQ_TWSI and OCTEON_IRQ_TWSI2. The interrupts are specified by the device tree and these hard coded irq numbers block the used of the irq lines by the irq_domain code. 2) Remove platform device setup code from octeon-platform.c, it is now unused. 3) Convert i2c-octeon.c to use device tree. Part of this includes using the devm_* functions instead of the raw counterparts, thus simplifying error handling. No functionality is changed. Signed-off-by: David Daney Acked-by: Rob Herring Acked-by: Wolfram Sang --- arch/mips/cavium-octeon/octeon-irq.c | 2 - arch/mips/cavium-octeon/octeon-platform.c | 84 -------------------------- arch/mips/include/asm/octeon/octeon.h | 5 -- drivers/i2c/busses/i2c-octeon.c | 92 +++++++++++++++------------- 4 files changed, 49 insertions(+), 134 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 52610ce..2a661ad 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -1192,13 +1192,11 @@ static void __init octeon_irq_init_ciu(void) for (i = 0; i < 4; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); for (i = 0; i < 4; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip, handle_edge_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 2754bc2..f62a40f 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -168,90 +168,6 @@ out: } device_initcall(octeon_rng_device_init); -static struct i2c_board_info __initdata octeon_i2c_devices[] = { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static int __init octeon_i2c_devices_init(void) -{ - return i2c_register_board_info(0, octeon_i2c_devices, - ARRAY_SIZE(octeon_i2c_devices)); -} -arch_initcall(octeon_i2c_devices_init); - -#define OCTEON_I2C_IO_BASE 0x1180000001000ull -#define OCTEON_I2C_IO_UNIT_OFFSET 0x200 - -static struct octeon_i2c_data octeon_i2c_data[2]; - -static int __init octeon_i2c_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - int port, num_ports; - - struct resource i2c_resources[] = { - { - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, - } - }; - - if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) - num_ports = 2; - else - num_ports = 1; - - for (port = 0; port < num_ports; port++) { - octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate(); - /*FIXME: should be examined. At the moment is set for 100Khz */ - octeon_i2c_data[port].i2c_freq = 100000; - - pd = platform_device_alloc("i2c-octeon", port); - if (!pd) { - ret = -ENOMEM; - goto out; - } - - pd->dev.platform_data = octeon_i2c_data + port; - - i2c_resources[0].start = - OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET); - i2c_resources[0].end = i2c_resources[0].start + 0x1f; - switch (port) { - case 0: - i2c_resources[1].start = OCTEON_IRQ_TWSI; - i2c_resources[1].end = OCTEON_IRQ_TWSI; - break; - case 1: - i2c_resources[1].start = OCTEON_IRQ_TWSI2; - i2c_resources[1].end = OCTEON_IRQ_TWSI2; - break; - default: - BUG(); - } - - ret = platform_device_add_resources(pd, - i2c_resources, - ARRAY_SIZE(i2c_resources)); - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - } - return ret; -fail: - platform_device_put(pd); -out: - return ret; -} -device_initcall(octeon_i2c_device_init); - /* Octeon SMI/MDIO interface. */ static int __init octeon_mdiobus_device_init(void) { diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index f72f768..1e2486e 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -215,11 +215,6 @@ struct octeon_cf_data { int dma_engine; /* -1 for no DMA */ }; -struct octeon_i2c_data { - unsigned int sys_freq; - unsigned int i2c_freq; -}; - extern void octeon_write_lcd(const char *s); extern void octeon_check_cpu_bist(void); extern int octeon_get_boot_debug_flag(void); diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c index ee139a5..f44c835 100644 --- a/drivers/i2c/busses/i2c-octeon.c +++ b/drivers/i2c/busses/i2c-octeon.c @@ -2,7 +2,7 @@ * (C) Copyright 2009-2010 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com * - * Portions Copyright (C) 2010 Cavium Networks, Inc. + * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc. * * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors. * @@ -11,17 +11,18 @@ * warranty of any kind, whether express or implied. */ +#include +#include #include #include +#include +#include #include #include #include - -#include #include -#include -#include -#include +#include +#include #include @@ -65,7 +66,7 @@ struct octeon_i2c { wait_queue_head_t queue; struct i2c_adapter adap; int irq; - int twsi_freq; + u32 twsi_freq; int sys_freq; resource_size_t twsi_phys; void __iomem *twsi_base; @@ -121,10 +122,8 @@ static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg) */ static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) { - u64 tmp; - __raw_writeq(data, i2c->twsi_base + TWSI_INT); - tmp = __raw_readq(i2c->twsi_base + TWSI_INT); + __raw_readq(i2c->twsi_base + TWSI_INT); } /** @@ -515,7 +514,6 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) { int irq, result = 0; struct octeon_i2c *i2c; - struct octeon_i2c_data *i2c_data; struct resource *res_mem; /* All adaptors have an irq. */ @@ -523,86 +521,90 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) if (irq < 0) return irq; - i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); if (!i2c) { dev_err(&pdev->dev, "kzalloc failed\n"); result = -ENOMEM; goto out; } i2c->dev = &pdev->dev; - i2c_data = pdev->dev.platform_data; res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res_mem == NULL) { dev_err(i2c->dev, "found no memory resource\n"); result = -ENXIO; - goto fail_region; + goto out; } + i2c->twsi_phys = res_mem->start; + i2c->regsize = resource_size(res_mem); - if (i2c_data == NULL) { - dev_err(i2c->dev, "no I2C frequency data\n"); + /* + * "clock-rate" is a legacy binding, the official binding is + * "clock-frequency". Try the official one first and then + * fall back if it doesn't exist. + */ + if (of_property_read_u32(pdev->dev.of_node, + "clock-frequency", &i2c->twsi_freq) && + of_property_read_u32(pdev->dev.of_node, + "clock-rate", &i2c->twsi_freq)) { + dev_err(i2c->dev, + "no I2C 'clock-rate' or 'clock-frequency' property\n"); result = -ENXIO; - goto fail_region; + goto out; } - i2c->twsi_phys = res_mem->start; - i2c->regsize = resource_size(res_mem); - i2c->twsi_freq = i2c_data->i2c_freq; - i2c->sys_freq = i2c_data->sys_freq; + i2c->sys_freq = octeon_get_io_clock_rate(); - if (!request_mem_region(i2c->twsi_phys, i2c->regsize, res_mem->name)) { + if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize, + res_mem->name)) { dev_err(i2c->dev, "request_mem_region failed\n"); - goto fail_region; + goto out; } - i2c->twsi_base = ioremap(i2c->twsi_phys, i2c->regsize); + i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize); init_waitqueue_head(&i2c->queue); i2c->irq = irq; - result = request_irq(i2c->irq, octeon_i2c_isr, 0, DRV_NAME, i2c); + result = devm_request_irq(&pdev->dev, i2c->irq, + octeon_i2c_isr, 0, DRV_NAME, i2c); if (result < 0) { dev_err(i2c->dev, "failed to attach interrupt\n"); - goto fail_irq; + goto out; } result = octeon_i2c_initlowlevel(i2c); if (result) { dev_err(i2c->dev, "init low level failed\n"); - goto fail_add; + goto out; } result = octeon_i2c_setclock(i2c); if (result) { dev_err(i2c->dev, "clock init failed\n"); - goto fail_add; + goto out; } i2c->adap = octeon_i2c_ops; i2c->adap.dev.parent = &pdev->dev; - i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0; + i2c->adap.dev.of_node = pdev->dev.of_node; i2c_set_adapdata(&i2c->adap, i2c); platform_set_drvdata(pdev, i2c); - result = i2c_add_numbered_adapter(&i2c->adap); + result = i2c_add_adapter(&i2c->adap); if (result < 0) { dev_err(i2c->dev, "failed to add adapter\n"); goto fail_add; } - dev_info(i2c->dev, "version %s\n", DRV_VERSION); - return result; + of_i2c_register_devices(&i2c->adap); + + return 0; fail_add: platform_set_drvdata(pdev, NULL); - free_irq(i2c->irq, i2c); -fail_irq: - iounmap(i2c->twsi_base); - release_mem_region(i2c->twsi_phys, i2c->regsize); -fail_region: - kfree(i2c); out: return result; }; @@ -613,19 +615,24 @@ static int __devexit octeon_i2c_remove(struct platform_device *pdev) i2c_del_adapter(&i2c->adap); platform_set_drvdata(pdev, NULL); - free_irq(i2c->irq, i2c); - iounmap(i2c->twsi_base); - release_mem_region(i2c->twsi_phys, i2c->regsize); - kfree(i2c); return 0; }; +static struct of_device_id octeon_i2c_match[] = { + { + .compatible = "cavium,octeon-3860-twsi", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_i2c_match); + static struct platform_driver octeon_i2c_driver = { .probe = octeon_i2c_probe, .remove = __devexit_p(octeon_i2c_remove), .driver = { .owner = THIS_MODULE, .name = DRV_NAME, + .of_match_table = octeon_i2c_match, }, }; @@ -635,4 +642,3 @@ MODULE_AUTHOR("Michael Lawnick "); MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_VERSION); -MODULE_ALIAS("platform:" DRV_NAME); -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 01:28:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 01:30:10 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:50992 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903744Ab2FFX2r (ORCPT ); Thu, 7 Jun 2012 01:28:47 +0200 Received: by pbbrq13 with SMTP id rq13so206403pbb.36 for ; Wed, 06 Jun 2012 16:28:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Sr4LMq+/RTqBGoct9NS5rW+2Yz0Cs6+1zw41iVZrQMI=; b=DfEOcaMsvpUb/ICYuVzeyPtcgVySXlsrNYmAyq7kNgEh09Cua8/OR05fSbCfkTvSvo UtGMmK14PbLbHQ41mFwjPjl92N5cupUAU1zDkNQWjRB/OTwJzYV/iraTpVGUumZuP2mT 9gSMelrjGUqZqaXEJjffDu5RgWu9lyaiwdbo4uxtcdmRUCir8pECGDlsu36lmBhkvfPI XTPEdQXG5S4c91m4H9C9IPSIRJtf0ogyMqvcmRJanYMcYVO5/waqFNe9wuHZm/7UFDN2 uEfTcIAkUTXoBoydbSLzUqKY6Aibc3+5wgd7w0EmutlU8HZ9hFDi0BLAztJ5nvPkctzK utqw== Received: by 10.68.219.135 with SMTP id po7mr1295495pbc.149.1339025320449; Wed, 06 Jun 2012 16:28:40 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id sy3sm1906031pbc.18.2012.06.06.16.28.38 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 16:28:38 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56NSba5024270; Wed, 6 Jun 2012 16:28:37 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56NSbs4024269; Wed, 6 Jun 2012 16:28:37 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v3 4/5] staging: octeon_ethernet: Convert to use device tree. Date: Wed, 6 Jun 2012 16:28:33 -0700 Message-Id: <1339025314-24216-5-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> References: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33590 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 11652 Lines: 371 From: David Daney Get MAC address and PHY connection from the device tree. The driver is converted to a platform driver. Signed-off-by: David Daney Acked-by: Grant Likely --- drivers/staging/octeon/ethernet-mdio.c | 28 +++--- drivers/staging/octeon/ethernet.c | 153 +++++++++++++++++++----------- drivers/staging/octeon/octeon-ethernet.h | 3 + 3 files changed, 117 insertions(+), 67 deletions(-) diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index e31949c..f15b31b 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -161,22 +162,23 @@ static void cvm_oct_adjust_link(struct net_device *dev) int cvm_oct_phy_setup_device(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); + struct device_node *phy_node; - int phy_addr = cvmx_helper_board_get_mii_address(priv->port); - if (phy_addr != -1) { - char phy_id[MII_BUS_ID_SIZE + 3]; + if (!priv->of_node) + return 0; - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", phy_addr); + phy_node = of_parse_phandle(priv->of_node, "phy-handle", 0); + if (!phy_node) + return 0; - priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0, - PHY_INTERFACE_MODE_GMII); + priv->phydev = of_phy_connect(dev, phy_node, cvm_oct_adjust_link, 0, + PHY_INTERFACE_MODE_GMII); + + if (priv->phydev == NULL) + return -ENODEV; + + priv->last_link = 0; + phy_start_aneg(priv->phydev); - if (IS_ERR(priv->phydev)) { - priv->phydev = NULL; - return -1; - } - priv->last_link = 0; - phy_start_aneg(priv->phydev); - } return 0; } diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 18f7a79..683bedc 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -24,6 +24,7 @@ * This file may also be available under a different license from Cavium. * Contact Cavium Networks for more information **********************************************************************/ +#include #include #include #include @@ -32,6 +33,7 @@ #include #include #include +#include #include @@ -113,15 +115,6 @@ int rx_napi_weight = 32; module_param(rx_napi_weight, int, 0444); MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter."); -/* - * The offset from mac_addr_base that should be used for the next port - * that is configured. By convention, if any mgmt ports exist on the - * chip, they get the first mac addresses, The ports controlled by - * this driver are numbered sequencially following any mgmt addresses - * that may exist. - */ -static unsigned int cvm_oct_mac_addr_offset; - /** * cvm_oct_poll_queue - Workqueue for polling operations. */ @@ -176,7 +169,7 @@ static void cvm_oct_periodic_worker(struct work_struct *work) queue_delayed_work(cvm_oct_poll_queue, &priv->port_periodic_work, HZ); } -static __init void cvm_oct_configure_common_hw(void) +static __devinit void cvm_oct_configure_common_hw(void) { /* Setup the FPA */ cvmx_fpa_enable(); @@ -396,23 +389,21 @@ static void cvm_oct_common_set_multicast_list(struct net_device *dev) * Returns Zero on success */ -static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) +static int cvm_oct_set_mac_filter(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); union cvmx_gmxx_prtx_cfg gmx_cfg; int interface = INTERFACE(priv->port); int index = INDEX(priv->port); - memcpy(dev->dev_addr, addr + 2, 6); - if ((interface < 2) && (cvmx_helper_interface_get_mode(interface) != CVMX_HELPER_INTERFACE_MODE_SPI)) { int i; - uint8_t *ptr = addr; + uint8_t *ptr = dev->dev_addr; uint64_t mac = 0; for (i = 0; i < 6; i++) - mac = (mac << 8) | (uint64_t) (ptr[i + 2]); + mac = (mac << 8) | (uint64_t)ptr[i]; gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); @@ -421,17 +412,17 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface), - ptr[2]); + ptr[0]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface), - ptr[3]); + ptr[1]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface), - ptr[4]); + ptr[2]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface), - ptr[5]); + ptr[3]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface), - ptr[6]); + ptr[4]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface), - ptr[7]); + ptr[5]); cvm_oct_common_set_multicast_list(dev); cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); @@ -439,6 +430,15 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) return 0; } +static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) +{ + int r = eth_mac_addr(dev, addr); + + if (r) + return r; + return cvm_oct_set_mac_filter(dev); +} + /** * cvm_oct_common_init - per network device initialization * @dev: Device to initialize @@ -448,26 +448,17 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) int cvm_oct_common_init(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); - struct sockaddr sa; - u64 mac = ((u64)(octeon_bootinfo->mac_addr_base[0] & 0xff) << 40) | - ((u64)(octeon_bootinfo->mac_addr_base[1] & 0xff) << 32) | - ((u64)(octeon_bootinfo->mac_addr_base[2] & 0xff) << 24) | - ((u64)(octeon_bootinfo->mac_addr_base[3] & 0xff) << 16) | - ((u64)(octeon_bootinfo->mac_addr_base[4] & 0xff) << 8) | - (u64)(octeon_bootinfo->mac_addr_base[5] & 0xff); - - mac += cvm_oct_mac_addr_offset; - sa.sa_data[0] = (mac >> 40) & 0xff; - sa.sa_data[1] = (mac >> 32) & 0xff; - sa.sa_data[2] = (mac >> 24) & 0xff; - sa.sa_data[3] = (mac >> 16) & 0xff; - sa.sa_data[4] = (mac >> 8) & 0xff; - sa.sa_data[5] = mac & 0xff; - - if (cvm_oct_mac_addr_offset >= octeon_bootinfo->mac_addr_count) - printk(KERN_DEBUG "%s: Using MAC outside of the assigned range:" - " %pM\n", dev->name, sa.sa_data); - cvm_oct_mac_addr_offset++; + const u8 *mac = NULL; + + if (priv->of_node) + mac = of_get_mac_address(priv->of_node); + + if (mac && is_valid_ether_addr(mac)) { + memcpy(dev->dev_addr, mac, ETH_ALEN); + dev->addr_assign_type &= ~NET_ADDR_RANDOM; + } else { + eth_hw_addr_random(dev); + } /* * Force the interface to use the POW send if always_use_pow @@ -488,7 +479,7 @@ int cvm_oct_common_init(struct net_device *dev) SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops); cvm_oct_phy_setup_device(dev); - dev->netdev_ops->ndo_set_mac_address(dev, &sa); + cvm_oct_set_mac_filter(dev); dev->netdev_ops->ndo_change_mtu(dev, dev->mtu); /* @@ -595,22 +586,55 @@ static const struct net_device_ops cvm_oct_pow_netdev_ops = { extern void octeon_mdiobus_force_mod_depencency(void); -static int __init cvm_oct_init_module(void) +static struct device_node * __devinit cvm_oct_of_get_child(const struct device_node *parent, + int reg_val) +{ + struct device_node *node = NULL; + int size; + const __be32 *addr; + + for (;;) { + node = of_get_next_child(parent, node); + if (!node) + break; + addr = of_get_property(node, "reg", &size); + if (addr && (be32_to_cpu(*addr) == reg_val)) + break; + } + return node; +} + +static struct device_node * __devinit cvm_oct_node_for_port(struct device_node *pip, + int interface, int port) +{ + struct device_node *ni, *np; + + ni = cvm_oct_of_get_child(pip, interface); + if (!ni) + return NULL; + + np = cvm_oct_of_get_child(ni, port); + of_node_put(ni); + + return np; +} + +static int __devinit cvm_oct_probe(struct platform_device *pdev) { int num_interfaces; int interface; int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; int qos; + struct device_node *pip; octeon_mdiobus_force_mod_depencency(); pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); - if (OCTEON_IS_MODEL(OCTEON_CN52XX)) - cvm_oct_mac_addr_offset = 2; /* First two are the mgmt ports. */ - else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) - cvm_oct_mac_addr_offset = 1; /* First one is the mgmt port. */ - else - cvm_oct_mac_addr_offset = 0; + pip = pdev->dev.of_node; + if (!pip) { + pr_err("Error: No 'pip' in /aliases\n"); + return -EINVAL; + } cvm_oct_poll_queue = create_singlethread_workqueue("octeon-ethernet"); if (cvm_oct_poll_queue == NULL) { @@ -689,10 +713,11 @@ static int __init cvm_oct_init_module(void) cvmx_helper_interface_get_mode(interface); int num_ports = cvmx_helper_ports_on_interface(interface); int port; + int port_index; - for (port = cvmx_helper_get_ipd_port(interface, 0); + for (port_index = 0, port = cvmx_helper_get_ipd_port(interface, 0); port < cvmx_helper_get_ipd_port(interface, num_ports); - port++) { + port_index++, port++) { struct octeon_ethernet *priv; struct net_device *dev = alloc_etherdev(sizeof(struct octeon_ethernet)); @@ -703,6 +728,7 @@ static int __init cvm_oct_init_module(void) /* Initialize the device private structure. */ priv = netdev_priv(dev); + priv->of_node = cvm_oct_node_for_port(pip, interface, port_index); INIT_DELAYED_WORK(&priv->port_periodic_work, cvm_oct_periodic_worker); @@ -787,7 +813,7 @@ static int __init cvm_oct_init_module(void) return 0; } -static void __exit cvm_oct_cleanup_module(void) +static int __devexit cvm_oct_remove(struct platform_device *pdev) { int port; @@ -835,10 +861,29 @@ static void __exit cvm_oct_cleanup_module(void) if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL) cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL, CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128); + return 0; } +static struct of_device_id cvm_oct_match[] = { + { + .compatible = "cavium,octeon-3860-pip", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, cvm_oct_match); + +static struct platform_driver cvm_oct_driver = { + .probe = cvm_oct_probe, + .remove = __devexit_p(cvm_oct_remove), + .driver = { + .owner = THIS_MODULE, + .name = KBUILD_MODNAME, + .of_match_table = cvm_oct_match, + }, +}; + +module_platform_driver(cvm_oct_driver); + MODULE_LICENSE("GPL"); MODULE_AUTHOR("Cavium Networks "); MODULE_DESCRIPTION("Cavium Networks Octeon ethernet driver."); -module_init(cvm_oct_init_module); -module_exit(cvm_oct_cleanup_module); diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h index d581925..9360e22 100644 --- a/drivers/staging/octeon/octeon-ethernet.h +++ b/drivers/staging/octeon/octeon-ethernet.h @@ -31,6 +31,8 @@ #ifndef OCTEON_ETHERNET_H #define OCTEON_ETHERNET_H +#include + /** * This is the definition of the Ethernet driver's private * driver state stored in netdev_priv(dev). @@ -59,6 +61,7 @@ struct octeon_ethernet { void (*poll) (struct net_device *dev); struct delayed_work port_periodic_work; struct work_struct port_work; /* may be unused. */ + struct device_node *of_node; }; int cvm_oct_free_work(void *work_queue_entry); -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 01:28:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 01:30:34 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:65364 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903745Ab2FFX2r (ORCPT ); Thu, 7 Jun 2012 01:28:47 +0200 Received: by dadm1 with SMTP id m1so8217dad.36 for ; Wed, 06 Jun 2012 16:28:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=hYzmn/lg6zEaTJ+EEmzo2r4qgpGCRPzAVPa9Wisq/KA=; b=b8a7gbfI2itWHOzzgbD8pmYlkQ/MjeX9rwxWePhytIXIKdC7fTNvYuxQ8fgpFPhG8P k7paYdjN11Rjp7zO9zcUgEQf228kIne7YE61ms+DmruHI4x+zYdGjtJAwdKhkIeK79k6 1hrTo0R6DIDhU/sVjxJcpv62mQ1iBuoXFWXUQ1HBg4dlV9L5/LD1c1XTBFjP6ToMvcbC QiDe/K9cTYo14JkJLI3YvYKEbK5D904PXcdXkXMaK00UYRuWM6+nePr10UoCCAyrAs3e 3dnOssgt8IAVm94+XTpKH4VsFsRL315F0HYVnVWvbiuMHhxX5azjKNBNw5cUENCNpMMy t87w== Received: by 10.68.116.203 with SMTP id jy11mr1336116pbb.129.1339025320787; Wed, 06 Jun 2012 16:28:40 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id vp4sm1887104pbc.61.2012.06.06.16.28.38 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 16:28:38 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56NSbR3024266; Wed, 6 Jun 2012 16:28:37 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56NSbI0024265; Wed, 6 Jun 2012 16:28:37 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v3 3/5] netdev: octeon_mgmt: Convert to use device tree. Date: Wed, 6 Jun 2012 16:28:32 -0700 Message-Id: <1339025314-24216-4-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> References: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33591 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 26560 Lines: 803 From: David Daney The device tree will supply the register bank base addresses, make register addressing relative to those. PHY connection is now described by the device tree. The OCTEON_IRQ_MII{0,1} symbols are also removed as they are now unused and interfere with the irq_domain used for device tree irq mapping. Acked-by: David S. Miller Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 2 - arch/mips/cavium-octeon/octeon-platform.c | 62 ------ drivers/net/ethernet/octeon/octeon_mgmt.c | 312 +++++++++++++++++++---------- 3 files changed, 207 insertions(+), 169 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 2a661ad..5fb76aa 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -1197,7 +1197,6 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip, handle_edge_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); /* CIU_1 */ @@ -1206,7 +1205,6 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); if (gpio_node) { diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 66cabc2..0938df1 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -168,68 +168,6 @@ out: } device_initcall(octeon_rng_device_init); -/* Octeon mgmt port Ethernet interface. */ -static int __init octeon_mgmt_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - int port, num_ports; - - struct resource mgmt_port_resource = { - .flags = IORESOURCE_IRQ, - .start = -1, - .end = -1 - }; - - if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX)) - return 0; - - if (OCTEON_IS_MODEL(OCTEON_CN56XX)) - num_ports = 1; - else - num_ports = 2; - - for (port = 0; port < num_ports; port++) { - pd = platform_device_alloc("octeon_mgmt", port); - if (!pd) { - ret = -ENOMEM; - goto out; - } - /* No DMA restrictions */ - pd->dev.coherent_dma_mask = DMA_BIT_MASK(64); - pd->dev.dma_mask = &pd->dev.coherent_dma_mask; - - switch (port) { - case 0: - mgmt_port_resource.start = OCTEON_IRQ_MII0; - break; - case 1: - mgmt_port_resource.start = OCTEON_IRQ_MII1; - break; - default: - BUG(); - } - mgmt_port_resource.end = mgmt_port_resource.start; - - ret = platform_device_add_resources(pd, &mgmt_port_resource, 1); - - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - } - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mgmt_device_init); - #ifdef CONFIG_USB static int __init octeon_ehci_device_init(void) diff --git a/drivers/net/ethernet/octeon/octeon_mgmt.c b/drivers/net/ethernet/octeon/octeon_mgmt.c index cd827ff..c42bbb1 100644 --- a/drivers/net/ethernet/octeon/octeon_mgmt.c +++ b/drivers/net/ethernet/octeon/octeon_mgmt.c @@ -6,19 +6,21 @@ * Copyright (C) 2009 Cavium Networks */ -#include +#include #include -#include -#include +#include +#include #include -#include #include -#include -#include +#include #include +#include +#include +#include +#include #include #include -#include +#include #include #include @@ -58,8 +60,56 @@ union mgmt_port_ring_entry { } s; }; +#define MIX_ORING1 0x0 +#define MIX_ORING2 0x8 +#define MIX_IRING1 0x10 +#define MIX_IRING2 0x18 +#define MIX_CTL 0x20 +#define MIX_IRHWM 0x28 +#define MIX_IRCNT 0x30 +#define MIX_ORHWM 0x38 +#define MIX_ORCNT 0x40 +#define MIX_ISR 0x48 +#define MIX_INTENA 0x50 +#define MIX_REMCNT 0x58 +#define MIX_BIST 0x78 + +#define AGL_GMX_PRT_CFG 0x10 +#define AGL_GMX_RX_FRM_CTL 0x18 +#define AGL_GMX_RX_FRM_MAX 0x30 +#define AGL_GMX_RX_JABBER 0x38 +#define AGL_GMX_RX_STATS_CTL 0x50 + +#define AGL_GMX_RX_STATS_PKTS_DRP 0xb0 +#define AGL_GMX_RX_STATS_OCTS_DRP 0xb8 +#define AGL_GMX_RX_STATS_PKTS_BAD 0xc0 + +#define AGL_GMX_RX_ADR_CTL 0x100 +#define AGL_GMX_RX_ADR_CAM_EN 0x108 +#define AGL_GMX_RX_ADR_CAM0 0x180 +#define AGL_GMX_RX_ADR_CAM1 0x188 +#define AGL_GMX_RX_ADR_CAM2 0x190 +#define AGL_GMX_RX_ADR_CAM3 0x198 +#define AGL_GMX_RX_ADR_CAM4 0x1a0 +#define AGL_GMX_RX_ADR_CAM5 0x1a8 + +#define AGL_GMX_TX_STATS_CTL 0x268 +#define AGL_GMX_TX_CTL 0x270 +#define AGL_GMX_TX_STAT0 0x280 +#define AGL_GMX_TX_STAT1 0x288 +#define AGL_GMX_TX_STAT2 0x290 +#define AGL_GMX_TX_STAT3 0x298 +#define AGL_GMX_TX_STAT4 0x2a0 +#define AGL_GMX_TX_STAT5 0x2a8 +#define AGL_GMX_TX_STAT6 0x2b0 +#define AGL_GMX_TX_STAT7 0x2b8 +#define AGL_GMX_TX_STAT8 0x2c0 +#define AGL_GMX_TX_STAT9 0x2c8 + struct octeon_mgmt { struct net_device *netdev; + u64 mix; + u64 agl; int port; int irq; u64 *tx_ring; @@ -85,31 +135,34 @@ struct octeon_mgmt { struct napi_struct napi; struct tasklet_struct tx_clean_tasklet; struct phy_device *phydev; + struct device_node *phy_np; + resource_size_t mix_phys; + resource_size_t mix_size; + resource_size_t agl_phys; + resource_size_t agl_size; }; static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) { - int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); + mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); mix_intena.s.ithena = enable ? 1 : 0; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) { - int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); + mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); mix_intena.s.othena = enable ? 1 : 0; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -146,7 +199,6 @@ static unsigned int ring_size_to_bytes(unsigned int ring_size) static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) { unsigned int size; @@ -177,24 +229,23 @@ static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE; p->rx_current_fill++; /* Ring the bell. */ - cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); + cvmx_write_csr(p->mix + MIX_IRING2, 1); } } static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) { - int port = p->port; union cvmx_mixx_orcnt mix_orcnt; union mgmt_port_ring_entry re; struct sk_buff *skb; int cleaned = 0; unsigned long flags; - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); while (mix_orcnt.s.orcnt) { spin_lock_irqsave(&p->tx_list.lock, flags); - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); if (mix_orcnt.s.orcnt == 0) { spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -214,7 +265,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) mix_orcnt.s.orcnt = 1; /* Acknowledge to hardware that we have the buffer. */ - cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64); + cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64); p->tx_current_fill--; spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -224,7 +275,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) dev_kfree_skb_any(skb); cleaned++; - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); } if (cleaned && netif_queue_stopped(p->netdev)) @@ -241,13 +292,12 @@ static void octeon_mgmt_clean_tx_tasklet(unsigned long arg) static void octeon_mgmt_update_rx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; unsigned long flags; u64 drop, bad; /* These reads also clear the count registers. */ - drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port)); - bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port)); + drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP); + bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD); if (drop || bad) { /* Do an atomic update. */ @@ -261,15 +311,14 @@ static void octeon_mgmt_update_rx_stats(struct net_device *netdev) static void octeon_mgmt_update_tx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; unsigned long flags; union cvmx_agl_gmx_txx_stat0 s0; union cvmx_agl_gmx_txx_stat1 s1; /* These reads also clear the count registers. */ - s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port)); - s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port)); + s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0); + s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1); if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) { /* Do an atomic update. */ @@ -308,7 +357,6 @@ static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p, static int octeon_mgmt_receive_one(struct octeon_mgmt *p) { - int port = p->port; struct net_device *netdev = p->netdev; union cvmx_mixx_ircnt mix_ircnt; union mgmt_port_ring_entry re; @@ -381,18 +429,17 @@ done: /* Tell the hardware we processed a packet. */ mix_ircnt.u64 = 0; mix_ircnt.s.ircnt = 1; - cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64); + cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64); return rc; } static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) { - int port = p->port; unsigned int work_done = 0; union cvmx_mixx_ircnt mix_ircnt; int rc; - mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); + mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); while (work_done < budget && mix_ircnt.s.ircnt) { rc = octeon_mgmt_receive_one(p); @@ -400,7 +447,7 @@ static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) work_done++; /* Check for more packets. */ - mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); + mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); } octeon_mgmt_rx_fill_ring(p->netdev); @@ -434,16 +481,16 @@ static void octeon_mgmt_reset_hw(struct octeon_mgmt *p) union cvmx_agl_gmx_bist agl_gmx_bist; mix_ctl.u64 = 0; - cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); } while (mix_ctl.s.busy); mix_ctl.s.reset = 1; - cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); - cvmx_read_csr(CVMX_MIXX_CTL(p->port)); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); + cvmx_read_csr(p->mix + MIX_CTL); cvmx_wait(64); - mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port)); + mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); if (mix_bist.u64) dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n", (unsigned long long)mix_bist.u64); @@ -474,7 +521,6 @@ static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs, static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_agl_gmx_rxx_adr_ctl adr_ctl; union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx; unsigned long flags; @@ -520,29 +566,29 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) spin_lock_irqsave(&p->lock, flags); /* Disable packet I/O. */ - agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prev_packet_enable = agl_gmx_prtx.s.en; agl_gmx_prtx.s.en = 0; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); adr_ctl.u64 = 0; adr_ctl.s.cam_mode = cam_mode; adr_ctl.s.mcst = multicast_mode; adr_ctl.s.bcst = 1; /* Allow broadcast */ - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask); /* Restore packet I/O. */ agl_gmx_prtx.s.en = prev_packet_enable; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -564,7 +610,6 @@ static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr) static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM; /* @@ -580,8 +625,8 @@ static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) netdev->mtu = new_mtu; - cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs); - cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port), + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, size_without_fcs); + cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER, (size_without_fcs + 7) & 0xfff8); return 0; @@ -591,14 +636,13 @@ static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id) { struct net_device *netdev = dev_id; struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_mixx_isr mixx_isr; - mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port)); + mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR); /* Clear any pending interrupts */ - cvmx_write_csr(CVMX_MIXX_ISR(port), mixx_isr.u64); - cvmx_read_csr(CVMX_MIXX_ISR(port)); + cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64); + cvmx_read_csr(p->mix + MIX_ISR); if (mixx_isr.s.irthresh) { octeon_mgmt_disable_rx_irq(p); @@ -629,7 +673,6 @@ static int octeon_mgmt_ioctl(struct net_device *netdev, static void octeon_mgmt_adjust_link(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_agl_gmx_prtx_cfg prtx_cfg; unsigned long flags; int link_changed = 0; @@ -640,11 +683,9 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) link_changed = 1; if (p->last_duplex != p->phydev->duplex) { p->last_duplex = p->phydev->duplex; - prtx_cfg.u64 = - cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.duplex = p->phydev->duplex; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), - prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); } } else { if (p->last_link) @@ -670,18 +711,16 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) static int octeon_mgmt_init_phy(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - char phy_id[MII_BUS_ID_SIZE + 3]; - if (octeon_is_simulation()) { + if (octeon_is_simulation() || p->phy_np == NULL) { /* No PHYs in the simulator. */ netif_carrier_on(netdev); return 0; } - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", p->port); - - p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0, - PHY_INTERFACE_MODE_MII); + p->phydev = of_phy_connect(netdev, p->phy_np, + octeon_mgmt_adjust_link, 0, + PHY_INTERFACE_MODE_MII); if (IS_ERR(p->phydev)) { p->phydev = NULL; @@ -737,14 +776,14 @@ static int octeon_mgmt_open(struct net_device *netdev) octeon_mgmt_reset_hw(p); - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); /* Bring it out of reset if needed. */ if (mix_ctl.s.reset) { mix_ctl.s.reset = 0; - cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); } while (mix_ctl.s.reset); } @@ -755,17 +794,17 @@ static int octeon_mgmt_open(struct net_device *netdev) oring1.u64 = 0; oring1.s.obase = p->tx_ring_handle >> 3; oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE; - cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64); + cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64); iring1.u64 = 0; iring1.s.ibase = p->rx_ring_handle >> 3; iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; - cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64); + cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); /* Disable packet I/O. */ - prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.en = 0; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); octeon_mgmt_set_mac_address(netdev, &sa); @@ -782,7 +821,7 @@ static int octeon_mgmt_open(struct net_device *netdev) mix_ctl.s.nbtarb = 0; /* Arbitration mode */ /* MII CB-request FIFO programmable high watermark */ mix_ctl.s.mrq_hwm = 1; - cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { @@ -809,16 +848,16 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Clear statistics. */ /* Clear on read. */ - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1); - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0); - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0); + cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1); + cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0); + cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0); /* Clear any pending interrupts */ - cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port))); + cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR)); if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name, netdev)) { @@ -829,18 +868,18 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Interrupt every single RX packet */ mix_irhwm.u64 = 0; mix_irhwm.s.irhwm = 0; - cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64); + cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64); /* Interrupt when we have 1 or more packets to clean. */ mix_orhwm.u64 = 0; mix_orhwm.s.orhwm = 1; - cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64); + cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); /* Enable receive and transmit interrupts */ mix_intena.u64 = 0; mix_intena.s.ithena = 1; mix_intena.s.othena = 1; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); /* Enable packet I/O. */ @@ -871,7 +910,7 @@ static int octeon_mgmt_open(struct net_device *netdev) * frame. GMX checks that the PREAMBLE is sent correctly. */ rxx_frm_ctl.s.pre_chk = 1; - cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64); + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); /* Enable the AGL block */ agl_gmx_inf_mode.u64 = 0; @@ -879,13 +918,13 @@ static int octeon_mgmt_open(struct net_device *netdev) cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); /* Configure the port duplex and enables */ - prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.tx_en = 1; prtx_cfg.s.rx_en = 1; prtx_cfg.s.en = 1; p->last_duplex = 1; prtx_cfg.s.duplex = p->last_duplex; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); p->last_link = 0; netif_carrier_off(netdev); @@ -949,7 +988,6 @@ static int octeon_mgmt_stop(struct net_device *netdev) static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union mgmt_port_ring_entry re; unsigned long flags; int rv = NETDEV_TX_BUSY; @@ -993,7 +1031,7 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) netdev->stats.tx_bytes += skb->len; /* Ring the bell. */ - cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); + cvmx_write_csr(p->mix + MIX_ORING2, 1); rv = NETDEV_TX_OK; out: @@ -1071,10 +1109,14 @@ static const struct net_device_ops octeon_mgmt_ops = { static int __devinit octeon_mgmt_probe(struct platform_device *pdev) { - struct resource *res_irq; struct net_device *netdev; struct octeon_mgmt *p; - int i; + const __be32 *data; + const u8 *mac; + struct resource *res_mix; + struct resource *res_agl; + int len; + int result; netdev = alloc_etherdev(sizeof(struct octeon_mgmt)); if (netdev == NULL) @@ -1088,14 +1130,63 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) p->netdev = netdev; p->dev = &pdev->dev; - p->port = pdev->id; + data = of_get_property(pdev->dev.of_node, "cell-index", &len); + if (data && len == sizeof(*data)) { + p->port = be32_to_cpup(data); + } else { + dev_err(&pdev->dev, "no 'cell-index' property\n"); + result = -ENXIO; + goto err; + } + snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port); - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_irq) + result = platform_get_irq(pdev, 0); + if (result < 0) + goto err; + + p->irq = result; + + res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res_mix == NULL) { + dev_err(&pdev->dev, "no 'reg' resource\n"); + result = -ENXIO; + goto err; + } + + res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res_agl == NULL) { + dev_err(&pdev->dev, "no 'reg' resource\n"); + result = -ENXIO; + goto err; + } + + p->mix_phys = res_mix->start; + p->mix_size = resource_size(res_mix); + p->agl_phys = res_agl->start; + p->agl_size = resource_size(res_agl); + + + if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size, + res_mix->name)) { + dev_err(&pdev->dev, "request_mem_region (%s) failed\n", + res_mix->name); + result = -ENXIO; + goto err; + } + + if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size, + res_agl->name)) { + result = -ENXIO; + dev_err(&pdev->dev, "request_mem_region (%s) failed\n", + res_agl->name); goto err; + } + + + p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size); + p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size); - p->irq = res_irq->start; spin_lock_init(&p->lock); skb_queue_head_init(&p->tx_list); @@ -1108,24 +1199,26 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) netdev->netdev_ops = &octeon_mgmt_ops; netdev->ethtool_ops = &octeon_mgmt_ethtool_ops; - /* The mgmt ports get the first N MACs. */ - for (i = 0; i < 6; i++) - netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i]; - netdev->dev_addr[5] += p->port; + mac = of_get_mac_address(pdev->dev.of_node); + + if (mac) + memcpy(netdev->dev_addr, mac, 6); - if (p->port >= octeon_bootinfo->mac_addr_count) - dev_err(&pdev->dev, - "Error %s: Using MAC outside of the assigned range: %pM\n", - netdev->name, netdev->dev_addr); + p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); - if (register_netdev(netdev)) + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + + result = register_netdev(netdev); + if (result) goto err; dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); return 0; + err: free_netdev(netdev); - return -ENOENT; + return result; } static int __devexit octeon_mgmt_remove(struct platform_device *pdev) @@ -1137,10 +1230,19 @@ static int __devexit octeon_mgmt_remove(struct platform_device *pdev) return 0; } +static struct of_device_id octeon_mgmt_match[] = { + { + .compatible = "cavium,octeon-5750-mix", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_mgmt_match); + static struct platform_driver octeon_mgmt_driver = { .driver = { .name = "octeon_mgmt", .owner = THIS_MODULE, + .of_match_table = octeon_mgmt_match, }, .probe = octeon_mgmt_probe, .remove = __devexit_p(octeon_mgmt_remove), -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 01:28:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 01:31:00 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:44113 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903747Ab2FFX2r (ORCPT ); Thu, 7 Jun 2012 01:28:47 +0200 Received: by pbbrq13 with SMTP id rq13so206414pbb.36 for ; Wed, 06 Jun 2012 16:28:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=SZZVlLSj60x8uq0mAGO2woz48nxDlwTMVq722ZLXCW4=; b=wdUseToPCptFqetHrzq549bGT2u0lOlyTHh6+gl1clB94JB2mMyL13ZjKMa+XIf3HJ 2pu+Kzfc7gKK7FjdoBd7ONJQWVu/WHsc9JQD4/2MMQRym6BcVCzTY+bQJrfHaI2XYhu+ z47/kZQCi0Qnn3lUWU8kSpeXO2YEOTUrd84WbO3zgmmYaGbTXpBEha0SHJk1nQqnKoT/ e7YBDA215l+PFNdjlf7qpvrdl3s8EyHYOWuTJKQMzbjkIE3ORo5i7rNjqHt3PCWvBD4o lb+9tyvthHq3/gjuLzlFKR0cyErX4BqM5I/Npia92Rnwnx3UOf9tqwpAFMLRBLo4f2h1 47WA== Received: by 10.68.222.165 with SMTP id qn5mr2974849pbc.14.1339025321132; Wed, 06 Jun 2012 16:28:41 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id hb5sm1887852pbc.58.2012.06.06.16.28.38 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 16:28:39 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q56NSbX6024274; Wed, 6 Jun 2012 16:28:37 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q56NSbMO024273; Wed, 6 Jun 2012 16:28:37 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v3 5/5] MIPS: Octeon: Use device tree to register serial ports. Date: Wed, 6 Jun 2012 16:28:34 -0700 Message-Id: <1339025314-24216-6-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> References: <1339025314-24216-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33592 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6410 Lines: 200 From: David Daney Switch to using the device tree to register serial ports. Add all the ports with compatible = "cavium,octeon-3860-uart". Octeon serial ports have their own device type, required port flags, and I/O functions, so using of_serial.c is not indicated. We need to do this as late_initcall, as the 8250 driver must be initialized before we add any ports. 8250 initialization is done at device_initcall time. The OCTEON_IRQ_UART{0,1,2} symbols are removed as they are now unused and interfere with irq_domain used by the device tree code. Signed-off-by: David Daney Acked-by: Grant Likely --- arch/mips/cavium-octeon/octeon-irq.c | 4 - arch/mips/cavium-octeon/serial.c | 134 +++++++++++++-------------------- 2 files changed, 53 insertions(+), 85 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 5fb76aa..7fb1f22 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -1184,9 +1184,6 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq); - for (i = 0; i < 4; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); for (i = 0; i < 4; i++) @@ -1203,7 +1200,6 @@ static void __init octeon_irq_init_ciu(void) for (i = 0; i < 16; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c index 057f0ae..138b221 100644 --- a/arch/mips/cavium-octeon/serial.c +++ b/arch/mips/cavium-octeon/serial.c @@ -43,95 +43,67 @@ void octeon_serial_out(struct uart_port *up, int offset, int value) cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value); } -/* - * Allocated in .bss, so it is all zeroed. - */ -#define OCTEON_MAX_UARTS 3 -static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1]; -static struct platform_device octeon_uart8250_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = octeon_uart8250_data, - }, -}; - -static void __init octeon_uart_set_common(struct plat_serial8250_port *p) +static int __devinit octeon_serial_probe(struct platform_device *pdev) { - p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; - p->type = PORT_OCTEON; - p->iotype = UPIO_MEM; - p->regshift = 3; /* I/O addresses are every 8 bytes */ + int irq, res; + struct resource *res_mem; + struct uart_port port; + + /* All adaptors have an irq. */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + memset(&port, 0, sizeof(port)); + + port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; + port.type = PORT_OCTEON; + port.iotype = UPIO_MEM; + port.regshift = 3; + port.dev = &pdev->dev; + if (octeon_is_simulation()) /* Make simulator output fast*/ - p->uartclk = 115200 * 16; + port.uartclk = 115200 * 16; else - p->uartclk = octeon_get_io_clock_rate(); - p->serial_in = octeon_serial_in; - p->serial_out = octeon_serial_out; -} + port.uartclk = octeon_get_io_clock_rate(); -static int __init octeon_serial_init(void) -{ - int enable_uart0; - int enable_uart1; - int enable_uart2; - struct plat_serial8250_port *p; - -#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL - /* - * If we are configured to run as the second of two kernels, - * disable uart0 and enable uart1. Uart0 is owned by the first - * kernel - */ - enable_uart0 = 0; - enable_uart1 = 1; -#else - /* - * We are configured for the first kernel. We'll enable uart0 - * if the bootloader told us to use 0, otherwise will enable - * uart 1. - */ - enable_uart0 = (octeon_get_boot_uart() == 0); - enable_uart1 = (octeon_get_boot_uart() == 1); -#ifdef CONFIG_KGDB - enable_uart1 = 1; -#endif -#endif - - /* Right now CN52XX is the only chip with a third uart */ - enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX); - - p = octeon_uart8250_data; - if (enable_uart0) { - /* Add a ttyS device for hardware uart 0 */ - octeon_uart_set_common(p); - p->membase = (void *) CVMX_MIO_UARTX_RBR(0); - p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1); - p->irq = OCTEON_IRQ_UART0; - p++; - } + port.serial_in = octeon_serial_in; + port.serial_out = octeon_serial_out; + port.irq = irq; - if (enable_uart1) { - /* Add a ttyS device for hardware uart 1 */ - octeon_uart_set_common(p); - p->membase = (void *) CVMX_MIO_UARTX_RBR(1); - p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1); - p->irq = OCTEON_IRQ_UART1; - p++; - } - if (enable_uart2) { - /* Add a ttyS device for hardware uart 2 */ - octeon_uart_set_common(p); - p->membase = (void *) CVMX_MIO_UART2_RBR; - p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1); - p->irq = OCTEON_IRQ_UART2; - p++; + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res_mem == NULL) { + dev_err(&pdev->dev, "found no memory resource\n"); + return -ENXIO; } + port.mapbase = res_mem->start; + port.membase = ioremap(res_mem->start, resource_size(res_mem)); - BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]); + res = serial8250_register_port(&port); - return platform_device_register(&octeon_uart8250_device); + return res >= 0 ? 0 : res; } -device_initcall(octeon_serial_init); +static struct of_device_id octeon_serial_match[] = { + { + .compatible = "cavium,octeon-3860-uart", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_serial_match); + +static struct platform_driver octeon_serial_driver = { + .probe = octeon_serial_probe, + .driver = { + .owner = THIS_MODULE, + .name = "octeon_serial", + .of_match_table = octeon_serial_match, + }, +}; + +static int __init octeon_serial_init(void) +{ + return platform_driver_register(&octeon_serial_driver); +} +late_initcall(octeon_serial_init); -- 1.7.2.3 From alex.shi@intel.com Thu Jun 7 02:35:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 02:35:35 +0200 (CEST) Received: from mga11.intel.com ([192.55.52.93]:53197 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903717Ab2FGAfa (ORCPT ); Thu, 7 Jun 2012 02:35:30 +0200 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 06 Jun 2012 17:35:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="175750030" Received: from debian.sh.intel.com (HELO [10.239.13.3]) ([10.239.13.3]) by fmsmga002.fm.intel.com with ESMTP; 06 Jun 2012 17:35:17 -0700 Message-ID: <4FCFF6D8.70507@intel.com> Date: Thu, 07 Jun 2012 08:33:28 +0800 From: Alex Shi User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:9.0) Gecko/20111229 Thunderbird/9.0 MIME-Version: 1.0 To: Peter Zijlstra CC: anton@samba.org, benh@kernel.crashing.org, cmetcalf@tilera.com, dhowells@redhat.com, davem@davemloft.net, fenghua.yu@intel.com, hpa@zytor.com, ink@jurassic.park.msu.ru, linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, mattst88@gmail.com, paulus@samba.org, lethal@linux-sh.org, ralf@linux-mips.org, rth@twiddle.net, sparclinux@vger.kernel.org, tony.luck@intel.com, x86@kernel.org, sivanich@sgi.com, greg.pearson@hp.com, kamezawa.hiroyu@jp.fujitsu.com, bob.picco@oracle.com, chris.mason@oracle.com, torvalds@linux-foundation.org, akpm@linux-foundation.org, mingo@kernel.org, pjt@google.com, tglx@linutronix.de, seto.hidetoshi@jp.fujitsu.com, ak@linux.intel.com, arjan.van.de.ven@intel.com Subject: Re: [RFC PATCH] sched/numa: do load balance between remote nodes References: <1338965571-9812-1-git-send-email-alex.shi@intel.com> <1338973295.2749.81.camel@twins> In-Reply-To: <1338973295.2749.81.camel@twins> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33593 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex.shi@intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 542 Lines: 20 On 06/06/2012 05:01 PM, Peter Zijlstra wrote: > On Wed, 2012-06-06 at 14:52 +0800, Alex Shi wrote: >> - if (sched_domains_numa_distance[level] > REMOTE_DISTANCE) >> + if (sched_domains_numa_distance[level] > RECLAIM_DISTANCE) > > I actually considered this.. I just felt a little uneasy re-purposing > the RECLAIM_DISTANCE for this, but I guess its all the same anyway. Both > mean expensive-away-distance. > I understand you, the BIOS guys don't have a good alignment with us on this. > So I've taken this. > > thanks! From robherring2@gmail.com Thu Jun 7 05:40:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 05:41:00 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:49987 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903544Ab2FGDkx (ORCPT ); Thu, 7 Jun 2012 05:40:53 +0200 Received: by obqv19 with SMTP id v19so310588obq.36 for ; Wed, 06 Jun 2012 20:40:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=fEP+WNGRy32yRZpCUo2CcvyjmFtnMh8pXS/h5u/88ck=; b=yFhcll2E8RFv7vx2UPrIMKuAPG+IxOxKgwTVVI4O04F6jQyMVEJlXwqsNyKfRskTBg Uu9fQq6kMAAg7PfbwObni9p3WyQbL9XzxjILUBLZBqIVNxB1PLmTF7DvP9LeWuZ0+XRa IJ497ZtHY74sj85fobaEvp04/3MuLZF2jw6fEEZJiAq3fmU3NwAIpPXUcA68JB8E9HXk i32J84UD/ax1YZ+tzFLoHix3LRpmR6yumE96VILJ75Ey3WKzLvMkqGzVoaTe1r6zjqT2 403g9nKZ0RFhQ491cHtOMgB9NnNa7Yaw3fxa0EO726fg/EP7gNbmfOXT/SXOMSol1JXK AbzA== Received: by 10.182.48.100 with SMTP id k4mr530860obn.21.1339040447152; Wed, 06 Jun 2012 20:40:47 -0700 (PDT) Received: from [192.168.1.103] (65-36-72-55.dyn.grandenetworks.net. [65.36.72.55]) by mx.google.com with ESMTPS id ie2sm1686393obb.17.2012.06.06.20.40.43 (version=SSLv3 cipher=OTHER); Wed, 06 Jun 2012 20:40:45 -0700 (PDT) Message-ID: <4FD022BA.8090109@gmail.com> Date: Wed, 06 Jun 2012 22:40:42 -0500 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:12.0) Gecko/20120430 Thunderbird/12.0.1 MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring , linux-kernel@vger.kernel.org, David Daney Subject: Re: [PATCH v8 1/1] of/lib: Allow scripts/dtc/libfdt to be used from kernel code References: <1339022972-20036-1-git-send-email-ddaney.cavm@gmail.com> In-Reply-To: <1339022972-20036-1-git-send-email-ddaney.cavm@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33594 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6023 Lines: 193 On 06/06/2012 05:49 PM, David Daney wrote: > From: David Daney > > libfdt is part of the device tree support in scripts/dtc/libfdt. For > some platforms that use the Device Tree, we want to be able to edit > the flattened device tree form. > > We don't want to burden kernel builds that do not require it, so we > gate compilation of libfdt files with CONFIG_LIBFDT. So if it is > needed, you need to do this in your Kconfig: > > select LIBFDT > > And in the Makefile of the code using libfdt something like: > > ccflags-y := -I$(src)/../../../scripts/dtc/libfdt > > Signed-off-by: David Daney Looks like you've addressed all of Grant's prior comments and looks okay to me. I'd merge it with the rest of patches thru the MIPS tree. Acked-by: Rob Herring > --- > This patch has been seen several times before as part of a larger > patch set for my OCTEON Device Tree work. After further refinement to > my patches that depend on core Device Tree functionality, this is the > only remaining patch to the common 'core' code. > > Here is the history: > > v8: Rebased lib/Makefile to avoid merge conflict. > > v7: No changes other that to split from other, now unneeded, patches. > > v6: No changes other than to split these out of the MIPS/OCTEON patch > set to allow them to be merged separately if desired. > > v5: Build libfdt in the lib directory instead of devices/of, and > include all libfdt files. > > Changes to of_find_node_by_path() requested by Grant Likely. > > v4: No changes to these two patches. > > v3: libfdt building moved to devices/of/libfdt. Cleanup and style > improvements as suggested by Grant Likely. > > v2: No changes to these two patches. > > There are a couple of possibility for merging this. > > 1) Via the Device Tree maintainers, thus blocking the follow-ons until > it is merged. > > 2) Via Ralf's Linux/MIPS tree with the rest of the patches after > Device Tree maintainer sign-off. > > include/linux/libfdt.h | 8 ++++++++ > include/linux/libfdt_env.h | 13 +++++++++++++ > lib/Kconfig | 6 ++++++ > lib/Makefile | 5 +++++ > lib/fdt.c | 2 ++ > lib/fdt_ro.c | 2 ++ > lib/fdt_rw.c | 2 ++ > lib/fdt_strerror.c | 2 ++ > lib/fdt_sw.c | 2 ++ > lib/fdt_wip.c | 2 ++ > 10 files changed, 44 insertions(+), 0 deletions(-) > create mode 100644 include/linux/libfdt.h > create mode 100644 include/linux/libfdt_env.h > create mode 100644 lib/fdt.c > create mode 100644 lib/fdt_ro.c > create mode 100644 lib/fdt_rw.c > create mode 100644 lib/fdt_strerror.c > create mode 100644 lib/fdt_sw.c > create mode 100644 lib/fdt_wip.c > > diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h > new file mode 100644 > index 0000000..4c0306c > --- /dev/null > +++ b/include/linux/libfdt.h > @@ -0,0 +1,8 @@ > +#ifndef _INCLUDE_LIBFDT_H_ > +#define _INCLUDE_LIBFDT_H_ > + > +#include > +#include "../../scripts/dtc/libfdt/fdt.h" > +#include "../../scripts/dtc/libfdt/libfdt.h" > + > +#endif /* _INCLUDE_LIBFDT_H_ */ > diff --git a/include/linux/libfdt_env.h b/include/linux/libfdt_env.h > new file mode 100644 > index 0000000..01508c7 > --- /dev/null > +++ b/include/linux/libfdt_env.h > @@ -0,0 +1,13 @@ > +#ifndef _LIBFDT_ENV_H > +#define _LIBFDT_ENV_H > + > +#include > + > +#include > + > +#define fdt32_to_cpu(x) be32_to_cpu(x) > +#define cpu_to_fdt32(x) cpu_to_be32(x) > +#define fdt64_to_cpu(x) be64_to_cpu(x) > +#define cpu_to_fdt64(x) cpu_to_be64(x) > + > +#endif /* _LIBFDT_ENV_H */ > diff --git a/lib/Kconfig b/lib/Kconfig > index a9e1540..e091300 100644 > --- a/lib/Kconfig > +++ b/lib/Kconfig > @@ -395,4 +395,10 @@ config SIGNATURE > Digital signature verification. Currently only RSA is supported. > Implementation is done using GnuPG MPI library > > +# > +# libfdt files, only selected if needed. > +# > +config LIBFDT > + bool > + > endmenu > diff --git a/lib/Makefile b/lib/Makefile > index 8c31a0c..2f2be5a 100644 > --- a/lib/Makefile > +++ b/lib/Makefile > @@ -130,6 +130,11 @@ obj-$(CONFIG_GENERIC_STRNLEN_USER) += strnlen_user.o > > obj-$(CONFIG_STMP_DEVICE) += stmp_device.o > > +libfdt_files = fdt.o fdt_ro.o fdt_wip.o fdt_rw.o fdt_sw.o fdt_strerror.o > +$(foreach file, $(libfdt_files), \ > + $(eval CFLAGS_$(file) = -I$(src)/../scripts/dtc/libfdt)) > +lib-$(CONFIG_LIBFDT) += $(libfdt_files) > + > hostprogs-y := gen_crc32table > clean-files := crc32table.h > > diff --git a/lib/fdt.c b/lib/fdt.c > new file mode 100644 > index 0000000..97f2006 > --- /dev/null > +++ b/lib/fdt.c > @@ -0,0 +1,2 @@ > +#include > +#include "../scripts/dtc/libfdt/fdt.c" > diff --git a/lib/fdt_ro.c b/lib/fdt_ro.c > new file mode 100644 > index 0000000..f73c04e > --- /dev/null > +++ b/lib/fdt_ro.c > @@ -0,0 +1,2 @@ > +#include > +#include "../scripts/dtc/libfdt/fdt_ro.c" > diff --git a/lib/fdt_rw.c b/lib/fdt_rw.c > new file mode 100644 > index 0000000..0c1f0f4 > --- /dev/null > +++ b/lib/fdt_rw.c > @@ -0,0 +1,2 @@ > +#include > +#include "../scripts/dtc/libfdt/fdt_rw.c" > diff --git a/lib/fdt_strerror.c b/lib/fdt_strerror.c > new file mode 100644 > index 0000000..8713e3f > --- /dev/null > +++ b/lib/fdt_strerror.c > @@ -0,0 +1,2 @@ > +#include > +#include "../scripts/dtc/libfdt/fdt_strerror.c" > diff --git a/lib/fdt_sw.c b/lib/fdt_sw.c > new file mode 100644 > index 0000000..9ac7e50 > --- /dev/null > +++ b/lib/fdt_sw.c > @@ -0,0 +1,2 @@ > +#include > +#include "../scripts/dtc/libfdt/fdt_sw.c" > diff --git a/lib/fdt_wip.c b/lib/fdt_wip.c > new file mode 100644 > index 0000000..45b3fc3 > --- /dev/null > +++ b/lib/fdt_wip.c > @@ -0,0 +1,2 @@ > +#include > +#include "../scripts/dtc/libfdt/fdt_wip.c" From pjohn@mvista.com Thu Jun 7 10:14:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 10:14:19 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:38784 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903730Ab2FGION (ORCPT ); Thu, 7 Jun 2012 10:14:13 +0200 Received: by pbbrq13 with SMTP id rq13so748925pbb.36 for ; Thu, 07 Jun 2012 01:14:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding:x-gm-message-state; bh=FRysA/vAd4QdbJphNuobgq47WLUGj03hnFNLQ46zo+s=; b=VhlyiY3cbTazXFWSrVa3Kqf3ndSQhlzq5pOusZF4OdZM0SnaHoVvEPu6AjcLrfpHIy mGQJGNslCvkaNSd73eZG9+YVTv3Aq4zwostpkQ/0piPui6SzLbKh+LzrAUCxbRmjhZy8 TKV1evTG2yZkO0Tp3fnmnfnAje+qYzgoIHCPV61Ci2TbCAS01B5yZ9xHHBcEfB24rzaR 93iAE8ZKK1Po4tpXx2zod8nG0IS2bJMFnuXtiTbPJSqWlZuho/hcj6cffo9fLxzqFnby AiIMwP+G2mJ2cQfiHvYjiVfX41iZijfOY0FFBp8y1+1dpzD+hyXCORGVWT6b0vu2xPS8 TpDQ== Received: by 10.68.222.133 with SMTP id qm5mr5956862pbc.113.1339056846408; Thu, 07 Jun 2012 01:14:06 -0700 (PDT) Received: from [10.0.0.4] ([115.118.107.144]) by mx.google.com with ESMTPS id qp3sm3326439pbc.17.2012.06.07.01.14.02 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jun 2012 01:14:05 -0700 (PDT) Subject: [PATCH 1/2] Octeon 6xxx: Initial commit porting executive files from sdk2.3 From: philby john To: linux-mips@linux-mips.org Cc: david.daney@caviumnetworks.com, ralf@linux-mips.org, prasun.kapoor@caviumnetworks.com Content-Type: text/plain; charset="UTF-8" Date: Thu, 07 Jun 2012 13:45:40 +0530 Message-ID: <1339056940.15045.9.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.32.3 (2.32.3-1.fc14) Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkBnZ/oBUPv/RP9KnZipWibgSC7Kyo4xaZ0iPQnbbX3Oiplt639QUskE35NMvQy2IudoCRo X-archive-position: 33595 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13626 Lines: 442 >From eb9d86c9ac6d23f36f01e6b8b364c3922e550fff Mon Sep 17 00:00:00 2001 From: Philby John Date: Thu, 7 Jun 2012 11:49:32 +0530 Subject: [PATCH] Octeon 6xxx: Initial commit porting executive files from sdk2.3 Initial commit that sets up the internal functions needed for implementing Power Throttling for Octeon 6xxx and above. Additional functionality such as setting throttle feedback cvmx_init_throttle_feedback(), calculating throttle percentage cvmx_power_throttle_get_powlim(), and other bugfixes not present in the SDK have been implemented. Signed-off-by: Philby John --- arch/mips/cavium-octeon/executive/Makefile | 2 +- .../cavium-octeon/executive/cvmx-power-throttle.c | 287 ++++++++++++++++++++ arch/mips/include/asm/octeon/cvmx-power-throttle.h | 103 +++++++ 3 files changed, 391 insertions(+), 1 deletions(-) create mode 100644 arch/mips/cavium-octeon/executive/cvmx-power-throttle.c create mode 100644 arch/mips/include/asm/octeon/cvmx-power-throttle.h diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile index b6d6e84..659cd9e 100644 --- a/arch/mips/cavium-octeon/executive/Makefile +++ b/arch/mips/cavium-octeon/executive/Makefile @@ -14,6 +14,6 @@ obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ - cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o + cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o cvmx-power-throttle.o obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o diff --git a/arch/mips/cavium-octeon/executive/cvmx-power-throttle.c b/arch/mips/cavium-octeon/executive/cvmx-power-throttle.c new file mode 100644 index 0000000..daa7f5a --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-power-throttle.c @@ -0,0 +1,287 @@ +/***********************license start*************** + * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights + * reserved. + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + + * * Neither the name of Cavium Inc. nor the names of + * its contributors may be used to endorse or promote products + * derived from this software without specific prior written + * permission. + + * This Software, including technical data, may be subject to U.S. export + * control laws, including the U.S. Export Administration Act and its + * associated regulations, and may be subject to export or import regulations + * in other countries. + + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" + * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR + * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT + * TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY + * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT + * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) + * WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A + * PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET + * ENJOYMENT QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE + * RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. + ***********************license end**************************************/ + +/** + * @file + * + * Interface to power-throttle control, measurement, and debugging + * facilities. + * + */ + +#include +#include +#include +#include + +#define CVMX_PTH_GET_MASK(len, pos) \ + ((((uint64_t)1 << (len)) - 1) << (pos)) + +#define CVMX_PTH_AVAILABLE \ + (cvmx_power_throttle_get_register(0) != (uint64_t)-1) + +/* + * a field of the POWTHROTTLE register + */ +static struct cvmx_power_throttle_rfield_t { + char name[16]; /* the field's name */ + int32_t pos; /* position of the field's LSb */ + int32_t len; /* the field's length */ + int present; /* 1 for present */ +} cvmx_power_throttle_rfield[] = { + {"MAXPOW", 56, 8, 0}, + {"POWER" , 48, 8, 0}, + {"THROTT", 40, 8, 0}, + {"Reserved", 28, 12, 0}, + {"DISTAG", 27, 1, 0}, + {"PERIOD", 24, 3, 0}, + {"POWLIM", 16, 8, 0}, + {"MAXTHR", 8, 8, 0}, + {"MINTHR", 0, 8, 0}, + {"HRMPOWADJ", 32, 8, 0}, + {"OVRRD", 28, 1, 0} +}; + +static uint64_t cvmx_power_throttle_csr_addr(int ppid); + +static int cvmx_power_throttle_initialized; + +/* + * @INTERNAL + * Initialize cvmx_power_throttle_rfield[] based on model. + */ +static void cvmx_power_throttle_init(void) +{ + /* Turn on the fields for a model */ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + int i; + struct cvmx_power_throttle_rfield_t *p; + + for (i = 0; i < CVMX_PTH_INDEX_MAX; i++) + cvmx_power_throttle_rfield[i].present = 1; + + if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + /* + * These fields do not come with o63 + */ + p = + &cvmx_power_throttle_rfield[CVMX_PTH_INDEX_HRMPOWADJ]; + p->present = 0; + p = &cvmx_power_throttle_rfield[CVMX_PTH_INDEX_OVRRD]; + p->present = 0; + } else { + /* + * The reserved field shrinks in models newer than o63 + */ + p = + &cvmx_power_throttle_rfield[CVMX_PTH_INDEX_RESERVED]; + p->pos = 29; + p->len = 3; + } + } +} + +uint64_t cvmx_power_throttle_get_field(uint64_t r, + enum cvmx_power_throttle_field_index i) +{ + uint64_t m; + struct cvmx_power_throttle_rfield_t *p; + + if (i > CVMX_PTH_INDEX_MAX) + return -EINVAL; + + p = &cvmx_power_throttle_rfield[i]; + if (!p->present) + return (uint64_t) -1; + m = CVMX_PTH_GET_MASK(p->len, p->pos); + + return (r & m) >> p->pos; +} + +/* + * @INTERNAL + * Set the i'th field of power-throttle register r to v. + */ +static int cvmx_power_throttle_set_field(int i, uint64_t r, uint64_t v) +{ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + uint64_t m; + struct cvmx_power_throttle_rfield_t *p; + + if (i > CVMX_PTH_INDEX_MAX) + return -EINVAL; + + p = &cvmx_power_throttle_rfield[i]; + m = CVMX_PTH_GET_MASK(p->len, p->pos); + + return (~m & r) | ((v << p->pos) & m); + } + return 0; +} + +int cvmx_init_throttle_feedback(cpu) +{ + uint64_t csr_addr, r; + + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + csr_addr = cvmx_power_throttle_csr_addr(cpu); + r = cvmx_read_csr(csr_addr); + r = + cvmx_power_throttle_set_field(CVMX_PTH_INDEX_MINTHR, r, 0x0); + cvmx_write_csr(csr_addr, r); + r = cvmx_read_csr(csr_addr); + r = + cvmx_power_throttle_set_field(CVMX_PTH_INDEX_MAXTHR, r, 0xFF); + cvmx_write_csr(csr_addr, r); + return 0; + } + return -EINVAL; +} + +/** + * @INTERNAL + * Get the POWLIM field as percentage% of the MAXPOW field in r. + */ +int cvmx_power_throttle_get_powlim(int cpu) +{ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + uint64_t t, csr_addr, r, s; + + csr_addr = cvmx_power_throttle_csr_addr(cpu); + r = cvmx_read_csr(csr_addr); + + t = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_MAXPOW); + if (!OCTEON_IS_MODEL(OCTEON_CN63XX)) { + s = cvmx_power_throttle_get_field(r, + CVMX_PTH_INDEX_HRMPOWADJ); + if (t < s) + return -EINVAL; + t = t - s; + } + s = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_POWLIM); + return (s * 100)/t; + } + return 0; +} + +/** + * @INTERNAL + * Set the POWLIM field as percentage% of the MAXPOW field in r. + */ +static uint64_t cvmx_power_throttle_set_powlim(int ppid, + uint8_t percentage) +{ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + uint64_t t, csr_addr, r; + + if (percentage > 101) + return -EINVAL; + csr_addr = cvmx_power_throttle_csr_addr(ppid); + r = cvmx_read_csr(csr_addr); + t = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_MAXPOW); + if (!OCTEON_IS_MODEL(OCTEON_CN63XX)) { + uint64_t s; + s = cvmx_power_throttle_get_field(r, + CVMX_PTH_INDEX_HRMPOWADJ); + if (t < s) + return -EINVAL; + t = t - s; + } + if (percentage > 0) + t = percentage * t / 100; + else + t = 0; + r = cvmx_power_throttle_set_field(CVMX_PTH_INDEX_POWLIM, r, t); + cvmx_write_csr(csr_addr, r); + return r; + } + return 0; +} + +/* + * @INTERNAL + * Given ppid, calculate its PowThrottle register's L2C_COP0_MAP CSR + * address. (ppid == PTH_PPID_BCAST is for broadcasting) + */ +static uint64_t cvmx_power_throttle_csr_addr(int ppid) +{ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + uint64_t csr_addr, reg_num, reg_reg, reg_sel; + + if (ppid > CVMX_MAX_CORES) + return -EINVAL; + /* + * register 11 selection 6 + */ + reg_reg = 11; + reg_sel = 6; + reg_num = (ppid << 8) + (reg_reg << 3) + reg_sel; + csr_addr = CVMX_L2C_COP0_MAPX(0) + ((reg_num) << 3); + return csr_addr; + } + return 0; +} + +int cvmx_power_throttle(uint8_t percentage, uint64_t cpu) +{ + int ret = 0; + + if (!CVMX_PTH_AVAILABLE) + return -EINVAL; + + if (cvmx_power_throttle_set_powlim(cpu, percentage) == 0) + ret = -EINVAL; + + return ret; +} + +uint64_t cvmx_power_throttle_get_register(int ppid) +{ + uint64_t csr_addr; + + if (!cvmx_power_throttle_initialized) { + cvmx_power_throttle_init(); + cvmx_power_throttle_initialized = 1; + } + csr_addr = cvmx_power_throttle_csr_addr(ppid); + if (csr_addr == 0) + return -EINVAL; + + return cvmx_read_csr(csr_addr); +} diff --git a/arch/mips/include/asm/octeon/cvmx-power-throttle.h b/arch/mips/include/asm/octeon/cvmx-power-throttle.h new file mode 100644 index 0000000..f0e6bb8 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-power-throttle.h @@ -0,0 +1,103 @@ +/***********************license start*************** + * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights + * reserved. + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + + * * Neither the name of Cavium Inc. nor the names of + * its contributors may be used to endorse or promote products + * derived from this software without specific prior written + * permission. + + * This Software, including technical data, may be subject to U.S. export + * control laws, including the U.S. Export Administration Act and its + * associated regulations, and may be subject to export or import regulations + * in other countries. + + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" + * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR + * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT + * TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY + * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT + * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) + * WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A + * PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET + * ENJOYMENT QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE + * RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. + ***********************license end**************************************/ + +/* + * @file + * + * Interface to power-throttle control, measurement, and debugging + * facilities. + * + */ + +#ifndef __CVMX_POWER_THROTTLE_H__ +#define __CVMX_POWER_THROTTLE_H__ + +enum cvmx_power_throttle_field_index { + CVMX_PTH_INDEX_MAXPOW, + CVMX_PTH_INDEX_POWER, + CVMX_PTH_INDEX_THROTT, + CVMX_PTH_INDEX_RESERVED, + CVMX_PTH_INDEX_DISTAG, + CVMX_PTH_INDEX_PERIOD, + CVMX_PTH_INDEX_POWLIM, + CVMX_PTH_INDEX_MAXTHR, + CVMX_PTH_INDEX_MINTHR, + CVMX_PTH_INDEX_HRMPOWADJ, + CVMX_PTH_INDEX_OVRRD, + CVMX_PTH_INDEX_MAX +}; + +extern int cvmx_power_throttle_get_powlim(int cpu); + +/* + * For maximum POWLIM feedback control freedom, set MINTHR = 0 and MAXTHR = 0xFF + */ +extern int cvmx_init_throttle_feedback(int cpu); + +/** + * Throttle power to percentage% of configured maximum (MAXPOW) + * for the cores identified in coremask. + * + * @param percentage 0 to 100 + * @param coremask bit mask where each bit identifies a core. + * @return 0 for success and -1 for error. + */ +extern int cvmx_power_throttle(uint8_t percentage, uint64_t coremask); + +/** + * Get the i'th field of the power throttle register + * + * @param r is the value of the power throttle register + * @param i is the index of the field + * + * @return (uint64_t)-1 on failure. + */ +extern uint64_t cvmx_power_throttle_get_field(uint64_t r, + enum cvmx_power_throttle_field_index i); + +/** + * Retrieve the content of the power throttle register of a core + * + * @param ppid is the core id + * + * @return (uint64_t)-1 on failure. + */ +extern uint64_t cvmx_power_throttle_get_register(int ppid); + +#endif /* __CVMX_POWER_THROTTLE_H__ */ -- 1.6.3.3.338.ge89ce From pjohn@mvista.com Thu Jun 7 10:14:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 10:14:46 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:38784 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903733Ab2FGIOc (ORCPT ); Thu, 7 Jun 2012 10:14:32 +0200 Received: by mail-pb0-f49.google.com with SMTP id rq13so748925pbb.36 for ; Thu, 07 Jun 2012 01:14:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding:x-gm-message-state; bh=tIr06geBlF1SzOK+743RWpKdvH9XUwPWAAkdz7dmQgQ=; b=QbV/x2x3C0vDwDUj+F+qdtijt6FhJVFjXZD3B1a+eK+ZFUoqKATAJjnLu4P0T3p+Pp kJEKFvla/Ib0SkBBzVCjk0GnklV0HVeMZDu1oA5iNfiuckvAAWie5hoF6xq0upM7GXWN 1fBXjbjitd6tTMF+oBubZPNf3+GVvD0CgG5Im8aC3RhvbNVTK9DFTQT8eolz2rq5z4+W nwp1NIKgP7UDriTOpH9urNJXpL2kTM2Fw1qh3ejtNJ8gcCR/M7DJzaMNYIkti3HQn+Nj 7wMT8gUHfxGZliWSn0ztcXARF5WvdlFn2y3K1h4KFeO3OFfxk+X/7cGsWHKzEYiGE+Jh Q61Q== Received: by 10.68.239.164 with SMTP id vt4mr5685875pbc.166.1339056872029; Thu, 07 Jun 2012 01:14:32 -0700 (PDT) Received: from [10.0.0.4] ([115.118.107.144]) by mx.google.com with ESMTPS id wn3sm3300832pbc.74.2012.06.07.01.14.28 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jun 2012 01:14:31 -0700 (PDT) Subject: [PATCH 2/2] Octeon 6xxx: Add Power Throttling support for CN6xxx and above From: philby john To: linux-mips@linux-mips.org Cc: david.daney@caviumnetworks.com, prasun.kapoor@caviumnetworks.com, ralf@linux-mips.org Content-Type: text/plain; charset="UTF-8" Date: Thu, 07 Jun 2012 13:46:06 +0530 Message-ID: <1339056966.15045.10.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.32.3 (2.32.3-1.fc14) Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkTN1MWWlb6/0RpA6fvpGvgqKhWqG3f76u0lvcW4vrIWRG8TqtRHG/44POj4cB3HOTb24vb X-archive-position: 33596 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7264 Lines: 242 >From 9d9f2b330ad635dff9aa141cd96bde2907385032 Mon Sep 17 00:00:00 2001 From: Philby John Date: Thu, 7 Jun 2012 12:09:31 +0530 Subject: [PATCH] Octeon 6xxx: Add Power Throttling support for CN6xxx and above This patch adds the sysfs primitives for power throttling. Octeon2 supports dynamic power control which aids to cut down power consumption. The code exposes a "percentage" power throttling limiter by means of /sys interface for each available cpu. Setting this value to 0 will set power consumption to a minimum as it will only execute a couple instructions every PERIOD as set in the PowThrottle register. If set to 100% for that particular cpu, it will consume maximum power. Signed-off-by: Philby John --- arch/mips/cavium-octeon/Kconfig | 12 ++ arch/mips/cavium-octeon/Makefile | 1 + arch/mips/cavium-octeon/octeon_pwr_throtl.c | 177 +++++++++++++++++++++++++++ 3 files changed, 190 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cavium-octeon/octeon_pwr_throtl.c diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index f9e275a..7a7f7e7 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -97,5 +97,17 @@ config SWIOTLB select IOMMU_HELPER select NEED_SG_DMA_LENGTH +config CAVIUM_POWER_THROTTLING + bool "Enable support for power throttling on Octeon 63xx and above" + depends on CPU_CAVIUM_OCTEON + default n + help + On Octeon 6xxx and above dynamic power can be controlled + by setting the PowThrottle registers for each cpu. This could be + beneficial for lower power consumption requirements. + + If your application makes extensive use of high-energy instructions + (such as Octeon cryptographic accleration) it's better to leave this + option disabled as it may have slight impact on performance. endif # CPU_CAVIUM_OCTEON diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 19eb043..912f9bb 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -15,3 +15,4 @@ obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_CAVIUM_POWER_THROTTLING) += octeon_pwr_throtl.o diff --git a/arch/mips/cavium-octeon/octeon_pwr_throtl.c b/arch/mips/cavium-octeon/octeon_pwr_throtl.c new file mode 100644 index 0000000..6348cc1 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_pwr_throtl.c @@ -0,0 +1,177 @@ +/* + * octeon_pwr_throtl.c - interface for controlling power throttling on Octeon + * based platforms 6xxx and above. + * Octeon2 supports dynamic power control which aids to cut down power + * consumption. The code exposes a "percentage" power throttling limiter by + * means of /sys interface for each available cpu. Setting this value to 0 + * will set power consumption to a minimum as it will only execute a couple + * instructions every PERIOD as set in the PowThrottle register. + * If set to 100% for that particular cpu; will consume maximum power. + * + * Copyright (C) 2012 MontaVista LLC. + * Author: Philby John + * Credits: This driver is derived from Dmitriy Zavin's (dmitriyz@google.com) + * thermal throttle event support code. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define define_pwr_throttle_one_rw(_name) \ + static DEVICE_ATTR(_name, 0644, power_throt_show_##_name, \ + power_throt_store_##_name) \ + +#define define_pwr_throttle_show_func(name) \ + \ +static ssize_t power_throt_show_##name( \ + struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + unsigned int cpu = dev->id; \ + ssize_t ret; \ + \ + preempt_disable(); /* CPU hotplug */ \ + if (cpu_online(cpu)) \ + ret = sprintf(buf, "%d\n", \ + cvmx_power_throttle_get_powlim(cpu)); \ + else \ + ret = 0; \ + preempt_enable(); \ + \ + return ret; \ +} + +#define define_pwr_throttle_store_func(name) \ + \ +static ssize_t power_throt_store_##name( \ + struct device *dev, \ + struct device_attribute *attr, \ + const char *buf, \ + size_t size) \ +{ \ + unsigned int cpu = dev->id; \ + unsigned long val; \ + int error; \ + \ + error = kstrtoul(buf, 0, &val); \ + if (error) \ + return error; \ + \ + preempt_disable(); \ + cvmx_power_throttle(val, cpu); \ + preempt_enable(); \ + \ + return size; \ +} + +define_pwr_throttle_store_func(percentage); +define_pwr_throttle_show_func(percentage); +define_pwr_throttle_one_rw(percentage); + +static struct attribute *pwr_throttle_attrs[] = { + &dev_attr_percentage.attr, + NULL +}; + +static struct attribute_group pwr_throttle_attr_group = { + .attrs = pwr_throttle_attrs, + .name = "power_throttle" +}; + +#ifdef CONFIG_SYSFS + +/* Mutex protecting device creation against CPU hotplug: */ +static DEFINE_MUTEX(pwr_throttl_cpu_lock); + +static __cpuinit int power_throttle_add_dev(struct device *dev) +{ + int err; + + err = sysfs_create_group(&dev->kobj, &pwr_throttle_attr_group); + if (err) + return err; + err = sysfs_add_file_to_group(&dev->kobj, + &dev_attr_percentage.attr, + pwr_throttle_attr_group.name); + return err; +} + +static __cpuinit void power_throttle_remove_dev(struct device *dev) +{ + sysfs_remove_group(&dev->kobj, &pwr_throttle_attr_group); +} + +static __cpuinit int +power_throttle_cpu_callback(struct notifier_block *nfb, + unsigned long action, + void *hcpu) +{ + unsigned int cpu = (unsigned long)hcpu; + struct device *dev; + int err = 0; + + dev = get_cpu_device(cpu); + + switch (action) { + case CPU_ONLINE: + case CPU_DOWN_FAILED: + case CPU_UP_PREPARE: + case CPU_UP_PREPARE_FROZEN: + mutex_lock(&pwr_throttl_cpu_lock); + err = power_throttle_add_dev(dev); + mutex_unlock(&pwr_throttl_cpu_lock); + WARN_ON(err); + break; + case CPU_UP_CANCELED: + case CPU_UP_CANCELED_FROZEN: + case CPU_DEAD: + case CPU_DEAD_FROZEN: + case CPU_DOWN_PREPARE: + mutex_lock(&pwr_throttl_cpu_lock); + power_throttle_remove_dev(dev); + mutex_unlock(&pwr_throttl_cpu_lock); + break; + } + return err ? NOTIFY_BAD : NOTIFY_OK; +} + +static struct notifier_block power_throttle_cpu_notifier = { + .notifier_call = power_throttle_cpu_callback, +}; + +static __init int power_throtl_init(void) +{ + unsigned int cpu = 0; + int err; + + register_hotcpu_notifier(&power_throttle_cpu_notifier); + +#ifdef CONFIG_HOTPLUG_CPU + mutex_lock(&pwr_throttl_cpu_lock); +#endif + /* connect live CPUs to sysfs */ + for_each_online_cpu(cpu) { + err = power_throttle_add_dev(get_cpu_device(cpu)); + WARN_ON(err); + cvmx_init_throttle_feedback(cpu); + } +#ifdef CONFIG_HOTPLUG_CPU + mutex_unlock(&pwr_throttl_cpu_lock); +#endif + return 0; +} +device_initcall(power_throtl_init); + +#endif -- 1.6.3.3.338.ge89ce From jyavenard@gmail.com Thu Jun 7 12:41:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 12:41:19 +0200 (CEST) Received: from mail-yw0-f49.google.com ([209.85.213.49]:34734 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903735Ab2FGKlO (ORCPT ); Thu, 7 Jun 2012 12:41:14 +0200 Received: by yhjj52 with SMTP id j52so302313yhj.36 for ; Thu, 07 Jun 2012 03:41:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=rWD+8FTi1HDtlq6EUGOISh5BVT+HyrBdwjFZ0LRDwVM=; b=igFd6OXETh3aaqflHDyitSy+c9uO7Es0hnaFakriIVEViCMDo8AmTy3MseKp8RKZy/ lOoVmeLegCpuZ4qvgEufNc6Z4QZzSHQH3r7SvgFLiQzijIASapv77cx0n0bxtYgqtghT A96OpTKyGL7RJxbWOENz8s4+Ab8jihcdNstEMf33Fsr/hjYwvguu2JYT66/douz8CkUf aj9Wbnq2e44sRv/tuqIZ+lmUYEv3ln0VA1x3ifEV+0C9NHW+QYUmWXs2LCWvyBkeNBqk hd4eY05+ZBh+ZRZQ0T+yZmfQSXeiYaHR3ToND8hCxM7yEZ+0pZegOjTCScEg7c3ChVfU MNsw== MIME-Version: 1.0 Received: by 10.236.173.135 with SMTP id v7mr1525232yhl.19.1339065667772; Thu, 07 Jun 2012 03:41:07 -0700 (PDT) Received: by 10.146.205.5 with HTTP; Thu, 7 Jun 2012 03:41:07 -0700 (PDT) Date: Thu, 7 Jun 2012 20:41:07 +1000 Message-ID: Subject: Patch for the "ug" bug From: Jean-Yves Avenard To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33597 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jyavenard@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13286 Lines: 383 Hello This is my first post here, so hopefully I'm doing it the right way. I recently an Asus RT-N66U router, powered by a Broadcom BCM5300. MIPS based obviously. I am an infrequent committer of the Tomato firmware team. One issue was reported that caused quite surprising problems. We call it the "ug" bug. In a shell: cd /tmp echo "#!/bin/sh" >bug echo 'echo -n $1.' >>bug chmod +x bug for i in 0 1 2 3 4 5 6 7 8 9; do bug $i; done would result in random data being output. Typically it would look something like: ug.1.ug.3.ug.5.ug.ug.ug.ug.root@RT-N66U:/tmp# This issue affects a few other firmware (ddwrt) in particular. This doesn't affect Asus stock firmware After a short investigation, I ruled out that the problem was either in uclibc or busybox and is something related to an issue in the kernel Looking at the kernel shipped with the Asus, they have made some modifications in how pages are initialised... The following patch, is a port of the required changes that fix the memory corruption exposed by the "ug" bug... Let me know if you would like this patch to be submitted differently. Not knowing the submit policy, I put it inline, but due to the presence of tabs (ugh!) it may not come out properly. The patch is for the linux that ships with Tomato obviously, but checking the linux git repository, it will apply with minor mod. Let me know if you want me to do those mods for you.. Best regards Jean-Yves Avenard >From 6e9e332d29f6cb6e5439f728a2b7cb2adf861002 Mon Sep 17 00:00:00 2001 From: Jean-Yves Avenard Date: Thu, 7 Jun 2012 20:31:54 +1000 Subject: [PATCH] Fix "ug" bug Port page map changes from Asus RT-N66U stock firmware --- .../linux/linux-2.6/arch/mips/kernel/syscall.c | 2 + .../src-rt/linux/linux-2.6/arch/mips/mm/c-r4k.c | 31 ++++++++++--- .../src-rt/linux/linux-2.6/arch/mips/mm/cache.c | 9 ++++ .../src-rt/linux/linux-2.6/arch/mips/mm/highmem.c | 48 ++++++++++++++------ release/src-rt/linux/linux-2.6/arch/mips/mm/init.c | 5 +- .../linux/linux-2.6/arch/mips/mm/pgtable-32.c | 2 +- .../linux/linux-2.6/include/asm-mips/fixmap.h | 11 ++++- .../src-rt/linux/linux-2.6/include/asm-mips/page.h | 8 ++++ 8 files changed, 92 insertions(+), 24 deletions(-) diff --git a/release/src-rt/linux/linux-2.6/arch/mips/kernel/syscall.c b/release/src-rt/linux/linux-2.6/arch/mips/kernel/syscall.c index a0a3771..54cbf54 100644 --- a/release/src-rt/linux/linux-2.6/arch/mips/kernel/syscall.c +++ b/release/src-rt/linux/linux-2.6/arch/mips/kernel/syscall.c @@ -56,8 +56,10 @@ out: } unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */ +unsigned char shm_align_shift = PAGE_SHIFT; /* Sane caches */ EXPORT_SYMBOL(shm_align_mask); +EXPORT_SYMBOL(shm_align_shift); #define COLOUR_ALIGN(addr,pgoff) \ ((((addr) + shm_align_mask) & ~shm_align_mask) + \ diff --git a/release/src-rt/linux/linux-2.6/arch/mips/mm/c-r4k.c b/release/src-rt/linux/linux-2.6/arch/mips/mm/c-r4k.c index 23e8fe3..67a7171 100644 --- a/release/src-rt/linux/linux-2.6/arch/mips/mm/c-r4k.c +++ b/release/src-rt/linux/linux-2.6/arch/mips/mm/c-r4k.c @@ -994,6 +994,30 @@ static void __cpuinit probe_pcache(void) dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz); } +void __init r4k_probe_cache(void) +{ + unsigned long config1 = read_c0_config1(); + unsigned int dcache_size, lsize, ways, sets; + + if ((lsize = ((config1 >> 10) & 7))) + lsize = 2 << lsize; + + sets = 64 << ((config1 >> 13) & 7); + ways = 1 + ((config1 >> 7) & 7); + + if (lsize) { + shm_align_mask = max_t( unsigned long, + sets * lsize - 1, + PAGE_SIZE - 1); + + if (shm_align_mask != (PAGE_SIZE - 1)) + shm_align_shift = ffs((shm_align_mask + 1)) - 1; + } else + shm_align_mask = PAGE_SIZE-1; + + +} + /* * If you even _breathe_ on this function, look at the gcc output and make sure * it does not pop things on and off the stack for the cache sizing loop that @@ -1262,12 +1286,7 @@ void __cpuinit r4k_cache_init(void) * This code supports virtually indexed processors and will be * unnecessarily inefficient on physically indexed processors. */ - if (c->dcache.linesz) - shm_align_mask = max_t( unsigned long, - c->dcache.sets * c->dcache.linesz - 1, - PAGE_SIZE - 1); - else - shm_align_mask = PAGE_SIZE-1; + flush_cache_all = r4k_flush_cache_all; __flush_cache_all = r4k___flush_cache_all; flush_cache_mm = r4k_flush_cache_mm; diff --git a/release/src-rt/linux/linux-2.6/arch/mips/mm/cache.c b/release/src-rt/linux/linux-2.6/arch/mips/mm/cache.c index cc26edb..3acb137 100644 --- a/release/src-rt/linux/linux-2.6/arch/mips/mm/cache.c +++ b/release/src-rt/linux/linux-2.6/arch/mips/mm/cache.c @@ -148,6 +148,15 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address, static char cache_panic[] __cpuinitdata = "Yeee, unsupported cache architecture."; +void __init cpu_early_probe_cache(void) +{ + if (cpu_has_4k_cache) { + extern void __weak r4k_probe_cache(void); + + return r4k_probe_cache(); + } +} + void __cpuinit cpu_cache_init(void) { if (cpu_has_3k_cache) { diff --git a/release/src-rt/linux/linux-2.6/arch/mips/mm/highmem.c b/release/src-rt/linux/linux-2.6/arch/mips/mm/highmem.c index e2e3c6b..2feb5b7 100644 --- a/release/src-rt/linux/linux-2.6/arch/mips/mm/highmem.c +++ b/release/src-rt/linux/linux-2.6/arch/mips/mm/highmem.c @@ -39,6 +39,7 @@ void __kunmap(struct page *page) struct kmap_map { struct page *page; void *vaddr; + unsigned long pfn; }; struct { @@ -61,8 +62,9 @@ kmap_atomic_page_address(struct page *page) void *__kmap_atomic(struct page *page, enum km_type type) { - enum fixed_addresses idx; + unsigned int idx; unsigned long vaddr; + unsigned long pfn; /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ pagefault_disable(); @@ -70,31 +72,38 @@ void *__kmap_atomic(struct page *page, enum km_type type) return page_address(page); idx = type + KM_TYPE_NR*smp_processor_id(); - vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); + pfn = page_to_pfn(page); + vaddr = fix_to_virt_noalias(VALIAS_IDX(FIX_KMAP_BEGIN + idx), pfn); #ifdef CONFIG_DEBUG_HIGHMEM - if (!pte_none(*(kmap_pte-idx))) + if (!pte_none(*(kmap_pte-(virt_to_fix(vaddr) - VALIAS_IDX(FIX_KMAP_BEGIN))))) BUG(); #endif - set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); + /* Vaddr could have been adjusted to avoid virt aliasing, + * recalculate the idx from vaddr. + */ + set_pte(kmap_pte-(virt_to_fix(vaddr) - VALIAS_IDX(FIX_KMAP_BEGIN)), \ + mk_pte(page, kmap_prot)); local_flush_tlb_one((unsigned long)vaddr); kmap_atomic_maps[smp_processor_id()].map[type].page = page; kmap_atomic_maps[smp_processor_id()].map[type].vaddr = (void *)vaddr; - + kmap_atomic_maps[smp_processor_id()].map[type].pfn = pfn; + return (void*) vaddr; } void __kunmap_atomic(void *kvaddr, enum km_type type) { unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; - enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); + unsigned int idx = type + KM_TYPE_NR*smp_processor_id(); + unsigned long pfn = kmap_atomic_maps[smp_processor_id()].map[type].pfn; if (vaddr < FIXADDR_START) { // FIXME pagefault_enable(); return; } - if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN+idx)) + if (vaddr != fix_to_virt_noalias(VALIAS_IDX(FIX_KMAP_BEGIN + idx), pfn)) BUG(); /* @@ -104,7 +113,8 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) if ( kmap_atomic_maps[smp_processor_id()].map[type].vaddr ) { kmap_atomic_maps[smp_processor_id()].map[type].page = (struct page *)0; kmap_atomic_maps[smp_processor_id()].map[type].vaddr = (void *) 0; - + kmap_atomic_maps[smp_processor_id()].map[type].pfn = 0; + flush_data_cache_page((unsigned long)vaddr); } @@ -113,7 +123,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) * force other mappings to Oops if they'll try to access * this pte without first remap it */ - pte_clear(&init_mm, vaddr, kmap_pte-idx); + pte_clear(&init_mm, vaddr, kmap_pte-(virt_to_fix(vaddr) - VALIAS_IDX(FIX_KMAP_BEGIN))); local_flush_tlb_one(vaddr); #endif @@ -126,14 +136,23 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) */ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) { - enum fixed_addresses idx; + unsigned int idx; unsigned long vaddr; pagefault_disable(); idx = type + KM_TYPE_NR*smp_processor_id(); - vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); - set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot)); + vaddr = fix_to_virt_noalias(VALIAS_IDX(FIX_KMAP_BEGIN + idx), pfn); + /* Vaddr could have been adjusted to avoid virt aliasing, + * recalculate the idx from vaddr. + */ + set_pte(kmap_pte-(virt_to_fix(vaddr) - VALIAS_IDX(FIX_KMAP_BEGIN)), \ + pfn_pte(pfn, kmap_prot)); + + kmap_atomic_maps[smp_processor_id()].map[type].page = (struct page *)0; + kmap_atomic_maps[smp_processor_id()].map[type].vaddr = (void *) vaddr; + kmap_atomic_maps[smp_processor_id()].map[type].pfn = pfn; + flush_tlb_one(vaddr); return (void*) vaddr; @@ -141,14 +160,13 @@ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) struct page *__kmap_atomic_to_page(void *ptr) { - unsigned long idx, vaddr = (unsigned long)ptr; + unsigned long vaddr = (unsigned long)ptr; pte_t *pte; if (vaddr < FIXADDR_START) return virt_to_page(ptr); - idx = virt_to_fix(vaddr); - pte = kmap_pte - (idx - FIX_KMAP_BEGIN); + pte = kmap_pte - (virt_to_fix(vaddr) - VALIAS_IDX(FIX_KMAP_BEGIN)); return pte_page(*pte); } diff --git a/release/src-rt/linux/linux-2.6/arch/mips/mm/init.c b/release/src-rt/linux/linux-2.6/arch/mips/mm/init.c index 12793c9..528a6ee 100644 --- a/release/src-rt/linux/linux-2.6/arch/mips/mm/init.c +++ b/release/src-rt/linux/linux-2.6/arch/mips/mm/init.c @@ -62,6 +62,7 @@ #endif /* CONFIG_MIPS_MT_SMTC */ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); +extern void cpu_early_probe_cache(); /* * We have up to 8 empty zeroed pages so we can map one of the right colour @@ -286,7 +287,7 @@ static void __init kmap_init(void) unsigned long kmap_vstart; /* cache the first kmap pte */ - kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); + kmap_vstart = __fix_to_virt(VALIAS_IDX(FIX_KMAP_BEGIN)); kmap_pte = kmap_get_fixmap_pte(kmap_vstart); kmap_prot = PAGE_KERNEL; @@ -362,6 +363,8 @@ void __init paging_init(void) unsigned long lastpfn; #endif /* CONFIG_FLATMEM */ + cpu_early_probe_cache(); + pagetable_init(); #ifdef CONFIG_HIGHMEM diff --git a/release/src-rt/linux/linux-2.6/arch/mips/mm/pgtable-32.c b/release/src-rt/linux/linux-2.6/arch/mips/mm/pgtable-32.c index adc6911..7a89f48 100644 --- a/release/src-rt/linux/linux-2.6/arch/mips/mm/pgtable-32.c +++ b/release/src-rt/linux/linux-2.6/arch/mips/mm/pgtable-32.c @@ -51,7 +51,7 @@ void __init pagetable_init(void) /* * Fixed mappings: */ - vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK; + vaddr = __fix_to_virt(VALIAS_IDX(__end_of_fixed_addresses - 1)) & PMD_MASK; fixrange_init(vaddr, vaddr + FIXADDR_SIZE, pgd_base); #ifdef CONFIG_HIGHMEM diff --git a/release/src-rt/linux/linux-2.6/include/asm-mips/fixmap.h b/release/src-rt/linux/linux-2.6/include/asm-mips/fixmap.h index 4c23947..a6761c6 100644 --- a/release/src-rt/linux/linux-2.6/include/asm-mips/fixmap.h +++ b/release/src-rt/linux/linux-2.6/include/asm-mips/fixmap.h @@ -84,12 +84,21 @@ extern void __set_fixmap (enum fixed_addresses idx, #else #define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) #endif -#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) +#define FIXADDR_SIZE (__end_of_fixed_addresses << (VALIAS_PAGE_SHIFT)) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) #define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT)) #define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT) +static inline unsigned long fix_to_virt_noalias(const unsigned int x, unsigned long pfn) +{ + unsigned long vaddr = __fix_to_virt(x); + unsigned long poffset = (pfn << PAGE_SHIFT) & VALIAS_PAGE_OFFSET_MASK; + unsigned long voffset = vaddr & VALIAS_PAGE_OFFSET_MASK; + + return ((!voffset || (poffset >= voffset)) ? (vaddr | poffset):(vaddr | poffset | VALIAS_PAGE_SIZE)); +} + extern void __this_fixmap_does_not_exist(void); /* diff --git a/release/src-rt/linux/linux-2.6/include/asm-mips/page.h b/release/src-rt/linux/linux-2.6/include/asm-mips/page.h index fa7289f..96f5245 100644 --- a/release/src-rt/linux/linux-2.6/include/asm-mips/page.h +++ b/release/src-rt/linux/linux-2.6/include/asm-mips/page.h @@ -56,6 +56,14 @@ extern void clear_page(void * page); extern void copy_page(void * to, void * from); extern unsigned long shm_align_mask; +extern unsigned char shm_align_shift; + +#define VALIAS_PAGE_OFFSET_MASK (shm_align_mask) +#define VALIAS_PAGE_MASK (~VALIAS_PAGE_OFFSET_MASK) +#define VALIAS_PAGE_SHIFT (shm_align_shift) +#define VALIAS_SHIFT (VALIAS_PAGE_SHIFT - PAGE_SHIFT) +#define VALIAS_PAGE_SIZE (1UL << VALIAS_PAGE_SHIFT) +#define VALIAS_IDX(x) ((x) << VALIAS_SHIFT) static inline unsigned long pages_do_alias(unsigned long addr1, unsigned long addr2) -- 1.7.9.5 From sjhill@realitydiluted.com Thu Jun 7 16:46:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 16:46:42 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:51424 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903735Ab2FGOqi (ORCPT ); Thu, 7 Jun 2012 16:46:38 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Scdyp-0004ia-3U for linux-mips@linux-mips.org; Thu, 07 Jun 2012 09:46:31 -0500 Message-ID: <4FD0BEBF.4070006@realitydiluted.com> Date: Thu, 07 Jun 2012 09:46:23 -0500 From: "Steven J. Hill" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120312 Thunderbird/11.0 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH 00/35] Cleanup firmware support across multiple platforms. References: <1338931179-9611-1-git-send-email-sjhill@mips.com> In-Reply-To: <1338931179-9611-1-git-send-email-sjhill@mips.com> X-Enigmail-Version: 1.4.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33598 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@realitydiluted.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 455 Lines: 17 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello. Are there any further comments or concerns on these patches before I submit a second version with the changes below? Thank you. - -Steve -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk/Qvr8ACgkQgyK5H2Ic36feogCfZkynMUs49+b6SrkYAum9izHw +QYAn1TT55Xmtd4oiG4nXazaT8qqN0oR =dv7K -----END PGP SIGNATURE----- From ddaney.cavm@gmail.com Thu Jun 7 21:52:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 21:52:20 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:64094 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903735Ab2FGTwR (ORCPT ); Thu, 7 Jun 2012 21:52:17 +0200 Received: by dadm1 with SMTP id m1so1427993dad.36 for ; Thu, 07 Jun 2012 12:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=ZzDm0Sk1yC/2I+TBQ93H9xUYlpr/q5jsNUw9B05mNds=; b=ZzOEo33YyWKb5kJItWJypWDFq+iUw1fYZRlyU7ZWNiSMYdZj8glBkfLlOO4b0PcJZb 65jk5Su+6f2UBqYQFs65Wm93ZigF5aKL4ybCUNXE2LzdcwSTBGMHeM4qcOga/eaXSAZt M2aODPAeEOMEaN5jsb9xnvH924u0ohkSbAo38U2I476mM0mgDnKX0M36MOvDv2qhmxZS ochn36b6rPfPKvOYcf0PpOdv+LMFpOIji/d0+0065hcS/bSDQKOz8MAkHiNZ7RY5j8Uw OnoZjULPUhVu07ZBq9guqgIuJelVUwKzjAJCRc2RkcKWw+Sj0VvupyLmKdhaMbpr/1UL OO/g== Received: by 10.68.201.195 with SMTP id kc3mr12739696pbc.33.1339098730077; Thu, 07 Jun 2012 12:52:10 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id wn3sm5084080pbc.74.2012.06.07.12.52.09 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jun 2012 12:52:09 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q57Jq7Jl009825; Thu, 7 Jun 2012 12:52:07 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q57Jq6kH009823; Thu, 7 Jun 2012 12:52:07 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 1/3] MIPS: OCTEON: Fix build error when configured without PCI_MSI Date: Thu, 7 Jun 2012 12:52:05 -0700 Message-Id: <1339098725-9792-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33599 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1159 Lines: 40 From: David Daney The build dies with complaints about missing definition of OCTEON_IRQ_RST. This symbol was removed, so don't use it as part of the definition of OCTEON_IRQ_LAST. Set OCTEON_IRQ_LAST to 127 so there is space for all the automatically allocated (via irq_domain) irqs. Signed-off-by: David Daney --- arch/mips/include/asm/mach-cavium-octeon/irq.h | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index f9bfb63..4189920 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -50,6 +50,9 @@ enum octeon_irq { OCTEON_IRQ_MII0, OCTEON_IRQ_MII1, OCTEON_IRQ_BOOTDMA, +#ifndef CONFIG_PCI_MSI + OCTEON_IRQ_LAST = 127 +#endif }; #ifdef CONFIG_PCI_MSI @@ -58,8 +61,6 @@ enum octeon_irq { #define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) #define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) -#else -#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1) #endif #endif -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 21:52:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 21:52:46 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:50595 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903731Ab2FGTwd (ORCPT ); Thu, 7 Jun 2012 21:52:33 +0200 Received: by pbbrq13 with SMTP id rq13so1614657pbb.36 for ; Thu, 07 Jun 2012 12:52:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=9d0mwAOl4W3cE0PHJPZMpzJBEDBytYNDwKd0UC1S2n8=; b=pqp3j1BQkGGrHGFd5VuyrfGvt9n/SSnXXDDpALqS/UHi1gBDjvjofoWFEDKtb/ezcj v5QR7Wh6c48W139vpAhxm+xzVd9oDVqkBnt1Rbs3kDxxeSLpXGIyE6IX5CjoITNb96Dj GekCxsrRBCIn0waZHSxrPmOHOX3zClpcqC7r6Aw2/RIPKvhS2BgqT7bMiIL7IAV5Pewc Wx9D/OsxBkOpmANjxWuzfho1Pud1zYZF5u5UB+ym1Bg5IBdaKHKcg2aH7JeGi3SaPF0e APLwpdlX+ON9IVkrm3w0SeZDNHVnFuZ9PB38qNk5h8smcf1P8ns/T4yTmMgfigsyvhsU wXnA== Received: by 10.68.136.106 with SMTP id pz10mr11657890pbb.143.1339098747261; Thu, 07 Jun 2012 12:52:27 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id to1sm5102352pbc.27.2012.06.07.12.52.26 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jun 2012 12:52:26 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q57JqPBc009906; Thu, 7 Jun 2012 12:52:25 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q57JqPuq009905; Thu, 7 Jun 2012 12:52:25 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 2/3] MIPS: OCTEON: Remove some unused OCTEON_IRQ_* definitions. Date: Thu, 7 Jun 2012 12:52:24 -0700 Message-Id: <1339098744-9874-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33600 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1169 Lines: 44 From: David Daney These are now unused. Remove them. Signed-off-by: David Daney --- arch/mips/include/asm/mach-cavium-octeon/irq.h | 7 ------- 1 files changed, 0 insertions(+), 7 deletions(-) diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 4189920..0a47c9f 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -26,9 +26,6 @@ enum octeon_irq { OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, OCTEON_IRQ_MBOX1, - OCTEON_IRQ_UART0, - OCTEON_IRQ_UART1, - OCTEON_IRQ_UART2, OCTEON_IRQ_PCI_INT0, OCTEON_IRQ_PCI_INT1, OCTEON_IRQ_PCI_INT2, @@ -38,8 +35,6 @@ enum octeon_irq { OCTEON_IRQ_PCI_MSI2, OCTEON_IRQ_PCI_MSI3, - OCTEON_IRQ_TWSI, - OCTEON_IRQ_TWSI2, OCTEON_IRQ_RML, OCTEON_IRQ_TIMER0, OCTEON_IRQ_TIMER1, @@ -47,8 +42,6 @@ enum octeon_irq { OCTEON_IRQ_TIMER3, OCTEON_IRQ_USB0, OCTEON_IRQ_USB1, - OCTEON_IRQ_MII0, - OCTEON_IRQ_MII1, OCTEON_IRQ_BOOTDMA, #ifndef CONFIG_PCI_MSI OCTEON_IRQ_LAST = 127 -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Jun 7 21:52:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 21:53:08 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:64094 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903735Ab2FGTwp (ORCPT ); Thu, 7 Jun 2012 21:52:45 +0200 Received: by mail-pz0-f49.google.com with SMTP id m1so1427993dad.36 for ; Thu, 07 Jun 2012 12:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=lL2e6XKhkEo8jr3KjHEyBZ9uKsZwMlMiTv8UCpWgpjw=; b=qkKmRJOB+OfEKNIbgXDWup6Dw1m37DgaWzr4PINkdVBKNPn0c8rgQ3PbrK2uh6ALt5 l6SoPClIJXaabc7y9sw6snnOPOuHIRz5dImTq9nJAlcdc1E+HgR6IQ/ye605huJFR0e1 IMeKQXv37+IfOnhDiYaCWMaCFlF183UMkZ5qozgRHaS9M3CrCtUcjjytTNOYyRvZDVol dbP/0soPoSdDjsZmWP3NaY5R9uR75J3xyVkreYJue5eTp5T7pK8hsFRei2+9I/X5oXrP nhaLSU6NKfp//0desJkX0laxjAhWIuuypz8vRzeOtI28H+yFwBOwbc5HwlJ4olb4a/t8 uWjg== Received: by 10.68.227.195 with SMTP id sc3mr11246490pbc.104.1339098764724; Thu, 07 Jun 2012 12:52:44 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ph1sm5096869pbb.45.2012.06.07.12.52.43 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jun 2012 12:52:44 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q57Jqg0m009987; Thu, 7 Jun 2012 12:52:42 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q57JqgLJ009986; Thu, 7 Jun 2012 12:52:42 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 3/3] MIPS:Update cavium-octeon_defconfig Date: Thu, 7 Jun 2012 12:52:41 -0700 Message-Id: <1339098761-9955-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33601 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6586 Lines: 242 From: David Daney Enable PCI,MSI and Ethernet drivers. Arbitrarily set page size to 16K Signed-off-by: David Daney --- arch/mips/configs/cavium-octeon_defconfig | 167 +++++++++++++++++++++++------ 1 files changed, 133 insertions(+), 34 deletions(-) diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig index 75165df..357e78e 100644 --- a/arch/mips/configs/cavium-octeon_defconfig +++ b/arch/mips/configs/cavium-octeon_defconfig @@ -1,38 +1,48 @@ CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y +CONFIG_CAVIUM_CN63XXP1=y CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 +CONFIG_PAGE_SIZE_16KB=y +CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_SPARSEMEM_MANUAL=y CONFIG_SMP=y -CONFIG_PREEMPT=y +CONFIG_NR_CPUS=32 +CONFIG_HZ_1000=y CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_FHANDLE=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_LOG_BUF_SHIFT=16 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set +CONFIG_PCI=y +CONFIG_PCI_MSI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_MIPS32_COMPAT=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=m CONFIG_INET=y CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y @@ -41,53 +51,142 @@ CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m # CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set +# CONFIG_IPV6_SIT is not set +CONFIG_BRIDGE=m +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_SLRAM=y +CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y -# CONFIG_MISC_DEVICES is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=500000 +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +# CONFIG_SATA_PMP is not set +CONFIG_SATA_AHCI=y +CONFIG_SATA_SIL24=y +CONFIG_PATA_OCTEON_CF=y +# CONFIG_ATA_BMDMA is not set CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_NETDEV_10000 is not set -# CONFIG_INPUT is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_MARVELL_PHY=y +CONFIG_BROADCOM_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=2 -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set +CONFIG_SERIAL_8250_NR_UARTS=6 +CONFIG_SERIAL_8250_RUNTIME_UARTS=6 +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA9541=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_OCTEON=y +CONFIG_SPI=y +CONFIG_SENSORS_TMP421=y +CONFIG_THERMAL=y CONFIG_WATCHDOG=y -# CONFIG_USB_SUPPORT is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_MON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OCTEON_EHCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_LIBUSUAL=y +CONFIG_MMC=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_STAGING=y +CONFIG_OCTEON_ETHERNET=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y CONFIG_PROC_KCORE=y CONFIG_TMPFS=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NLS=y +CONFIG_HUGETLBFS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_SCHED_DEBUG is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -# CONFIG_EARLY_PRINTK is not set +# CONFIG_FTRACE is not set CONFIG_SECURITY=y CONFIG_SECURITY_NETWORK=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -- 1.7.2.3 From david.daney@cavium.com Thu Jun 7 22:10:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 22:10:58 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12900 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903736Ab2FGUKx (ORCPT ); Thu, 7 Jun 2012 22:10:53 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 07 Jun 2012 13:12:16 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 7 Jun 2012 13:10:21 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 7 Jun 2012 13:10:21 -0700 Message-ID: <4FD10AAD.3050307@cavium.com> Date: Thu, 07 Jun 2012 13:10:21 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: David Daney CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: Re: [PATCH 2/3] MIPS: OCTEON: Remove some unused OCTEON_IRQ_* definitions. References: <1339098744-9874-1-git-send-email-ddaney.cavm@gmail.com> In-Reply-To: <1339098744-9874-1-git-send-email-ddaney.cavm@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 07 Jun 2012 20:10:21.0618 (UTC) FILETIME=[911B8120:01CD44E9] X-archive-position: 33602 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1352 Lines: 50 Drat! I missed one. Sending a new patch. David Daney On 06/07/2012 12:52 PM, David Daney wrote: > From: David Daney > > These are now unused. Remove them. > > Signed-off-by: David Daney > --- > arch/mips/include/asm/mach-cavium-octeon/irq.h | 7 ------- > 1 files changed, 0 insertions(+), 7 deletions(-) > > diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h > index 4189920..0a47c9f 100644 > --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h > +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h > @@ -26,9 +26,6 @@ enum octeon_irq { > OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, > OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, > OCTEON_IRQ_MBOX1, > - OCTEON_IRQ_UART0, > - OCTEON_IRQ_UART1, > - OCTEON_IRQ_UART2, > OCTEON_IRQ_PCI_INT0, > OCTEON_IRQ_PCI_INT1, > OCTEON_IRQ_PCI_INT2, > @@ -38,8 +35,6 @@ enum octeon_irq { > OCTEON_IRQ_PCI_MSI2, > OCTEON_IRQ_PCI_MSI3, > > - OCTEON_IRQ_TWSI, > - OCTEON_IRQ_TWSI2, > OCTEON_IRQ_RML, > OCTEON_IRQ_TIMER0, > OCTEON_IRQ_TIMER1, > @@ -47,8 +42,6 @@ enum octeon_irq { > OCTEON_IRQ_TIMER3, > OCTEON_IRQ_USB0, > OCTEON_IRQ_USB1, > - OCTEON_IRQ_MII0, > - OCTEON_IRQ_MII1, > OCTEON_IRQ_BOOTDMA, > #ifndef CONFIG_PCI_MSI > OCTEON_IRQ_LAST = 127 From ddaney.cavm@gmail.com Thu Jun 7 22:12:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Jun 2012 22:12:47 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:39925 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903731Ab2FGUMl (ORCPT ); Thu, 7 Jun 2012 22:12:41 +0200 Received: by dadm1 with SMTP id m1so1454718dad.36 for ; Thu, 07 Jun 2012 13:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=sliMkv32SFAlb7TKeak29br71gDmu4OhVvNrzJLfXuE=; b=xb1ZOq1+17z0zraLqmb9MCDeJOfD2OALU4w2VJK6lilJfZ+LkIM7OQQLRdX9Lbhx2E fCREHX5oHUdhZSlA9FgNF1OBhl7LagYbs2g82NP2nCRmjmHn9Cl05qIoL992/N5c444K IKIW5bfdx0szGPIMvk6mhfoM0i56OGPTmGZG8SiCA8OBmXs6AJflzeCh1Efk9avLbv14 bJ0mdmI66Q/KWLPRMt7eCCNw1Na4mqbWBIvwhUa/DKRWuOuHSDBHz49feIZvjXeqMcRP Zb718r6I+aRZuNG/mEH4nQeVePJnnklG5M0WiuJ2EhL5av2aSoy/fpM/pkjBBZ21V9oF p4aQ== Received: by 10.68.231.71 with SMTP id te7mr11388511pbc.161.1339099954660; Thu, 07 Jun 2012 13:12:34 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id tj4sm5149731pbc.33.2012.06.07.13.12.33 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jun 2012 13:12:34 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q57KCWb0018598; Thu, 7 Jun 2012 13:12:32 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q57KCWVG018596; Thu, 7 Jun 2012 13:12:32 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v2] MIPS: OCTEON: Remove some unused OCTEON_IRQ_* definitions. Date: Thu, 7 Jun 2012 13:12:31 -0700 Message-Id: <1339099951-18565-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33603 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1380 Lines: 50 From: David Daney These are now unused. Remove them. Signed-off-by: David Daney --- arch/mips/include/asm/mach-cavium-octeon/irq.h | 10 +--------- 1 files changed, 1 insertions(+), 9 deletions(-) diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 4189920..c22a307 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -21,14 +21,10 @@ enum octeon_irq { OCTEON_IRQ_TIMER, /* sources in CIU_INTX_EN0 */ OCTEON_IRQ_WORKQ0, - OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16, - OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16, + OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16, OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, OCTEON_IRQ_MBOX1, - OCTEON_IRQ_UART0, - OCTEON_IRQ_UART1, - OCTEON_IRQ_UART2, OCTEON_IRQ_PCI_INT0, OCTEON_IRQ_PCI_INT1, OCTEON_IRQ_PCI_INT2, @@ -38,8 +34,6 @@ enum octeon_irq { OCTEON_IRQ_PCI_MSI2, OCTEON_IRQ_PCI_MSI3, - OCTEON_IRQ_TWSI, - OCTEON_IRQ_TWSI2, OCTEON_IRQ_RML, OCTEON_IRQ_TIMER0, OCTEON_IRQ_TIMER1, @@ -47,8 +41,6 @@ enum octeon_irq { OCTEON_IRQ_TIMER3, OCTEON_IRQ_USB0, OCTEON_IRQ_USB1, - OCTEON_IRQ_MII0, - OCTEON_IRQ_MII1, OCTEON_IRQ_BOOTDMA, #ifndef CONFIG_PCI_MSI OCTEON_IRQ_LAST = 127 -- 1.7.2.3 From mcdonald.shane@gmail.com Mon Jun 11 06:16:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Jun 2012 06:16:28 +0200 (CEST) Received: from mail-gh0-f177.google.com ([209.85.160.177]:37175 "EHLO mail-gh0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901334Ab2FKEQW convert rfc822-to-8bit (ORCPT ); Mon, 11 Jun 2012 06:16:22 +0200 Received: by ghbf11 with SMTP id f11so2459116ghb.36 for ; Sun, 10 Jun 2012 21:16:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=l3fK+rcW3MGkW1zOH2gQoy74NlStA5xZynYVGjrayOc=; b=mbTwcPTdXYIl6omKRnvKQTpKJHeivw+nq6ff8EvdJSCeZPR6tv/SG93d7rlYHWJbzz 4cV5sxrUF6TzwmnE12UtltzE6jG8qK9iYNmmv7A0/8L14TW2EApkku/FUORXlC4b83QY plEB5KsuGmbiL97PQayfb+7Hg8ernIot7q1YOCcAPs81fTcSzuogMPYkM+9EPW1NHjNy 4njYZdB2c7GLhV5CP+aK51ZZj0hsBSF+5+w3yahqgkHEM61FncJ6qFjO50zIC910QzDx 1YTHx9QuAxZs+639NS4AlP/MsNs1It+OaGdQ1NyzkRLDwK0bRejh+2O8ia3sMjYp3Ykw 2AfA== MIME-Version: 1.0 Received: by 10.50.36.227 with SMTP id t3mr5719282igj.13.1339388175438; Sun, 10 Jun 2012 21:16:15 -0700 (PDT) Received: by 10.231.219.5 with HTTP; Sun, 10 Jun 2012 21:16:15 -0700 (PDT) In-Reply-To: <1337040290-16015-6-git-send-email-ddaney.cavm@gmail.com> References: <1337040290-16015-1-git-send-email-ddaney.cavm@gmail.com> <1337040290-16015-6-git-send-email-ddaney.cavm@gmail.com> Date: Sun, 10 Jun 2012 22:16:15 -0600 Message-ID: Subject: Re: [PATCH v2 5/5] MIPS: Move cache setup to setup_arch(). From: Shane McDonald To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, David Daney Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 33604 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4382 Lines: 124 I've run into a problem in linux-3.5-rc1, and I've tracked it down to this patch, MIPS: Move cache setup to setup_arch()., commit 6650df3c380e0db558dbfec63ed860402c6afb2a. On Mon, May 14, 2012 at 6:04 PM, David Daney wrote: > From: David Daney > > commit 97ce2c88f9ad42e3c60a9beb9fca87abf3639faa (jump-label: initialize > jump-label subsystem much earlier) breaks MIPS.  The jump_label_init() > call was moved before trap_init() which is where we initialize > flush_icache_range(). > > In order to be good citizens, we move cache initialization earlier so > that we don't jump through a null flush_icache_range function pointer > when doing the jump label initialization. > > Signed-off-by: David Daney > --- >  arch/mips/include/asm/setup.h |    3 ++- >  arch/mips/kernel/setup.c      |    2 ++ >  arch/mips/kernel/smp.c        |    2 +- >  arch/mips/kernel/traps.c      |    9 +++++---- >  4 files changed, 10 insertions(+), 6 deletions(-) > > diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h > index 6dce6d8..2560b6b 100644 > --- a/arch/mips/include/asm/setup.h > +++ b/arch/mips/include/asm/setup.h > @@ -14,7 +14,8 @@ extern void *set_vi_handler(int n, vi_handler_t addr); > >  extern void *set_except_vector(int n, void *addr); >  extern unsigned long ebase; > -extern void per_cpu_trap_init(void); > +extern void per_cpu_trap_init(bool); > +extern void cpu_cache_init(void); > >  #endif /* __KERNEL__ */ > > diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c > index c504b21..a53f8ec 100644 > --- a/arch/mips/kernel/setup.c > +++ b/arch/mips/kernel/setup.c > @@ -605,6 +605,8 @@ void __init setup_arch(char **cmdline_p) > >        resource_init(); >        plat_smp_setup(); > + > +       cpu_cache_init(); >  } > >  unsigned long kernelsp[NR_CPUS]; > diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c > index ba9376b..dc019a1 100644 > --- a/arch/mips/kernel/smp.c > +++ b/arch/mips/kernel/smp.c > @@ -106,7 +106,7 @@ asmlinkage __cpuinit void start_secondary(void) >  #endif /* CONFIG_MIPS_MT_SMTC */ >        cpu_probe(); >        cpu_report(); > -       per_cpu_trap_init(); > +       per_cpu_trap_init(false); >        mips_clockevent_init(); >        mp_ops->init_secondary(); > > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index 2b5675b..0ba66c0 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -1538,7 +1538,6 @@ void *set_vi_handler(int n, vi_handler_t addr) >        return set_vi_srs_handler(n, addr, 0); >  } > > -extern void cpu_cache_init(void); >  extern void tlb_init(void); >  extern void flush_tlb_handlers(void); > > @@ -1565,7 +1564,7 @@ static int __init ulri_disable(char *s) >  } >  __setup("noulri", ulri_disable); > > -void __cpuinit per_cpu_trap_init(void) > +void __cpuinit per_cpu_trap_init(bool is_boot_cpu) >  { >        unsigned int cpu = smp_processor_id(); >        unsigned int status_set = ST0_CU0; > @@ -1664,7 +1663,9 @@ void __cpuinit per_cpu_trap_init(void) >  #ifdef CONFIG_MIPS_MT_SMTC >        if (bootTC) { >  #endif /* CONFIG_MIPS_MT_SMTC */ > -               cpu_cache_init(); > +               /* Boot CPU's cache setup in setup_arch(). */ > +               if (!is_boot_cpu) > +                       cpu_cache_init(); >                tlb_init(); >  #ifdef CONFIG_MIPS_MT_SMTC >        } else if (!secondaryTC) { > @@ -1741,7 +1742,7 @@ void __init trap_init(void) > >        if (board_ebase_setup) >                board_ebase_setup(); > -       per_cpu_trap_init(); > +       per_cpu_trap_init(true); > >        /* >         * Copy the generic exception handlers to their final destination. > -- > 1.7.2.3 I'm running a single-CPU, PMC-Sierra RM7035C-based system. Before applying this patch, cca_setup() in arch/mips/mm/c-r4k.c is called before coherency_setup() (called from rk4_cache_init()). After applying the patch, it is called afterwards. Because coherency_setup() relies on cca_setup() properly setting the variable cca, it won't use the value of cca supplied on the kernel command line. I haven't verified it, but I suspect the same problem will occur with the call to setcoherentio(), also in c-r4k.c. Unfortunately, I don't have the knowledge to formulate a patch to this problem, but I wanted to raise the issue. Shane McDonald From pebolle@tiscali.nl Mon Jun 11 11:36:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Jun 2012 11:36:45 +0200 (CEST) Received: from cpsmtpb-ews05.kpnxchange.com ([213.75.39.8]:1860 "EHLO cpsmtpb-ews05.kpnxchange.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903647Ab2FKJgf (ORCPT ); Mon, 11 Jun 2012 11:36:35 +0200 Received: from cpsps-ews28.kpnxchange.com ([10.94.84.194]) by cpsmtpb-ews05.kpnxchange.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 11 Jun 2012 11:36:29 +0200 Received: from CPSMTPM-TLF103.kpnxchange.com ([195.121.3.6]) by cpsps-ews28.kpnxchange.com with Microsoft SMTPSVC(7.5.7601.17514); Mon, 11 Jun 2012 11:36:29 +0200 Received: from [192.168.1.102] ([212.123.169.34]) by CPSMTPM-TLF103.kpnxchange.com with Microsoft SMTPSVC(7.5.7601.17514); Mon, 11 Jun 2012 11:36:27 +0200 Message-ID: <1339407387.30984.87.camel@x61.thuisdomein> Subject: [PATCH] MIPS: Remove unused smvp.h From: Paul Bolle To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Date: Mon, 11 Jun 2012 11:36:27 +0200 Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Content-Transfer-Encoding: 7bit Mime-Version: 1.0 X-OriginalArrivalTime: 11 Jun 2012 09:36:27.0411 (UTC) FILETIME=[AC9B1630:01CD47B5] X-RcptDomain: linux-mips.org X-archive-position: 33605 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pebolle@tiscali.nl Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1457 Lines: 45 This header was added in commit 39b8d5254246ac56342b72f812255c8f7a74dca9 ("[MIPS] Add support for MIPS CMP platform."). None of the functions it declared were ever included in the tree. The sole file that included it got removed, because that file was itself unused, in commit cb7f39d2bc5a20615d016dd86fca0fd233c13b5d ("[MIPS] Remove unused maltasmp.h."). This header is unused and unneeded. It can safely be removed. Signed-off-by: Paul Bolle --- Tested only by "git grepping" the (history of the) tree in various ways. arch/mips/include/asm/smvp.h | 19 ------------------- 1 files changed, 0 insertions(+), 19 deletions(-) delete mode 100644 arch/mips/include/asm/smvp.h diff --git a/arch/mips/include/asm/smvp.h b/arch/mips/include/asm/smvp.h deleted file mode 100644 index 0d0e80a..0000000 --- a/arch/mips/include/asm/smvp.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _ASM_SMVP_H -#define _ASM_SMVP_H - -/* - * Definitions for SMVP multitasking on MIPS MT cores - */ -struct task_struct; - -extern void smvp_smp_setup(void); -extern void smvp_smp_finish(void); -extern void smvp_boot_secondary(int cpu, struct task_struct *t); -extern void smvp_init_secondary(void); -extern void smvp_smp_finish(void); -extern void smvp_cpus_done(void); -extern void smvp_prepare_cpus(unsigned int max_cpus); - -/* This is platform specific */ -extern void smvp_send_ipi(int cpu, unsigned int action); -#endif /* _ASM_SMVP_H */ -- 1.7.7.6 From sjhill@realitydiluted.com Mon Jun 11 15:12:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Jun 2012 15:12:54 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:41085 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903647Ab2FKNMq (ORCPT ); Mon, 11 Jun 2012 15:12:46 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Se4QA-0004mj-2s; Mon, 11 Jun 2012 08:12:38 -0500 Message-ID: <4FD5EEBE.50203@realitydiluted.com> Date: Mon, 11 Jun 2012 08:12:30 -0500 From: "Steven J. Hill" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120312 Thunderbird/11.0 MIME-Version: 1.0 To: Paul Bolle CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Remove unused smvp.h References: <1339407387.30984.87.camel@x61.thuisdomein> In-Reply-To: <1339407387.30984.87.camel@x61.thuisdomein> X-Enigmail-Version: 1.4.1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-archive-position: 33606 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@realitydiluted.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 491 Lines: 17 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I have confirmed that in our older kernels and in the latest 3.X kernels that this file is indeed unused. I approve this patch. - -Steve Acked-by: Steven J. Hill -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk/V7r4ACgkQgyK5H2Ic36dCNQCfYRj7YMNnMySN0LQI2qElTJv+ jMMAnj69FxKbakspch9toWtm5IlsDLFN =GvrB -----END PGP SIGNATURE----- From ddaney.cavm@gmail.com Mon Jun 11 18:22:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Jun 2012 18:22:14 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:58231 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903695Ab2FKQWI (ORCPT ); Mon, 11 Jun 2012 18:22:08 +0200 Received: by dadm1 with SMTP id m1so6161774dad.36 for ; Mon, 11 Jun 2012 09:22:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=/QKFVyNqMaK6c7jRVl7xuFsNXkObcM5xtcVXF546BEY=; b=GsVo6d/tAbqrDKw+r/4J5Oh/NMEbRaQ538loACq4C6FHYf3Hz/JUHDIGDzHDq7WKuG kmoPKAUJ0M13qozkXXujQNdp1L71/JH3rquLeKhu3eYL4luwAohsW7YhI8UuhdBEQ+DN t0YYqQVLmazPFZ7PKGrMCmj3puu4Cy93ILCk9UorjBRrz03bmweYTlQ4VXYBFHONl9VY n/dBVGNPzEULzBeHahiKqUwSxnHY8kLBFhIQEl/giGMesT+6KqDsPjnD7gLA5+p9TU6T G+l5ysy6sw5Oq0dvr8HVNdrg7xEEezMpGuUIdUe/EjIOXcd9oumqIicaEOky8nu7i832 gqSQ== Received: by 10.68.194.6 with SMTP id hs6mr28368788pbc.133.1339431717864; Mon, 11 Jun 2012 09:21:57 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ns5sm276073pbb.26.2012.06.11.09.21.55 (version=SSLv3 cipher=OTHER); Mon, 11 Jun 2012 09:21:56 -0700 (PDT) Message-ID: <4FD61B22.3040407@gmail.com> Date: Mon, 11 Jun 2012 09:21:54 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Shane McDonald CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2 5/5] MIPS: Move cache setup to setup_arch(). References: <1337040290-16015-1-git-send-email-ddaney.cavm@gmail.com> <1337040290-16015-6-git-send-email-ddaney.cavm@gmail.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 33607 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4816 Lines: 135 On 06/10/2012 09:16 PM, Shane McDonald wrote: > I've run into a problem in linux-3.5-rc1, and I've tracked it down > to this patch, MIPS: Move cache setup to setup_arch()., > commit 6650df3c380e0db558dbfec63ed860402c6afb2a. > Are you permitted to describe the problem in any additional detail? Knowing what type of system is affected and the nature of the problem would be useful in trying to arrive at a good solution. David Daney > On Mon, May 14, 2012 at 6:04 PM, David Daney wrote: >> From: David Daney >> >> commit 97ce2c88f9ad42e3c60a9beb9fca87abf3639faa (jump-label: initialize >> jump-label subsystem much earlier) breaks MIPS. The jump_label_init() >> call was moved before trap_init() which is where we initialize >> flush_icache_range(). >> >> In order to be good citizens, we move cache initialization earlier so >> that we don't jump through a null flush_icache_range function pointer >> when doing the jump label initialization. >> >> Signed-off-by: David Daney >> --- >> arch/mips/include/asm/setup.h | 3 ++- >> arch/mips/kernel/setup.c | 2 ++ >> arch/mips/kernel/smp.c | 2 +- >> arch/mips/kernel/traps.c | 9 +++++---- >> 4 files changed, 10 insertions(+), 6 deletions(-) >> >> diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h >> index 6dce6d8..2560b6b 100644 >> --- a/arch/mips/include/asm/setup.h >> +++ b/arch/mips/include/asm/setup.h >> @@ -14,7 +14,8 @@ extern void *set_vi_handler(int n, vi_handler_t addr); >> >> extern void *set_except_vector(int n, void *addr); >> extern unsigned long ebase; >> -extern void per_cpu_trap_init(void); >> +extern void per_cpu_trap_init(bool); >> +extern void cpu_cache_init(void); >> >> #endif /* __KERNEL__ */ >> >> diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c >> index c504b21..a53f8ec 100644 >> --- a/arch/mips/kernel/setup.c >> +++ b/arch/mips/kernel/setup.c >> @@ -605,6 +605,8 @@ void __init setup_arch(char **cmdline_p) >> >> resource_init(); >> plat_smp_setup(); >> + >> + cpu_cache_init(); >> } >> >> unsigned long kernelsp[NR_CPUS]; >> diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c >> index ba9376b..dc019a1 100644 >> --- a/arch/mips/kernel/smp.c >> +++ b/arch/mips/kernel/smp.c >> @@ -106,7 +106,7 @@ asmlinkage __cpuinit void start_secondary(void) >> #endif /* CONFIG_MIPS_MT_SMTC */ >> cpu_probe(); >> cpu_report(); >> - per_cpu_trap_init(); >> + per_cpu_trap_init(false); >> mips_clockevent_init(); >> mp_ops->init_secondary(); >> >> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c >> index 2b5675b..0ba66c0 100644 >> --- a/arch/mips/kernel/traps.c >> +++ b/arch/mips/kernel/traps.c >> @@ -1538,7 +1538,6 @@ void *set_vi_handler(int n, vi_handler_t addr) >> return set_vi_srs_handler(n, addr, 0); >> } >> >> -extern void cpu_cache_init(void); >> extern void tlb_init(void); >> extern void flush_tlb_handlers(void); >> >> @@ -1565,7 +1564,7 @@ static int __init ulri_disable(char *s) >> } >> __setup("noulri", ulri_disable); >> >> -void __cpuinit per_cpu_trap_init(void) >> +void __cpuinit per_cpu_trap_init(bool is_boot_cpu) >> { >> unsigned int cpu = smp_processor_id(); >> unsigned int status_set = ST0_CU0; >> @@ -1664,7 +1663,9 @@ void __cpuinit per_cpu_trap_init(void) >> #ifdef CONFIG_MIPS_MT_SMTC >> if (bootTC) { >> #endif /* CONFIG_MIPS_MT_SMTC */ >> - cpu_cache_init(); >> + /* Boot CPU's cache setup in setup_arch(). */ >> + if (!is_boot_cpu) >> + cpu_cache_init(); >> tlb_init(); >> #ifdef CONFIG_MIPS_MT_SMTC >> } else if (!secondaryTC) { >> @@ -1741,7 +1742,7 @@ void __init trap_init(void) >> >> if (board_ebase_setup) >> board_ebase_setup(); >> - per_cpu_trap_init(); >> + per_cpu_trap_init(true); >> >> /* >> * Copy the generic exception handlers to their final destination. >> -- >> 1.7.2.3 > > I'm running a single-CPU, PMC-Sierra RM7035C-based system. > > Before applying this patch, cca_setup() in arch/mips/mm/c-r4k.c > is called before coherency_setup() (called from rk4_cache_init()). > After applying the patch, it is called afterwards. Because > coherency_setup() relies on cca_setup() properly setting the > variable cca, it won't use the value of cca supplied on the > kernel command line. > > I haven't verified it, but I suspect the same problem will occur > with the call to setcoherentio(), also in c-r4k.c. > > Unfortunately, I don't have the knowledge to formulate a patch > to this problem, but I wanted to raise the issue. > > Shane McDonald > From ddaney.cavm@gmail.com Mon Jun 11 18:39:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Jun 2012 18:39:31 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:56495 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903691Ab2FKQjZ (ORCPT ); Mon, 11 Jun 2012 18:39:25 +0200 Received: by pbbrq13 with SMTP id rq13so6371782pbb.36 for ; Mon, 11 Jun 2012 09:39:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=QzFOTJJ4hbcRSW1my/7hUKMNZuea2njFJJopNQ05E7A=; b=LNQniiSizxYwE/3E/J09W/H+eA+Af8Qzturnk0m36KDjX7F0AiNDuuJ4mEzJKJk14K NnEJCbK3J4QHIO/px1St2d4jXPzO2iNh26r+JSH84eD7bm+I9jiVsuJvjdZz0d8CN4iR 4tQXg3X71Ui9eh8OydBoe97IDsgiwSR22znA6NiH2os+TSyn+ksHUxwuV0xzgwornG2g 8zdfx15msVDVTK59vU7iRR9BkFAs6pNpWbFEm2Hky5NFxsZUFQijiRIE/jwm6+j9g5hw CHSKSCxnl06iYlEblr1R5JpqpsFLimwyj3dhXIb3fsURftUZsmoK5ku392ldtUaDNIH6 kWIg== Received: by 10.68.228.102 with SMTP id sh6mr27634241pbc.134.1339432759084; Mon, 11 Jun 2012 09:39:19 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id mt9sm18989780pbb.14.2012.06.11.09.39.17 (version=SSLv3 cipher=OTHER); Mon, 11 Jun 2012 09:39:18 -0700 (PDT) Message-ID: <4FD61F35.1080103@gmail.com> Date: Mon, 11 Jun 2012 09:39:17 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Shane McDonald CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2 5/5] MIPS: Move cache setup to setup_arch(). References: <1337040290-16015-1-git-send-email-ddaney.cavm@gmail.com> <1337040290-16015-6-git-send-email-ddaney.cavm@gmail.com> <4FD61B22.3040407@gmail.com> In-Reply-To: <4FD61B22.3040407@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 33608 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1269 Lines: 39 On 06/11/2012 09:21 AM, David Daney wrote: > On 06/10/2012 09:16 PM, Shane McDonald wrote: >> I've run into a problem in linux-3.5-rc1, and I've tracked it down >> to this patch, MIPS: Move cache setup to setup_arch()., >> commit 6650df3c380e0db558dbfec63ed860402c6afb2a. >> > > Are you permitted to describe the problem in any additional detail? > > Knowing what type of system is affected and the nature of the problem > would be useful in trying to arrive at a good solution. > OK, for some reason I missed this bit... [...] >> >> I'm running a single-CPU, PMC-Sierra RM7035C-based system. >> >> Before applying this patch, cca_setup() in arch/mips/mm/c-r4k.c >> is called before coherency_setup() (called from rk4_cache_init()). >> After applying the patch, it is called afterwards. Because >> coherency_setup() relies on cca_setup() properly setting the >> variable cca, it won't use the value of cca supplied on the >> kernel command line. >> >> I haven't verified it, but I suspect the same problem will occur >> with the call to setcoherentio(), also in c-r4k.c. >> >> Unfortunately, I don't have the knowledge to formulate a patch >> to this problem, but I wanted to raise the issue. >> >> Shane McDonald >> > I will think about how to fix it. David Daney From mcdonald.shane@gmail.com Mon Jun 11 20:32:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Jun 2012 20:32:27 +0200 (CEST) Received: from mail-gg0-f177.google.com ([209.85.161.177]:44303 "EHLO mail-gg0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903657Ab2FKScU (ORCPT ); Mon, 11 Jun 2012 20:32:20 +0200 Received: by ggcs5 with SMTP id s5so3083111ggc.36 for ; Mon, 11 Jun 2012 11:32:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=39vOQUTcXt9ud77ak9CS4wCjWwz0LQA8vdKprK3pBXg=; b=zMvhH2LuHCKX0mOMf8r82O1FcloaKg59P8h1h+V5ScAkhlqcXnyt1o/c5S8oO7TTpQ U0ZaXuoeBco28uhO0W8Xx0GRYInDxWJpxJDb2awsGrce4tiucnxh0sForzRBU72Uedqv 9K6z4R+lG/is2WgUCxZ/26FWZTBrsITxnNemglgFwh95HIE3quIK/73x3S9S6hLlPsRd XlQyaUl4FPIMWAVcSIiEiS8uVVm6VOLocvhEBJTcz151YUXBllewL/r77dUNwwBfv5dP zmIAwzitrZvjukIVfz6mUC0dIW8GN4+H6MBz/zI6Lm5NfP8xNVDdPTcIvvqduNrWWumg UGig== MIME-Version: 1.0 Received: by 10.50.10.164 with SMTP id j4mr7068347igb.13.1339439533885; Mon, 11 Jun 2012 11:32:13 -0700 (PDT) Received: by 10.231.219.5 with HTTP; Mon, 11 Jun 2012 11:32:13 -0700 (PDT) In-Reply-To: <4FD61F35.1080103@gmail.com> References: <1337040290-16015-1-git-send-email-ddaney.cavm@gmail.com> <1337040290-16015-6-git-send-email-ddaney.cavm@gmail.com> <4FD61B22.3040407@gmail.com> <4FD61F35.1080103@gmail.com> Date: Mon, 11 Jun 2012 12:32:13 -0600 Message-ID: Subject: Re: [PATCH v2 5/5] MIPS: Move cache setup to setup_arch(). From: Shane McDonald To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33609 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4223 Lines: 135 Hi David: A little more info, if it's useful... On Mon, Jun 11, 2012 at 10:39 AM, David Daney wrote: >>> I've run into a problem in linux-3.5-rc1, and I've tracked it down >>> to this patch, MIPS: Move cache setup to setup_arch()., >>> commit 6650df3c380e0db558dbfec63ed860402c6afb2a. >>> >> >> Are you permitted to describe the problem in any additional detail? >> >> Knowing what type of system is affected and the nature of the problem >> would be useful in trying to arrive at a good solution. > >>> I'm running a single-CPU, PMC-Sierra RM7035C-based system. >>> >>> Before applying this patch, cca_setup() in arch/mips/mm/c-r4k.c >>> is called before coherency_setup() (called from rk4_cache_init()). >>> After applying the patch, it is called afterwards. Because >>> coherency_setup() relies on cca_setup() properly setting the >>> variable cca, it won't use the value of cca supplied on the >>> kernel command line. >>> >>> I haven't verified it, but I suspect the same problem will occur >>> with the call to setcoherentio(), also in c-r4k.c. >>> >>> Unfortunately, I don't have the knowledge to formulate a patch >>> to this problem, but I wanted to raise the issue. The board is the PMC-Sierra "Xiao Hu", described at http://www.linuxjournal.com/article/7854. The version I have has the 600 MHz RM7035C processor. The code supporting the board is not in-tree, unfortunately. I believe PMC-Sierra is no longer maintaining their BSP, but I've been keeping a copy of the kernel code up-to-date. Here is the info on the processor reported by PMON: CPU type RM7065. Rev 5.3. 600 MHz/100 MHz. Memory size 128 MB. Icache size 16 KB, 32/line (4 way) Dcache size 16 KB, 32/line (4 way) Scache size 256 KB, 32/line (4 way) I typically boot with the command-line options: root=/dev/hda1 cca=3 CPU information displayed upon booting is: CPU revision is: 00002753 (RM7000) FPU revision is: 00002750 Cache information displayed upon booting is: Primary instruction cache 16kB, VIPT, 4-way, linesize 32 bytes. Primary data cache 16kB, 4-way, VIPT, no aliases, linesize 32 bytes Secondary cache size 256K, linesize 32 bytes. Here are some snippets from the .config file (I've removed lines that are probably irrelevant to this problem): CONFIG_PMC_XIAOHU=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y CONFIG_CSRC_R4K_LIB=y CONFIG_CSRC_R4K=y # CONFIG_ARCH_DMA_ADDR_T_64BIT is not set CONFIG_DMA_NONCOHERENT=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # CONFIG_CPU_RM7000=y CONFIG_SYS_HAS_CPU_RM7000=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y # # Kernel type # CONFIG_32BIT=y # CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_BOARD_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set After adding in some debugging statements, I see that after applying the subject patch, coherency_setup() is called before cca_setup() is called. Before applying the patch, coherency_setup() is called after cca_setup(). cca_setup() grabs the value of the cca= command line parameter, and stores it in the variable cca. If no such command line parameter is given, cca uses its default value of -1. coherency_setup() then uses the cca variable when setting up the coherency mode. that value > I will think about how to fix it. > > David Daney Thanks. There is a line: __setup("cca=", cca_setup); that seems to be used to call cca_setup(). I don't know how the __setup() works, so I'm a little lost on the solution myself. Note that, besides the cca_setup(), there is also a routine setcoherentio() that is defined the same way as cca_setup(). I suspect that suffers from the same problem as cca_setup(). If there is any other information I can provide, please let me know! Thanks. Shane McDonald From jonas.gorski@gmail.com Tue Jun 12 10:24:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 10:24:42 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:54586 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903616Ab2FLIYe (ORCPT ); Tue, 12 Jun 2012 10:24:34 +0200 Received: by bkwj4 with SMTP id j4so5334449bkw.36 for ; Tue, 12 Jun 2012 01:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=WyRcAx28Hn24N1KAG0Ne6zk9GJALZB3eYj8ac0bOmq8=; b=kwPqZEuV/JIO7QbQYqcMoCmGjqiJGEQuVnEvNHsLBfh9b/QffMgSqA49Fk+i3FxLkd ElTEoNdfl8UHp01dPQyCTNHf79YWiobun9h8yorMc0yw1NKuzOebSR6Qk3SF/dtSoOPS u9rZW0LIANeKOazGNFS8SnPxr9IXb1ehhiKIBMptcC5tMFIAj/X8VDhl+fjBUR53m9J3 v2qbyg32noKhcO/H39eACNmWhWhpkiAfKi5zHfH0qkm3WuxSMIBJjvjIGlSxOidBiS4o 46AwkOf21UodQy3XDptHcVZaZUt8SaFnoCW7YSfb4WcZ/a+XY3Zqtafrr8VSbAJHi9yu aY9Q== Received: by 10.204.157.23 with SMTP id z23mr11608226bkw.71.1339489469446; Tue, 12 Jun 2012 01:24:29 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-055-195.pools.arcor-ip.net. [88.73.55.195]) by mx.google.com with ESMTPS id h18sm19177912bkh.8.2012.06.12.01.24.27 (version=SSLv3 cipher=OTHER); Tue, 12 Jun 2012 01:24:28 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Kevin Cernekee Subject: [PATCH 0/8] Add basic support for BCM6328 Date: Tue, 12 Jun 2012 10:23:37 +0200 Message-Id: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 33610 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2638 Lines: 55 This patchset adds basic support for BCM6328 and its PCIe port. The BCM6328 is an ADSL2+ SoC with support for NAND and SPI flash, integrated five port ethernet switch, and one PCIe port. Patches 1 and 2 add generic flash type detection, as different chips support different flash types, and the BCM6328 does not support parallel CFI flashes. Patches 3-4 add support for detecting and handling the BCM6328 itself. This allows booting to command line. Patches 5-7 add support for the PCIe port of the BCM6328 and expose the PCIe port driver for MIPS (I wonder what is so special about it that it isn't included in the standard PCI drivers). Patch 8 then adds a 6328 reference board definition, so one can actually boot to command line. Jonas Gorski (8): MIPS: BCM63XX: move flash registration out of board_bcm963xx.c MIPS: BCM63XX: add flash type detection MIPS: BCM63XX: use the Chip ID register for identifying the SoC MIPS: BCM63XX: add basic BCM6328 CPU support MIPS: BCM63XX: Move the PCI initialization into its own function MIPS: BCM63XX: Add PCIe Support for BCM6328 MIPS: expose PCIe drivers for MIPS MIPS: BCM63XX: add 96328avng reference board arch/mips/Kconfig | 2 + arch/mips/bcm63xx/Kconfig | 4 + arch/mips/bcm63xx/Makefile | 4 +- arch/mips/bcm63xx/boards/board_bcm963xx.c | 106 ++++++++-------- arch/mips/bcm63xx/cpu.c | 63 ++++++++-- arch/mips/bcm63xx/dev-flash.c | 123 ++++++++++++++++++ arch/mips/bcm63xx/dev-spi.c | 2 +- arch/mips/bcm63xx/irq.c | 21 +++ arch/mips/bcm63xx/prom.c | 4 +- arch/mips/bcm63xx/setup.c | 13 ++- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 120 +++++++++++++++++- .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 12 ++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 8 ++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 117 +++++++++++++++++ arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + arch/mips/pci/ops-bcm63xx.c | 61 +++++++++ arch/mips/pci/pci-bcm63xx.c | 133 +++++++++++++++++++- arch/mips/pci/pci-bcm63xx.h | 5 + 19 files changed, 729 insertions(+), 72 deletions(-) create mode 100644 arch/mips/bcm63xx/dev-flash.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h -- 1.7.2.5 From jonas.gorski@gmail.com Tue Jun 12 10:24:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 10:25:15 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:54586 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903618Ab2FLIYg (ORCPT ); Tue, 12 Jun 2012 10:24:36 +0200 Received: by mail-bk0-f49.google.com with SMTP id j4so5334449bkw.36 for ; Tue, 12 Jun 2012 01:24:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=hLfvLg5B53OwPVburhNT1DE3M90UvLx1tvb8f4AaZ9w=; b=vEeCP7h2MH/WhTBwqx2Huyr+2kwwyg3YF0Bi2OBRYu0VP3ehwJ0yJmXvgTnvLSlHQX Jdh/rhO/6LVUPczQ6kvw5gbOc1SHwt1+eHQurgOr3qEGph+eOvXjQ5x5oCcPhkjCVEUV 5+QFfxULKrHTbGMtZYN99RHeLmZMgrhw0fKn4jK5urC4bAPJJCHmC0nYdt0QIAInrzQ4 dZ10LoR8KpRHoeD7Ij6r4mTRyVuvVGg899Xk6K+XKgJd86yOrefE92Exjc4JhnH2bNIx IIpvyhASSCMbbPa4JsU58bsO+CF+YoNNTyqr/x+n4rkVSlXfaBtn6nRJ1WpH3bGZuOsf J+4Q== Received: by 10.204.157.23 with SMTP id z23mr11608341bkw.71.1339489476096; Tue, 12 Jun 2012 01:24:36 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-055-195.pools.arcor-ip.net. [88.73.55.195]) by mx.google.com with ESMTPS id h18sm19177912bkh.8.2012.06.12.01.24.34 (version=SSLv3 cipher=OTHER); Tue, 12 Jun 2012 01:24:35 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Kevin Cernekee Subject: [PATCH 4/8] MIPS: BCM63XX: add basic BCM6328 CPU support Date: Tue, 12 Jun 2012 10:23:41 +0200 Message-Id: <1339489425-19037-5-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> References: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33611 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 20830 Lines: 608 Add basic BCM6328 support. This includes CPU speed, memory size detection and working uart, but no support for attached flashes, lacking the appropriate drivers. Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/Kconfig | 3 + arch/mips/bcm63xx/boards/board_bcm963xx.c | 12 ++- arch/mips/bcm63xx/cpu.c | 43 ++++++++ arch/mips/bcm63xx/dev-flash.c | 6 + arch/mips/bcm63xx/dev-spi.c | 2 +- arch/mips/bcm63xx/irq.c | 21 ++++ arch/mips/bcm63xx/prom.c | 4 +- arch/mips/bcm63xx/setup.c | 13 ++- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 111 ++++++++++++++++++++- arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 54 ++++++++++ arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + 13 files changed, 265 insertions(+), 9 deletions(-) diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig index 6b1b9ad..09e93ca 100644 --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -1,6 +1,9 @@ menu "CPU support" depends on BCM63XX +config BCM63XX_CPU_6328 + bool "support 6328 CPU" + config BCM63XX_CPU_6338 bool "support 6338 CPU" select HW_HAS_PCI diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index bdfbdf9..be7498a 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -708,9 +708,15 @@ void __init board_prom_init(void) char cfe_version[32]; u32 val; - /* read base address of boot chip select (0) */ - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; + /* read base address of boot chip select (0) + * 6328 does not have MPI but boots from a fixed address + */ + if (BCMCPU_IS_6328()) + val = 0x18000000; + else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + } boot_addr = (u8 *)KSEG1ADDR(val); /* dump cfe version */ diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index e3c1da5..a7afb28 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev; static unsigned int bcm63xx_cpu_freq; static unsigned int bcm63xx_memory_size; +static const unsigned long bcm6328_regs_base[] = { + __GEN_CPU_REGS_TABLE(6328) +}; + +static const int bcm6328_irqs[] = { + __GEN_CPU_IRQ_TABLE(6328) +}; + static const unsigned long bcm6338_regs_base[] = { __GEN_CPU_REGS_TABLE(6338) }; @@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(void) static unsigned int detect_cpu_clock(void) { switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + { + unsigned int tmp, mips_pll_fcvo; + + tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG); + mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK) + >> STRAPBUS_6328_FCVO_SHIFT; + + switch (mips_pll_fcvo) { + case 0x12: + case 0x14: + case 0x19: + return 160000000; + case 0x1c: + return 192000000; + case 0x13: + case 0x15: + return 200000000; + case 0x1a: + return 384000000; + case 0x16: + return 400000000; + default: + return 320000000; + } + + } case BCM6338_CPU_ID: /* BCM6338 has a fixed 240 Mhz frequency */ return 240000000; @@ -170,6 +205,9 @@ static unsigned int detect_memory_size(void) unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; u32 val; + if (BCMCPU_IS_6328()) + return bcm_ddr_readl(DDR_CSEND_REG) << 24; + if (BCMCPU_IS_6345()) { val = bcm_sdram_readl(SDRAM_MBASE_REG); return (val * 8 * 1024 * 1024); @@ -237,6 +275,11 @@ void __init bcm63xx_cpu_init(void) u16 chip_id = bcm_readw(BCM_6368_PERF_BASE); switch (chip_id) { + case BCM6328_CPU_ID: + expected_cpu_id = BCM6328_CPU_ID; + bcm63xx_regs_base = bcm6328_regs_base; + bcm63xx_irqs = bcm6328_irqs; + break; case BCM6368_CPU_ID: expected_cpu_id = BCM6368_CPU_ID; bcm63xx_regs_base = bcm6368_regs_base; diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c index 1051fae..58371c7 100644 --- a/arch/mips/bcm63xx/dev-flash.c +++ b/arch/mips/bcm63xx/dev-flash.c @@ -60,6 +60,12 @@ static int __init bcm63xx_detect_flash_type(void) u32 val; switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); + if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else + return BCM63XX_FLASH_TYPE_NAND; case BCM6338_CPU_ID: case BCM6345_CPU_ID: case BCM6348_CPU_ID: diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c index 67fa45b..e39f730 100644 --- a/arch/mips/bcm63xx/dev-spi.c +++ b/arch/mips/bcm63xx/dev-spi.c @@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void) { struct clk *periph_clk; - if (BCMCPU_IS_6345()) + if (BCMCPU_IS_6328() || BCMCPU_IS_6345()) return -ENODEV; periph_clk = clk_get(NULL, "periph"); diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 9a216a4..18e051a 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #ifndef BCMCPU_RUNTIME_DETECT +#ifdef CONFIG_BCM63XX_CPU_6328 +#define irq_stat_reg PERF_IRQSTAT_6328_REG +#define irq_mask_reg PERF_IRQMASK_6328_REG +#define irq_bits 64 +#define is_ext_irq_cascaded 1 +#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE) +#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE) +#define ext_irq_count 4 +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328 +#define ext_irq_cfg_reg2 0 +#endif #ifdef CONFIG_BCM63XX_CPU_6338 #define irq_stat_reg PERF_IRQSTAT_6338_REG #define irq_mask_reg PERF_IRQMASK_6338_REG @@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void) irq_mask_addr = bcm63xx_regset_address(RSET_PERF); switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6328_REG; + irq_mask_addr += PERF_IRQMASK_6328_REG; + irq_bits = 64; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; + ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; + ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; + break; case BCM6338_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6338_REG; irq_mask_addr += PERF_IRQMASK_6338_REG; diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index 99d7f40..10eaff4 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -26,7 +26,9 @@ void __init prom_init(void) bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); /* disable all hardware blocks clock for now */ - if (BCMCPU_IS_6338()) + if (BCMCPU_IS_6328()) + mask = CKCTL_6328_ALL_SAFE_EN; + else if (BCMCPU_IS_6338()) mask = CKCTL_6338_ALL_SAFE_EN; else if (BCMCPU_IS_6345()) mask = CKCTL_6345_ALL_SAFE_EN; diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index 356b055..0e74a13 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void) /* mask and clear all external irq */ switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; + break; case BCM6338_CPU_ID: perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; break; @@ -95,9 +98,13 @@ void bcm63xx_machine_reboot(void) bcm6348_a1_reboot(); printk(KERN_INFO "triggering watchdog soft-reset...\n"); - reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); - reg |= SYS_PLL_SOFT_RESET; - bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); + if (BCMCPU_IS_6328()) { + bcm_wdt_writel(1, WDT_SOFTRESET_REG); + } else { + reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); + reg |= SYS_PLL_SOFT_RESET; + bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); + } while (1) ; } diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 0c981aa..b842b6d 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -9,6 +9,7 @@ * compile time if only one CPU support is enabled (idea stolen from * arm mach-types) */ +#define BCM6328_CPU_ID 0x6328 #define BCM6338_CPU_ID 0x6338 #define BCM6345_CPU_ID 0x6345 #define BCM6348_CPU_ID 0x6348 @@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void); u16 bcm63xx_get_cpu_rev(void); unsigned int bcm63xx_get_cpu_freq(void); +#ifdef CONFIG_BCM63XX_CPU_6328 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM6328_CPU_ID +# endif +# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) +#else +# define BCMCPU_IS_6328() (0) +#endif + #ifdef CONFIG_BCM63XX_CPU_6338 # ifdef bcm63xx_get_cpu_id # undef bcm63xx_get_cpu_id @@ -129,7 +143,8 @@ enum bcm63xx_regs_set { RSET_PCMDMA, RSET_PCMDMAC, RSET_PCMDMAS, - RSET_RNG + RSET_RNG, + RSET_MISC }; #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) @@ -156,6 +171,49 @@ enum bcm63xx_regs_set { #define RSET_RNG_SIZE 20 /* + * 6328 register sets base address + */ +#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) +#define BCM_6328_PERF_BASE (0xb0000000) +#define BCM_6328_TIMER_BASE (0xb0000040) +#define BCM_6328_WDT_BASE (0xb000005c) +#define BCM_6328_UART0_BASE (0xb0000100) +#define BCM_6328_UART1_BASE (0xb0000120) +#define BCM_6328_GPIO_BASE (0xb0000080) +#define BCM_6328_SPI_BASE (0xdeadbeef) +#define BCM_6328_UDC0_BASE (0xdeadbeef) +#define BCM_6328_USBDMA_BASE (0xdeadbeef) +#define BCM_6328_OHCI0_BASE (0xdeadbeef) +#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) +#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6328_MPI_BASE (0xdeadbeef) +#define BCM_6328_PCMCIA_BASE (0xdeadbeef) +#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef) +#define BCM_6328_DSL_BASE (0xb0001900) +#define BCM_6328_UBUS_BASE (0xdeadbeef) +#define BCM_6328_ENET0_BASE (0xdeadbeef) +#define BCM_6328_ENET1_BASE (0xdeadbeef) +#define BCM_6328_ENETDMA_BASE (0xb000d800) +#define BCM_6328_ENETDMAC_BASE (0xb000da00) +#define BCM_6328_ENETDMAS_BASE (0xb000dc00) +#define BCM_6328_ENETSW_BASE (0xb0e00000) +#define BCM_6328_EHCI0_BASE (0x10002500) +#define BCM_6328_SDRAM_BASE (0xdeadbeef) +#define BCM_6328_MEMC_BASE (0xdeadbeef) +#define BCM_6328_DDR_BASE (0xb0003000) +#define BCM_6328_M2M_BASE (0xdeadbeef) +#define BCM_6328_ATM_BASE (0xdeadbeef) +#define BCM_6328_XTM_BASE (0xdeadbeef) +#define BCM_6328_XTMDMA_BASE (0xb000b800) +#define BCM_6328_XTMDMAC_BASE (0xdeadbeef) +#define BCM_6328_XTMDMAS_BASE (0xdeadbeef) +#define BCM_6328_PCM_BASE (0xb000a800) +#define BCM_6328_PCMDMA_BASE (0xdeadbeef) +#define BCM_6328_PCMDMAC_BASE (0xdeadbeef) +#define BCM_6328_PCMDMAS_BASE (0xdeadbeef) +#define BCM_6328_RNG_BASE (0xdeadbeef) +#define BCM_6328_MISC_BASE (0xb0001800) +/* * 6338 register sets base address */ #define BCM_6338_DSL_LMEM_BASE (0xfff00000) @@ -198,6 +256,7 @@ enum bcm63xx_regs_set { #define BCM_6338_PCMDMAC_BASE (0xdeadbeef) #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) #define BCM_6338_RNG_BASE (0xdeadbeef) +#define BCM_6338_MISC_BASE (0xdeadbeef) /* * 6345 register sets base address @@ -242,6 +301,7 @@ enum bcm63xx_regs_set { #define BCM_6345_PCMDMAC_BASE (0xdeadbeef) #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) #define BCM_6345_RNG_BASE (0xdeadbeef) +#define BCM_6345_MISC_BASE (0xdeadbeef) /* * 6348 register sets base address @@ -283,6 +343,7 @@ enum bcm63xx_regs_set { #define BCM_6348_PCMDMAC_BASE (0xdeadbeef) #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) #define BCM_6348_RNG_BASE (0xdeadbeef) +#define BCM_6348_MISC_BASE (0xdeadbeef) /* * 6358 register sets base address @@ -324,6 +385,7 @@ enum bcm63xx_regs_set { #define BCM_6358_PCMDMAC_BASE (0xfffe1900) #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) #define BCM_6358_RNG_BASE (0xdeadbeef) +#define BCM_6358_MISC_BASE (0xdeadbeef) /* @@ -366,6 +428,7 @@ enum bcm63xx_regs_set { #define BCM_6368_PCMDMAC_BASE (0xb0005a00) #define BCM_6368_PCMDMAS_BASE (0xb0005c00) #define BCM_6368_RNG_BASE (0xb0004180) +#define BCM_6368_MISC_BASE (0xdeadbeef) extern const unsigned long *bcm63xx_regs_base; @@ -412,6 +475,7 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, PCMDMAC) \ __GEN_RSET_BASE(__cpu, PCMDMAS) \ __GEN_RSET_BASE(__cpu, RNG) \ + __GEN_RSET_BASE(__cpu, MISC) \ } #define __GEN_CPU_REGS_TABLE(__cpu) \ @@ -451,6 +515,7 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ + [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) @@ -458,6 +523,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) #ifdef BCMCPU_RUNTIME_DETECT return bcm63xx_regs_base[set]; #else +#ifdef CONFIG_BCM63XX_CPU_6328 + __GEN_RSET(6328) +#endif #ifdef CONFIG_BCM63XX_CPU_6338 __GEN_RSET(6338) #endif @@ -512,6 +580,47 @@ enum bcm63xx_irq { }; /* + * 6328 irqs + */ +#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) + +#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) +#define BCM_6328_SPI_IRQ 0 +#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28) +#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) +#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6328_UDC0_IRQ 0 +#define BCM_6328_ENET0_IRQ 0 +#define BCM_6328_ENET1_IRQ 0 +#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) +#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) +#define BCM_6328_PCMCIA_IRQ 0 +#define BCM_6328_ENET0_RXDMA_IRQ 0 +#define BCM_6328_ENET0_TXDMA_IRQ 0 +#define BCM_6328_ENET1_RXDMA_IRQ 0 +#define BCM_6328_ENET1_TXDMA_IRQ 0 +#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23) +#define BCM_6328_ATM_IRQ 0 +#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0) +#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1) +#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2) +#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3) +#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4) +#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5) +#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6) +#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) +#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31) +#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11) + +#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) +#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) +#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) +#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) +#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) + +/* * 6338 irqs */ #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 1d7dd96..0a9891f 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void); static inline unsigned long bcm63xx_gpio_count(void) { switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + return 32; case BCM6358_CPU_ID: return 40; case BCM6338_CPU_ID: diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h index 72477a6..6dcd8b2 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h @@ -91,5 +91,7 @@ #define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o)) #define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o)) #define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o)) +#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o)) +#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o)) #endif /* ! BCM63XX_IO_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 849fd97..4fc2ab2 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -15,6 +15,30 @@ /* Clock Control register */ #define PERF_CKCTL_REG 0x4 +#define CKCTL_6328_PHYMIPS_EN (1 << 0) +#define CKCTL_6328_ADSL_QPROC_EN (1 << 1) +#define CKCTL_6328_ADSL_AFE_EN (1 << 2) +#define CKCTL_6328_ADSL_EN (1 << 3) +#define CKCTL_6328_MIPS_EN (1 << 4) +#define CKCTL_6328_SAR_EN (1 << 5) +#define CKCTL_6328_PCM_EN (1 << 6) +#define CKCTL_6328_USBD_EN (1 << 7) +#define CKCTL_6328_USBH_EN (1 << 8) +#define CKCTL_6328_HSSPI_EN (1 << 9) +#define CKCTL_6328_PCIE_EN (1 << 10) +#define CKCTL_6328_ROBOSW_EN (1 << 11) + +#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \ + CKCTL_6328_ADSL_QPROC_EN | \ + CKCTL_6328_ADSL_AFE_EN | \ + CKCTL_6328_ADSL_EN | \ + CKCTL_6328_SAR_EN | \ + CKCTL_6328_PCM_EN | \ + CKCTL_6328_USBD_EN | \ + CKCTL_6328_USBH_EN | \ + CKCTL_6328_ROBOSW_EN | \ + CKCTL_6328_PCIE_EN) + #define CKCTL_6338_ADSLPHY_EN (1 << 0) #define CKCTL_6338_MPI_EN (1 << 1) #define CKCTL_6338_DRAM_EN (1 << 2) @@ -119,6 +143,7 @@ #define SYS_PLL_SOFT_RESET 0x1 /* Interrupt Mask register */ +#define PERF_IRQMASK_6328_REG 0x20 #define PERF_IRQMASK_6338_REG 0xc #define PERF_IRQMASK_6345_REG 0xc #define PERF_IRQMASK_6348_REG 0xc @@ -126,6 +151,7 @@ #define PERF_IRQMASK_6368_REG 0x20 /* Interrupt Status register */ +#define PERF_IRQSTAT_6328_REG 0x28 #define PERF_IRQSTAT_6338_REG 0x10 #define PERF_IRQSTAT_6345_REG 0x10 #define PERF_IRQSTAT_6348_REG 0x10 @@ -133,6 +159,7 @@ #define PERF_IRQSTAT_6368_REG 0x28 /* External Interrupt Configuration register */ +#define PERF_EXTIRQ_CFG_REG_6328 0x18 #define PERF_EXTIRQ_CFG_REG_6338 0x14 #define PERF_EXTIRQ_CFG_REG_6348 0x14 #define PERF_EXTIRQ_CFG_REG_6358 0x14 @@ -162,8 +189,21 @@ /* Soft Reset register */ #define PERF_SOFTRESET_REG 0x28 +#define PERF_SOFTRESET_6328_REG 0x10 #define PERF_SOFTRESET_6368_REG 0x10 +#define SOFTRESET_6328_SPI_MASK (1 << 0) +#define SOFTRESET_6328_EPHY_MASK (1 << 1) +#define SOFTRESET_6328_SAR_MASK (1 << 2) +#define SOFTRESET_6328_ENETSW_MASK (1 << 3) +#define SOFTRESET_6328_USBS_MASK (1 << 4) +#define SOFTRESET_6328_USBH_MASK (1 << 5) +#define SOFTRESET_6328_PCM_MASK (1 << 6) +#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7) +#define SOFTRESET_6328_PCIE_MASK (1 << 8) +#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9) +#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10) + #define SOFTRESET_6338_SPI_MASK (1 << 0) #define SOFTRESET_6338_ENET_MASK (1 << 2) #define SOFTRESET_6338_USBH_MASK (1 << 3) @@ -307,6 +347,8 @@ /* Watchdog reset length register */ #define WDT_RSTLEN_REG 0x8 +/* Watchdog soft reset register (BCM6328 only) */ +#define WDT_SOFTRESET_REG 0xc /************************************************************************* * _REG relative to RSET_UARTx @@ -933,6 +975,8 @@ * _REG relative to RSET_DDR *************************************************************************/ +#define DDR_CSEND_REG 0x8 + #define DDR_DMIPSPLLCFG_REG 0x18 #define DMIPSPLLCFG_M1_SHIFT 0 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) @@ -1115,4 +1159,14 @@ #define SPI_SSOFFTIME_SHIFT 3 #define SPI_BYTE_SWAP 0x80 +/************************************************************************* + * _REG relative to RSET_MISC + *************************************************************************/ + +#define MISC_STRAPBUS_6328_REG 0x240 +#define STRAPBUS_6328_FCVO_SHIFT 7 +#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) +#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) +#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28) + #endif /* BCM63XX_REGS_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h index ef94ba7..30931c4 100644 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h @@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset) if (offset >= 0xfff00000) return 1; break; + case BCM6328_CPU_ID: case BCM6368_CPU_ID: if (offset >= 0xb0000000 && offset < 0xb1000000) return 1; -- 1.7.2.5 From jonas.gorski@gmail.com Tue Jun 12 10:24:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 10:25:50 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:50801 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903628Ab2FLIYg (ORCPT ); Tue, 12 Jun 2012 10:24:36 +0200 Received: by bkwj4 with SMTP id j4so5334465bkw.36 for ; Tue, 12 Jun 2012 01:24:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=zBIccyE69e+ociGWzUgmv4LjBXudJW6x9lFy0JdM9AQ=; b=EbfTTyI4Ur0pkpwz7UpM+PsRwEuI3RppB9y3LB219HnwErqDh/CnFpK4nRQFCNHSfq rNj32b3gCLw5rxC8gVIDssIG/tYerFBXg69ou/Bed073C/fLaHXqw7VIiO9hLyzIAdQD PMEnnb6z73Q6//NU7hVEHfx7S6cnLIGKxkKgJAL8+kBrBvIdwOx3Uw+8Kedft6GM4OEE 5qf6IQfw1M276NLxsYMsQw0dCUHUMRLK4N59z+Bos7HCD5G0zuSNUDYbPdip0BqvM8kw tstP2TvFEb47rsCwoVMuOfegQadaHW0sohy2ud5jD44gZnMDI+VKzHWg8EWILqSESYfS KWvg== Received: by 10.204.145.78 with SMTP id c14mr11231615bkv.43.1339489471045; Tue, 12 Jun 2012 01:24:31 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-055-195.pools.arcor-ip.net. [88.73.55.195]) by mx.google.com with ESMTPS id h18sm19177912bkh.8.2012.06.12.01.24.29 (version=SSLv3 cipher=OTHER); Tue, 12 Jun 2012 01:24:30 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Kevin Cernekee Subject: [PATCH 1/8] MIPS: BCM63XX: move flash registration out of board_bcm963xx.c Date: Tue, 12 Jun 2012 10:23:38 +0200 Message-Id: <1339489425-19037-2-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> References: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33612 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 5651 Lines: 203 board_bcm963xx.c is already large enough. Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/Makefile | 4 +- arch/mips/bcm63xx/boards/board_bcm963xx.c | 49 +------------- arch/mips/bcm63xx/dev-flash.c | 69 ++++++++++++++++++++ .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 6 ++ 4 files changed, 79 insertions(+), 49 deletions(-) create mode 100644 arch/mips/bcm63xx/dev-flash.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index 349b206..833af72 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,6 +1,6 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ - dev-dsp.o dev-enet.o dev-pcmcia.o dev-rng.o dev-spi.o \ - dev-uart.o dev-wdt.o + dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \ + dev-spi.o dev-uart.o dev-wdt.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index ea65c0f..bdfbdf9 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -11,9 +11,6 @@ #include #include #include -#include -#include -#include #include #include #include @@ -24,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -809,40 +807,6 @@ void __init board_setup(void) panic("unexpected CPU for bcm963xx board"); } -static struct mtd_partition mtd_partitions[] = { - { - .name = "cfe", - .offset = 0x0, - .size = 0x40000, - } -}; - -static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL }; - -static struct physmap_flash_data flash_data = { - .width = 2, - .nr_parts = ARRAY_SIZE(mtd_partitions), - .parts = mtd_partitions, - .part_probe_types = bcm63xx_part_types, -}; - -static struct resource mtd_resources[] = { - { - .start = 0, /* filled at runtime */ - .end = 0, /* filled at runtime */ - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device mtd_dev = { - .name = "physmap-flash", - .resource = mtd_resources, - .num_resources = ARRAY_SIZE(mtd_resources), - .dev = { - .platform_data = &flash_data, - }, -}; - static struct gpio_led_platform_data bcm63xx_led_data; static struct platform_device bcm63xx_gpio_leds = { @@ -856,8 +820,6 @@ static struct platform_device bcm63xx_gpio_leds = { */ int __init board_register_devices(void) { - u32 val; - if (board.has_uart0) bcm63xx_uart_register(0); @@ -893,14 +855,7 @@ int __init board_register_devices(void) bcm63xx_spi_register(); - /* read base address of boot chip select (0) */ - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; - - mtd_resources[0].start = val; - mtd_resources[0].end = 0x1FFFFFFF; - - platform_device_register(&mtd_dev); + bcm63xx_flash_register(); bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); bcm63xx_led_data.leds = board.leds; diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c new file mode 100644 index 0000000..af52738 --- /dev/null +++ b/arch/mips/bcm63xx/dev-flash.c @@ -0,0 +1,69 @@ +/* + * Broadcom BCM63xx flash registration + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2008 Florian Fainelli + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct mtd_partition mtd_partitions[] = { + { + .name = "cfe", + .offset = 0x0, + .size = 0x40000, + } +}; + +static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL }; + +static struct physmap_flash_data flash_data = { + .width = 2, + .parts = mtd_partitions, + .part_probe_types = bcm63xx_part_types, +}; + +static struct resource mtd_resources[] = { + { + .start = 0, /* filled at runtime */ + .end = 0, /* filled at runtime */ + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device mtd_dev = { + .name = "physmap-flash", + .resource = mtd_resources, + .num_resources = ARRAY_SIZE(mtd_resources), + .dev = { + .platform_data = &flash_data, + }, +}; + +int __init bcm63xx_flash_register(void) +{ + u32 val; + + /* read base address of boot chip select (0) */ + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + + mtd_resources[0].start = val; + mtd_resources[0].end = 0x1FFFFFFF; + + return platform_device_register(&mtd_dev); +} diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h new file mode 100644 index 0000000..8dcb541 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h @@ -0,0 +1,6 @@ +#ifndef __BCM63XX_FLASH_H +#define __BCM63XX_FLASH_H + +int __init bcm63xx_flash_register(void); + +#endif /* __BCM63XX_FLASH_H */ -- 1.7.2.5 From jonas.gorski@gmail.com Tue Jun 12 10:24:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 10:26:18 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:54586 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903630Ab2FLIYh (ORCPT ); Tue, 12 Jun 2012 10:24:37 +0200 Received: by mail-bk0-f49.google.com with SMTP id j4so5334449bkw.36 for ; Tue, 12 Jun 2012 01:24:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=qq4OWip0gRX3wTKaP4KZm0q8silPzXYKYdvv6vtW/oI=; b=0nq9RUD6CKx9BEaPjV177V8Tvn45E6jvwzKp/g+d/I8aP48AK8bf2UfmURM0rF07uR vU9LLP4/5SrVaRDAAlFSRPx9aQnCxfWm8B20hk/7QMQ/q525JlQ4nrOYQVDBE6lNj+pq 7kyKXm3qiRRTpCHS2Hett3I+QzlIaRHrtKH5z8rgQCcXEskVBUCPUhQySUIqCUxJ56dZ b1IgWoJUKx41sa+rVoGPAsY0XRiPRQAJMsyAewQxRMzF+tDPkjjVGbFmJ+YOaodQvhqF 45oRicR6/HidNBIuCYbijmuD5BUjL0W7fBBnwPEICCuuxJ79mlikv2RsEZpz8yJHOUez bA5Q== Received: by 10.204.129.87 with SMTP id n23mr11326826bks.19.1339489477667; Tue, 12 Jun 2012 01:24:37 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-055-195.pools.arcor-ip.net. [88.73.55.195]) by mx.google.com with ESMTPS id h18sm19177912bkh.8.2012.06.12.01.24.36 (version=SSLv3 cipher=OTHER); Tue, 12 Jun 2012 01:24:36 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Kevin Cernekee Subject: [PATCH 5/8] MIPS: BCM63XX: Move the PCI initialization into its own function Date: Tue, 12 Jun 2012 10:23:42 +0200 Message-Id: <1339489425-19037-6-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> References: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33613 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1271 Lines: 54 Also make the cpu check a bit more explicit. Signed-off-by: Jonas Gorski --- arch/mips/pci/pci-bcm63xx.c | 25 +++++++++++++++++-------- 1 files changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c index 39eb7c4..a2b6d55 100644 --- a/arch/mips/pci/pci-bcm63xx.c +++ b/arch/mips/pci/pci-bcm63xx.c @@ -94,17 +94,10 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg) void __iomem *pci_iospace_start; -static int __init bcm63xx_pci_init(void) +static int __init bcm63xx_register_pci(void) { unsigned int mem_size; u32 val; - - if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368()) - return -ENODEV; - - if (!bcm63xx_pci_enabled) - return -ENODEV; - /* * configuration access are done through IO space, remap 4 * first bytes to access it from CPU. @@ -221,4 +214,20 @@ static int __init bcm63xx_pci_init(void) return 0; } + +static int __init bcm63xx_pci_init(void) +{ + if (!bcm63xx_pci_enabled) + return -ENODEV; + + switch (bcm63xx_get_cpu_id()) { + case BCM6348_CPU_ID: + case BCM6358_CPU_ID: + case BCM6368_CPU_ID: + return bcm63xx_register_pci(); + default: + return -ENODEV; + } +} + arch_initcall(bcm63xx_pci_init); -- 1.7.2.5 From jonas.gorski@gmail.com Tue Jun 12 10:24:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 10:26:45 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:49433 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2FLIYi (ORCPT ); Tue, 12 Jun 2012 10:24:38 +0200 Received: by bkwj4 with SMTP id j4so5334481bkw.36 for ; Tue, 12 Jun 2012 01:24:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=mrwixR2QFhMztxRZon6CO9h/RDkm9+pcAAtPL674NX8=; b=m1PBN7JhoBP+uY8os473SmTL7ngBKInTVT243J0TJf2UzFpAQcGAjFzqysPktRzpjn 0HalLb32+TMBwO9JeAq47+rGwOzU6qLFqKWGTTkzT2lUD9zkKKjKtz5rQsGqi3brVhUv 5AtcGUT5S2k6mi88JcN5hYgrzCjLH3lPa3YP4qleBiGNSs6py0W+bNvBw+wpLTQv+EL7 hRt/UWayXVL+u8qGB3hya5Dc9tAjJ/rV4cO2YrxdX6N8NwsexORTfZINoXFPSpJx5PeS u/cpiUYnXdUrZX2VXih+37vHmOpJq+DskrmoPuHiUCsVyRdJtRTeS3uW5Qzsp/V+l2qy Vj7Q== Received: by 10.204.151.200 with SMTP id d8mr11810172bkw.82.1339489472579; Tue, 12 Jun 2012 01:24:32 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-055-195.pools.arcor-ip.net. [88.73.55.195]) by mx.google.com with ESMTPS id h18sm19177912bkh.8.2012.06.12.01.24.31 (version=SSLv3 cipher=OTHER); Tue, 12 Jun 2012 01:24:31 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Kevin Cernekee Subject: [PATCH 2/8] MIPS: BCM63XX: add flash type detection Date: Tue, 12 Jun 2012 10:23:39 +0200 Message-Id: <1339489425-19037-3-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> References: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33614 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4242 Lines: 133 On BCM6358 and BCM6368 the attached flash type is exposed through a bootstrapping register. Use it for auto detecting the flash type on those and default to parallel flash for earlier SoCs. Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/dev-flash.c | 60 ++++++++++++++++++-- .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 6 ++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 9 +++ 3 files changed, 69 insertions(+), 6 deletions(-) diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c index af52738..1051fae 100644 --- a/arch/mips/bcm63xx/dev-flash.c +++ b/arch/mips/bcm63xx/dev-flash.c @@ -7,6 +7,7 @@ * * Copyright (C) 2008 Maxime Bizon * Copyright (C) 2008 Florian Fainelli + * Copyright (C) 2012 Jonas Gorski */ #include @@ -54,16 +55,63 @@ static struct platform_device mtd_dev = { }, }; +static int __init bcm63xx_detect_flash_type(void) +{ + u32 val; + + switch (bcm63xx_get_cpu_id()) { + case BCM6338_CPU_ID: + case BCM6345_CPU_ID: + case BCM6348_CPU_ID: + /* no way to auto detect so assume parallel */ + return BCM63XX_FLASH_TYPE_PARALLEL; + case BCM6358_CPU_ID: + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); + if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL) + return BCM63XX_FLASH_TYPE_PARALLEL; + else + return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6368_CPU_ID: + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); + switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { + case STRAPBUS_6368_BOOT_SEL_NAND: + return BCM63XX_FLASH_TYPE_NAND; + case STRAPBUS_6368_BOOT_SEL_SERIAL: + return BCM63XX_FLASH_TYPE_SERIAL; + case STRAPBUS_6368_BOOT_SEL_PARALLEL: + return BCM63XX_FLASH_TYPE_PARALLEL; + } + default: + return -EINVAL; + } +} + int __init bcm63xx_flash_register(void) { + int flash_type; u32 val; - /* read base address of boot chip select (0) */ - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; + flash_type = bcm63xx_detect_flash_type(); - mtd_resources[0].start = val; - mtd_resources[0].end = 0x1FFFFFFF; + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: + /* read base address of boot chip select (0) */ + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; - return platform_device_register(&mtd_dev); + mtd_resources[0].start = val; + mtd_resources[0].end = 0x1FFFFFFF; + + return platform_device_register(&mtd_dev); + case BCM63XX_FLASH_TYPE_SERIAL: + pr_warn("unsupported serial flash detected\n"); + return -ENODEV; + case BCM63XX_FLASH_TYPE_NAND: + pr_warn("unsupported NAND flash detected\n"); + return -ENODEV; + default: + pr_err("flash detection failed for BCM%x: %d\n", + bcm63xx_get_cpu_id(), flash_type); + return -ENODEV; + } } diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h index 8dcb541..354b848 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h @@ -1,6 +1,12 @@ #ifndef __BCM63XX_FLASH_H #define __BCM63XX_FLASH_H +enum { + BCM63XX_FLASH_TYPE_PARALLEL, + BCM63XX_FLASH_TYPE_SERIAL, + BCM63XX_FLASH_TYPE_NAND, +}; + int __init bcm63xx_flash_register(void); #endif /* __BCM63XX_FLASH_H */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 6a8df56..849fd97 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -507,6 +507,15 @@ #define GPIO_BASEMODE_6368_MASK 0x7 /* those bits must be kept as read in gpio basemode register*/ +#define GPIO_STRAPBUS_REG 0x40 +#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) +#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) +#define STRAPBUS_6368_BOOT_SEL_MASK 0x3 +#define STRAPBUS_6368_BOOT_SEL_NAND 0 +#define STRAPBUS_6368_BOOT_SEL_SERIAL 1 +#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 + + /************************************************************************* * _REG relative to RSET_ENET *************************************************************************/ -- 1.7.2.5 From jonas.gorski@gmail.com Tue Jun 12 10:24:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 10:27:10 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:48595 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903635Ab2FLIYj (ORCPT ); Tue, 12 Jun 2012 10:24:39 +0200 Received: by bkwj4 with SMTP id j4so5334495bkw.36 for ; Tue, 12 Jun 2012 01:24:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=vupu2FZxLDm4rhVdSmp5mi/PDBSRcOe/7O25ZCPMV2I=; b=mUCpSCROt1ulkyYcmIpktKRldmpkkQW0igL9yxJLkFSOob6vy4TTSH7UXgctxKj/U3 NFReT0ZQSsFGcRMTKi1KuPBjoAeV6ANSAYIj/1d0QFPuAxDHSUiOYu6PuknQQ+pxHPtc 7EUcfLEEDs0EFjaJx5PdKrqjQ5McWQnJ8AP4xKyWaiWpbQzV1GWJiHLr8tKCUrRLZmaJ jTJzgZAXkAvrui/iff7jZBh/+67SyH9c442bOal6gUcyhgzqRa6W+FyWoP3X/WiMS/xu a9mAJkCxEOPW5975tRNN3fPMROlsxWqun7vHXnGXbEQ++4nPTXgm5YXl1hNcicAnqcoK 6p6Q== Received: by 10.205.133.6 with SMTP id hw6mr10908733bkc.93.1339489474207; Tue, 12 Jun 2012 01:24:34 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-055-195.pools.arcor-ip.net. [88.73.55.195]) by mx.google.com with ESMTPS id h18sm19177912bkh.8.2012.06.12.01.24.32 (version=SSLv3 cipher=OTHER); Tue, 12 Jun 2012 01:24:33 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Kevin Cernekee Subject: [PATCH 3/8] MIPS: BCM63XX: use the Chip ID register for identifying the SoC Date: Tue, 12 Jun 2012 10:23:40 +0200 Message-Id: <1339489425-19037-4-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> References: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33615 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1337 Lines: 46 Newer BCM63XX SoCs use virtually the same CPU ID, differing only in the revision bits. But since they all have the Chip ID register at the same location, we can use that to identify the SoC we are running on. Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/cpu.c | 20 ++++++++++++-------- 1 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 8f0d6c7..e3c1da5 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -228,17 +228,21 @@ void __init bcm63xx_cpu_init(void) bcm63xx_irqs = bcm6345_irqs; break; case CPU_BMIPS4350: - switch (read_c0_prid() & 0xf0) { - case 0x10: + if ((read_c0_prid() & 0xf0) == 0x10) { expected_cpu_id = BCM6358_CPU_ID; bcm63xx_regs_base = bcm6358_regs_base; bcm63xx_irqs = bcm6358_irqs; - break; - case 0x30: - expected_cpu_id = BCM6368_CPU_ID; - bcm63xx_regs_base = bcm6368_regs_base; - bcm63xx_irqs = bcm6368_irqs; - break; + } else { + /* all newer chips have the same chip id location */ + u16 chip_id = bcm_readw(BCM_6368_PERF_BASE); + + switch (chip_id) { + case BCM6368_CPU_ID: + expected_cpu_id = BCM6368_CPU_ID; + bcm63xx_regs_base = bcm6368_regs_base; + bcm63xx_irqs = bcm6368_irqs; + break; + } } break; } -- 1.7.2.5 From jonas.gorski@gmail.com Tue Jun 12 10:24:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 10:27:36 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:50801 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903637Ab2FLIYj (ORCPT ); Tue, 12 Jun 2012 10:24:39 +0200 Received: by mail-bk0-f49.google.com with SMTP id j4so5334465bkw.36 for ; Tue, 12 Jun 2012 01:24:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=AbmLqXhldVeFyIK1+ur1aR/x8/NOdzOjdhTc7UIWOvE=; b=oPuGlqtFa6dR+EcVhKkWQkROowxhcxub7vvZOEicCPFR9wJy9/Ij4s4E/lQfMlvFZo zuOO1+WbylYO/GCb/o+sbT2ssPW+uatwQNntKzJGcnrDt2F54EAPKnrAFgrsHXWopUFn jbXj0k1A7Yutp0yZoKqeq9RNGQOOt3qwQKB5vAvhulElhHap8r1HQ1rWtbu9znoFCImO h1KxZmC0gt1KjtXyvHqH1fHU93tRcvEbHAWiVZT1v/vbd1FRIek7Bhyhw+PtTwcrSE6i 4elPiq4qFHBqmaPzSPNapF1d/SumARAof62QKllWOchSqaEn6MYE2WZ6hg/m0Xbcn8TY dzdQ== Received: by 10.204.129.17 with SMTP id m17mr11452055bks.4.1339489479702; Tue, 12 Jun 2012 01:24:39 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-055-195.pools.arcor-ip.net. [88.73.55.195]) by mx.google.com with ESMTPS id h18sm19177912bkh.8.2012.06.12.01.24.37 (version=SSLv3 cipher=OTHER); Tue, 12 Jun 2012 01:24:38 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Kevin Cernekee Subject: [PATCH 6/8] MIPS: BCM63XX: Add PCIe Support for BCM6328 Date: Tue, 12 Jun 2012 10:23:43 +0200 Message-Id: <1339489425-19037-7-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> References: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33616 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 14038 Lines: 432 Add support for the PCIe port found on BCM6328. Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/Kconfig | 1 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 ++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 54 ++++++++++ arch/mips/pci/ops-bcm63xx.c | 61 +++++++++++ arch/mips/pci/pci-bcm63xx.c | 112 +++++++++++++++++++++ arch/mips/pci/pci-bcm63xx.h | 5 + 7 files changed, 248 insertions(+), 0 deletions(-) diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig index 09e93ca..d03e879 100644 --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -3,6 +3,7 @@ menu "CPU support" config BCM63XX_CPU_6328 bool "support 6328 CPU" + select HW_HAS_PCI config BCM63XX_CPU_6338 bool "support 6338 CPU" diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index b842b6d..e104ddb 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -122,6 +122,7 @@ enum bcm63xx_regs_set { RSET_USBH_PRIV, RSET_MPI, RSET_PCMCIA, + RSET_PCIE, RSET_DSL, RSET_ENET0, RSET_ENET1, @@ -188,6 +189,7 @@ enum bcm63xx_regs_set { #define BCM_6328_USBH_PRIV_BASE (0xdeadbeef) #define BCM_6328_MPI_BASE (0xdeadbeef) #define BCM_6328_PCMCIA_BASE (0xdeadbeef) +#define BCM_6328_PCIE_BASE (0xb0e40000) #define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef) #define BCM_6328_DSL_BASE (0xb0001900) #define BCM_6328_UBUS_BASE (0xdeadbeef) @@ -232,6 +234,7 @@ enum bcm63xx_regs_set { #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) #define BCM_6338_MPI_BASE (0xfffe3160) #define BCM_6338_PCMCIA_BASE (0xdeadbeef) +#define BCM_6338_PCIE_BASE (0xdeadbeef) #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) #define BCM_6338_DSL_BASE (0xfffe1000) #define BCM_6338_UBUS_BASE (0xdeadbeef) @@ -279,6 +282,7 @@ enum bcm63xx_regs_set { #define BCM_6345_ENETSW_BASE (0xdeadbeef) #define BCM_6345_PCMCIA_BASE (0xfffe2028) #define BCM_6345_MPI_BASE (0xfffe2000) +#define BCM_6345_PCIE_BASE (0xdeadbeef) #define BCM_6345_OHCI0_BASE (0xfffe2100) #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) @@ -320,6 +324,7 @@ enum bcm63xx_regs_set { #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) #define BCM_6348_MPI_BASE (0xfffe2000) #define BCM_6348_PCMCIA_BASE (0xfffe2054) +#define BCM_6348_PCIE_BASE (0xdeadbeef) #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) #define BCM_6348_M2M_BASE (0xfffe2800) #define BCM_6348_DSL_BASE (0xfffe3000) @@ -362,6 +367,7 @@ enum bcm63xx_regs_set { #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) #define BCM_6358_MPI_BASE (0xfffe1000) #define BCM_6358_PCMCIA_BASE (0xfffe1054) +#define BCM_6358_PCIE_BASE (0xdeadbeef) #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) #define BCM_6358_M2M_BASE (0xdeadbeef) #define BCM_6358_DSL_BASE (0xfffe3000) @@ -405,6 +411,7 @@ enum bcm63xx_regs_set { #define BCM_6368_USBH_PRIV_BASE (0xb0001700) #define BCM_6368_MPI_BASE (0xb0001000) #define BCM_6368_PCMCIA_BASE (0xb0001054) +#define BCM_6368_PCIE_BASE (0xdeadbeef) #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) #define BCM_6368_M2M_BASE (0xdeadbeef) #define BCM_6368_DSL_BASE (0xdeadbeef) @@ -453,6 +460,7 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, USBH_PRIV) \ __GEN_RSET_BASE(__cpu, MPI) \ __GEN_RSET_BASE(__cpu, PCMCIA) \ + __GEN_RSET_BASE(__cpu, PCIE) \ __GEN_RSET_BASE(__cpu, DSL) \ __GEN_RSET_BASE(__cpu, ENET0) \ __GEN_RSET_BASE(__cpu, ENET1) \ @@ -493,6 +501,7 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ + [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h index 6dcd8b2..9203d90 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h @@ -40,6 +40,10 @@ #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ BCM_CB_MEM_SIZE - 1) +#define BCM_PCIE_MEM_BASE_PA 0x10f00000 +#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024) +#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \ + BCM_PCIE_MEM_SIZE - 1) /* * Internal registers are accessed through KSEG3 @@ -85,6 +89,8 @@ #define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o)) #define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o)) #define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o)) +#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o)) +#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o)) #define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o)) #define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o)) #define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o)) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 4fc2ab2..4ccc2a7 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -1162,6 +1162,9 @@ /************************************************************************* * _REG relative to RSET_MISC *************************************************************************/ +#define MISC_SERDES_CTRL_REG 0x0 +#define SERDES_PCIE_EN (1 << 0) +#define SERDES_PCIE_EXD_EN (1 << 15) #define MISC_STRAPBUS_6328_REG 0x240 #define STRAPBUS_6328_FCVO_SHIFT 7 @@ -1169,4 +1172,55 @@ #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28) +/************************************************************************* + * _REG relative to RSET_PCIE + *************************************************************************/ + +#define PCIE_CONFIG2_REG 0x408 +#define CONFIG2_BAR1_SIZE_EN 1 +#define CONFIG2_BAR1_SIZE_MASK 0xf + +#define PCIE_IDVAL3_REG 0x43c +#define IDVAL3_CLASS_CODE_MASK 0xffffff +#define IDVAL3_SUBCLASS_SHIFT 8 +#define IDVAL3_CLASS_SHIFT 16 + +#define PCIE_DLSTATUS_REG 0x1048 +#define DLSTATUS_PHYLINKUP (1 << 13) + +#define PCIE_BRIDGE_OPT1_REG 0x2820 +#define OPT1_RD_BE_OPT_EN (1 << 7) +#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9) +#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11) +#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12) + +#define PCIE_BRIDGE_OPT2_REG 0x2824 +#define OPT2_UBUS_UR_DECODE_DIS (1 << 2) +#define OPT2_TX_CREDIT_CHK_EN (1 << 4) +#define OPT2_CFG_TYPE1_BD_SEL (1 << 7) +#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16 +#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT) + +#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828 +#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830 +#define BASEMASK_REMAP_EN (1 << 0) +#define BASEMASK_SWAP_EN (1 << 1) +#define BASEMASK_MASK_SHIFT 4 +#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT) +#define BASEMASK_BASE_SHIFT 20 +#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT) + +#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c +#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834 +#define REBASE_ADDR_BASE_SHIFT 20 +#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT) + +#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854 +#define PCIE_RC_INT_A (1 << 0) +#define PCIE_RC_INT_B (1 << 1) +#define PCIE_RC_INT_C (1 << 2) +#define PCIE_RC_INT_D (1 << 3) + +#define PCIE_DEVICE_OFFSET 0x8000 + #endif /* BCM63XX_REGS_H_ */ diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c index 097239b..65c7bd1 100644 --- a/arch/mips/pci/ops-bcm63xx.c +++ b/arch/mips/pci/ops-bcm63xx.c @@ -465,3 +465,64 @@ static void __devinit bcm63xx_fixup(struct pci_dev *dev) DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup); #endif + +static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn) +{ + switch (bus->number) { + case PCIE_BUS_BRIDGE: + return (PCI_SLOT(devfn) == 0); + case PCIE_BUS_DEVICE: + if (PCI_SLOT(devfn) == 0) + return bcm_pcie_readl(PCIE_DLSTATUS_REG) + & DLSTATUS_PHYLINKUP; + default: + return false; + } +} + +static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data; + u32 reg = where & ~3; + + if (!bcm63xx_pcie_can_access(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (bus->number == PCIE_BUS_DEVICE) + reg += PCIE_DEVICE_OFFSET; + + data = bcm_pcie_readl(reg); + + *val = postprocess_read(data, where, size); + + return PCIBIOS_SUCCESSFUL; + +} + +static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data; + u32 reg = where & ~3; + + if (!bcm63xx_pcie_can_access(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (bus->number == PCIE_BUS_DEVICE) + reg += PCIE_DEVICE_OFFSET; + + + data = bcm_pcie_readl(reg); + + data = preprocess_write(data, val, where, size); + bcm_pcie_writel(data, reg); + + return PCIBIOS_SUCCESSFUL; +} + + +struct pci_ops bcm63xx_pcie_ops = { + .read = bcm63xx_pcie_read, + .write = bcm63xx_pcie_write +}; diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c index a2b6d55..8a48139 100644 --- a/arch/mips/pci/pci-bcm63xx.c +++ b/arch/mips/pci/pci-bcm63xx.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "pci-bcm63xx.h" @@ -71,6 +72,26 @@ struct pci_controller bcm63xx_cb_controller = { }; #endif +static struct resource bcm_pcie_mem_resource = { + .name = "bcm63xx PCIe memory space", + .start = BCM_PCIE_MEM_BASE_PA, + .end = BCM_PCIE_MEM_END_PA, + .flags = IORESOURCE_MEM, +}; + +static struct resource bcm_pcie_io_resource = { + .name = "bcm63xx PCIe IO space", + .start = 0, + .end = 0, + .flags = 0, +}; + +struct pci_controller bcm63xx_pcie_controller = { + .pci_ops = &bcm63xx_pcie_ops, + .io_resource = &bcm_pcie_io_resource, + .mem_resource = &bcm_pcie_mem_resource, +}; + static u32 bcm63xx_int_cfg_readl(u32 reg) { u32 tmp; @@ -94,6 +115,95 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg) void __iomem *pci_iospace_start; +static void __init bcm63xx_reset_pcie(void) +{ + u32 val; + + /* enable clock */ + val = bcm_perf_readl(PERF_CKCTL_REG); + val |= CKCTL_6328_PCIE_EN; + bcm_perf_writel(val, PERF_CKCTL_REG); + + /* enable SERDES */ + val = bcm_misc_readl(MISC_SERDES_CTRL_REG); + val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; + bcm_misc_writel(val, MISC_SERDES_CTRL_REG); + + /* reset the PCIe core */ + val = bcm_perf_readl(PERF_SOFTRESET_6328_REG); + + val &= ~SOFTRESET_6328_PCIE_MASK; + val &= ~SOFTRESET_6328_PCIE_CORE_MASK; + val &= ~SOFTRESET_6328_PCIE_HARD_MASK; + val &= ~SOFTRESET_6328_PCIE_EXT_MASK; + bcm_perf_writel(val, PERF_SOFTRESET_6328_REG); + mdelay(10); + + val |= SOFTRESET_6328_PCIE_MASK; + val |= SOFTRESET_6328_PCIE_CORE_MASK; + val |= SOFTRESET_6328_PCIE_HARD_MASK; + bcm_perf_writel(val, PERF_SOFTRESET_6328_REG); + mdelay(10); + + val |= SOFTRESET_6328_PCIE_EXT_MASK; + bcm_perf_writel(val, PERF_SOFTRESET_6328_REG); + mdelay(200); +} + +static int __init bcm63xx_register_pcie(void) +{ + u32 val; + + bcm63xx_reset_pcie(); + + /* configure the PCIe bridge */ + val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); + val |= OPT1_RD_BE_OPT_EN; + val |= OPT1_RD_REPLY_BE_FIX_EN; + val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN; + val |= OPT1_L1_INT_STATUS_MASK_POL; + bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG); + + /* setup the interrupts */ + val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG); + val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D; + bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG); + + val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG); + /* enable credit checking and error checking */ + val |= OPT2_TX_CREDIT_CHK_EN; + val |= OPT2_UBUS_UR_DECODE_DIS; + + /* set device bus/func for the pcie device */ + val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT); + val |= OPT2_CFG_TYPE1_BD_SEL; + bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG); + + /* setup class code as bridge */ + val = bcm_pcie_readl(PCIE_IDVAL3_REG); + val &= ~IDVAL3_CLASS_CODE_MASK; + val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT); + bcm_pcie_writel(val, PCIE_IDVAL3_REG); + + /* disable bar1 size */ + val = bcm_pcie_readl(PCIE_CONFIG2_REG); + val &= ~CONFIG2_BAR1_SIZE_MASK; + bcm_pcie_writel(val, PCIE_CONFIG2_REG); + + /* set bar0 to little endian */ + val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; + val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; + val |= BASEMASK_REMAP_EN; + bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); + + val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; + bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); + + register_pci_controller(&bcm63xx_pcie_controller); + + return 0; +} + static int __init bcm63xx_register_pci(void) { unsigned int mem_size; @@ -221,6 +331,8 @@ static int __init bcm63xx_pci_init(void) return -ENODEV; switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + return bcm63xx_register_pcie(); case BCM6348_CPU_ID: case BCM6358_CPU_ID: case BCM6368_CPU_ID: diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h index a6e594e..e6736d5 100644 --- a/arch/mips/pci/pci-bcm63xx.h +++ b/arch/mips/pci/pci-bcm63xx.h @@ -13,11 +13,16 @@ */ #define CARDBUS_PCI_IDSEL 0x8 + +#define PCIE_BUS_BRIDGE 0 +#define PCIE_BUS_DEVICE 1 + /* * defined in ops-bcm63xx.c */ extern struct pci_ops bcm63xx_pci_ops; extern struct pci_ops bcm63xx_cb_ops; +extern struct pci_ops bcm63xx_pcie_ops; /* * defined in pci-bcm63xx.c -- 1.7.2.5 From jonas.gorski@gmail.com Tue Jun 12 10:24:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 10:28:00 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:54586 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903638Ab2FLIYl (ORCPT ); Tue, 12 Jun 2012 10:24:41 +0200 Received: by mail-bk0-f49.google.com with SMTP id j4so5334449bkw.36 for ; Tue, 12 Jun 2012 01:24:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=cDCzWD+xfJ4McDl9ZeUAVe4QUVnrAVz1eXUGFo+ZI+s=; b=ZEDzABfRx6mkfKkH4vIRL2fk1SC6tI222eVwmVV/iys07p4qli65K3qnUXheqvTggL vJTubZiY9t8KKK+bKgqtmwMeuLbD5wWaZ5c6boG8qhOaX6s7azrSYjjA6eBaL9SHpdLg dyiI0bELYE/05yiTp+px8MaMG/iAsOWQAHdssw4dnw2bT7C5ds5Ywy7rWq6vegpvyt2q 3OyTRQhvITealJWPp+aIvOm5OFcph8qQo/qWz0Gb1pzuv265guC6EAZwFoEIaxYBlqZ+ kmB3XTxGqBNITAvkbwMKPFYqcXk1xKdLNWwKreWVSSv4LRo0SjXttvaS/5KUvY24KRFc zJiw== Received: by 10.204.136.214 with SMTP id s22mr11464450bkt.92.1339489481216; Tue, 12 Jun 2012 01:24:41 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-055-195.pools.arcor-ip.net. [88.73.55.195]) by mx.google.com with ESMTPS id h18sm19177912bkh.8.2012.06.12.01.24.39 (version=SSLv3 cipher=OTHER); Tue, 12 Jun 2012 01:24:40 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Kevin Cernekee Subject: [PATCH 7/8] MIPS: expose PCIe drivers for MIPS Date: Tue, 12 Jun 2012 10:23:44 +0200 Message-Id: <1339489425-19037-8-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> References: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33617 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 551 Lines: 21 Signed-off-by: Jonas Gorski --- arch/mips/Kconfig | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f39850c..08dfc79 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2370,6 +2370,8 @@ config PCI_DOMAINS source "drivers/pci/Kconfig" +source "drivers/pci/pcie/Kconfig" + # # ISA support is now enabled via select. Too many systems still have the one # or other ISA chip on the board that users don't know about so don't expect -- 1.7.2.5 From jonas.gorski@gmail.com Tue Jun 12 10:24:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 10:28:25 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:49433 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903642Ab2FLIYn (ORCPT ); Tue, 12 Jun 2012 10:24:43 +0200 Received: by mail-bk0-f49.google.com with SMTP id j4so5334481bkw.36 for ; Tue, 12 Jun 2012 01:24:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=V+33AX4HD+wBdtlZ70NqNIS/Z+qcKFcwS3zXYN4+9iQ=; b=WZNrzMzqE348udlxfQznIQatK2b6pOm+kpTQl9twd4Scs/mcozkoIGQ9qBsDPm737+ ce14SXUYB+jtpqod8PXxVrM9mXALX5rSyFfg80KSbMIcQpZmawaO4lyBbM4K3uRYXoYO wJfT+jicQwHC9ZIeXf65TTt3Lqm68+SbntUsye0HjPoNPfPomF3PuyqpDHJOXmJ8cVHc FFXTrwqiBQrQVAt2P/r1j0sUTHSBAVlNK/L+1IgiMxCivG1/X15SavukZQr2J53F1/sr lrmRqxpgeXq7adOgClBkAO5ywDm76dD0jgLa+ABWnqlnYmEgnnMhCTmBvdmUec6r2Pwo GHYg== Received: by 10.204.145.78 with SMTP id c14mr11231806bkv.43.1339489482791; Tue, 12 Jun 2012 01:24:42 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-055-195.pools.arcor-ip.net. [88.73.55.195]) by mx.google.com with ESMTPS id h18sm19177912bkh.8.2012.06.12.01.24.41 (version=SSLv3 cipher=OTHER); Tue, 12 Jun 2012 01:24:42 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , Kevin Cernekee Subject: [PATCH 8/8] MIPS: BCM63XX: add 96328avng reference board Date: Tue, 12 Jun 2012 10:23:45 +0200 Message-Id: <1339489425-19037-9-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> References: <1339489425-19037-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33618 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1670 Lines: 74 This allows booting to command line. Ethernet is not supported yet, but PCIe connected wireless should work. Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/boards/board_bcm963xx.c | 45 +++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index be7498a..feb0525 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -33,6 +33,48 @@ static unsigned int mac_addr_used; static struct board_info board; /* + * known 6328 boards + */ +#ifdef CONFIG_BCM63XX_CPU_6328 +static struct board_info __initdata board_96328avng = { + .name = "96328avng", + .expected_cpu_id = 0x6328, + + .has_uart0 = 1, + .has_pci = 1, + + .leds = { + { + .name = "96328avng::ppp-fail", + .gpio = 2, + .active_low = 1, + }, + { + .name = "96328avng::power", + .gpio = 4, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "96328avng::power-fail", + .gpio = 8, + .active_low = 1, + }, + { + .name = "96328avng::wps", + .gpio = 9, + .active_low = 1, + }, + { + .name = "96328avng::ppp", + .gpio = 11, + .active_low = 1, + }, + }, +}; +#endif + +/* * known 6338 boards */ #ifdef CONFIG_BCM63XX_CPU_6338 @@ -591,6 +633,9 @@ static struct board_info __initdata board_DWVS0 = { * all boards */ static const struct board_info __initdata *bcm963xx_boards[] = { +#ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, +#endif #ifdef CONFIG_BCM63XX_CPU_6338 &board_96338gw, &board_96338w, -- 1.7.2.5 From pebolle@tiscali.nl Tue Jun 12 11:03:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 11:03:33 +0200 (CEST) Received: from cpsmtpb-ews08.kpnxchange.com ([213.75.39.13]:1307 "EHLO cpsmtpb-ews08.kpnxchange.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903642Ab2FLJDU (ORCPT ); Tue, 12 Jun 2012 11:03:20 +0200 Received: from cpsps-ews22.kpnxchange.com ([10.94.84.188]) by cpsmtpb-ews08.kpnxchange.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 12 Jun 2012 11:03:14 +0200 Received: from CPSMTPM-TLF102.kpnxchange.com ([195.121.3.5]) by cpsps-ews22.kpnxchange.com with Microsoft SMTPSVC(7.5.7601.17514); Tue, 12 Jun 2012 11:03:13 +0200 Received: from [192.168.1.102] ([212.123.169.34]) by CPSMTPM-TLF102.kpnxchange.com with Microsoft SMTPSVC(7.5.7601.17514); Tue, 12 Jun 2012 11:03:12 +0200 Message-ID: <1339491792.30984.110.camel@x61.thuisdomein> Subject: [PATCH] MIPS: remove three unused headers From: Paul Bolle To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Date: Tue, 12 Jun 2012 11:03:12 +0200 Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Content-Transfer-Encoding: 7bit Mime-Version: 1.0 X-OriginalArrivalTime: 12 Jun 2012 09:03:12.0471 (UTC) FILETIME=[31F12670:01CD487A] X-RcptDomain: linux-mips.org X-archive-position: 33619 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pebolle@tiscali.nl Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 49656 Lines: 1144 No file includes these three headers. It seems they have never been included since at least v2.6.12-rc2. They can safely be removed. Signed-off-by: Paul Bolle --- Tested only by "git grepping" the (history of the) tree in various ways. Note that this included "git grepping" each named constant defined in these headers (against v3.5-rc2). That found no indication that they were used anywhere. Since these headers aren't included anyway, that's not really surprising. (But perhaps creative use of macro concatenation hides their usage in the code.) arch/mips/include/asm/sibyte/sb1250_l2c.h | 131 ------- arch/mips/include/asm/sibyte/sb1250_ldt.h | 422 ---------------------- arch/mips/include/asm/sibyte/sb1250_mc.h | 550 ----------------------------- 3 files changed, 0 insertions(+), 1103 deletions(-) delete mode 100644 arch/mips/include/asm/sibyte/sb1250_l2c.h delete mode 100644 arch/mips/include/asm/sibyte/sb1250_ldt.h delete mode 100644 arch/mips/include/asm/sibyte/sb1250_mc.h diff --git a/arch/mips/include/asm/sibyte/sb1250_l2c.h b/arch/mips/include/asm/sibyte/sb1250_l2c.h deleted file mode 100644 index 6554dcf..0000000 --- a/arch/mips/include/asm/sibyte/sb1250_l2c.h +++ /dev/null @@ -1,131 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * L2 Cache constants and macros File: sb1250_l2c.h - * - * This module contains constants useful for manipulating the - * level 2 cache. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_L2C_H -#define _SB1250_L2C_H - -#include "sb1250_defs.h" - -/* - * Level 2 Cache Tag register (Table 5-3) - */ - -#define S_L2C_TAG_MBZ 0 -#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ) - -#define S_L2C_TAG_INDEX 5 -#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX) -#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX) -#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX) - -#define S_L2C_TAG_TAG 17 -#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG) -#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG) -#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG) - -#define S_L2C_TAG_ECC 40 -#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC) -#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC) -#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC) - -#define S_L2C_TAG_WAY 46 -#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY) -#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY) -#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY) - -#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) -#define M_L2C_TAG_VALID _SB_MAKEMASK1(49) - -/* - * Format of level 2 cache management address (table 5-2) - */ - -#define S_L2C_MGMT_INDEX 5 -#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX) -#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX) -#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX) - -#define S_L2C_MGMT_QUADRANT 15 -#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT) -#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT) -#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT) - -#define S_L2C_MGMT_HALF 16 -#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF) - -#define S_L2C_MGMT_WAY 17 -#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY) -#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY) -#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY) - -#define S_L2C_MGMT_ECC_DIAG 21 -#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG) -#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG) -#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG) - -#define S_L2C_MGMT_TAG 23 -#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG) -#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG) -#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG) - -#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) -#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) - -#define A_L2C_MGMT_TAG_BASE 0x00D0000000 - -#define L2C_ENTRIES_PER_WAY 4096 -#define L2C_NUM_WAYS 4 - - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * L2 Read Misc. register (A_L2_READ_MISC) - */ -#define S_L2C_MISC_NO_WAY 10 -#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY) -#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY) -#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY) - -#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9) -#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8) -#define M_L2C_MISC_SOFT_DISABLE_T _SB_MAKEMASK1(7) -#define M_L2C_MISC_SOFT_DISABLE_B _SB_MAKEMASK1(6) -#define M_L2C_MISC_SOFT_DISABLE_R _SB_MAKEMASK1(5) -#define M_L2C_MISC_SOFT_DISABLE_L _SB_MAKEMASK1(4) -#define M_L2C_MISC_SCACHE_DISABLE_T _SB_MAKEMASK1(3) -#define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2) -#define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1) -#define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0) -#endif /* 1250 PASS3 || 112x PASS1 */ - - -#endif diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h deleted file mode 100644 index 1e76cf1..0000000 --- a/arch/mips/include/asm/sibyte/sb1250_ldt.h +++ /dev/null @@ -1,422 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * LDT constants File: sb1250_ldt.h - * - * This module contains constants and macros to describe - * the LDT interface on the SB1250. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000, 2001, 2002, 2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_LDT_H -#define _SB1250_LDT_H - -#include "sb1250_defs.h" - -#define K_LDT_VENDOR_SIBYTE 0x166D -#define K_LDT_DEVICE_SB1250 0x0002 - -/* - * LDT Interface Type 1 (bridge) configuration header - */ - -#define R_LDT_TYPE1_DEVICEID 0x0000 -#define R_LDT_TYPE1_CMDSTATUS 0x0004 -#define R_LDT_TYPE1_CLASSREV 0x0008 -#define R_LDT_TYPE1_DEVHDR 0x000C -#define R_LDT_TYPE1_BAR0 0x0010 /* not used */ -#define R_LDT_TYPE1_BAR1 0x0014 /* not used */ - -#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */ -#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */ -#define R_LDT_TYPE1_MEMLIMIT 0x0020 -#define R_LDT_TYPE1_PREFETCH 0x0024 -#define R_LDT_TYPE1_PREF_BASE 0x0028 -#define R_LDT_TYPE1_PREF_LIMIT 0x002C -#define R_LDT_TYPE1_IOLIMIT 0x0030 -#define R_LDT_TYPE1_CAPPTR 0x0034 -#define R_LDT_TYPE1_ROMADDR 0x0038 -#define R_LDT_TYPE1_BRCTL 0x003C -#define R_LDT_TYPE1_CMD 0x0040 -#define R_LDT_TYPE1_LINKCTRL 0x0044 -#define R_LDT_TYPE1_LINKFREQ 0x0048 -#define R_LDT_TYPE1_RESERVED1 0x004C -#define R_LDT_TYPE1_SRICMD 0x0050 -#define R_LDT_TYPE1_SRITXNUM 0x0054 -#define R_LDT_TYPE1_SRIRXNUM 0x0058 -#define R_LDT_TYPE1_ERRSTATUS 0x0068 -#define R_LDT_TYPE1_SRICTRL 0x006C -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define R_LDT_TYPE1_ADDSTATUS 0x0070 -#endif /* 1250 PASS2 || 112x PASS1 */ -#define R_LDT_TYPE1_TXBUFCNT 0x00C8 -#define R_LDT_TYPE1_EXPCRC 0x00DC -#define R_LDT_TYPE1_RXCRC 0x00F0 - - -/* - * LDT Device ID register - */ - -#define S_LDT_DEVICEID_VENDOR 0 -#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR) -#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR) -#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR) - -#define S_LDT_DEVICEID_DEVICEID 16 -#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID) -#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID) -#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID) - - -/* - * LDT Command Register (Table 8-13) - */ - -#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0) -#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1) -#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2) -#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3) -#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4) -#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5) -#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6) -#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7) -#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8) -#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9) - -/* - * LDT class and revision registers - */ - -#define S_LDT_CLASSREV_REV 0 -#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV) -#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV) -#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV) - -#define S_LDT_CLASSREV_CLASS 8 -#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS) -#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS) -#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS) - -#define K_LDT_REV 0x01 -#define K_LDT_CLASS 0x060000 - -/* - * Device Header (offset 0x0C) - */ - -#define S_LDT_DEVHDR_CLINESZ 0 -#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ) -#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ) -#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ) - -#define S_LDT_DEVHDR_LATTMR 8 -#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR) -#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR) -#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR) - -#define S_LDT_DEVHDR_HDRTYPE 16 -#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE) -#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE) -#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE) - -#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 - -#define S_LDT_DEVHDR_BIST 24 -#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST) -#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST) -#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST) - - - -/* - * LDT Status Register (Table 8-14). Note that these constants - * assume you've read the command and status register - * together (32-bit read at offset 0x04) - * - * These bits also apply to the secondary status - * register (Table 8-15), offset 0x1C - */ - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3) -#endif /* 1250 PASS2 || 112x PASS1 */ -#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20) -#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21) -#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22) -#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23) -#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) - -#define S_LDT_STATUS_DEVSELTIMING 25 -#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING) -#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING) -#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING) - -#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) -#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) -#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29) -#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30) -#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31) - -/* - * Bridge Control Register (Table 8-16). Note that these - * constants assume you've read the register as a 32-bit - * read (offset 0x3C) - */ - -#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16) -#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17) -#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18) -#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19) -#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21) -#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22) -#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23) -#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24) -#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25) -#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26) -#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27) - -/* - * LDT Command Register (Table 8-17). Note that these constants - * assume you've read the command and status register together - * 32-bit read at offset 0x40 - */ - -#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16) -#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) - -#define S_LDT_CMD_CAPTYPE 29 -#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE) -#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE) -#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE) - -/* - * LDT link control register (Table 8-18), and (Table 8-19) - */ - -#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1) -#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2) -#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3) -#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4) -#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5) -#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6) -#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) - -#define S_LDT_LINKCTRL_CRCERR 8 -#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR) -#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR) -#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR) - -#define S_LDT_LINKCTRL_MAXIN 16 -#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN) -#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN) -#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN) - -#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) - -#define S_LDT_LINKCTRL_MAXOUT 20 -#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT) -#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT) -#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT) - -#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) - -#define S_LDT_LINKCTRL_WIDTHIN 24 -#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN) -#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN) -#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN) - -#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) - -#define S_LDT_LINKCTRL_WIDTHOUT 28 -#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT) -#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT) -#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT) - -#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) - -/* - * LDT Link frequency register (Table 8-20) offset 0x48 - */ - -#define S_LDT_LINKFREQ_FREQ 8 -#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ) -#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ) -#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ) - -#define K_LDT_LINKFREQ_200MHZ 0 -#define K_LDT_LINKFREQ_300MHZ 1 -#define K_LDT_LINKFREQ_400MHZ 2 -#define K_LDT_LINKFREQ_500MHZ 3 -#define K_LDT_LINKFREQ_600MHZ 4 -#define K_LDT_LINKFREQ_800MHZ 5 -#define K_LDT_LINKFREQ_1000MHZ 6 - -/* - * LDT SRI Command Register (Table 8-21). Note that these constants - * assume you've read the command and status register together - * 32-bit read at offset 0x50 - */ - -#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16) -#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17) -#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18) -#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */ -#endif /* up to 1250 PASS1 */ -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19) -#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26) -#endif /* 1250 PASS2 || 112x PASS1 */ - - -#define S_LDT_SRICMD_RXMARGIN 20 -#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN) -#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN) -#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN) - -#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) - -#define S_LDT_SRICMD_TXINITIALOFFSET 28 -#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET) -#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET) -#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET) - -#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) - -/* - * LDT Error control and status register (Table 8-22) (Table 8-23) - */ - -#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0) -#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1) -#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2) -#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3) -#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4) -#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5) -#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6) -#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7) -#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8) -#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9) -#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10) -#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11) -#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12) -#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13) -#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14) -#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15) -#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16) -#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17) - -#define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24) -#define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25) -#define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26) -#define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27) -#define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28) - -/* - * SRI Control register (Table 8-24, 8-25) Offset 0x6C - */ - -#define S_LDT_SRICTRL_NEEDRESP 0 -#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP) -#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP) -#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP) - -#define S_LDT_SRICTRL_NEEDNPREQ 2 -#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ) -#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ) -#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ) - -#define S_LDT_SRICTRL_NEEDPREQ 4 -#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ) -#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ) -#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ) - -#define S_LDT_SRICTRL_WANTRESP 8 -#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP) -#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP) -#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP) - -#define S_LDT_SRICTRL_WANTNPREQ 10 -#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ) -#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ) -#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ) - -#define S_LDT_SRICTRL_WANTPREQ 12 -#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ) -#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ) -#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ) - -#define S_LDT_SRICTRL_BUFRELSPACE 16 -#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE) -#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE) -#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE) - -/* - * LDT SRI Transmit Buffer Count register (Table 8-26) - */ - -#define S_LDT_TXBUFCNT_PCMD 0 -#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD) -#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD) -#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD) - -#define S_LDT_TXBUFCNT_PDATA 4 -#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA) -#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA) -#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA) - -#define S_LDT_TXBUFCNT_NPCMD 8 -#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD) -#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD) -#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD) - -#define S_LDT_TXBUFCNT_NPDATA 12 -#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA) -#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA) -#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA) - -#define S_LDT_TXBUFCNT_RCMD 16 -#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD) -#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD) -#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD) - -#define S_LDT_TXBUFCNT_RDATA 20 -#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA) -#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA) -#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * Additional Status Register - */ - -#define S_LDT_ADDSTATUS_TGTDONE 0 -#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE) -#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE) -#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#endif diff --git a/arch/mips/include/asm/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h deleted file mode 100644 index 1eb1b5a..0000000 --- a/arch/mips/include/asm/sibyte/sb1250_mc.h +++ /dev/null @@ -1,550 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Memory Controller constants File: sb1250_mc.h - * - * This module contains constants and macros useful for - * programming the memory controller. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000, 2001, 2002, 2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_MC_H -#define _SB1250_MC_H - -#include "sb1250_defs.h" - -/* - * Memory Channel Config Register (table 6-14) - */ - -#define S_MC_RESERVED0 0 -#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0) - -#define S_MC_CHANNEL_SEL 8 -#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL) -#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) -#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) - -#define S_MC_BANK0_MAP 16 -#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP) -#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) -#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) - -#define K_MC_BANK0_MAP_DEFAULT 0x00 -#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) - -#define S_MC_BANK1_MAP 20 -#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP) -#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) -#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) - -#define K_MC_BANK1_MAP_DEFAULT 0x08 -#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) - -#define S_MC_BANK2_MAP 24 -#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP) -#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) -#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP) - -#define K_MC_BANK2_MAP_DEFAULT 0x09 -#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) - -#define S_MC_BANK3_MAP 28 -#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP) -#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP) -#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP) - -#define K_MC_BANK3_MAP_DEFAULT 0x0C -#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) - -#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32) - -#define S_MC_QUEUE_SIZE 40 -#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE) -#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) - -#define S_MC_AGE_LIMIT 44 -#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT) -#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) - -#define S_MC_WR_LIMIT 48 -#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT) -#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT) -#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT) -#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) - -#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) - -#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53) - -#define S_MC_CS_MODE 56 -#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE) -#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE) -#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE) - -#define K_MC_CS_MODE_MSB_CS 0 -#define K_MC_CS_MODE_INTLV_CS 15 -#define K_MC_CS_MODE_MIXED_CS_10 12 -#define K_MC_CS_MODE_MIXED_CS_30 6 -#define K_MC_CS_MODE_MIXED_CS_32 3 - -#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) -#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) -#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) -#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) -#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) - -#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) -#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) -#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) -#define M_MC_DEBUG _SB_MAKEMASK1(63) - -#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ - V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \ - V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \ - M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT - - -/* - * Memory clock config register (Table 6-15) - * - * Note: this field has been updated to be consistent with the errata to 0.2 - */ - -#define S_MC_CLK_RATIO 0 -#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO) -#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO) -#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO) - -#define K_MC_CLK_RATIO_2X 4 -#define K_MC_CLK_RATIO_25X 5 -#define K_MC_CLK_RATIO_3X 6 -#define K_MC_CLK_RATIO_35X 7 -#define K_MC_CLK_RATIO_4X 8 -#define K_MC_CLK_RATIO_45X 9 - -#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) -#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) -#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) -#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) -#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) -#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) -#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X - -#define S_MC_REF_RATE 8 -#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE) -#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE) -#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE) - -#define K_MC_REF_RATE_100MHz 0x62 -#define K_MC_REF_RATE_133MHz 0x81 -#define K_MC_REF_RATE_200MHz 0xC4 - -#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) -#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) -#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) -#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz - -#define S_MC_CLOCK_DRIVE 16 -#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE) -#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) - -#define S_MC_DATA_DRIVE 20 -#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE) -#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) - -#define S_MC_ADDR_DRIVE 24 -#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE) -#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MC_REF_DISABLE _SB_MAKEMASK1(30) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) - -#define S_MC_DQI_SKEW 32 -#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW) -#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW) -#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW) -#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) - -#define S_MC_DQO_SKEW 40 -#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW) -#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW) -#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW) -#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) - -#define S_MC_ADDR_SKEW 48 -#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW) -#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) - -#define S_MC_DLL_DEFAULT 56 -#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT) -#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) - -#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ - V_MC_ADDR_SKEW_DEFAULT | \ - V_MC_DQO_SKEW_DEFAULT | \ - V_MC_DQI_SKEW_DEFAULT | \ - V_MC_ADDR_DRIVE_DEFAULT | \ - V_MC_DATA_DRIVE_DEFAULT | \ - V_MC_CLOCK_DRIVE_DEFAULT | \ - V_MC_REF_RATE_DEFAULT - - - -/* - * DRAM Command Register (Table 6-13) - */ - -#define S_MC_COMMAND 0 -#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND) -#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND) -#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND) - -#define K_MC_COMMAND_EMRS 0 -#define K_MC_COMMAND_MRS 1 -#define K_MC_COMMAND_PRE 2 -#define K_MC_COMMAND_AR 3 -#define K_MC_COMMAND_SETRFSH 4 -#define K_MC_COMMAND_CLRRFSH 5 -#define K_MC_COMMAND_SETPWRDN 6 -#define K_MC_COMMAND_CLRPWRDN 7 - -#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) -#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) -#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) -#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) -#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) -#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) -#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) -#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) - -#define M_MC_CS0 _SB_MAKEMASK1(4) -#define M_MC_CS1 _SB_MAKEMASK1(5) -#define M_MC_CS2 _SB_MAKEMASK1(6) -#define M_MC_CS3 _SB_MAKEMASK1(7) - -/* - * DRAM Mode Register (Table 6-14) - */ - -#define S_MC_EMODE 0 -#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE) -#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE) -#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE) -#define V_MC_EMODE_DEFAULT V_MC_EMODE(0) - -#define S_MC_MODE 16 -#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE) -#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE) -#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE) -#define V_MC_MODE_DEFAULT V_MC_MODE(0x22) - -#define S_MC_DRAM_TYPE 32 -#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE) -#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE) -#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE) - -#define K_MC_DRAM_TYPE_JEDEC 0 -#define K_MC_DRAM_TYPE_FCRAM 1 -#define K_MC_DRAM_TYPE_SGRAM 2 - -#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) -#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) -#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) - -#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) -#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37) -#endif /* 1250 PASS3 || 112x PASS1 */ - - - -/* - * SDRAM Timing Register (Table 6-15) - */ - -#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60) -#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) -#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) - -#define S_MC_tFIFO 56 -#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO) -#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO) -#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO) -#define K_MC_tFIFO_DEFAULT 1 -#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) - -#define S_MC_tRFC 52 -#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC) -#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC) -#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC) -#define K_MC_tRFC_DEFAULT 12 -#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) -#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */ -#endif - -#define S_MC_tCwCr 40 -#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr) -#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr) -#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr) -#define K_MC_tCwCr_DEFAULT 4 -#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) - -#define S_MC_tRCr 28 -#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr) -#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr) -#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr) -#define K_MC_tRCr_DEFAULT 9 -#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) - -#define S_MC_tRCw 24 -#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw) -#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw) -#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw) -#define K_MC_tRCw_DEFAULT 10 -#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) - -#define S_MC_tRRD 20 -#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD) -#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD) -#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD) -#define K_MC_tRRD_DEFAULT 2 -#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) - -#define S_MC_tRP 16 -#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP) -#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP) -#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP) -#define K_MC_tRP_DEFAULT 4 -#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) - -#define S_MC_tCwD 8 -#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD) -#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD) -#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD) -#define K_MC_tCwD_DEFAULT 1 -#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) - -#define M_tCrDh _SB_MAKEMASK1(7) -#define M_MC_tCrDh M_tCrDh - -#define S_MC_tCrD 4 -#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD) -#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD) -#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD) -#define K_MC_tCrD_DEFAULT 2 -#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) - -#define S_MC_tRCD 0 -#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD) -#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD) -#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD) -#define K_MC_tRCD_DEFAULT 3 -#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) - -#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ - V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ - V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ - V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ - V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ - V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ - V_MC_tRP(K_MC_tRP_DEFAULT) | \ - V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ - V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ - V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ - M_MC_r2rIDLE_TWOCYCLES - -/* - * Errata says these are not the default - * M_MC_w2rIDLE_TWOCYCLES | \ - * M_MC_r2wIDLE_TWOCYCLES | \ - */ - - -/* - * Chip Select Start Address Register (Table 6-17) - */ - -#define S_MC_CS0_START 0 -#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START) -#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START) -#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START) - -#define S_MC_CS1_START 16 -#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START) -#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START) -#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START) - -#define S_MC_CS2_START 32 -#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START) -#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START) -#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START) - -#define S_MC_CS3_START 48 -#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START) -#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START) -#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START) - -/* - * Chip Select End Address Register (Table 6-18) - */ - -#define S_MC_CS0_END 0 -#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END) -#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END) -#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END) - -#define S_MC_CS1_END 16 -#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END) -#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END) -#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END) - -#define S_MC_CS2_END 32 -#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END) -#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END) -#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END) - -#define S_MC_CS3_END 48 -#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END) -#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END) -#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END) - -/* - * Chip Select Interleave Register (Table 6-19) - */ - -#define S_MC_INTLV_RESERVED 0 -#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED) - -#define S_MC_INTERLEAVE 7 -#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE) -#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE) - -#define S_MC_INTLV_MBZ 25 -#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ) - -/* - * Row Address Bits Register (Table 6-20) - */ - -#define S_MC_RAS_RESERVED 0 -#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED) - -#define S_MC_RAS_SELECT 12 -#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT) -#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT) - -#define S_MC_RAS_MBZ 37 -#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ) - - -/* - * Column Address Bits Register (Table 6-21) - */ - -#define S_MC_CAS_RESERVED 0 -#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED) - -#define S_MC_CAS_SELECT 5 -#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT) -#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT) - -#define S_MC_CAS_MBZ 23 -#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ) - - -/* - * Bank Address Address Bits Register (Table 6-22) - */ - -#define S_MC_BA_RESERVED 0 -#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED) - -#define S_MC_BA_SELECT 5 -#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT) -#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT) - -#define S_MC_BA_MBZ 25 -#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ) - -/* - * Chip Select Attribute Register (Table 6-23) - */ - -#define K_MC_CS_ATTR_CLOSED 0 -#define K_MC_CS_ATTR_CASCHECK 1 -#define K_MC_CS_ATTR_HINT 2 -#define K_MC_CS_ATTR_OPEN 3 - -#define S_MC_CS0_PAGE 0 -#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE) -#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE) -#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE) - -#define S_MC_CS1_PAGE 16 -#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE) -#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE) -#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE) - -#define S_MC_CS2_PAGE 32 -#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE) -#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE) -#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE) - -#define S_MC_CS3_PAGE 48 -#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE) -#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE) -#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE) - -/* - * ECC Test ECC Register (Table 6-25) - */ - -#define S_MC_ECC_INVERT 0 -#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT) - - -#endif -- 1.7.7.6 From pebolle@tiscali.nl Tue Jun 12 11:03:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Jun 2012 11:04:05 +0200 (CEST) Received: from cpsmtpb-ews02.kpnxchange.com ([213.75.39.5]:1269 "EHLO cpsmtpb-ews02.kpnxchange.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903699Ab2FLJDa (ORCPT ); Tue, 12 Jun 2012 11:03:30 +0200 Received: from cpsps-ews14.kpnxchange.com ([10.94.84.181]) by cpsmtpb-ews02.kpnxchange.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 12 Jun 2012 11:03:25 +0200 Received: from CPSMTPM-TLF101.kpnxchange.com ([195.121.3.4]) by cpsps-ews14.kpnxchange.com with Microsoft SMTPSVC(7.5.7601.17514); Tue, 12 Jun 2012 11:03:24 +0200 Received: from [192.168.1.102] ([212.123.169.34]) by CPSMTPM-TLF101.kpnxchange.com with Microsoft SMTPSVC(7.5.7601.17514); Tue, 12 Jun 2012 11:03:24 +0200 Message-ID: <1339491803.30984.111.camel@x61.thuisdomein> Subject: [PATCH] MIPS: remove two unused headers From: Paul Bolle To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Date: Tue, 12 Jun 2012 11:03:23 +0200 Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Content-Transfer-Encoding: 7bit Mime-Version: 1.0 X-OriginalArrivalTime: 12 Jun 2012 09:03:24.0459 (UTC) FILETIME=[39165FB0:01CD487A] X-RcptDomain: linux-mips.org X-archive-position: 33620 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pebolle@tiscali.nl Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 63142 Lines: 1197 No file includes these two headers. It seems they have never been included since they were added to the tree in commit 4cbf2beac2265b3619be9c8e88ff4ff45b49d7c2 ("BCM1480 headers"). They can safely be removed. Signed-off-by: Paul Bolle --- Again tested only by "git grepping" the (history of the) tree in various ways. Note that this included "git grepping" each named constant defined in these headers (against v3.5-rc2). That found no indication that they were used anywhere. Since these headers aren't included anyway, that's not really surprising. (But perhaps creative use of macro concatenation hides their usage in the code.) arch/mips/include/asm/sibyte/bcm1480_l2c.h | 176 ----- arch/mips/include/asm/sibyte/bcm1480_mc.h | 984 ---------------------------- 2 files changed, 0 insertions(+), 1160 deletions(-) delete mode 100644 arch/mips/include/asm/sibyte/bcm1480_l2c.h delete mode 100644 arch/mips/include/asm/sibyte/bcm1480_mc.h diff --git a/arch/mips/include/asm/sibyte/bcm1480_l2c.h b/arch/mips/include/asm/sibyte/bcm1480_l2c.h deleted file mode 100644 index fd75817..0000000 --- a/arch/mips/include/asm/sibyte/bcm1480_l2c.h +++ /dev/null @@ -1,176 +0,0 @@ -/* ********************************************************************* - * BCM1280/BCM1480 Board Support Package - * - * L2 Cache constants and macros File: bcm1480_l2c.h - * - * This module contains constants useful for manipulating the - * level 2 cache. - * - * BCM1400 specification level: 1280-UM100-D2 (11/14/03) - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _BCM1480_L2C_H -#define _BCM1480_L2C_H - -#include "sb1250_defs.h" - -/* - * Format of level 2 cache management address (Table 55) - */ - -#define S_BCM1480_L2C_MGMT_INDEX 5 -#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX) -#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX) -#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX) - -#define S_BCM1480_L2C_MGMT_WAY 17 -#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY) -#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY) -#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY) - -#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) -#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) - -#define S_BCM1480_L2C_MGMT_ECC_DIAG 22 -#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG) -#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG) -#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG) - -#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 - -#define BCM1480_L2C_ENTRIES_PER_WAY 4096 -#define BCM1480_L2C_NUM_WAYS 8 - - -/* - * Level 2 Cache Tag register (Table 59) - */ - -#define S_BCM1480_L2C_TAG_MBZ 0 -#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ) - -#define S_BCM1480_L2C_TAG_INDEX 5 -#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX) -#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX) -#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX) - -/* Note that index bit 16 is also tag bit 40 */ -#define S_BCM1480_L2C_TAG_TAG 17 -#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG) -#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG) -#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG) - -#define S_BCM1480_L2C_TAG_ECC 40 -#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC) -#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC) -#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC) - -#define S_BCM1480_L2C_TAG_WAY 46 -#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY) -#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY) -#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY) - -#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) -#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) - -#define S_BCM1480_L2C_DATA_ECC 51 -#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC) -#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC) -#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC) - - -/* - * L2 Misc0 Value Register (Table 60) - */ - -#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 -#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE) -#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE) - -#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 -#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL) -#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL) - -#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 -#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE) -#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE) - -#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 -#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE) -#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE) - -#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 -#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD) -#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD) - -#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 -#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) - -#define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31 -#define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP) - - -/* - * L2 Misc1 Value Register (Table 60) - */ - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0) - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1) - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2) - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3) - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4) - - -/* - * L2 Misc2 Value Register (Table 60) - */ - -#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8) - -#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9) - -#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A) - - -#endif /* _BCM1480_L2C_H */ diff --git a/arch/mips/include/asm/sibyte/bcm1480_mc.h b/arch/mips/include/asm/sibyte/bcm1480_mc.h deleted file mode 100644 index f26a41a..0000000 --- a/arch/mips/include/asm/sibyte/bcm1480_mc.h +++ /dev/null @@ -1,984 +0,0 @@ -/* ********************************************************************* - * BCM1280/BCM1480 Board Support Package - * - * Memory Controller constants File: bcm1480_mc.h - * - * This module contains constants and macros useful for - * programming the memory controller. - * - * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy) - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _BCM1480_MC_H -#define _BCM1480_MC_H - -#include "sb1250_defs.h" - -/* - * Memory Channel Configuration Register (Table 81) - */ - -#define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) - -#define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) - -#define S_BCM1480_MC_INTLV2 16 -#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2) -#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) -#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) -#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) - -#define S_BCM1480_MC_CS_MODE 32 -#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE) -#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) -#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) -#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) - -#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ - V_BCM1480_MC_INTLV1_DEFAULT | \ - V_BCM1480_MC_INTLV2_DEFAULT | \ - V_BCM1480_MC_CS_MODE_DEFAULT) - -#define K_BCM1480_MC_CS01_MODE 0x03 -#define K_BCM1480_MC_CS02_MODE 0x05 -#define K_BCM1480_MC_CS0123_MODE 0x0F -#define K_BCM1480_MC_CS0246_MODE 0x55 -#define K_BCM1480_MC_CS0145_MODE 0x33 -#define K_BCM1480_MC_CS0167_MODE 0xC3 -#define K_BCM1480_MC_CSFULL_MODE 0xFF - -/* - * Chip Select Start Address Register (Table 82) - */ - -#define S_BCM1480_MC_CS0_START 0 -#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START) -#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) -#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START) - -#define S_BCM1480_MC_CS1_START 16 -#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START) -#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START) -#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START) - -#define S_BCM1480_MC_CS2_START 32 -#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START) -#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START) -#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START) - -#define S_BCM1480_MC_CS3_START 48 -#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START) -#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START) -#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START) - -/* - * Chip Select End Address Register (Table 83) - */ - -#define S_BCM1480_MC_CS0_END 0 -#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END) -#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END) -#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END) - -#define S_BCM1480_MC_CS1_END 16 -#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END) -#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END) -#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END) - -#define S_BCM1480_MC_CS2_END 32 -#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END) -#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END) -#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END) - -#define S_BCM1480_MC_CS3_END 48 -#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END) -#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END) -#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END) - -/* - * Row Address Bit Select Register 0 (Table 84) - */ - -#define S_BCM1480_MC_ROW00 0 -#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00) -#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) -#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00) - -#define S_BCM1480_MC_ROW01 8 -#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01) -#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) -#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01) - -#define S_BCM1480_MC_ROW02 16 -#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02) -#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) -#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02) - -#define S_BCM1480_MC_ROW03 24 -#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03) -#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03) -#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03) - -#define S_BCM1480_MC_ROW04 32 -#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04) -#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04) -#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04) - -#define S_BCM1480_MC_ROW05 40 -#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05) -#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05) -#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05) - -#define S_BCM1480_MC_ROW06 48 -#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06) -#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06) -#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06) - -#define S_BCM1480_MC_ROW07 56 -#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07) -#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07) -#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07) - -/* - * Row Address Bit Select Register 1 (Table 85) - */ - -#define S_BCM1480_MC_ROW08 0 -#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08) -#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08) -#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08) - -#define S_BCM1480_MC_ROW09 8 -#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09) -#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09) -#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09) - -#define S_BCM1480_MC_ROW10 16 -#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10) -#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10) -#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10) - -#define S_BCM1480_MC_ROW11 24 -#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11) -#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11) -#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11) - -#define S_BCM1480_MC_ROW12 32 -#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12) -#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12) -#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12) - -#define S_BCM1480_MC_ROW13 40 -#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13) -#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13) -#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13) - -#define S_BCM1480_MC_ROW14 48 -#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14) -#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14) -#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14) - -#define K_BCM1480_MC_ROWX_BIT_SPACING 8 - -/* - * Column Address Bit Select Register 0 (Table 86) - */ - -#define S_BCM1480_MC_COL00 0 -#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00) -#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00) -#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00) - -#define S_BCM1480_MC_COL01 8 -#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01) -#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01) -#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01) - -#define S_BCM1480_MC_COL02 16 -#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02) -#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02) -#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02) - -#define S_BCM1480_MC_COL03 24 -#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03) -#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03) -#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03) - -#define S_BCM1480_MC_COL04 32 -#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04) -#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04) -#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04) - -#define S_BCM1480_MC_COL05 40 -#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05) -#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05) -#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05) - -#define S_BCM1480_MC_COL06 48 -#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06) -#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06) -#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06) - -#define S_BCM1480_MC_COL07 56 -#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07) -#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07) -#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07) - -/* - * Column Address Bit Select Register 1 (Table 87) - */ - -#define S_BCM1480_MC_COL08 0 -#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08) -#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08) -#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08) - -#define S_BCM1480_MC_COL09 8 -#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09) -#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09) -#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09) - -#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ - -#define S_BCM1480_MC_COL11 24 -#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11) -#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11) -#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11) - -#define S_BCM1480_MC_COL12 32 -#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12) -#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12) -#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12) - -#define S_BCM1480_MC_COL13 40 -#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13) -#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13) -#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13) - -#define S_BCM1480_MC_COL14 48 -#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14) -#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14) -#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14) - -#define K_BCM1480_MC_COLX_BIT_SPACING 8 - -/* - * CS0 and CS1 Bank Address Bit Select Register (Table 88) - */ - -#define S_BCM1480_MC_CS01_BANK0 0 -#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0) -#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0) -#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0) - -#define S_BCM1480_MC_CS01_BANK1 8 -#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1) -#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1) -#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1) - -#define S_BCM1480_MC_CS01_BANK2 16 -#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2) -#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2) -#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2) - -/* - * CS2 and CS3 Bank Address Bit Select Register (Table 89) - */ - -#define S_BCM1480_MC_CS23_BANK0 0 -#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0) -#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0) -#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0) - -#define S_BCM1480_MC_CS23_BANK1 8 -#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1) -#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1) -#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1) - -#define S_BCM1480_MC_CS23_BANK2 16 -#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2) -#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2) -#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2) - -#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 - -/* - * DRAM Command Register (Table 90) - */ - -#define S_BCM1480_MC_COMMAND 0 -#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND) -#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND) -#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND) - -#define K_BCM1480_MC_COMMAND_EMRS 0 -#define K_BCM1480_MC_COMMAND_MRS 1 -#define K_BCM1480_MC_COMMAND_PRE 2 -#define K_BCM1480_MC_COMMAND_AR 3 -#define K_BCM1480_MC_COMMAND_SETRFSH 4 -#define K_BCM1480_MC_COMMAND_CLRRFSH 5 -#define K_BCM1480_MC_COMMAND_SETPWRDN 6 -#define K_BCM1480_MC_COMMAND_CLRPWRDN 7 - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define K_BCM1480_MC_COMMAND_EMRS2 8 -#define K_BCM1480_MC_COMMAND_EMRS3 9 -#define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10 -#define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 -#endif - -#define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) -#define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) -#define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) -#define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) -#define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) -#define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) -#define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) -#define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) -#define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) -#define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) -#define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) -#endif - -#define S_BCM1480_MC_CS0 4 -#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) -#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) -#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) -#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) -#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) -#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) -#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) -#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) - -#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0) -#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) -#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0) - -#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) - -/* - * DRAM Mode Register (Table 91) - */ - -#define S_BCM1480_MC_EMODE 0 -#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE) -#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE) -#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE) -#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) - -#define S_BCM1480_MC_MODE 16 -#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE) -#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE) -#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE) -#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) - -#define S_BCM1480_MC_DRAM_TYPE 32 -#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE) -#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE) -#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE) - -#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 -#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define K_BCM1480_MC_DRAM_TYPE_DDR2 2 -#endif - -#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0 - -#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) -#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) -#endif - -#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) -#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) -#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) -#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) - -#define S_BCM1480_MC_PG_POLICY 40 -#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY) -#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY) -#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY) - -#define K_BCM1480_MC_PG_POLICY_CLOSED 0 -#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 - -#define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) -#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42) -#define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43) -#endif - -#define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ -