From sshtylyov@mvista.com Tue May 1 01:00:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 01:01:00 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:43265 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903720Ab2D3XAx (ORCPT ); Tue, 1 May 2012 01:00:53 +0200 Received: by lbbgg6 with SMTP id gg6so939417lbb.36 for ; Mon, 30 Apr 2012 16:00:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=EYs4+oqXLZaXmVvuOBoq6n7JvXBjwMyaBHuZlj3h3Y4=; b=Og0bsfq4MMKrGcBzPImqjah2pproHcIp+bSMVbS3cibTQ+yBuUZfiy7Uc4sJ0E8yRO gnxe2crNh/3+uvscQbRv4osuxrDYmh+pD4jhtRLhQv1OXUXX8rSjiYiREis18XQxTgyT ieW3sHsCpXZPhqhF9yFq6UpjLuzK+oemX4anPm7CbDxWX17jEr+Qi7t9z8+PuwJWoZ0U Smdbx+4YZDNdYNrmxb2nXjfXAHi+x//1LNOv804lsJqi9I9y8qQ3DXxt8KGrEMc1Cuet dkaw8S3YGO61WFOvM2HMSAT7yCNrr2o9O1BZL4kWrXRnjXoU77yYdAtXn2KDdc6VKBrf ejjQ== Received: by 10.112.25.40 with SMTP id z8mr10631197lbf.95.1335826844885; Mon, 30 Apr 2012 16:00:44 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-91-188.pppoe.mtu-net.ru. [91.79.91.188]) by mx.google.com with ESMTPS id pb13sm17970645lab.16.2012.04.30.16.00.41 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 Apr 2012 16:00:42 -0700 (PDT) Message-ID: <4F9F192D.8060207@mvista.com> Date: Tue, 01 May 2012 02:58:53 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120420 Thunderbird/12.0 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [PATCH 04/14] MIPS: Add helper function to allow platforms to point at a DTB. References: <1335785589-32532-1-git-send-email-blogic@openwrt.org> <1335785589-32532-4-git-send-email-blogic@openwrt.org> In-Reply-To: <1335785589-32532-4-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkOBub3nA2cZemkkMlLLUSEy5/VR6L4WgSbWvfCGrZNZst/a1odIa7PjTjyDVvn8OSULHRe X-archive-position: 33101 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1149 Lines: 42 Hello. On 30-04-2012 15:32, John Crispin wrote: > Add __dt_setup_arch() that can be called to load a builtin DT. > Additionally we add a macro to allow loading a specific symbol > from the __dtb_* section. > Signed-off-by: Ralf Baechle > Signed-off-by: John Crispin > --- > arch/mips/include/asm/prom.h | 11 +++++++++++ > arch/mips/kernel/prom.c | 14 ++++++++++++++ > 2 files changed, 25 insertions(+), 0 deletions(-) > diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c > index 558b539..271ad98 100644 > --- a/arch/mips/kernel/prom.c > +++ b/arch/mips/kernel/prom.c > @@ -95,3 +95,17 @@ void __init device_tree_init(void) > /* free the space reserved for the dt blob */ > free_mem_mach(base, size); > } > + > +void __init __dt_setup_arch(struct boot_param_header *bph) > +{ > + unsigned long size; > + > + if (be32_to_cpu(bph->magic) != OF_DT_HEADER) { > + pr_err("DTB has bad magic, ignoring builtin OF DTB\n"); > + > + return; > + } > + > + initial_boot_params = bph; > + size = be32_to_cpu(bph->totalsize); 'size' only assigned, not used. > +} WBR, Sergei From sshtylyov@mvista.com Tue May 1 01:03:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 01:03:42 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:54433 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903720Ab2D3XDf (ORCPT ); Tue, 1 May 2012 01:03:35 +0200 Received: by lbbgg6 with SMTP id gg6so940906lbb.36 for ; Mon, 30 Apr 2012 16:03:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=uomlzoNfU7YF6iNaEYGdDFLBnUGTpYX+JOlIv1HXYoU=; b=Wb9ynJjEWAZOvpanES4j1/6CJ7iNDrRdMYmzzsrNvX9y9+cLwk07J3KyXee3s+b7ju CdfVXaL/QC3b1t1bSUkh35J6gvc6M3pwJupjNvoGHZQ6OeAm0vpIe0psPppcH/8kg0j3 rwQQdKrTU3V2w4xQcqeDD0rxgI1d9Po52bW5Q37k4gqCBrZ4KxffLRZ5sCkK3Bf0NYME LozvV44R6lFhYvsVVeAL+6w/SfRketWFd6S3nl46p7/O2WpuMtSLyQthS/ZouWgrHcqa 5qlS8mCPDn51HvJGtad1WiHyi8+iouePoR93fRI1rOQsy64/aKGWviiE3KhdXuBM/ejT uASA== Received: by 10.112.29.40 with SMTP id g8mr10521361lbh.39.1335827010177; Mon, 30 Apr 2012 16:03:30 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-91-188.pppoe.mtu-net.ru. [91.79.91.188]) by mx.google.com with ESMTPS id ph8sm17979237lab.15.2012.04.30.16.03.27 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 Apr 2012 16:03:28 -0700 (PDT) Message-ID: <4F9F19D3.7040006@mvista.com> Date: Tue, 01 May 2012 03:01:39 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120420 Thunderbird/12.0 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [PATCH 08/14] MIPS: lantiq: clear all irqs properly on boot References: <1335785589-32532-1-git-send-email-blogic@openwrt.org> <1335785589-32532-8-git-send-email-blogic@openwrt.org> In-Reply-To: <1335785589-32532-8-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkfHr7xkj3z276YLYctUdaP+1qj5DZRu7PAOCa5Eb5NhJr1h4QxBTLAkaMpclvLY5Pcrqd5 X-archive-position: 33102 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1169 Lines: 40 Hello. On 30-04-2012 15:33, John Crispin wrote: > Due to a wrongly placed bracket, I don't see a bracket in old code at all. > the irq modules were not properly reset on > boot. > Signed-off-by: John Crispin > --- > arch/mips/lantiq/irq.c | 11 ++++++----- > 1 files changed, 6 insertions(+), 5 deletions(-) > diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c > index d673731..b6b1c72 100644 > --- a/arch/mips/lantiq/irq.c > +++ b/arch/mips/lantiq/irq.c > @@ -271,12 +271,13 @@ void __init arch_init_irq(void) > if (!ltq_eiu_membase) > panic("Failed to remap eiu memory"); > > - /* make sure all irqs are turned off by default */ > - for (i = 0; i< 5; i++) > + /* turn off all irqs by default */ > + for (i = 0; i< 5; i++) { > + /* make sure all irqs are turned off by default */ > ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); > - > - /* clear all possibly pending interrupts */ > - ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); > + /* clear all possibly pending interrupts */ > + ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); > + } > > mips_cpu_irq_init(); WBR, Sergei From macro@linux-mips.org Tue May 1 02:23:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 02:23:58 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:47343 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2EAAXw (ORCPT ); Tue, 1 May 2012 02:23:52 +0200 Date: Tue, 1 May 2012 01:23:52 +0100 (BST) From: "Maciej W. Rozycki" To: Jonas Gorski cc: "Steven J. Hill" , linux-mips@linux-mips.org, ralf@linux-mips.org, sjhill@realitydiluted.com Subject: Re: [PATCH 1/5] MIPS: Add support for the 1074K core. In-Reply-To: Message-ID: References: <1333735064-15672-1-git-send-email-sjhill@mips.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=ISO-8859-15 Content-Transfer-Encoding: 8BIT X-archive-position: 33103 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1165 Lines: 27 On Sat, 7 Apr 2012, Jonas Gorski wrote: > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > > index bda8eb2..a08e75d 100644 > > --- a/arch/mips/mm/c-r4k.c > > +++ b/arch/mips/mm/c-r4k.c > > @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) > >                        c->icache.linesz = 2 << lsize; > >                else > >                        c->icache.linesz = lsize; > > -               c->icache.sets = 64 << ((config1 >> 22) & 7); > > +               c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); > > Why this change? According to the 1074K datasheet it is still 64 * > 2^S, so to me it looks like the previous version was correct. Also > adding first and then masking looks really wrong, and will produce > wrong results for 0x7. FWIW the change looks correct to me. The 3-bit field means 32 for 7, 64 for 0, 128 for 1, etc., up to 4096 for 6. It used to be reserved for 7 in older versions of the architecture spec (rev. 3.05 referred here). Likewise the data cache. Of course it should be sent as a separate change too, even if the 1074K relies on it (which I suppose is why it's been included here). Maciej From macro@linux-mips.org Tue May 1 02:26:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 02:26:39 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:47506 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903724Ab2EAA0c (ORCPT ); Tue, 1 May 2012 02:26:32 +0200 Date: Tue, 1 May 2012 01:26:32 +0100 (BST) From: "Maciej W. Rozycki" To: "Steven J. Hill" cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 04/10] MIPS: Add micro-assembler support for 'ins' and 'ext' instructions. In-Reply-To: <1333817315-30091-5-git-send-email-sjhill@mips.com> Message-ID: References: <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-5-git-send-email-sjhill@mips.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33104 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1455 Lines: 31 On Sat, 7 Apr 2012, Steven J. Hill wrote: > diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c > index 5fa1851..fb6d8e27 100644 > --- a/arch/mips/mm/uasm.c > +++ b/arch/mips/mm/uasm.c > @@ -63,6 +63,7 @@ enum opcode { > insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, > insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, > insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret, > + insn_ins, insn_ext, > insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, > insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, > insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, > @@ -113,6 +114,8 @@ static struct insn insn_table[] __uasminitdata = { > { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, > { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, > { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, > + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, > + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, > { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, > { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, > { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, Not an extensive review -- just noticed this issue while browsing... These two data definitions are clearly alphabetically ordered, so please keep them as such. It seems rather a trivial update in this case -- just swap the new entries. Thanks. Maciej From david.daney@cavium.com Tue May 1 02:50:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 02:50:11 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17844 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903724Ab2EAAuD (ORCPT ); Tue, 1 May 2012 02:50:03 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 30 Apr 2012 17:51:49 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 30 Apr 2012 17:49:59 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 30 Apr 2012 17:49:59 -0700 Message-ID: <4F9F3337.6040604@cavium.com> Date: Mon, 30 Apr 2012 17:49:59 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 04/10] MIPS: Add micro-assembler support for 'ins' and 'ext' instructions. References: <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-5-git-send-email-sjhill@mips.com> In-Reply-To: <1333817315-30091-5-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 May 2012 00:49:59.0419 (UTC) FILETIME=[55C244B0:01CD2734] X-archive-position: 33105 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3881 Lines: 109 On 04/07/2012 09:48 AM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Add the MIPS32R2 'ins' and 'ext' instructions for use by the > kernel's micro-assembler. > > Signed-off-by: Steven J. Hill > --- > arch/mips/include/asm/uasm.h | 15 +++++++++++++++ > arch/mips/mm/tlbex.c | 17 +++++++++++++++++ I would split the tlbex.c changes into a separate patch. The changelog doesn't even mention the changes you are making to this file. > arch/mips/mm/uasm.c | 15 +++++++++++++++ > 3 files changed, 47 insertions(+) > [...] > --- a/arch/mips/mm/tlbex.c > +++ b/arch/mips/mm/tlbex.c > @@ -921,6 +921,13 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) > #endif > uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ > uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); > +#ifdef CONFIG_32BIT > + if (cpu_has_mips32r2) { > + uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT)); > + uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT)); > + return; > + } > +#endif Can we somehow get rid of the #ifdef? You are already doing if(condition) around the same code. > uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ > uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); > uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ > @@ -956,6 +963,16 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) > > static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) > { > +#ifdef CONFIG_32BIT > + if (cpu_has_mips32r2) { > + /* For MIPS32R2, PTE ptr offset is obtained from BadVAddr */ > + UASM_i_MFC0(p, tmp, C0_BADVADDR); > + UASM_i_LW(p, ptr, 0, ptr); > + UASM_i_EXT(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1); > + UASM_i_INS(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1); > + return; > + } > +#endif Same here. > /* > * Bug workaround for the Nevada. It seems as if under certain > * circumstances the move from cp0_context might produce a > diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c > index 5fa1851..fb6d8e27 100644 > --- a/arch/mips/mm/uasm.c > +++ b/arch/mips/mm/uasm.c > @@ -63,6 +63,7 @@ enum opcode { > insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, > insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, > insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret, > + insn_ins, insn_ext, > insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, > insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, > insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, > @@ -113,6 +114,8 @@ static struct insn insn_table[] __uasminitdata = { > { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, > { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, > { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, > + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, > + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, > { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, > { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, > { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, > @@ -287,6 +290,16 @@ static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) > (*buf)++; > } > > +#define I_bit_extract(op) \ > +Ip_bit_extract(op) \ The names don't match the pattern, look at the dins for example. > +{ \ > + build_insn(buf, insn##op, b, a, d-1, c); \ > +} > +#define I_bit_insert(op) \ > +Ip_bit_insert(op) \ > +{ \ > + build_insn(buf, insn##op, b, a, c+d-1, c); \ > +} > #define I_u1u2u3(op) \ > Ip_u1u2u3(op) \ > { \ > @@ -396,6 +409,8 @@ I_u2u1u3(_drotr) > I_u2u1u3(_drotr32) > I_u3u1u2(_dsubu) > I_0(_eret) > +I_bit_insert(_ins) > +I_bit_extract(_ext) > I_u1(_j) > I_u1(_jal) > I_u1(_jr) From david.daney@cavium.com Tue May 1 02:51:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 02:51:34 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17892 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903724Ab2EAAva (ORCPT ); Tue, 1 May 2012 02:51:30 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 30 Apr 2012 17:53:09 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 30 Apr 2012 17:51:20 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 30 Apr 2012 17:51:20 -0700 Message-ID: <4F9F3387.1050500@cavium.com> Date: Mon, 30 Apr 2012 17:51:19 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: "Steven J. Hill" , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 04/10] MIPS: Add micro-assembler support for 'ins' and 'ext' instructions. References: <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-5-git-send-email-sjhill@mips.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 May 2012 00:51:20.0045 (UTC) FILETIME=[85D0D1D0:01CD2734] X-archive-position: 33106 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1681 Lines: 38 On 04/30/2012 05:26 PM, Maciej W. Rozycki wrote: > On Sat, 7 Apr 2012, Steven J. Hill wrote: > >> diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c >> index 5fa1851..fb6d8e27 100644 >> --- a/arch/mips/mm/uasm.c >> +++ b/arch/mips/mm/uasm.c >> @@ -63,6 +63,7 @@ enum opcode { >> insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, >> insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, >> insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret, >> + insn_ins, insn_ext, >> insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, >> insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, >> insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, >> @@ -113,6 +114,8 @@ static struct insn insn_table[] __uasminitdata = { >> { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, >> { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, >> { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, >> + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, >> + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, >> { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, >> { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, >> { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, > > Not an extensive review -- just noticed this issue while browsing... > > These two data definitions are clearly alphabetically ordered, so please > keep them as such. It seems rather a trivial update in this case -- just > swap the new entries. Thanks. Well I broke the ordering with a bunch of my patches lower down. Perhaps we should fix it so it goes back to being ordered. David Daney From blogic@openwrt.org Tue May 1 08:38:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 08:38:34 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:33633 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901761Ab2EAGi2 (ORCPT ); Tue, 1 May 2012 08:38:28 +0200 Message-ID: <4F9F8494.1010002@openwrt.org> Date: Tue, 01 May 2012 08:37:08 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [PATCH 08/14] MIPS: lantiq: clear all irqs properly on boot References: <1335785589-32532-1-git-send-email-blogic@openwrt.org> <1335785589-32532-8-git-send-email-blogic@openwrt.org> <4F9F19D3.7040006@mvista.com> In-Reply-To: <4F9F19D3.7040006@mvista.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33107 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 275 Lines: 14 On 01/05/12 01:01, Sergei Shtylyov wrote: > Hello. > > On 30-04-2012 15:33, John Crispin wrote: > >> Due to a wrongly placed bracket, > > I don't see a bracket in old code at all. Wrongly placed in a different file :-) Thanks, i will make the message more precise John From macro@linux-mips.org Tue May 1 11:43:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 11:43:57 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:50107 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903542Ab2EAJns (ORCPT ); Tue, 1 May 2012 11:43:48 +0200 Date: Tue, 1 May 2012 10:43:48 +0100 (BST) From: "Maciej W. Rozycki" To: "Steven J. Hill" cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 2/9] MIPS: Optimise core library functions for microMIPS. In-Reply-To: <1333984923-445-3-git-send-email-sjhill@mips.com> Message-ID: References: <1333984923-445-1-git-send-email-sjhill@mips.com> <1333984923-445-3-git-send-email-sjhill@mips.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33108 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6295 Lines: 210 On Mon, 9 Apr 2012, Steven J. Hill wrote: > diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S > index 606c8a9..a0df003 100644 > --- a/arch/mips/lib/memset.S > +++ b/arch/mips/lib/memset.S > @@ -26,23 +35,36 @@ > .previous > > .macro f_fill64 dst, offset, val, fixup > - EX(LONG_S, \val, (\offset + 0 * LONGSIZE)(\dst), \fixup) > - EX(LONG_S, \val, (\offset + 1 * LONGSIZE)(\dst), \fixup) > - EX(LONG_S, \val, (\offset + 2 * LONGSIZE)(\dst), \fixup) > - EX(LONG_S, \val, (\offset + 3 * LONGSIZE)(\dst), \fixup) > - EX(LONG_S, \val, (\offset + 4 * LONGSIZE)(\dst), \fixup) > - EX(LONG_S, \val, (\offset + 5 * LONGSIZE)(\dst), \fixup) > - EX(LONG_S, \val, (\offset + 6 * LONGSIZE)(\dst), \fixup) > - EX(LONG_S, \val, (\offset + 7 * LONGSIZE)(\dst), \fixup) > +#ifdef CONFIG_CPU_MICROMIPS > + EX(swp, t8, (\offset + 0 * STORSIZE)(\dst), \fixup) > + EX(swp, t8, (\offset + 1 * STORSIZE)(\dst), \fixup) > + EX(swp, t8, (\offset + 2 * STORSIZE)(\dst), \fixup) > + EX(swp, t8, (\offset + 3 * STORSIZE)(\dst), \fixup) > +#if LONGSIZE == 4 > + EX(swp, t8, (\offset + 4 * STORSIZE)(\dst), \fixup) > + EX(swp, t8, (\offset + 5 * STORSIZE)(\dst), \fixup) > + EX(swp, t8, (\offset + 6 * STORSIZE)(\dst), \fixup) > + EX(swp, t8, (\offset + 7 * STORSIZE)(\dst), \fixup) > +#endif This looks bogus to me, either define LONG_SP to SWP or SDP (in ) based on _MIPS_SZLONG or #error on LONGSIZE != 4. Also it would make sense to make this macro respect val in the microMIPS mode too, then an appropriate #define to a1/t8 elsewhere in this file will do. Otherwise it's pure obfuscation. > diff --git a/arch/mips/lib/strlen_user.S b/arch/mips/lib/strlen_user.S > index fdbb970..60fa23b 100644 > --- a/arch/mips/lib/strlen_user.S > +++ b/arch/mips/lib/strlen_user.S > @@ -28,9 +29,13 @@ LEAF(__strlen_user_asm) > > FEXPORT(__strlen_user_nocheck_asm) > move v0, a0 > -1: EX(lb, t0, (v0), .Lfault) > +#ifdef CONFIG_CPU_MICROMIPS > +1: EX(lbu16, v1, (v0), .Lfault) > +#else > +1: EX(lb, v1, (v0), .Lfault) > +#endif > PTR_ADDIU v0, 1 > - bnez t0, 1b > + bnez v1, 1b > PTR_SUBU v0, a0 > jr ra > END(__strlen_user_asm) Perhaps just LBU in all cases? You'll avoid the ugly #ifdef. > diff --git a/arch/mips/lib/strncpy_user.S b/arch/mips/lib/strncpy_user.S > index 7201b2f..bcbb9a0 100644 > --- a/arch/mips/lib/strncpy_user.S > +++ b/arch/mips/lib/strncpy_user.S > @@ -30,30 +31,32 @@ > LEAF(__strncpy_from_user_asm) > LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? > and v0, a1 > +#ifdef CONFIG_CPU_MICROMIPS > + bnezc v0, .Lfault > +#else > bnez v0, .Lfault > +#endif You don't need this, .Lfault is surely within 126 bytes from here so GAS will relax the branch to its 16-bit encoding which will give an equivalent result. Relaxing to compact branches is not supported by GAS at the moment. > FEXPORT(__strncpy_from_user_nocheck_asm) > - move v0, zero > - move v1, a1 > .set noreorder > -1: EX(lbu, t0, (v1), .Lfault) > + move t0, zero > + move v1, a1 > +1: EX(lbu, v0, (v1), .Lfault) > PTR_ADDIU v1, 1 > R10KCBARRIER(0(ra)) > - beqz t0, 2f > - sb t0, (a0) > - PTR_ADDIU v0, 1 > - .set reorder > - PTR_ADDIU a0, 1 > - bne v0, a2, 1b > -2: PTR_ADDU t0, a1, v0 > - xor t0, a1 > - bltz t0, .Lfault > + beqz v0, 2f > + sb v0, (a0) > + PTR_ADDIU t0, 1 > + bne t0, a2, 1b > + PTR_ADDIU a0, 1 > +2: PTR_ADDU v0, a1, t0 > + xor v0, a1 > + bltz v0, .Lfault > + nop > jr ra # return n > + move v0, t0 > END(__strncpy_from_user_asm) You don't need all of this, GAS will schedule these delay slots just fine in the microMIPS mode. > -.Lfault: li v0, -EFAULT > +.Lfault: > jr ra > - > - .section __ex_table,"a" > - PTR 1b, .Lfault > - .previous > + li v0, -EFAULT It looks like an independent bug fix -- submit separately? > diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S > index 6445716..9090ced 100644 > --- a/arch/mips/lib/strnlen_user.S > +++ b/arch/mips/lib/strnlen_user.S > @@ -26,21 +27,34 @@ > * the maximum is a tad hairier ... > */ > LEAF(__strnlen_user_asm) > + .set noreorder > LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? > and v0, a0 > +#ifdef CONFIG_CPU_MICROMIPS > + bnezc v0, .Lfault > +#else > bnez v0, .Lfault > +#endif Again you don't need this, see above. > FEXPORT(__strnlen_user_nocheck_asm) > - move v0, a0 > PTR_ADDU a1, a0 # stop pointer > + move v0, a0 > 1: beq v0, a1, 1f # limit reached? > + nop > EX(lb, t0, (v0), .Lfault) > - PTR_ADDU v0, 1 > +#ifdef CONFIG_CPU_MICROMIPS > + addius5 v0, 1 > + bnezc t0, 1b > +1: jr ra > + PTR_SUBU v0, a0 > +#else > bnez t0, 1b > -1: PTR_SUBU v0, a0 > - jr ra > + PTR_ADDU v0, 1 > +1: jr ra > + PTR_SUBU v0, a0 > +#endif > END(__strnlen_user_asm) > > .Lfault: > - move v0, zero > jr ra > + move v0, zero You don't need all of this if you discard .set noreorder and let GAS schedule the instructions and pick their optimal encodings itself. > diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c > index cc0b626..be71d38 100644 > --- a/arch/mips/mm/page.c > +++ b/arch/mips/mm/page.c > @@ -368,6 +360,12 @@ void __cpuinit build_clear_page(void) > for (i = 0; i < (buf - clear_page_array); i++) > pr_debug("\t.word 0x%08x\n", clear_page_array[i]); > pr_debug("\t.set pop\n"); > +#ifdef CONFIG_CPU_MICROMIPS > + memcpy(((u8 *)clear_page) - 1, clear_page_array, > + ARRAY_SIZE(clear_page_array) * 4); > +#else > + memcpy(clear_page, clear_page_array, ARRAY_SIZE(clear_page_array) * 4); > +#endif > } > > static void __cpuinit build_copy_load(u32 **buf, int reg, int off) > @@ -607,6 +605,12 @@ void __cpuinit build_copy_page(void) > for (i = 0; i < (buf - copy_page_array); i++) > pr_debug("\t.word 0x%08x\n", copy_page_array[i]); > pr_debug("\t.set pop\n"); > +#ifdef CONFIG_CPU_MICROMIPS > + memcpy(((u8 *)copy_page) - 1, copy_page_array, > + ARRAY_SIZE(copy_page_array) * 4); > +#else > + memcpy(copy_page, copy_page_array, ARRAY_SIZE(copy_page_array) * 4); > +#endif > } > > #ifdef CONFIG_SIBYTE_DMA_PAGEOPS I suggest that instead of the hacks above you arrange for an alias to copy_page with the ISA bit clear. You won't need these changes then (and will get slightly better machine code). Maciej From blogic@openwrt.org Tue May 1 13:19:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 13:19:18 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:51547 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903542Ab2EALTM (ORCPT ); Tue, 1 May 2012 13:19:12 +0200 Message-ID: <4F9FC65E.6000501@openwrt.org> Date: Tue, 01 May 2012 13:17:50 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: David Daney CC: Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [PATCH 02/14] MIPS: pci: parse memory ranges from devicetree References: <1335785589-32532-1-git-send-email-blogic@openwrt.org> <1335785589-32532-2-git-send-email-blogic@openwrt.org> <4F9EC3FD.4010109@cavium.com> In-Reply-To: <4F9EC3FD.4010109@cavium.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33109 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 650 Lines: 24 On 30/04/12 18:55, David Daney wrote: >> struct pci_ops *pci_ops; >> struct resource *mem_resource; >> @@ -142,4 +148,10 @@ static inline int pci_get_legacy_ide_irq(struct >> pci_dev *dev, int channel) >> >> extern char * (*pcibios_plat_setup)(char *str); >> >> +#ifdef CONFIG_OF >> +/* this function parses memory ranges from a device node */ >> +extern void __devinit pci_load_OF_ranges(struct pci_controller *hose, >> + struct device_node *node); >> +#endif > > Again, no #ifdef. Hi, are you sure that we don't want to #ifdef this prototype ? The function is only available when OF is selected. Thanks, John From blogic@openwrt.org Tue May 1 15:29:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 15:29:54 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:47858 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903717Ab2EAN3p (ORCPT ); Tue, 1 May 2012 15:29:45 +0200 Message-ID: <4F9FE4F6.5070909@openwrt.org> Date: Tue, 01 May 2012 15:28:22 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: David Daney CC: Ralf Baechle , Grant Likely , linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org Subject: Re: [PATCH] OF: PCI: const usage needed by MIPS References: <1335808019-24502-1-git-send-email-blogic@openwrt.org> <4F9ED1DC.3050007@gmail.com> In-Reply-To: <4F9ED1DC.3050007@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33110 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 888 Lines: 29 On 30/04/12 19:54, David Daney wrote: > On 04/30/2012 10:46 AM, John Crispin wrote: >> On MIPS we want to call of_irq_map_pci from inside >> >> arch/mips/include/asm/pci.h:extern int pcibios_map_irq( >> const struct pci_dev *dev, u8 slot, u8 pin); >> >> For this to work we need to change several functions to const usage. > > I think there is a mismatch on this throughout the kernel. > > Properly fixing it requires touching many more places than these. > Although I haven't tried it, I wouldn't be surprised if doing this > caused warnings to appear in non-MIPS code. > > Ralf had a patch at one point that tried to make this consistent > tree-wide, but it is not yet applied. > > David Daney Hi, Ok, lets see what Ralf has to say. I just tested the patch on x86 with OF enabled and drivers turned on that use the API. I did not see any errors appear. Thanks, John From a.p.zijlstra@chello.nl Tue May 1 20:28:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 20:29:05 +0200 (CEST) Received: from casper.infradead.org ([85.118.1.10]:37251 "EHLO casper.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903733Ab2EAS27 (ORCPT ); Tue, 1 May 2012 20:28:59 +0200 Received: from dhcp-089-099-019-018.chello.nl ([89.99.19.18] helo=twins) by casper.infradead.org with esmtpsa (Exim 4.76 #1 (Red Hat Linux)) id 1SPHoM-0007h5-B5; Tue, 01 May 2012 18:28:30 +0000 Received: by twins (Postfix, from userid 0) id 8E9ED80306B7; Tue, 1 May 2012 20:28:21 +0200 (CEST) Message-Id: <20120501182610.986663560@chello.nl> User-Agent: quilt/0.48-1 Date: Tue, 01 May 2012 20:14:35 +0200 From: Peter Zijlstra To: mingo@kernel.org, pjt@google.com, vatsa@in.ibm.com, suresh.b.siddha@intel.com, efault@gmx.de Cc: linux-kernel@vger.kernel.org, Anton Blanchard , Benjamin Herrenschmidt , Chris Metcalf , David Howells , "David S. Miller" , Fenghua Yu , "H. Peter Anvin" , Ingo Molnar , Ivan Kokshaysky , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, Matt Turner , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , x86@kernel.org, Dimitri Sivanich , Greg Pearson , KAMEZAWA Hiroyuki , bob.picco@oracle.com, chris.mason@oracle.com, Peter Zijlstra Subject: [RFC][PATCH 5/5] sched: Rewrite the CONFIG_NUMA sched domain support References: <20120501181430.007891123@chello.nl> Content-Disposition: inline; filename=sched-numa-domains.patch X-archive-position: 33111 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: a.p.zijlstra@chello.nl Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 20096 Lines: 712 The current code groups up to 16 nodes in a level and then puts an ALLNODES domain spanning the entire tree on top of that. This doesn't reflect the numa topology and esp for the smaller not-fully-connected machines out there today this might make a difference. Therefore, build a proper numa topology based on node_distance(). Since there's no fixed numa layers anymore, the static SD_NODE_INIT and SD_ALLNODES_INIT aren't usable anymore, the new code tries to construct something similar and scales some values either on the number of cpus in the domain and/or the node_distance() ratio. Anton (IBM)/Dimitri (SGI)/Greg (HP)/Kamezawa-san (Fujitsu)/Oracle, could I get node_distance() tables for your 'current' line-up of silly large machines? You can get them by doing: $ cat /sys/devices/system/node/node*/distance If this information is 'sekrit' please consider sending it privately. If you're not the right person to ask, please redirect me. Also, testing this code on your favourite large NUMA machine would be most appreciated. Cc: Anton Blanchard Cc: Benjamin Herrenschmidt Cc: Chris Metcalf Cc: David Howells Cc: "David S. Miller" Cc: Fenghua Yu Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Ivan Kokshaysky Cc: linux-alpha@vger.kernel.org Cc: linux-ia64@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-sh@vger.kernel.org Cc: Matt Turner Cc: Paul Mackerras Cc: Paul Mundt Cc: Ralf Baechle Cc: Richard Henderson Cc: sparclinux@vger.kernel.org Cc: Thomas Gleixner Cc: Tony Luck Cc: x86@kernel.org Cc: Dimitri Sivanich Cc: Greg Pearson Cc: KAMEZAWA Hiroyuki Cc: bob.picco@oracle.com Cc: chris.mason@oracle.com Signed-off-by: Peter Zijlstra --- arch/ia64/include/asm/topology.h | 25 -- arch/mips/include/asm/mach-ip27/topology.h | 17 - arch/powerpc/include/asm/topology.h | 36 --- arch/sh/include/asm/topology.h | 25 -- arch/sparc/include/asm/topology_64.h | 19 - arch/tile/include/asm/topology.h | 26 -- arch/x86/include/asm/topology.h | 38 --- include/linux/topology.h | 37 --- kernel/sched/core.c | 280 +++++++++++++++++++---------- 9 files changed, 185 insertions(+), 318 deletions(-) --- a/arch/ia64/include/asm/topology.h +++ b/arch/ia64/include/asm/topology.h @@ -70,31 +70,6 @@ void build_cpu_to_node_map(void); .nr_balance_failed = 0, \ } -/* sched_domains SD_NODE_INIT for IA64 NUMA machines */ -#define SD_NODE_INIT (struct sched_domain) { \ - .parent = NULL, \ - .child = NULL, \ - .groups = NULL, \ - .min_interval = 8, \ - .max_interval = 8*(min(num_online_cpus(), 32U)), \ - .busy_factor = 64, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 2, \ - .busy_idx = 3, \ - .idle_idx = 2, \ - .newidle_idx = 0, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - .flags = SD_LOAD_BALANCE \ - | SD_BALANCE_NEWIDLE \ - | SD_BALANCE_EXEC \ - | SD_BALANCE_FORK \ - | SD_SERIALIZE, \ - .last_balance = jiffies, \ - .balance_interval = 64, \ - .nr_balance_failed = 0, \ -} - #endif /* CONFIG_NUMA */ #ifdef CONFIG_SMP --- a/arch/mips/include/asm/mach-ip27/topology.h +++ b/arch/mips/include/asm/mach-ip27/topology.h @@ -36,23 +36,6 @@ extern unsigned char __node_distances[MA #define node_distance(from, to) (__node_distances[(from)][(to)]) -/* sched_domains SD_NODE_INIT for SGI IP27 machines */ -#define SD_NODE_INIT (struct sched_domain) { \ - .parent = NULL, \ - .child = NULL, \ - .groups = NULL, \ - .min_interval = 8, \ - .max_interval = 32, \ - .busy_factor = 32, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 1, \ - .flags = SD_LOAD_BALANCE | \ - SD_BALANCE_EXEC, \ - .last_balance = jiffies, \ - .balance_interval = 1, \ - .nr_balance_failed = 0, \ -} - #include #endif /* _ASM_MACH_TOPOLOGY_H */ --- a/arch/powerpc/include/asm/topology.h +++ b/arch/powerpc/include/asm/topology.h @@ -18,12 +18,6 @@ struct device_node; */ #define RECLAIM_DISTANCE 10 -/* - * Avoid creating an extra level of balancing (SD_ALLNODES) on the largest - * POWER7 boxes which have a maximum of 32 nodes. - */ -#define SD_NODES_PER_DOMAIN 32 - #include static inline int cpu_to_node(int cpu) @@ -51,36 +45,6 @@ static inline int pcibus_to_node(struct cpu_all_mask : \ cpumask_of_node(pcibus_to_node(bus))) -/* sched_domains SD_NODE_INIT for PPC64 machines */ -#define SD_NODE_INIT (struct sched_domain) { \ - .min_interval = 8, \ - .max_interval = 32, \ - .busy_factor = 32, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 1, \ - .busy_idx = 3, \ - .idle_idx = 1, \ - .newidle_idx = 0, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - \ - .flags = 1*SD_LOAD_BALANCE \ - | 0*SD_BALANCE_NEWIDLE \ - | 1*SD_BALANCE_EXEC \ - | 1*SD_BALANCE_FORK \ - | 0*SD_BALANCE_WAKE \ - | 1*SD_WAKE_AFFINE \ - | 0*SD_PREFER_LOCAL \ - | 0*SD_SHARE_CPUPOWER \ - | 0*SD_POWERSAVINGS_BALANCE \ - | 0*SD_SHARE_PKG_RESOURCES \ - | 1*SD_SERIALIZE \ - | 0*SD_PREFER_SIBLING \ - , \ - .last_balance = jiffies, \ - .balance_interval = 1, \ -} - extern int __node_distance(int, int); #define node_distance(a, b) __node_distance(a, b) --- a/arch/sh/include/asm/topology.h +++ b/arch/sh/include/asm/topology.h @@ -3,31 +3,6 @@ #ifdef CONFIG_NUMA -/* sched_domains SD_NODE_INIT for sh machines */ -#define SD_NODE_INIT (struct sched_domain) { \ - .parent = NULL, \ - .child = NULL, \ - .groups = NULL, \ - .min_interval = 8, \ - .max_interval = 32, \ - .busy_factor = 32, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 2, \ - .busy_idx = 3, \ - .idle_idx = 2, \ - .newidle_idx = 0, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - .flags = SD_LOAD_BALANCE \ - | SD_BALANCE_FORK \ - | SD_BALANCE_EXEC \ - | SD_BALANCE_NEWIDLE \ - | SD_SERIALIZE, \ - .last_balance = jiffies, \ - .balance_interval = 1, \ - .nr_balance_failed = 0, \ -} - #define cpu_to_node(cpu) ((void)(cpu),0) #define parent_node(node) ((void)(node),0) --- a/arch/sparc/include/asm/topology_64.h +++ b/arch/sparc/include/asm/topology_64.h @@ -31,25 +31,6 @@ static inline int pcibus_to_node(struct cpu_all_mask : \ cpumask_of_node(pcibus_to_node(bus))) -#define SD_NODE_INIT (struct sched_domain) { \ - .min_interval = 8, \ - .max_interval = 32, \ - .busy_factor = 32, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 2, \ - .busy_idx = 3, \ - .idle_idx = 2, \ - .newidle_idx = 0, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - .flags = SD_LOAD_BALANCE \ - | SD_BALANCE_FORK \ - | SD_BALANCE_EXEC \ - | SD_SERIALIZE, \ - .last_balance = jiffies, \ - .balance_interval = 1, \ -} - #else /* CONFIG_NUMA */ #include --- a/arch/tile/include/asm/topology.h +++ b/arch/tile/include/asm/topology.h @@ -78,32 +78,6 @@ static inline const struct cpumask *cpum .balance_interval = 32, \ } -/* sched_domains SD_NODE_INIT for TILE architecture */ -#define SD_NODE_INIT (struct sched_domain) { \ - .min_interval = 16, \ - .max_interval = 512, \ - .busy_factor = 32, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 1, \ - .busy_idx = 3, \ - .idle_idx = 1, \ - .newidle_idx = 2, \ - .wake_idx = 1, \ - .flags = 1*SD_LOAD_BALANCE \ - | 1*SD_BALANCE_NEWIDLE \ - | 1*SD_BALANCE_EXEC \ - | 1*SD_BALANCE_FORK \ - | 0*SD_BALANCE_WAKE \ - | 0*SD_WAKE_AFFINE \ - | 0*SD_PREFER_LOCAL \ - | 0*SD_SHARE_CPUPOWER \ - | 0*SD_SHARE_PKG_RESOURCES \ - | 1*SD_SERIALIZE \ - , \ - .last_balance = jiffies, \ - .balance_interval = 128, \ -} - /* By definition, we create nodes based on online memory. */ #define node_has_online_mem(nid) 1 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -92,44 +92,6 @@ extern void setup_node_to_cpumask_map(vo #define pcibus_to_node(bus) __pcibus_to_node(bus) -#ifdef CONFIG_X86_32 -# define SD_CACHE_NICE_TRIES 1 -# define SD_IDLE_IDX 1 -#else -# define SD_CACHE_NICE_TRIES 2 -# define SD_IDLE_IDX 2 -#endif - -/* sched_domains SD_NODE_INIT for NUMA machines */ -#define SD_NODE_INIT (struct sched_domain) { \ - .min_interval = 8, \ - .max_interval = 32, \ - .busy_factor = 32, \ - .imbalance_pct = 125, \ - .cache_nice_tries = SD_CACHE_NICE_TRIES, \ - .busy_idx = 3, \ - .idle_idx = SD_IDLE_IDX, \ - .newidle_idx = 0, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - \ - .flags = 1*SD_LOAD_BALANCE \ - | 1*SD_BALANCE_NEWIDLE \ - | 1*SD_BALANCE_EXEC \ - | 1*SD_BALANCE_FORK \ - | 0*SD_BALANCE_WAKE \ - | 1*SD_WAKE_AFFINE \ - | 0*SD_PREFER_LOCAL \ - | 0*SD_SHARE_CPUPOWER \ - | 0*SD_POWERSAVINGS_BALANCE \ - | 0*SD_SHARE_PKG_RESOURCES \ - | 1*SD_SERIALIZE \ - | 0*SD_PREFER_SIBLING \ - , \ - .last_balance = jiffies, \ - .balance_interval = 1, \ -} - extern int __node_distance(int, int); #define node_distance(a, b) __node_distance(a, b) --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -70,7 +70,6 @@ int arch_update_cpu_topology(void); * Below are the 3 major initializers used in building sched_domains: * SD_SIBLING_INIT, for SMT domains * SD_CPU_INIT, for SMP domains - * SD_NODE_INIT, for NUMA domains * * Any architecture that cares to do any tuning to these values should do so * by defining their own arch-specific initializer in include/asm/topology.h. @@ -176,48 +175,12 @@ int arch_update_cpu_topology(void); } #endif -/* sched_domains SD_ALLNODES_INIT for NUMA machines */ -#define SD_ALLNODES_INIT (struct sched_domain) { \ - .min_interval = 64, \ - .max_interval = 64*num_online_cpus(), \ - .busy_factor = 128, \ - .imbalance_pct = 133, \ - .cache_nice_tries = 1, \ - .busy_idx = 3, \ - .idle_idx = 3, \ - .flags = 1*SD_LOAD_BALANCE \ - | 1*SD_BALANCE_NEWIDLE \ - | 0*SD_BALANCE_EXEC \ - | 0*SD_BALANCE_FORK \ - | 0*SD_BALANCE_WAKE \ - | 0*SD_WAKE_AFFINE \ - | 0*SD_SHARE_CPUPOWER \ - | 0*SD_POWERSAVINGS_BALANCE \ - | 0*SD_SHARE_PKG_RESOURCES \ - | 1*SD_SERIALIZE \ - | 0*SD_PREFER_SIBLING \ - , \ - .last_balance = jiffies, \ - .balance_interval = 64, \ -} - -#ifndef SD_NODES_PER_DOMAIN -#define SD_NODES_PER_DOMAIN 16 -#endif - #ifdef CONFIG_SCHED_BOOK #ifndef SD_BOOK_INIT #error Please define an appropriate SD_BOOK_INIT in include/asm/topology.h!!! #endif #endif /* CONFIG_SCHED_BOOK */ -#ifdef CONFIG_NUMA -#ifndef SD_NODE_INIT -#error Please define an appropriate SD_NODE_INIT in include/asm/topology.h!!! -#endif - -#endif /* CONFIG_NUMA */ - #ifdef CONFIG_USE_PERCPU_NUMA_NODE_ID DECLARE_PER_CPU(int, numa_node); --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5560,7 +5560,8 @@ static int sched_domain_debug_one(struct break; } - if (cpumask_intersects(groupmask, sched_group_cpus(group))) { + if (!(sd->flags & SD_OVERLAP) && + cpumask_intersects(groupmask, sched_group_cpus(group))) { printk(KERN_CONT "\n"); printk(KERN_ERR "ERROR: repeated CPUs\n"); break; @@ -5898,92 +5899,6 @@ static int __init isolated_cpu_setup(cha __setup("isolcpus=", isolated_cpu_setup); -#ifdef CONFIG_NUMA - -/** - * find_next_best_node - find the next node to include in a sched_domain - * @node: node whose sched_domain we're building - * @used_nodes: nodes already in the sched_domain - * - * Find the next node to include in a given scheduling domain. Simply - * finds the closest node not already in the @used_nodes map. - * - * Should use nodemask_t. - */ -static int find_next_best_node(int node, nodemask_t *used_nodes) -{ - int i, n, val, min_val, best_node = -1; - - min_val = INT_MAX; - - for (i = 0; i < nr_node_ids; i++) { - /* Start at @node */ - n = (node + i) % nr_node_ids; - - if (!nr_cpus_node(n)) - continue; - - /* Skip already used nodes */ - if (node_isset(n, *used_nodes)) - continue; - - /* Simple min distance search */ - val = node_distance(node, n); - - if (val < min_val) { - min_val = val; - best_node = n; - } - } - - if (best_node != -1) - node_set(best_node, *used_nodes); - return best_node; -} - -/** - * sched_domain_node_span - get a cpumask for a node's sched_domain - * @node: node whose cpumask we're constructing - * @span: resulting cpumask - * - * Given a node, construct a good cpumask for its sched_domain to span. It - * should be one that prevents unnecessary balancing, but also spreads tasks - * out optimally. - */ -static void sched_domain_node_span(int node, struct cpumask *span) -{ - nodemask_t used_nodes; - int i; - - cpumask_clear(span); - nodes_clear(used_nodes); - - cpumask_or(span, span, cpumask_of_node(node)); - node_set(node, used_nodes); - - for (i = 1; i < SD_NODES_PER_DOMAIN; i++) { - int next_node = find_next_best_node(node, &used_nodes); - if (next_node < 0) - break; - cpumask_or(span, span, cpumask_of_node(next_node)); - } -} - -static const struct cpumask *cpu_node_mask(int cpu) -{ - lockdep_assert_held(&sched_domains_mutex); - - sched_domain_node_span(cpu_to_node(cpu), sched_domains_tmpmask); - - return sched_domains_tmpmask; -} - -static const struct cpumask *cpu_allnodes_mask(int cpu) -{ - return cpu_possible_mask; -} -#endif /* CONFIG_NUMA */ - static const struct cpumask *cpu_cpu_mask(int cpu) { return cpumask_of_node(cpu_to_node(cpu)); @@ -6020,6 +5935,7 @@ struct sched_domain_topology_level { sched_domain_init_f init; sched_domain_mask_f mask; int flags; + int numa_level; struct sd_data data; }; @@ -6213,10 +6129,6 @@ sd_init_##type(struct sched_domain_topol } SD_INIT_FUNC(CPU) -#ifdef CONFIG_NUMA - SD_INIT_FUNC(ALLNODES) - SD_INIT_FUNC(NODE) -#endif #ifdef CONFIG_SCHED_SMT SD_INIT_FUNC(SIBLING) #endif @@ -6338,15 +6250,191 @@ static struct sched_domain_topology_leve { sd_init_BOOK, cpu_book_mask, }, #endif { sd_init_CPU, cpu_cpu_mask, }, -#ifdef CONFIG_NUMA - { sd_init_NODE, cpu_node_mask, SDTL_OVERLAP, }, - { sd_init_ALLNODES, cpu_allnodes_mask, }, -#endif { NULL, }, }; static struct sched_domain_topology_level *sched_domain_topology = default_topology; +#ifdef CONFIG_NUMA + +static int sched_domains_numa_levels; +static int sched_domains_numa_scale; +static int *sched_domains_numa_distance; +static struct cpumask ***sched_domains_numa_masks; +static int sched_domains_curr_level; + +static inline unsigned long numa_scale(unsigned long x, int level) +{ + return x * sched_domains_numa_distance[level] / sched_domains_numa_scale; +} + +static inline int sd_local_flags(int level) +{ + if (sched_domains_numa_distance[level] > REMOTE_DISTANCE) + return 0; + + return SD_BALANCE_EXEC | SD_BALANCE_FORK | SD_WAKE_AFFINE; +} + +static struct sched_domain * +sd_numa_init(struct sched_domain_topology_level *tl, int cpu) +{ + struct sched_domain *sd = *per_cpu_ptr(tl->data.sd, cpu); + int level = tl->numa_level; + int sd_weight = cpumask_weight( + sched_domains_numa_masks[level][cpu_to_node(cpu)]); + + *sd = (struct sched_domain){ + .min_interval = sd_weight, + .max_interval = 2*sd_weight, + .busy_factor = 32, + .imbalance_pct = 100 + numa_scale(25, level), + .cache_nice_tries = 2, + .busy_idx = 3, + .idle_idx = 2, + .newidle_idx = 0, + .wake_idx = 0, + .forkexec_idx = 0, + + .flags = 1*SD_LOAD_BALANCE + | 1*SD_BALANCE_NEWIDLE + | 0*SD_BALANCE_EXEC + | 0*SD_BALANCE_FORK + | 0*SD_BALANCE_WAKE + | 0*SD_WAKE_AFFINE + | 0*SD_PREFER_LOCAL + | 0*SD_SHARE_CPUPOWER + | 0*SD_POWERSAVINGS_BALANCE + | 0*SD_SHARE_PKG_RESOURCES + | 1*SD_SERIALIZE + | 0*SD_PREFER_SIBLING + | sd_local_flags(level) + , + .last_balance = jiffies, + .balance_interval = sd_weight, + }; + SD_INIT_NAME(sd, NUMA); + sd->private = &tl->data; + + /* + * Ugly hack to pass state to sd_numa_mask()... + */ + sched_domains_curr_level = tl->numa_level; + + return sd; +} + +static const struct cpumask *sd_numa_mask(int cpu) +{ + return sched_domains_numa_masks[sched_domains_curr_level][cpu_to_node(cpu)]; +} + +static void sched_init_numa(void) +{ + int next_distance, curr_distance = node_distance(0, 0); + struct sched_domain_topology_level *tl; + int level = 0; + int i, j, k; + + sched_domains_numa_scale = curr_distance; + sched_domains_numa_distance = kzalloc(sizeof(int) * nr_node_ids, GFP_KERNEL); + if (!sched_domains_numa_distance) + return; + + /* + * O(nr_nodes^2) deduplicating selection sort -- in order to find the + * unique distances in the node_distance() table. + * + * Assumes node_distance(0,j) includes all distances in + * node_distance(i,j) in order to avoid cubic time. + * + * XXX: could be optimized to O(n log n) by using sort() + */ + next_distance = curr_distance; + for (i = 0; i < nr_node_ids; i++) { + for (j = 0; j < nr_node_ids; j++) { + int distance = node_distance(0, j); + if (distance > curr_distance && + (distance < next_distance || + next_distance == curr_distance)) + next_distance = distance; + } + if (next_distance != curr_distance) { + sched_domains_numa_distance[level++] = next_distance; + sched_domains_numa_levels = level; + curr_distance = next_distance; + } else break; + } + /* + * 'level' contains the number of unique distances, excluding the + * identity distance node_distance(i,i). + * + * The sched_domains_nume_distance[] array includes the actual distance + * numbers. + */ + + sched_domains_numa_masks = kzalloc(sizeof(void *) * level, GFP_KERNEL); + if (!sched_domains_numa_masks) + return; + + /* + * Now for each level, construct a mask per node which contains all + * cpus of nodes that are that many hops away from us. + */ + for (i = 0; i < level; i++) { + sched_domains_numa_masks[i] = + kzalloc(nr_node_ids * sizeof(void *), GFP_KERNEL); + if (!sched_domains_numa_masks[i]) + return; + + for (j = 0; j < nr_node_ids; j++) { + struct cpumask *mask = kzalloc_node(cpumask_size(), GFP_KERNEL, j); + if (!mask) + return; + + sched_domains_numa_masks[i][j] = mask; + + for (k = 0; k < nr_node_ids; k++) { + if (node_distance(cpu_to_node(j), k) > + sched_domains_numa_distance[i]) + continue; + + cpumask_or(mask, mask, cpumask_of_node(k)); + } + } + } + + tl = kzalloc((ARRAY_SIZE(default_topology) + level) * + sizeof(struct sched_domain_topology_level), GFP_KERNEL); + if (!tl) + return; + + /* + * Copy the default topology bits.. + */ + for (i = 0; default_topology[i].init; i++) + tl[i] = default_topology[i]; + + /* + * .. and append 'j' levels of NUMA goodness. + */ + for (j = 0; j < level; i++, j++) { + tl[i] = (struct sched_domain_topology_level){ + .init = sd_numa_init, + .mask = sd_numa_mask, + .flags = SDTL_OVERLAP, + .numa_level = j, + }; + } + + sched_domain_topology = tl; +} +#else +static inline void sched_init_numa(void) +{ +} +#endif /* CONFIG_NUMA */ + static int __sdt_alloc(const struct cpumask *cpu_map) { struct sched_domain_topology_level *tl; @@ -6840,6 +6928,8 @@ void __init sched_init_smp(void) alloc_cpumask_var(&non_isolated_cpus, GFP_KERNEL); alloc_cpumask_var(&fallback_doms, GFP_KERNEL); + sched_init_numa(); + get_online_cpus(); mutex_lock(&sched_domains_mutex); init_sched_domains(cpu_active_mask); From paul.gortmaker@windriver.com Tue May 1 23:38:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 23:39:02 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:38102 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903736Ab2EAVix (ORCPT ); Tue, 1 May 2012 23:38:53 +0200 Received: from yow-lpgnfs-02.corp.ad.wrs.com (yow-lpgnfs-02.wrs.com [128.224.149.8]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q41LciFk022599; Tue, 1 May 2012 14:38:45 -0700 (PDT) From: Paul Gortmaker To: linux-usb@vger.kernel.org Cc: linux-mips@linux-mips.org, Paul Gortmaker , Ralf Baechle , Alan Stern , Greg Kroah-Hartman Subject: [PATCH] usb: [MIPS] fix unresolved err() reference in host/ohci-pnx8550.c Date: Tue, 1 May 2012 17:38:21 -0400 Message-Id: <1335908301-4869-1-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33112 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1208 Lines: 38 Commit af4e1ee04026908086d7ed252db2619a8ceaa333 (usb-next) "USB: remove err() macro" was preceeded by a tree-wide cleanup of users, however this one squeaked through the cracks because it had whitespace between the function name and the bracket for the args. Map it onto dev_err, just like all the "pre-commits" made in advance of af4e1ee04026, such as the example seen in the commit d57b177208b6ec20cacd7321ee32ef02f9f9e7fa: "USB: ohci-xls.c: remove err() usage" Build tested with the MIPS pnx8550-jbs_defconfig settings. Cc: Ralf Baechle Cc: Alan Stern Cc: Greg Kroah-Hartman Signed-off-by: Paul Gortmaker diff --git a/drivers/usb/host/ohci-pnx8550.c b/drivers/usb/host/ohci-pnx8550.c index f13d08f..148d27d 100644 --- a/drivers/usb/host/ohci-pnx8550.c +++ b/drivers/usb/host/ohci-pnx8550.c @@ -157,7 +157,8 @@ ohci_pnx8550_start (struct usb_hcd *hcd) return ret; if ((ret = ohci_run (ohci)) < 0) { - err ("can't start %s", hcd->self.bus_name); + dev_err(hcd->self.controller, "can't start %s", + hcd->self.bus_name); ohci_stop (hcd); return ret; } -- 1.7.9.1 From paul.gortmaker@windriver.com Tue May 1 23:39:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 May 2012 23:39:36 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:38171 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903736Ab2EAVja (ORCPT ); Tue, 1 May 2012 23:39:30 +0200 Received: from yow-lpgnfs-02.corp.ad.wrs.com (yow-lpgnfs-02.wrs.com [128.224.149.8]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q41LdM9j022655; Tue, 1 May 2012 14:39:23 -0700 (PDT) From: Paul Gortmaker To: linux-usb@vger.kernel.org Cc: linux-mips@linux-mips.org, Paul Gortmaker , Ralf Baechle , Alan Stern , Greg Kroah-Hartman Subject: [PATCH] usb: [MIPS] fix unresolved err() reference in host/ohci-au1xxx.c Date: Tue, 1 May 2012 17:39:11 -0400 Message-Id: <1335908351-4981-1-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33113 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1211 Lines: 38 Commit af4e1ee04026908086d7ed252db2619a8ceaa333 (usb-next) "USB: remove err() macro" was preceeded by a tree-wide cleanup of users, however this one squeaked through the cracks because it had whitespace between the function name and the bracket for the args. Map it onto dev_err, just like all the "pre-commits" made in advance of af4e1ee04026, such as the example seen in the commit d57b177208b6ec20cacd7321ee32ef02f9f9e7fa: "USB: ohci-xls.c: remove err() usage" Build tested with the MIPS gpr_defconfig settings. Cc: Ralf Baechle Cc: Alan Stern Cc: Greg Kroah-Hartman Signed-off-by: Paul Gortmaker diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index 4ea63b2..c611699 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -37,7 +37,8 @@ static int __devinit ohci_au1xxx_start(struct usb_hcd *hcd) return ret; if ((ret = ohci_run(ohci)) < 0) { - err ("can't start %s", hcd->self.bus_name); + dev_err(hcd->self.controller, "can't start %s", + hcd->self.bus_name); ohci_stop(hcd); return ret; } -- 1.7.9.1 From computersforpeace@gmail.com Wed May 2 02:13:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 02:13:31 +0200 (CEST) Received: from mail-yw0-f49.google.com ([209.85.213.49]:37020 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903743Ab2EBAN1 (ORCPT ); Wed, 2 May 2012 02:13:27 +0200 Received: by yhjj52 with SMTP id j52so95569yhj.36 for ; Tue, 01 May 2012 17:13:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=7Zgy/hyntyleTElgl/xN4ksc7HoghkJlbMNAJdNEXYY=; b=CCGpRywAN91yEXAlFTRX3ef22MOp01HQxH71LMSzVNzGm8tQ5tjS9aV1OJPikGPWb5 yCKHxSL7DD+VA1aUXXgzkg3iz9EslpfvHYMEv5/d4v6+O+d/a7AhLTEEyWj3cT5w6bQj afT8JMJeMEC4Zw5/2j1YLwMKNu7TaT05n2JcXMUUgruAxeYMoHrpLEXCMiAtdr6jABFj j9ErNwBoyXHl020IX6C+4Wk1v2j1x3OfJhVWcrvmeLgULMQFR34fwyxpLU4Eocpkw+/5 89tftp1wZgT0tkH+cG77e1+j5f1X4tWib069Qsna+U5xwZNVO2mYbw8uLQj9IHRYNg6V 7AYg== Received: by 10.68.194.1 with SMTP id hs1mr4469583pbc.6.1335917600674; Tue, 01 May 2012 17:13:20 -0700 (PDT) Received: from localhost.localdomain (5520-maca-inet1-outside.broadcom.com. [216.31.211.11]) by mx.google.com with ESMTPS id h10sm246271pbh.69.2012.05.01.17.13.19 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 01 May 2012 17:13:20 -0700 (PDT) From: Brian Norris To: Cc: Artem Bityutskiy , David Woodhouse , Scott Wood , Shmulik Ladkani , Brian Norris , linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org Subject: [PATCH 3/3] mtd: nand: kill NAND_NO_AUTOINCR option Date: Tue, 1 May 2012 17:12:55 -0700 Message-Id: <1335917575-14953-3-git-send-email-computersforpeace@gmail.com> X-Mailer: git-send-email 1.7.5.4.2.g519b1 In-Reply-To: <1335917575-14953-1-git-send-email-computersforpeace@gmail.com> References: <1335917575-14953-1-git-send-email-computersforpeace@gmail.com> X-archive-position: 33114 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: computersforpeace@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Status: A Content-Length: 13283 Lines: 336 No drivers use auto-increment NAND, so kill the NO_AUTOINCR option entirely. Signed-off-by: Brian Norris --- Documentation/DocBook/mtdnand.tmpl | 2 -- arch/arm/mach-ep93xx/snappercl15.c | 1 - arch/arm/mach-ixp4xx/ixdp425-setup.c | 1 - arch/arm/mach-nomadik/board-nhk8815.c | 2 +- arch/mips/rb532/devices.c | 1 - drivers/mtd/nand/au1550nd.c | 2 -- drivers/mtd/nand/cafe_nand.c | 2 +- drivers/mtd/nand/cs553x_nand.c | 1 - drivers/mtd/nand/docg4.c | 3 +-- drivers/mtd/nand/fsl_elbc_nand.c | 2 +- drivers/mtd/nand/fsl_ifc_nand.c | 2 +- drivers/mtd/nand/h1910.c | 1 - drivers/mtd/nand/mpc5121_nfc.c | 1 - drivers/mtd/nand/nand_base.c | 8 +------- drivers/mtd/nand/nand_ids.c | 6 ++---- drivers/mtd/nand/pasemi_nand.c | 1 - drivers/mtd/nand/pxa3xx_nand.c | 1 - drivers/mtd/nand/sh_flctl.c | 2 -- drivers/mtd/nand/sm_common.c | 9 ++++----- include/linux/mtd/nand.h | 5 +---- 20 files changed, 13 insertions(+), 40 deletions(-) diff --git a/Documentation/DocBook/mtdnand.tmpl b/Documentation/DocBook/mtdnand.tmpl index 0c674be..e0aedb7 100644 --- a/Documentation/DocBook/mtdnand.tmpl +++ b/Documentation/DocBook/mtdnand.tmpl @@ -1119,8 +1119,6 @@ in this page These constants are defined in nand.h. They are ored together to describe the chip functionality. -/* Chip can not auto increment pages */ -#define NAND_NO_AUTOINCR 0x00000001 /* Buswitdh is 16 bit */ #define NAND_BUSWIDTH_16 0x00000002 /* Device supports partial programming without padding */ diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c index 5df9092..376b8f5 100644 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ b/arch/arm/mach-ep93xx/snappercl15.c @@ -100,7 +100,6 @@ static struct platform_nand_data snappercl15_nand_data = { .nr_chips = 1, .partitions = snappercl15_nand_parts, .nr_partitions = ARRAY_SIZE(snappercl15_nand_parts), - .options = NAND_NO_AUTOINCR, .chip_delay = 25, }, .ctrl = { diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index fccfc73..108a9d3 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -98,7 +98,6 @@ static struct platform_nand_data ixdp425_flash_nand_data = { .chip = { .nr_chips = 1, .chip_delay = 30, - .options = NAND_NO_AUTOINCR, .partitions = ixdp425_partitions, .nr_partitions = ARRAY_SIZE(ixdp425_partitions), }, diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c index 58cacaf..2e8d3e1 100644 --- a/arch/arm/mach-nomadik/board-nhk8815.c +++ b/arch/arm/mach-nomadik/board-nhk8815.c @@ -111,7 +111,7 @@ static struct nomadik_nand_platform_data nhk8815_nand_data = { .parts = nhk8815_partitions, .nparts = ARRAY_SIZE(nhk8815_partitions), .options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \ - | NAND_NO_READRDY | NAND_NO_AUTOINCR, + | NAND_NO_READRDY, .init = nhk8815_nand_init, }; diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index a969eb8..08c4f8e 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -292,7 +292,6 @@ static void __init rb532_nand_setup(void) rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info); rb532_nand_data.chip.partitions = rb532_partition_info; rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY; - rb532_nand_data.chip.options = NAND_NO_AUTOINCR; } diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 73abbc3..9f609d2 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -508,8 +508,6 @@ static int __devinit au1550nd_probe(struct platform_device *pdev) this->chip_delay = 30; this->ecc.mode = NAND_ECC_SOFT; - this->options = NAND_NO_AUTOINCR; - if (pd->devwidth) this->options |= NAND_BUSWIDTH_16; diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c index 886ff3a..75fb77b 100644 --- a/drivers/mtd/nand/cafe_nand.c +++ b/drivers/mtd/nand/cafe_nand.c @@ -687,7 +687,7 @@ static int __devinit cafe_nand_probe(struct pci_dev *pdev, /* Enable the following for a flash based bad block table */ cafe->nand.bbt_options = NAND_BBT_USE_FLASH; - cafe->nand.options = NAND_NO_AUTOINCR | NAND_OWN_BUFFERS; + cafe->nand.options = NAND_OWN_BUFFERS; if (skipbbt) { cafe->nand.options |= NAND_SKIP_BBTSCAN; diff --git a/drivers/mtd/nand/cs553x_nand.c b/drivers/mtd/nand/cs553x_nand.c index 821c34c..adb6c3e 100644 --- a/drivers/mtd/nand/cs553x_nand.c +++ b/drivers/mtd/nand/cs553x_nand.c @@ -240,7 +240,6 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr) /* Enable the following for a flash based bad block table */ this->bbt_options = NAND_BBT_USE_FLASH; - this->options = NAND_NO_AUTOINCR; /* Scan to find existence of the device */ if (nand_scan(new_mtd, 1)) { diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c index 8e7da01..1540de2 100644 --- a/drivers/mtd/nand/docg4.c +++ b/drivers/mtd/nand/docg4.c @@ -1193,8 +1193,7 @@ static void __init init_mtd_structs(struct mtd_info *mtd) nand->ecc.prepad = 8; nand->ecc.bytes = 8; nand->ecc.strength = DOCG4_T; - nand->options = - NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE | NAND_NO_AUTOINCR; + nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE; nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA; nand->controller = &nand->hwcontrol; spin_lock_init(&nand->controller->lock); diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 8638b5e..4d99587 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -807,7 +807,7 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) chip->bbt_md = &bbt_mirror_descr; /* set up nand options */ - chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR; + chip->options = NAND_NO_READRDY; chip->bbt_options = NAND_BBT_USE_FLASH; chip->controller = &elbc_fcm_ctrl->controller; diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 0adde96..dffd2fa 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -806,7 +806,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) out_be32(&ifc->ifc_nand.ncfgr, 0x0); /* set up nand options */ - chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR; + chip->options = NAND_NO_READRDY; chip->bbt_options = NAND_BBT_USE_FLASH; diff --git a/drivers/mtd/nand/h1910.c b/drivers/mtd/nand/h1910.c index 11e4878..85e55a5 100644 --- a/drivers/mtd/nand/h1910.c +++ b/drivers/mtd/nand/h1910.c @@ -124,7 +124,6 @@ static int __init h1910_init(void) /* 15 us command delay time */ this->chip_delay = 50; this->ecc.mode = NAND_ECC_SOFT; - this->options = NAND_NO_AUTOINCR; /* Scan to find existence of the device */ if (nand_scan(h1910_nand_mtd, 1)) { diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index c240cf1..c259c24 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -734,7 +734,6 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op) chip->write_buf = mpc5121_nfc_write_buf; chip->verify_buf = mpc5121_nfc_verify_buf; chip->select_chip = mpc5121_nfc_select_chip; - chip->options = NAND_NO_AUTOINCR; chip->bbt_options = NAND_BBT_USE_FLASH; chip->ecc.mode = NAND_ECC_SOFT; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 6246b0f..5ec4d2c 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2895,8 +2895,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, *busw = NAND_BUSWIDTH_16; chip->options &= ~NAND_CHIPOPTIONS_MSK; - chip->options |= (NAND_NO_READRDY | - NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK; + chip->options |= NAND_NO_READRDY & NAND_CHIPOPTIONS_MSK; pr_info("ONFI flash detected\n"); return 1; @@ -3073,11 +3072,6 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; ident_done: - /* - * Set chip as a default. Board drivers can override it, if necessary. - */ - chip->options |= NAND_NO_AUTOINCR; - /* Try to identify manufacturer */ for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { if (nand_manuf_ids[maf_idx].id == *maf_id) diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index af4fe8c..621b70b 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -70,7 +70,7 @@ struct nand_flash_dev nand_flash_ids[] = { * These are the new chips with large page size. The pagesize and the * erasesize is determined from the extended id bytes */ -#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR) +#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY) #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) /* 512 Megabit */ @@ -157,9 +157,7 @@ struct nand_flash_dev nand_flash_ids[] = { * writes possible, but not implemented now */ {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, - NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY | - BBT_AUTO_REFRESH - }, + NAND_IS_AND | NAND_NO_READRDY | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH}, {NULL,} }; diff --git a/drivers/mtd/nand/pasemi_nand.c b/drivers/mtd/nand/pasemi_nand.c index 974dbf8..1440e51 100644 --- a/drivers/mtd/nand/pasemi_nand.c +++ b/drivers/mtd/nand/pasemi_nand.c @@ -155,7 +155,6 @@ static int __devinit pasemi_nand_probe(struct platform_device *ofdev) chip->ecc.mode = NAND_ECC_SOFT; /* Enable the following for a flash based bad block table */ - chip->options = NAND_NO_AUTOINCR; chip->bbt_options = NAND_BBT_USE_FLASH; /* Scan to find existence of the device */ diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index def50ca..36a32a0 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -1004,7 +1004,6 @@ KEEP_CONFIG: chip->ecc.size = host->page_size; chip->ecc.strength = 1; - chip->options = NAND_NO_AUTOINCR; chip->options |= NAND_NO_READRDY; if (host->reg_ndcr & NDCR_DWIDTH_M) chip->options |= NAND_BUSWIDTH_16; diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 4ea3e20..3f0788f 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -881,8 +881,6 @@ static int __devinit flctl_probe(struct platform_device *pdev) flctl->hwecc = pdata->has_hwecc; flctl->holden = pdata->use_holden; - nand->options = NAND_NO_AUTOINCR; - /* Set address of hardware control function */ /* 20 us command delay time */ nand->chip_delay = 20; diff --git a/drivers/mtd/nand/sm_common.c b/drivers/mtd/nand/sm_common.c index 774c3c2..082bcdc 100644 --- a/drivers/mtd/nand/sm_common.c +++ b/drivers/mtd/nand/sm_common.c @@ -94,17 +94,16 @@ static struct nand_flash_dev nand_smartmedia_flash_ids[] = { {NULL,} }; -#define XD_TYPEM (NAND_NO_AUTOINCR | NAND_BROKEN_XD) static struct nand_flash_dev nand_xd_flash_ids[] = { {"xD 16MiB 3,3V", 0x73, 512, 16, 0x4000, 0}, {"xD 32MiB 3,3V", 0x75, 512, 32, 0x4000, 0}, {"xD 64MiB 3,3V", 0x76, 512, 64, 0x4000, 0}, {"xD 128MiB 3,3V", 0x79, 512, 128, 0x4000, 0}, - {"xD 256MiB 3,3V", 0x71, 512, 256, 0x4000, XD_TYPEM}, - {"xD 512MiB 3,3V", 0xdc, 512, 512, 0x4000, XD_TYPEM}, - {"xD 1GiB 3,3V", 0xd3, 512, 1024, 0x4000, XD_TYPEM}, - {"xD 2GiB 3,3V", 0xd5, 512, 2048, 0x4000, XD_TYPEM}, + {"xD 256MiB 3,3V", 0x71, 512, 256, 0x4000, NAND_BROKEN_XD}, + {"xD 512MiB 3,3V", 0xdc, 512, 512, 0x4000, NAND_BROKEN_XD}, + {"xD 1GiB 3,3V", 0xd3, 512, 1024, 0x4000, NAND_BROKEN_XD}, + {"xD 2GiB 3,3V", 0xd5, 512, 2048, 0x4000, NAND_BROKEN_XD}, {NULL,} }; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 2829e8b..2abe758 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -161,8 +161,6 @@ typedef enum { * Option constants for bizarre disfunctionality and real * features. */ -/* Chip can not auto increment pages */ -#define NAND_NO_AUTOINCR 0x00000001 /* Buswidth is 16 bit */ #define NAND_BUSWIDTH_16 0x00000002 /* Device supports partial programming without padding */ @@ -207,7 +205,6 @@ typedef enum { (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) /* Macros to identify the above */ -#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) @@ -216,7 +213,7 @@ typedef enum { && (chip->page_shift > 9)) /* Mask to zero out the chip options, which come from the id table */ -#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) +#define NAND_CHIPOPTIONS_MSK 0x0000ffff /* Non chip related options */ /* This option skips the bbt scan during initialization. */ -- 1.7.5.4.2.g519b1 From blogic@openwrt.org Wed May 2 14:29:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 14:29:31 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48064 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903754Ab2EBM3Y (ORCPT ); Wed, 2 May 2012 14:29:24 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , John Crispin Subject: [PATCH V2 04/14] MIPS: Add helper function to allow platforms to point at a DTB. Date: Wed, 2 May 2012 14:27:34 +0200 Message-Id: <1335961659-21358-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1335961659-21358-1-git-send-email-blogic@openwrt.org> References: <1335961659-21358-1-git-send-email-blogic@openwrt.org> X-archive-position: 33115 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1645 Lines: 59 Add __dt_setup_arch() that can be called to load a builtin DT. Additionally we add a macro to allow loading a specific symbol from the __dtb_* section. Signed-off-by: Ralf Baechle Signed-off-by: John Crispin --- Changes in V2 * remove unused size variable arch/mips/include/asm/prom.h | 11 +++++++++++ arch/mips/kernel/prom.c | 11 +++++++++++ 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h index 40ed259..7206d44 100644 --- a/arch/mips/include/asm/prom.h +++ b/arch/mips/include/asm/prom.h @@ -36,6 +36,17 @@ static inline unsigned long pci_address_to_pio(phys_addr_t address) } #define pci_address_to_pio pci_address_to_pio +struct boot_param_header; + +extern void __dt_setup_arch(struct boot_param_header *bph); + +#define dt_setup_arch(sym) \ +({ \ + extern struct boot_param_header __dtb_##sym##_begin; \ + \ + __dt_setup_arch(&__dtb_##sym##_begin); \ +}) + #else /* CONFIG_OF */ static inline void device_tree_init(void) { } #endif /* CONFIG_OF */ diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 558b539..4c788d2 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -95,3 +95,14 @@ void __init device_tree_init(void) /* free the space reserved for the dt blob */ free_mem_mach(base, size); } + +void __init __dt_setup_arch(struct boot_param_header *bph) +{ + if (be32_to_cpu(bph->magic) != OF_DT_HEADER) { + pr_err("DTB has bad magic, ignoring builtin OF DTB\n"); + + return; + } + + initial_boot_params = bph; +} -- 1.7.9.1 From blogic@openwrt.org Wed May 2 14:29:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 14:29:59 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48060 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903746Ab2EBM3Y (ORCPT ); Wed, 2 May 2012 14:29:24 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , Felix Fietkau , John Crispin Subject: [PATCH V2 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set Date: Wed, 2 May 2012 14:27:32 +0200 Message-Id: <1335961659-21358-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33116 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1377 Lines: 54 From: Felix Fietkau Make the oprofile code use the performance counters irq. Signed-off-by: Felix Fietkau Signed-off-by: John Crispin --- Changes in V2 * set Author to Felix arch/mips/oprofile/op_model_mipsxx.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..86cf234 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -298,6 +298,11 @@ static void reset_counters(void *arg) } } +static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id) +{ + return mipsxx_perfcount_handler(); +} + static int __init mipsxx_init(void) { int counters; @@ -374,6 +379,10 @@ static int __init mipsxx_init(void) save_perf_irq = perf_irq; perf_irq = mipsxx_perfcount_handler; + if (cp0_perfcount_irq >= 0) + return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int, + IRQF_SHARED, "Perfcounter", save_perf_irq); + return 0; } @@ -381,6 +390,9 @@ static void mipsxx_exit(void) { int counters = op_model_mipsxx_ops.num_counters; + if (cp0_perfcount_irq >= 0) + free_irq(cp0_perfcount_irq, save_perf_irq); + counters = counters_per_cpu_to_total(counters); on_each_cpu(reset_counters, (void *)(long)counters, 1); -- 1.7.9.1 From blogic@openwrt.org Wed May 2 14:29:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 14:30:23 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48062 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903753Ab2EBM3Y (ORCPT ); Wed, 2 May 2012 14:29:24 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , John Crispin Subject: [PATCH V2 02/14] MIPS: pci: parse memory ranges from devicetree Date: Wed, 2 May 2012 14:27:33 +0200 Message-Id: <1335961659-21358-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1335961659-21358-1-git-send-email-blogic@openwrt.org> References: <1335961659-21358-1-git-send-email-blogic@openwrt.org> X-archive-position: 33117 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3288 Lines: 123 Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit bus width is supported. This function is based on the implementation found on powerpc. Signed-off-by: John Crispin --- Changes in V2 * remove some #ifdefs * rename to pci_load_of_ranges arch/mips/include/asm/pci.h | 6 ++++ arch/mips/pci/pci.c | 55 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index fcd4060..90bf3b3 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -17,6 +17,7 @@ */ #include +#include /* * Each pci channel is a top-level PCI bus seem by CPU. A machine with @@ -26,6 +27,7 @@ struct pci_controller { struct pci_controller *next; struct pci_bus *bus; + struct device_node *of_node; struct pci_ops *pci_ops; struct resource *mem_resource; @@ -142,4 +144,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) extern char * (*pcibios_plat_setup)(char *str); +/* this function parses memory ranges from a device node */ +extern void __devinit pci_load_of_ranges(struct pci_controller *hose, + struct device_node *node); + #endif /* _ASM_PCI_H */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 0514866..4d8a1b6 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -16,6 +16,7 @@ #include #include #include +#include #include @@ -114,9 +115,63 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) pci_bus_assign_resources(bus); pci_enable_bridges(bus); } + bus->dev.of_node = hose->of_node; } } +#ifdef CONFIG_OF +void __devinit pci_load_of_ranges(struct pci_controller *hose, + struct device_node *node) +{ + const __be32 *ranges; + int rlen; + int pna = of_n_addr_cells(node); + int np = pna + 5; + + pr_info("PCI host bridge %s ranges:\n", node->full_name); + ranges = of_get_property(node, "ranges", &rlen); + if (ranges == NULL) + return; + hose->of_node = node; + + while ((rlen -= np * 4) >= 0) { + u32 pci_space; + struct resource *res = 0; + unsigned long long addr, size; + + pci_space = ranges[0]; + addr = of_translate_address(node, ranges + 3); + size = of_read_number(ranges + pna + 3, 2); + ranges += np; + switch ((pci_space >> 24) & 0x3) { + case 1: /* PCI IO space */ + pr_info(" IO 0x%016llx..0x%016llx\n", + addr, addr + size - 1); + hose->io_map_base = + (unsigned long)ioremap(addr, size); + res = hose->io_resource; + res->flags = IORESOURCE_IO; + break; + case 2: /* PCI Memory space */ + case 3: /* PCI 64 bits Memory space */ + pr_info(" MEM 0x%016llx..0x%016llx\n", + addr, addr + size - 1); + res = hose->mem_resource; + res->flags = IORESOURCE_MEM; + break; + } + if (res != NULL) { + res->start = addr; + res->name = node->full_name; + res->end = res->start + size - 1; + res->parent = NULL; + res->sibling = NULL; + res->child = NULL; + } + } +} +#endif + static DEFINE_MUTEX(pci_scan_mutex); void __devinit register_pci_controller(struct pci_controller *hose) -- 1.7.9.1 From blogic@openwrt.org Wed May 2 14:29:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 14:30:51 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48066 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903755Ab2EBM3Z (ORCPT ); Wed, 2 May 2012 14:29:25 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , John Crispin Subject: [PATCH V2 05/14] MIPS: parse chosen node on boot Date: Wed, 2 May 2012 14:27:35 +0200 Message-Id: <1335961659-21358-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1335961659-21358-1-git-send-email-blogic@openwrt.org> References: <1335961659-21358-1-git-send-email-blogic@openwrt.org> X-archive-position: 33118 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 600 Lines: 26 Call early_init_devtree from inside __dt_setup_arch to allow parsing of the chosen node. Signed-off-by: John Crispin --- Changes in V2 * rebase on previous patch arch/mips/kernel/prom.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 4c788d2..f11b2bb 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -105,4 +105,6 @@ void __init __dt_setup_arch(struct boot_param_header *bph) } initial_boot_params = bph; + + early_init_devtree(initial_boot_params); } -- 1.7.9.1 From blogic@openwrt.org Wed May 2 14:29:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 14:31:16 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48068 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903756Ab2EBM3Z (ORCPT ); Wed, 2 May 2012 14:29:25 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , John Crispin Subject: [PATCH V2 08/14] MIPS: lantiq: clear all irqs properly on boot Date: Wed, 2 May 2012 14:27:36 +0200 Message-Id: <1335961659-21358-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1335961659-21358-1-git-send-email-blogic@openwrt.org> References: <1335961659-21358-1-git-send-email-blogic@openwrt.org> X-archive-position: 33119 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1057 Lines: 37 Due to missing brackets, the irq modules were not properly reset on boot. Signed-off-by: John Crispin --- Changes in V2 * make the commit message accurate arch/mips/lantiq/irq.c | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index d673731..b6b1c72 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -271,12 +271,13 @@ void __init arch_init_irq(void) if (!ltq_eiu_membase) panic("Failed to remap eiu memory"); - /* make sure all irqs are turned off by default */ - for (i = 0; i < 5; i++) + /* turn off all irqs by default */ + for (i = 0; i < 5; i++) { + /* make sure all irqs are turned off by default */ ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); - - /* clear all possibly pending interrupts */ - ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); + /* clear all possibly pending interrupts */ + ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); + } mips_cpu_irq_init(); -- 1.7.9.1 From blogic@openwrt.org Wed May 2 14:29:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 14:31:41 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48070 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903757Ab2EBM3Z (ORCPT ); Wed, 2 May 2012 14:29:25 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , John Crispin Subject: [PATCH V2 09/14] MIPS: lantiq: enable oprofile support on lantiq targets Date: Wed, 2 May 2012 14:27:37 +0200 Message-Id: <1335961659-21358-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1335961659-21358-1-git-send-email-blogic@openwrt.org> References: <1335961659-21358-1-git-send-email-blogic@openwrt.org> X-archive-position: 33120 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 918 Lines: 38 This patch sets the performance counters irq on Lantiq SoCs. Signed-off-by: John Crispin --- Changes in V2 * HAVE_OPROFILE was redundant arch/mips/lantiq/irq.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index b6b1c72..bfd4ad1 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -40,6 +40,9 @@ #define MAX_EIU 6 +/* the performance counter */ +#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) + /* irqs generated by device attached to the EBU need to be acked in * a special manner */ @@ -316,6 +319,9 @@ void __init arch_init_irq(void) set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); #endif + + /* tell oprofile which irq to use */ + cp0_perfcount_irq = LTQ_PERF_IRQ; } unsigned int __cpuinit get_c0_compare_int(void) -- 1.7.9.1 From blogic@openwrt.org Wed May 2 14:29:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 14:32:04 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48072 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903759Ab2EBM30 (ORCPT ); Wed, 2 May 2012 14:29:26 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , Thomas Langer , John Crispin Subject: [PATCH V2 11/14] MIPS: lantiq: fix early printk Date: Wed, 2 May 2012 14:27:38 +0200 Message-Id: <1335961659-21358-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1335961659-21358-1-git-send-email-blogic@openwrt.org> References: <1335961659-21358-1-git-send-email-blogic@openwrt.org> X-archive-position: 33121 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2361 Lines: 74 From: Thomas Langer The code was using a 32bit write operations in the early_printk code. This resulted in 3 zero bytes also being written to the serial port. This patch changes the memory access to 8bit. Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- Changes in V2 * set Author to Thomas .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 6 ++++++ arch/mips/lantiq/early_printk.c | 17 ++++++++--------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 8a3c6be..8bc9030 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -34,6 +34,12 @@ #define LTQ_ASC1_BASE_ADDR 0x1E100C00 #define LTQ_ASC_SIZE 0x400 +/* + * during early_printk no ioremap is possible + * lets use KSEG1 instead + */ +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) + /* RCU - reset control unit */ #define LTQ_RCU_BASE_ADDR 0x1F203000 #define LTQ_RCU_SIZE 0x1000 diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c index 972e05f..9b28d09 100644 --- a/arch/mips/lantiq/early_printk.c +++ b/arch/mips/lantiq/early_printk.c @@ -6,17 +6,16 @@ * Copyright (C) 2010 John Crispin */ -#include #include - -#include #include -/* no ioremap possible at this early stage, lets use KSEG1 instead */ -#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR) #define ASC_BUF 1024 -#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) -#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) +#define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048)) +#ifdef __BIG_ENDIAN +#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3)) +#else +#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020)) +#endif #define TXMASK 0x3F00 #define TXOFFSET 8 @@ -27,7 +26,7 @@ void prom_putchar(char c) local_irq_save(flags); do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); if (c == '\n') - ltq_w32('\r', LTQ_ASC_TBUF); - ltq_w32(c, LTQ_ASC_TBUF); + ltq_w8('\r', LTQ_ASC_TBUF); + ltq_w8(c, LTQ_ASC_TBUF); local_irq_restore(flags); } -- 1.7.9.1 From blogic@openwrt.org Wed May 2 14:29:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 14:32:28 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48075 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903760Ab2EBM30 (ORCPT ); Wed, 2 May 2012 14:29:26 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , Thomas Langer , John Crispin Subject: [PATCH V2 12/14] MIPS: lantiq: fix cmdline parsing Date: Wed, 2 May 2012 14:27:39 +0200 Message-Id: <1335961659-21358-8-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1335961659-21358-1-git-send-email-blogic@openwrt.org> References: <1335961659-21358-1-git-send-email-blogic@openwrt.org> X-archive-position: 33122 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1010 Lines: 36 From: Thomas Langer The code tested if the KSEG1 mapped address of argv was != 0. We need to use CPHYSADDR instead to make the conditional actually work. Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- Changes in V2 * set Author to Thomas arch/mips/lantiq/prom.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 664b7b7..cd56892 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -45,10 +45,12 @@ static void __init prom_init_cmdline(void) char **argv = (char **) KSEG1ADDR(fw_arg1); int i; + arcs_cmdline[0] = '\0'; + for (i = 0; i < argc; i++) { - char *p = (char *) KSEG1ADDR(argv[i]); + char *p = (char *) KSEG1ADDR(argv[i]); - if (p && *p) { + if (CPHYSADDR(p) && *p) { strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); } -- 1.7.9.1 From manuel.lauss@googlemail.com Wed May 2 18:14:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 18:14:42 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:60550 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903756Ab2EBQOj (ORCPT ); Wed, 2 May 2012 18:14:39 +0200 Received: by yenm7 with SMTP id m7so958579yen.36 for ; Wed, 02 May 2012 09:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=mime-version:from:date:message-id:subject:to:content-type; bh=KO3QNDFQH6LWvJzMwkTd5z6PAqp16Aehr4Tjjx6gmIc=; b=Pxp+OkQiJ9oTmZ+08NU0hpkQIKe1Hda9phJNCUb6XtwFREngom60u7VT3Rw0EplSG3 EF9vO2jksDBNw2SOzoGjIEYZNsuPFAErr6ou3hywh2MSJbiYh23t7ACbCJhg55Qf9u/w t5ksUlSVTAMljf1L7dphUugMnGLFJbl6gveV33WuFWyWqo6o1GFx00LvtUkwtzZ2j5pQ PlwnKZvDGSdQceTogVBNRgMGTf20K7Q620skC4gsaLArC5fYrUHGbcOND/VSPZhaN0wz UxdapuGROesqxKgmpliAyTK2cUm/XlWpXAHV+CPm6gpDuTFPbfnfm7wptP/sK8+yOqll DxIw== Received: by 10.236.152.41 with SMTP id c29mr18080761yhk.64.1335975273331; Wed, 02 May 2012 09:14:33 -0700 (PDT) MIME-Version: 1.0 Received: by 10.236.141.171 with HTTP; Wed, 2 May 2012 09:13:53 -0700 (PDT) From: Manuel Lauss Date: Wed, 2 May 2012 18:13:53 +0200 Message-ID: Subject: NFS data corruption on 3.4 To: Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33123 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 591 Lines: 19 Hello, I'm seeing an NFS data corruption problem on 3.4-rcX kernels: I copy the rootfs (~8 GB of data) from the DB1200 board using NFSv3 over to another machine, and a tiny fraction of files (~10 out of >300k) are corrupted on the target; interestingly it's always the same ones. In the case of /usr/bin/dbus-daemon, which is 464144 bytes in size, bytes ranging from offset 36865 (so 32768 + 1x 4k page + 1) to 65535 are garbage, every time. I haven't seen this with my x86/x64 machines, and also not with 3.3 or earlier versions. Does anyone have an idea? Thanks! Manuel Lauss From blogic@openwrt.org Wed May 2 19:34:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 19:34:37 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:43232 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903759Ab2EBRec (ORCPT ); Wed, 2 May 2012 19:34:32 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , Felix Fietkau , John Crispin Subject: [PATCH V3 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set Date: Wed, 2 May 2012 19:33:04 +0200 Message-Id: <1335979984-3973-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33124 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2090 Lines: 73 From: Felix Fietkau Make the oprofile code use the performance counters irq. Signed-off-by: Felix Fietkau Signed-off-by: John Crispin --- Changes in V2 * set Author to Felix Changes in V3 * remove IRQF_SHARED * make sure cp0_compare_irq != cp0_perfcount_irq arch/mips/kernel/perf_event_mipsxx.c | 3 ++- arch/mips/oprofile/op_model_mipsxx.c | 12 ++++++++++++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 811084f..574b4e9 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1532,7 +1532,8 @@ init_hw_perf_events(void) irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; } else { #endif - if (cp0_perfcount_irq >= 0) + if ((cp0_perfcount_irq >= 0) && + (cp0_compare_irq != cp0_perfcount_irq)) irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; else irq = -1; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..baba3bc 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -298,6 +298,11 @@ static void reset_counters(void *arg) } } +static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id) +{ + return mipsxx_perfcount_handler(); +} + static int __init mipsxx_init(void) { int counters; @@ -374,6 +379,10 @@ static int __init mipsxx_init(void) save_perf_irq = perf_irq; perf_irq = mipsxx_perfcount_handler; + if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq)) + return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int, + 0, "Perfcounter", save_perf_irq); + return 0; } @@ -381,6 +390,9 @@ static void mipsxx_exit(void) { int counters = op_model_mipsxx_ops.num_counters; + if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq)) + free_irq(cp0_perfcount_irq, save_perf_irq); + counters = counters_per_cpu_to_total(counters); on_each_cpu(reset_counters, (void *)(long)counters, 1); -- 1.7.9.1 From sshtylyov@mvista.com Wed May 2 20:14:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 May 2012 20:14:18 +0200 (CEST) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:54622 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903759Ab2EBSOK (ORCPT ); Wed, 2 May 2012 20:14:10 +0200 Received: by lagy4 with SMTP id y4so805402lag.36 for ; Wed, 02 May 2012 11:14:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=eJnJs3tqnIa+0D9q2zdjebwo9/Da3FBaSlLUzIUbKlI=; b=cCHCK7sHTyZFmO60x8ZE9jFmuGFRVWFOucAIUylNLPf8HLeKSzCkOyj5jc2TidB8wS AfwnXYG0YbNijCvaf4OImjaGCY2J7caABAMw9b6nG75P3bvQVaiZaqqbLdBAhkFd51ZZ jIQJllywS4tEP2Kov+GrPCRJqhXdQHE+ZLo1H1FuoqEk25TQ/aLVYx3lxviyD50o+wEk Aqr3s8NzYwZbl0plIFHmYY2giC/LZ+q9qNH7FUhEji/ay8735GFPgc4gUGnx+ITRPcRP zedSHjhvMvS8zKYhu2cw5dvraCYVJHduX9ZxcgyJteBHBN8WEY8ct8MqPflcgIX6ktMW Eh2A== Received: by 10.112.47.228 with SMTP id g4mr5921610lbn.92.1335982444094; Wed, 02 May 2012 11:14:04 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id tb4sm2711916lab.14.2012.05.02.11.14.01 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 11:14:02 -0700 (PDT) Message-ID: <4FA17925.6080707@mvista.com> Date: Wed, 02 May 2012 22:12:53 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [PATCH V2 02/14] MIPS: pci: parse memory ranges from devicetree References: <1335961659-21358-1-git-send-email-blogic@openwrt.org> <1335961659-21358-2-git-send-email-blogic@openwrt.org> In-Reply-To: <1335961659-21358-2-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlKegDWshnQrDGn2JiADIonxWGgVdKg1vXmj/MIj2nziRUAtCG07l+knuqI/LOGO1oo75Mt X-archive-position: 33125 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1350 Lines: 49 Hello. On 05/02/2012 04:27 PM, John Crispin wrote: > Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit > bus width is supported. This function is based on the implementation found on > powerpc. > Signed-off-by: John Crispin > --- > Changes in V2 > * remove some #ifdefs > * rename to pci_load_of_ranges > arch/mips/include/asm/pci.h | 6 ++++ > arch/mips/pci/pci.c | 55 +++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 61 insertions(+), 0 deletions(-) [...] > diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c > index 0514866..4d8a1b6 100644 > --- a/arch/mips/pci/pci.c > +++ b/arch/mips/pci/pci.c [...] > @@ -114,9 +115,63 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) [...] > +#ifdef CONFIG_OF > +void __devinit pci_load_of_ranges(struct pci_controller *hose, > + struct device_node *node) > +{ > + const __be32 *ranges; > + int rlen; > + int pna = of_n_addr_cells(node); > + int np = pna + 5; > + > + pr_info("PCI host bridge %s ranges:\n", node->full_name); > + ranges = of_get_property(node, "ranges",&rlen); > + if (ranges == NULL) > + return; > + hose->of_node = node; > + > + while ((rlen -= np * 4)>= 0) { > + u32 pci_space; > + struct resource *res = 0; s/0/NULL/ to avoid the warning (from sparse?). WBR, Sergei From ddaney.cavm@gmail.com Thu May 3 03:16:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 May 2012 03:16:59 +0200 (CEST) Received: from mail-pz0-f53.google.com ([209.85.210.53]:64781 "EHLO mail-pz0-f53.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903780Ab2ECBQy (ORCPT ); Thu, 3 May 2012 03:16:54 +0200 Received: by dadg9 with SMTP id g9so668659dad.26 for ; Wed, 02 May 2012 18:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=MjQkM6tv9H1oEqUIUiFy5gVDNF4AyYyuNIaGYIEFUsY=; b=EHu/7H/DkrMykWO83lXKf7mEHO/Vct9FR1iag/6d3afk1BcxYOtvXF0mhGmoDBCgjh Cv4q0F/tO/9kXar+Ptlkg2i6m/n9bhJR3VfFC5MnZQ85JsyS0gj4+UgvT8bPEOsv6jx0 SJrSyam+SLJm5HoQGHeZvkpRScc0FLMmGkR1Oi3/xIW8GerioRMoFAjqk2m8abRLf5YQ 3Ath77Q15hJ1JKxYzUH9CUWvGoQRvYl2Oi80gscFTYJ8zGW1Q7Z8bX0RCwRRMby/wRgb 1zJdDVUX+6l+JYNm/qo8H8puLZSZg/QkeHleYuE//X67GCn+qXl+zKLAvkrnEuke/ZSu 2Z/g== Received: by 10.68.218.198 with SMTP id pi6mr2170557pbc.121.1336007807500; Wed, 02 May 2012 18:16:47 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id pw10sm897013pbb.30.2012.05.02.18.16.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 18:16:45 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q431GiWP031052; Wed, 2 May 2012 18:16:44 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q431GfPb031049; Wed, 2 May 2012 18:16:41 -0700 From: David Daney To: Ralf Baechle , Grant Likely , Rob Herring , devicetree-discuss@lists.ozlabs.org, "David S. Miller" , netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, afleming@gmail.com, galak@kernel.crashing.org, David Daney Subject: [PATCH v6 0/3] netdev/of/phy: MDIO bus multiplexer support. Date: Wed, 2 May 2012 18:16:36 -0700 Message-Id: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33126 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2427 Lines: 62 From: David Daney This code has been working well for about six months on a couple of different configurations (boards), so I thought it would be a good time to send it out again, and I hope get it on the path towards merging. v6: Correct Kconfig depends in 2/3 as noticed by David Miller. Test against net-next. v5: Correct Kconfig depends in 3/3 as noticed by David Miller. v4: Correct some comment text and rename a couple of variables to better reflect their purpose. v3: Update binding to use "mdio-mux-gpio" compatible property. Cleanups suggested by Grant Likely. Now uses the driver probe deferral mechanism if GPIOs or parent bus not available. v2: Update bindings to use "reg" and "mdio-parent-bus" instead of "cell-index" and "parent-bus" v1: We have several different boards with a multiplexer in the MDIO bus. There is an MDIO bus controller connected to a switching device with several child MDIO busses. Everything is wired up using device tree bindings. 1/3 - New of_mdio_find_bus() function used to help configuring the driver topology. 2/3 - MDIO bus multiplexer framework. 3/3 - A driver for a GPIO controlled multiplexer. David Daney (3): netdev/of/phy: New function: of_mdio_find_bus(). netdev/of/phy: Add MDIO bus multiplexer support. netdev/of/phy: Add MDIO bus multiplexer driven by GPIO lines. .../devicetree/bindings/net/mdio-mux-gpio.txt | 127 +++++++++++++ Documentation/devicetree/bindings/net/mdio-mux.txt | 136 ++++++++++++++ drivers/net/phy/Kconfig | 19 ++ drivers/net/phy/Makefile | 2 + drivers/net/phy/mdio-mux-gpio.c | 142 +++++++++++++++ drivers/net/phy/mdio-mux.c | 192 ++++++++++++++++++++ drivers/net/phy/mdio_bus.c | 32 ++++ drivers/of/of_mdio.c | 2 + include/linux/mdio-mux.h | 21 ++ include/linux/of_mdio.h | 2 + 10 files changed, 675 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/mdio-mux-gpio.txt create mode 100644 Documentation/devicetree/bindings/net/mdio-mux.txt create mode 100644 drivers/net/phy/mdio-mux-gpio.c create mode 100644 drivers/net/phy/mdio-mux.c create mode 100644 include/linux/mdio-mux.h -- 1.7.2.3 From ddaney.cavm@gmail.com Thu May 3 03:16:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 May 2012 03:17:30 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:61693 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903781Ab2ECBQy (ORCPT ); Thu, 3 May 2012 03:16:54 +0200 Received: by pbbrq13 with SMTP id rq13so1938041pbb.36 for ; Wed, 02 May 2012 18:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=f1XsdDH2buwlYx70tDvzncmiNhdpCE9ME1w9owTEiFs=; b=PLwU5v2oteyU5VXRyV3epJsDe+lGWHHvc7h0Pdjj9KdcgtgLmyiaSzU7jlvpVjuYl3 mCckKe1ImxZpn4yRZq1s9NJfYKlVjHrr4ZjEAv6x62nruJGJZP23fnhiNvT7PNteS1oT rNgU4bkrJnPltW4AatUHHUS+jsC6+UTotdqnpMcd7IRYDYM3BXizBd7TQTagjsX5AWvg t6wDPsnu342pw8uV+0imbDZ5V31OKVl9ZIjz8BCWFGN+SSwIWFPruLaehSPO+gOIUtSW dZHFdl6MCS6gKw4bt8h9kogpCaiT5a8VNeSODgecEzpUp4va2fl/EH5teeHZs9q6fhhM N3wQ== Received: by 10.68.219.162 with SMTP id pp2mr2268735pbc.85.1336007807758; Wed, 02 May 2012 18:16:47 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id vn10sm3535461pbc.43.2012.05.02.18.16.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 18:16:46 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q431GidS031056; Wed, 2 May 2012 18:16:44 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q431GiYU031055; Wed, 2 May 2012 18:16:44 -0700 From: David Daney To: Ralf Baechle , Grant Likely , Rob Herring , devicetree-discuss@lists.ozlabs.org, "David S. Miller" , netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, afleming@gmail.com, galak@kernel.crashing.org, David Daney , Grant Likely , "David S. Miller" Subject: [PATCH v6 1/3] netdev/of/phy: New function: of_mdio_find_bus(). Date: Wed, 2 May 2012 18:16:37 -0700 Message-Id: <1336007799-31016-2-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> References: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33127 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2988 Lines: 95 From: David Daney Add of_mdio_find_bus() which allows an mii_bus to be located given its associated the device tree node. This is needed by the follow-on patch to add a driver for MDIO bus multiplexers. The of_mdiobus_register() function is modified so that the device tree node is recorded in the mii_bus. Then we can find it again by iterating over all mdio_bus_class devices. Because the OF device tree has now become an integral part of the kernel, this can live in mdio_bus.c (which contains the needed mdio_bus_class structure) instead of of_mdio.c. Signed-off-by: David Daney Cc: Grant Likely Cc: "David S. Miller" --- drivers/net/phy/mdio_bus.c | 32 ++++++++++++++++++++++++++++++++ drivers/of/of_mdio.c | 2 ++ include/linux/of_mdio.h | 2 ++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index 8985cc6..83d5c9f 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -88,6 +88,38 @@ static struct class mdio_bus_class = { .dev_release = mdiobus_release, }; +#ifdef CONFIG_OF_MDIO +/* Helper function for of_mdio_find_bus */ +static int of_mdio_bus_match(struct device *dev, void *mdio_bus_np) +{ + return dev->of_node == mdio_bus_np; +} +/** + * of_mdio_find_bus - Given an mii_bus node, find the mii_bus. + * @mdio_np: Pointer to the mii_bus. + * + * Returns a pointer to the mii_bus, or NULL if none found. + * + * Because the association of a device_node and mii_bus is made via + * of_mdiobus_register(), the mii_bus cannot be found before it is + * registered with of_mdiobus_register(). + * + */ +struct mii_bus *of_mdio_find_bus(struct device_node *mdio_bus_np) +{ + struct device *d; + + if (!mdio_bus_np) + return NULL; + + d = class_find_device(&mdio_bus_class, NULL, mdio_bus_np, + of_mdio_bus_match); + + return d ? to_mii_bus(d) : NULL; +} +EXPORT_SYMBOL(of_mdio_find_bus); +#endif + /** * mdiobus_register - bring up all the PHYs on a given bus and attach them to bus * @bus: target mii_bus diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c index 483c0ad..2574abd 100644 --- a/drivers/of/of_mdio.c +++ b/drivers/of/of_mdio.c @@ -45,6 +45,8 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np) for (i=0; iirq[i] = PHY_POLL; + mdio->dev.of_node = np; + /* Register the MDIO bus */ rc = mdiobus_register(mdio); if (rc) diff --git a/include/linux/of_mdio.h b/include/linux/of_mdio.h index 53b94e0..912c27a 100644 --- a/include/linux/of_mdio.h +++ b/include/linux/of_mdio.h @@ -22,4 +22,6 @@ extern struct phy_device *of_phy_connect_fixed_link(struct net_device *dev, void (*hndlr)(struct net_device *), phy_interface_t iface); +extern struct mii_bus *of_mdio_find_bus(struct device_node *mdio_np); + #endif /* __LINUX_OF_MDIO_H */ -- 1.7.2.3 From ddaney.cavm@gmail.com Thu May 3 03:16:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 May 2012 03:18:21 +0200 (CEST) Received: from mail-pz0-f53.google.com ([209.85.210.53]:60123 "EHLO mail-pz0-f53.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903782Ab2ECBQy (ORCPT ); Thu, 3 May 2012 03:16:54 +0200 Received: by dadg9 with SMTP id g9so668669dad.26 for ; Wed, 02 May 2012 18:16:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=T0G2bGRddeFotI7eRIRdLATqOcnDgahyKDDBqKMUXac=; b=BN1iwZxtHNmdMwgoNViZL+N9KRhi7nJk6Vxi2dgyew6wzI6vzlw9ZcV5U05JV1h0uv bAetdFWvR0OW5GK8i3VZEUi0H0AUKH+FyHf8ExBFzMKvu0gqYAG0+8xXQ7+NxeTg9U4L ju3HFqyLKO8dpis4/l7c9JuoU1ziyrDjPorPQXaHsCxbhucB2bC7PmEBTH0HZOKmxPFS q0EO8XLdoxGabci3pwywgkxnAGho/bldE2Hm2dteNo2okjxKsstAdrdY/qC5FQMIqXmy pZo+g7okCqRD8DmH5gNoQRPo1r839Tq49SFH1JVTD5UFzcM6NYlrSHN8vEBihiTFMc36 iNjA== Received: by 10.68.202.167 with SMTP id kj7mr2214221pbc.9.1336007808144; Wed, 02 May 2012 18:16:48 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ns3sm1147547pbb.8.2012.05.02.18.16.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 18:16:46 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q431Giw7031060; Wed, 2 May 2012 18:16:44 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q431Gi2X031059; Wed, 2 May 2012 18:16:44 -0700 From: David Daney To: Ralf Baechle , Grant Likely , Rob Herring , devicetree-discuss@lists.ozlabs.org, "David S. Miller" , netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, afleming@gmail.com, galak@kernel.crashing.org, David Daney Subject: [PATCH v6 2/3] netdev/of/phy: Add MDIO bus multiplexer support. Date: Wed, 2 May 2012 18:16:38 -0700 Message-Id: <1336007799-31016-3-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> References: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33128 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 12476 Lines: 454 From: David Daney This patch adds a somewhat generic framework for MDIO bus multiplexers. It is modeled on the I2C multiplexer. The multiplexer is needed if there are multiple PHYs with the same address connected to the same MDIO bus adepter, or if there is insufficient electrical drive capability for all the connected PHY devices. Conceptually it could look something like this: ------------------ | Control Signal | --------+--------- | --------------- --------+------ | MDIO MASTER |---| Multiplexer | --------------- --+-------+---- | | C C h h i i l l d d | | --------- A B --------- | | | | | | | PHY@1 +-------+ +---+ PHY@1 | | | | | | | --------- | | --------- --------- | | --------- | | | | | | | PHY@2 +-------+ +---+ PHY@2 | | | | | --------- --------- This framework configures the bus topology from device tree data. The mechanics of switching the multiplexer is left to device specific drivers. The follow-on patch contains a multiplexer driven by GPIO lines. Signed-off-by: David Daney --- Documentation/devicetree/bindings/net/mdio-mux.txt | 136 ++++++++++++++ drivers/net/phy/Kconfig | 9 + drivers/net/phy/Makefile | 1 + drivers/net/phy/mdio-mux.c | 192 ++++++++++++++++++++ include/linux/mdio-mux.h | 21 ++ 5 files changed, 359 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/mdio-mux.txt create mode 100644 drivers/net/phy/mdio-mux.c create mode 100644 include/linux/mdio-mux.h diff --git a/Documentation/devicetree/bindings/net/mdio-mux.txt b/Documentation/devicetree/bindings/net/mdio-mux.txt new file mode 100644 index 0000000..f65606f --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-mux.txt @@ -0,0 +1,136 @@ +Common MDIO bus multiplexer/switch properties. + +An MDIO bus multiplexer/switch will have several child busses that are +numbered uniquely in a device dependent manner. The nodes for an MDIO +bus multiplexer/switch will have one child node for each child bus. + +Required properties: +- mdio-parent-bus : phandle to the parent MDIO bus. +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties: +- Other properties specific to the multiplexer/switch hardware. + +Required properties for child nodes: +- #address-cells = <1>; +- #size-cells = <0>; +- reg : The sub-bus number. + + +Example : + + /* The parent MDIO bus. */ + smi1: mdio@1180000001900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001900 0x0 0x40>; + }; + + /* + An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a + pair of GPIO lines. Child busses 2 and 3 populated with 4 + PHYs each. + */ + mdio-mux { + compatible = "mdio-mux-gpio"; + gpios = <&gpio1 3 0>, <&gpio1 4 0>; + mdio-parent-bus = <&smi1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + phy11: ethernet-phy@1 { + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + phy12: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + phy13: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + phy14: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + }; + + mdio@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + phy21: ethernet-phy@1 { + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy22: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy23: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy24: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + }; + }; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 0e01f4e..99c0674a 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -135,6 +135,15 @@ config MDIO_OCTEON If in doubt, say Y. +config MDIO_BUS_MUX + tristate + depends on OF_MDIO + help + This module provides a driver framework for MDIO bus + multiplexers which connect one of several child MDIO busses + to a parent bus. Switching between child busses is done by + device specific drivers. + endif # PHYLIB config MICREL_KS8995MA diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index b7438b1..a6b50e7 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o obj-$(CONFIG_AMD_PHY) += amd.o +obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o diff --git a/drivers/net/phy/mdio-mux.c b/drivers/net/phy/mdio-mux.c new file mode 100644 index 0000000..39ea067 --- /dev/null +++ b/drivers/net/phy/mdio-mux.c @@ -0,0 +1,192 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011, 2012 Cavium, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#define DRV_VERSION "1.0" +#define DRV_DESCRIPTION "MDIO bus multiplexer driver" + +struct mdio_mux_child_bus; + +struct mdio_mux_parent_bus { + struct mii_bus *mii_bus; + int current_child; + int parent_id; + void *switch_data; + int (*switch_fn)(int current_child, int desired_child, void *data); + + /* List of our children linked through their next fields. */ + struct mdio_mux_child_bus *children; +}; + +struct mdio_mux_child_bus { + struct mii_bus *mii_bus; + struct mdio_mux_parent_bus *parent; + struct mdio_mux_child_bus *next; + int bus_number; + int phy_irq[PHY_MAX_ADDR]; +}; + +/* + * The parent bus' lock is used to order access to the switch_fn. + */ +static int mdio_mux_read(struct mii_bus *bus, int phy_id, int regnum) +{ + struct mdio_mux_child_bus *cb = bus->priv; + struct mdio_mux_parent_bus *pb = cb->parent; + int r; + + mutex_lock(&pb->mii_bus->mdio_lock); + r = pb->switch_fn(pb->current_child, cb->bus_number, pb->switch_data); + if (r) + goto out; + + pb->current_child = cb->bus_number; + + r = pb->mii_bus->read(pb->mii_bus, phy_id, regnum); +out: + mutex_unlock(&pb->mii_bus->mdio_lock); + + return r; +} + +/* + * The parent bus' lock is used to order access to the switch_fn. + */ +static int mdio_mux_write(struct mii_bus *bus, int phy_id, + int regnum, u16 val) +{ + struct mdio_mux_child_bus *cb = bus->priv; + struct mdio_mux_parent_bus *pb = cb->parent; + + int r; + + mutex_lock(&pb->mii_bus->mdio_lock); + r = pb->switch_fn(pb->current_child, cb->bus_number, pb->switch_data); + if (r) + goto out; + + pb->current_child = cb->bus_number; + + r = pb->mii_bus->write(pb->mii_bus, phy_id, regnum, val); +out: + mutex_unlock(&pb->mii_bus->mdio_lock); + + return r; +} + +static int parent_count; + +int mdio_mux_init(struct device *dev, + int (*switch_fn)(int cur, int desired, void *data), + void **mux_handle, + void *data) +{ + struct device_node *parent_bus_node; + struct device_node *child_bus_node; + int r, ret_val; + struct mii_bus *parent_bus; + struct mdio_mux_parent_bus *pb; + struct mdio_mux_child_bus *cb; + + if (!dev->of_node) + return -ENODEV; + + parent_bus_node = of_parse_phandle(dev->of_node, "mdio-parent-bus", 0); + + if (!parent_bus_node) + return -ENODEV; + + parent_bus = of_mdio_find_bus(parent_bus_node); + if (parent_bus == NULL) { + ret_val = -EPROBE_DEFER; + goto err_parent_bus; + } + + pb = devm_kzalloc(dev, sizeof(*pb), GFP_KERNEL); + if (pb == NULL) { + ret_val = -ENOMEM; + goto err_parent_bus; + } + + pb->switch_data = data; + pb->switch_fn = switch_fn; + pb->current_child = -1; + pb->parent_id = parent_count++; + pb->mii_bus = parent_bus; + + ret_val = -ENODEV; + for_each_child_of_node(dev->of_node, child_bus_node) { + u32 v; + + r = of_property_read_u32(child_bus_node, "reg", &v); + if (r) + continue; + + cb = devm_kzalloc(dev, sizeof(*cb), GFP_KERNEL); + if (cb == NULL) { + dev_err(dev, + "Error: Failed to allocate memory for child\n"); + ret_val = -ENOMEM; + break; + } + cb->bus_number = v; + cb->parent = pb; + cb->mii_bus = mdiobus_alloc(); + cb->mii_bus->priv = cb; + + cb->mii_bus->irq = cb->phy_irq; + cb->mii_bus->name = "mdio_mux"; + snprintf(cb->mii_bus->id, MII_BUS_ID_SIZE, "%x.%x", + pb->parent_id, v); + cb->mii_bus->parent = dev; + cb->mii_bus->read = mdio_mux_read; + cb->mii_bus->write = mdio_mux_write; + r = of_mdiobus_register(cb->mii_bus, child_bus_node); + if (r) { + mdiobus_free(cb->mii_bus); + devm_kfree(dev, cb); + } else { + of_node_get(child_bus_node); + cb->next = pb->children; + pb->children = cb; + } + } + if (pb->children) { + *mux_handle = pb; + dev_info(dev, "Version " DRV_VERSION "\n"); + return 0; + } +err_parent_bus: + of_node_put(parent_bus_node); + return ret_val; +} +EXPORT_SYMBOL_GPL(mdio_mux_init); + +void mdio_mux_uninit(void *mux_handle) +{ + struct mdio_mux_parent_bus *pb = mux_handle; + struct mdio_mux_child_bus *cb = pb->children; + + while (cb) { + mdiobus_unregister(cb->mii_bus); + mdiobus_free(cb->mii_bus); + cb = cb->next; + } +} +EXPORT_SYMBOL_GPL(mdio_mux_uninit); + +MODULE_DESCRIPTION(DRV_DESCRIPTION); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("David Daney"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mdio-mux.h b/include/linux/mdio-mux.h new file mode 100644 index 0000000..a243dbb --- /dev/null +++ b/include/linux/mdio-mux.h @@ -0,0 +1,21 @@ +/* + * MDIO bus multiplexer framwork. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011, 2012 Cavium, Inc. + */ +#ifndef __LINUX_MDIO_MUX_H +#define __LINUX_MDIO_MUX_H +#include + +int mdio_mux_init(struct device *dev, + int (*switch_fn) (int cur, int desired, void *data), + void **mux_handle, + void *data); + +void mdio_mux_uninit(void *mux_handle); + +#endif /* __LINUX_MDIO_MUX_H */ -- 1.7.2.3 From ddaney.cavm@gmail.com Thu May 3 03:16:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 May 2012 03:18:44 +0200 (CEST) Received: from mail-pz0-f53.google.com ([209.85.210.53]:61626 "EHLO mail-pz0-f53.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903783Ab2ECBQz (ORCPT ); Thu, 3 May 2012 03:16:55 +0200 Received: by dadg9 with SMTP id g9so668675dad.26 for ; Wed, 02 May 2012 18:16:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=BPQqjdHruNTkIEgrlrDnHeOgJlTT6QsUTllRXMfPvh8=; b=TL8+qsdWxvlCrl4GIkkxFot4sPdUkgbU3xkwwFuZlT0vNI8SkF2UAG5suMYXbMykp3 QF2eZoEAFT7zpTyigyXG4pTiNI73+6upkBfskisC0f0BrDVuOiPTgYWXIiB+5ucjxMqb 6RTP843mQljrf4zP6YQS/0OT7zeNDkleEQivFs3+4/QYavN7fladDj76x38cHUD6Rejv 7PRzxvP1Q3rgK1nQrbxAvwQdINlHT1h2w9JtfYoOxlXCW7CevDz3AYs6LBcuFQEiaWYW gm48zdNiohLTztQN/2YF99HCAsYrxBUw91RZhKvBVX4YUiSsVUF7vT4OZ03VZNg/BOcj g77A== Received: by 10.68.227.41 with SMTP id rx9mr2460494pbc.32.1336007808403; Wed, 02 May 2012 18:16:48 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id wn3sm3528066pbc.74.2012.05.02.18.16.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 18:16:46 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q431Giv2031064; Wed, 2 May 2012 18:16:44 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q431Gik4031063; Wed, 2 May 2012 18:16:44 -0700 From: David Daney To: Ralf Baechle , Grant Likely , Rob Herring , devicetree-discuss@lists.ozlabs.org, "David S. Miller" , netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, afleming@gmail.com, galak@kernel.crashing.org, David Daney Subject: [PATCH v6 3/3] netdev/of/phy: Add MDIO bus multiplexer driven by GPIO lines. Date: Wed, 2 May 2012 18:16:39 -0700 Message-Id: <1336007799-31016-4-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> References: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 33129 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8869 Lines: 331 From: David Daney The GPIO pins select which sub bus is connected to the master. Initially tested with an sn74cbtlv3253 switch device wired into the MDIO bus. Signed-off-by: David Daney --- .../devicetree/bindings/net/mdio-mux-gpio.txt | 127 +++++++++++++++++ drivers/net/phy/Kconfig | 10 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/mdio-mux-gpio.c | 142 ++++++++++++++++++++ 4 files changed, 280 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/mdio-mux-gpio.txt create mode 100644 drivers/net/phy/mdio-mux-gpio.c diff --git a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt b/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt new file mode 100644 index 0000000..7938411 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt @@ -0,0 +1,127 @@ +Properties for an MDIO bus multiplexer/switch controlled by GPIO pins. + +This is a special case of a MDIO bus multiplexer. One or more GPIO +lines are used to control which child bus is connected. + +Required properties in addition to the generic multiplexer properties: + +- compatible : mdio-mux-gpio. +- gpios : GPIO specifiers for each GPIO line. One or more must be specified. + + +Example : + + /* The parent MDIO bus. */ + smi1: mdio@1180000001900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001900 0x0 0x40>; + }; + + /* + An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a + pair of GPIO lines. Child busses 2 and 3 populated with 4 + PHYs each. + */ + mdio-mux { + compatible = "mdio-mux-gpio"; + gpios = <&gpio1 3 0>, <&gpio1 4 0>; + mdio-parent-bus = <&smi1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + phy11: ethernet-phy@1 { + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + phy12: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + phy13: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + phy14: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + }; + + mdio@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + phy21: ethernet-phy@1 { + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy22: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy23: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy24: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + }; + }; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 99c0674a..944cdfb 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -144,6 +144,16 @@ config MDIO_BUS_MUX to a parent bus. Switching between child busses is done by device specific drivers. +config MDIO_BUS_MUX_GPIO + tristate "Support for GPIO controlled MDIO bus multiplexers" + depends on OF_GPIO && OF_MDIO + select MDIO_BUS_MUX + help + This module provides a driver for MDIO bus multiplexers that + are controlled via GPIO lines. The multiplexer connects one of + several child MDIO busses to a parent bus. Child bus + selection is under the control of GPIO lines. + endif # PHYLIB config MICREL_KS8995MA diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index a6b50e7..f51af68 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o obj-$(CONFIG_AMD_PHY) += amd.o obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o +obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o diff --git a/drivers/net/phy/mdio-mux-gpio.c b/drivers/net/phy/mdio-mux-gpio.c new file mode 100644 index 0000000..e0cc4ef --- /dev/null +++ b/drivers/net/phy/mdio-mux-gpio.c @@ -0,0 +1,142 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011, 2012 Cavium, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_VERSION "1.0" +#define DRV_DESCRIPTION "GPIO controlled MDIO bus multiplexer driver" + +#define MDIO_MUX_GPIO_MAX_BITS 8 + +struct mdio_mux_gpio_state { + int gpio[MDIO_MUX_GPIO_MAX_BITS]; + unsigned int num_gpios; + void *mux_handle; +}; + +static int mdio_mux_gpio_switch_fn(int current_child, int desired_child, + void *data) +{ + int change; + unsigned int n; + struct mdio_mux_gpio_state *s = data; + + if (current_child == desired_child) + return 0; + + change = current_child == -1 ? -1 : current_child ^ desired_child; + + for (n = 0; n < s->num_gpios; n++) { + if (change & 1) + gpio_set_value_cansleep(s->gpio[n], + (desired_child & 1) != 0); + change >>= 1; + desired_child >>= 1; + } + + return 0; +} + +static int __devinit mdio_mux_gpio_probe(struct platform_device *pdev) +{ + enum of_gpio_flags f; + struct mdio_mux_gpio_state *s; + unsigned int num_gpios; + unsigned int n; + int r; + + if (!pdev->dev.of_node) + return -ENODEV; + + num_gpios = of_gpio_count(pdev->dev.of_node); + if (num_gpios == 0 || num_gpios > MDIO_MUX_GPIO_MAX_BITS) + return -ENODEV; + + s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); + if (!s) + return -ENOMEM; + + s->num_gpios = num_gpios; + + for (n = 0; n < num_gpios; ) { + int gpio = of_get_gpio_flags(pdev->dev.of_node, n, &f); + if (gpio < 0) { + r = (gpio == -ENODEV) ? -EPROBE_DEFER : gpio; + goto err; + } + s->gpio[n] = gpio; + + n++; + + r = gpio_request(gpio, "mdio_mux_gpio"); + if (r) + goto err; + + r = gpio_direction_output(gpio, 0); + if (r) + goto err; + } + + r = mdio_mux_init(&pdev->dev, + mdio_mux_gpio_switch_fn, &s->mux_handle, s); + + if (r == 0) { + pdev->dev.platform_data = s; + return 0; + } +err: + while (n) { + n--; + gpio_free(s->gpio[n]); + } + devm_kfree(&pdev->dev, s); + return r; +} + +static int __devexit mdio_mux_gpio_remove(struct platform_device *pdev) +{ + struct mdio_mux_gpio_state *s = pdev->dev.platform_data; + mdio_mux_uninit(s->mux_handle); + return 0; +} + +static struct of_device_id mdio_mux_gpio_match[] = { + { + .compatible = "mdio-mux-gpio", + }, + { + /* Legacy compatible property. */ + .compatible = "cavium,mdio-mux-sn74cbtlv3253", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mdio_mux_gpio_match); + +static struct platform_driver mdio_mux_gpio_driver = { + .driver = { + .name = "mdio-mux-gpio", + .owner = THIS_MODULE, + .of_match_table = mdio_mux_gpio_match, + }, + .probe = mdio_mux_gpio_probe, + .remove = __devexit_p(mdio_mux_gpio_remove), +}; + +module_platform_driver(mdio_mux_gpio_driver); + +MODULE_DESCRIPTION(DRV_DESCRIPTION); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("David Daney"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 From w.sang@pengutronix.de Thu May 3 13:26:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 May 2012 13:26:38 +0200 (CEST) Received: from metis.ext.pengutronix.de ([92.198.50.35]:56167 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903596Ab2ECL0d (ORCPT ); Thu, 3 May 2012 13:26:33 +0200 Received: from dude.hi.pengutronix.de ([2001:6f8:1178:2:21e:67ff:fe11:9c5c]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1SPuB1-0001B6-SB; Thu, 03 May 2012 13:26:27 +0200 Received: from wsa by dude.hi.pengutronix.de with local (Exim 4.77) (envelope-from ) id 1SPuAx-0003en-EN; Thu, 03 May 2012 13:26:23 +0200 Date: Thu, 3 May 2012 13:26:23 +0200 From: Wolfram Sang To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring , linux-kernel@vger.kernel.org, David Daney , "Jean Delvare (PC drivers, core)" , "Ben Dooks (embedded platforms)" , linux-i2c@vger.kernel.org Subject: Re: [PATCH v2 1/5] i2c: Convert i2c-octeon.c to use device tree. Message-ID: <20120503112623.GF9574@pengutronix.de> References: <1335489630-27017-1-git-send-email-ddaney.cavm@gmail.com> <1335489630-27017-2-git-send-email-ddaney.cavm@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="p8PhoBjPxaQXD0vg" Content-Disposition: inline In-Reply-To: <1335489630-27017-2-git-send-email-ddaney.cavm@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-SA-Exim-Connect-IP: 2001:6f8:1178:2:21e:67ff:fe11:9c5c X-SA-Exim-Mail-From: wsa@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-mips@linux-mips.org X-archive-position: 33130 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: w.sang@pengutronix.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1742 Lines: 51 --p8PhoBjPxaQXD0vg Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Apr 26, 2012 at 06:20:26PM -0700, David Daney wrote: > From: David Daney >=20 > There are three parts to this: >=20 > 1) Remove the definitions of OCTEON_IRQ_TWSI and OCTEON_IRQ_TWSI2. > The interrupts are specified by the device tree and these hard > coded irq numbers block the used of the irq lines by the irq_domain > code. >=20 > 2) Remove platform device setup code from octeon-platform.c, it is > now unused. >=20 > 3) Convert i2c-octeon.c to use device tree. Part of this includes > using the devm_* functions instead of the raw counterparts, thus > simplifying error handling. No functionality is changed. >=20 > Signed-off-by: David Daney > Acked-by: Rob Herring > Cc: "Jean Delvare (PC drivers, core)" > Cc: "Ben Dooks (embedded platforms)" > Cc: "Wolfram Sang (embedded platforms)" > Cc: linux-i2c@vger.kernel.org I2C changes look okay. I'd think this goes in via MIPS-tree? Acked-by: Wolfram Sang --=20 Pengutronix e.K. | Wolfram Sang | Industrial Linux Solutions | http://www.pengutronix.de/ | --p8PhoBjPxaQXD0vg Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iEYEARECAAYFAk+ia18ACgkQD27XaX1/VRvy0QCgw45MhoPCDZwSKlGvSSUYtFT4 KqgAn0dIv9IJZIyeWi2K8dXNg2coKDbO =pvhr -----END PGP SIGNATURE----- --p8PhoBjPxaQXD0vg-- From blogic@openwrt.org Thu May 3 19:43:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 May 2012 19:44:03 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:50541 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903771Ab2ECRn7 (ORCPT ); Thu, 3 May 2012 19:43:59 +0200 From: John Crispin To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , John Crispin Subject: [PATCH 02/14] MIPS: pci: parse memory ranges from devicetree Date: Thu, 3 May 2012 19:42:29 +0200 Message-Id: <1336066949-24546-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33131 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3339 Lines: 126 Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit bus width is supported. This function is based on the implementation found on powerpc. Signed-off-by: John Crispin --- Changes in V2 * remove some #ifdefs * rename to pci_load_of_ranges Changes in V3 * set pointers to NULL and not 0 arch/mips/include/asm/pci.h | 6 ++++ arch/mips/pci/pci.c | 55 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index fcd4060..90bf3b3 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -17,6 +17,7 @@ */ #include +#include /* * Each pci channel is a top-level PCI bus seem by CPU. A machine with @@ -26,6 +27,7 @@ struct pci_controller { struct pci_controller *next; struct pci_bus *bus; + struct device_node *of_node; struct pci_ops *pci_ops; struct resource *mem_resource; @@ -142,4 +144,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) extern char * (*pcibios_plat_setup)(char *str); +/* this function parses memory ranges from a device node */ +extern void __devinit pci_load_of_ranges(struct pci_controller *hose, + struct device_node *node); + #endif /* _ASM_PCI_H */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 0514866..a10c951 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -16,6 +16,7 @@ #include #include #include +#include #include @@ -114,9 +115,63 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) pci_bus_assign_resources(bus); pci_enable_bridges(bus); } + bus->dev.of_node = hose->of_node; } } +#ifdef CONFIG_OF +void __devinit pci_load_of_ranges(struct pci_controller *hose, + struct device_node *node) +{ + const __be32 *ranges; + int rlen; + int pna = of_n_addr_cells(node); + int np = pna + 5; + + pr_info("PCI host bridge %s ranges:\n", node->full_name); + ranges = of_get_property(node, "ranges", &rlen); + if (ranges == NULL) + return; + hose->of_node = node; + + while ((rlen -= np * 4) >= 0) { + u32 pci_space; + struct resource *res = NULL; + unsigned long long addr, size; + + pci_space = ranges[0]; + addr = of_translate_address(node, ranges + 3); + size = of_read_number(ranges + pna + 3, 2); + ranges += np; + switch ((pci_space >> 24) & 0x3) { + case 1: /* PCI IO space */ + pr_info(" IO 0x%016llx..0x%016llx\n", + addr, addr + size - 1); + hose->io_map_base = + (unsigned long)ioremap(addr, size); + res = hose->io_resource; + res->flags = IORESOURCE_IO; + break; + case 2: /* PCI Memory space */ + case 3: /* PCI 64 bits Memory space */ + pr_info(" MEM 0x%016llx..0x%016llx\n", + addr, addr + size - 1); + res = hose->mem_resource; + res->flags = IORESOURCE_MEM; + break; + } + if (res != NULL) { + res->start = addr; + res->name = node->full_name; + res->end = res->start + size - 1; + res->parent = NULL; + res->sibling = NULL; + res->child = NULL; + } + } +} +#endif + static DEFINE_MUTEX(pci_scan_mutex); void __devinit register_pci_controller(struct pci_controller *hose) -- 1.7.9.1 From geert@linux-m68k.org Thu May 3 21:30:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 May 2012 21:30:30 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:46136 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903765Ab2ECTa0 convert rfc822-to-8bit (ORCPT ); Thu, 3 May 2012 21:30:26 +0200 Received: by yenr9 with SMTP id r9so424471yen.36 for ; Thu, 03 May 2012 12:30:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=l1DlFo0gltURw60q+cQHRq36KSU7X6VDNin+NMLqdcA=; b=fWH+5Yz2ykhSVzx1E9G5//L9eHEUHR7ecMvFNi+4fQrWPrfkj+bi5HkNkej//7AVaD UN07Veza9IaOzjVqqiti58dCDXoggrS9LyY1fVVu8sZ1l0/VlmKG6aJ5lHdHhsRailJF sLlSsN/r9983N5mB/Mepj1TKx9EuWBFPXlGNvdanBtDsSUfAJvjpP7rF1iKRVDTG3oC4 8b9f8NoqkIiya3ihe4n4r0hLTg9q3Z4kgfjVhe+qWHD7p4AXcUk2VWCWDrXBCIjGwK8+ fxAV18JBgCL7A6i3Rt5P21fmUVXfs1FwLbeUlYSnoYaN6B86qAAyyKJ0JQalcPZ++fEg rjtg== MIME-Version: 1.0 Received: by 10.50.178.71 with SMTP id cw7mr1227470igc.19.1336073420081; Thu, 03 May 2012 12:30:20 -0700 (PDT) Received: by 10.231.144.135 with HTTP; Thu, 3 May 2012 12:30:20 -0700 (PDT) In-Reply-To: <1336066949-24546-1-git-send-email-blogic@openwrt.org> References: <1336066949-24546-1-git-send-email-blogic@openwrt.org> Date: Thu, 3 May 2012 21:30:20 +0200 X-Google-Sender-Auth: Ucju-3sORwKMowOXn4NvoCS2MDA Message-ID: Subject: Re: [PATCH 02/14] MIPS: pci: parse memory ranges from devicetree From: Geert Uytterhoeven To: John Crispin Cc: Ralf Baechle , "linux-mips@linux-mips.org" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 33132 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1707 Lines: 47 On Thu, May 3, 2012 at 7:42 PM, John Crispin wrote: > Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit > bus width is supported. This function is based on the implementation found on > powerpc. There's no pci_load_of_ranges() in arch/powerpc/? > +void __devinit pci_load_of_ranges(struct pci_controller *hose, > +                               struct device_node *node) > +{ > +       const __be32 *ranges; > +       int rlen; > +       int pna = of_n_addr_cells(node); > +       int np = pna + 5; > + > +       pr_info("PCI host bridge %s ranges:\n", node->full_name); > +       ranges = of_get_property(node, "ranges", &rlen); > +       if (ranges == NULL) > +               return; > +       hose->of_node = node; > + > +       while ((rlen -= np * 4) >= 0) { > +               u32 pci_space; > +               struct resource *res = NULL; > +               unsigned long long addr, size; You better use u64, as that's what of_translate_address() and of_read_number() return. > + > +               pci_space = ranges[0]; pci_space = be32_to_cpup(&ranges[0]) > +               addr = of_translate_address(node, ranges + 3); > +               size = of_read_number(ranges + pna + 3, 2); Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.                                 -- Linus Torvalds From blogic@openwrt.org Thu May 3 21:41:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 May 2012 21:41:06 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:43608 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903765Ab2ECTlA (ORCPT ); Thu, 3 May 2012 21:41:00 +0200 Message-ID: <4FA2DEF4.9050506@openwrt.org> Date: Thu, 03 May 2012 21:39:32 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: Geert Uytterhoeven CC: Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [PATCH 02/14] MIPS: pci: parse memory ranges from devicetree References: <1336066949-24546-1-git-send-email-blogic@openwrt.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-archive-position: 33133 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 174 Lines: 12 Hi Geert, > There's no pci_load_of_ranges() in arch/powerpc/? > Sorry, its based on pci_process_bridge_OF_ranges. I will fold your comments into the patch, Thanks, John From mattst88@gmail.com Fri May 4 00:41:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 00:41:09 +0200 (CEST) Received: from mail-gh0-f177.google.com ([209.85.160.177]:43565 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903771Ab2ECWlF (ORCPT ); Fri, 4 May 2012 00:41:05 +0200 Received: by ghbf11 with SMTP id f11so2655364ghb.36 for ; Thu, 03 May 2012 15:40:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=lrybytZ9Y5B/xyXwFJf88y+WIuWRpBUs5DV+T5g4bB0=; b=0C4lkCl9m6428UxmIKWOsjv3a1Bnva5zk6EIp1QXGJfRqRT9UlW6yIajHdocX1x/1z P9Lvaj5/2QeIisSewIEGjhP4O67T5WRadez/4NkXMphnWcQrxe6oTQFBALImuSLlidGu tQ6l5pAivoMbbvmfJfTmirivsSXsKubdZp7nSTZ2WhQ2yaWi3WL5/yg8u1AlNP21Cfpa Mc8mvVqTDAJxJvVvLMw1ZVEuAICA4WMt5jJGSzGrJL/JttZu8nlG7TZlpFRpwCX7cyof mAPggSBHYA+PoJ3MWTJfcdtlBCPcc+pmdiAKA7xidOTtW03eFr86fCBKqHzf/VxO4oQ3 D7+Q== Received: by 10.236.179.40 with SMTP id g28mr5055979yhm.86.1336084859529; Thu, 03 May 2012 15:40:59 -0700 (PDT) Received: from localhost (cpe-174-109-057-184.nc.res.rr.com. [174.109.57.184]) by mx.google.com with ESMTPS id k35sm10421203ani.3.2012.05.03.15.40.58 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 03 May 2012 15:40:58 -0700 (PDT) From: Matt Turner To: Ralf Baechle Cc: linux-mips@linux-mips.org, Matt Turner Subject: [PATCH] mips: set ST0_MX flag for MDMX Date: Thu, 3 May 2012 18:40:45 -0400 Message-Id: <1336084845-28995-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.3.4 X-archive-position: 33134 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1163 Lines: 35 As the comment in commit 3301edcb says, DSP and MDMX share the same config flag bit. Without this set, MDMX instructions cause Illegal instruction errors. Signed-off-by: Matt Turner --- Is MDMX implemented by anything other than some Broadcom CPUs? Is it totally replaced by DSP? I had a terrible time finding any documentation on it (which is annoying because Volume IV-b covering MDMX is referenced by all the MIPS64 documents.) but finally found a copy here: www.enlight.ru/docs/cpu/risc/mips/MDMXspec.pdf If it's dead, it's too bad because it's a pretty cool ISA. arch/mips/kernel/traps.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index cfdaaa4..89ead75 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1548,7 +1548,7 @@ void __cpuinit per_cpu_trap_init(void) #endif if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) status_set |= ST0_XX; - if (cpu_has_dsp) + if (cpu_has_dsp || cpu_has_mdmx) status_set |= ST0_MX; change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, -- 1.7.3.4 From bhelgaas@google.com Fri May 4 02:30:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 02:30:49 +0200 (CEST) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:60634 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903782Ab2EDAap convert rfc822-to-8bit (ORCPT ); Fri, 4 May 2012 02:30:45 +0200 Received: by lagy4 with SMTP id y4so2085942lag.36 for ; Thu, 03 May 2012 17:30:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding:x-system-of-record; bh=Y/Ftqp2+f0C33bWO5FyppNYLGW3qQdI+lguCiWNzNQ8=; b=WvIdsWIiYGPAVs28j/adO49txkSfOwjnEKxRrzL3JHXyh5K2Bpy+DO8N/EXopovbWk ZiT/JFpJa11Cezq/YviVhEzny0KDFO05CkpWbFSvfs2WFRj6X7wBWbYcp/mVuuP1PMDU Pohmk6ZP8RK+j33ltsFAxVrsuYRz1lhFGJ6ceIplZm3bU4NEN2YI2Hd2QdljVoMdUCOc jkbZp5/a+3dYGYgU7A/2xcMERnsy1EakEoeo1Zk/ndZm0Gkv1uAaLlSGqdxx1EQYOskx KceGw2A1+/5eBTg8Cut0L5aFXZfNh0A0qxfZTNTLMlA5NLvzlBCD98oDYjeVJ2htfzFa qLmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding:x-system-of-record :x-gm-message-state; bh=Y/Ftqp2+f0C33bWO5FyppNYLGW3qQdI+lguCiWNzNQ8=; b=mHvV4IaOBGsNypwxtOWSbpGzGK0co8b9dHMX4m2vdvVpLUZMgYVwDvr4cOlneF2ZHs HW24PRTMN9YN1TeOaw4jDHe6ZndVOriMF5CFYpT/GZ8NslcSISbaa+R5BaxhPFXw1/0b 8fQzfsTzYWt8uSBBks1a6Z5LoJ9AfElZLk3W9I2mHmxF+IrGJYW3K0fv/PhIVhKOIZSu 2MPtDrzjfOS8yaWmb5YnryrOMkE8BphkFbrTcwykc3HMydrljcwh2X95Ng7UOOHJjS/x rIVCLVy1qJC5a6F8Y8712H65Us8Rk/0jIciDkIAewUD1e0EsTPe6gG/jq+4El4e6ooTM kgCA== Received: by 10.152.128.137 with SMTP id no9mr3890873lab.2.1336091440360; Thu, 03 May 2012 17:30:40 -0700 (PDT) Received: by 10.152.128.137 with SMTP id no9mr3890856lab.2.1336091440239; Thu, 03 May 2012 17:30:40 -0700 (PDT) MIME-Version: 1.0 Received: by 10.112.86.6 with HTTP; Thu, 3 May 2012 17:30:20 -0700 (PDT) In-Reply-To: <4F9FE4F6.5070909@openwrt.org> References: <1335808019-24502-1-git-send-email-blogic@openwrt.org> <4F9ED1DC.3050007@gmail.com> <4F9FE4F6.5070909@openwrt.org> From: Bjorn Helgaas Date: Thu, 3 May 2012 18:30:20 -0600 Message-ID: Subject: Re: [PATCH] OF: PCI: const usage needed by MIPS To: John Crispin Cc: David Daney , Ralf Baechle , Grant Likely , linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-System-Of-Record: true X-Gm-Message-State: ALoCoQk4H8292E23VWjI4gKTNW2/gsXG/EmIThKYLZ2CAL5WoBbWMxTNmBnGhNzUDCImPxDocN6tZ8sQ7yJ3rGIpyUkPorG2F5xF3WpG7xyEvJFOczugHo08Kr0piSlN/7zQvl5xxu+xFy638AB29+uqagba7PQtcg== X-archive-position: 33135 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1635 Lines: 44 On Tue, May 1, 2012 at 7:28 AM, John Crispin wrote: > On 30/04/12 19:54, David Daney wrote: >> On 04/30/2012 10:46 AM, John Crispin wrote: >>> On MIPS we want to call of_irq_map_pci from inside >>> >>> arch/mips/include/asm/pci.h:extern int pcibios_map_irq( >>>                 const struct pci_dev *dev, u8 slot, u8 pin); >>> >>> For this to work we need to change several functions to const usage. >> >> I think there is a mismatch on this throughout the kernel. >> >> Properly fixing it requires touching many more places than these. >> Although I haven't tried it, I wouldn't be surprised if doing this >> caused warnings to appear in non-MIPS code. >> >> Ralf had a patch at one point that tried to make this consistent >> tree-wide, but it is not yet applied. >> >> David Daney > > Hi, > > Ok, lets see what Ralf has to say. > > I just tested the patch on x86 with OF enabled and drivers turned on > that use the API. I did not see any errors appear. I'm far from a const expert, but I think this should be safe. Here's my reasoning: We're changing pci_swizzle_interrupt_pin() to take a pointer to a constant struct pci_dev. pci_swizzle_interrupt_pin() only reads the struct pci_dev; it doesn't modify it. It is legal to pass either "struct pci_dev *" or "const struct pci_dev *" to a function expecting "const struct pci_dev *"; the callee just won't be able to modify the struct, even if the caller can. Similar reasoning applies to of_irq_map_pci(). So I'm fine with this. You sent it to Grant, so I'll assume he'll merge it unless I hear otherwise. Acked-by: Bjorn Helgaas From ddaney.cavm@gmail.com Fri May 4 03:18:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 03:18:15 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:64253 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903771Ab2EDBSI (ORCPT ); Fri, 4 May 2012 03:18:08 +0200 Received: by pbbrq13 with SMTP id rq13so3428443pbb.36 for ; Thu, 03 May 2012 18:18:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=l4sAEpx8MjtX1KI7Lhv/D/Am3O/SilbAfdb4moW3Uko=; b=H/8yAbyfwkQj0JVsdNbDGzpAgV005Sxg3Ry1nCViXQzGuC85XIvW+4MZcuAxDFAJVj KCP6poyWYlQNvVYz5VaGHlB7KybhchPgwN2Il3EimgtUPnEzOjRzJRLoH+SOcJ/2+p1+ kSycSLIXxhV6cCiKNLq+rqyhSVdLmhGPW6u6c0WA9vc+M6EasioEe5z/4i0BOtZN+471 myrkHP/4Leuo1B6Mp+k8wdgH5okw5RKuHrUi5nnzO55aI4ugPAHU869xYQ5bGKgeLYjh YUCw9EwON05xpRWBUOBGlgfqOMuO0ZbRLtvJN/8fKxTJXyZGVF2aE8A8xDNkLh5VRyQz 2Jlw== Received: by 10.68.200.74 with SMTP id jq10mr1839952pbc.66.1336094282010; Thu, 03 May 2012 18:18:02 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id ky10sm117171pbc.0.2012.05.03.18.18.00 (version=SSLv3 cipher=OTHER); Thu, 03 May 2012 18:18:00 -0700 (PDT) Message-ID: <4FA32E47.7020406@gmail.com> Date: Thu, 03 May 2012 18:17:59 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Bjorn Helgaas CC: John Crispin , Ralf Baechle , Grant Likely , linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org Subject: Re: [PATCH] OF: PCI: const usage needed by MIPS References: <1335808019-24502-1-git-send-email-blogic@openwrt.org> <4F9ED1DC.3050007@gmail.com> <4F9FE4F6.5070909@openwrt.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 33136 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2162 Lines: 64 On 05/03/2012 05:30 PM, Bjorn Helgaas wrote: > On Tue, May 1, 2012 at 7:28 AM, John Crispin wrote: >> On 30/04/12 19:54, David Daney wrote: >>> On 04/30/2012 10:46 AM, John Crispin wrote: >>>> On MIPS we want to call of_irq_map_pci from inside >>>> >>>> arch/mips/include/asm/pci.h:extern int pcibios_map_irq( >>>> const struct pci_dev *dev, u8 slot, u8 pin); >>>> >>>> For this to work we need to change several functions to const usage. >>> >>> I think there is a mismatch on this throughout the kernel. >>> >>> Properly fixing it requires touching many more places than these. >>> Although I haven't tried it, I wouldn't be surprised if doing this >>> caused warnings to appear in non-MIPS code. >>> >>> Ralf had a patch at one point that tried to make this consistent >>> tree-wide, but it is not yet applied. >>> >>> David Daney >> >> Hi, >> >> Ok, lets see what Ralf has to say. >> >> I just tested the patch on x86 with OF enabled and drivers turned on >> that use the API. I did not see any errors appear. > > I'm far from a const expert, but I think this should be safe. > Here's my reasoning: > > We're changing pci_swizzle_interrupt_pin() to take a pointer to a > constant struct pci_dev. pci_swizzle_interrupt_pin() only reads the > struct pci_dev; it doesn't modify it. It is legal to pass either > "struct pci_dev *" or "const struct pci_dev *" to a function expecting > "const struct pci_dev *"; the callee just won't be able to modify the > struct, even if the caller can. > The problem is when you start declaring function pointers in various ops vectors. Consider: void (*foo)(const struct pci_dev *) void (*bar)(struct pci_dev *) foo and bar are not type compatible, and you will get compiler warnings if you use one where the other is expected. So the question is: Are we ever going to the address of any of the functions that are being modified? If so, we have created a problem. > Similar reasoning applies to of_irq_map_pci(). > > So I'm fine with this. You sent it to Grant, so I'll assume he'll > merge it unless I hear otherwise. > > Acked-by: Bjorn Helgaas > From blogic@openwrt.org Fri May 4 12:51:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 12:51:50 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:50452 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903663Ab2EDKvn (ORCPT ); Fri, 4 May 2012 12:51:43 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V4 02/14] MIPS: pci: parse memory ranges from devicetree Date: Fri, 4 May 2012 12:50:13 +0200 Message-Id: <1336128613-7661-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33137 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3450 Lines: 130 Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit bus width is supported. This function is based on pci_process_bridge_OF_ranges from powerpc. Signed-off-by: John Crispin --- Changes in V2 * remove some #ifdefs * rename to pci_load_of_ranges Changes in V3 * set pointers to NULL and not 0 Changes in V4 * use u64 rather than unsigned long long * make sure pci_space has the correct endianess arch/mips/include/asm/pci.h | 6 ++++ arch/mips/pci/pci.c | 55 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index fcd4060..90bf3b3 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -17,6 +17,7 @@ */ #include +#include /* * Each pci channel is a top-level PCI bus seem by CPU. A machine with @@ -26,6 +27,7 @@ struct pci_controller { struct pci_controller *next; struct pci_bus *bus; + struct device_node *of_node; struct pci_ops *pci_ops; struct resource *mem_resource; @@ -142,4 +144,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) extern char * (*pcibios_plat_setup)(char *str); +/* this function parses memory ranges from a device node */ +extern void __devinit pci_load_of_ranges(struct pci_controller *hose, + struct device_node *node); + #endif /* _ASM_PCI_H */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 0514866..271e8c4a 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -16,6 +16,7 @@ #include #include #include +#include #include @@ -114,9 +115,63 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) pci_bus_assign_resources(bus); pci_enable_bridges(bus); } + bus->dev.of_node = hose->of_node; } } +#ifdef CONFIG_OF +void __devinit pci_load_of_ranges(struct pci_controller *hose, + struct device_node *node) +{ + const __be32 *ranges; + int rlen; + int pna = of_n_addr_cells(node); + int np = pna + 5; + + pr_info("PCI host bridge %s ranges:\n", node->full_name); + ranges = of_get_property(node, "ranges", &rlen); + if (ranges == NULL) + return; + hose->of_node = node; + + while ((rlen -= np * 4) >= 0) { + u32 pci_space; + struct resource *res = NULL; + u64 addr, size; + + pci_space = be32_to_cpup(&ranges[0]); + addr = of_translate_address(node, ranges + 3); + size = of_read_number(ranges + pna + 3, 2); + ranges += np; + switch ((pci_space >> 24) & 0x3) { + case 1: /* PCI IO space */ + pr_info(" IO 0x%016llx..0x%016llx\n", + addr, addr + size - 1); + hose->io_map_base = + (unsigned long)ioremap(addr, size); + res = hose->io_resource; + res->flags = IORESOURCE_IO; + break; + case 2: /* PCI Memory space */ + case 3: /* PCI 64 bits Memory space */ + pr_info(" MEM 0x%016llx..0x%016llx\n", + addr, addr + size - 1); + res = hose->mem_resource; + res->flags = IORESOURCE_MEM; + break; + } + if (res != NULL) { + res->start = addr; + res->name = node->full_name; + res->end = res->start + size - 1; + res->parent = NULL; + res->sibling = NULL; + res->child = NULL; + } + } +} +#endif + static DEFINE_MUTEX(pci_scan_mutex); void __devinit register_pci_controller(struct pci_controller *hose) -- 1.7.9.1 From blogic@openwrt.org Fri May 4 12:56:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 12:56:57 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:34022 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903663Ab2EDK4q (ORCPT ); Fri, 4 May 2012 12:56:46 +0200 Message-ID: <4FA3B596.3050106@openwrt.org> Date: Fri, 04 May 2012 12:55:18 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: David Daney CC: Bjorn Helgaas , Ralf Baechle , Grant Likely , linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org Subject: Re: [PATCH] OF: PCI: const usage needed by MIPS References: <1335808019-24502-1-git-send-email-blogic@openwrt.org> <4F9ED1DC.3050007@gmail.com> <4F9FE4F6.5070909@openwrt.org> <4FA32E47.7020406@gmail.com> In-Reply-To: <4FA32E47.7020406@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33138 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 941 Lines: 43 Hi David, > The problem is when you start declaring function pointers in various > ops vectors. > > Consider: > > void (*foo)(const struct pci_dev *) > void (*bar)(struct pci_dev *) > > foo and bar are not type compatible, and you will get compiler > warnings if you use one where the other is expected. > > So the question is: Are we ever going to the address of any of the > functions that are being modified? If so, we have created a problem. > i could not find any place in the code where this happens, which does not mean that there are none. >> Similar reasoning applies to of_irq_map_pci(). >> >> So I'm fine with this. You sent it to Grant, so I'll assume he'll >> merge it unless I hear otherwise. >> >> Acked-by: Bjorn Helgaas >> > Thanks for the Ack, i hope this patch gets accepted as is. I am simply missing the overview of the pci subsystem to evaluate if this can cause regressions. John From sshtylyov@mvista.com Fri May 4 13:17:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 13:17:28 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:54757 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903664Ab2EDLRW (ORCPT ); Fri, 4 May 2012 13:17:22 +0200 Received: by lbbgg6 with SMTP id gg6so2439395lbb.36 for ; Fri, 04 May 2012 04:17:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=ba75U3UMf0M0K0fqnzW9S5Fxge2qW+wAvYB3wpaXoe0=; b=OujX8dyG8IuGPrS/aDHkDSTbemZLCQDbl8v00R9771E2kwGlt2FZpBvYS8B5SeQann KjFKGrVJMN6Q92fBdyvDR+SiBGf3xgDrj3X9srxVJtKE31IoGHb4H5k40hUsF/+nL+0T hHSyDh9o0HCWVTBZKGQzWGoGjsIh2pPOTYneTsQ1FLyMDeHf/D8h8QrYLAwc45PSHDVA 8UbVpQ2V3Lnd57SLDNogr82smk4m3+1wdIr8uK52w9LJMXFoky5LJQMEF3I6mI3WrUv0 os8kSuA6niyjzuskGz4No1rcph6ZTGbkAs19sHZXhr7Jo+Gy2Ap3QH9PWLnj49TxX/Za /0NQ== Received: by 10.112.86.101 with SMTP id o5mr2738744lbz.1.1336130236588; Fri, 04 May 2012 04:17:16 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-80-122.pppoe.mtu-net.ru. [91.79.80.122]) by mx.google.com with ESMTPS id o9sm10583668lbm.14.2012.05.04.04.17.13 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 May 2012 04:17:14 -0700 (PDT) Message-ID: <4FA3BAA6.5060200@mvista.com> Date: Fri, 04 May 2012 15:16:54 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: Matt Turner CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] mips: set ST0_MX flag for MDMX References: <1336084845-28995-1-git-send-email-mattst88@gmail.com> In-Reply-To: <1336084845-28995-1-git-send-email-mattst88@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkUDAQARdnwS7eDQog0sjDw4W5jHeZdukclQ6gZH4JrMyyn29TmBwamsMwkcanwiarJ7Q6Z X-archive-position: 33139 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 736 Lines: 25 Hello. On 04-05-2012 2:40, Matt Turner wrote: > As the comment in commit 3301edcb Please also specify that commit's summary in parens. > says, DSP and MDMX share the same > config flag bit. > Without this set, MDMX instructions cause Illegal instruction errors. > Signed-off-by: Matt Turner > --- > Is MDMX implemented by anything other than some Broadcom CPUs? Is it > totally replaced by DSP? > I had a terrible time finding any documentation on it (which is annoying > because Volume IV-b covering MDMX is referenced by all the MIPS64 documents.) > but finally found a copy here: www.enlight.ru/docs/cpu/risc/mips/MDMXspec.pdf > If it's dead, it's too bad because it's a pretty cool ISA. WBR, Sergei From blogic@openwrt.org Fri May 4 14:20:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:20:14 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48613 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903664Ab2EDMUJ (ORCPT ); Fri, 4 May 2012 14:20:09 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 01/14] MIPS: lantiq: drop mips_machine support Date: Fri, 4 May 2012 14:18:26 +0200 Message-Id: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33140 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 17972 Lines: 692 Before we are able to add OF support, we really want to drop all the bloat needed to register all the platform devices. Signed-off-by: John Crispin --- arch/mips/Kconfig | 1 - arch/mips/lantiq/Kconfig | 2 - arch/mips/lantiq/Makefile | 2 +- arch/mips/lantiq/devices.c | 120 -------------------------------- arch/mips/lantiq/devices.h | 23 ------ arch/mips/lantiq/machtypes.h | 20 ----- arch/mips/lantiq/prom.h | 1 - arch/mips/lantiq/setup.c | 23 ------ arch/mips/lantiq/xway/Kconfig | 23 ------ arch/mips/lantiq/xway/Makefile | 9 +-- arch/mips/lantiq/xway/devices.c | 119 ------------------------------- arch/mips/lantiq/xway/devices.h | 20 ----- arch/mips/lantiq/xway/mach-easy50601.c | 57 --------------- arch/mips/lantiq/xway/mach-easy50712.c | 74 -------------------- arch/mips/lantiq/xway/setup-ase.c | 19 ----- arch/mips/lantiq/xway/setup-xway.c | 20 ----- 16 files changed, 4 insertions(+), 529 deletions(-) delete mode 100644 arch/mips/lantiq/devices.c delete mode 100644 arch/mips/lantiq/devices.h delete mode 100644 arch/mips/lantiq/machtypes.h delete mode 100644 arch/mips/lantiq/xway/Kconfig delete mode 100644 arch/mips/lantiq/xway/devices.c delete mode 100644 arch/mips/lantiq/xway/devices.h delete mode 100644 arch/mips/lantiq/xway/mach-easy50601.c delete mode 100644 arch/mips/lantiq/xway/mach-easy50712.c delete mode 100644 arch/mips/lantiq/xway/setup-ase.c delete mode 100644 arch/mips/lantiq/xway/setup-xway.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ce30e2f..7c85562 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -229,7 +229,6 @@ config LANTIQ select SWAP_IO_SPACE select BOOT_RAW select HAVE_CLK - select MIPS_MACHINE config LASAT bool "LASAT Networks platforms" diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index 3fccf21..2780461 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -18,6 +18,4 @@ config SOC_XWAY select HW_HAS_PCI endchoice -source "arch/mips/lantiq/xway/Kconfig" - endif diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index e5dae0e..a268391 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -4,7 +4,7 @@ # under the terms of the GNU General Public License version 2 as published # by the Free Software Foundation. -obj-y := irq.o setup.o clk.o prom.o devices.o +obj-y := irq.o setup.o clk.o prom.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c deleted file mode 100644 index de1cb2b..0000000 --- a/arch/mips/lantiq/devices.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include "devices.h" - -/* nor flash */ -static struct resource ltq_nor_resource = { - .name = "nor", - .start = LTQ_FLASH_START, - .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ltq_nor = { - .name = "ltq_nor", - .resource = <q_nor_resource, - .num_resources = 1, -}; - -void __init ltq_register_nor(struct physmap_flash_data *data) -{ - ltq_nor.dev.platform_data = data; - platform_device_register(<q_nor); -} - -/* watchdog */ -static struct resource ltq_wdt_resource = { - .name = "watchdog", - .start = LTQ_WDT_BASE_ADDR, - .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -void __init ltq_register_wdt(void) -{ - platform_device_register_simple("ltq_wdt", 0, <q_wdt_resource, 1); -} - -/* asc ports */ -static struct resource ltq_asc0_resources[] = { - { - .name = "asc0", - .start = LTQ_ASC0_BASE_ADDR, - .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - IRQ_RES(tx, LTQ_ASC_TIR(0)), - IRQ_RES(rx, LTQ_ASC_RIR(0)), - IRQ_RES(err, LTQ_ASC_EIR(0)), -}; - -static struct resource ltq_asc1_resources[] = { - { - .name = "asc1", - .start = LTQ_ASC1_BASE_ADDR, - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - IRQ_RES(tx, LTQ_ASC_TIR(1)), - IRQ_RES(rx, LTQ_ASC_RIR(1)), - IRQ_RES(err, LTQ_ASC_EIR(1)), -}; - -void __init ltq_register_asc(int port) -{ - switch (port) { - case 0: - platform_device_register_simple("ltq_asc", 0, - ltq_asc0_resources, ARRAY_SIZE(ltq_asc0_resources)); - break; - case 1: - platform_device_register_simple("ltq_asc", 1, - ltq_asc1_resources, ARRAY_SIZE(ltq_asc1_resources)); - break; - default: - break; - } -} - -#ifdef CONFIG_PCI -/* pci */ -static struct platform_device ltq_pci = { - .name = "ltq_pci", - .num_resources = 0, -}; - -void __init ltq_register_pci(struct ltq_pci_data *data) -{ - ltq_pci.dev.platform_data = data; - platform_device_register(<q_pci); -} -#else -void __init ltq_register_pci(struct ltq_pci_data *data) -{ - pr_err("kernel is compiled without PCI support\n"); -} -#endif diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h deleted file mode 100644 index 2947bb1..0000000 --- a/arch/mips/lantiq/devices.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#ifndef _LTQ_DEVICES_H__ -#define _LTQ_DEVICES_H__ - -#include -#include - -#define IRQ_RES(resname, irq) \ - {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} - -extern void ltq_register_nor(struct physmap_flash_data *data); -extern void ltq_register_wdt(void); -extern void ltq_register_asc(int port); -extern void ltq_register_pci(struct ltq_pci_data *data); - -#endif diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h deleted file mode 100644 index 7e01b8c..0000000 --- a/arch/mips/lantiq/machtypes.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#ifndef _LANTIQ_MACH_H__ -#define _LANTIQ_MACH_H__ - -#include - -enum lantiq_mach_type { - LTQ_MACH_GENERIC = 0, - LTQ_MACH_EASY50712, /* Danube evaluation board */ - LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ -}; - -#endif diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h index 90070a5..f7c2a79 100644 --- a/arch/mips/lantiq/prom.h +++ b/arch/mips/lantiq/prom.h @@ -24,7 +24,6 @@ struct ltq_soc_info { }; extern void ltq_soc_detect(struct ltq_soc_info *i); -extern void ltq_soc_setup(void); extern void ltq_soc_init(void); #endif diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c index 1ff6c9d..f1c605a 100644 --- a/arch/mips/lantiq/setup.c +++ b/arch/mips/lantiq/setup.c @@ -14,8 +14,6 @@ #include -#include "machtypes.h" -#include "devices.h" #include "prom.h" void __init plat_mem_setup(void) @@ -43,24 +41,3 @@ void __init plat_mem_setup(void) memsize *= 1024 * 1024; add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); } - -static int __init -lantiq_setup(void) -{ - ltq_soc_setup(); - mips_machine_setup(); - return 0; -} - -arch_initcall(lantiq_setup); - -static void __init -lantiq_generic_init(void) -{ - /* Nothing to do */ -} - -MIPS_MACHINE(LTQ_MACH_GENERIC, - "Generic", - "Generic Lantiq based board", - lantiq_generic_init); diff --git a/arch/mips/lantiq/xway/Kconfig b/arch/mips/lantiq/xway/Kconfig deleted file mode 100644 index 2b857de..0000000 --- a/arch/mips/lantiq/xway/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if SOC_XWAY - -menu "MIPS Machine" - -config LANTIQ_MACH_EASY50712 - bool "Easy50712 - Danube" - default y - -endmenu - -endif - -if SOC_AMAZON_SE - -menu "MIPS Machine" - -config LANTIQ_MACH_EASY50601 - bool "Easy50601 - Amazon SE" - default y - -endmenu - -endif diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 42d5fda..7a6c30f 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,7 +1,4 @@ -obj-y := prom.o pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o +obj-y := prom.o pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o dma.o -obj-$(CONFIG_SOC_XWAY) += clk-xway.o setup-xway.o -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o setup-ase.o - -obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o -obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o +obj-$(CONFIG_SOC_XWAY) += clk-xway.o +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c deleted file mode 100644 index d614aa7..0000000 --- a/arch/mips/lantiq/xway/devices.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "devices.h" - -/* gpio */ -static struct resource ltq_gpio_resource[] = { - { - .name = "gpio0", - .start = LTQ_GPIO0_BASE_ADDR, - .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "gpio1", - .start = LTQ_GPIO1_BASE_ADDR, - .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "gpio2", - .start = LTQ_GPIO2_BASE_ADDR, - .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - } -}; - -void __init ltq_register_gpio(void) -{ - platform_device_register_simple("ltq_gpio", 0, - <q_gpio_resource[0], 1); - platform_device_register_simple("ltq_gpio", 1, - <q_gpio_resource[1], 1); - - /* AR9 and VR9 have an extra gpio block */ - if (ltq_is_ar9() || ltq_is_vr9()) { - platform_device_register_simple("ltq_gpio", 2, - <q_gpio_resource[2], 1); - } -} - -/* serial to parallel conversion */ -static struct resource ltq_stp_resource = { - .name = "stp", - .start = LTQ_STP_BASE_ADDR, - .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -void __init ltq_register_gpio_stp(void) -{ - platform_device_register_simple("ltq_stp", 0, <q_stp_resource, 1); -} - -/* asc ports - amazon se has its own serial mapping */ -static struct resource ltq_ase_asc_resources[] = { - { - .name = "asc0", - .start = LTQ_ASC1_BASE_ADDR, - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - IRQ_RES(tx, LTQ_ASC_ASE_TIR), - IRQ_RES(rx, LTQ_ASC_ASE_RIR), - IRQ_RES(err, LTQ_ASC_ASE_EIR), -}; - -void __init ltq_register_ase_asc(void) -{ - platform_device_register_simple("ltq_asc", 0, - ltq_ase_asc_resources, ARRAY_SIZE(ltq_ase_asc_resources)); -} - -/* ethernet */ -static struct resource ltq_etop_resources = { - .name = "etop", - .start = LTQ_ETOP_BASE_ADDR, - .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ltq_etop = { - .name = "ltq_etop", - .resource = <q_etop_resources, - .num_resources = 1, -}; - -void __init -ltq_register_etop(struct ltq_eth_data *eth) -{ - if (eth) { - ltq_etop.dev.platform_data = eth; - platform_device_register(<q_etop); - } -} diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h deleted file mode 100644 index e904934..0000000 --- a/arch/mips/lantiq/xway/devices.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#ifndef _LTQ_DEVICES_XWAY_H__ -#define _LTQ_DEVICES_XWAY_H__ - -#include "../devices.h" -#include - -extern void ltq_register_gpio(void); -extern void ltq_register_gpio_stp(void); -extern void ltq_register_ase_asc(void); -extern void ltq_register_etop(struct ltq_eth_data *eth); - -#endif diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c deleted file mode 100644 index d5aaf63..0000000 --- a/arch/mips/lantiq/xway/mach-easy50601.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "../machtypes.h" -#include "devices.h" - -static struct mtd_partition easy50601_partitions[] = { - { - .name = "uboot", - .offset = 0x0, - .size = 0x10000, - }, - { - .name = "uboot_env", - .offset = 0x10000, - .size = 0x10000, - }, - { - .name = "linux", - .offset = 0x20000, - .size = 0xE0000, - }, - { - .name = "rootfs", - .offset = 0x100000, - .size = 0x300000, - }, -}; - -static struct physmap_flash_data easy50601_flash_data = { - .nr_parts = ARRAY_SIZE(easy50601_partitions), - .parts = easy50601_partitions, -}; - -static void __init easy50601_init(void) -{ - ltq_register_nor(&easy50601_flash_data); -} - -MIPS_MACHINE(LTQ_MACH_EASY50601, - "EASY50601", - "EASY50601 Eval Board", - easy50601_init); diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c deleted file mode 100644 index ea5027b..0000000 --- a/arch/mips/lantiq/xway/mach-easy50712.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "../machtypes.h" -#include "devices.h" - -static struct mtd_partition easy50712_partitions[] = { - { - .name = "uboot", - .offset = 0x0, - .size = 0x10000, - }, - { - .name = "uboot_env", - .offset = 0x10000, - .size = 0x10000, - }, - { - .name = "linux", - .offset = 0x20000, - .size = 0xe0000, - }, - { - .name = "rootfs", - .offset = 0x100000, - .size = 0x300000, - }, -}; - -static struct physmap_flash_data easy50712_flash_data = { - .nr_parts = ARRAY_SIZE(easy50712_partitions), - .parts = easy50712_partitions, -}; - -static struct ltq_pci_data ltq_pci_data = { - .clock = PCI_CLOCK_INT, - .gpio = PCI_GNT1 | PCI_REQ1, - .irq = { - [14] = INT_NUM_IM0_IRL0 + 22, - }, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_MII, -}; - -static void __init easy50712_init(void) -{ - ltq_register_gpio_stp(); - ltq_register_nor(&easy50712_flash_data); - ltq_register_pci(<q_pci_data); - ltq_register_etop(<q_eth_data); -} - -MIPS_MACHINE(LTQ_MACH_EASY50712, - "EASY50712", - "EASY50712 Eval Board", - easy50712_init); diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c deleted file mode 100644 index f6f3267..0000000 --- a/arch/mips/lantiq/xway/setup-ase.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin - */ - -#include - -#include "../prom.h" -#include "devices.h" - -void __init ltq_soc_setup(void) -{ - ltq_register_ase_asc(); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c deleted file mode 100644 index c292f64..0000000 --- a/arch/mips/lantiq/xway/setup-xway.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin - */ - -#include - -#include "../prom.h" -#include "devices.h" - -void __init ltq_soc_setup(void) -{ - ltq_register_asc(0); - ltq_register_asc(1); - ltq_register_gpio(); - ltq_register_wdt(); -} -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:20:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:20:45 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48615 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903665Ab2EDMUK (ORCPT ); Fri, 4 May 2012 14:20:10 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , devicetree-discuss@lists.ozlabs.org Subject: [PATCH 02/14] OF: MIPS: lantiq: implement OF support Date: Fri, 4 May 2012 14:18:27 +0200 Message-Id: <1336133919-26525-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33141 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 13653 Lines: 527 Activate USE_OF, add a sample DTS file and convert the core soc code to OF. Signed-off-by: John Crispin Cc: devicetree-discuss@lists.ozlabs.org --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. arch/mips/Kconfig | 1 + arch/mips/lantiq/Kconfig | 9 +++ arch/mips/lantiq/Makefile | 4 +- arch/mips/lantiq/dts/Makefile | 4 + arch/mips/lantiq/dts/danube.dtsi | 105 +++++++++++++++++++++++++++++++++ arch/mips/lantiq/dts/easy50712.dts | 113 ++++++++++++++++++++++++++++++++++++ arch/mips/lantiq/prom.c | 57 ++++++++++++++---- arch/mips/lantiq/prom.h | 2 + arch/mips/lantiq/setup.c | 43 -------------- arch/mips/lantiq/xway/ebu.c | 4 - arch/mips/lantiq/xway/reset.c | 29 ++++----- 11 files changed, 294 insertions(+), 77 deletions(-) create mode 100644 arch/mips/lantiq/dts/Makefile create mode 100644 arch/mips/lantiq/dts/danube.dtsi create mode 100644 arch/mips/lantiq/dts/easy50712.dts delete mode 100644 arch/mips/lantiq/setup.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7c85562..fbb5639 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -229,6 +229,7 @@ config LANTIQ select SWAP_IO_SPACE select BOOT_RAW select HAVE_CLK + select USE_OF config LASAT bool "LASAT Networks platforms" diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index 2780461..9485fe5 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -18,4 +18,13 @@ config SOC_XWAY select HW_HAS_PCI endchoice + +choice + prompt "Devicetree" + +config DT_EASY50712 + bool "Easy50712" + depends on SOC_XWAY +endchoice + endif diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index a268391..16f1c75 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -4,7 +4,9 @@ # under the terms of the GNU General Public License version 2 as published # by the Free Software Foundation. -obj-y := irq.o setup.o clk.o prom.o +obj-y := irq.o clk.o prom.o + +obj-y += dts/ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/lantiq/dts/Makefile b/arch/mips/lantiq/dts/Makefile new file mode 100644 index 0000000..674fca4 --- /dev/null +++ b/arch/mips/lantiq/dts/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_DT_EASY50712) := easy50712.dtb.o + +$(obj)/%.dtb: $(obj)/%.dts + $(call if_changed,dtc) diff --git a/arch/mips/lantiq/dts/danube.dtsi b/arch/mips/lantiq/dts/danube.dtsi new file mode 100644 index 0000000..3a4520f --- /dev/null +++ b/arch/mips/lantiq/dts/danube.dtsi @@ -0,0 +1,105 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,danube"; + + cpus { + cpu@0 { + compatible = "mips,mips24Kc"; + }; + }; + + biu@1F800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1F800000 0x800000>; + ranges = <0x0 0x1F800000 0x7FFFFF>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + reg = <0x80200 0x120>; + }; + + watchdog@803F0 { + compatible = "lantiq,wdt"; + reg = <0x803F0 0x10>; + }; + }; + + sram@1F000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram"; + reg = <0x1F000000 0x800000>; + ranges = <0x0 0x1F000000 0x7FFFFF>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + #clock-cells = <1>; + }; + + rcu0: rcu@203000 { + compatible = "lantiq,rcu-xway"; + reg = <0x203000 0x1000>; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xEEFFFFF>; + reg = <0x10000000 0xEF00000>; + + gptu@E100A00 { + compatible = "lantiq,gptu-xway"; + reg = <0xE100A00 0x100>; + }; + + serial@E100C00 { + compatible = "lantiq,asc"; + reg = <0xE100C00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; + }; + + dma0: dma@E104100 { + compatible = "lantiq,dma-xway"; + reg = <0xE104100 0x800>; + }; + + ebu0: ebu@E105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xE105300 0x100>; + }; + + pci0: pci@E105400 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xE105400 0x400>; /* pci bridge */ + }; + }; +}; diff --git a/arch/mips/lantiq/dts/easy50712.dts b/arch/mips/lantiq/dts/easy50712.dts new file mode 100644 index 0000000..68c1731 --- /dev/null +++ b/arch/mips/lantiq/dts/easy50712.dts @@ -0,0 +1,113 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; /* 64 KB */ + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; /* 64 KB */ + }; + + partition@20000 { + label = "linux"; + reg = <0x20000 0x3d0000>; + }; + + partition@400000 { + label = "rootfs"; + reg = <0x400000 0x400000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xway"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + pci { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io4", "io5", "io6"; /* stp */ + lantiq,open-drain; + lantiq,pull = <0>; + }; + }; + }; + + etop@E180000 { + compatible = "lantiq,etop-xway"; + reg = <0xE180000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <73 78>; + phy-mode = "rmii"; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + stp0: stp@E100BB0 { + #gpio-cells = <2>; + compatible = "lantiq,gpio-stp-xway"; + gpio-controller; + reg = <0xE100BB0 0x40>; + + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; + }; + + pci@E105400 { + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29 + >; + gpios-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + + }; +}; diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index cd56892..413ed53 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -8,6 +8,7 @@ #include #include +#include #include #include @@ -16,13 +17,15 @@ #include "prom.h" #include "clk.h" -static struct ltq_soc_info soc_info; +/* access to the ebu needs to be locked between different drivers */ +DEFINE_SPINLOCK(ebu_lock); +EXPORT_SYMBOL_GPL(ebu_lock); -unsigned int ltq_get_cpu_ver(void) -{ - return soc_info.rev; -} -EXPORT_SYMBOL(ltq_get_cpu_ver); +/* + * this struct is filled by the soc specific detection code and holds + * information about the specific soc type, revision and name + */ +static struct ltq_soc_info soc_info; unsigned int ltq_get_soc_type(void) { @@ -57,16 +60,28 @@ static void __init prom_init_cmdline(void) } } -void __init prom_init(void) +void __init plat_mem_setup(void) { - struct clk *clk; + ioport_resource.start = IOPORT_RESOURCE_START; + ioport_resource.end = IOPORT_RESOURCE_END; + iomem_resource.start = IOMEM_RESOURCE_START; + iomem_resource.end = IOMEM_RESOURCE_END; + + set_io_port_base((unsigned long) KSEG1); + + /* + * Load the builtin devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + __dt_setup_arch(&__dtb_start); +} +void __init prom_init(void) +{ + /* call the soc specific detetcion code and get it to fill soc_info */ ltq_soc_detect(&soc_info); - clk_init(); - clk = clk_get(0, "cpu"); - snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d", - soc_info.name, soc_info.rev); - clk_put(clk); + snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", + soc_info.name, soc_info.rev_type); soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; pr_info("SoC: %s\n", soc_info.sys_type); prom_init_cmdline(); @@ -76,3 +91,19 @@ void __init prom_init(void) panic("failed to register_vsmp_smp_ops()"); #endif } + +int __init plat_of_setup(void) +{ + static struct of_device_id of_ids[3]; + + if (!of_have_populated_dt()) + panic("device tree not present"); + + strncpy(of_ids[0].compatible, soc_info.compatible, + sizeof(of_ids[0].compatible)); + strncpy(of_ids[1].compatible, "simple-bus", + sizeof(of_ids[1].compatible)); + return of_platform_bus_probe(NULL, of_ids, NULL); +} + +arch_initcall(plat_of_setup); diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h index f7c2a79..a3fa1a2 100644 --- a/arch/mips/lantiq/prom.h +++ b/arch/mips/lantiq/prom.h @@ -26,4 +26,6 @@ struct ltq_soc_info { extern void ltq_soc_detect(struct ltq_soc_info *i); extern void ltq_soc_init(void); +extern struct boot_param_header __dtb_start; + #endif diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c deleted file mode 100644 index f1c605a..0000000 --- a/arch/mips/lantiq/setup.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include - -#include - -#include "prom.h" - -void __init plat_mem_setup(void) -{ - /* assume 16M as default incase uboot fails to pass proper ramsize */ - unsigned long memsize = 16; - char **envp = (char **) KSEG1ADDR(fw_arg2); - - ioport_resource.start = IOPORT_RESOURCE_START; - ioport_resource.end = IOPORT_RESOURCE_END; - iomem_resource.start = IOMEM_RESOURCE_START; - iomem_resource.end = IOMEM_RESOURCE_END; - - set_io_port_base((unsigned long) KSEG1); - - while (*envp) { - char *e = (char *)KSEG1ADDR(*envp); - if (!strncmp(e, "memsize=", 8)) { - e += 8; - if (strict_strtoul(e, 0, &memsize)) - pr_warn("bad memsize specified\n"); - } - envp++; - } - memsize *= 1024 * 1024; - add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); -} diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c index 862e3e8..419b47b 100644 --- a/arch/mips/lantiq/xway/ebu.c +++ b/arch/mips/lantiq/xway/ebu.c @@ -14,10 +14,6 @@ #include -/* all access to the ebu must be locked */ -DEFINE_SPINLOCK(ebu_lock); -EXPORT_SYMBOL_GPL(ebu_lock); - static struct resource ltq_ebu_resource = { .name = "ebu", .start = LTQ_EBU_BASE_ADDR, diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c index 3327211..22c55f7 100644 --- a/arch/mips/lantiq/xway/reset.c +++ b/arch/mips/lantiq/xway/reset.c @@ -37,13 +37,6 @@ #define RCU_BOOT_SEL_SHIFT 26 #define RCU_BOOT_SEL_MASK 0x7 -static struct resource ltq_rcu_resource = { - .name = "rcu", - .start = LTQ_RCU_BASE_ADDR, - .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - /* remapped base addr of the reset control unit */ static void __iomem *ltq_rcu_membase; @@ -91,17 +84,21 @@ static void ltq_machine_power_off(void) static int __init mips_reboot_setup(void) { - /* insert and request the memory region */ - if (insert_resource(&iomem_resource, <q_rcu_resource) < 0) - panic("Failed to insert rcu memory"); + struct resource res; + struct device_node *np = + of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway"); + + /* check if all the reset register range is available */ + if (!np) + panic("Failed to load reset resources from devicetree"); + + if (of_address_to_resource(np, 0, &res)) + panic("Failed to get rcu memory range"); - if (request_mem_region(ltq_rcu_resource.start, - resource_size(<q_rcu_resource), "rcu") < 0) - panic("Failed to request rcu memory"); + if (request_mem_region(res.start, resource_size(&res), res.name) < 0) + pr_err("Failed to request rcu memory"); - /* remap rcu register range */ - ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, - resource_size(<q_rcu_resource)); + ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res)); if (!ltq_rcu_membase) panic("Failed to remap core memory"); -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:20:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:21:08 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48617 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903667Ab2EDMUK (ORCPT ); Fri, 4 May 2012 14:20:10 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , devicetree-discuss@lists.ozlabs.org Subject: [PATCH 03/14] OF: MIPS: lantiq: implement irq_domain support Date: Fri, 4 May 2012 14:18:28 +0200 Message-Id: <1336133919-26525-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33142 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6965 Lines: 229 Add support for irq_domain on lantiq socs. The conversion is straight forward as the ICU found inside the socs allows the usage of irq_domain_add_linear. Signed-off-by: John Crispin Cc: devicetree-discuss@lists.ozlabs.org --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. arch/mips/lantiq/irq.c | 120 +++++++++++++++++++++++++++--------------------- 1 files changed, 68 insertions(+), 52 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index d227be1..170e6cb 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -9,6 +9,11 @@ #include #include +#include +#include +#include +#include +#include #include #include @@ -16,7 +21,7 @@ #include #include -/* register definitions */ +/* register definitions - internal irqs */ #define LTQ_ICU_IM0_ISR 0x0000 #define LTQ_ICU_IM0_IER 0x0008 #define LTQ_ICU_IM0_IOSR 0x0010 @@ -25,6 +30,7 @@ #define LTQ_ICU_IM1_ISR 0x0028 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) +/* register definitions - external irqs */ #define LTQ_EIU_EXIN_C 0x0000 #define LTQ_EIU_EXIN_INIC 0x0004 #define LTQ_EIU_EXIN_INEN 0x000C @@ -37,13 +43,13 @@ #define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1) #define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2) #define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30) - #define MAX_EIU 6 /* the performance counter */ #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) -/* irqs generated by device attached to the EBU need to be acked in +/* + * irqs generated by devices attached to the EBU need to be acked in * a special manner */ #define LTQ_ICU_EBU_IRQ 22 @@ -71,20 +77,6 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = { LTQ_EIU_IR5, }; -static struct resource ltq_icu_resource = { - .name = "icu", - .start = LTQ_ICU_BASE_ADDR, - .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct resource ltq_eiu_resource = { - .name = "eiu", - .start = LTQ_EIU_BASE_ADDR, - .end = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - static void __iomem *ltq_icu_membase; static void __iomem *ltq_eiu_membase; @@ -199,14 +191,15 @@ static void ltq_hw_irqdispatch(int module) if (irq == 0) return; - /* silicon bug causes only the msb set to 1 to be valid. all + /* + * silicon bug causes only the msb set to 1 to be valid. all * other bits might be bogus */ irq = __fls(irq); do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); /* if this is a EBU irq, we need to ack it or get a deadlock */ - if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) + if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, LTQ_EBU_PCC_ISTAT); } @@ -290,38 +283,62 @@ out: return; } +static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + if (((irq == LTQ_EIU_IR0) || (irq == LTQ_EIU_IR1) || + (irq == LTQ_EIU_IR2)) && ltq_eiu_membase) + irq_set_chip_and_handler(irq, <q_eiu_type, handle_level_irq); + /* EIU3-5 only exist on ar9 and vr9 */ + else if (((irq == LTQ_EIU_IR3) || (irq == LTQ_EIU_IR4) || + (irq == LTQ_EIU_IR5)) && + (of_machine_is_compatible("lantiq,ar9") || + of_machine_is_compatible("lantiq,vr9")) && + ltq_eiu_membase) + irq_set_chip_and_handler(irq, <q_eiu_type, handle_level_irq); + else + irq_set_chip_and_handler(irq, <q_irq_type, handle_level_irq); + + return 0; +} + +static const struct irq_domain_ops irq_domain_ops = { + .xlate = irq_domain_xlate_onetwocell, + .map = icu_map, +}; + static struct irqaction cascade = { .handler = no_action, .name = "cascade", }; -void __init arch_init_irq(void) +int __init icu_of_init(struct device_node *node, struct device_node *parent) { + struct device_node *eiu_node; + struct resource res; int i; - if (insert_resource(&iomem_resource, <q_icu_resource) < 0) - panic("Failed to insert icu memory"); + if (of_address_to_resource(node, 0, &res)) + panic("Failed to get icu memory range"); - if (request_mem_region(ltq_icu_resource.start, - resource_size(<q_icu_resource), "icu") < 0) - panic("Failed to request icu memory"); + if (request_mem_region(res.start, resource_size(&res), res.name) < 0) + pr_err("Failed to request icu memory"); - ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, - resource_size(<q_icu_resource)); + ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res)); if (!ltq_icu_membase) panic("Failed to remap icu memory"); - if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) - panic("Failed to insert eiu memory"); - - if (request_mem_region(ltq_eiu_resource.start, - resource_size(<q_eiu_resource), "eiu") < 0) - panic("Failed to request eiu memory"); - - ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, - resource_size(<q_eiu_resource)); - if (!ltq_eiu_membase) - panic("Failed to remap eiu memory"); + /* the external interrupts are optional and xway only */ + eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu"); + if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) { + if (request_mem_region(res.start, resource_size(&res), + res.name) < 0) + pr_err("Failed to request eiu memory"); + + ltq_eiu_membase = ioremap_nocache(res.start, + resource_size(&res)); + if (!ltq_eiu_membase) + panic("Failed to remap eiu memory"); + } /* turn off all irqs by default */ for (i = 0; i < 5; i++) { @@ -346,20 +363,8 @@ void __init arch_init_irq(void) set_vi_handler(7, ltq_hw5_irqdispatch); } - for (i = INT_NUM_IRQ0; - i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) - if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || - (i == LTQ_EIU_IR2)) - irq_set_chip_and_handler(i, <q_eiu_type, - handle_level_irq); - /* EIU3-5 only exist on ar9 and vr9 */ - else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) || - (i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9())) - irq_set_chip_and_handler(i, <q_eiu_type, - handle_level_irq); - else - irq_set_chip_and_handler(i, <q_irq_type, - handle_level_irq); + irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET, + &irq_domain_ops, 0); #if defined(CONFIG_MIPS_MT_SMP) if (cpu_has_vint) { @@ -382,9 +387,20 @@ void __init arch_init_irq(void) /* tell oprofile which irq to use */ cp0_perfcount_irq = LTQ_PERF_IRQ; + return 0; } unsigned int __cpuinit get_c0_compare_int(void) { return CP0_LEGACY_COMPARE_IRQ; } + +static struct of_device_id __initdata of_irq_ids[] = { + { .compatible = "lantiq,icu", .data = icu_of_init }, + {}, +}; + +void __init arch_init_irq(void) +{ + of_irq_init(of_irq_ids); +} -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:20:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:21:35 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48622 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903678Ab2EDMUN (ORCPT ); Fri, 4 May 2012 14:20:13 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 05/14] MIPS: lantiq: implement support for clkdev api Date: Fri, 4 May 2012 14:18:30 +0200 Message-Id: <1336133919-26525-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33143 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35449 Lines: 1338 This code unifies all clock generation and gating code into one file. All drivers will now be able to request their clocks via their device. This patch also adds support for the clockout feature, which allows clock generation on external pins. Support for COMMON_CLK will be provided in the next series. Signed-off-by: John Crispin --- arch/mips/Kconfig | 3 +- arch/mips/include/asm/mach-lantiq/lantiq.h | 27 +- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 5 + arch/mips/lantiq/clk.c | 140 ++++---- arch/mips/lantiq/clk.h | 67 ++++- arch/mips/lantiq/xway/Makefile | 5 +- arch/mips/lantiq/xway/clk-ase.c | 48 --- arch/mips/lantiq/xway/clk-xway.c | 223 ------------ arch/mips/lantiq/xway/clk.c | 151 ++++++++ arch/mips/lantiq/xway/ebu.c | 48 --- arch/mips/lantiq/xway/pmu.c | 69 ---- arch/mips/lantiq/xway/sysctrl.c | 364 ++++++++++++++++++++ 12 files changed, 671 insertions(+), 479 deletions(-) delete mode 100644 arch/mips/lantiq/xway/clk-ase.c delete mode 100644 arch/mips/lantiq/xway/clk-xway.c create mode 100644 arch/mips/lantiq/xway/clk.c delete mode 100644 arch/mips/lantiq/xway/ebu.c delete mode 100644 arch/mips/lantiq/xway/pmu.c create mode 100644 arch/mips/lantiq/xway/sysctrl.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 00a0482..8ba19da 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -229,7 +229,8 @@ config LANTIQ select ARCH_REQUIRE_GPIOLIB select SWAP_IO_SPACE select BOOT_RAW - select HAVE_CLK + select HAVE_MACH_CLKDEV + select CLKDEV_LOOKUP select USE_OF config LASAT diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index 7a90190..c955e8d 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -9,6 +9,8 @@ #define _LANTIQ_H__ #include +#include +#include /* generic reg access functions */ #define ltq_r32(reg) __raw_readl(reg) @@ -21,26 +23,13 @@ /* register access macros for EBU and CGU */ #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) -#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) -#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) - +#define ltq_ebu_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_ebu_membase + (z)) extern __iomem void *ltq_ebu_membase; -extern __iomem void *ltq_cgu_membase; extern unsigned int ltq_get_cpu_ver(void); extern unsigned int ltq_get_soc_type(void); -/* clock speeds */ -#define CLOCK_60M 60000000 -#define CLOCK_83M 83333333 -#define CLOCK_111M 111111111 -#define CLOCK_133M 133333333 -#define CLOCK_167M 166666667 -#define CLOCK_200M 200000000 -#define CLOCK_266M 266666666 -#define CLOCK_333M 333333333 -#define CLOCK_400M 400000000 - /* spinlock all ebu i/o */ extern spinlock_t ebu_lock; @@ -48,6 +37,14 @@ extern spinlock_t ebu_lock; extern void ltq_disable_irq(struct irq_data *data); extern void ltq_mask_and_ack_irq(struct irq_data *data); extern void ltq_enable_irq(struct irq_data *data); + +/* clock handling */ +extern int clk_activate(struct clk *clk); +extern void clk_deactivate(struct clk *clk); +extern struct clk *clk_get_cpu(void); +extern struct clk *clk_get_fpi(void); +#define clk_get_io clk_get_fpi + /* find out what bootsource we have */ extern unsigned char ltq_boot_select(void); /* find out what caused the last cpu reset */ diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 150c7be..b5a2acf 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -59,6 +59,11 @@ #define BS_NAND 0x6 #define BS_RMII0 0x7 +/* helpers used to access the cgu */ +#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) +#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) +extern __iomem void *ltq_cgu_membase; + /* * during early_printk no ioremap is possible * lets use KSEG1 instead diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index 412814f..f41fc52 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -22,46 +23,28 @@ #include #include "clk.h" +#include "prom.h" -struct clk { - const char *name; - unsigned long rate; - unsigned long (*get_rate) (void); -}; +/* lantiq socs have 3 static clocks */ +static struct clk cpu_clk_generic[2]; -static struct clk *cpu_clk; -static int cpu_clk_cnt; +void clkdev_add_static(unsigned long cpu, unsigned long fpi) +{ + cpu_clk_generic[0].rate = cpu; + cpu_clk_generic[1].rate = fpi; +} -/* lantiq socs have 3 static clocks */ -static struct clk cpu_clk_generic[] = { - { - .name = "cpu", - .get_rate = ltq_get_cpu_hz, - }, { - .name = "fpi", - .get_rate = ltq_get_fpi_hz, - }, { - .name = "io", - .get_rate = ltq_get_io_region_clock, - }, -}; - -static struct resource ltq_cgu_resource = { - .name = "cgu", - .start = LTQ_CGU_BASE_ADDR, - .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -/* remapped clock register range */ -void __iomem *ltq_cgu_membase; - -void clk_init(void) +struct clk *clk_get_cpu(void) { - cpu_clk = cpu_clk_generic; - cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic); + return &cpu_clk_generic[0]; } +struct clk *clk_get_fpi(void) +{ + return &cpu_clk_generic[1]; +} +EXPORT_SYMBOL_GPL(clk_get_fpi); + static inline int clk_good(struct clk *clk) { return clk && !IS_ERR(clk); @@ -82,38 +65,71 @@ unsigned long clk_get_rate(struct clk *clk) } EXPORT_SYMBOL(clk_get_rate); -struct clk *clk_get(struct device *dev, const char *id) +int clk_set_rate(struct clk *clk, unsigned long rate) { - int i; - - for (i = 0; i < cpu_clk_cnt; i++) - if (!strcmp(id, cpu_clk[i].name)) - return &cpu_clk[i]; - BUG(); - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ - /* not used */ + if (unlikely(!clk_good(clk))) + return 0; + if (clk->rates && *clk->rates) { + unsigned long *r = clk->rates; + + while (*r && (*r != rate)) + r++; + if (!*r) { + pr_err("clk %s.%s: trying to set invalid rate %ld\n", + clk->cl.dev_id, clk->cl.con_id, rate); + return -1; + } + } + clk->rate = rate; + return 0; } -EXPORT_SYMBOL(clk_put); +EXPORT_SYMBOL(clk_set_rate); int clk_enable(struct clk *clk) { - /* not used */ - return 0; + if (unlikely(!clk_good(clk))) + return -1; + + if (clk->enable) + return clk->enable(clk); + + return -1; } EXPORT_SYMBOL(clk_enable); void clk_disable(struct clk *clk) { - /* not used */ + if (unlikely(!clk_good(clk))) + return; + + if (clk->disable) + clk->disable(clk); } EXPORT_SYMBOL(clk_disable); -static inline u32 ltq_get_counter_resolution(void) +int clk_activate(struct clk *clk) +{ + if (unlikely(!clk_good(clk))) + return -1; + + if (clk->activate) + return clk->activate(clk); + + return -1; +} +EXPORT_SYMBOL(clk_activate); + +void clk_deactivate(struct clk *clk) +{ + if (unlikely(!clk_good(clk))) + return; + + if (clk->deactivate) + clk->deactivate(clk); +} +EXPORT_SYMBOL(clk_deactivate); + +static inline u32 get_counter_resolution(void) { u32 res; @@ -133,21 +149,11 @@ void __init plat_time_init(void) { struct clk *clk; - if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) - panic("Failed to insert cgu memory"); + ltq_soc_init(); - if (request_mem_region(ltq_cgu_resource.start, - resource_size(<q_cgu_resource), "cgu") < 0) - panic("Failed to request cgu memory"); - - ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, - resource_size(<q_cgu_resource)); - if (!ltq_cgu_membase) { - pr_err("Failed to remap cgu memory\n"); - unreachable(); - } - clk = clk_get(0, "cpu"); - mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); + clk = clk_get_cpu(); + mips_hpt_frequency = clk_get_rate(clk) / get_counter_resolution(); write_c0_compare(read_c0_count()); + pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); clk_put(clk); } diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h index 3328925..daed627 100644 --- a/arch/mips/lantiq/clk.h +++ b/arch/mips/lantiq/clk.h @@ -9,10 +9,69 @@ #ifndef _LTQ_CLK_H__ #define _LTQ_CLK_H__ -extern void clk_init(void); +#include -extern unsigned long ltq_get_cpu_hz(void); -extern unsigned long ltq_get_fpi_hz(void); -extern unsigned long ltq_get_io_region_clock(void); +/* clock speeds */ +#define CLOCK_33M 33333333 +#define CLOCK_60M 60000000 +#define CLOCK_62_5M 62500000 +#define CLOCK_83M 83333333 +#define CLOCK_83_5M 83500000 +#define CLOCK_98_304M 98304000 +#define CLOCK_100M 100000000 +#define CLOCK_111M 111111111 +#define CLOCK_125M 125000000 +#define CLOCK_133M 133333333 +#define CLOCK_150M 150000000 +#define CLOCK_166M 166666666 +#define CLOCK_167M 166666667 +#define CLOCK_196_608M 196608000 +#define CLOCK_200M 200000000 +#define CLOCK_250M 250000000 +#define CLOCK_266M 266666666 +#define CLOCK_300M 300000000 +#define CLOCK_333M 333333333 +#define CLOCK_393M 393215332 +#define CLOCK_400M 400000000 +#define CLOCK_500M 500000000 +#define CLOCK_600M 600000000 + +/* clock out speeds */ +#define CLOCK_32_768K 32768 +#define CLOCK_1_536M 1536000 +#define CLOCK_2_5M 2500000 +#define CLOCK_12M 12000000 +#define CLOCK_24M 24000000 +#define CLOCK_25M 25000000 +#define CLOCK_30M 30000000 +#define CLOCK_40M 40000000 +#define CLOCK_48M 48000000 +#define CLOCK_50M 50000000 +#define CLOCK_60M 60000000 + +struct clk { + struct clk_lookup cl; + unsigned long rate; + unsigned long *rates; + unsigned int module; + unsigned int bits; + unsigned long (*get_rate) (void); + int (*enable) (struct clk *clk); + void (*disable) (struct clk *clk); + int (*activate) (struct clk *clk); + void (*deactivate) (struct clk *clk); + void (*reboot) (struct clk *clk); +}; + +extern void clkdev_add_static(unsigned long cpu, unsigned long fpi); + +extern unsigned long ltq_danube_cpu_hz(void); +extern unsigned long ltq_danube_fpi_hz(void); + +extern unsigned long ltq_ar9_cpu_hz(void); +extern unsigned long ltq_ar9_fpi_hz(void); + +extern unsigned long ltq_vr9_cpu_hz(void); +extern unsigned long ltq_vr9_fpi_hz(void); #endif diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 323b574..6e930b70 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1 @@ -obj-y := prom.o pmu.o ebu.o reset.o gpio_stp.o gpio_ebu.o dma.o - -obj-$(CONFIG_SOC_XWAY) += clk-xway.o -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o +obj-y := prom.o sysctrl.o clk.o reset.o dma.o gpio_stp.o gpio_ebu.o diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c deleted file mode 100644 index 6522583..0000000 --- a/arch/mips/lantiq/xway/clk-ase.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include - -/* cgu registers */ -#define LTQ_CGU_SYS 0x0010 - -unsigned int ltq_get_io_region_clock(void) -{ - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_io_region_clock); - -unsigned int ltq_get_fpi_bus_clock(int fpi) -{ - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_fpi_bus_clock); - -unsigned int ltq_get_cpu_hz(void) -{ - if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) - return CLOCK_266M; - else - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_cpu_hz); - -unsigned int ltq_get_fpi_hz(void) -{ - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c deleted file mode 100644 index 696b1a3..0000000 --- a/arch/mips/lantiq/xway/clk-xway.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include - -static unsigned int ltq_ram_clocks[] = { - CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; -#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] - -#define BASIC_FREQUENCY_1 35328000 -#define BASIC_FREQUENCY_2 36000000 -#define BASIS_REQUENCY_USB 12000000 - -#define GET_BITS(x, msb, lsb) \ - (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) - -#define LTQ_CGU_PLL0_CFG 0x0004 -#define LTQ_CGU_PLL1_CFG 0x0008 -#define LTQ_CGU_PLL2_CFG 0x000C -#define LTQ_CGU_SYS 0x0010 -#define LTQ_CGU_UPDATE 0x0014 -#define LTQ_CGU_IF_CLK 0x0018 -#define LTQ_CGU_OSC_CON 0x001C -#define LTQ_CGU_SMD 0x0020 -#define LTQ_CGU_CT1SR 0x0028 -#define LTQ_CGU_CT2SR 0x002C -#define LTQ_CGU_PCMCR 0x0030 -#define LTQ_CGU_PCI_CR 0x0034 -#define LTQ_CGU_PD_PC 0x0038 -#define LTQ_CGU_FMR 0x003C - -#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) -#define CGU_PLL0_BYPASS \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) -#define CGU_PLL0_CFG_DSMSEL \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) -#define CGU_PLL0_CFG_FRAC_EN \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) -#define CGU_PLL1_SRC \ - (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) -#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ - (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) -#define CGU_SYS_FPI_SEL (1 << 6) -#define CGU_SYS_DDR_SEL 0x3 -#define CGU_PLL0_SRC (1 << 29) - -#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) -#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) -#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) -#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) -#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) - -static unsigned int ltq_get_pll0_fdiv(void); - -static inline unsigned int get_input_clock(int pll) -{ - switch (pll) { - case 0: - if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) - return BASIS_REQUENCY_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_FREQUENCY_1; - else - return BASIC_FREQUENCY_2; - case 1: - if (CGU_PLL1_SRC) - return BASIS_REQUENCY_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_FREQUENCY_1; - else - return BASIC_FREQUENCY_2; - case 2: - switch (CGU_PLL2_SRC) { - case 0: - return ltq_get_pll0_fdiv(); - case 1: - return CGU_PLL2_PHASE_DIVIDER_ENABLE ? - BASIC_FREQUENCY_1 : - BASIC_FREQUENCY_2; - case 2: - return BASIS_REQUENCY_USB; - } - default: - return 0; - } -} - -static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) -{ - u64 res, clock = get_input_clock(pll); - - res = num * clock; - do_div(res, den); - return res; -} - -static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 10) + K; - unsigned int den = (M + 1) << 10; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 11) + K + 512; - unsigned int den = (M + 1) << 11; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = K >= 512 ? - ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; - unsigned int den = (M + 1) << 12; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, - unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) -{ - if (!dsmsel) - return mash_dsm(pll, M, N, K); - else if (!phase_div_en) - return mash_dsm(pll, M, N, K); - else - return ssff_dsm_2(pll, M, N, K); -} - -static inline unsigned int ltq_get_pll0_fosc(void) -{ - if (CGU_PLL0_BYPASS) - return get_input_clock(0); - else - return !CGU_PLL0_CFG_FRAC_EN - ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, - CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE) - : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, - CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE); -} - -static unsigned int ltq_get_pll0_fdiv(void) -{ - unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; - - return (ltq_get_pll0_fosc() + (div >> 1)) / div; -} - -unsigned int ltq_get_io_region_clock(void) -{ - unsigned int ret = ltq_get_pll0_fosc(); - - switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { - default: - case 0: - return (ret + 1) / 2; - case 1: - return (ret * 2 + 2) / 5; - case 2: - return (ret + 1) / 3; - case 3: - return (ret + 2) / 4; - } -} -EXPORT_SYMBOL(ltq_get_io_region_clock); - -unsigned int ltq_get_fpi_bus_clock(int fpi) -{ - unsigned int ret = ltq_get_io_region_clock(); - - if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) - ret >>= 1; - return ret; -} -EXPORT_SYMBOL(ltq_get_fpi_bus_clock); - -unsigned int ltq_get_cpu_hz(void) -{ - switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { - case 0: - return CLOCK_333M; - case 4: - return DDR_HZ; - case 8: - return DDR_HZ << 1; - default: - return DDR_HZ >> 1; - } -} -EXPORT_SYMBOL(ltq_get_cpu_hz); - -unsigned int ltq_get_fpi_hz(void) -{ - unsigned int ddr_clock = DDR_HZ; - - if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) - return ddr_clock >> 1; - return ddr_clock; -} -EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c new file mode 100644 index 0000000..9aa17f7 --- /dev/null +++ b/arch/mips/lantiq/xway/clk.c @@ -0,0 +1,151 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "../clk.h" + +static unsigned int ram_clocks[] = { + CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; +#define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3] + +/* legacy xway clock */ +#define CGU_SYS 0x10 + +/* vr9 clock */ +#define CGU_SYS_VR9 0x0c +#define CGU_IF_CLK_VR9 0x24 + +unsigned long ltq_danube_fpi_hz(void) +{ + unsigned long ddr_clock = DDR_HZ; + + if (ltq_cgu_r32(CGU_SYS) & 0x40) + return ddr_clock >> 1; + return ddr_clock; +} + +unsigned long ltq_danube_cpu_hz(void) +{ + switch (ltq_cgu_r32(CGU_SYS) & 0xc) { + case 0: + return CLOCK_333M; + case 4: + return DDR_HZ; + case 8: + return DDR_HZ << 1; + default: + return DDR_HZ >> 1; + } +} + +unsigned long ltq_ar9_sys_hz(void) +{ + if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2) + return CLOCK_393M; + return CLOCK_333M; +} + +unsigned long ltq_ar9_fpi_hz(void) +{ + unsigned long sys = ltq_ar9_sys_hz(); + + if (ltq_cgu_r32(CGU_SYS) & BIT(0)) + return sys; + return sys >> 1; +} + +unsigned long ltq_ar9_cpu_hz(void) +{ + if (ltq_cgu_r32(CGU_SYS) & BIT(2)) + return ltq_ar9_fpi_hz(); + else + return ltq_ar9_sys_hz(); +} + +unsigned long ltq_vr9_cpu_hz(void) +{ + unsigned int cpu_sel; + unsigned long clk; + + cpu_sel = (ltq_cgu_r32(CGU_SYS_VR9) >> 4) & 0xf; + + switch (cpu_sel) { + case 0: + clk = CLOCK_600M; + break; + case 1: + clk = CLOCK_500M; + break; + case 2: + clk = CLOCK_393M; + break; + case 3: + clk = CLOCK_333M; + break; + case 5: + case 6: + clk = CLOCK_196_608M; + break; + case 7: + clk = CLOCK_167M; + break; + case 4: + case 8: + case 9: + clk = CLOCK_125M; + break; + default: + clk = 0; + break; + } + + return clk; +} + +unsigned long ltq_vr9_fpi_hz(void) +{ + unsigned int ocp_sel, cpu_clk; + unsigned long clk; + + cpu_clk = ltq_vr9_cpu_hz(); + ocp_sel = ltq_cgu_r32(CGU_SYS_VR9) & 0x3; + + switch (ocp_sel) { + case 0: + /* OCP ratio 1 */ + clk = cpu_clk; + break; + case 2: + /* OCP ratio 2 */ + clk = cpu_clk / 2; + break; + case 3: + /* OCP ratio 2.5 */ + clk = (cpu_clk * 2) / 5; + break; + case 4: + /* OCP ratio 3 */ + clk = cpu_clk / 3; + break; + default: + clk = 0; + break; + } + + return clk; +} diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c deleted file mode 100644 index 419b47b..0000000 --- a/arch/mips/lantiq/xway/ebu.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * EBU - the external bus unit attaches PCI, NOR and NAND - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include - -#include - -static struct resource ltq_ebu_resource = { - .name = "ebu", - .start = LTQ_EBU_BASE_ADDR, - .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -/* remapped base addr of the clock unit and external bus unit */ -void __iomem *ltq_ebu_membase; - -static int __init lantiq_ebu_init(void) -{ - /* insert and request the memory region */ - if (insert_resource(&iomem_resource, <q_ebu_resource) < 0) - panic("Failed to insert ebu memory"); - - if (request_mem_region(ltq_ebu_resource.start, - resource_size(<q_ebu_resource), "ebu") < 0) - panic("Failed to request ebu memory"); - - /* remap ebu register range */ - ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, - resource_size(<q_ebu_resource)); - if (!ltq_ebu_membase) - panic("Failed to remap ebu memory"); - - /* make sure to unprotect the memory region where flash is located */ - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); - return 0; -} - -postcore_initcall(lantiq_ebu_init); diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c deleted file mode 100644 index fe85361..0000000 --- a/arch/mips/lantiq/xway/pmu.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include - -#include - -/* PMU - the power management unit allows us to turn part of the core - * on and off - */ - -/* the enable / disable registers */ -#define LTQ_PMU_PWDCR 0x1C -#define LTQ_PMU_PWDSR 0x20 - -#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) -#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) - -static struct resource ltq_pmu_resource = { - .name = "pmu", - .start = LTQ_PMU_BASE_ADDR, - .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static void __iomem *ltq_pmu_membase; - -void ltq_pmu_enable(unsigned int module) -{ - int err = 1000000; - - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); - do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); - - if (!err) - panic("activating PMU module failed!"); -} -EXPORT_SYMBOL(ltq_pmu_enable); - -void ltq_pmu_disable(unsigned int module) -{ - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); -} -EXPORT_SYMBOL(ltq_pmu_disable); - -int __init ltq_pmu_init(void) -{ - if (insert_resource(&iomem_resource, <q_pmu_resource) < 0) - panic("Failed to insert pmu memory"); - - if (request_mem_region(ltq_pmu_resource.start, - resource_size(<q_pmu_resource), "pmu") < 0) - panic("Failed to request pmu memory"); - - ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, - resource_size(<q_pmu_resource)); - if (!ltq_pmu_membase) - panic("Failed to remap pmu memory"); - return 0; -} - -core_initcall(ltq_pmu_init); diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c new file mode 100644 index 0000000..3029139 --- /dev/null +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -0,0 +1,364 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011-2012 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "../clk.h" +#include "../prom.h" + +/* clock control register */ +#define CGU_IFCCR 0x0018 +/* system clock register */ +#define CGU_SYS 0x0010 +/* pci control register */ +#define CGU_PCICR 0x0034 +/* ephy configuration register */ +#define CGU_EPHY 0x10 +/* power control register */ +#define PMU_PWDCR 0x1C +/* power status register */ +#define PMU_PWDSR 0x20 +/* power control register */ +#define PMU_PWDCR1 0x24 +/* power status register */ +#define PMU_PWDSR1 0x28 +/* power control register */ +#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) +/* power status register */ +#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) + +/* clock gates that we can en/disable */ +#define PMU_USB0_P BIT(0) +#define PMU_PCI BIT(4) +#define PMU_USB0 BIT(6) +#define PMU_ASC0 BIT(7) +#define PMU_EPHY BIT(7) /* ase */ +#define PMU_SPI BIT(8) +#define PMU_DFE BIT(9) +#define PMU_EBU BIT(10) +#define PMU_STP BIT(11) +#define PMU_AHBS BIT(13) /* vr9 */ +#define PMU_AHBM BIT(15) +#define PMU_ASC1 BIT(17) +#define PMU_PPE_QSB BIT(18) +#define PMU_PPE_SLL01 BIT(19) +#define PMU_PPE_TC BIT(21) +#define PMU_PPE_EMA BIT(22) +#define PMU_PPE_DPLUM BIT(23) +#define PMU_PPE_DPLUS BIT(24) +#define PMU_USB1_P BIT(26) +#define PMU_USB1 BIT(27) +#define PMU_PPE_TOP BIT(29) +#define PMU_GPHY BIT(30) +#define PMU_PCIE_CLK BIT(31) + +#define PMU1_PCIE_PHY BIT(0) +#define PMU1_PCIE_CTL BIT(1) +#define PMU1_PCIE_PDI BIT(4) +#define PMU1_PCIE_MSI BIT(5) + +#define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y)) +#define pmu_r32(x) ltq_r32(pmu_membase + (x)) + +static void __iomem *pmu_membase; +void __iomem *ltq_cgu_membase; +void __iomem *ltq_ebu_membase; + +/* legacy function kept alive to ease clkdev transition */ +void ltq_pmu_enable(unsigned int module) +{ + int err = 1000000; + + pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR); + do {} while (--err && (pmu_r32(PMU_PWDSR) & module)); + + if (!err) + panic("activating PMU module failed!"); +} +EXPORT_SYMBOL(ltq_pmu_enable); + +/* legacy function kept alive to ease clkdev transition */ +void ltq_pmu_disable(unsigned int module) +{ + pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR); +} +EXPORT_SYMBOL(ltq_pmu_disable); + +/* enable a hw clock */ +static int cgu_enable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR); + return 0; +} + +/* disable a hw clock */ +static void cgu_disable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR); +} + +/* enable a clock gate */ +static int pmu_enable(struct clk *clk) +{ + int err = 1000000; + + pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, + PWDCR(clk->module)); + do {} while (--err && (pmu_r32(PWDSR(clk->module)) & clk->bits)); + + if (!err) + panic("activating PMU module failed!\n"); + + return 0; +} + +/* disable a clock gate */ +static void pmu_disable(struct clk *clk) +{ + pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, + PWDCR(clk->module)); +} + +/* the pci enable helper */ +static int pci_enable(struct clk *clk) +{ + unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); + /* set bus clock speed */ + if (of_machine_is_compatible("lantiq,ar9")) { + ifccr &= ~0x1f00000; + if (clk->rate == CLOCK_33M) + ifccr |= 0xe00000; + else + ifccr |= 0x700000; /* 62.5M */ + } else { + ifccr &= ~0xf00000; + if (clk->rate == CLOCK_33M) + ifccr |= 0x800000; + else + ifccr |= 0x400000; /* 62.5M */ + } + ltq_cgu_w32(ifccr, CGU_IFCCR); + pmu_enable(clk); + return 0; +} + +/* enable the external clock as a source */ +static int pci_ext_enable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16), + CGU_IFCCR); + ltq_cgu_w32((1 << 30), CGU_PCICR); + return 0; +} + +/* disable the external clock as a source */ +static void pci_ext_disable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16), + CGU_IFCCR); + ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR); +} + +/* enable a clockout source */ +static int clkout_enable(struct clk *clk) +{ + int i; + + /* get the correct rate */ + for (i = 0; i < 4; i++) { + if (clk->rates[i] == clk->rate) { + int shift = 14 - (2 * clk->module); + unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); + + ifccr &= ~(3 << shift); + ifccr |= i << shift; + ltq_cgu_w32(ifccr, CGU_IFCCR); + return 0; + } + } + return -1; +} + +/* manage the clock gates via PMU */ +static void clkdev_add_pmu(const char *dev, const char *con, + unsigned int module, unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = pmu_enable; + clk->disable = pmu_disable; + clk->module = module; + clk->bits = bits; + clkdev_add(&clk->cl); +} + +/* manage the clock generator */ +static void clkdev_add_cgu(const char *dev, const char *con, + unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = cgu_enable; + clk->disable = cgu_disable; + clk->bits = bits; + clkdev_add(&clk->cl); +} + +/* pci needs its own enable function as the setup is a bit more complex */ +static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0}; + +static void clkdev_add_pci(void) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); + + /* main pci clock */ + clk->cl.dev_id = "17000000.pci"; + clk->cl.con_id = NULL; + clk->cl.clk = clk; + clk->rate = CLOCK_33M; + clk->rates = valid_pci_rates; + clk->enable = pci_enable; + clk->disable = pmu_disable; + clk->module = 0; + clk->bits = PMU_PCI; + clkdev_add(&clk->cl); + + /* use internal/external bus clock */ + clk_ext->cl.dev_id = "17000000.pci"; + clk_ext->cl.con_id = "external"; + clk_ext->cl.clk = clk_ext; + clk_ext->enable = pci_ext_enable; + clk_ext->disable = pci_ext_disable; + clkdev_add(&clk_ext->cl); +} + +/* xway socs can generate clocks on gpio pins */ +static unsigned long valid_clkout_rates[4][5] = { + {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0}, + {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0}, + {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0}, + {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0}, +}; + +static void clkdev_add_clkout(void) +{ + int i; + + for (i = 0; i < 4; i++) { + struct clk *clk; + char *name; + + name = kzalloc(sizeof("clkout0"), GFP_KERNEL); + sprintf(name, "clkout%d", i); + + clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + clk->cl.dev_id = "1f103000.cgu"; + clk->cl.con_id = name; + clk->cl.clk = clk; + clk->rate = 0; + clk->rates = valid_clkout_rates[i]; + clk->enable = clkout_enable; + clk->module = i; + clkdev_add(&clk->cl); + } +} + +/* bring up all register ranges that we need for basic system control */ +void __init ltq_soc_init(void) +{ + struct resource res_pmu, res_cgu, res_ebu; + struct device_node *np_pmu = + of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway"); + struct device_node *np_cgu = + of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway"); + struct device_node *np_ebu = + of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway"); + + /* check if all the core register ranges are available */ + if (!np_pmu || !np_cgu || !np_ebu) + panic("Failed to load core nodess from devicetree"); + + if (of_address_to_resource(np_pmu, 0, &res_pmu) || + of_address_to_resource(np_cgu, 0, &res_cgu) || + of_address_to_resource(np_ebu, 0, &res_ebu)) + panic("Failed to get core resources"); + + if ((request_mem_region(res_pmu.start, resource_size(&res_pmu), + res_pmu.name) < 0) || + (request_mem_region(res_cgu.start, resource_size(&res_cgu), + res_cgu.name) < 0) || + (request_mem_region(res_ebu.start, resource_size(&res_ebu), + res_ebu.name) < 0)) + pr_err("Failed to request core reources"); + + pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu)); + ltq_cgu_membase = ioremap_nocache(res_cgu.start, + resource_size(&res_cgu)); + ltq_ebu_membase = ioremap_nocache(res_ebu.start, + resource_size(&res_ebu)); + if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase) + panic("Failed to remap core resources"); + + /* make sure to unprotect the memory region where flash is located */ + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); + + /* add our generic xway clocks */ + clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI); + clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0); + clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT); + clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP); + clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA); + clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI); + clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU); + clkdev_add_clkout(); + + /* add the soc dependent clocks */ + if (!of_machine_is_compatible("lantiq,vr9")) + clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE); + + if (!of_machine_is_compatible("lantiq,ase")) { + clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1); + clkdev_add_pci(); + } + + if (of_machine_is_compatible("lantiq,ase")) { + if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) + clkdev_add_static(CLOCK_266M, CLOCK_133M); + else + clkdev_add_static(CLOCK_133M, CLOCK_133M); + clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY), + clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY); + } else if (of_machine_is_compatible("lantiq,vr9")) { + clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz()); + clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY); + clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK); + clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI); + clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI); + clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL); + clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); + } else if (of_machine_is_compatible("lantiq,ar9")) { + clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz()); + clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH); + } else { + clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz()); + } +} -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:20:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:22:00 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48624 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903679Ab2EDMUN (ORCPT ); Fri, 4 May 2012 14:20:13 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 06/14] MIPS: lantiq: convert dma to platform driver Date: Fri, 4 May 2012 14:18:31 +0200 Message-Id: <1336133919-26525-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33144 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2984 Lines: 115 Add code to make the dma driver load as a platform device from the devicetree. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/dma.c | 65 ++++++++++++++++++++++++++++-------------- 1 files changed, 43 insertions(+), 22 deletions(-) diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index b210e93..0dffb94 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -19,7 +19,8 @@ #include #include #include -#include +#include +#include #include #include @@ -55,13 +56,6 @@ #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ ltq_dma_membase + (z)) -static struct resource ltq_dma_resource = { - .name = "dma", - .start = LTQ_DMA_BASE_ADDR, - .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - static void __iomem *ltq_dma_membase; void @@ -215,27 +209,28 @@ ltq_dma_init_port(int p) } EXPORT_SYMBOL_GPL(ltq_dma_init_port); -int __init -ltq_dma_init(void) +static int __devinit +ltq_dma_init(struct platform_device *pdev) { + struct clk *clk; + struct resource *res; int i; - /* insert and request the memory region */ - if (insert_resource(&iomem_resource, <q_dma_resource) < 0) - panic("Failed to insert dma memory"); - - if (request_mem_region(ltq_dma_resource.start, - resource_size(<q_dma_resource), "dma") < 0) - panic("Failed to request dma memory"); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + panic("Failed to get dma resource"); /* remap dma register range */ - ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, - resource_size(<q_dma_resource)); + ltq_dma_membase = devm_request_and_ioremap(&pdev->dev, res); if (!ltq_dma_membase) - panic("Failed to remap dma memory"); + panic("Failed to remap dma resource"); /* power up and reset the dma engine */ - ltq_pmu_enable(PMU_DMA); + clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) + panic("Failed to get dma clock"); + + clk_enable(clk); ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); /* disable all interrupts */ @@ -248,7 +243,33 @@ ltq_dma_init(void) ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); } + dev_info(&pdev->dev, "init done\n"); return 0; } -postcore_initcall(ltq_dma_init); +static const struct of_device_id dma_match[] = { + { .compatible = "lantiq,dma-xway" }, + {}, +}; +MODULE_DEVICE_TABLE(of, dma_match); + +static struct platform_driver dma_driver = { + .probe = ltq_dma_init, + .driver = { + .name = "dma-xway", + .owner = THIS_MODULE, + .of_match_table = dma_match, + }, +}; + +int __init +dma_init(void) +{ + int ret = platform_driver_register(&dma_driver); + + if (ret) + pr_info("ltq_dma : Error registering platfom driver!"); + return ret; +} + +postcore_initcall(dma_init); -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:20:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:22:25 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48626 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903680Ab2EDMUO (ORCPT ); Fri, 4 May 2012 14:20:14 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 07/14] MIPS: pci: convert lantiq driver to OF Date: Fri, 4 May 2012 14:18:32 +0200 Message-Id: <1336133919-26525-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33145 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 10636 Lines: 361 Implement support for OF inside the lantiq PCI driver. The patch also splits pcibios_plat_dev_init and pcibios_map_irq out into their own file to accomodate coexistance with the upcoming pcie driver. Signed-off-by: John Crispin --- arch/mips/lantiq/Kconfig | 5 +- arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-lantiq.c | 40 ++++++++++ arch/mips/pci/pci-lantiq.c | 177 ++++++++++++++++++++---------------------- 4 files changed, 131 insertions(+), 94 deletions(-) create mode 100644 arch/mips/pci/fixup-lantiq.c diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index b86d942..c645b44 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -19,7 +19,6 @@ config SOC_XWAY select HW_HAS_PCI endchoice - choice prompt "Devicetree" @@ -28,4 +27,8 @@ config DT_EASY50712 depends on SOC_XWAY endchoice +config PCI_LANTIQ + bool "PCI Support" + depends on SOC_XWAY && PCI + endif diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c3ac4b0..499a019 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -41,7 +41,8 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o -obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o +obj-$(CONFIG_LANTIQ) += fixup-lantiq.o +obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o diff --git a/arch/mips/pci/fixup-lantiq.c b/arch/mips/pci/fixup-lantiq.c new file mode 100644 index 0000000..6c829df --- /dev/null +++ b/arch/mips/pci/fixup-lantiq.c @@ -0,0 +1,40 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#include +#include + +int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; +int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + if (ltq_pci_plat_arch_init) + return ltq_pci_plat_arch_init(dev); + + if (ltq_pci_plat_dev_init) + return ltq_pci_plat_dev_init(dev); + + return 0; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct of_irq dev_irq; + int irq; + + if (of_irq_map_pci(dev, &dev_irq)) { + dev_err(&dev->dev, "trying to map irq for unknown slot:%d pin:%d\n", + slot, pin); + return 0; + } + irq = irq_create_of_mapping(dev_irq.controller, dev_irq.specifier, + dev_irq.size); + dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, irq); + return irq; +} diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 3418178..ea45353 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -13,8 +13,12 @@ #include #include #include -#include -#include +#include +#include +#include +#include +#include +#include #include #include @@ -22,17 +26,9 @@ #include #include -#include #include "pci-lantiq.h" -#define LTQ_PCI_CFG_BASE 0x17000000 -#define LTQ_PCI_CFG_SIZE 0x00008000 -#define LTQ_PCI_MEM_BASE 0x18000000 -#define LTQ_PCI_MEM_SIZE 0x02000000 -#define LTQ_PCI_IO_BASE 0x1AE00000 -#define LTQ_PCI_IO_SIZE 0x00200000 - #define PCI_CR_FCI_ADDR_MAP0 0x00C0 #define PCI_CR_FCI_ADDR_MAP1 0x00C4 #define PCI_CR_FCI_ADDR_MAP2 0x00C8 @@ -71,50 +67,24 @@ __iomem void *ltq_pci_mapped_cfg; static __iomem void *ltq_pci_membase; -int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; - -/* Since the PCI REQ pins can be reused for other functionality, make it - possible to exclude those from interpretation by the PCI controller */ -static int ltq_pci_req_mask = 0xf; - -static int *ltq_pci_irq_map; - -struct pci_ops ltq_pci_ops = { +static int reset_gpio; +static struct clk *clk_pci, *clk_external; +static struct resource pci_io_resource; +static struct resource pci_mem_resource; +static struct pci_ops pci_ops = { .read = ltq_pci_read_config_dword, .write = ltq_pci_write_config_dword }; -static struct resource pci_io_resource = { - .name = "pci io space", - .start = LTQ_PCI_IO_BASE, - .end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1, - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = { - .name = "pci memory space", - .start = LTQ_PCI_MEM_BASE, - .end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - -static struct pci_controller ltq_pci_controller = { - .pci_ops = <q_pci_ops, +static struct pci_controller pci_controller = { + .pci_ops = &pci_ops, .mem_resource = &pci_mem_resource, .mem_offset = 0x00000000UL, .io_resource = &pci_io_resource, .io_offset = 0x00000000UL, }; -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - if (ltqpci_plat_dev_init) - return ltqpci_plat_dev_init(dev); - - return 0; -} - -static u32 ltq_calc_bar11mask(void) +static inline u32 ltq_calc_bar11mask(void) { u32 mem, bar11mask; @@ -125,32 +95,42 @@ static u32 ltq_calc_bar11mask(void) return bar11mask; } -static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) +static int __devinit ltq_pci_startup(struct platform_device *pdev) { + struct device_node *node = pdev->dev.of_node; + const __be32 *req_mask, *bus_clk; u32 temp_buffer; - /* set clock to 33Mhz */ - if (ltq_is_ar9()) { - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR); - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR); - } else { - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR); - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR); + /* get our clocks */ + clk_pci = clk_get(&pdev->dev, NULL); + if (IS_ERR(clk_pci)) { + dev_err(&pdev->dev, "failed to get pci clock\n"); + return PTR_ERR(clk_pci); } - /* external or internal clock ? */ - if (conf->clock) { - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16), - LTQ_CGU_IFCCR); - ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR); - } else { - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16), - LTQ_CGU_IFCCR); - ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR); + clk_external = clk_get(&pdev->dev, "external"); + if (IS_ERR(clk_external)) { + clk_put(clk_pci); + dev_err(&pdev->dev, "failed to get external pci clock\n"); + return PTR_ERR(clk_external); } - /* setup pci clock and gpis used by pci */ - gpio_request(21, "pci-reset"); + /* read the bus speed that we want */ + bus_clk = of_get_property(node, "lantiq,bus-clock", NULL); + if (bus_clk) + clk_set_rate(clk_pci, *bus_clk); + + /* and enable the clocks */ + clk_enable(clk_pci); + if (of_find_property(node, "lantiq,external-clock", NULL)) + clk_enable(clk_external); + else + clk_disable(clk_external); + + /* setup reset gpio used by pci */ + reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); + if (reset_gpio > 0) + devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset"); /* enable auto-switching between PCI and EBU */ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); @@ -163,7 +143,12 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) /* enable external 2 PCI masters */ temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB); - temp_buffer &= (~(ltq_pci_req_mask << 16)); + /* setup the request mask */ + req_mask = of_get_property(node, "req-mask", NULL); + if (req_mask) + temp_buffer &= ~((*req_mask & 0xf) << 16); + else + temp_buffer &= ~0xf0000; /* enable internal arbiter */ temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); /* enable internal PCI master reqest */ @@ -207,47 +192,55 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN); /* toggle reset pin */ - __gpio_set_value(21, 0); - wmb(); - mdelay(1); - __gpio_set_value(21, 1); - return 0; -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - if (ltq_pci_irq_map[slot]) - return ltq_pci_irq_map[slot]; - printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n", - slot); - + if (reset_gpio > 0) { + __gpio_set_value(reset_gpio, 0); + wmb(); + mdelay(1); + __gpio_set_value(reset_gpio, 1); + } return 0; } static int __devinit ltq_pci_probe(struct platform_device *pdev) { - struct ltq_pci_data *ltq_pci_data = - (struct ltq_pci_data *) pdev->dev.platform_data; + struct resource *res_cfg, *res_bridge; pci_clear_flags(PCI_PROBE_ONLY); - ltq_pci_irq_map = ltq_pci_data->irq; - ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); - ltq_pci_mapped_cfg = - ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); - ltq_pci_controller.io_map_base = - (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); - ltq_pci_startup(ltq_pci_data); - register_pci_controller(<q_pci_controller); + res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res_cfg || !res_bridge) { + dev_err(&pdev->dev, "missing memory reources\n"); + return -EINVAL; + } + + ltq_pci_membase = devm_request_and_ioremap(&pdev->dev, res_bridge); + ltq_pci_mapped_cfg = devm_request_and_ioremap(&pdev->dev, res_cfg); + + if (!ltq_pci_membase || !ltq_pci_mapped_cfg) { + dev_err(&pdev->dev, "failed to remap resources\n"); + return -ENOMEM; + } + + ltq_pci_startup(pdev); + + pci_load_of_ranges(&pci_controller, pdev->dev.of_node); + register_pci_controller(&pci_controller); return 0; } -static struct platform_driver -ltq_pci_driver = { +static const struct of_device_id ltq_pci_match[] = { + { .compatible = "lantiq,pci-xway" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ltq_pci_match); + +static struct platform_driver ltq_pci_driver = { .probe = ltq_pci_probe, .driver = { - .name = "ltq_pci", + .name = "pci-xway", .owner = THIS_MODULE, + .of_match_table = ltq_pci_match, }, }; @@ -255,7 +248,7 @@ int __init pcibios_init(void) { int ret = platform_driver_register(<q_pci_driver); if (ret) - printk(KERN_INFO "ltq_pci: Error registering platform driver!"); + pr_info("pci-xway: Error registering platform driver!"); return ret; } -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:20:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:22:51 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48628 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903682Ab2EDMUQ (ORCPT ); Fri, 4 May 2012 14:20:16 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Grant Likely , linux-kernel@vger.kernel.org Subject: [PATCH 08/14] GPIO: MIPS: lantiq: convert gpio-stp to OF and move it to subsystem Date: Fri, 4 May 2012 14:18:33 +0200 Message-Id: <1336133919-26525-8-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33146 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 15827 Lines: 533 Implements OF support and moves the driver from arch/mips/lantiq/xway/ to the gpio subsystem. The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a peripheral controller used to drive external shift register cascades. At most 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem to drive the 2 LSBs of the cascade automatically. The driver currently only supports output functionality. Patches for the input feature found on newer generations of the soc will be provided in a later series. Signed-off-by: John Crispin Cc: Grant Likely Cc: linux-kernel@vger.kernel.org --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/gpio_stp.c | 152 ------------------- drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-stp-xway.c | 300 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 312 insertions(+), 153 deletions(-) delete mode 100644 arch/mips/lantiq/xway/gpio_stp.c create mode 100644 drivers/gpio/gpio-stp-xway.c diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 6e930b70..9c5d69f 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1 +1 @@ -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gpio_stp.o gpio_ebu.o +obj-y := prom.o sysctrl.o clk.o reset.o dma.o gpio_ebu.o diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c deleted file mode 100644 index 4f4bd61..0000000 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2007 John Crispin - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define LTQ_STP_CON0 0x00 -#define LTQ_STP_CON1 0x04 -#define LTQ_STP_CPU0 0x08 -#define LTQ_STP_CPU1 0x0C -#define LTQ_STP_AR 0x10 - -#define LTQ_STP_CON_SWU (1 << 31) -#define LTQ_STP_2HZ 0 -#define LTQ_STP_4HZ (1 << 23) -#define LTQ_STP_8HZ (2 << 23) -#define LTQ_STP_10HZ (3 << 23) -#define LTQ_STP_SPEED_MASK (0xf << 23) -#define LTQ_STP_UPD_FPI (1 << 31) -#define LTQ_STP_UPD_MASK (3 << 30) -#define LTQ_STP_ADSL_SRC (3 << 24) - -#define LTQ_STP_GROUP0 (1 << 0) - -#define LTQ_STP_RISING 0 -#define LTQ_STP_FALLING (1 << 26) -#define LTQ_STP_EDGE_MASK (1 << 26) - -#define ltq_stp_r32(reg) __raw_readl(ltq_stp_membase + reg) -#define ltq_stp_w32(val, reg) __raw_writel(val, ltq_stp_membase + reg) -#define ltq_stp_w32_mask(clear, set, reg) \ - ltq_w32((ltq_r32(ltq_stp_membase + reg) & ~(clear)) | (set), \ - ltq_stp_membase + (reg)) - -static int ltq_stp_shadow = 0xffff; -static void __iomem *ltq_stp_membase; - -static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value) -{ - if (value) - ltq_stp_shadow |= (1 << offset); - else - ltq_stp_shadow &= ~(1 << offset); - ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0); -} - -static int ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - ltq_stp_set(chip, offset, value); - - return 0; -} - -static struct gpio_chip ltq_stp_chip = { - .label = "ltq_stp", - .direction_output = ltq_stp_direction_output, - .set = ltq_stp_set, - .base = 48, - .ngpio = 24, - .can_sleep = 1, - .owner = THIS_MODULE, -}; - -static int ltq_stp_hw_init(void) -{ - /* sane defaults */ - ltq_stp_w32(0, LTQ_STP_AR); - ltq_stp_w32(0, LTQ_STP_CPU0); - ltq_stp_w32(0, LTQ_STP_CPU1); - ltq_stp_w32(LTQ_STP_CON_SWU, LTQ_STP_CON0); - ltq_stp_w32(0, LTQ_STP_CON1); - - /* rising or falling edge */ - ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0); - - /* per default stp 15-0 are set */ - ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1); - - /* stp are update periodically by the FPI bus */ - ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1); - - /* set stp update speed */ - ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1); - - /* tell the hardware that pin (led) 0 and 1 are controlled - * by the dsl arc - */ - ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0); - - ltq_pmu_enable(PMU_LED); - return 0; -} - -static int __devinit ltq_stp_probe(struct platform_device *pdev) -{ - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - int ret = 0; - - if (!res) - return -ENOENT; - res = devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), dev_name(&pdev->dev)); - if (!res) { - dev_err(&pdev->dev, "failed to request STP memory\n"); - return -EBUSY; - } - ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start, - resource_size(res)); - if (!ltq_stp_membase) { - dev_err(&pdev->dev, "failed to remap STP memory\n"); - return -ENOMEM; - } - ret = gpiochip_add(<q_stp_chip); - if (!ret) - ret = ltq_stp_hw_init(); - - return ret; -} - -static struct platform_driver ltq_stp_driver = { - .probe = ltq_stp_probe, - .driver = { - .name = "ltq_stp", - .owner = THIS_MODULE, - }, -}; - -int __init ltq_stp_init(void) -{ - int ret = platform_driver_register(<q_stp_driver); - - if (ret) - pr_info("ltq_stp: error registering platform driver"); - return ret; -} - -postcore_initcall(ltq_stp_init); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 7875c3f..2ec6a3b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -311,6 +311,16 @@ config GPIO_STMPE This enables support for the GPIOs found on the STMPE I/O Expanders. +config GPIO_STP_XWAY + bool "XWAY STP GPIOs" + depends on SOC_XWAY + help + This enables support for the Serial To Parallel (STP) unit found on + XWAY SoC. The STP allows the SoC to drive a shift registers cascade, + that can be up to 24 bit. This peripheral is aimed at driving leds. + Some of the gpios/leds can be auto updated by the soc with dsl and + phy status. + config GPIO_TC3589X bool "TC3589X GPIOs" depends on MFD_TC3589X diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 1c2f6c0..ff85e12 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_GPIO_SCH) += gpio-sch.o obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o +obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c new file mode 100644 index 0000000..9b53adf --- /dev/null +++ b/drivers/gpio/gpio-stp-xway.c @@ -0,0 +1,300 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a + * peripheral controller used to drive external shift register cascades. At most + * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem + * to drive the 2 LSBs of the cascade automatically. + */ + +/* control register 0 */ +#define XWAY_STP_CON0 0x00 +/* control register 1 */ +#define XWAY_STP_CON1 0x04 +/* data register 0 */ +#define XWAY_STP_CPU0 0x08 +/* data register 1 */ +#define XWAY_STP_CPU1 0x0C +/* access register */ +#define XWAY_STP_AR 0x10 + +/* software or hardware update select bit */ +#define XWAY_STP_CON_SWU BIT(31) + +/* automatic update rates */ +#define XWAY_STP_2HZ 0 +#define XWAY_STP_4HZ BIT(23) +#define XWAY_STP_8HZ BIT(24) +#define XWAY_STP_10HZ (BIT(24) | BIT(23)) +#define XWAY_STP_SPEED_MASK (0xf << 23) + +/* clock source for automatic update */ +#define XWAY_STP_UPD_FPI BIT(31) +#define XWAY_STP_UPD_MASK (BIT(31) | BIT(30)) + +/* let the adsl core drive the 2 LSBs */ +#define XWAY_STP_ADSL_SHIFT 24 +#define XWAY_STP_ADSL_MASK 0x3 + +/* 2 groups of 3 bits can be driven by the phys */ +#define XWAY_STP_PHY_MASK 0x3 +#define XWAY_STP_PHY1_SHIFT 27 +#define XWAY_STP_PHY2_SHIFT 15 + +/* STP has 3 groups of 8 bits */ +#define XWAY_STP_GROUP0 BIT(0) +#define XWAY_STP_GROUP1 BIT(1) +#define XWAY_STP_GROUP2 BIT(2) +#define XWAY_STP_GROUP_MASK (0x7) + +/* Edge configuration bits */ +#define XWAY_STP_FALLING BIT(26) +#define XWAY_STP_EDGE_MASK BIT(26) + +#define xway_stp_r32(m, reg) __raw_readl(m + reg) +#define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg) +#define xway_stp_w32_mask(m, clear, set, reg) \ + ltq_w32((ltq_r32(m + reg) & ~(clear)) | (set), \ + m + reg) + +struct xway_stp { + struct gpio_chip gc; + void __iomem *virt; + u32 edge; /* rising or falling edge triggered shift register */ + u16 shadow; /* shadow the shift registers state */ + u8 groups; /* we can drive 1-3 groups of 8bit each */ + u8 dsl; /* the 2 LSBs can be driven by the dsl core */ + u8 phy1; /* 3 bits can be driven by phy1 */ + u8 phy2; /* 3 bits can be driven by phy2 */ + u8 reserved; /* mask out the hw driven bits in gpio_request */ +}; + +/* + * xway_stp_set - gpio_chip->set - set gpios. + * @gc: Pointer to gpio_chip device structure. + * @gpio: GPIO signal number. + * @val: Value to be written to specified signal. + * + * Set the shadow value and call ltq_ebu_apply. + */ +static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val) +{ + struct xway_stp *chip = + container_of(gc, struct xway_stp, gc); + + if (val) + chip->shadow |= BIT(gpio); + else + chip->shadow &= ~BIT(gpio); + xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0); + xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0); +} + +/* + * xway_stp_dir_out - gpio_chip->dir_out - set gpio direction. + * @gc: Pointer to gpio_chip device structure. + * @gpio: GPIO signal number. + * @val: Value to be written to specified signal. + * + * Same as xway_stp_set, always returns 0. + */ +static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val) +{ + xway_stp_set(gc, gpio, val); + + return 0; +} + +/* + * xway_stp_request - gpio_chip->request + * @gc: Pointer to gpio_chip device structure. + * @gpio: GPIO signal number. + * + * We mask out the HW driven pins + */ +static int xway_stp_request(struct gpio_chip *gc, unsigned gpio) +{ + struct xway_stp *chip = + container_of(gc, struct xway_stp, gc); + + if ((gpio < 8) && (chip->reserved & BIT(gpio))) { + dev_err(gc->dev, "GPIO %d is driven by hardware\n", gpio); + return -ENODEV; + } + + return 0; +} + +/* + * xway_stp_hw_init - Configure the STP unit and enable the clock gate + * @virt: pointer to the remapped register range + */ +static int xway_stp_hw_init(struct xway_stp *chip) +{ + /* sane defaults */ + xway_stp_w32(chip->virt, 0, XWAY_STP_AR); + xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0); + xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1); + xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0); + xway_stp_w32(chip->virt, 0, XWAY_STP_CON1); + + /* apply edge trigger settings for the shift register */ + xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK, + chip->edge, XWAY_STP_CON0); + + /* apply led group settings */ + xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK, + chip->groups, XWAY_STP_CON1); + + /* tell the hardware which pins are controlled by the dsl modem */ + xway_stp_w32_mask(chip->virt, + XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT, + chip->dsl << XWAY_STP_ADSL_SHIFT, + XWAY_STP_CON0); + + /* tell the hardware which pins are controlled by the phys */ + xway_stp_w32_mask(chip->virt, + XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT, + chip->phy1 << XWAY_STP_PHY1_SHIFT, + XWAY_STP_CON0); + xway_stp_w32_mask(chip->virt, + XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT, + chip->phy2 << XWAY_STP_PHY2_SHIFT, + XWAY_STP_CON1); + + /* mask out the hw driven bits in gpio_request */ + chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl; + + /* + * if we have pins that are driven by hw, we need to tell the stp what + * clock to use as a timer. + */ + if (chip->reserved) + xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK, + XWAY_STP_UPD_FPI, XWAY_STP_CON1); + + return 0; +} + +static int __devinit xway_stp_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + const __be32 *shadow, *groups, *dsl, *phy; + struct xway_stp *chip; + struct clk *clk; + int ret = 0; + + if (!res) { + dev_err(&pdev->dev, "failed to request STP resource\n"); + return -ENOENT; + } + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->virt = devm_request_and_ioremap(&pdev->dev, res); + if (!chip->virt) { + dev_err(&pdev->dev, "failed to remap STP memory\n"); + return -ENOMEM; + } + chip->gc.dev = &pdev->dev; + chip->gc.label = "stp-xway"; + chip->gc.direction_output = xway_stp_dir_out; + chip->gc.set = xway_stp_set; + chip->gc.request = xway_stp_request; + chip->gc.base = -1; + chip->gc.owner = THIS_MODULE; + + /* store the shadow value if one was passed by the devicetree */ + shadow = of_get_property(pdev->dev.of_node, "lantiq,shadow", NULL); + if (shadow) + chip->shadow = *shadow; + + /* find out which gpio groups should be enabled */ + groups = of_get_property(pdev->dev.of_node, "lantiq,groups", NULL); + if (groups) + chip->groups = *groups & XWAY_STP_GROUP_MASK; + else + chip->groups = XWAY_STP_GROUP0; + chip->gc.ngpio = fls(chip->groups) * 8; + + /* find out which gpios are controlled by the dsl core */ + dsl = of_get_property(pdev->dev.of_node, "lantiq,dsl", NULL); + if (dsl) + chip->dsl = *dsl & XWAY_STP_ADSL_MASK; + + /* find out which gpios are controlled by the phys */ + if (of_machine_is_compatible("lantiq,ar9") || + of_machine_is_compatible("lantiq,gr9") || + of_machine_is_compatible("lantiq,vr9")) { + phy = of_get_property(pdev->dev.of_node, "lantiq,phy1", NULL); + if (phy) + chip->phy1 = *phy & XWAY_STP_PHY_MASK; + phy = of_get_property(pdev->dev.of_node, "lantiq,phy2", NULL); + if (phy) + chip->phy2 = *phy & XWAY_STP_PHY_MASK; + } + + /* check which edge trigger we should use, default to a falling edge */ + if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL)) + chip->edge = XWAY_STP_FALLING; + + clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Failed to get clock\n"); + return PTR_ERR(clk); + } + clk_enable(clk); + + ret = xway_stp_hw_init(chip); + if (!ret) + ret = gpiochip_add(&chip->gc); + + if (!ret) + dev_info(&pdev->dev, "Init done\n"); + + return ret; +} + +static const struct of_device_id xway_stp_match[] = { + { .compatible = "lantiq,gpio-stp-xway" }, + {}, +}; +MODULE_DEVICE_TABLE(of, xway_stp_match); + +static struct platform_driver xway_stp_driver = { + .probe = xway_stp_probe, + .driver = { + .name = "gpio-stp-xway", + .owner = THIS_MODULE, + .of_match_table = xway_stp_match, + }, +}; + +int __init xway_stp_init(void) +{ + return platform_driver_register(&xway_stp_driver); +} + +subsys_initcall(xway_stp_init); -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:20:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:23:16 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48630 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903684Ab2EDMUQ (ORCPT ); Fri, 4 May 2012 14:20:16 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Grant Likely , linux-kernel@vger.kernel.org Subject: [PATCH 09/14] GPIO: MIPS: lantiq: convert gpio-ebu to OF and move it to subsystem Date: Fri, 4 May 2012 14:18:34 +0200 Message-Id: <1336133919-26525-9-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33147 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 10493 Lines: 361 Implements OF support and moves the driver from arch/mips/lantiq/xway/ to the gpio subsystem. By attaching hardware latches to the External Bus Unit (EBU) on Lantiq SoC, it is possible to create output only gpios. This driver configures a special memory address, which when written to, outputs 16 bit to the latches. This driver makes use of of_mm_gpio. Signed-off-by: John Crispin Cc: Grant Likely Cc: linux-kernel@vger.kernel.org --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/gpio_ebu.c | 126 ------------------------------ drivers/gpio/Kconfig | 8 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-mm-lantiq.c | 157 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 167 insertions(+), 127 deletions(-) delete mode 100644 arch/mips/lantiq/xway/gpio_ebu.c create mode 100644 drivers/gpio/gpio-mm-lantiq.c diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 9c5d69f..729ea9e 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1 +1 @@ -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gpio_ebu.o +obj-y := prom.o sysctrl.o clk.o reset.o dma.o diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c deleted file mode 100644 index aae1717..0000000 --- a/arch/mips/lantiq/xway/gpio_ebu.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -/* - * By attaching hardware latches to the EBU it is possible to create output - * only gpios. This driver configures a special memory address, which when - * written to outputs 16 bit to the latches. - */ - -#define LTQ_EBU_BUSCON 0x1e7ff /* 16 bit access, slowest timing */ -#define LTQ_EBU_WP 0x80000000 /* write protect bit */ - -/* we keep a shadow value of the last value written to the ebu */ -static int ltq_ebu_gpio_shadow = 0x0; -static void __iomem *ltq_ebu_gpio_membase; - -static void ltq_ebu_apply(void) -{ - unsigned long flags; - - spin_lock_irqsave(&ebu_lock, flags); - ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1); - *((__u16 *)ltq_ebu_gpio_membase) = ltq_ebu_gpio_shadow; - ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1); - spin_unlock_irqrestore(&ebu_lock, flags); -} - -static void ltq_ebu_set(struct gpio_chip *chip, unsigned offset, int value) -{ - if (value) - ltq_ebu_gpio_shadow |= (1 << offset); - else - ltq_ebu_gpio_shadow &= ~(1 << offset); - ltq_ebu_apply(); -} - -static int ltq_ebu_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - ltq_ebu_set(chip, offset, value); - - return 0; -} - -static struct gpio_chip ltq_ebu_chip = { - .label = "ltq_ebu", - .direction_output = ltq_ebu_direction_output, - .set = ltq_ebu_set, - .base = 72, - .ngpio = 16, - .can_sleep = 1, - .owner = THIS_MODULE, -}; - -static int ltq_ebu_probe(struct platform_device *pdev) -{ - int ret = 0; - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - if (!res) { - dev_err(&pdev->dev, "failed to get memory resource\n"); - return -ENOENT; - } - - res = devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), dev_name(&pdev->dev)); - if (!res) { - dev_err(&pdev->dev, "failed to request memory resource\n"); - return -EBUSY; - } - - ltq_ebu_gpio_membase = devm_ioremap_nocache(&pdev->dev, res->start, - resource_size(res)); - if (!ltq_ebu_gpio_membase) { - dev_err(&pdev->dev, "Failed to ioremap mem region\n"); - return -ENOMEM; - } - - /* grab the default shadow value passed form the platform code */ - ltq_ebu_gpio_shadow = (unsigned int) pdev->dev.platform_data; - - /* tell the ebu controller which memory address we will be using */ - ltq_ebu_w32(pdev->resource->start | 0x1, LTQ_EBU_ADDRSEL1); - - /* write protect the region */ - ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1); - - ret = gpiochip_add(<q_ebu_chip); - if (!ret) - ltq_ebu_apply(); - return ret; -} - -static struct platform_driver ltq_ebu_driver = { - .probe = ltq_ebu_probe, - .driver = { - .name = "ltq_ebu", - .owner = THIS_MODULE, - }, -}; - -static int __init ltq_ebu_init(void) -{ - int ret = platform_driver_register(<q_ebu_driver); - - if (ret) - pr_info("ltq_ebu : Error registering platform driver!"); - return ret; -} - -postcore_initcall(ltq_ebu_init); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2ec6a3b..73da6bc 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -100,6 +100,14 @@ config GPIO_EP93XX depends on ARCH_EP93XX select GPIO_GENERIC +config GPIO_MM_LANTIQ + bool "Lantiq Memory mapped GPIOs" + depends on LANTIQ && SOC_XWAY + help + This enables support for memory mapped GPIOs on the External Bus Unit + (EBU) found on Lantiq SoCs. The gpios are output only as they are + created by attaching a 16bit latch to the bus. + config GPIO_MPC5200 def_bool y depends on PPC_MPC52xx diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ff85e12..239b290 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o +obj-$(CONFIG_GPIO_MM_LANTIQ) += gpio-mm-lantiq.o obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o obj-$(CONFIG_GPIO_MPC8XXX) += gpio-mpc8xxx.o obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o diff --git a/drivers/gpio/gpio-mm-lantiq.c b/drivers/gpio/gpio-mm-lantiq.c new file mode 100644 index 0000000..9296801 --- /dev/null +++ b/drivers/gpio/gpio-mm-lantiq.c @@ -0,0 +1,157 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * By attaching hardware latches to the EBU it is possible to create output + * only gpios. This driver configures a special memory address, which when + * written to outputs 16 bit to the latches. + */ + +#define LTQ_EBU_BUSCON 0x1e7ff /* 16 bit access, slowest timing */ +#define LTQ_EBU_WP 0x80000000 /* write protect bit */ + +struct ltq_mm { + struct of_mm_gpio_chip mmchip; + u16 shadow; /* shadow the latches state */ +}; + +/* + * ltq_mm_apply - write the shadow value to the ebu address. + * @chip: Pointer to our private data structure. + * + * Write the shadow value to the EBU to set the gpios. We need to set the + * global EBU lock to make sure that PCI/MTD dont break. + */ +static void ltq_mm_apply(struct ltq_mm *chip) +{ + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1); + *((__u16 *)chip->mmchip.regs) = chip->shadow; + ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1); + spin_unlock_irqrestore(&ebu_lock, flags); +} + +/* + * ltq_mm_set - gpio_chip->set - set gpios. + * @gc: Pointer to gpio_chip device structure. + * @gpio: GPIO signal number. + * @val: Value to be written to specified signal. + * + * Set the shadow value and call ltq_mm_apply. + */ +static void ltq_mm_set(struct gpio_chip *gc, unsigned offset, int value) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct ltq_mm *chip = + container_of(mm_gc, struct ltq_mm, mmchip); + + if (value) + chip->shadow |= (1 << offset); + else + chip->shadow &= ~(1 << offset); + ltq_mm_apply(chip); +} + +/* + * ltq_mm_dir_out - gpio_chip->dir_out - set gpio direction. + * @gc: Pointer to gpio_chip device structure. + * @gpio: GPIO signal number. + * @val: Value to be written to specified signal. + * + * Same as ltq_mm_set, always returns 0. + */ +static int ltq_mm_dir_out(struct gpio_chip *gc, unsigned offset, int value) +{ + ltq_mm_set(gc, offset, value); + + return 0; +} + +/* + * ltq_mm_save_regs - Set initial values of GPIO pins + * @mm_gc: pointer to memory mapped GPIO chip structure + */ +static void ltq_mm_save_regs(struct of_mm_gpio_chip *mm_gc) +{ + struct ltq_mm *chip = + container_of(mm_gc, struct ltq_mm, mmchip); + + /* tell the ebu controller which memory address we will be using */ + ltq_ebu_w32(CPHYSADDR(chip->mmchip.regs) | 0x1, LTQ_EBU_ADDRSEL1); + + ltq_mm_apply(chip); +} + +static int ltq_mm_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct ltq_mm *chip; + const __be32 *shadow; + int ret = 0; + + if (!res) { + dev_err(&pdev->dev, "failed to get memory resource\n"); + return -ENOENT; + } + + chip = kzalloc(sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->mmchip.gc.ngpio = 16; + chip->mmchip.gc.label = "gpio-mm-ltq"; + chip->mmchip.gc.direction_output = ltq_mm_dir_out; + chip->mmchip.gc.set = ltq_mm_set; + chip->mmchip.save_regs = ltq_mm_save_regs; + + /* store the shadow value if one was passed by the devicetree */ + shadow = of_get_property(pdev->dev.of_node, "lantiq,shadow", NULL); + if (shadow) + chip->shadow = *shadow; + + ret = of_mm_gpiochip_add(pdev->dev.of_node, &chip->mmchip); + if (ret) + kfree(chip); + return ret; +} + +static const struct of_device_id ltq_mm_match[] = { + { .compatible = "lantiq,gpio-mm" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ltq_mm_match); + +static struct platform_driver ltq_mm_driver = { + .probe = ltq_mm_probe, + .driver = { + .name = "gpio-mm-ltq", + .owner = THIS_MODULE, + .of_match_table = ltq_mm_match, + }, +}; + +static int __init ltq_mm_init(void) +{ + return platform_driver_register(<q_mm_driver); +} + +subsys_initcall(ltq_mm_init); -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:20:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:23:47 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48633 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903686Ab2EDMUQ (ORCPT ); Fri, 4 May 2012 14:20:16 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , devicetree-discuss@lists.ozlabs.org, Linus Walleij , Stephen Warren Subject: [PATCH 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support Date: Fri, 4 May 2012 14:18:29 +0200 Message-Id: <1336133919-26525-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33148 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 45628 Lines: 1617 Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by: John Crispin Cc: devicetree-discuss@lists.ozlabs.org Cc: Linus Walleij Cc: Stephen Warren --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. arch/mips/Kconfig | 1 + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 - arch/mips/lantiq/Kconfig | 1 + arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/gpio.c | 195 ------ arch/mips/lantiq/xway/gpio_stp.c | 5 - arch/mips/pci/pci-lantiq.c | 44 +-- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 2 + drivers/pinctrl/pinctrl-lantiq.c | 308 +++++++++ drivers/pinctrl/pinctrl-lantiq.h | 184 +++++ drivers/pinctrl/pinctrl-xway.c | 702 ++++++++++++++++++++ 12 files changed, 1209 insertions(+), 246 deletions(-) delete mode 100644 arch/mips/lantiq/xway/gpio.c create mode 100644 drivers/pinctrl/pinctrl-lantiq.c create mode 100644 drivers/pinctrl/pinctrl-lantiq.h create mode 100644 drivers/pinctrl/pinctrl-xway.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fbb5639..00a0482 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -216,6 +216,7 @@ config MACH_JZ4740 config LANTIQ bool "Lantiq based platforms" select DMA_NONCOHERENT + select PINCTRL select IRQ_CPU select CEVT_R4K select CSRC_R4K diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 15eb4dc..150c7be 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -153,8 +153,6 @@ #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) /* request a non-gpio and set the PIO config */ -extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, - unsigned int alt1, unsigned int dir, const char *name); extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index 9485fe5..b86d942 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -2,6 +2,7 @@ if LANTIQ config SOC_TYPE_XWAY bool + select PINCTRL_XWAY default n choice diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 7a6c30f..323b574 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1,4 @@ -obj-y := prom.o pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o dma.o +obj-y := prom.o pmu.o ebu.o reset.o gpio_stp.o gpio_ebu.o dma.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c deleted file mode 100644 index c429a5b..0000000 --- a/arch/mips/lantiq/xway/gpio.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include -#include - -#include - -#define LTQ_GPIO_OUT 0x00 -#define LTQ_GPIO_IN 0x04 -#define LTQ_GPIO_DIR 0x08 -#define LTQ_GPIO_ALTSEL0 0x0C -#define LTQ_GPIO_ALTSEL1 0x10 -#define LTQ_GPIO_OD 0x14 - -#define PINS_PER_PORT 16 -#define MAX_PORTS 3 - -#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) -#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) -#define ltq_gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r) - -struct ltq_gpio { - void __iomem *membase; - struct gpio_chip chip; -}; - -static struct ltq_gpio ltq_gpio_port[MAX_PORTS]; - -int gpio_to_irq(unsigned int gpio) -{ - return -EINVAL; -} -EXPORT_SYMBOL(gpio_to_irq); - -int irq_to_gpio(unsigned int gpio) -{ - return -EINVAL; -} -EXPORT_SYMBOL(irq_to_gpio); - -int ltq_gpio_request(unsigned int pin, unsigned int alt0, - unsigned int alt1, unsigned int dir, const char *name) -{ - int id = 0; - - if (pin >= (MAX_PORTS * PINS_PER_PORT)) - return -EINVAL; - if (gpio_request(pin, name)) { - pr_err("failed to setup lantiq gpio: %s\n", name); - return -EBUSY; - } - if (dir) - gpio_direction_output(pin, 1); - else - gpio_direction_input(pin); - while (pin >= PINS_PER_PORT) { - pin -= PINS_PER_PORT; - id++; - } - if (alt0) - ltq_gpio_setbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL0, pin); - else - ltq_gpio_clearbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL0, pin); - if (alt1) - ltq_gpio_setbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL1, pin); - else - ltq_gpio_clearbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL1, pin); - return 0; -} -EXPORT_SYMBOL(ltq_gpio_request); - -static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - if (value) - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); - else - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); -} - -static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset); -} - -static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); - - return 0; -} - -static int ltq_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); - ltq_gpio_set(chip, offset, value); - - return 0; -} - -static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset); - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); - return 0; -} - -static int ltq_gpio_probe(struct platform_device *pdev) -{ - struct resource *res; - - if (pdev->id >= MAX_PORTS) { - dev_err(&pdev->dev, "invalid gpio port %d\n", - pdev->id); - return -EINVAL; - } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "failed to get memory for gpio port %d\n", - pdev->id); - return -ENOENT; - } - res = devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), dev_name(&pdev->dev)); - if (!res) { - dev_err(&pdev->dev, - "failed to request memory for gpio port %d\n", - pdev->id); - return -EBUSY; - } - ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev, - res->start, resource_size(res)); - if (!ltq_gpio_port[pdev->id].membase) { - dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n", - pdev->id); - return -ENOMEM; - } - ltq_gpio_port[pdev->id].chip.label = "ltq_gpio"; - ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input; - ltq_gpio_port[pdev->id].chip.direction_output = - ltq_gpio_direction_output; - ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get; - ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set; - ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req; - ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id; - ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; - platform_set_drvdata(pdev, <q_gpio_port[pdev->id]); - return gpiochip_add(<q_gpio_port[pdev->id].chip); -} - -static struct platform_driver -ltq_gpio_driver = { - .probe = ltq_gpio_probe, - .driver = { - .name = "ltq_gpio", - .owner = THIS_MODULE, - }, -}; - -int __init ltq_gpio_init(void) -{ - int ret = platform_driver_register(<q_gpio_driver); - - if (ret) - pr_info("ltq_gpio : Error registering platform driver!"); - return ret; -} - -postcore_initcall(ltq_gpio_init); diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index fd07d87..4f4bd61 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -78,11 +78,6 @@ static struct gpio_chip ltq_stp_chip = { static int ltq_stp_hw_init(void) { - /* the 3 pins used to control the external stp */ - ltq_gpio_request(4, 1, 0, 1, "stp-st"); - ltq_gpio_request(5, 1, 0, 1, "stp-d"); - ltq_gpio_request(6, 1, 0, 1, "stp-sh"); - /* sane defaults */ ltq_stp_w32(0, LTQ_STP_AR); ltq_stp_w32(0, LTQ_STP_CPU0); diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 70fdf2c..3418178 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -68,32 +68,6 @@ #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) -struct ltq_pci_gpio_map { - int pin; - int alt0; - int alt1; - int dir; - char *name; -}; - -/* the pci core can make use of the following gpios */ -static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = { - { 0, 1, 0, 0, "pci-exin0" }, - { 1, 1, 0, 0, "pci-exin1" }, - { 2, 1, 0, 0, "pci-exin2" }, - { 39, 1, 0, 0, "pci-exin3" }, - { 10, 1, 0, 0, "pci-exin4" }, - { 9, 1, 0, 0, "pci-exin5" }, - { 30, 1, 0, 1, "pci-gnt1" }, - { 23, 1, 0, 1, "pci-gnt2" }, - { 19, 1, 0, 1, "pci-gnt3" }, - { 38, 1, 0, 1, "pci-gnt4" }, - { 29, 1, 0, 0, "pci-req1" }, - { 31, 1, 0, 0, "pci-req2" }, - { 3, 1, 0, 0, "pci-req3" }, - { 37, 1, 0, 0, "pci-req4" }, -}; - __iomem void *ltq_pci_mapped_cfg; static __iomem void *ltq_pci_membase; @@ -151,22 +125,6 @@ static u32 ltq_calc_bar11mask(void) return bar11mask; } -static void ltq_pci_setup_gpio(int gpio) -{ - int i; - for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { - if (gpio & (1 << i)) { - ltq_gpio_request(ltq_pci_gpio_map[i].pin, - ltq_pci_gpio_map[i].alt0, - ltq_pci_gpio_map[i].alt1, - ltq_pci_gpio_map[i].dir, - ltq_pci_gpio_map[i].name); - } - } - ltq_gpio_request(21, 0, 0, 1, "pci-reset"); - ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; -} - static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) { u32 temp_buffer; @@ -192,7 +150,7 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) } /* setup pci clock and gpis used by pci */ - ltq_pci_setup_gpio(conf->gpio); + gpio_request(21, "pci-reset"); /* enable auto-switching between PCI and EBU */ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f73a5ea..a19bac96 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -30,6 +30,11 @@ config PINCTRL_PXA3xx bool select PINMUX +config PINCTRL_LANTIQ + bool + select PINMUX + select PINCONF + config PINCTRL_MMP2 bool "MMP2 pin controller driver" depends on ARCH_MMP @@ -83,6 +88,10 @@ config PINCTRL_COH901 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 ports of 8 GPIO pins each. +config PINCTRL_XWAY + bool + select PINCTRL_LANTIQ + endmenu endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8e3c95a..15bf5a3 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -19,3 +19,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o +obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o +obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c new file mode 100644 index 0000000..f2e28a5 --- /dev/null +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -0,0 +1,308 @@ +/* + * linux/drivers/pinctrl/pinctrl-lantiq.c + * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include "core.h" + +#include "pinctrl-lantiq.h" + +static int ltq_get_group_count(struct pinctrl_dev *pctrldev) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + return info->num_grps; +} + +static const char *ltq_get_group_name(struct pinctrl_dev *pctrldev, + unsigned selector) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + if (selector >= info->num_grps) + return NULL; + return info->grps[selector].name; +} + +static int ltq_get_group_pins(struct pinctrl_dev *pctrldev, + unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + if (selector >= info->num_grps) + return -EINVAL; + *pins = info->grps[selector].pins; + *num_pins = info->grps[selector].npins; + return 0; +} + +void ltq_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + kfree(map); +} + +static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); + unsigned long configs[3]; + unsigned num_configs = 0; + struct property *prop; + const char *group, *pin; + const char *function; + int ret, i; + + ret = of_property_read_string(np, "lantiq,function", &function); + if (!ret) { + of_property_for_each_string(np, "lantiq,groups", prop, group) { + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->name = function; + (*map)->data.mux.group = group; + (*map)->data.mux.function = function; + (*map)++; + } + if (of_find_property(np, "lantiq,pins", NULL)) + dev_err(pctldev->dev, + "%s mixes pins and groups settings\n", + np->name); + return 0; + } + + for (i = 0; i < info->num_params; i++) { + u32 val; + int ret = of_property_read_u32(np, + info->params[i].property, &val); + if (!ret) + configs[num_configs++] = + LTQ_PINCONF_PACK(info->params[i].param, + val); + } + + if (!num_configs) + return -EINVAL; + + of_property_for_each_string(np, "lantiq,pins", prop, pin) { + (*map)->data.configs.configs = kmemdup(configs, + num_configs * sizeof(unsigned long), + GFP_KERNEL); + (*map)->type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)->name = pin; + (*map)->data.configs.group_or_pin = pin; + (*map)->data.configs.num_configs = num_configs; + (*map)++; + } + return 0; +} + +static int ltq_pinctrl_dt_subnode_size(struct device_node *np) +{ + int ret; + + ret = of_property_count_strings(np, "lantiq,groups"); + if (ret < 0) + ret = of_property_count_strings(np, "lantiq,pins"); + return ret; +} + +int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct pinctrl_map *tmp; + struct device_node *np; + int ret; + + *num_maps = 0; + for_each_child_of_node(np_config, np) + *num_maps += ltq_pinctrl_dt_subnode_size(np); + *map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL); + tmp = *map; + + for_each_child_of_node(np_config, np) { + ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp); + if (ret < 0) { + ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + return 0; +} + +static struct pinctrl_ops ltq_pctrl_ops = { + .get_groups_count = ltq_get_group_count, + .get_group_name = ltq_get_group_name, + .get_group_pins = ltq_get_group_pins, + .pin_dbg_show = ltq_pinctrl_pin_dbg_show, + .dt_node_to_map = ltq_pinctrl_dt_node_to_map, + .dt_free_map = ltq_pinctrl_dt_free_map, +}; + +static int ltq_pmx_func_count(struct pinctrl_dev *pctrldev) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + + return info->num_funcs; +} + +static const char *ltq_pmx_func_name(struct pinctrl_dev *pctrldev, + unsigned selector) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + + if (selector >= info->num_funcs) + return NULL; + + return info->funcs[selector].name; +} + +static int ltq_pmx_get_groups(struct pinctrl_dev *pctrldev, + unsigned func, + const char * const **groups, + unsigned * const num_groups) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + + *groups = info->funcs[func].groups; + *num_groups = info->funcs[func].num_groups; + + return 0; +} + +/* Return function number. If failure, return negative value. */ +static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux) +{ + int i; + for (i = 0; i < LTQ_MAX_MUX; i++) { + if (mfp->func[i] == mux) + break; + } + if (i >= LTQ_MAX_MUX) + return -EINVAL; + return i; +} + +/* check whether current pin configuration is valid. Negative for failure */ +static int match_group_mux(const struct ltq_pin_group *grp, + const struct ltq_pinmux_info *info, + unsigned mux) +{ + int i, pin, ret = 0; + for (i = 0; i < grp->npins; i++) { + pin = grp->pins[i]; + ret = match_mux(&info->mfp[pin], mux); + if (ret < 0) { + dev_err(info->dev, "Can't find mux %d on pin%d\n", + mux, pin); + break; + } + } + return ret; +} + +static int ltq_pmx_enable(struct pinctrl_dev *pctrldev, + unsigned func, + unsigned group) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + const struct ltq_pin_group *pin_grp = &info->grps[group]; + int i, pin, pin_func; + + if (!pin_grp->npins || + (match_group_mux(pin_grp, info, pin_grp->mux) < 0)) { + dev_err(info->dev, "Failed to set the pin group: %s\n", + info->grps[group].name); + return -EINVAL; + } + for (i = 0; i < pin_grp->npins; i++) { + pin = pin_grp->pins[i]; + pin_func = match_mux(&info->mfp[pin], pin_grp->mux); + info->apply_mux(pctrldev, pin, pin_func); + } + return 0; +} + +static void ltq_pmx_disable(struct pinctrl_dev *pctrldev, + unsigned func, + unsigned group) +{ +} + +static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + int pin_func; + + /* all our pins are gpio when muxing is set to 0. check anyhow */ + pin_func = match_mux(&info->mfp[pin], 0); + if (pin_func < 0) { + dev_err(info->dev, "No GPIO function on pin%d\n", pin); + return -EINVAL; + } + + info->apply_mux(pctrldev, pin, 0); + + return 0; +} + +static struct pinmux_ops ltq_pmx_ops = { + .get_functions_count = ltq_pmx_func_count, + .get_function_name = ltq_pmx_func_name, + .get_function_groups = ltq_pmx_get_groups, + .enable = ltq_pmx_enable, + .disable = ltq_pmx_disable, + .gpio_request_enable = ltq_pmx_gpio_request_enable, +}; + +/* + * allow different socs to register with the generic part of the lanti + * pinctrl code + */ +int ltq_pinctrl_register(struct platform_device *pdev, + struct ltq_pinmux_info *info) +{ + struct pinctrl_desc *desc; + + if (!info) + return -EINVAL; + desc = info->desc; + desc->pctlops = <q_pctrl_ops; + desc->pmxops = <q_pmx_ops; + info->dev = &pdev->dev; + + info->pctrl = pinctrl_register(desc, &pdev->dev, info); + if (!info->pctrl) { + dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n"); + return -EINVAL; + } + platform_set_drvdata(pdev, info); + return 0; +} diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h new file mode 100644 index 0000000..dc84c09 --- /dev/null +++ b/drivers/pinctrl/pinctrl-lantiq.h @@ -0,0 +1,184 @@ +/* + * linux/drivers/pinctrl/pinctrl-lantiq.h + * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#ifndef __PINCTRL_LANTIQ_H + +#include +#include +#include +#include +#include + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +#define LTQ_MAX_MUX 4 +#define MFPR_FUNC_MASK 0x3 + +#define LTQ_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) +#define LTQ_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) +#define LTQ_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) + +enum ltq_pinconf_param { + LTQ_PINCONF_PARAM_PULL, + LTQ_PINCONF_PARAM_OPEN_DRAIN, + LTQ_PINCONF_PARAM_DRIVE_CURRENT, + LTQ_PINCONF_PARAM_SLEW_RATE, +}; + +struct ltq_cfg_param { + const char *property; + enum ltq_pinconf_param param; +}; + +struct ltq_mfp_pin { + const char *name; + const unsigned int pin; + const unsigned short func[LTQ_MAX_MUX]; +}; + +struct ltq_pin_group { + const char *name; + const unsigned mux; + const unsigned *pins; + const unsigned npins; +}; + +struct ltq_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; +}; + +struct ltq_pinmux_info { + struct device *dev; + struct pinctrl_dev *pctrl; + + /* we need to manage up to 5 padcontrolers */ + void __iomem *membase[5]; + + /* the handler for the subsystem */ + struct pinctrl_desc *desc; + + /* we expose our pads to the subsystem */ + struct pinctrl_pin_desc *pads; + + /* the number of pads. this varies between socs */ + unsigned int num_gpio; + + /* these are our multifunction pins */ + const struct ltq_mfp_pin *mfp; + unsigned int num_mfp; + + /* a number of multifunction pins can be grouped together */ + const struct ltq_pin_group *grps; + unsigned int num_grps; + + /* a mapping between function string and id */ + const struct ltq_pmx_func *funcs; + unsigned int num_funcs; + + /* the pinconf options that we are able to read from the DT */ + const struct ltq_cfg_param *params; + unsigned int num_params; + + /* soc specific callback used to apply muxing */ + int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux); +}; + +enum ltq_pin_list { + GPIO0 = 0, + GPIO1, + GPIO2, + GPIO3, + GPIO4, + GPIO5, + GPIO6, + GPIO7, + GPIO8, + GPIO9, + GPIO10, /* 10 */ + GPIO11, + GPIO12, + GPIO13, + GPIO14, + GPIO15, + GPIO16, + GPIO17, + GPIO18, + GPIO19, + GPIO20, /* 20 */ + GPIO21, + GPIO22, + GPIO23, + GPIO24, + GPIO25, + GPIO26, + GPIO27, + GPIO28, + GPIO29, + GPIO30, /* 30 */ + GPIO31, + GPIO32, + GPIO33, + GPIO34, + GPIO35, + GPIO36, + GPIO37, + GPIO38, + GPIO39, + GPIO40, /* 40 */ + GPIO41, + GPIO42, + GPIO43, + GPIO44, + GPIO45, + GPIO46, + GPIO47, + GPIO48, + GPIO49, + GPIO50, /* 50 */ + GPIO51, + GPIO52, + GPIO53, + GPIO54, + GPIO55, + + GPIO64, + GPIO65, + GPIO66, + GPIO67, + GPIO68, + GPIO69, + GPIO70, + GPIO71, + GPIO72, + GPIO73, + GPIO74, + GPIO75, + GPIO76, + GPIO77, + GPIO78, + GPIO79, + GPIO80, + GPIO81, + GPIO82, + GPIO83, + GPIO84, + GPIO85, + GPIO86, + GPIO87, + GPIO88, +}; + +extern int ltq_pinctrl_register(struct platform_device *pdev, + struct ltq_pinmux_info *info); +extern int ltq_pinctrl_unregister(struct platform_device *pdev); +#endif /* __PINCTRL_PXA3XX_H */ diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c new file mode 100644 index 0000000..efc3174 --- /dev/null +++ b/drivers/pinctrl/pinctrl-xway.c @@ -0,0 +1,702 @@ +/* + * linux/drivers/pinctrl/pinmux-xway.c + * based on linux/drivers/pinctrl/pinmux-pxa910.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-lantiq.h" + +#include + +/* we have 3 1/2 banks of 16 bit each */ +#define PINS 16 +#define PORT(x) (x / PINS) +#define PORT_PIN(x) (x % PINS) + +/* + * each bank has this offset apart from the 1/2 bank that is mixed into the + * other 3 ranges + */ +#define REG_OFF 0x30 + +/* these are the offsets to our registers */ +#define GPIO_BASE(p) (REG_OFF * PORT(p)) +#define GPIO_OUT(p) GPIO_BASE(p) +#define GPIO_IN(p) (GPIO_BASE(p) + 0x04) +#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08) +#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C) +#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10) +#define GPIO_OD(p) (GPIO_BASE(p) + 0x14) +#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c) +#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20) + +/* the 1/2 port needs special offsets for some registers */ +#define GPIO3_OD (GPIO_BASE(0) + 0x24) +#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28) +#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C) +#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24) + +/* PORT3 only has 8 pins and its register layout + is slightly different */ +#define PINS_PER_PORT 16 +#define PINS_PORT3 8 +#define MAX_PORTS 4 +#define MAX_PIN 56 + +/* macros to help us access the registers */ +#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) +#define gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) +#define gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r) + +#define MFP_XWAY(a, f0, f1, f2, f3) \ + { \ + .name = #a, \ + .pin = a, \ + .func = { \ + XWAY_MUX_##f0, \ + XWAY_MUX_##f1, \ + XWAY_MUX_##f2, \ + XWAY_MUX_##f3, \ + }, \ + } + +#define GRP_MUX(a, m, p) \ + { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), } + +#define FUNC_MUX(f, m) \ + { .func = f, .mux = XWAY_MUX_##m, } + +enum xway_mux { + XWAY_MUX_GPIO = 0, + XWAY_MUX_SPI, + XWAY_MUX_ASC, + XWAY_MUX_PCI, + XWAY_MUX_CGU, + XWAY_MUX_EBU, + XWAY_MUX_JTAG, + XWAY_MUX_EXIN, + XWAY_MUX_TDM, + XWAY_MUX_STP, + XWAY_MUX_SIN, + XWAY_MUX_GPT, + XWAY_MUX_NMI, + XWAY_MUX_NONE = 0xffff, +}; + +static const struct ltq_mfp_pin xway_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM), + MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE), + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE), + MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI), + MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC), + MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE), + MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), + MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE), + MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), + MFP_XWAY(GPIO9, GPIO, ASC, SPI, NONE), + MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE), + MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI), + MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE), + MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE), + MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE), + MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE), + MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG), + MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG), + MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG), + MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE), + MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT), + MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE), + MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP), + MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI), + MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC), + MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM), + MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC), + MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE), + MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE), + MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU), + MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE), + MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO42, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO43, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), + MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE), +}; + +static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35}; +static const unsigned pins_asc0[] = {GPIO11, GPIO12}; +static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10}; +static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6}; +static const unsigned pins_nmi[] = {GPIO8}; + +static const unsigned pins_ebu_a24[] = {GPIO13}; +static const unsigned pins_ebu_clk[] = {GPIO21}; +static const unsigned pins_ebu_cs1[] = {GPIO23}; +static const unsigned pins_ebu_a23[] = {GPIO24}; +static const unsigned pins_ebu_wait[] = {GPIO26}; +static const unsigned pins_ebu_a25[] = {GPIO31}; +static const unsigned pins_ebu_rdy[] = {GPIO48}; +static const unsigned pins_ebu_rd[] = {GPIO49}; + +static const unsigned pins_nand_ale[] = {GPIO13}; +static const unsigned pins_nand_cs1[] = {GPIO23}; +static const unsigned pins_nand_cle[] = {GPIO24}; +static const unsigned pins_nand_rdy[] = {GPIO48}; +static const unsigned pins_nand_rd[] = {GPIO49}; + +static const unsigned pins_exin0[] = {GPIO0}; +static const unsigned pins_exin1[] = {GPIO1}; +static const unsigned pins_exin2[] = {GPIO2}; +static const unsigned pins_exin3[] = {GPIO39}; +static const unsigned pins_exin4[] = {GPIO46}; + +static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18}; +static const unsigned pins_spi_cs1[] = {GPIO15}; +static const unsigned pins_spi_cs2[] = {GPIO21}; +static const unsigned pins_spi_cs3[] = {GPIO13}; +static const unsigned pins_spi_cs4[] = {GPIO10}; +static const unsigned pins_spi_cs5[] = {GPIO9}; +static const unsigned pins_spi_cs6[] = {GPIO11}; + +static const unsigned pins_gpt1[] = {GPIO28}; +static const unsigned pins_gpt2[] = {GPIO21}; +static const unsigned pins_gpt3[] = {GPIO6}; + +static const unsigned pins_clkout0[] = {GPIO8}; +static const unsigned pins_clkout1[] = {GPIO7}; +static const unsigned pins_clkout2[] = {GPIO3}; +static const unsigned pins_clkout3[] = {GPIO2}; + +static const unsigned pins_pci_gnt1[] = {GPIO30}; +static const unsigned pins_pci_gnt2[] = {GPIO23}; +static const unsigned pins_pci_gnt3[] = {GPIO19}; +static const unsigned pins_pci_gnt4[] = {GPIO38}; +static const unsigned pins_pci_req1[] = {GPIO29}; +static const unsigned pins_pci_req2[] = {GPIO31}; +static const unsigned pins_pci_req3[] = {GPIO3}; +static const unsigned pins_pci_req4[] = {GPIO37}; + +static const struct ltq_pin_group xway_grps[] = { + GRP_MUX("exin0", EXIN, pins_exin0), + GRP_MUX("exin1", EXIN, pins_exin1), + GRP_MUX("exin2", EXIN, pins_exin2), + GRP_MUX("jtag", JTAG, pins_jtag), + GRP_MUX("ebu a23", EBU, pins_ebu_a23), + GRP_MUX("ebu a24", EBU, pins_ebu_a24), + GRP_MUX("ebu a25", EBU, pins_ebu_a25), + GRP_MUX("ebu clk", EBU, pins_ebu_clk), + GRP_MUX("ebu cs1", EBU, pins_ebu_cs1), + GRP_MUX("ebu wait", EBU, pins_ebu_wait), + GRP_MUX("nand ale", EBU, pins_nand_ale), + GRP_MUX("nand cs1", EBU, pins_nand_cs1), + GRP_MUX("nand cle", EBU, pins_nand_cle), + GRP_MUX("spi", SPI, pins_spi), + GRP_MUX("spi_cs1", SPI, pins_spi_cs1), + GRP_MUX("spi_cs2", SPI, pins_spi_cs2), + GRP_MUX("spi_cs3", SPI, pins_spi_cs3), + GRP_MUX("spi_cs4", SPI, pins_spi_cs4), + GRP_MUX("spi_cs5", SPI, pins_spi_cs5), + GRP_MUX("spi_cs6", SPI, pins_spi_cs6), + GRP_MUX("asc0", ASC, pins_asc0), + GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts), + GRP_MUX("stp", STP, pins_stp), + GRP_MUX("nmi", NMI, pins_nmi), + GRP_MUX("gpt1", GPT, pins_gpt1), + GRP_MUX("gpt2", GPT, pins_gpt2), + GRP_MUX("gpt3", GPT, pins_gpt3), + GRP_MUX("clkout0", CGU, pins_clkout0), + GRP_MUX("clkout1", CGU, pins_clkout1), + GRP_MUX("clkout2", CGU, pins_clkout2), + GRP_MUX("clkout3", CGU, pins_clkout3), + GRP_MUX("gnt1", PCI, pins_pci_gnt1), + GRP_MUX("gnt2", PCI, pins_pci_gnt2), + GRP_MUX("gnt3", PCI, pins_pci_gnt3), + GRP_MUX("req1", PCI, pins_pci_req1), + GRP_MUX("req2", PCI, pins_pci_req2), + GRP_MUX("req3", PCI, pins_pci_req3), +/* xrx only */ + GRP_MUX("nand rdy", EBU, pins_nand_rdy), + GRP_MUX("nand rd", EBU, pins_nand_rd), + GRP_MUX("exin3", EXIN, pins_exin3), + GRP_MUX("exin4", EXIN, pins_exin4), + GRP_MUX("gnt4", PCI, pins_pci_gnt4), + GRP_MUX("req4", PCI, pins_pci_gnt4), +}; + +static const char * const xway_pci_grps[] = {"gnt1", "gnt2", + "gnt3", "req1", + "req2", "req3"}; +static const char * const xway_spi_grps[] = {"spi", "spi_cs1", + "spi_cs2", "spi_cs3", + "spi_cs4", "spi_cs5", + "spi_cs6"}; +static const char * const xway_cgu_grps[] = {"clkout0", "clkout1", + "clkout2", "clkout3"}; +static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24", + "ebu a25", "ebu cs1", + "ebu wait", "ebu clk", + "nand ale", "nand cs1", + "nand cle"}; +static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"}; +static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; +static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"}; +static const char * const xway_jtag_grps[] = {"jtag"}; +static const char * const xway_stp_grps[] = {"stp"}; +static const char * const xway_nmi_grps[] = {"nmi"}; + +/* ar9/vr9/gr9 */ +static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24", + "ebu a25", "ebu cs1", + "ebu wait", "ebu clk", + "nand ale", "nand cs1", + "nand cle", "nand rdy", + "nand rd"}; +static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2", + "exin3", "exin4"}; +static const char * const xrx_pci_grps[] = {"gnt1", "gnt2", + "gnt3", "gnt4", + "req1", "req2", + "req3", "req4"}; + +static const struct ltq_pmx_func danube_funcs[] = { + {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, + {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, + {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, + {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, + {"exin", ARRAY_AND_SIZE(xway_exin_grps)}, + {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, + {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, + {"pci", ARRAY_AND_SIZE(xway_pci_grps)}, + {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)}, +}; + +static const struct ltq_pmx_func xrx_funcs[] = { + {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, + {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, + {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, + {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, + {"exin", ARRAY_AND_SIZE(xrx_exin_grps)}, + {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, + {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, + {"pci", ARRAY_AND_SIZE(xrx_pci_grps)}, + {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)}, +}; + + + + + + +/* --------- pinconf related code --------- */ +static int xway_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + return -ENOTSUPP; +} + +static int xway_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long config) +{ + return -ENOTSUPP; +} + +static int xway_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); + enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); + int port = PORT(pin); + u32 reg; + + switch (param) { + case LTQ_PINCONF_PARAM_OPEN_DRAIN: + if (port == 3) + reg = GPIO3_OD; + else + reg = GPIO_OD(port); + *config = LTQ_PINCONF_PACK(param, + !!gpio_getbit(info->membase[0], reg, PORT_PIN(port))); + break; + + case LTQ_PINCONF_PARAM_PULL: + if (port == 3) + reg = GPIO3_PUDEN; + else + reg = GPIO_PUDEN(port); + if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) { + *config = LTQ_PINCONF_PACK(param, 0); + break; + } + + if (port == 3) + reg = GPIO3_PUDSEL; + else + reg = GPIO_PUDSEL(port); + if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) + *config = LTQ_PINCONF_PACK(param, 2); + else + *config = LTQ_PINCONF_PACK(param, 1); + break; + + default: + pr_err("%s: Invalid config param %04x\n", + pinctrl_dev_get_name(pctldev), param); + return -ENOTSUPP; + } + return 0; +} + +static int xway_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long config) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); + enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); + int arg = LTQ_PINCONF_UNPACK_ARG(config); + int port = PORT(pin); + u32 reg; + + switch (param) { + case LTQ_PINCONF_PARAM_OPEN_DRAIN: + if (port == 3) + reg = GPIO3_OD; + else + reg = GPIO_OD(port); + gpio_setbit(info->membase[0], reg, PORT_PIN(port)); + break; + + case LTQ_PINCONF_PARAM_PULL: + if (port == 3) + reg = GPIO3_PUDEN; + else + reg = GPIO_PUDEN(port); + if (arg == 0) { + gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); + break; + } + gpio_setbit(info->membase[0], reg, PORT_PIN(port)); + + if (port == 3) + reg = GPIO3_PUDSEL; + else + reg = GPIO_PUDSEL(port); + if (arg == 1) + gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); + else if (arg == 2) + gpio_setbit(info->membase[0], reg, PORT_PIN(port)); + else + pr_err("%s: Invalid pull value %d\n", + pinctrl_dev_get_name(pctldev), arg); + break; + + default: + pr_err("%s: Invalid config param %04x\n", + pinctrl_dev_get_name(pctldev), param); + return -ENOTSUPP; + } + return 0; +} + +static void xway_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned offset) +{ +} + +static void xway_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned selector) +{ +} + +struct pinconf_ops xway_pinconf_ops = { + .pin_config_get = xway_pinconf_get, + .pin_config_set = xway_pinconf_set, + .pin_config_group_get = xway_pinconf_group_get, + .pin_config_group_set = xway_pinconf_group_set, + .pin_config_dbg_show = xway_pinconf_dbg_show, + .pin_config_group_dbg_show = xway_pinconf_group_dbg_show, +}; + +static struct pinctrl_desc xway_pctrl_desc = { + .owner = THIS_MODULE, + .confops = &xway_pinconf_ops, +}; + +static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, + int pin, int mux) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + int port = PORT(pin); + + if (mux & 0x1) + gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); + + if ((port == 3) && (mux & 0x2)) + gpio_setbit(info->membase[0], GPIO3_ALT1, PORT_PIN(pin)); + else if (mux & 0x2) + gpio_setbit(info->membase[0], GPIO_ALT1(pin), PORT_PIN(pin)); + else if (port == 3) + gpio_clearbit(info->membase[0], GPIO3_ALT1, PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], GPIO_ALT1(pin), PORT_PIN(pin)); + + return 0; +} + +static const struct ltq_cfg_param xway_cfg_params[] = { + {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, + {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN}, +}; + +static struct ltq_pinmux_info xway_info = { + .mfp = xway_mfp, + .desc = &xway_pctrl_desc, + .apply_mux = xway_mux_apply, + .params = xway_cfg_params, + .num_params = ARRAY_SIZE(xway_cfg_params), +}; + + + + +/* --------- gpio_chip related code --------- */ + +int gpio_to_irq(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(gpio_to_irq); + +int irq_to_gpio(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(irq_to_gpio); + +static inline int xway_gpio_pin_count(void) +{ + if (of_machine_is_compatible("lantiq,ar9") || + of_machine_is_compatible("lantiq,gr9") || + of_machine_is_compatible("lantiq,vr9")) + return 56; + return 32; +} + +static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + if (val) + gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); +} + +static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); +} + +static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); + + return 0; +} + +static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); + xway_gpio_set(chip, pin, val); + + return 0; +} + +static int xway_gpio_req(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + return pinctrl_request_gpio(gpio); +} + +static void xway_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + pinctrl_free_gpio(gpio); +} + +static struct gpio_chip xway_chip = { + .label = "gpio-xway", + .direction_input = xway_gpio_dir_in, + .direction_output = xway_gpio_dir_out, + .get = xway_gpio_get, + .set = xway_gpio_set, + .request = xway_gpio_req, + .free = xway_gpio_free, + .base = 0, +}; + + + + +/* --------- register the pinctrl layer --------- */ + +static struct pinctrl_gpio_range xway_gpio_range = { + .name = "XWAY GPIO", + .id = 0, + .base = 0, + .gc = &xway_chip, +}; + +static int __devinit pinmux_xway_probe(struct platform_device *pdev) +{ + struct resource *res; + int ret, i; + + /* get and remap our register range */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Failed to get resource\n"); + return -ENOENT; + } + xway_info.membase[0] = devm_request_and_ioremap(&pdev->dev, res); + if (!xway_info.membase[0]) { + dev_err(&pdev->dev, "Failed to remap resource\n"); + return -ENOMEM; + } + + /* find out how many pads we have */ + xway_chip.ngpio = xway_gpio_pin_count(); + + /* load our pad descriptors */ + xway_info.pads = devm_kzalloc(&pdev->dev, + sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio, + GFP_KERNEL); + if (!xway_info.pads) { + dev_err(&pdev->dev, "Failed to allocate pads\n"); + return -ENOMEM; + } + for (i = 0; i < xway_chip.ngpio; i++) { + /* strlen("ioXY") + 1 = 5 */ + char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL); + + if (!name) { + dev_err(&pdev->dev, "Failed to allocate pad name\n"); + return -ENOMEM; + } + snprintf(name, 5, "io%d", i); + xway_info.pads[i].number = GPIO0 + i; + xway_info.pads[i].name = name; + } + xway_pctrl_desc.pins = xway_info.pads; + + /* load the gpio chip */ + xway_chip.dev = &pdev->dev; + of_gpiochip_add(&xway_chip); + ret = gpiochip_add(&xway_chip); + if (ret) { + dev_err(&pdev->dev, "Failed to register gpio chip\n"); + return ret; + } + + /* setup the data needed by pinctrl */ + xway_pctrl_desc.name = dev_name(&pdev->dev); + xway_pctrl_desc.npins = xway_chip.ngpio; + + xway_info.num_gpio = xway_chip.ngpio; + xway_info.num_mfp = xway_chip.ngpio; + xway_info.grps = xway_grps; + xway_info.num_grps = ARRAY_SIZE(xway_grps); + if (xway_gpio_pin_count() == 56) { + xway_info.funcs = xrx_funcs; + xway_info.num_funcs = ARRAY_SIZE(xrx_funcs); + } else { + xway_info.funcs = danube_funcs; + xway_info.num_funcs = ARRAY_SIZE(danube_funcs); + } + + /* register with the generic lantiq layer */ + ret = ltq_pinctrl_register(pdev, &xway_info); + if (ret) { + dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); + return ret; + } + + /* finish with registering the gpio range in pinctrl */ + xway_gpio_range.npins = xway_chip.ngpio; + pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range); + dev_info(&pdev->dev, "Init done\n"); + return 0; +} + +static const struct of_device_id xway_match[] = { + { .compatible = "lantiq,pinctrl-xway" }, + {}, +}; +MODULE_DEVICE_TABLE(of, xway_match); + +static struct platform_driver pinmux_xway_driver = { + .probe = pinmux_xway_probe, + .driver = { + .name = "pinctrl-xway", + .owner = THIS_MODULE, + .of_match_table = xway_match, + }, +}; + +static int __init pinmux_xway_init(void) +{ + return platform_driver_register(&pinmux_xway_driver); +} + +core_initcall_sync(pinmux_xway_init); -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:20:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:24:12 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:48639 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903766Ab2EDMUR (ORCPT ); Fri, 4 May 2012 14:20:17 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Alan Cox , linux-serial@vger.kernel.org Subject: [PATCH 10/14] SERIAL: MIPS: lantiq: implement OF support Date: Fri, 4 May 2012 14:18:35 +0200 Message-Id: <1336133919-26525-10-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33149 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5669 Lines: 192 Add devicetree and handling for our new clkdev clocks. The patch is rather straightforward. .of_match_table is set and the 3 irqs are now loaded from the devicetree. This series converts the lantiq target to clkdev amongst other things. The driver needs to handle two clocks now. The fpi bus clock used to derive the divider and the clock gate needed on some socs to make the secondary port work. Signed-off-by: John Crispin Cc: Alan Cox Cc: linux-serial@vger.kernel.org --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. drivers/tty/serial/lantiq.c | 83 ++++++++++++++++++++++++++---------------- 1 files changed, 51 insertions(+), 32 deletions(-) diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index 96c1cac..b5044fa 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -31,16 +31,19 @@ #include #include #include -#include +#include +#include +#include #include #include +#include #include #define PORT_LTQ_ASC 111 #define MAXPORTS 2 #define UART_DUMMY_UER_RX 1 -#define DRVNAME "ltq_asc" +#define DRVNAME "lantiq,asc" #ifdef __BIG_ENDIAN #define LTQ_ASC_TBUF (0x0020 + 3) #define LTQ_ASC_RBUF (0x0024 + 3) @@ -114,6 +117,9 @@ static DEFINE_SPINLOCK(ltq_asc_lock); struct ltq_uart_port { struct uart_port port; + /* clock used to derive divider */ + struct clk *fpiclk; + /* clock gating of the ASC core */ struct clk *clk; unsigned int tx_irq; unsigned int rx_irq; @@ -316,7 +322,9 @@ lqasc_startup(struct uart_port *port) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); int retval; - port->uartclk = clk_get_rate(ltq_port->clk); + if (ltq_port->clk) + clk_enable(ltq_port->clk); + port->uartclk = clk_get_rate(ltq_port->fpiclk); ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), port->membase + LTQ_ASC_CLC); @@ -382,6 +390,8 @@ lqasc_shutdown(struct uart_port *port) port->membase + LTQ_ASC_RXFCON); ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, port->membase + LTQ_ASC_TXFCON); + if (ltq_port->clk) + clk_disable(ltq_port->clk); } static void @@ -630,7 +640,7 @@ lqasc_console_setup(struct console *co, char *options) port = <q_port->port; - port->uartclk = clk_get_rate(ltq_port->clk); + port->uartclk = clk_get_rate(ltq_port->fpiclk); if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); @@ -668,37 +678,32 @@ static struct uart_driver lqasc_reg = { static int __init lqasc_probe(struct platform_device *pdev) { + struct device_node *node = pdev->dev.of_node; struct ltq_uart_port *ltq_port; struct uart_port *port; - struct resource *mmres, *irqres; - int tx_irq, rx_irq, err_irq; - struct clk *clk; + struct resource *mmres, irqres[3]; + int line = 0; int ret; mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); - irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!mmres || !irqres) + ret = of_irq_to_resource_table(node, irqres, 3); + if (!mmres || (ret != 3)) { + dev_err(&pdev->dev, + "failed to get memory/irq for serial port\n"); return -ENODEV; + } - if (pdev->id >= MAXPORTS) - return -EBUSY; + /* check if this is the console port */ + if (mmres->start != LTQ_ASC1_BASE_ADDR) + line = 1; - if (lqasc_port[pdev->id] != NULL) + if (lqasc_port[line]) { + dev_err(&pdev->dev, "port %d already allocated\n", line); return -EBUSY; - - clk = clk_get(&pdev->dev, "fpi"); - if (IS_ERR(clk)) { - pr_err("failed to get fpi clk\n"); - return -ENOENT; } - tx_irq = platform_get_irq_byname(pdev, "tx"); - rx_irq = platform_get_irq_byname(pdev, "rx"); - err_irq = platform_get_irq_byname(pdev, "err"); - if ((tx_irq < 0) | (rx_irq < 0) | (err_irq < 0)) - return -ENODEV; - - ltq_port = kzalloc(sizeof(struct ltq_uart_port), GFP_KERNEL); + ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port), + GFP_KERNEL); if (!ltq_port) return -ENOMEM; @@ -709,19 +714,26 @@ lqasc_probe(struct platform_device *pdev) port->ops = &lqasc_pops; port->fifosize = 16; port->type = PORT_LTQ_ASC, - port->line = pdev->id; + port->line = line; port->dev = &pdev->dev; - - port->irq = tx_irq; /* unused, just to be backward-compatibe */ + /* unused, just to be backward-compatible */ + port->irq = irqres[0].start; port->mapbase = mmres->start; - ltq_port->clk = clk; + ltq_port->fpiclk = clk_get_fpi(); + if (IS_ERR(ltq_port->fpiclk)) { + pr_err("failed to get fpi clk\n"); + return -ENOENT; + } - ltq_port->tx_irq = tx_irq; - ltq_port->rx_irq = rx_irq; - ltq_port->err_irq = err_irq; + /* not all asc ports have clock gates, lets ignore the return code */ + ltq_port->clk = clk_get(&pdev->dev, NULL); - lqasc_port[pdev->id] = ltq_port; + ltq_port->tx_irq = irqres[0].start; + ltq_port->rx_irq = irqres[1].start; + ltq_port->err_irq = irqres[2].start; + + lqasc_port[line] = ltq_port; platform_set_drvdata(pdev, ltq_port); ret = uart_add_one_port(&lqasc_reg, port); @@ -729,10 +741,17 @@ lqasc_probe(struct platform_device *pdev) return ret; } +static const struct of_device_id ltq_asc_match[] = { + { .compatible = DRVNAME }, + {}, +}; +MODULE_DEVICE_TABLE(of, ltq_asc_match); + static struct platform_driver lqasc_driver = { .driver = { .name = DRVNAME, .owner = THIS_MODULE, + .of_match_table = ltq_asc_match, }, }; -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:49:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:49:53 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:33954 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903664Ab2EDMtn (ORCPT ); Fri, 4 May 2012 14:49:43 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Wim Van Sebroeck , linux-watchdog@vger.kernel.org Subject: [PATCH 11/14] watchdog: MIPS: lantiq: implement OF support and minor fixes Date: Fri, 4 May 2012 14:18:36 +0200 Message-Id: <1336133919-26525-11-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33150 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5306 Lines: 170 Add support for OF. We also apply the following small fixes * reduce boiler plate by using devm_request_and_ioremap * sane error path for the clock * move LTQ_RST_CAUSE_WDTRST to a soc specific header file * add a message to show that the driver loaded Signed-off-by: John Crispin Cc: Wim Van Sebroeck Cc: linux-watchdog@vger.kernel.org --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. arch/mips/include/asm/mach-lantiq/lantiq.h | 1 - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 + drivers/watchdog/lantiq_wdt.c | 56 +++++++++----------- 3 files changed, 27 insertions(+), 32 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index c955e8d..161cce3 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -49,7 +49,6 @@ extern struct clk *clk_get_fpi(void); extern unsigned char ltq_boot_select(void); /* find out what caused the last cpu reset */ extern int ltq_reset_cause(void); -#define LTQ_RST_CAUSE_WDTRST 0x20 #define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index b5a2acf..d0d40a4 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -133,6 +133,8 @@ extern __iomem void *ltq_cgu_membase; #define LTQ_WDT_BASE_ADDR 0x1F8803F0 #define LTQ_WDT_SIZE 0x10 +#define LTQ_RST_CAUSE_WDTRST 0x20 + /* STP - serial to parallel conversion unit */ #define LTQ_STP_BASE_ADDR 0x1E100BB0 #define LTQ_STP_SIZE 0x40 diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c index a9593a3..f66a9e6 100644 --- a/drivers/watchdog/lantiq_wdt.c +++ b/drivers/watchdog/lantiq_wdt.c @@ -13,14 +13,15 @@ #include #include #include -#include +#include #include #include #include -#include +#include -/* Section 3.4 of the datasheet +/* + * Section 3.4 of the datasheet * The password sequence protects the WDT control register from unintended * write actions, which might cause malfunction of the WDT. * @@ -70,7 +71,8 @@ ltq_wdt_disable(void) { /* write the first password magic */ ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); - /* write the second password magic with no config + /* + * write the second password magic with no config * this turns the watchdog off */ ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR); @@ -184,7 +186,7 @@ static struct miscdevice ltq_wdt_miscdev = { .fops = <q_wdt_fops, }; -static int __init +static int __devinit ltq_wdt_probe(struct platform_device *pdev) { struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -194,28 +196,27 @@ ltq_wdt_probe(struct platform_device *pdev) dev_err(&pdev->dev, "cannot obtain I/O memory region"); return -ENOENT; } - res = devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), dev_name(&pdev->dev)); - if (!res) { - dev_err(&pdev->dev, "cannot request I/O memory region"); - return -EBUSY; - } - ltq_wdt_membase = devm_ioremap_nocache(&pdev->dev, res->start, - resource_size(res)); + + ltq_wdt_membase = devm_request_and_ioremap(&pdev->dev, res); if (!ltq_wdt_membase) { dev_err(&pdev->dev, "cannot remap I/O memory region\n"); return -ENOMEM; } /* we do not need to enable the clock as it is always running */ - clk = clk_get(&pdev->dev, "io"); - WARN_ON(!clk); + clk = clk_get_fpi(); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Failed to get clock\n"); + return -ENOENT; + } ltq_io_region_clk_rate = clk_get_rate(clk); clk_put(clk); + /* find out if the watchdog caused the last reboot */ if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST) ltq_wdt_bootstatus = WDIOF_CARDRESET; + dev_info(&pdev->dev, "Init done\n"); return misc_register(<q_wdt_miscdev); } @@ -227,33 +228,26 @@ ltq_wdt_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id ltq_wdt_match[] = { + { .compatible = "lantiq,wdt" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ltq_wdt_match); static struct platform_driver ltq_wdt_driver = { + .probe = ltq_wdt_probe, .remove = __devexit_p(ltq_wdt_remove), .driver = { - .name = "ltq_wdt", + .name = "wdt", .owner = THIS_MODULE, + .of_match_table = ltq_wdt_match, }, }; -static int __init -init_ltq_wdt(void) -{ - return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); -} - -static void __exit -exit_ltq_wdt(void) -{ - return platform_driver_unregister(<q_wdt_driver); -} - -module_init(init_ltq_wdt); -module_exit(exit_ltq_wdt); +module_platform_driver(ltq_wdt_driver); module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); - MODULE_AUTHOR("John Crispin "); MODULE_DESCRIPTION("Lantiq SoC Watchdog"); MODULE_LICENSE("GPL"); -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:50:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:50:17 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:33977 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903667Ab2EDMuJ (ORCPT ); Fri, 4 May 2012 14:50:09 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 14/14] MIPS: lantiq: remove orphaned code Date: Fri, 4 May 2012 14:18:39 +0200 Message-Id: <1336133919-26525-14-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33151 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 10899 Lines: 364 Now that all drivers are converted to OF we are able to remove some remaining pieces of orphaned code. Signed-off-by: John Crispin --- arch/mips/include/asm/mach-lantiq/lantiq.h | 6 -- .../mips/include/asm/mach-lantiq/lantiq_platform.h | 53 ----------- .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 46 +---------- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 93 +------------------- arch/mips/lantiq/prom.c | 6 -- arch/mips/lantiq/xway/sysctrl.c | 25 +---- 6 files changed, 7 insertions(+), 222 deletions(-) delete mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_platform.h diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index 161cce3..1aaf265 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -27,9 +27,6 @@ ltq_w32_mask(x, y, ltq_ebu_membase + (z)) extern __iomem void *ltq_ebu_membase; -extern unsigned int ltq_get_cpu_ver(void); -extern unsigned int ltq_get_soc_type(void); - /* spinlock all ebu i/o */ extern spinlock_t ebu_lock; @@ -43,7 +40,6 @@ extern int clk_activate(struct clk *clk); extern void clk_deactivate(struct clk *clk); extern struct clk *clk_get_cpu(void); extern struct clk *clk_get_fpi(void); -#define clk_get_io clk_get_fpi /* find out what bootsource we have */ extern unsigned char ltq_boot_select(void); @@ -54,7 +50,5 @@ extern int ltq_reset_cause(void); #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xffffffff -#define LTQ_FLASH_START 0x10000000 -#define LTQ_FLASH_MAX 0x04000000 #endif diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h deleted file mode 100644 index a305f1d..0000000 --- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#ifndef _LANTIQ_PLATFORM_H__ -#define _LANTIQ_PLATFORM_H__ - -#include -#include - -/* struct used to pass info to the pci core */ -enum { - PCI_CLOCK_INT = 0, - PCI_CLOCK_EXT -}; - -#define PCI_EXIN0 0x0001 -#define PCI_EXIN1 0x0002 -#define PCI_EXIN2 0x0004 -#define PCI_EXIN3 0x0008 -#define PCI_EXIN4 0x0010 -#define PCI_EXIN5 0x0020 -#define PCI_EXIN_MAX 6 - -#define PCI_GNT1 0x0040 -#define PCI_GNT2 0x0080 -#define PCI_GNT3 0x0100 -#define PCI_GNT4 0x0200 - -#define PCI_REQ1 0x0400 -#define PCI_REQ2 0x0800 -#define PCI_REQ3 0x1000 -#define PCI_REQ4 0x2000 -#define PCI_REQ_SHIFT 10 -#define PCI_REQ_MASK 0xf - -struct ltq_pci_data { - int clock; - int gpio; - int irq[16]; -}; - -/* struct used to pass info to network drivers */ -struct ltq_eth_data { - struct sockaddr mac; - int mii_mode; -}; - -#endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h index b4465a8..885a429 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h @@ -17,50 +17,6 @@ #define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) #define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) -#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) -#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) -#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) - -#define LTQ_ASC_ASE_TIR INT_NUM_IM2_IRL0 -#define LTQ_ASC_ASE_RIR (INT_NUM_IM2_IRL0 + 2) -#define LTQ_ASC_ASE_EIR (INT_NUM_IM2_IRL0 + 3) - -#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15) -#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14) -#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16) - -#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) -#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23) - -#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) -#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22) -#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) - -#define MIPS_CPU_TIMER_IRQ 7 - -#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0) -#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) -#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) -#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) -#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) -#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) -#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) -#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) -#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) -#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) -#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) -#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) -#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) -#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) -#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) -#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) -#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) -#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) -#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) -#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) - -#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24) - -#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) +#define MIPS_CPU_TIMER_IRQ 7 #endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index d0d40a4..fb3e65f 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -44,11 +44,6 @@ #define SOC_TYPE_VR9_2 0x05 /* v1.2 */ #define SOC_TYPE_AMAZON_SE 0x06 -/* ASC0/1 - serial port */ -#define LTQ_ASC0_BASE_ADDR 0x1E100400 -#define LTQ_ASC1_BASE_ADDR 0x1E100C00 -#define LTQ_ASC_SIZE 0x400 - /* BOOT_SEL - find what boot media we have */ #define BS_EXT_ROM 0x0 #define BS_FLASH 0x1 @@ -68,23 +63,10 @@ extern __iomem void *ltq_cgu_membase; * during early_printk no ioremap is possible * lets use KSEG1 instead */ +#define LTQ_ASC1_BASE_ADDR 0x1E100C00 #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) -/* RCU - reset control unit */ -#define LTQ_RCU_BASE_ADDR 0x1F203000 -#define LTQ_RCU_SIZE 0x1000 - -/* GPTU - general purpose timer unit */ -#define LTQ_GPTU_BASE_ADDR 0x18000300 -#define LTQ_GPTU_SIZE 0x100 - /* EBU - external bus unit */ -#define LTQ_EBU_GPIO_START 0x14000000 -#define LTQ_EBU_GPIO_SIZE 0x1000 - -#define LTQ_EBU_BASE_ADDR 0x1E105300 -#define LTQ_EBU_SIZE 0x100 - #define LTQ_EBU_BUSCON0 0x0060 #define LTQ_EBU_PCC_CON 0x0090 #define LTQ_EBU_PCC_IEN 0x00A4 @@ -93,85 +75,12 @@ extern __iomem void *ltq_cgu_membase; #define LTQ_EBU_ADDRSEL1 0x0024 #define EBU_WRDIS 0x80000000 -/* CGU - clock generation unit */ -#define LTQ_CGU_BASE_ADDR 0x1F103000 -#define LTQ_CGU_SIZE 0x1000 - -/* ICU - interrupt control unit */ -#define LTQ_ICU_BASE_ADDR 0x1F880200 -#define LTQ_ICU_SIZE 0x100 - -/* EIU - external interrupt unit */ -#define LTQ_EIU_BASE_ADDR 0x1F101000 -#define LTQ_EIU_SIZE 0x1000 - -/* PMU - power management unit */ -#define LTQ_PMU_BASE_ADDR 0x1F102000 -#define LTQ_PMU_SIZE 0x1000 - -#define PMU_DMA 0x0020 -#define PMU_USB 0x8041 -#define PMU_LED 0x0800 -#define PMU_GPT 0x1000 -#define PMU_PPE 0x2000 -#define PMU_FPI 0x4000 -#define PMU_SWITCH 0x10000000 - -/* ETOP - ethernet */ -#define LTQ_ETOP_BASE_ADDR 0x1E180000 -#define LTQ_ETOP_SIZE 0x40000 - -/* DMA */ -#define LTQ_DMA_BASE_ADDR 0x1E104100 -#define LTQ_DMA_SIZE 0x800 - -/* PCI */ -#define PCI_CR_BASE_ADDR 0x1E105400 -#define PCI_CR_SIZE 0x400 - /* WDT */ -#define LTQ_WDT_BASE_ADDR 0x1F8803F0 -#define LTQ_WDT_SIZE 0x10 - #define LTQ_RST_CAUSE_WDTRST 0x20 -/* STP - serial to parallel conversion unit */ -#define LTQ_STP_BASE_ADDR 0x1E100BB0 -#define LTQ_STP_SIZE 0x40 - -/* GPIO */ -#define LTQ_GPIO0_BASE_ADDR 0x1E100B10 -#define LTQ_GPIO1_BASE_ADDR 0x1E100B40 -#define LTQ_GPIO2_BASE_ADDR 0x1E100B70 -#define LTQ_GPIO_SIZE 0x30 - -/* SSC */ -#define LTQ_SSC_BASE_ADDR 0x1e100800 -#define LTQ_SSC_SIZE 0x100 - -/* MEI - dsl core */ -#define LTQ_MEI_BASE_ADDR 0x1E116000 - -/* DEU - data encryption unit */ -#define LTQ_DEU_BASE_ADDR 0x1E103100 - /* MPS - multi processor unit (voice) */ #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) -/* request a non-gpio and set the PIO config */ -extern void ltq_pmu_enable(unsigned int module); -extern void ltq_pmu_disable(unsigned int module); - -static inline int ltq_is_ar9(void) -{ - return (ltq_get_soc_type() == SOC_TYPE_AR9); -} - -static inline int ltq_is_vr9(void) -{ - return (ltq_get_soc_type() == SOC_TYPE_VR9); -} - #endif /* CONFIG_SOC_TYPE_XWAY */ #endif /* _LTQ_XWAY_H__ */ diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 413ed53..d185e84 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -27,12 +27,6 @@ EXPORT_SYMBOL_GPL(ebu_lock); */ static struct ltq_soc_info soc_info; -unsigned int ltq_get_soc_type(void) -{ - return soc_info.type; -} -EXPORT_SYMBOL(ltq_get_soc_type); - const char *get_system_type(void) { return soc_info.sys_type; diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 3029139..02d2f15 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -42,6 +42,7 @@ /* clock gates that we can en/disable */ #define PMU_USB0_P BIT(0) #define PMU_PCI BIT(4) +#define PMU_DMA BIT(5) #define PMU_USB0 BIT(6) #define PMU_ASC0 BIT(7) #define PMU_EPHY BIT(7) /* ase */ @@ -49,7 +50,10 @@ #define PMU_DFE BIT(9) #define PMU_EBU BIT(10) #define PMU_STP BIT(11) +#define PMU_GPT BIT(12) +#define PMU_PPE BIT(13) #define PMU_AHBS BIT(13) /* vr9 */ +#define PMU_FPI BIT(14) #define PMU_AHBM BIT(15) #define PMU_ASC1 BIT(17) #define PMU_PPE_QSB BIT(18) @@ -60,6 +64,7 @@ #define PMU_PPE_DPLUS BIT(24) #define PMU_USB1_P BIT(26) #define PMU_USB1 BIT(27) +#define PMU_SWITCH BIT(28) #define PMU_PPE_TOP BIT(29) #define PMU_GPHY BIT(30) #define PMU_PCIE_CLK BIT(31) @@ -76,26 +81,6 @@ static void __iomem *pmu_membase; void __iomem *ltq_cgu_membase; void __iomem *ltq_ebu_membase; -/* legacy function kept alive to ease clkdev transition */ -void ltq_pmu_enable(unsigned int module) -{ - int err = 1000000; - - pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR); - do {} while (--err && (pmu_r32(PMU_PWDSR) & module)); - - if (!err) - panic("activating PMU module failed!"); -} -EXPORT_SYMBOL(ltq_pmu_enable); - -/* legacy function kept alive to ease clkdev transition */ -void ltq_pmu_disable(unsigned int module) -{ - pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR); -} -EXPORT_SYMBOL(ltq_pmu_disable); - /* enable a hw clock */ static int cgu_enable(struct clk *clk) { -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:50:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:50:42 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:33981 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903678Ab2EDMuK (ORCPT ); Fri, 4 May 2012 14:50:10 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , netdev@vger.kernel.org Subject: [PATCH 13/14] NET: MIPS: lantiq: implement OF support inside the etop driver Date: Fri, 4 May 2012 14:18:38 +0200 Message-Id: <1336133919-26525-13-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33152 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5599 Lines: 205 This patch makes it possible to load the driver for the ETOP ethernet on Lantiq SoC from a devicetree. Additionally we convert the driver to using the new clkdev clock in favour of the old ltq_pmu_*() api. Signed-off-by: John Crispin Cc: netdev@vger.kernel.org --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. drivers/net/ethernet/lantiq_etop.c | 63 +++++++++++++++++++++++++++++------ 1 files changed, 52 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index 5dc9cbd..c0443d4 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -29,19 +29,22 @@ #include #include #include -#include #include #include #include #include #include #include +#include +#include +#include +#include +#include #include #include #include -#include #define LTQ_ETOP_MDIO 0x11804 #define MDIO_REQUEST 0x80000000 @@ -73,6 +76,7 @@ #define ETOP_CGEN 0x800 /* use 2 static channels for TX/RX */ +#define LTQ_DMA_CH0_INT INT_NUM_IM2_IRL0 #define LTQ_ETOP_TX_CHANNEL 1 #define LTQ_ETOP_RX_CHANNEL 6 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) @@ -99,12 +103,17 @@ struct ltq_etop_chan { struct ltq_etop_priv { struct net_device *netdev; struct platform_device *pdev; - struct ltq_eth_data *pldata; struct resource *res; struct mii_bus *mii_bus; struct phy_device *phydev; + struct clk *clk; + const void *mac; + int mii_mode; + int tx_irq; + int rx_irq; + struct ltq_etop_chan ch[MAX_DMA_CHAN]; int tx_free[MAX_DMA_CHAN >> 1]; @@ -239,7 +248,7 @@ ltq_etop_hw_exit(struct net_device *dev) struct ltq_etop_priv *priv = netdev_priv(dev); int i; - ltq_pmu_disable(PMU_PPE); + clk_disable(priv->clk); for (i = 0; i < MAX_DMA_CHAN; i++) if (IS_TX(i) || IS_RX(i)) ltq_etop_free_channel(dev, &priv->ch[i]); @@ -251,9 +260,9 @@ ltq_etop_hw_init(struct net_device *dev) struct ltq_etop_priv *priv = netdev_priv(dev); int i; - ltq_pmu_enable(PMU_PPE); + clk_enable(priv->clk); - switch (priv->pldata->mii_mode) { + switch (priv->mii_mode) { case PHY_INTERFACE_MODE_RMII: ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE, LTQ_ETOP_CFG); @@ -266,7 +275,7 @@ ltq_etop_hw_init(struct net_device *dev) default: netdev_err(dev, "unknown mii mode %d\n", - priv->pldata->mii_mode); + priv->mii_mode); return -ENOTSUPP; } @@ -395,7 +404,7 @@ ltq_etop_mdio_probe(struct net_device *dev) } phydev = phy_connect(dev, dev_name(&phydev->dev), <q_etop_mdio_link, - 0, priv->pldata->mii_mode); + 0, priv->mii_mode); if (IS_ERR(phydev)) { netdev_err(dev, "Could not attach to PHY\n"); @@ -643,7 +652,7 @@ ltq_etop_init(struct net_device *dev) goto err_hw; ltq_etop_change_mtu(dev, 1500); - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); + memcpy(&mac.sa_data, &priv->mac, ETH_ALEN); if (!is_valid_ether_addr(mac.sa_data)) { pr_warn("etop: invalid MAC, using random\n"); random_ether_addr(mac.sa_data); @@ -707,9 +716,12 @@ static const struct net_device_ops ltq_eth_netdev_ops = { static int __init ltq_etop_probe(struct platform_device *pdev) { + struct device_node *node = pdev->dev.of_node; struct net_device *dev; struct ltq_etop_priv *priv; struct resource *res; + struct clk *clk; + struct resource irqres[2]; int err; int i; @@ -737,6 +749,20 @@ ltq_etop_probe(struct platform_device *pdev) goto err_out; } + err = of_irq_to_resource_table(node, irqres, 2); + if (err != 2) { + dev_err(&pdev->dev, "not enough irqs defined\n"); + err = -EINVAL; + goto err_out; + } + + clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Failed to get clock\n"); + err = PTR_ERR(clk); + goto err_out; + } + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); if (!dev) { err = -ENOMEM; @@ -748,9 +774,15 @@ ltq_etop_probe(struct platform_device *pdev) priv = netdev_priv(dev); priv->res = res; priv->pdev = pdev; - priv->pldata = dev_get_platdata(&pdev->dev); priv->netdev = dev; spin_lock_init(&priv->lock); + priv->tx_irq = irqres[0].start; + priv->rx_irq = irqres[1].start; + priv->mii_mode = of_get_phy_mode(node); + priv->mac = of_get_mac_address(node); + priv->clk = clk; + if (priv->mii_mode < 0) + priv->mii_mode = PHY_INTERFACE_MODE_MII; for (i = 0; i < MAX_DMA_CHAN; i++) { if (IS_TX(i)) @@ -779,21 +811,30 @@ static int __devexit ltq_etop_remove(struct platform_device *pdev) { struct net_device *dev = platform_get_drvdata(pdev); + struct ltq_etop_priv *priv = netdev_priv(dev); if (dev) { netif_tx_stop_all_queues(dev); ltq_etop_hw_exit(dev); ltq_etop_mdio_cleanup(dev); + clk_put(priv->clk); unregister_netdev(dev); } return 0; } +static const struct of_device_id ltq_etop_match[] = { + { .compatible = "lantiq,etop-xway" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ltq_etop_match); + static struct platform_driver ltq_mii_driver = { .remove = __devexit_p(ltq_etop_remove), .driver = { - .name = "ltq_etop", + .name = "etop-xway", .owner = THIS_MODULE, + .of_match_table = ltq_etop_match, }, }; -- 1.7.9.1 From blogic@openwrt.org Fri May 4 14:50:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 14:51:05 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:33986 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903664Ab2EDMuO (ORCPT ); Fri, 4 May 2012 14:50:14 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , linux-mtd@lists.infradead.org Subject: [PATCH 12/14] MTD: MIPS: lantiq: implement OF support Date: Fri, 4 May 2012 14:18:37 +0200 Message-Id: <1336133919-26525-12-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336133919-26525-1-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> X-archive-position: 33153 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4278 Lines: 146 Adds bindings for OF and make use of module_platform_driver for lantiq based socs. Signed-off-by: John Crispin Cc: linux-mtd@lists.infradead.org --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. drivers/mtd/maps/lantiq-flash.c | 69 ++++++++++++++------------------------- 1 files changed, 25 insertions(+), 44 deletions(-) diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c index b5401e3..aefa111 100644 --- a/drivers/mtd/maps/lantiq-flash.c +++ b/drivers/mtd/maps/lantiq-flash.c @@ -21,7 +21,6 @@ #include #include -#include /* * The NOR flash is connected to the same external bus unit (EBU) as PCI. @@ -44,8 +43,9 @@ struct ltq_mtd { struct map_info *map; }; -static char ltq_map_name[] = "ltq_nor"; -static const char *ltq_probe_types[] __devinitconst = { "cmdlinepart", NULL }; +static const char ltq_map_name[] = "ltq_nor"; +static const char *ltq_probe_types[] __devinitconst = { + "cmdlinepart", "ofpart", NULL }; static map_word ltq_read16(struct map_info *map, unsigned long adr) @@ -108,12 +108,11 @@ ltq_copy_to(struct map_info *map, unsigned long to, spin_unlock_irqrestore(&ebu_lock, flags); } -static int __init +static int __devinit ltq_mtd_probe(struct platform_device *pdev) { - struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev); + struct mtd_part_parser_data ppdata; struct ltq_mtd *ltq_mtd; - struct resource *res; struct cfi_private *cfi; int err; @@ -122,28 +121,19 @@ ltq_mtd_probe(struct platform_device *pdev) ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!ltq_mtd->res) { - dev_err(&pdev->dev, "failed to get memory resource"); + dev_err(&pdev->dev, "failed to get memory resource\n"); err = -ENOENT; goto err_out; } - res = devm_request_mem_region(&pdev->dev, ltq_mtd->res->start, - resource_size(ltq_mtd->res), dev_name(&pdev->dev)); - if (!ltq_mtd->res) { - dev_err(&pdev->dev, "failed to request mem resource"); - err = -EBUSY; - goto err_out; - } - ltq_mtd->map = kzalloc(sizeof(struct map_info), GFP_KERNEL); - ltq_mtd->map->phys = res->start; - ltq_mtd->map->size = resource_size(res); - ltq_mtd->map->virt = devm_ioremap_nocache(&pdev->dev, - ltq_mtd->map->phys, ltq_mtd->map->size); + ltq_mtd->map->phys = ltq_mtd->res->start; + ltq_mtd->map->size = resource_size(ltq_mtd->res); + ltq_mtd->map->virt = devm_request_and_ioremap(&pdev->dev, ltq_mtd->res); if (!ltq_mtd->map->virt) { - dev_err(&pdev->dev, "failed to ioremap!\n"); - err = -ENOMEM; - goto err_free; + dev_err(&pdev->dev, "failed to remap mem resource\n"); + err = -EBUSY; + goto err_out; } ltq_mtd->map->name = ltq_map_name; @@ -169,9 +159,9 @@ ltq_mtd_probe(struct platform_device *pdev) cfi->addr_unlock1 ^= 1; cfi->addr_unlock2 ^= 1; - err = mtd_device_parse_register(ltq_mtd->mtd, ltq_probe_types, NULL, - ltq_mtd_data->parts, - ltq_mtd_data->nr_parts); + ppdata.of_node = pdev->dev.of_node; + err = mtd_device_parse_register(ltq_mtd->mtd, ltq_probe_types, + &ppdata, NULL, 0); if (err) { dev_err(&pdev->dev, "failed to add partitions\n"); goto err_destroy; @@ -204,32 +194,23 @@ ltq_mtd_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id ltq_mtd_match[] = { + { .compatible = "lantiq,nor" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ltq_mtd_match); + static struct platform_driver ltq_mtd_driver = { + .probe = ltq_mtd_probe, .remove = __devexit_p(ltq_mtd_remove), .driver = { - .name = "ltq_nor", + .name = "ltq-nor", .owner = THIS_MODULE, + .of_match_table = ltq_mtd_match, }, }; -static int __init -init_ltq_mtd(void) -{ - int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); - - if (ret) - pr_err("ltq_nor: error registering platform driver"); - return ret; -} - -static void __exit -exit_ltq_mtd(void) -{ - platform_driver_unregister(<q_mtd_driver); -} - -module_init(init_ltq_mtd); -module_exit(exit_ltq_mtd); +module_platform_driver(ltq_mtd_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("John Crispin "); -- 1.7.9.1 From wim@iguana.be Fri May 4 15:22:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 15:22:18 +0200 (CEST) Received: from ns1.pc-advies.be ([83.149.101.17]:57733 "EHLO spo001.leaseweb.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903664Ab2EDNWM (ORCPT ); Fri, 4 May 2012 15:22:12 +0200 Received: from wimvs by spo001.leaseweb.com with local (Exim 4.50) id 1SQISZ-00034l-L8; Fri, 04 May 2012 15:22:11 +0200 Date: Fri, 4 May 2012 15:22:11 +0200 From: Wim Van Sebroeck To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH 11/14] watchdog: MIPS: lantiq: implement OF support and minor fixes Message-ID: <20120504132211.GV3074@spo001.leaseweb.com> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-11-git-send-email-blogic@openwrt.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1336133919-26525-11-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.4.1i X-archive-position: 33154 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 627 Lines: 21 Hi, > Add support for OF. We also apply the following small fixes > * reduce boiler plate by using devm_request_and_ioremap > * sane error path for the clock > * move LTQ_RST_CAUSE_WDTRST to a soc specific header file > * add a message to show that the driver loaded > > Signed-off-by: John Crispin > Cc: Wim Van Sebroeck > Cc: linux-watchdog@vger.kernel.org > > --- > This patch is part of a series moving the mips/lantiq target to OF and clkdev > support. The patch, once Acked, should go upstream via Ralf's MIPS tree. Acked-by: Wim Van Sebroeck Kind regards, Wim. From john@phrozen.org Fri May 4 15:39:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 15:39:06 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:37167 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903664Ab2EDNjC (ORCPT ); Fri, 4 May 2012 15:39:02 +0200 Message-ID: <4FA3DBA3.5030903@phrozen.org> Date: Fri, 04 May 2012 15:37:39 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: "linux-mips@linux-mips.org" Subject: pci and pcie coexistence X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33155 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 369 Lines: 18 Hi, I have some boards, where pcie and pci need to coexist. This implies, that both drivers share the same pcibios_plat_dev_init and pcibios_map_irq. I am trying to figure out, how to best differentiate between the 2 drivers. Would the following be sane ? if (pci_find_capability(pdev, PCI_CAP_ID_EXP)) do_pcie_stuf(); else do_pci_stuff(); Thanks, John From akhilesh.lxr@gmail.com Fri May 4 16:10:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 16:11:00 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:63602 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903678Ab2EDOKz (ORCPT ); Fri, 4 May 2012 16:10:55 +0200 Received: by pbbrq13 with SMTP id rq13so4175992pbb.36 for ; Fri, 04 May 2012 07:10:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:cc:content-type; bh=q71WkTRHTYlQhL6SAU5Tf+tt1yn6FgHm7Tgl+0lcbAo=; b=lcN2phjKlsbxG3RlkCZxe6dxjWLirOqAmdwMW8JWeeY42VB9l4EyNjpX7Vl4Hqp/Ca plf6bwMLCMs21LDlJLA+Vyw/OUWTQZv8ed16QIa2T3OliYDmlokETywDRc38fZchGMn3 TfN1G5qDnqhpTf2icdyfhC37cxfsm/OO+qOWX60boZYlKww5eJ0LPR5/n0xINGEkjyQa ln21dLrlEAWoTGZnVXfr6CI1XqRm+Dm9Qe7Yp81IMXJGkbMQxHisOG4qQxHPdmPh36J2 i0PBnNPu+BDlAB3vh3SrS55eHqsEffmhXv1urJsVpZVcQWUzyn9C9YeWWmvuQ/Q42gZL aavQ== MIME-Version: 1.0 Received: by 10.68.226.35 with SMTP id rp3mr8489515pbc.44.1336140646573; Fri, 04 May 2012 07:10:46 -0700 (PDT) Received: by 10.66.14.228 with HTTP; Fri, 4 May 2012 07:10:43 -0700 (PDT) Date: Fri, 4 May 2012 19:40:43 +0530 Message-ID: Subject: [Bug-fix] Fix-the-backtrcae-problem-Ftrace is enable From: Akhilesh Kumar To: ralf@linux-mips.org, paulmck@linux.vnet.ibm.com, fweisbec@gmail.com, paul.gortmaker@windriver.com, josh@joshtriplett.org, gergely@homejinni.com, akhipatel@gmail.com Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: multipart/mixed; boundary=e89a8ff24bab9be69a04bf367c90 X-archive-position: 33156 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akhilesh.lxr@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 24765 Lines: 491 --e89a8ff24bab9be69a04bf367c90 Content-Type: multipart/alternative; boundary=e89a8ff24bab9be69404bf367c8e --e89a8ff24bab9be69404bf367c8e Content-Type: text/plain; charset=ISO-8859-1 Hi All, Please find the bug fix patch when HAVE_FUNCTION_TRACER is enable. Thanks, Akhilesh >From 89004f88a1f8399be7a856b43b475f06c3d5bb30 Mon Sep 17 00:00:00 2001 From: Akhilesh Kumar Date: Fri, 4 May 2012 18:52:46 +0530 Subject: [PATCH 1/1] Patch fix the backtrcae problem using unwind_stack()) When ftrace is used, unwind_stack() is unable to retrieve the frame info and call-trace doesn't work. test module ---------------- static struct timer_list backtrace_timer; static void backtrace_test_timer(unsigned long data) { printk("Testing a backtrace from irq context.\n"); printk("The following trace is a kernel self test and not a bug!\n"); dump_stack(); } static int backtrace_regression_test(void) { printk("====[ backtrace testing ]===========\n"); printk("Testing a backtrace from process context.\n"); printk("The following trace is a kernel self test and not a bug!\n"); dump_stack(); init_timer(&backtrace_timer); backtrace_timer.function = backtrace_test_timer; mod_timer(&backtrace_timer, jiffies + 10); msleep(10); printk("====[ end of backtrace testing ]====\n"); return 0; } static void exitf(void) { } module_init(backtrace_regression_test); module_exit(exitf); MODULE_LICENSE("GPL"); --------------------------------------------------------------------- out put when HAVE_FUNCTION_TRACER is disable ====[ backtrace testing ]=========== Testing a backtrace from process context. The following trace is a kernel self test and not a bug! Testing a backtrace. The following trace is a kernel self test and not a bug! Call Trace: [<80295134>] dump_stack+0x8/0x34 [] backtrace_regression_test+0x60/0x94 [sisc_backtrcae] [<800004f0>] do_one_initcall+0xf0/0x1d0 [<80060954>] sys_init_module+0x19c8/0x1c60 [<8000a418>] stack_done+0x20/0x40 output befor patch when HAVE_FUNCTION_TRACER is enable --------------------------------------------------------------------- VDLinux#> insmod sisc_backtrcae.ko ====[ backtrace testing ]=========== Testing a backtrace from process context. The following trace is a kernel self test and not a bug! Testing a backtrace. The following trace is a kernel self test and not a bug! Call Trace: [<802e5164>] dump_stack+0x1c/0x50 [<802e5164>] dump_stack+0x1c/0x50 ====[ end of backtrace testing ]==== ------------------------------------------------------ above shows the wrong back trcae output after patch when HAVE_FUNCTION_TRACER is enable ---------------------------------------------------------------------- ====[ backtrace testing ]=========== Testing a backtrace from process context. The following trace is a kernel self test and not a bug! Testing a backtrace. The following trace is a kernel self test and not a bug! Call Trace: [<802eb1a4>] dump_stack+0x20/0x54 [] backtrace_test_timer+0x5c/0x74 [sisc_backtrcae] [] init_module+0x68/0xa0 [sisc_backtrcae] [<80000508>] do_one_initcall+0x108/0x1f0 [<8006d4c4>] sys_init_module+0x1a10/0x1c74 [<8000b038>] stack_done+0x20/0x40 ------------------------------------------------------------------ get_frame_info() is used to fetch the frame information from the function. However, 1. this function just considers the first stack adjustment for frame size. 2. On finding the save_lr instruction, it returns. It doesn't handle the ftrace condition. If Dynamic Frace "CONFIG_DYNAMIC_FTRACE" is enabled, the instrumentation code is: - jal - addiu sp,sp,-8 Thus, the current Frame Size of function is increased by 8 for Ftrace. Signed-off-by: Akhilesh Kumar Signed-off-by: Himanshu Maithani --- arch/mips/kernel/process.c | 67 ++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 67 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 7955409..df72738 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -290,12 +290,45 @@ static inline int is_sp_move_ins(union mips_instruction *ip) return 0; } +#ifdef CONFIG_DYNAMIC_FTRACE +/* + * To create the jal <> instruction from mcount. + * taken from: + * - arch/mips/kernel/ftrace.c + */ +#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ +#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */ +#define INSN_JAL(addr) \ + ((unsigned int)(JAL | (((addr) >> 2) & ADDR_MASK))) + +/* + * We assume jal / to be present in + * first JAL_MAX_OFFSET instructions. + * Increment this, if its otherwise + */ +#define JAL_MAX_OFFSET 16U +#define MCOUNT_STACK_INST 0x27bdfff8 /* addiu sp,sp,-8 */ + +/* + * If Dynamic Ftrace is enabled, ftrace_caller is the trace function. + * Otherwise its - mcount + */ +extern void ftrace_caller(void); +#endif /* CONFIG_DYNAMIC_FTRACE */ + static int get_frame_info(struct mips_frame_info *info) { union mips_instruction *ip = info->func; unsigned max_insns = info->func_size / sizeof(union mips_instruction); unsigned i; +#ifdef CONFIG_DYNAMIC_FTRACE + unsigned max_prolog_inst = max_insns; + int jal_found = 0; + /* instruction corresponding to jal <_mcount>/ */ + int jal_mcount = 0; +#endif + info->pc_offset = -1; info->frame_size = 0; @@ -306,6 +339,28 @@ static int get_frame_info(struct mips_frame_info *info) max_insns = 128U; /* unknown function size */ max_insns = min(128U, max_insns); +#ifdef CONFIG_DYNAMIC_FTRACE + max_prolog_inst = min(JAL_MAX_OFFSET, max_prolog_inst); + jal_mcount = INSN_JAL((unsigned)&ftrace_caller); + + for (i = 0; i < max_prolog_inst; i++, ip++) { + if ((*(int *)ip == jal_mcount) || + /* + * for dyn ftrace, the code initially has 0. + * so we check whether the next instruction is + * addiu sp,sp,-8 + */ + (!(*(int *)ip) && + (*(int *)(ip + 1) == MCOUNT_STACK_INST)) + ) { + jal_found = 1; + break; + } + } + /* restore the ip to start of function */ + ip = info->func; +#endif + for (i = 0; i < max_insns; i++, ip++) { if (is_jal_jalr_jr_ins(ip)) @@ -321,6 +376,18 @@ static int get_frame_info(struct mips_frame_info *info) break; } } +#ifdef CONFIG_DYNAMIC_FTRACE + /* + * to offset the effect of: + * addiu sp,sp,-8 + */ + if (jal_found) { + if (info->frame_size) + info->frame_size += 8; + if (info->pc_offset >= 0) + info->pc_offset += 8 / sizeof(long); + } +#endif if (info->frame_size && info->pc_offset >= 0) /* nested */ return 0; if (info->pc_offset < 0) /* leaf */ -- 1.7.8.4 --e89a8ff24bab9be69404bf367c8e Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Hi All,=A0
=A0
Please find the bug fix patch when HAVE_FUNCTION_TRACER is enable.=A0<= /div>
=A0
Thanks,=A0
Akhilesh=A0
=A0=A0
From 89004f88a1f8399be7a856b43b475f06c3d5bb30 Mon Sep 17 00:00:00 2001=
From:=A0 Akhilesh Kumar <a= khilesh.lxr@gmail.com>
Date: Fri, 4 May 2012 18:52:46 +0530
Su= bject: [PATCH 1/1] Patch fix the backtrcae=A0 problem using unwind_stack())=

When ftrace is used, unwind_stack() is unable to retrieve the frame info=
and call-trace doesn't work.

test module
----------------
static struct timer_list backtrace_ti= mer;
static void backtrace_test_timer(unsigned long data)
{
=A0=A0= =A0=A0=A0=A0=A0 printk("Testing a backtrace from irq context.\n")= ;
=A0=A0=A0=A0=A0=A0=A0 printk("The following trace is a kernel sel= f test and not a
bug!\n");
=A0=A0=A0=A0=A0=A0=A0 dump_stack();
}
static int ba= cktrace_regression_test(void)
{
=A0=A0=A0=A0=A0=A0=A0 printk("= =3D=3D=3D=3D[ backtrace testing ]=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n")= ;
=A0=A0=A0=A0=A0=A0=A0 printk("Testing a backtrace from process co= ntext.\n");
=A0=A0=A0=A0=A0=A0=A0 printk("The following trace is a kernel self tes= t and not a
bug!\n");
=A0=A0=A0=A0=A0=A0=A0 dump_stack();

=A0=A0=A0=A0=A0=A0=A0 init_timer(&backtrace_timer);
=A0=A0=A0=A0= =A0=A0=A0 backtrace_timer.function =3D backtrace_test_timer;
=A0=A0=A0= =A0=A0=A0=A0 mod_timer(&backtrace_timer, jiffies + 10);

=A0=A0=A0=A0=A0=A0=A0 msleep(10);
=A0=A0=A0=A0=A0=A0=A0 printk("= =3D=3D=3D=3D[ end of backtrace testing ]=3D=3D=3D=3D\n");
=A0=A0=A0= =A0=A0=A0=A0 return 0;
}
static void exitf(void)
{
}
module_= init(backtrace_regression_test);
module_exit(exitf);
MODULE_LICENSE("GPL");
---------------------------------------= ------------------------------
out put when HAVE_FUNCTION_TRACER is disa= ble

=3D=3D=3D=3D[ backtrace testing ]=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Te= sting a backtrace from process context.
The following trace is a kernel = self test and not a bug!
Testing a backtrace.
The following trace is = a kernel self test and not a bug!
Call Trace:
[<80295134>] dump_stack+0x8/0x34
[<c0946060>]= backtrace_regression_test+0x60/0x94 [sisc_backtrcae]
[<800004f0>]= do_one_initcall+0xf0/0x1d0
[<80060954>] sys_init_module+0x19c8/0x= 1c60
[<8000a418>] stack_done+0x20/0x40

output befor patch when HAVE_FUNCTION_TRACER is enable
--------------= -------------------------------------------------------
VDLinux#> ins= mod sisc_backtrcae.ko
=3D=3D=3D=3D[ backtrace testing ]=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D
Testing a backtrace from process context.
The following trace is a kernel self test and not a bug!
Testing a backt= race.
The following trace is a kernel self test and not a bug!
Call T= race:
[<802e5164>] dump_stack+0x1c/0x50
[<802e5164>] dump= _stack+0x1c/0x50
=3D=3D=3D=3D[ end of backtrace testing ]=3D=3D=3D=3D
-------------------= -----------------------------------
above shows the wrong back trcae

output after patch when HAVE_FUNCTION_TRACER is enable
--------------= --------------------------------------------------------
=3D=3D=3D=3D[ b= acktrace testing ]=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Testing a backtrace = from process context.
The following trace is a kernel self test and not a bug!
Testing a backt= race.
The following trace is a kernel self test and not a bug!
Call T= race:
[<802eb1a4>] dump_stack+0x20/0x54
[<c003405c>] back= trace_test_timer+0x5c/0x74 [sisc_backtrcae]
[<c00340dc>] init_module+0x68/0xa0 [sisc_backtrcae]
[<80000508&= gt;] do_one_initcall+0x108/0x1f0
[<8006d4c4>] sys_init_module+0x1a= 10/0x1c74
[<8000b038>] stack_done+0x20/0x40
-------------------= -----------------------------------------------

get_frame_info() is used to fetch the frame information from the
func= tion.
However,
1. this function just considers the first stack adjust= ment for frame
size.
2. On finding the save_lr instruction, it return= s.
It doesn't handle the ftrace condition.

If Dynamic Frace "CONFIG_DYNAMIC_FTRACE" is enabled, the instr= umentation code is:
=A0- jal <ftrace_caller>
=A0- addiu sp,sp,-= 8
Thus, the current Frame Size of function is increased by 8 for Ftrace.=

Signed-off-by: Akhilesh Kumar <akhilesh.lxr@gmail.com>
Signed-off-by: Himanshu Maithani <= hmaithani@gmail.com>
--- =A0arch/mips/kernel/process.c |=A0=A0 67 ++++++++++++++++++++++++++++++++++= ++++++++++
=A01 files changed, 67 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
= index 7955409..df72738 100644
--- a/arch/mips/kernel/process.c
+++ b/= arch/mips/kernel/process.c
@@ -290,12 +290,45 @@ static inline int is_sp= _move_ins(union mips_instruction *ip)
=A0=A0return 0;
=A0}
=A0
+#ifdef CONFIG_DYNAMIC_FTRACE
+/*
+= * To create the jal <> instruction from mcount.
+ * taken from:+ * - arch/mips/kernel/ftrace.c
+ */
+#define ADDR_MASK 0x03ffffff= =A0=A0=A0 /*=A0 op_code|addr : 31...26|25 ....0 */
+#define JAL 0x0c000000=A0=A0=A0=A0=A0 /* jump & link: ip --> ra, ju= mp to target */
+#define INSN_JAL(addr)=A0 \
+=A0=A0=A0=A0=A0 ((unsig= ned int)(JAL | (((addr) >> 2) & ADDR_MASK)))
+
+/*
+ * W= e assume jal <mcount>/<ftrace_caller> to be present in
+ * first JAL_MAX_OFFSET instructions.
+ * Increment this, if its otherw= ise
+ */
+#define JAL_MAX_OFFSET 16U
+#define MCOUNT_STACK_INST 0x= 27bdfff8 /* addiu=A0=A0 sp,sp,-8 */
+
+/*
+ * If Dynamic Ftrace is= enabled, ftrace_caller is the trace function.
+ * Otherwise its - mcount
+ */
+extern void=A0 ftrace_caller(void);<= br>+#endif /* CONFIG_DYNAMIC_FTRACE */
+
=A0static int get_frame_info= (struct mips_frame_info *info)
=A0{
=A0=A0union mips_instruction *ip = =3D info->func;
=A0=A0unsigned max_insns =3D info->func_size / sizeof(union mips_instruc= tion);
=A0=A0unsigned i;
=A0
+#ifdef CONFIG_DYNAMIC_FTRACE
+=A0= unsigned max_prolog_inst =3D max_insns;
+=A0int jal_found =3D 0;
+=A0= /* instruction corresponding to jal <_mcount>/<ftrace_caller> *= /
+=A0int jal_mcount =3D 0;
+#endif
+
=A0=A0info->pc_offset =3D -= 1;
=A0=A0info->frame_size =3D 0;
=A0
@@ -306,6 +339,28 @@ stati= c int get_frame_info(struct mips_frame_info *info)
=A0=A0=A0max_insns = =3D 128U;=A0/* unknown function size */
=A0=A0max_insns =3D min(128U, max_insns);
=A0
+#ifdef CONFIG_DYNAMIC_= FTRACE
+=A0max_prolog_inst =3D min(JAL_MAX_OFFSET, max_prolog_inst);
= +=A0jal_mcount =3D INSN_JAL((unsigned)&ftrace_caller);
+
+=A0for = (i =3D 0; i < max_prolog_inst; i++, ip++) {
+=A0=A0if ((*(int *)ip =3D=3D jal_mcount) ||
+=A0=A0=A0=A0/*
+=A0=A0= =A0=A0 * for dyn ftrace, the code initially has 0.
+=A0=A0=A0=A0 * so we= check whether the next instruction is
+=A0=A0=A0=A0 * addiu=A0=A0 sp,sp= ,-8
+=A0=A0=A0=A0 */
+=A0=A0=A0=A0(!(*(int *)ip) &&
+=A0=A0=A0=A0 (*(int *)(ip + 1) =3D=3D MCOUNT_STACK_INST))
+=A0=A0=A0=A0= ) {
+=A0=A0=A0jal_found =3D 1;
+=A0=A0=A0break;
+=A0=A0}
+=A0}=
+=A0/* restore the ip to start of function */
+=A0ip =3D info->fu= nc;
+#endif
+
=A0=A0for (i =3D 0; i < max_insns; i++, ip++) { =A0
=A0=A0=A0if (is_jal_jalr_jr_ins(ip))
@@ -321,6 +376,18 @@ static = int get_frame_info(struct mips_frame_info *info)
=A0=A0=A0=A0break;
= =A0=A0=A0}
=A0=A0}
+#ifdef CONFIG_DYNAMIC_FTRACE
+=A0/*
+=A0 * = to offset the effect of:
+=A0 * addiu=A0=A0 sp,sp,-8
+=A0 */
+=A0if (jal_found) {
+=A0=A0if= (info->frame_size)
+=A0=A0=A0info->frame_size +=3D 8;
+=A0=A0i= f (info->pc_offset >=3D 0)
+=A0=A0=A0info->pc_offset +=3D 8 / s= izeof(long);
+=A0}
+#endif
=A0=A0if (info->frame_size && info->pc_offset >=3D 0) /* n= ested */
=A0=A0=A0return 0;
=A0=A0if (info->pc_offset < 0) /* l= eaf */
--
1.7.8.4

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bmRpZgogCWlmIChpbmZvLT5mcmFtZV9zaXplICYmIGluZm8tPnBjX29mZnNldCA+PSAwKSAvKiBu ZXN0ZWQgKi8KIAkJcmV0dXJuIDA7CiAJaWYgKGluZm8tPnBjX29mZnNldCA8IDApIC8qIGxlYWYg Ki8KLS0gCjEuNy44LjQKCg== --e89a8ff24bab9be69a04bf367c90-- From ddaney.cavm@gmail.com Fri May 4 20:09:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 20:09:49 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:39201 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903667Ab2EDSJp (ORCPT ); Fri, 4 May 2012 20:09:45 +0200 Received: by pbbrq13 with SMTP id rq13so4459751pbb.36 for ; Fri, 04 May 2012 11:09:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=SIYEbHq1F/sEi2Nk2Jp2TVmFgUqxcSDRKy+0QiGeaHY=; b=i3p1NbKYLaeOV7YuBPU3OodrPCcXhB7VEpXCKh1V6xo45ntysopb6L9uUBxBuhYvXg N2rjdGo/I6HuKZdtsqxrnOfh2Nc1K/OJMimsiXKbRtR6Kpe2LR1lp5jsDufZcIcRRn0W m83GKGdhm8rEdza0Ez9KlQfiAviEPJ8OptdBkYAS3da/eaij0l9DdlLZxJ9FeJTV6kxb Y7bYhK+b2mnwXWecrCDZI5dNgpCvfopkekUVmLq8MyqGvJPOPvykKrFkq+DxSIx3nUQO bQRap+UJrLEiIm2WhhRrg53COup/8oDJ9jFIEkgJOVpKsIZ5rqKxDSJArVDEp7DVDMyy Uo9w== Received: by 10.68.217.40 with SMTP id ov8mr2919528pbc.35.1336154979251; Fri, 04 May 2012 11:09:39 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id pd3sm3473450pbc.53.2012.05.04.11.09.38 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 May 2012 11:09:38 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q44I9bel022182; Fri, 4 May 2012 11:09:37 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q44I9awh022180; Fri, 4 May 2012 11:09:36 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Handle huge pages with 64KB base page size. Date: Fri, 4 May 2012 11:09:35 -0700 Message-Id: <1336154975-22149-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33158 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1742 Lines: 52 From: David Daney When using sparsemem, we need to adjust some constants as the resulting huge pages are 512MB in size. Signed-off-by: David Daney --- arch/mips/Kconfig | 10 ++++++---- arch/mips/include/asm/sparsemem.h | 6 +++++- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3134457..e588610 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1789,10 +1789,12 @@ endchoice config FORCE_MAX_ZONEORDER int "Maximum zone order" - range 13 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB - default "13" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB - range 12 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB - default "12" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB + range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB + default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB + range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB + default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB + range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB + default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB range 11 64 default "11" help diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h index 7165333..4461198 100644 --- a/arch/mips/include/asm/sparsemem.h +++ b/arch/mips/include/asm/sparsemem.h @@ -6,7 +6,11 @@ * SECTION_SIZE_BITS 2^N: how big each section will be * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space */ -#define SECTION_SIZE_BITS 28 +#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PAGE_SIZE_64KB) +# define SECTION_SIZE_BITS 29 +#else +# define SECTION_SIZE_BITS 28 +#endif #define MAX_PHYSMEM_BITS 35 #endif /* CONFIG_SPARSEMEM */ -- 1.7.2.3 From swarren@wwwdotorg.org Fri May 4 22:57:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 May 2012 22:57:38 +0200 (CEST) Received: from avon.wwwdotorg.org ([70.85.31.133]:33969 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903800Ab2EDU5c (ORCPT ); Fri, 4 May 2012 22:57:32 +0200 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 84C2D6358; Fri, 4 May 2012 14:58:54 -0600 (MDT) Received: from [10.20.204.51] (searspoint.nvidia.com [216.228.112.21]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id D59AAE4103; Fri, 4 May 2012 14:57:27 -0600 (MDT) Message-ID: <4FA442B6.1020501@wwwdotorg.org> Date: Fri, 04 May 2012 14:57:26 -0600 From: Stephen Warren User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.28) Gecko/20120313 Thunderbird/3.1.20 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Linus Walleij Subject: Re: [PATCH 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-4-git-send-email-blogic@openwrt.org> In-Reply-To: <1336133919-26525-4-git-send-email-blogic@openwrt.org> X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean X-archive-position: 33159 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: swarren@wwwdotorg.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4307 Lines: 130 On 05/04/2012 06:18 AM, John Crispin wrote: > Implement support for pinctrl on lantiq/xway socs. The IO core found on these > socs has the registers for pinctrl, pinconf and gpio mixed up in the same > register range. As the gpio_chip handling is only a few lines, the driver also > implements the gpio functionality. This obseletes the old gpio driver that was > located in the arch/ folder. Overall looks pretty reasonable. Some comments below. There doesn't appear to be binding documentation. Something is needed to describe how to instantiate the pinctrl driver, and the format of the "pin configuration nodes". See Documentation/devicetree/bindings/pinctrl/ for some examples. > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > config LANTIQ ... > + select PINCTRL > diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig > config SOC_TYPE_XWAY > bool > + select PINCTRL_XWAY I'd be tempted to just select PINCTRL and PINCTRL_XWAY in the same place under SOC_TYPE_XWAY. > diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile > obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o > obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o > obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o > +obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o > +obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o It'd be nice to keep this sorted. I know COH901 isn't right now; I guess I should send a patch for that. > diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c > +static const char *ltq_get_group_name(struct pinctrl_dev *pctrldev, > + unsigned selector) > +{ > + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); > + if (selector >= info->num_grps) > + return NULL; Most/all other drivers removed this range checking, instead relying on the pinctrl core to not be buggy, and to respect the limits set out in the pinctrl device descriptor. > +static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, > + "%s mixes pins and groups settings\n", s/mixes/muxes/. > +int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, > + *map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL); Check for failure. > diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c > +static int xway_pinconf_get(struct pinctrl_dev *pctldev, ... > + default: > + pr_err("%s: Invalid config param %04x\n", > + pinctrl_dev_get_name(pctldev), param); Use dev_err instead of pr_err everywhere? > +int irq_to_gpio(unsigned int gpio) > +{ > + return -EINVAL; > +} > +EXPORT_SYMBOL(irq_to_gpio); Hasn't this function been removed? Perhaps it's only ARM that removed it. > +static inline int xway_gpio_pin_count(void) > +{ > + if (of_machine_is_compatible("lantiq,ar9") || > + of_machine_is_compatible("lantiq,gr9") || > + of_machine_is_compatible("lantiq,vr9")) > + return 56; > + return 32; > +} What are those compatible values? Are they SoC variants or boards? If they're SoC variants, then putting each of those compatible values into the of_device_id table, and storing the per-SoC information in the .data field is one way to go. Or, simply put this information into a device-tree property. If they're board names, this seems wrong; the code should be switching on the SoC variant rather than the individual board. If a board happens to hook up fewer of the pins that other boards that's fine, just don't use them, but they still exist on the SoC and hence are reasonable to represent in the driver. > +static int __devinit pinmux_xway_probe(struct platform_device *pdev) > + for (i = 0; i < xway_chip.ngpio; i++) { > + /* strlen("ioXY") + 1 = 5 */ > + char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL); > + > + if (!name) { > + dev_err(&pdev->dev, "Failed to allocate pad name\n"); > + return -ENOMEM; > + } > + snprintf(name, 5, "io%d", i); Maybe time for a devm_kasprintf()? > + /* finish with registering the gpio range in pinctrl */ > + xway_gpio_range.npins = xway_chip.ngpio; Presumably, of_gpiochip_add() above dynamically allocates the base GPIO number? If so, that value needs to be transferred into xway_gpio_range.base too. > +core_initcall_sync(pinmux_xway_init); Does this need to be a core_initcall_sync; would a simple module_init() do instead? From akhilesh.lxr@gmail.com Sat May 5 04:34:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 May 2012 04:34:58 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:42062 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901173Ab2EECes (ORCPT ); Sat, 5 May 2012 04:34:48 +0200 Received: by pbbrq13 with SMTP id rq13so4857562pbb.36 for ; Fri, 04 May 2012 19:34:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=3WUHQpWbs1HjdE4GKU91P5G6N6cMU8eGXmV2sUy3KNs=; b=PqRTpT3m1OmpXRQwvwzRFEAFj1BVsMra8uYqgYJaIa71HqSwCeIZ2RhLzPRRMBu/gk +1g7ynWcefuWm7dgclKxpz7yuDtd78NRooIchByLlJiGzM4AqL21RS5z4uGhJMEFyktj SmSDiujsHaCS8iuQf+jU2UGB10DE6UdSkDS8CGWlwkH52EltHJIIuR9XTGVDJ5ShgFor w8i/VUjBrkwTBU/xNopa2fSdLdCjQDX3on3jZs1LL+J0cS7WeAO9HadMaMnheQyQ8Q62 o91k5bXdtbCWfBvzs5nF0Uek4mZMmdp7op1siKV6rby5krkUc3zslbzyeCbfnU1BVW6n AsVQ== MIME-Version: 1.0 Received: by 10.68.220.134 with SMTP id pw6mr23804500pbc.149.1336185281291; Fri, 04 May 2012 19:34:41 -0700 (PDT) Received: by 10.66.14.228 with HTTP; Fri, 4 May 2012 19:34:41 -0700 (PDT) In-Reply-To: References: Date: Sat, 5 May 2012 08:04:41 +0530 Message-ID: Subject: Re: [Bug-fix] Fix-the-backtrcae-problem-Ftrace is enable From: Akhilesh Kumar To: ralf@linux-mips.org, paulmck@linux.vnet.ibm.com, fweisbec@gmail.com, paul.gortmaker@windriver.com, josh@joshtriplett.org, gergely@homejinni.com Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: multipart/mixed; boundary=047d7b2e4f620ba56504bf40e181 X-archive-position: 33161 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akhilesh.lxr@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 26905 Lines: 518 --047d7b2e4f620ba56504bf40e181 Content-Type: multipart/alternative; boundary=047d7b2e4f620ba55f04bf40e17f --047d7b2e4f620ba55f04bf40e17f Content-Type: text/plain; charset=ISO-8859-1 > > Hi Ralf, > > When ftrace is used, unwind_stack() is unable to retrieve the frame info > and call-trace doesn't work. Please find the bug fix patch when > HAVE_FUNCTION_TRACER is enable. > > Please comment. > > > > > From 89004f88a1f8399be7a856b43b475f06c3d5bb30 Mon Sep 17 00:00:00 2001 > From: Akhilesh Kumar > Date: Fri, 4 May 2012 18:52:46 +0530 > Subject: [PATCH 1/1] Patch fix the backtrcae problem using unwind_stack()) > When ftrace is used, unwind_stack() is unable to retrieve the frame info > and call-trace doesn't work. > > test module > ---------------- > static struct timer_list backtrace_timer; > static void backtrace_test_timer(unsigned long data) > { > printk("Testing a backtrace from irq context.\n"); > printk("The following trace is a kernel self test and not a > bug!\n"); > dump_stack(); > } > static int backtrace_regression_test(void) > { > printk("====[ backtrace testing ]===========\n"); > printk("Testing a backtrace from process context.\n"); > printk("The following trace is a kernel self test and not a > bug!\n"); > dump_stack(); > > init_timer(&backtrace_timer); > backtrace_timer.function = backtrace_test_timer; > mod_timer(&backtrace_timer, jiffies + 10); > > msleep(10); > printk("====[ end of backtrace testing ]====\n"); > return 0; > } > static void exitf(void) > { > } > module_init(backtrace_regression_test); > module_exit(exitf); > MODULE_LICENSE("GPL"); > --------------------------------------------------------------------- > out put when HAVE_FUNCTION_TRACER is disable > > ====[ backtrace testing ]=========== > Testing a backtrace from process context. > The following trace is a kernel self test and not a bug! > Testing a backtrace. > The following trace is a kernel self test and not a bug! > Call Trace: > [<80295134>] dump_stack+0x8/0x34 > [] backtrace_regression_test+0x60/0x94 [sisc_backtrcae] > [<800004f0>] do_one_initcall+0xf0/0x1d0 > [<80060954>] sys_init_module+0x19c8/0x1c60 > [<8000a418>] stack_done+0x20/0x40 > > output befor patch when HAVE_FUNCTION_TRACER is enable > --------------------------------------------------------------------- > VDLinux#> insmod sisc_backtrcae.ko > ====[ backtrace testing ]=========== > Testing a backtrace from process context. > The following trace is a kernel self test and not a bug! > Testing a backtrace. > The following trace is a kernel self test and not a bug! > Call Trace: > [<802e5164>] dump_stack+0x1c/0x50 > [<802e5164>] dump_stack+0x1c/0x50 > ====[ end of backtrace testing ]==== > ------------------------------------------------------ > above shows the wrong back trcae > > output after patch when HAVE_FUNCTION_TRACER is enable > ---------------------------------------------------------------------- > ====[ backtrace testing ]=========== > Testing a backtrace from process context. > The following trace is a kernel self test and not a bug! > Testing a backtrace. > The following trace is a kernel self test and not a bug! > Call Trace: > [<802eb1a4>] dump_stack+0x20/0x54 > [] backtrace_test_timer+0x5c/0x74 [sisc_backtrcae] > [] init_module+0x68/0xa0 [sisc_backtrcae] > [<80000508>] do_one_initcall+0x108/0x1f0 > [<8006d4c4>] sys_init_module+0x1a10/0x1c74 > [<8000b038>] stack_done+0x20/0x40 > ------------------------------------------------------------------ > > get_frame_info() is used to fetch the frame information from the > function. > However, > 1. this function just considers the first stack adjustment for frame > size. > 2. On finding the save_lr instruction, it returns. > It doesn't handle the ftrace condition. > > If Dynamic Frace "CONFIG_DYNAMIC_FTRACE" is enabled, the instrumentation > code is: > - jal > - addiu sp,sp,-8 > Thus, the current Frame Size of function is increased by 8 for Ftrace. > > Signed-off-by: Akhilesh Kumar > Signed-off-by: Himanshu Maithani > --- > arch/mips/kernel/process.c | 67 > ++++++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 67 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c > index 7955409..df72738 100644 > --- a/arch/mips/kernel/process.c > +++ b/arch/mips/kernel/process.c > @@ -290,12 +290,45 @@ static inline int is_sp_move_ins(union > mips_instruction *ip) > return 0; > } > > +#ifdef CONFIG_DYNAMIC_FTRACE > +/* > + * To create the jal <> instruction from mcount. > + * taken from: > + * - arch/mips/kernel/ftrace.c > + */ > +#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ > +#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */ > +#define INSN_JAL(addr) \ > + ((unsigned int)(JAL | (((addr) >> 2) & ADDR_MASK))) > + > +/* > + * We assume jal / to be present in > + * first JAL_MAX_OFFSET instructions. > + * Increment this, if its otherwise > + */ > +#define JAL_MAX_OFFSET 16U > +#define MCOUNT_STACK_INST 0x27bdfff8 /* addiu sp,sp,-8 */ > + > +/* > + * If Dynamic Ftrace is enabled, ftrace_caller is the trace function. > + * Otherwise its - mcount > + */ > +extern void ftrace_caller(void); > +#endif /* CONFIG_DYNAMIC_FTRACE */ > + > static int get_frame_info(struct mips_frame_info *info) > { > union mips_instruction *ip = info->func; > unsigned max_insns = info->func_size / sizeof(union mips_instruction); > unsigned i; > > +#ifdef CONFIG_DYNAMIC_FTRACE > + unsigned max_prolog_inst = max_insns; > + int jal_found = 0; > + /* instruction corresponding to jal <_mcount>/ */ > + int jal_mcount = 0; > +#endif > + > info->pc_offset = -1; > info->frame_size = 0; > > @@ -306,6 +339,28 @@ static int get_frame_info(struct mips_frame_info > *info) > max_insns = 128U; /* unknown function size */ > max_insns = min(128U, max_insns); > > +#ifdef CONFIG_DYNAMIC_FTRACE > + max_prolog_inst = min(JAL_MAX_OFFSET, max_prolog_inst); > + jal_mcount = INSN_JAL((unsigned)&ftrace_caller); > + > + for (i = 0; i < max_prolog_inst; i++, ip++) { > + if ((*(int *)ip == jal_mcount) || > + /* > + * for dyn ftrace, the code initially has 0. > + * so we check whether the next instruction is > + * addiu sp,sp,-8 > + */ > + (!(*(int *)ip) && > + (*(int *)(ip + 1) == MCOUNT_STACK_INST)) > + ) { > + jal_found = 1; > + break; > + } > + } > + /* restore the ip to start of function */ > + ip = info->func; > +#endif > + > for (i = 0; i < max_insns; i++, ip++) { > > if (is_jal_jalr_jr_ins(ip)) > @@ -321,6 +376,18 @@ static int get_frame_info(struct mips_frame_info > *info) > break; > } > } > +#ifdef CONFIG_DYNAMIC_FTRACE > + /* > + * to offset the effect of: > + * addiu sp,sp,-8 > + */ > + if (jal_found) { > + if (info->frame_size) > + info->frame_size += 8; > + if (info->pc_offset >= 0) > + info->pc_offset += 8 / sizeof(long); > + } > +#endif > if (info->frame_size && info->pc_offset >= 0) /* nested */ > return 0; > if (info->pc_offset < 0) /* leaf */ > -- > 1.7.8.4 > > --047d7b2e4f620ba55f04bf40e17f Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Hi Ralf,=A0<= /div>
=A0
When ftrace is used, unwind_stack() is unable to re= trieve the frame info
and call-trace doesn't work. Please find the bug fix patch when HA= VE_FUNCTION_TRACER is enable.=A0

Please comment.

=A0
=A0
=A0=A0
From 8= 9004f88a1f8399be7a856b43b475f06c3d5bb30 Mon Sep 17 00:00:00 2001
From: =A0Akhilesh Kumar <= akhilesh.lxr@gmail.com>
Date: Fri, 4 May 2012 18:52:46 +05= 30
Subject: [PATCH 1/1] Patch fix the backtrcae =A0problem using = unwind_stack())
When ftrace is used, unwind_stack() is unable to retrieve the frame in= fo
and call-trace doesn't work.

test= module
----------------
static struct timer_list backt= race_timer;
static void backtrace_test_timer(unsigned long data)
{
=
=A0 =A0 =A0 =A0 printk("Testing a backtrace from irq context.\n&q= uot;);
=A0 =A0 =A0 =A0 printk("The following trace is a kern= el self test and not a
bug!\n");
=A0 =A0 =A0 =A0 dump_stack();
}
static int backtrace_regression_test(void)
{
=A0= =A0 =A0 =A0 printk("=3D=3D=3D=3D[ backtrace testing ]=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D\n");
=A0 =A0 =A0 =A0 printk("Testing= a backtrace from process context.\n");
=A0 =A0 =A0 =A0 printk("The following trace is a kernel self test= and not a
bug!\n");
=A0 =A0 =A0 =A0 dump_stack();=

=A0 =A0 =A0 =A0 init_timer(&backtrace_timer);=
=A0 =A0 =A0 =A0 backtrace_timer.function =3D backtrace_test_time= r;
=A0 =A0 =A0 =A0 mod_timer(&backtrace_timer, jiffies + 10);

=A0 =A0 =A0 =A0 msleep(10);
=A0 =A0 =A0 =A0 pri= ntk("=3D=3D=3D=3D[ end of backtrace testing ]=3D=3D=3D=3D\n");
=A0 =A0 =A0 =A0 return 0;
}
static void exitf(void)
{
}
modul= e_init(backtrace_regression_test);
module_exit(exitf);
= MODULE_LICENSE("GPL");
--------------------------------= -------------------------------------
out put when HAVE_FUNCTION_TRACER is disable

= =3D=3D=3D=3D[ backtrace testing ]=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Testing a backtrace from process context.
The following trace i= s a kernel self test and not a bug!
Testing a backtrace.
The following trace is a kernel self te= st and not a bug!
Call Trace:
[<80295134>] dump_s= tack+0x8/0x34
[<c0946060>] backtrace_regression_test+0x60/0= x94 [sisc_backtrcae]
[<800004f0>] do_one_initcall+0xf0/0x1d0
[<80060954&= gt;] sys_init_module+0x19c8/0x1c60
[<8000a418>] stack_done+= 0x20/0x40

output befor patch when HAVE_FUNCTION_TR= ACER is enable
---------------------------------------------------------------------<= /div>
VDLinux#> insmod sisc_backtrcae.ko
=3D=3D=3D=3D[ bac= ktrace testing ]=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Testing a backt= race from process context.
The following trace is a kernel self test and not a bug!
Tes= ting a backtrace.
The following trace is a kernel self test and n= ot a bug!
Call Trace:
[<802e5164>] dump_stack+0x1= c/0x50
[<802e5164>] dump_stack+0x1c/0x50
=3D=3D=3D=3D[ end of= backtrace testing ]=3D=3D=3D=3D
--------------------------------= ----------------------
above shows the wrong back trcae

output after patch when HAVE_FUNCTION_TRACER is enable
----------= ------------------------------------------------------------
=3D= =3D=3D=3D[ backtrace testing ]=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
T= esting a backtrace from process context.
The following trace is a kernel self test and not a bug!
Tes= ting a backtrace.
The following trace is a kernel self test and n= ot a bug!
Call Trace:
[<802eb1a4>] dump_stack+0x2= 0/0x54
[<c003405c>] backtrace_test_timer+0x5c/0x74 [sisc_backtrcae]
[<c00340dc>] init_module+0x68/0xa0 [sisc_backtrcae]
= [<80000508>] do_one_initcall+0x108/0x1f0
[<8006d4c4>]= sys_init_module+0x1a10/0x1c74
[<8000b038>] stack_done+0x20/0x40
--------------------= ----------------------------------------------

get= _frame_info() is used to fetch the frame information from the
function.
However,
1. this function just considers the = first stack adjustment for frame
size.
2. On finding th= e save_lr instruction, it returns.
It doesn't handle the ftra= ce condition.

If Dynamic Frace "CONFIG_DYNAMIC_FTRACE" is e= nabled, the instrumentation code is:
=A0- jal <ftrace_caller&g= t;
=A0- addiu sp,sp,-8
Thus, the current Frame Size of = function is increased by 8 for Ftrace.

Signed-off-by: Akhilesh Kumar <akhilesh.lxr@gmail.com>
Signed-off-by= : Himanshu Maithani <hmaithani@gm= ail.com>
---
=A0arch/mips/kernel/process.c | =A0 67 +++++++++++++++++= +++++++++++++++++++++++++++
=A01 files changed, 67 insertions(+),= 0 deletions(-)

diff --git a/arch/mips/kernel/proc= ess.c b/arch/mips/kernel/process.c
index 7955409..df72738 100644
--- a/arch/mips/kernel/process= .c
+++ b/arch/mips/kernel/process.c
@@ -290,12 +290,45 = @@ static inline int is_sp_move_ins(union mips_instruction *ip)
=A0 return 0;
=A0}
=A0
+#ifdef CONFIG_DYNAMIC= _FTRACE
+/*
+ * To create the jal <> instruction = from mcount.
+ * taken from:
+ * - arch/mips/kernel/ftr= ace.c
+ */
+#define ADDR_MASK 0x03ffffff =A0 =A0/* =A0op_code|addr= : 31...26|25 ....0 */
+#define JAL 0x0c000000 =A0 =A0 =A0/* jump= & link: ip --> ra, jump to target */
+#define INSN_JAL(ad= dr) =A0\
+ =A0 =A0 =A0((unsigned int)(JAL | (((addr) >> 2) & ADDR_MAS= K)))
+
+/*
+ * We assume jal <mcount>/&= lt;ftrace_caller> to be present in
+ * first JAL_MAX_OFFSET in= structions.
+ * Increment this, if its otherwise
+ */
+#define= JAL_MAX_OFFSET 16U
+#define MCOUNT_STACK_INST 0x27bdfff8 /* addi= u =A0 sp,sp,-8 */
+
+/*
+ * If Dynamic Ftrace= is enabled, ftrace_caller is the trace function.
+ * Otherwise its - mcount
+ */
+extern void =A0ft= race_caller(void);
+#endif /* CONFIG_DYNAMIC_FTRACE */
= +
=A0static int get_frame_info(struct mips_frame_info *info)
=A0{
=A0 union mips_instruction *ip =3D info->func;
=
=A0 unsigned max_insns =3D info->func_size / sizeof(union mips_inst= ruction);
=A0 unsigned i;
=A0
+#ifdef CONFIG_= DYNAMIC_FTRACE
+ unsigned max_prolog_inst =3D max_insns;
+ int jal_found = =3D 0;
+ /* instruction corresponding to jal <_mcount>/<= ftrace_caller> */
+ int jal_mcount =3D 0;
+#endif
+
=A0 info->pc_offset =3D -1;
=A0 info->frame_siz= e =3D 0;
=A0
@@ -306,6 +339,28 @@ static int get_frame_= info(struct mips_frame_info *info)
=A0 =A0max_insns =3D 128U; /* = unknown function size */
=A0 max_insns =3D min(128U, max_insns);
=A0
+#ifde= f CONFIG_DYNAMIC_FTRACE
+ max_prolog_inst =3D min(JAL_MAX_OFFSET,= max_prolog_inst);
+ jal_mcount =3D INSN_JAL((unsigned)&ftrac= e_caller);
+
+ for (i =3D 0; i < max_prolog_inst; i++, ip++) {
=
+ =A0if ((*(int *)ip =3D=3D jal_mcount) ||
+ =A0 =A0/*
=
+ =A0 =A0 * for dyn ftrace, the code initially has 0.
+ =A0 = =A0 * so we check whether the next instruction is
+ =A0 =A0 * addiu =A0 sp,sp,-8
+ =A0 =A0 */
+ =A0 = =A0(!(*(int *)ip) &&
+ =A0 =A0 (*(int *)(ip + 1) =3D=3D M= COUNT_STACK_INST))
+ =A0 =A0 ) {
+ =A0 jal_found =3D 1;=
+ =A0 break;
+ =A0}
+ }
+ /* restore the ip to start of functio= n */
+ ip =3D info->func;
+#endif
+
<= div>=A0 for (i =3D 0; i < max_insns; i++, ip++) {
=A0
=A0 =A0if (is_jal_jalr_jr_ins(ip))
@@ -321,6 +376,18 @@ static int get_frame_info(struct mips_frame_info = *info)
=A0 =A0 break;
=A0 =A0}
=A0 }
+#ifdef CONFIG_DYNAMIC_FTRACE
+ /*
+ =A0* to offset t= he effect of:
+ =A0* addiu =A0 sp,sp,-8
+ =A0*/
+ if (jal_found)= {
+ =A0if (info->frame_size)
+ =A0 info->frame_s= ize +=3D 8;
+ =A0if (info->pc_offset >=3D 0)
+ = =A0 info->pc_offset +=3D 8 / sizeof(long);
+ }
+#endif
=A0 if (info->frame_size &&= info->pc_offset >=3D 0) /* nested */
=A0 =A0return 0;
=A0 if (info->pc_offset < 0) /* leaf */
--=A0
1.7.8.4


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desb02goqqLjyUnJa2/Ctz3Lzq8B4rDQO36hIAEsMeeQBtzlMR+UW4L7/kBAh7W43YP5 cDXhWCwuNSNjt3HSPTriIbNblu0sadzM2Y/hs5Mwc8gJB+f1Kr2mk7CJavmjXsaG44sY DI1jXRnmt6TbS+/2x/dZhJLovx1geL58363Uh5cm6keJYkfRPsU6/zw7VOMCo/1tEIvU k+Huo+VVqzQmDN6HP4JlecjUDBVXVjhqh5qtjrWdlObLS16Itcu3S/3VItV/Cv6lXfG7 DJKQ== Received: by 10.68.230.131 with SMTP id sy3mr291318pbc.17.1336256572990; Sat, 05 May 2012 15:22:52 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.196.163 with HTTP; Sat, 5 May 2012 15:22:32 -0700 (PDT) In-Reply-To: <4FA3BAA6.5060200@mvista.com> References: <1336084845-28995-1-git-send-email-mattst88@gmail.com> <4FA3BAA6.5060200@mvista.com> From: Matt Turner Date: Sat, 5 May 2012 18:22:32 -0400 Message-ID: Subject: Re: [PATCH] mips: set ST0_MX flag for MDMX To: Sergei Shtylyov Cc: Ralf Baechle , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 33162 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 428 Lines: 19 On Fri, May 4, 2012 at 7:16 AM, Sergei Shtylyov wrote: > Hello. > > > On 04-05-2012 2:40, Matt Turner wrote: > >> As the comment in commit 3301edcb > > >   Please also specify that commit's summary in parens. > > >> says, DSP and MDMX share the same >> config flag bit. Everything in the first sentence after the comma *is* the summary of that commit. "DSP and MDMX share the same config flag bit" Matt From mattst88@gmail.com Sun May 6 00:23:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 00:23:30 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:62080 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903612Ab2EEWXU (ORCPT ); Sun, 6 May 2012 00:23:20 +0200 Received: by yenr9 with SMTP id r9so1250858yen.36 for ; Sat, 05 May 2012 15:23:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=EFWEDx1FZ83DhuwolRn2h5RVIGoxnm9Tpt+aEad1lyE=; b=Togtd+XjQtLFsRanKEOvCN6aV6rkVYRVCBJyyvXU0aK+9RDXL2eSRb0BDPMkg9kfc0 0iKxW8HDKitYGusoIz+27Rl6tlkgox+FoZvuIhBhvZImxBGn+YP7i7WzKUcEi9MjxrI4 0dkttzB/Qa34ci7n0eu3Q4QvPji7DP/niAttAvUfRhC3PV0qJjJkoPWWuCIGu+VEnEtV GI7PT1Ai32zSKkjS++yHec2Sw34NKvJiMKBSO9qNj8VK75rlo42kMDg6QmnliLB3cY6f SDGn41QcDKPRaK5suD/oMCDzB4CW2QV2KzfyqOWLo3bsQnfE//7U1rM4VqBFmqhhZ2yU 6DlQ== Received: by 10.236.72.133 with SMTP id t5mr13265888yhd.94.1336256594569; Sat, 05 May 2012 15:23:14 -0700 (PDT) Received: from localhost (cpe-174-109-057-184.nc.res.rr.com. [174.109.57.184]) by mx.google.com with ESMTPS id 32sm20145032anu.14.2012.05.05.15.23.13 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 05 May 2012 15:23:13 -0700 (PDT) From: Matt Turner To: Ralf Baechle Cc: linux-mips@linux-mips.org, Matt Turner Subject: [PATCH] mips: include export.h in for EXPORT_SYMBOL in ops-loongson2.c Date: Sat, 5 May 2012 18:22:55 -0400 Message-Id: <1336256575-31038-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.3.4 X-archive-position: 33163 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 732 Lines: 25 Fixes warning: data definition has no type or storage class [enabled by default] warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' [-Wimplicit-int] warning: parameter names (without types) in function declaration [enabled by default] Signed-off-by: Matt Turner --- arch/mips/pci/ops-loongson2.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c index d657ee0..afd2211 100644 --- a/arch/mips/pci/ops-loongson2.c +++ b/arch/mips/pci/ops-loongson2.c @@ -15,6 +15,7 @@ #include #include #include +#include #include -- 1.7.3.4 From macro@linux-mips.org Sun May 6 02:30:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 02:30:08 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:44223 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903603Ab2EFAaB (ORCPT ); Sun, 6 May 2012 02:30:01 +0200 Date: Sun, 6 May 2012 01:30:01 +0100 (BST) From: "Maciej W. Rozycki" To: "Steven J. Hill" cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2,03/10] MIPS: Add support for the M14K core. In-Reply-To: <1334865913-12212-2-git-send-email-sjhill@mips.com> Message-ID: References: <1334865913-12212-1-git-send-email-sjhill@mips.com> <1334865913-12212-2-git-send-email-sjhill@mips.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33164 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1022 Lines: 25 On Thu, 19 Apr 2012, Steven J. Hill wrote: > diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h > index ddd8b4a..00e5adf 100644 > --- a/arch/mips/include/asm/cpu.h > +++ b/arch/mips/include/asm/cpu.h > @@ -95,6 +95,7 @@ > #define PRID_IMP_74K 0x9700 > #define PRID_IMP_1004K 0x9900 > #define PRID_IMP_1074K 0x9a00 > +#define PRID_IMP_14K 0x9c00 Here and all over this change -- shouldn't this be spelled M14K rather than 14K just as for M4K vs 4K? I think pretending the M14K is a 14K will cause us unnecessary hassle if an actual 14K is ever made (there's some functional pattern in how the M4K compares to the 4K and then how the transition from the M4K to the M14K has been made; if the 4K RTL is ever ported to microMIPS support one might expect it to be called the 14K, so let's keep the name space clean). Or actually this should even be PRID_IMP_M14KC (and likewise elsewhere throughout) as the M14K has a different PRId -> 0x9b00. Let's keep the naming correct. Maciej From macro@linux-mips.org Sun May 6 02:42:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 02:43:04 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:40304 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903603Ab2EFAm6 (ORCPT ); Sun, 6 May 2012 02:42:58 +0200 Date: Sun, 6 May 2012 01:42:58 +0100 (BST) From: "Maciej W. Rozycki" To: "Steven J. Hill" cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2,3/9] MIPS: Add support for the M14KE core. In-Reply-To: <1334867214-12451-1-git-send-email-sjhill@mips.com> Message-ID: References: <1334867214-12451-1-git-send-email-sjhill@mips.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33165 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1314 Lines: 38 On Thu, 19 Apr 2012, Steven J. Hill wrote: > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h > index 556afa2..3b50744 100644 > --- a/arch/mips/include/asm/cpu-features.h > +++ b/arch/mips/include/asm/cpu-features.h > @@ -98,6 +98,9 @@ > #ifndef kernel_uses_smartmips_rixi > #define kernel_uses_smartmips_rixi 0 > #endif > +#ifndef cpu_has_mmips > +#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) > +#endif > #ifndef cpu_has_vtag_icache > #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) > #endif I think this has crept in here from the microMIPS change, right? This patch doesn't make any use of this macro. > diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h > index 00e5adf..242a401 100644 > --- a/arch/mips/include/asm/cpu.h > +++ b/arch/mips/include/asm/cpu.h > @@ -96,6 +96,7 @@ > #define PRID_IMP_1004K 0x9900 > #define PRID_IMP_1074K 0x9a00 > #define PRID_IMP_14K 0x9c00 > +#define PRID_IMP_14KE 0x9e00 > > /* > * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE Like with the M14Kc this should be PRID_IMP_M14KEC here and throughout (spelled out as M14KEc -- with a small "c" -- where applicable). There's another processor called M14KE that is different. Maciej From macro@linux-mips.org Sun May 6 03:32:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 03:32:10 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:37498 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903609Ab2EFBcC (ORCPT ); Sun, 6 May 2012 03:32:02 +0200 Date: Sun, 6 May 2012 02:32:02 +0100 (BST) From: "Maciej W. Rozycki" To: "Steven J. Hill" cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2,4/9] MIPS: Add microMIPS versions of breakpoints, BUG, etc. In-Reply-To: <1334867225-12486-1-git-send-email-sjhill@mips.com> Message-ID: References: <1334867225-12486-1-git-send-email-sjhill@mips.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33166 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9269 Lines: 259 On Thu, 19 Apr 2012, Steven J. Hill wrote: > Add breakpoints, BUG() functions, DSP instruction masks, and > debug messages for microMIPS. Also add '.insn' directive to > a number of files that must assemble correctly when using the > microMIPS or MIPS16e instruction sets. Erm, you do not build the kernel as a MIPS16 binary, do you? I suggest that you remove the reference to the MIPS16 ASE to avoid confusion. > diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h > index 9161e68..56758eb 100644 > --- a/arch/mips/include/asm/break.h > +++ b/arch/mips/include/asm/break.h > @@ -27,6 +27,14 @@ > #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ > #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ > #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ > + > +/* microMIPS definitions */ > +#define MM_BRK_BUG 12 /* Used by BUG() */ > +#define MM_BRK_KDB 13 /* Used in KDB_ENTER() */ > +#define MM_BRK_MEMU 14 /* Used by FPU emulator */ > +#define MM_BRK_MULOVF 15 /* Multiply overflow */ > + > +/* MIPS32/64 definitions */ Hmm, "Standard MIPS..." perhaps, these bits date back to the MIPS I ISA that predates the invention of the MIPS32 and MIPS64 architectures by some 15 years... > #define BRK_BUG 512 /* Used by BUG() */ > #define BRK_KDB 513 /* Used in KDB_ENTER() */ > #define BRK_MEMU 514 /* Used by FPU emulator */ Hmm, not necessarily a problem with your change, but what exactly is BRK_MULOVF used by? GAS certainly does not produce it, it uses the standard code of 6 for run-time multiplication overflow checks. Do we need to reserve this code at all? > diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h > index 540c98a..7afa2e5 100644 > --- a/arch/mips/include/asm/bug.h > +++ b/arch/mips/include/asm/bug.h > @@ -10,7 +10,11 @@ > > static inline void __noreturn BUG(void) > { > +#ifdef CONFIG_CPU_MICROMIPS > + __asm__ __volatile__("break %0" : : "i" (MM_BRK_BUG)); > +#else > __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); > +#endif > unreachable(); > } > Ugh, please factor it out to a single macro, don't chop function bodies with #ifdef. > @@ -27,7 +31,11 @@ static inline void __BUG_ON(unsigned long condition) > return; > } > __asm__ __volatile__("tne $0, %0, %1" > +#ifdef CONFIG_CPU_MICROMIPS > + : : "r" (condition), "i" (MM_BRK_BUG)); > +#else > : : "r" (condition), "i" (BRK_BUG)); > +#endif > } > > #define BUG_ON(C) __BUG_ON((unsigned long)(C)) Likewise. > diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h > index e9bfc08..3149b30 100644 > --- a/arch/mips/include/asm/dsp.h > +++ b/arch/mips/include/asm/dsp.h > @@ -16,7 +16,11 @@ > #include > > #define DSP_DEFAULT 0x00000000 > +#ifdef CONFIG_CPU_MICROMIPS > +#define DSP_MASK 0x7f > +#else > #define DSP_MASK 0x3ff > +#endif > > #define __enable_dsp_hazard() \ > do { \ Where's the corresponding change to rddsp() and wrdsp() to encode the respective instructions correctly in the microMIPS mode? The bit patterns are not exactly the same. Also I think we should simply remove DSP_MASK and instead define rddsp_all() and wrdsp_all() macros that use the full mask by default (corresponding to single-argument assembly instructions; we'll be able to use them once we've decided to move away from the current hacks). Interestingly enough bits 9:6 of the mask aren't used in the MIPS32/64 variation of these instructions anyway, but I think it's safer to keep them as ones for future compatibility. > diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h > index 6ebf173..007adca 100644 > --- a/arch/mips/include/asm/futex.h > +++ b/arch/mips/include/asm/futex.h > @@ -31,6 +31,7 @@ > " beqzl $1, 1b \n" \ > __WEAK_LLSC_MB \ > "3: \n" \ > + " .insn \n" \ > " .set pop \n" \ > " .set mips0 \n" \ > " .section .fixup,\"ax\" \n" \ Ugh, that looks like a bug in GAS, although it may be difficult to fix. The assembler should note the section switch and annotate "3" appropriately according to what happens when the current section is restored. Meanwhile this is a reasonable workaround, thanks. Likewise elsewhere. I suggest to make all .insn additions a separate change though. > diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c > index e309665..2c0f781 100644 > --- a/arch/mips/kernel/proc.c > +++ b/arch/mips/kernel/proc.c > @@ -41,29 +41,30 @@ static int show_cpuinfo(struct seq_file *m, void *v) > > seq_printf(m, "processor\t\t: %ld\n", n); > sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", > - cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); > + cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); > seq_printf(m, fmt, __cpu_name[n], > - (version >> 4) & 0x0f, version & 0x0f, > - (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); > + (version >> 4) & 0x0f, version & 0x0f, > + (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); > seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", > - cpu_data[n].udelay_val / (500000/HZ), > - (cpu_data[n].udelay_val / (5000/HZ)) % 100); > + cpu_data[n].udelay_val / (500000/HZ), > + (cpu_data[n].udelay_val / (5000/HZ)) % 100); > seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); > seq_printf(m, "microsecond timers\t: %s\n", > - cpu_has_counter ? "yes" : "no"); > + cpu_has_counter ? "yes" : "no"); > seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); > seq_printf(m, "extra interrupt vector\t: %s\n", > - cpu_has_divec ? "yes" : "no"); > + cpu_has_divec ? "yes" : "no"); > seq_printf(m, "hardware watchpoint\t: %s", > - cpu_has_watch ? "yes, " : "no\n"); > + cpu_has_watch ? "yes, " : "no\n"); > if (cpu_has_watch) { > seq_printf(m, "count: %d, address/irw mask: [", > - cpu_data[n].watch_reg_count); > + cpu_data[n].watch_reg_count); > for (i = 0; i < cpu_data[n].watch_reg_count; i++) > seq_printf(m, "%s0x%04x", i ? ", " : "" , > - cpu_data[n].watch_reg_masks[i]); > + cpu_data[n].watch_reg_masks[i]); > seq_printf(m, "]\n"); > } > + seq_printf(m, "microMIPS\t\t: %s\n", cpu_has_mmips ? "yes" : "no"); > seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", > cpu_has_mips16 ? " mips16" : "", > cpu_has_mdmx ? " mdmx" : "", I suggest that you submit formatting fixes as a separate change. > @@ -73,13 +74,13 @@ static int show_cpuinfo(struct seq_file *m, void *v) > cpu_has_mipsmt ? " mt" : "" > ); > seq_printf(m, "shadow register sets\t: %d\n", > - cpu_data[n].srsets); > + cpu_data[n].srsets); > seq_printf(m, "kscratch registers\t: %d\n", > - hweight8(cpu_data[n].kscratch_mask)); > + hweight8(cpu_data[n].kscratch_mask)); > seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); > > sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", > - cpu_has_vce ? "%u" : "not available"); > + cpu_has_vce ? "%u" : "not available"); > seq_printf(m, fmt, 'D', vced_count); > seq_printf(m, fmt, 'I', vcei_count); > seq_printf(m, "\n"); Likewise. This doesn't even look valid to me. > diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c > index 7c24c29..4b4bbc0 100644 > --- a/arch/mips/kernel/ptrace.c > +++ b/arch/mips/kernel/ptrace.c > @@ -364,6 +364,7 @@ long arch_ptrace(struct task_struct *child, long request, > preempt_enable(); > break; > } > +#ifndef CONFIG_CPU_MICROMIPS > case DSP_BASE ... DSP_BASE + 5: { > dspreg_t *dregs; > > @@ -384,6 +385,7 @@ long arch_ptrace(struct task_struct *child, long request, > } > tmp = child->thread.dsp.dspcontrol; > break; > +#endif > default: > tmp = 0; > ret = -EIO; > @@ -453,6 +455,7 @@ long arch_ptrace(struct task_struct *child, long request, > case FPC_CSR: > child->thread.fpu.fcr31 = data; > break; > +#ifndef CONFIG_CPU_MICROMIPS > case DSP_BASE ... DSP_BASE + 5: { > dspreg_t *dregs; > > @@ -472,6 +475,7 @@ long arch_ptrace(struct task_struct *child, long request, > } > child->thread.dsp.dspcontrol = data; > break; > +#endif > default: > /* The rest are not allowed. */ > ret = -EIO; This looks bogus to me, there's nothing stopping one from poking at DSP registers if the kernel has been built as a microMIPS binary. > diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c > index c14f6df..bae32a7 100644 > --- a/arch/mips/mm/fault.c > +++ b/arch/mips/mm/fault.c > @@ -25,6 +25,7 @@ > #include > #include > #include /* For VMALLOC_END */ > +#include > #include > > /* > @@ -231,6 +232,7 @@ no_context: > "virtual address %0*lx, epc == %0*lx, ra == %0*lx\n", > raw_smp_processor_id(), field, address, field, regs->cp0_epc, > field, regs->regs[31]); > + dump_tlb_all(); > die("Oops", regs); > > out_of_memory: That does not appear relevant. Please submit separately and explain the purpose. Maciej From macro@linux-mips.org Sun May 6 09:04:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 09:04:41 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:38129 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903611Ab2EFHEd (ORCPT ); Sun, 6 May 2012 09:04:33 +0200 Date: Sun, 6 May 2012 08:04:33 +0100 (BST) From: "Maciej W. Rozycki" To: David Daney cc: Artem Bityutskiy , Ralf Baechle , MIPS Mailing List , MTD Maling List Subject: Re: [PATCH 1/2] MIPS: Kbuild: remove -Werror In-Reply-To: <4F9AD14E.9060008@gmail.com> Message-ID: References: <1335534510-12573-1-git-send-email-dedekind1@gmail.com> <4F9AD14E.9060008@gmail.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33167 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 850 Lines: 20 On Fri, 27 Apr 2012, David Daney wrote: > > MIPS build fails with the standard W=1 Kbuild switch with because of the > > -Werror gcc switch. > > > > This patch removes the gcc switch to make W=1 work. Mips is the only > > architecture I know which does not build with W=1 and this upsets my aiaiai > > scripts. And in general, you never know which warnings newer versions of gcc > > will start emiting so having -Werror by default is not the best idea. > > > > Signed-off-by: Artem Bityutskiy > > I think the warning messages are enough, we don't need to break things. I disagree. People generally don't fix their broken code just because it triggers warnings. The cases where GCC is genuinely confused are the minority -- and even if so, chances are the human reader of that code will also be. Maciej From macro@linux-mips.org Sun May 6 09:06:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 09:06:23 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:38291 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903611Ab2EFHGP (ORCPT ); Sun, 6 May 2012 09:06:15 +0200 Date: Sun, 6 May 2012 08:06:15 +0100 (BST) From: "Maciej W. Rozycki" To: Artem Bityutskiy cc: Ralf Baechle , MIPS Mailing List , MTD Maling List Subject: Re: [PATCH 2/2] MIPS: bcm63xx: kbuild: remove -Werror In-Reply-To: <1335534510-12573-2-git-send-email-dedekind1@gmail.com> Message-ID: References: <1335534510-12573-1-git-send-email-dedekind1@gmail.com> <1335534510-12573-2-git-send-email-dedekind1@gmail.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33168 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 865 Lines: 19 On Fri, 27 Apr 2012, Artem Bityutskiy wrote: > From: Artem Bityutskiy > > I cannot build bcm963xx with the standard Kbuild W=1 switch: > > arch/mips/bcm63xx/boards/board_bcm963xx.c: At top level: > arch/mips/bcm63xx/boards/board_bcm963xx.c:647:5: error: no previous prototype for 'bcm63xx_get_fallback_sprom' [-Werror=missing-prototypes] > cc1: all warnings being treated as errors > > This patch removes the gcc switch to make W=1 work. Mips is the only > architecture I know which does not build with W=1 and this upsets my aiaiai > scripts. And in general, you never know which warnings newer versions of gcc > will start emiting so having -Werror by default is not the best idea. If the function has no prototype, then it cannot be reasonably used from outside -- perhaps you meant to mark it static instead? Maciej From dedekind1@gmail.com Sun May 6 09:34:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 09:34:57 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:48483 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903611Ab2EFHex (ORCPT ); Sun, 6 May 2012 09:34:53 +0200 Received: by lbbgg6 with SMTP id gg6so3592568lbb.36 for ; Sun, 06 May 2012 00:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:subject:from:to:cc:date:in-reply-to:references :content-type:x-mailer:mime-version; bh=4dx8ECKyeY/p99+ZQuaB5XCz8zsx60Voaxr+w6/5O1k=; b=pYDtzSsmMfHyPd6UTKHiB9AprZ5E+3/uy8OlBbBx3mqwdnOg9Q+aqXLTgt13mHTHhV cFHoTFPPtTCz2wg8Wg4sCt3eZbODL1+Jek5m9iEg6embSwN6s1n9XxYy7NYzWdNvBS6c u2FjCZ9y+4tUSiFAZNh6k5BFod/4h+rRWakDvErAU0XV/oc+cnNLKIQ2pvsGBkSVmKi6 czZRZOG3ynZP2pHGO/HMmDKdxBQbMkioAyoCQtx6SaFtXKF4ACVh7p5R++KB7CjfD5mo SaNfuLoNUP2O89l6OsVNeYRDBagyDZ7BWUC71vNpWeW7L/uZ5Dy5CK1zNbY9ACdZUi1D veKw== Received: by 10.112.17.233 with SMTP id r9mr5368146lbd.67.1336289687443; Sun, 06 May 2012 00:34:47 -0700 (PDT) Received: from [192.168.255.2] (host-94-101-1-70.igua.fi. [94.101.1.70]) by mx.google.com with ESMTPS id u4sm14916893lad.5.2012.05.06.00.34.45 (version=SSLv3 cipher=OTHER); Sun, 06 May 2012 00:34:46 -0700 (PDT) Message-ID: <1336289676.1996.3.camel@koala> Subject: Re: [PATCH 1/2] MIPS: Kbuild: remove -Werror From: Artem Bityutskiy To: "Maciej W. Rozycki" Cc: David Daney , Ralf Baechle , MIPS Mailing List , MTD Maling List Date: Sun, 06 May 2012 10:34:36 +0300 In-Reply-To: References: <1335534510-12573-1-git-send-email-dedekind1@gmail.com> <4F9AD14E.9060008@gmail.com> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-XPE24xsvL2NdTEv8aqjS" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Mime-Version: 1.0 X-archive-position: 33169 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2281 Lines: 63 --=-XPE24xsvL2NdTEv8aqjS Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sun, 2012-05-06 at 08:04 +0100, Maciej W. Rozycki wrote: > On Fri, 27 Apr 2012, David Daney wrote: >=20 > > > MIPS build fails with the standard W=3D1 Kbuild switch with because o= f the > > > -Werror gcc switch. > > >=20 > > > This patch removes the gcc switch to make W=3D1 work. Mips is the onl= y > > > architecture I know which does not build with W=3D1 and this upsets m= y aiaiai > > > scripts. And in general, you never know which warnings newer versions= of gcc > > > will start emiting so having -Werror by default is not the best idea. > > >=20 > > > Signed-off-by: Artem Bityutskiy > >=20 > > I think the warning messages are enough, we don't need to break things. >=20 > I disagree. People generally don't fix their broken code just because i= t=20 > triggers warnings. The cases where GCC is genuinely confused are the=20 > minority -- and even if so, chances are the human reader of that code wil= l=20 > also be. Aggressive opinion, nothing more. A patch which fixes the real issue a better way would be way more respectful. --=20 Best Regards, Artem Bityutskiy --=-XPE24xsvL2NdTEv8aqjS Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPpimMAAoJECmIfjd9wqK0GLUP/2jpVnGbazRmuOKdKpUJPB5m zKeIVQIi2tuSOo2VZjE69kc3pr1Jml65v6moF3yh3j9Dke9soUVuuB3g5fayxFxb eDqamNWLTi+z2xotRVQz8/gSibytvF0I06AQQb4eA7bV22nz996lHdzGsxA6q8AG MD4lvPdzGw9UzX6FMad9p40M1uWtuqdHQedLQQIGrk6RnnpQw54S9IHiha2fVSx+ xBHC9CqwGDm9vyrYaduMSOV6CVxLDhyB3nKHaR43itjSjnNz5rbvnzDulP4Pj0JB gd+E1Z2RBRfUku0+yPu6o2pThGXu8BkAwbzXpPRY9ljic2mIZdAAaRKPLyycegv/ iT6xQOR/qjPfKXlAu61zbE03OUszj9y05unMe5jLeSoid2M2JXrvMDgMM8G2ibuY VVY/g9/bYXAwUiyBmNYprK8kpDWRt4EHA34A7sS2Wp1IyRlQlJdIBAZykdIM/bre xePOplM3US+b+EbSFjZ0z823FLmdOrtZ40qdVFmo/4qS+chGWUJekBF2KAhCxggp WCuqdjx+yPM9X1TpCddRVukT8VkywjPQ6sIibPgrlkh2z+GIp2uNOLm0ojpysd7v FF16jIF984ic+GgFkwtSYfxz236hGmACsLE1b78BEa63/Z+dLyRKz9bAou44X5A6 1Yzc8yLIgqJylRkONE3E =U2uA -----END PGP SIGNATURE----- --=-XPE24xsvL2NdTEv8aqjS-- From dedekind1@gmail.com Sun May 6 09:37:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 09:37:13 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:35146 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903611Ab2EFHhH (ORCPT ); Sun, 6 May 2012 09:37:07 +0200 Received: by lbbgg6 with SMTP id gg6so3593000lbb.36 for ; Sun, 06 May 2012 00:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:subject:from:to:cc:date:in-reply-to:references :content-type:x-mailer:mime-version; bh=JyXRzu0dOWBcfuz1EeIf9gEDV2VNuX3olol0Osvus2g=; b=k6S7aCLtqVUMdMlSSOC8NiPU/nac2OsObp+QvqWV1V1OLNy+SHH3dqtvB4lwq4vAhh 0IV+ATSF+fC0APR9Haqzx3Hn+Rs7OiSXYzgH+wr7U0uII2b92/cjQ1OK23et/KiZrqm0 gDiTcl5feSJXEGPdWYdH5neK3/tGKf/JDfcoLgVojMSP4Xgdf+cjyrVrPABYYJA/lSON HEddswRBYwSK+f3B4iWb1HrtXT4VivBgzO3wK2tYYaqZ1wa5l+N4A7r3KsE8oWf0Jeyn QBsN3u3UCxMMRjnLeOgoDBvpIAUO4r1jEOnIqWAWgRc8yPVQn+K4LdkFp1VVDDlCpID4 8qrg== Received: by 10.152.123.111 with SMTP id lz15mr10826391lab.18.1336289821459; Sun, 06 May 2012 00:37:01 -0700 (PDT) Received: from [192.168.255.2] (host-94-101-1-70.igua.fi. [94.101.1.70]) by mx.google.com with ESMTPS id uc6sm18262549lbb.3.2012.05.06.00.37.00 (version=SSLv3 cipher=OTHER); Sun, 06 May 2012 00:37:00 -0700 (PDT) Message-ID: <1336289819.1996.5.camel@koala> Subject: Re: [PATCH 2/2] MIPS: bcm63xx: kbuild: remove -Werror From: Artem Bityutskiy To: "Maciej W. Rozycki" Cc: Ralf Baechle , MIPS Mailing List , MTD Maling List Date: Sun, 06 May 2012 10:36:59 +0300 In-Reply-To: References: <1335534510-12573-1-git-send-email-dedekind1@gmail.com> <1335534510-12573-2-git-send-email-dedekind1@gmail.com> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-yeAv7sbnRzUmnPVNgf5D" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Mime-Version: 1.0 X-archive-position: 33170 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2235 Lines: 59 --=-yeAv7sbnRzUmnPVNgf5D Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sun, 2012-05-06 at 08:06 +0100, Maciej W. Rozycki wrote: > On Fri, 27 Apr 2012, Artem Bityutskiy wrote: >=20 > > From: Artem Bityutskiy > >=20 > > I cannot build bcm963xx with the standard Kbuild W=3D1 switch: > >=20 > > arch/mips/bcm63xx/boards/board_bcm963xx.c: At top level: > > arch/mips/bcm63xx/boards/board_bcm963xx.c:647:5: error: no previous pro= totype for 'bcm63xx_get_fallback_sprom' [-Werror=3Dmissing-prototypes] > > cc1: all warnings being treated as errors > >=20 > > This patch removes the gcc switch to make W=3D1 work. Mips is the only > > architecture I know which does not build with W=3D1 and this upsets my = aiaiai > > scripts. And in general, you never know which warnings newer versions o= f gcc > > will start emiting so having -Werror by default is not the best idea. >=20 > If the function has no prototype, then it cannot be reasonably used from= =20 > outside -- perhaps you meant to mark it static instead? No, I meant what I meant - MIPS does not build with W=3D1. --=20 Best Regards, Artem Bityutskiy --=-yeAv7sbnRzUmnPVNgf5D Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPpiobAAoJECmIfjd9wqK0CWgP/09IEFhQNvpYLax535k9UJp8 l7BHh7CoIUy8UOqwz/ofe/oG7mdUgap+Lf6SV97jfGGm5wEhrqrgwFPSo1G/wv0K MYOPcoRVizR+0WsHoksonhQ/34DlVUV7hIiOQPWv4aYeZD+npv9c49icW6z37tny DcYuSASQs0X6MEa1Y724LD7xYqvwTB+hcnnO/C6CsPT5VKf/Ul0NeFM0eojUsuWz lEVOps/GetRSqXLl7ft3M0kpIIk2CDJZir3QWeJyMKDGMC+r0rSaeS/bTiZDNcU7 CPx3puJKdBk2qyAz7kSG7PZSnRWLgWCdZ/n9+pa/R0YxVF+gTl1Uo2vGDGbnWJ9B V+8cG8kFJr4bH/ZLCG/n78252tTkow555eSH1WnGJJ4DGkP2w7LlcoY13Wse+2vQ x/2nGnFq0WPasxsv/I8iQ0JHC3jqG2bkTDqfbYbswzgAAhDsRU41OooUCIFGSSdq mrqQoJTIYPwWiSBIJQUSJLA6UQkNT5vbSeJ4Ia4xtBCDJOa2SKiQXv48+XSos3GC kxa9oa34EpsPiSIOb0T7gMS+f/sm3GycU7w3Dnme7WxfQT/MGmV8OB2dVhG0TmEb Z9MYry6Lj5GhsFoiI46MLFfnUI/eQT9kOuJLnvv+x4dC5BFAGWW15Ha4Ub0ayfls hkwaAo78S4DMR941lWpY =sbZ9 -----END PGP SIGNATURE----- --=-yeAv7sbnRzUmnPVNgf5D-- From macro@linux-mips.org Sun May 6 10:32:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 10:32:25 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:45219 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903614Ab2EFIcR (ORCPT ); Sun, 6 May 2012 10:32:17 +0200 Date: Sun, 6 May 2012 09:32:17 +0100 (BST) From: "Maciej W. Rozycki" To: Artem Bityutskiy cc: David Daney , Ralf Baechle , MIPS Mailing List , MTD Maling List Subject: Re: [PATCH 1/2] MIPS: Kbuild: remove -Werror In-Reply-To: <1336289676.1996.3.camel@koala> Message-ID: References: <1335534510-12573-1-git-send-email-dedekind1@gmail.com> <4F9AD14E.9060008@gmail.com> <1336289676.1996.3.camel@koala> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33171 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 870 Lines: 20 On Sun, 6 May 2012, Artem Bityutskiy wrote: > > I disagree. People generally don't fix their broken code just because it > > triggers warnings. The cases where GCC is genuinely confused are the > > minority -- and even if so, chances are the human reader of that code will > > also be. > > Aggressive opinion, nothing more. A patch which fixes the real issue a > better way would be way more respectful. I didn't trigger the issue, so I have nothing to fix. I would if it was me who did. And my opinion is based on experience. Please check the LMO archives for why Ralf added this option in the first place -- many years ago. It's probably recorded in the git repository too (I'm not sure if the option was added before or after we moved away from CVS, but in any case old change logs have been imported when our current repo was created). Maciej From dedekind1@gmail.com Sun May 6 10:41:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 10:41:23 +0200 (CEST) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:36742 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903611Ab2EFIlQ (ORCPT ); Sun, 6 May 2012 10:41:16 +0200 Received: by laap9 with SMTP id p9so145592laa.36 for ; Sun, 06 May 2012 01:41:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:subject:from:reply-to:to:cc:date:in-reply-to:references :content-type:x-mailer:mime-version; bh=XhQqW23WgQ1pPtm8IxQXKqXsfYYHEs1HLRBD/sTksBo=; b=A07KtA981MVMKXlvDaQIWp1hBCiOWg6AAy+nnKMcS4zFlPLhofAsMvCFZzpYWWvrr2 vorijhMQg5+3RbH9AvWh6x57w+Xoy3ZiLiz7Hq5SG1i8Adexw6Pa7TOWpxXfZbRFHRh2 MFGzlkhgvXn7zlsrabUU1akkz/DiN6W97XwVCSrAUR6fC23Kk/2/IcqTCkXJNmXutHRl lAgvZEWFhkDWETigf3iFsdxuRLWfoinjvxcw/c1bn76WNn8o9L5J46x8FXPmYmtEJCai BGOk6LWhHYJzEkA2wYaATrGVlcXc3dtB8b+DJReiyUF2ROR4bCHozIsGnsrsJcbthz0R g7Tg== Received: by 10.112.46.9 with SMTP id r9mr5371828lbm.81.1336293670658; Sun, 06 May 2012 01:41:10 -0700 (PDT) Received: from [192.168.255.6] (host-94-101-1-70.igua.fi. [94.101.1.70]) by mx.google.com with ESMTPS id n6sm18428266lbn.11.2012.05.06.01.41.09 (version=SSLv3 cipher=OTHER); Sun, 06 May 2012 01:41:09 -0700 (PDT) Message-ID: <1336293478.2801.4.camel@brekeke> Subject: Re: [PATCH 1/2] MIPS: Kbuild: remove -Werror From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: "Maciej W. Rozycki" Cc: David Daney , Ralf Baechle , MIPS Mailing List , MTD Maling List Date: Sun, 06 May 2012 11:37:58 +0300 In-Reply-To: References: <1335534510-12573-1-git-send-email-dedekind1@gmail.com> <4F9AD14E.9060008@gmail.com> <1336289676.1996.3.camel@koala> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-zx+FSKpyo6Iigd1GpIWq" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Mime-Version: 1.0 X-archive-position: 33172 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1731 Lines: 47 --=-zx+FSKpyo6Iigd1GpIWq Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sun, 2012-05-06 at 09:32 +0100, Maciej W. Rozycki wrote: > And my opinion is based on experience. Please check the LMO archives fo= r=20 > why Ralf added this option in the first place -- many years ago. It's= =20 > probably recorded in the git repository too (I'm not sure if the option= =20 > was added before or after we moved away from CVS, but in any case old=20 > change logs have been imported when our current repo was created). We need to figure out how to make -Werror be applied only when we do not have W=3D[123]. --=20 Best Regards, Artem Bityutskiy --=-zx+FSKpyo6Iigd1GpIWq Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPpjhmAAoJECmIfjd9wqK0Iu0P/ResM+xG1yFV6VxH307EfkB7 9PUcwBdciN88g2XvYKvDAGJTN4o2uVRAHVtDuob76yp1o+YbHSHtKWQnu++nFZGF EyVFWpNXFALhJ+tP8GiwZe+t4GGXb5iFWkDMZKGTYz1TokXeHF7uOtH9LbTMss8P hFgkfD9VmaN1BE5HHWndQH5MkQPG6nB0z/L03SzZd5VR7BZcKYYyEbb1wsq4awHD AeO6wpqS5ILtv81lmX5AT2eXbEfMOouXitfgf7VTort2A2KVV0zxBfORqUO+jvvx rPt/dXwYzgJRfOjLly+VUJ0A+2h9nHqGZqNnu6wyh7vfKhWRRSgv1aJkBNCNV0dL 87YGbF1i09hViFUXo9p1gHpcAVKP58T3VQcFg0RmfeBEtKMud9iehiOO7Lb8MPxk J/Td7Ehy9z1Kb+WYd2hWUeFA+7dJVl/5B8GT0sN4K6Zj9007nj67Dt/vqXPF0/Tf VMKzAB8sD1JCehj0YFI1vJPN/A+YN+zOmKVkUE5K5Lpa8AygzMeTHrmNCXNTivhd 7MbTAWhGf1VKtmeI7ZqHaR3imxb6H5wuxnx8LuTSFhaYm1rLWOamMxcKBgSwAAfu X+vyZz/t+gNvqJ0bJF6Gf9PyBMYdyDOctBZcNvVjFkUQnBKu7AIpIpx9e/XVGVUD FYT3A9ldZOgDu4KVgvHS =gV0L -----END PGP SIGNATURE----- --=-zx+FSKpyo6Iigd1GpIWq-- From macro@linux-mips.org Sun May 6 11:14:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 May 2012 11:14:53 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:45606 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903560Ab2EFJOq (ORCPT ); Sun, 6 May 2012 11:14:46 +0200 Date: Sun, 6 May 2012 10:14:46 +0100 (BST) From: "Maciej W. Rozycki" To: Artem Bityutskiy cc: David Daney , Ralf Baechle , MIPS Mailing List , MTD Maling List Subject: Re: [PATCH 1/2] MIPS: Kbuild: remove -Werror In-Reply-To: <1336293478.2801.4.camel@brekeke> Message-ID: References: <1335534510-12573-1-git-send-email-dedekind1@gmail.com> <4F9AD14E.9060008@gmail.com> <1336289676.1996.3.camel@koala> <1336293478.2801.4.camel@brekeke> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33173 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1321 Lines: 28 On Sun, 6 May 2012, Artem Bityutskiy wrote: > > And my opinion is based on experience. Please check the LMO archives for > > why Ralf added this option in the first place -- many years ago. It's > > probably recorded in the git repository too (I'm not sure if the option > > was added before or after we moved away from CVS, but in any case old > > change logs have been imported when our current repo was created). > > We need to figure out how to make -Werror be applied only when we do not > have W=[123]. Hmm, that sounds better, however has the counter-intuitive side-effect of lowering the severity of the warnings that are enabled even without W=[123]. Modern versions of GCC have that selective -Wno-error=foo option and I think it should be possible to build the precise list of warnings not to choke on locally in arch/mips/Kbuild with little Makefile magic, falling back to something sane for older GCC versions (I'm not sure exactly when these selective options were added, certainly sometime between 4.1 and 4.3). This will be a bit imperfect if any of these additional -Wfoo options duplicate ones already added to KBUILD_CFLAGS in our top-level Makefile (either explicitly or via -Wall), but that's about the best we can do. I'll see if I can cook up something quickly. Maciej From macro@linux-mips.org Mon May 7 07:18:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 May 2012 07:18:18 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:56727 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903615Ab2EGFSJ (ORCPT ); Mon, 7 May 2012 07:18:09 +0200 Date: Mon, 7 May 2012 06:18:09 +0100 (BST) From: "Maciej W. Rozycki" To: David Daney cc: "Steven J. Hill" , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 04/10] MIPS: Add micro-assembler support for 'ins' and 'ext' instructions. In-Reply-To: <4F9F3387.1050500@cavium.com> Message-ID: References: <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-5-git-send-email-sjhill@mips.com> <4F9F3387.1050500@cavium.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33174 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 205 Lines: 9 On Mon, 30 Apr 2012, David Daney wrote: > Well I broke the ordering with a bunch of my patches lower down. > > Perhaps we should fix it so it goes back to being ordered. That would be great. Maciej From sjhill@mips.com Mon May 7 15:33:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 May 2012 15:33:26 +0200 (CEST) Received: from dns0.mips.com ([12.201.5.70]:51113 "EHLO dns0.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903630Ab2EGNdR convert rfc822-to-8bit (ORCPT ); Mon, 7 May 2012 15:33:17 +0200 Received: from exchdb01.mips.com (exchdb01.mips.com [192.168.36.67]) by dns0.mips.com (8.13.8/8.13.8) with ESMTP id q47DX8TS005971; Mon, 7 May 2012 06:33:09 -0700 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([fe80::2897:a30d:a923:303%16]) with mapi id 14.01.0270.001; Mon, 7 May 2012 06:33:03 -0700 From: "Hill, Steven" To: "Maciej W. Rozycki" , David Daney CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: RE: [PATCH 04/10] MIPS: Add micro-assembler support for 'ins' and 'ext' instructions. Thread-Topic: [PATCH 04/10] MIPS: Add micro-assembler support for 'ins' and 'ext' instructions. Thread-Index: AQHNJzESflTF6hQ990i+/b3If2b04Ja0kACAgAm4i4CAABTZ7g== Date: Mon, 7 May 2012 13:33:03 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B8011468F70F@exchdb03.mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-5-git-send-email-sjhill@mips.com> <4F9F3387.1050500@cavium.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: +Kodc+nOJ7Yz5hbaJFkjug== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 33176 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 40 Lines: 1 I'll fix the ordering in my patch sets. From bhelgaas@google.com Mon May 7 17:11:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 May 2012 17:11:38 +0200 (CEST) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:49915 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903638Ab2EGPLe convert rfc822-to-8bit (ORCPT ); Mon, 7 May 2012 17:11:34 +0200 Received: by laap9 with SMTP id p9so895411laa.36 for ; Mon, 07 May 2012 08:11:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding:x-system-of-record; bh=6Wl6hVcAD/X4k+4T2wD3D0ZvUgFg32w7GYq3Bs3XCQ0=; b=ZwtSnz47ERv3KknxH4f3NPOoFJkLYW/aK6HPHKOSTmdbSStPAb1P2sOJsy3/2GrFOD d7o1Uq/26d9GefP3AX21Gse1F/zYlL6TnS52HdtC55XsXBjX9GQeHycFuqgMgwHj6bFH 76Y0Fn4lknF1SqlBfAw5L0y/SMaSgscY9h+aoD3J2DSO0+YOQEmsmrj9/qN3AdwgjM4l iocN4uhoMBA90GqT4fRVbkstU6PdAlY8m6No/+AwawMTm+2JPNvEj+ryGStiVKxQJIHf EplcZQMHQn9jJBHOk4xAQ+9jiG1VaABgOAB+A196Zc2H6il4TL5t/5i8HuRWc0E4QRPZ 4Q0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding:x-system-of-record :x-gm-message-state; bh=6Wl6hVcAD/X4k+4T2wD3D0ZvUgFg32w7GYq3Bs3XCQ0=; b=P2mSKIjqKw2JIwMFuB2MLA79sqD8s2j0Co0Du+tFzewi+DGODIIVo3549kzUps5gWH 5Xg0TmUHT5df8fPX5iNAqS56u1hmmAoYArofRYKXm/JdZetSpo4GnzNDM0wVt0emuUDA fBQ3L+wJe8U9GARhhltyVHliD/low3EXH4qCrQp5ONCV0YUrnIuo+YgoMSDohktMFXKl 46uGz05OKLlDlEeYvwHaP+iJUWxDjcRlLQks0cBAuk7z0nIx/nNd1g5bjSrRDwx4mn8/ XAGJBugMvsF14c3S8NJ+FgRB80x+5qf4+EC3zs1KERppCKmZ5bNdQGxZMBB+zsyuGmUJ bToA== Received: by 10.152.147.33 with SMTP id th1mr6673395lab.9.1336403488492; Mon, 07 May 2012 08:11:28 -0700 (PDT) Received: by 10.152.147.33 with SMTP id th1mr6673373lab.9.1336403488356; Mon, 07 May 2012 08:11:28 -0700 (PDT) MIME-Version: 1.0 Received: by 10.112.86.6 with HTTP; Mon, 7 May 2012 08:11:08 -0700 (PDT) In-Reply-To: <4FA3B596.3050106@openwrt.org> References: <1335808019-24502-1-git-send-email-blogic@openwrt.org> <4F9ED1DC.3050007@gmail.com> <4F9FE4F6.5070909@openwrt.org> <4FA32E47.7020406@gmail.com> <4FA3B596.3050106@openwrt.org> From: Bjorn Helgaas Date: Mon, 7 May 2012 08:11:08 -0700 Message-ID: Subject: Re: [PATCH] OF: PCI: const usage needed by MIPS To: John Crispin Cc: David Daney , Ralf Baechle , Grant Likely , linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-System-Of-Record: true X-Gm-Message-State: ALoCoQmXQ3Y+HFD+j/pBkvf4ADihwXGS9mf5phpt9DxcGSnAp5j3uI+k4nvJvk2eL9dmjxJcj0SkcuDIFKbkDyB/ugiCuAT7vGXME/PUoVcEN9SiGNBUiTQA+MqA6h3YIS6j9DEZmNr6Ox9p5KKzHulhV3ob+VO2oA== X-archive-position: 33177 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1099 Lines: 31 On Fri, May 4, 2012 at 3:55 AM, John Crispin wrote: > Hi David, > >> The problem is when you start declaring function pointers in various >> ops vectors. >> >> Consider: >> >> void (*foo)(const struct pci_dev *) >> void (*bar)(struct pci_dev *) >> >> foo and bar are not type compatible, and you will get compiler >> warnings if you use one where the other is expected. Oh, right. I vaguely remember tripping over this a few years ago when I refactored pci_swizzle_interrupt_pin(). Thanks for enhancing my simple understanding. >> So the question is:  Are we ever going to the address of any of the >> functions that are being modified?  If so, we have created a problem. > > i could not find any place in the code where this happens, which does > not mean that there are none. I compiled alpha, ia64, mips, parisc, powerpc, sh, sparc, and x86 and didn't see any issues related to this patch. There might still be something, but I'm willing to help work through them or revert this if it turns out to be a problem. I'm still assuming that Grant will handle this. Bjorn From sjhill@mips.com Mon May 7 21:22:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 May 2012 21:22:18 +0200 (CEST) Received: from dns0.mips.com ([12.201.5.70]:48942 "EHLO dns0.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903679Ab2EGTWL convert rfc822-to-8bit (ORCPT ); Mon, 7 May 2012 21:22:11 +0200 Received: from exchdb01.mips.com (exchdb01.mips.com [192.168.36.67]) by dns0.mips.com (8.13.8/8.13.8) with ESMTP id q47JM3Gf010946; Mon, 7 May 2012 12:22:03 -0700 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([fe80::2897:a30d:a923:303%16]) with mapi id 14.01.0270.001; Mon, 7 May 2012 12:21:58 -0700 From: "Hill, Steven" To: "Yegoshin, Leonid" , Kevin Cernekee CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: RE: [PATCH] Revert "MIPS: cache: Provide cache flush operations for XFS" Thread-Topic: [PATCH] Revert "MIPS: cache: Provide cache flush operations for XFS" Thread-Index: AQHNFmuxxILsfgPzqkG4GyH7KYn4CJaT0BiAgAEA54CAKgc73A== Date: Mon, 7 May 2012 19:21:57 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B80114692038@exchdb03.mips.com> References: <1333987989-1178-1-git-send-email-sjhill@mips.com> ,<4F8475F7.9060809@mips.com> In-Reply-To: <4F8475F7.9060809@mips.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: doPoeJGahz66P+8OflIw7Q== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 33178 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 67 Lines: 5 Leonid, I am dropping this patch for the 3.5 release too. -Steve From yegoshin@mips.com Mon May 7 21:28:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 May 2012 21:28:52 +0200 (CEST) Received: from dns0.mips.com ([12.201.5.70]:43765 "EHLO dns0.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903679Ab2EGT2q (ORCPT ); Mon, 7 May 2012 21:28:46 +0200 Received: from exchdb01.mips.com (exchhub01.mips.com [192.168.36.84]) by dns0.mips.com (8.13.8/8.13.8) with ESMTP id q47JSX5O011050; Mon, 7 May 2012 12:28:35 -0700 Received: from [192.168.65.146] (192.168.65.146) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Mon, 7 May 2012 12:28:32 -0700 Message-ID: <4FA8225F.1030401@mips.com> Date: Mon, 7 May 2012 12:28:31 -0700 From: Leonid Yegoshin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.18) Gecko/20110617 Thunderbird/3.1.11 MIME-Version: 1.0 To: "Hill, Steven" CC: Kevin Cernekee , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: Re: [PATCH] Revert "MIPS: cache: Provide cache flush operations for XFS" References: <1333987989-1178-1-git-send-email-sjhill@mips.com> ,<4F8475F7.9060809@mips.com> <31E06A9FC96CEC488B43B19E2957C1B80114692038@exchdb03.mips.com> In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B80114692038@exchdb03.mips.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: QelUtygNq6LlvReQY+eWww== X-archive-position: 33179 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yegoshin@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 442 Lines: 20 Steven, On 05/07/2012 12:21 PM, Hill, Steven wrote: > Leonid, > > I am dropping this patch for the 3.5 release too. > > -Steve I don't care - we still have it in internal repo, right? Sometime this/next month I will create a second patch for L1 only flushing optimization in this case and we can repeat it in future release. Unfortunately, right these weeks I have no time for that optimization, sorry for that. Thank you, - Leonid. From sjhill@mips.com Mon May 7 22:16:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 May 2012 22:16:48 +0200 (CEST) Received: from dns0.mips.com ([12.201.5.70]:53270 "EHLO dns0.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903682Ab2EGUQo convert rfc822-to-8bit (ORCPT ); Mon, 7 May 2012 22:16:44 +0200 Received: from exchdb01.mips.com (exchdb01.mips.com [192.168.36.67]) by dns0.mips.com (8.13.8/8.13.8) with ESMTP id q47KGaaL011761; Mon, 7 May 2012 13:16:36 -0700 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([fe80::2897:a30d:a923:303%16]) with mapi id 14.01.0270.001; Mon, 7 May 2012 13:16:31 -0700 From: "Hill, Steven" To: Shinya Kuribayashi CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "Leung, Douglas" , "Dearman, Chris" Subject: RE: [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform. Thread-Topic: [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform. Thread-Index: AQHNFN5TXaIyKURn50SCHT0BxYKwcJaTtvkAgCs4fmA= Date: Mon, 7 May 2012 20:16:31 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B8011469208F@exchdb03.mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-2-git-send-email-sjhill@mips.com>,<4F8386C8.9020401@renesas.com> In-Reply-To: <4F8386C8.9020401@renesas.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: N72dU3eGhiU9Dlrmtg/aPA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 33180 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 543 Lines: 5 Kuribayashi-san, I will certainly remove CONFIG_CPU_HAS_LLSC, thank you. I attempted to enable 'cpu_has_clo_clz' for SEAD-3, but it breaks my microMIPS-only kernel builds. Specifically, since microMIPS LL/SC instructions do not have 16-bit address offsets, in the '__cmpxchg_asm' macro function I get constraint errors because then the assembler has to use the %LO register in order to calculate the offset address. I am going to hold off on enabling the option until after the 3.5 release and then revisit for a solution. Thank you. -Steve From davem@davemloft.net Tue May 8 04:58:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 04:59:00 +0200 (CEST) Received: from shards.monkeyblade.net ([198.137.202.13]:38123 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901161Ab2EHC6x (ORCPT ); Tue, 8 May 2012 04:58:53 +0200 Received: from localhost (cpe-66-108-118-54.nyc.res.rr.com [66.108.118.54]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id q482wgTk009749 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NO); Mon, 7 May 2012 19:58:43 -0700 Date: Mon, 07 May 2012 22:58:42 -0400 (EDT) Message-Id: <20120507.225842.692131427998127266.davem@davemloft.net> To: ddaney.cavm@gmail.com Cc: ralf@linux-mips.org, grant.likely@secretlab.ca, rob.herring@calxeda.com, devicetree-discuss@lists.ozlabs.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, afleming@gmail.com, galak@kernel.crashing.org, david.daney@cavium.com Subject: Re: [PATCH v6 1/3] netdev/of/phy: New function: of_mdio_find_bus(). From: David Miller In-Reply-To: <1336007799-31016-2-git-send-email-ddaney.cavm@gmail.com> References: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> <1336007799-31016-2-git-send-email-ddaney.cavm@gmail.com> X-Mailer: Mew version 6.5 on Emacs 24.0.95 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (shards.monkeyblade.net [198.137.202.13]); Mon, 07 May 2012 19:58:45 -0700 (PDT) X-archive-position: 33181 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 764 Lines: 22 From: David Daney Date: Wed, 2 May 2012 18:16:37 -0700 > From: David Daney > > Add of_mdio_find_bus() which allows an mii_bus to be located given its > associated the device tree node. > > This is needed by the follow-on patch to add a driver for MDIO bus > multiplexers. > > The of_mdiobus_register() function is modified so that the device tree > node is recorded in the mii_bus. Then we can find it again by > iterating over all mdio_bus_class devices. > > Because the OF device tree has now become an integral part of the > kernel, this can live in mdio_bus.c (which contains the needed > mdio_bus_class structure) instead of of_mdio.c. > > Signed-off-by: David Daney Applied. From davem@davemloft.net Tue May 8 04:59:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 04:59:32 +0200 (CEST) Received: from shards.monkeyblade.net ([198.137.202.13]:38138 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903617Ab2EHC7B (ORCPT ); Tue, 8 May 2012 04:59:01 +0200 Received: from localhost (cpe-66-108-118-54.nyc.res.rr.com [66.108.118.54]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id q482wrAZ009757 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NO); Mon, 7 May 2012 19:58:54 -0700 Date: Mon, 07 May 2012 22:58:53 -0400 (EDT) Message-Id: <20120507.225853.1863347275703801019.davem@davemloft.net> To: ddaney.cavm@gmail.com Cc: ralf@linux-mips.org, grant.likely@secretlab.ca, rob.herring@calxeda.com, devicetree-discuss@lists.ozlabs.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, afleming@gmail.com, galak@kernel.crashing.org, david.daney@cavium.com Subject: Re: [PATCH v6 2/3] netdev/of/phy: Add MDIO bus multiplexer support. From: David Miller In-Reply-To: <1336007799-31016-3-git-send-email-ddaney.cavm@gmail.com> References: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> <1336007799-31016-3-git-send-email-ddaney.cavm@gmail.com> X-Mailer: Mew version 6.5 on Emacs 24.0.95 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (shards.monkeyblade.net [198.137.202.13]); Mon, 07 May 2012 19:58:55 -0700 (PDT) X-archive-position: 33182 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 808 Lines: 24 From: David Daney Date: Wed, 2 May 2012 18:16:38 -0700 > From: David Daney > > This patch adds a somewhat generic framework for MDIO bus > multiplexers. It is modeled on the I2C multiplexer. > > The multiplexer is needed if there are multiple PHYs with the same > address connected to the same MDIO bus adepter, or if there is > insufficient electrical drive capability for all the connected PHY > devices. > > Conceptually it could look something like this: ... > This framework configures the bus topology from device tree data. The > mechanics of switching the multiplexer is left to device specific > drivers. > > The follow-on patch contains a multiplexer driven by GPIO lines. > > Signed-off-by: David Daney Applied. From davem@davemloft.net Tue May 8 04:59:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 04:59:56 +0200 (CEST) Received: from shards.monkeyblade.net ([198.137.202.13]:38146 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903621Ab2EHC7H (ORCPT ); Tue, 8 May 2012 04:59:07 +0200 Received: from localhost (cpe-66-108-118-54.nyc.res.rr.com [66.108.118.54]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id q482x06M009764 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NO); Mon, 7 May 2012 19:59:01 -0700 Date: Mon, 07 May 2012 22:59:00 -0400 (EDT) Message-Id: <20120507.225900.1607360124849584710.davem@davemloft.net> To: ddaney.cavm@gmail.com Cc: ralf@linux-mips.org, grant.likely@secretlab.ca, rob.herring@calxeda.com, devicetree-discuss@lists.ozlabs.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, afleming@gmail.com, galak@kernel.crashing.org, david.daney@cavium.com Subject: Re: [PATCH v6 3/3] netdev/of/phy: Add MDIO bus multiplexer driven by GPIO lines. From: David Miller In-Reply-To: <1336007799-31016-4-git-send-email-ddaney.cavm@gmail.com> References: <1336007799-31016-1-git-send-email-ddaney.cavm@gmail.com> <1336007799-31016-4-git-send-email-ddaney.cavm@gmail.com> X-Mailer: Mew version 6.5 on Emacs 24.0.95 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (shards.monkeyblade.net [198.137.202.13]); Mon, 07 May 2012 19:59:02 -0700 (PDT) X-archive-position: 33183 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 346 Lines: 13 From: David Daney Date: Wed, 2 May 2012 18:16:39 -0700 > From: David Daney > > The GPIO pins select which sub bus is connected to the master. > > Initially tested with an sn74cbtlv3253 switch device wired into the > MDIO bus. > > Signed-off-by: David Daney Applied. From shinya.kuribayashi.px@renesas.com Tue May 8 06:01:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 06:01:28 +0200 (CEST) Received: from relmlor2.renesas.com ([210.160.252.172]:37448 "EHLO relmlor2.renesas.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903617Ab2EHEBK (ORCPT ); Tue, 8 May 2012 06:01:10 +0200 Received: from relmlir1.idc.renesas.com ([10.200.68.151]) by relmlor2.idc.renesas.com ( SJSMS) with ESMTP id <0M3O0019MR5T5MA0@relmlor2.idc.renesas.com>; Tue, 08 May 2012 13:01:05 +0900 (JST) Received: from relmlac1.idc.renesas.com ([10.200.69.21]) by relmlir1.idc.renesas.com (SJSMS) with ESMTP id <0M3O00KM7R5TOW60@relmlir1.idc.renesas.com>; Tue, 08 May 2012 13:01:05 +0900 (JST) Received: by relmlac1.idc.renesas.com (Postfix, from userid 0) id 7FDD78015D; Tue, 08 May 2012 13:01:05 +0900 (JST) Received: from relmlac1.idc.renesas.com (localhost [127.0.0.1]) by relmlac1.idc.renesas.com (Postfix) with ESMTP id 4408680193; Tue, 08 May 2012 13:01:05 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac1.idc.renesas.com with ESMTP id PAB29899; Tue, 08 May 2012 13:01:05 +0900 X-IronPort-AV: E=Sophos;i="4.75,547,1330873200"; d="scan'208";a="80159051" Received: from unknown (HELO [10.161.69.127]) ([10.161.69.127]) by relmlii2.idc.renesas.com with ESMTP; Tue, 08 May 2012 13:01:05 +0900 Message-id: <4FA89A80.6060407@renesas.com> Date: Tue, 08 May 2012 13:01:04 +0900 From: Shinya Kuribayashi User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-version: 1.0 To: sjhill@mips.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, douglas@mips.com, chris@mips.com Subject: Re: [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform. References: <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-2-git-send-email-sjhill@mips.com> <4F8386C8.9020401@renesas.com> <31E06A9FC96CEC488B43B19E2957C1B8011469208F@exchdb03.mips.com> In-reply-to: <31E06A9FC96CEC488B43B19E2957C1B8011469208F@exchdb03.mips.com> Content-type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: 7bit X-archive-position: 33184 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shinya.kuribayashi.px@renesas.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 760 Lines: 17 Hi Steven-san, On 5/8/2012 5:16 AM, Hill, Steven wrote: > I will certainly remove CONFIG_CPU_HAS_LLSC, thank you. I attempted to > enable 'cpu_has_clo_clz' for SEAD-3, but it breaks my microMIPS-only > kernel builds. Specifically, since microMIPS LL/SC instructions do > not have 16-bit address offsets, in the '__cmpxchg_asm' macro function > I get constraint errors because then the assembler has to use the %LO > register in order to calculate the offset address. I am going to hold > off on enabling the option until after the 3.5 release and then > revisit for a solution. Thank you. Got it, find no problems with your plan. It seems there must be other issues with optimization on microMIPS-only kernels :-) -- Shinya Kuribayashi Renesas Electronics From dedekind1@gmail.com Tue May 8 12:18:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 12:18:28 +0200 (CEST) Received: from mga03.intel.com ([143.182.124.21]:57600 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903626Ab2EHKSR (ORCPT ); Tue, 8 May 2012 12:18:17 +0200 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 08 May 2012 03:18:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="140264858" Received: from blue.fi.intel.com ([10.237.72.50]) by azsmga001.ch.intel.com with ESMTP; 08 May 2012 03:18:08 -0700 From: Artem Bityutskiy To: Ralf Baechle , MIPS Mailing List Cc: Linux Kernel Maling List Subject: [PATCH] mips: bcm63xx: fix compilation problems Date: Tue, 8 May 2012 13:19:07 +0300 Message-Id: <1336472347-25822-1-git-send-email-dedekind1@gmail.com> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33185 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2007 Lines: 40 From: Artem Bityutskiy I get the following build error when I am compiling the MTD gpio-nand driver for bcm63xx: In file included from arch/mips/include/asm/mach-bcm63xx/gpio.h:4:0, from arch/mips/include/asm/gpio.h:4, from include/linux/gpio.h:36, from drivers/mtd/maps/gpio-addr-flash.c:16: arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h: In function 'bcm63xx_gpio_count': arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:10:2: error: implicit declaration of function 'bcm63xx_get_cpu_id' [-Werror=implicit-function-declaration] arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: error: 'BCM6358_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: note: each undeclared identifier is reported only once for each function it appears in arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:13:7: error: 'BCM6338_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:15:7: error: 'BCM6345_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:17:7: error: 'BCM6368_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:19:7: error: 'BCM6348_CPU_ID' undeclared (first use in this function) This patch sloves the problem. Signed-off-by: Artem Bityutskiy --- arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 3d5de96..b4b9103 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -1,6 +1,7 @@ #ifndef BCM63XX_GPIO_H #define BCM63XX_GPIO_H +#include "bcm63xx_cpu.h" #include int __init bcm63xx_gpio_init(void); -- 1.7.9.1 From blogic@openwrt.org Tue May 8 12:37:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 12:37:19 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:42690 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903627Ab2EHKhM (ORCPT ); Tue, 8 May 2012 12:37:12 +0200 Message-ID: <4FA8F6F9.10703@openwrt.org> Date: Tue, 08 May 2012 12:35:37 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: Bjorn Helgaas CC: David Daney , Ralf Baechle , Grant Likely , linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org Subject: Re: [PATCH] OF: PCI: const usage needed by MIPS References: <1335808019-24502-1-git-send-email-blogic@openwrt.org> <4F9ED1DC.3050007@gmail.com> <4F9FE4F6.5070909@openwrt.org> <4FA32E47.7020406@gmail.com> <4FA3B596.3050106@openwrt.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33186 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 345 Lines: 11 Hi Bjorn, > I compiled alpha, ia64, mips, parisc, powerpc, sh, sparc, and x86 and > didn't see any issues related to this patch. There might still be > something, but I'm willing to help work through them or revert this > if it turns out to be a problem. I'm still assuming that Grant will > handle this. > > Bjorn Thanks for the help, John From dedekind1@gmail.com Tue May 8 12:53:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 12:53:11 +0200 (CEST) Received: from mga02.intel.com ([134.134.136.20]:57273 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903627Ab2EHKxG (ORCPT ); Tue, 8 May 2012 12:53:06 +0200 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 08 May 2012 03:52:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.67,352,1309762800"; d="scan'208";a="138150219" Received: from blue.fi.intel.com ([10.237.72.50]) by orsmga001.jf.intel.com with ESMTP; 08 May 2012 03:52:57 -0700 From: Artem Bityutskiy To: John Crispin Cc: MTD Maling List , MIPS Mailing List Subject: [PATCH] mtd: xway_nand: add OF dependency Date: Tue, 8 May 2012 13:53:56 +0300 Message-Id: <1336474436-9755-1-git-send-email-dedekind1@gmail.com> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33187 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 756 Lines: 25 From: Artem Bityutskiy xway_nand.c requires OF support - add dependency in Kconfig. Signed-off-by: Artem Bityutskiy --- drivers/mtd/nand/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index fd4d064..eacf379 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -569,7 +569,7 @@ config MTD_NAND_FSMC config MTD_NAND_XWAY tristate "Support for NAND on Lantiq XWAY SoC" - depends on LANTIQ && SOC_TYPE_XWAY + depends on LANTIQ && SOC_TYPE_XWAY && OF select MTD_NAND_PLATFORM help Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached -- 1.7.9.1 From blogic@openwrt.org Tue May 8 12:57:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 12:57:04 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:34527 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903632Ab2EHK5A (ORCPT ); Tue, 8 May 2012 12:57:00 +0200 Message-ID: <4FA8FBA3.1090803@openwrt.org> Date: Tue, 08 May 2012 12:55:31 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: Artem Bityutskiy CC: MTD Maling List , MIPS Mailing List Subject: Re: [PATCH] mtd: xway_nand: add OF dependency References: <1336474436-9755-1-git-send-email-dedekind1@gmail.com> In-Reply-To: <1336474436-9755-1-git-send-email-dedekind1@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33188 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 295 Lines: 13 On 08/05/12 12:53, Artem Bityutskiy wrote: > From: Artem Bityutskiy > > xway_nand.c requires OF support - add dependency in Kconfig. > > Signed-off-by: Artem Bityutskiy Thanks Acked-by: John Crispin From dedekind1@gmail.com Tue May 8 12:57:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 12:57:32 +0200 (CEST) Received: from mga02.intel.com ([134.134.136.20]:41856 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903627Ab2EHK5X (ORCPT ); Tue, 8 May 2012 12:57:23 +0200 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 08 May 2012 03:57:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.67,352,1309762800"; d="asc'?scan'208";a="138150900" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by orsmga001.jf.intel.com with ESMTP; 08 May 2012 03:57:15 -0700 Received: from [10.237.72.159] (sauron.fi.intel.com [10.237.72.159]) by linux.intel.com (Postfix) with ESMTP id 221ED6A4001; Tue, 8 May 2012 03:57:13 -0700 (PDT) Message-ID: <1336474838.23308.28.camel@sauron.fi.intel.com> Subject: xway_nand does not build From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: MIPS Mailing List , MTD Maling List Date: Tue, 08 May 2012 14:00:38 +0300 Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-OT8eGRILOihL4wV9qs9O" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Mime-Version: 1.0 X-archive-position: 33189 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 51732 Lines: 717 --=-OT8eGRILOihL4wV9qs9O Content-Type: multipart/mixed; boundary="=-JnOGUmRcAlpQiZcFqqLb" --=-JnOGUmRcAlpQiZcFqqLb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi John, I get the following build error when building xway_nand.c: dedekind@blue:~/git/l2-mtd$ make ARCH=3Dmips CROSS_COMPILE=3Dmips-linux- CHK include/linux/version.h CHK include/generated/utsrelease.h UPD include/generated/utsrelease.h CALL scripts/checksyscalls.sh CHK include/generated/compile.h CC init/version.o LD init/built-in.o CC kernel/sys.o LD kernel/built-in.o LD drivers/mtd/nand/nand.o CC drivers/mtd/nand/xway_nand.o drivers/mtd/nand/xway_nand.c: In function 'xway_select_chip': drivers/mtd/nand/xway_nand.c:78:3: error: implicit declaration of function = 'ltq_ebu_w32_mask' [-Werror=3Dimplicit-function-declaration] cc1: some warnings being treated as errors make[3]: *** [drivers/mtd/nand/xway_nand.o] Error 1 make[2]: *** [drivers/mtd/nand] Error 2 make[1]: *** [drivers/mtd] Error 2 make: *** [drivers] Error 2 and I cannot figure out how to fix this. This build failure makes me really unhappy and shame on me I did not notice it before, of course. Would you have a fix? I am attaching the defconfig which I used. --=20 Best Regards, Artem Bityutskiy --=-JnOGUmRcAlpQiZcFqqLb Content-Disposition: attachment; filename=".config" Content-Transfer-Encoding: base64 Content-Type: text/plain; name=".config"; charset="UTF-8" Iw0KIyBBdXRvbWF0aWNhbGx5IGdlbmVyYXRlZCBmaWxlOyBETyBOT1QgRURJVC4NCiMgTGludXgv bWlwcyAzLjQuMC1yYzQgS2VybmVsIENvbmZpZ3VyYXRpb24NCiMNCkNPTkZJR19NSVBTPXkNCg0K Iw0KIyBNYWNoaW5lIHNlbGVjdGlvbg0KIw0KIyBDT05GSUdfTUlQU19BTENIRU1ZIGlzIG5vdCBz ZXQNCiMgQ09ORklHX0FSNyBpcyBub3Qgc2V0DQojIENPTkZJR19BVEg3OSBpcyBub3Qgc2V0DQoj IENPTkZJR19CQ000N1hYIGlzIG5vdCBzZXQNCiMgQ09ORklHX0JDTTYzWFggaXMgbm90IHNldA0K IyBDT05GSUdfTUlQU19DT0JBTFQgaXMgbm90IHNldA0KIyBDT05GSUdfTUFDSF9ERUNTVEFUSU9O IGlzIG5vdCBzZXQNCiMgQ09ORklHX01BQ0hfSkFaWiBpcyBub3Qgc2V0DQojIENPTkZJR19NQUNI X0paNDc0MCBpcyBub3Qgc2V0DQpDT05GSUdfTEFOVElRPXkNCiMgQ09ORklHX0xBU0FUIGlzIG5v dCBzZXQNCiMgQ09ORklHX01BQ0hfTE9PTkdTT04gaXMgbm90IHNldA0KIyBDT05GSUdfTUlQU19N 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1.0 To: dedekind1@gmail.com CC: MIPS Mailing List , MTD Maling List Subject: Re: xway_nand does not build References: <1336474838.23308.28.camel@sauron.fi.intel.com> In-Reply-To: <1336474838.23308.28.camel@sauron.fi.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-archive-position: 33190 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1584 Lines: 45 On 08/05/12 13:00, Artem Bityutskiy wrote: > Hi John, > > I get the following build error when building xway_nand.c: > > dedekind@blue:~/git/l2-mtd$ make ARCH=mips CROSS_COMPILE=mips-linux- > CHK include/linux/version.h > CHK include/generated/utsrelease.h > UPD include/generated/utsrelease.h > CALL scripts/checksyscalls.sh > CHK include/generated/compile.h > CC init/version.o > LD init/built-in.o > CC kernel/sys.o > LD kernel/built-in.o > LD drivers/mtd/nand/nand.o > CC drivers/mtd/nand/xway_nand.o > drivers/mtd/nand/xway_nand.c: In function 'xway_select_chip': > drivers/mtd/nand/xway_nand.c:78:3: error: implicit declaration of function 'ltq_ebu_w32_mask' [-Werror=implicit-function-declaration] > cc1: some warnings being treated as errors > make[3]: *** [drivers/mtd/nand/xway_nand.o] Error 1 > make[2]: *** [drivers/mtd/nand] Error 2 > make[1]: *** [drivers/mtd] Error 2 > make: *** [drivers] Error 2 > > and I cannot figure out how to fix this. This build failure makes > me really unhappy and shame on me I did not notice it before, of > course. Would you have a fix? Hi, I should have spotted this myself infact. I split these patches out of a huge series and did infact check that it builds outside the series. looks like i missed a define. Would it be possible, that patch 4 of my series flows via Ralfs MIPS tree ? That way we dont need to split out a single "#define ltq_ebu_w32_mask" out of the bigger MIPS series ? Sorry about this, John > I am attaching the defconfig which I used. > From dedekind1@gmail.com Tue May 8 13:10:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 13:10:37 +0200 (CEST) Received: from mga03.intel.com ([143.182.124.21]:36418 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903640Ab2EHLKd (ORCPT ); Tue, 8 May 2012 13:10:33 +0200 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 08 May 2012 04:10:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="asc'?scan'208";a="140282044" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by azsmga001.ch.intel.com with ESMTP; 08 May 2012 04:10:16 -0700 Received: from [10.237.72.159] (sauron.fi.intel.com [10.237.72.159]) by linux.intel.com (Postfix) with ESMTP id BE3466A4008; Tue, 8 May 2012 04:10:14 -0700 (PDT) Message-ID: <1336475618.23308.30.camel@sauron.fi.intel.com> Subject: Re: xway_nand does not build From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: MIPS Mailing List , MTD Maling List Date: Tue, 08 May 2012 14:13:38 +0300 In-Reply-To: <4FA8FD24.6060908@openwrt.org> References: <1336474838.23308.28.camel@sauron.fi.intel.com> <4FA8FD24.6060908@openwrt.org> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-6fKC/UqtgesG1WK+A/6B" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Mime-Version: 1.0 X-archive-position: 33191 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3444 Lines: 95 --=-6fKC/UqtgesG1WK+A/6B Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2012-05-08 at 13:01 +0200, John Crispin wrote: > On 08/05/12 13:00, Artem Bityutskiy wrote: > > Hi John, > > > > I get the following build error when building xway_nand.c: > > > > dedekind@blue:~/git/l2-mtd$ make ARCH=3Dmips CROSS_COMPILE=3Dmips-linux= - > > CHK include/linux/version.h > > CHK include/generated/utsrelease.h > > UPD include/generated/utsrelease.h > > CALL scripts/checksyscalls.sh > > CHK include/generated/compile.h > > CC init/version.o > > LD init/built-in.o > > CC kernel/sys.o > > LD kernel/built-in.o > > LD drivers/mtd/nand/nand.o > > CC drivers/mtd/nand/xway_nand.o > > drivers/mtd/nand/xway_nand.c: In function 'xway_select_chip': > > drivers/mtd/nand/xway_nand.c:78:3: error: implicit declaration of funct= ion 'ltq_ebu_w32_mask' [-Werror=3Dimplicit-function-declaration] > > cc1: some warnings being treated as errors > > make[3]: *** [drivers/mtd/nand/xway_nand.o] Error 1 > > make[2]: *** [drivers/mtd/nand] Error 2 > > make[1]: *** [drivers/mtd] Error 2 > > make: *** [drivers] Error 2 > > > > and I cannot figure out how to fix this. This build failure makes > > me really unhappy and shame on me I did not notice it before, of > > course. Would you have a fix? >=20 > Hi, >=20 > I should have spotted this myself infact. I split these patches out of a > huge series and did infact check that it builds outside the series. > looks like i missed a define. Would it be possible, that patch 4 of my > series flows via Ralfs MIPS tree ? That way we dont need to split out a > single "#define ltq_ebu_w32_mask" out of the bigger MIPS series ? OK, so I should drop this patch from l2-mtd.git: commit e4445062be41c27b2a0b4f2e1e770d24b68686f4 Author: John Crispin Date: Mon Apr 30 19:30:48 2012 +0200 mtd: mips: lantiq: add xway nand support =20 Add NAND support on Lantiq XWAY SoC. =20 The driver uses plat_nand. As the platform_device is loaded from DT, we= need to lookup the node and attach our xway specific "struct platform_nand_d= ata" to it. =20 Signed-off-by: John Crispin Signed-off-by: Artem Bityutskiy Right? --=20 Best Regards, Artem Bityutskiy --=-6fKC/UqtgesG1WK+A/6B Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPqP/iAAoJECmIfjd9wqK002oQAK/GwXGDVkk1iJ8N+z7UiIaB 9akTZzB5KUOdXPU2XjN+hAtqn1pXDU1D3vcUZ5nR/epVb/YmC/drpHS0arFb/xyV b4cUG6Z2Yw3e9zM70TKAAbDrnmZP0YERKsjv3kYTJk/z2iT0W62laLZetUqnQfdJ W8maauUrL86iWcKpDbxBmBA4Hdhj3UGMqJHiEZaQcwWLfSPU03b7Q+VO93lQG3wK JsXApjZQj7L+YcNIs39jsnRXT5mrZghwm3rwv2hnIYIK7fQpXlhV0N5wcOgi7qxR qoCj9mg6WxFemtemqQN4PaQ7z6Atibg0o10AHQ3irCjabMw+klV1b6tA2Lf3Wqbv dXL86iy5DEQCCJcxKGl2XUFtexVmKqw5E65ZR6GS7tDQCtpBUBuhLQH0rWOvFk3q 4DsRTQrtRatLsjh3z3+xgfHH66RF5VpFjfR+02hstPQU3Vy3xO+FslDlsqZSQmot 7Fp10IDajDQ31E9GNt/5OJKM/M6Achq3ldQdDDXd2RH9xVfPxMT3//Z07FIa4MSY qrzQPVa86DANuBqwp2n6gowZyK/F3/dkiochTgoOwjMDlQcHpK5B2ZKXsjfoWPUz +QCvUgT6808aS8picjWq9QvBpNAFwRUtIoxlHxHLdRxqUKo0AtufwgvTv5mCLCdt oAHtfGmXdzQN8xhxi1iX =clWZ -----END PGP SIGNATURE----- --=-6fKC/UqtgesG1WK+A/6B-- From blogic@openwrt.org Tue May 8 13:12:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 13:12:40 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:42798 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903640Ab2EHLMg (ORCPT ); Tue, 8 May 2012 13:12:36 +0200 Message-ID: <4FA8FF4C.5050400@openwrt.org> Date: Tue, 08 May 2012 13:11:08 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: dedekind1@gmail.com CC: MIPS Mailing List , MTD Maling List Subject: Re: xway_nand does not build References: <1336474838.23308.28.camel@sauron.fi.intel.com> <4FA8FD24.6060908@openwrt.org> <1336475618.23308.30.camel@sauron.fi.intel.com> In-Reply-To: <1336475618.23308.30.camel@sauron.fi.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-archive-position: 33192 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 736 Lines: 26 > OK, so I should drop this patch from l2-mtd.git: > > commit e4445062be41c27b2a0b4f2e1e770d24b68686f4 > Author: John Crispin > Date: Mon Apr 30 19:30:48 2012 +0200 > > mtd: mips: lantiq: add xway nand support > > Add NAND support on Lantiq XWAY SoC. > > The driver uses plat_nand. As the platform_device is loaded from DT, we need > to lookup the node and attach our xway specific "struct platform_nand_data" > to it. > > Signed-off-by: John Crispin > Signed-off-by: Artem Bityutskiy > > Right? Hi, That would be appreciated. i will get aligned with Ralf to make sure this patch flow via his tree Thanks, John From macro@linux-mips.org Tue May 8 13:16:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 13:17:05 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:36798 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903640Ab2EHLQ6 (ORCPT ); Tue, 8 May 2012 13:16:58 +0200 Date: Tue, 8 May 2012 12:16:58 +0100 (BST) From: "Maciej W. Rozycki" To: "Hill, Steven" cc: Shinya Kuribayashi , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "Leung, Douglas" , "Dearman, Chris" Subject: RE: [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform. In-Reply-To: <31E06A9FC96CEC488B43B19E2957C1B8011469208F@exchdb03.mips.com> Message-ID: References: <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-2-git-send-email-sjhill@mips.com>,<4F8386C8.9020401@renesas.com> <31E06A9FC96CEC488B43B19E2957C1B8011469208F@exchdb03.mips.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33193 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1275 Lines: 38 On Mon, 7 May 2012, Hill, Steven wrote: > I will certainly remove CONFIG_CPU_HAS_LLSC, thank you. I attempted to > enable 'cpu_has_clo_clz' for SEAD-3, but it breaks my microMIPS-only > kernel builds. Specifically, since microMIPS LL/SC instructions do not > have 16-bit address offsets, in the '__cmpxchg_asm' macro function I get > constraint errors because then the assembler has to use the %LO register > in order to calculate the offset address. I am going to hold off on > enabling the option until after the 3.5 release and then revisit for a > solution. Thank you. It's OK to ask. :) Try using the "YC" constraint, this piece: int test(void *p) { int i; __asm__ __volatile__("ll\t%0,%1" : "=r" (i) : "YC" (*p)); return i; } assembles to: ll $2,0($4) jrc $31 for me (with "-O2 -mmicromips"). You may have to factor in backwards compatibility -- while "YC" is supported both in the microMIPS and the standard MIPS mode, switching the width of the immediate offset between 12 and 16 bits as appropriate, it's certainly a new constraint older compilers did not support. I suggest using a macro, as usually, you can use some existing examples as a reference, e.g. (you know where to place this stuff now too :) ). Maciej From dedekind1@gmail.com Tue May 8 13:18:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 13:18:36 +0200 (CEST) Received: from mga11.intel.com ([192.55.52.93]:28764 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903640Ab2EHLSb (ORCPT ); Tue, 8 May 2012 13:18:31 +0200 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 08 May 2012 04:18:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="asc'?scan'208";a="163362518" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by fmsmga002.fm.intel.com with ESMTP; 08 May 2012 04:18:24 -0700 Received: from [10.237.72.159] (sauron.fi.intel.com [10.237.72.159]) by linux.intel.com (Postfix) with ESMTP id 7CBD96A4008; Tue, 8 May 2012 04:18:23 -0700 (PDT) Message-ID: <1336476107.23308.31.camel@sauron.fi.intel.com> Subject: Re: xway_nand does not build From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: MIPS Mailing List , MTD Maling List Date: Tue, 08 May 2012 14:21:47 +0300 In-Reply-To: <4FA8FF4C.5050400@openwrt.org> References: <1336474838.23308.28.camel@sauron.fi.intel.com> <4FA8FD24.6060908@openwrt.org> <1336475618.23308.30.camel@sauron.fi.intel.com> <4FA8FF4C.5050400@openwrt.org> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-cQdinkxw5GsU3SC3EaA6" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Mime-Version: 1.0 X-archive-position: 33194 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2166 Lines: 65 --=-cQdinkxw5GsU3SC3EaA6 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2012-05-08 at 13:11 +0200, John Crispin wrote: > > OK, so I should drop this patch from l2-mtd.git: > > > > commit e4445062be41c27b2a0b4f2e1e770d24b68686f4 > > Author: John Crispin > > Date: Mon Apr 30 19:30:48 2012 +0200 > > > > mtd: mips: lantiq: add xway nand support > > =20 > > Add NAND support on Lantiq XWAY SoC. > > =20 > > The driver uses plat_nand. As the platform_device is loaded from DT= , we need > > to lookup the node and attach our xway specific "struct platform_na= nd_data" > > to it. > > =20 > > Signed-off-by: John Crispin > > Signed-off-by: Artem Bityutskiy > > > > Right? > Hi, >=20 > That would be appreciated. i will get aligned with Ralf to make sure > this patch flow via his tree OK, dropped. Please, add the OF dependency to the Kconfig yourself then because I do not have this driver in my tree anymore. Thanks! --=20 Best Regards, Artem Bityutskiy --=-cQdinkxw5GsU3SC3EaA6 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPqQHLAAoJECmIfjd9wqK0PbsP/3jEzYQ3cRR6o81IufDJ8qfe rV57e0kUp1/peaNg+njd7Yx9CYl/aac/BLszTAAebDG95kgwDePebmHfW1pOyYjs D4DMu+E3+Sr6AszY/k45yF4eR3aGkgetj5KdaR4KTVXjf5g/nxh0l7aUg6qcrSG+ A5HDyZP98p2vtELN+FV7giEA6jsmrMnt8RYVsqpel3upg9cJQc1r13tgQ2sPYn6V KLZUr/q4UBF4SPGRflfDyqKiQeyzALymlwgZeDGrmc4oiB8LWg4kwU2o9BWipATW MU3eCFoi/X+sXzI88UpviFUgu1FSDvkNghbIeZpIcmYeJEu0+MqzfujR/stIK8z7 bEI+/tL5Us4qKGt8aVKgsCV2vXVfWdmMqj0UQKbYAlotXLrfBwdmWevJXt3P6jXk W75SCZToIFAOKXGoSRjElIbwLjQzbQialAzr7X+OpGrZMUU7EAea2cRXX/FYU7GC RpgElbFSpGxxEm/HJUJaNYdtuhskDM8fYGfsbqpVEZTwV5yWTDCcc/ndgVsALqb/ T+3+dxoQldPxFfdmOa1Sgd5eIaee3pVQhn7DkJqbqU/fLSsnanqh0B859tIvWr+m m6XjF1CqdqBGww3iXXMiv2t20qh7xldWeoyhVsLYkqxysHCvNWK7/4BwJwm6V5r4 Csj7OAEW+lCJebnSehRW =ONlD -----END PGP SIGNATURE----- --=-cQdinkxw5GsU3SC3EaA6-- From dedekind1@gmail.com Tue May 8 13:19:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 13:19:42 +0200 (CEST) Received: from mga09.intel.com ([134.134.136.24]:33841 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903640Ab2EHLTh (ORCPT ); Tue, 8 May 2012 13:19:37 +0200 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 08 May 2012 04:19:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.67,352,1309762800"; d="asc'?scan'208";a="138156086" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by orsmga001.jf.intel.com with ESMTP; 08 May 2012 04:19:30 -0700 Received: from [10.237.72.159] (sauron.fi.intel.com [10.237.72.159]) by linux.intel.com (Postfix) with ESMTP id 119136A4008; Tue, 8 May 2012 04:19:29 -0700 (PDT) Message-ID: <1336476174.23308.32.camel@sauron.fi.intel.com> Subject: Re: xway_nand does not build From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: MIPS Mailing List , MTD Maling List Date: Tue, 08 May 2012 14:22:54 +0300 In-Reply-To: <4FA8FF4C.5050400@openwrt.org> References: <1336474838.23308.28.camel@sauron.fi.intel.com> <4FA8FD24.6060908@openwrt.org> <1336475618.23308.30.camel@sauron.fi.intel.com> <4FA8FF4C.5050400@openwrt.org> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-ntJ3kIXU1PPEY1rrLb4x" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Mime-Version: 1.0 X-archive-position: 33195 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1473 Lines: 42 --=-ntJ3kIXU1PPEY1rrLb4x Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2012-05-08 at 13:11 +0200, John Crispin wrote: > That would be appreciated. i will get aligned with Ralf to make sure > this patch flow via his tree Feel free to add the following when you send to Ralf: Acked-by: Artem Bityutskiy --=20 Best Regards, Artem Bityutskiy --=-ntJ3kIXU1PPEY1rrLb4x Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPqQIOAAoJECmIfjd9wqK0SL0QAJOkcSNreolgiIYZD5nJBjL7 DBlS8vzfvH3TBhX8wd8TylVM7wLzuVgtKP2r/LsDN48Qzgod6ccswuNHresrCxgQ O7k/dHZV921nbkVGLUqrLb4G8BbsTbI+Gx1hlS7EoJoOprJJ6N/SYdNvg7riSMxf O3/5vXUspg+hcd0fjC2bPd/OVV93ZQx+lbaTRmmEZoPj9Dngj4blfnpW7yfOqmJs 9swnDWu4HsPWxgGvzYmqyPTehyXNrFrWe3p8cUa3VWtHFbBU3RTT2FzN0Doe/zZJ 1JwDDiXoBZFu2H2cuNjiXq3O+JzAC4DAjKrYXF03OWMh+R9BHCRJydS7T2osPub7 bHj+C7qDKB/O0Of+kE1EpHvELCUlWL5qx+7TdySm/fN5nQJSETU+o34pNlRaZBSv /fZ8Z1tVr8AzI8lKREB67i4LQaSiTcxcn5MBlo+IA0yXLJT7CdpwWN9XNeTrH0jK 1OKIn4/P+e74evqiLYQf5uSxaya9TF9ug0BSu/TmHfQQNE5l56QhAiotkEMEK+pn ZXPIG3ucun+e6hOyZXhri6HVDHlo8Zyo6Rgd/K+dA86C0iLopjkHd9r5Jj765F/w FrAs5yLZ/Pk7GBqwd1dOam/YYkC5bhSecSXgRFKG/I2iRwqeV5SEDQMneZcRDd5J eyFB2V8YMoDhypvOWzlQ =s0vS -----END PGP SIGNATURE----- --=-ntJ3kIXU1PPEY1rrLb4x-- From jayachandranc@netlogicmicro.com Tue May 8 14:42:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:42:52 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2768 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903640Ab2EHMmo (ORCPT ); Tue, 8 May 2012 14:42:44 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:52 -0700 X-Server-Uuid: 72204117-5C29-4314-8910-60DB108979CB Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:42:28 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 1747A9F9F5; Tue, 8 May 2012 05:42:28 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:27 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 05/14] MIPS: Netlogic: Update comments in smpboot.S Date: Tue, 8 May 2012 18:11:59 +0530 Message-ID: <1336480928-18887-6-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB4644G1245195-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33196 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6680 Lines: 226 No change in logic, comments update and whitespace cleanup. * A few comments in the file were in assembler style and the rest int C style, convert all of them to C style. * Mark workarounds for Ax silicon with a macro XLP_AX_WORKAROUND * Whitespace fixes - use tabs consistently * rename __config_lsu macro to xlp_config_lsu Signed-off-by: Jayachandran C --- arch/mips/netlogic/common/smpboot.S | 112 +++++++++++++++++++---------------- 1 file changed, 61 insertions(+), 51 deletions(-) diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index c138b1a..bfe9060 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -54,28 +54,36 @@ XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ SYS_CPU_NONCOHERENT_MODE * 4 -.macro __config_lsu - li t0, LSU_DEFEATURE - mfcr t1, t0 +#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */ - lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */ - or t1, t1, t2 - li t2, ~0xe /* S1RCM */ +/* Enable XLP features and workarounds in the LSU */ +.macro xlp_config_lsu + li t0, LSU_DEFEATURE + mfcr t1, t0 + + lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */ + or t1, t1, t2 +#ifdef XLP_AX_WORKAROUND + li t2, ~0xe /* S1RCM */ and t1, t1, t2 +#endif mtcr t1, t0 - li t0, SCHED_DEFEATURE - lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */ - mtcr t1, t0 +#ifdef XLP_AX_WORKAROUND + li t0, SCHED_DEFEATURE + lui t1, 0x0100 /* Disable BRU accepting ALU ops */ + mtcr t1, t0 +#endif .endm /* - * The cores can come start when they are woken up. This is also the NMI - * entry, so check that first. + * This is the code that will be copied to the reset entry point for + * XLR and XLP. The XLP cores start here when they are woken up. This + * is also the NMI entry point. * - * The data corresponding to reset is stored at RESET_DATA_PHYS location, - * this will have the thread mask (used when core is woken up) and the - * current NMI handler in case we reached here for an NMI. + * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS + * location, this will have the thread mask (used when core is woken up) + * and the current NMI handler in case we reached here for an NMI. * * When a core or thread is newly woken up, it loops in a 'wait'. When * the CPU really needs waking up, we send an NMI to it, with the NMI @@ -89,12 +97,12 @@ FEXPORT(nlm_reset_entry) dmtc0 k0, $22, 6 dmtc0 k1, $22, 7 - mfc0 k0, CP0_STATUS - li k1, 0x80000 - and k1, k0, k1 - beqz k1, 1f /* go to real reset entry */ + mfc0 k0, CP0_STATUS + li k1, 0x80000 + and k1, k0, k1 + beqz k1, 1f /* go to real reset entry */ nop - li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ + li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ ld k0, BOOT_NMI_HANDLER(k1) jr k0 nop @@ -114,21 +122,23 @@ FEXPORT(nlm_reset_entry) li t2, SYS_CPU_COHERENT_BASE(0) add t2, t2, t3 /* t2 <- SYS offset for node */ lw t1, 0(t2) - and t1, t1, t0 - sw t1, 0(t2) + and t1, t1, t0 + sw t1, 0(t2) /* read back to ensure complete */ - lw t1, 0(t2) + lw t1, 0(t2) sync /* Configure LSU on Non-0 Cores. */ - __config_lsu + xlp_config_lsu + /* FALL THROUGH */ /* * Wake up sibling threads from the initial thread in * a core. */ EXPORT(nlm_boot_siblings) + /* Enable hw threads by writing to MAP_THREADMODE of the core */ li t0, CKSEG1ADDR(RESET_DATA_PHYS) lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) @@ -139,24 +149,24 @@ EXPORT(nlm_boot_siblings) /* * The new hardware thread starts at the next instruction * For all the cases other than core 0 thread 0, we will - * jump to the secondary wait function. - */ + * jump to the secondary wait function. + */ mfc0 v0, CP0_EBASE, 1 andi v0, 0x7f /* v0 <- node/core */ -#if 1 - /* A0 errata - Write MMU_SETUP after changing thread mode register. */ + /* Init MMU in the first thread after changing THREAD_MODE + * register (Ax Errata?) + */ andi v1, v0, 0x3 /* v1 <- thread id */ bnez v1, 2f nop - li t0, MMU_SETUP - li t1, 0 - mtcr t1, t0 + li t0, MMU_SETUP + li t1, 0 + mtcr t1, t0 ehb -#endif -2: beqz v0, 4f +2: beqz v0, 4f /* boot cpu (cpuid == 0)? */ nop /* setup status reg */ @@ -183,9 +193,9 @@ EXPORT(nlm_boot_siblings) * For the boot CPU, we have to restore registers and * return */ -4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ +4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ li t1, 0xfadebeef - dmtc0 t1, $4, 2 /* restore SP from UserLocal */ + dmtc0 t1, $4, 2 /* restore SP from UserLocal */ PTR_SUBU sp, t0, PT_SIZE RESTORE_ALL jr ra @@ -193,7 +203,7 @@ EXPORT(nlm_boot_siblings) EXPORT(nlm_reset_entry_end) FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ - __config_lsu + xlp_config_lsu dmtc0 sp, $4, 2 /* SP saved in UserLocal */ SAVE_ALL sync @@ -234,36 +244,36 @@ END(nlm_boot_secondary_cpus) */ __CPUINIT NESTED(nlm_rmiboot_preboot, 16, sp) - mfc0 t0, $15, 1 # read ebase - andi t0, 0x1f # t0 has the processor_id() - andi t2, t0, 0x3 # thread no - sll t0, 2 # offset in cpu array + mfc0 t0, $15, 1 /* read ebase */ + andi t0, 0x1f /* t0 has the processor_id() */ + andi t2, t0, 0x3 /* thread num */ + sll t0, 2 /* offset in cpu array */ - PTR_LA t1, nlm_cpu_ready # mark CPU ready + PTR_LA t1, nlm_cpu_ready /* mark CPU ready */ PTR_ADDU t1, t0 li t3, 1 sw t3, 0(t1) - bnez t2, 1f # skip thread programming - nop # for non zero hw threads + bnez t2, 1f /* skip thread programming */ + nop /* for thread id != 0 */ /* - * MMU setup only for first thread in core + * XLR MMU setup only for first thread in core */ li t0, 0x400 mfcr t1, t0 - li t2, 6 # XLR thread mode mask + li t2, 6 /* XLR thread mode mask */ nor t3, t2, zero - and t2, t1, t2 # t2 - current thread mode + and t2, t1, t2 /* t2 - current thread mode */ li v0, CKSEG1ADDR(RESET_DATA_PHYS) - lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode + lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */ sll v1, 1 - beq v1, t2, 1f # same as request value - nop # nothing to do */ + beq v1, t2, 1f /* same as request value */ + nop /* nothing to do */ - and t2, t1, t3 # mask out old thread mode - or t1, t2, v1 # put in new value - mtcr t1, t0 # update core control + and t2, t1, t3 /* mask out old thread mode */ + or t1, t2, v1 /* put in new value */ + mtcr t1, t0 /* update core control */ 1: wait j 1b -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:43:17 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2742 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903633Ab2EHMmn (ORCPT ); Tue, 8 May 2012 14:42:43 +0200 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:44 -0700 X-Server-Uuid: 72204117-5C29-4314-8910-60DB108979CB Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:41:40 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id D82019F9F9; Tue, 8 May 2012 05:42:19 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:19 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 01/14] MIPS: Netlogic: Fix PCIX irq on XLR chips Date: Tue, 8 May 2012 18:11:55 +0530 Message-ID: <1336480928-18887-2-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB4E44G1245127-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33197 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 590 Lines: 24 The correct irq is PIC_PCIX_IRQ Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 1644805..50ff4dc 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -327,7 +327,7 @@ static int __init pcibios_init(void) } } else { /* XLR PCI controller ACK */ - irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack); + irq_set_handler_data(PIC_PCIX_IRQ, xlr_pci_ack); } return 0; -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:43:41 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2743 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903636Ab2EHMmn (ORCPT ); Tue, 8 May 2012 14:42:43 +0200 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:42 -0700 X-Server-Uuid: 72204117-5C29-4314-8910-60DB108979CB Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:41:38 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id DA1019F9F7; Tue, 8 May 2012 05:42:17 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:17 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH UPDATED 00/14] Netlogic XLR/XLS/XLP updates. Date: Tue, 8 May 2012 18:11:54 +0530 Message-ID: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB4844G1245115-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33198 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3391 Lines: 76 This is an update for the patcheset I had posted earlier. The changes from v1 are: - re-write the MSI fix a bit make it look better [and also update commit message - noted by sshtylyov@mvista.com] - Add two more patches for XLP - one to probe FDT SoC devices, and another to add a few IRQs which will be used for SoC devices. [Description of the patchset from v1] Fixes and updates for the next merge window. This includes - PCI fixs for XLR/XLS - I2C, Flash and USB platform drivers for XLR/XLS - XLP SMP code update and clean up - XLP TLB size fix - XLP USB and PCI changes. Let me know if there are any comments. Thanks, JC. Ganesan Ramalingam (5): MIPS: Netlogic: MSI enable fix for XLS MIPS: Netlogic: Platform NAND/NOR flash support MIPS: Netlogic: XLP PCIe controller support. MIPS: Netlogic: USB support for XLP MIPS: Netlogic: Add XLP SoC devices in FDT Jayachandran C (9): MIPS: Netlogic: Fix PCIX irq on XLR chips MIPS: Netlogic: Remove unused pcibios_fixups MIPS: Netlogic: Fix TLB size of boot CPU. MIPS: Netlogic: Update comments in smpboot.S MIPS: Netlogic: SMP wakeup code update MIPS: Netlogic: Remove NETLOGIC_ prefix MIPS: Netlogic: Platform changes for XLS USB MIPS: Netlogic: Platform changes for XLR/XLS I2C MIPS: Netlogic: Add IRQ mappings for more devices arch/mips/Kconfig | 3 +- arch/mips/configs/nlm_xlr_defconfig | 4 + .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 4 +- arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 5 +- arch/mips/include/asm/netlogic/xlp-hal/pcibus.h | 76 ++++++ arch/mips/include/asm/netlogic/xlp-hal/pic.h | 4 + arch/mips/include/asm/netlogic/xlp-hal/usb.h | 64 +++++ arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 17 +- arch/mips/include/asm/netlogic/xlr/bridge.h | 104 +++++++++ arch/mips/include/asm/netlogic/xlr/flash.h | 55 +++++ arch/mips/include/asm/netlogic/xlr/gpio.h | 59 ++--- arch/mips/netlogic/common/smpboot.S | 159 ++++++++----- arch/mips/netlogic/xlp/Makefile | 1 + arch/mips/netlogic/xlp/nlm_hal.c | 52 +++++ arch/mips/netlogic/xlp/platform.c | 2 +- arch/mips/netlogic/xlp/setup.c | 24 +- arch/mips/netlogic/xlp/usb-init.c | 124 ++++++++++ arch/mips/netlogic/xlr/Makefile | 2 +- arch/mips/netlogic/xlr/platform-flash.c | 220 +++++++++++++++++ arch/mips/netlogic/xlr/platform.c | 140 +++++++++++ arch/mips/netlogic/xlr/setup.c | 2 +- arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-xlp.c | 247 ++++++++++++++++++++ arch/mips/pci/pci-xlr.c | 65 ++++-- 24 files changed, 1326 insertions(+), 108 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/usb.h create mode 100644 arch/mips/include/asm/netlogic/xlr/bridge.h create mode 100644 arch/mips/include/asm/netlogic/xlr/flash.h create mode 100644 arch/mips/netlogic/xlp/usb-init.c create mode 100644 arch/mips/netlogic/xlr/platform-flash.c create mode 100644 arch/mips/pci/pci-xlp.c -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:44:07 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2765 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903643Ab2EHMmo (ORCPT ); Tue, 8 May 2012 14:42:44 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:50 -0700 X-Server-Uuid: 72204117-5C29-4314-8910-60DB108979CB Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:42:26 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 17A5D9F9F5; Tue, 8 May 2012 05:42:26 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:25 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 04/14] MIPS: Netlogic: Fix TLB size of boot CPU. Date: Tue, 8 May 2012 18:11:58 +0530 Message-ID: <1336480928-18887-5-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB4044G1245167-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33199 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1397 Lines: 43 Starting other threads in the core will change the number of TLB entries of a CPU. Re-calculate current_cpu_data.tlbsize on the boot cpu after enabling and waking up other threads. The secondary CPUs do not need this logic because the threads are enabled on the secondary cores at wakeup and before cpu_probe. Signed-off-by: Jayachandran C --- arch/mips/netlogic/xlp/setup.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index acb677a..b3df7c2 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -82,8 +82,10 @@ void __init prom_free_prom_memory(void) void xlp_mmu_init(void) { + /* enable extended TLB and Large Fixed TLB */ write_c0_config6(read_c0_config6() | 0x24); - current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; + + /* set page mask of Fixed TLB in config7 */ write_c0_config7(PM_DEFAULT_MASK >> (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); } @@ -100,6 +102,10 @@ void __init prom_init(void) nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); #ifdef CONFIG_SMP nlm_wakeup_secondary_cpus(0xffffffff); + + /* update TLB size after waking up threads */ + current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; + register_smp_ops(&nlm_smp_ops); #endif } -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:44:31 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2259 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903688Ab2EHMmo (ORCPT ); Tue, 8 May 2012 14:42:44 +0200 Received: from [10.9.200.133] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:40 -0700 X-Server-Uuid: B730DE51-FC43-4C83-941F-F1F78A914BDD Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:41:44 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 1DE199F9FB; Tue, 8 May 2012 05:42:24 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:23 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 03/14] MIPS: Netlogic: Remove unused pcibios_fixups Date: Tue, 8 May 2012 18:11:57 +0530 Message-ID: <1336480928-18887-4-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB4A3E029935964-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33200 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 522 Lines: 24 This global is unneeded, and seems to be carried over from ancient code. Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlr.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 172af1c..18af021 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -375,7 +375,3 @@ static int __init pcibios_init(void) } arch_initcall(pcibios_init); - -struct pci_fixup pcibios_fixups[] = { - {0} -}; -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:44:56 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2260 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903687Ab2EHMmo (ORCPT ); Tue, 8 May 2012 14:42:44 +0200 Received: from [10.9.200.133] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:39 -0700 X-Server-Uuid: B730DE51-FC43-4C83-941F-F1F78A914BDD Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:41:42 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 1B60F9F9FA; Tue, 8 May 2012 05:42:22 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:21 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Ganesan Ramalingam" , "Jayachandran C" Subject: [PATCH 02/14] MIPS: Netlogic: MSI enable fix for XLS Date: Tue, 8 May 2012 18:11:56 +0530 Message-ID: <1336480928-18887-3-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB353E029935953-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33201 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3459 Lines: 130 From: Ganesan Ramalingam MSI interrupts do not work on XLS after commit a776c49 ( "PCI: msi: Disable msi interrupts when we initialize a pci device" ) because the change disables MSI interrupts on the XLS PCIe bridges during the PCI enumeration. Fix this by enabling MSI interrupts on the bridge in the arch_setup_msi_irq() function. A new function xls_get_pcie_link() has been introduced to get the PCI device corresponding to the top level PCIe bridge on which MSI has to be enabled. Also, update get_irq_vector() to use the new xls_get_pcie_link() function and PCI_SLOT() macro for determining the IRQ of PCI devices. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlr.c | 59 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 50 insertions(+), 9 deletions(-) diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 50ff4dc..172af1c 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -41,6 +41,7 @@ #include #include #include +#include #include @@ -156,35 +157,55 @@ struct pci_controller nlm_pci_controller = { .io_offset = 0x00000000UL, }; +/* + * The top level PCIe links on the XLS PCIe controller appear as + * bridges. Given a device, this function finds which link it is + * on. + */ +static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev) +{ + struct pci_bus *bus, *p; + + /* Find the bridge on bus 0 */ + bus = dev->bus; + for (p = bus->parent; p && p->number != 0; p = p->parent) + bus = p; + + return p ? bus->self : NULL; +} + static int get_irq_vector(const struct pci_dev *dev) { + struct pci_dev *lnk; + if (!nlm_chip_is_xls()) - return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ + return PIC_PCIX_IRQ; /* for XLR just one IRQ */ /* * For XLS PCIe, there is an IRQ per Link, find out which * link the device is on to assign interrupts - */ - if (dev->bus->self == NULL) + */ + lnk = xls_get_pcie_link(dev); + if (lnk == NULL) return 0; - switch (dev->bus->self->devfn) { - case 0x0: + switch (PCI_SLOT(lnk->devfn)) { + case 0: return PIC_PCIE_LINK0_IRQ; - case 0x8: + case 1: return PIC_PCIE_LINK1_IRQ; - case 0x10: + case 2: if (nlm_chip_is_xls_b()) return PIC_PCIE_XLSB0_LINK2_IRQ; else return PIC_PCIE_LINK2_IRQ; - case 0x18: + case 3: if (nlm_chip_is_xls_b()) return PIC_PCIE_XLSB0_LINK3_IRQ; else return PIC_PCIE_LINK3_IRQ; } - WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); + WARN(1, "Unexpected devfn %d\n", lnk->devfn); return 0; } @@ -202,7 +223,27 @@ void arch_teardown_msi_irq(unsigned int irq) int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) { struct msi_msg msg; + struct pci_dev *lnk; int irq, ret; + u16 val; + + /* MSI not supported on XLR */ + if (!nlm_chip_is_xls()) + return 1; + + /* + * Enable MSI on the XLS PCIe controller bridge which was disabled + * at enumeration, the bridge MSI capability is at 0x50 + */ + lnk = xls_get_pcie_link(dev); + if (lnk == NULL) + return 1; + + pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val); + if ((val & PCI_MSI_FLAGS_ENABLE) == 0) { + val |= PCI_MSI_FLAGS_ENABLE; + pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val); + } irq = get_irq_vector(dev); if (irq <= 0) -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:45:19 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2802 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903689Ab2EHMmt (ORCPT ); Tue, 8 May 2012 14:42:49 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:56 -0700 X-Server-Uuid: 72204117-5C29-4314-8910-60DB108979CB Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:42:32 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 1491D9F9FC; Tue, 8 May 2012 05:42:32 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:31 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 07/14] MIPS: Netlogic: Remove NETLOGIC_ prefix Date: Tue, 8 May 2012 18:12:01 +0530 Message-ID: <1336480928-18887-8-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB5A44G1245233-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33202 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3576 Lines: 103 Remove NETLOGIC_ prefix from gpio register definitions, this will bring it in-line with the other Netlogic headers. Having NETLOGIC prefix here is misleading because these are XLR/XLS specific register definitions. Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlr/gpio.h | 59 +++++++++++++++-------------- arch/mips/netlogic/xlr/setup.c | 2 +- 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h index 51f6ad4..8492e83 100644 --- a/arch/mips/include/asm/netlogic/xlr/gpio.h +++ b/arch/mips/include/asm/netlogic/xlr/gpio.h @@ -35,39 +35,40 @@ #ifndef _ASM_NLM_GPIO_H #define _ASM_NLM_GPIO_H -#define NETLOGIC_GPIO_INT_EN_REG 0 -#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 -#define NETLOGIC_GPIO_IO_DIR_REG 2 -#define NETLOGIC_GPIO_IO_DATA_WR_REG 3 -#define NETLOGIC_GPIO_IO_DATA_RD_REG 4 +#define GPIO_INT_EN_REG 0 +#define GPIO_INPUT_INVERSION_REG 1 +#define GPIO_IO_DIR_REG 2 +#define GPIO_IO_DATA_WR_REG 3 +#define GPIO_IO_DATA_RD_REG 4 -#define NETLOGIC_GPIO_SWRESET_REG 8 -#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 -#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 -#define NETLOGIC_GPIO_DRAM1_RESET_REG 11 -#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 -#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 -#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 -#define NETLOGIC_GPIO_DRAM2_RESET_REG 15 -#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 +#define GPIO_SWRESET_REG 8 +#define GPIO_DRAM1_CNTRL_REG 9 +#define GPIO_DRAM1_RATIO_REG 10 +#define GPIO_DRAM1_RESET_REG 11 +#define GPIO_DRAM1_STATUS_REG 12 +#define GPIO_DRAM2_CNTRL_REG 13 +#define GPIO_DRAM2_RATIO_REG 14 +#define GPIO_DRAM2_RESET_REG 15 +#define GPIO_DRAM2_STATUS_REG 16 -#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 -#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 -#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 -#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 +#define GPIO_PWRON_RESET_CFG_REG 21 +#define GPIO_BIST_ALL_GO_STATUS_REG 24 +#define GPIO_BIST_CPU_GO_STATUS_REG 25 +#define GPIO_BIST_DEV_GO_STATUS_REG 26 -#define NETLOGIC_GPIO_FUSE_BANK_REG 35 -#define NETLOGIC_GPIO_CPU_RESET_REG 40 -#define NETLOGIC_GPIO_RNG_REG 43 +#define GPIO_FUSE_BANK_REG 35 +#define GPIO_CPU_RESET_REG 40 +#define GPIO_RNG_REG 43 -#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 -#define NETLOGIC_GPIO_LED_BITMAP 0x1700000 -#define NETLOGIC_GPIO_LED_0_SHIFT 20 -#define NETLOGIC_GPIO_LED_1_SHIFT 24 +#define PWRON_RESET_PCMCIA_BOOT 17 -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 +#define GPIO_LED_BITMAP 0x1700000 +#define GPIO_LED_0_SHIFT 20 +#define GPIO_LED_1_SHIFT 24 + +#define GPIO_LED_OUTPUT_CODE_RESET 0x01 +#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 +#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 +#define GPIO_LED_OUTPUT_CODE_MAIN 0x04 #endif diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index c9d066d..81b1d31 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -85,7 +85,7 @@ static void nlm_linux_exit(void) gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ - nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1); + nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1); for ( ; ; ) cpu_wait(); } -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:45:42 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2302 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903690Ab2EHMmt (ORCPT ); Tue, 8 May 2012 14:42:49 +0200 Received: from [10.9.200.133] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:47 -0700 X-Server-Uuid: B730DE51-FC43-4C83-941F-F1F78A914BDD Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:41:50 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 161EA9F9F5; Tue, 8 May 2012 05:42:30 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:29 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 06/14] MIPS: Netlogic: SMP wakeup code update Date: Tue, 8 May 2012 18:12:00 +0530 Message-ID: <1336480928-18887-7-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB4C3E029936001-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33203 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3110 Lines: 116 Update for core intialization code. Initialize status register after receiving NMI for CPU wakeup. Add the low level L1D flush code before enabling threads in core. Also convert the ehb to _ehb so that it works under more GCC versions. Signed-off-by: Jayachandran C --- .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 4 +- arch/mips/netlogic/common/smpboot.S | 47 +++++++++++++++++--- 2 files changed, 45 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h index bf7d41d..7b63a6b 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h @@ -47,7 +47,9 @@ #define CPU_BLOCKID_MAP 10 #define LSU_DEFEATURE 0x304 -#define LSU_CERRLOG_REGID 0x09 +#define LSU_DEBUG_ADDR 0x305 +#define LSU_DEBUG_DATA0 0x306 +#define LSU_CERRLOG_REGID 0x309 #define SCHED_DEFEATURE 0x700 /* Offsets of interest from the 'MAP' Block */ diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index bfe9060..aa86590 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -77,6 +77,38 @@ .endm /* + * Low level L1 d-cache flush for core, needs to be called before + * threads are enabled + */ +.macro xlp_flush_l1_dcache + li t0, LSU_DEBUG_DATA0 + li t1, LSU_DEBUG_ADDR + li t2, 0 /* index */ + li t3, 0x200 /* loop count, 512 sets */ +1: + sll v0, t2, 5 + mtcr zero, t0 + ori v1, v0, 0x3 /* way0 | write_enable | write_active */ + mtcr v1, t1 +2: + mfcr v1, t1 + andi v1, 0x1 /* wait for write_active == 0 */ + bnez v1, 2b + nop + mtcr zero, t0 + ori v1, v0, 0x7 /* way1 | write_enable | write_active */ + mtcr v1, t1 +3: + mfcr v1, t1 + andi v1, 0x1 /* wait for write_active == 0 */ + bnez v1, 3b + nop + addi t2, 1 + bne t3, t2, 1b + nop +.endm + +/* * This is the code that will be copied to the reset entry point for * XLR and XLP. The XLP cores start here when they are woken up. This * is also the NMI entry point. @@ -138,6 +170,8 @@ FEXPORT(nlm_reset_entry) * a core. */ EXPORT(nlm_boot_siblings) + /* core L1D flush before enable threads */ + xlp_flush_l1_dcache /* Enable hw threads by writing to MAP_THREADMODE of the core */ li t0, CKSEG1ADDR(RESET_DATA_PHYS) lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ @@ -164,16 +198,13 @@ EXPORT(nlm_boot_siblings) li t0, MMU_SETUP li t1, 0 mtcr t1, t0 - ehb + _ehb 2: beqz v0, 4f /* boot cpu (cpuid == 0)? */ nop /* setup status reg */ - mfc0 t1, CP0_STATUS - li t0, ST0_BEV - or t1, t0 - xor t1, t0 + move t1, zero #ifdef CONFIG_64BIT ori t1, ST0_KX #endif @@ -220,6 +251,12 @@ FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ __CPUINIT NESTED(nlm_boot_secondary_cpus, 16, sp) + /* Initialize CP0 Status */ + move t1, zero +#ifdef CONFIG_64BIT + ori t1, ST0_KX +#endif + mtc0 t1, CP0_STATUS PTR_LA t1, nlm_next_sp PTR_L sp, 0(t1) PTR_LA t1, nlm_next_gp -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:46:13 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2743 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903692Ab2EHMmx (ORCPT ); Tue, 8 May 2012 14:42:53 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:43:08 -0700 X-Server-Uuid: 72204117-5C29-4314-8910-60DB108979CB Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:42:43 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id B95209F9F5; Tue, 8 May 2012 05:42:43 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:42 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Ganesan Ramalingam" , "Jayachandran C" Subject: [PATCH 12/14] MIPS: Netlogic: USB support for XLP Date: Tue, 8 May 2012 18:12:06 +0530 Message-ID: <1336480928-18887-13-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB5644G1245331-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33204 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 12233 Lines: 339 From: Ganesan Ramalingam The XLP USB controller appears as a device on the internal SoC PCIe bus, the block has 2 EHCI blocks and 4 OHCI blocks. Change are to: * Add files netlogic/xlp/usb-init.c and asm/netlogic/xlp-hal/usb.h to initialize the USB controller and define PCI fixups. The PCI fixups are to setup interrupts and DMA mask. * Update include/asm/xlp-hal/{iomap.h,pic.h,xlp.h} to add interrupt mapping for EHCI/OHCI interrupts. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 2 +- arch/mips/include/asm/netlogic/xlp-hal/pic.h | 4 + arch/mips/include/asm/netlogic/xlp-hal/usb.h | 64 ++++++++++++ arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 6 ++ arch/mips/netlogic/xlp/Makefile | 1 + arch/mips/netlogic/xlp/nlm_hal.c | 24 +++++ arch/mips/netlogic/xlp/platform.c | 2 +- arch/mips/netlogic/xlp/usb-init.c | 124 ++++++++++++++++++++++++ 8 files changed, 225 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/usb.h create mode 100644 arch/mips/netlogic/xlp/usb-init.c diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h index ece86f1..2c63f97 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h @@ -132,7 +132,7 @@ #define PCI_DEVICE_ID_NLM_PIC 0x1003 #define PCI_DEVICE_ID_NLM_PCIE 0x1004 #define PCI_DEVICE_ID_NLM_EHCI 0x1007 -#define PCI_DEVICE_ID_NLM_ILK 0x1008 +#define PCI_DEVICE_ID_NLM_OHCI 0x1008 #define PCI_DEVICE_ID_NLM_NAE 0x1009 #define PCI_DEVICE_ID_NLM_POE 0x100A #define PCI_DEVICE_ID_NLM_FMN 0x100B diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h index b6628f7..ad8b802 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h @@ -201,7 +201,11 @@ #define PIC_NUM_USB_IRTS 6 #define PIC_IRT_USB_0_INDEX 115 #define PIC_IRT_EHCI_0_INDEX 115 +#define PIC_IRT_OHCI_0_INDEX 116 +#define PIC_IRT_OHCI_1_INDEX 117 #define PIC_IRT_EHCI_1_INDEX 118 +#define PIC_IRT_OHCI_2_INDEX 119 +#define PIC_IRT_OHCI_3_INDEX 120 #define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX) /* 115 to 120 */ #define PIC_IRT_GDX_INDEX 121 diff --git a/arch/mips/include/asm/netlogic/xlp-hal/usb.h b/arch/mips/include/asm/netlogic/xlp-hal/usb.h new file mode 100644 index 0000000..a9cd350 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/usb.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NLM_HAL_USB_H__ +#define __NLM_HAL_USB_H__ + +#define USB_CTL_0 0x01 +#define USB_PHY_0 0x0A +#define USB_PHY_RESET 0x01 +#define USB_PHY_PORT_RESET_0 0x10 +#define USB_PHY_PORT_RESET_1 0x20 +#define USB_CONTROLLER_RESET 0x01 +#define USB_INT_STATUS 0x0E +#define USB_INT_EN 0x0F +#define USB_PHY_INTERRUPT_EN 0x01 +#define USB_OHCI_INTERRUPT_EN 0x02 +#define USB_OHCI_INTERRUPT1_EN 0x04 +#define USB_OHCI_INTERRUPT2_EN 0x08 +#define USB_CTRL_INTERRUPT_EN 0x10 + +#ifndef __ASSEMBLY__ + +#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_get_usb_pcibase(node, inst) \ + nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst)) +#define nlm_get_usb_hcd_base(node, inst) \ + nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst)) +#define nlm_get_usb_regbase(node, inst) \ + (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) + +#endif +#endif /* __NLM_HAL_USB_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index dc6e98e..3921a31 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -41,6 +41,12 @@ #define PIC_PCIE_LINK_1_IRQ 20 #define PIC_PCIE_LINK_2_IRQ 21 #define PIC_PCIE_LINK_3_IRQ 22 +#define PIC_EHCI_0_IRQ 23 +#define PIC_EHCI_1_IRQ 24 +#define PIC_OHCI_0_IRQ 25 +#define PIC_OHCI_1_IRQ 26 +#define PIC_OHCI_2_IRQ 27 +#define PIC_OHCI_3_IRQ 28 #ifndef __ASSEMBLY__ diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile index b93ed83..5bd24b6 100644 --- a/arch/mips/netlogic/xlp/Makefile +++ b/arch/mips/netlogic/xlp/Makefile @@ -1,2 +1,3 @@ obj-y += setup.o platform.o nlm_hal.o obj-$(CONFIG_SMP) += wakeup.o +obj-$(CONFIG_USB) += usb-init.o diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c index 3a4a172..fad2cae 100644 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ b/arch/mips/netlogic/xlp/nlm_hal.c @@ -77,6 +77,18 @@ int nlm_irq_to_irt(int irq) return PIC_IRT_PCIE_LINK_2_INDEX; case PIC_PCIE_LINK_3_IRQ: return PIC_IRT_PCIE_LINK_3_INDEX; + case PIC_EHCI_0_IRQ: + return PIC_IRT_EHCI_0_INDEX; + case PIC_EHCI_1_IRQ: + return PIC_IRT_EHCI_1_INDEX; + case PIC_OHCI_0_IRQ: + return PIC_IRT_OHCI_0_INDEX; + case PIC_OHCI_1_IRQ: + return PIC_IRT_OHCI_1_INDEX; + case PIC_OHCI_2_IRQ: + return PIC_IRT_OHCI_2_INDEX; + case PIC_OHCI_3_IRQ: + return PIC_IRT_OHCI_3_INDEX; default: return -1; } @@ -97,6 +109,18 @@ int nlm_irt_to_irq(int irt) return PIC_PCIE_LINK_2_IRQ; case PIC_IRT_PCIE_LINK_3_INDEX: return PIC_PCIE_LINK_3_IRQ; + case PIC_IRT_EHCI_0_INDEX: + return PIC_EHCI_0_IRQ; + case PIC_IRT_EHCI_1_INDEX: + return PIC_EHCI_1_IRQ; + case PIC_IRT_OHCI_0_INDEX: + return PIC_OHCI_0_IRQ; + case PIC_IRT_OHCI_1_INDEX: + return PIC_OHCI_1_IRQ; + case PIC_IRT_OHCI_2_INDEX: + return PIC_OHCI_2_IRQ; + case PIC_IRT_OHCI_3_INDEX: + return PIC_OHCI_3_IRQ; default: return -1; } diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c index 1f5e4cb..2c510d5 100644 --- a/arch/mips/netlogic/xlp/platform.c +++ b/arch/mips/netlogic/xlp/platform.c @@ -53,7 +53,7 @@ static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset) { - return nlm_read_reg(p->iobase, offset); + return nlm_read_reg(p->iobase, offset); } static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value) diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c new file mode 100644 index 0000000..dbe083a --- /dev/null +++ b/arch/mips/netlogic/xlp/usb-init.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static void nlm_usb_intr_en(int node, int port) +{ + uint32_t val; + uint64_t port_addr; + + port_addr = nlm_get_usb_regbase(node, port); + val = nlm_read_usb_reg(port_addr, USB_INT_EN); + val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | + USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN | + USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN; + nlm_write_usb_reg(port_addr, USB_INT_EN, val); +} + +static void nlm_usb_hw_reset(int node, int port) +{ + uint64_t port_addr; + uint32_t val; + + /* reset USB phy */ + port_addr = nlm_get_usb_regbase(node, port); + val = nlm_read_usb_reg(port_addr, USB_PHY_0); + val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1); + nlm_write_usb_reg(port_addr, USB_PHY_0, val); + + mdelay(100); + val = nlm_read_usb_reg(port_addr, USB_CTL_0); + val &= ~(USB_CONTROLLER_RESET); + val |= 0x4; + nlm_write_usb_reg(port_addr, USB_CTL_0, val); +} + +static int __init nlm_platform_usb_init(void) +{ + pr_info("Initializing USB Interface\n"); + nlm_usb_hw_reset(0, 0); + nlm_usb_hw_reset(0, 3); + + /* Enable PHY interrupts */ + nlm_usb_intr_en(0, 0); + nlm_usb_intr_en(0, 3); + + return 0; +} + +arch_initcall(nlm_platform_usb_init); + +static u64 xlp_usb_dmamask = ~(u32)0; + +/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */ +static void nlm_usb_fixup_final(struct pci_dev *dev) +{ + dev->dev.dma_mask = &xlp_usb_dmamask; + dev->dev.coherent_dma_mask = DMA_BIT_MASK(64); + switch (dev->devfn) { + case 0x10: + dev->irq = PIC_EHCI_0_IRQ; + break; + case 0x11: + dev->irq = PIC_OHCI_0_IRQ; + break; + case 0x12: + dev->irq = PIC_OHCI_1_IRQ; + break; + case 0x13: + dev->irq = PIC_EHCI_1_IRQ; + break; + case 0x14: + dev->irq = PIC_OHCI_2_IRQ; + break; + case 0x15: + dev->irq = PIC_OHCI_3_IRQ; + break; + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI, + nlm_usb_fixup_final); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI, + nlm_usb_fixup_final); -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:46:38 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2302 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903696Ab2EHMmy (ORCPT ); Tue, 8 May 2012 14:42:54 +0200 Received: from [10.9.200.131] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:55 -0700 X-Server-Uuid: B730DE51-FC43-4C83-941F-F1F78A914BDD Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:42:39 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2CCAE9F9F6; Tue, 8 May 2012 05:42:39 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:38 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 10/14] MIPS: Netlogic: Platform changes for XLR/XLS I2C Date: Tue, 8 May 2012 18:12:04 +0530 Message-ID: <1336480928-18887-11-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB453E029936068-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33205 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2530 Lines: 94 Add platform code for XLR/XLS I2C controller and devices. Add devices on the I2C bus on the XLR/XLS developement boards. Signed-off-by: Jayachandran C --- arch/mips/configs/nlm_xlr_defconfig | 4 +++ arch/mips/netlogic/xlr/platform.c | 51 +++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig index d0b857d..138f698 100644 --- a/arch/mips/configs/nlm_xlr_defconfig +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -367,6 +367,10 @@ CONFIG_SERIAL_8250_RSA=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m CONFIG_RAW_DRIVER=m +CONFIG_I2C=y +CONFIG_I2C_XLR=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1374=y # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set # CONFIG_HID_SUPPORT is not set diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c index cb0ab63..71b44d8 100644 --- a/arch/mips/netlogic/xlr/platform.c +++ b/arch/mips/netlogic/xlr/platform.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -186,3 +187,53 @@ int xls_platform_usb_init(void) arch_initcall(xls_platform_usb_init); #endif + +#ifdef CONFIG_I2C +static struct i2c_board_info nlm_i2c_board_info1[] __initdata = { + /* All XLR boards have this RTC and Max6657 Temp Chip */ + [0] = { + .type = "ds1374", + .addr = 0x68 + }, + [1] = { + .type = "lm90", + .addr = 0x4c + }, +}; + +static struct resource i2c_resources[] = { + [0] = { + .start = 0, /* filled at init */ + .end = 0, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device nlm_xlr_i2c_1 = { + .name = "xlr-i2cbus", + .id = 1, + .num_resources = 1, + .resource = i2c_resources, +}; + +static int __init nlm_i2c_init(void) +{ + int err = 0; + unsigned int offset; + + /* I2C bus 0 does not have any useful devices, configure only bus 1 */ + offset = NETLOGIC_IO_I2C_1_OFFSET; + nlm_xlr_i2c_1.resource[0].start = CPHYSADDR(nlm_mmio_base(offset)); + nlm_xlr_i2c_1.resource[0].end = nlm_xlr_i2c_1.resource[0].start + 0xfff; + + platform_device_register(&nlm_xlr_i2c_1); + + err = i2c_register_board_info(1, nlm_i2c_board_info1, + ARRAY_SIZE(nlm_i2c_board_info1)); + if (err < 0) + pr_err("nlm-i2c: cannot register board I2C devices\n"); + return err; +} + +arch_initcall(nlm_i2c_init); +#endif -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:47:03 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2260 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903694Ab2EHMmy (ORCPT ); Tue, 8 May 2012 14:42:54 +0200 Received: from [10.9.200.133] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:53 -0700 X-Server-Uuid: B730DE51-FC43-4C83-941F-F1F78A914BDD Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:41:57 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2F0629F9F5; Tue, 8 May 2012 05:42:37 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:36 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Ganesan Ramalingam" , "Jayachandran C" Subject: [PATCH 09/14] MIPS: Netlogic: Platform NAND/NOR flash support Date: Tue, 8 May 2012 18:12:03 +0530 Message-ID: <1336480928-18887-10-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB473E029936048-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33206 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 13885 Lines: 426 From: Ganesan Ramalingam Changes to add support for the boot NOR flash on XLR boards and the boot NAND/NOR flash drivers on the XLS boards. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlr/bridge.h | 104 +++++++++++++ arch/mips/include/asm/netlogic/xlr/flash.h | 55 +++++++ arch/mips/netlogic/xlr/Makefile | 2 +- arch/mips/netlogic/xlr/platform-flash.c | 220 +++++++++++++++++++++++++++ 4 files changed, 380 insertions(+), 1 deletion(-) create mode 100644 arch/mips/include/asm/netlogic/xlr/bridge.h create mode 100644 arch/mips/include/asm/netlogic/xlr/flash.h create mode 100644 arch/mips/netlogic/xlr/platform-flash.c diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h new file mode 100644 index 0000000..2d02428 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/bridge.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _ASM_NLM_BRIDGE_H_ +#define _ASM_NLM_BRIDGE_H_ + +#define BRIDGE_DRAM_0_BAR 0 +#define BRIDGE_DRAM_1_BAR 1 +#define BRIDGE_DRAM_2_BAR 2 +#define BRIDGE_DRAM_3_BAR 3 +#define BRIDGE_DRAM_4_BAR 4 +#define BRIDGE_DRAM_5_BAR 5 +#define BRIDGE_DRAM_6_BAR 6 +#define BRIDGE_DRAM_7_BAR 7 +#define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8 +#define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9 +#define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10 +#define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11 +#define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12 +#define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13 +#define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14 +#define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15 +#define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16 +#define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17 +#define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18 +#define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19 +#define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20 +#define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21 +#define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22 +#define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23 +#define BRIDGE_CFG_BAR 24 +#define BRIDGE_PHNX_IO_BAR 25 +#define BRIDGE_FLASH_BAR 26 +#define BRIDGE_SRAM_BAR 27 +#define BRIDGE_HTMEM_BAR 28 +#define BRIDGE_HTINT_BAR 29 +#define BRIDGE_HTPIC_BAR 30 +#define BRIDGE_HTSM_BAR 31 +#define BRIDGE_HTIO_BAR 32 +#define BRIDGE_HTCFG_BAR 33 +#define BRIDGE_PCIXCFG_BAR 34 +#define BRIDGE_PCIXMEM_BAR 35 +#define BRIDGE_PCIXIO_BAR 36 +#define BRIDGE_DEVICE_MASK 37 +#define BRIDGE_AERR_INTR_LOG1 38 +#define BRIDGE_AERR_INTR_LOG2 39 +#define BRIDGE_AERR_INTR_LOG3 40 +#define BRIDGE_AERR_DEV_STAT 41 +#define BRIDGE_AERR1_LOG1 42 +#define BRIDGE_AERR1_LOG2 43 +#define BRIDGE_AERR1_LOG3 44 +#define BRIDGE_AERR1_DEV_STAT 45 +#define BRIDGE_AERR_INTR_EN 46 +#define BRIDGE_AERR_UPG 47 +#define BRIDGE_AERR_CLEAR 48 +#define BRIDGE_AERR1_CLEAR 49 +#define BRIDGE_SBE_COUNTS 50 +#define BRIDGE_DBE_COUNTS 51 +#define BRIDGE_BITERR_INT_EN 52 + +#define BRIDGE_SYS2IO_CREDITS 53 +#define BRIDGE_EVNT_CNT_CTRL1 54 +#define BRIDGE_EVNT_COUNTER1 55 +#define BRIDGE_EVNT_CNT_CTRL2 56 +#define BRIDGE_EVNT_COUNTER2 57 +#define BRIDGE_RESERVED1 58 + +#define BRIDGE_DEFEATURE 59 +#define BRIDGE_SCRATCH0 60 +#define BRIDGE_SCRATCH1 61 +#define BRIDGE_SCRATCH2 62 +#define BRIDGE_SCRATCH3 63 + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h new file mode 100644 index 0000000..f8aca54 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/flash.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _ASM_NLM_FLASH_H_ +#define _ASM_NLM_FLASH_H_ + +#define FLASH_CSBASE_ADDR(cs) (cs) +#define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) +#define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) +#define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) +#define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) + +#define FLASH_INT_MASK 0x50 +#define FLASH_INT_STATUS 0x60 +#define FLASH_ERROR_STATUS 0x70 +#define FLASH_ERROR_ADDR 0x80 + +#define FLASH_NAND_CLE(cs) (0x90 + (cs)) +#define FLASH_NAND_ALE(cs) (0xa0 + (cs)) + +#define FLASH_NAND_CSDEV_PARAM 0x000041e6 +#define FLASH_NAND_CSTIME_PARAMA 0x4f400e22 +#define FLASH_NAND_CSTIME_PARAMB 0x000083cf + +#endif diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile index f01e4d7..c287dea 100644 --- a/arch/mips/netlogic/xlr/Makefile +++ b/arch/mips/netlogic/xlr/Makefile @@ -1,2 +1,2 @@ -obj-y += setup.o platform.o +obj-y += setup.o platform.o platform-flash.o obj-$(CONFIG_SMP) += wakeup.o diff --git a/arch/mips/netlogic/xlr/platform-flash.c b/arch/mips/netlogic/xlr/platform-flash.c new file mode 100644 index 0000000..340ab16 --- /dev/null +++ b/arch/mips/netlogic/xlr/platform-flash.c @@ -0,0 +1,220 @@ +/* + * Copyright 2011, Netlogic Microsystems. + * Copyright 2004, Matt Porter + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* + * Default NOR partition layout + */ +static struct mtd_partition xlr_nor_parts[] = { + { + .name = "User FS", + .offset = 0x800000, + .size = MTDPART_SIZ_FULL, + } +}; + +/* + * Default NAND partition layout + */ +static struct mtd_partition xlr_nand_parts[] = { + { + .name = "Root Filesystem", + .offset = 64 * 64 * 2048, + .size = 432 * 64 * 2048, + }, + { + .name = "Home Filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +/* Use PHYSMAP flash for NOR */ +struct physmap_flash_data xlr_nor_data = { + .width = 2, + .parts = xlr_nor_parts, + .nr_parts = ARRAY_SIZE(xlr_nor_parts), +}; + +static struct resource xlr_nor_res[] = { + { + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device xlr_nor_dev = { + .name = "physmap-flash", + .dev = { + .platform_data = &xlr_nor_data, + }, + .num_resources = ARRAY_SIZE(xlr_nor_res), + .resource = xlr_nor_res, +}; + +const char *xlr_part_probes[] = { "cmdlinepart", NULL }; + +/* + * Use "gen_nand" driver for NAND flash + * + * There seems to be no way to store a private pointer containing + * platform specific info in gen_nand drivier. We will use a global + * struct for now, since we currently have only one NAND chip per board. + */ +struct xlr_nand_flash_priv { + int cs; + uint64_t flash_mmio; +}; + +static struct xlr_nand_flash_priv nand_priv; + +static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CLE) + nlm_write_reg(nand_priv.flash_mmio, + FLASH_NAND_CLE(nand_priv.cs), cmd); + else if (ctrl & NAND_ALE) + nlm_write_reg(nand_priv.flash_mmio, + FLASH_NAND_ALE(nand_priv.cs), cmd); +} + +struct platform_nand_data xlr_nand_data = { + .chip = { + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(xlr_nand_parts), + .chip_delay = 50, + .partitions = xlr_nand_parts, + .part_probe_types = xlr_part_probes, + }, + .ctrl = { + .cmd_ctrl = xlr_nand_ctrl, + }, +}; + +static struct resource xlr_nand_res[] = { + { + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device xlr_nand_dev = { + .name = "gen_nand", + .id = -1, + .num_resources = ARRAY_SIZE(xlr_nand_res), + .resource = xlr_nand_res, + .dev = { + .platform_data = &xlr_nand_data, + } +}; + +/* + * XLR/XLS supports upto 8 devices on its FLASH interface. The value in + * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the + * flash devices. + * Under this, each flash device has an offset and size given by the + * CSBASE_ADDR and CSBASE_MASK registers for the device. + * + * The CSBASE_ registers are expected to be setup by the bootloader. + */ +static void setup_flash_resource(uint64_t flash_mmio, + uint64_t flash_map_base, int cs, struct resource *res) +{ + u32 base, mask; + + base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); + mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); + + res->start = flash_map_base + ((unsigned long)base << 16); + res->end = res->start + (mask + 1) * 64 * 1024; +} + +static int __init xlr_flash_init(void) +{ + uint64_t gpio_mmio, flash_mmio, flash_map_base; + u32 gpio_resetcfg, flash_bar; + int cs, boot_nand, boot_nor; + + /* Flash address bits 39:24 is in bridge flash BAR */ + flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR); + flash_map_base = (flash_bar & 0xffff0000) << 8; + + gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); + flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET); + + /* Get the chip reset config */ + gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG); + + /* Check for boot flash type */ + boot_nor = boot_nand = 0; + if (nlm_chip_is_xls()) { + /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */ + if (gpio_resetcfg & (1 << 16)) + boot_nand = 1; + + /* check boot from PCMCIA, (GPIO reset reg bit 15 */ + if ((gpio_resetcfg & (1 << 15)) == 0) + boot_nor = 1; /* not set, booted from NOR */ + } else { /* XLR */ + /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */ + if ((gpio_resetcfg & (1 << 16)) == 0) + boot_nor = 1; /* not set, booted from NOR */ + } + + /* boot flash at chip select 0 */ + cs = 0; + + if (boot_nand) { + nand_priv.cs = cs; + nand_priv.flash_mmio = flash_mmio; + setup_flash_resource(flash_mmio, flash_map_base, cs, + xlr_nand_res); + + /* Initialize NAND flash at CS 0 */ + nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs), + FLASH_NAND_CSDEV_PARAM); + nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs), + FLASH_NAND_CSTIME_PARAMA); + nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs), + FLASH_NAND_CSTIME_PARAMB); + + pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res); + return platform_device_register(&xlr_nand_dev); + } + + if (boot_nor) { + setup_flash_resource(flash_mmio, flash_map_base, cs, + xlr_nor_res); + pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res); + return platform_device_register(&xlr_nor_dev); + } + return 0; +} + +arch_initcall(xlr_flash_init); -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:47:28 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2259 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2EHMmy (ORCPT ); Tue, 8 May 2012 14:42:54 +0200 Received: from [10.9.200.131] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:51 -0700 X-Server-Uuid: B730DE51-FC43-4C83-941F-F1F78A914BDD Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:42:34 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 17E879F9F7; Tue, 8 May 2012 05:42:34 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:33 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 08/14] MIPS: Netlogic: Platform changes for XLS USB Date: Tue, 8 May 2012 18:12:02 +0530 Message-ID: <1336480928-18887-9-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB413E029936035-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33207 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3658 Lines: 124 Add USB initialization code, setup resources and add USB platform driver in mips/netlogic/xlr/platform.c. Add USB support for XLR/XLS platform in Kconfig. Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 2 + arch/mips/netlogic/xlr/platform.c | 89 +++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ce30e2f..b3811dd 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -780,6 +780,8 @@ config NLM_XLR_BOARD select ZONE_DMA if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK + select USB_ARCH_HAS_OHCI if USB_SUPPORT + select USB_ARCH_HAS_EHCI if USB_SUPPORT help Support for systems based on Netlogic XLR and XLS processors. Say Y here if you have a XLR or XLS based board. diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c index eab64b4..cb0ab63 100644 --- a/arch/mips/netlogic/xlr/platform.c +++ b/arch/mips/netlogic/xlr/platform.c @@ -97,3 +97,92 @@ static int __init nlm_uart_init(void) } arch_initcall(nlm_uart_init); + +#ifdef CONFIG_USB +/* Platform USB devices, only on XLS chips */ +static u64 xls_usb_dmamask = ~(u32)0; +#define USB_PLATFORM_DEV(n, i, irq) \ + { \ + .name = n, \ + .id = i, \ + .num_resources = 2, \ + .dev = { \ + .dma_mask = &xls_usb_dmamask, \ + .coherent_dma_mask = 0xffffffff, \ + }, \ + .resource = (struct resource[]) { \ + { \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }, \ + } + +static struct platform_device xls_usb_ehci_device = + USB_PLATFORM_DEV("ehci-xls", 0, PIC_USB_IRQ); +static struct platform_device xls_usb_ohci_device_0 = + USB_PLATFORM_DEV("ohci-xls-0", 1, PIC_USB_IRQ); +static struct platform_device xls_usb_ohci_device_1 = + USB_PLATFORM_DEV("ohci-xls-1", 2, PIC_USB_IRQ); + +static struct platform_device *xls_platform_devices[] = { + &xls_usb_ehci_device, + &xls_usb_ohci_device_0, + &xls_usb_ohci_device_1, +}; + +int xls_platform_usb_init(void) +{ + uint64_t usb_mmio, gpio_mmio; + unsigned long memres; + uint32_t val; + + if (!nlm_chip_is_xls()) + return 0; + + gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); + usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_1_OFFSET); + + /* Clear Rogue Phy INTs */ + nlm_write_reg(usb_mmio, 49, 0x10000000); + /* Enable all interrupts */ + nlm_write_reg(usb_mmio, 50, 0x1f000000); + + /* Enable ports */ + nlm_write_reg(usb_mmio, 1, 0x07000500); + + val = nlm_read_reg(gpio_mmio, 21); + if (((val >> 22) & 0x01) == 0) { + pr_info("Detected USB Device mode - Not supported!\n"); + nlm_write_reg(usb_mmio, 0, 0x01000000); + return 0; + } + + pr_info("Detected USB Host mode - Adding XLS USB devices.\n"); + /* Clear reset, host mode */ + nlm_write_reg(usb_mmio, 0, 0x02000000); + + /* Memory resource for various XLS usb ports */ + usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET); + memres = CPHYSADDR((unsigned long)usb_mmio); + xls_usb_ehci_device.resource[0].start = memres; + xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1; + + memres += 0x400; + xls_usb_ohci_device_0.resource[0].start = memres; + xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1; + + memres += 0x400; + xls_usb_ohci_device_1.resource[0].start = memres; + xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1; + + return platform_add_devices(xls_platform_devices, + ARRAY_SIZE(xls_platform_devices)); +} + +arch_initcall(xls_platform_usb_init); +#endif -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:42:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:47:59 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2395 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903697Ab2EHMm7 (ORCPT ); Tue, 8 May 2012 14:42:59 +0200 Received: from [10.9.200.133] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:42:58 -0700 X-Server-Uuid: B730DE51-FC43-4C83-941F-F1F78A914BDD Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:42:02 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 6EFEA9F9F5; Tue, 8 May 2012 05:42:41 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:40 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Ganesan Ramalingam" , "Jayachandran C" Subject: [PATCH 11/14] MIPS: Netlogic: XLP PCIe controller support. Date: Tue, 8 May 2012 18:12:05 +0530 Message-ID: <1336480928-18887-12-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB583E029936084-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33208 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 14660 Lines: 454 From: Ganesan Ramalingam Adds support for the XLP on-chip PCIe controller. On XLP, the on-chip devices(including the 4 PCIe links) appear in the PCIe configuration space of the XLP as PCI devices. The changes are to initialize and register the PCIe controller, enable hardware byte swap in the PCIe IO and MEM space, and to enable PCIe interrupts. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 1 - arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 3 + arch/mips/include/asm/netlogic/xlp-hal/pcibus.h | 76 +++++++ arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 8 +- arch/mips/netlogic/xlp/nlm_hal.c | 16 ++ arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-xlp.c | 247 +++++++++++++++++++++++ 7 files changed, 349 insertions(+), 3 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h create mode 100644 arch/mips/pci/pci-xlp.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b3811dd..db465fb 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -794,7 +794,6 @@ config NLM_XLP_BOARD select SYS_HAS_CPU_XLP select SYS_SUPPORTS_SMP select HW_HAS_PCI - select SWAP_IO_SPACE select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select 64BIT_PHYS_ADDR diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h index 86cc339..ece86f1 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h @@ -36,6 +36,9 @@ #define __NLM_HAL_IOMAP_H__ #define XLP_DEFAULT_IO_BASE 0x18000000 +#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE +#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000 + #define NMI_BASE 0xbfc00000 #define XLP_IO_CLK 133333333 diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h new file mode 100644 index 0000000..66c323d --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NLM_HAL_PCIBUS_H__ +#define __NLM_HAL_PCIBUS_H__ + +/* PCIE Memory and IO regions */ +#define PCIE_MEM_BASE 0xd0000000ULL +#define PCIE_MEM_LIMIT 0xdfffffffULL +#define PCIE_IO_BASE 0x14000000ULL +#define PCIE_IO_LIMIT 0x15ffffffULL + +#define PCIE_BRIDGE_CMD 0x1 +#define PCIE_BRIDGE_MSI_CAP 0x14 +#define PCIE_BRIDGE_MSI_ADDRL 0x15 +#define PCIE_BRIDGE_MSI_ADDRH 0x16 +#define PCIE_BRIDGE_MSI_DATA 0x17 + +/* XLP Global PCIE configuration space registers */ +#define PCIE_BYTE_SWAP_MEM_BASE 0x247 +#define PCIE_BYTE_SWAP_MEM_LIM 0x248 +#define PCIE_BYTE_SWAP_IO_BASE 0x249 +#define PCIE_BYTE_SWAP_IO_LIM 0x24A +#define PCIE_MSI_STATUS 0x25A +#define PCIE_MSI_EN 0x25B +#define PCIE_INT_EN0 0x261 + +/* PCIE_MSI_EN */ +#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF + +/* PCIE_INT_EN0 */ +#define PCIE_MSI_INT_EN (1 << 9) + +#ifndef __ASSEMBLY__ + +#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_get_pcie_base(node, inst) \ + nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) +#define nlm_get_pcie_regbase(node, inst) \ + (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) + +int xlp_pcie_link_irt(int link); +#endif +#endif /* __NLM_HAL_PCIBUS_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index 1540588..dc6e98e 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -35,8 +35,12 @@ #ifndef _NLM_HAL_XLP_H #define _NLM_HAL_XLP_H -#define PIC_UART_0_IRQ 17 -#define PIC_UART_1_IRQ 18 +#define PIC_UART_0_IRQ 17 +#define PIC_UART_1_IRQ 18 +#define PIC_PCIE_LINK_0_IRQ 19 +#define PIC_PCIE_LINK_1_IRQ 20 +#define PIC_PCIE_LINK_2_IRQ 21 +#define PIC_PCIE_LINK_3_IRQ 22 #ifndef __ASSEMBLY__ diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c index 9428e71..3a4a172 100644 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ b/arch/mips/netlogic/xlp/nlm_hal.c @@ -69,6 +69,14 @@ int nlm_irq_to_irt(int irq) return PIC_IRT_UART_0_INDEX; case PIC_UART_1_IRQ: return PIC_IRT_UART_1_INDEX; + case PIC_PCIE_LINK_0_IRQ: + return PIC_IRT_PCIE_LINK_0_INDEX; + case PIC_PCIE_LINK_1_IRQ: + return PIC_IRT_PCIE_LINK_1_INDEX; + case PIC_PCIE_LINK_2_IRQ: + return PIC_IRT_PCIE_LINK_2_INDEX; + case PIC_PCIE_LINK_3_IRQ: + return PIC_IRT_PCIE_LINK_3_INDEX; default: return -1; } @@ -81,6 +89,14 @@ int nlm_irt_to_irq(int irt) return PIC_UART_0_IRQ; case PIC_IRT_UART_1_INDEX: return PIC_UART_1_IRQ; + case PIC_IRT_PCIE_LINK_0_INDEX: + return PIC_PCIE_LINK_0_IRQ; + case PIC_IRT_PCIE_LINK_1_INDEX: + return PIC_PCIE_LINK_1_IRQ; + case PIC_IRT_PCIE_LINK_2_INDEX: + return PIC_PCIE_LINK_2_IRQ; + case PIC_IRT_PCIE_LINK_3_INDEX: + return PIC_PCIE_LINK_3_IRQ; default: return -1; } diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c3ac4b0..44cdf55 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o obj-$(CONFIG_CPU_XLR) += pci-xlr.o +obj-$(CONFIG_CPU_XLP) += pci-xlp.o ifdef CONFIG_PCI_MSI obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c new file mode 100644 index 0000000..3e177e9 --- /dev/null +++ b/arch/mips/pci/pci-xlp.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include + +static void *pci_config_base; + +#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) + +/* PCI ops */ +static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, + int where) +{ + u32 data; + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + data = *cfgaddr; + return data; +} + +static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, + int where, u32 data) +{ + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + *cfgaddr = data; +} + +static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + + +static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + pci_cfg_write_32bit(bus, devfn, where, data); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops nlm_pci_ops = { + .read = nlm_pcibios_read, + .write = nlm_pcibios_write +}; + +static struct resource nlm_pci_mem_resource = { + .name = "XLP PCI MEM", + .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ + .end = 0xdfffffffUL, + .flags = IORESOURCE_MEM, +}; + +static struct resource nlm_pci_io_resource = { + .name = "XLP IO MEM", + .start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */ + .end = 0x17ffffffUL, + .flags = IORESOURCE_IO, +}; + +struct pci_controller nlm_pci_controller = { + .index = 0, + .pci_ops = &nlm_pci_ops, + .mem_resource = &nlm_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &nlm_pci_io_resource, + .io_offset = 0x00000000UL, +}; + +static int get_irq_vector(const struct pci_dev *dev) +{ + /* + * For XLP PCIe, there is an IRQ per Link, find out which + * link the device is on to assign interrupts + */ + if (dev->bus->self == NULL) + return 0; + + switch (dev->bus->self->devfn) { + case 0x8: + return PIC_PCIE_LINK_0_IRQ; + case 0x9: + return PIC_PCIE_LINK_1_IRQ; + case 0xa: + return PIC_PCIE_LINK_2_IRQ; + case 0xb: + return PIC_PCIE_LINK_3_IRQ; + } + WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); + return 0; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return get_irq_vector(dev); +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static int xlp_enable_pci_bswap(void) +{ + uint64_t pciebase, sysbase; + int node, i; + u32 reg; + + /* Chip-0 so node set to 0 */ + node = 0; + sysbase = nlm_get_bridge_regbase(node); + /* + * Enable byte swap in hardware. Program each link's PCIe SWAP regions + * from the link's address ranges. + */ + for (i = 0; i < 4; i++) { + pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i)); + if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) + continue; + + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); + + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, reg); + + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); + + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg); + } + return 0; +} + +static int __init pcibios_init(void) +{ + /* Firmware assigns PCI resources */ + pci_set_flags(PCI_PROBE_ONLY); + pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); + + /* Extend IO port for memory mapped io */ + ioport_resource.start = 0; + ioport_resource.end = ~0; + + xlp_enable_pci_bswap(); + set_io_port_base(CKSEG1); + nlm_pci_controller.io_map_base = CKSEG1; + + register_pci_controller(&nlm_pci_controller); + pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource, + &nlm_pci_mem_resource); + + return 0; +} +arch_initcall(pcibios_init); -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:43:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:48:25 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2743 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903698Ab2EHMnI (ORCPT ); Tue, 8 May 2012 14:43:08 +0200 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:43:10 -0700 X-Server-Uuid: 72204117-5C29-4314-8910-60DB108979CB Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:42:06 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id BB1359F9F8; Tue, 8 May 2012 05:42:45 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:44 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 13/14] MIPS: Netlogic: Add IRQ mappings for more devices Date: Tue, 8 May 2012 18:12:07 +0530 Message-ID: <1336480928-18887-14-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB5444G1245347-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33209 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1590 Lines: 56 Add IRT to IRQ translation for the MMC and I2C IRQs. Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 3 +++ arch/mips/netlogic/xlp/nlm_hal.c | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index 3921a31..7e47209 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -47,6 +47,9 @@ #define PIC_OHCI_1_IRQ 26 #define PIC_OHCI_2_IRQ 27 #define PIC_OHCI_3_IRQ 28 +#define PIC_MMC_IRQ 29 +#define PIC_I2C_0_IRQ 30 +#define PIC_I2C_1_IRQ 31 #ifndef __ASSEMBLY__ diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c index fad2cae..6c65ac7 100644 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ b/arch/mips/netlogic/xlp/nlm_hal.c @@ -89,6 +89,12 @@ int nlm_irq_to_irt(int irq) return PIC_IRT_OHCI_2_INDEX; case PIC_OHCI_3_IRQ: return PIC_IRT_OHCI_3_INDEX; + case PIC_MMC_IRQ: + return PIC_IRT_MMC_INDEX; + case PIC_I2C_0_IRQ: + return PIC_IRT_I2C_0_INDEX; + case PIC_I2C_1_IRQ: + return PIC_IRT_I2C_1_INDEX; default: return -1; } @@ -121,6 +127,12 @@ int nlm_irt_to_irq(int irt) return PIC_OHCI_2_IRQ; case PIC_IRT_OHCI_3_INDEX: return PIC_OHCI_3_IRQ; + case PIC_IRT_MMC_INDEX: + return PIC_MMC_IRQ; + case PIC_IRT_I2C_0_INDEX: + return PIC_I2C_0_IRQ; + case PIC_IRT_I2C_1_INDEX: + return PIC_I2C_1_IRQ; default: return -1; } -- 1.7.9.5 From jayachandranc@netlogicmicro.com Tue May 8 14:43:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:48:48 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2742 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903699Ab2EHMnI (ORCPT ); Tue, 8 May 2012 14:43:08 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 08 May 2012 05:43:12 -0700 X-Server-Uuid: 72204117-5C29-4314-8910-60DB108979CB Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 May 2012 05:42:48 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 133099F9F6; Tue, 8 May 2012 05:42:48 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Tue, 8 May 2012 05:42:47 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Ganesan Ramalingam" , "Jayachandran C" Subject: [PATCH 14/14] MIPS: Netlogic: Add XLP SoC devices in FDT Date: Tue, 8 May 2012 18:12:08 +0530 Message-ID: <1336480928-18887-15-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1336480928-18887-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 63B7CB6A44G1245370-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33210 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1215 Lines: 47 From: Ganesan Ramalingam Probe and add devices on SoC "simple-bus" on startup. This will in turn add devices like I2C controller that are specified in the device tree under 'soc'. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/netlogic/xlp/setup.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index b3df7c2..3dec9f2 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -41,6 +41,8 @@ #include #include +#include +#include #include #include @@ -109,3 +111,17 @@ void __init prom_init(void) register_smp_ops(&nlm_smp_ops); #endif } + +static struct of_device_id __initdata xlp_ids[] = { + { .compatible = "simple-bus", }, + {}, +}; + +int __init xlp8xx_ds_publish_devices(void) +{ + if (!of_have_populated_dt()) + return 0; + return of_platform_bus_probe(NULL, xlp_ids, NULL); +} + +device_initcall(xlp8xx_ds_publish_devices); -- 1.7.9.5 From jonas.gorski@gmail.com Tue May 8 14:49:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 14:49:29 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:56925 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903688Ab2EHMtI convert rfc822-to-8bit (ORCPT ); Tue, 8 May 2012 14:49:08 +0200 Received: by obqv19 with SMTP id v19so12115049obq.36 for ; Tue, 08 May 2012 05:49:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=JBdnFaMOQXJTYZuafggE4pGVx1jyN+LE2CLLCXVebIg=; b=hXP3KDMUecgiAZtWd5mefYFnq/P5Pbzfy9oicFfBaW5nAEc3gR/cVOTwlNHcIbow/3 Lo1Y9wsz1iMgQPMDQZXKh/3S5RrNBRyQIAyH1kBz76xvk3Qo9CH9ezDyQ0f1RHOipjRB U4rHfYzFpoChKk7qSH1WacEO7SwEL9tDbnZR50ywjMMkOtPbmZGVQUj0lJECXLBIBLFx d/po5Ed5IDtkTPq6CYUWtOw0D1L8aSvOuCezdQfjsKuZCr2t6O17Poak46214VDj2eAX FpMMb65ZGYS9f/sMzoH/sllg8v3C39TJaldDOwFrUWeuXkuSw6vianpngzXJkSGvKvDG Gv2Q== Received: by 10.182.119.101 with SMTP id kt5mr26912112obb.70.1336481342076; Tue, 08 May 2012 05:49:02 -0700 (PDT) MIME-Version: 1.0 Received: by 10.76.169.138 with HTTP; Tue, 8 May 2012 05:48:41 -0700 (PDT) In-Reply-To: <1336472347-25822-1-git-send-email-dedekind1@gmail.com> References: <1336472347-25822-1-git-send-email-dedekind1@gmail.com> From: Jonas Gorski Date: Tue, 8 May 2012 14:48:41 +0200 Message-ID: Subject: Re: [PATCH] mips: bcm63xx: fix compilation problems To: Artem Bityutskiy Cc: Ralf Baechle , MIPS Mailing List , Linux Kernel Maling List Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 33211 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1666 Lines: 32 Hi Artem, On 8 May 2012 12:19, Artem Bityutskiy wrote: > From: Artem Bityutskiy > > I get the following build error when I am compiling the MTD gpio-nand driver > for bcm63xx: > > In file included from arch/mips/include/asm/mach-bcm63xx/gpio.h:4:0, >                 from arch/mips/include/asm/gpio.h:4, >                 from include/linux/gpio.h:36, >                 from drivers/mtd/maps/gpio-addr-flash.c:16: > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h: In function 'bcm63xx_gpio_count': > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:10:2: error: implicit declaration of function 'bcm63xx_get_cpu_id' [-Werror=implicit-function-declaration] > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: error: 'BCM6358_CPU_ID' undeclared (first use in this function) > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: note: each undeclared identifier is reported only once for each function it appears in > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:13:7: error: 'BCM6338_CPU_ID' undeclared (first use in this function) > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:15:7: error: 'BCM6345_CPU_ID' undeclared (first use in this function) > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:17:7: error: 'BCM6368_CPU_ID' undeclared (first use in this function) > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:19:7: error: 'BCM6348_CPU_ID' undeclared (first use in this function) > > (snip) I already submitted almost the same patch ~3 months ago: http://patchwork.linux-mips.org/patch/3351/ > This patch sloves the problem. "sloves"? ;p Jonas From linus.walleij@linaro.org Tue May 8 15:21:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 15:21:47 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:41979 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903636Ab2EHNVj convert rfc822-to-8bit (ORCPT ); Tue, 8 May 2012 15:21:39 +0200 Received: by yenr9 with SMTP id r9so3233628yen.36 for ; Tue, 08 May 2012 06:21:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding:x-gm-message-state; bh=DErMd9HjGuxGJnUUQ4UfLaCRGoJ/rEk1o+Fx33hzhyU=; b=QR3aTBtLUou4OP+wRNxcaZj/gPZM9NgQpFnGwqCuQPt2XDZxQ848KLggkGewCRsDEa zUKEkLtrG25jyBJPHYFN6iJtjaaK0wCs2Z6pSNySv6T56w+X7JvY92M0HreHgAJD2O/2 lZSGxOp8pcHqdA314r2ZJkYaY+HfFEBWH4kNYypMDkd3cew6yUxs4Od8Qpy4We82nU1u i4VhDZ3pV/CazVl9k/0OUV0/QN0ZHg0KA/5CHSNPnyYf9DL+eDXTi+/gxvBEobdkhyFL DbsatqGeGFe1z178YjAmga8X4sv30YyphiQIvlWhZ7rKO0ZzrRXE819Qone1yw/0V2Vj wPrQ== MIME-Version: 1.0 Received: by 10.236.192.198 with SMTP id i46mr24441971yhn.22.1336483293235; Tue, 08 May 2012 06:21:33 -0700 (PDT) Received: by 10.236.115.164 with HTTP; Tue, 8 May 2012 06:21:33 -0700 (PDT) In-Reply-To: <1336133919-26525-4-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-4-git-send-email-blogic@openwrt.org> Date: Tue, 8 May 2012 15:21:33 +0200 Message-ID: Subject: Re: [PATCH 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support From: Linus Walleij To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Stephen Warren Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-Gm-Message-State: ALoCoQlo6rNUZP2XwSC+/BUNOatPoqE5+hoeQWCXWXeHFK/IRsTvaRzUlQ832AnfBul4cVyAHqGh X-archive-position: 33212 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linus.walleij@linaro.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8542 Lines: 303 On Fri, May 4, 2012 at 2:18 PM, John Crispin wrote: > Implement support for pinctrl on lantiq/xway socs. The IO core found on these > socs has the registers for pinctrl, pinconf and gpio mixed up in the same > register range. As the gpio_chip handling is only a few lines, the driver also > implements the gpio functionality. This obseletes the old gpio driver that was > located in the arch/ folder. > > Signed-off-by: John Crispin > Cc: devicetree-discuss@lists.ozlabs.org > Cc: Linus Walleij > Cc: Stephen Warren Overall this is looking very good and a positive development for these SoCs. Nitpicking below. > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -216,6 +216,7 @@ config MACH_JZ4740 >  config LANTIQ >        bool "Lantiq based platforms" >        select DMA_NONCOHERENT > +       select PINCTRL Shouldn't this be: select PINCTRL select PINCTRL_LANTIQ ? > diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig > index 9485fe5..b86d942 100644 > --- a/arch/mips/lantiq/Kconfig > +++ b/arch/mips/lantiq/Kconfig > @@ -2,6 +2,7 @@ if LANTIQ > >  config SOC_TYPE_XWAY >        bool > +       select PINCTRL_XWAY >        default n OK... > -obj-y := prom.o pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o dma.o > +obj-y := prom.o pmu.o ebu.o reset.o gpio_stp.o gpio_ebu.o dma.o Yeah good riddance :-) > diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig > index f73a5ea..a19bac96 100644 > --- a/drivers/pinctrl/Kconfig > +++ b/drivers/pinctrl/Kconfig > @@ -30,6 +30,11 @@ config PINCTRL_PXA3xx >        bool >        select PINMUX > > +config PINCTRL_LANTIQ > +       bool > +       select PINMUX > +       select PINCONF depends on LANTIQ ? I don't think anyone else is going to want to compile this. > + >  config PINCTRL_MMP2 >        bool "MMP2 pin controller driver" >        depends on ARCH_MMP > @@ -83,6 +88,10 @@ config PINCTRL_COH901 >          COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 >          ports of 8 GPIO pins each. > > +config PINCTRL_XWAY > +       bool > +       select PINCTRL_LANTIQ Shouldn't this be: depends on SOC_TYPE_XWAY depends on PINCTRL_LANTIQ ? So LANTIQ selects it's pinctrl driver, the the xway SoC selects its driver and they both are dependent on their respective system. > diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h > +#define ARRAY_AND_SIZE(x)      (x), ARRAY_SIZE(x) Hm if we redefine this I start to wonder if this should go into No big deal, we can alsway refactor later. > +#define LTQ_PINCONF_PACK(_param_, _arg_)       ((_param_) << 16 | (_arg_)) > +#define LTQ_PINCONF_UNPACK_PARAM(_conf_)       ((_conf_) >> 16) > +#define LTQ_PINCONF_UNPACK_ARG(_conf_)         ((_conf_) & 0xffff) No need to add _underscores_ around the macro parameters? I've not seen any coding convention requiring this. > +struct ltq_pinmux_info { > +       struct device *dev; > +       struct pinctrl_dev *pctrl; > + > +       /* we need to manage up to 5 padcontrolers */ controllers > +       void __iomem *membase[5]; > + > +       /* the handler for the subsystem */ > +       struct pinctrl_desc *desc; It's a descriptor not a handler. > +       /* we expose our pads to the subsystem */ > +       struct pinctrl_pin_desc *pads; > + > +       /* the number of pads. this varies between socs */ > +       unsigned int num_gpio; Why not call it num_pads, atleast use the same name for the array and the count. > +       /* these are our multifunction pins */ > +       const struct ltq_mfp_pin *mfp; > +       unsigned int num_mfp; > + > +       /* a number of multifunction pins can be grouped together */ > +       const struct ltq_pin_group *grps; > +       unsigned int num_grps; > + > +       /* a mapping between function string and id */ > +       const struct ltq_pmx_func *funcs; > +       unsigned int num_funcs; > + > +       /* the pinconf options that we are able to read from the DT */ > +       const struct ltq_cfg_param *params; > +       unsigned int num_params; > + > +       /* soc specific callback used to apply muxing */ > +       int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux); > +}; > > +enum ltq_pin_list { > +       GPIO0 = 0, > +       GPIO1, Wait, this enum is called something ending with _list but it's not a list, it's a pin. The enum is like a type, so should define the basic unit we're dealing with, not a collection of such units, so rename it "ltq_pin" simply. You could also consider using: #define GPIO0 0 #define GPIO1 1 etc like some other drivers do. (Your pick.) > diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c > +/* macros to help us access the registers */ > +#define gpio_getbit(m, r, p)   (!!(ltq_r32(m + r) & (1 << p))) > +#define gpio_setbit(m, r, p)   ltq_w32_mask(0, (1 << p), m + r) > +#define gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r) So what makes this arch so fantastic that it needs its own read/write functions? (Just curious...) You could replace (1 << p) with BIT(p) by using > +       {"pci",         ARRAY_AND_SIZE(xrx_pci_grps)}, > +       {"ebu",         ARRAY_AND_SIZE(xrx_ebu_grps)}, > +}; > + > + > + > + > + > + You can never get enough whitespace :-) Please trim it down... > +/* ---------  pinconf related code --------- */ > +static int xway_pinconf_group_get(struct pinctrl_dev *pctldev, > +                               unsigned group, > +                               unsigned long *config) > +{ > +       return -ENOTSUPP; > +} > + > +static int xway_pinconf_group_set(struct pinctrl_dev *pctldev, > +                               unsigned group, > +                               unsigned long config) > +{ > +       return -ENOTSUPP; > +} Just don't define these function pointers and leave callbacks as NULL. The pinctrl core should handle this and if it doesn't, patch the core in pinconf.c. > +static void xway_pinconf_dbg_show(struct pinctrl_dev *pctldev, > +                                       struct seq_file *s, unsigned offset) > +{ > +} > + > +static void xway_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, > +                                       struct seq_file *s, unsigned selector) > +{ > +} Just don't define them if you don't use them, leave pointers as NULL. These are however good for verbose pretty-printing the pins/groups hardware state. > +static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, > +                               int pin, int mux) > +{ > +       struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); > +       int port = PORT(pin); > + > +       if (mux & 0x1) > +               gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); > +       else > +               gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); > + > +       if ((port == 3) && (mux & 0x2)) > +               gpio_setbit(info->membase[0], GPIO3_ALT1, PORT_PIN(pin)); > +       else if (mux & 0x2) > +               gpio_setbit(info->membase[0], GPIO_ALT1(pin), PORT_PIN(pin)); > +       else if (port == 3) > +               gpio_clearbit(info->membase[0], GPIO3_ALT1, PORT_PIN(pin)); > +       else > +               gpio_clearbit(info->membase[0], GPIO_ALT1(pin), PORT_PIN(pin)); > + > +       return 0; > +} Please introduce some #defines for the magic numbers used above: 0x1, 3, 0x2, 3, etc so we can easily figure out what's going on. > +static struct ltq_pinmux_info xway_info = { > +       .mfp            = xway_mfp, > +       .desc           = &xway_pctrl_desc, > +       .apply_mux      = xway_mux_apply, > +       .params         = xway_cfg_params, > +       .num_params     = ARRAY_SIZE(xway_cfg_params), > +}; > + > + > + > + Whitespacey... > +/* ---------  gpio_chip related code --------- */ > + > +int gpio_to_irq(unsigned int gpio) > +{ > +       return -EINVAL; > +} > +EXPORT_SYMBOL(gpio_to_irq); > + > +int irq_to_gpio(unsigned int gpio) > +{ > +       return -EINVAL; > +} > +EXPORT_SYMBOL(irq_to_gpio); Can't you just leave them undefined? > +static struct gpio_chip xway_chip = { > +       .label = "gpio-xway", > +       .direction_input = xway_gpio_dir_in, > +       .direction_output = xway_gpio_dir_out, > +       .get = xway_gpio_get, > +       .set = xway_gpio_set, > +       .request = xway_gpio_req, > +       .free = xway_gpio_free, > +       .base = 0, > +}; > + > + > + > + Whitespace. Yours, Linus Walleij From blogic@openwrt.org Tue May 8 16:13:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 16:13:50 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:41456 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903633Ab2EHONk (ORCPT ); Tue, 8 May 2012 16:13:40 +0200 Message-ID: <4FA929BA.9020702@openwrt.org> Date: Tue, 08 May 2012 16:12:10 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: Linus Walleij CC: linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Ralf Baechle Subject: Re: [PATCH 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-4-git-send-email-blogic@openwrt.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33213 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1964 Lines: 65 Hi Linus, Thanks. I will fold your comments with Stephen's into a V2 and resend it. > Shouldn't this be: > > depends on SOC_TYPE_XWAY > depends on PINCTRL_LANTIQ > > ? > > So LANTIQ selects it's pinctrl driver, the the xway SoC > selects its driver and they both are dependent on their > respective system. > The whole select/depends part is broken. I will clean this up properly >> diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h >> +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) I was actually considering to drop this. Having a "," inside a macro is a bit ugly. It leads to the calling code invoking the function with N-1 parameters, although the function takes N parameters. I find this a bit confusing/inconsistent. >> +/* macros to help us access the registers */ >> +#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) >> +#define gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) >> +#define gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r) > So what makes this arch so fantastic that it needs its own read/write functions? > (Just curious...) Nothing. Its a legacy macro from a few years ago when I first added lantiq support inside openwrt. I personally like the macro. I use it wherever I access lantiq registers. When accessing generic memory ranges, as in the nand driver, I use writeb() and co. Matter of taste really. I would prefer to keep it this way if there are no guidelines against it. >> +/* --------- gpio_chip related code --------- */ >> + >> +int gpio_to_irq(unsigned int gpio) >> +{ >> + return -EINVAL; >> +} >> +EXPORT_SYMBOL(gpio_to_irq); >> + >> +int irq_to_gpio(unsigned int gpio) >> +{ >> + return -EINVAL; >> +} >> +EXPORT_SYMBOL(irq_to_gpio); > Can't you just leave them undefined? I just checked how ARM does it. They use arch/arm/include/asm/gpio.h Let me talk to Ralf about this and make a MIPS version of said header file. Thanks, John From swarren@wwwdotorg.org Tue May 8 17:28:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 17:28:36 +0200 (CEST) Received: from avon.wwwdotorg.org ([70.85.31.133]:45008 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903633Ab2EHP2a (ORCPT ); Tue, 8 May 2012 17:28:30 +0200 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 1F5D16412; Tue, 8 May 2012 09:30:04 -0600 (MDT) Received: from [10.20.204.51] (searspoint.nvidia.com [216.228.112.21]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 89E32E461C; Tue, 8 May 2012 09:28:25 -0600 (MDT) Message-ID: <4FA93B97.4070406@wwwdotorg.org> Date: Tue, 08 May 2012 09:28:23 -0600 From: Stephen Warren User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:12.0) Gecko/20120430 Thunderbird/12.0.1 MIME-Version: 1.0 To: Linus Walleij CC: John Crispin , Ralf Baechle , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org Subject: Re: [PATCH 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-4-git-send-email-blogic@openwrt.org> In-Reply-To: X-Enigmail-Version: 1.5pre Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean X-archive-position: 33214 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: swarren@wwwdotorg.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2066 Lines: 64 On 05/08/2012 07:21 AM, Linus Walleij wrote: > On Fri, May 4, 2012 at 2:18 PM, John Crispin wrote: > >> Implement support for pinctrl on lantiq/xway socs. The IO core found on these >> socs has the registers for pinctrl, pinconf and gpio mixed up in the same >> register range. As the gpio_chip handling is only a few lines, the driver also >> implements the gpio functionality. This obseletes the old gpio driver that was >> located in the arch/ folder. ... >> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig >> index f73a5ea..a19bac96 100644 >> --- a/drivers/pinctrl/Kconfig >> +++ b/drivers/pinctrl/Kconfig >> @@ -30,6 +30,11 @@ config PINCTRL_PXA3xx >> bool >> select PINMUX >> >> +config PINCTRL_LANTIQ >> + bool >> + select PINMUX >> + select PINCONF > > depends on LANTIQ > > ? > > I don't think anyone else is going to want to compile > this. This Kconfig option is selected by the ARCH Kconfig, so only selected at the right time. The user won't get prompted for it since there's no string after "bool". I think this is OK. Tegra's pinctrl Kconfig option doesn't have any "depends ARCH_TEGRA" here either, although I note that many other pinctrl drivers do. >> config PINCTRL_MMP2 >> bool "MMP2 pin controller driver" >> depends on ARCH_MMP >> @@ -83,6 +88,10 @@ config PINCTRL_COH901 >> COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 >> ports of 8 GPIO pins each. >> >> +config PINCTRL_XWAY >> + bool >> + select PINCTRL_LANTIQ > > Shouldn't this be: > > depends on SOC_TYPE_XWAY Maybe, but see comments above. > depends on PINCTRL_LANTIQ Selecting PINCTRL_LANTIQ seems more appropriate; the ARCH Kconfig just selects PINCTRL_XWAY when appropriate, and that then selects anything it depends on. (IIRC, the driver for SOC_TYPE_XWAY uses the driver for LANTIQ, not the other way around?) > So LANTIQ selects it's pinctrl driver, the the xway SoC > selects its driver and they both are dependent on their > respective system. From john@phrozen.org Tue May 8 17:41:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 17:41:16 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:59394 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903633Ab2EHPlJ (ORCPT ); Tue, 8 May 2012 17:41:09 +0200 Message-ID: <4FA93E37.70305@phrozen.org> Date: Tue, 08 May 2012 17:39:35 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: Stephen Warren CC: Linus Walleij , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Ralf Baechle Subject: Re: [PATCH 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-4-git-send-email-blogic@openwrt.org> <4FA93B97.4070406@wwwdotorg.org> In-Reply-To: <4FA93B97.4070406@wwwdotorg.org> X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33215 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1214 Lines: 39 >> I don't think anyone else is going to want to compile >> this. > > This Kconfig option is selected by the ARCH Kconfig, so only selected at > the right time. The user won't get prompted for it since there's no > string after "bool". I think this is OK. Tegra's pinctrl Kconfig option > doesn't have any "depends ARCH_TEGRA" here either, although I note that > many other pinctrl drivers do. Hi, I guess it makes it more apparent, that the symbol is specific to a arch/soc. Tegra is a well known SoC, so its easy to figure out what the codes purpose is. Other files might not be that easy to guess. For the Lantiq SoC to function normally we need to always load these drivers. PINTCTRL_LANTIQ has some generic functions and PINTCTRL_LANTIQ_XWAY holds the code specific to the XWAY SoC. (i have a patch in the local queue to add FALCON SoC support, giving PINTCTRL_LANTIQ 2 users) How about we do the following. config LANTIQ select PINCTRL config PINCTRL_LANTIQ def_bool y depends on LANTIQ config PINCTRL_LANTIQ_XWAY def_bool y depends on SOC_TYPE_XWAY This would auto select the right symbols, have all the dependency logic in 1 place and reduce the size of arch/mips/lantiq/Kconfig Thanks, John From swarren@wwwdotorg.org Tue May 8 17:51:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 17:51:30 +0200 (CEST) Received: from avon.wwwdotorg.org ([70.85.31.133]:38330 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903633Ab2EHPvW (ORCPT ); Tue, 8 May 2012 17:51:22 +0200 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id D1E636412; Tue, 8 May 2012 09:52:57 -0600 (MDT) Received: from [10.20.204.51] (searspoint.nvidia.com [216.228.112.21]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id CBBBBE461C; Tue, 8 May 2012 09:51:19 -0600 (MDT) Message-ID: <4FA940F3.4090008@wwwdotorg.org> Date: Tue, 08 May 2012 09:51:15 -0600 From: Stephen Warren User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:12.0) Gecko/20120430 Thunderbird/12.0.1 MIME-Version: 1.0 To: John Crispin CC: Linus Walleij , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Ralf Baechle Subject: Re: [PATCH 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-4-git-send-email-blogic@openwrt.org> <4FA93B97.4070406@wwwdotorg.org> <4FA93E37.70305@phrozen.org> In-Reply-To: <4FA93E37.70305@phrozen.org> X-Enigmail-Version: 1.5pre Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean X-archive-position: 33216 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: swarren@wwwdotorg.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1552 Lines: 42 On 05/08/2012 09:39 AM, John Crispin wrote: >>> I don't think anyone else is going to want to compile >>> this. >> >> This Kconfig option is selected by the ARCH Kconfig, so only selected at >> the right time. The user won't get prompted for it since there's no >> string after "bool". I think this is OK. Tegra's pinctrl Kconfig option >> doesn't have any "depends ARCH_TEGRA" here either, although I note that >> many other pinctrl drivers do. > > Hi, > > I guess it makes it more apparent, that the symbol is specific to a > arch/soc. Tegra is a well known SoC, so its easy to figure out what the > codes purpose is. Other files might not be that easy to guess. > > For the Lantiq SoC to function normally we need to always load these > drivers. PINTCTRL_LANTIQ has some generic functions and > PINTCTRL_LANTIQ_XWAY holds the code specific to the XWAY SoC. (i have a > patch in the local queue to add FALCON SoC support, giving > PINTCTRL_LANTIQ 2 users) > > How about we do the following. > > config LANTIQ > select PINCTRL > > config PINCTRL_LANTIQ > def_bool y > depends on LANTIQ > > config PINCTRL_LANTIQ_XWAY > def_bool y > depends on SOC_TYPE_XWAY > > This would auto select the right symbols, have all the dependency logic > in 1 place and reduce the size of arch/mips/lantiq/Kconfig Is it useful to build a kernel for XWAY without pinctrl, once the driver is there? That's the main difference between arch/mips/lantiq/Kconfig selecting PINCTRL_LANTIQ_XWAY vs that being a def_bool, and hence allowing the user to deselect it. From john@phrozen.org Tue May 8 18:01:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 18:01:09 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:38162 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903633Ab2EHQBD (ORCPT ); Tue, 8 May 2012 18:01:03 +0200 Message-ID: <4FA942E5.20906@phrozen.org> Date: Tue, 08 May 2012 17:59:33 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: Stephen Warren CC: Linus Walleij , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Ralf Baechle Subject: Re: [PATCH 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-4-git-send-email-blogic@openwrt.org> <4FA93B97.4070406@wwwdotorg.org> <4FA93E37.70305@phrozen.org> <4FA940F3.4090008@wwwdotorg.org> In-Reply-To: <4FA940F3.4090008@wwwdotorg.org> X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33217 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 759 Lines: 28 >> How about we do the following. >> >> config LANTIQ >> select PINCTRL >> >> config PINCTRL_LANTIQ >> def_bool y >> depends on LANTIQ >> >> config PINCTRL_LANTIQ_XWAY >> def_bool y >> depends on SOC_TYPE_XWAY >> >> This would auto select the right symbols, have all the dependency logic >> in 1 place and reduce the size of arch/mips/lantiq/Kconfig > > Is it useful to build a kernel for XWAY without pinctrl, once the driver > is there? That's the main difference between arch/mips/lantiq/Kconfig > selecting PINCTRL_LANTIQ_XWAY vs that being a def_bool, and hence > allowing the user to deselect it. > it would not make sense to build an image without. config LANTIQ and config SOC_TYPE_XWAY should explicitly select the symbols that they need. From SSA.Grosswangen@edulu.ch Tue May 8 19:32:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 19:32:15 +0200 (CEST) Received: from mx2.lu.ch ([194.40.144.252]:56402 "EHLO mx2.lu.ch" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903640Ab2EHRcJ convert rfc822-to-8bit (ORCPT ); Tue, 8 May 2012 19:32:09 +0200 From: Grosswangen SSA Subject: Sehr geehrte Webmail User Thread-Topic: Sehr geehrte Webmail User Thread-Index: Ac0tQGcEO0IT+WrERv6Fh2aEHUN6IQ== Date: Tue, 8 May 2012 17:32:02 +0000 Message-ID: <44F059946EEC5D4FB924F0DCDACC56581C4483C6@mxm-v106.kt.lunet.ch> Accept-Language: de-CH, de-DE, en-US Content-Language: de-CH X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 To: undisclosed-recipients:; Received-SPF: none X-archive-position: 33218 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: SSA.Grosswangen@edulu.ch Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 470 Lines: 6 Sehr geehrte Webmail User, Aufgrund zu vieler Nutzung unserer Webmail-Dienst, gab es Staus auf unsere Datenbank, also unsere Web-Admin wäre Herunterfahren alle nicht verwendeten Konten, müssen Sie auf Ihr Konto als ein aktives Konto zu bestätigen, indem Sie auf diesen Link und füllen Sie die erforderlichen Informationen http://aktualisieren-sieweb-konto.webs.com/ und Ihr Konto wird automatisch als noch im Einsatz Konto verifiziert werden. Dank WEB-Administrator From grant.likely@secretlab.ca Tue May 8 19:53:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 19:53:34 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:36894 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903636Ab2EHRx0 (ORCPT ); Tue, 8 May 2012 19:53:26 +0200 Received: by dadm1 with SMTP id m1so4575093dad.36 for ; Tue, 08 May 2012 10:53:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:subject:to:cc:in-reply-to:references:date:message-id :x-gm-message-state; bh=YDG8f9yxMTq93A/2F1KIJlBNsc0Gl1MvdzmKp0eaOWE=; b=KoGq58py/IbFftupPqNEVO/oPvfJ2rSnfZULgOASQ80QoePzPswJ/iFySubRVfZi0n 9SblV79K3XzdYD+9ks5xKx2GYq99zY2gqUDt9yvxA5VHJtjPQjz38qPDfjVl7cKbfsER pvdWKWgbT+y6A+wNdRQZjASMgTbggDiLk0ioAZOsrtzsWu6X4DUfXMnovwlQ+6+kafx8 Yr7wE1teOQH5nbubJUYdyBcwhB0BwbqQPv80GbLphgr163MRxfgeHa3CuCoil4/16NHQ G8h+TjKL6sPeGzFOoEUiN7ytPzXym5tw0u5ABM9d6awW0LoT0akycj1X9Eq+CiCynk0V gMwg== Received: by 10.68.203.225 with SMTP id kt1mr41474314pbc.133.1336499599993; Tue, 08 May 2012 10:53:19 -0700 (PDT) Received: from localhost (S0106d8b37715ee14.cg.shawcable.net. [68.146.14.168]) by mx.google.com with ESMTPS id sh10sm3050222pbc.48.2012.05.08.10.53.17 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 08 May 2012 10:53:18 -0700 (PDT) Received: by localhost (Postfix, from userid 1000) id EA2113E05D0; Tue, 8 May 2012 11:53:16 -0600 (MDT) From: Grant Likely Subject: Re: [PATCH 03/14] OF: MIPS: lantiq: implement irq_domain support To: John Crispin , Ralf Baechle Cc: linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org In-Reply-To: <1336133919-26525-3-git-send-email-blogic@openwrt.org> References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-3-git-send-email-blogic@openwrt.org> Date: Tue, 08 May 2012 11:53:16 -0600 Message-Id: <20120508175316.EA2113E05D0@localhost> X-Gm-Message-State: ALoCoQk+/LUMnWS/UR9XporUWt+3Eja+p3L5+7UxCgQDIzxM08/0CuUn9xDzZZ4mERBwqKlte/Fc X-archive-position: 33219 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8595 Lines: 258 On Fri, 4 May 2012 14:18:28 +0200, John Crispin wrote: > Add support for irq_domain on lantiq socs. The conversion is straight forward > as the ICU found inside the socs allows the usage of irq_domain_add_linear. > > Signed-off-by: John Crispin > Cc: devicetree-discuss@lists.ozlabs.org > --- > This patch is part of a series moving the mips/lantiq target to OF and clkdev > support. The patch, once Acked, should go upstream via Ralf's MIPS tree. Yes, this looks like the right direction, but there is a pretty major bug that needs to be delt with. All of the irq ops need are still using hardcoded (d->irq - INT_NUM_IRQ0) calculations to figure out the irq number, but that doesn't work with the linear mapping. The only reason it's probably working right now is that the linear mapping uses a 'hint' value to try and make the irq and the hwirq the same number, but the hint feature is going to be removed soon. All of the references to d->irq - INT_NUM_IRQ0 need to be replaced with d->hwirq which the irq_domain manages for you. You should probably also inspect the ltq_{startup,shutdown}_eiu_irq functions to make sure they're also doing the right thing. I could also complain about some cosmetic ugliness in the map function, but that really isn't something I'm going to get upset over. g. > > arch/mips/lantiq/irq.c | 120 +++++++++++++++++++++++++++--------------------- > 1 files changed, 68 insertions(+), 52 deletions(-) > > diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c > index d227be1..170e6cb 100644 > --- a/arch/mips/lantiq/irq.c > +++ b/arch/mips/lantiq/irq.c > @@ -9,6 +9,11 @@ > > #include > #include > +#include > +#include > +#include > +#include > +#include > > #include > #include > @@ -16,7 +21,7 @@ > #include > #include > > -/* register definitions */ > +/* register definitions - internal irqs */ > #define LTQ_ICU_IM0_ISR 0x0000 > #define LTQ_ICU_IM0_IER 0x0008 > #define LTQ_ICU_IM0_IOSR 0x0010 > @@ -25,6 +30,7 @@ > #define LTQ_ICU_IM1_ISR 0x0028 > #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) > > +/* register definitions - external irqs */ > #define LTQ_EIU_EXIN_C 0x0000 > #define LTQ_EIU_EXIN_INIC 0x0004 > #define LTQ_EIU_EXIN_INEN 0x000C > @@ -37,13 +43,13 @@ > #define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1) > #define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2) > #define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30) > - > #define MAX_EIU 6 > > /* the performance counter */ > #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) > > -/* irqs generated by device attached to the EBU need to be acked in > +/* > + * irqs generated by devices attached to the EBU need to be acked in > * a special manner > */ > #define LTQ_ICU_EBU_IRQ 22 > @@ -71,20 +77,6 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = { > LTQ_EIU_IR5, > }; > > -static struct resource ltq_icu_resource = { > - .name = "icu", > - .start = LTQ_ICU_BASE_ADDR, > - .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1, > - .flags = IORESOURCE_MEM, > -}; > - > -static struct resource ltq_eiu_resource = { > - .name = "eiu", > - .start = LTQ_EIU_BASE_ADDR, > - .end = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1, > - .flags = IORESOURCE_MEM, > -}; > - > static void __iomem *ltq_icu_membase; > static void __iomem *ltq_eiu_membase; > > @@ -199,14 +191,15 @@ static void ltq_hw_irqdispatch(int module) > if (irq == 0) > return; > > - /* silicon bug causes only the msb set to 1 to be valid. all > + /* > + * silicon bug causes only the msb set to 1 to be valid. all > * other bits might be bogus > */ > irq = __fls(irq); > do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); > > /* if this is a EBU irq, we need to ack it or get a deadlock */ > - if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) > + if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) > ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, > LTQ_EBU_PCC_ISTAT); > } > @@ -290,38 +283,62 @@ out: > return; > } > > +static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) > +{ > + if (((irq == LTQ_EIU_IR0) || (irq == LTQ_EIU_IR1) || > + (irq == LTQ_EIU_IR2)) && ltq_eiu_membase) > + irq_set_chip_and_handler(irq, <q_eiu_type, handle_level_irq); > + /* EIU3-5 only exist on ar9 and vr9 */ > + else if (((irq == LTQ_EIU_IR3) || (irq == LTQ_EIU_IR4) || > + (irq == LTQ_EIU_IR5)) && > + (of_machine_is_compatible("lantiq,ar9") || > + of_machine_is_compatible("lantiq,vr9")) && > + ltq_eiu_membase) > + irq_set_chip_and_handler(irq, <q_eiu_type, handle_level_irq); > + else > + irq_set_chip_and_handler(irq, <q_irq_type, handle_level_irq); > + > + return 0; > +} > + > +static const struct irq_domain_ops irq_domain_ops = { > + .xlate = irq_domain_xlate_onetwocell, > + .map = icu_map, > +}; > + > static struct irqaction cascade = { > .handler = no_action, > .name = "cascade", > }; > > -void __init arch_init_irq(void) > +int __init icu_of_init(struct device_node *node, struct device_node *parent) > { > + struct device_node *eiu_node; > + struct resource res; > int i; > > - if (insert_resource(&iomem_resource, <q_icu_resource) < 0) > - panic("Failed to insert icu memory"); > + if (of_address_to_resource(node, 0, &res)) > + panic("Failed to get icu memory range"); > > - if (request_mem_region(ltq_icu_resource.start, > - resource_size(<q_icu_resource), "icu") < 0) > - panic("Failed to request icu memory"); > + if (request_mem_region(res.start, resource_size(&res), res.name) < 0) > + pr_err("Failed to request icu memory"); > > - ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, > - resource_size(<q_icu_resource)); > + ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res)); > if (!ltq_icu_membase) > panic("Failed to remap icu memory"); > > - if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) > - panic("Failed to insert eiu memory"); > - > - if (request_mem_region(ltq_eiu_resource.start, > - resource_size(<q_eiu_resource), "eiu") < 0) > - panic("Failed to request eiu memory"); > - > - ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, > - resource_size(<q_eiu_resource)); > - if (!ltq_eiu_membase) > - panic("Failed to remap eiu memory"); > + /* the external interrupts are optional and xway only */ > + eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu"); > + if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) { > + if (request_mem_region(res.start, resource_size(&res), > + res.name) < 0) > + pr_err("Failed to request eiu memory"); > + > + ltq_eiu_membase = ioremap_nocache(res.start, > + resource_size(&res)); > + if (!ltq_eiu_membase) > + panic("Failed to remap eiu memory"); > + } > > /* turn off all irqs by default */ > for (i = 0; i < 5; i++) { > @@ -346,20 +363,8 @@ void __init arch_init_irq(void) > set_vi_handler(7, ltq_hw5_irqdispatch); > } > > - for (i = INT_NUM_IRQ0; > - i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) > - if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || > - (i == LTQ_EIU_IR2)) > - irq_set_chip_and_handler(i, <q_eiu_type, > - handle_level_irq); > - /* EIU3-5 only exist on ar9 and vr9 */ > - else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) || > - (i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9())) > - irq_set_chip_and_handler(i, <q_eiu_type, > - handle_level_irq); > - else > - irq_set_chip_and_handler(i, <q_irq_type, > - handle_level_irq); > + irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET, > + &irq_domain_ops, 0); > > #if defined(CONFIG_MIPS_MT_SMP) > if (cpu_has_vint) { > @@ -382,9 +387,20 @@ void __init arch_init_irq(void) > > /* tell oprofile which irq to use */ > cp0_perfcount_irq = LTQ_PERF_IRQ; > + return 0; > } > > unsigned int __cpuinit get_c0_compare_int(void) > { > return CP0_LEGACY_COMPARE_IRQ; > } > + > +static struct of_device_id __initdata of_irq_ids[] = { > + { .compatible = "lantiq,icu", .data = icu_of_init }, > + {}, > +}; > + > +void __init arch_init_irq(void) > +{ > + of_irq_init(of_irq_ids); > +} > -- > 1.7.9.1 > > _______________________________________________ > devicetree-discuss mailing list > devicetree-discuss@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/devicetree-discuss -- Grant Likely, B.Sc, P.Eng. Secret Lab Technologies, Ltd. From blogic@openwrt.org Tue May 8 20:07:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 20:07:09 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:38949 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903643Ab2EHSHD (ORCPT ); Tue, 8 May 2012 20:07:03 +0200 Message-ID: <4FA96068.90400@openwrt.org> Date: Tue, 08 May 2012 20:05:28 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: Grant Likely CC: Ralf Baechle , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org Subject: Re: [PATCH 03/14] OF: MIPS: lantiq: implement irq_domain support References: <1336133919-26525-1-git-send-email-blogic@openwrt.org> <1336133919-26525-3-git-send-email-blogic@openwrt.org> <20120508175316.EA2113E05D0@localhost> In-Reply-To: <20120508175316.EA2113E05D0@localhost> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33220 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 230 Lines: 9 Hi Grant, > I could also complain about some cosmetic ugliness in the map > function, but that really isn't something I'm going to get upset over. Let me clean up the map function while I am at it. Thanks for the comments John From sjhill@mips.com Tue May 8 22:38:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 May 2012 22:38:31 +0200 (CEST) Received: from dns0.mips.com ([12.201.5.70]:57786 "EHLO dns0.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903640Ab2EHUiZ convert rfc822-to-8bit (ORCPT ); Tue, 8 May 2012 22:38:25 +0200 Received: from exchdb01.mips.com (exchhub01.mips.com [192.168.36.84]) by dns0.mips.com (8.13.8/8.13.8) with ESMTP id q48KcFWA030704; Tue, 8 May 2012 13:38:16 -0700 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.01.0270.001; Tue, 8 May 2012 13:38:13 -0700 From: "Hill, Steven" To: "Maciej W. Rozycki" CC: Shinya Kuribayashi , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: RE: [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform. Thread-Topic: [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform. Thread-Index: AQHNFN5TXaIyKURn50SCHT0BxYKwcJaTtvkAgCs4fmCAAXRPAIAAJgYC Date: Tue, 8 May 2012 20:38:12 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B80114692157@exchdb03.mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-2-git-send-email-sjhill@mips.com>,<4F8386C8.9020401@renesas.com> <31E06A9FC96CEC488B43B19E2957C1B8011469208F@exchdb03.mips.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: uLjfLfQ3rFtUcXiijDWEXw== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 33221 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 288 Lines: 1 I thought the "YC" constraint was only present in CodeSourcery toolchains, correct? If so, then that levies the requirement for a vendor-specific toolchain to build a microMIPS kernel. I do not consider that palpable. If it is not CodeSourcery-specific, then I will certainly try it out. From macro@linux-mips.org Wed May 9 19:20:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 May 2012 19:20:50 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:34910 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901170Ab2EIRUm (ORCPT ); Wed, 9 May 2012 19:20:42 +0200 Date: Wed, 9 May 2012 18:20:42 +0100 (BST) From: "Maciej W. Rozycki" To: Matt Turner cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] mips: set ST0_MX flag for MDMX In-Reply-To: <1336084845-28995-1-git-send-email-mattst88@gmail.com> Message-ID: References: <1336084845-28995-1-git-send-email-mattst88@gmail.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33222 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1647 Lines: 38 Hi Matt, > As the comment in commit 3301edcb says, DSP and MDMX share the same > config flag bit. > > Without this set, MDMX instructions cause Illegal instruction errors. NAK, it's all pretty and nice, but I am afraid you're missing the point with your change. The bit has its purpose, the MDMX accumulator has to be saved and restored -- just as the DSP or the FPU context -- between task switches and the bit provides for doing that lazily (of course you can do that eagerly instead if you like). > Is MDMX implemented by anything other than some Broadcom CPUs? Is it > totally replaced by DSP? You can have both ASEs on a single processor and they serve different purposes as far as I can tell. I think NEC had an implementation as well, but it could have been an older revision than Broadcom's. > I had a terrible time finding any documentation on it (which is annoying > because Volume IV-b covering MDMX is referenced by all the MIPS64 documents.) > but finally found a copy here: www.enlight.ru/docs/cpu/risc/mips/MDMXspec.pdf That's the old spec, back from SGI days, using the COP2 opcode space. It may not have been implemented and is certainly obsolete. COP2 is available for user-defined coprocessors in the current architecture definition and MDMX instructions use different encodings (peek at libopcodes for details). > If it's dead, it's too bad because it's a pretty cool ISA. I don't think MaDMaX is dead, it's still referred to from the architecture spec as of revision 3.12 and I am fairly sure you'll be able to implement it in your processor if you get the right architecture licences. Maciej From ddaney.cavm@gmail.com Wed May 9 21:07:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 May 2012 21:07:26 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:55646 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901341Ab2EITHS (ORCPT ); Wed, 9 May 2012 21:07:18 +0200 Received: by dadm1 with SMTP id m1so774382dad.36 for ; Wed, 09 May 2012 12:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=tKiS/ELIZS0FewLFVOgftGx1NuAZJaL1cJc5X8HJq6g=; b=IJk8bphmDfq6fVGDqyo9QgAw9mf5Rer6Mtn0Q/BplYyMdrQ4FDFJrNJPYcZvOfWsDO r+rJakWr8FojFPTqLHSHahT6nz9khqw5hXW3HfDvU++Y/U2m7sHZnIcYbrLAX5tV5w42 e8QSz2iVV8+jZSNFTDOEL8nxbAFyKIjfm/VEiYBBxCdEGrjsIxhrwxxW7HCRfWZsU1fs SroEMcIrTqBBPhbveezTHZioaQToZN58mxd6yDW4IE2icnN3oAy/2HilkTaOgL2dORoT 4cBGwpX0rap93lzaOcgy/bke28yMtQVgV8aZmVAU+CBxt6GqGJ7lj+Ml5DOYRKSrv+Et mlBw== Received: by 10.68.194.230 with SMTP id hz6mr1388285pbc.128.1336590431520; Wed, 09 May 2012 12:07:11 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id rj4sm6946662pbc.30.2012.05.09.12.07.09 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 09 May 2012 12:07:10 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q49J78i4010413; Wed, 9 May 2012 12:07:08 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q49J76bB010411; Wed, 9 May 2012 12:07:06 -0700 From: David Daney To: Chris Ball , linux-mmc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, David Daney Subject: [PATCH RFC] mmc: Add host driver for OCTEON MMC controller. Date: Wed, 9 May 2012 12:07:05 -0700 Message-Id: <1336590425-10381-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 33223 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 34036 Lines: 1231 From: David Daney The OCTEON MMC controller is currently found on cn61XX and cnf71XX devices. Device parameters are configured from device tree data. Currenly supported are eMMC, MMC and SD devices. Signed-off-by: David Daney --- This patch depends on: http://www.linux-mips.org/archives/linux-mips/2012-04/msg00198.html Which isn't merged yet, so for the time being this remains an RFC. However, once Ralf merges the prerequisite, we could consider merging this one as well. .../devicetree/bindings/mmc/octeon-mmc.txt | 51 + drivers/mmc/host/Kconfig | 10 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/octeon_mmc.c | 1107 ++++++++++++++++++++ 4 files changed, 1169 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/octeon-mmc.txt create mode 100644 drivers/mmc/host/octeon_mmc.c diff --git a/Documentation/devicetree/bindings/mmc/octeon-mmc.txt b/Documentation/devicetree/bindings/mmc/octeon-mmc.txt new file mode 100644 index 0000000..86f1fe5 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/octeon-mmc.txt @@ -0,0 +1,51 @@ +* OCTEON SD/MMC Host Controller + +This controller is present on some members of the Cavium OCTEON SoC +family, provide an interface for eMMC, MMC and SD devices. There is a +single controller that may have several "slots" connected. These +slots appear as children of the main controller node. + +Required properties: +- compatible : Should be "cavium,octeon-6130-mmc" +- reg : Two entries: + 1) The base address of the MMC controller register bank. + 2) The base address of the MMC DMA engine register bank. +- interrupts : Two entries: + 1) The MMC controller interrupt line. + 2) The MMC DMA engine interrupt line. +- #address-cells : Must be <1> +- #size-cells : Must be <0> + +Required properties of child nodes: +- compatible : Should be "cavium,octeon-6130-mmc-slot". +- reg : The slot number. +- cavium,bus-max-width : The number of data lines present in the slot. +- spi-max-frequency : The maximum operating frequency of the slot. + +Optional properties of child nodes: +- cd-gpios : Specify GPIOs for card detection +- wp-gpios : Specify GPIOs for write protection +- power-gpios : Specify GPIOs for power control + +Example: + mmc@1180000002000 { + compatible = "cavium,octeon-6130-mmc"; + reg = <0x11800 0x00002000 0x0 0x100>, + <0x11800 0x00000168 0x0 0x20>; + #address-cells = <1>; + #size-cells = <0>; + /* EMM irq, DMA irq */ + interrupts = <1 19>, <0 63>; + + /* The board only has a single MMC slot */ + mmc-slot@0 { + compatible = "cavium,octeon-6130-mmc-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + /* bus width can be 1, 4 or 8 */ + cavium,bus-max-width = <8>; + cd-gpios = <&gpio 9 0>; + wp-gpios = <&gpio 10 0>; + power-gpios = <&gpio 8 0>; + }; + }; diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 2bc06e7..37de129 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -229,6 +229,16 @@ config MMC_SDHCI_S3C_DMA YMMV. +config MMC_OCTEON + tristate "Cavium OCTEON Multimedia Card Interface support" + depends on CPU_CAVIUM_OCTEON + help + This selects Cavium OCTEON Multimedia card Interface. + If you have an OCTEON board with a Multimedia Card slot, + say Y or M here. + + If unsure, say N. + config MMC_OMAP tristate "TI OMAP Multimedia Card Interface support" depends on ARCH_OMAP diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 3e7e26d..f58f49c 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o obj-$(CONFIG_MMC_WBSD) += wbsd.o obj-$(CONFIG_MMC_AU1X) += au1xmmc.o +obj-$(CONFIG_MMC_OCTEON) += octeon_mmc.o obj-$(CONFIG_MMC_OMAP) += omap.o obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o obj-$(CONFIG_MMC_AT91) += at91_mci.o diff --git a/drivers/mmc/host/octeon_mmc.c b/drivers/mmc/host/octeon_mmc.c new file mode 100644 index 0000000..cb4243d --- /dev/null +++ b/drivers/mmc/host/octeon_mmc.c @@ -0,0 +1,1107 @@ +/* + * Driver for MMC and SSD cards for Cavium OCTEON SOCs. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 Cavium Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#define DRV_NAME "octeon_mmc" +#define DRV_VERSION "1.0" + +#define OCTEON_MAX_MMC 4 + +#define OCT_MIO_NDF_DMA_CFG 0x00 +#define OCT_MIO_NDF_DMA_INT 0x08 +#define OCT_MIO_NDF_DMA_INT_EN 0x10 + +#define OCT_MIO_EMM_CFG 0x00 +#define OCT_MIO_EMM_SWITCH 0x48 +#define OCT_MIO_EMM_DMA 0x50 +#define OCT_MIO_EMM_CMD 0x58 +#define OCT_MIO_EMM_RSP_STS 0x60 +#define OCT_MIO_EMM_RSP_LO 0x68 +#define OCT_MIO_EMM_RSP_HI 0x70 +#define OCT_MIO_EMM_INT 0x78 +#define OCT_MIO_EMM_INT_EN 0x80 +#define OCT_MIO_EMM_WDOG 0x88 +#define OCT_MIO_EMM_STS_MASK 0x98 +#define OCT_MIO_EMM_RCA 0xa0 +#define OCT_MIO_EMM_BUF_IDX 0xe0 +#define OCT_MIO_EMM_BUF_DAT 0xe8 + +struct octeon_mmc_host { + spinlock_t lock; + u64 base; + u64 ndf_base; + u64 last_emm_switch; + + struct mmc_request *current_req; + struct sg_mapping_iter smi; + int sg_idx; + bool dma_active; + + struct semaphore mmc_serializer; + + struct platform_device *pdev; + + struct octeon_mmc_slot *slot[OCTEON_MAX_MMC]; +}; + +struct octeon_mmc_slot { + struct mmc_host *mmc; + struct octeon_mmc_host *host; + + unsigned int clock; + unsigned int sclock; + + int bus_width; + int bus_id; + int ro_gpio; + int cd_gpio; + int power_gpio; + bool cd_gpio_active_low; + bool ro_gpio_active_low; + bool power_gpio_active_low; +}; + +struct octeon_mmc_cr_type { + u8 ctype; + u8 rtype; +}; + +/* + * The OCTEON MMC host hardware assumes that all commands have fixed + * command and response types. These are correct if MMC devices are + * being used. However, non-MMC devices like SD use command and + * response types that are unexpected by the host hardware. + * + * The command and response types can be overridden by supplying an + * XOR value that is applied to the type. We calculate the XOR value + * from the values in this table and the flags passed from the MMC + * core. + */ +static struct octeon_mmc_cr_type octeon_mmc_cr_types[] = { + {0, 0}, /* CMD0 */ + {0, 3}, /* CMD1 */ + {0, 2}, /* CMD2 */ + {0, 1}, /* CMD3 */ + {0, 0}, /* CMD4 */ + {0, 1}, /* CMD5 */ + {0, 1}, /* CMD6 */ + {0, 1}, /* CMD7 */ + {1, 1}, /* CMD8 */ + {0, 2}, /* CMD9 */ + {0, 2}, /* CMD10 */ + {1, 1}, /* CMD11 */ + {0, 1}, /* CMD12 */ + {0, 1}, /* CMD13 */ + {1, 1}, /* CMD14 */ + {0, 0}, /* CMD15 */ + {0, 1}, /* CMD16 */ + {1, 1}, /* CMD17 */ + {1, 1}, /* CMD18 */ + {3, 1}, /* CMD19 */ + {2, 1}, /* CMD20 */ + {0, 0}, /* CMD21 */ + {0, 0}, /* CMD22 */ + {0, 1}, /* CMD23 */ + {2, 1}, /* CMD24 */ + {2, 1}, /* CMD25 */ + {2, 1}, /* CMD26 */ + {2, 1}, /* CMD27 */ + {0, 1}, /* CMD28 */ + {0, 1}, /* CMD29 */ + {1, 1}, /* CMD30 */ + {1, 1}, /* CMD31 */ + {0, 0}, /* CMD32 */ + {0, 0}, /* CMD33 */ + {0, 0}, /* CMD34 */ + {0, 1}, /* CMD35 */ + {0, 1}, /* CMD36 */ + {0, 0}, /* CMD37 */ + {0, 1}, /* CMD38 */ + {0, 4}, /* CMD39 */ + {0, 5}, /* CMD40 */ + {0, 0}, /* CMD41 */ + {2, 1}, /* CMD42 */ + {0, 0}, /* CMD43 */ + {0, 0}, /* CMD44 */ + {0, 0}, /* CMD45 */ + {0, 0}, /* CMD46 */ + {0, 0}, /* CMD47 */ + {0, 0}, /* CMD48 */ + {0, 0}, /* CMD49 */ + {0, 0}, /* CMD50 */ + {0, 0}, /* CMD51 */ + {0, 0}, /* CMD52 */ + {0, 0}, /* CMD53 */ + {0, 0}, /* CMD54 */ + {0, 1}, /* CMD55 */ + {0xff, 0xff}, /* CMD56 */ + {0, 0}, /* CMD57 */ + {0, 0}, /* CMD58 */ + {0, 0}, /* CMD59 */ + {0, 0}, /* CMD60 */ + {0, 0}, /* CMD61 */ + {0, 0}, /* CMD62 */ + {0, 0} /* CMD63 */ +}; + +struct octeon_mmc_cr_mods { + u8 ctype_xor; + u8 rtype_xor; +}; + +static struct octeon_mmc_cr_mods octeon_mmc_get_cr_mods(struct mmc_command *cmd) +{ + struct octeon_mmc_cr_type *cr; + u8 desired_ctype, hardware_ctype; + u8 desired_rtype, hardware_rtype; + struct octeon_mmc_cr_mods r; + + cr = octeon_mmc_cr_types + (cmd->opcode & 0x3f); + hardware_ctype = cr->ctype; + hardware_rtype = cr->rtype; + if (cmd->opcode == 56) { /* CMD56 GEN_CMD */ + hardware_ctype = (cmd->arg & 1) ? 1 : 2; + } + + switch (mmc_cmd_type(cmd)) { + case MMC_CMD_ADTC: + desired_ctype = (cmd->data->flags & MMC_DATA_WRITE) ? 2 : 1; + break; + case MMC_CMD_AC: + case MMC_CMD_BC: + case MMC_CMD_BCR: + desired_ctype = 0; + break; + } + + switch (mmc_resp_type(cmd)) { + case MMC_RSP_NONE: + desired_rtype = 0; + break; + case MMC_RSP_R1:/* MMC_RSP_R5, MMC_RSP_R6, MMC_RSP_R7 */ + case MMC_RSP_R1B: + desired_rtype = 1; + break; + case MMC_RSP_R2: + desired_rtype = 2; + break; + case MMC_RSP_R3: /* MMC_RSP_R4 */ + desired_rtype = 3; + break; + } + r.ctype_xor = desired_ctype ^ hardware_ctype; + r.rtype_xor = desired_rtype ^ hardware_rtype; + return r; +} + +static bool octeon_mmc_switch_val_changed(struct octeon_mmc_slot *slot, + u64 new_val) +{ + /* Match BUS_ID, HS_TIMING, BUS_WIDTH, POWER_CLASS, CLK_HI, CLK_LO */ + u64 m = 0x3001070fffffffffull; + return (slot->host->last_emm_switch & m) != (new_val & m); +} + +static unsigned int octeon_mmc_timeout_to_wdog(struct octeon_mmc_slot *slot, + unsigned int ns) +{ + u64 bt = (u64)slot->clock * (u64)ns; + return (unsigned int)(bt / 1000000000); +} + +static void octeon_mmc_dma_next(struct octeon_mmc_host *host) +{ + struct scatterlist *sg; + struct mmc_data *data; + union cvmx_mio_ndf_dma_cfg dma_cfg; + u64 dma_int_en; + + data = host->current_req->data; + sg = data->sg + host->sg_idx; + + dma_cfg.u64 = 0; + dma_cfg.s.en = 1; + dma_cfg.s.rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; +#ifdef __LITTLE_ENDIAN + dma_cfg.s.endian = 1; +#endif + dma_cfg.s.size = (sg->length / 8) - 1; + dma_cfg.s.adr = sg_phys(sg); + + host->sg_idx++; + + if (host->sg_idx >= host->current_req->data->sg_len) + dma_int_en = 0; + else + dma_int_en = 1; + + cvmx_write_csr(host->ndf_base + OCT_MIO_NDF_DMA_INT_EN, dma_int_en); + cvmx_write_csr(host->ndf_base + OCT_MIO_NDF_DMA_CFG, dma_cfg.u64); + +} + +static irqreturn_t octeon_mmc_dma_interrupt(int irq, void *dev_id) +{ + struct octeon_mmc_host *host = dev_id; + unsigned long flags; + + pr_debug("Got interrupt: NDF_DMA_INT\n"); + spin_lock_irqsave(&host->lock, flags); + /* Clear any pending irqs */ + cvmx_write_csr(host->ndf_base + OCT_MIO_NDF_DMA_INT, 1); + + if (!host->current_req || !host->current_req->data) { + pr_err("ERROR: no current_req for octeon_mmc_dma_interrupt\n"); + goto out; + } + + if (host->sg_idx < host->current_req->data->sg_len) + octeon_mmc_dma_next(host); +out: + spin_unlock_irqrestore(&host->lock, flags); + + return IRQ_RETVAL(1); +} + +static irqreturn_t octeon_mmc_interrupt(int irq, void *dev_id) +{ + struct octeon_mmc_host *host = dev_id; + union cvmx_mio_emm_int emm_int; + struct mmc_request *req; + bool host_done; + union cvmx_mio_emm_rsp_sts rsp_sts; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + emm_int.u64 = cvmx_read_csr(host->base + OCT_MIO_EMM_INT); + req = host->current_req; + cvmx_write_csr(host->base + OCT_MIO_EMM_INT, emm_int.u64); + + pr_debug("Got interrupt: EMM_INT = 0x%llx\n", emm_int.u64); + + if (!req) + goto out; + + rsp_sts.u64 = cvmx_read_csr(host->base + OCT_MIO_EMM_RSP_STS); + pr_debug("octeon_mmc_interrupt MIO_EMM_RSP_STS 0x%llx\n", rsp_sts.u64); + + if (!host->dma_active && emm_int.s.buf_done && req->cmd->data && + ((rsp_sts.u64 >> 7) & 3) == 1) { + /* Read */ + int dbuf = rsp_sts.s.dbuf; + struct sg_mapping_iter *smi = &host->smi; + unsigned int bytes_xfered = 0; + u64 dat = 0; + int shift = -1; + + /* Auto inc from offset zero */ + cvmx_write_csr(host->base + OCT_MIO_EMM_BUF_IDX, (u64)(0x10000 | (dbuf << 6))); + + for (;;) { + if (smi->consumed >= smi->length) { + if (!sg_miter_next(smi)) + break; + smi->consumed = 0; + } + if (shift < 0) { + dat = cvmx_read_csr(host->base + OCT_MIO_EMM_BUF_DAT); + shift = 56; + } + + while (smi->consumed < smi->length && shift >= 0) { + *(u8 *)(smi->addr) = (dat >> shift) & 0xff; + bytes_xfered++; + smi->addr++; + smi->consumed++; + shift -= 8; + } + } + sg_miter_stop(smi); + req->cmd->data->bytes_xfered = bytes_xfered; + req->cmd->data->error = 0; + } + host_done = emm_int.s.cmd_done || emm_int.s.dma_done || + emm_int.s.cmd_err || emm_int.s.dma_err; + if (host_done && req->done) { + if (rsp_sts.u64 & (7ull << 13)) + req->cmd->error = -EILSEQ; + else + req->cmd->error = 0; + + if (host->dma_active && req->cmd->data) { + req->cmd->data->error = 0; + req->cmd->data->bytes_xfered = req->cmd->data->blocks * req->cmd->data->blksz; + } + if (rsp_sts.s.rsp_val) { + u64 rsp_hi; + u64 rsp_lo = cvmx_read_csr(host->base + OCT_MIO_EMM_RSP_LO); + + switch (rsp_sts.s.rsp_type) { + case 1: + case 3: + req->cmd->resp[0] = (rsp_lo >> 8) & 0xffffffff; + req->cmd->resp[1] = 0; + req->cmd->resp[2] = 0; + req->cmd->resp[3] = 0; + break; + case 2: + req->cmd->resp[3] = rsp_lo & 0xffffffff; + req->cmd->resp[2] = (rsp_lo >> 32) & 0xffffffff; + rsp_hi = cvmx_read_csr(host->base + OCT_MIO_EMM_RSP_HI); + req->cmd->resp[1] = rsp_hi & 0xffffffff; + req->cmd->resp[0] = (rsp_hi >> 32) & 0xffffffff; + break; + default: + pr_debug("octeon_mmc_interrupt unhandled rsp_val %d\n", + rsp_sts.s.rsp_type); + break; + } + pr_debug("octeon_mmc_interrupt resp %08x %08x %08x %08x\n", + req->cmd->resp[0], req->cmd->resp[1], + req->cmd->resp[2], req->cmd->resp[3]); + } + if (emm_int.s.dma_err && rsp_sts.s.dma_pend) { + /* Try to clean up failed DMA */ + union cvmx_mio_emm_dma emm_dma; + emm_dma.u64 = 0; + emm_dma.s.dma_val = 1; + emm_dma.s.dat_null = 1; + emm_dma.s.bus_id = rsp_sts.s.bus_id; + cvmx_write_csr(host->base + OCT_MIO_EMM_DMA, + emm_dma.u64); + } + + host->current_req = NULL; + req->done(req); + } + spin_unlock_irqrestore(&host->lock, flags); + if (host_done) + up(&host->mmc_serializer); +out: + return IRQ_RETVAL(emm_int.u64 != 0); +} + +static void octeon_mmc_dma_request(struct mmc_host *mmc, + struct mmc_request *mrq) +{ + struct octeon_mmc_slot *slot; + struct octeon_mmc_host *host; + struct mmc_command *cmd; + struct mmc_data *data; + union cvmx_mio_emm_int emm_int; + union cvmx_mio_emm_dma emm_dma; + unsigned long flags; + + cmd = mrq->cmd; + if (mrq->data == NULL || mrq->data->sg == NULL || !mrq->data->sg_len || + mrq->stop == NULL || mrq->stop->opcode != MMC_STOP_TRANSMISSION) { + pr_err("Error: octeon_mmc_dma_request no data\n"); + cmd->error = -EINVAL; + if (mrq->done) + mrq->done(mrq); + return; + } + + slot = mmc_priv(mmc); + host = slot->host; + + /* Only a single user of the host block at a time. */ + down(&host->mmc_serializer); + + data = mrq->data; + + if (data->timeout_ns) { + cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, + octeon_mmc_timeout_to_wdog(slot, data->timeout_ns)); + pr_debug("OCT_MIO_EMM_WDOG %llu\n", + cvmx_read_csr(host->base + OCT_MIO_EMM_WDOG)); + } + + spin_lock_irqsave(&host->lock, flags); + WARN_ON(host->current_req); + host->current_req = mrq; + + host->sg_idx = 0; + + /* Clear any pending irqs */ + cvmx_write_csr(host->ndf_base + OCT_MIO_NDF_DMA_INT, 1); + + octeon_mmc_dma_next(host); + emm_dma.u64 = 0; + emm_dma.s.bus_id = slot->bus_id; + emm_dma.s.dma_val = 1; + emm_dma.s.sector = mmc_card_blockaddr(mmc->card) ? 1 : 0; + emm_dma.s.rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; + if (mmc_card_mmc(mmc->card) || + (mmc_card_sd(mmc->card) && + (mmc->card->scr.cmds & SD_SCR_CMD23_SUPPORT))) + emm_dma.s.multi = 1; + emm_dma.s.block_cnt = data->blocks; + emm_dma.s.card_addr = cmd->arg; + + emm_int.u64 = 0; + emm_int.s.dma_done = 1; + emm_int.s.cmd_err = 1; + emm_int.s.dma_err = 1; + /* Clear the bit. */ + cvmx_write_csr(host->base + OCT_MIO_EMM_INT, emm_int.u64); + cvmx_write_csr(host->base + OCT_MIO_EMM_INT_EN, emm_int.u64); + host->dma_active = true; + + spin_unlock_irqrestore(&host->lock, flags); + + cvmx_write_csr(host->base + OCT_MIO_EMM_STS_MASK, 0xe4f90080ull); + cvmx_write_csr(host->base + OCT_MIO_EMM_STS_MASK, 0); + cvmx_write_csr(host->base + OCT_MIO_EMM_DMA, emm_dma.u64); + pr_debug("Send the dma command: %llx\n", emm_dma.u64); +} + +static void octeon_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct octeon_mmc_slot *slot; + struct octeon_mmc_host *host; + struct mmc_command *cmd; + union cvmx_mio_emm_int emm_int; + union cvmx_mio_emm_cmd emm_cmd; + struct octeon_mmc_cr_mods mods; + unsigned long flags; + + cmd = mrq->cmd; + + if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK || cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) { + octeon_mmc_dma_request(mmc, mrq); + return; + } + + mods = octeon_mmc_get_cr_mods(cmd); + + slot = mmc_priv(mmc); + host = slot->host; + + /* Only a single user of the host block at a time. */ + down(&host->mmc_serializer); + + spin_lock_irqsave(&host->lock, flags); + WARN_ON(host->current_req); + host->current_req = mrq; + + emm_int.u64 = 0; + emm_int.s.cmd_done = 1; + emm_int.s.cmd_err = 1; + if (cmd->data) { + pr_debug("command has data\n"); + cmd->error = -EINPROGRESS; + if (cmd->data->flags & MMC_DATA_READ) { + emm_int.s.buf_done = 1; + sg_miter_start(&host->smi, mrq->cmd->data->sg, + mrq->cmd->data->sg_len, SG_MITER_ATOMIC | SG_MITER_TO_SG); + } else { + struct sg_mapping_iter *smi = &host->smi; + unsigned int bytes_xfered = 0; + u64 dat = 0; + int shift = 56; + /* Copy data to the xmit buffer before issuing the command */ + sg_miter_start(smi, mrq->cmd->data->sg, + mrq->cmd->data->sg_len, SG_MITER_TO_SG); + /* Auto inc from offset zero, dbuf zero */ + cvmx_write_csr(host->base + OCT_MIO_EMM_BUF_IDX, 0x10000ull); + + for (;;) { + if (smi->consumed >= smi->length) { + if (!sg_miter_next(smi)) + break; + smi->consumed = 0; + } + + while (smi->consumed < smi->length && shift >= 0) { + dat |= (u64)(*(u8 *)(smi->addr)) << shift; + bytes_xfered++; + smi->addr++; + smi->consumed++; + shift -= 8; + } + if (shift < 0) { + cvmx_write_csr(host->base + OCT_MIO_EMM_BUF_DAT, dat); + shift = 56; + dat = 0; + } + } + sg_miter_stop(smi); + cmd->data->bytes_xfered = bytes_xfered; + cmd->data->error = 0; + } + if (cmd->data->timeout_ns) { + cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, + octeon_mmc_timeout_to_wdog(slot, cmd->data->timeout_ns)); + pr_debug("OCT_MIO_EMM_WDOG %llu\n", + cvmx_read_csr(host->base + OCT_MIO_EMM_WDOG)); + } + } else { + cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, + ((u64)slot->clock * 850ull) / 1000ull); + pr_debug("OCT_MIO_EMM_WDOG %llu\n", + cvmx_read_csr(host->base + OCT_MIO_EMM_WDOG)); + } + /* Clear the bit. */ + cvmx_write_csr(host->base + OCT_MIO_EMM_INT, emm_int.u64); + cvmx_write_csr(host->base + OCT_MIO_EMM_INT_EN, emm_int.u64); + host->dma_active = false; + spin_unlock_irqrestore(&host->lock, flags); + + emm_cmd.u64 = 0; + emm_cmd.s.cmd_val = 1; + emm_cmd.s.ctype_xor = mods.ctype_xor; + emm_cmd.s.rtype_xor = mods.rtype_xor; + if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) + emm_cmd.s.offset = 64 - ((cmd->data->blksz * cmd->data->blocks) / 8); + emm_cmd.s.bus_id = slot->bus_id; + emm_cmd.s.cmd_idx = cmd->opcode; + emm_cmd.s.arg = cmd->arg; + cvmx_write_csr(host->base + OCT_MIO_EMM_STS_MASK, 0); + cvmx_write_csr(host->base + OCT_MIO_EMM_CMD, emm_cmd.u64); + pr_debug("Send the command: %llx\n", emm_cmd.u64); + +} + +static void octeon_mmc_reset_bus(struct octeon_mmc_slot *slot, int preserve) +{ + union cvmx_mio_emm_cfg emm_cfg; + union cvmx_mio_emm_switch emm_switch; + u64 wdog = 0; + + emm_cfg.u64 = cvmx_read_csr(slot->host->base + OCT_MIO_EMM_CFG); + if (preserve) { + emm_switch.u64 = cvmx_read_csr(slot->host->base + OCT_MIO_EMM_SWITCH); + wdog = cvmx_read_csr(slot->host->base + OCT_MIO_EMM_WDOG); + } + + /* Reset the bus */ + emm_cfg.u64 &= ~(1 << slot->bus_id); + cvmx_write_csr(slot->host->base + OCT_MIO_EMM_CFG, emm_cfg.u64); + msleep(10); /* Wait 10ms */ + emm_cfg.u64 |= 1 << slot->bus_id; + cvmx_write_csr(slot->host->base + OCT_MIO_EMM_CFG, emm_cfg.u64); + + msleep(10); + + /* Restore switch settings */ + if (preserve) { + emm_switch.s.switch_exe = 0; + emm_switch.s.switch_err0 = 0; + emm_switch.s.switch_err1 = 0; + emm_switch.s.switch_err2 = 0; + slot->host->last_emm_switch = emm_switch.u64; + cvmx_write_csr(slot->host->base + OCT_MIO_EMM_SWITCH, + emm_switch.u64); + msleep(10); + cvmx_write_csr(slot->host->base + OCT_MIO_EMM_WDOG, wdog); + } else { + slot->host->last_emm_switch = 0; + } +} + +static void octeon_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct octeon_mmc_slot *slot; + struct octeon_mmc_host *host; + int bus_width; + int clock; + int hs_timing; + int power_class = 10; + int clk_period; + int timeout = 2000; + union cvmx_mio_emm_switch emm_switch; + union cvmx_mio_emm_rsp_sts emm_sts; + + slot = mmc_priv(mmc); + host = slot->host; + + /* Only a single user of the host block at a time. */ + down(&host->mmc_serializer); + + pr_debug("Calling set_ios: slot: clk = 0x%x, bus_width = %d\n", + slot->clock, slot->bus_width); + pr_debug("Calling set_ios: ios: clk = 0x%x, vdd = %u, bus_width = %u, power_mode = %u, timing = %u\n", + ios->clock, ios->vdd, ios->bus_width, ios->power_mode, + ios->timing); + pr_debug("Calling set_ios: mmc: caps = 0x%lx, bus_width = %d\n", + mmc->caps, mmc->ios.bus_width); + + /* + * Reset the chip on each power off + */ + if (ios->power_mode == MMC_POWER_OFF) { + octeon_mmc_reset_bus(slot, 1); + if (slot->power_gpio >= 0) + gpio_set_value_cansleep(slot->power_gpio, + slot->power_gpio_active_low ? 1 : 0); + } else { + if (slot->power_gpio >= 0) + gpio_set_value_cansleep(slot->power_gpio, + slot->power_gpio_active_low ? 0 : 1); + } + + switch (ios->bus_width) { + case MMC_BUS_WIDTH_8: + bus_width = 2; + break; + case MMC_BUS_WIDTH_4: + bus_width = 1; + break; + case MMC_BUS_WIDTH_1: + bus_width = 0; + break; + default: + pr_debug("unknown bus width %d\n", ios->bus_width); + bus_width = 0; + break; + } + hs_timing = (ios->timing == MMC_TIMING_MMC_HS); + if (ios->clock) { + slot->clock = ios->clock; + slot->bus_width = bus_width; + + clock = slot->clock; + + if (clock > 52000000) + clock = 50000000; + + clk_period = (octeon_get_io_clock_rate() + clock - 1) / (2 * clock); + + emm_switch.u64 = 0; + emm_switch.s.bus_id = slot->bus_id; + emm_switch.s.hs_timing = hs_timing; + emm_switch.s.bus_width = bus_width; + emm_switch.s.power_class = power_class; + emm_switch.s.clk_hi = clk_period; + emm_switch.s.clk_lo = clk_period; + + if (!octeon_mmc_switch_val_changed(slot, emm_switch.u64)) { + pr_debug("No change from 0x%llx mio_emm_switch, returning.\n", + emm_switch.u64); + goto out; + } + + pr_debug("Writing 0x%llx to mio_emm_wdog\n", + ((u64)clock * 850ull) / 1000ull); + cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, + ((u64)clock * 850ull) / 1000ull); + pr_debug("Writing 0x%llx to mio_emm_switch\n", emm_switch.u64); + cvmx_write_csr(host->base + OCT_MIO_EMM_SWITCH, emm_switch.u64); + slot->host->last_emm_switch = emm_switch.u64; + + do { + emm_sts.u64 = cvmx_read_csr(host->base + OCT_MIO_EMM_RSP_STS); + if (!emm_sts.s.switch_val) + break; + udelay(100); + } while (timeout-- > 0); + + if (timeout <= 0) { + pr_debug("%s: switch command timed out, status=0x%llx\n", + __func__, emm_sts.u64); + goto out; + } + } +out: + up(&host->mmc_serializer); +} + +static int octeon_mmc_get_ro(struct mmc_host *mmc) +{ + struct octeon_mmc_slot *slot = mmc_priv(mmc); + + if (slot->ro_gpio >= 0) { + int pin = gpio_get_value_cansleep(slot->ro_gpio); + if (pin < 0) + return pin; + if (slot->ro_gpio_active_low) + pin = !pin; + return pin; + } else { + return -ENOSYS; + } +} + +static int octeon_mmc_get_cd(struct mmc_host *mmc) +{ + struct octeon_mmc_slot *slot = mmc_priv(mmc); + + if (slot->cd_gpio >= 0) { + int pin = gpio_get_value_cansleep(slot->cd_gpio); + if (pin < 0) + return pin; + if (slot->cd_gpio_active_low) + pin = !pin; + return pin; + } else { + return -ENOSYS; + } +} + +static const struct mmc_host_ops octeon_mmc_ops = { + .request = octeon_mmc_request, + .set_ios = octeon_mmc_set_ios, + .get_ro = octeon_mmc_get_ro, + .get_cd = octeon_mmc_get_cd, +}; + +static void octeon_mmc_set_clock(struct octeon_mmc_slot *slot, + unsigned int clock) +{ + struct mmc_host *mmc = slot->mmc; + clock = min(clock, mmc->f_max); + clock = max(clock, mmc->f_min); + slot->clock = clock; +} + +static int octeon_mmc_initlowlevel(struct octeon_mmc_slot *slot, int id, + int bus_width) +{ + union cvmx_mio_emm_switch emm_switch; + struct octeon_mmc_host *host = slot->host; + + octeon_mmc_reset_bus(slot, 0); + + octeon_mmc_set_clock(slot, 400000); + + /* Program initial clock speed and power */ + emm_switch.u64 = 0; + emm_switch.s.bus_id = id; + emm_switch.s.power_class = 10; + emm_switch.s.clk_hi = (slot->sclock / slot->clock) / 2; + emm_switch.s.clk_lo = (slot->sclock / slot->clock) / 2; + slot->host->last_emm_switch = emm_switch.u64; + cvmx_write_csr(host->base + OCT_MIO_EMM_SWITCH, emm_switch.u64); + cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, + ((u64)slot->clock * 850ull) / 1000ull); + cvmx_write_csr(host->base + OCT_MIO_EMM_STS_MASK, 0xe4f90080ull); + + return 0; +} + +static int __devinit octeon_init_slot(struct octeon_mmc_host *host, int id, + int bus_width, int max_freq, + int ro_gpio, int cd_gpio, int power_gpio, + bool ro_low, bool cd_low, bool power_low) +{ + struct mmc_host *mmc; + struct octeon_mmc_slot *slot; + int ret; + + /* + * Allocate MMC structue + */ + mmc = mmc_alloc_host(sizeof(struct octeon_mmc_slot), &host->pdev->dev); + if (!mmc) { + pr_debug("alloc host failed\n"); + return -ENOMEM; + } + + slot = mmc_priv(mmc); + slot->mmc = mmc; + slot->host = host; + slot->ro_gpio = ro_gpio; + slot->cd_gpio = cd_gpio; + slot->power_gpio = power_gpio; + slot->ro_gpio_active_low = ro_low; + slot->cd_gpio_active_low = cd_low; + slot->power_gpio_active_low = power_low; + + if (slot->ro_gpio >= 0) + gpio_direction_input(slot->ro_gpio); + if (slot->cd_gpio >= 0) + gpio_direction_input(slot->cd_gpio); + if (slot->power_gpio >= 0) + gpio_direction_output(slot->power_gpio, + slot->power_gpio_active_low ? 1 : 0); + + /* + * Set up host parameters. + */ + mmc->ops = &octeon_mmc_ops; + mmc->f_min = 400000; + mmc->f_max = max_freq; + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | + MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | + MMC_CAP_ERASE | MMC_CAP_CMD23; + mmc->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | + MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | + MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36; + + mmc->max_segs = 64; + mmc->max_seg_size = (1 << 23) - 8; + mmc->max_req_size = mmc->max_seg_size; + mmc->max_blk_size = 512; + mmc->max_blk_count = mmc->max_req_size / 512; + + + slot->clock = mmc->f_min; + slot->sclock = octeon_get_io_clock_rate(); + + slot->bus_width = bus_width; + slot->bus_id = id; + + /* Initialize MMC Block. */ + octeon_mmc_initlowlevel(slot, id, bus_width); + + host->slot[id] = slot; + ret = mmc_add_host(mmc); + pr_debug("mmc_add_host returned %d\n", ret); + + return 0; +} + +static int __devinit octeon_mmc_probe(struct platform_device *pdev) +{ + union cvmx_mio_emm_cfg emm_cfg; + struct octeon_mmc_host *host; + struct resource *res; + int mmc_irq, dma_irq; + int ret = 0; + struct device_node *node; + int found = 0; + + mmc_irq = platform_get_irq(pdev, 0); + if (mmc_irq < 0) + return mmc_irq; + + dma_irq = platform_get_irq(pdev, 1); + if (dma_irq < 0) + return dma_irq; + + host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); + if (!host) { + dev_err(&pdev->dev, "devm_kzalloc failed\n"); + ret = -ENOMEM; + goto err; + } + + host->pdev = pdev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Platform resource is missing\n"); + ret = -ENXIO; + goto err; + } + if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), + res->name)) { + dev_err(&pdev->dev, "request_mem_region 0 failed\n"); + goto err; + } + + host->base = (u64)devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!host->base) { + dev_err(&pdev->dev, "Platform resource0 is missing\n"); + ret = -EINVAL; + goto err; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "Platform resource1 is missing\n"); + ret = -EINVAL; + goto err; + } + if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), + res->name)) { + dev_err(&pdev->dev, "request_mem_region 1 failed\n"); + goto err; + } + host->ndf_base = (u64)devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!host->ndf_base) { + dev_err(&pdev->dev, "Platform resource0 is missing\n"); + ret = -EINVAL; + goto err; + } + + ret = devm_request_irq(&pdev->dev, mmc_irq, octeon_mmc_interrupt, + 0, DRV_NAME, host); + if (ret < 0) { + dev_err(&pdev->dev, "Error: devm_request_irq %d\n", mmc_irq); + goto err; + } + + ret = devm_request_irq(&pdev->dev, dma_irq, octeon_mmc_dma_interrupt, + IRQF_SHARED, DRV_NAME, host); + if (ret < 0) { + dev_err(&pdev->dev, "Error: devm_request_irq %d\n", dma_irq); + goto err; + } + + + spin_lock_init(&host->lock); + sema_init(&host->mmc_serializer, 1); + + platform_set_drvdata(pdev, host); + + node = of_get_next_child(pdev->dev.of_node, NULL); + while (node) { + int size; + const __be32 *data; + found = 0; + + data = of_get_property(node, "reg", &size); + if (data) { + enum of_gpio_flags f; + int ro_gpio, cd_gpio, power_gpio; + bool ro_low, cd_low, power_low; + int bus_width, max_freq; + int slot = be32_to_cpu(*data); + data = of_get_property(node, + "cavium,bus-max-width", + &size); + if (!data || size != 4) { + pr_info("Bus width not found for slot %d\n", + slot); + bus_width = 8; + } else { + bus_width = be32_to_cpup(data); + switch (bus_width) { + case 1: + case 4: + case 8: + break; + default: + bus_width = 8; + break; + } + } + data = of_get_property(node, + "spi-max-frequency", + &size); + if (!data || size != 4) { + max_freq = 52000000; + pr_info("no spi-max-frequency for slot %d, defautling to %d\n", + slot, max_freq); + } else { + max_freq = be32_to_cpup(data); + } + + ro_gpio = of_get_named_gpio_flags(node, "wp-gpios", 0, &f); + ro_low = (ro_gpio >= 0 && f == OF_GPIO_ACTIVE_LOW); + cd_gpio = of_get_named_gpio_flags(node, "cd-gpios", 0, &f); + cd_low = (cd_gpio >= 0 && f == OF_GPIO_ACTIVE_LOW); + power_gpio = of_get_named_gpio_flags(node, "power-gpios", 0, &f); + power_low = (power_gpio >= 0 && f == OF_GPIO_ACTIVE_LOW); + + ret = octeon_init_slot(host, slot, bus_width, max_freq, + ro_gpio, cd_gpio, power_gpio, + ro_low, cd_low, power_low); + pr_debug("init slot %d, ret = %d\n", slot, ret); + if (ret) + goto err; + } + node = of_get_next_child(pdev->dev.of_node, node); + } + + return ret; + +err: + /* Disable MMC controller */ + emm_cfg.s.bus_ena = 0; + cvmx_write_csr(host->base + OCT_MIO_EMM_CFG, emm_cfg.u64); + return ret; +} + +static int __devexit octeon_mmc_remove(struct platform_device *pdev) +{ + union cvmx_mio_ndf_dma_int ndf_dma_int; + union cvmx_mio_ndf_dma_cfg ndf_dma_cfg; + struct octeon_mmc_host *host = platform_get_drvdata(pdev); + + if (host) { + /* Reset bus_id */ + ndf_dma_cfg.u64 = cvmx_read_csr(host->ndf_base + OCT_MIO_NDF_DMA_CFG); + ndf_dma_cfg.s.en = 0; + cvmx_write_csr(host->ndf_base + OCT_MIO_NDF_DMA_CFG, + ndf_dma_cfg.u64); + + /* Disable the interrupt */ + ndf_dma_int.u64 = 0; + cvmx_write_csr(host->ndf_base + OCT_MIO_NDF_DMA_INT, + ndf_dma_int.u64); + } + + platform_set_drvdata(pdev, NULL); + return 0; +} + +static struct of_device_id octeon_mmc_match[] = { + { + .compatible = "cavium,octeon-6130-mmc", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_mmc_match); + +static struct platform_driver octeon_mmc_driver = { + .probe = octeon_mmc_probe, + .remove = __devexit_p(octeon_mmc_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = octeon_mmc_match, + }, +}; + +static int __init octeon_mmc_init(void) +{ + int ret; + + pr_debug("calling octeon_mmc_init\n"); + + ret = platform_driver_register(&octeon_mmc_driver); + pr_debug("driver probe returned %d\n", ret); + + if (ret) + pr_err("%s: Failed to register driver\n", DRV_NAME); + + return ret; +} + +static void __exit octeon_mmc_cleanup(void) +{ + /* Unregister MMC driver */ + platform_driver_unregister(&octeon_mmc_driver); +} + +module_init(octeon_mmc_init); +module_exit(octeon_mmc_cleanup); + +MODULE_AUTHOR("Cavium Inc. "); +MODULE_DESCRIPTION("low-level driver for Cavium OCTEON MMC/SSD card"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); -- 1.7.2.3 From mattst88@gmail.com Wed May 9 21:22:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 May 2012 21:22:06 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:63729 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901170Ab2EITWB convert rfc822-to-8bit (ORCPT ); Wed, 9 May 2012 21:22:01 +0200 Received: by pbbrq13 with SMTP id rq13so996233pbb.36 for ; Wed, 09 May 2012 12:21:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=47BeUfd23lsw5Y9niuFQez5kpWqVF1PI0cPvRVhcLDY=; b=lPRdLOgezezUSmS201s10x9MaJOnEDFvc2DXFf1YFj5ZIWTYJPHK3AMHuS920suClQ rc1eFTAl/FVMVPjerhC/RySmChmsQs4sS0wnTFjAbvkkZ97x1Apw7Dc1aLhU+kFI3PY3 LUJ96AOVhwZgf4ivrz64lbNrvM3WLSYzP6nWhtzq1uG71UH2ZOF5Dlzd+5JLXm/nvyyA j+Tba2G5NfJLdPRr5JoC7PDbAxlrVgAWssneimyw6ll4FOxVmI8fWEhjix6QFGsP/QK1 YUFAfuiL2jpwVK13n3DBbml6iHdgjIDQLypr0TmKXL2UfGo05y9a3XSvBVaVRa5Ln5pL rs6w== Received: by 10.68.221.74 with SMTP id qc10mr11986138pbc.80.1336591314210; Wed, 09 May 2012 12:21:54 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.43.102 with HTTP; Wed, 9 May 2012 12:21:33 -0700 (PDT) In-Reply-To: References: <1336084845-28995-1-git-send-email-mattst88@gmail.com> From: Matt Turner Date: Wed, 9 May 2012 15:21:33 -0400 Message-ID: Subject: Re: [PATCH] mips: set ST0_MX flag for MDMX To: "Maciej W. Rozycki" Cc: Ralf Baechle , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 33224 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 753 Lines: 15 On Wed, May 9, 2012 at 1:20 PM, Maciej W. Rozycki wrote: >> As the comment in commit 3301edcb says, DSP and MDMX share the same >> config flag bit. >> >> Without this set, MDMX instructions cause Illegal instruction errors. > >  NAK, it's all pretty and nice, but I am afraid you're missing the point > with your change.  The bit has its purpose, the MDMX accumulator has to be > saved and restored -- just as the DSP or the FPU context -- between task > switches and the bit provides for doing that lazily (of course you can do > that eagerly instead if you like). Okay. It looks like I also need to add save/restoring of the MDMX accumulator to arch/mips/power/cpu.c and arch/mips/include/asm/switch_to.h:finish_arch_switch()? From paul.gortmaker@windriver.com Thu May 10 00:58:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 00:58:57 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:33323 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903649Ab2EIW6w convert rfc822-to-8bit (ORCPT ); Thu, 10 May 2012 00:58:52 +0200 Received: by lbbgg6 with SMTP id gg6so778428lbb.36 for ; Wed, 09 May 2012 15:58:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type :content-transfer-encoding; bh=VYCMPmXwMcXrGgFXUlmLo6c/YiKk2vP8GQr6OQWVuYE=; b=E3g5qGhpcH21IBuz3/p5vo/xQKfW5cwa408aFYaRe0Xfo23ByQ4sqfedG2ltTzR68v gClYnLJpJziUGujHrIcgRBuO7NpBcKVubDZeB51I/QtbAd4dZ5ynJ14kRqpCKmFzYLbw pWX2wHS8T9G4CFZN0E7cPrQVgRicQR8y+u7tcv1eUI4huJHLSIzQ+rFtQzmjMNotGHMk /fZ5ZiY8yv1xCLpBdzHN14IquzeuFu5JzIcJ3g9dHNxsszVwEoJZGKdbt696dHZjEPkU yfXMz0cSet4013xHMTgpVNsR8kx8JTTErEW02SS16beuKm0CSvFIEbi9aOZ28TEayVfo XCMA== Received: by 10.112.99.198 with SMTP id es6mr786935lbb.66.1336604326426; Wed, 09 May 2012 15:58:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.112.12.15 with HTTP; Wed, 9 May 2012 15:58:16 -0700 (PDT) In-Reply-To: <20120508165118.GA11750@merkur.ravnborg.org> References: <20120428205651.GA7426@merkur.ravnborg.org> <20120428205919.GC7442@merkur.ravnborg.org> <4FA460AB.6060309@suse.cz> <20120505082916.GA14006@merkur.ravnborg.org> <20120508165118.GA11750@merkur.ravnborg.org> From: Paul Gortmaker Date: Wed, 9 May 2012 18:58:16 -0400 X-Google-Sender-Auth: hBZjgnkToQiuUDj08rIywATPKZ8 Message-ID: Subject: Re: [PATCH 3/4] kbuild: link of vmlinux moved to a script To: Sam Ravnborg Cc: Tony Luck , Michal Marek , linux arch , lkml , linux-kbuild , Richard Weinberger , "David S. Miller" , Arnaud Lacombe , Andi Kleen , ralf@linux-mips.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 33225 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2255 Lines: 61 On Tue, May 8, 2012 at 12:51 PM, Sam Ravnborg wrote: > Hi Tony. > > On Mon, May 07, 2012 at 04:15:44PM -0700, Tony Luck wrote: >> This patch is now in linux-next (tag next-20120507). But it looks to have >> broken the ia64 build. I see this error: >> >>   CC      init/version.o >>   LD      init/built-in.o >>   KSYM    .tmp_kallsyms1.o >> ld: .tmp_kallsyms1.o: linking constant-gp files with non-constant-gp files >> ld: failed to merge target specific data of file .tmp_kallsyms1.o >> make: *** [vmlinux] Error 1 >> >> which looks like we used the wrong compile options when building >> .tmp_kallsyms1.o > > Thanks for testing! > > Could you try if this helps. > >        Sam > > diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinux.sh > index 26c5b65..1f4c27b 100644 > --- a/scripts/link-vmlinux.sh > +++ b/scripts/link-vmlinux.sh > @@ -78,8 +78,8 @@ kallsyms() >                kallsymopt=--all-symbols >        fi > > -       local aflags="${KBUILD_AFLAGS} ${NOSTDINC_FLAGS}                     \ > -                     ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" > +       local aflags="${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL}               \ > +                     ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" All the linux-next builds for mips are failing, which I tracked down to this. Applying the above update doesn't help. What is happening is that MIPS gets KBUILD_CPPFLAGS double-quoted, and then you get: + mips-wrs-linux-gnu-nm -n .tmp_vmlinux1 + scripts/kallsyms + mips-wrs-linux-gnu-gcc -D__ASSEMBLY__ <..snip..> -D__KERNEL__ '-D"VMLINUX_LOAD_ADDRESS=0xffffffff81100000"' '-D"DATAOFFSET=0"' -c -o .tmp_kallsyms1.o -x assembler-with-cpp - :0: error: macro names must be identifiers :0: error: macro names must be identifiers make[1]: *** [vmlinux] Error 1 Note the '-D"VMLINUX_LOAD_ADDRESS=0xffffffff81100000"' '-D"DATAOFFSET=0"' part -- that is what triggers the two above errors. Paul. > >        ${NM} -n ${1} | \ >                scripts/kallsyms ${kallsymopt} | \ > -- > To unsubscribe from this list: send the line "unsubscribe linux-arch" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at  http://vger.kernel.org/majordomo-info.html From Donald.McGillivray@uoit.ca Thu May 10 03:19:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 03:19:21 +0200 (CEST) Received: from smtpo0.dc-uoit.net ([205.211.180.195]:41959 "EHLO smtpo0.dc-uoit.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903646Ab2EJBTQ convert rfc822-to-8bit (ORCPT ); Thu, 10 May 2012 03:19:16 +0200 Received: from itomgwpp02.oncampus.local (itomgwpp02.oncampus.local [10.120.201.123]) by smtpo0.dc-uoit.net (8.14.3/8.14.3/Debian-9.4) with ESMTP id q4A06lFl007001; Wed, 9 May 2012 21:18:14 -0400 Received: from ITOMSCPP01.oncampus.local ([10.120.201.121]) by itomgwpp02.oncampus.local ([10.120.201.123]) with mapi; Wed, 9 May 2012 21:06:43 -0400 From: Donald McGillivray To: "info@notice.com" Date: Wed, 9 May 2012 21:06:42 -0400 Subject: Webmail Quota Warning! Thread-Topic: Webmail Quota Warning! Thread-Index: AQHNLkkpbgqk/xuEJk68jnChVQQsZw== Message-ID: <66DD8A7A10B3F043ACB11A509D71C8A21BAC1ECD61@ITOMSCPP01.oncampus.local> Accept-Language: en-US, en-CA Content-Language: en-CA X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US, en-CA Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7BIT MIME-Version: 1.0 X-DC-UOIT-MailScanner-ID: q4A06lFl007001 X-DC-UOIT-MailScanner: Found to be clean X-DC-UOIT-MailScanner-SpamCheck: not spam, SpamAssassin (cached, score=0.1, required 5, BAYES_00 -1.90, LOCAL_MAILBOX_FULL 2.00) X-DC-UOIT-MailScanner-From: donald.mcgillivray@uoit.ca X-archive-position: 33226 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Donald.McGillivray@uoit.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 197 Lines: 2 Your Mailbox Has Exceeded It Storage Limit As Set By Your Administrator, And You Will Not Be Able To Receive New Mails Until You Re-Validate It. To Re-Validate - > Click Here From sam@ravnborg.org Thu May 10 07:16:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 07:16:57 +0200 (CEST) Received: from smtp.snhosting.dk ([87.238.248.203]:14266 "EHLO smtp.domainteam.dk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903541Ab2EJFQx (ORCPT ); Thu, 10 May 2012 07:16:53 +0200 Received: from merkur.ravnborg.org (unknown [188.228.89.252]) by smtp.domainteam.dk (Postfix) with ESMTPA id 0242FF1BA9; Thu, 10 May 2012 07:16:47 +0200 (CEST) Date: Thu, 10 May 2012 07:16:46 +0200 From: Sam Ravnborg To: Paul Gortmaker Cc: Tony Luck , Michal Marek , linux arch , lkml , linux-kbuild , Richard Weinberger , "David S. Miller" , Arnaud Lacombe , Andi Kleen , ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 3/4] kbuild: link of vmlinux moved to a script Message-ID: <20120510051646.GA14138@merkur.ravnborg.org> References: <20120428205651.GA7426@merkur.ravnborg.org> <20120428205919.GC7442@merkur.ravnborg.org> <4FA460AB.6060309@suse.cz> <20120505082916.GA14006@merkur.ravnborg.org> <20120508165118.GA11750@merkur.ravnborg.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) X-archive-position: 33227 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2206 Lines: 58 On Wed, May 09, 2012 at 06:58:16PM -0400, Paul Gortmaker wrote: > On Tue, May 8, 2012 at 12:51 PM, Sam Ravnborg wrote: > > Hi Tony. > > > > On Mon, May 07, 2012 at 04:15:44PM -0700, Tony Luck wrote: > >> This patch is now in linux-next (tag next-20120507). But it looks to have > >> broken the ia64 build. I see this error: > >> > >>   CC      init/version.o > >>   LD      init/built-in.o > >>   KSYM    .tmp_kallsyms1.o > >> ld: .tmp_kallsyms1.o: linking constant-gp files with non-constant-gp files > >> ld: failed to merge target specific data of file .tmp_kallsyms1.o > >> make: *** [vmlinux] Error 1 > >> > >> which looks like we used the wrong compile options when building > >> .tmp_kallsyms1.o > > > > Thanks for testing! > > > > Could you try if this helps. > > > >        Sam > > > > diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinux.sh > > index 26c5b65..1f4c27b 100644 > > --- a/scripts/link-vmlinux.sh > > +++ b/scripts/link-vmlinux.sh > > @@ -78,8 +78,8 @@ kallsyms() > >                kallsymopt=--all-symbols > >        fi > > > > -       local aflags="${KBUILD_AFLAGS} ${NOSTDINC_FLAGS}                     \ > > -                     ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" > > +       local aflags="${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL}               \ > > +                     ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" > > All the linux-next builds for mips are failing, which I tracked down to this. > Applying the above update doesn't help. What is happening is that MIPS > gets KBUILD_CPPFLAGS double-quoted, and then you get: > > + mips-wrs-linux-gnu-nm -n .tmp_vmlinux1 > + scripts/kallsyms > + mips-wrs-linux-gnu-gcc -D__ASSEMBLY__ <..snip..> -D__KERNEL__ > '-D"VMLINUX_LOAD_ADDRESS=0xffffffff81100000"' '-D"DATAOFFSET=0"' -c -o > .tmp_kallsyms1.o -x assembler-with-cpp - > :0: error: macro names must be identifiers > :0: error: macro names must be identifiers > make[1]: *** [vmlinux] Error 1 > > Note the '-D"VMLINUX_LOAD_ADDRESS=0xffffffff81100000"' '-D"DATAOFFSET=0"' > part -- that is what triggers the two above errors. Hi Paul. I will take a look at this tonight. Thanks for the report! Sam From mmarek@suse.cz Thu May 10 14:22:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 14:22:25 +0200 (CEST) Received: from cantor2.suse.de ([195.135.220.15]:57352 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903655Ab2EJMWT (ORCPT ); Thu, 10 May 2012 14:22:19 +0200 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id C943EA2CD3; Thu, 10 May 2012 14:22:11 +0200 (CEST) Received: by sepie.suse.cz (Postfix, from userid 10020) id BAE6476447; Thu, 10 May 2012 14:22:10 +0200 (CEST) Date: Thu, 10 May 2012 14:22:10 +0200 From: Michal Marek To: Paul Gortmaker Cc: Sam Ravnborg , Tony Luck , linux arch , lkml , linux-kbuild , Richard Weinberger , "David S. Miller" , Arnaud Lacombe , Andi Kleen , ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 3/4] kbuild: link of vmlinux moved to a script Message-ID: <20120510122210.GA17550@sepie.suse.cz> References: <20120428205651.GA7426@merkur.ravnborg.org> <20120428205919.GC7442@merkur.ravnborg.org> <4FA460AB.6060309@suse.cz> <20120505082916.GA14006@merkur.ravnborg.org> <20120508165118.GA11750@merkur.ravnborg.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33228 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mmarek@suse.cz Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2572 Lines: 63 On Wed, May 09, 2012 at 06:58:16PM -0400, Paul Gortmaker wrote: > On Tue, May 8, 2012 at 12:51 PM, Sam Ravnborg wrote: > > diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinux.sh > > index 26c5b65..1f4c27b 100644 > > --- a/scripts/link-vmlinux.sh > > +++ b/scripts/link-vmlinux.sh > > @@ -78,8 +78,8 @@ kallsyms() > >                kallsymopt=--all-symbols > >        fi > > > > -       local aflags="${KBUILD_AFLAGS} ${NOSTDINC_FLAGS}                     \ > > -                     ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" > > +       local aflags="${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL}               \ > > +                     ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" > > All the linux-next builds for mips are failing, which I tracked down to this. > Applying the above update doesn't help. What is happening is that MIPS > gets KBUILD_CPPFLAGS double-quoted, and then you get: > > + mips-wrs-linux-gnu-nm -n .tmp_vmlinux1 > + scripts/kallsyms > + mips-wrs-linux-gnu-gcc -D__ASSEMBLY__ <..snip..> -D__KERNEL__ > '-D"VMLINUX_LOAD_ADDRESS=0xffffffff81100000"' '-D"DATAOFFSET=0"' -c -o > .tmp_kallsyms1.o -x assembler-with-cpp - > :0: error: macro names must be identifiers > :0: error: macro names must be identifiers > make[1]: *** [vmlinux] Error 1 > > Note the '-D"VMLINUX_LOAD_ADDRESS=0xffffffff81100000"' '-D"DATAOFFSET=0"' > part -- that is what triggers the two above errors. I think it should be as simple as the below patch. But I have no mips machine to verify myself. Michal >From d801533d5e6e509d5e115d2fb47655267c4c5ed4 Mon Sep 17 00:00:00 2001 From: Michal Marek Date: Thu, 10 May 2012 14:15:49 +0200 Subject: [PATCH] mips: Fix KBUILD_CPPFLAGS definition The KBUILD_CPPFLAGS variable is no longer passed to sh -c 'gcc ...', but exported and used by the link-vmlinux.sh script. This means that the double-quotes will not be evaluated by the shell. Reported-by: Paul Gortmaker Signed-off-by: Michal Marek diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 4fedf5a..722e04a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -219,8 +219,8 @@ endif KBUILD_AFLAGS += $(cflags-y) KBUILD_CFLAGS += $(cflags-y) -KBUILD_CPPFLAGS += -D"VMLINUX_LOAD_ADDRESS=$(load-y)" -KBUILD_CPPFLAGS += -D"DATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)" +KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) +KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0) LDFLAGS += -m $(ld-emul) From blogic@openwrt.org Thu May 10 14:29:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 14:29:14 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:39800 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903648Ab2EJM3G (ORCPT ); Thu, 10 May 2012 14:29:06 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , devicetree-discuss@lists.ozlabs.org, Grant Likely Subject: [PATCH V2 03/14] OF: MIPS: lantiq: implement irq_domain support Date: Thu, 10 May 2012 14:27:25 +0200 Message-Id: <1336652846-31871-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33229 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 10820 Lines: 351 Add support for irq_domain on lantiq socs. The conversion is straight forward as the ICU found inside the socs allows the usage of irq_domain_add_linear. Harware IRQ 0->7 are the generic MIPS IRQs. 8->199 are the Lantiq IRQ Modules. Our irq_chip callbacks need to substract 8 (MIPS_CPU_IRQ_CASCADE) from d->hwirq to find out the correct offset into the Interrupt Modules register range. Signed-off-by: John Crispin Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. Changes in V2 * properly reserve 8 irqs for MIPS * use d->hwirq rather than d->irq * use BIT(x) instead of (1 << x) * adds a optional property to allow setting the number of available EIU sources * simplify icu_map() arch/mips/lantiq/irq.c | 177 +++++++++++++++++++++++++++--------------------- 1 files changed, 101 insertions(+), 76 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index d227be1..9b5c3fc 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -9,6 +9,11 @@ #include #include +#include +#include +#include +#include +#include #include #include @@ -16,7 +21,7 @@ #include #include -/* register definitions */ +/* register definitions - internal irqs */ #define LTQ_ICU_IM0_ISR 0x0000 #define LTQ_ICU_IM0_IER 0x0008 #define LTQ_ICU_IM0_IOSR 0x0010 @@ -25,6 +30,7 @@ #define LTQ_ICU_IM1_ISR 0x0028 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) +/* register definitions - external irqs */ #define LTQ_EIU_EXIN_C 0x0000 #define LTQ_EIU_EXIN_INIC 0x0004 #define LTQ_EIU_EXIN_INEN 0x000C @@ -37,13 +43,14 @@ #define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1) #define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2) #define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30) - +#define XWAY_EXIN_COUNT 3 #define MAX_EIU 6 /* the performance counter */ #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) -/* irqs generated by device attached to the EBU need to be acked in +/* + * irqs generated by devices attached to the EBU need to be acked in * a special manner */ #define LTQ_ICU_EBU_IRQ 22 @@ -58,6 +65,9 @@ #define MIPS_CPU_IPI_RESCHED_IRQ 0 #define MIPS_CPU_IPI_CALL_IRQ 1 +/* we have a cascade of 8 irqs */ +#define MIPS_CPU_IRQ_CASCADE 8 + #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) int gic_present; #endif @@ -71,64 +81,51 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = { LTQ_EIU_IR5, }; -static struct resource ltq_icu_resource = { - .name = "icu", - .start = LTQ_ICU_BASE_ADDR, - .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct resource ltq_eiu_resource = { - .name = "eiu", - .start = LTQ_EIU_BASE_ADDR, - .end = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - +static int exin_avail; static void __iomem *ltq_icu_membase; static void __iomem *ltq_eiu_membase; void ltq_disable_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; - int irq_nr = d->irq - INT_NUM_IRQ0; + int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; - ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); + ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); + offset %= INT_NUM_IM_OFFSET; + ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier); } void ltq_mask_and_ack_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; u32 isr = LTQ_ICU_IM0_ISR; - int irq_nr = d->irq - INT_NUM_IRQ0; + int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); - isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; - ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); - ltq_icu_w32((1 << irq_nr), isr); + ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); + isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); + offset %= INT_NUM_IM_OFFSET; + ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier); + ltq_icu_w32(BIT(offset), isr); } static void ltq_ack_irq(struct irq_data *d) { u32 isr = LTQ_ICU_IM0_ISR; - int irq_nr = d->irq - INT_NUM_IRQ0; + int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; - ltq_icu_w32((1 << irq_nr), isr); + isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); + offset %= INT_NUM_IM_OFFSET; + ltq_icu_w32(BIT(offset), isr); } void ltq_enable_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; - int irq_nr = d->irq - INT_NUM_IRQ0; + int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; - ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier); + ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); + offset %= INT_NUM_IM_OFFSET; + ltq_icu_w32(ltq_icu_r32(ier) | BIT(offset), ier); } static unsigned int ltq_startup_eiu_irq(struct irq_data *d) @@ -137,15 +134,15 @@ static unsigned int ltq_startup_eiu_irq(struct irq_data *d) ltq_enable_irq(d); for (i = 0; i < MAX_EIU; i++) { - if (d->irq == ltq_eiu_irq[i]) { + if (d->hwirq == ltq_eiu_irq[i]) { /* low level - we should really handle set_type */ ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | (0x6 << (i * 4)), LTQ_EIU_EXIN_C); /* clear all pending */ - ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~(1 << i), + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i), LTQ_EIU_EXIN_INIC); /* enable */ - ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | (1 << i), + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i), LTQ_EIU_EXIN_INEN); break; } @@ -160,9 +157,9 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d) ltq_disable_irq(d); for (i = 0; i < MAX_EIU; i++) { - if (d->irq == ltq_eiu_irq[i]) { + if (d->hwirq == ltq_eiu_irq[i]) { /* disable */ - ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i), + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i), LTQ_EIU_EXIN_INEN); break; } @@ -199,14 +196,15 @@ static void ltq_hw_irqdispatch(int module) if (irq == 0) return; - /* silicon bug causes only the msb set to 1 to be valid. all + /* + * silicon bug causes only the msb set to 1 to be valid. all * other bits might be bogus */ irq = __fls(irq); - do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); + do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module)); /* if this is a EBU irq, we need to ack it or get a deadlock */ - if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) + if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, LTQ_EBU_PCC_ISTAT); } @@ -290,38 +288,66 @@ out: return; } +static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + struct irq_chip *chip = <q_irq_type; + int i; + + for (i = 0; i < exin_avail; i++) + if (hw == ltq_eiu_irq[i]) + chip = <q_eiu_type; + + irq_set_chip_and_handler(hw, chip, handle_level_irq); + + return 0; +} + +static const struct irq_domain_ops irq_domain_ops = { + .xlate = irq_domain_xlate_onetwocell, + .map = icu_map, +}; + static struct irqaction cascade = { .handler = no_action, .name = "cascade", }; -void __init arch_init_irq(void) +int __init icu_of_init(struct device_node *node, struct device_node *parent) { + struct device_node *eiu_node; + struct resource res; int i; - if (insert_resource(&iomem_resource, <q_icu_resource) < 0) - panic("Failed to insert icu memory"); + if (of_address_to_resource(node, 0, &res)) + panic("Failed to get icu memory range"); - if (request_mem_region(ltq_icu_resource.start, - resource_size(<q_icu_resource), "icu") < 0) - panic("Failed to request icu memory"); + if (request_mem_region(res.start, resource_size(&res), res.name) < 0) + pr_err("Failed to request icu memory"); - ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, - resource_size(<q_icu_resource)); + ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res)); if (!ltq_icu_membase) panic("Failed to remap icu memory"); - if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) - panic("Failed to insert eiu memory"); - - if (request_mem_region(ltq_eiu_resource.start, - resource_size(<q_eiu_resource), "eiu") < 0) - panic("Failed to request eiu memory"); - - ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, - resource_size(<q_eiu_resource)); - if (!ltq_eiu_membase) - panic("Failed to remap eiu memory"); + /* the external interrupts are optional and xway only */ + eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu"); + if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) { + /* find out how many external irq sources we have */ + const __be32 *count = of_get_property(node, "lantiq,count", NULL); + + if (count) + exin_avail = *count; + if (exin_avail > MAX_EIU) + exin_avail = MAX_EIU; + + if (request_mem_region(res.start, resource_size(&res), + res.name) < 0) + pr_err("Failed to request eiu memory"); + + ltq_eiu_membase = ioremap_nocache(res.start, + resource_size(&res)); + if (!ltq_eiu_membase) + panic("Failed to remap eiu memory"); + } /* turn off all irqs by default */ for (i = 0; i < 5; i++) { @@ -346,20 +372,8 @@ void __init arch_init_irq(void) set_vi_handler(7, ltq_hw5_irqdispatch); } - for (i = INT_NUM_IRQ0; - i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) - if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || - (i == LTQ_EIU_IR2)) - irq_set_chip_and_handler(i, <q_eiu_type, - handle_level_irq); - /* EIU3-5 only exist on ar9 and vr9 */ - else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) || - (i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9())) - irq_set_chip_and_handler(i, <q_eiu_type, - handle_level_irq); - else - irq_set_chip_and_handler(i, <q_irq_type, - handle_level_irq); + irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET, + &irq_domain_ops, 0); #if defined(CONFIG_MIPS_MT_SMP) if (cpu_has_vint) { @@ -382,9 +396,20 @@ void __init arch_init_irq(void) /* tell oprofile which irq to use */ cp0_perfcount_irq = LTQ_PERF_IRQ; + return 0; } unsigned int __cpuinit get_c0_compare_int(void) { return CP0_LEGACY_COMPARE_IRQ; } + +static struct of_device_id __initdata of_irq_ids[] = { + { .compatible = "lantiq,icu", .data = icu_of_init }, + {}, +}; + +void __init arch_init_irq(void) +{ + of_irq_init(of_irq_ids); +} -- 1.7.9.1 From blogic@openwrt.org Thu May 10 14:29:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 14:29:40 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:39802 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903652Ab2EJM3G (ORCPT ); Thu, 10 May 2012 14:29:06 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , devicetree-discuss@lists.ozlabs.org, Linus Walleij , Stephen Warren Subject: [PATCH V2 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support Date: Thu, 10 May 2012 14:27:26 +0200 Message-Id: <1336652846-31871-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1336652846-31871-1-git-send-email-blogic@openwrt.org> References: <1336652846-31871-1-git-send-email-blogic@openwrt.org> X-archive-position: 33230 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 46803 Lines: 1638 Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by: John Crispin Cc: devicetree-discuss@lists.ozlabs.org Cc: Linus Walleij Cc: Stephen Warren --- This patch is part of a series moving the mips/lantiq target to OF and clkdev support. The patch, once Acked, should go upstream via Ralf's MIPS tree. Changes in V2 * cleanup select/depends of the relevant Kconfig symbols * dont assume that the arry with out MFPs is linearly mapped * sane return code checks inside ltq_pinctrl_dt_node_to_map * remove 2 calls to pr_err and replace them with calls to dev_err * propagate gpio_chips base addr to the gpio_range * define the pin count inside the of_device_id.data * minor changes to accomodate the pinctrl-falcon driver (more virt pointers and clocks) * change from core_initcall_sync to arch_initcall * several typos, codestyle and whitespace cleanups * use BIT(x) in favour of (1 << x) arch/mips/Kconfig | 2 + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 - arch/mips/lantiq/Kconfig | 2 + arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/gpio.c | 195 ------ arch/mips/lantiq/xway/gpio_stp.c | 5 - arch/mips/pci/pci-lantiq.c | 44 +-- drivers/pinctrl/Kconfig | 11 + drivers/pinctrl/Makefile | 2 + drivers/pinctrl/pinctrl-lantiq.c | 342 ++++++++++ drivers/pinctrl/pinctrl-lantiq.h | 190 ++++++ drivers/pinctrl/pinctrl-xway.c | 652 ++++++++++++++++++++ 12 files changed, 1203 insertions(+), 246 deletions(-) delete mode 100644 arch/mips/lantiq/xway/gpio.c create mode 100644 drivers/pinctrl/pinctrl-lantiq.c create mode 100644 drivers/pinctrl/pinctrl-lantiq.h create mode 100644 drivers/pinctrl/pinctrl-xway.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fbb5639..200e920 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -229,6 +229,8 @@ config LANTIQ select SWAP_IO_SPACE select BOOT_RAW select HAVE_CLK + select PINCTRL + select PINCTRL_LANTIQ select USE_OF config LASAT diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 15eb4dc..150c7be 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -153,8 +153,6 @@ #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) /* request a non-gpio and set the PIO config */ -extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, - unsigned int alt1, unsigned int dir, const char *name); extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index 9485fe5..60d0f64 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -2,6 +2,7 @@ if LANTIQ config SOC_TYPE_XWAY bool + select PINCTRL_XWAY default n choice @@ -16,6 +17,7 @@ config SOC_XWAY bool "XWAY" select SOC_TYPE_XWAY select HW_HAS_PCI + endchoice diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 7a6c30f..323b574 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1,4 @@ -obj-y := prom.o pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o dma.o +obj-y := prom.o pmu.o ebu.o reset.o gpio_stp.o gpio_ebu.o dma.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c deleted file mode 100644 index c429a5b..0000000 --- a/arch/mips/lantiq/xway/gpio.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include -#include - -#include - -#define LTQ_GPIO_OUT 0x00 -#define LTQ_GPIO_IN 0x04 -#define LTQ_GPIO_DIR 0x08 -#define LTQ_GPIO_ALTSEL0 0x0C -#define LTQ_GPIO_ALTSEL1 0x10 -#define LTQ_GPIO_OD 0x14 - -#define PINS_PER_PORT 16 -#define MAX_PORTS 3 - -#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) -#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) -#define ltq_gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r) - -struct ltq_gpio { - void __iomem *membase; - struct gpio_chip chip; -}; - -static struct ltq_gpio ltq_gpio_port[MAX_PORTS]; - -int gpio_to_irq(unsigned int gpio) -{ - return -EINVAL; -} -EXPORT_SYMBOL(gpio_to_irq); - -int irq_to_gpio(unsigned int gpio) -{ - return -EINVAL; -} -EXPORT_SYMBOL(irq_to_gpio); - -int ltq_gpio_request(unsigned int pin, unsigned int alt0, - unsigned int alt1, unsigned int dir, const char *name) -{ - int id = 0; - - if (pin >= (MAX_PORTS * PINS_PER_PORT)) - return -EINVAL; - if (gpio_request(pin, name)) { - pr_err("failed to setup lantiq gpio: %s\n", name); - return -EBUSY; - } - if (dir) - gpio_direction_output(pin, 1); - else - gpio_direction_input(pin); - while (pin >= PINS_PER_PORT) { - pin -= PINS_PER_PORT; - id++; - } - if (alt0) - ltq_gpio_setbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL0, pin); - else - ltq_gpio_clearbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL0, pin); - if (alt1) - ltq_gpio_setbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL1, pin); - else - ltq_gpio_clearbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL1, pin); - return 0; -} -EXPORT_SYMBOL(ltq_gpio_request); - -static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - if (value) - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); - else - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); -} - -static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset); -} - -static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); - - return 0; -} - -static int ltq_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); - ltq_gpio_set(chip, offset, value); - - return 0; -} - -static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset); - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); - return 0; -} - -static int ltq_gpio_probe(struct platform_device *pdev) -{ - struct resource *res; - - if (pdev->id >= MAX_PORTS) { - dev_err(&pdev->dev, "invalid gpio port %d\n", - pdev->id); - return -EINVAL; - } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "failed to get memory for gpio port %d\n", - pdev->id); - return -ENOENT; - } - res = devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), dev_name(&pdev->dev)); - if (!res) { - dev_err(&pdev->dev, - "failed to request memory for gpio port %d\n", - pdev->id); - return -EBUSY; - } - ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev, - res->start, resource_size(res)); - if (!ltq_gpio_port[pdev->id].membase) { - dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n", - pdev->id); - return -ENOMEM; - } - ltq_gpio_port[pdev->id].chip.label = "ltq_gpio"; - ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input; - ltq_gpio_port[pdev->id].chip.direction_output = - ltq_gpio_direction_output; - ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get; - ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set; - ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req; - ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id; - ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; - platform_set_drvdata(pdev, <q_gpio_port[pdev->id]); - return gpiochip_add(<q_gpio_port[pdev->id].chip); -} - -static struct platform_driver -ltq_gpio_driver = { - .probe = ltq_gpio_probe, - .driver = { - .name = "ltq_gpio", - .owner = THIS_MODULE, - }, -}; - -int __init ltq_gpio_init(void) -{ - int ret = platform_driver_register(<q_gpio_driver); - - if (ret) - pr_info("ltq_gpio : Error registering platform driver!"); - return ret; -} - -postcore_initcall(ltq_gpio_init); diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index fd07d87..4f4bd61 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -78,11 +78,6 @@ static struct gpio_chip ltq_stp_chip = { static int ltq_stp_hw_init(void) { - /* the 3 pins used to control the external stp */ - ltq_gpio_request(4, 1, 0, 1, "stp-st"); - ltq_gpio_request(5, 1, 0, 1, "stp-d"); - ltq_gpio_request(6, 1, 0, 1, "stp-sh"); - /* sane defaults */ ltq_stp_w32(0, LTQ_STP_AR); ltq_stp_w32(0, LTQ_STP_CPU0); diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 70fdf2c..3418178 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -68,32 +68,6 @@ #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) -struct ltq_pci_gpio_map { - int pin; - int alt0; - int alt1; - int dir; - char *name; -}; - -/* the pci core can make use of the following gpios */ -static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = { - { 0, 1, 0, 0, "pci-exin0" }, - { 1, 1, 0, 0, "pci-exin1" }, - { 2, 1, 0, 0, "pci-exin2" }, - { 39, 1, 0, 0, "pci-exin3" }, - { 10, 1, 0, 0, "pci-exin4" }, - { 9, 1, 0, 0, "pci-exin5" }, - { 30, 1, 0, 1, "pci-gnt1" }, - { 23, 1, 0, 1, "pci-gnt2" }, - { 19, 1, 0, 1, "pci-gnt3" }, - { 38, 1, 0, 1, "pci-gnt4" }, - { 29, 1, 0, 0, "pci-req1" }, - { 31, 1, 0, 0, "pci-req2" }, - { 3, 1, 0, 0, "pci-req3" }, - { 37, 1, 0, 0, "pci-req4" }, -}; - __iomem void *ltq_pci_mapped_cfg; static __iomem void *ltq_pci_membase; @@ -151,22 +125,6 @@ static u32 ltq_calc_bar11mask(void) return bar11mask; } -static void ltq_pci_setup_gpio(int gpio) -{ - int i; - for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { - if (gpio & (1 << i)) { - ltq_gpio_request(ltq_pci_gpio_map[i].pin, - ltq_pci_gpio_map[i].alt0, - ltq_pci_gpio_map[i].alt1, - ltq_pci_gpio_map[i].dir, - ltq_pci_gpio_map[i].name); - } - } - ltq_gpio_request(21, 0, 0, 1, "pci-reset"); - ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; -} - static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) { u32 temp_buffer; @@ -192,7 +150,7 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) } /* setup pci clock and gpis used by pci */ - ltq_pci_setup_gpio(conf->gpio); + gpio_request(21, "pci-reset"); /* enable auto-switching between PCI and EBU */ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f73a5ea..802ae9f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -26,6 +26,12 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. +config PINCTRL_LANTIQ + bool + depends on LANTIQ + select PINMUX + select PINCONF + config PINCTRL_PXA3xx bool select PINMUX @@ -83,6 +89,11 @@ config PINCTRL_COH901 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 ports of 8 GPIO pins each. +config PINCTRL_XWAY + bool + depends on SOC_TYPE_XWAY + depends on PINCTRL_LANTIQ + endmenu endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8e3c95a..7896a12 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -9,6 +9,7 @@ ifeq ($(CONFIG_OF),y) obj-$(CONFIG_PINCTRL) += devicetree.o endif obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o +obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o @@ -19,3 +20,4 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o +obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c new file mode 100644 index 0000000..07ba768 --- /dev/null +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -0,0 +1,342 @@ +/* + * linux/drivers/pinctrl/pinctrl-lantiq.c + * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-lantiq.h" + +static int ltq_get_group_count(struct pinctrl_dev *pctrldev) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + return info->num_grps; +} + +static const char *ltq_get_group_name(struct pinctrl_dev *pctrldev, + unsigned selector) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + if (selector >= info->num_grps) + return NULL; + return info->grps[selector].name; +} + +static int ltq_get_group_pins(struct pinctrl_dev *pctrldev, + unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + if (selector >= info->num_grps) + return -EINVAL; + *pins = info->grps[selector].pins; + *num_pins = info->grps[selector].npins; + return 0; +} + +void ltq_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + kfree(map); +} + +static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); + unsigned long configs[3]; + unsigned num_configs = 0; + struct property *prop; + const char *group, *pin; + const char *function; + int ret, i; + + ret = of_property_read_string(np, "lantiq,function", &function); + if (!ret) { + of_property_for_each_string(np, "lantiq,groups", prop, group) { + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->name = function; + (*map)->data.mux.group = group; + (*map)->data.mux.function = function; + (*map)++; + } + if (of_find_property(np, "lantiq,pins", NULL)) + dev_err(pctldev->dev, + "%s mixes pins and groups settings\n", + np->name); + return 0; + } + + for (i = 0; i < info->num_params; i++) { + u32 val; + int ret = of_property_read_u32(np, + info->params[i].property, &val); + if (!ret) + configs[num_configs++] = + LTQ_PINCONF_PACK(info->params[i].param, + val); + } + + if (!num_configs) + return -EINVAL; + + of_property_for_each_string(np, "lantiq,pins", prop, pin) { + (*map)->data.configs.configs = kmemdup(configs, + num_configs * sizeof(unsigned long), + GFP_KERNEL); + (*map)->type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)->name = pin; + (*map)->data.configs.group_or_pin = pin; + (*map)->data.configs.num_configs = num_configs; + (*map)++; + } + return 0; +} + +static int ltq_pinctrl_dt_subnode_size(struct device_node *np) +{ + int ret; + + ret = of_property_count_strings(np, "lantiq,groups"); + if (ret < 0) + ret = of_property_count_strings(np, "lantiq,pins"); + return ret; +} + +int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct pinctrl_map *tmp; + struct device_node *np; + int ret; + + *num_maps = 0; + for_each_child_of_node(np_config, np) + *num_maps += ltq_pinctrl_dt_subnode_size(np); + *map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL); + if (!*map) + return -ENOMEM; + tmp = *map; + + for_each_child_of_node(np_config, np) { + ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp); + if (ret < 0) { + ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + return 0; +} + +static struct pinctrl_ops ltq_pctrl_ops = { + .get_groups_count = ltq_get_group_count, + .get_group_name = ltq_get_group_name, + .get_group_pins = ltq_get_group_pins, + .pin_dbg_show = ltq_pinctrl_pin_dbg_show, + .dt_node_to_map = ltq_pinctrl_dt_node_to_map, + .dt_free_map = ltq_pinctrl_dt_free_map, +}; + +static int ltq_pmx_func_count(struct pinctrl_dev *pctrldev) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + + return info->num_funcs; +} + +static const char *ltq_pmx_func_name(struct pinctrl_dev *pctrldev, + unsigned selector) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + + if (selector >= info->num_funcs) + return NULL; + + return info->funcs[selector].name; +} + +static int ltq_pmx_get_groups(struct pinctrl_dev *pctrldev, + unsigned func, + const char * const **groups, + unsigned * const num_groups) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + + *groups = info->funcs[func].groups; + *num_groups = info->funcs[func].num_groups; + + return 0; +} + +/* Return function number. If failure, return negative value. */ +static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux) +{ + int i; + for (i = 0; i < LTQ_MAX_MUX; i++) { + if (mfp->func[i] == mux) + break; + } + if (i >= LTQ_MAX_MUX) + return -EINVAL; + return i; +} + +/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */ +static int match_mfp(const struct ltq_pinmux_info *info, int pin) +{ + int i; + for (i = 0; i < info->num_mfp; i++) { + if (info->mfp[i].pin == pin) + return i; + } + return -1; +} + +/* check whether current pin configuration is valid. Negative for failure */ +static int match_group_mux(const struct ltq_pin_group *grp, + const struct ltq_pinmux_info *info, + unsigned mux) +{ + int i, pin, ret = 0; + for (i = 0; i < grp->npins; i++) { + pin = match_mfp(info, grp->pins[i]); + if (pin < 0) { + dev_err(info->dev, "could not find mfp for pin %d\n", + grp->pins[i]); + return -EINVAL; + } + ret = match_mux(&info->mfp[pin], mux); + if (ret < 0) { + dev_err(info->dev, "Can't find mux %d on pin%d\n", + mux, pin); + break; + } + } + return ret; +} + +static int ltq_pmx_enable(struct pinctrl_dev *pctrldev, + unsigned func, + unsigned group) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + const struct ltq_pin_group *pin_grp = &info->grps[group]; + int i, pin, pin_func, ret; + + if (!pin_grp->npins || + (match_group_mux(pin_grp, info, pin_grp->mux) < 0)) { + dev_err(info->dev, "Failed to set the pin group: %s\n", + info->grps[group].name); + return -EINVAL; + } + for (i = 0; i < pin_grp->npins; i++) { + pin = match_mfp(info, pin_grp->pins[i]); + if (pin < 0) { + dev_err(info->dev, "could not find mfp for pin %d\n", + pin_grp->pins[i]); + return -EINVAL; + } + pin_func = match_mux(&info->mfp[pin], pin_grp->mux); + ret = info->apply_mux(pctrldev, pin, pin_func); + if (ret) { + dev_err(info->dev, + "failed to apply mux %d for pin %d\n", + pin_func, pin); + return ret; + } + } + return 0; +} + +static void ltq_pmx_disable(struct pinctrl_dev *pctrldev, + unsigned func, + unsigned group) +{ + /* + * Nothing to do here. However, pinconf_check_ops() requires this + * callback to be defined. + */ +} + +static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + int mfp = match_mfp(info, pin + (range->id * 32)); + int pin_func; + + if (mfp < 0) { + dev_err(info->dev, "could not find mfp for pin %d\n", pin); + return -EINVAL; + } + + pin_func = match_mux(&info->mfp[mfp], 0); + if (pin_func < 0) { + dev_err(info->dev, "No GPIO function on pin%d\n", mfp); + return -EINVAL; + } + + return info->apply_mux(pctrldev, mfp, pin_func); +} + +static struct pinmux_ops ltq_pmx_ops = { + .get_functions_count = ltq_pmx_func_count, + .get_function_name = ltq_pmx_func_name, + .get_function_groups = ltq_pmx_get_groups, + .enable = ltq_pmx_enable, + .disable = ltq_pmx_disable, + .gpio_request_enable = ltq_pmx_gpio_request_enable, +}; + +/* + * allow different socs to register with the generic part of the lanti + * pinctrl code + */ +int ltq_pinctrl_register(struct platform_device *pdev, + struct ltq_pinmux_info *info) +{ + struct pinctrl_desc *desc; + + if (!info) + return -EINVAL; + desc = info->desc; + desc->pctlops = <q_pctrl_ops; + desc->pmxops = <q_pmx_ops; + info->dev = &pdev->dev; + + info->pctrl = pinctrl_register(desc, &pdev->dev, info); + if (!info->pctrl) { + dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n"); + return -EINVAL; + } + platform_set_drvdata(pdev, info); + return 0; +} diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h new file mode 100644 index 0000000..9ccc1a6 --- /dev/null +++ b/drivers/pinctrl/pinctrl-lantiq.h @@ -0,0 +1,190 @@ +/* + * linux/drivers/pinctrl/pinctrl-lantiq.h + * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#ifndef __PINCTRL_LANTIQ_H + +#include +#include +#include +#include +#include +#include + +#include "core.h" + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +#define LTQ_MAX_MUX 4 +#define MFPR_FUNC_MASK 0x3 + +#define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg)) +#define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16) +#define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff) + +enum ltq_pinconf_param { + LTQ_PINCONF_PARAM_PULL, + LTQ_PINCONF_PARAM_OPEN_DRAIN, + LTQ_PINCONF_PARAM_DRIVE_CURRENT, + LTQ_PINCONF_PARAM_SLEW_RATE, +}; + +struct ltq_cfg_param { + const char *property; + enum ltq_pinconf_param param; +}; + +struct ltq_mfp_pin { + const char *name; + const unsigned int pin; + const unsigned short func[LTQ_MAX_MUX]; +}; + +struct ltq_pin_group { + const char *name; + const unsigned mux; + const unsigned *pins; + const unsigned npins; +}; + +struct ltq_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; +}; + +struct ltq_pinmux_info { + struct device *dev; + struct pinctrl_dev *pctrl; + + /* we need to manage up to 5 pad controllers */ + void __iomem *membase[5]; + + /* the descriptor for the subsystem */ + struct pinctrl_desc *desc; + + /* we expose our pads to the subsystem */ + struct pinctrl_pin_desc *pads; + + /* the number of pads. this varies between socs */ + unsigned int num_pads; + + /* these are our multifunction pins */ + const struct ltq_mfp_pin *mfp; + unsigned int num_mfp; + + /* a number of multifunction pins can be grouped together */ + const struct ltq_pin_group *grps; + unsigned int num_grps; + + /* a mapping between function string and id */ + const struct ltq_pmx_func *funcs; + unsigned int num_funcs; + + /* the pinconf options that we are able to read from the DT */ + const struct ltq_cfg_param *params; + unsigned int num_params; + + /* we need 5 clocks max */ + struct clk *clk[5]; + + /* soc specific callback used to apply muxing */ + int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux); +}; + +enum ltq_pin { + GPIO0 = 0, + GPIO1, + GPIO2, + GPIO3, + GPIO4, + GPIO5, + GPIO6, + GPIO7, + GPIO8, + GPIO9, + GPIO10, /* 10 */ + GPIO11, + GPIO12, + GPIO13, + GPIO14, + GPIO15, + GPIO16, + GPIO17, + GPIO18, + GPIO19, + GPIO20, /* 20 */ + GPIO21, + GPIO22, + GPIO23, + GPIO24, + GPIO25, + GPIO26, + GPIO27, + GPIO28, + GPIO29, + GPIO30, /* 30 */ + GPIO31, + GPIO32, + GPIO33, + GPIO34, + GPIO35, + GPIO36, + GPIO37, + GPIO38, + GPIO39, + GPIO40, /* 40 */ + GPIO41, + GPIO42, + GPIO43, + GPIO44, + GPIO45, + GPIO46, + GPIO47, + GPIO48, + GPIO49, + GPIO50, /* 50 */ + GPIO51, + GPIO52, + GPIO53, + GPIO54, + GPIO55, + + GPIO64, + GPIO65, + GPIO66, + GPIO67, + GPIO68, + GPIO69, + GPIO70, + GPIO71, + GPIO72, + GPIO73, + GPIO74, + GPIO75, + GPIO76, + GPIO77, + GPIO78, + GPIO79, + GPIO80, + GPIO81, + GPIO82, + GPIO83, + GPIO84, + GPIO85, + GPIO86, + GPIO87, + GPIO88, +}; + +extern int ltq_pinctrl_register(struct platform_device *pdev, + struct ltq_pinmux_info *info); +extern int ltq_pinctrl_unregister(struct platform_device *pdev); +#endif /* __PINCTRL_PXA3XX_H */ diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c new file mode 100644 index 0000000..bd0910a9 --- /dev/null +++ b/drivers/pinctrl/pinctrl-xway.c @@ -0,0 +1,652 @@ +/* + * linux/drivers/pinctrl/pinmux-xway.c + * based on linux/drivers/pinctrl/pinmux-pxa910.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-lantiq.h" + +#include + +/* we have 3 1/2 banks of 16 bit each */ +#define PINS 16 +#define PORT3 3 +#define PORT(x) (x / PINS) +#define PORT_PIN(x) (x % PINS) + +/* we have 2 mux bits that can be set for each pin */ +#define MUX_ALT0 0x1 +#define MUX_ALT1 0x2 + +/* + * each bank has this offset apart from the 1/2 bank that is mixed into the + * other 3 ranges + */ +#define REG_OFF 0x30 + +/* these are the offsets to our registers */ +#define GPIO_BASE(p) (REG_OFF * PORT(p)) +#define GPIO_OUT(p) GPIO_BASE(p) +#define GPIO_IN(p) (GPIO_BASE(p) + 0x04) +#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08) +#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C) +#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10) +#define GPIO_OD(p) (GPIO_BASE(p) + 0x14) +#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c) +#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20) + +/* the 1/2 port needs special offsets for some registers */ +#define GPIO3_OD (GPIO_BASE(0) + 0x24) +#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28) +#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C) +#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24) + +/* macros to help us access the registers */ +#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p))) +#define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r) +#define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r) + +#define MFP_XWAY(a, f0, f1, f2, f3) \ + { \ + .name = #a, \ + .pin = a, \ + .func = { \ + XWAY_MUX_##f0, \ + XWAY_MUX_##f1, \ + XWAY_MUX_##f2, \ + XWAY_MUX_##f3, \ + }, \ + } + +#define GRP_MUX(a, m, p) \ + { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), } + +#define FUNC_MUX(f, m) \ + { .func = f, .mux = XWAY_MUX_##m, } + +#define XWAY_MAX_PIN 32 +#define XR9_MAX_PIN 56 + +enum xway_mux { + XWAY_MUX_GPIO = 0, + XWAY_MUX_SPI, + XWAY_MUX_ASC, + XWAY_MUX_PCI, + XWAY_MUX_CGU, + XWAY_MUX_EBU, + XWAY_MUX_JTAG, + XWAY_MUX_EXIN, + XWAY_MUX_TDM, + XWAY_MUX_STP, + XWAY_MUX_SIN, + XWAY_MUX_GPT, + XWAY_MUX_NMI, + XWAY_MUX_NONE = 0xffff, +}; + +static const struct ltq_mfp_pin xway_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM), + MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE), + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE), + MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI), + MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC), + MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE), + MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), + MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE), + MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), + MFP_XWAY(GPIO9, GPIO, ASC, SPI, NONE), + MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE), + MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI), + MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE), + MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE), + MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE), + MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE), + MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG), + MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG), + MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG), + MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE), + MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT), + MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE), + MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP), + MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI), + MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC), + MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM), + MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC), + MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE), + MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE), + MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU), + MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE), + MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO42, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO43, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), + MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE), +}; + +static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35}; +static const unsigned pins_asc0[] = {GPIO11, GPIO12}; +static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10}; +static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6}; +static const unsigned pins_nmi[] = {GPIO8}; + +static const unsigned pins_ebu_a24[] = {GPIO13}; +static const unsigned pins_ebu_clk[] = {GPIO21}; +static const unsigned pins_ebu_cs1[] = {GPIO23}; +static const unsigned pins_ebu_a23[] = {GPIO24}; +static const unsigned pins_ebu_wait[] = {GPIO26}; +static const unsigned pins_ebu_a25[] = {GPIO31}; +static const unsigned pins_ebu_rdy[] = {GPIO48}; +static const unsigned pins_ebu_rd[] = {GPIO49}; + +static const unsigned pins_nand_ale[] = {GPIO13}; +static const unsigned pins_nand_cs1[] = {GPIO23}; +static const unsigned pins_nand_cle[] = {GPIO24}; +static const unsigned pins_nand_rdy[] = {GPIO48}; +static const unsigned pins_nand_rd[] = {GPIO49}; + +static const unsigned pins_exin0[] = {GPIO0}; +static const unsigned pins_exin1[] = {GPIO1}; +static const unsigned pins_exin2[] = {GPIO2}; +static const unsigned pins_exin3[] = {GPIO39}; +static const unsigned pins_exin4[] = {GPIO46}; + +static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18}; +static const unsigned pins_spi_cs1[] = {GPIO15}; +static const unsigned pins_spi_cs2[] = {GPIO21}; +static const unsigned pins_spi_cs3[] = {GPIO13}; +static const unsigned pins_spi_cs4[] = {GPIO10}; +static const unsigned pins_spi_cs5[] = {GPIO9}; +static const unsigned pins_spi_cs6[] = {GPIO11}; + +static const unsigned pins_gpt1[] = {GPIO28}; +static const unsigned pins_gpt2[] = {GPIO21}; +static const unsigned pins_gpt3[] = {GPIO6}; + +static const unsigned pins_clkout0[] = {GPIO8}; +static const unsigned pins_clkout1[] = {GPIO7}; +static const unsigned pins_clkout2[] = {GPIO3}; +static const unsigned pins_clkout3[] = {GPIO2}; + +static const unsigned pins_pci_gnt1[] = {GPIO30}; +static const unsigned pins_pci_gnt2[] = {GPIO23}; +static const unsigned pins_pci_gnt3[] = {GPIO19}; +static const unsigned pins_pci_gnt4[] = {GPIO38}; +static const unsigned pins_pci_req1[] = {GPIO29}; +static const unsigned pins_pci_req2[] = {GPIO31}; +static const unsigned pins_pci_req3[] = {GPIO3}; +static const unsigned pins_pci_req4[] = {GPIO37}; + +static const struct ltq_pin_group xway_grps[] = { + GRP_MUX("exin0", EXIN, pins_exin0), + GRP_MUX("exin1", EXIN, pins_exin1), + GRP_MUX("exin2", EXIN, pins_exin2), + GRP_MUX("jtag", JTAG, pins_jtag), + GRP_MUX("ebu a23", EBU, pins_ebu_a23), + GRP_MUX("ebu a24", EBU, pins_ebu_a24), + GRP_MUX("ebu a25", EBU, pins_ebu_a25), + GRP_MUX("ebu clk", EBU, pins_ebu_clk), + GRP_MUX("ebu cs1", EBU, pins_ebu_cs1), + GRP_MUX("ebu wait", EBU, pins_ebu_wait), + GRP_MUX("nand ale", EBU, pins_nand_ale), + GRP_MUX("nand cs1", EBU, pins_nand_cs1), + GRP_MUX("nand cle", EBU, pins_nand_cle), + GRP_MUX("spi", SPI, pins_spi), + GRP_MUX("spi_cs1", SPI, pins_spi_cs1), + GRP_MUX("spi_cs2", SPI, pins_spi_cs2), + GRP_MUX("spi_cs3", SPI, pins_spi_cs3), + GRP_MUX("spi_cs4", SPI, pins_spi_cs4), + GRP_MUX("spi_cs5", SPI, pins_spi_cs5), + GRP_MUX("spi_cs6", SPI, pins_spi_cs6), + GRP_MUX("asc0", ASC, pins_asc0), + GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts), + GRP_MUX("stp", STP, pins_stp), + GRP_MUX("nmi", NMI, pins_nmi), + GRP_MUX("gpt1", GPT, pins_gpt1), + GRP_MUX("gpt2", GPT, pins_gpt2), + GRP_MUX("gpt3", GPT, pins_gpt3), + GRP_MUX("clkout0", CGU, pins_clkout0), + GRP_MUX("clkout1", CGU, pins_clkout1), + GRP_MUX("clkout2", CGU, pins_clkout2), + GRP_MUX("clkout3", CGU, pins_clkout3), + GRP_MUX("gnt1", PCI, pins_pci_gnt1), + GRP_MUX("gnt2", PCI, pins_pci_gnt2), + GRP_MUX("gnt3", PCI, pins_pci_gnt3), + GRP_MUX("req1", PCI, pins_pci_req1), + GRP_MUX("req2", PCI, pins_pci_req2), + GRP_MUX("req3", PCI, pins_pci_req3), +/* xrx only */ + GRP_MUX("nand rdy", EBU, pins_nand_rdy), + GRP_MUX("nand rd", EBU, pins_nand_rd), + GRP_MUX("exin3", EXIN, pins_exin3), + GRP_MUX("exin4", EXIN, pins_exin4), + GRP_MUX("gnt4", PCI, pins_pci_gnt4), + GRP_MUX("req4", PCI, pins_pci_gnt4), +}; + +static const char * const xway_pci_grps[] = {"gnt1", "gnt2", + "gnt3", "req1", + "req2", "req3"}; +static const char * const xway_spi_grps[] = {"spi", "spi_cs1", + "spi_cs2", "spi_cs3", + "spi_cs4", "spi_cs5", + "spi_cs6"}; +static const char * const xway_cgu_grps[] = {"clkout0", "clkout1", + "clkout2", "clkout3"}; +static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24", + "ebu a25", "ebu cs1", + "ebu wait", "ebu clk", + "nand ale", "nand cs1", + "nand cle"}; +static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"}; +static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; +static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"}; +static const char * const xway_jtag_grps[] = {"jtag"}; +static const char * const xway_stp_grps[] = {"stp"}; +static const char * const xway_nmi_grps[] = {"nmi"}; + +/* ar9/vr9/gr9 */ +static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24", + "ebu a25", "ebu cs1", + "ebu wait", "ebu clk", + "nand ale", "nand cs1", + "nand cle", "nand rdy", + "nand rd"}; +static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2", + "exin3", "exin4"}; +static const char * const xrx_pci_grps[] = {"gnt1", "gnt2", + "gnt3", "gnt4", + "req1", "req2", + "req3", "req4"}; + +static const struct ltq_pmx_func danube_funcs[] = { + {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, + {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, + {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, + {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, + {"exin", ARRAY_AND_SIZE(xway_exin_grps)}, + {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, + {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, + {"pci", ARRAY_AND_SIZE(xway_pci_grps)}, + {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)}, +}; + +static const struct ltq_pmx_func xrx_funcs[] = { + {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, + {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, + {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, + {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, + {"exin", ARRAY_AND_SIZE(xrx_exin_grps)}, + {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, + {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, + {"pci", ARRAY_AND_SIZE(xrx_pci_grps)}, + {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)}, +}; + +/* --------- pinconf related code --------- */ +static int xway_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); + enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); + int port = PORT(pin); + u32 reg; + + switch (param) { + case LTQ_PINCONF_PARAM_OPEN_DRAIN: + if (port == PORT3) + reg = GPIO3_OD; + else + reg = GPIO_OD(port); + *config = LTQ_PINCONF_PACK(param, + !!gpio_getbit(info->membase[0], reg, PORT_PIN(port))); + break; + + case LTQ_PINCONF_PARAM_PULL: + if (port == PORT3) + reg = GPIO3_PUDEN; + else + reg = GPIO_PUDEN(port); + if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) { + *config = LTQ_PINCONF_PACK(param, 0); + break; + } + + if (port == PORT3) + reg = GPIO3_PUDSEL; + else + reg = GPIO_PUDSEL(port); + if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) + *config = LTQ_PINCONF_PACK(param, 2); + else + *config = LTQ_PINCONF_PACK(param, 1); + break; + + default: + dev_err(pctldev->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + return 0; +} + +static int xway_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long config) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); + enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); + int arg = LTQ_PINCONF_UNPACK_ARG(config); + int port = PORT(pin); + u32 reg; + + switch (param) { + case LTQ_PINCONF_PARAM_OPEN_DRAIN: + if (port == PORT3) + reg = GPIO3_OD; + else + reg = GPIO_OD(port); + gpio_setbit(info->membase[0], reg, PORT_PIN(port)); + break; + + case LTQ_PINCONF_PARAM_PULL: + if (port == PORT3) + reg = GPIO3_PUDEN; + else + reg = GPIO_PUDEN(port); + if (arg == 0) { + gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); + break; + } + gpio_setbit(info->membase[0], reg, PORT_PIN(port)); + + if (port == PORT3) + reg = GPIO3_PUDSEL; + else + reg = GPIO_PUDSEL(port); + if (arg == 1) + gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); + else if (arg == 2) + gpio_setbit(info->membase[0], reg, PORT_PIN(port)); + else + dev_err(pctldev->dev, "Invalid pull value %d\n", arg); + break; + + default: + dev_err(pctldev->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + return 0; +} + +struct pinconf_ops xway_pinconf_ops = { + .pin_config_get = xway_pinconf_get, + .pin_config_set = xway_pinconf_set, +}; + +static struct pinctrl_desc xway_pctrl_desc = { + .owner = THIS_MODULE, + .confops = &xway_pinconf_ops, +}; + +static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, + int pin, int mux) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + int port = PORT(pin); + u32 alt1_reg = GPIO_ALT1(pin); + + if (port == PORT3) + alt1_reg = GPIO3_ALT1; + + if (mux & MUX_ALT0) + gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); + + if (mux & MUX_ALT1) + gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin)); + + return 0; +} + +static const struct ltq_cfg_param xway_cfg_params[] = { + {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, + {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN}, +}; + +static struct ltq_pinmux_info xway_info = { + .mfp = xway_mfp, + .desc = &xway_pctrl_desc, + .apply_mux = xway_mux_apply, + .params = xway_cfg_params, + .num_params = ARRAY_SIZE(xway_cfg_params), +}; + +/* --------- gpio_chip related code --------- */ +static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + if (val) + gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); +} + +static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); +} + +static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); + + return 0; +} + +static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); + xway_gpio_set(chip, pin, val); + + return 0; +} + +static int xway_gpio_req(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + return pinctrl_request_gpio(gpio); +} + +static void xway_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + pinctrl_free_gpio(gpio); +} + +static struct gpio_chip xway_chip = { + .label = "gpio-xway", + .direction_input = xway_gpio_dir_in, + .direction_output = xway_gpio_dir_out, + .get = xway_gpio_get, + .set = xway_gpio_set, + .request = xway_gpio_req, + .free = xway_gpio_free, + .base = -1, +}; + +/* --------- register the pinctrl layer --------- */ +static struct pinctrl_xway_soc { + int pin_count; + const struct ltq_pmx_func *funcs; + unsigned int num_funcs; +} soc_cfg[] = { + /* legacy xway */ + {XWAY_MAX_PIN, danube_funcs, ARRAY_SIZE(danube_funcs)}, + /* xway xr9 series */ + {XR9_MAX_PIN, xrx_funcs, ARRAY_SIZE(xrx_funcs)}, +}; + +static struct pinctrl_gpio_range xway_gpio_range = { + .name = "XWAY GPIO", + .gc = &xway_chip, +}; + +static const struct of_device_id xway_match[] = { + { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]}, + { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]}, + {}, +}; +MODULE_DEVICE_TABLE(of, xway_match); + +static int __devinit pinmux_xway_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + const struct pinctrl_xway_soc *xway_soc; + struct resource *res; + int ret, i; + + /* get and remap our register range */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Failed to get resource\n"); + return -ENOENT; + } + xway_info.membase[0] = devm_request_and_ioremap(&pdev->dev, res); + if (!xway_info.membase[0]) { + dev_err(&pdev->dev, "Failed to remap resource\n"); + return -ENOMEM; + } + + match = of_match_device(xway_match, &pdev->dev); + if (match) + xway_soc = (const struct pinctrl_xway_soc*) match->data; + else + xway_soc = &soc_cfg[0]; + + /* find out how many pads we have */ + xway_chip.ngpio = xway_soc->pin_count; + + /* load our pad descriptors */ + xway_info.pads = devm_kzalloc(&pdev->dev, + sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio, + GFP_KERNEL); + if (!xway_info.pads) { + dev_err(&pdev->dev, "Failed to allocate pads\n"); + return -ENOMEM; + } + for (i = 0; i < xway_chip.ngpio; i++) { + /* strlen("ioXY") + 1 = 5 */ + char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL); + + if (!name) { + dev_err(&pdev->dev, "Failed to allocate pad name\n"); + return -ENOMEM; + } + snprintf(name, 5, "io%d", i); + xway_info.pads[i].number = GPIO0 + i; + xway_info.pads[i].name = name; + } + xway_pctrl_desc.pins = xway_info.pads; + + /* load the gpio chip */ + xway_chip.dev = &pdev->dev; + of_gpiochip_add(&xway_chip); + ret = gpiochip_add(&xway_chip); + if (ret) { + dev_err(&pdev->dev, "Failed to register gpio chip\n"); + return ret; + } + + /* setup the data needed by pinctrl */ + xway_pctrl_desc.name = dev_name(&pdev->dev); + xway_pctrl_desc.npins = xway_chip.ngpio; + + xway_info.num_pads = xway_chip.ngpio; + xway_info.num_mfp = xway_chip.ngpio; + xway_info.grps = xway_grps; + xway_info.num_grps = ARRAY_SIZE(xway_grps); + xway_info.funcs = xway_soc->funcs; + xway_info.num_funcs = xway_soc->num_funcs; + + /* register with the generic lantiq layer */ + ret = ltq_pinctrl_register(pdev, &xway_info); + if (ret) { + dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); + return ret; + } + + /* finish with registering the gpio range in pinctrl */ + xway_gpio_range.npins = xway_chip.ngpio; + xway_gpio_range.base = xway_chip.base; + pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range); + dev_info(&pdev->dev, "Init done\n"); + return 0; +} + +static struct platform_driver pinmux_xway_driver = { + .probe = pinmux_xway_probe, + .driver = { + .name = "pinctrl-xway", + .owner = THIS_MODULE, + .of_match_table = xway_match, + }, +}; + +static int __init pinmux_xway_init(void) +{ + return platform_driver_register(&pinmux_xway_driver); +} + +arch_initcall(pinmux_xway_init); -- 1.7.9.1 From linus.walleij@linaro.org Thu May 10 15:24:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 15:24:15 +0200 (CEST) Received: from mail-gg0-f177.google.com ([209.85.161.177]:53867 "EHLO mail-gg0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903652Ab2EJNYL convert rfc822-to-8bit (ORCPT ); Thu, 10 May 2012 15:24:11 +0200 Received: by ggcs5 with SMTP id s5so1084508ggc.36 for ; Thu, 10 May 2012 06:24:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding:x-gm-message-state; bh=SfqS7ImB/x9zZG2IV1Zz0fAPIufHU6UGB6s9C3thDsU=; b=S6ou5RnTNVKwEjnahY6nz+AHicE9HAshId/cSSqeMt912z3NNxwKb/S+YN+BYYTvmK HY+O7XmNve7OglSyyuQ/7RFACCZEp4LpmrgNUIaCdCg+GqdLT1uEMK+CBcIli7AQ2zAt mJp3gaNW1DN3JoedP57Gc+o+BTD7W1AkpaQbxJkLqGsfhafN84kKdY/1ANGyY5t3J35J Q/OuPoX2e+KTcmnasmUwm7ecpPv+XkHwR2W490QvYfBct4vP8M4LE8aGKXSEAsvdT05O ofY7cLo06cIkaQ9U3spbqowiRBbyx0LE70oAF92cwCoD7IF2JP6PECPJJRC1QFHJaKnb Dn2w== MIME-Version: 1.0 Received: by 10.236.76.41 with SMTP id a29mr5034089yhe.117.1336656244835; Thu, 10 May 2012 06:24:04 -0700 (PDT) Received: by 10.147.137.4 with HTTP; Thu, 10 May 2012 06:24:04 -0700 (PDT) In-Reply-To: <1336652846-31871-2-git-send-email-blogic@openwrt.org> References: <1336652846-31871-1-git-send-email-blogic@openwrt.org> <1336652846-31871-2-git-send-email-blogic@openwrt.org> Date: Thu, 10 May 2012 15:24:04 +0200 Message-ID: Subject: Re: [PATCH V2 04/14] OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support From: Linus Walleij To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Stephen Warren Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-Gm-Message-State: ALoCoQkdgjfKxavM/HPbf5DZdCX2znvi/U9k40D27kDvNmbn5Vjxzc+aIOel651FDI9nY9sG7edL X-archive-position: 33231 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linus.walleij@linaro.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1458 Lines: 33 On Thu, May 10, 2012 at 2:27 PM, John Crispin wrote: > Implement support for pinctrl on lantiq/xway socs. The IO core found on these > socs has the registers for pinctrl, pinconf and gpio mixed up in the same > register range. As the gpio_chip handling is only a few lines, the driver also > implements the gpio functionality. This obseletes the old gpio driver that was > located in the arch/ folder. > > Signed-off-by: John Crispin > Cc: devicetree-discuss@lists.ozlabs.org > Cc: Linus Walleij > Cc: Stephen Warren > --- > This patch is part of a series moving the mips/lantiq target to OF and clkdev > support. The patch, once Acked, should go upstream via Ralf's MIPS tree. > > Changes in V2 > * cleanup select/depends of the relevant Kconfig symbols > * dont assume that the arry with out MFPs is linearly mapped > * sane return code checks inside ltq_pinctrl_dt_node_to_map > * remove 2 calls to pr_err and replace them with calls to dev_err > * propagate gpio_chips base addr to the gpio_range > * define the pin count inside the of_device_id.data > * minor changes to accomodate the pinctrl-falcon driver (more virt pointers >  and clocks) > * change from core_initcall_sync to arch_initcall > * several typos, codestyle and whitespace cleanups > * use BIT(x) in favour of (1 << x) Acked-by: Linus Walleij Yours, Linus Walleij From paul.gortmaker@windriver.com Thu May 10 16:44:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 16:44:51 +0200 (CEST) Received: from mail1.windriver.com ([147.11.146.13]:61409 "EHLO mail1.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903656Ab2EJOoq (ORCPT ); Thu, 10 May 2012 16:44:46 +0200 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail1.windriver.com (8.14.3/8.14.3) with ESMTP id q4AEhMaU013035 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Thu, 10 May 2012 07:44:31 -0700 (PDT) Received: from [128.224.146.65] (128.224.146.65) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server id 14.1.255.0; Thu, 10 May 2012 07:44:16 -0700 Message-ID: <4FABD436.7070402@windriver.com> Date: Thu, 10 May 2012 10:44:06 -0400 From: Paul Gortmaker User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120412 Thunderbird/11.0.1 MIME-Version: 1.0 To: Michal Marek CC: Sam Ravnborg , Tony Luck , linux arch , lkml , linux-kbuild , Richard Weinberger , "David S. Miller" , Arnaud Lacombe , Andi Kleen , , Subject: Re: [PATCH 3/4] kbuild: link of vmlinux moved to a script References: <20120428205651.GA7426@merkur.ravnborg.org> <20120428205919.GC7442@merkur.ravnborg.org> <4FA460AB.6060309@suse.cz> <20120505082916.GA14006@merkur.ravnborg.org> <20120508165118.GA11750@merkur.ravnborg.org> <20120510122210.GA17550@sepie.suse.cz> In-Reply-To: <20120510122210.GA17550@sepie.suse.cz> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [128.224.146.65] X-archive-position: 33232 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2845 Lines: 72 On 12-05-10 08:22 AM, Michal Marek wrote: > On Wed, May 09, 2012 at 06:58:16PM -0400, Paul Gortmaker wrote: >> On Tue, May 8, 2012 at 12:51 PM, Sam Ravnborg wrote: >>> diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinux.sh >>> index 26c5b65..1f4c27b 100644 >>> --- a/scripts/link-vmlinux.sh >>> +++ b/scripts/link-vmlinux.sh >>> @@ -78,8 +78,8 @@ kallsyms() >>> kallsymopt=--all-symbols >>> fi >>> >>> - local aflags="${KBUILD_AFLAGS} ${NOSTDINC_FLAGS} \ >>> - ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" >>> + local aflags="${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL} \ >>> + ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" >> >> All the linux-next builds for mips are failing, which I tracked down to this. >> Applying the above update doesn't help. What is happening is that MIPS >> gets KBUILD_CPPFLAGS double-quoted, and then you get: >> >> + mips-wrs-linux-gnu-nm -n .tmp_vmlinux1 >> + scripts/kallsyms >> + mips-wrs-linux-gnu-gcc -D__ASSEMBLY__ <..snip..> -D__KERNEL__ >> '-D"VMLINUX_LOAD_ADDRESS=0xffffffff81100000"' '-D"DATAOFFSET=0"' -c -o >> .tmp_kallsyms1.o -x assembler-with-cpp - >> :0: error: macro names must be identifiers >> :0: error: macro names must be identifiers >> make[1]: *** [vmlinux] Error 1 >> >> Note the '-D"VMLINUX_LOAD_ADDRESS=0xffffffff81100000"' '-D"DATAOFFSET=0"' >> part -- that is what triggers the two above errors. > > I think it should be as simple as the below patch. But I have no mips > machine to verify myself. Well I haven't boot tested it on anything either, but it does seem to resolve the double quoting that caused the compile failure. Thanks, Paul. -- > > Michal > > From d801533d5e6e509d5e115d2fb47655267c4c5ed4 Mon Sep 17 00:00:00 2001 > From: Michal Marek > Date: Thu, 10 May 2012 14:15:49 +0200 > Subject: [PATCH] mips: Fix KBUILD_CPPFLAGS definition > > The KBUILD_CPPFLAGS variable is no longer passed to sh -c 'gcc ...', > but exported and used by the link-vmlinux.sh script. This means that the > double-quotes will not be evaluated by the shell. > > Reported-by: Paul Gortmaker > Signed-off-by: Michal Marek > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index 4fedf5a..722e04a 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -219,8 +219,8 @@ endif > > KBUILD_AFLAGS += $(cflags-y) > KBUILD_CFLAGS += $(cflags-y) > -KBUILD_CPPFLAGS += -D"VMLINUX_LOAD_ADDRESS=$(load-y)" > -KBUILD_CPPFLAGS += -D"DATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)" > +KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) > +KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0) > > LDFLAGS += -m $(ld-emul) > From sjhill@mips.com Thu May 10 23:14:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 23:14:17 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:60830 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903691Ab2EJVON (ORCPT ); Thu, 10 May 2012 23:14:13 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SSagW-0000zV-T2; Thu, 10 May 2012 16:14:04 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH v2,1/5] MIPS: Add support for the 1074K core. Date: Thu, 10 May 2012 16:13:59 -0500 Message-Id: <1336684439-25109-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10 X-archive-position: 33233 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3759 Lines: 117 From: "Steven J. Hill" This patch adds support for detecting and using 1074K cores. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu.h | 1 + arch/mips/kernel/cpu-probe.c | 4 ++++ arch/mips/mm/c-r4k.c | 24 +++++++++++++++++++++--- arch/mips/oprofile/op_model_mipsxx.c | 6 ------ 4 files changed, 26 insertions(+), 9 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f9fa2a4..9f8feeb 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -94,6 +94,7 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 +#define PRID_IMP_1074K 0x9a00 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5099201..4b5c7d6 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -835,6 +835,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; break; + case PRID_IMP_1074K: + c->cputype = CPU_74K; + __cpu_name[cpu] = "MIPS 1074Kc"; + break; } spram_config(); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index bda8eb2..c646a79 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) c->icache.linesz = 2 << lsize; else c->icache.linesz = lsize; - c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); c->icache.ways = 1 + ((config1 >> 16) & 7); icache_size = c->icache.sets * @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) c->dcache.linesz = 2 << lsize; else c->dcache.linesz= lsize; - c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); c->dcache.ways = 1 + ((config1 >> 7) & 7); dcache_size = c->dcache.sets * @@ -1051,9 +1051,26 @@ static void __cpuinit probe_pcache(void) case CPU_R14000: break; + case CPU_74K: + /* + * Early versions of the 74k do not update + * the cache tags on a vtag miss/ptag hit + * which can occur in the case of KSEG0/KUSEG aliases + * In this case it is better to treat the cache as always + * having aliases + */ + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) + c->dcache.flags |= MIPS_CACHE_VTAG; + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + if (((c->processor_id & 0xff00) == PRID_IMP_1074K) && + ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) { + c->dcache.flags |= MIPS_CACHE_VTAG; + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + } + /* fall through */ case CPU_24K: case CPU_34K: - case CPU_74K: case CPU_1004K: if ((read_c0_config7() & (1 << 16))) { /* effectively physically indexed dcache, @@ -1061,6 +1078,7 @@ static void __cpuinit probe_pcache(void) c->dcache.flags |= MIPS_CACHE_PINDEX; break; } + /* fall through */ default: if (c->dcache.waysize > PAGE_SIZE) c->dcache.flags |= MIPS_CACHE_ALIASES; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..53bbe55 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -330,12 +330,6 @@ static int __init mipsxx_init(void) break; case CPU_1004K: -#if 0 - /* FIXME: report as 34K for now */ - op_model_mipsxx_ops.cpu_type = "mips/1004K"; - break; -#endif - case CPU_34K: op_model_mipsxx_ops.cpu_type = "mips/34K"; break; -- 1.7.10 From sjhill@mips.com Thu May 10 23:25:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 23:26:04 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:60866 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903691Ab2EJVZ5 (ORCPT ); Thu, 10 May 2012 23:25:57 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SSaru-00010i-3K; Thu, 10 May 2012 16:25:50 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH v2,3/5] MIPS: Updates to SMTC and SMVP support for threaded cores. Date: Thu, 10 May 2012 16:25:39 -0500 Message-Id: <1336685139-25376-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10 X-archive-position: 33234 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 44308 Lines: 1474 From: "Steven J. Hill" Changes for sharing interrupts between VPEs. Add support for APRP and loading a VPE with an ELF image. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 34 +- arch/mips/include/asm/mips_mt.h | 1 + arch/mips/include/asm/topology.h | 3 + arch/mips/include/asm/vpe.h | 30 +- arch/mips/kernel/rtlx.c | 21 +- arch/mips/kernel/smp-mt.c | 39 +- arch/mips/kernel/syscall.c | 5 +- arch/mips/kernel/vpe.c | 844 ++++++++++++++++++++++++++++++++++---- 8 files changed, 857 insertions(+), 120 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ce30e2f..8d33a91 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1862,14 +1862,14 @@ config MIPS_MT_SMP select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a VSMP but lately has been - marketesed into SMVP. - Virtual SMP uses the processor's VPEs to implement virtual - processors. In currently available configuration of the 34K processor - this allows for a dual processor. Both processors will share the same - primary caches; each will obtain the half of the TLB for it's own - exclusive use. For a layman this model can be described as similar to - what Intel calls Hyperthreading. + Virtual SMP uses the processor's VPEs to implement virtual + processors. In currently available configurations of the 34K + processor this allows for a dual processor. Both processors will + share the same primary caches and each will obtain the half of + the TLB for its own exclusive use. For a layman this model can + be described as similar to what Intel calls Hyperthreading. At + some point MIPS marketing decided to renamed to SMVP but the + renaming hasn't caught on as of yet. For further information see http://www.linux-mips.org/wiki/34K#VSMP @@ -1886,14 +1886,16 @@ config MIPS_MT_SMTC select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a SMTC or lately has been - marketesed into SMVP. - is presenting the available TC's of the core as processors to Linux. - On currently available 34K processors this means a Linux system will - see up to 5 processors. The implementation of the SMTC kernel differs - significantly from VSMP and cannot efficiently coexist in the same - kernel binary so the choice between VSMP and SMTC is a compile time - decision. + SMTC is presenting the available TCs of the core as processors to + Linux. On currently available 34K processors this means a Linux + system will see up to 5 processors. The implementation of the SMTC + kernel differs significantly from VSMP. It was found that SMTC cannot + efficiently coexist in the same kernel binary with other modes of + multiprocessor support, so enabling SMTC is a compile time decision. + The choice between VSMP and SMTC is a bit delicate as it is affected + by clockspeed, memory speed, the specific workload and other factors. + As such the choice should not be made on an evaluation board such as + the Malta but preferably on final target hardware. For further information see http://www.linux-mips.org/wiki/34K#SMTC diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h index ac79352..3177c83 100644 --- a/arch/mips/include/asm/mips_mt.h +++ b/arch/mips/include/asm/mips_mt.h @@ -19,6 +19,7 @@ extern unsigned long mt_fpemul_threshold; extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); extern void mips_mt_set_cpuoptions(void); +extern void cmp_send_ipi_single(int cpu, unsigned int action); struct class; extern struct class *mt_class; diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h index 259145e..709e78a 100644 --- a/arch/mips/include/asm/topology.h +++ b/arch/mips/include/asm/topology.h @@ -12,6 +12,9 @@ #ifdef CONFIG_SMP #define smt_capable() (smp_num_siblings > 1) +/* FIXME: cpu_sibling_map is not a per_cpu variable */ +/*#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) */ +#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu]) #endif #endif /* __ASM_TOPOLOGY_H */ diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index c6e1b96..e5e4033 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -26,12 +26,40 @@ struct vpe_notifications { struct list_head list; }; - +extern unsigned long physical_memsize; extern int vpe_notify(int index, struct vpe_notifications *notify); +extern void save_gp_address(unsigned int secbase, unsigned int rel); + +/* + * libc style I/O support hooks + */ extern void *vpe_get_shared(int index); extern int vpe_getuid(int index); extern int vpe_getgid(int index); extern char *vpe_getcwd(int index); +/* + * Kernel/Kernel message passing support hooks + */ + +extern void *vpe_get_shared_area(int index, int type); + +/* "Well-Known" Area Types */ + +#define VPE_SHARED_NULL 0 +#define VPE_SHARED_RESERVED -1 + +struct vpe_shared_area { + int type; + void *addr; +}; + +/* + * IRQ assignment and initialization hook for RP services. + */ + +int arch_get_xcpu_irq(void); + +int vpe_send_interrupt(int v, int i); #endif /* _ASM_VPE_H */ diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index b8c18dc..25278d0 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -57,12 +57,6 @@ static int sp_stopping; extern void *vpe_get_shared(int index); -static void rtlx_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); -} - - /* Interrupt handler may be called before rtlx_init has otherwise had a chance to run. */ @@ -483,7 +477,7 @@ static char register_chrdev_failed[] __initdata = static int __init rtlx_module_init(void) { struct device *dev; - int i, err; + int i, err, irq; if (!cpu_has_mipsmt) { printk("VPE loader: not a MIPS MT capable processor\n"); @@ -523,18 +517,17 @@ static int __init rtlx_module_init(void) notify.start = starting; notify.stop = stopping; vpe_notify(tclimit, ¬ify); - - if (cpu_has_vint) - set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); - else { + irq = arch_get_xcpu_irq(); + if (irq < 0) { pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); err = -ENODEV; goto out_chrdev; } - rtlx_irq.dev_id = rtlx; - setup_irq(rtlx_irq_num, &rtlx_irq); - + err = request_irq(irq, &rtlx_interrupt, IRQF_SHARED, + module_name, (void *)dev); + if (err) + goto out_chrdev; return 0; out_chrdev: diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ff17868..f2bf036 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -34,7 +34,9 @@ #include #include #include +#include +extern int gic_present; static void __init smvp_copy_vpe_config(void) { write_vpe_c0_status( @@ -70,6 +72,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0, /* Record this as available CPU */ set_cpu_possible(tc, true); + set_cpu_present(tc, true); __cpu_number_map[tc] = ++ncpu; __cpu_logical_map[ncpu] = tc; } @@ -111,12 +114,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) write_tc_c0_tchalt(TCHALT_H); } +static void mp_send_ipi_single(int cpu, unsigned int action) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (action) { + case SMP_CALL_FUNCTION: + gic_send_ipi(plat_ipi_call_int_xlate(cpu)); + break; + + case SMP_RESCHEDULE_YOURSELF: + gic_send_ipi(plat_ipi_resched_int_xlate(cpu)); + break; + } + + local_irq_restore(flags); +} + static void vsmp_send_ipi_single(int cpu, unsigned int action) { int i; unsigned long flags; int vpflags; + if (gic_present) { + mp_send_ipi_single(cpu, action); + return; + } local_irq_save(flags); vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ @@ -150,9 +176,8 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) static void __cpuinit vsmp_init_secondary(void) { - extern int gic_present; - - /* This is Malta specific: IPI,performance and timer interrupts */ + pr_debug("SMPMT: CPU%d: vsmp_init_secondary\n", smp_processor_id()); + /* This is Malta specific: IPI,performance and timer inetrrupts */ if (gic_present) change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 | STATUSF_IP7); @@ -163,6 +188,8 @@ static void __cpuinit vsmp_init_secondary(void) static void __cpuinit vsmp_smp_finish(void) { + pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id()); + /* CDFIXME: remove this? */ write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); @@ -177,6 +204,7 @@ static void __cpuinit vsmp_smp_finish(void) static void vsmp_cpus_done(void) { + pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id()); } /* @@ -190,6 +218,8 @@ static void vsmp_cpus_done(void) static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) { struct thread_info *gp = task_thread_info(idle); + pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n", + smp_processor_id(), cpu); dvpe(); set_c0_mvpcontrol(MVPCONTROL_VPC); @@ -231,6 +261,7 @@ static void __init vsmp_smp_setup(void) unsigned int mvpconf0, ntc, tc, ncpu = 0; unsigned int nvpe; + pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id()); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ if (cpu_has_fpu) @@ -271,6 +302,8 @@ static void __init vsmp_smp_setup(void) static void __init vsmp_prepare_cpus(unsigned int max_cpus) { + pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n", + smp_processor_id(), max_cpus); mips_mt_set_cpuoptions(); } diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index b08220c..bacd9bf 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -124,7 +124,7 @@ _sys_clone(nabi_no_regargs struct pt_regs regs) child_tidptr = (int __user *) regs.regs[8]; #endif return do_fork(clone_flags, newsp, ®s, 0, - parent_tidptr, child_tidptr); + parent_tidptr, child_tidptr); } /* @@ -264,11 +264,12 @@ save_static_function(sys_sysmips); static int __used noinline _sys_sysmips(nabi_no_regargs struct pt_regs regs) { - long cmd, arg1, arg2; + long cmd, arg1, arg2, arg3; cmd = regs.regs[4]; arg1 = regs.regs[5]; arg2 = regs.regs[6]; + arg3 = regs.regs[7]; switch (cmd) { case MIPS_ATOMIC_SET: diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index f6f9152..e8c99a4 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -73,17 +73,14 @@ static const int minor = 1; /* fixed for now */ static struct kspd_notifications kspd_events; static int kspd_events_reqd; #endif - -/* grab the likely amount of memory we will need. */ -#ifdef CONFIG_MIPS_VPE_LOADER_TOM -#define P_SIZE (2 * 1024 * 1024) -#else -/* add an overhead to the max kmalloc size for non-striped symbols/etc */ +/* + * Size of private kernel buffer for ELF headers and sections + */ #define P_SIZE (256 * 1024) -#endif - -extern unsigned long physical_memsize; +/* + * Size of private kernel buffer for ELF headers and sections + */ #define MAX_VPES 16 #define VPE_PATH_MAX 256 @@ -100,6 +97,16 @@ enum tc_state { TC_STATE_DYNAMIC }; +enum load_state { + LOAD_STATE_EHDR, + LOAD_STATE_PHDR, + LOAD_STATE_SHDR, + LOAD_STATE_PIMAGE, + LOAD_STATE_TRAILER, + LOAD_STATE_DONE, + LOAD_STATE_ERROR +}; + struct vpe { enum vpe_state state; @@ -107,10 +114,25 @@ struct vpe { int minor; /* elfloader stuff */ + unsigned long offset; /* File offset into input stream */ void *load_addr; - unsigned long len; + unsigned long copied; char *pbuffer; - unsigned long plen; + unsigned long pbsize; + /* Program loading state */ + enum load_state l_state; + Elf_Ehdr *l_ehdr; + struct elf_phdr *l_phdr; + unsigned int l_phlen; + Elf_Shdr *l_shdr; + unsigned int l_shlen; + int *l_phsort; /* Sorted index list of program headers */ + int l_segoff; /* Offset into current program segment */ + int l_cur_seg; /* Indirect index of segment currently being loaded */ + unsigned int l_progminad; + unsigned int l_progmaxad; + unsigned int l_trailer; + unsigned int uid, gid; char cwd[VPE_PATH_MAX]; @@ -122,9 +144,12 @@ struct vpe { /* The list of vpe's */ struct list_head list; - /* shared symbol address */ + /* legacy shared symbol address */ void *shared_ptr; + /* shared area descriptor array address */ + struct vpe_shared_area *shared_areas; + /* the list of who wants to know when something major happens */ struct list_head notify; @@ -146,13 +171,24 @@ struct { spinlock_t tc_list_lock; struct list_head tc_list; /* Thread contexts */ } vpecontrol = { - .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), + .vpe_list_lock = SPIN_LOCK_UNLOCKED, .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), - .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), + .tc_list_lock = SPIN_LOCK_UNLOCKED, .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) }; static void release_progmem(void *ptr); +/* + * Values and state associated with publishing shared memory areas + */ + +#define N_PUB_AREAS 4 + +static struct vpe_shared_area published_vpe_area[N_PUB_AREAS] = { + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0} }; /* get the vpe associated with this minor */ static struct vpe *get_vpe(int minor) @@ -175,7 +211,7 @@ static struct vpe *get_vpe(int minor) return res; } -/* get the vpe associated with this minor */ +/* get the tc associated with this minor */ static struct tc *get_tc(int index) { struct tc *res, *t; @@ -200,7 +236,8 @@ static struct vpe *alloc_vpe(int minor) if ((v = kzalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) return NULL; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct vpe), (unsigned int)v); INIT_LIST_HEAD(&v->tc); spin_lock(&vpecontrol.vpe_list_lock); list_add_tail(&v->list, &vpecontrol.vpe_list); @@ -219,7 +256,8 @@ static struct tc *alloc_tc(int index) if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) goto out; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct tc), (unsigned int)tc); INIT_LIST_HEAD(&tc->tc); tc->index = index; @@ -237,6 +275,11 @@ static void release_vpe(struct vpe *v) list_del(&v->list); if (v->load_addr) release_progmem(v); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v->l_phsort); + kfree(v->l_phsort); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v); kfree(v); } @@ -260,8 +303,88 @@ static void __maybe_unused dump_mtregs(void) val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); } +/* + * The original APRP prototype assumed a single, unshared IRQ for + * cross-VPE interrupts, used by the RTLX code. But M3P networking + * and other future functions may need to share an IRQ, particularly + * in 34K/Malta configurations without an external interrupt controller. + * All cross-VPE insterrupt users need to coordinate through shared + * functions here. + */ + +/* + * It would be nice if I could just have this initialized to zero, + * but the patchcheck police won't hear of it... + */ + +static int xvpe_vector_set; + +#define XVPE_INTR_OFFSET 0 + +static int xvpe_irq = MIPS_CPU_IRQ_BASE + XVPE_INTR_OFFSET; + +static void xvpe_dispatch(void) +{ + do_IRQ(xvpe_irq); +} + +/* Name here is generic, as m3pnet.c could in principle be used by non-MIPS */ +int arch_get_xcpu_irq() +{ + /* + * Some of this will ultimately become platform code, + * but for now, we're only targeting 34K/FPGA/Malta, + * and there's only one generic mechanism. + */ + if (!xvpe_vector_set) { + /* + * A more elaborate shared variable shouldn't be needed. + * Two initializations back-to-back should be harmless. + */ + if (cpu_has_vint) { + set_vi_handler(XVPE_INTR_OFFSET, xvpe_dispatch); + xvpe_vector_set = 1; + } else { + printk(KERN_ERR "APRP requires vectored interrupts\n"); + return -1; + } + } + + return xvpe_irq; +} +EXPORT_SYMBOL(arch_get_xcpu_irq); + +int vpe_send_interrupt(int vpe, int inter) +{ + unsigned long flags; + unsigned int vpeflags; + + local_irq_save(flags); + vpeflags = dvpe(); + + /* + * Initial version makes same simple-minded assumption + * as is implicit elsewhere in this module, that the + * only RP of interest is using the first non-Linux TC. + * We ignore the parameters provided by the caller! + */ + settc(tclimit); + /* + * In 34K/Malta, the only cross-VPE interrupts possible + * are done by setting SWINT bits in Cause, of which there + * are two. SMTC uses SW1 for a multiplexed class of IPIs, + * and this mechanism should be generalized to APRP and use + * the same protocol. Until that's implemented, send only + * SW0 here, regardless of requested type. + */ + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); + evpe(vpeflags); + local_irq_restore(flags); + return 1; +} +EXPORT_SYMBOL(vpe_send_interrupt); /* Find some VPE program space */ -static void *alloc_progmem(unsigned long len) +static void *alloc_progmem(void *requested, unsigned long len) { void *addr; @@ -271,10 +394,28 @@ static void *alloc_progmem(unsigned long len) * physically have, for example by passing a mem= boot argument. */ addr = pfn_to_kaddr(max_low_pfn); - memset(addr, 0, len); + if (requested != 0) { + if (requested >= addr) + addr = requested; + else + addr = 0; + } + if (addr != 0) + memset(addr, 0, len); + printk(KERN_DEBUG "pfn_to_kaddr returns %lu bytes of memory at %x\n", + len, (unsigned int)addr); #else - /* simple grab some mem for now */ - addr = kzalloc(len, GFP_KERNEL); + if (requested != 0) { + /* If we have a target in mind, grab a 2x slice and hope... */ + addr = kzalloc(len*2, GFP_KERNEL); + if ((requested >= addr) && (requested < (addr + len))) + addr = requested; + else + addr = 0; + } else { + /* simply grab some mem for now */ + addr = kzalloc(len, GFP_KERNEL); + } #endif return addr; @@ -446,6 +587,8 @@ static int apply_r_mips_hi16(struct module *me, uint32_t *location, * actual relocation. */ n = kmalloc(sizeof *n, GFP_KERNEL); + printk(KERN_DEBUG "Used kmalloc to allocate %d bytes at %x\n", + sizeof(struct mips_hi16), (unsigned int)n); if (!n) return -ENOMEM; @@ -503,6 +646,8 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, *l->addr = insn; next = l->next; + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)l); kfree(l); l = next; } @@ -596,7 +741,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs, return 0; } -static inline void save_gp_address(unsigned int secbase, unsigned int rel) +void save_gp_address(unsigned int secbase, unsigned int rel) { gp_addr = secbase + rel; gp_offs = gp_addr - (secbase & 0xffff0000); @@ -816,16 +961,41 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, struct module *mod) { Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; - unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); + unsigned int i, j, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); for (i = 1; i < n; i++) { - if (strcmp(strtab + sym[i].st_name, "__start") == 0) { - v->__start = sym[i].st_value; + if (strcmp(strtab + sym[i].st_name, "__start") == 0) + v->__start = sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) + v->shared_ptr = (void *)sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "_vpe_shared_areas") == 0) { + struct vpe_shared_area *psa + = (struct vpe_shared_area *)sym[i].st_value; + struct vpe_shared_area *tpsa; + v->shared_areas = psa; + printk(KERN_INFO"_vpe_shared_areas found, 0x%x\n", + (unsigned int)v->shared_areas); + /* + * Copy any "published" areas to the descriptor + */ + for (j = 0; j < N_PUB_AREAS; j++) { + if (published_vpe_area[j].type != VPE_SHARED_RESERVED) { + tpsa = psa; + while (tpsa->type != VPE_SHARED_NULL) { + if ((tpsa->type == VPE_SHARED_RESERVED) + || (tpsa->type == published_vpe_area[j].type)) { + tpsa->type = published_vpe_area[j].type; + tpsa->addr = published_vpe_area[j].addr; + break; + } + tpsa++; + } + } } + } - if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) { - v->shared_ptr = (void *)sym[i].st_value; - } } if ( (v->__start == 0) || (v->shared_ptr == NULL)) @@ -850,14 +1020,12 @@ static int vpe_elfload(struct vpe * v) memset(&mod, 0, sizeof(struct module)); strcpy(mod.name, "VPE loader"); - - hdr = (Elf_Ehdr *) v->pbuffer; - len = v->plen; + hdr = v->l_ehdr; + len = v->pbsize; /* Sanity checks against insmoding binaries or wrong arch, weird elf version */ - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0 - || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) + if ((hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) || !elf_check_arch(hdr) || hdr->e_shentsize != sizeof(*sechdrs)) { printk(KERN_WARNING @@ -869,9 +1037,8 @@ static int vpe_elfload(struct vpe * v) if (hdr->e_type == ET_REL) relocate = 1; - if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { - printk(KERN_ERR "VPE loader: program length %u truncated\n", - len); + if (len < v->l_phlen + v->l_shlen) { + printk(KERN_ERR "VPE loader: Headers exceed %u bytes\n", len); return -ENOEXEC; } @@ -905,9 +1072,13 @@ static int vpe_elfload(struct vpe * v) } } layout_sections(&mod, hdr, sechdrs, secstrings); + /* + * Non-relocatable loads should have already done their + * allocates, based on program header table. + */ } - v->load_addr = alloc_progmem(mod.core_size); + memset(v->load_addr, 0, mod.core_size); if (!v->load_addr) return -ENOMEM; @@ -960,19 +1131,10 @@ static int vpe_elfload(struct vpe * v) } } else { - struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); - - for (i = 0; i < hdr->e_phnum; i++) { - if (phdr->p_type == PT_LOAD) { - memcpy((void *)phdr->p_paddr, - (char *)hdr + phdr->p_offset, - phdr->p_filesz); - memset((void *)phdr->p_paddr + phdr->p_filesz, - 0, phdr->p_memsz - phdr->p_filesz); - } - phdr++; - } + /* + * Program image is already in memory. + */ for (i = 0; i < hdr->e_shnum; i++) { /* Internal symbols and strings. */ if (sechdrs[i].sh_type == SHT_SYMTAB) { @@ -989,7 +1151,7 @@ static int vpe_elfload(struct vpe * v) /* make sure it's physically written out */ flush_icache_range((unsigned long)v->load_addr, - (unsigned long)v->load_addr + v->len); + (unsigned long)v->load_addr + v->copied); if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { if (v->__start == 0) { @@ -1003,8 +1165,8 @@ static int vpe_elfload(struct vpe * v) "program does not contain vpe_shared symbol.\n" " Unable to use AMVP (AP/SP) facilities.\n"); } + pr_info("APRP VPE loader: elf loaded\n"); - printk(" elf loaded\n"); return 0; } @@ -1069,6 +1231,10 @@ static int vpe_open(struct inode *inode, struct file *filp) return -ENODEV; } + /* + * This treats the tclimit command line configuration input + * as a minor device indication, which is probably unwholesome. + */ if ((v = get_vpe(tclimit)) == NULL) { pr_warning("VPE loader: unable to get vpe\n"); @@ -1085,18 +1251,20 @@ static int vpe_open(struct inode *inode, struct file *filp) } release_progmem(v->load_addr); + kfree(v->l_phsort); cleanup_tc(get_tc(tclimit)); } /* this of-course trashes what was there before... */ v->pbuffer = vmalloc(P_SIZE); - if (!v->pbuffer) { - pr_warning("VPE loader: unable to allocate memory\n"); - return -ENOMEM; - } - v->plen = P_SIZE; v->load_addr = NULL; - v->len = 0; + v->copied = 0; + v->offset = 0; + v->l_state = LOAD_STATE_EHDR; + v->l_ehdr = NULL; + v->l_phdr = NULL; + v->l_phsort = NULL; + v->l_shdr = NULL; v->uid = filp->f_cred->fsuid; v->gid = filp->f_cred->fsgid; @@ -1115,6 +1283,7 @@ static int vpe_open(struct inode *inode, struct file *filp) printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret); v->shared_ptr = NULL; + v->shared_areas = NULL; v->__start = 0; return 0; @@ -1123,26 +1292,39 @@ static int vpe_open(struct inode *inode, struct file *filp) static int vpe_release(struct inode *inode, struct file *filp) { struct vpe *v; - Elf_Ehdr *hdr; int ret = 0; v = get_vpe(tclimit); if (v == NULL) return -ENODEV; + /* + * If image load had no errors, massage program/section tables + * to reflect movement of program/section data into VPE program + * memory. + */ + if (v->l_state != LOAD_STATE_DONE) { + printk(KERN_WARNING "VPE Release after incomplete load\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); + return -ENOEXEC; + } - hdr = (Elf_Ehdr *) v->pbuffer; - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) { - if (vpe_elfload(v) >= 0) { - vpe_run(v); - } else { - printk(KERN_WARNING "VPE loader: ELF load failed.\n"); - ret = -ENOEXEC; - } + if (vpe_elfload(v) >= 0) { + vpe_run(v); } else { - printk(KERN_WARNING "VPE loader: only elf files are supported\n"); + printk(KERN_WARNING "VPE loader: ELF load failed.\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); ret = -ENOEXEC; } + /* It's good to be able to run the SP and if it chokes have a look at the /dev/rt?. But if we reset the pointer to the shared struct we lose what has happened. So perhaps if garbage is sent to the vpe @@ -1151,17 +1333,68 @@ static int vpe_release(struct inode *inode, struct file *filp) if (ret < 0) v->shared_ptr = NULL; - vfree(v->pbuffer); - v->plen = 0; - + // cleanup any temp buffers + if (v->pbuffer) { + printk(KERN_DEBUG "Used vfree to free memory at %x\n", + (unsigned int)v->pbuffer); + vfree(v->pbuffer); + } + v->pbsize = 0; return ret; } +/* + * A sort of insertion sort to generate list of program header indices + * in order of their file offsets. + */ + +static void indexort(struct elf_phdr *phdr, int nph, int *index) +{ + int i, j, t; + unsigned int toff; + + /* Create initial mapping */ + for (i = 0; i < nph; i++) + index[i] = i; + /* Do the indexed insert sort */ + for (i = 1; i < nph; i++) { + j = i; + t = index[j]; + toff = phdr[t].p_offset; + while ((j > 0) && (phdr[index[j-1]].p_offset > toff)) { + index[j] = index[j-1]; + j--; + } + index[j] = t; + } +} + + +/* + * This function has to convert the ELF file image being sequentially + * streamed to the pseudo-device into the binary image, symbol, and + * string information, which the ELF format allows to be in some degree + * of disorder. + * + * The ELF header and, if present, program header table, are copied into + * a temporary buffer. Loadable program segments, if present, are copied + * into the RP program memory at the addresses specified by the program + * header table. + * + * Sections not specified by the program header table are loaded into + * memory following the program segments if they are "allocated", or + * into the temporary buffer if they are not. The section header + * table is loaded into the temporary buffer.??? + */ +#define CURPHDR (v->l_phdr[v->l_phsort[v->l_cur_seg]]) static ssize_t vpe_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos) { size_t ret = count; struct vpe *v; + int tocopy, uncopied; + int i; + unsigned int progmemlen; if (iminor(file->f_path.dentry->d_inode) != minor) return -ENODEV; @@ -1170,17 +1403,357 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, if (v == NULL) return -ENODEV; - if ((count + v->len) > v->plen) { - printk(KERN_WARNING - "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + if (v->pbuffer == NULL) { + printk(KERN_ERR "VPE loader: no buffer for program\n"); return -ENOMEM; } - count -= copy_from_user(v->pbuffer + v->len, buffer, count); - if (!count) - return -EFAULT; + while (count) { + switch (v->l_state) { + case LOAD_STATE_EHDR: + /* Loading ELF Header into scratch buffer */ + tocopy = min((unsigned long)count, + sizeof(Elf_Ehdr) - v->offset); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->copied == sizeof(Elf_Ehdr)) { + v->l_ehdr = (Elf_Ehdr *)v->pbuffer; + if (memcmp(v->l_ehdr->e_ident, ELFMAG, 4) != 0) { + printk(KERN_WARNING "VPE loader: %s\n", + "non-ELF file image"); + ret = -ENOEXEC; + v->l_state = LOAD_STATE_ERROR; + break; + } + if (v->l_ehdr->e_phoff != 0) { + v->l_phdr = (struct elf_phdr *) + (v->pbuffer + v->l_ehdr->e_phoff); + v->l_phlen = v->l_ehdr->e_phentsize + * v->l_ehdr->e_phnum; + /* Check against buffer overflow */ + if ((v->copied + v->l_phlen) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf program header table size too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_PHDR; + /* + * Program headers generally indicate + * linked executable with possibly + * valid entry point. + */ + v->__start = v->l_ehdr->e_entry; + } else if (v->l_ehdr->e_shoff != 0) { + /* + * No program headers, but a section + * header table. A relocatable binary. + * We need to load the works into the + * kernel temp buffer to compute the + * RP program image. That limits our + * binary size, but at least we're no + * worse off than the original APRP + * prototype. + */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big.\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + } else { + /* + * If neither program nor section tables, + * we don't know what to do. + */ + v->l_state = LOAD_STATE_ERROR; + return -ENOEXEC; + } + } + break; + case LOAD_STATE_PHDR: + /* Loading Program Headers into scratch */ + tocopy = min((unsigned long)count, + v->l_ehdr->e_phoff + v->l_phlen - v->copied); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + + if (v->copied == v->l_ehdr->e_phoff + v->l_phlen) { + /* + * It's legal for the program headers to be + * out of order with respect to the file layout. + * Generate a list of indices, sorted by file + * offset. + */ + v->l_phsort = kmalloc(v->l_ehdr->e_phnum + * sizeof(int), GFP_KERNEL); + printk(KERN_DEBUG + "Used kmalloc to allocate %d bytes of memory at %x\n", + v->l_ehdr->e_phnum*sizeof(int), + (unsigned int)v->l_phsort); + if (!v->l_phsort) + return -ENOMEM; /* Preposterous, but... */ + indexort(v->l_phdr, v->l_ehdr->e_phnum, + v->l_phsort); + + v->l_progminad = (unsigned int)-1; + v->l_progmaxad = 0; + progmemlen = 0; + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + /* Unstripped .reginfo sections are bad */ + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "User-mode p_vaddr, ", + "skipping program segment,"); + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "strip .reginfo from binary ", + "if necessary."); + continue; + } + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < v->l_progminad) + v->l_progminad = + v->l_phdr[v->l_phsort[i]].p_vaddr; + if ((v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz) + > v->l_progmaxad) + v->l_progmaxad = + v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz; + } + } + printk(KERN_INFO "APRP RP program 0x%x to 0x%x\n", + v->l_progminad, v->l_progmaxad); + /* + * Do a simple sanity check of the memory being + * allocated. Abort if greater than an arbitrary + * value of 32MB + */ + if (v->l_progmaxad - v->l_progminad > + 32*1024*1024) { + printk(KERN_WARNING + "RP program failed to allocate %d kbytes - limit is 32,768 KB\n", + (v->l_progmaxad - v->l_progminad)/1024); + return -ENOMEM; + } + + v->load_addr = alloc_progmem((void *)v->l_progminad, + v->l_progmaxad - v->l_progminad); + if (!v->load_addr) + return -ENOMEM; + if ((unsigned int)v->load_addr + > v->l_progminad) { + release_progmem(v->load_addr); + return -ENOMEM; + } + /* Find first segment with loadable content */ + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + if (i == v->l_ehdr->e_phnum) { + /* No loadable program segment? Bogus file. */ + printk(KERN_WARNING "Bad ELF file for APRP\n"); + return -ENOEXEC; + } + v->l_segoff = 0; + v->l_state = LOAD_STATE_PIMAGE; + } + break; + case LOAD_STATE_PIMAGE: + /* + * Skip through input stream until + * first program segment. Would be + * better to have loaded up to here + * into the temp buffer, but for now + * we simply rule out "interesting" + * sections prior to the last program + * segment in an executable file. + */ + if (v->offset < CURPHDR.p_offset) { + uncopied = CURPHDR.p_offset - v->offset; + if (uncopied > count) + uncopied = count; + count -= uncopied; + buffer += uncopied; + v->offset += uncopied; + /* Go back through the "while" */ + break; + } + /* + * Having dispensed with any unlikely fluff, + * copy from user I/O buffer to program segment. + */ + tocopy = min(count, CURPHDR.p_filesz - v->l_segoff); + + /* Loading image into RP memory */ + uncopied = copy_from_user((char *)CURPHDR.p_vaddr + + v->l_segoff, buffer, tocopy); + count -= tocopy - uncopied; + v->offset += tocopy - uncopied; + v->l_segoff += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->l_segoff >= CURPHDR.p_filesz) { + /* Finished current segment load */ + /* Zero out non-file-sourced image */ + uncopied = CURPHDR.p_memsz - CURPHDR.p_filesz; + if (uncopied > 0) + memset((char *)CURPHDR.p_vaddr + v->l_segoff, + 0, uncopied); + /* Advance to next segment */ + for (i = v->l_cur_seg + 1; + i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + /* If none left, prepare to load section headers */ + if (i == v->l_ehdr->e_phnum) { + if (v->l_ehdr->e_shoff != 0) { + /* Copy to where we left off in temp buffer */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + break; + } + } else { + /* reset offset for new program segment */ + v->l_segoff = 0; + } + } + break; + case LOAD_STATE_SHDR: + /* + * Read stream into private buffer up + * through and including the section header + * table. + */ - v->len += count; + tocopy = min((unsigned long)count, + v->l_ehdr->e_shoff + v->l_shlen - v->offset); + if (tocopy) { + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + /* Finished? */ + if (v->offset == v->l_ehdr->e_shoff + v->l_shlen) { + unsigned int offset_delta = v->offset - v->copied; + + v->l_shdr = (Elf_Shdr *)(v->pbuffer + + v->l_ehdr->e_shoff - offset_delta); + /* + * Check for sections after the section table, + * which for gcc MIPS binaries includes + * the symbol table. Do any other processing + * that requires value within stream, and + * normalize offsets to be relative to + * the header-only layout of temp buffer. + */ + + /* Assume no trailer until we detect one */ + v->l_trailer = 0; + v->l_state = LOAD_STATE_DONE; + for (i = 0; i < v->l_ehdr->e_shnum; i++) { + if (v->l_shdr[i].sh_offset + > v->l_ehdr->e_shoff) { + v->l_state = LOAD_STATE_TRAILER; + /* Track trailing data length */ + if (v->l_trailer + < (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen)) + v->l_trailer = + (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen); + } + /* Adjust section offset if necessary */ + v->l_shdr[i].sh_offset -= offset_delta; + } + if ((v->copied + v->l_trailer) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + + /* Fix up offsets in ELF header */ + v->l_ehdr->e_shoff = (unsigned int)v->l_shdr + - (unsigned int)v->pbuffer; + } + break; + case LOAD_STATE_TRAILER: + /* + * Symbol and string tables follow section headers + * in gcc binaries for MIPS. Copy into temp buffer. + */ + if (v->l_trailer) { + tocopy = min(count, v->l_trailer); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->l_trailer -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + if (!v->l_trailer) + v->l_state = LOAD_STATE_DONE; + break; + case LOAD_STATE_DONE: + if (count) + count = 0; + break; + case LOAD_STATE_ERROR: + default: + return -EINVAL; + } + } return ret; } @@ -1216,7 +1789,9 @@ int vpe_start(vpe_handle vpe, unsigned long start) { struct vpe *v = vpe; - v->__start = start; + /* Null start address means use value from ELF file */ + if (start) + v->__start = start; return vpe_run(v); } @@ -1341,6 +1916,99 @@ char *vpe_getcwd(int index) EXPORT_SYMBOL(vpe_getcwd); +/* + * RP applications may contain a _vpe_shared_area descriptor + * array to allow for data sharing with Linux kernel functions + * that's slightly more abstracted and extensible than the + * fixed binding used by the rtlx support. Indeed, the rtlx + * support should ideally be converted to use the generic + * shared area descriptor scheme at some point. + * + * mips_get_vpe_shared_area() can be used by AP kernel + * modules to get an area pointer of a given type, if + * it exists. + * + * mips_publish_vpe_area() is used by AP kernel modules + * to share kseg0 kernel memory with the RP. It maintains + * a private table, so that publishing can be done before + * the RP program is launched. Making this table dynamically + * allocated and extensible would be good scalable OS design. + * however, until there's more than one user of the mechanism, + * it should be an acceptable simplification to allow a static + * maximum of 4 published areas. + */ + +void *mips_get_vpe_shared_area(int index, int type) +{ + struct vpe *v; + struct vpe_shared_area *vsa; + + v = get_vpe(index); + if (v == NULL) + return NULL; + + if (v->shared_areas == NULL) + return NULL; + + vsa = v->shared_areas; + + while (vsa->type != VPE_SHARED_NULL) { + if (vsa->type == type) + return vsa->addr; + else + vsa++; + } + /* Fell through without finding type */ + + return NULL; +} +EXPORT_SYMBOL(mips_get_vpe_shared_area); + +int mips_publish_vpe_area(int type, void *ptr) +{ + int i; + int retval = 0; + struct vpe *v; + unsigned long flags; + unsigned int vpflags; + + printk(KERN_INFO "mips_publish_vpe_area(0x%x, 0x%x)\n", type, (int)ptr); + if ((unsigned int)ptr >= KSEG2) { + printk(KERN_ERR "VPE area pubish of invalid address 0x%x\n", + (int)ptr); + return 0; + } + for (i = 0; i < N_PUB_AREAS; i++) { + if (published_vpe_area[i].type == VPE_SHARED_RESERVED) { + published_vpe_area[i].type = type; + published_vpe_area[i].addr = ptr; + retval = type; + break; + } + } + /* + * If we've already got a VPE up and running, try to + * update the shared descriptor with the new data. + */ + list_for_each_entry(v, &vpecontrol.vpe_list, list) { + if (v->shared_areas != NULL) { + local_irq_save(flags); + vpflags = dvpe(); + for (i = 0; v->shared_areas[i].type != VPE_SHARED_NULL; i++) { + if ((v->shared_areas[i].type == type) + || (v->shared_areas[i].type == VPE_SHARED_RESERVED)) { + v->shared_areas[i].type = type; + v->shared_areas[i].addr = ptr; + } + } + evpe(vpflags); + local_irq_restore(flags); + } + } + return retval; +} +EXPORT_SYMBOL(mips_publish_vpe_area); + #ifdef CONFIG_MIPS_APSP_KSPD static void kspd_sp_exit( int sp_id) { @@ -1359,6 +2027,7 @@ static ssize_t store_kill(struct device *dev, struct device_attribute *attr, } release_progmem(vpe->load_addr); + kfree(vpe->l_phsort); cleanup_tc(get_tc(tclimit)); vpe_stop(vpe); vpe_free(vpe); @@ -1404,6 +2073,8 @@ static struct device_attribute vpe_class_attributes[] = { static void vpe_device_release(struct device *cd) { + printk(KERN_DEBUG "Using kfree to free vpe class device at %x\n", + (unsigned int)cd); kfree(cd); } @@ -1430,19 +2101,24 @@ static int __init vpe_module_init(void) } if (vpelimit == 0) { - printk(KERN_WARNING "No VPEs reserved for AP/SP, not " - "initializing VPE loader.\nPass maxvpes= argument as " - "kernel argument\n"); - +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) + printk(KERN_WARNING "No VPEs reserved for VPE loader.\n" + "Pass maxvpes= argument as kernel argument\n"); return -ENODEV; +#else + vpelimit = 1; +#endif } if (tclimit == 0) { +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) printk(KERN_WARNING "No TCs reserved for AP/SP, not " "initializing VPE loader.\nPass maxtcs= argument as " "kernel argument\n"); - return -ENODEV; +#else + tclimit = 1; +#endif } major = register_chrdev(0, module_name, &vpe_fops); @@ -1456,7 +2132,7 @@ static int __init vpe_module_init(void) printk(KERN_ERR "vpe_class registration failed\n"); goto out_chrdev; } - + xvpe_vector_set = 0; device_initialize(&vpe_device); vpe_device.class = &vpe_class, vpe_device.parent = NULL, -- 1.7.10 From sjhill@mips.com Thu May 10 23:31:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 May 2012 23:31:14 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:60882 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903691Ab2EJVbF (ORCPT ); Thu, 10 May 2012 23:31:05 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SSaws-00011O-I3; Thu, 10 May 2012 16:30:58 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH v2,5/5] MIPS: Add option to disable software I/O coherency. Date: Thu, 10 May 2012 16:30:46 -0500 Message-Id: <1336685446-25532-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10 X-archive-position: 33235 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7626 Lines: 259 From: "Steven J. Hill" Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mach-generic/dma-coherence.h | 4 +- arch/mips/mm/c-r4k.c | 21 +--- arch/mips/mm/dma-default.c | 8 +- arch/mips/mti-malta/malta-memory.c | 2 +- arch/mips/mti-malta/malta-setup.c | 102 ++++++++++++++++++++ 5 files changed, 117 insertions(+), 20 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177..9f1cd31 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -63,7 +63,9 @@ static inline int plat_device_is_coherent(struct device *dev) return 1; #endif #ifdef CONFIG_DMA_NONCOHERENT - return 0; + extern int coherentio; + + return coherentio; #endif } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c646a79..07ca54c 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1389,26 +1389,13 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; - -static int __init setcoherentio(char *str) -{ - coherentio = 1; - - return 1; -} - -__setup("coherentio", setcoherentio); -#endif - void __cpuinit r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); extern char __weak except_vec2_generic; extern char __weak except_vec2_sb1; + extern int coherentio; struct cpuinfo_mips *c = ¤t_cpu_data; switch (c->cputype) { @@ -1479,8 +1466,10 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* We want to run CMP kernels on core(s) with and without coherent caches */ + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 3fab204..058c2ca 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -100,6 +100,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); static void *mips_dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) { + extern int hw_coherentio; void *ret; if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) @@ -115,7 +116,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, if (!plat_device_is_coherent(dev)) { dma_cache_wback_inv((unsigned long) ret, size); - ret = UNCAC_ADDR(ret); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } } @@ -134,6 +136,7 @@ EXPORT_SYMBOL(dma_free_noncoherent); static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs) { + extern int hw_coherentio; unsigned long addr = (unsigned long) vaddr; int order = get_order(size); @@ -143,7 +146,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) - addr = CAC_ADDR(addr); + if (!hw_coherentio) + addr = CAC_ADDR(addr); free_pages(addr, get_order(size)); } diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index a96d281..d57a233 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -158,7 +158,7 @@ void __init prom_meminit(void) size = p->size; add_memory_region(base, size, type); - p++; + p++; } } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index b45b343..4ca09bf 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -32,6 +32,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -105,6 +106,105 @@ static void __init fd_activate(void) } #endif +int coherentio = -1; /* no DMA cache coherency (may be set by user) */ +int hw_coherentio; /* init to 0 => no HW DMA cache coherency (reflects real HW) */ +static int __init setcoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); + return 1; +} +__setup("coherentio", setcoherentio); + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 1; +} +__setup("nocoherentio", setnocoherentio); + +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(prom_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + hw_coherentio = supported; + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -207,6 +307,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif -- 1.7.10 From sjhill@mips.com Fri May 11 05:20:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 May 2012 05:20:34 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:33745 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903543Ab2EKDUU (ORCPT ); Fri, 11 May 2012 05:20:20 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SSgOp-0001a7-06; Thu, 10 May 2012 22:20:11 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Douglas Leung , Chris Dearman Subject: [PATCH v3,01/10] MIPS: Add core files for MIPS SEAD-3 development platform. Date: Thu, 10 May 2012 22:20:01 -0500 Message-Id: <1336706401-27530-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.10 X-archive-position: 33236 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 77354 Lines: 2812 From: "Steven J. Hill" More information about the SEAD-3 platform can be found at on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- .../include/asm/mach-sead3/cpu-feature-overrides.h | 72 ++++ arch/mips/include/asm/mach-sead3/irq.h | 9 + .../include/asm/mach-sead3/kernel-entry-init.h | 52 +++ arch/mips/include/asm/mach-sead3/war.h | 25 ++ arch/mips/include/asm/mips-boards/sead3int.h | 67 +++ arch/mips/mti-sead3/Makefile | 24 ++ arch/mips/mti-sead3/Platform | 7 + arch/mips/mti-sead3/leds-sead3.c | 133 ++++++ arch/mips/mti-sead3/sead3-cmdline.c | 59 +++ arch/mips/mti-sead3/sead3-console.c | 52 +++ arch/mips/mti-sead3/sead3-display.c | 90 ++++ arch/mips/mti-sead3/sead3-ehci.c | 52 +++ arch/mips/mti-sead3/sead3-i2c-dev.c | 38 ++ arch/mips/mti-sead3/sead3-i2c.c | 42 ++ arch/mips/mti-sead3/sead3-init.c | 244 +++++++++++ arch/mips/mti-sead3/sead3-int.c | 146 +++++++ arch/mips/mti-sead3/sead3-lcd.c | 55 +++ arch/mips/mti-sead3/sead3-leds.c | 91 ++++ arch/mips/mti-sead3/sead3-memory.c | 178 ++++++++ arch/mips/mti-sead3/sead3-mtd.c | 58 +++ arch/mips/mti-sead3/sead3-net.c | 56 +++ arch/mips/mti-sead3/sead3-pic32-bus.c | 112 +++++ arch/mips/mti-sead3/sead3-pic32-i2c-drv.c | 441 ++++++++++++++++++++ arch/mips/mti-sead3/sead3-platform.c | 49 +++ arch/mips/mti-sead3/sead3-reset.c | 64 +++ arch/mips/mti-sead3/sead3-setup.c | 49 +++ arch/mips/mti-sead3/sead3-smtc.c | 162 +++++++ arch/mips/mti-sead3/sead3-time.c | 145 +++++++ 28 files changed, 2572 insertions(+) create mode 100644 arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-sead3/irq.h create mode 100644 arch/mips/include/asm/mach-sead3/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-sead3/war.h create mode 100644 arch/mips/include/asm/mips-boards/sead3int.h create mode 100644 arch/mips/mti-sead3/Makefile create mode 100644 arch/mips/mti-sead3/Platform create mode 100644 arch/mips/mti-sead3/leds-sead3.c create mode 100644 arch/mips/mti-sead3/sead3-cmdline.c create mode 100644 arch/mips/mti-sead3/sead3-console.c create mode 100644 arch/mips/mti-sead3/sead3-display.c create mode 100644 arch/mips/mti-sead3/sead3-ehci.c create mode 100644 arch/mips/mti-sead3/sead3-i2c-dev.c create mode 100644 arch/mips/mti-sead3/sead3-i2c.c create mode 100644 arch/mips/mti-sead3/sead3-init.c create mode 100644 arch/mips/mti-sead3/sead3-int.c create mode 100644 arch/mips/mti-sead3/sead3-lcd.c create mode 100644 arch/mips/mti-sead3/sead3-leds.c create mode 100644 arch/mips/mti-sead3/sead3-memory.c create mode 100644 arch/mips/mti-sead3/sead3-mtd.c create mode 100644 arch/mips/mti-sead3/sead3-net.c create mode 100644 arch/mips/mti-sead3/sead3-pic32-bus.c create mode 100644 arch/mips/mti-sead3/sead3-pic32-i2c-drv.c create mode 100644 arch/mips/mti-sead3/sead3-platform.c create mode 100644 arch/mips/mti-sead3/sead3-reset.c create mode 100644 arch/mips/mti-sead3/sead3-setup.c create mode 100644 arch/mips/mti-sead3/sead3-smtc.c create mode 100644 arch/mips/mti-sead3/sead3-time.c diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h new file mode 100644 index 0000000..7f3e3f9 --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h @@ -0,0 +1,72 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Chris Dearman + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H + + +/* + * CPU feature overrides for MIPS boards + */ +#ifdef CONFIG_CPU_MIPS32 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#ifdef CONFIG_CPU_HAS_LLSC +#define cpu_has_llsc 1 +#else +#define cpu_has_llsc 0 +#endif +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#ifdef CONFIG_CPU_MIPS64 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#define cpu_has_llsc 1 +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h new file mode 100644 index 0000000..652ea4c --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/irq.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_MIPS_IRQ_H +#define __ASM_MACH_MIPS_IRQ_H + +#define NR_IRQS 256 + + +#include_next + +#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h new file mode 100644 index 0000000..3dfbd8e --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Chris Dearman (chris@mips.com) + * Copyright (C) 2007 Mips Technologies, Inc. + */ +#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H +#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H + + .macro kernel_entry_setup +#ifdef CONFIG_MIPS_MT_SMTC + mfc0 t0, CP0_CONFIG + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 1 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 2 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 3 + and t0, 1<<2 + bnez t0, 0f +9 : + /* Assume we came from YAMON... */ + PTR_LA v0, 0x9fc00534 /* YAMON print */ + lw v0, (v0) + move a0, zero + PTR_LA a1, nonmt_processor + jal v0 + + PTR_LA v0, 0x9fc00520 /* YAMON exit */ + lw v0, (v0) + li a0, 1 + jal v0 + +1 : b 1b + + __INITDATA +nonmt_processor : + .asciz "SMTC kernel requires the MT ASE to run\n" + __FINIT +0 : +#endif + .endm + +/* + * Do SMP slave processor setup necessary before we can safely execute C code. + */ + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h new file mode 100644 index 0000000..7c6931d --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h new file mode 100644 index 0000000..2563b82 --- /dev/null +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -0,0 +1,67 @@ +/* + * Douglas Leung, douglas@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Defines for the SEAD3 interrupt controller. + * + */ +#ifndef _MIPS_SEAD3INT_H +#define _MIPS_SEAD3INT_H + +/* + * SEAD3 GIC's address space definitions + */ +#define GIC_BASE_ADDR 0x1b1c0000 +#define GIC_ADDRSPACE_SZ (128 * 1024) + +/* GIC's Nomenclature for Core Interrupt Pins on the SEAD3 */ +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ +#define GIC_CPU_INT1 1 /* . */ +#define GIC_CPU_INT2 2 /* . */ +#define GIC_CPU_INT3 3 /* . */ +#define GIC_CPU_INT4 4 /* . */ +#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ + +/* SEAD3 GIC local interrupts */ +#define GIC_INT_TMR (GIC_CPU_INT5) +#define GIC_INT_PERFCTR (GIC_CPU_INT5) + +/* SEAD3 GIC constants */ +/* Add 2 to convert non-eic hw int # to eic vector # */ +#define GIC_CPU_TO_VEC_OFFSET (2) + +/* GIC constants */ +/* If we map an intr to pin X, GIC will actually generate vector X+1 */ +#define GIC_PIN_TO_VEC_OFFSET (1) + +#define GIC_EXT_INTR(x) x + +/* Dummy data */ +#define X 0xdead + +/* External Interrupts used for IPI */ +/* Currently linux don't know about GIC => GIC base must be same as what Linux is using */ +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) + +#ifndef __ASSEMBLY__ +extern void sead3int_init(void); +#endif + +#endif /* !(_MIPS_SEAD3INT_H) */ diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile new file mode 100644 index 0000000..8797977 --- /dev/null +++ b/arch/mips/mti-sead3/Makefile @@ -0,0 +1,24 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# Copyright (C) 2008 Wind River Systems, Inc. +# written by Ralf Baechle +# +obj-y := sead3-lcd.o sead3-cmdline.o \ + sead3-display.o sead3-init.o sead3-int.o \ + sead3-mtd.o sead3-net.o \ + sead3-memory.o sead3-platform.o \ + sead3-reset.o sead3-setup.o sead3-time.o + +obj-y += sead3-i2c-dev.o sead3-i2c.o \ + sead3-pic32-i2c-drv.o sead3-pic32-bus.o \ + leds-sead3.o sead3-leds.o + +obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o +obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o + +# FIXME +obj-$(CONFIG_MIPS_MT_SMTC) += sead3-smtc.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mti-sead3/Platform b/arch/mips/mti-sead3/Platform new file mode 100644 index 0000000..596e484 --- /dev/null +++ b/arch/mips/mti-sead3/Platform @@ -0,0 +1,7 @@ +# +# MIPS Sead3 board +# +platform-$(CONFIG_MIPS_SEAD3) += mti-sead3/ +cflags-$(CONFIG_MIPS_SEAD3) += -I$(srctree)/arch/mips/include/asm/mach-sead3 +load-$(CONFIG_MIPS_SEAD3) += 0xffffffff80100000 +all-$(CONFIG_MIPS_SEAD3) := $(COMPRESSION_FNAME).srec diff --git a/arch/mips/mti-sead3/leds-sead3.c b/arch/mips/mti-sead3/leds-sead3.c new file mode 100644 index 0000000..89954ce --- /dev/null +++ b/arch/mips/mti-sead3/leds-sead3.c @@ -0,0 +1,133 @@ +/* + * LEDs driver for SEAD3 + * + * Copyright (C) 2006 Kristian Kielhofner + * + * Based on leds-wrap.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "sead3-led" + +static struct platform_device *pdev; + +static void sead3_pled_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + pr_debug("sead3_pled_set\n"); + writel(value, (void __iomem *)0xBF000210); /* FIXME */ +} + +static void sead3_fled_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + pr_debug("sead3_fled_set\n"); + writel(value, (void __iomem *)0xBF000218); /* FIXME */ +} + +static struct led_classdev sead3_pled = { + .name = "sead3::pled", + .brightness_set = sead3_pled_set, +}; + +static struct led_classdev sead3_fled = { + .name = "sead3::fled", + .brightness_set = sead3_fled_set, +}; + +#ifdef CONFIG_PM +static int sead3_led_suspend(struct platform_device *dev, + pm_message_t state) +{ + led_classdev_suspend(&sead3_pled); + led_classdev_suspend(&sead3_fled); + return 0; +} + +static int sead3_led_resume(struct platform_device *dev) +{ + led_classdev_resume(&sead3_pled); + led_classdev_resume(&sead3_fled); + return 0; +} +#else +#define sead3_led_suspend NULL +#define sead3_led_resume NULL +#endif + +static int sead3_led_probe(struct platform_device *pdev) +{ + int ret; + + ret = led_classdev_register(&pdev->dev, &sead3_pled); + if (ret < 0) + return ret; + + ret = led_classdev_register(&pdev->dev, &sead3_fled); + if (ret < 0) + led_classdev_unregister(&sead3_pled); + + return ret; +} + +static int sead3_led_remove(struct platform_device *pdev) +{ + led_classdev_unregister(&sead3_pled); + led_classdev_unregister(&sead3_fled); + return 0; +} + +static struct platform_driver sead3_led_driver = { + .probe = sead3_led_probe, + .remove = sead3_led_remove, + .suspend = sead3_led_suspend, + .resume = sead3_led_resume, + .driver = { + .name = DRVNAME, + .owner = THIS_MODULE, + }, +}; + +static int __init sead3_led_init(void) +{ + int ret; + + ret = platform_driver_register(&sead3_led_driver); + if (ret < 0) + goto out; + + pdev = platform_device_register_simple(DRVNAME, -1, NULL, 0); + if (IS_ERR(pdev)) { + ret = PTR_ERR(pdev); + platform_driver_unregister(&sead3_led_driver); + goto out; + } + +out: + return ret; +} + +static void __exit sead3_led_exit(void) +{ + platform_device_unregister(pdev); + platform_driver_unregister(&sead3_led_driver); +} + +module_init(sead3_led_init); +module_exit(sead3_led_exit); + +MODULE_AUTHOR("Kristian Kielhofner "); +MODULE_DESCRIPTION("SEAD3 LED driver"); +MODULE_LICENSE("GPL"); + diff --git a/arch/mips/mti-sead3/sead3-cmdline.c b/arch/mips/mti-sead3/sead3-cmdline.c new file mode 100644 index 0000000..8d6ad39 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-cmdline.c @@ -0,0 +1,59 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Kernel command line creation using the prom monitor (YAMON) argc/argv. + */ +#include +#include + +#include + +extern int prom_argc; +extern int *_prom_argv; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while (actr < prom_argc) { + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) { + /* get rid of trailing space */ + --cp; + *cp = '\0'; + } +} diff --git a/arch/mips/mti-sead3/sead3-console.c b/arch/mips/mti-sead3/sead3-console.c new file mode 100644 index 0000000..a799a5d --- /dev/null +++ b/arch/mips/mti-sead3/sead3-console.c @@ -0,0 +1,52 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include +#include +#include +#include + + +#define SEAD_UART1_REGS_BASE 0xbf000800 /* ttyS1 = RS232 port */ +#define SEAD_UART0_REGS_BASE 0xbf000900 /* ttyS0 = USB port */ + +#define PORT(base_addr, offset) ((unsigned int __iomem *)(base_addr+(offset)*4)) + +static inline unsigned int serial_in(int offset, unsigned int base_addr) +{ + return __raw_readl(PORT(base_addr, offset)) & 0xff; +} + +static inline void serial_out(int offset, int value, unsigned int base_addr) +{ + __raw_writel(value, PORT(base_addr, offset)); +} + +int prom_putchar(char c, char port) +{ + unsigned int base_addr; + + base_addr = port ? SEAD_UART1_REGS_BASE : SEAD_UART0_REGS_BASE; + + while ((serial_in(UART_LSR, base_addr) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c, base_addr); + + return 1; +} diff --git a/arch/mips/mti-sead3/sead3-display.c b/arch/mips/mti-sead3/sead3-display.c new file mode 100644 index 0000000..f6e2231 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-display.c @@ -0,0 +1,90 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#include +#include +#include +#include +#include + +extern const char display_string[]; +static unsigned int display_count; +static unsigned int max_display_count; + +#define DISPLAY_LCDINSTRUCTION (0*2) +#define DISPLAY_LCDDATA (1*2) +#define DISPLAY_CPLDSTATUS (2*2) +#define DISPLAY_CPLDDATA (3*2) +#define LCD_SETDDRAM 0x80 +#define LCD_IR_BF 0x80 + +static void lcd_wait(unsigned int __iomem *display) +{ + /* wait for CPLD state machine to become idle */ + do { + } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); + + do { + __raw_readl(display + DISPLAY_LCDINSTRUCTION); + + /* wait for CPLD state machine to become idle */ + do { + } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); + } while (__raw_readl(display + DISPLAY_CPLDDATA) & LCD_IR_BF); +} + +void mips_display_message(const char *str) +{ + static unsigned int __iomem *display; /* static => auto initialized to NULL */ + int i; + char ch; + + if (unlikely(display == NULL)) + display = ioremap_nocache(LCD_DISPLAY_POS_BASE, 4*2*sizeof(int)); + + for (i = 0; i < 16; i++) { + if (*str) + ch = *str++; + else + ch = ' '; + lcd_wait(display); + __raw_writel(LCD_SETDDRAM | i, display + DISPLAY_LCDINSTRUCTION); + lcd_wait(display); + __raw_writel(ch, display + DISPLAY_LCDDATA); + } +} + +static void scroll_display_message(unsigned long data); +static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0); + +static void scroll_display_message(unsigned long data) +{ + mips_display_message(&display_string[display_count++]); + if (display_count == max_display_count) + display_count = 0; + + mod_timer(&mips_scroll_timer, jiffies + HZ); +} + +void mips_scroll_message(void) +{ + del_timer_sync(&mips_scroll_timer); + max_display_count = strlen(display_string) + 1 - 16; + mod_timer(&mips_scroll_timer, jiffies + 1); +} diff --git a/arch/mips/mti-sead3/sead3-ehci.c b/arch/mips/mti-sead3/sead3-ehci.c new file mode 100644 index 0000000..cf4d93c --- /dev/null +++ b/arch/mips/mti-sead3/sead3-ehci.c @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 MIPS Technologies, vInc. + * written by Chris Dearman (chris@mips.com) + * + * Probe driver for the SEAD3 EHCI device + * + */ +#include +#include +#include +#include +#include + +struct resource ehci_resources[] = { + { + .start = 0x1b200000, + .end = 0x1b200fff, + .flags = IORESOURCE_MEM + }, + { + .start = MIPS_CPU_IRQ_BASE + 2, + .flags = IORESOURCE_IRQ + } +}; + +u64 sead3_usbdev_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device ehci_device = { + .name = "sead3-ehci", + .id = 0, + .dev = { + .dma_mask = &sead3_usbdev_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32) + }, + .num_resources = ARRAY_SIZE(ehci_resources), + .resource = ehci_resources +}; + +static int __init ehci_init(void) +{ + return platform_device_register(&ehci_device); +} + +module_init(ehci_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("EHCI probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-i2c-dev.c b/arch/mips/mti-sead3/sead3-i2c-dev.c new file mode 100644 index 0000000..7e7a911 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c-dev.c @@ -0,0 +1,38 @@ +#define DEBUG +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include + +static struct i2c_board_info sead3_i2c_info2[] __initdata = { + { + I2C_BOARD_INFO("adt7476", 0x2c), + .irq = 0, + }, + { + I2C_BOARD_INFO("m41t80", 0x68), + .irq = 0, + }, +}; + +static int __init sead3_i2c_init(void) +{ + int err; + + pr_debug("sead3_i2c_init\n"); + + err = i2c_register_board_info(2, sead3_i2c_info2, + ARRAY_SIZE(sead3_i2c_info2)); + if (err < 0) + printk(KERN_ERR + "sead3-i2c-dev: cannot register board I2C devices\n"); + return err; +} + +arch_initcall(sead3_i2c_init); diff --git a/arch/mips/mti-sead3/sead3-i2c.c b/arch/mips/mti-sead3/sead3-i2c.c new file mode 100644 index 0000000..bf5f8d3 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c.c @@ -0,0 +1,42 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 MIPS Technologies, Inc. + * written by Ralf Baechle (ralf@linux-mips.org) + * + * Probe driver for the SEAD3 network device + * + */ +#include +#include +#include +#include + + +struct resource i2c_resources[] = { + { + .start = 0x805200, + .end = 0x8053FF, + .flags = IORESOURCE_MEM + }, +}; + +static struct platform_device i2c_device = { + .name = "i2c_pic32", + .id = 2, + .num_resources = ARRAY_SIZE(i2c_resources), + .resource = i2c_resources +}; + +static int __init i2c_init(void) +{ + return platform_device_register(&i2c_device); +} + +module_init(i2c_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("I2C probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c new file mode 100644 index 0000000..25bdb0a --- /dev/null +++ b/arch/mips/mti-sead3/sead3-init.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library initialisation code. + */ +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +int prom_argc; +int *_prom_argv, *_prom_envp; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension, if running in 64-bit mode. + */ +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +int init_debug; /* global var => auto initialized to 0 */ + +int mips_revision_corid; +int mips_revision_sconid; + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index = 0; + + i = strlen(envname); + + while (prom_envp(index)) { + if (strncmp(envname, prom_envp(index), i) == 0) + return prom_envp(index+1); + index += 2; + } + + return NULL; +} + +static inline unsigned char str2hexnum(unsigned char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return 0; /* foo */ +} + +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if ((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk(KERN_WARNING "ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + + if (init_debug > 1) { + int i; + printk(KERN_DEBUG "get_ethernet_addr: "); + for (i = 0; i < 5; i++) + printk("%02x:", (unsigned char)*(ethernet_addr+i)); + printk("%02x\n", *(ethernet_addr+i)); + } + + return 0; +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static void __init console_config(void) +{ + char console_string[40]; + int baud = 0; + char parity = '\0', bits = '\0', flow = '\0'; + char *s; + + if ((strstr(prom_getcmdline(), "console=")) == NULL) { + s = prom_getenv("modetty0"); + if (s) { + while (*s >= '0' && *s <= '9') + baud = baud*10 + *s++ - '0'; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; + } + if (baud == 0) + baud = 38400; + if (parity != 'n' && parity != 'o' && parity != 'e') + parity = 'n'; + if (bits != '7' && bits != '8') + bits = '8'; + if (flow == '\0') + flow = 'r'; + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, + parity, bits, flow); + strcat(prom_getcmdline(), console_string); + pr_info("Config serial console:%s\n", console_string); + } +} +#endif + +static void __init mips_nmi_setup(void) +{ + void *base; + extern char except_vec_nmi; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); + memcpy(base, &except_vec_nmi, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +static void __init mips_ejtag_setup(void) +{ + void *base; + extern char except_vec_ejtag_debug; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); + memcpy(base, &except_vec_ejtag_debug, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +extern struct plat_smp_ops msmtc_smp_ops; + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + _prom_argv = (int *) fw_arg1; + _prom_envp = (int *) fw_arg2; + + mips_display_message("LINUX"); + + mips_revision_corid = MIPS_REVISION_CORID; + mips_revision_sconid = MIPS_REVISION_SCONID; + if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { + switch (mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_FPGAR2: + mips_revision_sconid = MIPS_REVISION_SCON_GT64120; + break; + case MIPS_REVISION_CORID_CORE_EMUL_BON: + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + mips_revision_sconid = MIPS_REVISION_SCON_BONITO; + break; + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_24K: + /* + * SOCit/ROCit support is essentially identical + * but make an attempt to distinguish them + */ + mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; + break; + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_FPGA4: + case MIPS_REVISION_CORID_CORE_FPGA5: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: + default: + /* See above */ + mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; + break; + } + } + + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + + pr_info("\nLINUX started...\n"); + prom_init_cmdline(); + prom_meminit(); +#ifdef CONFIG_SERIAL_8250_CONSOLE + console_config(); +#endif +#ifdef CONFIG_MIPS_CMP + register_smp_ops(&cmp_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMP + register_smp_ops(&vsmp_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&msmtc_smp_ops); +#endif +} diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c new file mode 100644 index 0000000..4cd569e --- /dev/null +++ b/arch/mips/mti-sead3/sead3-int.c @@ -0,0 +1,146 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines for generic manipulation of the interrupts found on the MIPS + * Malta board. + * The interrupt controller is located in the South Bridge a PIIX4 device + * with two internal 82C95 interrupt controllers. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define SEAD_CONFIG_GIC_PRESENT_SHF (1) +#define SEAD_CONFIG_GIC_PRESENT_MSK (1 << SEAD_CONFIG_GIC_PRESENT_SHF) +#define SEAD_CONFIG_BASE (0x1B100110) +#define SEAD_CONFIG_SIZE (4) + +int gic_present; /* global var => auto initialized to 0 */ +static unsigned long sead3_config_reg; + +/* + * This table defines the setup for each external GIC interrupt + * It is indexed by interrupt number + */ +#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + /* The remainder of this table is initialised by fill_ipi_map */ +}; + +/* + * Version of ffs that only looks at bits 8..15 + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + return fls(pending) - CAUSEB_IP - 1; +#else + unsigned int a0 = 7; + unsigned int t0; + + t0 = pending & 0xf000; + t0 = t0 < 1; + t0 = t0 << 2; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0xc000; + t0 = t0 < 1; + t0 = t0 << 1; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0x8000; + t0 = t0 < 1; + /* t0 = t0 << 2; */ + a0 = a0 - t0; + /* pending = pending << t0; */ + + return a0; +#endif +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = irq_ffs(pending); + + if (irq >= 0) + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + int i; + + if (!cpu_has_veic) { + mips_cpu_irq_init(); + + if (cpu_has_vint) { + /* install generic handler */ + for (i = 0; i < 8; i++) + set_vi_handler(i, plat_irq_dispatch); + } + } + + sead3_config_reg = (unsigned long)ioremap_nocache(SEAD_CONFIG_BASE, SEAD_CONFIG_SIZE); + gic_present = (REG32(sead3_config_reg) & SEAD_CONFIG_GIC_PRESENT_MSK) >> + SEAD_CONFIG_GIC_PRESENT_SHF; + printk("GIC: %spresent\n", (gic_present) ? "" : "not "); + printk("EIC: %s\n", (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off"); + + if (gic_present) { + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); + } +} + diff --git a/arch/mips/mti-sead3/sead3-lcd.c b/arch/mips/mti-sead3/sead3-lcd.c new file mode 100644 index 0000000..654b447 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-lcd.c @@ -0,0 +1,55 @@ +/* + * Registration of Sead3 LCD platform device. + * + * Copyright (C) 2008 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include + +static struct resource sead3_lcd_resource __initdata = { + .start = 0x1f000400, + .end = 0x1f00041f, + .flags = IORESOURCE_MEM, +}; + +static __init int sead3_lcd_add(void) +{ + struct platform_device *pdev; + int retval; + + pdev = platform_device_alloc("cobalt-lcd", -1); + if (!pdev) + return -ENOMEM; + + retval = platform_device_add_resources(pdev, &sead3_lcd_resource, 1); + if (retval) + goto err_free_device; + + retval = platform_device_add(pdev); + if (retval) + goto err_free_device; + + return 0; + +err_free_device: + platform_device_put(pdev); + + return retval; +} +device_initcall(sead3_lcd_add); diff --git a/arch/mips/mti-sead3/sead3-leds.c b/arch/mips/mti-sead3/sead3-leds.c new file mode 100644 index 0000000..ff003d2 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-leds.c @@ -0,0 +1,91 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 MIPS Technologies, Inc. + * written by Chris Dearman (chris@mips.com) + * + * Probe driver for the SEAD3 LED devices + * + */ +#include +#include +#include +#include +#include + + +#define LEDFLAGS(bits, shift) \ + ((bits << 8) | (shift << 8)) + +#define LEDBITS(id, shift, bits) \ + .name = id #shift, \ + .flags = LEDFLAGS(bits, shift) + +struct led_info led_data_info[] = { + { LEDBITS("bit", 0, 1) }, + { LEDBITS("bit", 1, 1) }, + { LEDBITS("bit", 2, 1) }, + { LEDBITS("bit", 3, 1) }, + { LEDBITS("bit", 4, 1) }, + { LEDBITS("bit", 5, 1) }, + { LEDBITS("bit", 6, 1) }, + { LEDBITS("bit", 7, 1) }, + { LEDBITS("all", 0, 8) }, +}; + +static struct led_platform_data led_data = { + .num_leds = ARRAY_SIZE(led_data_info), + .leds = led_data_info +}; + +static struct resource pled_resources[] = { + { + .start = 0x1F000210, + .end = 0x1F000217, + .flags = IORESOURCE_MEM + } +}; + +static struct platform_device pled_device = { + .name = "sead3::pled", + .id = 0, + .dev = { + .platform_data = &led_data, + }, + .num_resources = ARRAY_SIZE(pled_resources), + .resource = pled_resources +}; + + +static struct resource fled_resources[] = { + { + .start = 0x1F000218, + .end = 0x1F00021f, + .flags = IORESOURCE_MEM + } +}; + +static struct platform_device fled_device = { + .name = "sead3::fled", + .id = 0, + .dev = { + .platform_data = &led_data, + }, + .num_resources = ARRAY_SIZE(fled_resources), + .resource = fled_resources +}; + + +static int __init led_init(void) +{ + platform_device_register(&pled_device); + return platform_device_register(&fled_device); +} + +module_init(led_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("LED probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-memory.c b/arch/mips/mti-sead3/sead3-memory.c new file mode 100644 index 0000000..b27419c --- /dev/null +++ b/arch/mips/mti-sead3/sead3-memory.c @@ -0,0 +1,178 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library functions for acquiring/using memory descriptors given to + * us from the YAMON. + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/*#define DEBUG*/ + +enum yamon_memtypes { + yamon_dontuse, + yamon_prom, + yamon_free, +}; +static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +#ifdef DEBUG +static char *mtypes[3] = { + "Dont use memory", + "YAMON PROM memory", + "Free memmory", +}; +#endif + +/* determined physical memory size, not overridden by command line args */ +unsigned long physical_memsize = 0L; + +static struct prom_pmemblock * __init prom_getmdesc(void) +{ + char *memsize_str; + unsigned int memsize; + char *ptr; + static char cmdline[COMMAND_LINE_SIZE] __initdata; + + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + printk(KERN_WARNING + "memsize not set in boot prom, set to default (32Mb)\n"); + physical_memsize = 0x02000000; + } else { +#ifdef DEBUG + pr_debug("prom_memsize = %s\n", memsize_str); +#endif + physical_memsize = simple_strtol(memsize_str, NULL, 0); + } + +#ifdef CONFIG_CPU_BIG_ENDIAN + /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last + word of physical memory */ + physical_memsize -= PAGE_SIZE; +#endif + + /* Check the command line for a memsize directive that overrides + the physical/default amount */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) + memsize = memparse(ptr + 8, &ptr); + else + memsize = physical_memsize; + + memset(mdesc, 0, sizeof(mdesc)); + + mdesc[0].type = yamon_dontuse; + mdesc[0].base = 0x00000000; + mdesc[0].size = 0x00001000; + + mdesc[1].type = yamon_prom; + mdesc[1].base = 0x00001000; + mdesc[1].size = 0x000ef000; + + /* + * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the + * south bridge and PCI access always forwarded to the ISA Bus and + * BIOSCS# is always generated. + * This mean that this area can't be used as DMA memory for PCI + * devices. + */ + mdesc[2].type = yamon_dontuse; + mdesc[2].base = 0x000f0000; + mdesc[2].size = 0x00010000; + + mdesc[3].type = yamon_dontuse; + mdesc[3].base = 0x00100000; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; + + mdesc[4].type = yamon_free; + mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[4].size = memsize - mdesc[4].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify(unsigned int type) +{ + switch (type) { + case yamon_free: + return BOOT_MEM_RAM; + case yamon_prom: + return BOOT_MEM_ROM_DATA; + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + +#ifdef DEBUG + pr_debug("YAMON MEMORY DESCRIPTOR dump:\n"); + p = prom_getmdesc(); + while (p->size) { + int i = 0; + pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", + i, p, p->base, p->size, mtypes[p->type]); + p++; + i++; + } +#endif + p = prom_getmdesc(); + + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify(p->type); + base = p->base; + size = p->size; + + add_memory_region(base, size, type); + p++; + } +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/mti-sead3/sead3-mtd.c b/arch/mips/mti-sead3/sead3-mtd.c new file mode 100644 index 0000000..30450b4 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-mtd.c @@ -0,0 +1,58 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 MIPS Technologies, Inc. + * written by Ralf Baechle + */ + +#include +#include +#include +#include +#include + +static struct mtd_partition sead3_mtd_partitions[] = { + { + .name = "User FS", + .offset = 0x00000000, + .size = 0x01fc0000, + }, { + .name = "Board Config", + .offset = 0x01fc0000, + .size = 0x00040000, + .mask_flags = MTD_WRITEABLE + }, +}; + +static struct physmap_flash_data sead3_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(sead3_mtd_partitions), + .parts = sead3_mtd_partitions +}; + +static struct resource sead3_flash_resource = { + .start = 0x1c000000, + .end = 0x1dffffff, + .flags = IORESOURCE_MEM +}; + +static struct platform_device sead3_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &sead3_flash_data, + }, + .num_resources = 1, + .resource = &sead3_flash_resource, +}; + +static int __init sead3_mtd_init(void) +{ + platform_device_register(&sead3_flash); + + return 0; +} + +module_init(sead3_mtd_init) diff --git a/arch/mips/mti-sead3/sead3-net.c b/arch/mips/mti-sead3/sead3-net.c new file mode 100644 index 0000000..1a5018d --- /dev/null +++ b/arch/mips/mti-sead3/sead3-net.c @@ -0,0 +1,56 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007-2011 MIPS Technologies, Inc. + * written by Ralf Baechle (ralf@linux-mips.org) + * + * Probe driver for the SEAD3 network device + * + */ +#include +#include +#include +#include +#include + +static struct smsc911x_platform_config net_data = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +struct resource net_resources[] = { + { + .start = 0x1f010000, + .end = 0x1f01ffff, + .flags = IORESOURCE_MEM + }, + { + .start = MIPS_CPU_IRQ_BASE + 6, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device net_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &net_data, + }, + .num_resources = ARRAY_SIZE(net_resources), + .resource = net_resources +}; + +static int __init net_init(void) +{ + return platform_device_register(&net_device); +} + +module_init(net_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Network probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c new file mode 100644 index 0000000..b0bb326 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-pic32-bus.c @@ -0,0 +1,112 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include + +#define PIC32_NULL 0x00 +#define PIC32_RD 0x01 +#define PIC32_SYSRD 0x02 +#define PIC32_WR 0x10 +#define PIC32_SYSWR 0x20 +#define PIC32_IRQ_CLR 0x40 +#define PIC32_STATUS 0x80 + +#define DELAY() udelay(100) /* FIXME: needed? */ + +/* spinlock to ensure atomic access to PIC32 */ +static DEFINE_SPINLOCK(pic32_bus_lock); + +/* FIXME: io_remap these */ +static void __iomem *bus_xfer = (void __iomem *)0xbf000600; +static void __iomem *bus_status = (void __iomem *)0xbf000060; + +static inline unsigned int ioready(void) +{ + return readl(bus_status) & 1; +} + +static inline void wait_ioready(void) +{ + do { } while (!ioready()); +} + +static inline void wait_ioclear(void) +{ + do { } while (ioready()); +} + +static inline void check_ioclear(void) +{ + if (ioready()) { + pr_debug("ioclear: initially busy\n"); + do { + (void) readl(bus_xfer); + DELAY(); + } while (ioready()); + pr_debug("ioclear: cleared busy\n"); + } +} + +u32 pic32_bus_readl(u32 reg) +{ + unsigned long flags; + u32 status, val; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + + writel((PIC32_RD << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + DELAY(); + val = readl(bus_xfer); + wait_ioclear(); + + pr_debug("pic32_bus_readl: *%x -> %x (status=%x)\n", reg, val, status); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); + + return val; +} + +void pic32_bus_writel(u32 val, u32 reg) +{ + unsigned long flags; + u32 status; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + + writel((PIC32_WR << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + writel(val, bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + wait_ioclear(); + + pr_debug("pic32_bus_writel: *%x <- %x (status=%x)\n", reg, val, status); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); +} diff --git a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c new file mode 100644 index 0000000..053b23e --- /dev/null +++ b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c @@ -0,0 +1,441 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PIC32_I2CxCON 0x0000 +#define PIC32_I2CxCONCLR 0x0004 +#define PIC32_I2CxCONSET 0x0008 +#define PIC32_I2CxCONINV 0x000C +#define I2CCON_ON (1<<15) +#define I2CCON_FRZ (1<<14) +#define I2CCON_SIDL (1<<13) +#define I2CCON_SCLREL (1<<12) +#define I2CCON_STRICT (1<<11) +#define I2CCON_A10M (1<<10) +#define I2CCON_DISSLW (1<<9) +#define I2CCON_SMEN (1<<8) +#define I2CCON_GCEN (1<<7) +#define I2CCON_STREN (1<<6) +#define I2CCON_ACKDT (1<<5) +#define I2CCON_ACKEN (1<<4) +#define I2CCON_RCEN (1<<3) +#define I2CCON_PEN (1<<2) +#define I2CCON_RSEN (1<<1) +#define I2CCON_SEN (1<<0) + +#define PIC32_I2CxSTAT 0x0010 +#define PIC32_I2CxSTATCLR 0x0014 +#define PIC32_I2CxSTATSET 0x0018 +#define PIC32_I2CxSTATINV 0x001C +#define I2CSTAT_ACKSTAT (1<<15) +#define I2CSTAT_TRSTAT (1<<14) +#define I2CSTAT_BCL (1<<10) +#define I2CSTAT_GCSTAT (1<<9) +#define I2CSTAT_ADD10 (1<<8) +#define I2CSTAT_IWCOL (1<<7) +#define I2CSTAT_I2COV (1<<6) +#define I2CSTAT_DA (1<<5) +#define I2CSTAT_P (1<<4) +#define I2CSTAT_S (1<<3) +#define I2CSTAT_RW (1<<2) +#define I2CSTAT_RBF (1<<1) +#define I2CSTAT_TBF (1<<0) + +#define PIC32_I2CxADD 0x0020 +#define PIC32_I2CxADDCLR 0x0024 +#define PIC32_I2CxADDSET 0x0028 +#define PIC32_I2CxADDINV 0x002C +#define PIC32_I2CxMSK 0x0030 +#define PIC32_I2CxMSKCLR 0x0034 +#define PIC32_I2CxMSKSET 0x0038 +#define PIC32_I2CxMSKINV 0x003C +#define PIC32_I2CxBRG 0x0040 +#define PIC32_I2CxBRGCLR 0x0044 +#define PIC32_I2CxBRGSET 0x0048 +#define PIC32_I2CxBRGINV 0x004C +#define PIC32_I2CxTRN 0x0050 +#define PIC32_I2CxTRNCLR 0x0054 +#define PIC32_I2CxTRNSET 0x0058 +#define PIC32_I2CxTRNINV 0x005C +#define PIC32_I2CxRCV 0x0060 + +struct i2c_platform_data { + u32 base; + struct i2c_adapter adap; + u32 xfer_timeout; + u32 ack_timeout; + u32 ctl_timeout; +}; + +extern u32 pic32_bus_readl(u32 reg); +extern void pic32_bus_writel(u32 val, u32 reg); + +static inline void +StartI2C(struct i2c_platform_data *adap) +{ + pr_debug("StartI2C\n"); + pic32_bus_writel(I2CCON_SEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +StopI2C(struct i2c_platform_data *adap) +{ + pr_debug("StopI2C\n"); + pic32_bus_writel(I2CCON_PEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +AckI2C(struct i2c_platform_data *adap) +{ + pr_debug("AckI2C\n"); + pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR); + pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +NotAckI2C(struct i2c_platform_data *adap) +{ + pr_debug("NakI2C\n"); + pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET); + pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline int +IdleI2C(struct i2c_platform_data *adap) +{ + int i; + + pr_debug("IdleI2C\n"); + for (i = 0; i < adap->ctl_timeout; i++) { + if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) & + (I2CCON_ACKEN|I2CCON_RCEN|I2CCON_PEN|I2CCON_RSEN|I2CCON_SEN)) == 0) && + ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + (I2CSTAT_TRSTAT)) == 0)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static inline u32 +MasterWriteI2C(struct i2c_platform_data *adap, u32 byte) +{ + pr_debug("MasterWriteI2C\n"); + + pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN); + + return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_IWCOL; +} + +static inline u32 +MasterReadI2C(struct i2c_platform_data *adap) +{ + pr_debug("MasterReadI2C\n"); + + pic32_bus_writel(I2CCON_RCEN, adap->base + PIC32_I2CxCONSET); + + while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & I2CCON_RCEN) + ; + + pic32_bus_writel(I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR); + + return pic32_bus_readl(adap->base + PIC32_I2CxRCV); +} + +static int +do_address(struct i2c_platform_data *adap, unsigned int addr, int rd) +{ + pr_debug("doaddress\n"); + + IdleI2C(adap); + StartI2C(adap); + IdleI2C(adap); + + addr <<= 1; + if (rd) + addr |= 1; + + if (MasterWriteI2C(adap, addr)) + return -EIO; + IdleI2C(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_ACKSTAT) + return -EIO; + return 0; +} + +static int +i2c_read(struct i2c_platform_data *adap, unsigned char *buf, + unsigned int len) +{ + int i; + u32 data; + + pr_debug("i2c_read\n"); + + i = 0; + while (i < len) { + data = MasterReadI2C(adap); + buf[i++] = data; + if (i < len) + AckI2C(adap); + else + NotAckI2C(adap); + } + + StopI2C(adap); + IdleI2C(adap); + return 0; +} + +static int +i2c_write(struct i2c_platform_data *adap, unsigned char *buf, + unsigned int len) +{ + int i; + u32 data; + + pr_debug("i2c_write\n"); + + i = 0; + while (i < len) { + data = buf[i]; + if (MasterWriteI2C(adap, data)) + return -EIO; + IdleI2C(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_ACKSTAT) + return -EIO; + i++; + } + + StopI2C(adap); + IdleI2C(adap); + return 0; +} + +static int +platform_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) +{ + struct i2c_platform_data *adap = i2c_adap->algo_data; + struct i2c_msg *p; + int i, err = 0; + + pr_debug("platform_xfer\n"); + for (i = 0; i < num; i++) { +#define __BUFSIZE 80 + int ii; + static char buf[__BUFSIZE]; + char *b = buf; + + p = &msgs[i]; + b += sprintf(buf, " [%d bytes]", p->len); + if ((p->flags & I2C_M_RD) == 0) { + for (ii = 0; ii < p->len; ii++) { + if (b < &buf[__BUFSIZE-4]) { + b += sprintf(b, " %02x", p->buf[ii]); + } else { + strcat(b, "..."); + break; + } + } + } + pr_debug("xfer%d: DevAddr: %04x Op:%s Data:%s\n", i, p->addr, + (p->flags & I2C_M_RD) ? "Rd" : "Wr", buf); + } + + + for (i = 0; !err && i < num; i++) { + p = &msgs[i]; + err = do_address(adap, p->addr, p->flags & I2C_M_RD); + if (err || !p->len) + continue; + if (p->flags & I2C_M_RD) + err = i2c_read(adap, p->buf, p->len); + else + err = i2c_write(adap, p->buf, p->len); + } + + /* Return the number of messages processed, or the error code. */ + if (err == 0) + err = num; + + return err; +} + +static u32 +platform_func(struct i2c_adapter *adap) +{ + pr_debug("platform_algo\n"); + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm platform_algo = { + .master_xfer = platform_xfer, + .functionality = platform_func, +}; + +static void i2c_platform_setup(struct i2c_platform_data *priv) +{ + pr_debug("i2c_platform_setup\n"); + + pic32_bus_writel(500, priv->base + PIC32_I2CxBRG); + pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONCLR); + pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONSET); + pic32_bus_writel(I2CSTAT_BCL|I2CSTAT_IWCOL, priv->base + PIC32_I2CxSTATCLR); +} + +static void i2c_platform_disable(struct i2c_platform_data *priv) +{ + pr_debug("i2c_platform_disable\n"); +} + +static int __devinit +i2c_platform_probe(struct platform_device *pdev) +{ + struct i2c_platform_data *priv; + struct resource *r; + int ret; + + pr_debug("i2c_platform_probe\n"); + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENODEV; + goto out; + } + + priv = kzalloc(sizeof(struct i2c_platform_data), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + goto out; + } + + /* FIXME: need to allocate resource in PIC32 space */ +#if 0 + priv->base = bus_request_region(r->start, resource_size(r), + pdev->name); +#else + priv->base = r->start; +#endif + if (!priv->base) { + ret = -EBUSY; + goto out_mem; + } + + priv->xfer_timeout = 200; + priv->ack_timeout = 200; + priv->ctl_timeout = 200; + + priv->adap.nr = pdev->id; + priv->adap.algo = &platform_algo; + priv->adap.algo_data = priv; + priv->adap.dev.parent = &pdev->dev; + strlcpy(priv->adap.name, "PIC32 I2C", sizeof(priv->adap.name)); + + i2c_platform_setup(priv); + + ret = i2c_add_numbered_adapter(&priv->adap); + if (ret == 0) { + platform_set_drvdata(pdev, priv); + return 0; + } + + i2c_platform_disable(priv); + +out_mem: + kfree(priv); +out: + return ret; +} + +static int __devexit +i2c_platform_remove(struct platform_device *pdev) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + pr_debug("i2c_platform_remove\n"); + platform_set_drvdata(pdev, NULL); + i2c_del_adapter(&priv->adap); + i2c_platform_disable(priv); + kfree(priv); + return 0; +} + +#ifdef CONFIG_PM +static int +i2c_platform_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "i2c_platform_disable\n"); + i2c_platform_disable(priv); + + return 0; +} + +static int +i2c_platform_resume(struct platform_device *pdev) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "i2c_platform_setup\n"); + i2c_platform_setup(priv); + + return 0; +} +#else +#define i2c_platform_suspend NULL +#define i2c_platform_resume NULL +#endif + +static struct platform_driver i2c_platform_driver = { + .driver = { + .name = "i2c_pic32", + .owner = THIS_MODULE, + }, + .probe = i2c_platform_probe, + .remove = __devexit_p(i2c_platform_remove), + .suspend = i2c_platform_suspend, + .resume = i2c_platform_resume, +}; + +static int __init +i2c_platform_init(void) +{ + pr_debug("i2c_platform_init\n"); + return platform_driver_register(&i2c_platform_driver); +} + +static void __exit +i2c_platform_exit(void) +{ + pr_debug("i2c_platform_exit\n"); + platform_driver_unregister(&i2c_platform_driver); +} + +MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC."); +MODULE_DESCRIPTION("PIC32 I2C driver"); +MODULE_LICENSE("GPL"); + +module_init(i2c_platform_init); +module_exit(i2c_platform_exit); diff --git a/arch/mips/mti-sead3/sead3-platform.c b/arch/mips/mti-sead3/sead3-platform.c new file mode 100644 index 0000000..ddd28f6 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-platform.c @@ -0,0 +1,49 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 MIPS Technologies, Inc. + * written by Ralf Baechle (ralf@linux-mips.org) + * + * Probe driver for the SEAD3 UART ports + * + */ +#include +#include +#include + +#define UART(base, int) \ +{ \ + .mapbase = base, \ + .irq = int, \ + .uartclk = 14745600, \ + .iotype = UPIO_MEM32, \ + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, \ + .regshift = 2, \ +} + +static struct plat_serial8250_port uart8250_data[] = { + UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */ + UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */ + { }, +}; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-reset.c b/arch/mips/mti-sead3/sead3-reset.c new file mode 100644 index 0000000..4aec9f9 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-reset.c @@ -0,0 +1,64 @@ +#define DEBUG +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Reset the MIPS boards. + * + */ +#include +#include + +#include +#include + +#define SOFTRES_REG 0x1F000050 +#define GORESET 0x4D + +static void mips_machine_restart(char *command); +static void mips_machine_halt(void); + +static void mips_machine_restart(char *command) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + +static void mips_machine_halt(void) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + + +static int __init mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; + _machine_halt = mips_machine_halt; + pm_power_off = mips_machine_halt; + + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c new file mode 100644 index 0000000..1ddd4c3 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -0,0 +1,49 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2008 Dmitri Vorobiev + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +int coherentio; /* init to 0 => no DMA cache coherency (may be set by user) */ +int hw_coherentio; /* init to 0 => no HW DMA cache coherency (reflects real HW) */ + +const char *get_system_type(void) +{ + return "MIPS SEAD3"; +} + +#if defined(CONFIG_MIPS_MT_SMTC) +const char display_string[] = " SMTC LINUX ON SEAD3 "; +#else +const char display_string[] = " LINUX ON SEAD3 "; +#endif /* CONFIG_MIPS_MT_SMTC */ + +void __init plat_mem_setup(void) +{ +} diff --git a/arch/mips/mti-sead3/sead3-smtc.c b/arch/mips/mti-sead3/sead3-smtc.c new file mode 100644 index 0000000..192cfd2 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-smtc.c @@ -0,0 +1,162 @@ +/* + * Malta Platform-specific hooks for SMP operation + */ +#include +#include + +#include +#include +#include +#include + +/* VPE/SMP Prototype implements platform interfaces directly */ + +/* + * Cause the specified action to be performed on a targeted "CPU" + */ + +static void msmtc_send_ipi_single(int cpu, unsigned int action) +{ + /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ + smtc_send_ipi(cpu, LINUX_SMP_IPI, action); +} + +static void msmtc_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu(i, mask) + msmtc_send_ipi_single(i, action); +} + +/* + * Post-config but pre-boot cleanup entry point + */ +static void __cpuinit msmtc_init_secondary(void) +{ + void smtc_init_secondary(void); + int myvpe; + + /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ + myvpe = read_c0_tcbind() & TCBIND_CURVPE; + if (myvpe != 0) { + /* Ideally, this should be done only once per VPE, but... */ + clear_c0_status(ST0_IM); + set_c0_status((0x100 << cp0_compare_irq) + | (0x100 << MIPS_CPU_IPI_IRQ)); + if (cp0_perfcount_irq >= 0) + set_c0_status(0x100 << cp0_perfcount_irq); + } + + smtc_init_secondary(); +} + +/* + * Platform "CPU" startup hook + */ +static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle) +{ + smtc_boot_secondary(cpu, idle); +} + +/* + * SMP initialization finalization entry point + */ +static void __cpuinit msmtc_smp_finish(void) +{ + smtc_smp_finish(); +} + +/* + * Hook for after all CPUs are online + */ + +static void msmtc_cpus_done(void) +{ +} + +/* + * Platform SMP pre-initialization + * + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. + */ + +static void __init msmtc_smp_setup(void) +{ + /* + * we won't get the definitive value until + * we've run smtc_prepare_cpus later, but + * we would appear to need an upper bound now. + */ + smp_num_siblings = smtc_build_cpu_map(0); +} + +static void __init msmtc_prepare_cpus(unsigned int max_cpus) +{ + smtc_prepare_cpus(max_cpus); +} + +struct plat_smp_ops msmtc_smp_ops = { + .send_ipi_single = msmtc_send_ipi_single, + .send_ipi_mask = msmtc_send_ipi_mask, + .init_secondary = msmtc_init_secondary, + .smp_finish = msmtc_smp_finish, + .cpus_done = msmtc_cpus_done, + .boot_secondary = msmtc_boot_secondary, + .smp_setup = msmtc_smp_setup, + .prepare_cpus = msmtc_prepare_cpus, +}; + +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * IRQ affinity hook + */ + + +int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) +{ + cpumask_t tmask; + int cpu = 0; + void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); + + /* + * On the legacy Malta development board, all I/O interrupts + * are routed through the 8259 and combined in a single signal + * to the CPU daughterboard, and on the CoreFPGA2/3 34K models, + * that signal is brought to IP2 of both VPEs. To avoid racing + * concurrent interrupt service events, IP2 is enabled only on + * one VPE, by convention VPE0. So long as no bits are ever + * cleared in the affinity mask, there will never be any + * interrupt forwarding. But as soon as a program or operator + * sets affinity for one of the related IRQs, we need to make + * sure that we don't ever try to forward across the VPE boundry, + * at least not until we engineer a system where the interrupt + * _ack() or _end() function can somehow know that it corresponds + * to an interrupt taken on another VPE, and perform the appropriate + * restoration of Status.IM state using MFTR/MTTR instead of the + * normal local behavior. We also ensure that no attempt will + * be made to forward to an offline "CPU". + */ + + cpumask_copy(&tmask, affinity); + for_each_cpu(cpu, affinity) { + if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) + cpu_clear(cpu, tmask); + } + cpumask_copy(irq_desc[irq].affinity, &tmask); + + if (cpus_empty(tmask)) + /* + * We could restore a default mas