From linuxppcemb@lkmail.de Sun Apr 1 00:19:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 00:19:34 +0200 (CEST) Received: from pm1.terions.de ([83.137.96.25]:47733 "EHLO pm1.terions.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2CaWTb (ORCPT ); Sun, 1 Apr 2012 00:19:31 +0200 Received: (qmail 23754 invoked by uid 98); 31 Mar 2012 22:19:27 -0000 Received: from unknown (HELO ?192.168.178.33?) (postmaster@lkmail.de@78.43.56.110) by 0 with ESMTPA; 31 Mar 2012 22:19:27 -0000 Message-ID: <4F7782ED.7050407@lkmail.de> Date: Sun, 01 Apr 2012 00:19:25 +0200 From: Lorenz Kolb User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.1.16) Gecko/20101125 Thunderbird/3.0.11 MIME-Version: 1.0 To: paulmck@linux.vnet.ibm.com CC: Eric Dumazet , linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-ia64@vger.kernel.org, linux-sh@vger.kernel.org, dhowells@redhat.com, sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, linux-am33-list@redhat.com, linux@arm.linux.org.uk, linux-hexagon@vger.kernel.org, x86@kernel.org, jejb@parisc-linux.org, cmetcalf@tilera.com, uclinux-dist-devel@blackfin.uclinux.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-m32r@ml.linux-m32r.org, linux-parisc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux390@de.ibm.com, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH RFC] Simplify the Linux kernel by reducing its state space References: <20120331163321.GA15809@linux.vnet.ibm.com> <1333227608.2325.4054.camel@edumazet-glaptop> <20120331212149.GI2450@linux.vnet.ibm.com> In-Reply-To: <20120331212149.GI2450@linux.vnet.ibm.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32846 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linuxppcemb@lkmail.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2642 Lines: 66 With that patchset in mind, I am working on a really huge patch, which will greatly simplify the Linux kernel for the real problem of having that number of CPUs. That patch will have a lot of changes all over the architectures, so what will be the best way to post it? Should I split it architecture dependend and into one generic part. Currently it is a large blob of millions of changes, but will greatly simplify the Linux kernel. Regards, Lorenz Kolb Am 31.03.2012 23:21, schrieb Paul E. McKenney: > On Sat, Mar 31, 2012 at 11:00:08PM +0200, Eric Dumazet wrote: > >> On Sun, 2012-04-01 at 00:33 +0800, Paul E. McKenney wrote: >> >>> Although there have been numerous complaints about the complexity of >>> parallel programming (especially over the past 5-10 years), the plain >>> truth is that the incremental complexity of parallel programming over >>> that of sequential programming is not as large as is commonly believed. >>> Despite that you might have heard, the mind-numbing complexity of modern >>> computer systems is not due so much to there being multiple CPUs, but >>> rather to there being any CPUs at all. In short, for the ultimate in >>> computer-system simplicity, the optimal choice is NR_CPUS=0. >>> >>> This commit therefore limits kernel builds to zero CPUs. This change >>> has the beneficial side effect of rendering all kernel bugs harmless. >>> Furthermore, this commit enables additional beneficial changes, for >>> example, the removal of those parts of the kernel that are not needed >>> when there are zero CPUs. >>> >>> Signed-off-by: Paul E. McKenney >>> Reviewed-by: Thomas Gleixner >>> --- >>> >> Hmm... I believe you could go one step forward and allow negative values >> as well. Antimatter was proven to exist after all. >> >> Hint : nr_cpu_ids is an "int", not an "unsigned int" >> >> Bonus: Existing bugs become "must have" features. >> > ;-) ;-) ;-) > > >> Of course there is no hurry and this can wait 365 days. >> > James Bottomley suggested imaginary numbers of CPUs some time back, > and I suppose there is no reason you cannot have fractional numbers of > CPUs, and perhaps irrational numbers as well. Of course, these last two > would require use of floating-point arithmetic (or something similar) > in the kernel. So I guess we have at several years worth. Over to you > for the negative numbers. ;-) > > Thanx, Paul > > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/linuxppc-dev > From linux@arm.linux.org.uk Sun Apr 1 00:33:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 00:33:44 +0200 (CEST) Received: from caramon.arm.linux.org.uk ([78.32.30.218]:53973 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2CaWdk (ORCPT ); Sun, 1 Apr 2012 00:33:40 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=caramon; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=hBaV9W9sNKgUd6Ul4Hvq0QZAqdOZdWtEgmbnoBVlZcw=; b=Lbb3zPOt5jMZjSnpH/K+UAXPqkdbREsb8ISmC+5PTT2USoyX4S1oxGhAe0gLBDnMjhwkNH2KAtpt8ykrgT5IhiAjNkfnF/DeFQEahPDGAHP0sY1c1aJqW3qkTs4gubrUdWkjWHETR60lirSRKyTk+8GWM+BnvW1kTSkJYDU49mg=; Received: from n2100.arm.linux.org.uk ([2002:4e20:1eda:1:214:fdff:fe10:4f86]:45501) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1SE6q2-0006nQ-SJ; Sat, 31 Mar 2012 23:32:03 +0100 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1SE6q1-0003L5-7f; Sat, 31 Mar 2012 23:32:01 +0100 Date: Sat, 31 Mar 2012 23:32:00 +0100 From: Russell King - ARM Linux To: "Paul E. McKenney" Cc: linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, tglx@linutronix.de, dhowells@redhat.com, jejb@parisc-linux.org, linux390@de.ibm.com, x86@kernel.org, cmetcalf@tilera.com Subject: Re: [PATCH RFC] Simplify the Linux kernel by reducing its state space Message-ID: <20120331223200.GA32482@n2100.arm.linux.org.uk> References: <20120331163321.GA15809@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120331163321.GA15809@linux.vnet.ibm.com> User-Agent: Mutt/1.5.19 (2009-01-05) X-archive-position: 32847 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux@arm.linux.org.uk Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1945 Lines: 37 On Sun, Apr 01, 2012 at 12:33:21AM +0800, Paul E. McKenney wrote: > Although there have been numerous complaints about the complexity of > parallel programming (especially over the past 5-10 years), the plain > truth is that the incremental complexity of parallel programming over > that of sequential programming is not as large as is commonly believed. > Despite that you might have heard, the mind-numbing complexity of modern > computer systems is not due so much to there being multiple CPUs, but > rather to there being any CPUs at all. In short, for the ultimate in > computer-system simplicity, the optimal choice is NR_CPUS=0. > > This commit therefore limits kernel builds to zero CPUs. This change > has the beneficial side effect of rendering all kernel bugs harmless. > Furthermore, this commit enables additional beneficial changes, for > example, the removal of those parts of the kernel that are not needed > when there are zero CPUs. > > Signed-off-by: Paul E. McKenney > Reviewed-by: Thomas Gleixner Great work, but I don't think you've gone far enough with this. What would really help is if you could consolidate all these NR_CPUS definitions into one place so we don't have essentially the same thing scattered across all these architectures. We're already doing this on ARM across our platforms, and its about time such an approach was taken across the entire kernel tree. It looks like the MIPS solution would be the best one to pick. Could you rework your patch to do this please? While you're at it, you might like to consider that having zero CPUs makes all this architecture support redundant, so maybe you've missed a trick there - according to my count, we could get rid of almost 3 million lines of code from arch. We could replace all that with a single standard implementation. Bah, maybe I shouldn't have pushed that bpf_jit code for ARM after all... From paulmck@linux.vnet.ibm.com Sun Apr 1 00:34:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 00:34:37 +0200 (CEST) Received: from e39.co.us.ibm.com ([32.97.110.160]:49237 "EHLO e39.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2CaWec (ORCPT ); Sun, 1 Apr 2012 00:34:32 +0200 Received: from /spool/local by e39.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sat, 31 Mar 2012 16:34:24 -0600 Received: from d03dlp03.boulder.ibm.com (9.17.202.179) by e39.co.us.ibm.com (192.168.1.139) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Sat, 31 Mar 2012 16:34:21 -0600 Received: from d03relay01.boulder.ibm.com (d03relay01.boulder.ibm.com [9.17.195.226]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id 9B55719D8048 for ; Sat, 31 Mar 2012 16:34:13 -0600 (MDT) Received: from d03av01.boulder.ibm.com (d03av01.boulder.ibm.com [9.17.195.167]) by d03relay01.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q2VMYLDs187470 for ; Sat, 31 Mar 2012 16:34:21 -0600 Received: from d03av01.boulder.ibm.com (loopback [127.0.0.1]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q2VMYJBL024491 for ; Sat, 31 Mar 2012 16:34:21 -0600 Received: from paulmck-ThinkPad-W500 (sig-9-49-152-53.mts.ibm.com [9.49.152.53]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q2VMYIOw024480; Sat, 31 Mar 2012 16:34:18 -0600 Received: by paulmck-ThinkPad-W500 (Postfix, from userid 1000) id 69335E4ABB; Sat, 31 Mar 2012 15:34:09 -0700 (PDT) Date: Sat, 31 Mar 2012 15:34:09 -0700 From: "Paul E. McKenney" To: Lorenz Kolb Cc: Eric Dumazet , linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-ia64@vger.kernel.org, linux-sh@vger.kernel.org, dhowells@redhat.com, sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, linux-am33-list@redhat.com, linux@arm.linux.org.uk, linux-hexagon@vger.kernel.org, x86@kernel.org, jejb@parisc-linux.org, cmetcalf@tilera.com, uclinux-dist-devel@blackfin.uclinux.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-m32r@ml.linux-m32r.org, linux-parisc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux390@de.ibm.com, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH RFC] Simplify the Linux kernel by reducing its state space Message-ID: <20120331223409.GM2450@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <20120331163321.GA15809@linux.vnet.ibm.com> <1333227608.2325.4054.camel@edumazet-glaptop> <20120331212149.GI2450@linux.vnet.ibm.com> <4F7782ED.7050407@lkmail.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4F7782ED.7050407@lkmail.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Content-Scanned: Fidelis XPS MAILER x-cbid: 12033122-4242-0000-0000-000001369589 X-archive-position: 32848 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paulmck@linux.vnet.ibm.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2875 Lines: 66 On Sun, Apr 01, 2012 at 12:19:25AM +0200, Lorenz Kolb wrote: > With that patchset in mind, I am working on a really huge patch, > which will greatly simplify the Linux kernel for the real problem > of having that number of CPUs. > > That patch will have a lot of changes all over the architectures, so > what will be the best way to post it? Should I split it architecture > dependend and into one generic part. > > Currently it is a large blob of millions of changes, but will > greatly simplify the Linux kernel. Perhaps a branch on a public git tree? If you are doing what I suspect you are, you will end up with a very large patch set. ;-) Thanx, Paul > Regards, > > Lorenz Kolb > > Am 31.03.2012 23:21, schrieb Paul E. McKenney: > >On Sat, Mar 31, 2012 at 11:00:08PM +0200, Eric Dumazet wrote: > >>On Sun, 2012-04-01 at 00:33 +0800, Paul E. McKenney wrote: > >>>Although there have been numerous complaints about the complexity of > >>>parallel programming (especially over the past 5-10 years), the plain > >>>truth is that the incremental complexity of parallel programming over > >>>that of sequential programming is not as large as is commonly believed. > >>>Despite that you might have heard, the mind-numbing complexity of modern > >>>computer systems is not due so much to there being multiple CPUs, but > >>>rather to there being any CPUs at all. In short, for the ultimate in > >>>computer-system simplicity, the optimal choice is NR_CPUS=0. > >>> > >>>This commit therefore limits kernel builds to zero CPUs. This change > >>>has the beneficial side effect of rendering all kernel bugs harmless. > >>>Furthermore, this commit enables additional beneficial changes, for > >>>example, the removal of those parts of the kernel that are not needed > >>>when there are zero CPUs. > >>> > >>>Signed-off-by: Paul E. McKenney > >>>Reviewed-by: Thomas Gleixner > >>>--- > >>Hmm... I believe you could go one step forward and allow negative values > >>as well. Antimatter was proven to exist after all. > >> > >>Hint : nr_cpu_ids is an "int", not an "unsigned int" > >> > >>Bonus: Existing bugs become "must have" features. > >;-) ;-) ;-) > > > >>Of course there is no hurry and this can wait 365 days. > >James Bottomley suggested imaginary numbers of CPUs some time back, > >and I suppose there is no reason you cannot have fractional numbers of > >CPUs, and perhaps irrational numbers as well. Of course, these last two > >would require use of floating-point arithmetic (or something similar) > >in the kernel. So I guess we have at several years worth. Over to you > >for the negative numbers. ;-) > > > > Thanx, Paul > > > >_______________________________________________ > >Linuxppc-dev mailing list > >Linuxppc-dev@lists.ozlabs.org > >https://lists.ozlabs.org/listinfo/linuxppc-dev > From paulmck@linux.vnet.ibm.com Sun Apr 1 03:22:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 03:22:40 +0200 (CEST) Received: from e33.co.us.ibm.com ([32.97.110.151]:60986 "EHLO e33.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903702Ab2DABWf (ORCPT ); Sun, 1 Apr 2012 03:22:35 +0200 Received: from /spool/local by e33.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sat, 31 Mar 2012 19:22:28 -0600 Received: from d03dlp01.boulder.ibm.com (9.17.202.177) by e33.co.us.ibm.com (192.168.1.133) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Sat, 31 Mar 2012 19:22:26 -0600 Received: from d03relay02.boulder.ibm.com (d03relay02.boulder.ibm.com [9.17.195.227]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id AA9A71FF004A for ; Sat, 31 Mar 2012 19:22:23 -0600 (MDT) Received: from d03av01.boulder.ibm.com (d03av01.boulder.ibm.com [9.17.195.167]) by d03relay02.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q311MNZR144190 for ; Sat, 31 Mar 2012 19:22:24 -0600 Received: from d03av01.boulder.ibm.com (loopback [127.0.0.1]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q311MMRm022984 for ; Sat, 31 Mar 2012 19:22:23 -0600 Received: from paulmck-ThinkPad-W500 (sig-9-49-152-53.mts.ibm.com [9.49.152.53]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q311ML7p022961; Sat, 31 Mar 2012 19:22:22 -0600 Received: by paulmck-ThinkPad-W500 (Postfix, from userid 1000) id B5E0BE4ABB; Sat, 31 Mar 2012 18:22:12 -0700 (PDT) Date: Sat, 31 Mar 2012 18:22:12 -0700 From: "Paul E. McKenney" To: Russell King - ARM Linux Cc: linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, tglx@linutronix.de, dhowells@redhat.com, jejb@parisc-linux.org, linux390@de.ibm.com, x86@kernel.org, cmetcalf@tilera.com Subject: Re: [PATCH RFC] Simplify the Linux kernel by reducing its state space Message-ID: <20120401012212.GP2450@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <20120331163321.GA15809@linux.vnet.ibm.com> <20120331223200.GA32482@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120331223200.GA32482@n2100.arm.linux.org.uk> User-Agent: Mutt/1.5.21 (2010-09-15) X-Content-Scanned: Fidelis XPS MAILER x-cbid: 12040101-2398-0000-0000-0000057BFD9B X-archive-position: 32849 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paulmck@linux.vnet.ibm.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2127 Lines: 43 On Sat, Mar 31, 2012 at 11:32:00PM +0100, Russell King - ARM Linux wrote: > On Sun, Apr 01, 2012 at 12:33:21AM +0800, Paul E. McKenney wrote: > > Although there have been numerous complaints about the complexity of > > parallel programming (especially over the past 5-10 years), the plain > > truth is that the incremental complexity of parallel programming over > > that of sequential programming is not as large as is commonly believed. > > Despite that you might have heard, the mind-numbing complexity of modern > > computer systems is not due so much to there being multiple CPUs, but > > rather to there being any CPUs at all. In short, for the ultimate in > > computer-system simplicity, the optimal choice is NR_CPUS=0. > > > > This commit therefore limits kernel builds to zero CPUs. This change > > has the beneficial side effect of rendering all kernel bugs harmless. > > Furthermore, this commit enables additional beneficial changes, for > > example, the removal of those parts of the kernel that are not needed > > when there are zero CPUs. > > > > Signed-off-by: Paul E. McKenney > > Reviewed-by: Thomas Gleixner > > Great work, but I don't think you've gone far enough with this. > > What would really help is if you could consolidate all these NR_CPUS > definitions into one place so we don't have essentially the same thing > scattered across all these architectures. We're already doing this on > ARM across our platforms, and its about time such an approach was taken > across the entire kernel tree. > > It looks like the MIPS solution would be the best one to pick. > Could you rework your patch to do this please? > > While you're at it, you might like to consider that having zero CPUs > makes all this architecture support redundant, so maybe you've missed > a trick there - according to my count, we could get rid of almost 3 > million lines of code from arch. We could replace all that with a > single standard implementation. > > Bah, maybe I shouldn't have pushed that bpf_jit code for ARM after all... ;-) ;-) ;-) Thanx, Paul From rusty@rustcorp.com.au Sun Apr 1 07:56:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 07:56:34 +0200 (CEST) Received: from ozlabs.org ([203.10.76.45]:38444 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903638Ab2DAF4Y (ORCPT ); Sun, 1 Apr 2012 07:56:24 +0200 Received: by ozlabs.org (Postfix, from userid 1011) id B01DDB6EEC; Sun, 1 Apr 2012 15:56:18 +1000 (EST) From: Rusty Russell To: "Linus Torvalds" Cc: "LKML" Cc: Chris Metcalf (arch/tile) Cc: cpufreq@vger.kernel.org Cc: Dave Jones Cc: Helge Deller Cc: Jonas Aaberg Cc: Kyle McMartin Cc: linux-arm-kernel@lists.infradead.org Cc: linux-hexagon@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Martin Persson Cc: Ralf Baechle Cc: Richard Kuo Cc: Russell King Cc: Sundar Iyer Cc: user-mode-linux-devel@lists.sourceforge.net Subject: [PULL] cpumask cleanups User-Agent: Notmuch/0.6.1-1 (http://notmuchmail.org) Emacs/23.3.1 (i686-pc-linux-gnu) Date: Sun, 01 Apr 2012 15:25:50 +0930 Message-ID: <87sjgovvvd.fsf@rustcorp.com.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-archive-position: 32850 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rusty@rustcorp.com.au Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2343 Lines: 51 (Somehow forgot to send this out; it's been sitting in linux-next, and if you don't want it, it can sit there another cycle) To git@github.com:rustyrussell/linux.git f946eeb..615399c master -> master + 9dcbe9d...6ac67b9 for-linus -> for-linus (forced update) The following changes since commit b5174fa3a7f4f8f150bfa3b917c92608953dfa0f: Merge tag 'mmc-merge-for-3.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc (2012-03-28 20:59:45 -0700) are available in the git repository at: git://github.com/rustyrussell/linux.git master Rusty Russell (4): remove references to cpu_*_map in arch/ drivers/cpufreq/db8500-cpufreq: remove references to cpu_*_map. documentation: remove references to cpu_*_map. cpumask: remove old cpu_*_map. Documentation/cgroups/cpusets.txt | 2 +- Documentation/cpu-hotplug.txt | 22 +++++++++++----------- arch/alpha/kernel/smp.c | 2 +- arch/arm/kernel/kprobes.c | 4 ++-- arch/arm/kernel/smp.c | 7 ++++--- arch/hexagon/kernel/smp.c | 8 ++++---- arch/ia64/kernel/acpi.c | 2 +- arch/mips/cavium-octeon/smp.c | 4 ++-- arch/mips/kernel/mips-mt-fpaff.c | 2 +- arch/mips/kernel/proc.c | 2 +- arch/mips/kernel/smp-bmips.c | 2 +- arch/mips/kernel/smp.c | 27 ++++++++++++--------------- arch/mips/kernel/smtc.c | 2 +- arch/mips/mm/c-octeon.c | 6 +++--- arch/mips/netlogic/common/smp.c | 6 +++--- arch/mips/pmc-sierra/yosemite/smp.c | 8 ++++---- arch/mips/sgi-ip27/ip27-smp.c | 2 +- arch/mips/sibyte/bcm1480/smp.c | 7 +++---- arch/mips/sibyte/sb1250/smp.c | 7 +++---- arch/sparc/kernel/leon_kernel.c | 6 +++--- arch/tile/kernel/setup.c | 8 ++++---- arch/um/kernel/skas/process.c | 2 +- arch/um/kernel/smp.c | 9 ++++----- arch/x86/xen/enlighten.c | 2 +- drivers/cpufreq/db8500-cpufreq.c | 2 +- include/linux/cpumask.h | 6 ------ init/Kconfig | 4 ++-- kernel/cpuset.c | 10 +++++----- 28 files changed, 80 insertions(+), 91 deletions(-) -- How could I marry someone with more hair than me? http://baldalex.org From bp@alien8.de Sun Apr 1 12:04:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 12:04:55 +0200 (CEST) Received: from mail.skyhub.de ([78.46.96.112]:56907 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903642Ab2DAKEv (ORCPT ); Sun, 1 Apr 2012 12:04:51 +0200 Received: from localhost (localhost [127.0.0.1]) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTP id 4487F1D9C11; Sun, 1 Apr 2012 12:04:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alien8.de; s=alien8; t=1333274690; bh=fgfW1dIwbkHrIwNqgGQYRlP+jtXz1e1sbfrsBb6KgmY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:In-Reply-To; b=YaX6/gEGQne0Sa4MLA6gXja4tar7YIHIlSnZZy Hv2rbpF08atGOYiVww/ccmWVM0IJDn4VoPI5BAvKkqaxR8EGg9ra+1IGoNFEPIEpvDp 2VBWYpevhqiniR5klEScrQY03tribAqda01SWT34RpeQinIZdpS9pPDX2IamL4Vnyc= X-Virus-Scanned: Nedap ESD1 at mail.skyhub.de Received: from mail.skyhub.de ([127.0.0.1]) by localhost (door.skyhub.de [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id a4sRHMOeaefi; Sun, 1 Apr 2012 12:04:50 +0200 (CEST) Received: from liondog.tnic (p4FF1D52B.dip.t-dialin.net [79.241.213.43]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id A52D71D9B04; Sun, 1 Apr 2012 12:04:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alien8.de; s=alien8; t=1333274689; bh=fgfW1dIwbkHrIwNqgGQYRlP+jtXz1e1sbfrsBb6KgmY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:In-Reply-To; b=BdGci+M7wnSfbDrg7Zjh5aTbjEidehfCbQY8Bw oTqjS9ycftxmrSI0Nr0Ndaz/kfLkqlH9BNgdvadcKVZ87Txawq/voaoPLnTUeNj4FJs KCwdy2/0dwU6zs4KHpgZ8Haex+De2enfOZ5nyOxYegw3khCPoCTx+Fjjm7DgNusIqs= Received: by liondog.tnic (Postfix, from userid 1000) id 455264B8D46; Sun, 1 Apr 2012 12:04:48 +0200 (CEST) Date: Sun, 1 Apr 2012 12:04:48 +0200 From: Borislav Petkov To: "Paul E. McKenney" Cc: linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, tglx@linutronix.de, linux@arm.linux.org.uk, dhowells@redhat.com, jejb@parisc-linux.org, linux390@de.ibm.com, x86@kernel.org, cmetcalf@tilera.com Subject: Re: [PATCH RFC] Simplify the Linux kernel by reducing its state space Message-ID: <20120401100448.GD14848@liondog.tnic> Mail-Followup-To: Borislav Petkov , "Paul E. McKenney" , linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, tglx@linutronix.de, linux@arm.linux.org.uk, dhowells@redhat.com, jejb@parisc-linux.org, linux390@de.ibm.com, x86@kernel.org, cmetcalf@tilera.com References: <20120331163321.GA15809@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20120331163321.GA15809@linux.vnet.ibm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bp@alien8.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1472 Lines: 34 On Sun, Apr 01, 2012 at 12:33:21AM +0800, Paul E. McKenney wrote: > Although there have been numerous complaints about the complexity of > parallel programming (especially over the past 5-10 years), the plain > truth is that the incremental complexity of parallel programming over > that of sequential programming is not as large as is commonly believed. > Despite that you might have heard, the mind-numbing complexity of modern > computer systems is not due so much to there being multiple CPUs, but > rather to there being any CPUs at all. In short, for the ultimate in > computer-system simplicity, the optimal choice is NR_CPUS=0. > > This commit therefore limits kernel builds to zero CPUs. This change > has the beneficial side effect of rendering all kernel bugs harmless. > Furthermore, this commit enables additional beneficial changes, for > example, the removal of those parts of the kernel that are not needed > when there are zero CPUs. > > Signed-off-by: Paul E. McKenney > Reviewed-by: Thomas Gleixner Looks good, thanks for doing that. Btw, I just got confirmation from hw folk that we can actually give you hardware support for that code with an upcoming CPU which has NR_CPUS=0 cores. Oh, and additionally, we can disable some of those so getting into the negative is also doable from the hw perspective, so feel free to explore that side of the problem too. ACK. -- Regards/Gruss, Boris. From aaro.koskinen@iki.fi Sun Apr 1 18:54:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 18:54:25 +0200 (CEST) Received: from filtteri1.pp.htv.fi ([213.243.153.184]:34000 "EHLO filtteri1.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903717Ab2DAQyS (ORCPT ); Sun, 1 Apr 2012 18:54:18 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri1.pp.htv.fi (Postfix) with ESMTP id 0A95721B020; Sun, 1 Apr 2012 19:54:18 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp5.welho.com ([213.243.153.39]) by localhost (filtteri1.pp.htv.fi [213.243.153.184]) (amavisd-new, port 10024) with ESMTP id Qa4hSwoNHeZV; Sun, 1 Apr 2012 19:54:17 +0300 (EEST) Received: from dell.pp.htv.fi (cs78193253.pp.htv.fi [62.78.193.253]) by smtp5.welho.com (Postfix) with ESMTP id 910755BC002; Sun, 1 Apr 2012 19:54:17 +0300 (EEST) From: Aaro Koskinen To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH] mips: cmpxchg: add missing include Date: Sun, 1 Apr 2012 19:54:13 +0300 Message-Id: <1333299253-3308-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 32852 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 840 Lines: 28 Fix the following build breakage in v3.4-rc1: CC kernel/irq_work.o In file included from include/linux/irq_work.h:4:0, from kernel/irq_work.c:10: include/linux/llist.h: In function 'llist_del_all': include/linux/llist.h:178:2: error: implicit declaration of function 'BUILD_BUG_ON' [-Werror=implicit-function-declaration] Signed-off-by: Aaro Koskinen --- arch/mips/include/asm/cmpxchg.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index 285a41f..eee10dc 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -8,6 +8,7 @@ #ifndef __ASM_CMPXCHG_H #define __ASM_CMPXCHG_H +#include #include #include -- 1.7.2.5 From tglx@linutronix.de Sun Apr 1 19:35:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 19:35:27 +0200 (CEST) Received: from www.linutronix.de ([62.245.132.108]:57170 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903720Ab2DARfW (ORCPT ); Sun, 1 Apr 2012 19:35:22 +0200 Received: from localhost ([127.0.0.1]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SEOg5-00051j-Aw; Sun, 01 Apr 2012 19:34:57 +0200 Date: Sun, 1 Apr 2012 19:34:55 +0200 (CEST) From: Thomas Gleixner To: Russell King - ARM Linux cc: "Paul E. McKenney" , linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, dhowells@redhat.com, jejb@parisc-linux.org, linux390@de.ibm.com, x86@kernel.org, cmetcalf@tilera.com Subject: Re: [PATCH RFC] Simplify the Linux kernel by reducing its state space In-Reply-To: <20120331223200.GA32482@n2100.arm.linux.org.uk> Message-ID: References: <20120331163321.GA15809@linux.vnet.ibm.com> <20120331223200.GA32482@n2100.arm.linux.org.uk> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 X-archive-position: 32853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tglx@linutronix.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3682 Lines: 92 On Sat, 31 Mar 2012, Russell King - ARM Linux wrote: > On Sun, Apr 01, 2012 at 12:33:21AM +0800, Paul E. McKenney wrote: > > Although there have been numerous complaints about the complexity of > > parallel programming (especially over the past 5-10 years), the plain > > truth is that the incremental complexity of parallel programming over > > that of sequential programming is not as large as is commonly believed. > > Despite that you might have heard, the mind-numbing complexity of modern > > computer systems is not due so much to there being multiple CPUs, but > > rather to there being any CPUs at all. In short, for the ultimate in > > computer-system simplicity, the optimal choice is NR_CPUS=0. > > > > This commit therefore limits kernel builds to zero CPUs. This change > > has the beneficial side effect of rendering all kernel bugs harmless. > > Furthermore, this commit enables additional beneficial changes, for > > example, the removal of those parts of the kernel that are not needed > > when there are zero CPUs. > > > > Signed-off-by: Paul E. McKenney > > Reviewed-by: Thomas Gleixner > > Great work, but I don't think you've gone far enough with this. > > What would really help is if you could consolidate all these NR_CPUS > definitions into one place so we don't have essentially the same thing > scattered across all these architectures. We're already doing this on > ARM across our platforms, and its about time such an approach was taken > across the entire kernel tree. > > It looks like the MIPS solution would be the best one to pick. > Could you rework your patch to do this please? > > While you're at it, you might like to consider that having zero CPUs > makes all this architecture support redundant, so maybe you've missed > a trick there - according to my count, we could get rid of almost 3 > million lines of code from arch. We could replace all that with a > single standard implementation. For a first step we can deprecated arch/ and make it depend on CONFIG_STAGING. That way we can have it around a bit for sentimental reasons w/o having a lot of churn. Suggested-by: Russell King Signed-off-by: Thomas Gleixner Index: tip/Makefile =================================================================== --- tip.orig/Makefile +++ tip/Makefile @@ -564,7 +564,9 @@ else KBUILD_CFLAGS += -O2 endif +ifdef CONFIG_ARCH_SUPPORT include $(srctree)/arch/$(SRCARCH)/Makefile +endif ifneq ($(CONFIG_FRAME_WARN),0) KBUILD_CFLAGS += $(call cc-option,-Wframe-larger-than=${CONFIG_FRAME_WARN}) Index: tip/drivers/staging/Kconfig =================================================================== --- tip.orig/drivers/staging/Kconfig +++ tip/drivers/staging/Kconfig @@ -1,6 +1,10 @@ +config ARCH_SUPPORT + bool + menuconfig STAGING bool "Staging drivers" default n + select ARCH_SUPPORT ---help--- This option allows you to select a number of drivers that are not of the "normal" Linux kernel quality level. These drivers Index: tip/Documentation/feature-removal-schedule.txt =================================================================== --- tip.orig/Documentation/feature-removal-schedule.txt +++ tip/Documentation/feature-removal-schedule.txt @@ -537,3 +537,13 @@ When: 3.6 Why: setitimer is not returning -EFAULT if user pointer is NULL. This violates the spec. Who: Sasikantha Babu + +----------------------------- + +What: Remove arch +When: April 1st 2013 +Why: NR_CPUS=0 made arch/ obsolete. Keep it around a bit for + sentimental reasons. +Who: paulmck,tglx.rmk + + From paulmck@linux.vnet.ibm.com Sun Apr 1 20:11:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 20:11:41 +0200 (CEST) Received: from e39.co.us.ibm.com ([32.97.110.160]:51223 "EHLO e39.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903724Ab2DASLg (ORCPT ); Sun, 1 Apr 2012 20:11:36 +0200 Received: from /spool/local by e39.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 1 Apr 2012 12:11:29 -0600 Received: from d03dlp03.boulder.ibm.com (9.17.202.179) by e39.co.us.ibm.com (192.168.1.139) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Sun, 1 Apr 2012 12:11:27 -0600 Received: from d03relay03.boulder.ibm.com (d03relay03.boulder.ibm.com [9.17.195.228]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id 64DC819D8048 for ; Sun, 1 Apr 2012 12:11:19 -0600 (MDT) Received: from d03av01.boulder.ibm.com (d03av01.boulder.ibm.com [9.17.195.167]) by d03relay03.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q31IBR0n189660 for ; Sun, 1 Apr 2012 12:11:27 -0600 Received: from d03av01.boulder.ibm.com (loopback [127.0.0.1]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q31IBPGX024210 for ; Sun, 1 Apr 2012 12:11:26 -0600 Received: from paulmck-ThinkPad-W500 (sig-9-49-152-53.mts.ibm.com [9.49.152.53]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q31IBO59024187; Sun, 1 Apr 2012 12:11:25 -0600 Received: by paulmck-ThinkPad-W500 (Postfix, from userid 1000) id 0E3C3E4ABB; Sun, 1 Apr 2012 11:11:15 -0700 (PDT) Date: Sun, 1 Apr 2012 11:11:15 -0700 From: "Paul E. McKenney" To: Borislav Petkov , linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, tglx@linutronix.de, linux@arm.linux.org.uk, dhowells@redhat.com, jejb@parisc-linux.org, linux390@de.ibm.com, x86@kernel.org, cmetcalf@tilera.com Subject: Re: [PATCH RFC] Simplify the Linux kernel by reducing its state space Message-ID: <20120401181114.GY2450@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <20120331163321.GA15809@linux.vnet.ibm.com> <20120401100448.GD14848@liondog.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120401100448.GD14848@liondog.tnic> User-Agent: Mutt/1.5.21 (2010-09-15) X-Content-Scanned: Fidelis XPS MAILER x-cbid: 12040118-4242-0000-0000-00000137C7FF X-archive-position: 32854 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paulmck@linux.vnet.ibm.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1599 Lines: 36 On Sun, Apr 01, 2012 at 12:04:48PM +0200, Borislav Petkov wrote: > On Sun, Apr 01, 2012 at 12:33:21AM +0800, Paul E. McKenney wrote: > > Although there have been numerous complaints about the complexity of > > parallel programming (especially over the past 5-10 years), the plain > > truth is that the incremental complexity of parallel programming over > > that of sequential programming is not as large as is commonly believed. > > Despite that you might have heard, the mind-numbing complexity of modern > > computer systems is not due so much to there being multiple CPUs, but > > rather to there being any CPUs at all. In short, for the ultimate in > > computer-system simplicity, the optimal choice is NR_CPUS=0. > > > > This commit therefore limits kernel builds to zero CPUs. This change > > has the beneficial side effect of rendering all kernel bugs harmless. > > Furthermore, this commit enables additional beneficial changes, for > > example, the removal of those parts of the kernel that are not needed > > when there are zero CPUs. > > > > Signed-off-by: Paul E. McKenney > > Reviewed-by: Thomas Gleixner > > Looks good, thanks for doing that. > > Btw, I just got confirmation from hw folk that we can actually give you > hardware support for that code with an upcoming CPU which has NR_CPUS=0 > cores. > > Oh, and additionally, we can disable some of those so getting into the > negative is also doable from the hw perspective, so feel free to explore > that side of the problem too. > > ACK. Cute! ;-) Thanx, Paul From paulmck@linux.vnet.ibm.com Sun Apr 1 20:12:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2012 20:12:41 +0200 (CEST) Received: from e32.co.us.ibm.com ([32.97.110.150]:48656 "EHLO e32.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903728Ab2DASMd (ORCPT ); Sun, 1 Apr 2012 20:12:33 +0200 Received: from /spool/local by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 1 Apr 2012 12:12:26 -0600 Received: from d03dlp03.boulder.ibm.com (9.17.202.179) by e32.co.us.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Sun, 1 Apr 2012 12:12:24 -0600 Received: from d03relay02.boulder.ibm.com (d03relay02.boulder.ibm.com [9.17.195.227]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id 3E02719D8048 for ; Sun, 1 Apr 2012 12:12:16 -0600 (MDT) Received: from d03av01.boulder.ibm.com (d03av01.boulder.ibm.com [9.17.195.167]) by d03relay02.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q31ICNfo191644 for ; Sun, 1 Apr 2012 12:12:23 -0600 Received: from d03av01.boulder.ibm.com (loopback [127.0.0.1]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q31ICMob026550 for ; Sun, 1 Apr 2012 12:12:23 -0600 Received: from paulmck-ThinkPad-W500 (sig-9-49-152-53.mts.ibm.com [9.49.152.53]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q31ICLaX026518; Sun, 1 Apr 2012 12:12:21 -0600 Received: by paulmck-ThinkPad-W500 (Postfix, from userid 1000) id B6E85E4ABB; Sun, 1 Apr 2012 11:12:11 -0700 (PDT) Date: Sun, 1 Apr 2012 11:12:11 -0700 From: "Paul E. McKenney" To: Thomas Gleixner Cc: Russell King - ARM Linux , linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, dhowells@redhat.com, jejb@parisc-linux.org, linux390@de.ibm.com, x86@kernel.org, cmetcalf@tilera.com Subject: Re: [PATCH RFC] Simplify the Linux kernel by reducing its state space Message-ID: <20120401181211.GZ2450@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <20120331163321.GA15809@linux.vnet.ibm.com> <20120331223200.GA32482@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Content-Scanned: Fidelis XPS MAILER x-cbid: 12040118-3270-0000-0000-0000053D61CD X-archive-position: 32855 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paulmck@linux.vnet.ibm.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4024 Lines: 101 On Sun, Apr 01, 2012 at 07:34:55PM +0200, Thomas Gleixner wrote: > On Sat, 31 Mar 2012, Russell King - ARM Linux wrote: > > > On Sun, Apr 01, 2012 at 12:33:21AM +0800, Paul E. McKenney wrote: > > > Although there have been numerous complaints about the complexity of > > > parallel programming (especially over the past 5-10 years), the plain > > > truth is that the incremental complexity of parallel programming over > > > that of sequential programming is not as large as is commonly believed. > > > Despite that you might have heard, the mind-numbing complexity of modern > > > computer systems is not due so much to there being multiple CPUs, but > > > rather to there being any CPUs at all. In short, for the ultimate in > > > computer-system simplicity, the optimal choice is NR_CPUS=0. > > > > > > This commit therefore limits kernel builds to zero CPUs. This change > > > has the beneficial side effect of rendering all kernel bugs harmless. > > > Furthermore, this commit enables additional beneficial changes, for > > > example, the removal of those parts of the kernel that are not needed > > > when there are zero CPUs. > > > > > > Signed-off-by: Paul E. McKenney > > > Reviewed-by: Thomas Gleixner > > > > Great work, but I don't think you've gone far enough with this. > > > > What would really help is if you could consolidate all these NR_CPUS > > definitions into one place so we don't have essentially the same thing > > scattered across all these architectures. We're already doing this on > > ARM across our platforms, and its about time such an approach was taken > > across the entire kernel tree. > > > > It looks like the MIPS solution would be the best one to pick. > > Could you rework your patch to do this please? > > > > While you're at it, you might like to consider that having zero CPUs > > makes all this architecture support redundant, so maybe you've missed > > a trick there - according to my count, we could get rid of almost 3 > > million lines of code from arch. We could replace all that with a > > single standard implementation. > > For a first step we can deprecated arch/ and make it depend on > CONFIG_STAGING. That way we can have it around a bit for sentimental > reasons w/o having a lot of churn. > > Suggested-by: Russell King > Signed-off-by: Thomas Gleixner ;-) ;-) ;-) Reviewed-by: Paul E. McKenney Thanx, Paul > Index: tip/Makefile > =================================================================== > --- tip.orig/Makefile > +++ tip/Makefile > @@ -564,7 +564,9 @@ else > KBUILD_CFLAGS += -O2 > endif > > +ifdef CONFIG_ARCH_SUPPORT > include $(srctree)/arch/$(SRCARCH)/Makefile > +endif > > ifneq ($(CONFIG_FRAME_WARN),0) > KBUILD_CFLAGS += $(call cc-option,-Wframe-larger-than=${CONFIG_FRAME_WARN}) > Index: tip/drivers/staging/Kconfig > =================================================================== > --- tip.orig/drivers/staging/Kconfig > +++ tip/drivers/staging/Kconfig > @@ -1,6 +1,10 @@ > +config ARCH_SUPPORT > + bool > + > menuconfig STAGING > bool "Staging drivers" > default n > + select ARCH_SUPPORT > ---help--- > This option allows you to select a number of drivers that are > not of the "normal" Linux kernel quality level. These drivers > Index: tip/Documentation/feature-removal-schedule.txt > =================================================================== > --- tip.orig/Documentation/feature-removal-schedule.txt > +++ tip/Documentation/feature-removal-schedule.txt > @@ -537,3 +537,13 @@ When: 3.6 > Why: setitimer is not returning -EFAULT if user pointer is NULL. This > violates the spec. > Who: Sasikantha Babu > + > +----------------------------- > + > +What: Remove arch > +When: April 1st 2013 > +Why: NR_CPUS=0 made arch/ obsolete. Keep it around a bit for > + sentimental reasons. > +Who: paulmck,tglx.rmk > + > + > From dedekind1@gmail.com Mon Apr 2 13:05:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Apr 2012 13:05:47 +0200 (CEST) Received: from mga01.intel.com ([192.55.52.88]:2472 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903756Ab2DBLFk (ORCPT ); Mon, 2 Apr 2012 13:05:40 +0200 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 02 Apr 2012 04:05:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="asc'?scan'208";a="136540543" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by fmsmga001.fm.intel.com with ESMTP; 02 Apr 2012 04:05:33 -0700 Received: from [10.237.72.167] (sauron.fi.intel.com [10.237.72.167]) by linux.intel.com (Postfix) with ESMTP id 9DAD56A4008; Mon, 2 Apr 2012 04:05:29 -0700 (PDT) Message-ID: <1333364925.5440.104.camel@sauron.fi.intel.com> Subject: Re: [PATCH 0/5] mtd: plat_nand: Add default partition parser and use it From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: H Hartley Sweeten Cc: Linux Kernel , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linux-sh@vger.kernel.org, linux-mips@linux-mips.org Date: Mon, 02 Apr 2012 14:08:45 +0300 In-Reply-To: <201203281112.48788.hartleys@visionengravers.com> References: <201203281112.48788.hartleys@visionengravers.com> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-tYG+VEjJEvHHNxPyqYt8" X-Mailer: Evolution 3.2.3 (3.2.3-2.fc16) Mime-Version: 1.0 X-archive-position: 32857 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1637 Lines: 46 --=-tYG+VEjJEvHHNxPyqYt8 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2012-03-28 at 11:12 -0700, H Hartley Sweeten wrote: > This patch series adds cmdlinepart as the default partition parser for th= e > plat_nand driver and updates all the arch setup code to use it. >=20 > Arch setup code that requires other partition parsers can still pass that > information as chip.part_probe_types. >=20 > Signed-off-by: H Hartley Sweeten Pushed the series to l2-mtd.git, thanks! --=20 Best Regards, Artem Bityutskiy --=-tYG+VEjJEvHHNxPyqYt8 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPeYi9AAoJECmIfjd9wqK01TkQAMewuEX1gPp1EPSpGZQcSvXs jsTvmYqJE6vhHRv8KlbN+bfz5Gjh4xsUyz63/QqILHv8ru3R3MypineF9tGlV+k+ fvWdcmMuXQ4VmkfsIKQIQ4Y51wWJG91J4QG5Va/Epk7yXzyvskINWN3YWKp0J0Mk zePW7mBxEZFFRr45/sTK7Wx3Us8FU3NEV71cbXWjjw+AosLc4G92dIDXEie7BTUn OqS2+oRbNyigsDSb9WPTAu4O9Ln5p7F99elipFtBP/OGuSVK9Q92ImUwPB6FJf6E +rZs/PiYrfMxkyCUsIw/4FVT49PbRusDsVSKzIrTxzzZ/mjb6ANx3gRJBqDXNyvH hdhzlacV4H4Id60jIuDeAocI95v39MPX5oQ075P4dNBDd06og9K0RGXvpFPXrVy5 ZUwfws9ltOEy1oo4Mg8FpJ6j2OWTK/9xc0jFHcLB8WrQ669W9ScM+xQNpki1eaJk u5qPSAYr7mod3RLahiPytspkqGdXdtdK256ceUZ0c2u/Bc18mEtq27flRVA3/tc5 OiWFAS+8d/qCR8evTAn5PSJoGmZk0ZAldcoZ2IRimwEuz8aXZjdX0pkezc8yhulV INJBhHNlei00Rop7Gq851ob32uUQrUO5DiPyhF/4WwIxMfeTQ3PsYjEI+j3IzfEF DyRHjIGr/NVucPumONWe =pJwc -----END PGP SIGNATURE----- --=-tYG+VEjJEvHHNxPyqYt8-- From standby24x7@gmail.com Tue Apr 3 14:02:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Apr 2012 14:02:17 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:50501 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903649Ab2DCMCA (ORCPT ); Tue, 3 Apr 2012 14:02:00 +0200 Received: by dadq36 with SMTP id q36so2907831dad.36 for ; Tue, 03 Apr 2012 05:01:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=OmAowsoKBYdtqANVRaFu3OqJ9T1GmGB++S0MxYkbkBI=; b=jbWSSCXaTniCcxDkId0lBTybfjRicuJtW0BI7ldpbuwbk4oK3eHRwdxFvxr5xBp11g 4sakt7VUJ88OtPc/ejVBqw4VRgNTg6cmTjDGlqe+mUv+/U/PFFxsneITsFHqpx83/oUw Le0CpdLzKylfDz16YAwqN1bZ/v3RdfxkJ96RRQrkSg0CaXnTNwL6ojIbEVuYKEluQwDS EY1p/wLd9Z77LE5ztyebIB7inkJh5weIG/dfTLYEDq4K4NjzO3KuxkxJO/Z7mBXQ/q4x xW26icj0zJPTZ87A3iDHF4egnkYHAzzPFBBpfmamaAOmvI04KGgF85O19AC+QX2iv/qX TSlg== Received: by 10.68.221.227 with SMTP id qh3mr28557793pbc.43.1333454513295; Tue, 03 Apr 2012 05:01:53 -0700 (PDT) Received: from masabert (i118-21-156-233.s30.a048.ap.plala.or.jp. [118.21.156.233]) by mx.google.com with ESMTPS id r10sm16200208pbf.22.2012.04.03.05.01.51 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 03 Apr 2012 05:01:52 -0700 (PDT) Received: by masabert (Postfix, from userid 500) id 91AA1A36E5; Tue, 3 Apr 2012 21:01:48 +0900 (JST) From: Masanari Iida To: linux-mips@linux-mips.org Cc: trivial@kernel.org, linux-kernel@vger.kernel.org, Masanari Iida , Ralf Baechle Subject: [PATCH] [trivial] mips: Fix typo in mips Date: Tue, 3 Apr 2012 21:01:45 +0900 Message-Id: <1333454506-7625-1-git-send-email-standby24x7@gmail.com> X-Mailer: git-send-email 1.7.10.rc3.11.gd8282 X-archive-position: 32858 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: standby24x7@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4475 Lines: 127 Correct spelling typo in printk messages, comments and macro. Signed-off-by: Masanari Iida Cc: Ralf Baechle --- arch/mips/Kconfig | 4 ++-- arch/mips/Kconfig.debug | 2 +- arch/mips/lantiq/xway/dma.c | 6 +++--- arch/mips/lantiq/xway/gpio.c | 2 +- arch/mips/lantiq/xway/gpio_ebu.c | 2 +- arch/mips/lantiq/xway/gpio_stp.c | 2 +- arch/mips/pci/pci-lantiq.c | 2 +- 7 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ce30e2f..923a6c3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1001,12 +1001,12 @@ config HOLES_IN_ZONE bool # -# Endianess selection. Sufficiently obscure so many users don't know what to +# Endianness selection. Sufficiently obscure so many users don't know what to # answer,so we try hard to limit the available choices. Also the use of a # choice statement should be more obvious to the user. # choice - prompt "Endianess selection" + prompt "Endianness selection" help Some MIPS machines can be configured for either little or big endian byte order. These modes require different kernels and a different diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 83ed00a..5a43aa0 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -57,7 +57,7 @@ config CMDLINE options. config CMDLINE_OVERRIDE - bool "Built-in command line overrides firware arguments" + bool "Built-in command line overrides firmware arguments" default n depends on CMDLINE_BOOL help diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index b210e93..d1eafb0 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -47,7 +47,7 @@ #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ #define DMA_2W_BURST BIT(1) /* 2 word burst length */ #define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ -#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */ +#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) @@ -197,10 +197,10 @@ ltq_dma_init_port(int p) switch (p) { case DMA_PORT_ETOP: /* - * Tell the DMA engine to swap the endianess of data frames and + * Tell the DMA engine to swap the endianness of data frames and * drop packets if the channel arbitration fails. */ - ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN, + ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, LTQ_DMA_PCTRL); break; diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c index d2fa98f..c429a5b 100644 --- a/arch/mips/lantiq/xway/gpio.c +++ b/arch/mips/lantiq/xway/gpio.c @@ -188,7 +188,7 @@ int __init ltq_gpio_init(void) int ret = platform_driver_register(<q_gpio_driver); if (ret) - pr_info("ltq_gpio : Error registering platfom driver!"); + pr_info("ltq_gpio : Error registering platform driver!"); return ret; } diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c index b91c7f1..aae1717 100644 --- a/arch/mips/lantiq/xway/gpio_ebu.c +++ b/arch/mips/lantiq/xway/gpio_ebu.c @@ -119,7 +119,7 @@ static int __init ltq_ebu_init(void) int ret = platform_driver_register(<q_ebu_driver); if (ret) - pr_info("ltq_ebu : Error registering platfom driver!"); + pr_info("ltq_ebu : Error registering platform driver!"); return ret; } diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index ff9991c..fd07d87 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -150,7 +150,7 @@ int __init ltq_stp_init(void) int ret = platform_driver_register(<q_stp_driver); if (ret) - pr_info("ltq_stp: error registering platfom driver"); + pr_info("ltq_stp: error registering platform driver"); return ret; } diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 030c77e..70fdf2c 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -297,7 +297,7 @@ int __init pcibios_init(void) { int ret = platform_driver_register(<q_pci_driver); if (ret) - printk(KERN_INFO "ltq_pci: Error registering platfom driver!"); + printk(KERN_INFO "ltq_pci: Error registering platform driver!"); return ret; } -- 1.7.10.rc3.11.gd8282 From macro@linux-mips.org Tue Apr 3 14:26:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Apr 2012 14:26:12 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:41698 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903797Ab2DCM0H (ORCPT ); Tue, 3 Apr 2012 14:26:07 +0200 Date: Tue, 3 Apr 2012 13:26:07 +0100 (BST) From: "Maciej W. Rozycki" To: Matt Turner cc: Jean Delvare , linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts In-Reply-To: Message-ID: References: <1313710991-3596-1-git-send-email-mattst88@gmail.com> <20110903103036.161616a5@endymion.delvare> <20111031105354.4b888e44@endymion.delvare> <20120110153834.531664db@endymion.delvare> <20120331082346.26cc95cb@endymion.delvare> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32859 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 639 Lines: 18 On Sat, 31 Mar 2012, Matt Turner wrote: > >> It's hard to prioritize volunteer work for hardware you and two other > >> people have. :) > > > > Matt, Maciej, does any of you have an updated patch ready by now? If I > > don't receive anything by the end of April I'll just drop it. > > I'll do my best to get you an updated patch. > > Thanks for keeping after me. And thanks for looking after the patches -- regrettably I still have no ETA on updating my Linux sources to a version that would let me work on upstream patches, sigh... I'll do my best to review or provide other feedback on these changes if needed though. Maciej From dmitry.adamushko@gmail.com Thu Apr 5 20:37:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Apr 2012 20:38:09 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:63011 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904016Ab2DEShv (ORCPT ); Thu, 5 Apr 2012 20:37:51 +0200 Received: by eaak13 with SMTP id k13so600516eaa.36 for ; Thu, 05 Apr 2012 11:37:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=UYRGSNYuaPrcuTTxZZpdBdLtYo1uIiSqKXvur1rj4g0=; b=fclZzgLCkqYxa0edQ56xLrsD73y1bacG4amLyjEwP0CEVgz3Qj2Vx1Rqz7uKZER9Tt 8U6cADx4oomtVrsRW6y+04f+x0XXFrqd1nYhOxWknof5MCeB7w5bQypQsg3e01AHPaQ4 sZDXXj4TKWYey8obnXYFAkGkpIyIi34B9MLsq0eJ/JRXnG3e8x7k2HeREQvg+E7GSF5L B3FWEUrU7BMt87BTQHEN9ueAuSF1GtS9rOluKoiKCD/r2oBhOUbM4iDZIjN8PtGQenl6 rNxRW4xjloYC5MIDDPR7Hd09BJm5OjUiUpsmcaivPOOVJbYfQt3ELu36R/vl2IcFPAQ/ pgHw== Received: by 10.213.20.19 with SMTP id d19mr500835ebb.37.1333651066333; Thu, 05 Apr 2012 11:37:46 -0700 (PDT) Received: from [192.168.0.100] (d54C476BA.access.telenet.be. [84.196.118.186]) by mx.google.com with ESMTPS id n56sm15803855eeb.4.2012.04.05.11.37.44 (version=SSLv3 cipher=OTHER); Thu, 05 Apr 2012 11:37:45 -0700 (PDT) Subject: [PATCH] mips: fix endless loop when processing signals for kernel tasks From: dimm To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset="UTF-8" Date: Thu, 05 Apr 2012 20:37:34 +0200 Message-ID: <1333651054.3680.11.camel@dimm> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit X-archive-position: 32860 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitry.adamushko@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1967 Lines: 59 From: Dmitry Adamushko The problem occurs [1] when a kernel-mode task returns from a system call with a pending signal. A real-life scenario is a child of 'khelper' returning from a failed kernel_execve() in ____call_usermodehelper() [ kernel/kmod.c ]. kernel_execve() fails due to a pending SIGKILL, which is the result of "kill -9 -1" (at least, busybox's init does it upon reboot). The loop is as follows: * syscall_exit_work: - work_pending: // start_of_the_loop - work_notifysig: - do_notify_resume() - do_signal() - if (!user_mode(regs)) return; - resume_userspace // TIF_SIGPENDING is still set - work_pending // so we call work_pending => goto // start_of_the_loop More information can be found in another LKML thread: http://www.serverphorums.com/read.php?12,457826 [1] The problem was also reproduced on !CONFIG_VM86 x86, and the following fix was accepted. http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=29a2e2836ff9ea65a603c89df217f4198973a74f Signed-off-by: Dmitry Adamushko Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/kernel/entry.S.old 2012-04-05 10:57:12.500976124 +0200 +++ arch/mips/kernel/entry.S 2012-04-05 11:21:24.128174358 +0200 @@ -36,6 +36,11 @@ FEXPORT(ret_from_exception) FEXPORT(ret_from_irq) LONG_S s0, TI_REGS($28) FEXPORT(__ret_from_irq) +/* + * We can be coming here from a syscall done in the kernel space, + * e.g. a failed kernel_execve(). + */ +resume_userspace_check: LONG_L t0, PT_STATUS(sp) # returning to kernel mode? andi t0, t0, KU_USER beqz t0, resume_kernel @@ -162,7 +167,7 @@ work_notifysig: # deal with pending s move a0, sp li a1, 0 jal do_notify_resume # a2 already loaded - j resume_userspace + j resume_userspace_check FEXPORT(syscall_exit_work_partial) SAVE_STATIC From sjhill@mips.com Thu Apr 5 21:00:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Apr 2012 21:01:00 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:33565 "EHLO guruplug.inter.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1904016Ab2DETAq (ORCPT ); Thu, 5 Apr 2012 21:00:46 +0200 Received: from solomon.inter.net ([10.0.0.2]) by guruplug.inter.net with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SFrvB-0002Hn-8R; Thu, 05 Apr 2012 14:00:37 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , sjhill@realitydiluted.com Subject: [PATCH] Update core files for the MALTA platform. Date: Thu, 5 Apr 2012 14:00:24 -0500 Message-Id: <1333652424-9298-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32861 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 60406 Lines: 1979 From: "Steven J. Hill" fad fadsfdassadfdfa Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 34 +- arch/mips/include/asm/cpu.h | 3 +- arch/mips/include/asm/gic.h | 15 +- arch/mips/include/asm/irq.h | 1 + arch/mips/include/asm/mach-generic/dma-coherence.h | 4 +- arch/mips/include/asm/mips-boards/maltaint.h | 10 + arch/mips/include/asm/mips_mt.h | 1 + arch/mips/include/asm/topology.h | 3 + arch/mips/include/asm/vpe.h | 30 +- arch/mips/kernel/cpu-probe.c | 5 + arch/mips/kernel/rtlx.c | 21 +- arch/mips/kernel/smp-mt.c | 39 +- arch/mips/kernel/spram.c | 1 + arch/mips/kernel/syscall.c | 5 +- arch/mips/kernel/vpe.c | 844 ++++++++++++++++++-- arch/mips/mm/c-r4k.c | 49 +- arch/mips/mm/dma-default.c | 8 +- arch/mips/mti-malta/malta-memory.c | 2 +- arch/mips/mti-malta/malta-pci.c | 5 +- arch/mips/mti-malta/malta-setup.c | 113 +++ arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 7 +- 22 files changed, 1048 insertions(+), 153 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index edbbae1..0c7fb5d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1862,14 +1862,14 @@ config MIPS_MT_SMP select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a VSMP but lately has been - marketesed into SMVP. - Virtual SMP uses the processor's VPEs to implement virtual - processors. In currently available configuration of the 34K processor - this allows for a dual processor. Both processors will share the same - primary caches; each will obtain the half of the TLB for it's own - exclusive use. For a layman this model can be described as similar to - what Intel calls Hyperthreading. + Virtual SMP uses the processor's VPEs to implement virtual + processors. In currently available configurations of the 34K + processor this allows for a dual processor. Both processors will + share the same primary caches and each will obtain the half of + the TLB for its own exclusive use. For a layman this model can + be described as similar to what Intel calls Hyperthreading. At + some point MIPS marketing decided to renamed to SMVP but the + renaming hasn't caught on as of yet. For further information see http://www.linux-mips.org/wiki/34K#VSMP @@ -1886,14 +1886,16 @@ config MIPS_MT_SMTC select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a SMTC or lately has been - marketesed into SMVP. - is presenting the available TC's of the core as processors to Linux. - On currently available 34K processors this means a Linux system will - see up to 5 processors. The implementation of the SMTC kernel differs - significantly from VSMP and cannot efficiently coexist in the same - kernel binary so the choice between VSMP and SMTC is a compile time - decision. + SMTC is presenting the available TCs of the core as processors to + Linux. On currently available 34K processors this means a Linux + system will see up to 5 processors. The implementation of the SMTC + kernel differs significantly from VSMP. It was found that SMTC cannot + efficiently coexist in the same kernel binary with other modes of + multiprocessor support, so enabling SMTC is a compile time decision. + The choice between VSMP and SMTC is a bit delicate as it is affected + by clockspeed, memory speed, the specific workload and other factors. + As such the choice should not be made on an evaluation board such as + the Malta but preferably on final target hardware. For further information see http://www.linux-mips.org/wiki/34K#SMTC diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f9fa2a4..ddd8b4a 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -94,6 +94,7 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 +#define PRID_IMP_1074K 0x9a00 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -260,7 +261,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, - CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, + CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_1074K, /* * MIPS64 class processors diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 86548da..991b659 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -206,7 +206,7 @@ #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 #define GIC_VPE_EIC_SS(intr) \ - (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) + (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr)) #define GIC_VPE_EIC_VEC_BASE 0x0800 #define GIC_VPE_EIC_VEC(intr) \ @@ -330,6 +330,17 @@ struct gic_intr_map { #define GIC_FLAG_TRANSPARENT 0x02 }; +/* + * This is only used in EIC mode. This helps to figure out which + * shared interrupts we need to process when we get a vector interrupt. + */ +#define GIC_MAX_SHARED_INTR 0x5 +struct gic_shared_intr_map { + unsigned int num_shared_intr; + unsigned int intr_list[GIC_MAX_SHARED_INTR]; + unsigned int local_intr_mask; +}; + extern void gic_init(unsigned long gic_base_addr, unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, unsigned int intrmap_size, unsigned int irqbase); @@ -338,5 +349,7 @@ extern unsigned int gic_get_int(void); extern void gic_send_ipi(unsigned int intr); extern unsigned int plat_ipi_call_int_xlate(unsigned int); extern unsigned int plat_ipi_resched_int_xlate(unsigned int); +extern void gic_bind_eic_interrupt(int irq, int set); +extern unsigned int gic_get_timer_pending(void); #endif /* _ASM_GICREGS_H */ diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index fb698dc..78dbb8a 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq); * IE7. Since R2 their number has to be read from the c0_intctl register. */ #define CP0_LEGACY_COMPARE_IRQ 7 +#define CP0_LEGACY_PERFCNT_IRQ 7 extern int cp0_compare_irq; extern int cp0_compare_irq_shift; diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177..9f1cd31 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -63,7 +63,9 @@ static inline int plat_device_is_coherent(struct device *dev) return 1; #endif #ifdef CONFIG_DMA_NONCOHERENT - return 0; + extern int coherentio; + + return coherentio; #endif } diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index d11aa02..5447d9f 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -86,6 +86,16 @@ #define GIC_CPU_INT4 4 /* . */ #define GIC_CPU_INT5 5 /* Core Interrupt 5 */ +/* MALTA GIC local interrupts */ +#define GIC_INT_TMR (GIC_CPU_INT5) +#define GIC_INT_PERFCTR (GIC_CPU_INT5) + +/* GIC constants */ +/* Add 2 to convert non-eic hw int # to eic vector # */ +#define GIC_CPU_TO_VEC_OFFSET (2) +/* If we map an intr to pin X, GIC will actually generate vector X+1 */ +#define GIC_PIN_TO_VEC_OFFSET (1) + #define GIC_EXT_INTR(x) x /* External Interrupts used for IPI */ diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h index ac79352..3177c83 100644 --- a/arch/mips/include/asm/mips_mt.h +++ b/arch/mips/include/asm/mips_mt.h @@ -19,6 +19,7 @@ extern unsigned long mt_fpemul_threshold; extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); extern void mips_mt_set_cpuoptions(void); +extern void cmp_send_ipi_single(int cpu, unsigned int action); struct class; extern struct class *mt_class; diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h index 259145e..709e78a 100644 --- a/arch/mips/include/asm/topology.h +++ b/arch/mips/include/asm/topology.h @@ -12,6 +12,9 @@ #ifdef CONFIG_SMP #define smt_capable() (smp_num_siblings > 1) +/* FIXME: cpu_sibling_map is not a per_cpu variable */ +/*#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) */ +#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu]) #endif #endif /* __ASM_TOPOLOGY_H */ diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index c6e1b96..e5e4033 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -26,12 +26,40 @@ struct vpe_notifications { struct list_head list; }; - +extern unsigned long physical_memsize; extern int vpe_notify(int index, struct vpe_notifications *notify); +extern void save_gp_address(unsigned int secbase, unsigned int rel); + +/* + * libc style I/O support hooks + */ extern void *vpe_get_shared(int index); extern int vpe_getuid(int index); extern int vpe_getgid(int index); extern char *vpe_getcwd(int index); +/* + * Kernel/Kernel message passing support hooks + */ + +extern void *vpe_get_shared_area(int index, int type); + +/* "Well-Known" Area Types */ + +#define VPE_SHARED_NULL 0 +#define VPE_SHARED_RESERVED -1 + +struct vpe_shared_area { + int type; + void *addr; +}; + +/* + * IRQ assignment and initialization hook for RP services. + */ + +int arch_get_xcpu_irq(void); + +int vpe_send_interrupt(int v, int i); #endif /* _ASM_VPE_H */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5099201..cb1e2e9 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -207,6 +207,7 @@ void __init check_wait(void) cpu_wait = r4k_wait_irqoff; break; + case CPU_1074K: case CPU_74K: cpu_wait = r4k_wait; if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) @@ -835,6 +836,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; break; + case PRID_IMP_1074K: + c->cputype = CPU_1074K; + __cpu_name[cpu] = "MIPS 1074Kc"; + break; } spram_config(); diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index b8c18dc..25278d0 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -57,12 +57,6 @@ static int sp_stopping; extern void *vpe_get_shared(int index); -static void rtlx_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); -} - - /* Interrupt handler may be called before rtlx_init has otherwise had a chance to run. */ @@ -483,7 +477,7 @@ static char register_chrdev_failed[] __initdata = static int __init rtlx_module_init(void) { struct device *dev; - int i, err; + int i, err, irq; if (!cpu_has_mipsmt) { printk("VPE loader: not a MIPS MT capable processor\n"); @@ -523,18 +517,17 @@ static int __init rtlx_module_init(void) notify.start = starting; notify.stop = stopping; vpe_notify(tclimit, ¬ify); - - if (cpu_has_vint) - set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); - else { + irq = arch_get_xcpu_irq(); + if (irq < 0) { pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); err = -ENODEV; goto out_chrdev; } - rtlx_irq.dev_id = rtlx; - setup_irq(rtlx_irq_num, &rtlx_irq); - + err = request_irq(irq, &rtlx_interrupt, IRQF_SHARED, + module_name, (void *)dev); + if (err) + goto out_chrdev; return 0; out_chrdev: diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ff17868..4f54cea 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -34,7 +34,9 @@ #include #include #include +#include +extern int gic_present; static void __init smvp_copy_vpe_config(void) { write_vpe_c0_status( @@ -111,12 +113,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) write_tc_c0_tchalt(TCHALT_H); } +static void mp_send_ipi_single(int cpu, unsigned int action) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (action) { + case SMP_CALL_FUNCTION: + gic_send_ipi(plat_ipi_call_int_xlate(cpu)); + break; + + case SMP_RESCHEDULE_YOURSELF: + gic_send_ipi(plat_ipi_resched_int_xlate(cpu)); + break; + } + + local_irq_restore(flags); +} + static void vsmp_send_ipi_single(int cpu, unsigned int action) { int i; unsigned long flags; int vpflags; + if (gic_present) { + mp_send_ipi_single(cpu, action); + return; + } local_irq_save(flags); vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ @@ -150,9 +175,8 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) static void __cpuinit vsmp_init_secondary(void) { - extern int gic_present; - - /* This is Malta specific: IPI,performance and timer interrupts */ + pr_debug("SMPMT: CPU%d: vsmp_init_secondary\n", smp_processor_id()); + /* This is Malta specific: IPI,performance and timer inetrrupts */ if (gic_present) change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 | STATUSF_IP7); @@ -163,6 +187,8 @@ static void __cpuinit vsmp_init_secondary(void) static void __cpuinit vsmp_smp_finish(void) { + pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id()); + /* CDFIXME: remove this? */ write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); @@ -177,6 +203,7 @@ static void __cpuinit vsmp_smp_finish(void) static void vsmp_cpus_done(void) { + pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id()); } /* @@ -190,6 +217,8 @@ static void vsmp_cpus_done(void) static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) { struct thread_info *gp = task_thread_info(idle); + pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n", + smp_processor_id(), cpu); dvpe(); set_c0_mvpcontrol(MVPCONTROL_VPC); @@ -231,6 +260,7 @@ static void __init vsmp_smp_setup(void) unsigned int mvpconf0, ntc, tc, ncpu = 0; unsigned int nvpe; + pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id()); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ if (cpu_has_fpu) @@ -260,6 +290,7 @@ static void __init vsmp_smp_setup(void) smvp_tc_init(tc, mvpconf0); ncpu = smvp_vpe_init(tc, mvpconf0, ncpu); } + cpu_present_map = cpu_possible_map; /* Release config state */ clear_c0_mvpcontrol(MVPCONTROL_VPC); @@ -271,6 +302,8 @@ static void __init vsmp_smp_setup(void) static void __init vsmp_prepare_cpus(unsigned int max_cpus) { + pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n", + smp_processor_id(), max_cpus); mips_mt_set_cpuoptions(); } diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 6af08d8..5781dbf 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -205,6 +205,7 @@ void __cpuinit spram_config(void) case CPU_24K: case CPU_34K: case CPU_74K: + case CPU_1074K: case CPU_1004K: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index b08220c..bacd9bf 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -124,7 +124,7 @@ _sys_clone(nabi_no_regargs struct pt_regs regs) child_tidptr = (int __user *) regs.regs[8]; #endif return do_fork(clone_flags, newsp, ®s, 0, - parent_tidptr, child_tidptr); + parent_tidptr, child_tidptr); } /* @@ -264,11 +264,12 @@ save_static_function(sys_sysmips); static int __used noinline _sys_sysmips(nabi_no_regargs struct pt_regs regs) { - long cmd, arg1, arg2; + long cmd, arg1, arg2, arg3; cmd = regs.regs[4]; arg1 = regs.regs[5]; arg2 = regs.regs[6]; + arg3 = regs.regs[7]; switch (cmd) { case MIPS_ATOMIC_SET: diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index f6f9152..e8c99a4 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -73,17 +73,14 @@ static const int minor = 1; /* fixed for now */ static struct kspd_notifications kspd_events; static int kspd_events_reqd; #endif - -/* grab the likely amount of memory we will need. */ -#ifdef CONFIG_MIPS_VPE_LOADER_TOM -#define P_SIZE (2 * 1024 * 1024) -#else -/* add an overhead to the max kmalloc size for non-striped symbols/etc */ +/* + * Size of private kernel buffer for ELF headers and sections + */ #define P_SIZE (256 * 1024) -#endif - -extern unsigned long physical_memsize; +/* + * Size of private kernel buffer for ELF headers and sections + */ #define MAX_VPES 16 #define VPE_PATH_MAX 256 @@ -100,6 +97,16 @@ enum tc_state { TC_STATE_DYNAMIC }; +enum load_state { + LOAD_STATE_EHDR, + LOAD_STATE_PHDR, + LOAD_STATE_SHDR, + LOAD_STATE_PIMAGE, + LOAD_STATE_TRAILER, + LOAD_STATE_DONE, + LOAD_STATE_ERROR +}; + struct vpe { enum vpe_state state; @@ -107,10 +114,25 @@ struct vpe { int minor; /* elfloader stuff */ + unsigned long offset; /* File offset into input stream */ void *load_addr; - unsigned long len; + unsigned long copied; char *pbuffer; - unsigned long plen; + unsigned long pbsize; + /* Program loading state */ + enum load_state l_state; + Elf_Ehdr *l_ehdr; + struct elf_phdr *l_phdr; + unsigned int l_phlen; + Elf_Shdr *l_shdr; + unsigned int l_shlen; + int *l_phsort; /* Sorted index list of program headers */ + int l_segoff; /* Offset into current program segment */ + int l_cur_seg; /* Indirect index of segment currently being loaded */ + unsigned int l_progminad; + unsigned int l_progmaxad; + unsigned int l_trailer; + unsigned int uid, gid; char cwd[VPE_PATH_MAX]; @@ -122,9 +144,12 @@ struct vpe { /* The list of vpe's */ struct list_head list; - /* shared symbol address */ + /* legacy shared symbol address */ void *shared_ptr; + /* shared area descriptor array address */ + struct vpe_shared_area *shared_areas; + /* the list of who wants to know when something major happens */ struct list_head notify; @@ -146,13 +171,24 @@ struct { spinlock_t tc_list_lock; struct list_head tc_list; /* Thread contexts */ } vpecontrol = { - .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), + .vpe_list_lock = SPIN_LOCK_UNLOCKED, .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), - .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), + .tc_list_lock = SPIN_LOCK_UNLOCKED, .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) }; static void release_progmem(void *ptr); +/* + * Values and state associated with publishing shared memory areas + */ + +#define N_PUB_AREAS 4 + +static struct vpe_shared_area published_vpe_area[N_PUB_AREAS] = { + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0} }; /* get the vpe associated with this minor */ static struct vpe *get_vpe(int minor) @@ -175,7 +211,7 @@ static struct vpe *get_vpe(int minor) return res; } -/* get the vpe associated with this minor */ +/* get the tc associated with this minor */ static struct tc *get_tc(int index) { struct tc *res, *t; @@ -200,7 +236,8 @@ static struct vpe *alloc_vpe(int minor) if ((v = kzalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) return NULL; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct vpe), (unsigned int)v); INIT_LIST_HEAD(&v->tc); spin_lock(&vpecontrol.vpe_list_lock); list_add_tail(&v->list, &vpecontrol.vpe_list); @@ -219,7 +256,8 @@ static struct tc *alloc_tc(int index) if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) goto out; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct tc), (unsigned int)tc); INIT_LIST_HEAD(&tc->tc); tc->index = index; @@ -237,6 +275,11 @@ static void release_vpe(struct vpe *v) list_del(&v->list); if (v->load_addr) release_progmem(v); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v->l_phsort); + kfree(v->l_phsort); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v); kfree(v); } @@ -260,8 +303,88 @@ static void __maybe_unused dump_mtregs(void) val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); } +/* + * The original APRP prototype assumed a single, unshared IRQ for + * cross-VPE interrupts, used by the RTLX code. But M3P networking + * and other future functions may need to share an IRQ, particularly + * in 34K/Malta configurations without an external interrupt controller. + * All cross-VPE insterrupt users need to coordinate through shared + * functions here. + */ + +/* + * It would be nice if I could just have this initialized to zero, + * but the patchcheck police won't hear of it... + */ + +static int xvpe_vector_set; + +#define XVPE_INTR_OFFSET 0 + +static int xvpe_irq = MIPS_CPU_IRQ_BASE + XVPE_INTR_OFFSET; + +static void xvpe_dispatch(void) +{ + do_IRQ(xvpe_irq); +} + +/* Name here is generic, as m3pnet.c could in principle be used by non-MIPS */ +int arch_get_xcpu_irq() +{ + /* + * Some of this will ultimately become platform code, + * but for now, we're only targeting 34K/FPGA/Malta, + * and there's only one generic mechanism. + */ + if (!xvpe_vector_set) { + /* + * A more elaborate shared variable shouldn't be needed. + * Two initializations back-to-back should be harmless. + */ + if (cpu_has_vint) { + set_vi_handler(XVPE_INTR_OFFSET, xvpe_dispatch); + xvpe_vector_set = 1; + } else { + printk(KERN_ERR "APRP requires vectored interrupts\n"); + return -1; + } + } + + return xvpe_irq; +} +EXPORT_SYMBOL(arch_get_xcpu_irq); + +int vpe_send_interrupt(int vpe, int inter) +{ + unsigned long flags; + unsigned int vpeflags; + + local_irq_save(flags); + vpeflags = dvpe(); + + /* + * Initial version makes same simple-minded assumption + * as is implicit elsewhere in this module, that the + * only RP of interest is using the first non-Linux TC. + * We ignore the parameters provided by the caller! + */ + settc(tclimit); + /* + * In 34K/Malta, the only cross-VPE interrupts possible + * are done by setting SWINT bits in Cause, of which there + * are two. SMTC uses SW1 for a multiplexed class of IPIs, + * and this mechanism should be generalized to APRP and use + * the same protocol. Until that's implemented, send only + * SW0 here, regardless of requested type. + */ + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); + evpe(vpeflags); + local_irq_restore(flags); + return 1; +} +EXPORT_SYMBOL(vpe_send_interrupt); /* Find some VPE program space */ -static void *alloc_progmem(unsigned long len) +static void *alloc_progmem(void *requested, unsigned long len) { void *addr; @@ -271,10 +394,28 @@ static void *alloc_progmem(unsigned long len) * physically have, for example by passing a mem= boot argument. */ addr = pfn_to_kaddr(max_low_pfn); - memset(addr, 0, len); + if (requested != 0) { + if (requested >= addr) + addr = requested; + else + addr = 0; + } + if (addr != 0) + memset(addr, 0, len); + printk(KERN_DEBUG "pfn_to_kaddr returns %lu bytes of memory at %x\n", + len, (unsigned int)addr); #else - /* simple grab some mem for now */ - addr = kzalloc(len, GFP_KERNEL); + if (requested != 0) { + /* If we have a target in mind, grab a 2x slice and hope... */ + addr = kzalloc(len*2, GFP_KERNEL); + if ((requested >= addr) && (requested < (addr + len))) + addr = requested; + else + addr = 0; + } else { + /* simply grab some mem for now */ + addr = kzalloc(len, GFP_KERNEL); + } #endif return addr; @@ -446,6 +587,8 @@ static int apply_r_mips_hi16(struct module *me, uint32_t *location, * actual relocation. */ n = kmalloc(sizeof *n, GFP_KERNEL); + printk(KERN_DEBUG "Used kmalloc to allocate %d bytes at %x\n", + sizeof(struct mips_hi16), (unsigned int)n); if (!n) return -ENOMEM; @@ -503,6 +646,8 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, *l->addr = insn; next = l->next; + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)l); kfree(l); l = next; } @@ -596,7 +741,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs, return 0; } -static inline void save_gp_address(unsigned int secbase, unsigned int rel) +void save_gp_address(unsigned int secbase, unsigned int rel) { gp_addr = secbase + rel; gp_offs = gp_addr - (secbase & 0xffff0000); @@ -816,16 +961,41 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, struct module *mod) { Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; - unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); + unsigned int i, j, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); for (i = 1; i < n; i++) { - if (strcmp(strtab + sym[i].st_name, "__start") == 0) { - v->__start = sym[i].st_value; + if (strcmp(strtab + sym[i].st_name, "__start") == 0) + v->__start = sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) + v->shared_ptr = (void *)sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "_vpe_shared_areas") == 0) { + struct vpe_shared_area *psa + = (struct vpe_shared_area *)sym[i].st_value; + struct vpe_shared_area *tpsa; + v->shared_areas = psa; + printk(KERN_INFO"_vpe_shared_areas found, 0x%x\n", + (unsigned int)v->shared_areas); + /* + * Copy any "published" areas to the descriptor + */ + for (j = 0; j < N_PUB_AREAS; j++) { + if (published_vpe_area[j].type != VPE_SHARED_RESERVED) { + tpsa = psa; + while (tpsa->type != VPE_SHARED_NULL) { + if ((tpsa->type == VPE_SHARED_RESERVED) + || (tpsa->type == published_vpe_area[j].type)) { + tpsa->type = published_vpe_area[j].type; + tpsa->addr = published_vpe_area[j].addr; + break; + } + tpsa++; + } + } } + } - if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) { - v->shared_ptr = (void *)sym[i].st_value; - } } if ( (v->__start == 0) || (v->shared_ptr == NULL)) @@ -850,14 +1020,12 @@ static int vpe_elfload(struct vpe * v) memset(&mod, 0, sizeof(struct module)); strcpy(mod.name, "VPE loader"); - - hdr = (Elf_Ehdr *) v->pbuffer; - len = v->plen; + hdr = v->l_ehdr; + len = v->pbsize; /* Sanity checks against insmoding binaries or wrong arch, weird elf version */ - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0 - || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) + if ((hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) || !elf_check_arch(hdr) || hdr->e_shentsize != sizeof(*sechdrs)) { printk(KERN_WARNING @@ -869,9 +1037,8 @@ static int vpe_elfload(struct vpe * v) if (hdr->e_type == ET_REL) relocate = 1; - if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { - printk(KERN_ERR "VPE loader: program length %u truncated\n", - len); + if (len < v->l_phlen + v->l_shlen) { + printk(KERN_ERR "VPE loader: Headers exceed %u bytes\n", len); return -ENOEXEC; } @@ -905,9 +1072,13 @@ static int vpe_elfload(struct vpe * v) } } layout_sections(&mod, hdr, sechdrs, secstrings); + /* + * Non-relocatable loads should have already done their + * allocates, based on program header table. + */ } - v->load_addr = alloc_progmem(mod.core_size); + memset(v->load_addr, 0, mod.core_size); if (!v->load_addr) return -ENOMEM; @@ -960,19 +1131,10 @@ static int vpe_elfload(struct vpe * v) } } else { - struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); - - for (i = 0; i < hdr->e_phnum; i++) { - if (phdr->p_type == PT_LOAD) { - memcpy((void *)phdr->p_paddr, - (char *)hdr + phdr->p_offset, - phdr->p_filesz); - memset((void *)phdr->p_paddr + phdr->p_filesz, - 0, phdr->p_memsz - phdr->p_filesz); - } - phdr++; - } + /* + * Program image is already in memory. + */ for (i = 0; i < hdr->e_shnum; i++) { /* Internal symbols and strings. */ if (sechdrs[i].sh_type == SHT_SYMTAB) { @@ -989,7 +1151,7 @@ static int vpe_elfload(struct vpe * v) /* make sure it's physically written out */ flush_icache_range((unsigned long)v->load_addr, - (unsigned long)v->load_addr + v->len); + (unsigned long)v->load_addr + v->copied); if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { if (v->__start == 0) { @@ -1003,8 +1165,8 @@ static int vpe_elfload(struct vpe * v) "program does not contain vpe_shared symbol.\n" " Unable to use AMVP (AP/SP) facilities.\n"); } + pr_info("APRP VPE loader: elf loaded\n"); - printk(" elf loaded\n"); return 0; } @@ -1069,6 +1231,10 @@ static int vpe_open(struct inode *inode, struct file *filp) return -ENODEV; } + /* + * This treats the tclimit command line configuration input + * as a minor device indication, which is probably unwholesome. + */ if ((v = get_vpe(tclimit)) == NULL) { pr_warning("VPE loader: unable to get vpe\n"); @@ -1085,18 +1251,20 @@ static int vpe_open(struct inode *inode, struct file *filp) } release_progmem(v->load_addr); + kfree(v->l_phsort); cleanup_tc(get_tc(tclimit)); } /* this of-course trashes what was there before... */ v->pbuffer = vmalloc(P_SIZE); - if (!v->pbuffer) { - pr_warning("VPE loader: unable to allocate memory\n"); - return -ENOMEM; - } - v->plen = P_SIZE; v->load_addr = NULL; - v->len = 0; + v->copied = 0; + v->offset = 0; + v->l_state = LOAD_STATE_EHDR; + v->l_ehdr = NULL; + v->l_phdr = NULL; + v->l_phsort = NULL; + v->l_shdr = NULL; v->uid = filp->f_cred->fsuid; v->gid = filp->f_cred->fsgid; @@ -1115,6 +1283,7 @@ static int vpe_open(struct inode *inode, struct file *filp) printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret); v->shared_ptr = NULL; + v->shared_areas = NULL; v->__start = 0; return 0; @@ -1123,26 +1292,39 @@ static int vpe_open(struct inode *inode, struct file *filp) static int vpe_release(struct inode *inode, struct file *filp) { struct vpe *v; - Elf_Ehdr *hdr; int ret = 0; v = get_vpe(tclimit); if (v == NULL) return -ENODEV; + /* + * If image load had no errors, massage program/section tables + * to reflect movement of program/section data into VPE program + * memory. + */ + if (v->l_state != LOAD_STATE_DONE) { + printk(KERN_WARNING "VPE Release after incomplete load\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); + return -ENOEXEC; + } - hdr = (Elf_Ehdr *) v->pbuffer; - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) { - if (vpe_elfload(v) >= 0) { - vpe_run(v); - } else { - printk(KERN_WARNING "VPE loader: ELF load failed.\n"); - ret = -ENOEXEC; - } + if (vpe_elfload(v) >= 0) { + vpe_run(v); } else { - printk(KERN_WARNING "VPE loader: only elf files are supported\n"); + printk(KERN_WARNING "VPE loader: ELF load failed.\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); ret = -ENOEXEC; } + /* It's good to be able to run the SP and if it chokes have a look at the /dev/rt?. But if we reset the pointer to the shared struct we lose what has happened. So perhaps if garbage is sent to the vpe @@ -1151,17 +1333,68 @@ static int vpe_release(struct inode *inode, struct file *filp) if (ret < 0) v->shared_ptr = NULL; - vfree(v->pbuffer); - v->plen = 0; - + // cleanup any temp buffers + if (v->pbuffer) { + printk(KERN_DEBUG "Used vfree to free memory at %x\n", + (unsigned int)v->pbuffer); + vfree(v->pbuffer); + } + v->pbsize = 0; return ret; } +/* + * A sort of insertion sort to generate list of program header indices + * in order of their file offsets. + */ + +static void indexort(struct elf_phdr *phdr, int nph, int *index) +{ + int i, j, t; + unsigned int toff; + + /* Create initial mapping */ + for (i = 0; i < nph; i++) + index[i] = i; + /* Do the indexed insert sort */ + for (i = 1; i < nph; i++) { + j = i; + t = index[j]; + toff = phdr[t].p_offset; + while ((j > 0) && (phdr[index[j-1]].p_offset > toff)) { + index[j] = index[j-1]; + j--; + } + index[j] = t; + } +} + + +/* + * This function has to convert the ELF file image being sequentially + * streamed to the pseudo-device into the binary image, symbol, and + * string information, which the ELF format allows to be in some degree + * of disorder. + * + * The ELF header and, if present, program header table, are copied into + * a temporary buffer. Loadable program segments, if present, are copied + * into the RP program memory at the addresses specified by the program + * header table. + * + * Sections not specified by the program header table are loaded into + * memory following the program segments if they are "allocated", or + * into the temporary buffer if they are not. The section header + * table is loaded into the temporary buffer.??? + */ +#define CURPHDR (v->l_phdr[v->l_phsort[v->l_cur_seg]]) static ssize_t vpe_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos) { size_t ret = count; struct vpe *v; + int tocopy, uncopied; + int i; + unsigned int progmemlen; if (iminor(file->f_path.dentry->d_inode) != minor) return -ENODEV; @@ -1170,17 +1403,357 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, if (v == NULL) return -ENODEV; - if ((count + v->len) > v->plen) { - printk(KERN_WARNING - "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + if (v->pbuffer == NULL) { + printk(KERN_ERR "VPE loader: no buffer for program\n"); return -ENOMEM; } - count -= copy_from_user(v->pbuffer + v->len, buffer, count); - if (!count) - return -EFAULT; + while (count) { + switch (v->l_state) { + case LOAD_STATE_EHDR: + /* Loading ELF Header into scratch buffer */ + tocopy = min((unsigned long)count, + sizeof(Elf_Ehdr) - v->offset); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->copied == sizeof(Elf_Ehdr)) { + v->l_ehdr = (Elf_Ehdr *)v->pbuffer; + if (memcmp(v->l_ehdr->e_ident, ELFMAG, 4) != 0) { + printk(KERN_WARNING "VPE loader: %s\n", + "non-ELF file image"); + ret = -ENOEXEC; + v->l_state = LOAD_STATE_ERROR; + break; + } + if (v->l_ehdr->e_phoff != 0) { + v->l_phdr = (struct elf_phdr *) + (v->pbuffer + v->l_ehdr->e_phoff); + v->l_phlen = v->l_ehdr->e_phentsize + * v->l_ehdr->e_phnum; + /* Check against buffer overflow */ + if ((v->copied + v->l_phlen) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf program header table size too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_PHDR; + /* + * Program headers generally indicate + * linked executable with possibly + * valid entry point. + */ + v->__start = v->l_ehdr->e_entry; + } else if (v->l_ehdr->e_shoff != 0) { + /* + * No program headers, but a section + * header table. A relocatable binary. + * We need to load the works into the + * kernel temp buffer to compute the + * RP program image. That limits our + * binary size, but at least we're no + * worse off than the original APRP + * prototype. + */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big.\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + } else { + /* + * If neither program nor section tables, + * we don't know what to do. + */ + v->l_state = LOAD_STATE_ERROR; + return -ENOEXEC; + } + } + break; + case LOAD_STATE_PHDR: + /* Loading Program Headers into scratch */ + tocopy = min((unsigned long)count, + v->l_ehdr->e_phoff + v->l_phlen - v->copied); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + + if (v->copied == v->l_ehdr->e_phoff + v->l_phlen) { + /* + * It's legal for the program headers to be + * out of order with respect to the file layout. + * Generate a list of indices, sorted by file + * offset. + */ + v->l_phsort = kmalloc(v->l_ehdr->e_phnum + * sizeof(int), GFP_KERNEL); + printk(KERN_DEBUG + "Used kmalloc to allocate %d bytes of memory at %x\n", + v->l_ehdr->e_phnum*sizeof(int), + (unsigned int)v->l_phsort); + if (!v->l_phsort) + return -ENOMEM; /* Preposterous, but... */ + indexort(v->l_phdr, v->l_ehdr->e_phnum, + v->l_phsort); + + v->l_progminad = (unsigned int)-1; + v->l_progmaxad = 0; + progmemlen = 0; + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + /* Unstripped .reginfo sections are bad */ + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "User-mode p_vaddr, ", + "skipping program segment,"); + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "strip .reginfo from binary ", + "if necessary."); + continue; + } + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < v->l_progminad) + v->l_progminad = + v->l_phdr[v->l_phsort[i]].p_vaddr; + if ((v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz) + > v->l_progmaxad) + v->l_progmaxad = + v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz; + } + } + printk(KERN_INFO "APRP RP program 0x%x to 0x%x\n", + v->l_progminad, v->l_progmaxad); + /* + * Do a simple sanity check of the memory being + * allocated. Abort if greater than an arbitrary + * value of 32MB + */ + if (v->l_progmaxad - v->l_progminad > + 32*1024*1024) { + printk(KERN_WARNING + "RP program failed to allocate %d kbytes - limit is 32,768 KB\n", + (v->l_progmaxad - v->l_progminad)/1024); + return -ENOMEM; + } + + v->load_addr = alloc_progmem((void *)v->l_progminad, + v->l_progmaxad - v->l_progminad); + if (!v->load_addr) + return -ENOMEM; + if ((unsigned int)v->load_addr + > v->l_progminad) { + release_progmem(v->load_addr); + return -ENOMEM; + } + /* Find first segment with loadable content */ + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + if (i == v->l_ehdr->e_phnum) { + /* No loadable program segment? Bogus file. */ + printk(KERN_WARNING "Bad ELF file for APRP\n"); + return -ENOEXEC; + } + v->l_segoff = 0; + v->l_state = LOAD_STATE_PIMAGE; + } + break; + case LOAD_STATE_PIMAGE: + /* + * Skip through input stream until + * first program segment. Would be + * better to have loaded up to here + * into the temp buffer, but for now + * we simply rule out "interesting" + * sections prior to the last program + * segment in an executable file. + */ + if (v->offset < CURPHDR.p_offset) { + uncopied = CURPHDR.p_offset - v->offset; + if (uncopied > count) + uncopied = count; + count -= uncopied; + buffer += uncopied; + v->offset += uncopied; + /* Go back through the "while" */ + break; + } + /* + * Having dispensed with any unlikely fluff, + * copy from user I/O buffer to program segment. + */ + tocopy = min(count, CURPHDR.p_filesz - v->l_segoff); + + /* Loading image into RP memory */ + uncopied = copy_from_user((char *)CURPHDR.p_vaddr + + v->l_segoff, buffer, tocopy); + count -= tocopy - uncopied; + v->offset += tocopy - uncopied; + v->l_segoff += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->l_segoff >= CURPHDR.p_filesz) { + /* Finished current segment load */ + /* Zero out non-file-sourced image */ + uncopied = CURPHDR.p_memsz - CURPHDR.p_filesz; + if (uncopied > 0) + memset((char *)CURPHDR.p_vaddr + v->l_segoff, + 0, uncopied); + /* Advance to next segment */ + for (i = v->l_cur_seg + 1; + i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + /* If none left, prepare to load section headers */ + if (i == v->l_ehdr->e_phnum) { + if (v->l_ehdr->e_shoff != 0) { + /* Copy to where we left off in temp buffer */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + break; + } + } else { + /* reset offset for new program segment */ + v->l_segoff = 0; + } + } + break; + case LOAD_STATE_SHDR: + /* + * Read stream into private buffer up + * through and including the section header + * table. + */ - v->len += count; + tocopy = min((unsigned long)count, + v->l_ehdr->e_shoff + v->l_shlen - v->offset); + if (tocopy) { + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + /* Finished? */ + if (v->offset == v->l_ehdr->e_shoff + v->l_shlen) { + unsigned int offset_delta = v->offset - v->copied; + + v->l_shdr = (Elf_Shdr *)(v->pbuffer + + v->l_ehdr->e_shoff - offset_delta); + /* + * Check for sections after the section table, + * which for gcc MIPS binaries includes + * the symbol table. Do any other processing + * that requires value within stream, and + * normalize offsets to be relative to + * the header-only layout of temp buffer. + */ + + /* Assume no trailer until we detect one */ + v->l_trailer = 0; + v->l_state = LOAD_STATE_DONE; + for (i = 0; i < v->l_ehdr->e_shnum; i++) { + if (v->l_shdr[i].sh_offset + > v->l_ehdr->e_shoff) { + v->l_state = LOAD_STATE_TRAILER; + /* Track trailing data length */ + if (v->l_trailer + < (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen)) + v->l_trailer = + (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen); + } + /* Adjust section offset if necessary */ + v->l_shdr[i].sh_offset -= offset_delta; + } + if ((v->copied + v->l_trailer) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + + /* Fix up offsets in ELF header */ + v->l_ehdr->e_shoff = (unsigned int)v->l_shdr + - (unsigned int)v->pbuffer; + } + break; + case LOAD_STATE_TRAILER: + /* + * Symbol and string tables follow section headers + * in gcc binaries for MIPS. Copy into temp buffer. + */ + if (v->l_trailer) { + tocopy = min(count, v->l_trailer); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->l_trailer -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + if (!v->l_trailer) + v->l_state = LOAD_STATE_DONE; + break; + case LOAD_STATE_DONE: + if (count) + count = 0; + break; + case LOAD_STATE_ERROR: + default: + return -EINVAL; + } + } return ret; } @@ -1216,7 +1789,9 @@ int vpe_start(vpe_handle vpe, unsigned long start) { struct vpe *v = vpe; - v->__start = start; + /* Null start address means use value from ELF file */ + if (start) + v->__start = start; return vpe_run(v); } @@ -1341,6 +1916,99 @@ char *vpe_getcwd(int index) EXPORT_SYMBOL(vpe_getcwd); +/* + * RP applications may contain a _vpe_shared_area descriptor + * array to allow for data sharing with Linux kernel functions + * that's slightly more abstracted and extensible than the + * fixed binding used by the rtlx support. Indeed, the rtlx + * support should ideally be converted to use the generic + * shared area descriptor scheme at some point. + * + * mips_get_vpe_shared_area() can be used by AP kernel + * modules to get an area pointer of a given type, if + * it exists. + * + * mips_publish_vpe_area() is used by AP kernel modules + * to share kseg0 kernel memory with the RP. It maintains + * a private table, so that publishing can be done before + * the RP program is launched. Making this table dynamically + * allocated and extensible would be good scalable OS design. + * however, until there's more than one user of the mechanism, + * it should be an acceptable simplification to allow a static + * maximum of 4 published areas. + */ + +void *mips_get_vpe_shared_area(int index, int type) +{ + struct vpe *v; + struct vpe_shared_area *vsa; + + v = get_vpe(index); + if (v == NULL) + return NULL; + + if (v->shared_areas == NULL) + return NULL; + + vsa = v->shared_areas; + + while (vsa->type != VPE_SHARED_NULL) { + if (vsa->type == type) + return vsa->addr; + else + vsa++; + } + /* Fell through without finding type */ + + return NULL; +} +EXPORT_SYMBOL(mips_get_vpe_shared_area); + +int mips_publish_vpe_area(int type, void *ptr) +{ + int i; + int retval = 0; + struct vpe *v; + unsigned long flags; + unsigned int vpflags; + + printk(KERN_INFO "mips_publish_vpe_area(0x%x, 0x%x)\n", type, (int)ptr); + if ((unsigned int)ptr >= KSEG2) { + printk(KERN_ERR "VPE area pubish of invalid address 0x%x\n", + (int)ptr); + return 0; + } + for (i = 0; i < N_PUB_AREAS; i++) { + if (published_vpe_area[i].type == VPE_SHARED_RESERVED) { + published_vpe_area[i].type = type; + published_vpe_area[i].addr = ptr; + retval = type; + break; + } + } + /* + * If we've already got a VPE up and running, try to + * update the shared descriptor with the new data. + */ + list_for_each_entry(v, &vpecontrol.vpe_list, list) { + if (v->shared_areas != NULL) { + local_irq_save(flags); + vpflags = dvpe(); + for (i = 0; v->shared_areas[i].type != VPE_SHARED_NULL; i++) { + if ((v->shared_areas[i].type == type) + || (v->shared_areas[i].type == VPE_SHARED_RESERVED)) { + v->shared_areas[i].type = type; + v->shared_areas[i].addr = ptr; + } + } + evpe(vpflags); + local_irq_restore(flags); + } + } + return retval; +} +EXPORT_SYMBOL(mips_publish_vpe_area); + #ifdef CONFIG_MIPS_APSP_KSPD static void kspd_sp_exit( int sp_id) { @@ -1359,6 +2027,7 @@ static ssize_t store_kill(struct device *dev, struct device_attribute *attr, } release_progmem(vpe->load_addr); + kfree(vpe->l_phsort); cleanup_tc(get_tc(tclimit)); vpe_stop(vpe); vpe_free(vpe); @@ -1404,6 +2073,8 @@ static struct device_attribute vpe_class_attributes[] = { static void vpe_device_release(struct device *cd) { + printk(KERN_DEBUG "Using kfree to free vpe class device at %x\n", + (unsigned int)cd); kfree(cd); } @@ -1430,19 +2101,24 @@ static int __init vpe_module_init(void) } if (vpelimit == 0) { - printk(KERN_WARNING "No VPEs reserved for AP/SP, not " - "initializing VPE loader.\nPass maxvpes= argument as " - "kernel argument\n"); - +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) + printk(KERN_WARNING "No VPEs reserved for VPE loader.\n" + "Pass maxvpes= argument as kernel argument\n"); return -ENODEV; +#else + vpelimit = 1; +#endif } if (tclimit == 0) { +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) printk(KERN_WARNING "No TCs reserved for AP/SP, not " "initializing VPE loader.\nPass maxtcs= argument as " "kernel argument\n"); - return -ENODEV; +#else + tclimit = 1; +#endif } major = register_chrdev(0, module_name, &vpe_fops); @@ -1456,7 +2132,7 @@ static int __init vpe_module_init(void) printk(KERN_ERR "vpe_class registration failed\n"); goto out_chrdev; } - + xvpe_vector_set = 0; device_initialize(&vpe_device); vpe_device.class = &vpe_class, vpe_device.parent = NULL, diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index bda8eb2..efcf385 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) c->icache.linesz = 2 << lsize; else c->icache.linesz = lsize; - c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); c->icache.ways = 1 + ((config1 >> 16) & 7); icache_size = c->icache.sets * @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) c->dcache.linesz = 2 << lsize; else c->dcache.linesz= lsize; - c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); c->dcache.ways = 1 + ((config1 >> 7) & 7); dcache_size = c->dcache.sets * @@ -1051,9 +1051,30 @@ static void __cpuinit probe_pcache(void) case CPU_R14000: break; + case CPU_74K: + /* + * Early versions of the 74k do not update + * the cache tags on a vtag miss/ptag hit + * which can occur in the case of KSEG0/KUSEG aliases + * In this case it is better to treat the cache as always + * having aliases + */ + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) + c->dcache.flags |= MIPS_CACHE_VTAG; + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + goto bypass1074; + + case CPU_1074K: + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) { + c->dcache.flags |= MIPS_CACHE_VTAG; + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + } + /* fall through */ +bypass1074: + ; case CPU_24K: case CPU_34K: - case CPU_74K: case CPU_1004K: if ((read_c0_config7() & (1 << 16))) { /* effectively physically indexed dcache, @@ -1061,6 +1082,7 @@ static void __cpuinit probe_pcache(void) c->dcache.flags |= MIPS_CACHE_PINDEX; break; } + /* fall through */ default: if (c->dcache.waysize > PAGE_SIZE) c->dcache.flags |= MIPS_CACHE_ALIASES; @@ -1371,26 +1393,13 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; - -static int __init setcoherentio(char *str) -{ - coherentio = 1; - - return 1; -} - -__setup("coherentio", setcoherentio); -#endif - void __cpuinit r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); extern char __weak except_vec2_generic; extern char __weak except_vec2_sb1; + extern int coherentio; struct cpuinfo_mips *c = ¤t_cpu_data; switch (c->cputype) { @@ -1461,8 +1470,10 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* We want to run CMP kernels on core(s) with and without coherent caches */ + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 4608491..669995a 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -100,6 +100,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); static void *mips_dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t * dma_handle, gfp_t gfp) { + extern int hw_coherentio; void *ret; if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) @@ -115,7 +116,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, if (!plat_device_is_coherent(dev)) { dma_cache_wback_inv((unsigned long) ret, size); - ret = UNCAC_ADDR(ret); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } } @@ -134,6 +136,7 @@ EXPORT_SYMBOL(dma_free_noncoherent); static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { + extern int hw_coherentio; unsigned long addr = (unsigned long) vaddr; int order = get_order(size); @@ -143,7 +146,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) - addr = CAC_ADDR(addr); + if (!hw_coherentio) + addr = CAC_ADDR(addr); free_pages(addr, get_order(size)); } diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index a96d281..d57a233 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -158,7 +158,7 @@ void __init prom_meminit(void) size = p->size; add_memory_region(base, size, type); - p++; + p++; } } diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index bf80921..afeb619 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -241,8 +241,9 @@ void __init mips_pcibios_init(void) return; } - if (controller->io_resource->start < 0x00001000UL) /* FIXME */ - controller->io_resource->start = 0x00001000UL; + /* Change start address to avoid conflicts with ACPI and SMB devices */ + if (controller->io_resource->start < 0x00002000UL) /* FIXME */ + controller->io_resource->start = 0x00002000UL; iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index b7f37d4..618f503 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -32,6 +32,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -105,6 +106,105 @@ static void __init fd_activate(void) } #endif +int coherentio = -1; /* no DMA cache coherency (may be set by user) */ +int hw_coherentio; /* init to 0 => no HW DMA cache coherency (reflects real HW) */ +static int __init setcoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); + return 1; +} +__setup("coherentio", setcoherentio); + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 1; +} +__setup("nocoherentio", setnocoherentio); + +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(prom_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + hw_coherentio = supported; + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -207,6 +307,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif @@ -222,3 +324,14 @@ void __init plat_mem_setup(void) board_be_init = malta_be_init; board_be_handler = malta_be_handler; } +/* Enable PCI 2.1 compatibility in PIIX4 */ +static void __init quirk_dlcsetup(struct pci_dev *dev) +{ + u8 odlc, ndlc; + (void) pci_read_config_byte(dev, 0x82, &odlc); + /* Enable passive releases and delayed transaction */ + ndlc = odlc | 7; + (void) pci_write_config_byte(dev, 0x82, ndlc); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + quirk_dlcsetup); diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index d1f2d4c..846faf7 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -83,6 +83,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_25KF: case CPU_34K: case CPU_1004K: + case CPU_1074K: case CPU_74K: case CPU_SB1: case CPU_SB1A: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..13487a9 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -330,16 +330,11 @@ static int __init mipsxx_init(void) break; case CPU_1004K: -#if 0 - /* FIXME: report as 34K for now */ - op_model_mipsxx_ops.cpu_type = "mips/1004K"; - break; -#endif - case CPU_34K: op_model_mipsxx_ops.cpu_type = "mips/34K"; break; + case CPU_1074K: case CPU_74K: op_model_mipsxx_ops.cpu_type = "mips/74K"; break; -- 1.7.9.6 From sjhill@mips.com Thu Apr 5 22:26:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Apr 2012 22:27:03 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:33662 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904025Ab2DEU0y (ORCPT ); Thu, 5 Apr 2012 22:26:54 +0200 Received: from solomon.inter.net ([10.0.0.2]) by guruplug.inter.net with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SFtGX-0002eA-80; Thu, 05 Apr 2012 15:26:45 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , sjhill@realitydiluted.com Subject: [PATCH v2] Update core files for the MALTA platform. Date: Thu, 5 Apr 2012 15:26:37 -0500 Message-Id: <1333657597-10355-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32862 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 60501 Lines: 1979 From: "Steven J. Hill" Add newer 1074K core support which also includes needed updates to the SMVP and SMTC core code and GIC controller. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 34 +- arch/mips/include/asm/cpu.h | 3 +- arch/mips/include/asm/gic.h | 15 +- arch/mips/include/asm/irq.h | 1 + arch/mips/include/asm/mach-generic/dma-coherence.h | 4 +- arch/mips/include/asm/mips-boards/maltaint.h | 10 + arch/mips/include/asm/mips_mt.h | 1 + arch/mips/include/asm/topology.h | 3 + arch/mips/include/asm/vpe.h | 30 +- arch/mips/kernel/cpu-probe.c | 5 + arch/mips/kernel/rtlx.c | 21 +- arch/mips/kernel/smp-mt.c | 39 +- arch/mips/kernel/spram.c | 1 + arch/mips/kernel/syscall.c | 5 +- arch/mips/kernel/vpe.c | 844 ++++++++++++++++++-- arch/mips/mm/c-r4k.c | 49 +- arch/mips/mm/dma-default.c | 8 +- arch/mips/mti-malta/malta-memory.c | 2 +- arch/mips/mti-malta/malta-pci.c | 5 +- arch/mips/mti-malta/malta-setup.c | 113 +++ arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 7 +- 22 files changed, 1048 insertions(+), 153 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index edbbae1..0c7fb5d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1862,14 +1862,14 @@ config MIPS_MT_SMP select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a VSMP but lately has been - marketesed into SMVP. - Virtual SMP uses the processor's VPEs to implement virtual - processors. In currently available configuration of the 34K processor - this allows for a dual processor. Both processors will share the same - primary caches; each will obtain the half of the TLB for it's own - exclusive use. For a layman this model can be described as similar to - what Intel calls Hyperthreading. + Virtual SMP uses the processor's VPEs to implement virtual + processors. In currently available configurations of the 34K + processor this allows for a dual processor. Both processors will + share the same primary caches and each will obtain the half of + the TLB for its own exclusive use. For a layman this model can + be described as similar to what Intel calls Hyperthreading. At + some point MIPS marketing decided to renamed to SMVP but the + renaming hasn't caught on as of yet. For further information see http://www.linux-mips.org/wiki/34K#VSMP @@ -1886,14 +1886,16 @@ config MIPS_MT_SMTC select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a SMTC or lately has been - marketesed into SMVP. - is presenting the available TC's of the core as processors to Linux. - On currently available 34K processors this means a Linux system will - see up to 5 processors. The implementation of the SMTC kernel differs - significantly from VSMP and cannot efficiently coexist in the same - kernel binary so the choice between VSMP and SMTC is a compile time - decision. + SMTC is presenting the available TCs of the core as processors to + Linux. On currently available 34K processors this means a Linux + system will see up to 5 processors. The implementation of the SMTC + kernel differs significantly from VSMP. It was found that SMTC cannot + efficiently coexist in the same kernel binary with other modes of + multiprocessor support, so enabling SMTC is a compile time decision. + The choice between VSMP and SMTC is a bit delicate as it is affected + by clockspeed, memory speed, the specific workload and other factors. + As such the choice should not be made on an evaluation board such as + the Malta but preferably on final target hardware. For further information see http://www.linux-mips.org/wiki/34K#SMTC diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f9fa2a4..ddd8b4a 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -94,6 +94,7 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 +#define PRID_IMP_1074K 0x9a00 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -260,7 +261,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, - CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, + CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_1074K, /* * MIPS64 class processors diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 86548da..991b659 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -206,7 +206,7 @@ #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 #define GIC_VPE_EIC_SS(intr) \ - (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) + (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr)) #define GIC_VPE_EIC_VEC_BASE 0x0800 #define GIC_VPE_EIC_VEC(intr) \ @@ -330,6 +330,17 @@ struct gic_intr_map { #define GIC_FLAG_TRANSPARENT 0x02 }; +/* + * This is only used in EIC mode. This helps to figure out which + * shared interrupts we need to process when we get a vector interrupt. + */ +#define GIC_MAX_SHARED_INTR 0x5 +struct gic_shared_intr_map { + unsigned int num_shared_intr; + unsigned int intr_list[GIC_MAX_SHARED_INTR]; + unsigned int local_intr_mask; +}; + extern void gic_init(unsigned long gic_base_addr, unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, unsigned int intrmap_size, unsigned int irqbase); @@ -338,5 +349,7 @@ extern unsigned int gic_get_int(void); extern void gic_send_ipi(unsigned int intr); extern unsigned int plat_ipi_call_int_xlate(unsigned int); extern unsigned int plat_ipi_resched_int_xlate(unsigned int); +extern void gic_bind_eic_interrupt(int irq, int set); +extern unsigned int gic_get_timer_pending(void); #endif /* _ASM_GICREGS_H */ diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index fb698dc..78dbb8a 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq); * IE7. Since R2 their number has to be read from the c0_intctl register. */ #define CP0_LEGACY_COMPARE_IRQ 7 +#define CP0_LEGACY_PERFCNT_IRQ 7 extern int cp0_compare_irq; extern int cp0_compare_irq_shift; diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177..9f1cd31 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -63,7 +63,9 @@ static inline int plat_device_is_coherent(struct device *dev) return 1; #endif #ifdef CONFIG_DMA_NONCOHERENT - return 0; + extern int coherentio; + + return coherentio; #endif } diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index d11aa02..5447d9f 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -86,6 +86,16 @@ #define GIC_CPU_INT4 4 /* . */ #define GIC_CPU_INT5 5 /* Core Interrupt 5 */ +/* MALTA GIC local interrupts */ +#define GIC_INT_TMR (GIC_CPU_INT5) +#define GIC_INT_PERFCTR (GIC_CPU_INT5) + +/* GIC constants */ +/* Add 2 to convert non-eic hw int # to eic vector # */ +#define GIC_CPU_TO_VEC_OFFSET (2) +/* If we map an intr to pin X, GIC will actually generate vector X+1 */ +#define GIC_PIN_TO_VEC_OFFSET (1) + #define GIC_EXT_INTR(x) x /* External Interrupts used for IPI */ diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h index ac79352..3177c83 100644 --- a/arch/mips/include/asm/mips_mt.h +++ b/arch/mips/include/asm/mips_mt.h @@ -19,6 +19,7 @@ extern unsigned long mt_fpemul_threshold; extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); extern void mips_mt_set_cpuoptions(void); +extern void cmp_send_ipi_single(int cpu, unsigned int action); struct class; extern struct class *mt_class; diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h index 259145e..709e78a 100644 --- a/arch/mips/include/asm/topology.h +++ b/arch/mips/include/asm/topology.h @@ -12,6 +12,9 @@ #ifdef CONFIG_SMP #define smt_capable() (smp_num_siblings > 1) +/* FIXME: cpu_sibling_map is not a per_cpu variable */ +/*#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) */ +#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu]) #endif #endif /* __ASM_TOPOLOGY_H */ diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index c6e1b96..e5e4033 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -26,12 +26,40 @@ struct vpe_notifications { struct list_head list; }; - +extern unsigned long physical_memsize; extern int vpe_notify(int index, struct vpe_notifications *notify); +extern void save_gp_address(unsigned int secbase, unsigned int rel); + +/* + * libc style I/O support hooks + */ extern void *vpe_get_shared(int index); extern int vpe_getuid(int index); extern int vpe_getgid(int index); extern char *vpe_getcwd(int index); +/* + * Kernel/Kernel message passing support hooks + */ + +extern void *vpe_get_shared_area(int index, int type); + +/* "Well-Known" Area Types */ + +#define VPE_SHARED_NULL 0 +#define VPE_SHARED_RESERVED -1 + +struct vpe_shared_area { + int type; + void *addr; +}; + +/* + * IRQ assignment and initialization hook for RP services. + */ + +int arch_get_xcpu_irq(void); + +int vpe_send_interrupt(int v, int i); #endif /* _ASM_VPE_H */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5099201..cb1e2e9 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -207,6 +207,7 @@ void __init check_wait(void) cpu_wait = r4k_wait_irqoff; break; + case CPU_1074K: case CPU_74K: cpu_wait = r4k_wait; if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) @@ -835,6 +836,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; break; + case PRID_IMP_1074K: + c->cputype = CPU_1074K; + __cpu_name[cpu] = "MIPS 1074Kc"; + break; } spram_config(); diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index b8c18dc..25278d0 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -57,12 +57,6 @@ static int sp_stopping; extern void *vpe_get_shared(int index); -static void rtlx_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); -} - - /* Interrupt handler may be called before rtlx_init has otherwise had a chance to run. */ @@ -483,7 +477,7 @@ static char register_chrdev_failed[] __initdata = static int __init rtlx_module_init(void) { struct device *dev; - int i, err; + int i, err, irq; if (!cpu_has_mipsmt) { printk("VPE loader: not a MIPS MT capable processor\n"); @@ -523,18 +517,17 @@ static int __init rtlx_module_init(void) notify.start = starting; notify.stop = stopping; vpe_notify(tclimit, ¬ify); - - if (cpu_has_vint) - set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); - else { + irq = arch_get_xcpu_irq(); + if (irq < 0) { pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); err = -ENODEV; goto out_chrdev; } - rtlx_irq.dev_id = rtlx; - setup_irq(rtlx_irq_num, &rtlx_irq); - + err = request_irq(irq, &rtlx_interrupt, IRQF_SHARED, + module_name, (void *)dev); + if (err) + goto out_chrdev; return 0; out_chrdev: diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ff17868..4f54cea 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -34,7 +34,9 @@ #include #include #include +#include +extern int gic_present; static void __init smvp_copy_vpe_config(void) { write_vpe_c0_status( @@ -111,12 +113,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) write_tc_c0_tchalt(TCHALT_H); } +static void mp_send_ipi_single(int cpu, unsigned int action) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (action) { + case SMP_CALL_FUNCTION: + gic_send_ipi(plat_ipi_call_int_xlate(cpu)); + break; + + case SMP_RESCHEDULE_YOURSELF: + gic_send_ipi(plat_ipi_resched_int_xlate(cpu)); + break; + } + + local_irq_restore(flags); +} + static void vsmp_send_ipi_single(int cpu, unsigned int action) { int i; unsigned long flags; int vpflags; + if (gic_present) { + mp_send_ipi_single(cpu, action); + return; + } local_irq_save(flags); vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ @@ -150,9 +175,8 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) static void __cpuinit vsmp_init_secondary(void) { - extern int gic_present; - - /* This is Malta specific: IPI,performance and timer interrupts */ + pr_debug("SMPMT: CPU%d: vsmp_init_secondary\n", smp_processor_id()); + /* This is Malta specific: IPI,performance and timer inetrrupts */ if (gic_present) change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 | STATUSF_IP7); @@ -163,6 +187,8 @@ static void __cpuinit vsmp_init_secondary(void) static void __cpuinit vsmp_smp_finish(void) { + pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id()); + /* CDFIXME: remove this? */ write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); @@ -177,6 +203,7 @@ static void __cpuinit vsmp_smp_finish(void) static void vsmp_cpus_done(void) { + pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id()); } /* @@ -190,6 +217,8 @@ static void vsmp_cpus_done(void) static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) { struct thread_info *gp = task_thread_info(idle); + pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n", + smp_processor_id(), cpu); dvpe(); set_c0_mvpcontrol(MVPCONTROL_VPC); @@ -231,6 +260,7 @@ static void __init vsmp_smp_setup(void) unsigned int mvpconf0, ntc, tc, ncpu = 0; unsigned int nvpe; + pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id()); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ if (cpu_has_fpu) @@ -260,6 +290,7 @@ static void __init vsmp_smp_setup(void) smvp_tc_init(tc, mvpconf0); ncpu = smvp_vpe_init(tc, mvpconf0, ncpu); } + cpu_present_map = cpu_possible_map; /* Release config state */ clear_c0_mvpcontrol(MVPCONTROL_VPC); @@ -271,6 +302,8 @@ static void __init vsmp_smp_setup(void) static void __init vsmp_prepare_cpus(unsigned int max_cpus) { + pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n", + smp_processor_id(), max_cpus); mips_mt_set_cpuoptions(); } diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 6af08d8..5781dbf 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -205,6 +205,7 @@ void __cpuinit spram_config(void) case CPU_24K: case CPU_34K: case CPU_74K: + case CPU_1074K: case CPU_1004K: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index b08220c..bacd9bf 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -124,7 +124,7 @@ _sys_clone(nabi_no_regargs struct pt_regs regs) child_tidptr = (int __user *) regs.regs[8]; #endif return do_fork(clone_flags, newsp, ®s, 0, - parent_tidptr, child_tidptr); + parent_tidptr, child_tidptr); } /* @@ -264,11 +264,12 @@ save_static_function(sys_sysmips); static int __used noinline _sys_sysmips(nabi_no_regargs struct pt_regs regs) { - long cmd, arg1, arg2; + long cmd, arg1, arg2, arg3; cmd = regs.regs[4]; arg1 = regs.regs[5]; arg2 = regs.regs[6]; + arg3 = regs.regs[7]; switch (cmd) { case MIPS_ATOMIC_SET: diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index f6f9152..e8c99a4 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -73,17 +73,14 @@ static const int minor = 1; /* fixed for now */ static struct kspd_notifications kspd_events; static int kspd_events_reqd; #endif - -/* grab the likely amount of memory we will need. */ -#ifdef CONFIG_MIPS_VPE_LOADER_TOM -#define P_SIZE (2 * 1024 * 1024) -#else -/* add an overhead to the max kmalloc size for non-striped symbols/etc */ +/* + * Size of private kernel buffer for ELF headers and sections + */ #define P_SIZE (256 * 1024) -#endif - -extern unsigned long physical_memsize; +/* + * Size of private kernel buffer for ELF headers and sections + */ #define MAX_VPES 16 #define VPE_PATH_MAX 256 @@ -100,6 +97,16 @@ enum tc_state { TC_STATE_DYNAMIC }; +enum load_state { + LOAD_STATE_EHDR, + LOAD_STATE_PHDR, + LOAD_STATE_SHDR, + LOAD_STATE_PIMAGE, + LOAD_STATE_TRAILER, + LOAD_STATE_DONE, + LOAD_STATE_ERROR +}; + struct vpe { enum vpe_state state; @@ -107,10 +114,25 @@ struct vpe { int minor; /* elfloader stuff */ + unsigned long offset; /* File offset into input stream */ void *load_addr; - unsigned long len; + unsigned long copied; char *pbuffer; - unsigned long plen; + unsigned long pbsize; + /* Program loading state */ + enum load_state l_state; + Elf_Ehdr *l_ehdr; + struct elf_phdr *l_phdr; + unsigned int l_phlen; + Elf_Shdr *l_shdr; + unsigned int l_shlen; + int *l_phsort; /* Sorted index list of program headers */ + int l_segoff; /* Offset into current program segment */ + int l_cur_seg; /* Indirect index of segment currently being loaded */ + unsigned int l_progminad; + unsigned int l_progmaxad; + unsigned int l_trailer; + unsigned int uid, gid; char cwd[VPE_PATH_MAX]; @@ -122,9 +144,12 @@ struct vpe { /* The list of vpe's */ struct list_head list; - /* shared symbol address */ + /* legacy shared symbol address */ void *shared_ptr; + /* shared area descriptor array address */ + struct vpe_shared_area *shared_areas; + /* the list of who wants to know when something major happens */ struct list_head notify; @@ -146,13 +171,24 @@ struct { spinlock_t tc_list_lock; struct list_head tc_list; /* Thread contexts */ } vpecontrol = { - .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), + .vpe_list_lock = SPIN_LOCK_UNLOCKED, .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), - .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), + .tc_list_lock = SPIN_LOCK_UNLOCKED, .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) }; static void release_progmem(void *ptr); +/* + * Values and state associated with publishing shared memory areas + */ + +#define N_PUB_AREAS 4 + +static struct vpe_shared_area published_vpe_area[N_PUB_AREAS] = { + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0} }; /* get the vpe associated with this minor */ static struct vpe *get_vpe(int minor) @@ -175,7 +211,7 @@ static struct vpe *get_vpe(int minor) return res; } -/* get the vpe associated with this minor */ +/* get the tc associated with this minor */ static struct tc *get_tc(int index) { struct tc *res, *t; @@ -200,7 +236,8 @@ static struct vpe *alloc_vpe(int minor) if ((v = kzalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) return NULL; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct vpe), (unsigned int)v); INIT_LIST_HEAD(&v->tc); spin_lock(&vpecontrol.vpe_list_lock); list_add_tail(&v->list, &vpecontrol.vpe_list); @@ -219,7 +256,8 @@ static struct tc *alloc_tc(int index) if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) goto out; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct tc), (unsigned int)tc); INIT_LIST_HEAD(&tc->tc); tc->index = index; @@ -237,6 +275,11 @@ static void release_vpe(struct vpe *v) list_del(&v->list); if (v->load_addr) release_progmem(v); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v->l_phsort); + kfree(v->l_phsort); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v); kfree(v); } @@ -260,8 +303,88 @@ static void __maybe_unused dump_mtregs(void) val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); } +/* + * The original APRP prototype assumed a single, unshared IRQ for + * cross-VPE interrupts, used by the RTLX code. But M3P networking + * and other future functions may need to share an IRQ, particularly + * in 34K/Malta configurations without an external interrupt controller. + * All cross-VPE insterrupt users need to coordinate through shared + * functions here. + */ + +/* + * It would be nice if I could just have this initialized to zero, + * but the patchcheck police won't hear of it... + */ + +static int xvpe_vector_set; + +#define XVPE_INTR_OFFSET 0 + +static int xvpe_irq = MIPS_CPU_IRQ_BASE + XVPE_INTR_OFFSET; + +static void xvpe_dispatch(void) +{ + do_IRQ(xvpe_irq); +} + +/* Name here is generic, as m3pnet.c could in principle be used by non-MIPS */ +int arch_get_xcpu_irq() +{ + /* + * Some of this will ultimately become platform code, + * but for now, we're only targeting 34K/FPGA/Malta, + * and there's only one generic mechanism. + */ + if (!xvpe_vector_set) { + /* + * A more elaborate shared variable shouldn't be needed. + * Two initializations back-to-back should be harmless. + */ + if (cpu_has_vint) { + set_vi_handler(XVPE_INTR_OFFSET, xvpe_dispatch); + xvpe_vector_set = 1; + } else { + printk(KERN_ERR "APRP requires vectored interrupts\n"); + return -1; + } + } + + return xvpe_irq; +} +EXPORT_SYMBOL(arch_get_xcpu_irq); + +int vpe_send_interrupt(int vpe, int inter) +{ + unsigned long flags; + unsigned int vpeflags; + + local_irq_save(flags); + vpeflags = dvpe(); + + /* + * Initial version makes same simple-minded assumption + * as is implicit elsewhere in this module, that the + * only RP of interest is using the first non-Linux TC. + * We ignore the parameters provided by the caller! + */ + settc(tclimit); + /* + * In 34K/Malta, the only cross-VPE interrupts possible + * are done by setting SWINT bits in Cause, of which there + * are two. SMTC uses SW1 for a multiplexed class of IPIs, + * and this mechanism should be generalized to APRP and use + * the same protocol. Until that's implemented, send only + * SW0 here, regardless of requested type. + */ + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); + evpe(vpeflags); + local_irq_restore(flags); + return 1; +} +EXPORT_SYMBOL(vpe_send_interrupt); /* Find some VPE program space */ -static void *alloc_progmem(unsigned long len) +static void *alloc_progmem(void *requested, unsigned long len) { void *addr; @@ -271,10 +394,28 @@ static void *alloc_progmem(unsigned long len) * physically have, for example by passing a mem= boot argument. */ addr = pfn_to_kaddr(max_low_pfn); - memset(addr, 0, len); + if (requested != 0) { + if (requested >= addr) + addr = requested; + else + addr = 0; + } + if (addr != 0) + memset(addr, 0, len); + printk(KERN_DEBUG "pfn_to_kaddr returns %lu bytes of memory at %x\n", + len, (unsigned int)addr); #else - /* simple grab some mem for now */ - addr = kzalloc(len, GFP_KERNEL); + if (requested != 0) { + /* If we have a target in mind, grab a 2x slice and hope... */ + addr = kzalloc(len*2, GFP_KERNEL); + if ((requested >= addr) && (requested < (addr + len))) + addr = requested; + else + addr = 0; + } else { + /* simply grab some mem for now */ + addr = kzalloc(len, GFP_KERNEL); + } #endif return addr; @@ -446,6 +587,8 @@ static int apply_r_mips_hi16(struct module *me, uint32_t *location, * actual relocation. */ n = kmalloc(sizeof *n, GFP_KERNEL); + printk(KERN_DEBUG "Used kmalloc to allocate %d bytes at %x\n", + sizeof(struct mips_hi16), (unsigned int)n); if (!n) return -ENOMEM; @@ -503,6 +646,8 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, *l->addr = insn; next = l->next; + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)l); kfree(l); l = next; } @@ -596,7 +741,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs, return 0; } -static inline void save_gp_address(unsigned int secbase, unsigned int rel) +void save_gp_address(unsigned int secbase, unsigned int rel) { gp_addr = secbase + rel; gp_offs = gp_addr - (secbase & 0xffff0000); @@ -816,16 +961,41 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, struct module *mod) { Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; - unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); + unsigned int i, j, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); for (i = 1; i < n; i++) { - if (strcmp(strtab + sym[i].st_name, "__start") == 0) { - v->__start = sym[i].st_value; + if (strcmp(strtab + sym[i].st_name, "__start") == 0) + v->__start = sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) + v->shared_ptr = (void *)sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "_vpe_shared_areas") == 0) { + struct vpe_shared_area *psa + = (struct vpe_shared_area *)sym[i].st_value; + struct vpe_shared_area *tpsa; + v->shared_areas = psa; + printk(KERN_INFO"_vpe_shared_areas found, 0x%x\n", + (unsigned int)v->shared_areas); + /* + * Copy any "published" areas to the descriptor + */ + for (j = 0; j < N_PUB_AREAS; j++) { + if (published_vpe_area[j].type != VPE_SHARED_RESERVED) { + tpsa = psa; + while (tpsa->type != VPE_SHARED_NULL) { + if ((tpsa->type == VPE_SHARED_RESERVED) + || (tpsa->type == published_vpe_area[j].type)) { + tpsa->type = published_vpe_area[j].type; + tpsa->addr = published_vpe_area[j].addr; + break; + } + tpsa++; + } + } } + } - if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) { - v->shared_ptr = (void *)sym[i].st_value; - } } if ( (v->__start == 0) || (v->shared_ptr == NULL)) @@ -850,14 +1020,12 @@ static int vpe_elfload(struct vpe * v) memset(&mod, 0, sizeof(struct module)); strcpy(mod.name, "VPE loader"); - - hdr = (Elf_Ehdr *) v->pbuffer; - len = v->plen; + hdr = v->l_ehdr; + len = v->pbsize; /* Sanity checks against insmoding binaries or wrong arch, weird elf version */ - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0 - || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) + if ((hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) || !elf_check_arch(hdr) || hdr->e_shentsize != sizeof(*sechdrs)) { printk(KERN_WARNING @@ -869,9 +1037,8 @@ static int vpe_elfload(struct vpe * v) if (hdr->e_type == ET_REL) relocate = 1; - if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { - printk(KERN_ERR "VPE loader: program length %u truncated\n", - len); + if (len < v->l_phlen + v->l_shlen) { + printk(KERN_ERR "VPE loader: Headers exceed %u bytes\n", len); return -ENOEXEC; } @@ -905,9 +1072,13 @@ static int vpe_elfload(struct vpe * v) } } layout_sections(&mod, hdr, sechdrs, secstrings); + /* + * Non-relocatable loads should have already done their + * allocates, based on program header table. + */ } - v->load_addr = alloc_progmem(mod.core_size); + memset(v->load_addr, 0, mod.core_size); if (!v->load_addr) return -ENOMEM; @@ -960,19 +1131,10 @@ static int vpe_elfload(struct vpe * v) } } else { - struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); - - for (i = 0; i < hdr->e_phnum; i++) { - if (phdr->p_type == PT_LOAD) { - memcpy((void *)phdr->p_paddr, - (char *)hdr + phdr->p_offset, - phdr->p_filesz); - memset((void *)phdr->p_paddr + phdr->p_filesz, - 0, phdr->p_memsz - phdr->p_filesz); - } - phdr++; - } + /* + * Program image is already in memory. + */ for (i = 0; i < hdr->e_shnum; i++) { /* Internal symbols and strings. */ if (sechdrs[i].sh_type == SHT_SYMTAB) { @@ -989,7 +1151,7 @@ static int vpe_elfload(struct vpe * v) /* make sure it's physically written out */ flush_icache_range((unsigned long)v->load_addr, - (unsigned long)v->load_addr + v->len); + (unsigned long)v->load_addr + v->copied); if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { if (v->__start == 0) { @@ -1003,8 +1165,8 @@ static int vpe_elfload(struct vpe * v) "program does not contain vpe_shared symbol.\n" " Unable to use AMVP (AP/SP) facilities.\n"); } + pr_info("APRP VPE loader: elf loaded\n"); - printk(" elf loaded\n"); return 0; } @@ -1069,6 +1231,10 @@ static int vpe_open(struct inode *inode, struct file *filp) return -ENODEV; } + /* + * This treats the tclimit command line configuration input + * as a minor device indication, which is probably unwholesome. + */ if ((v = get_vpe(tclimit)) == NULL) { pr_warning("VPE loader: unable to get vpe\n"); @@ -1085,18 +1251,20 @@ static int vpe_open(struct inode *inode, struct file *filp) } release_progmem(v->load_addr); + kfree(v->l_phsort); cleanup_tc(get_tc(tclimit)); } /* this of-course trashes what was there before... */ v->pbuffer = vmalloc(P_SIZE); - if (!v->pbuffer) { - pr_warning("VPE loader: unable to allocate memory\n"); - return -ENOMEM; - } - v->plen = P_SIZE; v->load_addr = NULL; - v->len = 0; + v->copied = 0; + v->offset = 0; + v->l_state = LOAD_STATE_EHDR; + v->l_ehdr = NULL; + v->l_phdr = NULL; + v->l_phsort = NULL; + v->l_shdr = NULL; v->uid = filp->f_cred->fsuid; v->gid = filp->f_cred->fsgid; @@ -1115,6 +1283,7 @@ static int vpe_open(struct inode *inode, struct file *filp) printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret); v->shared_ptr = NULL; + v->shared_areas = NULL; v->__start = 0; return 0; @@ -1123,26 +1292,39 @@ static int vpe_open(struct inode *inode, struct file *filp) static int vpe_release(struct inode *inode, struct file *filp) { struct vpe *v; - Elf_Ehdr *hdr; int ret = 0; v = get_vpe(tclimit); if (v == NULL) return -ENODEV; + /* + * If image load had no errors, massage program/section tables + * to reflect movement of program/section data into VPE program + * memory. + */ + if (v->l_state != LOAD_STATE_DONE) { + printk(KERN_WARNING "VPE Release after incomplete load\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); + return -ENOEXEC; + } - hdr = (Elf_Ehdr *) v->pbuffer; - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) { - if (vpe_elfload(v) >= 0) { - vpe_run(v); - } else { - printk(KERN_WARNING "VPE loader: ELF load failed.\n"); - ret = -ENOEXEC; - } + if (vpe_elfload(v) >= 0) { + vpe_run(v); } else { - printk(KERN_WARNING "VPE loader: only elf files are supported\n"); + printk(KERN_WARNING "VPE loader: ELF load failed.\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); ret = -ENOEXEC; } + /* It's good to be able to run the SP and if it chokes have a look at the /dev/rt?. But if we reset the pointer to the shared struct we lose what has happened. So perhaps if garbage is sent to the vpe @@ -1151,17 +1333,68 @@ static int vpe_release(struct inode *inode, struct file *filp) if (ret < 0) v->shared_ptr = NULL; - vfree(v->pbuffer); - v->plen = 0; - + // cleanup any temp buffers + if (v->pbuffer) { + printk(KERN_DEBUG "Used vfree to free memory at %x\n", + (unsigned int)v->pbuffer); + vfree(v->pbuffer); + } + v->pbsize = 0; return ret; } +/* + * A sort of insertion sort to generate list of program header indices + * in order of their file offsets. + */ + +static void indexort(struct elf_phdr *phdr, int nph, int *index) +{ + int i, j, t; + unsigned int toff; + + /* Create initial mapping */ + for (i = 0; i < nph; i++) + index[i] = i; + /* Do the indexed insert sort */ + for (i = 1; i < nph; i++) { + j = i; + t = index[j]; + toff = phdr[t].p_offset; + while ((j > 0) && (phdr[index[j-1]].p_offset > toff)) { + index[j] = index[j-1]; + j--; + } + index[j] = t; + } +} + + +/* + * This function has to convert the ELF file image being sequentially + * streamed to the pseudo-device into the binary image, symbol, and + * string information, which the ELF format allows to be in some degree + * of disorder. + * + * The ELF header and, if present, program header table, are copied into + * a temporary buffer. Loadable program segments, if present, are copied + * into the RP program memory at the addresses specified by the program + * header table. + * + * Sections not specified by the program header table are loaded into + * memory following the program segments if they are "allocated", or + * into the temporary buffer if they are not. The section header + * table is loaded into the temporary buffer.??? + */ +#define CURPHDR (v->l_phdr[v->l_phsort[v->l_cur_seg]]) static ssize_t vpe_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos) { size_t ret = count; struct vpe *v; + int tocopy, uncopied; + int i; + unsigned int progmemlen; if (iminor(file->f_path.dentry->d_inode) != minor) return -ENODEV; @@ -1170,17 +1403,357 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, if (v == NULL) return -ENODEV; - if ((count + v->len) > v->plen) { - printk(KERN_WARNING - "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + if (v->pbuffer == NULL) { + printk(KERN_ERR "VPE loader: no buffer for program\n"); return -ENOMEM; } - count -= copy_from_user(v->pbuffer + v->len, buffer, count); - if (!count) - return -EFAULT; + while (count) { + switch (v->l_state) { + case LOAD_STATE_EHDR: + /* Loading ELF Header into scratch buffer */ + tocopy = min((unsigned long)count, + sizeof(Elf_Ehdr) - v->offset); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->copied == sizeof(Elf_Ehdr)) { + v->l_ehdr = (Elf_Ehdr *)v->pbuffer; + if (memcmp(v->l_ehdr->e_ident, ELFMAG, 4) != 0) { + printk(KERN_WARNING "VPE loader: %s\n", + "non-ELF file image"); + ret = -ENOEXEC; + v->l_state = LOAD_STATE_ERROR; + break; + } + if (v->l_ehdr->e_phoff != 0) { + v->l_phdr = (struct elf_phdr *) + (v->pbuffer + v->l_ehdr->e_phoff); + v->l_phlen = v->l_ehdr->e_phentsize + * v->l_ehdr->e_phnum; + /* Check against buffer overflow */ + if ((v->copied + v->l_phlen) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf program header table size too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_PHDR; + /* + * Program headers generally indicate + * linked executable with possibly + * valid entry point. + */ + v->__start = v->l_ehdr->e_entry; + } else if (v->l_ehdr->e_shoff != 0) { + /* + * No program headers, but a section + * header table. A relocatable binary. + * We need to load the works into the + * kernel temp buffer to compute the + * RP program image. That limits our + * binary size, but at least we're no + * worse off than the original APRP + * prototype. + */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big.\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + } else { + /* + * If neither program nor section tables, + * we don't know what to do. + */ + v->l_state = LOAD_STATE_ERROR; + return -ENOEXEC; + } + } + break; + case LOAD_STATE_PHDR: + /* Loading Program Headers into scratch */ + tocopy = min((unsigned long)count, + v->l_ehdr->e_phoff + v->l_phlen - v->copied); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + + if (v->copied == v->l_ehdr->e_phoff + v->l_phlen) { + /* + * It's legal for the program headers to be + * out of order with respect to the file layout. + * Generate a list of indices, sorted by file + * offset. + */ + v->l_phsort = kmalloc(v->l_ehdr->e_phnum + * sizeof(int), GFP_KERNEL); + printk(KERN_DEBUG + "Used kmalloc to allocate %d bytes of memory at %x\n", + v->l_ehdr->e_phnum*sizeof(int), + (unsigned int)v->l_phsort); + if (!v->l_phsort) + return -ENOMEM; /* Preposterous, but... */ + indexort(v->l_phdr, v->l_ehdr->e_phnum, + v->l_phsort); + + v->l_progminad = (unsigned int)-1; + v->l_progmaxad = 0; + progmemlen = 0; + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + /* Unstripped .reginfo sections are bad */ + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "User-mode p_vaddr, ", + "skipping program segment,"); + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "strip .reginfo from binary ", + "if necessary."); + continue; + } + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < v->l_progminad) + v->l_progminad = + v->l_phdr[v->l_phsort[i]].p_vaddr; + if ((v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz) + > v->l_progmaxad) + v->l_progmaxad = + v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz; + } + } + printk(KERN_INFO "APRP RP program 0x%x to 0x%x\n", + v->l_progminad, v->l_progmaxad); + /* + * Do a simple sanity check of the memory being + * allocated. Abort if greater than an arbitrary + * value of 32MB + */ + if (v->l_progmaxad - v->l_progminad > + 32*1024*1024) { + printk(KERN_WARNING + "RP program failed to allocate %d kbytes - limit is 32,768 KB\n", + (v->l_progmaxad - v->l_progminad)/1024); + return -ENOMEM; + } + + v->load_addr = alloc_progmem((void *)v->l_progminad, + v->l_progmaxad - v->l_progminad); + if (!v->load_addr) + return -ENOMEM; + if ((unsigned int)v->load_addr + > v->l_progminad) { + release_progmem(v->load_addr); + return -ENOMEM; + } + /* Find first segment with loadable content */ + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + if (i == v->l_ehdr->e_phnum) { + /* No loadable program segment? Bogus file. */ + printk(KERN_WARNING "Bad ELF file for APRP\n"); + return -ENOEXEC; + } + v->l_segoff = 0; + v->l_state = LOAD_STATE_PIMAGE; + } + break; + case LOAD_STATE_PIMAGE: + /* + * Skip through input stream until + * first program segment. Would be + * better to have loaded up to here + * into the temp buffer, but for now + * we simply rule out "interesting" + * sections prior to the last program + * segment in an executable file. + */ + if (v->offset < CURPHDR.p_offset) { + uncopied = CURPHDR.p_offset - v->offset; + if (uncopied > count) + uncopied = count; + count -= uncopied; + buffer += uncopied; + v->offset += uncopied; + /* Go back through the "while" */ + break; + } + /* + * Having dispensed with any unlikely fluff, + * copy from user I/O buffer to program segment. + */ + tocopy = min(count, CURPHDR.p_filesz - v->l_segoff); + + /* Loading image into RP memory */ + uncopied = copy_from_user((char *)CURPHDR.p_vaddr + + v->l_segoff, buffer, tocopy); + count -= tocopy - uncopied; + v->offset += tocopy - uncopied; + v->l_segoff += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->l_segoff >= CURPHDR.p_filesz) { + /* Finished current segment load */ + /* Zero out non-file-sourced image */ + uncopied = CURPHDR.p_memsz - CURPHDR.p_filesz; + if (uncopied > 0) + memset((char *)CURPHDR.p_vaddr + v->l_segoff, + 0, uncopied); + /* Advance to next segment */ + for (i = v->l_cur_seg + 1; + i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + /* If none left, prepare to load section headers */ + if (i == v->l_ehdr->e_phnum) { + if (v->l_ehdr->e_shoff != 0) { + /* Copy to where we left off in temp buffer */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + break; + } + } else { + /* reset offset for new program segment */ + v->l_segoff = 0; + } + } + break; + case LOAD_STATE_SHDR: + /* + * Read stream into private buffer up + * through and including the section header + * table. + */ - v->len += count; + tocopy = min((unsigned long)count, + v->l_ehdr->e_shoff + v->l_shlen - v->offset); + if (tocopy) { + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + /* Finished? */ + if (v->offset == v->l_ehdr->e_shoff + v->l_shlen) { + unsigned int offset_delta = v->offset - v->copied; + + v->l_shdr = (Elf_Shdr *)(v->pbuffer + + v->l_ehdr->e_shoff - offset_delta); + /* + * Check for sections after the section table, + * which for gcc MIPS binaries includes + * the symbol table. Do any other processing + * that requires value within stream, and + * normalize offsets to be relative to + * the header-only layout of temp buffer. + */ + + /* Assume no trailer until we detect one */ + v->l_trailer = 0; + v->l_state = LOAD_STATE_DONE; + for (i = 0; i < v->l_ehdr->e_shnum; i++) { + if (v->l_shdr[i].sh_offset + > v->l_ehdr->e_shoff) { + v->l_state = LOAD_STATE_TRAILER; + /* Track trailing data length */ + if (v->l_trailer + < (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen)) + v->l_trailer = + (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen); + } + /* Adjust section offset if necessary */ + v->l_shdr[i].sh_offset -= offset_delta; + } + if ((v->copied + v->l_trailer) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + + /* Fix up offsets in ELF header */ + v->l_ehdr->e_shoff = (unsigned int)v->l_shdr + - (unsigned int)v->pbuffer; + } + break; + case LOAD_STATE_TRAILER: + /* + * Symbol and string tables follow section headers + * in gcc binaries for MIPS. Copy into temp buffer. + */ + if (v->l_trailer) { + tocopy = min(count, v->l_trailer); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->l_trailer -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + if (!v->l_trailer) + v->l_state = LOAD_STATE_DONE; + break; + case LOAD_STATE_DONE: + if (count) + count = 0; + break; + case LOAD_STATE_ERROR: + default: + return -EINVAL; + } + } return ret; } @@ -1216,7 +1789,9 @@ int vpe_start(vpe_handle vpe, unsigned long start) { struct vpe *v = vpe; - v->__start = start; + /* Null start address means use value from ELF file */ + if (start) + v->__start = start; return vpe_run(v); } @@ -1341,6 +1916,99 @@ char *vpe_getcwd(int index) EXPORT_SYMBOL(vpe_getcwd); +/* + * RP applications may contain a _vpe_shared_area descriptor + * array to allow for data sharing with Linux kernel functions + * that's slightly more abstracted and extensible than the + * fixed binding used by the rtlx support. Indeed, the rtlx + * support should ideally be converted to use the generic + * shared area descriptor scheme at some point. + * + * mips_get_vpe_shared_area() can be used by AP kernel + * modules to get an area pointer of a given type, if + * it exists. + * + * mips_publish_vpe_area() is used by AP kernel modules + * to share kseg0 kernel memory with the RP. It maintains + * a private table, so that publishing can be done before + * the RP program is launched. Making this table dynamically + * allocated and extensible would be good scalable OS design. + * however, until there's more than one user of the mechanism, + * it should be an acceptable simplification to allow a static + * maximum of 4 published areas. + */ + +void *mips_get_vpe_shared_area(int index, int type) +{ + struct vpe *v; + struct vpe_shared_area *vsa; + + v = get_vpe(index); + if (v == NULL) + return NULL; + + if (v->shared_areas == NULL) + return NULL; + + vsa = v->shared_areas; + + while (vsa->type != VPE_SHARED_NULL) { + if (vsa->type == type) + return vsa->addr; + else + vsa++; + } + /* Fell through without finding type */ + + return NULL; +} +EXPORT_SYMBOL(mips_get_vpe_shared_area); + +int mips_publish_vpe_area(int type, void *ptr) +{ + int i; + int retval = 0; + struct vpe *v; + unsigned long flags; + unsigned int vpflags; + + printk(KERN_INFO "mips_publish_vpe_area(0x%x, 0x%x)\n", type, (int)ptr); + if ((unsigned int)ptr >= KSEG2) { + printk(KERN_ERR "VPE area pubish of invalid address 0x%x\n", + (int)ptr); + return 0; + } + for (i = 0; i < N_PUB_AREAS; i++) { + if (published_vpe_area[i].type == VPE_SHARED_RESERVED) { + published_vpe_area[i].type = type; + published_vpe_area[i].addr = ptr; + retval = type; + break; + } + } + /* + * If we've already got a VPE up and running, try to + * update the shared descriptor with the new data. + */ + list_for_each_entry(v, &vpecontrol.vpe_list, list) { + if (v->shared_areas != NULL) { + local_irq_save(flags); + vpflags = dvpe(); + for (i = 0; v->shared_areas[i].type != VPE_SHARED_NULL; i++) { + if ((v->shared_areas[i].type == type) + || (v->shared_areas[i].type == VPE_SHARED_RESERVED)) { + v->shared_areas[i].type = type; + v->shared_areas[i].addr = ptr; + } + } + evpe(vpflags); + local_irq_restore(flags); + } + } + return retval; +} +EXPORT_SYMBOL(mips_publish_vpe_area); + #ifdef CONFIG_MIPS_APSP_KSPD static void kspd_sp_exit( int sp_id) { @@ -1359,6 +2027,7 @@ static ssize_t store_kill(struct device *dev, struct device_attribute *attr, } release_progmem(vpe->load_addr); + kfree(vpe->l_phsort); cleanup_tc(get_tc(tclimit)); vpe_stop(vpe); vpe_free(vpe); @@ -1404,6 +2073,8 @@ static struct device_attribute vpe_class_attributes[] = { static void vpe_device_release(struct device *cd) { + printk(KERN_DEBUG "Using kfree to free vpe class device at %x\n", + (unsigned int)cd); kfree(cd); } @@ -1430,19 +2101,24 @@ static int __init vpe_module_init(void) } if (vpelimit == 0) { - printk(KERN_WARNING "No VPEs reserved for AP/SP, not " - "initializing VPE loader.\nPass maxvpes= argument as " - "kernel argument\n"); - +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) + printk(KERN_WARNING "No VPEs reserved for VPE loader.\n" + "Pass maxvpes= argument as kernel argument\n"); return -ENODEV; +#else + vpelimit = 1; +#endif } if (tclimit == 0) { +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) printk(KERN_WARNING "No TCs reserved for AP/SP, not " "initializing VPE loader.\nPass maxtcs= argument as " "kernel argument\n"); - return -ENODEV; +#else + tclimit = 1; +#endif } major = register_chrdev(0, module_name, &vpe_fops); @@ -1456,7 +2132,7 @@ static int __init vpe_module_init(void) printk(KERN_ERR "vpe_class registration failed\n"); goto out_chrdev; } - + xvpe_vector_set = 0; device_initialize(&vpe_device); vpe_device.class = &vpe_class, vpe_device.parent = NULL, diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index bda8eb2..efcf385 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) c->icache.linesz = 2 << lsize; else c->icache.linesz = lsize; - c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); c->icache.ways = 1 + ((config1 >> 16) & 7); icache_size = c->icache.sets * @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) c->dcache.linesz = 2 << lsize; else c->dcache.linesz= lsize; - c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); c->dcache.ways = 1 + ((config1 >> 7) & 7); dcache_size = c->dcache.sets * @@ -1051,9 +1051,30 @@ static void __cpuinit probe_pcache(void) case CPU_R14000: break; + case CPU_74K: + /* + * Early versions of the 74k do not update + * the cache tags on a vtag miss/ptag hit + * which can occur in the case of KSEG0/KUSEG aliases + * In this case it is better to treat the cache as always + * having aliases + */ + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) + c->dcache.flags |= MIPS_CACHE_VTAG; + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + goto bypass1074; + + case CPU_1074K: + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) { + c->dcache.flags |= MIPS_CACHE_VTAG; + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + } + /* fall through */ +bypass1074: + ; case CPU_24K: case CPU_34K: - case CPU_74K: case CPU_1004K: if ((read_c0_config7() & (1 << 16))) { /* effectively physically indexed dcache, @@ -1061,6 +1082,7 @@ static void __cpuinit probe_pcache(void) c->dcache.flags |= MIPS_CACHE_PINDEX; break; } + /* fall through */ default: if (c->dcache.waysize > PAGE_SIZE) c->dcache.flags |= MIPS_CACHE_ALIASES; @@ -1371,26 +1393,13 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; - -static int __init setcoherentio(char *str) -{ - coherentio = 1; - - return 1; -} - -__setup("coherentio", setcoherentio); -#endif - void __cpuinit r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); extern char __weak except_vec2_generic; extern char __weak except_vec2_sb1; + extern int coherentio; struct cpuinfo_mips *c = ¤t_cpu_data; switch (c->cputype) { @@ -1461,8 +1470,10 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* We want to run CMP kernels on core(s) with and without coherent caches */ + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 4608491..669995a 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -100,6 +100,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); static void *mips_dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t * dma_handle, gfp_t gfp) { + extern int hw_coherentio; void *ret; if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) @@ -115,7 +116,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, if (!plat_device_is_coherent(dev)) { dma_cache_wback_inv((unsigned long) ret, size); - ret = UNCAC_ADDR(ret); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } } @@ -134,6 +136,7 @@ EXPORT_SYMBOL(dma_free_noncoherent); static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { + extern int hw_coherentio; unsigned long addr = (unsigned long) vaddr; int order = get_order(size); @@ -143,7 +146,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) - addr = CAC_ADDR(addr); + if (!hw_coherentio) + addr = CAC_ADDR(addr); free_pages(addr, get_order(size)); } diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index a96d281..d57a233 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -158,7 +158,7 @@ void __init prom_meminit(void) size = p->size; add_memory_region(base, size, type); - p++; + p++; } } diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index bf80921..afeb619 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -241,8 +241,9 @@ void __init mips_pcibios_init(void) return; } - if (controller->io_resource->start < 0x00001000UL) /* FIXME */ - controller->io_resource->start = 0x00001000UL; + /* Change start address to avoid conflicts with ACPI and SMB devices */ + if (controller->io_resource->start < 0x00002000UL) /* FIXME */ + controller->io_resource->start = 0x00002000UL; iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index b7f37d4..618f503 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -32,6 +32,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -105,6 +106,105 @@ static void __init fd_activate(void) } #endif +int coherentio = -1; /* no DMA cache coherency (may be set by user) */ +int hw_coherentio; /* init to 0 => no HW DMA cache coherency (reflects real HW) */ +static int __init setcoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); + return 1; +} +__setup("coherentio", setcoherentio); + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 1; +} +__setup("nocoherentio", setnocoherentio); + +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(prom_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + hw_coherentio = supported; + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -207,6 +307,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif @@ -222,3 +324,14 @@ void __init plat_mem_setup(void) board_be_init = malta_be_init; board_be_handler = malta_be_handler; } +/* Enable PCI 2.1 compatibility in PIIX4 */ +static void __init quirk_dlcsetup(struct pci_dev *dev) +{ + u8 odlc, ndlc; + (void) pci_read_config_byte(dev, 0x82, &odlc); + /* Enable passive releases and delayed transaction */ + ndlc = odlc | 7; + (void) pci_write_config_byte(dev, 0x82, ndlc); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + quirk_dlcsetup); diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index d1f2d4c..846faf7 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -83,6 +83,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_25KF: case CPU_34K: case CPU_1004K: + case CPU_1074K: case CPU_74K: case CPU_SB1: case CPU_SB1A: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..13487a9 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -330,16 +330,11 @@ static int __init mipsxx_init(void) break; case CPU_1004K: -#if 0 - /* FIXME: report as 34K for now */ - op_model_mipsxx_ops.cpu_type = "mips/1004K"; - break; -#endif - case CPU_34K: op_model_mipsxx_ops.cpu_type = "mips/34K"; break; + case CPU_1074K: case CPU_74K: op_model_mipsxx_ops.cpu_type = "mips/74K"; break; -- 1.7.9.6 From ddaney.cavm@gmail.com Fri Apr 6 01:52:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 01:52:48 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:63462 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904025Ab2DEXwe (ORCPT ); Fri, 6 Apr 2012 01:52:34 +0200 Received: by obhx4 with SMTP id x4so2945967obh.36 for ; Thu, 05 Apr 2012 16:52:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=iB3Qf0Qpr6bF1lspJ0HSloMGWoAYbAf1n2stKU+KFA0=; b=uLWo90+ehcrwEOX241RwMIYZSHwCbbIYB3hqA+gIDzINv1Jjv5WA6d4emhoNLvul+h sBZUBdwGu8aGjcXTs1DOT+UrD7UIbjbgTIVQs6+UZtLyrl9Ile1yqSiLkQ+JOJ5CGT3t Kks6eMcFb4umyLl7uqt/8c72oO+1XQKTUFBHhC3KLx3BuX6Rr8Mgahlfug6pTi4CaC4W hcirxb5V5iLi8Niz/XTYAN9upbUE+PAB27Rrk2ItM6OhnL43KQys79BSod7eOu6U3hOm WomTwHCy4F3WnbljSFzQLY6VogkvxNM0eD45NF/p2XqV5rZ6gJEzwidMULlgi+ZzsvN/ pZ+w== Received: by 10.60.22.70 with SMTP id b6mr6698956oef.5.1333669947669; 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[64.2.3.195]) by mx.google.com with ESMTPS id xb7sm5666960obb.10.2012.04.05.16.52.26 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 05 Apr 2012 16:52:26 -0700 (PDT) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q35NqLLR025300; Thu, 5 Apr 2012 16:52:21 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q35NqFcF025298; Thu, 5 Apr 2012 16:52:16 -0700 From: David Daney To: devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring , Benjamin Herrenschmidt , Thomas Gleixner Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Subject: [PATCH] irq/irq_domain: Quit ignoring error returns from irq_alloc_desc_from(). Date: Thu, 5 Apr 2012 16:52:13 -0700 Message-Id: <1333669933-25267-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 32863 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1825 Lines: 59 From: David Daney In commit 4bbdd45a (irq_domain/powerpc: eliminate irq_map; use irq_alloc_desc() instead) code was added that ignores error returns from irq_alloc_desc_from() by (silently) casting the return value to unsigned. The negitive value error return now suddenly looks like a valid irq number. Commits cc79ca69 (irq_domain: Move irq_domain code from powerpc to kernel/irq) and 1bc04f2c (irq_domain: Add support for base irq and hwirq in legacy mappings) move this code to its current location in irqdomain.c The result of all of this is a null pointer dereference OOPS if one of the error cases is hit. The fix: Don't cast away the negativeness of the return value and then check for errors. Signed-off-by: David Daney --- kernel/irq/irqdomain.c | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-) diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index af48e59..9d3e3ae 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -351,6 +351,7 @@ unsigned int irq_create_mapping(struct irq_domain *domain, irq_hw_number_t hwirq) { unsigned int virq, hint; + int irq; pr_debug("irq: irq_create_mapping(0x%p, 0x%lx)\n", domain, hwirq); @@ -380,14 +381,14 @@ unsigned int irq_create_mapping(struct irq_domain *domain, hint = hwirq % irq_virq_count; if (hint == 0) hint++; - virq = irq_alloc_desc_from(hint, 0); - if (!virq) - virq = irq_alloc_desc_from(1, 0); - if (!virq) { + irq = irq_alloc_desc_from(hint, 0); + if (irq <= 0) + irq = irq_alloc_desc_from(1, 0); + if (irq <= 0) { pr_debug("irq: -> virq allocation failed\n"); return 0; } - + virq = irq; if (irq_setup_virq(domain, virq, hwirq)) { if (domain->revmap_type != IRQ_DOMAIN_MAP_LEGACY) irq_free_desc(virq); -- 1.7.2.3 From robherring2@gmail.com Fri Apr 6 05:37:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 05:37:32 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:57921 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901346Ab2DFDhS (ORCPT ); Fri, 6 Apr 2012 05:37:18 +0200 Received: by obhx4 with SMTP id x4so3172556obh.36 for ; Thu, 05 Apr 2012 20:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=yXaelibPcftGTS+vcOBg9qlNwv/j4rEukrjrmUdp9qY=; b=KMakba/1z/r9jmnmP/ulShyFP4lbk6lCbcOBYoYxRgr8gFbOnMpUzTpUA3URiHN+0V BXA2b/oGswdZXC0lPta1YAq8qyn6XZANDaektSCDgML7eDvzqeONMbyDiReB4gkdBGc3 5N7wuqgzi8zyw33KquiyXRXs1Kg5KhWfkPow8jZlpieV2B1NuHSL0usoUQDO910Y7/Uv /OlDR3E3fPEv++GZ8C2vYuL9HRlk/CeBkNokEjKrFxkZLyry7B9ac8Ul+Re4Cfkk6WIf ofcCtdpSpPEu2cOW4YrrQ6gtdz6kujm+rYPfP25EN6s5AoGuZxFvqvt6PtFkOWuycoKm qYQQ== Received: by 10.60.32.210 with SMTP id l18mr7278615oei.1.1333683432252; Thu, 05 Apr 2012 20:37:12 -0700 (PDT) Received: from [192.168.1.103] (65-36-72-55.dyn.grandenetworks.net. [65.36.72.55]) by mx.google.com with ESMTPS id c6sm5005332oec.13.2012.04.05.20.37.09 (version=SSLv3 cipher=OTHER); Thu, 05 Apr 2012 20:37:10 -0700 (PDT) Message-ID: <4F7E64E4.3080509@gmail.com> Date: Thu, 05 Apr 2012 22:37:08 -0500 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120329 Thunderbird/11.0.1 MIME-Version: 1.0 To: David Daney CC: devicetree-discuss@lists.ozlabs.org, Grant Likely , Benjamin Herrenschmidt , Thomas Gleixner , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Subject: Re: [PATCH] irq/irq_domain: Quit ignoring error returns from irq_alloc_desc_from(). References: <1333669933-25267-1-git-send-email-ddaney.cavm@gmail.com> In-Reply-To: <1333669933-25267-1-git-send-email-ddaney.cavm@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32864 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2087 Lines: 64 On 04/05/2012 06:52 PM, David Daney wrote: > From: David Daney > > In commit 4bbdd45a (irq_domain/powerpc: eliminate irq_map; use > irq_alloc_desc() instead) code was added that ignores error returns > from irq_alloc_desc_from() by (silently) casting the return value to > unsigned. The negitive value error return now suddenly looks like a > valid irq number. > > Commits cc79ca69 (irq_domain: Move irq_domain code from powerpc to > kernel/irq) and 1bc04f2c (irq_domain: Add support for base irq and > hwirq in legacy mappings) move this code to its current location in > irqdomain.c > > The result of all of this is a null pointer dereference OOPS if one of > the error cases is hit. > > The fix: Don't cast away the negativeness of the return value and then > check for errors. > > Signed-off-by: David Daney > --- > kernel/irq/irqdomain.c | 11 ++++++----- > 1 files changed, 6 insertions(+), 5 deletions(-) > > diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c > index af48e59..9d3e3ae 100644 > --- a/kernel/irq/irqdomain.c > +++ b/kernel/irq/irqdomain.c > @@ -351,6 +351,7 @@ unsigned int irq_create_mapping(struct irq_domain *domain, > irq_hw_number_t hwirq) > { > unsigned int virq, hint; > + int irq; > > pr_debug("irq: irq_create_mapping(0x%p, 0x%lx)\n", domain, hwirq); > > @@ -380,14 +381,14 @@ unsigned int irq_create_mapping(struct irq_domain *domain, > hint = hwirq % irq_virq_count; > if (hint == 0) > hint++; > - virq = irq_alloc_desc_from(hint, 0); You are not looking at mainline. hint was removed in later versions, and the referenced commit ids don't exist. Rob > - if (!virq) > - virq = irq_alloc_desc_from(1, 0); > - if (!virq) { > + irq = irq_alloc_desc_from(hint, 0); > + if (irq <= 0) > + irq = irq_alloc_desc_from(1, 0); > + if (irq <= 0) { > pr_debug("irq: -> virq allocation failed\n"); > return 0; > } > - > + virq = irq; > if (irq_setup_virq(domain, virq, hwirq)) { > if (domain->revmap_type != IRQ_DOMAIN_MAP_LEGACY) > irq_free_desc(virq); From ddaney.cavm@gmail.com Fri Apr 6 18:37:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 18:38:12 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:37969 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904062Ab2DFQh6 (ORCPT ); Fri, 6 Apr 2012 18:37:58 +0200 Received: by obhx4 with SMTP id x4so3925357obh.36 for ; Fri, 06 Apr 2012 09:37:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=fCd88IgiXQPi34oq70KkR1e9JTRIpA0ReSNe6SAQndU=; b=j4/7TbQSSQXkc5OmuT4yPkRq1lSSaO8K6Ki2Qxs6e7mADJJmdbfdHZyBD1OFCJegH1 T8Cdz9U06gIILSwo/1+iFrsTvZF8r0/oE/KN2GXzPwpTz7vVefg1tORFxrkD9h6QPhp4 je7y82nA2SXiVgXe96LzSBcxWFJlBqS7ewJVoQQPHG4u6yt92KcnaLi3EF7MPM+re1D3 TD8b9fEq+De2JTAJOYrw2RBm87GRvnW89uCIUtvCj7rW5i2EZLRhuC7/BDJBNsQa1jFq 8tFtz4tFMniD1AIA8Cy0LuQ7KcHLGau5JcYhJ439XZ+elVVnoDxPGksRQfl0n9iHnNkA /Y3w== Received: by 10.182.13.8 with SMTP id d8mr10020453obc.36.1333730272204; Fri, 06 Apr 2012 09:37:52 -0700 (PDT) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id tx2sm7698911obb.8.2012.04.06.09.37.50 (version=SSLv3 cipher=OTHER); Fri, 06 Apr 2012 09:37:51 -0700 (PDT) Message-ID: <4F7F1BDD.4070205@gmail.com> Date: Fri, 06 Apr 2012 09:37:49 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Rob Herring , Grant Likely , Benjamin Herrenschmidt , Thomas Gleixner CC: David Daney , devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH] irq/irq_domain: Quit ignoring error returns from irq_alloc_desc_from(). References: <1333669933-25267-1-git-send-email-ddaney.cavm@gmail.com> <4F7E64E4.3080509@gmail.com> In-Reply-To: <4F7E64E4.3080509@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32865 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2868 Lines: 88 Rob, What the he*%? ... On 04/05/2012 08:37 PM, Rob Herring wrote: > On 04/05/2012 06:52 PM, David Daney wrote: >> From: David Daney >> >> In commit 4bbdd45a (irq_domain/powerpc: eliminate irq_map; use >> irq_alloc_desc() instead) code was added that ignores error returns >> from irq_alloc_desc_from() by (silently) casting the return value to >> unsigned. The negitive value error return now suddenly looks like a >> valid irq number. >> >> Commits cc79ca69 (irq_domain: Move irq_domain code from powerpc to >> kernel/irq) and 1bc04f2c (irq_domain: Add support for base irq and >> hwirq in legacy mappings) move this code to its current location in That would be commits: http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=4bbdd45afdae208a7c4ade89cf602f89a6397cff http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=cc79ca691c292e9fd44f589c7940b9654e22f2f6 http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=1bc04f2cf8c2a1feadbd994f50c40bb145bf2989 >> irqdomain.c >> >> The result of all of this is a null pointer dereference OOPS if one of >> the error cases is hit. >> >> The fix: Don't cast away the negativeness of the return value and then >> check for errors. >> >> Signed-off-by: David Daney >> --- >> kernel/irq/irqdomain.c | 11 ++++++----- >> 1 files changed, 6 insertions(+), 5 deletions(-) >> >> diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c >> index af48e59..9d3e3ae 100644 >> --- a/kernel/irq/irqdomain.c >> +++ b/kernel/irq/irqdomain.c >> @@ -351,6 +351,7 @@ unsigned int irq_create_mapping(struct irq_domain *domain, >> irq_hw_number_t hwirq) >> { >> unsigned int virq, hint; >> + int irq; >> >> pr_debug("irq: irq_create_mapping(0x%p, 0x%lx)\n", domain, hwirq); >> >> @@ -380,14 +381,14 @@ unsigned int irq_create_mapping(struct irq_domain *domain, >> hint = hwirq % irq_virq_count; >> if (hint == 0) >> hint++; >> - virq = irq_alloc_desc_from(hint, 0); > > You are not looking at mainline. hint was removed in later versions, and > the referenced commit ids don't exist. Please look at Linus' tree before making incorrect statements about whether or not code exists on the 'mainline' The current kernel.org tree contains the bug and will cause anything using irq_create_mapping() to crash in a semi-random manner. David Daney > > Rob > >> - if (!virq) >> - virq = irq_alloc_desc_from(1, 0); >> - if (!virq) { >> + irq = irq_alloc_desc_from(hint, 0); >> + if (irq<= 0) >> + irq = irq_alloc_desc_from(1, 0); >> + if (irq<= 0) { >> pr_debug("irq: -> virq allocation failed\n"); >> return 0; >> } >> - >> + virq = irq; >> if (irq_setup_virq(domain, virq, hwirq)) { >> if (domain->revmap_type != IRQ_DOMAIN_MAP_LEGACY) >> irq_free_desc(virq); > > From robherring2@gmail.com Fri Apr 6 19:32:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 19:32:52 +0200 (CEST) Received: from mail-gx0-f177.google.com ([209.85.161.177]:63589 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904078Ab2DFRci (ORCPT ); Fri, 6 Apr 2012 19:32:38 +0200 Received: by ggnk1 with SMTP id k1so1532941ggn.36 for ; Fri, 06 Apr 2012 10:32:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=bsHxJioAWywJxNCFc3GPyvtLmKVEHUWWz0zEPlgVyyg=; b=lDODrCSWWD3uBFKolMoBnlw0myFSO2f+pQcIu5GoCcf9pvm6sjedZvKvF3tWcVMtlH ob8y7mBdwQRDHVLvvYVv7FH3iYihUVZqwIbTefgJZwGIMHMp8S3GVfpZKVFfkzjEJQwl I3tNMopz78psZmk5wQ5r5txuTuE1KDiy4NYi5aXsUpBYzUUeWaVO3dOT9HK0fVxSCB1C YebQNIvXQu6/3BAnOcTqJ/pxKQSrNPeLN9klmizEV6adXtEurHUYcfviZXJm8tL/ANfj iRWyQI9h+IxfFHdd9l2CfRUk+yyxNNhLkDLfXJtNfIfV2+06e5dMwRX/NmrVWZAaUNWU OFGw== Received: by 10.60.18.198 with SMTP id y6mr10273129oed.38.1333733552668; Fri, 06 Apr 2012 10:32:32 -0700 (PDT) Received: from [10.10.10.90] ([173.226.190.126]) by mx.google.com with ESMTPS id t1sm3410071obl.5.2012.04.06.10.32.30 (version=SSLv3 cipher=OTHER); Fri, 06 Apr 2012 10:32:31 -0700 (PDT) Message-ID: <4F7F28AD.4050109@gmail.com> Date: Fri, 06 Apr 2012 12:32:29 -0500 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120329 Thunderbird/11.0.1 MIME-Version: 1.0 To: David Daney CC: Grant Likely , Benjamin Herrenschmidt , Thomas Gleixner , devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH] irq/irq_domain: Quit ignoring error returns from irq_alloc_desc_from(). References: <1333669933-25267-1-git-send-email-ddaney.cavm@gmail.com> <4F7E64E4.3080509@gmail.com> <4F7F1BDD.4070205@gmail.com> In-Reply-To: <4F7F1BDD.4070205@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32866 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3555 Lines: 109 On 04/06/2012 11:37 AM, David Daney wrote: > Rob, > > What the he*%? ... > > > On 04/05/2012 08:37 PM, Rob Herring wrote: >> On 04/05/2012 06:52 PM, David Daney wrote: >>> From: David Daney >>> >>> In commit 4bbdd45a (irq_domain/powerpc: eliminate irq_map; use >>> irq_alloc_desc() instead) code was added that ignores error returns >>> from irq_alloc_desc_from() by (silently) casting the return value to >>> unsigned. The negitive value error return now suddenly looks like a >>> valid irq number. >>> >>> Commits cc79ca69 (irq_domain: Move irq_domain code from powerpc to >>> kernel/irq) and 1bc04f2c (irq_domain: Add support for base irq and >>> hwirq in legacy mappings) move this code to its current location in > > That would be commits: > > http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=4bbdd45afdae208a7c4ade89cf602f89a6397cff > > http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=cc79ca691c292e9fd44f589c7940b9654e22f2f6 > > http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=1bc04f2cf8c2a1feadbd994f50c40bb145bf2989 > > >>> irqdomain.c >>> >>> The result of all of this is a null pointer dereference OOPS if one of >>> the error cases is hit. >>> >>> The fix: Don't cast away the negativeness of the return value and then >>> check for errors. >>> >>> Signed-off-by: David Daney >>> --- >>> kernel/irq/irqdomain.c | 11 ++++++----- >>> 1 files changed, 6 insertions(+), 5 deletions(-) >>> >>> diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c >>> index af48e59..9d3e3ae 100644 >>> --- a/kernel/irq/irqdomain.c >>> +++ b/kernel/irq/irqdomain.c >>> @@ -351,6 +351,7 @@ unsigned int irq_create_mapping(struct irq_domain >>> *domain, >>> irq_hw_number_t hwirq) >>> { >>> unsigned int virq, hint; >>> + int irq; >>> >>> pr_debug("irq: irq_create_mapping(0x%p, 0x%lx)\n", domain, hwirq); >>> >>> @@ -380,14 +381,14 @@ unsigned int irq_create_mapping(struct >>> irq_domain *domain, >>> hint = hwirq % irq_virq_count; >>> if (hint == 0) >>> hint++; >>> - virq = irq_alloc_desc_from(hint, 0); >> >> You are not looking at mainline. hint was removed in later versions, and >> the referenced commit ids don't exist. > > Please look at Linus' tree before making incorrect statements about > whether or not code exists on the 'mainline' > > The current kernel.org tree contains the bug and will cause anything > using irq_create_mapping() to crash in a semi-random manner. > Doh, evidently I need git training... Sorry about that. I was looking at a 3.2 branch even though I did check that. Plus I was remembering Grant removed some of the hint code in later versions of the irq domain code. My only comment is perhaps the pr_debug should be an error msg unless you get an error message already. Otherwise, FWIW: Acked-by: Rob Herring Off to find my brain, Rob > David Daney > >> >> Rob >> >>> - if (!virq) >>> - virq = irq_alloc_desc_from(1, 0); >>> - if (!virq) { >>> + irq = irq_alloc_desc_from(hint, 0); >>> + if (irq<= 0) >>> + irq = irq_alloc_desc_from(1, 0); >>> + if (irq<= 0) { >>> pr_debug("irq: -> virq allocation failed\n"); >>> return 0; >>> } >>> - >>> + virq = irq; >>> if (irq_setup_virq(domain, virq, hwirq)) { >>> if (domain->revmap_type != IRQ_DOMAIN_MAP_LEGACY) >>> irq_free_desc(virq); >> >> > From sjhill@mips.com Fri Apr 6 19:58:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 19:58:23 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:35098 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904078Ab2DFR6Q (ORCPT ); Fri, 6 Apr 2012 19:58:16 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGDQH-00045d-1Z; Fri, 06 Apr 2012 12:58:09 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , sjhill@realitydiluted.com Subject: [PATCH 1/5] MIPS: Add support for the 1074K core. Date: Fri, 6 Apr 2012 12:57:44 -0500 Message-Id: <1333735064-15672-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32867 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5234 Lines: 169 From: "Steven J. Hill" This patch adds support for detecting and using 1074K cores. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu.h | 3 ++- arch/mips/kernel/cpu-probe.c | 5 +++++ arch/mips/kernel/spram.c | 1 + arch/mips/mm/c-r4k.c | 28 +++++++++++++++++++++++++--- arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 7 +------ 6 files changed, 35 insertions(+), 10 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f9fa2a4..ddd8b4a 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -94,6 +94,7 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 +#define PRID_IMP_1074K 0x9a00 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -260,7 +261,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, - CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, + CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_1074K, /* * MIPS64 class processors diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5099201..cb1e2e9 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -207,6 +207,7 @@ void __init check_wait(void) cpu_wait = r4k_wait_irqoff; break; + case CPU_1074K: case CPU_74K: cpu_wait = r4k_wait; if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) @@ -835,6 +836,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; break; + case PRID_IMP_1074K: + c->cputype = CPU_1074K; + __cpu_name[cpu] = "MIPS 1074Kc"; + break; } spram_config(); diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 6af08d8..5781dbf 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -205,6 +205,7 @@ void __cpuinit spram_config(void) case CPU_24K: case CPU_34K: case CPU_74K: + case CPU_1074K: case CPU_1004K: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index bda8eb2..a08e75d 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) c->icache.linesz = 2 << lsize; else c->icache.linesz = lsize; - c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); c->icache.ways = 1 + ((config1 >> 16) & 7); icache_size = c->icache.sets * @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) c->dcache.linesz = 2 << lsize; else c->dcache.linesz= lsize; - c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); c->dcache.ways = 1 + ((config1 >> 7) & 7); dcache_size = c->dcache.sets * @@ -1051,9 +1051,30 @@ static void __cpuinit probe_pcache(void) case CPU_R14000: break; + case CPU_74K: + /* + * Early versions of the 74k do not update + * the cache tags on a vtag miss/ptag hit + * which can occur in the case of KSEG0/KUSEG aliases + * In this case it is better to treat the cache as always + * having aliases + */ + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) + c->dcache.flags |= MIPS_CACHE_VTAG; + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + goto bypass1074; + + case CPU_1074K: + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) { + c->dcache.flags |= MIPS_CACHE_VTAG; + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + } + /* fall through */ +bypass1074: + ; case CPU_24K: case CPU_34K: - case CPU_74K: case CPU_1004K: if ((read_c0_config7() & (1 << 16))) { /* effectively physically indexed dcache, @@ -1061,6 +1082,7 @@ static void __cpuinit probe_pcache(void) c->dcache.flags |= MIPS_CACHE_PINDEX; break; } + /* fall through */ default: if (c->dcache.waysize > PAGE_SIZE) c->dcache.flags |= MIPS_CACHE_ALIASES; diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index d1f2d4c..846faf7 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -83,6 +83,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_25KF: case CPU_34K: case CPU_1004K: + case CPU_1074K: case CPU_74K: case CPU_SB1: case CPU_SB1A: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..13487a9 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -330,16 +330,11 @@ static int __init mipsxx_init(void) break; case CPU_1004K: -#if 0 - /* FIXME: report as 34K for now */ - op_model_mipsxx_ops.cpu_type = "mips/1004K"; - break; -#endif - case CPU_34K: op_model_mipsxx_ops.cpu_type = "mips/34K"; break; + case CPU_1074K: case CPU_74K: op_model_mipsxx_ops.cpu_type = "mips/74K"; break; -- 1.7.9.6 From sjhill@mips.com Fri Apr 6 19:59:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 19:59:21 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:35100 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904081Ab2DFR7O (ORCPT ); Fri, 6 Apr 2012 19:59:14 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGDRE-00045p-5j; Fri, 06 Apr 2012 12:59:08 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , sjhill@realitydiluted.com Subject: [PATCH 2/5] MIPS: Clean-up GIC and vectored interrupts. Date: Fri, 6 Apr 2012 12:59:00 -0500 Message-Id: <1333735140-15719-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32868 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3109 Lines: 88 From: "Steven J. Hill" This change adds macros for routing of GIC interrupts for EIC and non-EIC hardware modes. Also added Malta GIC macros having to do with performance and timer interrupts. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/gic.h | 15 ++++++++++++++- arch/mips/include/asm/irq.h | 1 + arch/mips/include/asm/mips-boards/maltaint.h | 10 ++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 86548da..991b659 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -206,7 +206,7 @@ #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 #define GIC_VPE_EIC_SS(intr) \ - (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) + (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr)) #define GIC_VPE_EIC_VEC_BASE 0x0800 #define GIC_VPE_EIC_VEC(intr) \ @@ -330,6 +330,17 @@ struct gic_intr_map { #define GIC_FLAG_TRANSPARENT 0x02 }; +/* + * This is only used in EIC mode. This helps to figure out which + * shared interrupts we need to process when we get a vector interrupt. + */ +#define GIC_MAX_SHARED_INTR 0x5 +struct gic_shared_intr_map { + unsigned int num_shared_intr; + unsigned int intr_list[GIC_MAX_SHARED_INTR]; + unsigned int local_intr_mask; +}; + extern void gic_init(unsigned long gic_base_addr, unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, unsigned int intrmap_size, unsigned int irqbase); @@ -338,5 +349,7 @@ extern unsigned int gic_get_int(void); extern void gic_send_ipi(unsigned int intr); extern unsigned int plat_ipi_call_int_xlate(unsigned int); extern unsigned int plat_ipi_resched_int_xlate(unsigned int); +extern void gic_bind_eic_interrupt(int irq, int set); +extern unsigned int gic_get_timer_pending(void); #endif /* _ASM_GICREGS_H */ diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index fb698dc..78dbb8a 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq); * IE7. Since R2 their number has to be read from the c0_intctl register. */ #define CP0_LEGACY_COMPARE_IRQ 7 +#define CP0_LEGACY_PERFCNT_IRQ 7 extern int cp0_compare_irq; extern int cp0_compare_irq_shift; diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index d11aa02..5447d9f 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -86,6 +86,16 @@ #define GIC_CPU_INT4 4 /* . */ #define GIC_CPU_INT5 5 /* Core Interrupt 5 */ +/* MALTA GIC local interrupts */ +#define GIC_INT_TMR (GIC_CPU_INT5) +#define GIC_INT_PERFCTR (GIC_CPU_INT5) + +/* GIC constants */ +/* Add 2 to convert non-eic hw int # to eic vector # */ +#define GIC_CPU_TO_VEC_OFFSET (2) +/* If we map an intr to pin X, GIC will actually generate vector X+1 */ +#define GIC_PIN_TO_VEC_OFFSET (1) + #define GIC_EXT_INTR(x) x /* External Interrupts used for IPI */ -- 1.7.9.6 From sjhill@mips.com Fri Apr 6 19:59:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 19:59:52 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:35103 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904078Ab2DFR7a (ORCPT ); Fri, 6 Apr 2012 19:59:30 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGDRT-00045x-SZ; Fri, 06 Apr 2012 12:59:23 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , sjhill@realitydiluted.com Subject: [PATCH 3/5] MIPS: Updates to SMTC and SMVP support for threaded cores. Date: Fri, 6 Apr 2012 12:59:17 -0500 Message-Id: <1333735157-15758-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32869 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 44339 Lines: 1475 From: "Steven J. Hill" Changes for sharing interrupts between VPEs. Add support for APRP and loading a VPE with an ELF image. Change-Id: I56ffc0536c2c3814320521fb26aa65fa73b3b414 Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 34 +- arch/mips/include/asm/mips_mt.h | 1 + arch/mips/include/asm/topology.h | 3 + arch/mips/include/asm/vpe.h | 30 +- arch/mips/kernel/rtlx.c | 21 +- arch/mips/kernel/smp-mt.c | 39 +- arch/mips/kernel/syscall.c | 5 +- arch/mips/kernel/vpe.c | 844 ++++++++++++++++++++++++++++++++++---- 8 files changed, 857 insertions(+), 120 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index edbbae1..0c7fb5d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1862,14 +1862,14 @@ config MIPS_MT_SMP select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a VSMP but lately has been - marketesed into SMVP. - Virtual SMP uses the processor's VPEs to implement virtual - processors. In currently available configuration of the 34K processor - this allows for a dual processor. Both processors will share the same - primary caches; each will obtain the half of the TLB for it's own - exclusive use. For a layman this model can be described as similar to - what Intel calls Hyperthreading. + Virtual SMP uses the processor's VPEs to implement virtual + processors. In currently available configurations of the 34K + processor this allows for a dual processor. Both processors will + share the same primary caches and each will obtain the half of + the TLB for its own exclusive use. For a layman this model can + be described as similar to what Intel calls Hyperthreading. At + some point MIPS marketing decided to renamed to SMVP but the + renaming hasn't caught on as of yet. For further information see http://www.linux-mips.org/wiki/34K#VSMP @@ -1886,14 +1886,16 @@ config MIPS_MT_SMTC select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a SMTC or lately has been - marketesed into SMVP. - is presenting the available TC's of the core as processors to Linux. - On currently available 34K processors this means a Linux system will - see up to 5 processors. The implementation of the SMTC kernel differs - significantly from VSMP and cannot efficiently coexist in the same - kernel binary so the choice between VSMP and SMTC is a compile time - decision. + SMTC is presenting the available TCs of the core as processors to + Linux. On currently available 34K processors this means a Linux + system will see up to 5 processors. The implementation of the SMTC + kernel differs significantly from VSMP. It was found that SMTC cannot + efficiently coexist in the same kernel binary with other modes of + multiprocessor support, so enabling SMTC is a compile time decision. + The choice between VSMP and SMTC is a bit delicate as it is affected + by clockspeed, memory speed, the specific workload and other factors. + As such the choice should not be made on an evaluation board such as + the Malta but preferably on final target hardware. For further information see http://www.linux-mips.org/wiki/34K#SMTC diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h index ac79352..3177c83 100644 --- a/arch/mips/include/asm/mips_mt.h +++ b/arch/mips/include/asm/mips_mt.h @@ -19,6 +19,7 @@ extern unsigned long mt_fpemul_threshold; extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); extern void mips_mt_set_cpuoptions(void); +extern void cmp_send_ipi_single(int cpu, unsigned int action); struct class; extern struct class *mt_class; diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h index 259145e..709e78a 100644 --- a/arch/mips/include/asm/topology.h +++ b/arch/mips/include/asm/topology.h @@ -12,6 +12,9 @@ #ifdef CONFIG_SMP #define smt_capable() (smp_num_siblings > 1) +/* FIXME: cpu_sibling_map is not a per_cpu variable */ +/*#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) */ +#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu]) #endif #endif /* __ASM_TOPOLOGY_H */ diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index c6e1b96..e5e4033 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -26,12 +26,40 @@ struct vpe_notifications { struct list_head list; }; - +extern unsigned long physical_memsize; extern int vpe_notify(int index, struct vpe_notifications *notify); +extern void save_gp_address(unsigned int secbase, unsigned int rel); + +/* + * libc style I/O support hooks + */ extern void *vpe_get_shared(int index); extern int vpe_getuid(int index); extern int vpe_getgid(int index); extern char *vpe_getcwd(int index); +/* + * Kernel/Kernel message passing support hooks + */ + +extern void *vpe_get_shared_area(int index, int type); + +/* "Well-Known" Area Types */ + +#define VPE_SHARED_NULL 0 +#define VPE_SHARED_RESERVED -1 + +struct vpe_shared_area { + int type; + void *addr; +}; + +/* + * IRQ assignment and initialization hook for RP services. + */ + +int arch_get_xcpu_irq(void); + +int vpe_send_interrupt(int v, int i); #endif /* _ASM_VPE_H */ diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index b8c18dc..25278d0 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -57,12 +57,6 @@ static int sp_stopping; extern void *vpe_get_shared(int index); -static void rtlx_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); -} - - /* Interrupt handler may be called before rtlx_init has otherwise had a chance to run. */ @@ -483,7 +477,7 @@ static char register_chrdev_failed[] __initdata = static int __init rtlx_module_init(void) { struct device *dev; - int i, err; + int i, err, irq; if (!cpu_has_mipsmt) { printk("VPE loader: not a MIPS MT capable processor\n"); @@ -523,18 +517,17 @@ static int __init rtlx_module_init(void) notify.start = starting; notify.stop = stopping; vpe_notify(tclimit, ¬ify); - - if (cpu_has_vint) - set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); - else { + irq = arch_get_xcpu_irq(); + if (irq < 0) { pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); err = -ENODEV; goto out_chrdev; } - rtlx_irq.dev_id = rtlx; - setup_irq(rtlx_irq_num, &rtlx_irq); - + err = request_irq(irq, &rtlx_interrupt, IRQF_SHARED, + module_name, (void *)dev); + if (err) + goto out_chrdev; return 0; out_chrdev: diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ff17868..4f54cea 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -34,7 +34,9 @@ #include #include #include +#include +extern int gic_present; static void __init smvp_copy_vpe_config(void) { write_vpe_c0_status( @@ -111,12 +113,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) write_tc_c0_tchalt(TCHALT_H); } +static void mp_send_ipi_single(int cpu, unsigned int action) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (action) { + case SMP_CALL_FUNCTION: + gic_send_ipi(plat_ipi_call_int_xlate(cpu)); + break; + + case SMP_RESCHEDULE_YOURSELF: + gic_send_ipi(plat_ipi_resched_int_xlate(cpu)); + break; + } + + local_irq_restore(flags); +} + static void vsmp_send_ipi_single(int cpu, unsigned int action) { int i; unsigned long flags; int vpflags; + if (gic_present) { + mp_send_ipi_single(cpu, action); + return; + } local_irq_save(flags); vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ @@ -150,9 +175,8 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) static void __cpuinit vsmp_init_secondary(void) { - extern int gic_present; - - /* This is Malta specific: IPI,performance and timer interrupts */ + pr_debug("SMPMT: CPU%d: vsmp_init_secondary\n", smp_processor_id()); + /* This is Malta specific: IPI,performance and timer inetrrupts */ if (gic_present) change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 | STATUSF_IP7); @@ -163,6 +187,8 @@ static void __cpuinit vsmp_init_secondary(void) static void __cpuinit vsmp_smp_finish(void) { + pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id()); + /* CDFIXME: remove this? */ write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); @@ -177,6 +203,7 @@ static void __cpuinit vsmp_smp_finish(void) static void vsmp_cpus_done(void) { + pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id()); } /* @@ -190,6 +217,8 @@ static void vsmp_cpus_done(void) static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) { struct thread_info *gp = task_thread_info(idle); + pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n", + smp_processor_id(), cpu); dvpe(); set_c0_mvpcontrol(MVPCONTROL_VPC); @@ -231,6 +260,7 @@ static void __init vsmp_smp_setup(void) unsigned int mvpconf0, ntc, tc, ncpu = 0; unsigned int nvpe; + pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id()); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ if (cpu_has_fpu) @@ -260,6 +290,7 @@ static void __init vsmp_smp_setup(void) smvp_tc_init(tc, mvpconf0); ncpu = smvp_vpe_init(tc, mvpconf0, ncpu); } + cpu_present_map = cpu_possible_map; /* Release config state */ clear_c0_mvpcontrol(MVPCONTROL_VPC); @@ -271,6 +302,8 @@ static void __init vsmp_smp_setup(void) static void __init vsmp_prepare_cpus(unsigned int max_cpus) { + pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n", + smp_processor_id(), max_cpus); mips_mt_set_cpuoptions(); } diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index b08220c..bacd9bf 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -124,7 +124,7 @@ _sys_clone(nabi_no_regargs struct pt_regs regs) child_tidptr = (int __user *) regs.regs[8]; #endif return do_fork(clone_flags, newsp, ®s, 0, - parent_tidptr, child_tidptr); + parent_tidptr, child_tidptr); } /* @@ -264,11 +264,12 @@ save_static_function(sys_sysmips); static int __used noinline _sys_sysmips(nabi_no_regargs struct pt_regs regs) { - long cmd, arg1, arg2; + long cmd, arg1, arg2, arg3; cmd = regs.regs[4]; arg1 = regs.regs[5]; arg2 = regs.regs[6]; + arg3 = regs.regs[7]; switch (cmd) { case MIPS_ATOMIC_SET: diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index f6f9152..e8c99a4 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -73,17 +73,14 @@ static const int minor = 1; /* fixed for now */ static struct kspd_notifications kspd_events; static int kspd_events_reqd; #endif - -/* grab the likely amount of memory we will need. */ -#ifdef CONFIG_MIPS_VPE_LOADER_TOM -#define P_SIZE (2 * 1024 * 1024) -#else -/* add an overhead to the max kmalloc size for non-striped symbols/etc */ +/* + * Size of private kernel buffer for ELF headers and sections + */ #define P_SIZE (256 * 1024) -#endif - -extern unsigned long physical_memsize; +/* + * Size of private kernel buffer for ELF headers and sections + */ #define MAX_VPES 16 #define VPE_PATH_MAX 256 @@ -100,6 +97,16 @@ enum tc_state { TC_STATE_DYNAMIC }; +enum load_state { + LOAD_STATE_EHDR, + LOAD_STATE_PHDR, + LOAD_STATE_SHDR, + LOAD_STATE_PIMAGE, + LOAD_STATE_TRAILER, + LOAD_STATE_DONE, + LOAD_STATE_ERROR +}; + struct vpe { enum vpe_state state; @@ -107,10 +114,25 @@ struct vpe { int minor; /* elfloader stuff */ + unsigned long offset; /* File offset into input stream */ void *load_addr; - unsigned long len; + unsigned long copied; char *pbuffer; - unsigned long plen; + unsigned long pbsize; + /* Program loading state */ + enum load_state l_state; + Elf_Ehdr *l_ehdr; + struct elf_phdr *l_phdr; + unsigned int l_phlen; + Elf_Shdr *l_shdr; + unsigned int l_shlen; + int *l_phsort; /* Sorted index list of program headers */ + int l_segoff; /* Offset into current program segment */ + int l_cur_seg; /* Indirect index of segment currently being loaded */ + unsigned int l_progminad; + unsigned int l_progmaxad; + unsigned int l_trailer; + unsigned int uid, gid; char cwd[VPE_PATH_MAX]; @@ -122,9 +144,12 @@ struct vpe { /* The list of vpe's */ struct list_head list; - /* shared symbol address */ + /* legacy shared symbol address */ void *shared_ptr; + /* shared area descriptor array address */ + struct vpe_shared_area *shared_areas; + /* the list of who wants to know when something major happens */ struct list_head notify; @@ -146,13 +171,24 @@ struct { spinlock_t tc_list_lock; struct list_head tc_list; /* Thread contexts */ } vpecontrol = { - .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), + .vpe_list_lock = SPIN_LOCK_UNLOCKED, .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), - .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), + .tc_list_lock = SPIN_LOCK_UNLOCKED, .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) }; static void release_progmem(void *ptr); +/* + * Values and state associated with publishing shared memory areas + */ + +#define N_PUB_AREAS 4 + +static struct vpe_shared_area published_vpe_area[N_PUB_AREAS] = { + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0} }; /* get the vpe associated with this minor */ static struct vpe *get_vpe(int minor) @@ -175,7 +211,7 @@ static struct vpe *get_vpe(int minor) return res; } -/* get the vpe associated with this minor */ +/* get the tc associated with this minor */ static struct tc *get_tc(int index) { struct tc *res, *t; @@ -200,7 +236,8 @@ static struct vpe *alloc_vpe(int minor) if ((v = kzalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) return NULL; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct vpe), (unsigned int)v); INIT_LIST_HEAD(&v->tc); spin_lock(&vpecontrol.vpe_list_lock); list_add_tail(&v->list, &vpecontrol.vpe_list); @@ -219,7 +256,8 @@ static struct tc *alloc_tc(int index) if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) goto out; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct tc), (unsigned int)tc); INIT_LIST_HEAD(&tc->tc); tc->index = index; @@ -237,6 +275,11 @@ static void release_vpe(struct vpe *v) list_del(&v->list); if (v->load_addr) release_progmem(v); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v->l_phsort); + kfree(v->l_phsort); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v); kfree(v); } @@ -260,8 +303,88 @@ static void __maybe_unused dump_mtregs(void) val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); } +/* + * The original APRP prototype assumed a single, unshared IRQ for + * cross-VPE interrupts, used by the RTLX code. But M3P networking + * and other future functions may need to share an IRQ, particularly + * in 34K/Malta configurations without an external interrupt controller. + * All cross-VPE insterrupt users need to coordinate through shared + * functions here. + */ + +/* + * It would be nice if I could just have this initialized to zero, + * but the patchcheck police won't hear of it... + */ + +static int xvpe_vector_set; + +#define XVPE_INTR_OFFSET 0 + +static int xvpe_irq = MIPS_CPU_IRQ_BASE + XVPE_INTR_OFFSET; + +static void xvpe_dispatch(void) +{ + do_IRQ(xvpe_irq); +} + +/* Name here is generic, as m3pnet.c could in principle be used by non-MIPS */ +int arch_get_xcpu_irq() +{ + /* + * Some of this will ultimately become platform code, + * but for now, we're only targeting 34K/FPGA/Malta, + * and there's only one generic mechanism. + */ + if (!xvpe_vector_set) { + /* + * A more elaborate shared variable shouldn't be needed. + * Two initializations back-to-back should be harmless. + */ + if (cpu_has_vint) { + set_vi_handler(XVPE_INTR_OFFSET, xvpe_dispatch); + xvpe_vector_set = 1; + } else { + printk(KERN_ERR "APRP requires vectored interrupts\n"); + return -1; + } + } + + return xvpe_irq; +} +EXPORT_SYMBOL(arch_get_xcpu_irq); + +int vpe_send_interrupt(int vpe, int inter) +{ + unsigned long flags; + unsigned int vpeflags; + + local_irq_save(flags); + vpeflags = dvpe(); + + /* + * Initial version makes same simple-minded assumption + * as is implicit elsewhere in this module, that the + * only RP of interest is using the first non-Linux TC. + * We ignore the parameters provided by the caller! + */ + settc(tclimit); + /* + * In 34K/Malta, the only cross-VPE interrupts possible + * are done by setting SWINT bits in Cause, of which there + * are two. SMTC uses SW1 for a multiplexed class of IPIs, + * and this mechanism should be generalized to APRP and use + * the same protocol. Until that's implemented, send only + * SW0 here, regardless of requested type. + */ + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); + evpe(vpeflags); + local_irq_restore(flags); + return 1; +} +EXPORT_SYMBOL(vpe_send_interrupt); /* Find some VPE program space */ -static void *alloc_progmem(unsigned long len) +static void *alloc_progmem(void *requested, unsigned long len) { void *addr; @@ -271,10 +394,28 @@ static void *alloc_progmem(unsigned long len) * physically have, for example by passing a mem= boot argument. */ addr = pfn_to_kaddr(max_low_pfn); - memset(addr, 0, len); + if (requested != 0) { + if (requested >= addr) + addr = requested; + else + addr = 0; + } + if (addr != 0) + memset(addr, 0, len); + printk(KERN_DEBUG "pfn_to_kaddr returns %lu bytes of memory at %x\n", + len, (unsigned int)addr); #else - /* simple grab some mem for now */ - addr = kzalloc(len, GFP_KERNEL); + if (requested != 0) { + /* If we have a target in mind, grab a 2x slice and hope... */ + addr = kzalloc(len*2, GFP_KERNEL); + if ((requested >= addr) && (requested < (addr + len))) + addr = requested; + else + addr = 0; + } else { + /* simply grab some mem for now */ + addr = kzalloc(len, GFP_KERNEL); + } #endif return addr; @@ -446,6 +587,8 @@ static int apply_r_mips_hi16(struct module *me, uint32_t *location, * actual relocation. */ n = kmalloc(sizeof *n, GFP_KERNEL); + printk(KERN_DEBUG "Used kmalloc to allocate %d bytes at %x\n", + sizeof(struct mips_hi16), (unsigned int)n); if (!n) return -ENOMEM; @@ -503,6 +646,8 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, *l->addr = insn; next = l->next; + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)l); kfree(l); l = next; } @@ -596,7 +741,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs, return 0; } -static inline void save_gp_address(unsigned int secbase, unsigned int rel) +void save_gp_address(unsigned int secbase, unsigned int rel) { gp_addr = secbase + rel; gp_offs = gp_addr - (secbase & 0xffff0000); @@ -816,16 +961,41 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, struct module *mod) { Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; - unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); + unsigned int i, j, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); for (i = 1; i < n; i++) { - if (strcmp(strtab + sym[i].st_name, "__start") == 0) { - v->__start = sym[i].st_value; + if (strcmp(strtab + sym[i].st_name, "__start") == 0) + v->__start = sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) + v->shared_ptr = (void *)sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "_vpe_shared_areas") == 0) { + struct vpe_shared_area *psa + = (struct vpe_shared_area *)sym[i].st_value; + struct vpe_shared_area *tpsa; + v->shared_areas = psa; + printk(KERN_INFO"_vpe_shared_areas found, 0x%x\n", + (unsigned int)v->shared_areas); + /* + * Copy any "published" areas to the descriptor + */ + for (j = 0; j < N_PUB_AREAS; j++) { + if (published_vpe_area[j].type != VPE_SHARED_RESERVED) { + tpsa = psa; + while (tpsa->type != VPE_SHARED_NULL) { + if ((tpsa->type == VPE_SHARED_RESERVED) + || (tpsa->type == published_vpe_area[j].type)) { + tpsa->type = published_vpe_area[j].type; + tpsa->addr = published_vpe_area[j].addr; + break; + } + tpsa++; + } + } } + } - if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) { - v->shared_ptr = (void *)sym[i].st_value; - } } if ( (v->__start == 0) || (v->shared_ptr == NULL)) @@ -850,14 +1020,12 @@ static int vpe_elfload(struct vpe * v) memset(&mod, 0, sizeof(struct module)); strcpy(mod.name, "VPE loader"); - - hdr = (Elf_Ehdr *) v->pbuffer; - len = v->plen; + hdr = v->l_ehdr; + len = v->pbsize; /* Sanity checks against insmoding binaries or wrong arch, weird elf version */ - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0 - || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) + if ((hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) || !elf_check_arch(hdr) || hdr->e_shentsize != sizeof(*sechdrs)) { printk(KERN_WARNING @@ -869,9 +1037,8 @@ static int vpe_elfload(struct vpe * v) if (hdr->e_type == ET_REL) relocate = 1; - if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { - printk(KERN_ERR "VPE loader: program length %u truncated\n", - len); + if (len < v->l_phlen + v->l_shlen) { + printk(KERN_ERR "VPE loader: Headers exceed %u bytes\n", len); return -ENOEXEC; } @@ -905,9 +1072,13 @@ static int vpe_elfload(struct vpe * v) } } layout_sections(&mod, hdr, sechdrs, secstrings); + /* + * Non-relocatable loads should have already done their + * allocates, based on program header table. + */ } - v->load_addr = alloc_progmem(mod.core_size); + memset(v->load_addr, 0, mod.core_size); if (!v->load_addr) return -ENOMEM; @@ -960,19 +1131,10 @@ static int vpe_elfload(struct vpe * v) } } else { - struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); - - for (i = 0; i < hdr->e_phnum; i++) { - if (phdr->p_type == PT_LOAD) { - memcpy((void *)phdr->p_paddr, - (char *)hdr + phdr->p_offset, - phdr->p_filesz); - memset((void *)phdr->p_paddr + phdr->p_filesz, - 0, phdr->p_memsz - phdr->p_filesz); - } - phdr++; - } + /* + * Program image is already in memory. + */ for (i = 0; i < hdr->e_shnum; i++) { /* Internal symbols and strings. */ if (sechdrs[i].sh_type == SHT_SYMTAB) { @@ -989,7 +1151,7 @@ static int vpe_elfload(struct vpe * v) /* make sure it's physically written out */ flush_icache_range((unsigned long)v->load_addr, - (unsigned long)v->load_addr + v->len); + (unsigned long)v->load_addr + v->copied); if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { if (v->__start == 0) { @@ -1003,8 +1165,8 @@ static int vpe_elfload(struct vpe * v) "program does not contain vpe_shared symbol.\n" " Unable to use AMVP (AP/SP) facilities.\n"); } + pr_info("APRP VPE loader: elf loaded\n"); - printk(" elf loaded\n"); return 0; } @@ -1069,6 +1231,10 @@ static int vpe_open(struct inode *inode, struct file *filp) return -ENODEV; } + /* + * This treats the tclimit command line configuration input + * as a minor device indication, which is probably unwholesome. + */ if ((v = get_vpe(tclimit)) == NULL) { pr_warning("VPE loader: unable to get vpe\n"); @@ -1085,18 +1251,20 @@ static int vpe_open(struct inode *inode, struct file *filp) } release_progmem(v->load_addr); + kfree(v->l_phsort); cleanup_tc(get_tc(tclimit)); } /* this of-course trashes what was there before... */ v->pbuffer = vmalloc(P_SIZE); - if (!v->pbuffer) { - pr_warning("VPE loader: unable to allocate memory\n"); - return -ENOMEM; - } - v->plen = P_SIZE; v->load_addr = NULL; - v->len = 0; + v->copied = 0; + v->offset = 0; + v->l_state = LOAD_STATE_EHDR; + v->l_ehdr = NULL; + v->l_phdr = NULL; + v->l_phsort = NULL; + v->l_shdr = NULL; v->uid = filp->f_cred->fsuid; v->gid = filp->f_cred->fsgid; @@ -1115,6 +1283,7 @@ static int vpe_open(struct inode *inode, struct file *filp) printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret); v->shared_ptr = NULL; + v->shared_areas = NULL; v->__start = 0; return 0; @@ -1123,26 +1292,39 @@ static int vpe_open(struct inode *inode, struct file *filp) static int vpe_release(struct inode *inode, struct file *filp) { struct vpe *v; - Elf_Ehdr *hdr; int ret = 0; v = get_vpe(tclimit); if (v == NULL) return -ENODEV; + /* + * If image load had no errors, massage program/section tables + * to reflect movement of program/section data into VPE program + * memory. + */ + if (v->l_state != LOAD_STATE_DONE) { + printk(KERN_WARNING "VPE Release after incomplete load\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); + return -ENOEXEC; + } - hdr = (Elf_Ehdr *) v->pbuffer; - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) { - if (vpe_elfload(v) >= 0) { - vpe_run(v); - } else { - printk(KERN_WARNING "VPE loader: ELF load failed.\n"); - ret = -ENOEXEC; - } + if (vpe_elfload(v) >= 0) { + vpe_run(v); } else { - printk(KERN_WARNING "VPE loader: only elf files are supported\n"); + printk(KERN_WARNING "VPE loader: ELF load failed.\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); ret = -ENOEXEC; } + /* It's good to be able to run the SP and if it chokes have a look at the /dev/rt?. But if we reset the pointer to the shared struct we lose what has happened. So perhaps if garbage is sent to the vpe @@ -1151,17 +1333,68 @@ static int vpe_release(struct inode *inode, struct file *filp) if (ret < 0) v->shared_ptr = NULL; - vfree(v->pbuffer); - v->plen = 0; - + // cleanup any temp buffers + if (v->pbuffer) { + printk(KERN_DEBUG "Used vfree to free memory at %x\n", + (unsigned int)v->pbuffer); + vfree(v->pbuffer); + } + v->pbsize = 0; return ret; } +/* + * A sort of insertion sort to generate list of program header indices + * in order of their file offsets. + */ + +static void indexort(struct elf_phdr *phdr, int nph, int *index) +{ + int i, j, t; + unsigned int toff; + + /* Create initial mapping */ + for (i = 0; i < nph; i++) + index[i] = i; + /* Do the indexed insert sort */ + for (i = 1; i < nph; i++) { + j = i; + t = index[j]; + toff = phdr[t].p_offset; + while ((j > 0) && (phdr[index[j-1]].p_offset > toff)) { + index[j] = index[j-1]; + j--; + } + index[j] = t; + } +} + + +/* + * This function has to convert the ELF file image being sequentially + * streamed to the pseudo-device into the binary image, symbol, and + * string information, which the ELF format allows to be in some degree + * of disorder. + * + * The ELF header and, if present, program header table, are copied into + * a temporary buffer. Loadable program segments, if present, are copied + * into the RP program memory at the addresses specified by the program + * header table. + * + * Sections not specified by the program header table are loaded into + * memory following the program segments if they are "allocated", or + * into the temporary buffer if they are not. The section header + * table is loaded into the temporary buffer.??? + */ +#define CURPHDR (v->l_phdr[v->l_phsort[v->l_cur_seg]]) static ssize_t vpe_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos) { size_t ret = count; struct vpe *v; + int tocopy, uncopied; + int i; + unsigned int progmemlen; if (iminor(file->f_path.dentry->d_inode) != minor) return -ENODEV; @@ -1170,17 +1403,357 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, if (v == NULL) return -ENODEV; - if ((count + v->len) > v->plen) { - printk(KERN_WARNING - "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + if (v->pbuffer == NULL) { + printk(KERN_ERR "VPE loader: no buffer for program\n"); return -ENOMEM; } - count -= copy_from_user(v->pbuffer + v->len, buffer, count); - if (!count) - return -EFAULT; + while (count) { + switch (v->l_state) { + case LOAD_STATE_EHDR: + /* Loading ELF Header into scratch buffer */ + tocopy = min((unsigned long)count, + sizeof(Elf_Ehdr) - v->offset); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->copied == sizeof(Elf_Ehdr)) { + v->l_ehdr = (Elf_Ehdr *)v->pbuffer; + if (memcmp(v->l_ehdr->e_ident, ELFMAG, 4) != 0) { + printk(KERN_WARNING "VPE loader: %s\n", + "non-ELF file image"); + ret = -ENOEXEC; + v->l_state = LOAD_STATE_ERROR; + break; + } + if (v->l_ehdr->e_phoff != 0) { + v->l_phdr = (struct elf_phdr *) + (v->pbuffer + v->l_ehdr->e_phoff); + v->l_phlen = v->l_ehdr->e_phentsize + * v->l_ehdr->e_phnum; + /* Check against buffer overflow */ + if ((v->copied + v->l_phlen) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf program header table size too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_PHDR; + /* + * Program headers generally indicate + * linked executable with possibly + * valid entry point. + */ + v->__start = v->l_ehdr->e_entry; + } else if (v->l_ehdr->e_shoff != 0) { + /* + * No program headers, but a section + * header table. A relocatable binary. + * We need to load the works into the + * kernel temp buffer to compute the + * RP program image. That limits our + * binary size, but at least we're no + * worse off than the original APRP + * prototype. + */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big.\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + } else { + /* + * If neither program nor section tables, + * we don't know what to do. + */ + v->l_state = LOAD_STATE_ERROR; + return -ENOEXEC; + } + } + break; + case LOAD_STATE_PHDR: + /* Loading Program Headers into scratch */ + tocopy = min((unsigned long)count, + v->l_ehdr->e_phoff + v->l_phlen - v->copied); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + + if (v->copied == v->l_ehdr->e_phoff + v->l_phlen) { + /* + * It's legal for the program headers to be + * out of order with respect to the file layout. + * Generate a list of indices, sorted by file + * offset. + */ + v->l_phsort = kmalloc(v->l_ehdr->e_phnum + * sizeof(int), GFP_KERNEL); + printk(KERN_DEBUG + "Used kmalloc to allocate %d bytes of memory at %x\n", + v->l_ehdr->e_phnum*sizeof(int), + (unsigned int)v->l_phsort); + if (!v->l_phsort) + return -ENOMEM; /* Preposterous, but... */ + indexort(v->l_phdr, v->l_ehdr->e_phnum, + v->l_phsort); + + v->l_progminad = (unsigned int)-1; + v->l_progmaxad = 0; + progmemlen = 0; + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + /* Unstripped .reginfo sections are bad */ + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "User-mode p_vaddr, ", + "skipping program segment,"); + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "strip .reginfo from binary ", + "if necessary."); + continue; + } + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < v->l_progminad) + v->l_progminad = + v->l_phdr[v->l_phsort[i]].p_vaddr; + if ((v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz) + > v->l_progmaxad) + v->l_progmaxad = + v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz; + } + } + printk(KERN_INFO "APRP RP program 0x%x to 0x%x\n", + v->l_progminad, v->l_progmaxad); + /* + * Do a simple sanity check of the memory being + * allocated. Abort if greater than an arbitrary + * value of 32MB + */ + if (v->l_progmaxad - v->l_progminad > + 32*1024*1024) { + printk(KERN_WARNING + "RP program failed to allocate %d kbytes - limit is 32,768 KB\n", + (v->l_progmaxad - v->l_progminad)/1024); + return -ENOMEM; + } + + v->load_addr = alloc_progmem((void *)v->l_progminad, + v->l_progmaxad - v->l_progminad); + if (!v->load_addr) + return -ENOMEM; + if ((unsigned int)v->load_addr + > v->l_progminad) { + release_progmem(v->load_addr); + return -ENOMEM; + } + /* Find first segment with loadable content */ + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + if (i == v->l_ehdr->e_phnum) { + /* No loadable program segment? Bogus file. */ + printk(KERN_WARNING "Bad ELF file for APRP\n"); + return -ENOEXEC; + } + v->l_segoff = 0; + v->l_state = LOAD_STATE_PIMAGE; + } + break; + case LOAD_STATE_PIMAGE: + /* + * Skip through input stream until + * first program segment. Would be + * better to have loaded up to here + * into the temp buffer, but for now + * we simply rule out "interesting" + * sections prior to the last program + * segment in an executable file. + */ + if (v->offset < CURPHDR.p_offset) { + uncopied = CURPHDR.p_offset - v->offset; + if (uncopied > count) + uncopied = count; + count -= uncopied; + buffer += uncopied; + v->offset += uncopied; + /* Go back through the "while" */ + break; + } + /* + * Having dispensed with any unlikely fluff, + * copy from user I/O buffer to program segment. + */ + tocopy = min(count, CURPHDR.p_filesz - v->l_segoff); + + /* Loading image into RP memory */ + uncopied = copy_from_user((char *)CURPHDR.p_vaddr + + v->l_segoff, buffer, tocopy); + count -= tocopy - uncopied; + v->offset += tocopy - uncopied; + v->l_segoff += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->l_segoff >= CURPHDR.p_filesz) { + /* Finished current segment load */ + /* Zero out non-file-sourced image */ + uncopied = CURPHDR.p_memsz - CURPHDR.p_filesz; + if (uncopied > 0) + memset((char *)CURPHDR.p_vaddr + v->l_segoff, + 0, uncopied); + /* Advance to next segment */ + for (i = v->l_cur_seg + 1; + i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + /* If none left, prepare to load section headers */ + if (i == v->l_ehdr->e_phnum) { + if (v->l_ehdr->e_shoff != 0) { + /* Copy to where we left off in temp buffer */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + break; + } + } else { + /* reset offset for new program segment */ + v->l_segoff = 0; + } + } + break; + case LOAD_STATE_SHDR: + /* + * Read stream into private buffer up + * through and including the section header + * table. + */ - v->len += count; + tocopy = min((unsigned long)count, + v->l_ehdr->e_shoff + v->l_shlen - v->offset); + if (tocopy) { + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + /* Finished? */ + if (v->offset == v->l_ehdr->e_shoff + v->l_shlen) { + unsigned int offset_delta = v->offset - v->copied; + + v->l_shdr = (Elf_Shdr *)(v->pbuffer + + v->l_ehdr->e_shoff - offset_delta); + /* + * Check for sections after the section table, + * which for gcc MIPS binaries includes + * the symbol table. Do any other processing + * that requires value within stream, and + * normalize offsets to be relative to + * the header-only layout of temp buffer. + */ + + /* Assume no trailer until we detect one */ + v->l_trailer = 0; + v->l_state = LOAD_STATE_DONE; + for (i = 0; i < v->l_ehdr->e_shnum; i++) { + if (v->l_shdr[i].sh_offset + > v->l_ehdr->e_shoff) { + v->l_state = LOAD_STATE_TRAILER; + /* Track trailing data length */ + if (v->l_trailer + < (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen)) + v->l_trailer = + (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen); + } + /* Adjust section offset if necessary */ + v->l_shdr[i].sh_offset -= offset_delta; + } + if ((v->copied + v->l_trailer) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + + /* Fix up offsets in ELF header */ + v->l_ehdr->e_shoff = (unsigned int)v->l_shdr + - (unsigned int)v->pbuffer; + } + break; + case LOAD_STATE_TRAILER: + /* + * Symbol and string tables follow section headers + * in gcc binaries for MIPS. Copy into temp buffer. + */ + if (v->l_trailer) { + tocopy = min(count, v->l_trailer); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->l_trailer -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + if (!v->l_trailer) + v->l_state = LOAD_STATE_DONE; + break; + case LOAD_STATE_DONE: + if (count) + count = 0; + break; + case LOAD_STATE_ERROR: + default: + return -EINVAL; + } + } return ret; } @@ -1216,7 +1789,9 @@ int vpe_start(vpe_handle vpe, unsigned long start) { struct vpe *v = vpe; - v->__start = start; + /* Null start address means use value from ELF file */ + if (start) + v->__start = start; return vpe_run(v); } @@ -1341,6 +1916,99 @@ char *vpe_getcwd(int index) EXPORT_SYMBOL(vpe_getcwd); +/* + * RP applications may contain a _vpe_shared_area descriptor + * array to allow for data sharing with Linux kernel functions + * that's slightly more abstracted and extensible than the + * fixed binding used by the rtlx support. Indeed, the rtlx + * support should ideally be converted to use the generic + * shared area descriptor scheme at some point. + * + * mips_get_vpe_shared_area() can be used by AP kernel + * modules to get an area pointer of a given type, if + * it exists. + * + * mips_publish_vpe_area() is used by AP kernel modules + * to share kseg0 kernel memory with the RP. It maintains + * a private table, so that publishing can be done before + * the RP program is launched. Making this table dynamically + * allocated and extensible would be good scalable OS design. + * however, until there's more than one user of the mechanism, + * it should be an acceptable simplification to allow a static + * maximum of 4 published areas. + */ + +void *mips_get_vpe_shared_area(int index, int type) +{ + struct vpe *v; + struct vpe_shared_area *vsa; + + v = get_vpe(index); + if (v == NULL) + return NULL; + + if (v->shared_areas == NULL) + return NULL; + + vsa = v->shared_areas; + + while (vsa->type != VPE_SHARED_NULL) { + if (vsa->type == type) + return vsa->addr; + else + vsa++; + } + /* Fell through without finding type */ + + return NULL; +} +EXPORT_SYMBOL(mips_get_vpe_shared_area); + +int mips_publish_vpe_area(int type, void *ptr) +{ + int i; + int retval = 0; + struct vpe *v; + unsigned long flags; + unsigned int vpflags; + + printk(KERN_INFO "mips_publish_vpe_area(0x%x, 0x%x)\n", type, (int)ptr); + if ((unsigned int)ptr >= KSEG2) { + printk(KERN_ERR "VPE area pubish of invalid address 0x%x\n", + (int)ptr); + return 0; + } + for (i = 0; i < N_PUB_AREAS; i++) { + if (published_vpe_area[i].type == VPE_SHARED_RESERVED) { + published_vpe_area[i].type = type; + published_vpe_area[i].addr = ptr; + retval = type; + break; + } + } + /* + * If we've already got a VPE up and running, try to + * update the shared descriptor with the new data. + */ + list_for_each_entry(v, &vpecontrol.vpe_list, list) { + if (v->shared_areas != NULL) { + local_irq_save(flags); + vpflags = dvpe(); + for (i = 0; v->shared_areas[i].type != VPE_SHARED_NULL; i++) { + if ((v->shared_areas[i].type == type) + || (v->shared_areas[i].type == VPE_SHARED_RESERVED)) { + v->shared_areas[i].type = type; + v->shared_areas[i].addr = ptr; + } + } + evpe(vpflags); + local_irq_restore(flags); + } + } + return retval; +} +EXPORT_SYMBOL(mips_publish_vpe_area); + #ifdef CONFIG_MIPS_APSP_KSPD static void kspd_sp_exit( int sp_id) { @@ -1359,6 +2027,7 @@ static ssize_t store_kill(struct device *dev, struct device_attribute *attr, } release_progmem(vpe->load_addr); + kfree(vpe->l_phsort); cleanup_tc(get_tc(tclimit)); vpe_stop(vpe); vpe_free(vpe); @@ -1404,6 +2073,8 @@ static struct device_attribute vpe_class_attributes[] = { static void vpe_device_release(struct device *cd) { + printk(KERN_DEBUG "Using kfree to free vpe class device at %x\n", + (unsigned int)cd); kfree(cd); } @@ -1430,19 +2101,24 @@ static int __init vpe_module_init(void) } if (vpelimit == 0) { - printk(KERN_WARNING "No VPEs reserved for AP/SP, not " - "initializing VPE loader.\nPass maxvpes= argument as " - "kernel argument\n"); - +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) + printk(KERN_WARNING "No VPEs reserved for VPE loader.\n" + "Pass maxvpes= argument as kernel argument\n"); return -ENODEV; +#else + vpelimit = 1; +#endif } if (tclimit == 0) { +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) printk(KERN_WARNING "No TCs reserved for AP/SP, not " "initializing VPE loader.\nPass maxtcs= argument as " "kernel argument\n"); - return -ENODEV; +#else + tclimit = 1; +#endif } major = register_chrdev(0, module_name, &vpe_fops); @@ -1456,7 +2132,7 @@ static int __init vpe_module_init(void) printk(KERN_ERR "vpe_class registration failed\n"); goto out_chrdev; } - + xvpe_vector_set = 0; device_initialize(&vpe_device); vpe_device.class = &vpe_class, vpe_device.parent = NULL, -- 1.7.9.6 From sjhill@mips.com Fri Apr 6 19:59:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 20:00:17 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:35104 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904082Ab2DFR7z (ORCPT ); Fri, 6 Apr 2012 19:59:55 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGDRt-000468-0W; Fri, 06 Apr 2012 12:59:49 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , sjhill@realitydiluted.com Subject: [PATCH 4/5] MIPS: Malta PCI changes for PCI 2.1 compatibility and conflicts. Date: Fri, 6 Apr 2012 12:59:43 -0500 Message-Id: <1333735183-15796-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32870 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1801 Lines: 50 From: "Steven J. Hill" Turns on PCI 2.1 compatibility for the Malta platform for the PIIX4 controller. Change start address to avoid conflicts with the ACPI and SMB devices. Signed-off-by: Steven J. Hill --- arch/mips/mti-malta/malta-pci.c | 5 +++-- arch/mips/mti-malta/malta-setup.c | 11 +++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index bf80921..afeb619 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -241,8 +241,9 @@ void __init mips_pcibios_init(void) return; } - if (controller->io_resource->start < 0x00001000UL) /* FIXME */ - controller->io_resource->start = 0x00001000UL; + /* Change start address to avoid conflicts with ACPI and SMB devices */ + if (controller->io_resource->start < 0x00002000UL) /* FIXME */ + controller->io_resource->start = 0x00002000UL; iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index b7f37d4..5f7d113 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -222,3 +222,14 @@ void __init plat_mem_setup(void) board_be_init = malta_be_init; board_be_handler = malta_be_handler; } +/* Enable PCI 2.1 compatibility in PIIX4 */ +static void __init quirk_dlcsetup(struct pci_dev *dev) +{ + u8 odlc, ndlc; + (void) pci_read_config_byte(dev, 0x82, &odlc); + /* Enable passive releases and delayed transaction */ + ndlc = odlc | 7; + (void) pci_write_config_byte(dev, 0x82, ndlc); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + quirk_dlcsetup); -- 1.7.9.6 From sjhill@mips.com Fri Apr 6 20:00:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 20:00:41 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:35107 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904078Ab2DFSAK (ORCPT ); Fri, 6 Apr 2012 20:00:10 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGDS8-00046H-7i; Fri, 06 Apr 2012 13:00:04 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , sjhill@realitydiluted.com Subject: [PATCH 5/5] MIPS: Add option to disable software I/O coherency. Date: Fri, 6 Apr 2012 12:59:59 -0500 Message-Id: <1333735199-15835-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32871 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7577 Lines: 259 From: "Steven J. Hill" Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mach-generic/dma-coherence.h | 4 +- arch/mips/mm/c-r4k.c | 21 +--- arch/mips/mm/dma-default.c | 8 +- arch/mips/mti-malta/malta-memory.c | 2 +- arch/mips/mti-malta/malta-setup.c | 102 ++++++++++++++++++++ 5 files changed, 117 insertions(+), 20 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177..9f1cd31 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -63,7 +63,9 @@ static inline int plat_device_is_coherent(struct device *dev) return 1; #endif #ifdef CONFIG_DMA_NONCOHERENT - return 0; + extern int coherentio; + + return coherentio; #endif } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a08e75d..efcf385 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1393,26 +1393,13 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; - -static int __init setcoherentio(char *str) -{ - coherentio = 1; - - return 1; -} - -__setup("coherentio", setcoherentio); -#endif - void __cpuinit r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); extern char __weak except_vec2_generic; extern char __weak except_vec2_sb1; + extern int coherentio; struct cpuinfo_mips *c = ¤t_cpu_data; switch (c->cputype) { @@ -1483,8 +1470,10 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* We want to run CMP kernels on core(s) with and without coherent caches */ + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 4608491..669995a 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -100,6 +100,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); static void *mips_dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t * dma_handle, gfp_t gfp) { + extern int hw_coherentio; void *ret; if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) @@ -115,7 +116,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, if (!plat_device_is_coherent(dev)) { dma_cache_wback_inv((unsigned long) ret, size); - ret = UNCAC_ADDR(ret); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } } @@ -134,6 +136,7 @@ EXPORT_SYMBOL(dma_free_noncoherent); static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { + extern int hw_coherentio; unsigned long addr = (unsigned long) vaddr; int order = get_order(size); @@ -143,7 +146,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) - addr = CAC_ADDR(addr); + if (!hw_coherentio) + addr = CAC_ADDR(addr); free_pages(addr, get_order(size)); } diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index a96d281..d57a233 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -158,7 +158,7 @@ void __init prom_meminit(void) size = p->size; add_memory_region(base, size, type); - p++; + p++; } } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 5f7d113..618f503 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -32,6 +32,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -105,6 +106,105 @@ static void __init fd_activate(void) } #endif +int coherentio = -1; /* no DMA cache coherency (may be set by user) */ +int hw_coherentio; /* init to 0 => no HW DMA cache coherency (reflects real HW) */ +static int __init setcoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); + return 1; +} +__setup("coherentio", setcoherentio); + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 1; +} +__setup("nocoherentio", setnocoherentio); + +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(prom_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + hw_coherentio = supported; + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -207,6 +307,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif -- 1.7.9.6 From sjhill@mips.com Fri Apr 6 20:03:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 20:03:58 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:35115 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904085Ab2DFSDs (ORCPT ); Fri, 6 Apr 2012 20:03:48 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGDVd-00046i-0a; Fri, 06 Apr 2012 13:03:41 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , sjhill@realitydiluted.com Subject: [PATCH 3/5] MIPS: Updates to SMTC and SMVP support for threaded cores. Date: Fri, 6 Apr 2012 13:03:23 -0500 Message-Id: <1333735403-15881-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32872 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 44286 Lines: 1474 From: "Steven J. Hill" Changes for sharing interrupts between VPEs. Add support for APRP and loading a VPE with an ELF image. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 34 +- arch/mips/include/asm/mips_mt.h | 1 + arch/mips/include/asm/topology.h | 3 + arch/mips/include/asm/vpe.h | 30 +- arch/mips/kernel/rtlx.c | 21 +- arch/mips/kernel/smp-mt.c | 39 +- arch/mips/kernel/syscall.c | 5 +- arch/mips/kernel/vpe.c | 844 ++++++++++++++++++++++++++++++++++---- 8 files changed, 857 insertions(+), 120 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index edbbae1..0c7fb5d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1862,14 +1862,14 @@ config MIPS_MT_SMP select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a VSMP but lately has been - marketesed into SMVP. - Virtual SMP uses the processor's VPEs to implement virtual - processors. In currently available configuration of the 34K processor - this allows for a dual processor. Both processors will share the same - primary caches; each will obtain the half of the TLB for it's own - exclusive use. For a layman this model can be described as similar to - what Intel calls Hyperthreading. + Virtual SMP uses the processor's VPEs to implement virtual + processors. In currently available configurations of the 34K + processor this allows for a dual processor. Both processors will + share the same primary caches and each will obtain the half of + the TLB for its own exclusive use. For a layman this model can + be described as similar to what Intel calls Hyperthreading. At + some point MIPS marketing decided to renamed to SMVP but the + renaming hasn't caught on as of yet. For further information see http://www.linux-mips.org/wiki/34K#VSMP @@ -1886,14 +1886,16 @@ config MIPS_MT_SMTC select SYS_SUPPORTS_SMP select SMP_UP help - This is a kernel model which is known a SMTC or lately has been - marketesed into SMVP. - is presenting the available TC's of the core as processors to Linux. - On currently available 34K processors this means a Linux system will - see up to 5 processors. The implementation of the SMTC kernel differs - significantly from VSMP and cannot efficiently coexist in the same - kernel binary so the choice between VSMP and SMTC is a compile time - decision. + SMTC is presenting the available TCs of the core as processors to + Linux. On currently available 34K processors this means a Linux + system will see up to 5 processors. The implementation of the SMTC + kernel differs significantly from VSMP. It was found that SMTC cannot + efficiently coexist in the same kernel binary with other modes of + multiprocessor support, so enabling SMTC is a compile time decision. + The choice between VSMP and SMTC is a bit delicate as it is affected + by clockspeed, memory speed, the specific workload and other factors. + As such the choice should not be made on an evaluation board such as + the Malta but preferably on final target hardware. For further information see http://www.linux-mips.org/wiki/34K#SMTC diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h index ac79352..3177c83 100644 --- a/arch/mips/include/asm/mips_mt.h +++ b/arch/mips/include/asm/mips_mt.h @@ -19,6 +19,7 @@ extern unsigned long mt_fpemul_threshold; extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); extern void mips_mt_set_cpuoptions(void); +extern void cmp_send_ipi_single(int cpu, unsigned int action); struct class; extern struct class *mt_class; diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h index 259145e..709e78a 100644 --- a/arch/mips/include/asm/topology.h +++ b/arch/mips/include/asm/topology.h @@ -12,6 +12,9 @@ #ifdef CONFIG_SMP #define smt_capable() (smp_num_siblings > 1) +/* FIXME: cpu_sibling_map is not a per_cpu variable */ +/*#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) */ +#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu]) #endif #endif /* __ASM_TOPOLOGY_H */ diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index c6e1b96..e5e4033 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -26,12 +26,40 @@ struct vpe_notifications { struct list_head list; }; - +extern unsigned long physical_memsize; extern int vpe_notify(int index, struct vpe_notifications *notify); +extern void save_gp_address(unsigned int secbase, unsigned int rel); + +/* + * libc style I/O support hooks + */ extern void *vpe_get_shared(int index); extern int vpe_getuid(int index); extern int vpe_getgid(int index); extern char *vpe_getcwd(int index); +/* + * Kernel/Kernel message passing support hooks + */ + +extern void *vpe_get_shared_area(int index, int type); + +/* "Well-Known" Area Types */ + +#define VPE_SHARED_NULL 0 +#define VPE_SHARED_RESERVED -1 + +struct vpe_shared_area { + int type; + void *addr; +}; + +/* + * IRQ assignment and initialization hook for RP services. + */ + +int arch_get_xcpu_irq(void); + +int vpe_send_interrupt(int v, int i); #endif /* _ASM_VPE_H */ diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index b8c18dc..25278d0 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -57,12 +57,6 @@ static int sp_stopping; extern void *vpe_get_shared(int index); -static void rtlx_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); -} - - /* Interrupt handler may be called before rtlx_init has otherwise had a chance to run. */ @@ -483,7 +477,7 @@ static char register_chrdev_failed[] __initdata = static int __init rtlx_module_init(void) { struct device *dev; - int i, err; + int i, err, irq; if (!cpu_has_mipsmt) { printk("VPE loader: not a MIPS MT capable processor\n"); @@ -523,18 +517,17 @@ static int __init rtlx_module_init(void) notify.start = starting; notify.stop = stopping; vpe_notify(tclimit, ¬ify); - - if (cpu_has_vint) - set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); - else { + irq = arch_get_xcpu_irq(); + if (irq < 0) { pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); err = -ENODEV; goto out_chrdev; } - rtlx_irq.dev_id = rtlx; - setup_irq(rtlx_irq_num, &rtlx_irq); - + err = request_irq(irq, &rtlx_interrupt, IRQF_SHARED, + module_name, (void *)dev); + if (err) + goto out_chrdev; return 0; out_chrdev: diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ff17868..4f54cea 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -34,7 +34,9 @@ #include #include #include +#include +extern int gic_present; static void __init smvp_copy_vpe_config(void) { write_vpe_c0_status( @@ -111,12 +113,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) write_tc_c0_tchalt(TCHALT_H); } +static void mp_send_ipi_single(int cpu, unsigned int action) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (action) { + case SMP_CALL_FUNCTION: + gic_send_ipi(plat_ipi_call_int_xlate(cpu)); + break; + + case SMP_RESCHEDULE_YOURSELF: + gic_send_ipi(plat_ipi_resched_int_xlate(cpu)); + break; + } + + local_irq_restore(flags); +} + static void vsmp_send_ipi_single(int cpu, unsigned int action) { int i; unsigned long flags; int vpflags; + if (gic_present) { + mp_send_ipi_single(cpu, action); + return; + } local_irq_save(flags); vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ @@ -150,9 +175,8 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) static void __cpuinit vsmp_init_secondary(void) { - extern int gic_present; - - /* This is Malta specific: IPI,performance and timer interrupts */ + pr_debug("SMPMT: CPU%d: vsmp_init_secondary\n", smp_processor_id()); + /* This is Malta specific: IPI,performance and timer inetrrupts */ if (gic_present) change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 | STATUSF_IP7); @@ -163,6 +187,8 @@ static void __cpuinit vsmp_init_secondary(void) static void __cpuinit vsmp_smp_finish(void) { + pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id()); + /* CDFIXME: remove this? */ write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); @@ -177,6 +203,7 @@ static void __cpuinit vsmp_smp_finish(void) static void vsmp_cpus_done(void) { + pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id()); } /* @@ -190,6 +217,8 @@ static void vsmp_cpus_done(void) static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) { struct thread_info *gp = task_thread_info(idle); + pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n", + smp_processor_id(), cpu); dvpe(); set_c0_mvpcontrol(MVPCONTROL_VPC); @@ -231,6 +260,7 @@ static void __init vsmp_smp_setup(void) unsigned int mvpconf0, ntc, tc, ncpu = 0; unsigned int nvpe; + pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id()); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ if (cpu_has_fpu) @@ -260,6 +290,7 @@ static void __init vsmp_smp_setup(void) smvp_tc_init(tc, mvpconf0); ncpu = smvp_vpe_init(tc, mvpconf0, ncpu); } + cpu_present_map = cpu_possible_map; /* Release config state */ clear_c0_mvpcontrol(MVPCONTROL_VPC); @@ -271,6 +302,8 @@ static void __init vsmp_smp_setup(void) static void __init vsmp_prepare_cpus(unsigned int max_cpus) { + pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n", + smp_processor_id(), max_cpus); mips_mt_set_cpuoptions(); } diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index b08220c..bacd9bf 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -124,7 +124,7 @@ _sys_clone(nabi_no_regargs struct pt_regs regs) child_tidptr = (int __user *) regs.regs[8]; #endif return do_fork(clone_flags, newsp, ®s, 0, - parent_tidptr, child_tidptr); + parent_tidptr, child_tidptr); } /* @@ -264,11 +264,12 @@ save_static_function(sys_sysmips); static int __used noinline _sys_sysmips(nabi_no_regargs struct pt_regs regs) { - long cmd, arg1, arg2; + long cmd, arg1, arg2, arg3; cmd = regs.regs[4]; arg1 = regs.regs[5]; arg2 = regs.regs[6]; + arg3 = regs.regs[7]; switch (cmd) { case MIPS_ATOMIC_SET: diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index f6f9152..e8c99a4 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -73,17 +73,14 @@ static const int minor = 1; /* fixed for now */ static struct kspd_notifications kspd_events; static int kspd_events_reqd; #endif - -/* grab the likely amount of memory we will need. */ -#ifdef CONFIG_MIPS_VPE_LOADER_TOM -#define P_SIZE (2 * 1024 * 1024) -#else -/* add an overhead to the max kmalloc size for non-striped symbols/etc */ +/* + * Size of private kernel buffer for ELF headers and sections + */ #define P_SIZE (256 * 1024) -#endif - -extern unsigned long physical_memsize; +/* + * Size of private kernel buffer for ELF headers and sections + */ #define MAX_VPES 16 #define VPE_PATH_MAX 256 @@ -100,6 +97,16 @@ enum tc_state { TC_STATE_DYNAMIC }; +enum load_state { + LOAD_STATE_EHDR, + LOAD_STATE_PHDR, + LOAD_STATE_SHDR, + LOAD_STATE_PIMAGE, + LOAD_STATE_TRAILER, + LOAD_STATE_DONE, + LOAD_STATE_ERROR +}; + struct vpe { enum vpe_state state; @@ -107,10 +114,25 @@ struct vpe { int minor; /* elfloader stuff */ + unsigned long offset; /* File offset into input stream */ void *load_addr; - unsigned long len; + unsigned long copied; char *pbuffer; - unsigned long plen; + unsigned long pbsize; + /* Program loading state */ + enum load_state l_state; + Elf_Ehdr *l_ehdr; + struct elf_phdr *l_phdr; + unsigned int l_phlen; + Elf_Shdr *l_shdr; + unsigned int l_shlen; + int *l_phsort; /* Sorted index list of program headers */ + int l_segoff; /* Offset into current program segment */ + int l_cur_seg; /* Indirect index of segment currently being loaded */ + unsigned int l_progminad; + unsigned int l_progmaxad; + unsigned int l_trailer; + unsigned int uid, gid; char cwd[VPE_PATH_MAX]; @@ -122,9 +144,12 @@ struct vpe { /* The list of vpe's */ struct list_head list; - /* shared symbol address */ + /* legacy shared symbol address */ void *shared_ptr; + /* shared area descriptor array address */ + struct vpe_shared_area *shared_areas; + /* the list of who wants to know when something major happens */ struct list_head notify; @@ -146,13 +171,24 @@ struct { spinlock_t tc_list_lock; struct list_head tc_list; /* Thread contexts */ } vpecontrol = { - .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), + .vpe_list_lock = SPIN_LOCK_UNLOCKED, .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), - .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), + .tc_list_lock = SPIN_LOCK_UNLOCKED, .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) }; static void release_progmem(void *ptr); +/* + * Values and state associated with publishing shared memory areas + */ + +#define N_PUB_AREAS 4 + +static struct vpe_shared_area published_vpe_area[N_PUB_AREAS] = { + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0}, + {VPE_SHARED_RESERVED, 0} }; /* get the vpe associated with this minor */ static struct vpe *get_vpe(int minor) @@ -175,7 +211,7 @@ static struct vpe *get_vpe(int minor) return res; } -/* get the vpe associated with this minor */ +/* get the tc associated with this minor */ static struct tc *get_tc(int index) { struct tc *res, *t; @@ -200,7 +236,8 @@ static struct vpe *alloc_vpe(int minor) if ((v = kzalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) return NULL; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct vpe), (unsigned int)v); INIT_LIST_HEAD(&v->tc); spin_lock(&vpecontrol.vpe_list_lock); list_add_tail(&v->list, &vpecontrol.vpe_list); @@ -219,7 +256,8 @@ static struct tc *alloc_tc(int index) if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) goto out; - + printk(KERN_DEBUG "Used kzalloc to allocate %d bytes at %x\n", + sizeof(struct tc), (unsigned int)tc); INIT_LIST_HEAD(&tc->tc); tc->index = index; @@ -237,6 +275,11 @@ static void release_vpe(struct vpe *v) list_del(&v->list); if (v->load_addr) release_progmem(v); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v->l_phsort); + kfree(v->l_phsort); + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)v); kfree(v); } @@ -260,8 +303,88 @@ static void __maybe_unused dump_mtregs(void) val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); } +/* + * The original APRP prototype assumed a single, unshared IRQ for + * cross-VPE interrupts, used by the RTLX code. But M3P networking + * and other future functions may need to share an IRQ, particularly + * in 34K/Malta configurations without an external interrupt controller. + * All cross-VPE insterrupt users need to coordinate through shared + * functions here. + */ + +/* + * It would be nice if I could just have this initialized to zero, + * but the patchcheck police won't hear of it... + */ + +static int xvpe_vector_set; + +#define XVPE_INTR_OFFSET 0 + +static int xvpe_irq = MIPS_CPU_IRQ_BASE + XVPE_INTR_OFFSET; + +static void xvpe_dispatch(void) +{ + do_IRQ(xvpe_irq); +} + +/* Name here is generic, as m3pnet.c could in principle be used by non-MIPS */ +int arch_get_xcpu_irq() +{ + /* + * Some of this will ultimately become platform code, + * but for now, we're only targeting 34K/FPGA/Malta, + * and there's only one generic mechanism. + */ + if (!xvpe_vector_set) { + /* + * A more elaborate shared variable shouldn't be needed. + * Two initializations back-to-back should be harmless. + */ + if (cpu_has_vint) { + set_vi_handler(XVPE_INTR_OFFSET, xvpe_dispatch); + xvpe_vector_set = 1; + } else { + printk(KERN_ERR "APRP requires vectored interrupts\n"); + return -1; + } + } + + return xvpe_irq; +} +EXPORT_SYMBOL(arch_get_xcpu_irq); + +int vpe_send_interrupt(int vpe, int inter) +{ + unsigned long flags; + unsigned int vpeflags; + + local_irq_save(flags); + vpeflags = dvpe(); + + /* + * Initial version makes same simple-minded assumption + * as is implicit elsewhere in this module, that the + * only RP of interest is using the first non-Linux TC. + * We ignore the parameters provided by the caller! + */ + settc(tclimit); + /* + * In 34K/Malta, the only cross-VPE interrupts possible + * are done by setting SWINT bits in Cause, of which there + * are two. SMTC uses SW1 for a multiplexed class of IPIs, + * and this mechanism should be generalized to APRP and use + * the same protocol. Until that's implemented, send only + * SW0 here, regardless of requested type. + */ + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); + evpe(vpeflags); + local_irq_restore(flags); + return 1; +} +EXPORT_SYMBOL(vpe_send_interrupt); /* Find some VPE program space */ -static void *alloc_progmem(unsigned long len) +static void *alloc_progmem(void *requested, unsigned long len) { void *addr; @@ -271,10 +394,28 @@ static void *alloc_progmem(unsigned long len) * physically have, for example by passing a mem= boot argument. */ addr = pfn_to_kaddr(max_low_pfn); - memset(addr, 0, len); + if (requested != 0) { + if (requested >= addr) + addr = requested; + else + addr = 0; + } + if (addr != 0) + memset(addr, 0, len); + printk(KERN_DEBUG "pfn_to_kaddr returns %lu bytes of memory at %x\n", + len, (unsigned int)addr); #else - /* simple grab some mem for now */ - addr = kzalloc(len, GFP_KERNEL); + if (requested != 0) { + /* If we have a target in mind, grab a 2x slice and hope... */ + addr = kzalloc(len*2, GFP_KERNEL); + if ((requested >= addr) && (requested < (addr + len))) + addr = requested; + else + addr = 0; + } else { + /* simply grab some mem for now */ + addr = kzalloc(len, GFP_KERNEL); + } #endif return addr; @@ -446,6 +587,8 @@ static int apply_r_mips_hi16(struct module *me, uint32_t *location, * actual relocation. */ n = kmalloc(sizeof *n, GFP_KERNEL); + printk(KERN_DEBUG "Used kmalloc to allocate %d bytes at %x\n", + sizeof(struct mips_hi16), (unsigned int)n); if (!n) return -ENOMEM; @@ -503,6 +646,8 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, *l->addr = insn; next = l->next; + printk(KERN_DEBUG "Used kfree to free memory at %x\n", + (unsigned int)l); kfree(l); l = next; } @@ -596,7 +741,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs, return 0; } -static inline void save_gp_address(unsigned int secbase, unsigned int rel) +void save_gp_address(unsigned int secbase, unsigned int rel) { gp_addr = secbase + rel; gp_offs = gp_addr - (secbase & 0xffff0000); @@ -816,16 +961,41 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, struct module *mod) { Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; - unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); + unsigned int i, j, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); for (i = 1; i < n; i++) { - if (strcmp(strtab + sym[i].st_name, "__start") == 0) { - v->__start = sym[i].st_value; + if (strcmp(strtab + sym[i].st_name, "__start") == 0) + v->__start = sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) + v->shared_ptr = (void *)sym[i].st_value; + + if (strcmp(strtab + sym[i].st_name, "_vpe_shared_areas") == 0) { + struct vpe_shared_area *psa + = (struct vpe_shared_area *)sym[i].st_value; + struct vpe_shared_area *tpsa; + v->shared_areas = psa; + printk(KERN_INFO"_vpe_shared_areas found, 0x%x\n", + (unsigned int)v->shared_areas); + /* + * Copy any "published" areas to the descriptor + */ + for (j = 0; j < N_PUB_AREAS; j++) { + if (published_vpe_area[j].type != VPE_SHARED_RESERVED) { + tpsa = psa; + while (tpsa->type != VPE_SHARED_NULL) { + if ((tpsa->type == VPE_SHARED_RESERVED) + || (tpsa->type == published_vpe_area[j].type)) { + tpsa->type = published_vpe_area[j].type; + tpsa->addr = published_vpe_area[j].addr; + break; + } + tpsa++; + } + } } + } - if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) { - v->shared_ptr = (void *)sym[i].st_value; - } } if ( (v->__start == 0) || (v->shared_ptr == NULL)) @@ -850,14 +1020,12 @@ static int vpe_elfload(struct vpe * v) memset(&mod, 0, sizeof(struct module)); strcpy(mod.name, "VPE loader"); - - hdr = (Elf_Ehdr *) v->pbuffer; - len = v->plen; + hdr = v->l_ehdr; + len = v->pbsize; /* Sanity checks against insmoding binaries or wrong arch, weird elf version */ - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0 - || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) + if ((hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) || !elf_check_arch(hdr) || hdr->e_shentsize != sizeof(*sechdrs)) { printk(KERN_WARNING @@ -869,9 +1037,8 @@ static int vpe_elfload(struct vpe * v) if (hdr->e_type == ET_REL) relocate = 1; - if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { - printk(KERN_ERR "VPE loader: program length %u truncated\n", - len); + if (len < v->l_phlen + v->l_shlen) { + printk(KERN_ERR "VPE loader: Headers exceed %u bytes\n", len); return -ENOEXEC; } @@ -905,9 +1072,13 @@ static int vpe_elfload(struct vpe * v) } } layout_sections(&mod, hdr, sechdrs, secstrings); + /* + * Non-relocatable loads should have already done their + * allocates, based on program header table. + */ } - v->load_addr = alloc_progmem(mod.core_size); + memset(v->load_addr, 0, mod.core_size); if (!v->load_addr) return -ENOMEM; @@ -960,19 +1131,10 @@ static int vpe_elfload(struct vpe * v) } } else { - struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); - - for (i = 0; i < hdr->e_phnum; i++) { - if (phdr->p_type == PT_LOAD) { - memcpy((void *)phdr->p_paddr, - (char *)hdr + phdr->p_offset, - phdr->p_filesz); - memset((void *)phdr->p_paddr + phdr->p_filesz, - 0, phdr->p_memsz - phdr->p_filesz); - } - phdr++; - } + /* + * Program image is already in memory. + */ for (i = 0; i < hdr->e_shnum; i++) { /* Internal symbols and strings. */ if (sechdrs[i].sh_type == SHT_SYMTAB) { @@ -989,7 +1151,7 @@ static int vpe_elfload(struct vpe * v) /* make sure it's physically written out */ flush_icache_range((unsigned long)v->load_addr, - (unsigned long)v->load_addr + v->len); + (unsigned long)v->load_addr + v->copied); if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { if (v->__start == 0) { @@ -1003,8 +1165,8 @@ static int vpe_elfload(struct vpe * v) "program does not contain vpe_shared symbol.\n" " Unable to use AMVP (AP/SP) facilities.\n"); } + pr_info("APRP VPE loader: elf loaded\n"); - printk(" elf loaded\n"); return 0; } @@ -1069,6 +1231,10 @@ static int vpe_open(struct inode *inode, struct file *filp) return -ENODEV; } + /* + * This treats the tclimit command line configuration input + * as a minor device indication, which is probably unwholesome. + */ if ((v = get_vpe(tclimit)) == NULL) { pr_warning("VPE loader: unable to get vpe\n"); @@ -1085,18 +1251,20 @@ static int vpe_open(struct inode *inode, struct file *filp) } release_progmem(v->load_addr); + kfree(v->l_phsort); cleanup_tc(get_tc(tclimit)); } /* this of-course trashes what was there before... */ v->pbuffer = vmalloc(P_SIZE); - if (!v->pbuffer) { - pr_warning("VPE loader: unable to allocate memory\n"); - return -ENOMEM; - } - v->plen = P_SIZE; v->load_addr = NULL; - v->len = 0; + v->copied = 0; + v->offset = 0; + v->l_state = LOAD_STATE_EHDR; + v->l_ehdr = NULL; + v->l_phdr = NULL; + v->l_phsort = NULL; + v->l_shdr = NULL; v->uid = filp->f_cred->fsuid; v->gid = filp->f_cred->fsgid; @@ -1115,6 +1283,7 @@ static int vpe_open(struct inode *inode, struct file *filp) printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret); v->shared_ptr = NULL; + v->shared_areas = NULL; v->__start = 0; return 0; @@ -1123,26 +1292,39 @@ static int vpe_open(struct inode *inode, struct file *filp) static int vpe_release(struct inode *inode, struct file *filp) { struct vpe *v; - Elf_Ehdr *hdr; int ret = 0; v = get_vpe(tclimit); if (v == NULL) return -ENODEV; + /* + * If image load had no errors, massage program/section tables + * to reflect movement of program/section data into VPE program + * memory. + */ + if (v->l_state != LOAD_STATE_DONE) { + printk(KERN_WARNING "VPE Release after incomplete load\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); + return -ENOEXEC; + } - hdr = (Elf_Ehdr *) v->pbuffer; - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) { - if (vpe_elfload(v) >= 0) { - vpe_run(v); - } else { - printk(KERN_WARNING "VPE loader: ELF load failed.\n"); - ret = -ENOEXEC; - } + if (vpe_elfload(v) >= 0) { + vpe_run(v); } else { - printk(KERN_WARNING "VPE loader: only elf files are supported\n"); + printk(KERN_WARNING "VPE loader: ELF load failed.\n"); + printk(KERN_DEBUG "Used vfree to free memory at " + "%x after failed load attempt\n", + (unsigned int)v->pbuffer); + if (v->pbuffer != NULL) + vfree(v->pbuffer); ret = -ENOEXEC; } + /* It's good to be able to run the SP and if it chokes have a look at the /dev/rt?. But if we reset the pointer to the shared struct we lose what has happened. So perhaps if garbage is sent to the vpe @@ -1151,17 +1333,68 @@ static int vpe_release(struct inode *inode, struct file *filp) if (ret < 0) v->shared_ptr = NULL; - vfree(v->pbuffer); - v->plen = 0; - + // cleanup any temp buffers + if (v->pbuffer) { + printk(KERN_DEBUG "Used vfree to free memory at %x\n", + (unsigned int)v->pbuffer); + vfree(v->pbuffer); + } + v->pbsize = 0; return ret; } +/* + * A sort of insertion sort to generate list of program header indices + * in order of their file offsets. + */ + +static void indexort(struct elf_phdr *phdr, int nph, int *index) +{ + int i, j, t; + unsigned int toff; + + /* Create initial mapping */ + for (i = 0; i < nph; i++) + index[i] = i; + /* Do the indexed insert sort */ + for (i = 1; i < nph; i++) { + j = i; + t = index[j]; + toff = phdr[t].p_offset; + while ((j > 0) && (phdr[index[j-1]].p_offset > toff)) { + index[j] = index[j-1]; + j--; + } + index[j] = t; + } +} + + +/* + * This function has to convert the ELF file image being sequentially + * streamed to the pseudo-device into the binary image, symbol, and + * string information, which the ELF format allows to be in some degree + * of disorder. + * + * The ELF header and, if present, program header table, are copied into + * a temporary buffer. Loadable program segments, if present, are copied + * into the RP program memory at the addresses specified by the program + * header table. + * + * Sections not specified by the program header table are loaded into + * memory following the program segments if they are "allocated", or + * into the temporary buffer if they are not. The section header + * table is loaded into the temporary buffer.??? + */ +#define CURPHDR (v->l_phdr[v->l_phsort[v->l_cur_seg]]) static ssize_t vpe_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos) { size_t ret = count; struct vpe *v; + int tocopy, uncopied; + int i; + unsigned int progmemlen; if (iminor(file->f_path.dentry->d_inode) != minor) return -ENODEV; @@ -1170,17 +1403,357 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, if (v == NULL) return -ENODEV; - if ((count + v->len) > v->plen) { - printk(KERN_WARNING - "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + if (v->pbuffer == NULL) { + printk(KERN_ERR "VPE loader: no buffer for program\n"); return -ENOMEM; } - count -= copy_from_user(v->pbuffer + v->len, buffer, count); - if (!count) - return -EFAULT; + while (count) { + switch (v->l_state) { + case LOAD_STATE_EHDR: + /* Loading ELF Header into scratch buffer */ + tocopy = min((unsigned long)count, + sizeof(Elf_Ehdr) - v->offset); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->copied == sizeof(Elf_Ehdr)) { + v->l_ehdr = (Elf_Ehdr *)v->pbuffer; + if (memcmp(v->l_ehdr->e_ident, ELFMAG, 4) != 0) { + printk(KERN_WARNING "VPE loader: %s\n", + "non-ELF file image"); + ret = -ENOEXEC; + v->l_state = LOAD_STATE_ERROR; + break; + } + if (v->l_ehdr->e_phoff != 0) { + v->l_phdr = (struct elf_phdr *) + (v->pbuffer + v->l_ehdr->e_phoff); + v->l_phlen = v->l_ehdr->e_phentsize + * v->l_ehdr->e_phnum; + /* Check against buffer overflow */ + if ((v->copied + v->l_phlen) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf program header table size too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_PHDR; + /* + * Program headers generally indicate + * linked executable with possibly + * valid entry point. + */ + v->__start = v->l_ehdr->e_entry; + } else if (v->l_ehdr->e_shoff != 0) { + /* + * No program headers, but a section + * header table. A relocatable binary. + * We need to load the works into the + * kernel temp buffer to compute the + * RP program image. That limits our + * binary size, but at least we're no + * worse off than the original APRP + * prototype. + */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big.\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + } else { + /* + * If neither program nor section tables, + * we don't know what to do. + */ + v->l_state = LOAD_STATE_ERROR; + return -ENOEXEC; + } + } + break; + case LOAD_STATE_PHDR: + /* Loading Program Headers into scratch */ + tocopy = min((unsigned long)count, + v->l_ehdr->e_phoff + v->l_phlen - v->copied); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + + if (v->copied == v->l_ehdr->e_phoff + v->l_phlen) { + /* + * It's legal for the program headers to be + * out of order with respect to the file layout. + * Generate a list of indices, sorted by file + * offset. + */ + v->l_phsort = kmalloc(v->l_ehdr->e_phnum + * sizeof(int), GFP_KERNEL); + printk(KERN_DEBUG + "Used kmalloc to allocate %d bytes of memory at %x\n", + v->l_ehdr->e_phnum*sizeof(int), + (unsigned int)v->l_phsort); + if (!v->l_phsort) + return -ENOMEM; /* Preposterous, but... */ + indexort(v->l_phdr, v->l_ehdr->e_phnum, + v->l_phsort); + + v->l_progminad = (unsigned int)-1; + v->l_progmaxad = 0; + progmemlen = 0; + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + /* Unstripped .reginfo sections are bad */ + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "User-mode p_vaddr, ", + "skipping program segment,"); + printk(KERN_WARNING "%s%s%s\n", + "VPE loader: ", + "strip .reginfo from binary ", + "if necessary."); + continue; + } + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < v->l_progminad) + v->l_progminad = + v->l_phdr[v->l_phsort[i]].p_vaddr; + if ((v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz) + > v->l_progmaxad) + v->l_progmaxad = + v->l_phdr[v->l_phsort[i]].p_vaddr + + v->l_phdr[v->l_phsort[i]].p_memsz; + } + } + printk(KERN_INFO "APRP RP program 0x%x to 0x%x\n", + v->l_progminad, v->l_progmaxad); + /* + * Do a simple sanity check of the memory being + * allocated. Abort if greater than an arbitrary + * value of 32MB + */ + if (v->l_progmaxad - v->l_progminad > + 32*1024*1024) { + printk(KERN_WARNING + "RP program failed to allocate %d kbytes - limit is 32,768 KB\n", + (v->l_progmaxad - v->l_progminad)/1024); + return -ENOMEM; + } + + v->load_addr = alloc_progmem((void *)v->l_progminad, + v->l_progmaxad - v->l_progminad); + if (!v->load_addr) + return -ENOMEM; + if ((unsigned int)v->load_addr + > v->l_progminad) { + release_progmem(v->load_addr); + return -ENOMEM; + } + /* Find first segment with loadable content */ + for (i = 0; i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + if (i == v->l_ehdr->e_phnum) { + /* No loadable program segment? Bogus file. */ + printk(KERN_WARNING "Bad ELF file for APRP\n"); + return -ENOEXEC; + } + v->l_segoff = 0; + v->l_state = LOAD_STATE_PIMAGE; + } + break; + case LOAD_STATE_PIMAGE: + /* + * Skip through input stream until + * first program segment. Would be + * better to have loaded up to here + * into the temp buffer, but for now + * we simply rule out "interesting" + * sections prior to the last program + * segment in an executable file. + */ + if (v->offset < CURPHDR.p_offset) { + uncopied = CURPHDR.p_offset - v->offset; + if (uncopied > count) + uncopied = count; + count -= uncopied; + buffer += uncopied; + v->offset += uncopied; + /* Go back through the "while" */ + break; + } + /* + * Having dispensed with any unlikely fluff, + * copy from user I/O buffer to program segment. + */ + tocopy = min(count, CURPHDR.p_filesz - v->l_segoff); + + /* Loading image into RP memory */ + uncopied = copy_from_user((char *)CURPHDR.p_vaddr + + v->l_segoff, buffer, tocopy); + count -= tocopy - uncopied; + v->offset += tocopy - uncopied; + v->l_segoff += tocopy - uncopied; + buffer += tocopy - uncopied; + if (v->l_segoff >= CURPHDR.p_filesz) { + /* Finished current segment load */ + /* Zero out non-file-sourced image */ + uncopied = CURPHDR.p_memsz - CURPHDR.p_filesz; + if (uncopied > 0) + memset((char *)CURPHDR.p_vaddr + v->l_segoff, + 0, uncopied); + /* Advance to next segment */ + for (i = v->l_cur_seg + 1; + i < v->l_ehdr->e_phnum; i++) { + if (v->l_phdr[v->l_phsort[i]].p_type + == PT_LOAD) { + if (v->l_phdr[v->l_phsort[i]].p_vaddr + < __UA_LIMIT) { + /* Skip userspace segments */ + continue; + } + v->l_cur_seg = i; + break; + } + } + /* If none left, prepare to load section headers */ + if (i == v->l_ehdr->e_phnum) { + if (v->l_ehdr->e_shoff != 0) { + /* Copy to where we left off in temp buffer */ + v->l_shlen = v->l_ehdr->e_shentsize + * v->l_ehdr->e_shnum; + if ((v->l_ehdr->e_shoff + v->l_shlen + - v->offset) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf sections/section table too big\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + v->l_state = LOAD_STATE_SHDR; + break; + } + } else { + /* reset offset for new program segment */ + v->l_segoff = 0; + } + } + break; + case LOAD_STATE_SHDR: + /* + * Read stream into private buffer up + * through and including the section header + * table. + */ - v->len += count; + tocopy = min((unsigned long)count, + v->l_ehdr->e_shoff + v->l_shlen - v->offset); + if (tocopy) { + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + /* Finished? */ + if (v->offset == v->l_ehdr->e_shoff + v->l_shlen) { + unsigned int offset_delta = v->offset - v->copied; + + v->l_shdr = (Elf_Shdr *)(v->pbuffer + + v->l_ehdr->e_shoff - offset_delta); + /* + * Check for sections after the section table, + * which for gcc MIPS binaries includes + * the symbol table. Do any other processing + * that requires value within stream, and + * normalize offsets to be relative to + * the header-only layout of temp buffer. + */ + + /* Assume no trailer until we detect one */ + v->l_trailer = 0; + v->l_state = LOAD_STATE_DONE; + for (i = 0; i < v->l_ehdr->e_shnum; i++) { + if (v->l_shdr[i].sh_offset + > v->l_ehdr->e_shoff) { + v->l_state = LOAD_STATE_TRAILER; + /* Track trailing data length */ + if (v->l_trailer + < (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen)) + v->l_trailer = + (v->l_shdr[i].sh_offset + + v->l_shdr[i].sh_size) + - (v->l_ehdr->e_shoff + + v->l_shlen); + } + /* Adjust section offset if necessary */ + v->l_shdr[i].sh_offset -= offset_delta; + } + if ((v->copied + v->l_trailer) > v->pbsize) { + printk(KERN_WARNING + "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); + v->l_state = LOAD_STATE_ERROR; + return -ENOMEM; + } + + /* Fix up offsets in ELF header */ + v->l_ehdr->e_shoff = (unsigned int)v->l_shdr + - (unsigned int)v->pbuffer; + } + break; + case LOAD_STATE_TRAILER: + /* + * Symbol and string tables follow section headers + * in gcc binaries for MIPS. Copy into temp buffer. + */ + if (v->l_trailer) { + tocopy = min(count, v->l_trailer); + uncopied = copy_from_user(v->pbuffer + v->copied, + buffer, tocopy); + count -= tocopy - uncopied; + v->l_trailer -= tocopy - uncopied; + v->copied += tocopy - uncopied; + v->offset += tocopy - uncopied; + buffer += tocopy - uncopied; + } + if (!v->l_trailer) + v->l_state = LOAD_STATE_DONE; + break; + case LOAD_STATE_DONE: + if (count) + count = 0; + break; + case LOAD_STATE_ERROR: + default: + return -EINVAL; + } + } return ret; } @@ -1216,7 +1789,9 @@ int vpe_start(vpe_handle vpe, unsigned long start) { struct vpe *v = vpe; - v->__start = start; + /* Null start address means use value from ELF file */ + if (start) + v->__start = start; return vpe_run(v); } @@ -1341,6 +1916,99 @@ char *vpe_getcwd(int index) EXPORT_SYMBOL(vpe_getcwd); +/* + * RP applications may contain a _vpe_shared_area descriptor + * array to allow for data sharing with Linux kernel functions + * that's slightly more abstracted and extensible than the + * fixed binding used by the rtlx support. Indeed, the rtlx + * support should ideally be converted to use the generic + * shared area descriptor scheme at some point. + * + * mips_get_vpe_shared_area() can be used by AP kernel + * modules to get an area pointer of a given type, if + * it exists. + * + * mips_publish_vpe_area() is used by AP kernel modules + * to share kseg0 kernel memory with the RP. It maintains + * a private table, so that publishing can be done before + * the RP program is launched. Making this table dynamically + * allocated and extensible would be good scalable OS design. + * however, until there's more than one user of the mechanism, + * it should be an acceptable simplification to allow a static + * maximum of 4 published areas. + */ + +void *mips_get_vpe_shared_area(int index, int type) +{ + struct vpe *v; + struct vpe_shared_area *vsa; + + v = get_vpe(index); + if (v == NULL) + return NULL; + + if (v->shared_areas == NULL) + return NULL; + + vsa = v->shared_areas; + + while (vsa->type != VPE_SHARED_NULL) { + if (vsa->type == type) + return vsa->addr; + else + vsa++; + } + /* Fell through without finding type */ + + return NULL; +} +EXPORT_SYMBOL(mips_get_vpe_shared_area); + +int mips_publish_vpe_area(int type, void *ptr) +{ + int i; + int retval = 0; + struct vpe *v; + unsigned long flags; + unsigned int vpflags; + + printk(KERN_INFO "mips_publish_vpe_area(0x%x, 0x%x)\n", type, (int)ptr); + if ((unsigned int)ptr >= KSEG2) { + printk(KERN_ERR "VPE area pubish of invalid address 0x%x\n", + (int)ptr); + return 0; + } + for (i = 0; i < N_PUB_AREAS; i++) { + if (published_vpe_area[i].type == VPE_SHARED_RESERVED) { + published_vpe_area[i].type = type; + published_vpe_area[i].addr = ptr; + retval = type; + break; + } + } + /* + * If we've already got a VPE up and running, try to + * update the shared descriptor with the new data. + */ + list_for_each_entry(v, &vpecontrol.vpe_list, list) { + if (v->shared_areas != NULL) { + local_irq_save(flags); + vpflags = dvpe(); + for (i = 0; v->shared_areas[i].type != VPE_SHARED_NULL; i++) { + if ((v->shared_areas[i].type == type) + || (v->shared_areas[i].type == VPE_SHARED_RESERVED)) { + v->shared_areas[i].type = type; + v->shared_areas[i].addr = ptr; + } + } + evpe(vpflags); + local_irq_restore(flags); + } + } + return retval; +} +EXPORT_SYMBOL(mips_publish_vpe_area); + #ifdef CONFIG_MIPS_APSP_KSPD static void kspd_sp_exit( int sp_id) { @@ -1359,6 +2027,7 @@ static ssize_t store_kill(struct device *dev, struct device_attribute *attr, } release_progmem(vpe->load_addr); + kfree(vpe->l_phsort); cleanup_tc(get_tc(tclimit)); vpe_stop(vpe); vpe_free(vpe); @@ -1404,6 +2073,8 @@ static struct device_attribute vpe_class_attributes[] = { static void vpe_device_release(struct device *cd) { + printk(KERN_DEBUG "Using kfree to free vpe class device at %x\n", + (unsigned int)cd); kfree(cd); } @@ -1430,19 +2101,24 @@ static int __init vpe_module_init(void) } if (vpelimit == 0) { - printk(KERN_WARNING "No VPEs reserved for AP/SP, not " - "initializing VPE loader.\nPass maxvpes= argument as " - "kernel argument\n"); - +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) + printk(KERN_WARNING "No VPEs reserved for VPE loader.\n" + "Pass maxvpes= argument as kernel argument\n"); return -ENODEV; +#else + vpelimit = 1; +#endif } if (tclimit == 0) { +#if defined(CONFIG_MIPS_MT_SMTC) || defined(MIPS_MT_SMP) printk(KERN_WARNING "No TCs reserved for AP/SP, not " "initializing VPE loader.\nPass maxtcs= argument as " "kernel argument\n"); - return -ENODEV; +#else + tclimit = 1; +#endif } major = register_chrdev(0, module_name, &vpe_fops); @@ -1456,7 +2132,7 @@ static int __init vpe_module_init(void) printk(KERN_ERR "vpe_class registration failed\n"); goto out_chrdev; } - + xvpe_vector_set = 0; device_initialize(&vpe_device); vpe_device.class = &vpe_class, vpe_device.parent = NULL, -- 1.7.9.6 From sshtylyov@mvista.com Fri Apr 6 20:13:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 20:13:21 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:37691 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904086Ab2DFSNP (ORCPT ); Fri, 6 Apr 2012 20:13:15 +0200 Received: by bkcjk13 with SMTP id jk13so2949669bkc.36 for ; Fri, 06 Apr 2012 11:13:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=rg4SKF/yt8zjjBHfj/VYrFfi1lEVWnJtwd10m9otpVA=; b=BM6gLW5DjHup7SdU7aQ309CxzoICxWKbZruEca/bsmkZZB1Z+g2dn73YuYgjNSSvXq 5yzkRrojbtJeXTxPBM0BN7MQXAUSvSFtl8xzaa/kE6zWKEHQ7nOUrhBtnpR49Wnd5sA5 6oiU8/ozfHbVE6NlV6/dvFE3evjeNiSGsMA/8hi8v5O22KVJOgqrvWUxEWcTCw96+twB 7xhQmflLA7cNhrfUUamvgAfnqH1EhrG4H91tSkiNmOZDBEIp1o2L13t1rsH0pqHCSp8h KwVqIVXXAtvw0M30ZmE312U8sF0fgu9RKGEHhrJmQxbe+DUS1tGyihy5+eOzy/DfJGWs 6/RA== Received: by 10.204.128.152 with SMTP id k24mr3129290bks.127.1333735990114; Fri, 06 Apr 2012 11:13:10 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id iv11sm11325196bkc.16.2012.04.06.11.13.08 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 06 Apr 2012 11:13:09 -0700 (PDT) Message-ID: <4F7F31F9.7030706@mvista.com> Date: Fri, 06 Apr 2012 22:12:09 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:11.0) Gecko/20120327 Thunderbird/11.0.1 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org, sjhill@realitydiluted.com Subject: Re: [PATCH 4/5] MIPS: Malta PCI changes for PCI 2.1 compatibility and conflicts. References: <1333735183-15796-1-git-send-email-sjhill@mips.com> In-Reply-To: <1333735183-15796-1-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQnpUAjp+QnNrqD3nECH4TGPyk6H9SPtYYRTLgiRyg/HZSvqLJwEisnogOG8tR971JLsOOLn X-archive-position: 32873 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1177 Lines: 38 Hello. On 04/06/2012 09:59 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > Turns on PCI 2.1 compatibility for the Malta platform for the > PIIX4 controller. Change start address to avoid conflicts with > the ACPI and SMB devices. > Signed-off-by: Steven J. Hill > --- [...] > diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c > index b7f37d4..5f7d113 100644 > --- a/arch/mips/mti-malta/malta-setup.c > +++ b/arch/mips/mti-malta/malta-setup.c > @@ -222,3 +222,14 @@ void __init plat_mem_setup(void) > board_be_init = malta_be_init; > board_be_handler = malta_be_handler; > } > +/* Enable PCI 2.1 compatibility in PIIX4 */ > +static void __init quirk_dlcsetup(struct pci_dev *dev) > +{ > + u8 odlc, ndlc; You don't need two variables. And please add an empty line after declaration block. > + (void) pci_read_config_byte(dev, 0x82,&odlc); > + /* Enable passive releases and delayed transaction */ > + ndlc = odlc | 7; > + (void) pci_write_config_byte(dev, 0x82, ndlc); > +} > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, > + quirk_dlcsetup); WBR, Sergei From sjhill@mips.com Fri Apr 6 22:08:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2012 22:08:12 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:35279 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904078Ab2DFUIF (ORCPT ); Fri, 6 Apr 2012 22:08:05 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGFRt-0004Bl-W1; Fri, 06 Apr 2012 15:07:57 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [v2,4/5] MIPS: Malta PCI changes for PCI 2.1 compatibility and conflicts. Date: Fri, 6 Apr 2012 15:07:49 -0500 Message-Id: <1333742869-17373-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32874 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1798 Lines: 53 From: "Steven J. Hill" Turns on PCI 2.1 compatibility for the Malta platform for the PIIX4 controller. Change start address to avoid conflicts with the ACPI and SMB devices. Signed-off-by: Steven J. Hill --- arch/mips/mti-malta/malta-pci.c | 5 +++-- arch/mips/mti-malta/malta-setup.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index bf80921..afeb619 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -241,8 +241,9 @@ void __init mips_pcibios_init(void) return; } - if (controller->io_resource->start < 0x00001000UL) /* FIXME */ - controller->io_resource->start = 0x00001000UL; + /* Change start address to avoid conflicts with ACPI and SMB devices */ + if (controller->io_resource->start < 0x00002000UL) /* FIXME */ + controller->io_resource->start = 0x00002000UL; iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index b7f37d4..b45b343 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -222,3 +222,17 @@ void __init plat_mem_setup(void) board_be_init = malta_be_init; board_be_handler = malta_be_handler; } + +/* Enable PCI 2.1 compatibility in PIIX4. */ +static void __init quirk_dlcsetup(struct pci_dev *dev) +{ + u8 dlc; + + /* Enable passive releases and delayed transactions. */ + (void) pci_read_config_byte(dev, 0x82, &dlc); + dlc |= 7; + (void) pci_write_config_byte(dev, 0x82, dlc); +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + quirk_dlcsetup); -- 1.7.9.6 From grant.likely@secretlab.ca Sat Apr 7 03:51:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 03:52:00 +0200 (CEST) Received: from mail-gx0-f177.google.com ([209.85.161.177]:59333 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904084Ab2DGBvz (ORCPT ); Sat, 7 Apr 2012 03:51:55 +0200 Received: by ggnk1 with SMTP id k1so1609490ggn.36 for ; Fri, 06 Apr 2012 18:51:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:subject:to:cc:in-reply-to:references:date:message-id :x-gm-message-state; bh=nI8zXZJZpwIoHZ6XeMQP8Mw/SuzNU8LHjQif08NtX48=; b=imhFcFEg0JQZj0BZwy1xC2ci399B/pRMiTjIJryV2j1z0roWQGIOaKe5b0qNuhDgVV jPqmiTk012jtdXacB4dSsBIZmho225KYoo+b9t40WlbkjsADirenfjrlmPJtn8ft0Box Oemz+8Hm92E+PmHsvHOPUm+JMVhSF+gyPoCYPn9LXt/TN2MWR7BQuE1pkQP2AubTCQ9N rbzfYZag/lmC8WBfKN617vced35Z6wumiRfZ9NmmrFJmv3wCPbFA5C81DP9KNT+CD5oo hzUPDEqDgImP4IxibAN0PtoZMNgSBJxcNW23uPjNXNUCYbn/B7qOTxXX9njyRaFTWa5U tQFQ== Received: by 10.236.168.41 with SMTP id j29mr30759yhl.24.1333763509575; Fri, 06 Apr 2012 18:51:49 -0700 (PDT) Received: from localhost (mf90f36d0.tmodns.net. [208.54.15.249]) by mx.google.com with ESMTPS id 34sm14860486anu.6.2012.04.06.18.51.45 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 06 Apr 2012 18:51:48 -0700 (PDT) Received: by localhost (Postfix, from userid 1000) id 62D133E17B2; Fri, 6 Apr 2012 18:26:16 -0700 (PDT) From: Grant Likely Subject: Re: [PATCH] irq/irq_domain: Quit ignoring error returns from irq_alloc_desc_from(). To: David Daney , devicetree-discuss@lists.ozlabs.org, Rob Herring , Benjamin Herrenschmidt , Thomas Gleixner Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney In-Reply-To: <1333669933-25267-1-git-send-email-ddaney.cavm@gmail.com> References: <1333669933-25267-1-git-send-email-ddaney.cavm@gmail.com> Date: Fri, 06 Apr 2012 18:26:16 -0700 Message-Id: <20120407012616.62D133E17B2@localhost> X-Gm-Message-State: ALoCoQmDRLjydZscKYTOoYmkiSdY1Ke3Ka/qu1JtqGH5VCLTvGra+tjp/rzKceqDzAnLQPjcbtyL X-archive-position: 32875 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2195 Lines: 70 On Thu, 5 Apr 2012 16:52:13 -0700, David Daney wrote: > From: David Daney > > In commit 4bbdd45a (irq_domain/powerpc: eliminate irq_map; use > irq_alloc_desc() instead) code was added that ignores error returns > from irq_alloc_desc_from() by (silently) casting the return value to > unsigned. The negitive value error return now suddenly looks like a > valid irq number. > > Commits cc79ca69 (irq_domain: Move irq_domain code from powerpc to > kernel/irq) and 1bc04f2c (irq_domain: Add support for base irq and > hwirq in legacy mappings) move this code to its current location in > irqdomain.c > > The result of all of this is a null pointer dereference OOPS if one of > the error cases is hit. > > The fix: Don't cast away the negativeness of the return value and then > check for errors. > > Signed-off-by: David Daney > --- > kernel/irq/irqdomain.c | 11 ++++++----- > 1 files changed, 6 insertions(+), 5 deletions(-) > > diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c > index af48e59..9d3e3ae 100644 > --- a/kernel/irq/irqdomain.c > +++ b/kernel/irq/irqdomain.c > @@ -351,6 +351,7 @@ unsigned int irq_create_mapping(struct irq_domain *domain, > irq_hw_number_t hwirq) > { > unsigned int virq, hint; > + int irq; Merged, but I've dropped the new variable in favour of making virq an int. Makes for a smaller diffstat. g. > > pr_debug("irq: irq_create_mapping(0x%p, 0x%lx)\n", domain, hwirq); > > @@ -380,14 +381,14 @@ unsigned int irq_create_mapping(struct irq_domain *domain, > hint = hwirq % irq_virq_count; > if (hint == 0) > hint++; > - virq = irq_alloc_desc_from(hint, 0); > - if (!virq) > - virq = irq_alloc_desc_from(1, 0); > - if (!virq) { > + irq = irq_alloc_desc_from(hint, 0); > + if (irq <= 0) > + irq = irq_alloc_desc_from(1, 0); > + if (irq <= 0) { > pr_debug("irq: -> virq allocation failed\n"); > return 0; > } > - > + virq = irq; > if (irq_setup_virq(domain, virq, hwirq)) { > if (domain->revmap_type != IRQ_DOMAIN_MAP_LEGACY) > irq_free_desc(virq); > -- > 1.7.2.3 > -- Grant Likely, B.Sc, P.Eng. Secret Lab Technologies,Ltd. From grant.likely@secretlab.ca Sat Apr 7 03:51:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 03:52:21 +0200 (CEST) Received: from mail-gx0-f177.google.com ([209.85.161.177]:34061 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904093Ab2DGBv4 (ORCPT ); Sat, 7 Apr 2012 03:51:56 +0200 Received: by ggnk1 with SMTP id k1so1609492ggn.36 for ; Fri, 06 Apr 2012 18:51:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:subject:to:cc:in-reply-to:references:date:message-id :x-gm-message-state; bh=eBmYzAEgkWArDmsbrjpt7yGeINhvMHin1nL4kz2utCc=; b=RyNW1B4BLqRL2uO6EZ5PtELfFbySEOaOIeEDdyUSgvXv4AFNR9TEFhvzG129cTcP/U ZJobbWGpTNCnFp2P/i102e30ss5Apj7AgXZHIJWzzg9V/ApglYMBYeC7r9yy2iWu8bZa 08ckWrbQDck+y/I1ruDPysLs8w4MR1KBjR6QPj7+W7lS/s/5vWTJwOSaAPFDjxvZ/8FF aU93QdSZbqjgaAwBw8NEud7pfagOL8+xLLvqlnIj6wMueUrFjXDhoC5yvBe5mOESwEZm G0Z3zS/l4mrZxk2VqvMmtiG2FoOXMrGX/qVunQ2IGuT7H25rFMvBM4hYm6R1e0iRVzgJ dDaw== Received: by 10.100.249.1 with SMTP id w1mr6463anh.38.1333763510565; Fri, 06 Apr 2012 18:51:50 -0700 (PDT) Received: from localhost (mf90f36d0.tmodns.net. [208.54.15.249]) by mx.google.com with ESMTPS id r5sm14847455ani.19.2012.04.06.18.51.45 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 06 Apr 2012 18:51:48 -0700 (PDT) Received: by localhost (Postfix, from userid 1000) id DCCD53E15E9; Fri, 6 Apr 2012 16:56:07 -0700 (PDT) From: Grant Likely Subject: Re: [PATCH] irq/irq_domain: Quit ignoring error returns from irq_alloc_desc_from(). To: David Daney , Rob Herring , Benjamin Herrenschmidt , Thomas Gleixner Cc: David Daney , devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Linus Torvalds In-Reply-To: <4F7F1BDD.4070205@gmail.com> References: <1333669933-25267-1-git-send-email-ddaney.cavm@gmail.com> <4F7E64E4.3080509@gmail.com> <4F7F1BDD.4070205@gmail.com> Date: Fri, 06 Apr 2012 16:56:07 -0700 Message-Id: <20120406235607.DCCD53E15E9@localhost> X-Gm-Message-State: ALoCoQlAGuNTpC5Uh3AKCiqXJHRNdyMNLfFwMEJqRSKPN2XjhFufiql0r9skeG03L/+0dI0Bs2qB X-archive-position: 32876 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1030 Lines: 25 On Fri, 06 Apr 2012 09:37:49 -0700, David Daney wrote: > On 04/05/2012 08:37 PM, Rob Herring wrote: > > On 04/05/2012 06:52 PM, David Daney wrote: > >> From: David Daney > >> @@ -380,14 +381,14 @@ unsigned int irq_create_mapping(struct irq_domain *domain, > >> hint = hwirq % irq_virq_count; > >> if (hint == 0) > >> hint++; > >> - virq = irq_alloc_desc_from(hint, 0); > > > > You are not looking at mainline. hint was removed in later versions, and > > the referenced commit ids don't exist. > > Please look at Linus' tree before making incorrect statements about > whether or not code exists on the 'mainline' Rob is indeed mistaken here, but please let's keep things civil. I did write the patches to remove the hint, but I avoided merging them because I think they are risky. I wanted to get the core irq_domain changes in first. The removal of hint will be applied during the next merge window. I will take your bug fix and get it pushed up to Linus soon. g. From jonas.gorski@gmail.com Sat Apr 7 12:47:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 12:48:10 +0200 (CEST) Received: from mail-iy0-f177.google.com ([209.85.210.177]:53317 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904105Ab2DGKrx convert rfc822-to-8bit (ORCPT ); Sat, 7 Apr 2012 12:47:53 +0200 Received: by iaky10 with SMTP id y10so5002382iak.36 for ; Sat, 07 Apr 2012 03:47:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=zuv1IqXPti0IU5BmZ75kblFNCIACtH3XD1ImdEoTN1w=; b=xJNOCz6Xs7P3GJW6twCbRm7Cl/j0Zc+xCC2eH7kDIYkWRq30Qskc79GhfGKO2M0ulu 69ZkhBgz04EhbhB/fwLHsvhpaDKalZbu+rr03I6Z/v1nKtCpTMIdOOMcrWjf8Jc/HRbe 2sBQ/hpiqsXCmRwAmOTOTkAvSRNv8unFv4yfBtps80a6BP5f9JhEv/PJ2h3e3Mogotsb /yQ42gCX6mes9+OskoCmF4EY4OhyBtVRZiW8ReLDKjgW/zzoTZKqa1Ke+h61wS7s2j/J A3FO2WGtd5yCH5UdEfo8JxNzuH9UuzimzZ+g3G18d+o2yVf1LLC8RoVfIUgrz1hdCm3T 8PsQ== Received: by 10.50.46.138 with SMTP id v10mr697637igm.18.1333795667532; Sat, 07 Apr 2012 03:47:47 -0700 (PDT) MIME-Version: 1.0 Received: by 10.42.202.144 with HTTP; Sat, 7 Apr 2012 03:47:27 -0700 (PDT) In-Reply-To: <1333735064-15672-1-git-send-email-sjhill@mips.com> References: <1333735064-15672-1-git-send-email-sjhill@mips.com> From: Jonas Gorski Date: Sat, 7 Apr 2012 12:47:27 +0200 Message-ID: Subject: Re: [PATCH 1/5] MIPS: Add support for the 1074K core. To: "Steven J. Hill" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, sjhill@realitydiluted.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32877 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1640 Lines: 45 Hi, On 6 April 2012 19:57, Steven J. Hill wrote: > From: "Steven J. Hill" > > This patch adds support for detecting and using 1074K cores. > Signed-off-by: Steven J. Hill > > (snip) > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > index bda8eb2..a08e75d 100644 > --- a/arch/mips/mm/c-r4k.c > +++ b/arch/mips/mm/c-r4k.c > @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) >                        c->icache.linesz = 2 << lsize; >                else >                        c->icache.linesz = lsize; > -               c->icache.sets = 64 << ((config1 >> 22) & 7); > +               c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); Why this change? According to the 1074K datasheet it is still 64 * 2^S, so to me it looks like the previous version was correct. Also adding first and then masking looks really wrong, and will produce wrong results for 0x7. >                c->icache.ways = 1 + ((config1 >> 16) & 7); > >                icache_size = c->icache.sets * > @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) >                        c->dcache.linesz = 2 << lsize; >                else >                        c->dcache.linesz= lsize; > -               c->dcache.sets = 64 << ((config1 >> 13) & 7); > +               c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); See above. >                c->dcache.ways = 1 + ((config1 >> 7) & 7); > >                dcache_size = c->dcache.sets * > (snip) Jonas From sjhill@mips.com Sat Apr 7 18:48:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:49:01 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36596 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904106Ab2DGQsy (ORCPT ); Sat, 7 Apr 2012 18:48:54 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYof-0004dH-TH; Sat, 07 Apr 2012 11:48:45 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 00/10] Add support MIPS SEAD-3 Development Platform. Date: Sat, 7 Apr 2012 11:48:25 -0500 Message-Id: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32878 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5600 Lines: 103 From: "Steven J. Hill" This patch set adds support for the MIPS Technologies, Inc. SEAD-3 development platform. Please visit for more detailed information. Steven J. Hill (10): MIPS: Add core files for MIPS SEAD-3 development platform. MIPS: Changes to configuration files for SEAD-3 platform. MIPS: Add support for the M14K core. MIPS: Add micro-assembler support for 'ins' and 'ext' instructions. MIPS: GIC interrupt changes for M14K and SEAD-3 support. MIPS: Code formatting fixes. MIPS: Add support for early serial debug and LCD device on SEAD-3. MIPS: MIPS32R2 optimisations for pipeline stalls and code size. cobalt_lcdfb: LCD panel framebuffer support for SEAD-3 platform. usb: host: mips: sead3: USB Host controller support for SEAD-3 platform. arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 33 +- arch/mips/configs/sead3_defconfig | 1757 ++++++++++++++++++++ arch/mips/include/asm/cpu-features.h | 4 +- arch/mips/include/asm/cpu.h | 5 +- .../include/asm/mach-sead3/cpu-feature-overrides.h | 72 + arch/mips/include/asm/mach-sead3/irq.h | 9 + .../include/asm/mach-sead3/kernel-entry-init.h | 52 + arch/mips/include/asm/mach-sead3/war.h | 25 + arch/mips/include/asm/mips-boards/generic.h | 1 + arch/mips/include/asm/mips-boards/sead3int.h | 67 + arch/mips/include/asm/uasm.h | 15 + arch/mips/kernel/cevt-r4k.c | 5 + arch/mips/kernel/cpu-probe.c | 64 +- arch/mips/kernel/early_printk.c | 25 + arch/mips/kernel/irq-gic.c | 168 +- arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 54 +- arch/mips/mm/uasm.c | 15 + arch/mips/mti-sead3/Makefile | 24 + arch/mips/mti-sead3/Platform | 7 + arch/mips/mti-sead3/leds-sead3.c | 133 ++ arch/mips/mti-sead3/sead3-cmdline.c | 59 + arch/mips/mti-sead3/sead3-console.c | 52 + arch/mips/mti-sead3/sead3-display.c | 90 + arch/mips/mti-sead3/sead3-ehci.c | 52 + arch/mips/mti-sead3/sead3-i2c-dev.c | 38 + arch/mips/mti-sead3/sead3-i2c.c | 42 + arch/mips/mti-sead3/sead3-init.c | 244 +++ arch/mips/mti-sead3/sead3-int.c | 146 ++ arch/mips/mti-sead3/sead3-lcd.c | 55 + arch/mips/mti-sead3/sead3-leds.c | 91 + arch/mips/mti-sead3/sead3-memory.c | 178 ++ arch/mips/mti-sead3/sead3-mtd.c | 58 + arch/mips/mti-sead3/sead3-net.c | 56 + arch/mips/mti-sead3/sead3-pic32-bus.c | 112 ++ arch/mips/mti-sead3/sead3-pic32-i2c-drv.c | 441 +++++ arch/mips/mti-sead3/sead3-platform.c | 49 + arch/mips/mti-sead3/sead3-reset.c | 64 + arch/mips/mti-sead3/sead3-setup.c | 49 + arch/mips/mti-sead3/sead3-smtc.c | 162 ++ arch/mips/mti-sead3/sead3-time.c | 145 ++ arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 4 + drivers/usb/host/Kconfig | 4 +- drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-sead3.c | 299 ++++ drivers/video/Kconfig | 2 +- drivers/video/cobalt_lcdfb.c | 45 +- 49 files changed, 5029 insertions(+), 51 deletions(-) create mode 100644 arch/mips/configs/sead3_defconfig create mode 100644 arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-sead3/irq.h create mode 100644 arch/mips/include/asm/mach-sead3/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-sead3/war.h create mode 100644 arch/mips/include/asm/mips-boards/sead3int.h create mode 100644 arch/mips/mti-sead3/Makefile create mode 100644 arch/mips/mti-sead3/Platform create mode 100644 arch/mips/mti-sead3/leds-sead3.c create mode 100644 arch/mips/mti-sead3/sead3-cmdline.c create mode 100644 arch/mips/mti-sead3/sead3-console.c create mode 100644 arch/mips/mti-sead3/sead3-display.c create mode 100644 arch/mips/mti-sead3/sead3-ehci.c create mode 100644 arch/mips/mti-sead3/sead3-i2c-dev.c create mode 100644 arch/mips/mti-sead3/sead3-i2c.c create mode 100644 arch/mips/mti-sead3/sead3-init.c create mode 100644 arch/mips/mti-sead3/sead3-int.c create mode 100644 arch/mips/mti-sead3/sead3-lcd.c create mode 100644 arch/mips/mti-sead3/sead3-leds.c create mode 100644 arch/mips/mti-sead3/sead3-memory.c create mode 100644 arch/mips/mti-sead3/sead3-mtd.c create mode 100644 arch/mips/mti-sead3/sead3-net.c create mode 100644 arch/mips/mti-sead3/sead3-pic32-bus.c create mode 100644 arch/mips/mti-sead3/sead3-pic32-i2c-drv.c create mode 100644 arch/mips/mti-sead3/sead3-platform.c create mode 100644 arch/mips/mti-sead3/sead3-reset.c create mode 100644 arch/mips/mti-sead3/sead3-setup.c create mode 100644 arch/mips/mti-sead3/sead3-smtc.c create mode 100644 arch/mips/mti-sead3/sead3-time.c create mode 100644 drivers/usb/host/ehci-sead3.c -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:48:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:49:34 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36598 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904115Ab2DGQs5 (ORCPT ); Sat, 7 Apr 2012 18:48:57 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYok-0004dH-HV; Sat, 07 Apr 2012 11:48:50 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Douglas Leung , Chris Dearman Subject: [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform. Date: Sat, 7 Apr 2012 11:48:26 -0500 Message-Id: <1333817315-30091-2-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32879 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 77354 Lines: 2812 From: "Steven J. Hill" More information about the SEAD-3 platform can be found at on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- .../include/asm/mach-sead3/cpu-feature-overrides.h | 72 ++++ arch/mips/include/asm/mach-sead3/irq.h | 9 + .../include/asm/mach-sead3/kernel-entry-init.h | 52 +++ arch/mips/include/asm/mach-sead3/war.h | 25 ++ arch/mips/include/asm/mips-boards/sead3int.h | 67 +++ arch/mips/mti-sead3/Makefile | 24 ++ arch/mips/mti-sead3/Platform | 7 + arch/mips/mti-sead3/leds-sead3.c | 133 ++++++ arch/mips/mti-sead3/sead3-cmdline.c | 59 +++ arch/mips/mti-sead3/sead3-console.c | 52 +++ arch/mips/mti-sead3/sead3-display.c | 90 ++++ arch/mips/mti-sead3/sead3-ehci.c | 52 +++ arch/mips/mti-sead3/sead3-i2c-dev.c | 38 ++ arch/mips/mti-sead3/sead3-i2c.c | 42 ++ arch/mips/mti-sead3/sead3-init.c | 244 +++++++++++ arch/mips/mti-sead3/sead3-int.c | 146 +++++++ arch/mips/mti-sead3/sead3-lcd.c | 55 +++ arch/mips/mti-sead3/sead3-leds.c | 91 ++++ arch/mips/mti-sead3/sead3-memory.c | 178 ++++++++ arch/mips/mti-sead3/sead3-mtd.c | 58 +++ arch/mips/mti-sead3/sead3-net.c | 56 +++ arch/mips/mti-sead3/sead3-pic32-bus.c | 112 +++++ arch/mips/mti-sead3/sead3-pic32-i2c-drv.c | 441 ++++++++++++++++++++ arch/mips/mti-sead3/sead3-platform.c | 49 +++ arch/mips/mti-sead3/sead3-reset.c | 64 +++ arch/mips/mti-sead3/sead3-setup.c | 49 +++ arch/mips/mti-sead3/sead3-smtc.c | 162 +++++++ arch/mips/mti-sead3/sead3-time.c | 145 +++++++ 28 files changed, 2572 insertions(+) create mode 100644 arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-sead3/irq.h create mode 100644 arch/mips/include/asm/mach-sead3/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-sead3/war.h create mode 100644 arch/mips/include/asm/mips-boards/sead3int.h create mode 100644 arch/mips/mti-sead3/Makefile create mode 100644 arch/mips/mti-sead3/Platform create mode 100644 arch/mips/mti-sead3/leds-sead3.c create mode 100644 arch/mips/mti-sead3/sead3-cmdline.c create mode 100644 arch/mips/mti-sead3/sead3-console.c create mode 100644 arch/mips/mti-sead3/sead3-display.c create mode 100644 arch/mips/mti-sead3/sead3-ehci.c create mode 100644 arch/mips/mti-sead3/sead3-i2c-dev.c create mode 100644 arch/mips/mti-sead3/sead3-i2c.c create mode 100644 arch/mips/mti-sead3/sead3-init.c create mode 100644 arch/mips/mti-sead3/sead3-int.c create mode 100644 arch/mips/mti-sead3/sead3-lcd.c create mode 100644 arch/mips/mti-sead3/sead3-leds.c create mode 100644 arch/mips/mti-sead3/sead3-memory.c create mode 100644 arch/mips/mti-sead3/sead3-mtd.c create mode 100644 arch/mips/mti-sead3/sead3-net.c create mode 100644 arch/mips/mti-sead3/sead3-pic32-bus.c create mode 100644 arch/mips/mti-sead3/sead3-pic32-i2c-drv.c create mode 100644 arch/mips/mti-sead3/sead3-platform.c create mode 100644 arch/mips/mti-sead3/sead3-reset.c create mode 100644 arch/mips/mti-sead3/sead3-setup.c create mode 100644 arch/mips/mti-sead3/sead3-smtc.c create mode 100644 arch/mips/mti-sead3/sead3-time.c diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h new file mode 100644 index 0000000..7f3e3f9 --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h @@ -0,0 +1,72 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Chris Dearman + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H + + +/* + * CPU feature overrides for MIPS boards + */ +#ifdef CONFIG_CPU_MIPS32 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#ifdef CONFIG_CPU_HAS_LLSC +#define cpu_has_llsc 1 +#else +#define cpu_has_llsc 0 +#endif +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#ifdef CONFIG_CPU_MIPS64 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#define cpu_has_llsc 1 +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h new file mode 100644 index 0000000..652ea4c --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/irq.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_MIPS_IRQ_H +#define __ASM_MACH_MIPS_IRQ_H + +#define NR_IRQS 256 + + +#include_next + +#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h new file mode 100644 index 0000000..3dfbd8e --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Chris Dearman (chris@mips.com) + * Copyright (C) 2007 Mips Technologies, Inc. + */ +#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H +#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H + + .macro kernel_entry_setup +#ifdef CONFIG_MIPS_MT_SMTC + mfc0 t0, CP0_CONFIG + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 1 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 2 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 3 + and t0, 1<<2 + bnez t0, 0f +9 : + /* Assume we came from YAMON... */ + PTR_LA v0, 0x9fc00534 /* YAMON print */ + lw v0, (v0) + move a0, zero + PTR_LA a1, nonmt_processor + jal v0 + + PTR_LA v0, 0x9fc00520 /* YAMON exit */ + lw v0, (v0) + li a0, 1 + jal v0 + +1 : b 1b + + __INITDATA +nonmt_processor : + .asciz "SMTC kernel requires the MT ASE to run\n" + __FINIT +0 : +#endif + .endm + +/* + * Do SMP slave processor setup necessary before we can safely execute C code. + */ + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h new file mode 100644 index 0000000..7c6931d --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h new file mode 100644 index 0000000..2563b82 --- /dev/null +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -0,0 +1,67 @@ +/* + * Douglas Leung, douglas@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Defines for the SEAD3 interrupt controller. + * + */ +#ifndef _MIPS_SEAD3INT_H +#define _MIPS_SEAD3INT_H + +/* + * SEAD3 GIC's address space definitions + */ +#define GIC_BASE_ADDR 0x1b1c0000 +#define GIC_ADDRSPACE_SZ (128 * 1024) + +/* GIC's Nomenclature for Core Interrupt Pins on the SEAD3 */ +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ +#define GIC_CPU_INT1 1 /* . */ +#define GIC_CPU_INT2 2 /* . */ +#define GIC_CPU_INT3 3 /* . */ +#define GIC_CPU_INT4 4 /* . */ +#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ + +/* SEAD3 GIC local interrupts */ +#define GIC_INT_TMR (GIC_CPU_INT5) +#define GIC_INT_PERFCTR (GIC_CPU_INT5) + +/* SEAD3 GIC constants */ +/* Add 2 to convert non-eic hw int # to eic vector # */ +#define GIC_CPU_TO_VEC_OFFSET (2) + +/* GIC constants */ +/* If we map an intr to pin X, GIC will actually generate vector X+1 */ +#define GIC_PIN_TO_VEC_OFFSET (1) + +#define GIC_EXT_INTR(x) x + +/* Dummy data */ +#define X 0xdead + +/* External Interrupts used for IPI */ +/* Currently linux don't know about GIC => GIC base must be same as what Linux is using */ +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) + +#ifndef __ASSEMBLY__ +extern void sead3int_init(void); +#endif + +#endif /* !(_MIPS_SEAD3INT_H) */ diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile new file mode 100644 index 0000000..8797977 --- /dev/null +++ b/arch/mips/mti-sead3/Makefile @@ -0,0 +1,24 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# Copyright (C) 2008 Wind River Systems, Inc. +# written by Ralf Baechle +# +obj-y := sead3-lcd.o sead3-cmdline.o \ + sead3-display.o sead3-init.o sead3-int.o \ + sead3-mtd.o sead3-net.o \ + sead3-memory.o sead3-platform.o \ + sead3-reset.o sead3-setup.o sead3-time.o + +obj-y += sead3-i2c-dev.o sead3-i2c.o \ + sead3-pic32-i2c-drv.o sead3-pic32-bus.o \ + leds-sead3.o sead3-leds.o + +obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o +obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o + +# FIXME +obj-$(CONFIG_MIPS_MT_SMTC) += sead3-smtc.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mti-sead3/Platform b/arch/mips/mti-sead3/Platform new file mode 100644 index 0000000..596e484 --- /dev/null +++ b/arch/mips/mti-sead3/Platform @@ -0,0 +1,7 @@ +# +# MIPS Sead3 board +# +platform-$(CONFIG_MIPS_SEAD3) += mti-sead3/ +cflags-$(CONFIG_MIPS_SEAD3) += -I$(srctree)/arch/mips/include/asm/mach-sead3 +load-$(CONFIG_MIPS_SEAD3) += 0xffffffff80100000 +all-$(CONFIG_MIPS_SEAD3) := $(COMPRESSION_FNAME).srec diff --git a/arch/mips/mti-sead3/leds-sead3.c b/arch/mips/mti-sead3/leds-sead3.c new file mode 100644 index 0000000..89954ce --- /dev/null +++ b/arch/mips/mti-sead3/leds-sead3.c @@ -0,0 +1,133 @@ +/* + * LEDs driver for SEAD3 + * + * Copyright (C) 2006 Kristian Kielhofner + * + * Based on leds-wrap.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "sead3-led" + +static struct platform_device *pdev; + +static void sead3_pled_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + pr_debug("sead3_pled_set\n"); + writel(value, (void __iomem *)0xBF000210); /* FIXME */ +} + +static void sead3_fled_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + pr_debug("sead3_fled_set\n"); + writel(value, (void __iomem *)0xBF000218); /* FIXME */ +} + +static struct led_classdev sead3_pled = { + .name = "sead3::pled", + .brightness_set = sead3_pled_set, +}; + +static struct led_classdev sead3_fled = { + .name = "sead3::fled", + .brightness_set = sead3_fled_set, +}; + +#ifdef CONFIG_PM +static int sead3_led_suspend(struct platform_device *dev, + pm_message_t state) +{ + led_classdev_suspend(&sead3_pled); + led_classdev_suspend(&sead3_fled); + return 0; +} + +static int sead3_led_resume(struct platform_device *dev) +{ + led_classdev_resume(&sead3_pled); + led_classdev_resume(&sead3_fled); + return 0; +} +#else +#define sead3_led_suspend NULL +#define sead3_led_resume NULL +#endif + +static int sead3_led_probe(struct platform_device *pdev) +{ + int ret; + + ret = led_classdev_register(&pdev->dev, &sead3_pled); + if (ret < 0) + return ret; + + ret = led_classdev_register(&pdev->dev, &sead3_fled); + if (ret < 0) + led_classdev_unregister(&sead3_pled); + + return ret; +} + +static int sead3_led_remove(struct platform_device *pdev) +{ + led_classdev_unregister(&sead3_pled); + led_classdev_unregister(&sead3_fled); + return 0; +} + +static struct platform_driver sead3_led_driver = { + .probe = sead3_led_probe, + .remove = sead3_led_remove, + .suspend = sead3_led_suspend, + .resume = sead3_led_resume, + .driver = { + .name = DRVNAME, + .owner = THIS_MODULE, + }, +}; + +static int __init sead3_led_init(void) +{ + int ret; + + ret = platform_driver_register(&sead3_led_driver); + if (ret < 0) + goto out; + + pdev = platform_device_register_simple(DRVNAME, -1, NULL, 0); + if (IS_ERR(pdev)) { + ret = PTR_ERR(pdev); + platform_driver_unregister(&sead3_led_driver); + goto out; + } + +out: + return ret; +} + +static void __exit sead3_led_exit(void) +{ + platform_device_unregister(pdev); + platform_driver_unregister(&sead3_led_driver); +} + +module_init(sead3_led_init); +module_exit(sead3_led_exit); + +MODULE_AUTHOR("Kristian Kielhofner "); +MODULE_DESCRIPTION("SEAD3 LED driver"); +MODULE_LICENSE("GPL"); + diff --git a/arch/mips/mti-sead3/sead3-cmdline.c b/arch/mips/mti-sead3/sead3-cmdline.c new file mode 100644 index 0000000..8d6ad39 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-cmdline.c @@ -0,0 +1,59 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Kernel command line creation using the prom monitor (YAMON) argc/argv. + */ +#include +#include + +#include + +extern int prom_argc; +extern int *_prom_argv; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while (actr < prom_argc) { + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) { + /* get rid of trailing space */ + --cp; + *cp = '\0'; + } +} diff --git a/arch/mips/mti-sead3/sead3-console.c b/arch/mips/mti-sead3/sead3-console.c new file mode 100644 index 0000000..a799a5d --- /dev/null +++ b/arch/mips/mti-sead3/sead3-console.c @@ -0,0 +1,52 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include +#include +#include +#include + + +#define SEAD_UART1_REGS_BASE 0xbf000800 /* ttyS1 = RS232 port */ +#define SEAD_UART0_REGS_BASE 0xbf000900 /* ttyS0 = USB port */ + +#define PORT(base_addr, offset) ((unsigned int __iomem *)(base_addr+(offset)*4)) + +static inline unsigned int serial_in(int offset, unsigned int base_addr) +{ + return __raw_readl(PORT(base_addr, offset)) & 0xff; +} + +static inline void serial_out(int offset, int value, unsigned int base_addr) +{ + __raw_writel(value, PORT(base_addr, offset)); +} + +int prom_putchar(char c, char port) +{ + unsigned int base_addr; + + base_addr = port ? SEAD_UART1_REGS_BASE : SEAD_UART0_REGS_BASE; + + while ((serial_in(UART_LSR, base_addr) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c, base_addr); + + return 1; +} diff --git a/arch/mips/mti-sead3/sead3-display.c b/arch/mips/mti-sead3/sead3-display.c new file mode 100644 index 0000000..f6e2231 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-display.c @@ -0,0 +1,90 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#include +#include +#include +#include +#include + +extern const char display_string[]; +static unsigned int display_count; +static unsigned int max_display_count; + +#define DISPLAY_LCDINSTRUCTION (0*2) +#define DISPLAY_LCDDATA (1*2) +#define DISPLAY_CPLDSTATUS (2*2) +#define DISPLAY_CPLDDATA (3*2) +#define LCD_SETDDRAM 0x80 +#define LCD_IR_BF 0x80 + +static void lcd_wait(unsigned int __iomem *display) +{ + /* wait for CPLD state machine to become idle */ + do { + } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); + + do { + __raw_readl(display + DISPLAY_LCDINSTRUCTION); + + /* wait for CPLD state machine to become idle */ + do { + } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); + } while (__raw_readl(display + DISPLAY_CPLDDATA) & LCD_IR_BF); +} + +void mips_display_message(const char *str) +{ + static unsigned int __iomem *display; /* static => auto initialized to NULL */ + int i; + char ch; + + if (unlikely(display == NULL)) + display = ioremap_nocache(LCD_DISPLAY_POS_BASE, 4*2*sizeof(int)); + + for (i = 0; i < 16; i++) { + if (*str) + ch = *str++; + else + ch = ' '; + lcd_wait(display); + __raw_writel(LCD_SETDDRAM | i, display + DISPLAY_LCDINSTRUCTION); + lcd_wait(display); + __raw_writel(ch, display + DISPLAY_LCDDATA); + } +} + +static void scroll_display_message(unsigned long data); +static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0); + +static void scroll_display_message(unsigned long data) +{ + mips_display_message(&display_string[display_count++]); + if (display_count == max_display_count) + display_count = 0; + + mod_timer(&mips_scroll_timer, jiffies + HZ); +} + +void mips_scroll_message(void) +{ + del_timer_sync(&mips_scroll_timer); + max_display_count = strlen(display_string) + 1 - 16; + mod_timer(&mips_scroll_timer, jiffies + 1); +} diff --git a/arch/mips/mti-sead3/sead3-ehci.c b/arch/mips/mti-sead3/sead3-ehci.c new file mode 100644 index 0000000..07aaa5d --- /dev/null +++ b/arch/mips/mti-sead3/sead3-ehci.c @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 MIPS Technologies, vInc. + * written by Chris Dearman (chris@mips.com) + * + * Probe driver for the SEAD3 EHCI device + * + */ +#include +#include +#include +#include +#include + +struct resource ehci_resources[] = { + { + .start = 0x1b200000, + .end = 0x1b200fff, + .flags = IORESOURCE_MEM + }, + { + .start = MIPS_CPU_IRQ_BASE + 2, + .flags = IORESOURCE_IRQ + } +}; + +u64 sead3_usbdev_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device ehci_device = { + .name = "ci13xxx-ehci", + .id = 0, + .dev = { + .dma_mask = &sead3_usbdev_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32) + }, + .num_resources = ARRAY_SIZE(ehci_resources), + .resource = ehci_resources +}; + +static int __init ehci_init(void) +{ + return platform_device_register(&ehci_device); +} + +module_init(ehci_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("EHCI probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-i2c-dev.c b/arch/mips/mti-sead3/sead3-i2c-dev.c new file mode 100644 index 0000000..7e7a911 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c-dev.c @@ -0,0 +1,38 @@ +#define DEBUG +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include + +static struct i2c_board_info sead3_i2c_info2[] __initdata = { + { + I2C_BOARD_INFO("adt7476", 0x2c), + .irq = 0, + }, + { + I2C_BOARD_INFO("m41t80", 0x68), + .irq = 0, + }, +}; + +static int __init sead3_i2c_init(void) +{ + int err; + + pr_debug("sead3_i2c_init\n"); + + err = i2c_register_board_info(2, sead3_i2c_info2, + ARRAY_SIZE(sead3_i2c_info2)); + if (err < 0) + printk(KERN_ERR + "sead3-i2c-dev: cannot register board I2C devices\n"); + return err; +} + +arch_initcall(sead3_i2c_init); diff --git a/arch/mips/mti-sead3/sead3-i2c.c b/arch/mips/mti-sead3/sead3-i2c.c new file mode 100644 index 0000000..bf5f8d3 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c.c @@ -0,0 +1,42 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 MIPS Technologies, Inc. + * written by Ralf Baechle (ralf@linux-mips.org) + * + * Probe driver for the SEAD3 network device + * + */ +#include +#include +#include +#include + + +struct resource i2c_resources[] = { + { + .start = 0x805200, + .end = 0x8053FF, + .flags = IORESOURCE_MEM + }, +}; + +static struct platform_device i2c_device = { + .name = "i2c_pic32", + .id = 2, + .num_resources = ARRAY_SIZE(i2c_resources), + .resource = i2c_resources +}; + +static int __init i2c_init(void) +{ + return platform_device_register(&i2c_device); +} + +module_init(i2c_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("I2C probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c new file mode 100644 index 0000000..14e0c49 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-init.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library initialisation code. + */ +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +int prom_argc; +int *_prom_argv, *_prom_envp; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension, if running in 64-bit mode. + */ +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +int init_debug; /* global var => auto initialized to 0 */ + +int mips_revision_corid; +int mips_revision_sconid; + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index = 0; + + i = strlen(envname); + + while (prom_envp(index)) { + if (strncmp(envname, prom_envp(index), i) == 0) + return prom_envp(index+1); + index += 2; + } + + return NULL; +} + +static inline unsigned char str2hexnum(unsigned char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return 0; /* foo */ +} + +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if ((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + + if (init_debug > 1) { + int i; + printk("get_ethernet_addr: "); + for (i = 0; i < 5; i++) + printk("%02x:", (unsigned char)*(ethernet_addr+i)); + printk("%02x\n", *(ethernet_addr+i)); + } + + return 0; +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static void __init console_config(void) +{ + char console_string[40]; + int baud = 0; + char parity = '\0', bits = '\0', flow = '\0'; + char *s; + + if ((strstr(prom_getcmdline(), "console=")) == NULL) { + s = prom_getenv("modetty0"); + if (s) { + while (*s >= '0' && *s <= '9') + baud = baud*10 + *s++ - '0'; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; + } + if (baud == 0) + baud = 38400; + if (parity != 'n' && parity != 'o' && parity != 'e') + parity = 'n'; + if (bits != '7' && bits != '8') + bits = '8'; + if (flow == '\0') + flow = 'r'; + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + strcat(prom_getcmdline(), console_string); + pr_info("Config serial console:%s\n", console_string); + } +} +#endif + +static void __init mips_nmi_setup(void) +{ + void *base; + extern char except_vec_nmi; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); + memcpy(base, &except_vec_nmi, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +static void __init mips_ejtag_setup(void) +{ + void *base; + extern char except_vec_ejtag_debug; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); + memcpy(base, &except_vec_ejtag_debug, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +extern struct plat_smp_ops msmtc_smp_ops; + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + _prom_argv = (int *) fw_arg1; + _prom_envp = (int *) fw_arg2; + + mips_display_message("LINUX"); + + mips_revision_corid = MIPS_REVISION_CORID; + mips_revision_sconid = MIPS_REVISION_SCONID; + if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { + switch (mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_FPGAR2: + mips_revision_sconid = MIPS_REVISION_SCON_GT64120; + break; + case MIPS_REVISION_CORID_CORE_EMUL_BON: + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + mips_revision_sconid = MIPS_REVISION_SCON_BONITO; + break; + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_24K: + /* + * SOCit/ROCit support is essentially identical + * but make an attempt to distinguish them + */ + mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; + break; + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_FPGA4: + case MIPS_REVISION_CORID_CORE_FPGA5: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: + default: + /* See above */ + mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; + break; + } + } + + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + + pr_info("\nLINUX started...\n"); + prom_init_cmdline(); + prom_meminit(); +#ifdef CONFIG_SERIAL_8250_CONSOLE + console_config(); +#endif +#ifdef CONFIG_MIPS_CMP + register_smp_ops(&cmp_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMP + register_smp_ops(&vsmp_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&msmtc_smp_ops); +#endif +} diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c new file mode 100644 index 0000000..4cd569e --- /dev/null +++ b/arch/mips/mti-sead3/sead3-int.c @@ -0,0 +1,146 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines for generic manipulation of the interrupts found on the MIPS + * Malta board. + * The interrupt controller is located in the South Bridge a PIIX4 device + * with two internal 82C95 interrupt controllers. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define SEAD_CONFIG_GIC_PRESENT_SHF (1) +#define SEAD_CONFIG_GIC_PRESENT_MSK (1 << SEAD_CONFIG_GIC_PRESENT_SHF) +#define SEAD_CONFIG_BASE (0x1B100110) +#define SEAD_CONFIG_SIZE (4) + +int gic_present; /* global var => auto initialized to 0 */ +static unsigned long sead3_config_reg; + +/* + * This table defines the setup for each external GIC interrupt + * It is indexed by interrupt number + */ +#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + /* The remainder of this table is initialised by fill_ipi_map */ +}; + +/* + * Version of ffs that only looks at bits 8..15 + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + return fls(pending) - CAUSEB_IP - 1; +#else + unsigned int a0 = 7; + unsigned int t0; + + t0 = pending & 0xf000; + t0 = t0 < 1; + t0 = t0 << 2; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0xc000; + t0 = t0 < 1; + t0 = t0 << 1; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0x8000; + t0 = t0 < 1; + /* t0 = t0 << 2; */ + a0 = a0 - t0; + /* pending = pending << t0; */ + + return a0; +#endif +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = irq_ffs(pending); + + if (irq >= 0) + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + int i; + + if (!cpu_has_veic) { + mips_cpu_irq_init(); + + if (cpu_has_vint) { + /* install generic handler */ + for (i = 0; i < 8; i++) + set_vi_handler(i, plat_irq_dispatch); + } + } + + sead3_config_reg = (unsigned long)ioremap_nocache(SEAD_CONFIG_BASE, SEAD_CONFIG_SIZE); + gic_present = (REG32(sead3_config_reg) & SEAD_CONFIG_GIC_PRESENT_MSK) >> + SEAD_CONFIG_GIC_PRESENT_SHF; + printk("GIC: %spresent\n", (gic_present) ? "" : "not "); + printk("EIC: %s\n", (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off"); + + if (gic_present) { + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); + } +} + diff --git a/arch/mips/mti-sead3/sead3-lcd.c b/arch/mips/mti-sead3/sead3-lcd.c new file mode 100644 index 0000000..654b447 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-lcd.c @@ -0,0 +1,55 @@ +/* + * Registration of Sead3 LCD platform device. + * + * Copyright (C) 2008 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include + +static struct resource sead3_lcd_resource __initdata = { + .start = 0x1f000400, + .end = 0x1f00041f, + .flags = IORESOURCE_MEM, +}; + +static __init int sead3_lcd_add(void) +{ + struct platform_device *pdev; + int retval; + + pdev = platform_device_alloc("cobalt-lcd", -1); + if (!pdev) + return -ENOMEM; + + retval = platform_device_add_resources(pdev, &sead3_lcd_resource, 1); + if (retval) + goto err_free_device; + + retval = platform_device_add(pdev); + if (retval) + goto err_free_device; + + return 0; + +err_free_device: + platform_device_put(pdev); + + return retval; +} +device_initcall(sead3_lcd_add); diff --git a/arch/mips/mti-sead3/sead3-leds.c b/arch/mips/mti-sead3/sead3-leds.c new file mode 100644 index 0000000..ff003d2 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-leds.c @@ -0,0 +1,91 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 MIPS Technologies, Inc. + * written by Chris Dearman (chris@mips.com) + * + * Probe driver for the SEAD3 LED devices + * + */ +#include +#include +#include +#include +#include + + +#define LEDFLAGS(bits, shift) \ + ((bits << 8) | (shift << 8)) + +#define LEDBITS(id, shift, bits) \ + .name = id #shift, \ + .flags = LEDFLAGS(bits, shift) + +struct led_info led_data_info[] = { + { LEDBITS("bit", 0, 1) }, + { LEDBITS("bit", 1, 1) }, + { LEDBITS("bit", 2, 1) }, + { LEDBITS("bit", 3, 1) }, + { LEDBITS("bit", 4, 1) }, + { LEDBITS("bit", 5, 1) }, + { LEDBITS("bit", 6, 1) }, + { LEDBITS("bit", 7, 1) }, + { LEDBITS("all", 0, 8) }, +}; + +static struct led_platform_data led_data = { + .num_leds = ARRAY_SIZE(led_data_info), + .leds = led_data_info +}; + +static struct resource pled_resources[] = { + { + .start = 0x1F000210, + .end = 0x1F000217, + .flags = IORESOURCE_MEM + } +}; + +static struct platform_device pled_device = { + .name = "sead3::pled", + .id = 0, + .dev = { + .platform_data = &led_data, + }, + .num_resources = ARRAY_SIZE(pled_resources), + .resource = pled_resources +}; + + +static struct resource fled_resources[] = { + { + .start = 0x1F000218, + .end = 0x1F00021f, + .flags = IORESOURCE_MEM + } +}; + +static struct platform_device fled_device = { + .name = "sead3::fled", + .id = 0, + .dev = { + .platform_data = &led_data, + }, + .num_resources = ARRAY_SIZE(fled_resources), + .resource = fled_resources +}; + + +static int __init led_init(void) +{ + platform_device_register(&pled_device); + return platform_device_register(&fled_device); +} + +module_init(led_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("LED probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-memory.c b/arch/mips/mti-sead3/sead3-memory.c new file mode 100644 index 0000000..b27419c --- /dev/null +++ b/arch/mips/mti-sead3/sead3-memory.c @@ -0,0 +1,178 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library functions for acquiring/using memory descriptors given to + * us from the YAMON. + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/*#define DEBUG*/ + +enum yamon_memtypes { + yamon_dontuse, + yamon_prom, + yamon_free, +}; +static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +#ifdef DEBUG +static char *mtypes[3] = { + "Dont use memory", + "YAMON PROM memory", + "Free memmory", +}; +#endif + +/* determined physical memory size, not overridden by command line args */ +unsigned long physical_memsize = 0L; + +static struct prom_pmemblock * __init prom_getmdesc(void) +{ + char *memsize_str; + unsigned int memsize; + char *ptr; + static char cmdline[COMMAND_LINE_SIZE] __initdata; + + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + printk(KERN_WARNING + "memsize not set in boot prom, set to default (32Mb)\n"); + physical_memsize = 0x02000000; + } else { +#ifdef DEBUG + pr_debug("prom_memsize = %s\n", memsize_str); +#endif + physical_memsize = simple_strtol(memsize_str, NULL, 0); + } + +#ifdef CONFIG_CPU_BIG_ENDIAN + /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last + word of physical memory */ + physical_memsize -= PAGE_SIZE; +#endif + + /* Check the command line for a memsize directive that overrides + the physical/default amount */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) + memsize = memparse(ptr + 8, &ptr); + else + memsize = physical_memsize; + + memset(mdesc, 0, sizeof(mdesc)); + + mdesc[0].type = yamon_dontuse; + mdesc[0].base = 0x00000000; + mdesc[0].size = 0x00001000; + + mdesc[1].type = yamon_prom; + mdesc[1].base = 0x00001000; + mdesc[1].size = 0x000ef000; + + /* + * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the + * south bridge and PCI access always forwarded to the ISA Bus and + * BIOSCS# is always generated. + * This mean that this area can't be used as DMA memory for PCI + * devices. + */ + mdesc[2].type = yamon_dontuse; + mdesc[2].base = 0x000f0000; + mdesc[2].size = 0x00010000; + + mdesc[3].type = yamon_dontuse; + mdesc[3].base = 0x00100000; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; + + mdesc[4].type = yamon_free; + mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[4].size = memsize - mdesc[4].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify(unsigned int type) +{ + switch (type) { + case yamon_free: + return BOOT_MEM_RAM; + case yamon_prom: + return BOOT_MEM_ROM_DATA; + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + +#ifdef DEBUG + pr_debug("YAMON MEMORY DESCRIPTOR dump:\n"); + p = prom_getmdesc(); + while (p->size) { + int i = 0; + pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", + i, p, p->base, p->size, mtypes[p->type]); + p++; + i++; + } +#endif + p = prom_getmdesc(); + + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify(p->type); + base = p->base; + size = p->size; + + add_memory_region(base, size, type); + p++; + } +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/mti-sead3/sead3-mtd.c b/arch/mips/mti-sead3/sead3-mtd.c new file mode 100644 index 0000000..30450b4 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-mtd.c @@ -0,0 +1,58 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 MIPS Technologies, Inc. + * written by Ralf Baechle + */ + +#include +#include +#include +#include +#include + +static struct mtd_partition sead3_mtd_partitions[] = { + { + .name = "User FS", + .offset = 0x00000000, + .size = 0x01fc0000, + }, { + .name = "Board Config", + .offset = 0x01fc0000, + .size = 0x00040000, + .mask_flags = MTD_WRITEABLE + }, +}; + +static struct physmap_flash_data sead3_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(sead3_mtd_partitions), + .parts = sead3_mtd_partitions +}; + +static struct resource sead3_flash_resource = { + .start = 0x1c000000, + .end = 0x1dffffff, + .flags = IORESOURCE_MEM +}; + +static struct platform_device sead3_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &sead3_flash_data, + }, + .num_resources = 1, + .resource = &sead3_flash_resource, +}; + +static int __init sead3_mtd_init(void) +{ + platform_device_register(&sead3_flash); + + return 0; +} + +module_init(sead3_mtd_init) diff --git a/arch/mips/mti-sead3/sead3-net.c b/arch/mips/mti-sead3/sead3-net.c new file mode 100644 index 0000000..1a5018d --- /dev/null +++ b/arch/mips/mti-sead3/sead3-net.c @@ -0,0 +1,56 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007-2011 MIPS Technologies, Inc. + * written by Ralf Baechle (ralf@linux-mips.org) + * + * Probe driver for the SEAD3 network device + * + */ +#include +#include +#include +#include +#include + +static struct smsc911x_platform_config net_data = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +struct resource net_resources[] = { + { + .start = 0x1f010000, + .end = 0x1f01ffff, + .flags = IORESOURCE_MEM + }, + { + .start = MIPS_CPU_IRQ_BASE + 6, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device net_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &net_data, + }, + .num_resources = ARRAY_SIZE(net_resources), + .resource = net_resources +}; + +static int __init net_init(void) +{ + return platform_device_register(&net_device); +} + +module_init(net_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Network probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c new file mode 100644 index 0000000..b0bb326 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-pic32-bus.c @@ -0,0 +1,112 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include + +#define PIC32_NULL 0x00 +#define PIC32_RD 0x01 +#define PIC32_SYSRD 0x02 +#define PIC32_WR 0x10 +#define PIC32_SYSWR 0x20 +#define PIC32_IRQ_CLR 0x40 +#define PIC32_STATUS 0x80 + +#define DELAY() udelay(100) /* FIXME: needed? */ + +/* spinlock to ensure atomic access to PIC32 */ +static DEFINE_SPINLOCK(pic32_bus_lock); + +/* FIXME: io_remap these */ +static void __iomem *bus_xfer = (void __iomem *)0xbf000600; +static void __iomem *bus_status = (void __iomem *)0xbf000060; + +static inline unsigned int ioready(void) +{ + return readl(bus_status) & 1; +} + +static inline void wait_ioready(void) +{ + do { } while (!ioready()); +} + +static inline void wait_ioclear(void) +{ + do { } while (ioready()); +} + +static inline void check_ioclear(void) +{ + if (ioready()) { + pr_debug("ioclear: initially busy\n"); + do { + (void) readl(bus_xfer); + DELAY(); + } while (ioready()); + pr_debug("ioclear: cleared busy\n"); + } +} + +u32 pic32_bus_readl(u32 reg) +{ + unsigned long flags; + u32 status, val; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + + writel((PIC32_RD << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + DELAY(); + val = readl(bus_xfer); + wait_ioclear(); + + pr_debug("pic32_bus_readl: *%x -> %x (status=%x)\n", reg, val, status); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); + + return val; +} + +void pic32_bus_writel(u32 val, u32 reg) +{ + unsigned long flags; + u32 status; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + + writel((PIC32_WR << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + writel(val, bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + wait_ioclear(); + + pr_debug("pic32_bus_writel: *%x <- %x (status=%x)\n", reg, val, status); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); +} diff --git a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c new file mode 100644 index 0000000..053b23e --- /dev/null +++ b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c @@ -0,0 +1,441 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PIC32_I2CxCON 0x0000 +#define PIC32_I2CxCONCLR 0x0004 +#define PIC32_I2CxCONSET 0x0008 +#define PIC32_I2CxCONINV 0x000C +#define I2CCON_ON (1<<15) +#define I2CCON_FRZ (1<<14) +#define I2CCON_SIDL (1<<13) +#define I2CCON_SCLREL (1<<12) +#define I2CCON_STRICT (1<<11) +#define I2CCON_A10M (1<<10) +#define I2CCON_DISSLW (1<<9) +#define I2CCON_SMEN (1<<8) +#define I2CCON_GCEN (1<<7) +#define I2CCON_STREN (1<<6) +#define I2CCON_ACKDT (1<<5) +#define I2CCON_ACKEN (1<<4) +#define I2CCON_RCEN (1<<3) +#define I2CCON_PEN (1<<2) +#define I2CCON_RSEN (1<<1) +#define I2CCON_SEN (1<<0) + +#define PIC32_I2CxSTAT 0x0010 +#define PIC32_I2CxSTATCLR 0x0014 +#define PIC32_I2CxSTATSET 0x0018 +#define PIC32_I2CxSTATINV 0x001C +#define I2CSTAT_ACKSTAT (1<<15) +#define I2CSTAT_TRSTAT (1<<14) +#define I2CSTAT_BCL (1<<10) +#define I2CSTAT_GCSTAT (1<<9) +#define I2CSTAT_ADD10 (1<<8) +#define I2CSTAT_IWCOL (1<<7) +#define I2CSTAT_I2COV (1<<6) +#define I2CSTAT_DA (1<<5) +#define I2CSTAT_P (1<<4) +#define I2CSTAT_S (1<<3) +#define I2CSTAT_RW (1<<2) +#define I2CSTAT_RBF (1<<1) +#define I2CSTAT_TBF (1<<0) + +#define PIC32_I2CxADD 0x0020 +#define PIC32_I2CxADDCLR 0x0024 +#define PIC32_I2CxADDSET 0x0028 +#define PIC32_I2CxADDINV 0x002C +#define PIC32_I2CxMSK 0x0030 +#define PIC32_I2CxMSKCLR 0x0034 +#define PIC32_I2CxMSKSET 0x0038 +#define PIC32_I2CxMSKINV 0x003C +#define PIC32_I2CxBRG 0x0040 +#define PIC32_I2CxBRGCLR 0x0044 +#define PIC32_I2CxBRGSET 0x0048 +#define PIC32_I2CxBRGINV 0x004C +#define PIC32_I2CxTRN 0x0050 +#define PIC32_I2CxTRNCLR 0x0054 +#define PIC32_I2CxTRNSET 0x0058 +#define PIC32_I2CxTRNINV 0x005C +#define PIC32_I2CxRCV 0x0060 + +struct i2c_platform_data { + u32 base; + struct i2c_adapter adap; + u32 xfer_timeout; + u32 ack_timeout; + u32 ctl_timeout; +}; + +extern u32 pic32_bus_readl(u32 reg); +extern void pic32_bus_writel(u32 val, u32 reg); + +static inline void +StartI2C(struct i2c_platform_data *adap) +{ + pr_debug("StartI2C\n"); + pic32_bus_writel(I2CCON_SEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +StopI2C(struct i2c_platform_data *adap) +{ + pr_debug("StopI2C\n"); + pic32_bus_writel(I2CCON_PEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +AckI2C(struct i2c_platform_data *adap) +{ + pr_debug("AckI2C\n"); + pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR); + pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +NotAckI2C(struct i2c_platform_data *adap) +{ + pr_debug("NakI2C\n"); + pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET); + pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline int +IdleI2C(struct i2c_platform_data *adap) +{ + int i; + + pr_debug("IdleI2C\n"); + for (i = 0; i < adap->ctl_timeout; i++) { + if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) & + (I2CCON_ACKEN|I2CCON_RCEN|I2CCON_PEN|I2CCON_RSEN|I2CCON_SEN)) == 0) && + ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + (I2CSTAT_TRSTAT)) == 0)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static inline u32 +MasterWriteI2C(struct i2c_platform_data *adap, u32 byte) +{ + pr_debug("MasterWriteI2C\n"); + + pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN); + + return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_IWCOL; +} + +static inline u32 +MasterReadI2C(struct i2c_platform_data *adap) +{ + pr_debug("MasterReadI2C\n"); + + pic32_bus_writel(I2CCON_RCEN, adap->base + PIC32_I2CxCONSET); + + while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & I2CCON_RCEN) + ; + + pic32_bus_writel(I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR); + + return pic32_bus_readl(adap->base + PIC32_I2CxRCV); +} + +static int +do_address(struct i2c_platform_data *adap, unsigned int addr, int rd) +{ + pr_debug("doaddress\n"); + + IdleI2C(adap); + StartI2C(adap); + IdleI2C(adap); + + addr <<= 1; + if (rd) + addr |= 1; + + if (MasterWriteI2C(adap, addr)) + return -EIO; + IdleI2C(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_ACKSTAT) + return -EIO; + return 0; +} + +static int +i2c_read(struct i2c_platform_data *adap, unsigned char *buf, + unsigned int len) +{ + int i; + u32 data; + + pr_debug("i2c_read\n"); + + i = 0; + while (i < len) { + data = MasterReadI2C(adap); + buf[i++] = data; + if (i < len) + AckI2C(adap); + else + NotAckI2C(adap); + } + + StopI2C(adap); + IdleI2C(adap); + return 0; +} + +static int +i2c_write(struct i2c_platform_data *adap, unsigned char *buf, + unsigned int len) +{ + int i; + u32 data; + + pr_debug("i2c_write\n"); + + i = 0; + while (i < len) { + data = buf[i]; + if (MasterWriteI2C(adap, data)) + return -EIO; + IdleI2C(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_ACKSTAT) + return -EIO; + i++; + } + + StopI2C(adap); + IdleI2C(adap); + return 0; +} + +static int +platform_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) +{ + struct i2c_platform_data *adap = i2c_adap->algo_data; + struct i2c_msg *p; + int i, err = 0; + + pr_debug("platform_xfer\n"); + for (i = 0; i < num; i++) { +#define __BUFSIZE 80 + int ii; + static char buf[__BUFSIZE]; + char *b = buf; + + p = &msgs[i]; + b += sprintf(buf, " [%d bytes]", p->len); + if ((p->flags & I2C_M_RD) == 0) { + for (ii = 0; ii < p->len; ii++) { + if (b < &buf[__BUFSIZE-4]) { + b += sprintf(b, " %02x", p->buf[ii]); + } else { + strcat(b, "..."); + break; + } + } + } + pr_debug("xfer%d: DevAddr: %04x Op:%s Data:%s\n", i, p->addr, + (p->flags & I2C_M_RD) ? "Rd" : "Wr", buf); + } + + + for (i = 0; !err && i < num; i++) { + p = &msgs[i]; + err = do_address(adap, p->addr, p->flags & I2C_M_RD); + if (err || !p->len) + continue; + if (p->flags & I2C_M_RD) + err = i2c_read(adap, p->buf, p->len); + else + err = i2c_write(adap, p->buf, p->len); + } + + /* Return the number of messages processed, or the error code. */ + if (err == 0) + err = num; + + return err; +} + +static u32 +platform_func(struct i2c_adapter *adap) +{ + pr_debug("platform_algo\n"); + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm platform_algo = { + .master_xfer = platform_xfer, + .functionality = platform_func, +}; + +static void i2c_platform_setup(struct i2c_platform_data *priv) +{ + pr_debug("i2c_platform_setup\n"); + + pic32_bus_writel(500, priv->base + PIC32_I2CxBRG); + pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONCLR); + pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONSET); + pic32_bus_writel(I2CSTAT_BCL|I2CSTAT_IWCOL, priv->base + PIC32_I2CxSTATCLR); +} + +static void i2c_platform_disable(struct i2c_platform_data *priv) +{ + pr_debug("i2c_platform_disable\n"); +} + +static int __devinit +i2c_platform_probe(struct platform_device *pdev) +{ + struct i2c_platform_data *priv; + struct resource *r; + int ret; + + pr_debug("i2c_platform_probe\n"); + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENODEV; + goto out; + } + + priv = kzalloc(sizeof(struct i2c_platform_data), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + goto out; + } + + /* FIXME: need to allocate resource in PIC32 space */ +#if 0 + priv->base = bus_request_region(r->start, resource_size(r), + pdev->name); +#else + priv->base = r->start; +#endif + if (!priv->base) { + ret = -EBUSY; + goto out_mem; + } + + priv->xfer_timeout = 200; + priv->ack_timeout = 200; + priv->ctl_timeout = 200; + + priv->adap.nr = pdev->id; + priv->adap.algo = &platform_algo; + priv->adap.algo_data = priv; + priv->adap.dev.parent = &pdev->dev; + strlcpy(priv->adap.name, "PIC32 I2C", sizeof(priv->adap.name)); + + i2c_platform_setup(priv); + + ret = i2c_add_numbered_adapter(&priv->adap); + if (ret == 0) { + platform_set_drvdata(pdev, priv); + return 0; + } + + i2c_platform_disable(priv); + +out_mem: + kfree(priv); +out: + return ret; +} + +static int __devexit +i2c_platform_remove(struct platform_device *pdev) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + pr_debug("i2c_platform_remove\n"); + platform_set_drvdata(pdev, NULL); + i2c_del_adapter(&priv->adap); + i2c_platform_disable(priv); + kfree(priv); + return 0; +} + +#ifdef CONFIG_PM +static int +i2c_platform_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "i2c_platform_disable\n"); + i2c_platform_disable(priv); + + return 0; +} + +static int +i2c_platform_resume(struct platform_device *pdev) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "i2c_platform_setup\n"); + i2c_platform_setup(priv); + + return 0; +} +#else +#define i2c_platform_suspend NULL +#define i2c_platform_resume NULL +#endif + +static struct platform_driver i2c_platform_driver = { + .driver = { + .name = "i2c_pic32", + .owner = THIS_MODULE, + }, + .probe = i2c_platform_probe, + .remove = __devexit_p(i2c_platform_remove), + .suspend = i2c_platform_suspend, + .resume = i2c_platform_resume, +}; + +static int __init +i2c_platform_init(void) +{ + pr_debug("i2c_platform_init\n"); + return platform_driver_register(&i2c_platform_driver); +} + +static void __exit +i2c_platform_exit(void) +{ + pr_debug("i2c_platform_exit\n"); + platform_driver_unregister(&i2c_platform_driver); +} + +MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC."); +MODULE_DESCRIPTION("PIC32 I2C driver"); +MODULE_LICENSE("GPL"); + +module_init(i2c_platform_init); +module_exit(i2c_platform_exit); diff --git a/arch/mips/mti-sead3/sead3-platform.c b/arch/mips/mti-sead3/sead3-platform.c new file mode 100644 index 0000000..ddd28f6 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-platform.c @@ -0,0 +1,49 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 MIPS Technologies, Inc. + * written by Ralf Baechle (ralf@linux-mips.org) + * + * Probe driver for the SEAD3 UART ports + * + */ +#include +#include +#include + +#define UART(base, int) \ +{ \ + .mapbase = base, \ + .irq = int, \ + .uartclk = 14745600, \ + .iotype = UPIO_MEM32, \ + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, \ + .regshift = 2, \ +} + +static struct plat_serial8250_port uart8250_data[] = { + UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */ + UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */ + { }, +}; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-reset.c b/arch/mips/mti-sead3/sead3-reset.c new file mode 100644 index 0000000..4aec9f9 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-reset.c @@ -0,0 +1,64 @@ +#define DEBUG +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Reset the MIPS boards. + * + */ +#include +#include + +#include +#include + +#define SOFTRES_REG 0x1F000050 +#define GORESET 0x4D + +static void mips_machine_restart(char *command); +static void mips_machine_halt(void); + +static void mips_machine_restart(char *command) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + +static void mips_machine_halt(void) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + + +static int __init mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; + _machine_halt = mips_machine_halt; + pm_power_off = mips_machine_halt; + + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c new file mode 100644 index 0000000..1ddd4c3 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -0,0 +1,49 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2008 Dmitri Vorobiev + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +int coherentio; /* init to 0 => no DMA cache coherency (may be set by user) */ +int hw_coherentio; /* init to 0 => no HW DMA cache coherency (reflects real HW) */ + +const char *get_system_type(void) +{ + return "MIPS SEAD3"; +} + +#if defined(CONFIG_MIPS_MT_SMTC) +const char display_string[] = " SMTC LINUX ON SEAD3 "; +#else +const char display_string[] = " LINUX ON SEAD3 "; +#endif /* CONFIG_MIPS_MT_SMTC */ + +void __init plat_mem_setup(void) +{ +} diff --git a/arch/mips/mti-sead3/sead3-smtc.c b/arch/mips/mti-sead3/sead3-smtc.c new file mode 100644 index 0000000..192cfd2 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-smtc.c @@ -0,0 +1,162 @@ +/* + * Malta Platform-specific hooks for SMP operation + */ +#include +#include + +#include +#include +#include +#include + +/* VPE/SMP Prototype implements platform interfaces directly */ + +/* + * Cause the specified action to be performed on a targeted "CPU" + */ + +static void msmtc_send_ipi_single(int cpu, unsigned int action) +{ + /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ + smtc_send_ipi(cpu, LINUX_SMP_IPI, action); +} + +static void msmtc_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu(i, mask) + msmtc_send_ipi_single(i, action); +} + +/* + * Post-config but pre-boot cleanup entry point + */ +static void __cpuinit msmtc_init_secondary(void) +{ + void smtc_init_secondary(void); + int myvpe; + + /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ + myvpe = read_c0_tcbind() & TCBIND_CURVPE; + if (myvpe != 0) { + /* Ideally, this should be done only once per VPE, but... */ + clear_c0_status(ST0_IM); + set_c0_status((0x100 << cp0_compare_irq) + | (0x100 << MIPS_CPU_IPI_IRQ)); + if (cp0_perfcount_irq >= 0) + set_c0_status(0x100 << cp0_perfcount_irq); + } + + smtc_init_secondary(); +} + +/* + * Platform "CPU" startup hook + */ +static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle) +{ + smtc_boot_secondary(cpu, idle); +} + +/* + * SMP initialization finalization entry point + */ +static void __cpuinit msmtc_smp_finish(void) +{ + smtc_smp_finish(); +} + +/* + * Hook for after all CPUs are online + */ + +static void msmtc_cpus_done(void) +{ +} + +/* + * Platform SMP pre-initialization + * + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. + */ + +static void __init msmtc_smp_setup(void) +{ + /* + * we won't get the definitive value until + * we've run smtc_prepare_cpus later, but + * we would appear to need an upper bound now. + */ + smp_num_siblings = smtc_build_cpu_map(0); +} + +static void __init msmtc_prepare_cpus(unsigned int max_cpus) +{ + smtc_prepare_cpus(max_cpus); +} + +struct plat_smp_ops msmtc_smp_ops = { + .send_ipi_single = msmtc_send_ipi_single, + .send_ipi_mask = msmtc_send_ipi_mask, + .init_secondary = msmtc_init_secondary, + .smp_finish = msmtc_smp_finish, + .cpus_done = msmtc_cpus_done, + .boot_secondary = msmtc_boot_secondary, + .smp_setup = msmtc_smp_setup, + .prepare_cpus = msmtc_prepare_cpus, +}; + +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * IRQ affinity hook + */ + + +int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) +{ + cpumask_t tmask; + int cpu = 0; + void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); + + /* + * On the legacy Malta development board, all I/O interrupts + * are routed through the 8259 and combined in a single signal + * to the CPU daughterboard, and on the CoreFPGA2/3 34K models, + * that signal is brought to IP2 of both VPEs. To avoid racing + * concurrent interrupt service events, IP2 is enabled only on + * one VPE, by convention VPE0. So long as no bits are ever + * cleared in the affinity mask, there will never be any + * interrupt forwarding. But as soon as a program or operator + * sets affinity for one of the related IRQs, we need to make + * sure that we don't ever try to forward across the VPE boundry, + * at least not until we engineer a system where the interrupt + * _ack() or _end() function can somehow know that it corresponds + * to an interrupt taken on another VPE, and perform the appropriate + * restoration of Status.IM state using MFTR/MTTR instead of the + * normal local behavior. We also ensure that no attempt will + * be made to forward to an offline "CPU". + */ + + cpumask_copy(&tmask, affinity); + for_each_cpu(cpu, affinity) { + if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) + cpu_clear(cpu, tmask); + } + cpumask_copy(irq_desc[irq].affinity, &tmask); + + if (cpus_empty(tmask)) + /* + * We could restore a default mask here, but the + * runtime code can anyway deal with the null set + */ + printk(KERN_WARNING + "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); + + /* Do any generic SMTC IRQ affinity setup */ + smtc_set_irq_affinity(irq, tmask); + + return 0; +} +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c new file mode 100644 index 0000000..a31dd35 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-time.c @@ -0,0 +1,145 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Setting up the clock on the MIPS boards. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +unsigned long cpu_khz; + +static int mips_cpu_timer_irq; +static int mips_cpu_perf_irq; +extern int cp0_perfcount_irq; + +static void mips_timer_dispatch(void) +{ + do_IRQ(mips_cpu_timer_irq); +} + +static void mips_perf_dispatch(void) +{ + do_IRQ(mips_cpu_perf_irq); +} + +static void __iomem *status_reg = (void __iomem *)0xbf000410; + +/* + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect + */ +static unsigned int __init estimate_cpu_frequency(void) +{ + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int tick = 0; + unsigned int freq; + unsigned int orig; + unsigned long flags; + + local_irq_save(flags); + + orig = readl(status_reg) & 0x2; /* get original sample */ + /* wait for transition */ + while ((readl(status_reg) & 0x2) == orig) + ; + orig = orig ^ 0x2; /* flip the bit */ + + write_c0_count(0); + + /* wait 1 second (the sampling clock transitions every 10ms) */ + while (tick < 100) { + /* wait for transition */ + while ((readl(status_reg) & 0x2) == orig) + ; + orig = orig ^ 0x2; /* flip the bit */ + tick++; + } + + freq = read_c0_count(); + + local_irq_restore(flags); + + mips_hpt_frequency = freq; + + /* Adjust for processor */ + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + freq *= 2; + + freq += 5000; /* rounding */ + freq -= freq%10000; + + return freq ; +} + +void read_persistent_clock(struct timespec *ts) +{ + ts->tv_sec = 0; /* FIXME - i2c is not up yet => can't access RTC */ + ts->tv_nsec = 0; +} + +static void __init plat_perf_setup(void) +{ + if (cp0_perfcount_irq >= 0) { + if (cpu_has_vint) + set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); + mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; + } +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ + if (cpu_has_vint) + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; + return mips_cpu_timer_irq; +} + +void __init plat_time_init(void) +{ + unsigned int est_freq; + + est_freq = estimate_cpu_frequency(); + + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + (est_freq%1000000)*100/1000000); + + cpu_khz = est_freq / 1000; + + mips_scroll_message(); + + plat_perf_setup(); +} -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:48:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:49:59 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36601 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904117Ab2DGQs6 (ORCPT ); Sat, 7 Apr 2012 18:48:58 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYol-0004dH-BI; Sat, 07 Apr 2012 11:48:51 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 02/10] MIPS: Changes to configuration files for SEAD-3 platform. Date: Sat, 7 Apr 2012 11:48:27 -0500 Message-Id: <1333817315-30091-3-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32880 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 48593 Lines: 1856 From: "Steven J. Hill" Change MIPS configuration files to add the SEAD-3. Also add new default configuration file for a SEAD-3 kernel. Signed-off-by: Steven J. Hill --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 33 +- arch/mips/configs/sead3_defconfig | 1757 +++++++++++++++++++++++++++++++++++++ 3 files changed, 1788 insertions(+), 3 deletions(-) create mode 100644 arch/mips/configs/sead3_defconfig diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 5ce8029..84a3a81 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -16,6 +16,7 @@ platforms += lasat platforms += loongson platforms += mipssim platforms += mti-malta +platforms += mti-sead3 platforms += netlogic platforms += pmc-sierra platforms += pnx833x diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0c7fb5d..4eae8f4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -297,6 +297,35 @@ config MIPS_MALTA This enables support for the MIPS Technologies Malta evaluation board. +config MIPS_SEAD3 + bool "MIPS SEAD3 board" + select BOOT_ELF32 + select BOOT_RAW + select CEVT_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select IRQ_GIC + select MIPS_BOARDS_GEN + select MIPS_CPU_SCACHE + select MIPS_MSC + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS64_R1 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MULTITHREADING + select SYS_SUPPORTS_SMARTMIPS + select SYS_SUPPORTS_MICROMIPS + select USB_ARCH_HAS_EHCI + select USB_EHCI_BIG_ENDIAN_DESC + select USB_EHCI_BIG_ENDIAN_MMIO + help + This enables support for the MIPS Technologies SEAD3 evaluation + board. + config MIPS_SIM bool 'MIPS simulator (MIPSsim)' select CEVT_R4K @@ -1710,7 +1739,6 @@ config HARDWARE_WATCHPOINTS menu "Kernel type" choice - prompt "Kernel code model" help You should only select this option if you have a workload that @@ -1852,7 +1880,7 @@ config MIPS_MT_DISABLED config MIPS_MT_SMP bool "Use 1 TC on each available VPE for SMP" - depends on SYS_SUPPORTS_MULTITHREADING + depends on SYS_SUPPORTS_MULTITHREADING && !MIPS_SEAD3 select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT @@ -1916,7 +1944,6 @@ config SCHED_SMT config SYS_SUPPORTS_SCHED_SMT bool - config SYS_SUPPORTS_MULTITHREADING bool diff --git a/arch/mips/configs/sead3_defconfig b/arch/mips/configs/sead3_defconfig new file mode 100644 index 0000000..0482328 --- /dev/null +++ b/arch/mips/configs/sead3_defconfig @@ -0,0 +1,1757 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/mips 3.3.0 Kernel Configuration +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LANTIQ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +CONFIG_MIPS_SEAD3=y +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set + +# +# Clock source +# + +# +# Select one or more precise CPU clock source kernel modules below: +# +CONFIG_CSRC_R4K=y +# CONFIG_CSRC_GIC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_BOOT_RAW=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_MSC=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_GIC=y +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_BOARD_SCACHE=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +# CONFIG_MIPS_VPE_LOADER is not set +# CONFIG_CPU_HAS_SMARTMIPS is not set +# CONFIG_CPU_MICROMIPS is not set +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_FORCED_THREADING=y + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +# CONFIG_PM_RUNTIME is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +CONFIG_BQL=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +CONFIG_MTD_UBI_GLUEBI=y +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=m + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +CONFIG_MII=y +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_ENC28J60 is not set +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_8390=y +# CONFIG_AX88796 is not set +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_SEEQ=y +# CONFIG_SEEQ8005 is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_SMC91X is not set +CONFIG_SMSC911X=y +# CONFIG_SMSC911X_ARCH_HOOKS is not set +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_ICPLUS_PHY=y +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_CONSOLE_TRANSLATIONS is not set +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=32 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +CONFIG_SENSORS_ADT7475=y +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_EXYNOS_VIDEO is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LP855X is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB_ARCH_HAS_XHCI is not set +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_SPI=y +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_OT200 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +CONFIG_RTC_DRV_M41T80=y +# CONFIG_RTC_DRV_M41T80_WDT is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=y +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC7=y +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:48:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:50:25 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36603 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904118Ab2DGQs6 (ORCPT ); Sat, 7 Apr 2012 18:48:58 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYol-0004dH-Si; Sat, 07 Apr 2012 11:48:51 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 03/10] MIPS: Add support for the M14K core. Date: Sat, 7 Apr 2012 11:48:28 -0500 Message-Id: <1333817315-30091-4-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32881 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5111 Lines: 158 From: "Steven J. Hill" This patch depends on the 1074K core support patch being applied first. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu.h | 5 +++-- arch/mips/kernel/cpu-probe.c | 10 +++++++++- arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 4 +++- arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 4 ++++ 6 files changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index ddd8b4a..00e5adf 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -95,6 +95,7 @@ #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 #define PRID_IMP_1074K 0x9a00 +#define PRID_IMP_14K 0x9c00 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -261,7 +262,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, - CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_1074K, + CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_1074K, CPU_14K, /* * MIPS64 class processors @@ -289,7 +290,7 @@ enum cpu_type_enum { #define MIPS_CPU_ISA_M64R2 0x00000100 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ - MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) + MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2) #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index cb1e2e9..0fccb8c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -4,7 +4,7 @@ * Copyright (C) xxxx the Anonymous * Copyright (C) 1994 - 2006 Ralf Baechle * Copyright (C) 2003, 2004 Maciej W. Rozycki - * Copyright (C) 2001, 2004 MIPS Inc. + * Copyright (C) 2001, 2004, 2011 MIPS Technologies, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -199,6 +200,7 @@ void __init check_wait(void) cpu_wait = rm7k_wait_irqoff; break; + case CPU_14K: case CPU_24K: case CPU_34K: case CPU_1004K: @@ -743,6 +745,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->ases |= MIPS_ASE_MIPSMT; if (config3 & MIPS_CONF3_ULRI) c->options |= MIPS_CPU_ULRI; + if (config3 & MIPS_CONF3_CTXTC) + c->options |= MIPS_CPU_CTXTC; return config3 & MIPS_CONF_M; } @@ -832,6 +836,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_74K; __cpu_name[cpu] = "MIPS 74Kc"; break; + case PRID_IMP_14K: + c->cputype = CPU_14K; + __cpu_name[cpu] = "MIPS 14Kc"; + break; case PRID_IMP_1004K: c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index efcf385..9cd86fa 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1073,6 +1073,7 @@ static void __cpuinit probe_pcache(void) /* fall through */ bypass1074: ; + case CPU_14K: case CPU_24K: case CPU_34K: case CPU_1004K: diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 0bc485b..a034229b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -8,7 +8,8 @@ * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2008, 2009 Cavium Networks, Inc. + * Copyright (C) 2008, 2009 Cavium Networks, Inc. + * Copyright (C) 2011 MIPS Technologies, Inc. * * ... and the days got worse and worse and now you see * I've gone completly out of my mind. @@ -494,6 +495,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_R14000: case CPU_4KC: case CPU_4KEC: + case CPU_14K: case CPU_SB1: case CPU_SB1A: case CPU_4KSC: diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index 846faf7..b2e850e 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -78,6 +78,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) switch (current_cpu_type()) { case CPU_5KC: + case CPU_14K: case CPU_20KC: case CPU_24K: case CPU_25KF: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 13487a9..fdf3ce5 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -317,6 +317,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.num_counters = counters; switch (current_cpu_type()) { + case CPU_14K: + op_model_mipsxx_ops.cpu_type = "mips/14K"; + break; + case CPU_20KC: op_model_mipsxx_ops.cpu_type = "mips/20K"; break; -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:48:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:50:49 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36604 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904119Ab2DGQs7 (ORCPT ); Sat, 7 Apr 2012 18:48:59 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYom-0004dH-T2; Sat, 07 Apr 2012 11:48:52 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 04/10] MIPS: Add micro-assembler support for 'ins' and 'ext' instructions. Date: Sat, 7 Apr 2012 11:48:29 -0500 Message-Id: <1333817315-30091-5-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32882 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4943 Lines: 137 From: "Steven J. Hill" Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/uasm.h | 15 +++++++++++++++ arch/mips/mm/tlbex.c | 17 +++++++++++++++++ arch/mips/mm/uasm.c | 15 +++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 504d40a..f400629 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -60,6 +60,16 @@ void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b) #define Ip_0(op) void __uasminit uasm_i##op(u32 **buf) +#define Ip_bit_extract(op) \ +void __cpuinit \ +uasm_i##op(u32 **buf, unsigned int a, unsigned int b, \ + unsigned int c, unsigned int d) + +#define Ip_bit_insert(op) \ +void __cpuinit \ +uasm_i##op(u32 **buf, unsigned int a, unsigned int b, \ + unsigned int c, unsigned int d) + Ip_u2u1s3(_addiu); Ip_u3u1u2(_addu); Ip_u2u1u3(_andi); @@ -114,6 +124,8 @@ Ip_0(_tlbwi); Ip_0(_tlbwr); Ip_u3u1u2(_xor); Ip_u2u1u3(_xori); +Ip_bit_extract(_ext); +Ip_bit_insert(_ins); Ip_u2u1msbu3(_dins); Ip_u2u1msbu3(_dinsm); Ip_u1(_syscall); @@ -161,6 +173,9 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ # define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off) # define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd) #else +/* actually, the argument sequence is: rt, rs, pos, size. -- LY22 */ +# define UASM_i_EXT(buf, rs, rt, size, pos) uasm_i_ext(buf, rs, rt, size, pos) +# define UASM_i_INS(buf, rs, rt, size, pos) uasm_i_ins(buf, rs, rt, size, pos) # define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off) # define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off) # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index a034229b..4db0d19 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -921,6 +921,13 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) #endif uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); +#ifdef CONFIG_32BIT + if (cpu_has_mips32r2) { + uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT)); + uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT)); + return; + } +#endif uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -956,6 +963,16 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { +#ifdef CONFIG_32BIT + if (cpu_has_mips32r2) { + /* For MIPS32R2, PTE ptr offset is obtained from BadVAddr */ + UASM_i_MFC0(p, tmp, C0_BADVADDR); + UASM_i_LW(p, ptr, 0, ptr); + UASM_i_EXT(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1); + UASM_i_INS(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1); + return; + } +#endif /* * Bug workaround for the Nevada. It seems as if under certain * circumstances the move from cp0_context might produce a diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 5fa1851..fb6d8e27 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -63,6 +63,7 @@ enum opcode { insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret, + insn_ins, insn_ext, insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, @@ -113,6 +114,8 @@ static struct insn insn_table[] __uasminitdata = { { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, @@ -287,6 +290,16 @@ static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) (*buf)++; } +#define I_bit_extract(op) \ +Ip_bit_extract(op) \ +{ \ + build_insn(buf, insn##op, b, a, d-1, c); \ +} +#define I_bit_insert(op) \ +Ip_bit_insert(op) \ +{ \ + build_insn(buf, insn##op, b, a, c+d-1, c); \ +} #define I_u1u2u3(op) \ Ip_u1u2u3(op) \ { \ @@ -396,6 +409,8 @@ I_u2u1u3(_drotr) I_u2u1u3(_drotr32) I_u3u1u2(_dsubu) I_0(_eret) +I_bit_insert(_ins) +I_bit_extract(_ext) I_u1(_j) I_u1(_jal) I_u1(_jr) -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:48:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:51:12 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36606 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904120Ab2DGQs7 (ORCPT ); Sat, 7 Apr 2012 18:48:59 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYon-0004dH-HA; Sat, 07 Apr 2012 11:48:53 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Douglas Leung , Chris Dearman Subject: [PATCH 05/10] MIPS: GIC interrupt changes for M14K and SEAD-3 support. Date: Sat, 7 Apr 2012 11:48:30 -0500 Message-Id: <1333817315-30091-6-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32883 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 11641 Lines: 359 From: "Steven J. Hill" These changes are to support the different GIC implementation that is used with M14K cores. It also supports the new SEAD-3 platform interrupt sources. Signed-off-by: Douglas Leung Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu-features.h | 4 +- arch/mips/kernel/cevt-r4k.c | 5 + arch/mips/kernel/irq-gic.c | 168 ++++++++++++++++++++++++++++++++-- 3 files changed, 169 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7..556afa2 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -222,13 +222,13 @@ # endif #endif -#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) +#if (defined(CONFIG_MIPS_SEAD3) || defined(CONFIG_CPU_MIPSR2_IRQ_VI)) && !defined(cpu_has_vint) # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) #elif !defined(cpu_has_vint) # define cpu_has_vint 0 #endif -#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) +#if (defined(CONFIG_MIPS_SEAD3) || defined(CONFIG_CPU_MIPSR2_IRQ_EI)) && !defined(cpu_has_veic) # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) #elif !defined(cpu_has_veic) # define cpu_has_veic 0 diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 51095dd9..17a59a5 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -15,6 +15,7 @@ #include #include #include +#include /* * The SMTC Kernel for the 34K, 1004K, et. al. replaces several @@ -98,6 +99,10 @@ void mips_event_handler(struct clock_event_device *dev) */ static int c0_compare_int_pending(void) { +#ifdef CONFIG_MIPS_SEAD3 + if (cpu_has_veic) + return gic_get_timer_pending(); +#endif return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); } diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 0c527f6..275b163 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -8,19 +8,93 @@ #include #include #include +#include + +#ifdef CONFIG_MIPS_SEAD3 +#include +#else +#include +#endif + +#include #include #include - static unsigned long _gic_base; static unsigned int _irqbase; static unsigned int gic_irq_flags[GIC_NUM_INTRS]; #define GIC_IRQ_FLAG_EDGE 0x0001 +/* The index into this array is the vector # of the interrupt. */ +static struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS]; + struct gic_pcpu_mask pcpu_masks[NR_CPUS]; static struct gic_pending_regs pending_regs[NR_CPUS]; static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; +unsigned int gic_get_timer_pending(void) +{ + unsigned int vpe_pending; + + GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0); + GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending); + return vpe_pending & GIC_VPE_PEND_TIMER_MSK; +} + +/* Helper function to enable the interrupt */ +/* NOTE: the _irqbase have already been removed. */ +void gic_enable_interrupt(int irq_vec) +{ +#ifdef CONFIG_MIPS_SEAD3 + unsigned int i; + unsigned int irq_source; + + /* enable all the interrupts associated with this vector */ + for (i = 0; i < gic_shared_intr_map[irq_vec].num_shared_intr; i++) { + irq_source = gic_shared_intr_map[irq_vec].intr_list[i]; + GIC_SET_INTR_MASK(irq_source); + } + /* enable all local interrupts associated with this vector */ + if (gic_shared_intr_map[irq_vec].local_intr_mask) { + GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0); + GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), gic_shared_intr_map[irq_vec].local_intr_mask); + } +#else + GIC_SET_INTR_MASK(irq_vec); +#endif +} + +/* Helper function to disable the interrupt */ +/* NOTE: the _irqbase have already been removed. */ +void gic_disable_interrupt(int irq_vec) +{ +#ifdef CONFIG_MIPS_SEAD3 + unsigned int i; + unsigned int irq_source; + + /* disable all the interrupts associated with this vector */ + for (i = 0; i < gic_shared_intr_map[irq_vec].num_shared_intr; i++) { + irq_source = gic_shared_intr_map[irq_vec].intr_list[i]; + GIC_CLR_INTR_MASK(irq_source); + } + /* disable all local interrupts associated with this vector */ + if (gic_shared_intr_map[irq_vec].local_intr_mask) { + GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0); + GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), gic_shared_intr_map[irq_vec].local_intr_mask); + } +#else + GIC_CLR_INTR_MASK(irq_vec); +#endif +} + +void gic_bind_eic_interrupt(int irq, int set) +{ + irq = irq - GIC_PIN_TO_VEC_OFFSET; /* convert irq vector # to hw int # */ + + /* set irq to use shadow set */ + GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set); +} + void gic_send_ipi(unsigned int intr) { pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, @@ -28,13 +102,35 @@ void gic_send_ipi(unsigned int intr) GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); } +static void gic_eic_irq_dispatch(void) +{ + unsigned int cause = read_c0_cause(); + int irq; + + irq = (cause & ST0_IM) >> STATUSB_IP2; + if (irq == 0) + irq = -1; + + if (irq >= 0) + do_IRQ(_irqbase + irq); + else + spurious_interrupt(); +} + /* This is Malta specific and needs to be exported */ static void __init vpe_local_setup(unsigned int numvpes) { int i; - unsigned long timer_interrupt = 5, perf_interrupt = 5; + unsigned long timer_interrupt = GIC_INT_TMR, perf_interrupt = GIC_INT_PERFCTR; unsigned int vpe_ctl; + if (cpu_has_veic) { + /* GIC timer interrupt -> CPU HW Int X (vector X+2) -> map to pin X+2-1 (since GIC adds 1) */ + timer_interrupt += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET); + /* GIC perfcnt interrupt -> CPU HW Int X (vector X+2) -> map to pin X+2-1 (since GIC adds 1) */ + perf_interrupt += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET); + } + /* * Setup the default performance counter timer interrupts * for all VPEs @@ -47,10 +143,18 @@ static void __init vpe_local_setup(unsigned int numvpes) if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK) GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), GIC_MAP_TO_PIN_MSK | timer_interrupt); + if (cpu_has_veic) { + set_vi_handler(timer_interrupt+GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch); + gic_shared_intr_map[timer_interrupt+GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK; + } if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK) GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), GIC_MAP_TO_PIN_MSK | perf_interrupt); + if (cpu_has_veic) { + set_vi_handler(perf_interrupt+GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch); + gic_shared_intr_map[perf_interrupt+GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK; + } } } @@ -94,8 +198,10 @@ static void gic_irq_ack(struct irq_data *d) pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); GIC_CLR_INTR_MASK(irq); +#ifndef CONFIG_MIPS_SEAD3 if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE) GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); +#endif } static void gic_mask_irq(struct irq_data *d) @@ -112,6 +218,26 @@ static void gic_unmask_irq(struct irq_data *d) GIC_SET_INTR_MASK(irq); } +static void gic_finish_irq(struct irq_data *d) +{ + unsigned int irq = d->irq - _irqbase; +#ifdef CONFIG_MIPS_SEAD3 + unsigned int i; + unsigned int irq_source; + + /* clear edge detectors */ + for (i = 0; i < gic_shared_intr_map[irq].num_shared_intr; i++) { + irq_source = gic_shared_intr_map[irq].intr_list[i]; + if (gic_irq_flags[irq_source] & GIC_IRQ_FLAG_EDGE) + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq_source); + } +#endif + + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); + /* enable interrupts */ + GIC_SET_INTR_MASK(irq); +} + #ifdef CONFIG_SMP static DEFINE_SPINLOCK(gic_lock); @@ -154,7 +280,7 @@ static struct irq_chip gic_irq_controller = { .irq_mask = gic_mask_irq, .irq_mask_ack = gic_mask_irq, .irq_unmask = gic_unmask_irq, - .irq_eoi = gic_unmask_irq, + .irq_eoi = gic_finish_irq, #ifdef CONFIG_SMP .irq_set_affinity = gic_set_affinity, #endif @@ -164,6 +290,8 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, unsigned int pin, unsigned int polarity, unsigned int trigtype, unsigned int flags) { + struct gic_shared_intr_map *map_ptr; + /* Setup Intr to Pin mapping */ if (pin & GIC_MAP_TO_NMI_MSK) { GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin); @@ -178,6 +306,13 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, GIC_MAP_TO_PIN_MSK | pin); /* Setup Intr to CPU mapping */ GIC_SH_MAP_TO_VPE_SMASK(intr, cpu); + if (cpu_has_veic) { + set_vi_handler(pin+GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch); + map_ptr = &gic_shared_intr_map[pin+GIC_PIN_TO_VEC_OFFSET]; + if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR) + BUG(); + map_ptr->intr_list[map_ptr->num_shared_intr++] = intr; + } } /* Setup Intr Polarity */ @@ -191,7 +326,7 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, /* Initialise per-cpu Interrupt software masks */ if (flags & GIC_FLAG_IPI) set_bit(intr, pcpu_masks[cpu].pcpu_mask); - if (flags & GIC_FLAG_TRANSPARENT) + if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0)) GIC_SET_INTR_MASK(intr); if (trigtype == GIC_TRIG_EDGE) gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE; @@ -201,16 +336,27 @@ static void __init gic_basic_init(int numintrs, int numvpes, struct gic_intr_map *intrmap, int mapsize) { unsigned int i, cpu; + unsigned int pin_offset = 0; + + board_bind_eic_interrupt = &gic_bind_eic_interrupt; /* Setup defaults */ for (i = 0; i < numintrs; i++) { GIC_SET_POLARITY(i, GIC_POL_POS); GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); GIC_CLR_INTR_MASK(i); - if (i < GIC_NUM_INTRS) + if (i < GIC_NUM_INTRS) { gic_irq_flags[i] = 0; + gic_shared_intr_map[i].num_shared_intr = 0; + gic_shared_intr_map[i].local_intr_mask = 0; + } } + /* In EIC mode, the HW_INT# is offset by (2-1). */ + /* Need to subtract one because the GIC will add one (since 0=no intr). */ + if (cpu_has_veic) + pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET); + /* Setup specifics */ for (i = 0; i < mapsize; i++) { cpu = intrmap[i].cpunum; @@ -220,7 +366,7 @@ static void __init gic_basic_init(int numintrs, int numvpes, continue; gic_setup_intr(i, intrmap[i].cpunum, - intrmap[i].pin, + intrmap[i].pin + pin_offset, intrmap[i].polarity, intrmap[i].trigtype, intrmap[i].flags); @@ -228,8 +374,17 @@ static void __init gic_basic_init(int numintrs, int numvpes, vpe_local_setup(numvpes); +#ifdef CONFIG_MIPS_SEAD3 + /* for non-eic mode, we want to setup the GIC in pass-through mode. */ + /* That is, as if the GIC don't exist. */ + if (cpu_has_veic) { + for (i = _irqbase; i < (_irqbase + numintrs); i++) + irq_set_chip_and_handler(i, &gic_irq_controller, handle_percpu_irq); + } +#else for (i = _irqbase; i < (_irqbase + numintrs); i++) irq_set_chip(i, &gic_irq_controller); +#endif } void __init gic_init(unsigned long gic_base_addr, @@ -251,6 +406,7 @@ void __init gic_init(unsigned long gic_base_addr, numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> GIC_SH_CONFIG_NUMVPES_SHF; + numvpes = numvpes + 1; pr_debug("%s called\n", __func__); -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:49:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:51:35 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36609 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904121Ab2DGQtA (ORCPT ); Sat, 7 Apr 2012 18:49:00 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYoo-0004dH-6m; Sat, 07 Apr 2012 11:48:54 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 06/10] MIPS: Code formatting fixes. Date: Sat, 7 Apr 2012 11:48:31 -0500 Message-Id: <1333817315-30091-7-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32884 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8249 Lines: 219 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/kernel/cpu-probe.c | 54 +++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0fccb8c..7d95e62 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -343,7 +343,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R2000"; c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | - MIPS_CPU_NOFPUEX; + MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; @@ -364,7 +364,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) } c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | - MIPS_CPU_NOFPUEX; + MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; @@ -390,8 +390,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_WATCH | MIPS_CPU_VCE | - MIPS_CPU_LLSC; + MIPS_CPU_WATCH | MIPS_CPU_VCE | + MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_VR41XX: @@ -437,7 +437,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R4300"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; c->tlbsize = 32; break; case PRID_IMP_R4600: @@ -449,7 +449,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->tlbsize = 48; break; #if 0 - case PRID_IMP_R4650: + case PRID_IMP_R4650: /* * This processor doesn't have an MMU, so it's not * "real easy" to run Linux on it. It is left purely @@ -458,9 +458,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) */ c->cputype = CPU_R4650; __cpu_name[cpu] = "R4650"; - c->isa_level = MIPS_CPU_ISA_III; + c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; - c->tlbsize = 48; + c->tlbsize = 48; break; #endif case PRID_IMP_TX39: @@ -491,7 +491,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R4700"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_TX49: @@ -508,7 +508,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R5000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_R5432: @@ -516,7 +516,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R5432"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_WATCH | MIPS_CPU_LLSC; + MIPS_CPU_WATCH | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_R5500: @@ -524,7 +524,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R5500"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_WATCH | MIPS_CPU_LLSC; + MIPS_CPU_WATCH | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_NEVADA: @@ -532,7 +532,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Nevada"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_DIVEC | MIPS_CPU_LLSC; + MIPS_CPU_DIVEC | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_R6000: @@ -540,7 +540,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R6000"; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; c->tlbsize = 32; break; case PRID_IMP_R6000A: @@ -548,7 +548,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R6000A"; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; c->tlbsize = 32; break; case PRID_IMP_RM7000: @@ -556,7 +556,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "RM7000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; /* * Undocumented RM7000: Bit 29 in the info register of * the RM7000 v2.0 indicates if the TLB has 48 or 64 @@ -572,7 +572,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "RM9000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; /* * Bit 29 in the info register of the RM9000 * indicates if the TLB has 48 or 64 entries. @@ -587,8 +587,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "RM8000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_LLSC; + MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ break; case PRID_IMP_R10000: @@ -596,9 +596,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R10000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | - MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; c->tlbsize = 64; break; case PRID_IMP_R12000: @@ -606,9 +606,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R12000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | - MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; c->tlbsize = 64; break; case PRID_IMP_R14000: @@ -616,9 +616,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R14000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | - MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | - MIPS_CPU_LLSC; + MIPS_CPU_LLSC; c->tlbsize = 64; break; case PRID_IMP_LOONGSON2: @@ -742,7 +742,7 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) if (config3 & MIPS_CONF3_VEIC) c->options |= MIPS_CPU_VEIC; if (config3 & MIPS_CONF3_MT) - c->ases |= MIPS_ASE_MIPSMT; + c->ases |= MIPS_ASE_MIPSMT; if (config3 & MIPS_CONF3_ULRI) c->options |= MIPS_CPU_ULRI; if (config3 & MIPS_CONF3_CTXTC) @@ -772,7 +772,7 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) /* MIPS32 or MIPS64 compliant CPU. */ c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | - MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; + MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; c->scache.flags = MIPS_CACHE_NOT_PRESENT; -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:49:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:51:56 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36611 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904122Ab2DGQtA (ORCPT ); Sat, 7 Apr 2012 18:49:00 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYoo-0004dH-Ou; Sat, 07 Apr 2012 11:48:54 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Douglas Leung , Chris Dearman Subject: [PATCH 07/10] MIPS: Add support for early serial debug and LCD device on SEAD-3. Date: Sat, 7 Apr 2012 11:48:32 -0500 Message-Id: <1333817315-30091-8-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32885 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2120 Lines: 78 From: "Steven J. Hill" Add SEAD-3 support for early serial printk and the address for the small LCD display. The actual framebuffer support is contained in another patch. Signed-off-by: Douglas Leung Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mips-boards/generic.h | 1 + arch/mips/kernel/early_printk.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index 46c0856..a857264 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -29,6 +29,7 @@ */ #define ASCII_DISPLAY_WORD_BASE 0x1f000410 #define ASCII_DISPLAY_POS_BASE 0x1f000418 +#define LCD_DISPLAY_POS_BASE 0x1f000400 /* SEAD-3 */ /* diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c index 9ae813e..e078cae 100644 --- a/arch/mips/kernel/early_printk.c +++ b/arch/mips/kernel/early_printk.c @@ -12,6 +12,23 @@ #include +#ifdef CONFIG_MIPS_SEAD3 +#include +#include + +extern void prom_putchar(char, char); + +static void __init +early_console_write(struct console *con, const char *s, unsigned n) +{ + while (n-- && *s) { + if (*s == '\n') + prom_putchar('\r', con->index); + prom_putchar(*s, con->index); + s++; + } +} +#else extern void prom_putchar(char); static void __init @@ -24,6 +41,7 @@ early_console_write(struct console *con, const char *s, unsigned n) s++; } } +#endif static struct console early_console __initdata = { .name = "early", @@ -40,5 +58,12 @@ void __init setup_early_printk(void) return; early_console_initialized = 1; +#ifdef CONFIG_MIPS_SEAD3 + if ((strstr(prom_getcmdline(), "console=ttyS0")) != NULL) + early_console.index = 0; + else if ((strstr(prom_getcmdline(), "console=ttyS1")) != NULL) + early_console.index = 1; +#endif + register_console(&early_console); } -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:49:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:52:18 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36613 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904123Ab2DGQtB (ORCPT ); Sat, 7 Apr 2012 18:49:01 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYop-0004dH-9M; Sat, 07 Apr 2012 11:48:55 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 08/10] MIPS: MIPS32R2 optimisations for pipeline stalls and code size. Date: Sat, 7 Apr 2012 11:48:33 -0500 Message-Id: <1333817315-30091-9-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32886 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3348 Lines: 128 From: "Steven J. Hill" If the CPU type is selected as MIPS32R2, then we can surround some code with #ifdef's to reduce the binary size. Detect when to use 'ehb' instruction to avoid pipeline stalls. Signed-off-by: Steven J. Hill --- arch/mips/mm/tlbex.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4db0d19..87f57ae 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -74,10 +74,12 @@ static inline int __maybe_unused bcm1250_m3_war(void) return BCM1250_M3_WAR; } +#ifndef CONFIG_CPU_MIPS32_R2 static inline int __maybe_unused r10000_llsc_war(void) { return R10000_LLSC_WAR; } +#endif static int use_bbit_insns(void) { @@ -340,6 +342,7 @@ static void __cpuinit build_restore_work_registers(u32 **p) */ extern unsigned long pgd_current[]; +# ifndef CONFIG_CPU_MIPS32_R2 /* * The R3000 TLB handler is simple. */ @@ -379,6 +382,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void) dump_handler((u32 *)ebase, 32); } +# endif /* !CONFIG_CPU_MIPS32_R2 */ #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ /* @@ -449,8 +453,23 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, } if (cpu_has_mips_r2) { - if (cpu_has_mips_r2_exec_hazard) - uasm_i_ehb(p); + /* + * The architecture spec says an ehb is required here, + * but a number of cores do not have the hazard and + * using an ehb causes an expensive pipeline stall. + */ + if (cpu_has_mips_r2_exec_hazard) { + switch (current_cpu_type()) { + case CPU_14K: + case CPU_74K: + case CPU_1074K: + break; + + default: + uasm_i_ehb(p); + break; + } + } tlbw(p); return; } @@ -910,7 +929,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) #else /* * smp_processor_id() << 3 is stored in CONTEXT. - */ + */ uasm_i_mfc0(p, ptr, C0_CONTEXT); UASM_i_LA_mostly(p, tmp, pgdc); uasm_i_srl(p, ptr, ptr, 23); @@ -1513,9 +1532,11 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, # endif UASM_i_SC(p, pte, 0, ptr); +#ifndef CONFIG_CPU_MIPS32_R2 if (r10000_llsc_war()) uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); else +#endif uasm_il_beqz(p, r, pte, label_smp_pgtable_change); # ifdef CONFIG_64BIT_PHYS_ADDR @@ -1649,7 +1670,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r, } } -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT +#if !defined(CONFIG_MIPS_PGD_C0_CONTEXT) && !defined(CONFIG_CPU_MIPS32_R2) /* @@ -1803,7 +1824,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void) dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); } -#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ +#endif /* !CONFIG_MIPS_PGD_C0_CONTEXT && !CONFIG_CPU_MIPS32_R2 */ /* * R4000 style TLB load/store/modify handlers. @@ -2120,6 +2141,7 @@ void __cpuinit build_tlb_refill_handler(void) #endif switch (current_cpu_type()) { +#ifndef CONFIG_CPU_MIPS32_R2 case CPU_R2000: case CPU_R3000: case CPU_R3000A: @@ -2149,6 +2171,7 @@ void __cpuinit build_tlb_refill_handler(void) panic("No R8000 TLB refill handler yet"); break; +#endif /* !CONFIG_CPU_MIPS32_R2 */ default: if (!run_once) { scratch_reg = allocate_kscratch(); -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:49:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:52:42 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36615 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904124Ab2DGQtB (ORCPT ); Sat, 7 Apr 2012 18:49:01 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYop-0004dH-Ps; Sat, 07 Apr 2012 11:48:55 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Douglas Leung , Chris Dearman Subject: [PATCH 09/10] cobalt_lcdfb: LCD panel framebuffer support for SEAD-3 platform. Date: Sat, 7 Apr 2012 11:48:34 -0500 Message-Id: <1333817315-30091-10-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32887 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2764 Lines: 98 From: "Steven J. Hill" Add support for LCD panel on MIPS SEAD-3 development platform. Signed-off-by: Douglas Leung Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- drivers/video/Kconfig | 2 +- drivers/video/cobalt_lcdfb.c | 45 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index a8a897a..e921a45 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2210,7 +2210,7 @@ config FB_XILINX config FB_COBALT tristate "Cobalt server LCD frame buffer support" - depends on FB && MIPS_COBALT + depends on FB && (MIPS_COBALT || MIPS_SEAD3) config FB_SH7760 bool "SH7760/SH7763/SH7720/SH7721 LCDC support" diff --git a/drivers/video/cobalt_lcdfb.c b/drivers/video/cobalt_lcdfb.c index f56699d..eae46f6 100644 --- a/drivers/video/cobalt_lcdfb.c +++ b/drivers/video/cobalt_lcdfb.c @@ -1,7 +1,8 @@ /* - * Cobalt server LCD frame buffer driver. + * Cobalt/SEAD3 LCD frame buffer driver. * * Copyright (C) 2008 Yoichi Yuasa + * Copyright (C) 2012 MIPS Technologies, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -62,6 +63,7 @@ #define LCD_CUR_POS(x) ((x) & LCD_CUR_POS_MASK) #define LCD_TEXT_POS(x) ((x) | LCD_TEXT_MODE) +#ifdef CONFIG_MIPS_COBALT static inline void lcd_write_control(struct fb_info *info, u8 control) { writel((u32)control << 24, info->screen_base); @@ -81,6 +83,47 @@ static inline u8 lcd_read_data(struct fb_info *info) { return readl(info->screen_base + LCD_DATA_REG_OFFSET) >> 24; } +#else + +#define LCD_CTL 0x00 +#define LCD_DATA 0x08 +#define CPLD_STATUS 0x10 +#define CPLD_DATA 0x18 + +static inline void cpld_wait(struct fb_info *info) +{ + do { + } while (readl(info->screen_base + CPLD_STATUS) & 1); +} + +static inline void lcd_write_control(struct fb_info *info, u8 control) +{ + cpld_wait(info); + writel(control, info->screen_base + LCD_CTL); +} + +static inline u8 lcd_read_control(struct fb_info *info) +{ + cpld_wait(info); + readl(info->screen_base + LCD_CTL); + cpld_wait(info); + return readl(info->screen_base + CPLD_DATA) & 0xff; +} + +static inline void lcd_write_data(struct fb_info *info, u8 data) +{ + cpld_wait(info); + writel(data, info->screen_base + LCD_DATA); +} + +static inline u8 lcd_read_data(struct fb_info *info) +{ + cpld_wait(info); + readl(info->screen_base + LCD_DATA); + cpld_wait(info); + return readl(info->screen_base + CPLD_DATA) & 0xff; +} +#endif static int lcd_busy_wait(struct fb_info *info) { -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:57:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 18:57:17 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36625 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904124Ab2DGQ5K (ORCPT ); Sat, 7 Apr 2012 18:57:10 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYwh-0004eT-MW; Sat, 07 Apr 2012 11:57:03 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: linux-fbdev@vger.kernel.org, "Steven J. Hill" , Douglas Leung , Chris Dearman Subject: [PATCH 09/10] cobalt_lcdfb: LCD panel framebuffer support for SEAD-3 platform. Date: Sat, 7 Apr 2012 11:56:40 -0500 Message-Id: <1333817800-30222-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32888 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2764 Lines: 98 From: "Steven J. Hill" Add support for LCD panel on MIPS SEAD-3 development platform. Signed-off-by: Douglas Leung Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- drivers/video/Kconfig | 2 +- drivers/video/cobalt_lcdfb.c | 45 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index a8a897a..e921a45 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2210,7 +2210,7 @@ config FB_XILINX config FB_COBALT tristate "Cobalt server LCD frame buffer support" - depends on FB && MIPS_COBALT + depends on FB && (MIPS_COBALT || MIPS_SEAD3) config FB_SH7760 bool "SH7760/SH7763/SH7720/SH7721 LCDC support" diff --git a/drivers/video/cobalt_lcdfb.c b/drivers/video/cobalt_lcdfb.c index f56699d..eae46f6 100644 --- a/drivers/video/cobalt_lcdfb.c +++ b/drivers/video/cobalt_lcdfb.c @@ -1,7 +1,8 @@ /* - * Cobalt server LCD frame buffer driver. + * Cobalt/SEAD3 LCD frame buffer driver. * * Copyright (C) 2008 Yoichi Yuasa + * Copyright (C) 2012 MIPS Technologies, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -62,6 +63,7 @@ #define LCD_CUR_POS(x) ((x) & LCD_CUR_POS_MASK) #define LCD_TEXT_POS(x) ((x) | LCD_TEXT_MODE) +#ifdef CONFIG_MIPS_COBALT static inline void lcd_write_control(struct fb_info *info, u8 control) { writel((u32)control << 24, info->screen_base); @@ -81,6 +83,47 @@ static inline u8 lcd_read_data(struct fb_info *info) { return readl(info->screen_base + LCD_DATA_REG_OFFSET) >> 24; } +#else + +#define LCD_CTL 0x00 +#define LCD_DATA 0x08 +#define CPLD_STATUS 0x10 +#define CPLD_DATA 0x18 + +static inline void cpld_wait(struct fb_info *info) +{ + do { + } while (readl(info->screen_base + CPLD_STATUS) & 1); +} + +static inline void lcd_write_control(struct fb_info *info, u8 control) +{ + cpld_wait(info); + writel(control, info->screen_base + LCD_CTL); +} + +static inline u8 lcd_read_control(struct fb_info *info) +{ + cpld_wait(info); + readl(info->screen_base + LCD_CTL); + cpld_wait(info); + return readl(info->screen_base + CPLD_DATA) & 0xff; +} + +static inline void lcd_write_data(struct fb_info *info, u8 data) +{ + cpld_wait(info); + writel(data, info->screen_base + LCD_DATA); +} + +static inline u8 lcd_read_data(struct fb_info *info) +{ + cpld_wait(info); + readl(info->screen_base + LCD_DATA); + cpld_wait(info); + return readl(info->screen_base + CPLD_DATA) & 0xff; +} +#endif static int lcd_busy_wait(struct fb_info *info) { -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 18:59:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 19:00:06 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36633 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904124Ab2DGQ76 (ORCPT ); Sat, 7 Apr 2012 18:59:58 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYzP-0004eZ-5Q; Sat, 07 Apr 2012 11:59:51 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, "Steven J. Hill" , Chris Dearman Subject: [PATCH 10/10] usb: host: mips: sead3: USB Host controller support for SEAD-3 platform. Date: Sat, 7 Apr 2012 11:59:39 -0500 Message-Id: <1333817979-30288-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32889 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9498 Lines: 357 From: "Steven J. Hill" Add EHCI driver for MIPS SEAD-3 development platform. Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- drivers/usb/host/Kconfig | 4 +- drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-sead3.c | 299 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 306 insertions(+), 2 deletions(-) create mode 100644 drivers/usb/host/ehci-sead3.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index f788eb8..db29a9f 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -110,13 +110,13 @@ config USB_EHCI_BIG_ENDIAN_MMIO depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ PPC_MPC512x || CPU_CAVIUM_OCTEON || \ - PMC_MSP || SPARC_LEON) + PMC_MSP || SPARC_LEON || MIPS_SEAD3) default y config USB_EHCI_BIG_ENDIAN_DESC bool depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ - PPC_MPC512x || PMC_MSP || SPARC_LEON) + PPC_MPC512x || PMC_MSP || SPARC_LEON || MIPS_SEAD3) default y config XPS_USB_HCD_XILINX diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index aede637..30563ff 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1371,6 +1371,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_ls1x_driver #endif +#ifdef CONFIG_MIPS_SEAD3 +#include "ehci-sead3.c" +#define PLATFORM_DRIVER ehci_hcd_mips_driver +#endif + #ifdef CONFIG_USB_EHCI_HCD_PLATFORM #include "ehci-platform.c" #define PLATFORM_DRIVER ehci_platform_driver diff --git a/drivers/usb/host/ehci-sead3.c b/drivers/usb/host/ehci-sead3.c new file mode 100644 index 0000000..743a0c1 --- /dev/null +++ b/drivers/usb/host/ehci-sead3.c @@ -0,0 +1,299 @@ +/* + * MIPS CI13320A EHCI Host Controller driver + * Based on "ehci-au1xxx.c" by K.Boge + * + * Copyright (C) 2012 MIPS Technologies, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#ifdef CONFIG_PM +static void mips_start_ehc(void) +{ + pr_debug("mips_start_ehc\n"); +} +#endif + +static void mips_stop_ehc(void) +{ + pr_debug("mips_start_ehc\n"); +} + +static int mips_run(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 temp; + + temp = ehci_reset(ehci); + if (temp != 0) { + ehci_mem_cleanup(ehci); + return temp; + } + + return ehci_run(hcd); +} + +const struct hc_driver ehci_mips_hc_driver = { + .description = hcd_name, + .product_desc = "MIPS EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + * + */ + .reset = ehci_init, + .start = mips_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, +}; + +static int ehci_hcd_mips_drv_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct ehci_hcd *ehci; + int ret; + + if (usb_disabled()) + return -ENODEV; + + if (pdev->resource[1].flags != IORESOURCE_IRQ) { + pr_debug("resource[1] is not IORESOURCE_IRQ"); + return -ENOMEM; + } + hcd = usb_create_hcd(&ehci_mips_hc_driver, &pdev->dev, "MIPS"); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = pdev->resource[0].start; + hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_debug("request_mem_region failed"); + ret = -EBUSY; + goto err1; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed"); + ret = -ENOMEM; + goto err2; + } + + hcd->has_tt = 1; + + ehci = hcd_to_ehci(hcd); + ehci->caps = hcd->regs + 0x100; + ehci->regs = hcd->regs + 0x100 + + HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = readl(&ehci->caps->hcs_params); + + /* SEAD-3 EHCI matches CPU endianness. */ +#ifdef __BIG_ENDIAN + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; +#endif + + /* Set burst length to 16 words */ + /* FIXME: should be tunable */ + ehci_writel(ehci, 0x1010, &ehci->regs->reserved[1]); + + ret = usb_add_hcd(hcd, pdev->resource[1].start, + IRQF_DISABLED | IRQF_SHARED); + if (ret == 0) { + platform_set_drvdata(pdev, hcd); + return ret; + } + + mips_stop_ehc(); + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + return ret; +} + +static int ehci_hcd_mips_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + mips_stop_ehc(); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int ehci_hcd_mips_drv_suspend(struct platform_device *pdev, + pm_message_t message) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + unsigned long flags; + int rc; + + return 0; + rc = 0; + + if (time_before(jiffies, ehci->next_statechange)) + msleep(10); + + /* Root hub was already suspended. Disable irq emission and + * mark HW unaccessible, bail out if RH has been resumed. Use + * the spinlock to properly synchronize with possible pending + * RH suspend or resume activity. + * + * This is still racy as hcd->state is manipulated outside of + * any locks =P But that will be a different fix. + */ + spin_lock_irqsave(&ehci->lock, flags); + if (hcd->state != HC_STATE_SUSPENDED) { + rc = -EINVAL; + goto bail; + } + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + (void)ehci_readl(ehci, &ehci->regs->intr_enable); + + /* make sure snapshot being resumed re-enumerates everything */ + if (message.event == PM_EVENT_PRETHAW) { + ehci_halt(ehci); + ehci_reset(ehci); + } + + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + mips_stop_ehc(); + +bail: + spin_unlock_irqrestore(&ehci->lock, flags); + + /* could save FLADJ in case of Vaux power loss */ + /* ... we'd only use it to handle clock skew */ + + return rc; +} + + +static int ehci_hcd_mips_drv_resume(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + mips_start_ehc(); + + /* maybe restore FLADJ */ + + if (time_before(jiffies, ehci->next_statechange)) + msleep(100); + + /* Mark hardware accessible again as we are out of D3 state by now */ + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + /* If CF is still set, we maintained PCI Vaux power. + * Just undo the effect of ehci_pci_suspend(). + */ + if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) { + int mask = INTR_MASK; + + if (!hcd->self.root_hub->do_remote_wakeup) + mask &= ~STS_PCD; + ehci_writel(ehci, mask, &ehci->regs->intr_enable); + ehci_readl(ehci, &ehci->regs->intr_enable); + return 0; + } + + ehci_dbg(ehci, "lost power, restarting\n"); + usb_root_hub_lost_power(hcd->self.root_hub); + + /* Else reset, to cope with power loss or flush-to-storage + * style "resume" having let BIOS kick in during reboot. + */ + (void) ehci_halt(ehci); + (void) ehci_reset(ehci); + + /* emptying the schedule aborts any urbs */ + spin_lock_irq(&ehci->lock); + if (ehci->reclaim) + end_unlink_async(ehci); + ehci_work(ehci); + spin_unlock_irq(&ehci->lock); + + ehci_writel(ehci, ehci->command, &ehci->regs->command); + ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); + ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ + + /* here we "know" root ports should always stay powered */ + ehci_port_power(ehci, 1); + + hcd->state = HC_STATE_SUSPENDED; + + return 0; +} + +#else +#define ehci_hcd_mips_drv_suspend NULL +#define ehci_hcd_mips_drv_resume NULL +#endif + +static struct platform_driver ehci_hcd_mips_driver = { + .probe = ehci_hcd_mips_drv_probe, + .remove = ehci_hcd_mips_drv_remove, + .shutdown = usb_hcd_platform_shutdown, + .suspend = ehci_hcd_mips_drv_suspend, + .resume = ehci_hcd_mips_drv_resume, + .driver = { + .name = "sead3-ehci", + .owner = THIS_MODULE, + } +}; + +MODULE_ALIAS("platform:sead3-ehci"); -- 1.7.9.6 From sjhill@mips.com Sat Apr 7 19:10:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 19:10:37 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:36649 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904124Ab2DGRKa (ORCPT ); Sat, 7 Apr 2012 19:10:30 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SGYoq-0004dH-KR; Sat, 07 Apr 2012 11:48:56 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Chris Dearman Subject: [PATCH 10/10] usb: host: mips: sead3: USB Host controller support for SEAD-3 platform. Date: Sat, 7 Apr 2012 11:48:35 -0500 Message-Id: <1333817315-30091-11-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333817315-30091-1-git-send-email-sjhill@mips.com> References: <1333817315-30091-1-git-send-email-sjhill@mips.com> X-archive-position: 32890 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9498 Lines: 357 From: "Steven J. Hill" Add EHCI driver for MIPS SEAD-3 development platform. Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- drivers/usb/host/Kconfig | 4 +- drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-sead3.c | 299 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 306 insertions(+), 2 deletions(-) create mode 100644 drivers/usb/host/ehci-sead3.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index f788eb8..db29a9f 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -110,13 +110,13 @@ config USB_EHCI_BIG_ENDIAN_MMIO depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ PPC_MPC512x || CPU_CAVIUM_OCTEON || \ - PMC_MSP || SPARC_LEON) + PMC_MSP || SPARC_LEON || MIPS_SEAD3) default y config USB_EHCI_BIG_ENDIAN_DESC bool depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ - PPC_MPC512x || PMC_MSP || SPARC_LEON) + PPC_MPC512x || PMC_MSP || SPARC_LEON || MIPS_SEAD3) default y config XPS_USB_HCD_XILINX diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index aede637..30563ff 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1371,6 +1371,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_ls1x_driver #endif +#ifdef CONFIG_MIPS_SEAD3 +#include "ehci-sead3.c" +#define PLATFORM_DRIVER ehci_hcd_mips_driver +#endif + #ifdef CONFIG_USB_EHCI_HCD_PLATFORM #include "ehci-platform.c" #define PLATFORM_DRIVER ehci_platform_driver diff --git a/drivers/usb/host/ehci-sead3.c b/drivers/usb/host/ehci-sead3.c new file mode 100644 index 0000000..743a0c1 --- /dev/null +++ b/drivers/usb/host/ehci-sead3.c @@ -0,0 +1,299 @@ +/* + * MIPS CI13320A EHCI Host Controller driver + * Based on "ehci-au1xxx.c" by K.Boge + * + * Copyright (C) 2012 MIPS Technologies, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#ifdef CONFIG_PM +static void mips_start_ehc(void) +{ + pr_debug("mips_start_ehc\n"); +} +#endif + +static void mips_stop_ehc(void) +{ + pr_debug("mips_start_ehc\n"); +} + +static int mips_run(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 temp; + + temp = ehci_reset(ehci); + if (temp != 0) { + ehci_mem_cleanup(ehci); + return temp; + } + + return ehci_run(hcd); +} + +const struct hc_driver ehci_mips_hc_driver = { + .description = hcd_name, + .product_desc = "MIPS EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + * + */ + .reset = ehci_init, + .start = mips_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, +}; + +static int ehci_hcd_mips_drv_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct ehci_hcd *ehci; + int ret; + + if (usb_disabled()) + return -ENODEV; + + if (pdev->resource[1].flags != IORESOURCE_IRQ) { + pr_debug("resource[1] is not IORESOURCE_IRQ"); + return -ENOMEM; + } + hcd = usb_create_hcd(&ehci_mips_hc_driver, &pdev->dev, "MIPS"); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = pdev->resource[0].start; + hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_debug("request_mem_region failed"); + ret = -EBUSY; + goto err1; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed"); + ret = -ENOMEM; + goto err2; + } + + hcd->has_tt = 1; + + ehci = hcd_to_ehci(hcd); + ehci->caps = hcd->regs + 0x100; + ehci->regs = hcd->regs + 0x100 + + HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = readl(&ehci->caps->hcs_params); + + /* SEAD-3 EHCI matches CPU endianness. */ +#ifdef __BIG_ENDIAN + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; +#endif + + /* Set burst length to 16 words */ + /* FIXME: should be tunable */ + ehci_writel(ehci, 0x1010, &ehci->regs->reserved[1]); + + ret = usb_add_hcd(hcd, pdev->resource[1].start, + IRQF_DISABLED | IRQF_SHARED); + if (ret == 0) { + platform_set_drvdata(pdev, hcd); + return ret; + } + + mips_stop_ehc(); + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + return ret; +} + +static int ehci_hcd_mips_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + mips_stop_ehc(); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int ehci_hcd_mips_drv_suspend(struct platform_device *pdev, + pm_message_t message) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + unsigned long flags; + int rc; + + return 0; + rc = 0; + + if (time_before(jiffies, ehci->next_statechange)) + msleep(10); + + /* Root hub was already suspended. Disable irq emission and + * mark HW unaccessible, bail out if RH has been resumed. Use + * the spinlock to properly synchronize with possible pending + * RH suspend or resume activity. + * + * This is still racy as hcd->state is manipulated outside of + * any locks =P But that will be a different fix. + */ + spin_lock_irqsave(&ehci->lock, flags); + if (hcd->state != HC_STATE_SUSPENDED) { + rc = -EINVAL; + goto bail; + } + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + (void)ehci_readl(ehci, &ehci->regs->intr_enable); + + /* make sure snapshot being resumed re-enumerates everything */ + if (message.event == PM_EVENT_PRETHAW) { + ehci_halt(ehci); + ehci_reset(ehci); + } + + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + mips_stop_ehc(); + +bail: + spin_unlock_irqrestore(&ehci->lock, flags); + + /* could save FLADJ in case of Vaux power loss */ + /* ... we'd only use it to handle clock skew */ + + return rc; +} + + +static int ehci_hcd_mips_drv_resume(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + mips_start_ehc(); + + /* maybe restore FLADJ */ + + if (time_before(jiffies, ehci->next_statechange)) + msleep(100); + + /* Mark hardware accessible again as we are out of D3 state by now */ + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + /* If CF is still set, we maintained PCI Vaux power. + * Just undo the effect of ehci_pci_suspend(). + */ + if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) { + int mask = INTR_MASK; + + if (!hcd->self.root_hub->do_remote_wakeup) + mask &= ~STS_PCD; + ehci_writel(ehci, mask, &ehci->regs->intr_enable); + ehci_readl(ehci, &ehci->regs->intr_enable); + return 0; + } + + ehci_dbg(ehci, "lost power, restarting\n"); + usb_root_hub_lost_power(hcd->self.root_hub); + + /* Else reset, to cope with power loss or flush-to-storage + * style "resume" having let BIOS kick in during reboot. + */ + (void) ehci_halt(ehci); + (void) ehci_reset(ehci); + + /* emptying the schedule aborts any urbs */ + spin_lock_irq(&ehci->lock); + if (ehci->reclaim) + end_unlink_async(ehci); + ehci_work(ehci); + spin_unlock_irq(&ehci->lock); + + ehci_writel(ehci, ehci->command, &ehci->regs->command); + ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); + ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ + + /* here we "know" root ports should always stay powered */ + ehci_port_power(ehci, 1); + + hcd->state = HC_STATE_SUSPENDED; + + return 0; +} + +#else +#define ehci_hcd_mips_drv_suspend NULL +#define ehci_hcd_mips_drv_resume NULL +#endif + +static struct platform_driver ehci_hcd_mips_driver = { + .probe = ehci_hcd_mips_drv_probe, + .remove = ehci_hcd_mips_drv_remove, + .shutdown = usb_hcd_platform_shutdown, + .suspend = ehci_hcd_mips_drv_suspend, + .resume = ehci_hcd_mips_drv_resume, + .driver = { + .name = "sead3-ehci", + .owner = THIS_MODULE, + } +}; + +MODULE_ALIAS("platform:sead3-ehci"); -- 1.7.9.6 From stern@rowland.harvard.edu Sat Apr 7 21:45:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2012 21:45:50 +0200 (CEST) Received: from netrider.rowland.org ([192.131.102.5]:42767 "HELO netrider.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1904117Ab2DGTpn (ORCPT ); Sat, 7 Apr 2012 21:45:43 +0200 Received: (qmail 32454 invoked by uid 500); 7 Apr 2012 15:45:37 -0400 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 7 Apr 2012 15:45:37 -0400 Date: Sat, 7 Apr 2012 15:45:37 -0400 (EDT) From: Alan Stern X-X-Sender: stern@netrider.rowland.org To: "Steven J. Hill" cc: linux-mips@linux-mips.org, , , Chris Dearman Subject: Re: [PATCH 10/10] usb: host: mips: sead3: USB Host controller support for SEAD-3 platform. In-Reply-To: <1333817979-30288-1-git-send-email-sjhill@mips.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32891 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4913 Lines: 186 On Sat, 7 Apr 2012, Steven J. Hill wrote: > From: "Steven J. Hill" > > Add EHCI driver for MIPS SEAD-3 development platform. > > Signed-off-by: Chris Dearman > Signed-off-by: Steven J. Hill > --- > drivers/usb/host/Kconfig | 4 +- > drivers/usb/host/ehci-hcd.c | 5 + > drivers/usb/host/ehci-sead3.c | 299 +++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 306 insertions(+), 2 deletions(-) > create mode 100644 drivers/usb/host/ehci-sead3.c > > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig > index f788eb8..db29a9f 100644 > --- a/drivers/usb/host/Kconfig > +++ b/drivers/usb/host/Kconfig > @@ -110,13 +110,13 @@ config USB_EHCI_BIG_ENDIAN_MMIO > depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ > ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ > PPC_MPC512x || CPU_CAVIUM_OCTEON || \ > - PMC_MSP || SPARC_LEON) > + PMC_MSP || SPARC_LEON || MIPS_SEAD3) > default y > > config USB_EHCI_BIG_ENDIAN_DESC > bool > depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ > - PPC_MPC512x || PMC_MSP || SPARC_LEON) > + PPC_MPC512x || PMC_MSP || SPARC_LEON || MIPS_SEAD3) How about wrapping this to another line, to respect the 80-column limit? > default y > > config XPS_USB_HCD_XILINX > --- /dev/null > +++ b/drivers/usb/host/ehci-sead3.c > +#ifdef CONFIG_PM > +static void mips_start_ehc(void) > +{ > + pr_debug("mips_start_ehc\n"); > +} > +#endif > + > +static void mips_stop_ehc(void) > +{ > + pr_debug("mips_start_ehc\n"); > +} Do these really need to be separate functions? Also, you should use ehci_dbg() instead of pr_debug(). Likewise throughout the rest of this file. > + > +static int mips_run(struct usb_hcd *hcd) > +{ > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > + u32 temp; > + > + temp = ehci_reset(ehci); > + if (temp != 0) { > + ehci_mem_cleanup(ehci); > + return temp; > + } > + > + return ehci_run(hcd); > +} > + > +const struct hc_driver ehci_mips_hc_driver = { > + .description = hcd_name, > + .product_desc = "MIPS EHCI", > + .hcd_priv_size = sizeof(struct ehci_hcd), > + > + /* > + * generic hardware linkage > + */ > + .irq = ehci_irq, > + .flags = HCD_MEMORY | HCD_USB2, > + > + /* > + * basic lifecycle operations > + * > + */ > + .reset = ehci_init, > + .start = mips_run, > + .stop = ehci_stop, > + .shutdown = ehci_shutdown, > + > + /* > + * managing i/o requests and associated device resources > + */ > + .urb_enqueue = ehci_urb_enqueue, > + .urb_dequeue = ehci_urb_dequeue, > + .endpoint_disable = ehci_endpoint_disable, > + > + /* > + * scheduling support > + */ > + .get_frame_number = ehci_get_frame, > + > + /* > + * root hub support > + */ > + .hub_status_data = ehci_hub_status_data, > + .hub_control = ehci_hub_control, > + .bus_suspend = ehci_bus_suspend, > + .bus_resume = ehci_bus_resume, > + .relinquish_port = ehci_relinquish_port, > + .port_handed_over = ehci_port_handed_over, > +}; This looks like it was copied from a rather old copy of ehci-au1xxx. You should allways base new work on the current version. > +static int ehci_hcd_mips_drv_probe(struct platform_device *pdev) > +{ > + struct usb_hcd *hcd; > + struct ehci_hcd *ehci; > + int ret; > + > + if (usb_disabled()) > + return -ENODEV; > + > + if (pdev->resource[1].flags != IORESOURCE_IRQ) { > + pr_debug("resource[1] is not IORESOURCE_IRQ"); > + return -ENOMEM; > + } > + hcd = usb_create_hcd(&ehci_mips_hc_driver, &pdev->dev, "MIPS"); > + if (!hcd) > + return -ENOMEM; > + > + hcd->rsrc_start = pdev->resource[0].start; > + hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; > + > + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { > + pr_debug("request_mem_region failed"); > + ret = -EBUSY; > + goto err1; > + } > + > + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); > + if (!hcd->regs) { > + pr_debug("ioremap failed"); > + ret = -ENOMEM; > + goto err2; > + } > + > + hcd->has_tt = 1; > + > + ehci = hcd_to_ehci(hcd); > + ehci->caps = hcd->regs + 0x100; Some of this (along with mips_run() above) can be replaced with a call to ehci_setup(). > + ehci->regs = hcd->regs + 0x100 + > + HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); > + /* cache this readonly data; minimize chip reads */ > + ehci->hcs_params = readl(&ehci->caps->hcs_params); > + > + /* SEAD-3 EHCI matches CPU endianness. */ > +#ifdef __BIG_ENDIAN > + ehci->big_endian_mmio = 1; > + ehci->big_endian_desc = 1; > +#endif > + > + /* Set burst length to 16 words */ > + /* FIXME: should be tunable */ > + ehci_writel(ehci, 0x1010, &ehci->regs->reserved[1]); > + > + ret = usb_add_hcd(hcd, pdev->resource[1].start, > + IRQF_DISABLED | IRQF_SHARED); > + if (ret == 0) { > + platform_set_drvdata(pdev, hcd); > + return ret; > + } Alan Stern From sjhill@mips.com Mon Apr 9 17:22:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:22:30 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39797 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903628Ab2DIPWX (ORCPT ); Mon, 9 Apr 2012 17:22:23 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQ2-0005vf-Tb; Mon, 09 Apr 2012 10:22:14 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 0/9] Add support for pure microMIPS kernel. Date: Mon, 9 Apr 2012 10:21:54 -0500 Message-Id: <1333984923-445-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32892 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3095 Lines: 66 From: "Steven J. Hill" This set of patches is to support building a pure microMIPS kernel image using only instruction from the microMIPS ISA. The result is a kernel binary reduction of more than 20% and an increase in the speed of execution due to the smaller and faster instructions. Steven J. Hill (9): MIPS: Add microMIPS configuration option. MIPS: Optimise core library functions for microMIPS. MIPS: Add support for the M14KE core. MIPS: Add microMIPS versions of breakpoints, BUG, etc. MIPS: Add support for microMIPS instructions. MIPS: Add support for microMIPS exception handling. MIPS: Support microMIPS/MIPS16e handling of delay slots. MIPS: Support microMIPS/MIPS16e unaligned accesses. MIPS: Support microMIPS/MIPS16e floating point. arch/mips/Kconfig | 10 + arch/mips/Makefile | 1 + arch/mips/configs/sead3micro_defconfig | 1757 ++++++++++++++++++++++++++++++++ arch/mips/include/asm/branch.h | 33 +- arch/mips/include/asm/break.h | 8 + arch/mips/include/asm/bug.h | 8 + arch/mips/include/asm/cpu-features.h | 3 + arch/mips/include/asm/cpu.h | 4 +- arch/mips/include/asm/dsp.h | 6 +- arch/mips/include/asm/fpu_emulator.h | 7 + arch/mips/include/asm/futex.h | 4 + arch/mips/include/asm/inst.h | 882 +++++++++++++++- arch/mips/include/asm/mipsregs.h | 359 +++---- arch/mips/include/asm/paccess.h | 2 + arch/mips/include/asm/page.h | 6 + arch/mips/include/asm/stackframe.h | 12 +- arch/mips/include/asm/uaccess.h | 14 +- arch/mips/kernel/branch.c | 183 +++- arch/mips/kernel/cpu-probe.c | 10 + arch/mips/kernel/genex.S | 82 +- arch/mips/kernel/proc.c | 27 +- arch/mips/kernel/process.c | 101 ++ arch/mips/kernel/ptrace.c | 4 + arch/mips/kernel/scall32-o32.S | 22 +- arch/mips/kernel/smtc-asm.S | 3 + arch/mips/kernel/traps.c | 377 ++++--- arch/mips/kernel/unaligned.c | 1496 +++++++++++++++++++++++---- arch/mips/lib/memcpy.S | 17 +- arch/mips/lib/memset.S | 90 +- arch/mips/lib/strlen_user.S | 13 +- arch/mips/lib/strncpy_user.S | 39 +- arch/mips/lib/strnlen_user.S | 24 +- arch/mips/math-emu/cp1emu.c | 766 ++++++++++++-- arch/mips/math-emu/dsemul.c | 40 +- arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/fault.c | 2 + arch/mips/mm/page.c | 26 +- arch/mips/mm/tlbex.c | 23 + arch/mips/mm/uasm.c | 174 +++- arch/mips/mti-sead3/sead3-init.c | 57 +- arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 4 + 42 files changed, 5877 insertions(+), 821 deletions(-) create mode 100644 arch/mips/configs/sead3micro_defconfig -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:22:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:23:04 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39795 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903630Ab2DIPWY (ORCPT ); Mon, 9 Apr 2012 17:22:24 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQ4-0005vf-Ge; Mon, 09 Apr 2012 10:22:16 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 1/9] MIPS: Add microMIPS configuration option. Date: Mon, 9 Apr 2012 10:21:55 -0500 Message-Id: <1333984923-445-2-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333984923-445-1-git-send-email-sjhill@mips.com> References: <1333984923-445-1-git-send-email-sjhill@mips.com> X-archive-position: 32893 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 47900 Lines: 1820 From: "Steven J. Hill" This adds the option to build the Linux kernel using only the microMIPS ISA. The resulting kernel binary is, at a minimum, 20% smaller than using the MIPS32R2 ISA. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 10 + arch/mips/Makefile | 1 + arch/mips/configs/sead3micro_defconfig | 1757 ++++++++++++++++++++++++++++++++ 3 files changed, 1768 insertions(+) create mode 100644 arch/mips/configs/sead3micro_defconfig diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4eae8f4..991de91 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2056,6 +2056,13 @@ config CPU_HAS_SMARTMIPS you don't know you probably don't have SmartMIPS and should say N here. +config CPU_MICROMIPS + depends on SYS_SUPPORTS_MICROMIPS + bool "Build kernel using microMIPS ISA" + help + When this option is enabled the kernel will be built using the + microMIPS ISA + config CPU_HAS_WB bool @@ -2121,6 +2128,9 @@ config SYS_SUPPORTS_HIGHMEM config SYS_SUPPORTS_SMARTMIPS bool +config SYS_SUPPORTS_MICROMIPS + bool + config ARCH_FLATMEM_ENABLE def_bool y depends on !NUMA && !CPU_LOONGSON2 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 4fedf5a..5370458 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -114,6 +114,7 @@ cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*e cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le)) cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips) +cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips -mno-jals) cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ -fno-omit-frame-pointer diff --git a/arch/mips/configs/sead3micro_defconfig b/arch/mips/configs/sead3micro_defconfig new file mode 100644 index 0000000..6bc3ea3 --- /dev/null +++ b/arch/mips/configs/sead3micro_defconfig @@ -0,0 +1,1757 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/mips 3.3.0 Kernel Configuration +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LANTIQ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +CONFIG_MIPS_SEAD3=y +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set + +# +# Clock source +# + +# +# Select one or more precise CPU clock source kernel modules below: +# +CONFIG_CSRC_R4K=y +# CONFIG_CSRC_GIC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_BOOT_RAW=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_MSC=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_GIC=y +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_BOARD_SCACHE=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +# CONFIG_MIPS_VPE_LOADER is not set +# CONFIG_CPU_HAS_SMARTMIPS is not set +CONFIG_CPU_MICROMIPS=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_FORCED_THREADING=y + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +# CONFIG_PM_RUNTIME is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +CONFIG_BQL=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +CONFIG_MTD_UBI_GLUEBI=y +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=m + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +CONFIG_MII=y +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_ENC28J60 is not set +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_8390=y +# CONFIG_AX88796 is not set +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_SEEQ=y +# CONFIG_SEEQ8005 is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_SMC91X is not set +CONFIG_SMSC911X=y +# CONFIG_SMSC911X_ARCH_HOOKS is not set +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_ICPLUS_PHY=y +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_CONSOLE_TRANSLATIONS is not set +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=32 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +CONFIG_SENSORS_ADT7475=y +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_EXYNOS_VIDEO is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LP855X is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB_ARCH_HAS_XHCI is not set +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_SPI=y +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_OT200 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +CONFIG_RTC_DRV_M41T80=y +# CONFIG_RTC_DRV_M41T80_WDT is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=y +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC7=y +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:22:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:23:34 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39798 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2DIPWZ (ORCPT ); Mon, 9 Apr 2012 17:22:25 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQ7-0005vf-5L; Mon, 09 Apr 2012 10:22:19 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 2/9] MIPS: Optimise core library functions for microMIPS. Date: Mon, 9 Apr 2012 10:21:56 -0500 Message-Id: <1333984923-445-3-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333984923-445-1-git-send-email-sjhill@mips.com> References: <1333984923-445-1-git-send-email-sjhill@mips.com> X-archive-position: 32894 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 13558 Lines: 475 From: "Steven J. Hill" Optimise some of the core library functions to use microMIPS instructions for binary size reduction. When the microMIPS ISA is not being used, the library functions compiled to binary are identical. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/page.h | 6 +++ arch/mips/lib/memcpy.S | 17 ++++++-- arch/mips/lib/memset.S | 90 ++++++++++++++++++++++++++++++------------ arch/mips/lib/strlen_user.S | 13 ++++-- arch/mips/lib/strncpy_user.S | 39 +++++++++--------- arch/mips/lib/strnlen_user.S | 24 ++++++++--- arch/mips/mm/page.c | 26 ++++++------ 7 files changed, 147 insertions(+), 68 deletions(-) diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index da9bd7d..5767678 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -45,6 +45,12 @@ #define HUGETLB_PAGE_ORDER ({BUILD_BUG(); 0; }) #endif /* CONFIG_HUGETLB_PAGE */ +/* + * Clear and copy array sizes for micro-assembly of clear_page/copy_page. + */ +#define CLEAR_PAGE_ARRAY_SIZE 288 +#define COPY_PAGE_ARRAY_SIZE 1344 + #ifndef __ASSEMBLY__ #include diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S index 56a1f85..0fa4617 100644 --- a/arch/mips/lib/memcpy.S +++ b/arch/mips/lib/memcpy.S @@ -10,6 +10,7 @@ * Copyright (C) 2002 Broadcom, Inc. * memcpy/copy_user author: Mark Vandevoorde * Copyright (C) 2007 Maciej W. Rozycki + * Copyright (C) 2011 MIPS Technologies, Inc. * * Mnemonic names for arguments to memcpy/__copy_user */ @@ -21,16 +22,14 @@ * end of memory on some systems. It's also a seriously bad idea on non * dma-coherent systems. */ -#ifdef CONFIG_DMA_NONCOHERENT -#undef CONFIG_CPU_HAS_PREFETCH -#endif -#ifdef CONFIG_MIPS_MALTA +#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_MIPS_MALTA) #undef CONFIG_CPU_HAS_PREFETCH #endif #include #include #include +#include #define dst a0 #define src a1 @@ -564,3 +563,13 @@ LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ jr ra move a2, zero END(__rmemcpy) + +LEAF(clear_page) +1: j 1b /* Dummy, will be replaced. */ + .space CLEAR_PAGE_ARRAY_SIZE + END(clear_page) + +LEAF(copy_page) +1: j 1b /* Dummy, will be replaced. */ + .space COPY_PAGE_ARRAY_SIZE + END(copy_page) diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S index 606c8a9..a0df003 100644 --- a/arch/mips/lib/memset.S +++ b/arch/mips/lib/memset.S @@ -5,7 +5,8 @@ * * Copyright (C) 1998, 1999, 2000 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki + * Copyright (C) 2007 by Maciej W. Rozycki + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include #include @@ -19,6 +20,14 @@ #define LONG_S_R sdr #endif +#ifdef CONFIG_CPU_MICROMIPS +#define STORSIZE (LONGSIZE * 2) +#define STORMASK (STORSIZE - 1) +#else +#define STORSIZE LONGSIZE +#define STORMASK LONGMASK +#endif + #define EX(insn,reg,addr,handler) \ 9: insn reg, addr; \ .section __ex_table,"a"; \ @@ -26,23 +35,36 @@ .previous .macro f_fill64 dst, offset, val, fixup - EX(LONG_S, \val, (\offset + 0 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 1 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 2 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 3 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 4 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 5 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 6 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 7 * LONGSIZE)(\dst), \fixup) +#ifdef CONFIG_CPU_MICROMIPS + EX(swp, t8, (\offset + 0 * STORSIZE)(\dst), \fixup) + EX(swp, t8, (\offset + 1 * STORSIZE)(\dst), \fixup) + EX(swp, t8, (\offset + 2 * STORSIZE)(\dst), \fixup) + EX(swp, t8, (\offset + 3 * STORSIZE)(\dst), \fixup) +#if LONGSIZE == 4 + EX(swp, t8, (\offset + 4 * STORSIZE)(\dst), \fixup) + EX(swp, t8, (\offset + 5 * STORSIZE)(\dst), \fixup) + EX(swp, t8, (\offset + 6 * STORSIZE)(\dst), \fixup) + EX(swp, t8, (\offset + 7 * STORSIZE)(\dst), \fixup) +#endif +#else + EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup) #if LONGSIZE == 4 - EX(LONG_S, \val, (\offset + 8 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 9 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 10 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 11 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 12 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 13 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 14 * LONGSIZE)(\dst), \fixup) - EX(LONG_S, \val, (\offset + 15 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup) +#endif #endif .endm @@ -71,16 +93,20 @@ LEAF(memset) 1: FEXPORT(__bzero) - sltiu t0, a2, LONGSIZE /* very small region? */ + sltiu t0, a2, STORSIZE /* very small region? */ bnez t0, .Lsmall_memset - andi t0, a0, LONGMASK /* aligned? */ + andi t0, a0, STORMASK /* aligned? */ +#ifdef CONFIG_CPU_MICROMIPS + move t8, a1 + move t9, a1 +#endif #ifndef CONFIG_CPU_DADDI_WORKAROUNDS beqz t0, 1f - PTR_SUBU t0, LONGSIZE /* alignment in bytes */ + PTR_SUBU t0, STORSIZE /* alignment in bytes */ #else .set noat - li AT, LONGSIZE + li AT, STORSIZE beqz t0, 1f PTR_SUBU t0, AT /* alignment in bytes */ .set at @@ -99,7 +125,7 @@ FEXPORT(__bzero) 1: ori t1, a2, 0x3f /* # of full blocks */ xori t1, 0x3f beqz t1, .Lmemset_partial /* no block to fill */ - andi t0, a2, 0x40-LONGSIZE + andi t0, a2, 0x40-STORSIZE PTR_ADDU t1, a0 /* end address */ .set reorder @@ -112,14 +138,26 @@ FEXPORT(__bzero) .Lmemset_partial: R10KCBARRIER(0(ra)) PTR_LA t1, 2f /* where to start */ +#ifdef CONFIG_CPU_MICROMIPS + LONG_SRL t7, t0, 1 +#if LONGSIZE == 4 + PTR_SUBU t1, t7 +#else + .set noat + LONG_SRL AT, t7, 1 + PTR_SUBU t1, AT + .set at +#endif +#else #if LONGSIZE == 4 PTR_SUBU t1, t0 #else .set noat - LONG_SRL AT, t0, 1 + LONG_SRL AT, t0, 1 PTR_SUBU t1, AT .set at #endif +#endif jr t1 PTR_ADDU a0, t0 /* dest ptr */ @@ -128,7 +166,7 @@ FEXPORT(__bzero) .set nomacro f_fill64 a0, -64, a1, .Lpartial_fixup /* ... but first do longs ... */ 2: .set pop - andi a2, LONGMASK /* At most one long to go */ + andi a2, STORMASK /* At most one long to go */ beqz a2, 1f PTR_ADDU a0, a2 /* What's left */ @@ -169,7 +207,7 @@ FEXPORT(__bzero) .Lpartial_fixup: PTR_L t0, TI_TASK($28) - andi a2, LONGMASK + andi a2, STORMASK LONG_L t0, THREAD_BUADDR(t0) LONG_ADDU a2, t1 jr ra @@ -177,4 +215,4 @@ FEXPORT(__bzero) .Llast_fixup: jr ra - andi v1, a2, LONGMASK + andi v1, a2, STORMASK diff --git a/arch/mips/lib/strlen_user.S b/arch/mips/lib/strlen_user.S index fdbb970..60fa23b 100644 --- a/arch/mips/lib/strlen_user.S +++ b/arch/mips/lib/strlen_user.S @@ -3,8 +3,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1996, 1998, 1999, 2004 by Ralf Baechle - * Copyright (c) 1999 Silicon Graphics, Inc. + * Copyright (C) 1996, 1998, 1999, 2004 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include #include @@ -28,9 +29,13 @@ LEAF(__strlen_user_asm) FEXPORT(__strlen_user_nocheck_asm) move v0, a0 -1: EX(lb, t0, (v0), .Lfault) +#ifdef CONFIG_CPU_MICROMIPS +1: EX(lbu16, v1, (v0), .Lfault) +#else +1: EX(lb, v1, (v0), .Lfault) +#endif PTR_ADDIU v0, 1 - bnez t0, 1b + bnez v1, 1b PTR_SUBU v0, a0 jr ra END(__strlen_user_asm) diff --git a/arch/mips/lib/strncpy_user.S b/arch/mips/lib/strncpy_user.S index 7201b2f..bcbb9a0 100644 --- a/arch/mips/lib/strncpy_user.S +++ b/arch/mips/lib/strncpy_user.S @@ -3,7 +3,8 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1996, 1999 by Ralf Baechle + * Copyright (C) 1996, 1999 by Ralf Baechle + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include #include @@ -30,30 +31,32 @@ LEAF(__strncpy_from_user_asm) LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a1 +#ifdef CONFIG_CPU_MICROMIPS + bnezc v0, .Lfault +#else bnez v0, .Lfault +#endif FEXPORT(__strncpy_from_user_nocheck_asm) - move v0, zero - move v1, a1 .set noreorder -1: EX(lbu, t0, (v1), .Lfault) + move t0, zero + move v1, a1 +1: EX(lbu, v0, (v1), .Lfault) PTR_ADDIU v1, 1 R10KCBARRIER(0(ra)) - beqz t0, 2f - sb t0, (a0) - PTR_ADDIU v0, 1 - .set reorder - PTR_ADDIU a0, 1 - bne v0, a2, 1b -2: PTR_ADDU t0, a1, v0 - xor t0, a1 - bltz t0, .Lfault + beqz v0, 2f + sb v0, (a0) + PTR_ADDIU t0, 1 + bne t0, a2, 1b + PTR_ADDIU a0, 1 +2: PTR_ADDU v0, a1, t0 + xor v0, a1 + bltz v0, .Lfault + nop jr ra # return n + move v0, t0 END(__strncpy_from_user_asm) -.Lfault: li v0, -EFAULT +.Lfault: jr ra - - .section __ex_table,"a" - PTR 1b, .Lfault - .previous + li v0, -EFAULT diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S index 6445716..9090ced 100644 --- a/arch/mips/lib/strnlen_user.S +++ b/arch/mips/lib/strnlen_user.S @@ -5,6 +5,7 @@ * * Copyright (c) 1996, 1998, 1999, 2004 by Ralf Baechle * Copyright (c) 1999 Silicon Graphics, Inc. + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include #include @@ -26,21 +27,34 @@ * the maximum is a tad hairier ... */ LEAF(__strnlen_user_asm) + .set noreorder LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a0 +#ifdef CONFIG_CPU_MICROMIPS + bnezc v0, .Lfault +#else bnez v0, .Lfault +#endif FEXPORT(__strnlen_user_nocheck_asm) - move v0, a0 PTR_ADDU a1, a0 # stop pointer + move v0, a0 1: beq v0, a1, 1f # limit reached? + nop EX(lb, t0, (v0), .Lfault) - PTR_ADDU v0, 1 +#ifdef CONFIG_CPU_MICROMIPS + addius5 v0, 1 + bnezc t0, 1b +1: jr ra + PTR_SUBU v0, a0 +#else bnez t0, 1b -1: PTR_SUBU v0, a0 - jr ra + PTR_ADDU v0, 1 +1: jr ra + PTR_SUBU v0, a0 +#endif END(__strnlen_user_asm) .Lfault: - move v0, zero jr ra + move v0, zero diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index cc0b626..be71d38 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -6,6 +6,7 @@ * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2007 Maciej W. Rozycki * Copyright (C) 2008 Thiemo Seufer + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include #include @@ -79,17 +80,12 @@ static struct uasm_reloc __cpuinitdata relocs[5]; * R4600 v2.0: 0x060 bytes * With prefetching, 16 word strides 0x120 bytes */ - -static u32 clear_page_array[0x120 / 4]; +u32 clear_page_array[CLEAR_PAGE_ARRAY_SIZE / 4]; #ifdef CONFIG_SIBYTE_DMA_PAGEOPS void clear_page_cpu(void *page) __attribute__((alias("clear_page_array"))); -#else -void clear_page(void *page) __attribute__((alias("clear_page_array"))); #endif -EXPORT_SYMBOL(clear_page); - /* * Maximum sizes: * @@ -98,17 +94,13 @@ EXPORT_SYMBOL(clear_page); * R4600 v2.0: 0x07c bytes * With prefetching, 16 word strides 0x540 bytes */ -static u32 copy_page_array[0x540 / 4]; +u32 copy_page_array[COPY_PAGE_ARRAY_SIZE / 4]; #ifdef CONFIG_SIBYTE_DMA_PAGEOPS void copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array"))); -#else -void copy_page(void *to, void *from) __attribute__((alias("copy_page_array"))); #endif -EXPORT_SYMBOL(copy_page); - static int pref_bias_clear_store __cpuinitdata; static int pref_bias_copy_load __cpuinitdata; @@ -368,6 +360,12 @@ void __cpuinit build_clear_page(void) for (i = 0; i < (buf - clear_page_array); i++) pr_debug("\t.word 0x%08x\n", clear_page_array[i]); pr_debug("\t.set pop\n"); +#ifdef CONFIG_CPU_MICROMIPS + memcpy(((u8 *)clear_page) - 1, clear_page_array, + ARRAY_SIZE(clear_page_array) * 4); +#else + memcpy(clear_page, clear_page_array, ARRAY_SIZE(clear_page_array) * 4); +#endif } static void __cpuinit build_copy_load(u32 **buf, int reg, int off) @@ -607,6 +605,12 @@ void __cpuinit build_copy_page(void) for (i = 0; i < (buf - copy_page_array); i++) pr_debug("\t.word 0x%08x\n", copy_page_array[i]); pr_debug("\t.set pop\n"); +#ifdef CONFIG_CPU_MICROMIPS + memcpy(((u8 *)copy_page) - 1, copy_page_array, + ARRAY_SIZE(copy_page_array) * 4); +#else + memcpy(copy_page, copy_page_array, ARRAY_SIZE(copy_page_array) * 4); +#endif } #ifdef CONFIG_SIBYTE_DMA_PAGEOPS -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:22:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:24:00 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39800 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903687Ab2DIPWZ (ORCPT ); Mon, 9 Apr 2012 17:22:25 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQ7-0005vf-TX; Mon, 09 Apr 2012 10:22:19 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 3/9] MIPS: Add support for the M14KE core. Date: Mon, 9 Apr 2012 10:21:57 -0500 Message-Id: <1333984923-445-4-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333984923-445-1-git-send-email-sjhill@mips.com> References: <1333984923-445-1-git-send-email-sjhill@mips.com> X-archive-position: 32895 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5024 Lines: 156 From: "Steven J. Hill" This patch depends on the M14K core support patch being applied first. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu-features.h | 3 +++ arch/mips/include/asm/cpu.h | 4 +++- arch/mips/kernel/cpu-probe.c | 10 ++++++++++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 2 ++ arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 4 ++++ 7 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 556afa2..3b50744 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -98,6 +98,9 @@ #ifndef kernel_uses_smartmips_rixi #define kernel_uses_smartmips_rixi 0 #endif +#ifndef cpu_has_mmips +#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) +#endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 00e5adf..242a401 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -96,6 +96,7 @@ #define PRID_IMP_1004K 0x9900 #define PRID_IMP_1074K 0x9a00 #define PRID_IMP_14K 0x9c00 +#define PRID_IMP_14KE 0x9e00 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -262,7 +263,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, - CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_1074K, CPU_14K, + CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_1074K, CPU_14K, CPU_14KE, /* * MIPS64 class processors @@ -319,6 +320,7 @@ enum cpu_type_enum { #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ +#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ /* * CPU ASE encodings diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 7d95e62..0a3e3f6 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -201,6 +201,7 @@ void __init check_wait(void) break; case CPU_14K: + case CPU_14KE: case CPU_24K: case CPU_34K: case CPU_1004K: @@ -747,6 +748,11 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->options |= MIPS_CPU_ULRI; if (config3 & MIPS_CONF3_CTXTC) c->options |= MIPS_CPU_CTXTC; + if (config3 & MIPS_CONF3_ISA) + c->options |= MIPS_CPU_MICROMIPS; +#ifdef CONFIG_CPU_MICROMIPS + write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE); +#endif return config3 & MIPS_CONF_M; } @@ -840,6 +846,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_14K; __cpu_name[cpu] = "MIPS 14Kc"; break; + case PRID_IMP_14KE: + c->cputype = CPU_14KE; + __cpu_name[cpu] = "MIPS 14KEc"; + break; case PRID_IMP_1004K: c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 9cd86fa..821a8bd 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1074,6 +1074,7 @@ static void __cpuinit probe_pcache(void) bypass1074: ; case CPU_14K: + case CPU_14KE: case CPU_24K: case CPU_34K: case CPU_1004K: diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 87f57ae..64d631e 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -461,6 +461,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, if (cpu_has_mips_r2_exec_hazard) { switch (current_cpu_type()) { case CPU_14K: + case CPU_14KE: case CPU_74K: case CPU_1074K: break; @@ -515,6 +516,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_4KC: case CPU_4KEC: case CPU_14K: + case CPU_14KE: case CPU_SB1: case CPU_SB1A: case CPU_4KSC: diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index b2e850e..09b485c 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -79,6 +79,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) switch (current_cpu_type()) { case CPU_5KC: case CPU_14K: + case CPU_14KE: case CPU_20KC: case CPU_24K: case CPU_25KF: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index fdf3ce5..9ee2aaf 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -321,6 +321,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/14K"; break; + case CPU_14KE: + op_model_mipsxx_ops.cpu_type = "mips/14KE"; + break; + case CPU_20KC: op_model_mipsxx_ops.cpu_type = "mips/20K"; break; -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:22:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:24:25 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39802 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903691Ab2DIPW1 (ORCPT ); Mon, 9 Apr 2012 17:22:27 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQ8-0005vf-GJ; Mon, 09 Apr 2012 10:22:20 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 4/9] MIPS: Add microMIPS versions of breakpoints, BUG, etc. Date: Mon, 9 Apr 2012 10:21:58 -0500 Message-Id: <1333984923-445-5-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333984923-445-1-git-send-email-sjhill@mips.com> References: <1333984923-445-1-git-send-email-sjhill@mips.com> X-archive-position: 32896 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 11120 Lines: 341 From: "Steven J. Hill" Add breakpoints, BUG() functions, DSP instruction masks, and debug messages for microMIPS. Also add '.insn' directive to a number of files that must assemble correctly when using the microMIPS or MIPS16e instruction sets. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/break.h | 8 ++++++++ arch/mips/include/asm/bug.h | 8 ++++++++ arch/mips/include/asm/dsp.h | 6 +++++- arch/mips/include/asm/futex.h | 4 ++++ arch/mips/include/asm/paccess.h | 2 ++ arch/mips/include/asm/uaccess.h | 14 ++++++++++++-- arch/mips/kernel/proc.c | 27 ++++++++++++++------------- arch/mips/kernel/ptrace.c | 4 ++++ arch/mips/mm/fault.c | 2 ++ 9 files changed, 59 insertions(+), 16 deletions(-) diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 9161e68..56758eb 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -27,6 +27,14 @@ #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ + +/* microMIPS definitions */ +#define MM_BRK_BUG 12 /* Used by BUG() */ +#define MM_BRK_KDB 13 /* Used in KDB_ENTER() */ +#define MM_BRK_MEMU 14 /* Used by FPU emulator */ +#define MM_BRK_MULOVF 15 /* Multiply overflow */ + +/* MIPS32/64 definitions */ #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ #define BRK_MEMU 514 /* Used by FPU emulator */ diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h index 540c98a..7afa2e5 100644 --- a/arch/mips/include/asm/bug.h +++ b/arch/mips/include/asm/bug.h @@ -10,7 +10,11 @@ static inline void __noreturn BUG(void) { +#ifdef CONFIG_CPU_MICROMIPS + __asm__ __volatile__("break %0" : : "i" (MM_BRK_BUG)); +#else __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); +#endif unreachable(); } @@ -27,7 +31,11 @@ static inline void __BUG_ON(unsigned long condition) return; } __asm__ __volatile__("tne $0, %0, %1" +#ifdef CONFIG_CPU_MICROMIPS + : : "r" (condition), "i" (MM_BRK_BUG)); +#else : : "r" (condition), "i" (BRK_BUG)); +#endif } #define BUG_ON(C) __BUG_ON((unsigned long)(C)) diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h index e9bfc08..ee21c2a 100644 --- a/arch/mips/include/asm/dsp.h +++ b/arch/mips/include/asm/dsp.h @@ -10,13 +10,17 @@ #ifndef _ASM_DSP_H #define _ASM_DSP_H -#include +#include #include #include #include #define DSP_DEFAULT 0x00000000 +#ifdef CONFIG_CPU_MICROMIPS +#define DSP_MASK 0x7f +#else #define DSP_MASK 0x3ff +#endif #define __enable_dsp_hazard() \ do { \ diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h index 6ebf173..007adca 100644 --- a/arch/mips/include/asm/futex.h +++ b/arch/mips/include/asm/futex.h @@ -31,6 +31,7 @@ " beqzl $1, 1b \n" \ __WEAK_LLSC_MB \ "3: \n" \ + " .insn \n" \ " .set pop \n" \ " .set mips0 \n" \ " .section .fixup,\"ax\" \n" \ @@ -57,6 +58,7 @@ " beqz $1, 1b \n" \ __WEAK_LLSC_MB \ "3: \n" \ + " .insn \n" \ " .set pop \n" \ " .set mips0 \n" \ " .section .fixup,\"ax\" \n" \ @@ -156,6 +158,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, " beqzl $1, 1b \n" __WEAK_LLSC_MB "3: \n" + " .insn \n" " .set pop \n" " .section .fixup,\"ax\" \n" "4: li %0, %6 \n" @@ -183,6 +186,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, " beqz $1, 1b \n" __WEAK_LLSC_MB "3: \n" + " .insn \n" " .set pop \n" " .section .fixup,\"ax\" \n" "4: li %0, %6 \n" diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h index 9ce5a1e..f479742 100644 --- a/arch/mips/include/asm/paccess.h +++ b/arch/mips/include/asm/paccess.h @@ -56,6 +56,7 @@ struct __large_pstruct { unsigned long buf[100]; }; "1:\t" insn "\t%1,%2\n\t" \ "move\t%0,$0\n" \ "2:\n\t" \ + ".insn\n\t" \ ".section\t.fixup,\"ax\"\n" \ "3:\tli\t%0,%3\n\t" \ "move\t%1,$0\n\t" \ @@ -94,6 +95,7 @@ extern void __get_dbe_unknown(void); "1:\t" insn "\t%1,%2\n\t" \ "move\t%0,$0\n" \ "2:\n\t" \ + ".insn\n\t" \ ".section\t.fixup,\"ax\"\n" \ "3:\tli\t%0,%3\n\t" \ "j\t2b\n\t" \ diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index 653a412..9510015 100644 --- a/arch/mips/include/asm/uaccess.h +++ b/arch/mips/include/asm/uaccess.h @@ -261,6 +261,7 @@ do { \ __asm__ __volatile__( \ "1: " insn " %1, %3 \n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -287,7 +288,9 @@ do { \ __asm__ __volatile__( \ "1: lw %1, (%3) \n" \ "2: lw %D1, 4(%3) \n" \ - "3: .section .fixup,\"ax\" \n" \ + "3: \n" \ + " .insn \n" \ + " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " move %1, $0 \n" \ " move %D1, $0 \n" \ @@ -355,6 +358,7 @@ do { \ __asm__ __volatile__( \ "1: " insn " %z2, %3 # __put_user_asm\n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -373,6 +377,7 @@ do { \ "1: sw %2, (%3) # __put_user_asm_ll32 \n" \ "2: sw %D2, 4(%3) \n" \ "3: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " j 3b \n" \ @@ -524,6 +529,7 @@ do { \ __asm__ __volatile__( \ "1: " insn " %1, %3 \n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -549,7 +555,9 @@ do { \ "1: ulw %1, (%3) \n" \ "2: ulw %D1, 4(%3) \n" \ " move %0, $0 \n" \ - "3: .section .fixup,\"ax\" \n" \ + "3: \n" \ + " .insn \n" \ + " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " move %1, $0 \n" \ " move %D1, $0 \n" \ @@ -616,6 +624,7 @@ do { \ __asm__ __volatile__( \ "1: " insn " %z2, %3 # __put_user_unaligned_asm\n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -634,6 +643,7 @@ do { \ "1: sw %2, (%3) # __put_user_unaligned_asm_ll32 \n" \ "2: sw %D2, 4(%3) \n" \ "3: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " j 3b \n" \ diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index e309665..2c0f781 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -41,29 +41,30 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", - cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); + cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); seq_printf(m, fmt, __cpu_name[n], - (version >> 4) & 0x0f, version & 0x0f, - (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); + (version >> 4) & 0x0f, version & 0x0f, + (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", - cpu_data[n].udelay_val / (500000/HZ), - (cpu_data[n].udelay_val / (5000/HZ)) % 100); + cpu_data[n].udelay_val / (500000/HZ), + (cpu_data[n].udelay_val / (5000/HZ)) % 100); seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); seq_printf(m, "microsecond timers\t: %s\n", - cpu_has_counter ? "yes" : "no"); + cpu_has_counter ? "yes" : "no"); seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); seq_printf(m, "extra interrupt vector\t: %s\n", - cpu_has_divec ? "yes" : "no"); + cpu_has_divec ? "yes" : "no"); seq_printf(m, "hardware watchpoint\t: %s", - cpu_has_watch ? "yes, " : "no\n"); + cpu_has_watch ? "yes, " : "no\n"); if (cpu_has_watch) { seq_printf(m, "count: %d, address/irw mask: [", - cpu_data[n].watch_reg_count); + cpu_data[n].watch_reg_count); for (i = 0; i < cpu_data[n].watch_reg_count; i++) seq_printf(m, "%s0x%04x", i ? ", " : "" , - cpu_data[n].watch_reg_masks[i]); + cpu_data[n].watch_reg_masks[i]); seq_printf(m, "]\n"); } + seq_printf(m, "microMIPS\t\t: %s\n", cpu_has_mmips ? "yes" : "no"); seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", cpu_has_mips16 ? " mips16" : "", cpu_has_mdmx ? " mdmx" : "", @@ -73,13 +74,13 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_has_mipsmt ? " mt" : "" ); seq_printf(m, "shadow register sets\t: %d\n", - cpu_data[n].srsets); + cpu_data[n].srsets); seq_printf(m, "kscratch registers\t: %d\n", - hweight8(cpu_data[n].kscratch_mask)); + hweight8(cpu_data[n].kscratch_mask)); seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", - cpu_has_vce ? "%u" : "not available"); + cpu_has_vce ? "%u" : "not available"); seq_printf(m, fmt, 'D', vced_count); seq_printf(m, fmt, 'I', vcei_count); seq_printf(m, "\n"); diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 7c24c29..4b4bbc0 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -364,6 +364,7 @@ long arch_ptrace(struct task_struct *child, long request, preempt_enable(); break; } +#ifndef CONFIG_CPU_MICROMIPS case DSP_BASE ... DSP_BASE + 5: { dspreg_t *dregs; @@ -384,6 +385,7 @@ long arch_ptrace(struct task_struct *child, long request, } tmp = child->thread.dsp.dspcontrol; break; +#endif default: tmp = 0; ret = -EIO; @@ -453,6 +455,7 @@ long arch_ptrace(struct task_struct *child, long request, case FPC_CSR: child->thread.fpu.fcr31 = data; break; +#ifndef CONFIG_CPU_MICROMIPS case DSP_BASE ... DSP_BASE + 5: { dspreg_t *dregs; @@ -472,6 +475,7 @@ long arch_ptrace(struct task_struct *child, long request, } child->thread.dsp.dspcontrol = data; break; +#endif default: /* The rest are not allowed. */ ret = -EIO; diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index c14f6df..bae32a7 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -25,6 +25,7 @@ #include #include #include /* For VMALLOC_END */ +#include #include /* @@ -231,6 +232,7 @@ no_context: "virtual address %0*lx, epc == %0*lx, ra == %0*lx\n", raw_smp_processor_id(), field, address, field, regs->cp0_epc, field, regs->regs[31]); + dump_tlb_all(); die("Oops", regs); out_of_memory: -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:22:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:24:52 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39804 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903692Ab2DIPW1 (ORCPT ); Mon, 9 Apr 2012 17:22:27 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQ8-0005vf-W8; Mon, 09 Apr 2012 10:22:21 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 5/9] MIPS: Add support for microMIPS instructions. Date: Mon, 9 Apr 2012 10:21:59 -0500 Message-Id: <1333984923-445-6-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333984923-445-1-git-send-email-sjhill@mips.com> References: <1333984923-445-1-git-send-email-sjhill@mips.com> X-archive-position: 32897 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 45810 Lines: 1790 From: "Steven J. Hill" The MIPS micro-assembler needs to use microMIPS instructions when building all of the core exception handlers. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/inst.h | 882 +++++++++++++++++++++++++++++++++++--- arch/mips/include/asm/mipsregs.h | 359 +++++++--------- arch/mips/mm/uasm.c | 174 +++++++- 3 files changed, 1134 insertions(+), 281 deletions(-) diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index 7ebfc39..7e8f793 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -5,8 +5,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 2000 by Ralf Baechle - * Copyright (C) 2006 by Thiemo Seufer + * Copyright (C) 1996, 2000 Ralf Baechle + * Copyright (C) 2006 Thiemo Seufer + * Copyright (C) 2011 MIPS Technologies, Inc. */ #ifndef _ASM_INST_H #define _ASM_INST_H @@ -116,7 +117,7 @@ enum bcop_op { enum cop0_coi_func { tlbr_op = 0x01, tlbwi_op = 0x02, tlbwr_op = 0x06, tlbp_op = 0x08, - rfe_op = 0x10, eret_op = 0x18 + rfe_op = 0x10, eret_op = 0x18, }; /* @@ -261,85 +262,523 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */ unsigned int fmt : 2; }; -struct b_format { /* BREAK and SYSCALL */ +struct b_format { /* BREAK and SYSCALL */ unsigned int opcode:6; unsigned int code:20; unsigned int func:6; }; +struct fb_format { /* FPU branch format */ + unsigned int opcode:6; + unsigned int bc:5; + unsigned int cc:3; + unsigned int flag:2; + unsigned int simmediate:16; +}; + +struct fp0_format { /* FPU multipy and add format (MIPS32) */ + unsigned int opcode:6; + unsigned int fmt:5; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:6; +}; + +struct mm_fp0_format { /* FPU multipy and add format (micro_mips) */ + unsigned int opcode:6; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int fmt:3; + unsigned int op:2; + unsigned int func:6; +}; + +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ + unsigned int opcode:6; + unsigned int op:5; + unsigned int rt:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:6; +}; + +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (micro_mips) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int fs:5; + unsigned int fmt:2; + unsigned int op:8; + unsigned int func:6; +}; + +struct mm_fp2_format { /* FPU movt and movf format (micro_mips) */ + unsigned int opcode:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int cc:3; + unsigned int zero:2; + unsigned int fmt:2; + unsigned int op:3; + unsigned int func:6; +}; + +struct mm_fp3_format { /* FPU abs and neg format (micro_mips) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int fs:5; + unsigned int fmt:3; + unsigned int op:7; + unsigned int func:6; +}; + +struct mm_fp4_format { /* FPU c.cond format (micro_mips) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int fs:5; + unsigned int cc:3; + unsigned int fmt:3; + unsigned int cond:4; + unsigned int func:6; +}; + +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (micro_mips) */ + unsigned int opcode:6; + unsigned int index:5; + unsigned int base:5; + unsigned int fd:5; + unsigned int op:5; + unsigned int func:6; +}; + +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ + unsigned int opcode:6; + unsigned int fr:5; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:6; +}; + +struct mm_fp6_format { /* FPU madd and msub format (micro_mips) */ + unsigned int opcode:6; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int fr:5; + unsigned int func:6; +}; + +struct mm16b1_format { /* micro_mips 16-bit branch format */ + unsigned int opcode:6; + unsigned int rs:3; + signed int simmediate:7; + unsigned int duplicate:16; /* a copy of the instn */ +}; + +struct mm16b0_format { /* micro_mips 16-bit branch format */ + unsigned int opcode:6; + signed int simmediate:10; + unsigned int duplicate:16; /* a copy of the instn */ +}; + +struct mm_i_format { /* Immediate format (addi, lw, ...) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int rs:5; + signed int simmediate:16; +}; + +/* MIPS16e */ + +struct rr { + unsigned int opcode:5; + unsigned int rx:3; + unsigned int nd:1; + unsigned int l:1; + unsigned int ra:1; + unsigned int func:5; +}; + +struct jal { + unsigned int opcode:5; + unsigned int x:1; + unsigned int imm20_16:5; + signed int imm25_21:5; + /* unsigned int imm20_15:0; here is only first 16bits in first HW */ +}; + +struct i64 { + unsigned int opcode:5; + unsigned int func:3; + unsigned int imm:8; +}; + +struct ri64 { + unsigned int opcode:5; + unsigned int func:3; + unsigned int ry:3; + unsigned int imm:5; +}; + +struct ri { + unsigned int opcode:5; + unsigned int rx:3; + unsigned int imm:8; +}; + +struct rri { + unsigned int opcode:5; + unsigned int rx:3; + unsigned int ry:3; + unsigned int imm:5; +}; + +struct i8 { + unsigned int opcode:5; + unsigned int func:3; + unsigned int imm:8; +}; + +struct mm_m_format { + unsigned int opcode:6; + unsigned int rd:5; + unsigned int base:5; + unsigned int func:4; + signed int simmediate:12; +}; + +struct mm_x_format { + unsigned int opcode:6; + unsigned int index:5; + unsigned int base:5; + unsigned int rd:5; + unsigned int func:11; +}; + +struct mm16_m_format { + unsigned int opcode:6; + unsigned int func:4; + unsigned int rlist:2; + unsigned int imm:4; + unsigned int duplicate:16; /* a copy of the instn */ +}; + +struct mm16_rb_format { + unsigned int opcode:6; + unsigned int rt:3; + unsigned int base:3; + signed int simmediate:4; + unsigned int duplicate:16; /* a copy of the instn */ +}; + +struct mm16_r5_format { + unsigned int opcode:6; + unsigned int rt:5; + signed int simmediate:5; + unsigned int duplicate:16; /* a copy of the instn */ +}; + +struct mm16_r3_format { + unsigned int opcode:6; + unsigned int rt:3; + signed int simmediate:7; + unsigned int duplicate:16; /* a copy of the instn */ +}; + #elif defined(__MIPSEL__) -struct j_format { /* Jump format */ - unsigned int target : 26; - unsigned int opcode : 6; +struct j_format { /* Jump format */ + unsigned int target:26; + unsigned int opcode:6; }; -struct i_format { /* Immediate format */ - signed int simmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; +struct i_format { /* Immediate format */ + signed int simmediate:16; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; -struct u_format { /* Unsigned immediate format */ - unsigned int uimmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; +struct u_format { /* Unsigned immediate format */ + unsigned int uimmediate:16; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; -struct c_format { /* Cache (>= R6000) format */ - unsigned int simmediate : 16; - unsigned int cache : 2; - unsigned int c_op : 3; - unsigned int rs : 5; - unsigned int opcode : 6; +struct c_format { /* Cache (>= R6000) format */ + unsigned int simmediate:16; + unsigned int cache:2; + unsigned int c_op:3; + unsigned int rs:5; + unsigned int opcode:6; }; -struct r_format { /* Register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; +struct r_format { /* Register format */ + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; -struct p_format { /* Performance counter format (R10000) */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; +struct p_format { /* Performance counter format (R10000) */ + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; -struct f_format { /* FPU register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int fmt : 4; - unsigned int : 1; - unsigned int opcode : 6; +struct f_format { /* FPU register format */ + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int fmt:4; + unsigned int:1; + unsigned int opcode:6; }; -struct ma_format { /* FPU multipy and add format (MIPS IV) */ - unsigned int fmt : 2; - unsigned int func : 4; - unsigned int fd : 5; - unsigned int fs : 5; - unsigned int ft : 5; - unsigned int fr : 5; - unsigned int opcode : 6; +struct ma_format { /* FPU multipy and add format (MIPS IV) */ + unsigned int fmt:2; + unsigned int func:4; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fr:5; + unsigned int opcode:6; }; -struct b_format { /* BREAK and SYSCALL */ +struct b_format { /* BREAK and SYSCALL */ unsigned int func:6; unsigned int code:20; unsigned int opcode:6; }; +struct fb_format { /* FPU branch format */ + unsigned int simmediate:16; + unsigned int flag:2; + unsigned int cc:3; + unsigned int bc:5; + unsigned int opcode:6; +}; + +struct fp0_format { /* FPU multipy and add format (MIPS32) */ + unsigned int func:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fmt:5; + unsigned int opcode:6; +}; + +struct mm_fp0_format { /* FPU multipy and add format (micro_mips) */ + unsigned int func:6; + unsigned int op:2; + unsigned int fmt:3; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int opcode:6; +}; + +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ + unsigned int func:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int rt:5; + unsigned int op:5; + unsigned int opcode:6; +}; + +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (micro_mips) */ + unsigned int func:6; + unsigned int op:8; + unsigned int fmt:2; + unsigned int fs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm_fp2_format { /* FPU movt and movf format (micro_mips) */ + unsigned int func:6; + unsigned int op:3; + unsigned int fmt:2; + unsigned int zero:2; + unsigned int cc:3; + unsigned int fs:5; + unsigned int fd:5; + unsigned int opcode:6; +}; + +struct mm_fp3_format { /* FPU abs and neg format (micro_mips) */ + unsigned int func:6; + unsigned int op:7; + unsigned int fmt:3; + unsigned int fs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm_fp4_format { /* FPU c.cond format (micro_mips) */ + unsigned int func:6; + unsigned int cond:4; + unsigned int fmt:3; + unsigned int cc:3; + unsigned int fs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (micro_mips) */ + unsigned int func:6; + unsigned int op:5; + unsigned int fd:5; + unsigned int base:5; + unsigned int index:5; + unsigned int opcode:6; +}; + +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ + unsigned int func:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fr:5; + unsigned int opcode:6; +}; + +struct mm_fp6_format { /* FPU madd and msub format (micro_mips) */ + unsigned int func:6; + unsigned int fr:5; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int opcode:6; +}; + +struct mm16b1_format { /* micro_mips 16-bit branch format */ + unsigned int duplicate:16; /* a copy of the instn */ + signed int simmediate:7; + unsigned int rs:3; + unsigned int opcode:6; +}; + +struct mm16b0_format { /* micro_mips 16-bit branch format */ + unsigned int duplicate:16; /* a copy of the instn */ + signed int simmediate:10; + unsigned int opcode:6; +}; + +struct mm_i_format { /* Immediate format */ + signed int simmediate:16; + unsigned int rs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +/* MIPS16e */ + +struct rr { + unsigned int func:5; + unsigned int ra:1; + unsigned int l:1; + unsigned int nd:1; + unsigned int rx:3; + unsigned int opcode:5; +}; + +struct jal { + /* unsigned int imm20_15:0; here is only first 16bits in first HW */ + signed int imm25_21:5; + unsigned int imm20_16:5; + unsigned int x:1; + unsigned int opcode:5; +}; + +struct i64 { + unsigned int imm:8; + unsigned int func:3; + unsigned int opcode:5; +}; + +struct ri64 { + unsigned int imm:5; + unsigned int ry:3; + unsigned int func:3; + unsigned int opcode:5; +}; + +struct ri { + unsigned int imm:8; + unsigned int rx:3; + unsigned int opcode:5; +}; + +struct rri { + unsigned int imm:5; + unsigned int ry:3; + unsigned int rx:3; + unsigned int opcode:5; +}; + +struct i8 { + unsigned int imm:8; + unsigned int func:3; + unsigned int opcode:5; +}; + +struct mm_m_format { + signed int simmediate:12; + unsigned int func:4; + unsigned int base:5; + unsigned int rd:5; + unsigned int opcode:6; +}; + +struct mm_x_format { + unsigned int func:11; + unsigned int rd:5; + unsigned int base:5; + unsigned int index:5; + unsigned int opcode:6; +}; + +struct mm16_m_format { + unsigned int duplicate:16; /* a copy of the instn */ + unsigned int imm:4; + unsigned int rlist:2; + unsigned int func:4; + unsigned int opcode:6; +}; + +struct mm16_rb_format { + unsigned int duplicate:16; /* a copy of the instn */ + signed int simmediate:4; + unsigned int base:3; + unsigned int rt:3; + unsigned int opcode:6; +}; + +struct mm16_r5_format { + unsigned int duplicate:16; /* a copy of the instn */ + signed int simmediate:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm16_r3_format { + unsigned int duplicate:16; /* a copy of the instn */ + signed int simmediate:7; + unsigned int rt:3; + unsigned int opcode:6; +}; + #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" #endif @@ -356,6 +795,26 @@ union mips_instruction { struct f_format f_format; struct ma_format ma_format; struct b_format b_format; + struct mm16b0_format mm16b0_format; + struct mm16b1_format mm16b1_format; + struct mm_i_format mm_i_format; + struct fb_format fb_format; + struct fp0_format fp0_format; + struct fp1_format fp1_format; + struct fp6_format fp6_format; + struct mm_fp0_format mm_fp0_format; + struct mm_fp1_format mm_fp1_format; + struct mm_fp2_format mm_fp2_format; + struct mm_fp3_format mm_fp3_format; + struct mm_fp4_format mm_fp4_format; + struct mm_fp5_format mm_fp5_format; + struct mm_fp6_format mm_fp6_format; + struct mm_m_format mm_m_format; + struct mm_x_format mm_x_format; + struct mm16_m_format mm16_m_format; + struct mm16_rb_format mm16_rb_format; + struct mm16_r3_format mm16_r3_format; + struct mm16_r5_format mm16_r5_format; }; /* HACHACHAHCAHC ... */ @@ -418,4 +877,319 @@ union mips_instruction { typedef unsigned int mips_instruction; +/* The following are for micro_mips mode */ +#define MM_16_OPCODE_SFT 10 +#define MM_NOP16 0x0c00 +#define MM_POOL32A_MINOR_MSK 0x3f +#define MM_POOL32A_MINOR_SFT 0x6 +#define MIPS32_COND_FC 0x30 + +/* + * Major opcodes; micro_mips mode. + */ +enum mm_major_op { + mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, + mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, + mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, + mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, + mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, + mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, + mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, + mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, + mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, + mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, + mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, + mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, + mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, + mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, + mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, + mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, +}; + +/* + * POOL32I minor opcodes. + */ +enum mm_32i_minor_op { + mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, + mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, + mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, + mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, + mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, + mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, + mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, + mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, + mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, +}; + +/* + * POOL32A minor opcodes. + */ +enum mm_32a_minor_op { + mm_sll32_op = 0x000, + mm_ins_op = 0x00c, + mm_ext_op = 0x02c, + mm_pool32axf_op = 0x03c, + mm_srl32_op = 0x040, + mm_sra_op = 0x080, + mm_rotr_op = 0x0c0, + mm_lwxs_op = 0x118, + mm_addu32_op = 0x150, + mm_subu32_op = 0x1d0, + mm_and_op = 0x250, + mm_or32_op = 0x290, + mm_xor32_op = 0x310, +}; + +/* + * POOL32B functions. + */ +enum mm_32b_func { + mm_lwc2_func = 0x0, + mm_lwp_func = 0x1, + mm_ldc2_func = 0x2, + mm_ldp_func = 0x4, + mm_lwm32_func = 0x5, + mm_cache_func = 0x6, + mm_ldm_func = 0x7, + mm_swc2_func = 0x8, + mm_swp_func = 0x9, + mm_sdc2_func = 0xa, + mm_sdp_func = 0xc, + mm_swm32_func = 0xd, + mm_sdm_func = 0xf, +}; + +/* + * POOL32C functions. + */ +enum mm_32c_func { + mm_pref_func = 0x2, + mm_ll_func = 0x3, + mm_swr_func = 0x9, + mm_sc_func = 0xb, + mm_lwu_func = 0xe, +}; + +/* + * POOL32AXF minor opcodes. + */ +enum mm_32axf_minor_op { + mm_mfc0_op = 0x003, + mm_mtc0_op = 0x00b, + mm_tlbp_op = 0x00d, + mm_jalr_op = 0x03c, + mm_tlbr_op = 0x04d, + mm_jalrhb_op = 0x07c, + mm_tlbwi_op = 0x08d, + mm_tlbwr_op = 0x0cd, + mm_jalrs_op = 0x13c, + mm_jalrshb_op = 0x17c, + mm_syscall_op = 0x22d, + mm_eret_op = 0x3cd, +}; + +/* + * POOL32F minor opcodes. + */ +enum mm_32f_minor_op { + mm_32f_00_op = 0x00, + mm_32f_01_op = 0x01, + mm_32f_02_op = 0x02, + mm_32f_10_op = 0x08, + mm_32f_11_op = 0x09, + mm_32f_12_op = 0x0a, + mm_32f_20_op = 0x10, + mm_32f_30_op = 0x18, + mm_32f_40_op = 0x20, + mm_32f_41_op = 0x21, + mm_32f_42_op = 0x22, + mm_32f_50_op = 0x28, + mm_32f_51_op = 0x29, + mm_32f_52_op = 0x2a, + mm_32f_60_op = 0x30, + mm_32f_70_op = 0x38, + mm_32f_73_op = 0x3b, + mm_32f_74_op = 0x3c, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_10_minor_op { + mm_lwxc1_op = 0x1, + mm_swxc1_op, + mm_ldxc1_op, + mm_sdxc1_op, + mm_luxc1_op, + mm_suxc1_op, +}; + +enum mm_32f_func { + mm_lwxc1_func = 0x048, + mm_swxc1_func = 0x088, + mm_ldxc1_func = 0x0c8, + mm_sdxc1_func = 0x108, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_40_minor_op { + mm_fmovf_op, + mm_fmovt_op, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_60_minor_op { + mm_fadd_op, + mm_fsub_op, + mm_fmul_op, + mm_fdiv_op, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_70_minor_op { + mm_fmovn_op, + mm_fmovz_op, +}; + +/* + * POOL32F secondary minor opcodes (POOL32FXF). + */ +enum mm_32f_73_minor_op { + mm_fmov0_op = 0x01, + mm_fcvtl_op = 0x04, + mm_movf0_op = 0x05, + mm_frsqrt_op = 0x08, + mm_ffloorl_op = 0x0c, + mm_fabs0_op = 0x0d, + mm_fcvtw_op = 0x24, + mm_movt0_op = 0x25, + mm_fsqrt_op = 0x28, + mm_ffloorw_op = 0x2c, + mm_fneg0_op = 0x2d, + mm_cfc1_op = 0x40, + mm_frecip_op = 0x48, + mm_fceill_op = 0x4c, + mm_fcvtd0_op = 0x4d, + mm_ctc1_op = 0x60, + mm_fceilw_op = 0x6c, + mm_fcvts0_op = 0x6d, + mm_mfc1_op = 0x80, + mm_fmov1_op = 0x81, + mm_movf1_op = 0x85, + mm_ftruncl_op = 0x8c, + mm_fabs1_op = 0x8d, + mm_mtc1_op = 0xa0, + mm_movt1_op = 0xa5, + mm_ftruncw_op = 0xac, + mm_fneg1_op = 0xad, + mm_froundl_op = 0xcc, + mm_fcvtd1_op = 0xcd, + mm_froundw_op = 0xec, + mm_fcvts1_op = 0xed, +}; + +/* + * POOL16C minor opcodes. + */ +enum mm_16c_minor_op { + mm_lwm16_op = 0x04, + mm_swm16_op = 0x05, + mm_jr16_op = 0x18, + mm_jrc_op = 0x1a, + mm_jalr16_op = 0x1c, + mm_jalrs16_op = 0x1e, +}; + +/* + * POOL16D minor opcodes. + */ +enum mm_16d_minor_op { + mm_addius5_func, + mm_addiusp_func, +}; + +struct decoded_instn { + mips_instruction insn; + mips_instruction next_insn; + int pc_inc; + int next_pc_inc; + int micro_mips_mode; +}; + +/* recode table from MIPS16e register notation to GPR */ +extern int mips16e_reg2gpr[]; + +union mips16e_instruction { + unsigned int full:16; + struct rr rr; + struct jal jal; + struct i64 i64; + struct ri64 ri64; + struct ri ri; + struct rri rri; + struct i8 i8; +}; + +enum MIPS16e_ops { + MIPS16e_jal_op = 003, + MIPS16e_ld_op = 007, + MIPS16e_i8_op = 014, + MIPS16e_sd_op = 017, + MIPS16e_lb_op = 020, + MIPS16e_lh_op = 021, + MIPS16e_lwsp_op = 022, + MIPS16e_lw_op = 023, + MIPS16e_lbu_op = 024, + MIPS16e_lhu_op = 025, + MIPS16e_lwpc_op = 026, + MIPS16e_lwu_op = 027, + MIPS16e_sb_op = 030, + MIPS16e_sh_op = 031, + MIPS16e_swsp_op = 032, + MIPS16e_sw_op = 033, + MIPS16e_rr_op = 035, + MIPS16e_extend_op = 036, + MIPS16e_i64_op = 037, +}; + +enum MIPS16e_i64_func { + MIPS16e_ldsp_func, + MIPS16e_sdsp_func, + MIPS16e_sdrasp_func, + MIPS16e_dadjsp_func, + MIPS16e_ldpc_func, +}; + +enum MIPS16e_rr_func { + MIPS16e_jr_func, +}; + +enum MIPS6e_i8_func { + MIPS16e_swrasp_func = 02, +}; + +/* + * This functions returns 1 if the micro_mips instr is a 16 bit instr. + * Otherwise return 0. + */ +#define MIPS_ISA_MODE 01 +#define is16mode(regs) (regs->cp0_epc & MIPS_ISA_MODE) + +static inline int mm_is16bit(u16 instr) +{ + /* take LS 3 bits */ + u16 opcode_low = (instr >> MM_16_OPCODE_SFT) & 0x7; + + if (opcode_low >= 1 && opcode_low <= 3) + return 1; + else + return 0; +} + #endif /* _ASM_INST_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7f87d82..a16d9d0 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -9,6 +9,7 @@ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000, 07 MIPS Technologies, Inc. * Copyright (C) 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2011 MIPS Technologies, Inc. */ #ifndef _ASM_MIPSREGS_H #define _ASM_MIPSREGS_H @@ -106,6 +107,11 @@ #define CP0_S3_SRSMAP $12 /* MIPSR2 */ /* + * Coprocessor 0 Set 5 register names + */ +#define CP0_S5_SRSMAP2 $12 /* MIPSR2 */ + +/* * TX39 Series */ #define CP0_TX39_CACHE $7 @@ -591,13 +597,18 @@ #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) +#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) +#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) -#define MIPS_CONF7_WII (_ULCAST_(1) << 31) +#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) +#define MIPS_CONF7_WII (_ULCAST_(1) << 31) +#define MIPS_CONF7_AR (_ULCAST_(1) << 16) +#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) @@ -626,10 +637,10 @@ unsigned int __res; \ __asm__ __volatile__( \ "mfpc\t%0, %1" \ - : "=r" (__res) \ + : "=r" (__res) \ : "i" (counter)); \ \ - __res; \ + __res; \ }) #define write_r10k_perf_cntr(counter,val) \ @@ -645,10 +656,10 @@ do { \ unsigned int __res; \ __asm__ __volatile__( \ "mfps\t%0, %1" \ - : "=r" (__res) \ + : "=r" (__res) \ : "i" (counter)); \ \ - __res; \ + __res; \ }) #define write_r10k_perf_cntl(counter,val) \ @@ -1073,6 +1084,9 @@ do { \ #define read_c0_srsmap() __read_32bit_c0_register($12, 3) #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) +#define read_c0_srsmap2() __read_32bit_c0_register($12, 5) +#define write_c0_srsmap2(val) __write_32bit_c0_register($12, 5, val) + #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) @@ -1144,48 +1158,31 @@ do { \ /* * Macros to access the floating point coprocessor control registers */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) - -#define rddsp(mask) \ +#define read_32bit_cp1_register(source) \ ({ \ - unsigned int __res; \ + int __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ - : "i" (mask)); \ - __res; \ -}) - -#define wrdsp(val, mask) \ -do { \ - __asm__ __volatile__( \ " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ + " .set reorder \n" \ + " # gas fails to assemble cfc1 for some archs, \n" \ + " # like Octeon. \n" \ + " .set mips1 \n" \ + " cfc1 %0,"STR(source)" \n" \ " .set pop \n" \ - : \ - : "r" (val), "i" (mask)); \ -} while (0) + : "=r" (__res)); \ + __res; \ +}) +/* + * Macros to access the DSP ASE registers + */ #if 0 /* Need DSP ASE capable assembler ... */ +#define rddsp(mask) \ +({ long dspctl; __asm__("rddsp %0, %x1" : "=r" (dspctl) : "i" (mask)); dspctl;}) + +#define wrdsp(val, mask) (__asm__("wrdsp %0, %x1" : "r" (val) : "i" (mask))) + #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) @@ -1208,230 +1205,178 @@ do { \ #else -#define mfhi0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac0 \n" \ - " .word 0x00000810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac1 \n" \ - " .word 0x00200810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac2 \n" \ - " .word 0x00400810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac3 \n" \ - " .word 0x00600810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac0 \n" \ - " .word 0x00000812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac1 \n" \ - " .word 0x00200812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac2 \n" \ - " .word 0x00400812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo3() \ +#ifdef CONFIG_CPU_MICROMIPS +#define rddsp(mask) \ ({ \ - unsigned long __treg; \ + unsigned int __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac3 \n" \ - " .word 0x00600812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mthi0(x) \ -do { \ - __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac0 \n" \ - " .word 0x00200011 \n" \ + " # rddsp $1, %x1 \n" \ + " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) -#define mthi1(x) \ +#define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mthi $1, $ac1 \n" \ - " .word 0x00200811 \n" \ + " # wrdsp $1, %x1 \n" \ + " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (mask)); \ } while (0) -#define mthi2(x) \ -do { \ +#define _umips_dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac2 \n" \ - " .word 0x00201011 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mthi3(x) \ +#define _umips_dsp_mtxxx(val, ins) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mthi $1, $ac3 \n" \ - " .word 0x00201811 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (ins)); \ } while (0) -#define mtlo0(x) \ -do { \ +#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) +#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) + +#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) +#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) + +#define mflo0() _umips_dsp_mflo(0) +#define mflo1() _umips_dsp_mflo(1) +#define mflo2() _umips_dsp_mflo(2) +#define mflo3() _umips_dsp_mflo(3) + +#define mfhi0() _umips_dsp_mfhi(0) +#define mfhi1() _umips_dsp_mfhi(1) +#define mfhi2() _umips_dsp_mfhi(2) +#define mfhi3() _umips_dsp_mfhi(3) + +#define mtlo0(x) _umips_dsp_mtlo(x, 0) +#define mtlo1(x) _umips_dsp_mtlo(x, 1) +#define mtlo2(x) _umips_dsp_mtlo(x, 2) +#define mtlo3(x) _umips_dsp_mtlo(x, 3) + +#define mthi0(x) _umips_dsp_mthi(x, 0) +#define mthi1(x) _umips_dsp_mthi(x, 1) +#define mthi2(x) _umips_dsp_mthi(x, 2) +#define mthi3(x) _umips_dsp_mthi(x, 3) + +#else /* !CONFIG_CPU_MICROMIPS */ + +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac0 \n" \ - " .word 0x00200013 \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) -#define mtlo1(x) \ +#define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac1 \n" \ - " .word 0x00200813 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (mask)); \ } while (0) -#define mtlo2(x) \ -do { \ +#define _dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac2 \n" \ - " .word 0x00201013 \n" \ + " .word (0x00000810 | %1) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mtlo3(x) \ +#define _dsp_mtxxx(val, ins) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac3 \n" \ - " .word 0x00201813 \n" \ + " .word (0x00200011 | %1) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (ins)); \ } while (0) +#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) +#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) + +#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) +#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) + +#define mflo0() _dsp_mflo(0) +#define mflo1() _dsp_mflo(1) +#define mflo2() _dsp_mflo(2) +#define mflo3() _dsp_mflo(3) + +#define mfhi0() _dsp_mfhi(0) +#define mfhi1() _dsp_mfhi(1) +#define mfhi2() _dsp_mfhi(2) +#define mfhi3() _dsp_mfhi(3) + +#define mtlo0(x) _dsp_mtlo(x, 0) +#define mtlo1(x) _dsp_mtlo(x, 1) +#define mtlo2(x) _dsp_mtlo(x, 2) +#define mtlo3(x) _dsp_mtlo(x, 3) + +#define mthi0(x) _dsp_mthi(x, 0) +#define mthi1(x) _dsp_mthi(x, 1) +#define mthi2(x) _dsp_mthi(x, 2) +#define mthi3(x) _dsp_mthi(x, 3) + +#endif /* CONFIG_CPU_MICROMIPS */ #endif /* @@ -1665,8 +1610,10 @@ __BUILD_SET_C0(status) __BUILD_SET_C0(cause) __BUILD_SET_C0(config) __BUILD_SET_C0(intcontrol) +__BUILD_SET_C0(srsctl) __BUILD_SET_C0(intctl) __BUILD_SET_C0(srsmap) +__BUILD_SET_C0(srsmap2) __BUILD_SET_C0(brcm_config_0) __BUILD_SET_C0(brcm_bus_pll) __BUILD_SET_C0(brcm_reset) diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index fb6d8e27..7351c5d 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -10,6 +10,7 @@ * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer * Copyright (C) 2005, 2007 Maciej W. Rozycki * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include @@ -38,9 +39,18 @@ enum fields { #define OP_MASK 0x3f #define OP_SH 26 #define RS_MASK 0x1f -#define RS_SH 21 #define RT_MASK 0x1f +#ifdef CONFIG_CPU_MICROMIPS +#define RS_SH 16 +#define RT_SH 21 +#define SCIMM_MASK 0x3ff +#define SCIMM_SH 16 +#else +#define RS_SH 21 #define RT_SH 16 +#define SCIMM_MASK 0xfffff +#define SCIMM_SH 6 +#endif #define RD_MASK 0x1f #define RD_SH 11 #define RE_MASK 0x1f @@ -53,8 +63,6 @@ enum fields { #define FUNC_SH 0 #define SET_MASK 0x7 #define SET_SH 0 -#define SCIMM_MASK 0xfffff -#define SCIMM_SH 6 enum opcode { insn_invalid, @@ -80,6 +88,15 @@ struct insn { }; /* This macro sets the non-variable bits of an instruction. */ +#ifdef CONFIG_CPU_MICROMIPS +#define M(a, b, c, d, e, f) \ + ((a) << OP_SH \ + | (b) << RT_SH \ + | (c) << RS_SH \ + | (d) << RD_SH \ + | (e) << RE_SH \ + | (f) << FUNC_SH) +#else #define M(a, b, c, d, e, f) \ ((a) << OP_SH \ | (b) << RS_SH \ @@ -87,10 +104,79 @@ struct insn { | (d) << RD_SH \ | (e) << RE_SH \ | (f) << FUNC_SH) +#endif +#ifdef CONFIG_CPU_MICROMIPS +static struct insn insn_table[] __uasminitdata = { + { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD }, + { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD }, + { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_beql, 0, 0 }, + { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM }, + { insn_bgezl, 0, 0 }, + { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM }, + { insn_bltzl, 0, 0 }, + { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM }, + { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM }, + { insn_daddu, 0, 0 }, + { insn_daddiu, 0, 0 }, + { insn_dmfc0, 0, 0 }, + { insn_dmtc0, 0, 0 }, + { insn_dsll, 0, 0 }, + { insn_dsll32, 0, 0 }, + { insn_dsra, 0, 0 }, + { insn_dsrl, 0, 0 }, + { insn_dsrl32, 0, 0 }, + { insn_drotr, 0, 0 }, + { insn_drotr32, 0, 0 }, + { insn_dsubu, 0, 0 }, + { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 }, + { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE }, + { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE }, + { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS }, + { insn_ld, 0, 0 }, + { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM }, + { insn_lld, 0, 0 }, + { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM }, + { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, + { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, + { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, + { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM }, + { insn_rfe, 0, 0 }, + { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM }, + { insn_scd, 0, 0 }, + { insn_sd, 0, 0 }, + { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD }, + { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD }, + { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD }, + { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, + { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, + { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 }, + { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, + { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, + { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 }, + { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD }, + { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_dins, 0, 0 }, + { insn_dinsm, 0, 0 }, + { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM}, + { insn_bbit0, 0, 0 }, + { insn_bbit1, 0, 0 }, + { insn_lwx, 0, 0 }, + { insn_ldx, 0, 0 }, + { insn_invalid, 0, 0 } +}; +#else static struct insn insn_table[] __uasminitdata = { - { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, + { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, @@ -101,8 +187,8 @@ static struct insn insn_table[] __uasminitdata = { { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, + { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, @@ -154,88 +240,112 @@ static struct insn insn_table[] __uasminitdata = { { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, { insn_invalid, 0, 0 } }; +#endif #undef M static inline __uasminit u32 build_rs(u32 arg) { - WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler RS field overflow\n"); return (arg & RS_MASK) << RS_SH; } static inline __uasminit u32 build_rt(u32 arg) { - WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RT_MASK) + printk(KERN_WARNING "Micro-assembler RT field overflow\n"); return (arg & RT_MASK) << RT_SH; } static inline __uasminit u32 build_rd(u32 arg) { - WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RD_MASK) + printk(KERN_WARNING "Micro-assembler RD field overflow\n"); return (arg & RD_MASK) << RD_SH; } static inline __uasminit u32 build_re(u32 arg) { - WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RE_MASK) + printk(KERN_WARNING "Micro-assembler RE field overflow\n"); return (arg & RE_MASK) << RE_SH; } static inline __uasminit u32 build_simm(s32 arg) { - WARN(arg > 0x7fff || arg < -0x8000, - KERN_WARNING "Micro-assembler field overflow\n"); + if (arg > 0x7fff || arg < -0x8000) + printk(KERN_WARNING "Micro-assembler SIMM field overflow\n"); return arg & 0xffff; } static inline __uasminit u32 build_uimm(u32 arg) { - WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~IMM_MASK) + printk(KERN_WARNING "Micro-assembler UIMM field overflow\n"); return arg & IMM_MASK; } static inline __uasminit u32 build_bimm(s32 arg) { - WARN(arg > 0x1ffff || arg < -0x20000, - KERN_WARNING "Micro-assembler field overflow\n"); +#ifdef CONFIG_CPU_MICROMIPS + if (arg > 0xffff || arg < -0x10000) +#else + if (arg > 0x1ffff || arg < -0x20000) +#endif + printk(KERN_WARNING "Micro-assembler BIMM field overflow\n"); - WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); + if (arg & 0x3) + printk(KERN_WARNING "Invalid micro-assembler branch target\n"); +#ifdef CONFIG_CPU_MICROMIPS + return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff); +#else return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); +#endif } static inline __uasminit u32 build_jimm(u32 arg) { - WARN(arg & ~(JIMM_MASK << 2), - KERN_WARNING "Micro-assembler field overflow\n"); +#ifdef CONFIG_CPU_MICROMIPS + if ((arg & ~((JIMM_MASK) << 1)) - 1) +#else + if (arg & ~((JIMM_MASK) << 2)) +#endif + printk(KERN_WARNING "Micro-assembler JIMM field overflow\n"); +#ifdef CONFIG_CPU_MICROMIPS + return (arg >> 1) & JIMM_MASK; +#else return (arg >> 2) & JIMM_MASK; +#endif } static inline __uasminit u32 build_scimm(u32 arg) { - WARN(arg & ~SCIMM_MASK, - KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~SCIMM_MASK) + printk(KERN_WARNING "Micro-assembler SCIMM field overflow\n"); return (arg & SCIMM_MASK) << SCIMM_SH; } static inline __uasminit u32 build_func(u32 arg) { - WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~FUNC_MASK) + printk(KERN_WARNING "Micro-assembler FUNC field overflow\n"); return arg & FUNC_MASK; } static inline __uasminit u32 build_set(u32 arg) { - WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~SET_MASK) + printk(KERN_WARNING "Micro-assembler SET field overflow\n"); return arg & SET_MASK; } @@ -263,9 +373,23 @@ static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) op = ip->match; va_start(ap, opc); if (ip->fields & RS) + { +#ifdef CONFIG_CPU_MICROMIPS + if (opc == insn_mfc0 || opc == insn_mtc0) + op |= build_rt(va_arg(ap, u32)); + else +#endif op |= build_rs(va_arg(ap, u32)); + } if (ip->fields & RT) + { +#ifdef CONFIG_CPU_MICROMIPS + if (opc == insn_mfc0 || opc == insn_mtc0) + op |= build_rs(va_arg(ap, u32)); + else +#endif op |= build_rt(va_arg(ap, u32)); + } if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); if (ip->fields & RE) @@ -286,7 +410,11 @@ static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) op |= build_scimm(va_arg(ap, u32)); va_end(ap); +#if defined(CONFIG_CPU_MICROMIPS) && defined(CONFIG_CPU_LITTLE_ENDIAN) + **buf = ((op & 0xffff) << 16) | (op >> 16); +#else **buf = op; +#endif (*buf)++; } @@ -564,7 +692,11 @@ __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) switch (rel->type) { case R_MIPS_PC16: +#if defined(CONFIG_CPU_MICROMIPS) && defined(CONFIG_CPU_LITTLE_ENDIAN) + *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16); +#else *rel->addr |= build_bimm(laddr - (raddr + 4)); +#endif break; default: -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:22:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:25:22 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39807 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2DIPW2 (ORCPT ); Mon, 9 Apr 2012 17:22:28 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQ9-0005vf-IJ; Mon, 09 Apr 2012 10:22:21 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH 6/9] MIPS: Add support for microMIPS exception handling. Date: Mon, 9 Apr 2012 10:22:00 -0500 Message-Id: <1333984923-445-7-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333984923-445-1-git-send-email-sjhill@mips.com> References: <1333984923-445-1-git-send-email-sjhill@mips.com> X-archive-position: 32898 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 32834 Lines: 1120 From: "Steven J. Hill" All exceptions must be taken in microMIPS mode, never in MIPS32R2 mode or the kernel falls apart. A few 'nop' instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/stackframe.h | 12 +- arch/mips/kernel/genex.S | 82 +++++--- arch/mips/kernel/scall32-o32.S | 22 ++- arch/mips/kernel/smtc-asm.S | 3 + arch/mips/kernel/traps.c | 377 +++++++++++++++++++++++++----------- arch/mips/mm/tlbex.c | 21 ++ arch/mips/mti-sead3/sead3-init.c | 57 +++++- 7 files changed, 424 insertions(+), 150 deletions(-) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index cb41af5..335ce06 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -139,7 +139,7 @@ 1: move ra, k0 li k0, 3 mtc0 k0, $22 -#endif /* CONFIG_CPU_LOONGSON2F */ +#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */ #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -189,6 +189,7 @@ LONG_S $0, PT_R0(sp) mfc0 v1, CP0_STATUS LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) #ifdef CONFIG_MIPS_MT_SMTC /* * Ideally, these instructions would be shuffled in @@ -200,21 +201,20 @@ LONG_S k0, PT_TCSTATUS(sp) #endif /* CONFIG_MIPS_MT_SMTC */ LONG_S $4, PT_R4(sp) - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_STATUS(sp) mfc0 v1, CP0_CAUSE - LONG_S $6, PT_R6(sp) - LONG_S $7, PT_R7(sp) + LONG_S $5, PT_R5(sp) LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) #ifdef CONFIG_64BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif + LONG_S v1, PT_EPC(sp) LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) - LONG_S v1, PT_EPC(sp) ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 8882e57..f094c82 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -3,9 +3,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 1994 - 2001, 2003 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2001, 2011 MIPS Technologies, Inc. * Copyright (C) 2002, 2007 Maciej W. Rozycki */ #include @@ -22,8 +22,10 @@ #include #include +#ifdef CONFIG_MIPS_MT_SMTC #define PANIC_PIC(msg) \ - .set push; \ + .set push; \ + .set nomicromips; \ .set reorder; \ PTR_LA a0,8f; \ .set noat; \ @@ -32,17 +34,10 @@ 9: b 9b; \ .set pop; \ TEXT(msg) +#endif __INIT -NESTED(except_vec0_generic, 0, sp) - PANIC_PIC("Exception vector 0 called") - END(except_vec0_generic) - -NESTED(except_vec1_generic, 0, sp) - PANIC_PIC("Exception vector 1 called") - END(except_vec1_generic) - /* * General exception vector for all other CPUs. * @@ -65,6 +60,7 @@ NESTED(except_vec3_generic, 0, sp) .set pop END(except_vec3_generic) +#if (cpu_has_vce != 0) /* * General exception handler for CPUs with virtual coherency exception. * @@ -124,6 +120,7 @@ handle_vcei: eret .set pop END(except_vec3_r4000) +#endif /* (cpu_has_vce == 0) */ __FINIT @@ -139,12 +136,19 @@ LEAF(r4k_wait) nop nop nop +#ifdef CONFIG_CPU_MICROMIPS + nop + nop + nop + nop +#endif .set mips3 wait /* end of rollback region (the region size must be power of two) */ - .set pop 1: jr ra + nop + .set pop END(r4k_wait) .macro BUILD_ROLLBACK_PROLOGUE handler @@ -202,7 +206,11 @@ NESTED(handle_int, PT_SIZE, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) PTR_LA ra, ret_from_irq - j plat_irq_dispatch + PTR_LA v0, plat_irq_dispatch + jr v0 +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif END(handle_int) __INIT @@ -223,11 +231,14 @@ NESTED(except_vec4, 0, sp) /* * EJTAG debug exception handler. * The EJTAG debug exception entry point is 0xbfc00480, which - * normally is in the boot PROM, so the boot PROM must do a + * normally is in the boot PROM, so the boot PROM must do an * unconditional jump to this vector. */ NESTED(except_vec_ejtag_debug, 0, sp) j ejtag_debug_handler +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif END(except_vec_ejtag_debug) __FINIT @@ -252,9 +263,10 @@ NESTED(except_vec_vi, 0, sp) FEXPORT(except_vec_vi_mori) ori a0, $0, 0 #endif /* CONFIG_MIPS_MT_SMTC */ + PTR_LA v1, except_vec_vi_handler FEXPORT(except_vec_vi_lui) lui v0, 0 /* Patched */ - j except_vec_vi_handler + jr v1 FEXPORT(except_vec_vi_ori) ori v0, 0 /* Patched */ .set pop @@ -355,6 +367,9 @@ EXPORT(ejtag_debug_buffer) */ NESTED(except_vec_nmi, 0, sp) j nmi_handler +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif END(except_vec_nmi) __FINIT @@ -363,7 +378,7 @@ NESTED(nmi_handler, PT_SIZE, sp) .set push .set noat SAVE_ALL - move a0, sp + move a0, sp jal nmi_exception_handler RESTORE_ALL .set mips3 @@ -501,13 +516,36 @@ NESTED(nmi_handler, PT_SIZE, sp) .set push .set noat .set noreorder - /* 0x7c03e83b: rdhwr v1,$29 */ + /* MIPS32: 0x7c03e83b: rdhwr v1,$29 */ + /* uMIPS: 0x007d6b3c: rdhwr v1,$29 -- in MIPS16e it is */ + /* ADDIUSP $16,0x7d; LI $3,0x3c and never RI. LY22 */ MFC0 k1, CP0_EPC - lui k0, 0x7c03 - lw k1, (k1) - ori k0, 0xe83b - .set reorder +#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2) + and k0, k1, 1 + beqz k0, 1f + xor k1, k0 + lhu k0, (k1) + lhu k1, 2(k1) + ins k1, k0, 16, 16 + lui k0, 0x007d + b docheck + ori k0, 0x6b3c +1: + lui k0, 0x7c03 + lw k1, (k1) + ori k0, 0xe83b +#else + andi k0, k1, 1 + bnez k0, handle_ri + lui k0, 0x7c03 + lw k1, (k1) + ori k0, 0xe83b +#endif + .set reorder +docheck: bne k0, k1, handle_ri /* if not ours */ + +isrdhwr: /* The insn is rdhwr. No need to check CAUSE.BD here. */ get_saved_sp /* k1 := current_thread_info */ .set noreorder diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index a632bc1..62e7cff 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -143,15 +143,29 @@ stackargs: jr t1 addiu t1, 6f - 5f -2: lw t8, 28(t0) # argument #8 from usp -3: lw t7, 24(t0) # argument #7 from usp -4: lw t6, 20(t0) # argument #6 from usp -5: jr t1 +2: .insn + lw t8, 28(t0) # argument #8 from usp +3: .insn + lw t7, 24(t0) # argument #7 from usp +4: .insn + lw t6, 20(t0) # argument #6 from usp +5: .insn + jr t1 sw t5, 16(sp) # argument #5 to ksp +#ifdef CONFIG_CPU_MICROMIPS + ## FIXME: + sw t8, 28(sp) # argument #8 to ksp + nop + sw t7, 24(sp) # argument #7 to ksp + nop + sw t6, 20(sp) # argument #6 to ksp + nop +#else sw t8, 28(sp) # argument #8 to ksp sw t7, 24(sp) # argument #7 to ksp sw t6, 20(sp) # argument #6 to ksp +#endif 6: j stack_done # go back nop .set pop diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index 20938a4..8e9ae50 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S @@ -49,6 +49,9 @@ CAN WE PROVE THAT WE WON'T DO THIS IF INTS DISABLED?? .text .align 5 FEXPORT(__smtc_ipi_vector) +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif .set noat /* Disable thread scheduling to make Status update atomic */ DMT 27 # dmt k1 diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index f4858a0..b88e63d 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -10,6 +10,7 @@ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000, 01 MIPS Technologies, Inc. * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include #include @@ -81,10 +82,6 @@ extern asmlinkage void handle_dsp(void); extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); -extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, - struct mips_fpu_struct *ctx, int has_fpu, - void *__user *fault_addr); - void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); void (*board_nmi_handler_setup)(void); @@ -92,6 +89,7 @@ void (*board_ejtag_handler_setup)(void); void (*board_bind_eic_interrupt)(int irq, int regset); void (*board_ebase_setup)(void); +static void mt_ase_fp_affinity(void); static void show_raw_backtrace(unsigned long reg29) { @@ -487,6 +485,12 @@ asmlinkage void do_be(struct pt_regs *regs) #define SYNC 0x0000000f #define RDHWR 0x0000003b +/* microMIPS definitions */ +#define MM_POOL32A_FUNC 0xfc00ffff +#define MM_RDHWR 0x00006b3c +#define MM_RS 0x001f0000 +#define MM_RT 0x03e00000 + /* * The ll_bit is cleared by r*_switch.S */ @@ -510,7 +514,7 @@ static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); if ((unsigned long)vaddr & 3) return SIGBUS; @@ -550,7 +554,7 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); reg = (opcode & RT) >> 16; if ((unsigned long)vaddr & 3) @@ -601,48 +605,72 @@ static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) * Simulate trapping 'rdhwr' instructions to provide user accessible * registers not implemented in hardware. */ -static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) +static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) { struct thread_info *ti = task_thread_info(current); + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, regs, 0); + switch (rd) { + case 0: /* CPU number */ + regs->regs[rt] = smp_processor_id(); + return 0; + case 1: /* SYNCI length */ + regs->regs[rt] = min(current_cpu_data.dcache.linesz, + current_cpu_data.icache.linesz); + return 0; + case 2: /* Read count register */ + regs->regs[rt] = read_c0_count(); + return 0; + case 3: /* Count register resolution */ + switch (current_cpu_data.cputype) { + case CPU_20KC: + case CPU_25KF: + regs->regs[rt] = 1; + break; + default: + regs->regs[rt] = 2; + } + return 0; + case 29: + regs->regs[rt] = ti->tp_value; + return 0; + default: + return -1; + } +} + +static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) +{ if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { int rd = (opcode & RD) >> 11; int rt = (opcode & RT) >> 16; - perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, - 1, regs, 0); - switch (rd) { - case 0: /* CPU number */ - regs->regs[rt] = smp_processor_id(); - return 0; - case 1: /* SYNCI length */ - regs->regs[rt] = min(current_cpu_data.dcache.linesz, - current_cpu_data.icache.linesz); - return 0; - case 2: /* Read count register */ - regs->regs[rt] = read_c0_count(); - return 0; - case 3: /* Count register resolution */ - switch (current_cpu_data.cputype) { - case CPU_20KC: - case CPU_25KF: - regs->regs[rt] = 1; - break; - default: - regs->regs[rt] = 2; - } - return 0; - case 29: - regs->regs[rt] = ti->tp_value; - return 0; - default: - return -1; - } + + simulate_rdhwr(regs, rd, rt); + return 0; + } + + /* Not ours. */ + return -1; +} + +static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) +{ + if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { + int rd = (opcode & MM_RS) >> 16; + int rt = (opcode & MM_RT) >> 21; + simulate_rdhwr(regs, rd, rt); + return 0; } /* Not ours. */ return -1; } + + + + static int simulate_sync(struct pt_regs *regs, unsigned int opcode) { if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { @@ -667,7 +695,7 @@ asmlinkage void do_ov(struct pt_regs *regs) force_sig_info(SIGFPE, &info, current); } -static int process_fpemu_return(int sig, void __user *fault_addr) +int process_fpemu_return(int sig, void __user *fault_addr) { if (sig == SIGSEGV || sig == SIGBUS) { struct siginfo si = {0}; @@ -789,10 +817,12 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; + case MM_BRK_BUG: case BRK_BUG: die_if_kernel("Kernel bug detected", regs); force_sig(SIGTRAP, current); break; + case MM_BRK_MEMU: case BRK_MEMU: /* * Address errors may be deliberately induced by the FPU @@ -818,9 +848,29 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, asmlinkage void do_bp(struct pt_regs *regs) { unsigned int opcode, bcode; - - if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) - goto out_sigsegv; + unsigned long epc; + u16 instr[2]; + + if (regs->cp0_epc & MIPS_ISA_MODE) { + /* calc exception pc */ + epc = exception_epc(regs); + if (cpu_has_mmips) { + if ((__get_user(instr[0], (u16 __user *)(epc & ~MIPS_ISA_MODE))) || + (__get_user(instr[1], (u16 __user *)((epc+2) & ~MIPS_ISA_MODE)))) + goto out_sigsegv; + opcode = (instr[0] << 16) | instr[1]; + } else { + /* MIPS16e mode */ + if (__get_user(instr[0], (u16 __user *)(epc & ~MIPS_ISA_MODE))) + goto out_sigsegv; + bcode = (instr[0] >> 6) & 0x3f; + do_trap_or_bp(regs, bcode, "Break"); + return; + } + } else { + if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) + goto out_sigsegv; + } /* * There is the ancient bug in the MIPS assemblers that the break @@ -861,13 +911,22 @@ out_sigsegv: asmlinkage void do_tr(struct pt_regs *regs) { unsigned int opcode, tcode = 0; + u16 instr[2]; + unsigned long epc = exception_epc(regs); - if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) - goto out_sigsegv; + if ((__get_user(instr[0], (u16 __user *)(epc & ~MIPS_ISA_MODE))) || + (__get_user(instr[1], (u16 __user *)((epc+2) & ~MIPS_ISA_MODE)))) + goto out_sigsegv; + opcode = (instr[0] << 16) | instr[1]; /* Immediate versions don't provide a code. */ - if (!(opcode & OPCODE)) - tcode = ((opcode >> 6) & ((1 << 10) - 1)); + if (!(opcode & OPCODE)) { + if (is16mode(regs)) + /* microMIPS */ + tcode = (opcode >> 12) & 0x1f; + else + tcode = ((opcode >> 6) & ((1 << 10) - 1)); + } do_trap_or_bp(regs, tcode, "Trap"); return; @@ -880,8 +939,10 @@ asmlinkage void do_ri(struct pt_regs *regs) { unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); unsigned long old_epc = regs->cp0_epc; + unsigned long old31 = regs->regs[31]; unsigned int opcode = 0; int status = -1; + unsigned short mmop[2]; if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) == NOTIFY_STOP) @@ -892,23 +953,35 @@ asmlinkage void do_ri(struct pt_regs *regs) if (unlikely(compute_return_epc(regs) < 0)) return; - if (unlikely(get_user(opcode, epc) < 0)) - status = SIGSEGV; + if (is16mode(regs)) { + if (unlikely(get_user(mmop[0], epc) < 0)) + status = SIGSEGV; + if (unlikely(get_user(mmop[1], epc) < 0)) + status = SIGSEGV; + opcode = (mmop[0] << 16) | mmop[1]; - if (!cpu_has_llsc && status < 0) - status = simulate_llsc(regs, opcode); + if (status < 0) + status = simulate_rdhwr_mm(regs, opcode); + } else { + if (unlikely(get_user(opcode, epc) < 0)) + status = SIGSEGV; - if (status < 0) - status = simulate_rdhwr(regs, opcode); + if (!cpu_has_llsc && status < 0) + status = simulate_llsc(regs, opcode); - if (status < 0) - status = simulate_sync(regs, opcode); + if (status < 0) + status = simulate_rdhwr_normal(regs, opcode); + + if (status < 0) + status = simulate_sync(regs, opcode); + } if (status < 0) status = SIGILL; if (unlikely(status > 0)) { - regs->cp0_epc = old_epc; /* Undo skip-over. */ + regs->cp0_epc = old_epc; /* Undo skip-over. */ + regs->regs[31] = old31; force_sig(status, current); } } @@ -978,11 +1051,12 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action, asmlinkage void do_cpu(struct pt_regs *regs) { unsigned int __user *epc; - unsigned long old_epc; + unsigned long old_epc, old31; unsigned int opcode; unsigned int cpid; int status; unsigned long __maybe_unused flags; + unsigned short mmop[2]; die_if_kernel("do_cpu invoked from kernel context!", regs); @@ -992,26 +1066,39 @@ asmlinkage void do_cpu(struct pt_regs *regs) case 0: epc = (unsigned int __user *)exception_epc(regs); old_epc = regs->cp0_epc; + old31 = regs->regs[31]; opcode = 0; status = -1; if (unlikely(compute_return_epc(regs) < 0)) return; - if (unlikely(get_user(opcode, epc) < 0)) - status = SIGSEGV; + if (is16mode(regs)) { + if (unlikely(get_user(mmop[0], epc) < 0)) + status = SIGSEGV; + if (unlikely(get_user(mmop[1], epc) < 0)) + status = SIGSEGV; + opcode = (mmop[0] << 16) | mmop[1]; - if (!cpu_has_llsc && status < 0) - status = simulate_llsc(regs, opcode); + if (status < 0) + status = simulate_rdhwr_mm(regs, opcode); + } else { + if (unlikely(get_user(opcode, epc) < 0)) + status = SIGSEGV; - if (status < 0) - status = simulate_rdhwr(regs, opcode); + if (!cpu_has_llsc && status < 0) + status = simulate_llsc(regs, opcode); + + if (status < 0) + status = simulate_rdhwr_normal(regs, opcode); + } if (status < 0) status = SIGILL; if (unlikely(status > 0)) { - regs->cp0_epc = old_epc; /* Undo skip-over. */ + regs->cp0_epc = old_epc; /* Undo skip-over. */ + regs->regs[31] = old31; force_sig(status, current); } @@ -1208,6 +1295,7 @@ static inline void parity_protection_init(void) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_1074K: { #define ERRCTL_PE 0x80000000 #define ERRCTL_L2P 0x00800000 @@ -1323,7 +1411,7 @@ asmlinkage void cache_parity_error(void) void ejtag_exception_handler(struct pt_regs *regs) { const int field = 2 * sizeof(unsigned long); - unsigned long depc, old_epc; + unsigned long depc, old_epc, old_ra; unsigned int debug; printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); @@ -1338,10 +1426,12 @@ void ejtag_exception_handler(struct pt_regs *regs) * calculation. */ old_epc = regs->cp0_epc; + old_ra = regs->regs[31]; regs->cp0_epc = depc; - __compute_return_epc(regs); + compute_return_epc(regs); depc = regs->cp0_epc; regs->cp0_epc = old_epc; + regs->regs[31] = old_ra; } else depc += 4; write_c0_depc(depc); @@ -1377,14 +1467,59 @@ unsigned long ebase; unsigned long exception_handlers[32]; unsigned long vi_handlers[64]; +/* Install CPU exception handler */ +void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) +{ +#ifdef CONFIG_CPU_MICROMIPS + memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); +#else + memcpy((void *)(ebase + offset), addr, size); +#endif + local_flush_icache_range(ebase + offset, ebase + offset + size); +} + +static char panic_null_cerr[] __cpuinitdata = + "Trying to set NULL cache error exception handler"; + +/* + * Install uncached CPU exception handler. + * This is suitable only for the cache error exception which is the only + * exception handler that is being run uncached. + */ +void __cpuinit set_uncached_handler(unsigned long offset, void *addr, + unsigned long size) +{ + unsigned long uncached_ebase = CKSEG1ADDR(ebase); + + if (!addr) + panic(panic_null_cerr); + + memcpy((void *)(uncached_ebase + offset), addr, size); +} + void __init *set_except_vector(int n, void *addr) { unsigned long handler = (unsigned long) addr; unsigned long old_handler = exception_handlers[n]; +#ifdef CONFIG_CPU_MICROMIPS + /* + * Only the TLB handlers are cache aligned with an even + * address. All other handlers are on an odd address and + * require no modification. Otherwise, MIPS32 mode will + * be entered when handling any TLB exceptions. That + * would be bad...since we must stay in microMIPS mode. + */ + if (!(handler & 0x1)) + handler |= 1; +#endif exception_handlers[n] = handler; if (n == 0 && cpu_has_divec) { +#ifdef CONFIG_CPU_MICROMIPS + unsigned long jump_mask = ~((1 << 27) - 1); +#else unsigned long jump_mask = ~((1 << 28) - 1); +#endif u32 *buf = (u32 *)(ebase + 0x200); unsigned int k0 = 26; if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { @@ -1411,17 +1546,18 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) unsigned long handler; unsigned long old_handler = vi_handlers[n]; int srssets = current_cpu_data.srsets; - u32 *w; + u16 *h; unsigned char *b; BUG_ON(!cpu_has_veic && !cpu_has_vint); + BUG_ON((n < 0) && (n > 9)); if (addr == NULL) { handler = (unsigned long) do_default_vi; srs = 0; } else handler = (unsigned long) addr; - vi_handlers[n] = (unsigned long) addr; + vi_handlers[n] = handler; b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); @@ -1434,15 +1570,21 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) } else if (cpu_has_vint) { /* SRSMap is only defined if shadow sets are implemented */ if (srssets > 1) - change_c0_srsmap(0xf << n*4, srs << n*4); + { + if (n < 8) + change_c0_srsmap(0xf << (n * 4), + srs << (n * 4)); + else + change_c0_srsmap2(0xf << ((n - 8) * 4), + srs << ((n - 8) * 4)); + } } if (srs == 0) { /* * If no shadow set is selected then use the default handler - * that does normal register saving and a standard interrupt exit + * that does normal register saving and standard interrupt exit */ - extern char except_vec_vi, except_vec_vi_lui; extern char except_vec_vi_ori, except_vec_vi_end; extern char rollback_except_vec_vi; @@ -1455,11 +1597,20 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * Status.IM bit to be masked before going there. */ extern char except_vec_vi_mori; +#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) + const int mori_offset = &except_vec_vi_mori - vec_start + 2; +#else const int mori_offset = &except_vec_vi_mori - vec_start; +#endif #endif /* CONFIG_MIPS_MT_SMTC */ - const int handler_len = &except_vec_vi_end - vec_start; +#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) + const int lui_offset = &except_vec_vi_lui - vec_start + 2; + const int ori_offset = &except_vec_vi_ori - vec_start + 2; +#else const int lui_offset = &except_vec_vi_lui - vec_start; const int ori_offset = &except_vec_vi_ori - vec_start; +#endif + const int handler_len = &except_vec_vi_end - vec_start; if (handler_len > VECTORSPACING) { /* @@ -1469,30 +1620,44 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) panic("VECTORSPACING too small"); } - memcpy(b, vec_start, handler_len); + set_handler(((unsigned long)b - ebase), vec_start, +#ifdef CONFIG_CPU_MICROMIPS + (handler_len - 1)); +#else + handler_len); +#endif #ifdef CONFIG_MIPS_MT_SMTC BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ - w = (u32 *)(b + mori_offset); - *w = (*w & 0xffff0000) | (0x100 << n); + h = (u16 *)(b + mori_offset); + *h = (0x100 << n); #endif /* CONFIG_MIPS_MT_SMTC */ - w = (u32 *)(b + lui_offset); - *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); - w = (u32 *)(b + ori_offset); - *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); + h = (u16 *)(b + lui_offset); + *h = (handler >> 16) & 0xffff; + h = (u16 *)(b + ori_offset); + *h = (handler & 0xffff); local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } else { /* - * In other cases jump directly to the interrupt handler - * - * It is the handlers responsibility to save registers if required - * (eg hi/lo) and return from the exception using "eret" + * In other cases jump directly to the interrupt handler. It + * is the handler's responsibility to save registers if required + * (eg hi/lo) and return from the exception using "eret". */ - w = (u32 *)b; - *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ - *w = 0; + u32 insn; + + h = (u16 *)b; + /* j handler */ +#ifdef CONFIG_CPU_MICROMIPS + insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); +#else + insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); +#endif + h[0] = (insn >> 16) & 0xffff; + h[1] = insn & 0xffff; + h[2] = 0; + h[3] = 0; local_flush_icache_range((unsigned long)b, (unsigned long)(b+8)); } @@ -1607,7 +1772,11 @@ void __cpuinit per_cpu_trap_init(void) if (cpu_has_mips_r2) { cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; + if (!cp0_compare_irq) + cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; + if (!cp0_perfcount_irq) + cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; if (cp0_perfcount_irq == cp0_compare_irq) cp0_perfcount_irq = -1; } else { @@ -1646,32 +1815,6 @@ void __cpuinit per_cpu_trap_init(void) TLBMISS_HANDLER_SETUP(); } -/* Install CPU exception handler */ -void __init set_handler(unsigned long offset, void *addr, unsigned long size) -{ - memcpy((void *)(ebase + offset), addr, size); - local_flush_icache_range(ebase + offset, ebase + offset + size); -} - -static char panic_null_cerr[] __cpuinitdata = - "Trying to set NULL cache error exception handler"; - -/* - * Install uncached CPU exception handler. - * This is suitable only for the cache error exception which is the only - * exception handler that is being run uncached. - */ -void __cpuinit set_uncached_handler(unsigned long offset, void *addr, - unsigned long size) -{ - unsigned long uncached_ebase = CKSEG1ADDR(ebase); - - if (!addr) - panic(panic_null_cerr); - - memcpy((void *)(uncached_ebase + offset), addr, size); -} - static int __initdata rdhwr_noopt; static int __init set_rdhwr_noopt(char *str) { @@ -1683,8 +1826,11 @@ __setup("rdhwr_noopt", set_rdhwr_noopt); void __init trap_init(void) { - extern char except_vec3_generic, except_vec3_r4000; + extern char except_vec3_generic; extern char except_vec4; +#if (cpu_has_vce != 0) + extern char except_vec3_r4000; +#endif unsigned long i; int rollback; @@ -1812,13 +1958,16 @@ void __init trap_init(void) set_except_vector(26, handle_dsp); +#if (cpu_has_vce != 0) if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); - else if (cpu_has_4kex) - memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); + set_handler(0x180, &except_vec3_r4000, 0x100); + else +#endif + if (cpu_has_4kex) + set_handler(0x180, &except_vec3_generic, 0x80); else - memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); + set_handler(0x080, &except_vec3_generic, 0x80); local_flush_icache_range(ebase, ebase + 0x400); flush_tlb_handlers(); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 64d631e..4bebe04 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2021,6 +2021,13 @@ static void __cpuinit build_r4000_tlb_load_handler(void) uasm_l_nopage_tlbl(&l, p); build_restore_work_registers(&p); +#ifdef CONFIG_CPU_MICROMIPS + if ((unsigned long)tlb_do_page_fault_0 & 1) { + uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); + uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); + uasm_i_jr(&p, K0); + } else +#endif uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); uasm_i_nop(&p); @@ -2068,6 +2075,13 @@ static void __cpuinit build_r4000_tlb_store_handler(void) uasm_l_nopage_tlbs(&l, p); build_restore_work_registers(&p); +#ifdef CONFIG_CPU_MICROMIPS + if ((unsigned long)tlb_do_page_fault_1 & 1) { + uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); + uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); + uasm_i_jr(&p, K0); + } else +#endif uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); @@ -2116,6 +2130,13 @@ static void __cpuinit build_r4000_tlb_modify_handler(void) uasm_l_nopage_tlbm(&l, p); build_restore_work_registers(&p); +#ifdef CONFIG_CPU_MICROMIPS + if ((unsigned long)tlb_do_page_fault_1 & 1) { + uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); + uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); + uasm_i_jr(&p, K0); + } else +#endif uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c index 14e0c49..f4ca42b 100644 --- a/arch/mips/mti-sead3/sead3-init.c +++ b/arch/mips/mti-sead3/sead3-init.c @@ -22,9 +22,9 @@ #include #include #include +#include #include -#include #include #include #include @@ -97,14 +97,14 @@ int get_ethernet_addr(char *ethernet_addr) ethaddr_str = prom_getenv("ethaddr"); if (!ethaddr_str) { - printk("ethaddr not set in boot prom\n"); + printk(KERN_WARN "ethaddr not set in boot prom\n"); return -1; } str2eaddr(ethernet_addr, ethaddr_str); if (init_debug > 1) { int i; - printk("get_ethernet_addr: "); + printk(KERN_DEBUG "get_ethernet_addr: "); for (i = 0; i < 5; i++) printk("%02x:", (unsigned char)*(ethernet_addr+i)); printk("%02x\n", *(ethernet_addr+i)); @@ -147,7 +147,8 @@ static void __init console_config(void) bits = '8'; if (flow == '\0') flow = 'r'; - sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, + parity, bits, flow); strcat(prom_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } @@ -162,7 +163,41 @@ static void __init mips_nmi_setup(void) base = cpu_has_veic ? (void *)(CAC_BASE + 0xa80) : (void *)(CAC_BASE + 0x380); +#ifdef CONFIG_CPU_MICROMIPS + /* + * Decrement the exception vector address by one for microMIPS. + */ + memcpy(base, (&except_vec_nmi - 1), 0x80); + + /* + * This is a hack. We do not know if the boot loader was built with + * microMIPS instructions or not. If it was not, the NMI exception + * code at 0x80000a80 will be taken in MIPS32 mode. The hand coded + * assembly below forces us into microMIPS mode if we are a pure + * microMIPS kernel. The assembly instructions are: + * + * 3C1A8000 lui k0,0x8000 + * 375A0381 ori k0,k0,0x381 + * 03400008 jr k0 + * 00000000 nop + * + * The mode switch occurs by jumping to the unaligned exception + * vector address at 0x80000381 which would have been 0x80000380 + * in MIPS32 mode. The jump to the unaligned address transitions + * us into microMIPS mode. + */ + if (!cpu_has_veic) { + void *base2 = (void *)(CAC_BASE + 0xa80); + *((unsigned int *)base2) = 0x3c1a8000; + *((unsigned int *)base2 + 1) = 0x375a0381; + *((unsigned int *)base2 + 2) = 0x03400008; + *((unsigned int *)base2 + 3) = 0x00000000; + flush_icache_range((unsigned long)base2, + (unsigned long)base2 + 0x10); + } +#else memcpy(base, &except_vec_nmi, 0x80); +#endif flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } @@ -174,7 +209,21 @@ static void __init mips_ejtag_setup(void) base = cpu_has_veic ? (void *)(CAC_BASE + 0xa00) : (void *)(CAC_BASE + 0x300); +#ifdef CONFIG_CPU_MICROMIPS + /* Deja vu... */ + memcpy(base, (&except_vec_ejtag_debug - 1), 0x80); + if (!cpu_has_veic) { + void *base2 = (void *)(CAC_BASE + 0xa00); + *((unsigned int *)base2) = 0x3c1a8000; + *((unsigned int *)base2 + 1) = 0x375a0301; + *((unsigned int *)base2 + 2) = 0x03400008; + *((unsigned int *)base2 + 3) = 0x00000000; + flush_icache_range((unsigned long)base2, + (unsigned long)base2 + 0x10); + } +#else memcpy(base, &except_vec_ejtag_debug, 0x80); +#endif flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:22:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:25:46 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39808 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903694Ab2DIPW2 (ORCPT ); Mon, 9 Apr 2012 17:22:28 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQA-0005vf-G1; Mon, 09 Apr 2012 10:22:22 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Leonid Yegoshin Subject: [PATCH 7/9] MIPS: Support microMIPS/MIPS16e handling of delay slots. Date: Mon, 9 Apr 2012 10:22:01 -0500 Message-Id: <1333984923-445-8-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333984923-445-1-git-send-email-sjhill@mips.com> References: <1333984923-445-1-git-send-email-sjhill@mips.com> X-archive-position: 32899 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7369 Lines: 295 From: "Steven J. Hill" Add logic needed to properly calculate exceptions for delay slots when in microMIPS or MIPS16e mode. Signed-off-by: Leonid Yegoshin Signed-off-by: Steven J. Hill --- arch/mips/include/asm/branch.h | 33 +++++++- arch/mips/kernel/branch.c | 183 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 213 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h index 888766a..ccc938a 100644 --- a/arch/mips/include/asm/branch.h +++ b/arch/mips/include/asm/branch.h @@ -16,11 +16,16 @@ static inline int delay_slot(struct pt_regs *regs) return regs->cp0_cause & CAUSEF_BD; } +extern int __isa_exception_epc(struct pt_regs *regs); + static inline unsigned long exception_epc(struct pt_regs *regs) { - if (!delay_slot(regs)) + if (likely(!delay_slot(regs))) return regs->cp0_epc; + if (is16mode(regs)) + return __isa_exception_epc(regs); + return regs->cp0_epc + 4; } @@ -29,9 +34,20 @@ static inline unsigned long exception_epc(struct pt_regs *regs) extern int __compute_return_epc(struct pt_regs *regs); extern int __compute_return_epc_for_insn(struct pt_regs *regs, union mips_instruction insn); +extern int __MIPS16e_compute_return_epc(struct pt_regs *regs); +extern int __microMIPS_compute_return_epc(struct pt_regs *regs); +/* only for MIPS32/64 but not 16bits variants */ static inline int compute_return_epc(struct pt_regs *regs) { + if (is16mode(regs)) { + if (cpu_has_mips16) + return __MIPS16e_compute_return_epc(regs); + if (cpu_has_mmips) + return __microMIPS_compute_return_epc(regs); + return regs->cp0_epc; + } + if (!delay_slot(regs)) { regs->cp0_epc += 4; return 0; @@ -40,4 +56,19 @@ static inline int compute_return_epc(struct pt_regs *regs) return __compute_return_epc(regs); } +static inline int MIPS16e_compute_return_epc(struct pt_regs *regs, + union mips16e_instruction *inst) +{ + if (likely(!delay_slot(regs))) { + if (inst->ri.opcode == MIPS16e_extend_op) { + regs->cp0_epc += 4; + return 0; + } + regs->cp0_epc += 2; + return 0; + } + + return __MIPS16e_compute_return_epc(regs); +} + #endif /* _ASM_BRANCH_H */ diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index 4d735d0..01b4e91 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -14,10 +14,188 @@ #include #include #include +#include #include #include #include +/* + * Calculate and return exception epc in case of + * branch delay slot for microMIPS/MIPS16e + * It doesn't clear ISA mode bit. + */ +int __isa_exception_epc(struct pt_regs *regs) +{ + long epc; + union mips16e_instruction inst; + + /* calc exception pc in branch delay slot */ + epc = regs->cp0_epc; + if (__get_user(inst.full, (u16 __user *) (epc & ~MIPS_ISA_MODE))) { + /* it should never happens... because delay slot was checked */ + force_sig(SIGSEGV, current); + return epc; + } + if (cpu_has_mips16) { + if (inst.ri.opcode == MIPS16e_jal_op) + epc += 4; + else + epc += 2; + } else if (mm_is16bit(inst.full)) + epc += 2; + else + epc += 4; + + return epc; +} + +/* + * Compute the return address and do emulate branch simulation in MIPS16e mode, + * if required. + * After exception only - doesn't do 'compact' branch/jumps and can't be used + * during interrupt (compact B/J doesn't do exception) + */ +int __MIPS16e_compute_return_epc(struct pt_regs *regs) +{ + u16 __user *addr; + union mips16e_instruction inst; + u16 inst2; + u32 fullinst; + long epc; + + epc = regs->cp0_epc; + /* + * Read the instruction + */ + addr = (u16 __user *) (epc & ~MIPS_ISA_MODE); + if (__get_user(inst.full, addr)) { + force_sig(SIGSEGV, current); + return -EFAULT; + } + + switch (inst.ri.opcode) { + case MIPS16e_extend_op: + regs->cp0_epc += 4; + return 0; + + /* + * JAL and JALX in MIPS16e mode + */ + case MIPS16e_jal_op: + addr += 1; + if (__get_user(inst2, addr)) { + force_sig(SIGSEGV, current); + return -EFAULT; + } + fullinst = ((unsigned)inst.full << 16) | inst2; + regs->regs[31] = epc + 6; + epc += 4; + epc >>= 28; + epc <<= 28; + /* + * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16 + * + * ......TARGET[15:0].................TARGET[20:16]........... + * ......TARGET[25:21] + */ + epc |= + ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) | + ((fullinst & 0x1f0000) << 7); + if (!inst.jal.x) + epc |= MIPS_ISA_MODE; /* set ISA mode 1 */ + regs->cp0_epc = epc; + return 0; + + /* + * J(AL)R(C) + */ + case MIPS16e_rr_op: + if (inst.rr.func == MIPS16e_jr_func) { + + if (inst.rr.ra) + regs->cp0_epc = regs->regs[31]; + else + regs->cp0_epc = + regs->regs[mips16e_reg2gpr[inst.rr.rx]]; + + if (inst.rr.l) { + if (inst.rr.nd) + regs->regs[31] = epc + 2; + else + regs->regs[31] = epc + 4; + } + return 0; + } + break; + } + + /* all other cases have no branch delay slot and are 16bits, + and branches do not do exception */ + regs->cp0_epc += 2; + + return 0; +} + +/* + * Compute the return address and do emulate branch simulation in + * microMIPS mode, if required. + * After exception only - doesn't do 'compact' branch/jumps and can't be used + * during interrupt (compact B/J doesn't do exception) + */ +int __microMIPS_compute_return_epc(struct pt_regs *regs) +{ + u16 __user *pc16; + u16 halfword; + unsigned int word; + unsigned long contpc; + struct decoded_instn mminst = { 0 }; + + mminst.micro_mips_mode = 1; + + /* + * This load never faults. + */ + pc16 = (unsigned short __user *)(regs->cp0_epc & ~MIPS_ISA_MODE); + __get_user(halfword, pc16); + pc16++; + contpc = regs->cp0_epc + 2; + word = ((unsigned int)halfword << 16); + mminst.pc_inc = 2; + + if (!mm_is16bit(halfword)) { + __get_user(halfword, pc16); + pc16++; + contpc = regs->cp0_epc + 4; + mminst.pc_inc = 4; + word |= halfword; + } + mminst.insn = word; + + if (get_user(halfword, pc16)) + goto sigsegv; + mminst.next_pc_inc = 2; + word = ((unsigned int)halfword << 16); + + if (!mm_is16bit(halfword)) { + pc16++; + if (get_user(halfword, pc16)) + goto sigsegv; + mminst.next_pc_inc = 4; + word |= halfword; + } + mminst.next_insn = word; + + mm_isBranchInstr(regs, mminst, &contpc); + + regs->cp0_epc = contpc; + + return 0; + +sigsegv: + force_sig(SIGSEGV, current); + return -EFAULT; +} + /** * __compute_return_epc_for_insn - Computes the return address and do emulate * branch simulation, if required. @@ -57,7 +235,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, */ case bcond_op: switch (insn.i_format.rt) { - case bltz_op: + case bltz_op: case bltzl_op: if ((long)regs->regs[insn.i_format.rs] < 0) { epc = epc + 4 + (insn.i_format.simmediate << 2); @@ -129,6 +307,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, epc <<= 28; epc |= (insn.j_format.target << 2); regs->cp0_epc = epc; + if (insn.i_format.opcode == jalx_op) + regs->cp0_epc |= MIPS_ISA_MODE; break; /* @@ -289,5 +469,4 @@ unaligned: printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); force_sig(SIGBUS, current); return -EFAULT; - } -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:22:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:26:16 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39811 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903696Ab2DIPWa (ORCPT ); Mon, 9 Apr 2012 17:22:30 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQB-0005vf-G2; Mon, 09 Apr 2012 10:22:23 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Leonid Yegoshin Subject: [PATCH 8/9] MIPS: Support microMIPS/MIPS16e unaligned accesses. Date: Mon, 9 Apr 2012 10:22:02 -0500 Message-Id: <1333984923-445-9-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333984923-445-1-git-send-email-sjhill@mips.com> References: <1333984923-445-1-git-send-email-sjhill@mips.com> X-archive-position: 32900 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 47866 Lines: 1809 From: "Steven J. Hill" Add logic needed to properly handle unaligned accesses when in microMIPS or MIPS16e modes. Signed-off-by: Leonid Yegoshin Signed-off-by: Steven J. Hill --- arch/mips/kernel/process.c | 101 +++ arch/mips/kernel/unaligned.c | 1496 ++++++++++++++++++++++++++++++++++++------ 2 files changed, 1391 insertions(+), 206 deletions(-) diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index e9a5fd7..2f24d70 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -7,6 +7,7 @@ * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2004 Thiemo Seufer + * Copyright (C) 2011 MIPS Technologies, Inc. */ #include #include @@ -262,34 +263,115 @@ struct mips_frame_info { static inline int is_ra_save_ins(union mips_instruction *ip) { +#ifdef CONFIG_CPU_MICROMIPS + union mips_instruction mmi; + + /* + * swsp ra,offset + * swm16 reglist,offset(sp) + * swm32 reglist,offset(sp) + * sw32 ra,offset(sp) + * jradiussp - NOT SUPPORTED + * + * microMIPS is way more fun... + */ + if (mm_is16bit(ip->halfword[0])) { + mmi.word = (ip->halfword[0] << 16); + return ((mmi.mm16_r5_format.opcode == mm_swsp16_op && + mmi.mm16_r5_format.rt == 31) || + (mmi.mm16_m_format.opcode == mm_pool16c_op && + mmi.mm16_m_format.func == mm_swm16_op)); + } + else { + mmi.halfword[0] = ip->halfword[1]; + mmi.halfword[1] = ip->halfword[0]; + return ((mmi.mm_m_format.opcode == mm_pool32b_op && + mmi.mm_m_format.rd > 9 && + mmi.mm_m_format.base == 29 && + mmi.mm_m_format.func == mm_swm32_func) || + (mmi.i_format.opcode == mm_sw32_op && + mmi.i_format.rs == 29 && + mmi.i_format.rt == 31)); + } +#else /* sw / sd $ra, offset($sp) */ return (ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && ip->i_format.rs == 29 && ip->i_format.rt == 31; +#endif } static inline int is_jal_jalr_jr_ins(union mips_instruction *ip) { +#ifdef CONFIG_CPU_MICROMIPS + /* + * jr16,jrc,jalr16,jalr16 + * jal + * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb + * jraddiusp - NOT SUPPORTED + * + * microMIPS is kind of more fun... + */ + union mips_instruction mmi; + + mmi.word = (ip->halfword[0] << 16); + + if ((mmi.mm16_r5_format.opcode == mm_pool16c_op && + (mmi.mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op) || + ip->j_format.opcode == mm_jal32_op) + return 1; + if (ip->r_format.opcode != mm_pool32a_op || + ip->r_format.func != mm_pool32axf_op) + return 0; + return (((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op); +#else if (ip->j_format.opcode == jal_op) return 1; if (ip->r_format.opcode != spec_op) return 0; return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; +#endif } static inline int is_sp_move_ins(union mips_instruction *ip) { +#ifdef CONFIG_CPU_MICROMIPS + /* + * addiusp -imm + * addius5 sp,-imm + * addiu32 sp,sp,-imm + * jradiussp - NOT SUPPORTED + * + * microMIPS is not more fun... + */ + if (mm_is16bit(ip->halfword[0])) { + union mips_instruction mmi; + + mmi.word = (ip->halfword[0] << 16); + return ((mmi.mm16_r3_format.opcode == mm_pool16d_op && + mmi.mm16_r3_format.simmediate && mm_addiusp_func) || + (mmi.mm16_r5_format.opcode == mm_pool16d_op && + mmi.mm16_r5_format.rt == 29)); + } + return (ip->mm_i_format.opcode == mm_addiu32_op && + ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29); +#else /* addiu/daddiu sp,sp,-imm */ if (ip->i_format.rs != 29 || ip->i_format.rt != 29) return 0; if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) return 1; +#endif return 0; } static int get_frame_info(struct mips_frame_info *info) { +#ifdef CONFIG_CPU_MICROMIPS + union mips_instruction *ip = (void *) (((char *) info->func) - 1); +#else union mips_instruction *ip = info->func; +#endif unsigned max_insns = info->func_size / sizeof(union mips_instruction); unsigned i; @@ -309,7 +391,26 @@ static int get_frame_info(struct mips_frame_info *info) break; if (!info->frame_size) { if (is_sp_move_ins(ip)) + { +#ifdef CONFIG_CPU_MICROMIPS + if (mm_is16bit(ip->halfword[0])) + { + unsigned short tmp; + + if (ip->halfword[0] & mm_addiusp_func) + { + tmp = (((ip->halfword[0] >> 1) & 0x1ff) << 2); + info->frame_size = -(signed short)(tmp | ((tmp & 0x100) ? 0xfe00 : 0)); + } else { + tmp = (ip->halfword[0] >> 1); + info->frame_size = -(signed short)(tmp & 0xf); + } + ip = (void *) &ip->halfword[1]; + ip--; + } else +#endif info->frame_size = - ip->i_format.simmediate; + } continue; } if (info->pc_offset == -1 && is_ra_save_ins(ip)) { diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 9c58bdf..6a9927a 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -85,6 +85,8 @@ #include #include #include +#include +#include #define STR(x) __STR(x) #define __STR(x) #x @@ -102,12 +104,333 @@ static u32 unaligned_action; #endif extern void show_registers(struct pt_regs *regs); +#ifdef __BIG_ENDIAN +#define LoadHW(addr, value, res) \ + __asm__ __volatile__ (".set\tnoat\n" \ + "1:\tlb\t%0, 0(%2)\n" \ + "2:\tlbu\t$1, 1(%2)\n\t" \ + "sll\t%0, 0x8\n\t" \ + "or\t%0, $1\n\t" \ + "li\t%1, 0\n" \ + "3:\t.set\tat\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tlwl\t%0, (%2)\n" \ + "2:\tlwr\t%0, 3(%2)\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadHWU(addr, value, res) \ + __asm__ __volatile__ ( \ + ".set\tnoat\n" \ + "1:\tlbu\t%0, 0(%2)\n" \ + "2:\tlbu\t$1, 1(%2)\n\t" \ + "sll\t%0, 0x8\n\t" \ + "or\t%0, $1\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".set\tat\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadWU(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tlwl\t%0, (%2)\n" \ + "2:\tlwr\t%0, 3(%2)\n\t" \ + "dsll\t%0, %0, 32\n\t" \ + "dsrl\t%0, %0, 32\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + "\t.section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadDW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tldl\t%0, (%2)\n" \ + "2:\tldr\t%0, 7(%2)\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + "\t.section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define StoreHW(addr, value, res) \ + __asm__ __volatile__ ( \ + ".set\tnoat\n" \ + "1:\tsb\t%1, 1(%2)\n\t" \ + "srl\t$1, %1, 0x8\n" \ + "2:\tsb\t$1, 0(%2)\n\t" \ + ".set\tat\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); + +#define StoreW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tswl\t%1,(%2)\n" \ + "2:\tswr\t%1, 3(%2)\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); + +#define StoreDW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tsdl\t%1,(%2)\n" \ + "2:\tsdr\t%1, 7(%2)\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); +#endif + +#ifdef __LITTLE_ENDIAN +#define LoadHW(addr, value, res) \ + __asm__ __volatile__ (".set\tnoat\n" \ + "1:\tlb\t%0, 1(%2)\n" \ + "2:\tlbu\t$1, 0(%2)\n\t" \ + "sll\t%0, 0x8\n\t" \ + "or\t%0, $1\n\t" \ + "li\t%1, 0\n" \ + "3:\t.set\tat\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tlwl\t%0, 3(%2)\n" \ + "2:\tlwr\t%0, (%2)\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadHWU(addr, value, res) \ + __asm__ __volatile__ ( \ + ".set\tnoat\n" \ + "1:\tlbu\t%0, 1(%2)\n" \ + "2:\tlbu\t$1, 0(%2)\n\t" \ + "sll\t%0, 0x8\n\t" \ + "or\t%0, $1\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".set\tat\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadWU(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tlwl\t%0, 3(%2)\n" \ + "2:\tlwr\t%0, (%2)\n\t" \ + "dsll\t%0, %0, 32\n\t" \ + "dsrl\t%0, %0, 32\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + "\t.section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define LoadDW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tldl\t%0, 7(%2)\n" \ + "2:\tldr\t%0, (%2)\n\t" \ + "li\t%1, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + "\t.section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%1, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=&r" (value), "=r" (res) \ + : "r" (addr), "i" (-EFAULT)); + +#define StoreHW(addr, value, res) \ + __asm__ __volatile__ ( \ + ".set\tnoat\n" \ + "1:\tsb\t%1, 0(%2)\n\t" \ + "srl\t$1,%1, 0x8\n" \ + "2:\tsb\t$1, 1(%2)\n\t" \ + ".set\tat\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); + +#define StoreW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tswl\t%1, 3(%2)\n" \ + "2:\tswr\t%1, (%2)\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); + +#define StoreDW(addr, value, res) \ + __asm__ __volatile__ ( \ + "1:\tsdl\t%1, 7(%2)\n" \ + "2:\tsdr\t%1, (%2)\n\t" \ + "li\t%0, 0\n" \ + "3:\n\t" \ + ".insn\n\t" \ + ".section\t.fixup,\"ax\"\n\t" \ + "4:\tli\t%0, %3\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR)"\t1b, 4b\n\t" \ + STR(PTR)"\t2b, 4b\n\t" \ + ".previous" \ + : "=r" (res) \ + : "r" (value), "r" (addr), "i" (-EFAULT)); +#endif + static void emulate_load_store_insn(struct pt_regs *regs, - void __user *addr, unsigned int __user *pc) + void __user *addr, + unsigned int __user *pc) { union mips_instruction insn; unsigned long value; unsigned int res; + unsigned long origpc; + unsigned long orig31; + void __user *fault_addr = NULL; + + origpc = (unsigned long)pc; + orig31 = regs->regs[31]; perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); @@ -117,22 +440,22 @@ static void emulate_load_store_insn(struct pt_regs *regs, __get_user(insn.word, pc); switch (insn.i_format.opcode) { - /* - * These are instructions that a compiler doesn't generate. We - * can assume therefore that the code is MIPS-aware and - * really buggy. Emulating these instructions would break the - * semantics anyway. - */ + /* + * These are instructions that a compiler doesn't generate. We + * can assume therefore that the code is MIPS-aware and + * really buggy. Emulating these instructions would break the + * semantics anyway. + */ case ll_op: case lld_op: case sc_op: case scd_op: - /* - * For these instructions the only way to create an address - * error is an attempted access to kernel/supervisor address - * space. - */ + /* + * For these instructions the only way to create an address + * error is an attempted access to kernel/supervisor address + * space. + */ case ldl_op: case ldr_op: case lwl_op: @@ -146,36 +469,15 @@ static void emulate_load_store_insn(struct pt_regs *regs, case sb_op: goto sigbus; - /* - * The remaining opcodes are the ones that are really of interest. - */ + /* + * The remaining opcodes are the ones that are really of + * interest. + */ case lh_op: if (!access_ok(VERIFY_READ, addr, 2)) goto sigbus; - __asm__ __volatile__ (".set\tnoat\n" -#ifdef __BIG_ENDIAN - "1:\tlb\t%0, 0(%2)\n" - "2:\tlbu\t$1, 1(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tlb\t%0, 1(%2)\n" - "2:\tlbu\t$1, 0(%2)\n\t" -#endif - "sll\t%0, 0x8\n\t" - "or\t%0, $1\n\t" - "li\t%1, 0\n" - "3:\t.set\tat\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadHW(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -186,26 +488,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_READ, addr, 4)) goto sigbus; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tlwl\t%0, (%2)\n" - "2:\tlwr\t%0, 3(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tlwl\t%0, 3(%2)\n" - "2:\tlwr\t%0, (%2)\n\t" -#endif - "li\t%1, 0\n" - "3:\t.section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadW(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -216,30 +499,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_READ, addr, 2)) goto sigbus; - __asm__ __volatile__ ( - ".set\tnoat\n" -#ifdef __BIG_ENDIAN - "1:\tlbu\t%0, 0(%2)\n" - "2:\tlbu\t$1, 1(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tlbu\t%0, 1(%2)\n" - "2:\tlbu\t$1, 0(%2)\n\t" -#endif - "sll\t%0, 0x8\n\t" - "or\t%0, $1\n\t" - "li\t%1, 0\n" - "3:\t.set\tat\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadHWU(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -258,28 +518,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_READ, addr, 4)) goto sigbus; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tlwl\t%0, (%2)\n" - "2:\tlwr\t%0, 3(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tlwl\t%0, 3(%2)\n" - "2:\tlwr\t%0, (%2)\n\t" -#endif - "dsll\t%0, %0, 32\n\t" - "dsrl\t%0, %0, 32\n\t" - "li\t%1, 0\n" - "3:\t.section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadWU(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -302,26 +541,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_READ, addr, 8)) goto sigbus; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tldl\t%0, (%2)\n" - "2:\tldr\t%0, 7(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tldl\t%0, 7(%2)\n" - "2:\tldr\t%0, (%2)\n\t" -#endif - "li\t%1, 0\n" - "3:\t.section\t.fixup,\"ax\"\n\t" - "4:\tli\t%1, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=&r" (value), "=r" (res) - : "r" (addr), "i" (-EFAULT)); + LoadDW(addr, value, res); if (res) goto fault; compute_return_epc(regs); @@ -336,68 +556,22 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, addr, 2)) goto sigbus; + compute_return_epc(regs); value = regs->regs[insn.i_format.rt]; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - ".set\tnoat\n" - "1:\tsb\t%1, 1(%2)\n\t" - "srl\t$1, %1, 0x8\n" - "2:\tsb\t$1, 0(%2)\n\t" - ".set\tat\n\t" -#endif -#ifdef __LITTLE_ENDIAN - ".set\tnoat\n" - "1:\tsb\t%1, 0(%2)\n\t" - "srl\t$1,%1, 0x8\n" - "2:\tsb\t$1, 1(%2)\n\t" - ".set\tat\n\t" -#endif - "li\t%0, 0\n" - "3:\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%0, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=r" (res) - : "r" (value), "r" (addr), "i" (-EFAULT)); + StoreHW(addr, value, res); if (res) goto fault; - compute_return_epc(regs); break; case sw_op: if (!access_ok(VERIFY_WRITE, addr, 4)) goto sigbus; + compute_return_epc(regs); value = regs->regs[insn.i_format.rt]; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tswl\t%1,(%2)\n" - "2:\tswr\t%1, 3(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tswl\t%1, 3(%2)\n" - "2:\tswr\t%1, (%2)\n\t" -#endif - "li\t%0, 0\n" - "3:\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%0, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=r" (res) - : "r" (value), "r" (addr), "i" (-EFAULT)); + StoreW(addr, value, res); if (res) goto fault; - compute_return_epc(regs); break; case sd_op: @@ -412,31 +586,11 @@ static void emulate_load_store_insn(struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, addr, 8)) goto sigbus; + compute_return_epc(regs); value = regs->regs[insn.i_format.rt]; - __asm__ __volatile__ ( -#ifdef __BIG_ENDIAN - "1:\tsdl\t%1,(%2)\n" - "2:\tsdr\t%1, 7(%2)\n\t" -#endif -#ifdef __LITTLE_ENDIAN - "1:\tsdl\t%1, 7(%2)\n" - "2:\tsdr\t%1, (%2)\n\t" -#endif - "li\t%0, 0\n" - "3:\n\t" - ".section\t.fixup,\"ax\"\n\t" - "4:\tli\t%0, %3\n\t" - "j\t3b\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b, 4b\n\t" - STR(PTR)"\t2b, 4b\n\t" - ".previous" - : "=r" (res) - : "r" (value), "r" (addr), "i" (-EFAULT)); + StoreDW(addr, value, res); if (res) goto fault; - compute_return_epc(regs); break; #endif /* CONFIG_64BIT */ @@ -447,10 +601,21 @@ static void emulate_load_store_insn(struct pt_regs *regs, case ldc1_op: case swc1_op: case sdc1_op: - /* - * I herewith declare: this does not happen. So send SIGBUS. - */ - goto sigbus; + die_if_kernel("Unaligned FP access in kernel code", regs); + BUG_ON(!used_math()); + BUG_ON(!is_fpu_owner()); + + lose_fpu(1); /* save the FPU state for the emulator */ + res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, + &fault_addr); + own_fpu(1); /* restore FPU state */ + + /* If something went wrong, signal */ + process_fpemu_return(res, fault_addr); + + if (res == 0) + break; + return; /* * COP2 is available to implementor for application specific use. @@ -488,6 +653,883 @@ static void emulate_load_store_insn(struct pt_regs *regs, return; fault: + /* roll back jump/branch */ + regs->cp0_epc = origpc; + regs->regs[31] = orig31; + /* Did we have an exception handler installed? */ + if (fixup_exception(regs)) + return; + + die_if_kernel("Unhandled kernel unaligned access", regs); + force_sig(SIGSEGV, current); + + return; + +sigbus: + die_if_kernel("Unhandled kernel unaligned access", regs); + force_sig(SIGBUS, current); + + return; + +sigill: + die_if_kernel + ("Unhandled kernel unaligned access or invalid instruction", regs); + force_sig(SIGILL, current); +} + +/* recode table from micromips register notation to GPR */ +static int mmreg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + +/* recode table from micromips STORE register notation to GPR */ +static int mmreg16to32_st[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; + +void emulate_load_store_microMIPS(struct pt_regs *regs, void __user * addr) +{ + unsigned long value; + unsigned int res; + int i; + unsigned int reg = 0, rvar; + unsigned long orig31; + u16 __user *pc16; + u16 halfword; + unsigned int word; + unsigned long origpc, contpc; + union mips_instruction insn; + struct decoded_instn mminst; + void __user *fault_addr = NULL; + + origpc = regs->cp0_epc; + orig31 = regs->regs[31]; + + mminst.micro_mips_mode = 1; + + /* + * This load never faults. + */ + pc16 = (unsigned short __user *)(regs->cp0_epc & ~MIPS_ISA_MODE); + __get_user(halfword, pc16); + pc16++; + contpc = regs->cp0_epc + 2; + word = ((unsigned int)halfword << 16); + mminst.pc_inc = 2; + + if (!mm_is16bit(halfword)) { + __get_user(halfword, pc16); + pc16++; + contpc = regs->cp0_epc + 4; + mminst.pc_inc = 4; + word |= halfword; + } + mminst.insn = word; + + if (get_user(halfword, pc16)) + goto fault; + mminst.next_pc_inc = 2; + word = ((unsigned int)halfword << 16); + + if (!mm_is16bit(halfword)) { + pc16++; + if (get_user(halfword, pc16)) + goto fault; + mminst.next_pc_inc = 4; + word |= halfword; + } + mminst.next_insn = word; + + insn = (union mips_instruction)(mminst.insn); + if (mm_isBranchInstr(regs, mminst, &contpc)) + insn = (union mips_instruction)(mminst.next_insn); + + /* Parse instruction to find what to do */ + + switch (insn.mm_i_format.opcode) { + + case mm_pool32a_op: + switch (insn.mm_x_format.func) { + case mm_lwxs_op: + reg = insn.mm_x_format.rd; + goto loadW; + } + + goto sigbus; + + case mm_pool32b_op: + switch (insn.mm_m_format.func) { + case mm_lwp_func: + reg = insn.mm_m_format.rd; + if (reg == 31) + goto sigbus; + + if (!access_ok(VERIFY_READ, addr, 8)) + goto sigbus; + + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + addr += 4; + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[reg + 1] = value; + goto success; + + case mm_swp_func: + reg = insn.mm_m_format.rd; + if (reg == 31) + goto sigbus; + + if (!access_ok(VERIFY_WRITE, addr, 8)) + goto sigbus; + + value = regs->regs[reg]; + StoreW(addr, value, res); + if (res) + goto fault; + addr += 4; + value = regs->regs[reg + 1]; + StoreW(addr, value, res); + if (res) + goto fault; + goto success; + + case mm_ldp_func: +#ifdef CONFIG_64BIT + reg = insn.mm_m_format.rd; + if (reg == 31) + goto sigbus; + + if (!access_ok(VERIFY_READ, addr, 16)) + goto sigbus; + + LoadDW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + addr += 8; + LoadDW(addr, value, res); + if (res) + goto fault; + regs->regs[reg + 1] = value; + goto success; +#endif /* CONFIG_64BIT */ + + goto sigill; + + case mm_sdp_func: +#ifdef CONFIG_64BIT + reg = insn.mm_m_format.rd; + if (reg == 31) + goto sigbus; + + if (!access_ok(VERIFY_WRITE, addr, 16)) + goto sigbus; + + value = regs->regs[reg]; + StoreDW(addr, value, res); + if (res) + goto fault; + addr += 8; + value = regs->regs[reg + 1]; + StoreDW(addr, value, res); + if (res) + goto fault; + goto success; +#endif /* CONFIG_64BIT */ + + goto sigill; + + case mm_lwm32_func: + reg = insn.mm_m_format.rd; + rvar = reg & 0xf; + if ((rvar > 9) || !reg) + goto sigill; + if (reg & 0x10) { + if (!access_ok + (VERIFY_READ, addr, 4 * (rvar + 1))) + goto sigbus; + } else { + if (!access_ok(VERIFY_READ, addr, 4 * rvar)) + goto sigbus; + } + if (rvar == 9) + rvar = 8; + for (i = 16; rvar; rvar--, i++) { + LoadW(addr, value, res); + if (res) + goto fault; + addr += 4; + regs->regs[i] = value; + } + if ((reg & 0xf) == 9) { + LoadW(addr, value, res); + if (res) + goto fault; + addr += 4; + regs->regs[30] = value; + } + if (reg & 0x10) { + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[31] = value; + } + goto success; + + case mm_swm32_func: + reg = insn.mm_m_format.rd; + rvar = reg & 0xf; + if ((rvar > 9) || !reg) + goto sigill; + if (reg & 0x10) { + if (!access_ok + (VERIFY_WRITE, addr, 4 * (rvar + 1))) + goto sigbus; + } else { + if (!access_ok(VERIFY_WRITE, addr, 4 * rvar)) + goto sigbus; + } + if (rvar == 9) + rvar = 8; + for (i = 16; rvar; rvar--, i++) { + value = regs->regs[i]; + StoreW(addr, value, res); + if (res) + goto fault; + addr += 4; + } + if ((reg & 0xf) == 9) { + value = regs->regs[30]; + StoreW(addr, value, res); + if (res) + goto fault; + addr += 4; + } + if (reg & 0x10) { + value = regs->regs[31]; + StoreW(addr, value, res); + if (res) + goto fault; + } + goto success; + + case mm_ldm_func: +#ifdef CONFIG_64BIT + reg = insn.mm_m_format.rd; + rvar = reg & 0xf; + if ((rvar > 9) || !reg) + goto sigill; + if (reg & 0x10) { + if (!access_ok + (VERIFY_READ, addr, 8 * (rvar + 1))) + goto sigbus; + } else { + if (!access_ok(VERIFY_READ, addr, 8 * rvar)) + goto sigbus; + } + if (rvar == 9) + rvar = 8; + + for (i = 16; rvar; rvar--, i++) { + LoadDW(addr, value, res); + if (res) + goto fault; + addr += 4; + regs->regs[i] = value; + } + if ((reg & 0xf) == 9) { + LoadDW(addr, value, res); + if (res) + goto fault; + addr += 8; + regs->regs[30] = value; + } + if (reg & 0x10) { + LoadDW(addr, value, res); + if (res) + goto fault; + regs->regs[31] = value; + } + goto success; +#endif /* CONFIG_64BIT */ + + goto sigill; + + case mm_sdm_func: +#ifdef CONFIG_64BIT + reg = insn.mm_m_format.rd; + rvar = reg & 0xf; + if ((rvar > 9) || !reg) + goto sigill; + if (reg & 0x10) { + if (!access_ok + (VERIFY_WRITE, addr, 8 * (rvar + 1))) + goto sigbus; + } else { + if (!access_ok(VERIFY_WRITE, addr, 8 * rvar)) + goto sigbus; + } + if (rvar == 9) + rvar = 8; + + for (i = 16; rvar; rvar--, i++) { + value = regs->regs[i]; + StoreDW(addr, value, res); + if (res) + goto fault; + addr += 8; + } + if ((reg & 0xf) == 9) { + value = regs->regs[30]; + StoreDW(addr, value, res); + if (res) + goto fault; + addr += 8; + } + if (reg & 0x10) { + value = regs->regs[31]; + StoreDW(addr, value, res); + if (res) + goto fault; + } + goto success; +#endif /* CONFIG_64BIT */ + + goto sigill; + + /* LWC2, SWC2, LDC2, SDC2 are not serviced */ + } + + goto sigbus; + + case mm_pool32c_op: + switch (insn.mm_m_format.func) { + case mm_lwu_func: + reg = insn.mm_m_format.rd; + goto loadWU; + } + + /* LL,SC,LLD,SCD are not serviced */ + goto sigbus; + + case mm_pool32f_op: + switch (insn.mm_x_format.func) { + case mm_lwxc1_func: + case mm_swxc1_func: + case mm_ldxc1_func: + case mm_sdxc1_func: + goto fpu_emul; + } + + goto sigbus; + + case mm_ldc132_op: + case mm_sdc132_op: + case mm_lwc132_op: + case mm_swc132_op: +fpu_emul: + /* roll back jump/branch */ + regs->cp0_epc = origpc; + regs->regs[31] = orig31; + + die_if_kernel("Unaligned FP access in kernel code", regs); + BUG_ON(!used_math()); + BUG_ON(!is_fpu_owner()); + + lose_fpu(1); /* save the FPU state for the emulator */ + res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, + &fault_addr); + own_fpu(1); /* restore FPU state */ + + /* If something went wrong, signal */ + process_fpemu_return(res, fault_addr); + + if (res == 0) + goto success; + return; + + case mm_lh32_op: + reg = insn.mm_i_format.rt; + goto loadHW; + + case mm_lhu32_op: + reg = insn.mm_i_format.rt; + goto loadHWU; + + case mm_lw32_op: + reg = insn.mm_i_format.rt; + goto loadW; + + case mm_sh32_op: + reg = insn.mm_i_format.rt; + goto storeHW; + + case mm_sw32_op: + reg = insn.mm_i_format.rt; + goto storeW; + + case mm_ld32_op: + reg = insn.mm_i_format.rt; + goto loadDW; + + case mm_sd32_op: + reg = insn.mm_i_format.rt; + goto storeDW; + + case mm_pool16c_op: + switch (insn.mm16_m_format.func) { + case mm_lwm16_op: + reg = insn.mm16_m_format.rlist; + rvar = reg + 1; + if (!access_ok(VERIFY_READ, addr, 4 * rvar)) + goto sigbus; + + for (i = 16; rvar; rvar--, i++) { + LoadW(addr, value, res); + if (res) + goto fault; + addr += 4; + regs->regs[i] = value; + } + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[31] = value; + + goto success; + + case mm_swm16_op: + reg = insn.mm16_m_format.rlist; + rvar = reg + 1; + if (!access_ok(VERIFY_WRITE, addr, 4 * rvar)) + goto sigbus; + + for (i = 16; rvar; rvar--, i++) { + value = regs->regs[i]; + StoreW(addr, value, res); + if (res) + goto fault; + addr += 4; + } + value = regs->regs[31]; + StoreW(addr, value, res); + if (res) + goto fault; + + goto success; + + } + + goto sigbus; + + case mm_lhu16_op: + reg = mmreg16to32[insn.mm16_rb_format.rt]; + goto loadHWU; + + case mm_lw16_op: + reg = mmreg16to32[insn.mm16_rb_format.rt]; + goto loadW; + + case mm_sh16_op: + reg = mmreg16to32_st[insn.mm16_rb_format.rt]; + goto storeHW; + + case mm_sw16_op: + reg = mmreg16to32_st[insn.mm16_rb_format.rt]; + goto storeW; + + case mm_lwsp16_op: + reg = insn.mm16_r5_format.rt; + goto loadW; + + case mm_swsp16_op: + reg = insn.mm16_r5_format.rt; + goto storeW; + + case mm_lwgp16_op: + reg = mmreg16to32[insn.mm16_r3_format.rt]; + goto loadW; + + default: + goto sigill; + } + +loadHW: + if (!access_ok(VERIFY_READ, addr, 2)) + goto sigbus; + + LoadHW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; + +loadHWU: + if (!access_ok(VERIFY_READ, addr, 2)) + goto sigbus; + + LoadHWU(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; + +loadW: + if (!access_ok(VERIFY_READ, addr, 4)) + goto sigbus; + + LoadW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; + +loadWU: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_READ, addr, 4)) + goto sigbus; + + LoadWU(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + +loadDW: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_READ, addr, 8)) + goto sigbus; + + LoadDW(addr, value, res); + if (res) + goto fault; + regs->regs[reg] = value; + goto success; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + +storeHW: + if (!access_ok(VERIFY_WRITE, addr, 2)) + goto sigbus; + + value = regs->regs[reg]; + StoreHW(addr, value, res); + if (res) + goto fault; + goto success; + +storeW: + if (!access_ok(VERIFY_WRITE, addr, 4)) + goto sigbus; + + value = regs->regs[reg]; + StoreW(addr, value, res); + if (res) + goto fault; + goto success; + +storeDW: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_WRITE, addr, 8)) + goto sigbus; + + value = regs->regs[reg]; + StoreDW(addr, value, res); + if (res) + goto fault; + goto success; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + +success: + regs->cp0_epc = contpc; /* advance or branch */ + +#ifdef CONFIG_DEBUG_FS + unaligned_instructions++; +#endif + return; + +fault: + /* roll back jump/branch */ + regs->cp0_epc = origpc; + regs->regs[31] = orig31; + /* Did we have an exception handler installed? */ + if (fixup_exception(regs)) + return; + + die_if_kernel("Unhandled kernel unaligned access", regs); + force_sig(SIGSEGV, current); + + return; + +sigbus: + die_if_kernel("Unhandled kernel unaligned access", regs); + force_sig(SIGBUS, current); + + return; + +sigill: + die_if_kernel + ("Unhandled kernel unaligned access or invalid instruction", regs); + force_sig(SIGILL, current); +} + +/* recode table from MIPS16e register notation to GPR */ +int mips16e_reg2gpr[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + +static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr) +{ + unsigned long value; + unsigned int res; + int reg; + unsigned long orig31; + u16 __user *pc16; + unsigned long origpc; + union mips16e_instruction mips16inst, oldinst; + + origpc = regs->cp0_epc; + orig31 = regs->regs[31]; + pc16 = (unsigned short __user *)(origpc & ~MIPS_ISA_MODE); + /* + * This load never faults. + */ + __get_user(mips16inst.full, pc16); + oldinst = mips16inst; + + /* skip EXTEND instruction */ + if (mips16inst.ri.opcode == MIPS16e_extend_op) { + pc16++; + __get_user(mips16inst.full, pc16); + } else if (delay_slot(regs)) { + /* skip jump instructions */ + /* JAL/JALX are 32 bits but have OPCODE in first short int */ + if (mips16inst.ri.opcode == MIPS16e_jal_op) + pc16++; + pc16++; + if (get_user(mips16inst.full, pc16)) + goto sigbus; + } + + switch (mips16inst.ri.opcode) { + case MIPS16e_i64_op: /* I64 or RI64 instruction */ + switch (mips16inst.i64.func) { /* I64/RI64 func field check */ + case MIPS16e_ldpc_func: + case MIPS16e_ldsp_func: + reg = mips16e_reg2gpr[mips16inst.ri64.ry]; + goto loadDW; + + case MIPS16e_sdsp_func: + reg = mips16e_reg2gpr[mips16inst.ri64.ry]; + goto writeDW; + + case MIPS16e_sdrasp_func: + reg = 29; /* GPRSP */ + goto writeDW; + } + + goto sigbus; + + case MIPS16e_swsp_op: + case MIPS16e_lwpc_op: + case MIPS16e_lwsp_op: + reg = mips16e_reg2gpr[mips16inst.ri.rx]; + break; + + case MIPS16e_i8_op: + if (mips16inst.i8.func != MIPS16e_swrasp_func) + goto sigbus; + reg = 29; /* GPRSP */ + break; + + default: + reg = mips16e_reg2gpr[mips16inst.rri.ry]; + break; + } + + switch (mips16inst.ri.opcode) { + + case MIPS16e_lb_op: + case MIPS16e_lbu_op: + case MIPS16e_sb_op: + goto sigbus; + + case MIPS16e_lh_op: + if (!access_ok(VERIFY_READ, addr, 2)) + goto sigbus; + + LoadHW(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; + + case MIPS16e_lhu_op: + if (!access_ok(VERIFY_READ, addr, 2)) + goto sigbus; + + LoadHWU(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; + + case MIPS16e_lw_op: + case MIPS16e_lwpc_op: + case MIPS16e_lwsp_op: + if (!access_ok(VERIFY_READ, addr, 4)) + goto sigbus; + + LoadW(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; + + case MIPS16e_lwu_op: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_READ, addr, 4)) + goto sigbus; + + LoadWU(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + + case MIPS16e_ld_op: +loadDW: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_READ, addr, 8)) + goto sigbus; + + LoadDW(addr, value, res); + if (res) + goto fault; + MIPS16e_compute_return_epc(regs, &oldinst); + regs->regs[reg] = value; + break; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + + case MIPS16e_sh_op: + if (!access_ok(VERIFY_WRITE, addr, 2)) + goto sigbus; + + MIPS16e_compute_return_epc(regs, &oldinst); + value = regs->regs[reg]; + StoreHW(addr, value, res); + if (res) + goto fault; + break; + + case MIPS16e_sw_op: + case MIPS16e_swsp_op: + case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */ + if (!access_ok(VERIFY_WRITE, addr, 4)) + goto sigbus; + + MIPS16e_compute_return_epc(regs, &oldinst); + value = regs->regs[reg]; + StoreW(addr, value, res); + if (res) + goto fault; + break; + + case MIPS16e_sd_op: +writeDW: +#ifdef CONFIG_64BIT + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (!access_ok(VERIFY_WRITE, addr, 8)) + goto sigbus; + + MIPS16e_compute_return_epc(regs, &oldinst); + value = regs->regs[reg]; + StoreDW(addr, value, res); + if (res) + goto fault; + break; +#endif /* CONFIG_64BIT */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; + + default: + /* + * Pheeee... We encountered an yet unknown instruction or + * cache coherence problem. Die sucker, die ... + */ + goto sigill; + } + +#ifdef CONFIG_DEBUG_FS + unaligned_instructions++; +#endif + + return; + +fault: + /* roll back jump/branch */ + regs->cp0_epc = origpc; + regs->regs[31] = orig31; /* Did we have an exception handler installed? */ if (fixup_exception(regs)) return; @@ -504,7 +1546,8 @@ sigbus: return; sigill: - die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); + die_if_kernel + ("Unhandled kernel unaligned access or invalid instruction", regs); force_sig(SIGILL, current); } @@ -517,23 +1560,64 @@ asmlinkage void do_ade(struct pt_regs *regs) 1, regs, regs->cp0_badvaddr); /* * Did we catch a fault trying to load an instruction? - * Or are we running in MIPS16 mode? */ - if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1)) + if (regs->cp0_badvaddr == regs->cp0_epc) goto sigbus; - pc = (unsigned int __user *) exception_epc(regs); if (user_mode(regs) && !test_thread_flag(TIF_FIXADE)) goto sigbus; if (unaligned_action == UNALIGNED_ACTION_SIGNAL) goto sigbus; - else if (unaligned_action == UNALIGNED_ACTION_SHOW) - show_registers(regs); /* * Do branch emulation only if we didn't forward the exception. * This is all so but ugly ... */ + + /* + * Are we running in MIPS16e/microMIPS mode? + */ + if (is16mode(regs)) { + /* + * Did we catch a fault trying to load an instruction in + * 16bit mode? + */ + if (regs->cp0_badvaddr == (regs->cp0_epc & ~MIPS_ISA_MODE)) + goto sigbus; + if (unaligned_action == UNALIGNED_ACTION_SHOW) + show_registers(regs); + + if (cpu_has_mips16) { + seg = get_fs(); + if (!user_mode(regs)) + set_fs(KERNEL_DS); + emulate_load_store_MIPS16e(regs, + (void __user *)regs-> + cp0_badvaddr); + set_fs(seg); + + return; + } + + if (cpu_has_mmips) { /* micromips unaligned access */ + seg = get_fs(); + if (!user_mode(regs)) + set_fs(KERNEL_DS); + emulate_load_store_microMIPS(regs, + (void __user *)regs-> + cp0_badvaddr); + set_fs(seg); + + return; + } + + goto sigbus; + } + + if (unaligned_action == UNALIGNED_ACTION_SHOW) + show_registers(regs); + pc = (unsigned int __user *)exception_epc(regs); + seg = get_fs(); if (!user_mode(regs)) set_fs(KERNEL_DS); -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:22:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:26:42 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39812 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903697Ab2DIPWb (ORCPT ); Mon, 9 Apr 2012 17:22:31 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGQC-0005vf-Ej; Mon, 09 Apr 2012 10:22:24 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Leonid Yegoshin Subject: [PATCH 9/9] MIPS: Support microMIPS/MIPS16e floating point. Date: Mon, 9 Apr 2012 10:22:03 -0500 Message-Id: <1333984923-445-10-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 In-Reply-To: <1333984923-445-1-git-send-email-sjhill@mips.com> References: <1333984923-445-1-git-send-email-sjhill@mips.com> X-archive-position: 32901 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 33260 Lines: 1006 From: "Steven J. Hill" Add logic needed to do floating point emulation when in microMIPS or MIPS16e mode. Signed-off-by: Leonid Yegoshin Signed-off-by: Steven J. Hill --- arch/mips/include/asm/fpu_emulator.h | 7 + arch/mips/math-emu/cp1emu.c | 766 ++++++++++++++++++++++++++++++---- arch/mips/math-emu/dsemul.c | 40 +- 3 files changed, 717 insertions(+), 96 deletions(-) diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 3b40927..67d5028 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -54,6 +54,12 @@ do { \ extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); extern int do_dsemulret(struct pt_regs *xcp); +extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, + struct mips_fpu_struct *ctx, int has_fpu, + void *__user *fault_addr); +int process_fpemu_return(int sig, void __user *fault_addr); +int mm_isBranchInstr(struct pt_regs *regs, struct decoded_instn dec_insn, + unsigned long *contpc); /* * Instruction inserted following the badinst to further tag the sequence @@ -64,5 +70,6 @@ extern int do_dsemulret(struct pt_regs *xcp); * Break instruction with special math emu break code set */ #define BREAK_MATH (0x0000000d | (BRK_MEMU << 16)) +#define MM_BREAK_MATH (0x00000007 | (MM_BRK_MEMU << 16)) #endif /* _ASM_FPU_EMULATOR_H */ diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index a03bf00..366c0c5 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -110,6 +111,477 @@ static const unsigned int fpucondbit[8] = { }; #endif +/* convert 16-bit register encoding to 32-bit register encoding */ +static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; + +/* convert micro_mips to mips32 format */ +static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; +static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; +static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; +static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; + +/* + * This functions translates a 32 bit micro_mips instr into a 32 bit mips32 instr. + * It return 0 or SIGILL. + */ +static int micro_mips32_to_mips32(union mips_instruction *insn_ptr) +{ + union mips_instruction insn = *insn_ptr; + union mips_instruction mips32_insn = insn; /* assume they are the same */ + int func; + int fmt; + int op; + + switch (insn.mm_i_format.opcode) { + case mm_ldc132_op: + mips32_insn.mm_i_format.opcode = ldc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_lwc132_op: + mips32_insn.mm_i_format.opcode = lwc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_sdc132_op: + mips32_insn.mm_i_format.opcode = sdc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_swc132_op: + mips32_insn.mm_i_format.opcode = swc1_op; + mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; + mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; + break; + case mm_pool32i_op: + /* NOTE: offset is << by 1 if in micro_mips mode */ + if ((insn.mm_i_format.rt == mm_bc1f_op) || (insn.mm_i_format.rt == mm_bc1t_op)) { + mips32_insn.fb_format.opcode = cop1_op; + mips32_insn.fb_format.bc = bc_op; + mips32_insn.fb_format.flag = (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; + } else + return SIGILL; + break; + case mm_pool32f_op: + switch (insn.mm_fp0_format.func) { + case mm_32f_01_op: + case mm_32f_11_op: + case mm_32f_02_op: + case mm_32f_12_op: + case mm_32f_41_op: + case mm_32f_51_op: + case mm_32f_42_op: + case mm_32f_52_op: + op = insn.mm_fp0_format.func; + if (op == mm_32f_01_op) + func = madd_s_op; + else if (op == mm_32f_11_op) + func = madd_d_op; + else if (op == mm_32f_02_op) + func = nmadd_s_op; + else if (op == mm_32f_12_op) + func = nmadd_d_op; + else if (op == mm_32f_41_op) + func = msub_s_op; + else if (op == mm_32f_51_op) + func = msub_d_op; + else if (op == mm_32f_42_op) + func = nmsub_s_op; + else + func = nmsub_d_op; + mips32_insn.fp6_format.opcode = cop1x_op; + mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; + mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; + mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; + mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; + mips32_insn.fp6_format.func = func; + break; + case mm_32f_10_op: + func = -1; /* set to invalid value */ + op = insn.mm_fp5_format.op & 0x7; + if (op == mm_ldxc1_op) + func = ldxc1_op; + else if (op == mm_sdxc1_op) + func = sdxc1_op; + else if (op == mm_lwxc1_op) + func = lwxc1_op; + else if (op == mm_swxc1_op) + func = swxc1_op; + + if (func != -1) { + mips32_insn.r_format.opcode = cop1x_op; + mips32_insn.r_format.rs = insn.mm_fp5_format.base; + mips32_insn.r_format.rt = insn.mm_fp5_format.index; + mips32_insn.r_format.rd = 0; + mips32_insn.r_format.re = insn.mm_fp5_format.fd; + mips32_insn.r_format.func = func; + } else + return SIGILL; + break; + case mm_32f_40_op: + op = -1; /* set to invalid value */ + if (insn.mm_fp2_format.op == mm_fmovt_op) + op = 1; + else if (insn.mm_fp2_format.op == mm_fmovf_op) + op = 0; + if (op != -1) { + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp2_format.fmt]; + mips32_insn.fp0_format.ft = (insn.mm_fp2_format.cc<<2) + op; + mips32_insn.fp0_format.fs = insn.mm_fp2_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp2_format.fd; + mips32_insn.fp0_format.func = fmovc_op; + } else + return SIGILL; + break; + case mm_32f_60_op: + func = -1; /* set to invalid value */ + if (insn.mm_fp0_format.op == mm_fadd_op) + func = fadd_op; + else if (insn.mm_fp0_format.op == mm_fsub_op) + func = fsub_op; + else if (insn.mm_fp0_format.op == mm_fmul_op) + func = fmul_op; + else if (insn.mm_fp0_format.op == mm_fdiv_op) + func = fdiv_op; + if (func != -1) { + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp0_format.fmt]; + mips32_insn.fp0_format.ft = insn.mm_fp0_format.ft; + mips32_insn.fp0_format.fs = insn.mm_fp0_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp0_format.fd; + mips32_insn.fp0_format.func = func; + } else + return SIGILL; + break; + case mm_32f_70_op: + func = -1; /* set to invalid value */ + if (insn.mm_fp0_format.op == mm_fmovn_op) + func = fmovn_op; + else if (insn.mm_fp0_format.op == mm_fmovz_op) + func = fmovz_op; + if (func != -1) { + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp0_format.fmt]; + mips32_insn.fp0_format.ft = insn.mm_fp0_format.ft; + mips32_insn.fp0_format.fs = insn.mm_fp0_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp0_format.fd; + mips32_insn.fp0_format.func = func; + } else + return SIGILL; + break; + case mm_32f_73_op: /* POOL32FXF */ + switch (insn.mm_fp1_format.op) { + case mm_movf0_op: + case mm_movf1_op: + case mm_movt0_op: + case mm_movt1_op: + if ((insn.mm_fp1_format.op & 0x7f) == mm_movf0_op) + op = 0; + else + op = 1; + mips32_insn.r_format.opcode = spec_op; + mips32_insn.r_format.rs = insn.mm_fp4_format.fs; + mips32_insn.r_format.rt = (insn.mm_fp4_format.cc<<2) + op; + mips32_insn.r_format.rd = insn.mm_fp4_format.rt; + mips32_insn.r_format.re = 0; + mips32_insn.r_format.func = movc_op; + break; + case mm_fcvtd0_op: + case mm_fcvtd1_op: + case mm_fcvts0_op: + case mm_fcvts1_op: + if ((insn.mm_fp1_format.op & 0x7f) == mm_fcvtd0_op) { + func = fcvtd_op; + fmt = swl_format[insn.mm_fp3_format.fmt]; + } else { + func = fcvts_op; + fmt = dwl_format[insn.mm_fp3_format.fmt]; + } + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = fmt; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp3_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp3_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_fmov0_op: + case mm_fmov1_op: + case mm_fabs0_op: + case mm_fabs1_op: + case mm_fneg0_op: + case mm_fneg1_op: + if ((insn.mm_fp1_format.op & 0x7f) == mm_fmov0_op) + func = fmov_op; + else if ((insn.mm_fp1_format.op & 0x7f) == mm_fabs0_op) + func = fabs_op; + else + func = fneg_op; + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp3_format.fmt]; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp3_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp3_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_ffloorl_op: + case mm_ffloorw_op: + case mm_fceill_op: + case mm_fceilw_op: + case mm_ftruncl_op: + case mm_ftruncw_op: + case mm_froundl_op: + case mm_froundw_op: + case mm_fcvtl_op: + case mm_fcvtw_op: + if (insn.mm_fp1_format.op == mm_ffloorl_op) + func = ffloorl_op; + else if (insn.mm_fp1_format.op == mm_ffloorw_op) + func = ffloor_op; + else if (insn.mm_fp1_format.op == mm_fceill_op) + func = fceill_op; + else if (insn.mm_fp1_format.op == mm_fceilw_op) + func = fceil_op; + else if (insn.mm_fp1_format.op == mm_ftruncl_op) + func = ftruncl_op; + else if (insn.mm_fp1_format.op == mm_ftruncw_op) + func = ftrunc_op; + else if (insn.mm_fp1_format.op == mm_froundl_op) + func = froundl_op; + else if (insn.mm_fp1_format.op == mm_froundw_op) + func = fround_op; + else if (insn.mm_fp1_format.op == mm_fcvtl_op) + func = fcvtl_op; + else + func = fcvtw_op; + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sd_format[insn.mm_fp1_format.fmt]; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp1_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp1_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_frsqrt_op: + case mm_fsqrt_op: + case mm_frecip_op: + if (insn.mm_fp1_format.op == mm_frsqrt_op) + func = frsqrt_op; + else if (insn.mm_fp1_format.op == mm_fsqrt_op) + func = fsqrt_op; + else + func = frecip_op; + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp1_format.fmt]; + mips32_insn.fp0_format.ft = 0; + mips32_insn.fp0_format.fs = insn.mm_fp1_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp1_format.rt; + mips32_insn.fp0_format.func = func; + break; + case mm_mfc1_op: + case mm_mtc1_op: + case mm_cfc1_op: + case mm_ctc1_op: + if (insn.mm_fp1_format.op == mm_mfc1_op) + op = mfc_op; + else if (insn.mm_fp1_format.op == mm_mtc1_op) + op = mtc_op; + else if (insn.mm_fp1_format.op == mm_cfc1_op) + op = cfc_op; + else + op = ctc_op; + mips32_insn.fp1_format.opcode = cop1_op; + mips32_insn.fp1_format.op = op; + mips32_insn.fp1_format.rt = insn.mm_fp1_format.rt; + mips32_insn.fp1_format.fs = insn.mm_fp1_format.fs; + mips32_insn.fp1_format.fd = 0; + mips32_insn.fp1_format.func = 0; + break; + default: + return SIGILL; + break; + } + break; + case mm_32f_74_op: /* c.cond.fmt */ + mips32_insn.fp0_format.opcode = cop1_op; + mips32_insn.fp0_format.fmt = sdps_format[insn.mm_fp4_format.fmt]; + mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; + mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; + mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc<<2; + mips32_insn.fp0_format.func = insn.mm_fp4_format.cond | MIPS32_COND_FC; + break; + default: + return SIGILL; + break; + } + break; + default: + return SIGILL; + break; + } + + *insn_ptr = mips32_insn; + return 0; +} + +/* micro_mips version of isBranchInstr() */ +int mm_isBranchInstr(struct pt_regs *regs, struct decoded_instn dec_insn, + unsigned long *contpc) +{ + union mips_instruction insn = (union mips_instruction)dec_insn.insn; + int bc_false = 0; + unsigned int fcr31; + unsigned int bit; + + /* NOTE: for 16-bit instructions, they are duplicated and stored as a 32-bit value. */ + switch (insn.mm_i_format.opcode) { + case mm_pool32a_op: + if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MSK) == mm_pool32axf_op) { + switch (insn.mm_i_format.simmediate >> MM_POOL32A_MINOR_SFT) { + case mm_jalr_op: + case mm_jalrhb_op: + case mm_jalrs_op: + case mm_jalrshb_op: + if (insn.mm_i_format.rt != 0) /* not a mm_jr_op */ + regs->regs[insn.mm_i_format.rt] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + *contpc = regs->regs[insn.mm_i_format.rs]; + return 1; + break; + } + } + break; + case mm_pool32i_op: + switch (insn.mm_i_format.rt) { + case mm_bltzals_op: + case mm_bltzal_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_bltz_op: + if ((long)regs->regs[insn.mm_i_format.rs] < 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bgezals_op: + case mm_bgezal_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_bgez_op: + if ((long)regs->regs[insn.mm_i_format.rs] >= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_blez_op: + if ((long)regs->regs[insn.mm_i_format.rs] <= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bgtz_op: + if ((long)regs->regs[insn.mm_i_format.rs] <= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bc2f_op: + case mm_bc1f_op: + bc_false = 1; + /* Fall through */ + case mm_bc2t_op: + case mm_bc1t_op: + preempt_disable(); + if (is_fpu_owner()) + asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); + else + fcr31 = current->thread.fpu.fcr31; + preempt_enable(); + + if (bc_false) + fcr31 = ~fcr31; + + bit = (insn.mm_i_format.rs >> 2); + bit += (bit != 0); + bit += 23; + if (fcr31 & (1 << bit)) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + } + break; + case mm_pool16c_op: + switch (insn.mm_i_format.rt) { + case mm_jalr16_op: + case mm_jalrs16_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_jr16_op: + *contpc = regs->regs[insn.mm_i_format.rs]; + return 1; + break; + } + break; + case mm_beqz16_op: + if ((long)regs->regs[reg16to32map[insn.mm16b1_format.rs]] == 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm16b1_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bnez16_op: + if ((long)regs->regs[reg16to32map[insn.mm16b1_format.rs]] != 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm16b1_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_b16_op: + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm16b0_format.simmediate << 1); + return 1; + break; + case mm_beq32_op: + if (regs->regs[insn.mm_i_format.rs] == regs->regs[insn.mm_i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_bne32_op: + if (regs->regs[insn.mm_i_format.rs] != regs->regs[insn.mm_i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_i_format.simmediate << 1); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case mm_jalx32_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + + dec_insn.next_pc_inc; + *contpc = regs->cp0_epc + dec_insn.pc_inc; + *contpc >>= 28; + *contpc <<= 28; + *contpc |= (insn.j_format.target << 2); + return 1; + break; + case mm_jals32_op: + case mm_jal32_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case mm_j32_op: + *contpc = regs->cp0_epc + dec_insn.pc_inc; + *contpc >>= 27; + *contpc <<= 27; + *contpc |= (insn.j_format.target << 1); + *contpc |= MIPS_ISA_MODE; + return 1; + break; + } + return 0; +} /* * Redundant with logic already in kernel/branch.c, @@ -117,53 +589,134 @@ static const unsigned int fpucondbit[8] = { * a single subroutine should be used across both * modules. */ -static int isBranchInstr(mips_instruction * i) +static int isBranchInstr(struct pt_regs *regs, struct decoded_instn dec_insn, unsigned long *contpc) { - switch (MIPSInst_OPCODE(*i)) { + union mips_instruction insn = (union mips_instruction)dec_insn.insn; + unsigned int fcr31; + unsigned int bit = 0; + + switch (insn.i_format.opcode) { case spec_op: - switch (MIPSInst_FUNC(*i)) { + switch (insn.r_format.func) { case jalr_op: + regs->regs[insn.r_format.rd] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ case jr_op: + *contpc = regs->regs[insn.r_format.rs]; return 1; + break; } break; - case bcond_op: - switch (MIPSInst_RT(*i)) { + switch (insn.i_format.rt) { + case bltzal_op: + case bltzall_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ case bltz_op: - case bgez_op: case bltzl_op: - case bgezl_op: - case bltzal_op: + if ((long)regs->regs[insn.i_format.rs] < 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; case bgezal_op: - case bltzall_op: case bgezall_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case bgez_op: + case bgezl_op: + if ((long)regs->regs[insn.i_format.rs] >= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; + break; } break; - - case j_op: - case jal_op: case jalx_op: + bit = MIPS_ISA_MODE; + case jal_op: + regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + /* Fall through */ + case j_op: + *contpc = regs->cp0_epc + dec_insn.pc_inc; + *contpc >>= 28; + *contpc <<= 28; + *contpc |= (insn.j_format.target << 2); + /* set micro_mips mode bit: xor for jalx. LY22 */ + *contpc ^= bit; + return 1; + break; case beq_op: - case bne_op: - case blez_op: - case bgtz_op: case beql_op: + if (regs->regs[insn.i_format.rs] == regs->regs[insn.i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case bne_op: case bnel_op: + if (regs->regs[insn.i_format.rs] != regs->regs[insn.i_format.rt]) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case blez_op: case blezl_op: + if ((long)regs->regs[insn.i_format.rs] <= 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case bgtz_op: case bgtzl_op: + if ((long)regs->regs[insn.i_format.rs] > 0) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - + break; case cop0_op: case cop1_op: case cop2_op: case cop1x_op: - if (MIPSInst_RS(*i) == bc_op) - return 1; + if (insn.i_format.rs == bc_op) { + preempt_disable(); + if (is_fpu_owner()) + asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); + else + fcr31 = current->thread.fpu.fcr31; + preempt_enable(); + + bit = (insn.i_format.rt >> 2); + bit += (bit != 0); + bit += 23; + switch (insn.i_format.rt & 3) { + case 0: /* bc1f */ + case 2: /* bc1fl */ + if (~fcr31 & (1 << bit)) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + case 1: /* bc1t */ + case 3: /* bc1tl */ + if (fcr31 & (1 << bit)) + *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.i_format.simmediate << 2); + else + *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; + return 1; + break; + } /* end of inner switch-statement */ + } break; } - return 0; } @@ -209,26 +762,23 @@ static inline int cop1_64bit(struct pt_regs *xcp) */ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - void *__user *fault_addr) + struct decoded_instn dec_insn, void *__user *fault_addr) { mips_instruction ir; - unsigned long emulpc, contpc; + unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; unsigned int cond; - - if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGBUS; - } - if (__get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGSEGV; - } + int pc_inc; /* XXX NEC Vr54xx bug workaround */ - if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir)) - xcp->cp0_cause &= ~CAUSEF_BD; + if (xcp->cp0_cause & CAUSEF_BD) { + if (dec_insn.micro_mips_mode) { + if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) + xcp->cp0_cause &= ~CAUSEF_BD; + } else { + if (!isBranchInstr(xcp, dec_insn, &contpc)) + xcp->cp0_cause &= ~CAUSEF_BD; + } + } if (xcp->cp0_cause & CAUSEF_BD) { /* @@ -243,32 +793,27 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * Linux MIPS branch emulator operates on context, updating the * cp0_epc. */ - emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */ - if (__compute_return_epc(xcp) < 0) { -#ifdef CP1DBG - printk("failed to emulate branch at %p\n", - (void *) (xcp->cp0_epc)); -#endif - return SIGILL; - } - if (!access_ok(VERIFY_READ, emulpc, sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)emulpc; - return SIGBUS; - } - if (__get_user(ir, (mips_instruction __user *) emulpc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)emulpc; - return SIGSEGV; - } - /* __compute_return_epc() will have updated cp0_epc */ - contpc = xcp->cp0_epc; - /* In order not to confuse ptrace() et al, tweak context */ - xcp->cp0_epc = emulpc - 4; + /* NOTE: contpc is modified by isBranchInstr() if it is a branch instr */ + + ir = dec_insn.next_insn; /* process delay slot instr */ + pc_inc = dec_insn.next_pc_inc; } else { - emulpc = xcp->cp0_epc; - contpc = xcp->cp0_epc + 4; + ir = dec_insn.insn; /* process current instr */ + pc_inc = dec_insn.pc_inc; + } + + /* Since micro_mips FPU instructios are a subset of mips32 FPU instructions, */ + /* we want to convert micro_mips FPU instructions into mips32 instrunction so */ + /* that we could reuse all of the FPU emulation code. */ + /* NOTE: we can't do this for branch instructions since they are not a subset */ + /* ex: can't emulate a 16-bit aligned target address with a mips32 instn */ + if (dec_insn.micro_mips_mode) { + /* if next instn is a 16-bit instn then it can't be FPU instn */ + /* This could happen since this function can be called with non FPU instructions. */ + if ((pc_inc == 2) || + (micro_mips32_to_mips32((union mips_instruction *)&ir) == SIGILL)) + return SIGILL; } emul: @@ -473,22 +1018,30 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, /* branch taken: emulate dslot * instruction */ - xcp->cp0_epc += 4; - contpc = (xcp->cp0_epc + - (MIPSInst_SIMM(ir) << 2)); - - if (!access_ok(VERIFY_READ, xcp->cp0_epc, - sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGBUS; - } - if (__get_user(ir, - (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGSEGV; - } + xcp->cp0_epc += dec_insn.pc_inc; + + contpc = MIPSInst_SIMM(ir); + ir = dec_insn.next_insn; + if (dec_insn.micro_mips_mode) { + contpc = (xcp->cp0_epc + (contpc << 1)); + + /* if next instn is a 16-bit instn then it can't be FPU instn */ + if ((dec_insn.next_pc_inc == 2) || + (micro_mips32_to_mips32((union mips_instruction *)&ir) == SIGILL)) { + + /* since this instn will be put on the stack with 32-bit words */ + /* get around this problem by putting a NOP16 as the 2nd instn */ + if (dec_insn.next_pc_inc == 2) + ir = (ir & (~0xffff)) | MM_NOP16; + + /* + * Single step the non-cp1 + * instruction in the dslot + */ + return mips_dsemul(xcp, ir, contpc); + } + } else + contpc = (xcp->cp0_epc + (contpc << 2)); switch (MIPSInst_OPCODE(ir)) { case lwc1_op: @@ -524,8 +1077,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * branch likely nullifies * dslot if not taken */ - xcp->cp0_epc += 4; - contpc += 4; + xcp->cp0_epc += dec_insn.pc_inc; + contpc += dec_insn.pc_inc; /* * else continue & execute * dslot as normal insn @@ -1312,25 +1865,58 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu, void *__user *fault_addr) { unsigned long oldepc, prevepc; - mips_instruction insn; + struct decoded_instn dec_insn; + u16 instr[4]; + u16 *instr_ptr; int sig = 0; oldepc = xcp->cp0_epc; do { prevepc = xcp->cp0_epc; - if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGBUS; - } - if (__get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); - *fault_addr = (mips_instruction __user *)xcp->cp0_epc; - return SIGSEGV; + if (is16mode(xcp) && cpu_has_mmips) { + /* get the next 2 micro_mips instn and decode them into 2 mips32 instn */ + if ((get_user(instr[0], (u16 __user *)(xcp->cp0_epc & ~MIPS_ISA_MODE))) || + (get_user(instr[1], (u16 __user *)((xcp->cp0_epc+2) & ~MIPS_ISA_MODE))) || + (get_user(instr[2], (u16 __user *)((xcp->cp0_epc+4) & ~MIPS_ISA_MODE))) || + (get_user(instr[3], (u16 __user *)((xcp->cp0_epc+6) & ~MIPS_ISA_MODE)))) { + MIPS_FPU_EMU_INC_STATS(errors); + return SIGBUS; + } + instr_ptr = instr; + /* get 1st instruction */ + if (mm_is16bit(*instr_ptr)) { + dec_insn.insn = (*instr_ptr << 16) | (*instr_ptr); /* duplicate the half-word */ + dec_insn.pc_inc = 2; /* 16 bit instr */ + instr_ptr += 1; + } else { + dec_insn.insn = (*instr_ptr << 16) | *(instr_ptr+1); + dec_insn.pc_inc = 4; /* 32 bit instr */ + instr_ptr += 2; + } + /* get 2nd instruction */ + if (mm_is16bit(*instr_ptr)) { + dec_insn.next_insn = (*instr_ptr << 16) | (*instr_ptr); /* duplicate the half-word */ + dec_insn.next_pc_inc = 2; /* 16 bit instr */ + } else { + dec_insn.next_insn = (*instr_ptr << 16) | *(instr_ptr+1); + dec_insn.next_pc_inc = 4; /* 32 bit instr */ + } + dec_insn.micro_mips_mode = 1; + } else { + if ((get_user(dec_insn.insn, (mips_instruction __user *) xcp->cp0_epc)) || + (get_user(dec_insn.next_insn, (mips_instruction __user *)(xcp->cp0_epc+4)))) { + MIPS_FPU_EMU_INC_STATS(errors); + return SIGBUS; + } + dec_insn.pc_inc = 4; + dec_insn.next_pc_inc = 4; + dec_insn.micro_mips_mode = 0; } - if (insn == 0) - xcp->cp0_epc += 4; /* skip nops */ + + if ((dec_insn.insn == 0) || + ((dec_insn.pc_inc == 2) && ((dec_insn.insn & 0xffff) == MM_NOP16))) + xcp->cp0_epc += dec_insn.pc_inc; /* skip nops */ else { /* * The 'ieee754_csr' is an alias of @@ -1340,7 +1926,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, */ /* convert to ieee library modes */ ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; - sig = cop1Emulate(xcp, ctx, fault_addr); + sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); /* revert to mips rounding mode */ ieee754_csr.rm = mips_rm[ieee754_csr.rm]; } @@ -1358,6 +1944,8 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, /* but if epc has advanced, then ignore it */ sig = 0; + /*if (sig == SIGILL) printk("Illegal micro_mips FPU instruction: 0x%x, 0x%x\n", dec_insn.insn, dec_insn.next_insn);*/ + return sig; } diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 384a3b0..67bf6d5 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -54,8 +54,15 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) extern asmlinkage void handle_dsemulret(void); struct emuframe __user *fr; int err; + int nop = 0; - if (ir == 0) { /* a nop is easy */ + if (regs->cp0_epc & 1) { + if ((ir >> 16) == MM_NOP16) + nop = 1; + } else if (ir == 0) + nop = 1; + + if (nop == 1) { /* a nop is easy */ regs->cp0_epc = cpc; regs->cp0_cause &= ~CAUSEF_BD; return 0; @@ -91,8 +98,17 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) return SIGBUS; - err = __put_user(ir, &fr->emul); - err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); + if (regs->cp0_epc & 1) { + err = __put_user(ir >> 16, (u16 __user *)(&fr->emul)); + err |= __put_user(ir & 0xffff, (u16 __user *)((long)(&fr->emul) + 2)); + err |= __put_user(MM_BREAK_MATH >> 16, (u16 __user *)(&fr->badinst)); + err |= __put_user(MM_BREAK_MATH & 0xffff, (u16 __user *)((long)(&fr->badinst) + 2)); + } else { + err = __put_user(ir, &fr->emul); + err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); + } + + /* NOTE: assume the 2nd instn is never executed => can leave as mips32 instr */ err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); err |= __put_user(cpc, &fr->epc); @@ -101,7 +117,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) return SIGBUS; } - regs->cp0_epc = (unsigned long) &fr->emul; + regs->cp0_epc = ((unsigned long) &fr->emul) | (regs->cp0_epc & 1); flush_cache_sigtramp((unsigned long)&fr->badinst); @@ -114,9 +130,14 @@ int do_dsemulret(struct pt_regs *xcp) unsigned long epc; u32 insn, cookie; int err = 0; + u32 break_math = BREAK_MATH; + u16 instr[2]; + + if (xcp->cp0_epc & 1) + break_math = MM_BREAK_MATH; fr = (struct emuframe __user *) - (xcp->cp0_epc - sizeof(mips_instruction)); + ((xcp->cp0_epc & (~1)) - sizeof(mips_instruction)); /* * If we can't even access the area, something is very wrong, but we'll @@ -131,10 +152,15 @@ int do_dsemulret(struct pt_regs *xcp) * - Is the instruction pointed to by the EPC an BREAK_MATH? * - Is the following memory word the BD_COOKIE? */ - err = __get_user(insn, &fr->badinst); + if (xcp->cp0_epc & 1) { + err = __get_user(instr[0], (u16 __user *)(&fr->badinst)); + err |= __get_user(instr[1], (u16 __user *)((long)(&fr->badinst) + 2)); + insn = (instr[0] << 16) | instr[1]; + } else + err = __get_user(insn, &fr->badinst); err |= __get_user(cookie, &fr->cookie); - if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { + if (unlikely(err || (insn != break_math) || (cookie != BD_COOKIE))) { MIPS_FPU_EMU_INC_STATS(errors); return 0; } -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 17:58:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 17:59:02 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39869 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903628Ab2DIP6y (ORCPT ); Mon, 9 Apr 2012 17:58:54 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHGzP-0005yg-99; Mon, 09 Apr 2012 10:58:47 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH] Multi-threaded FPU support for SMTC configuration. Date: Mon, 9 Apr 2012 10:58:39 -0500 Message-Id: <1333987119-605-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32902 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7550 Lines: 241 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mipsmtregs.h | 15 ++++++- arch/mips/include/asm/smtc.h | 6 +++ arch/mips/kernel/smp.c | 4 +- arch/mips/kernel/smtc.c | 84 ++++++++++++++++++++++++++++++------ 4 files changed, 95 insertions(+), 14 deletions(-) diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h index c9420aa..5b3cb85 100644 --- a/arch/mips/include/asm/mipsmtregs.h +++ b/arch/mips/include/asm/mipsmtregs.h @@ -28,6 +28,9 @@ #define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) +#define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) +#define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) + #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) @@ -48,7 +51,7 @@ #define CP0_VPECONF0 $1, 2 #define CP0_VPECONF1 $1, 3 #define CP0_YQMASK $1, 4 -#define CP0_VPESCHEDULE $1, 5 +#define CP0_VPESCHEDULE $1, 5 #define CP0_VPESCHEFBK $1, 6 #define CP0_TCSTATUS $2, 1 #define CP0_TCBIND $2, 2 @@ -124,6 +127,14 @@ #define VPECONF0_XTC_SHIFT 21 #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) +/* VPEConf1 fields (per VPE) */ +#define VPECONF1_NCP1_SHIFT 0 +#define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT) +#define VPECONF1_NCP2_SHIFT 10 +#define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT) +#define VPECONF1_NCX_SHIFT 20 +#define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT) + /* TCStatus fields (per TC) */ #define TCSTATUS_TASID (_ULCAST_(0xff)) #define TCSTATUS_IXMT_SHIFT 10 @@ -350,6 +361,8 @@ do { \ #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) #define read_vpe_c0_vpeconf0() mftc0(1, 2) #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) +#define read_vpe_c0_vpeconf1() mftc0(1, 3) +#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) #define read_vpe_c0_count() mftc0(9, 0) #define write_vpe_c0_count(val) mttc0(9, 0, val) #define read_vpe_c0_status() mftc0(12, 0) diff --git a/arch/mips/include/asm/smtc.h b/arch/mips/include/asm/smtc.h index c9736fc..8935426 100644 --- a/arch/mips/include/asm/smtc.h +++ b/arch/mips/include/asm/smtc.h @@ -33,6 +33,12 @@ typedef long asiduse; #endif #endif +/* + * VPE Management information + */ + +#define MAX_SMTC_VPES MAX_SMTC_TLBS /* FIXME: May not always be true. */ + extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; struct mm_struct; diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 9c1cce9..a5bc9ad 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -102,7 +102,9 @@ asmlinkage __cpuinit void start_secondary(void) #ifdef CONFIG_MIPS_MT_SMTC /* Only do cpu_probe for first TC of CPU */ - if ((read_c0_tcbind() & TCBIND_CURTC) == 0) + if ((read_c0_tcbind() & TCBIND_CURTC) != 0) + __cpu_name[smp_processor_id()] = __cpu_name[0]; + else #endif /* CONFIG_MIPS_MT_SMTC */ cpu_probe(); cpu_report(); diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index c4f75bb..12ec8ed 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -86,6 +86,13 @@ struct smtc_ipi_q IPIQ[NR_CPUS]; static struct smtc_ipi_q freeIPIq; +/* + * Number of FPU contexts for each VPE + */ + +static int smtc_nconf1[MAX_SMTC_VPES]; + + /* Forward declarations */ void ipi_decode(struct smtc_ipi *); @@ -174,9 +181,9 @@ static int __init tintq(char *str) __setup("tintq=", tintq); -static int imstuckcount[2][8]; +static int imstuckcount[MAX_SMTC_VPES][8]; /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ -static int vpemask[2][8] = { +static int vpemask[MAX_SMTC_VPES][8] = { {0, 0, 1, 0, 0, 0, 0, 1}, {0, 0, 0, 0, 0, 0, 0, 1} }; @@ -322,7 +329,7 @@ int __init smtc_build_cpu_map(int start_cpu_slot) /* * Common setup before any secondaries are started - * Make sure all CPU's are in a sensible state before we boot any of the + * Make sure all CPUs are in a sensible state before we boot any of the * secondaries. * * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly @@ -331,6 +338,22 @@ int __init smtc_build_cpu_map(int start_cpu_slot) static void smtc_tc_setup(int vpe, int tc, int cpu) { + static int cp1contexts[MAX_SMTC_VPES]; + + /* + * Make a local copy of the available FPU contexts in order + * to keep track of TCs that can have one. + */ + if (tc == 1) + { + /* + * FIXME: Multi-core SMTC hasn't been tested and the + * maximum number of VPEs may change. + */ + cp1contexts[0] = smtc_nconf1[0] - 1; + cp1contexts[1] = smtc_nconf1[1]; + } + settc(tc); write_tc_c0_tchalt(TCHALT_H); mips_ihb(); @@ -340,26 +363,33 @@ static void smtc_tc_setup(int vpe, int tc, int cpu) /* * TCContext gets an offset from the base of the IPIQ array * to be used in low-level code to detect the presence of - * an active IPI queue + * an active IPI queue. */ write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16); - /* Bind tc to vpe */ + + /* Bind TC to VPE. */ write_tc_c0_tcbind(vpe); - /* In general, all TCs should have the same cpu_data indications */ + + /* In general, all TCs should have the same cpu_data indications. */ memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); - /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ - if (cpu_data[0].cputype == CPU_34K || - cpu_data[0].cputype == CPU_1004K) + + /* Check to see if there is a FPU context available for this TC. */ + if (!cp1contexts[vpe]) cpu_data[cpu].options &= ~MIPS_CPU_FPU; + else + cp1contexts[vpe]--; + + /* Store the TC and VPE into the cpu_data structure. */ cpu_data[cpu].vpe_id = vpe; cpu_data[cpu].tc_id = tc; - /* Multi-core SMTC hasn't been tested, but be prepared */ + + /* FIXME: Multi-core SMTC hasn't been tested, but be prepared. */ cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff; } /* - * Tweak to get Count registes in as close a sync as possible. - * Value seems good for 34K-class cores. + * Tweak to get Count registers synced as closely as possible. The + * value seems good for 34K-class cores. */ #define CP0_SKEW 8 @@ -466,6 +496,24 @@ void smtc_prepare_cpus(int cpus) smtc_configure_tlb(); for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) { + /* Get number of CP1 contexts for each VPE. */ + if (tc == 0) + { + /* + * Do not call settc() for TC0 or the FPU context + * value will be incorrect. Besides, we know that + * we are TC0 anyway. + */ + smtc_nconf1[0] = ((read_vpe_c0_vpeconf1() & + VPECONF1_NCP1) >> VPECONF1_NCP1_SHIFT); + if (nvpe == 2) + { + settc(1); + smtc_nconf1[1] = ((read_vpe_c0_vpeconf1() & + VPECONF1_NCP1) >> VPECONF1_NCP1_SHIFT); + settc(0); + } + } if (tcpervpe[vpe] == 0) continue; if (vpe != 0) @@ -479,6 +527,18 @@ void smtc_prepare_cpus(int cpus) */ if (tc != 0) { smtc_tc_setup(vpe, tc, cpu); + if (vpe != 0) { + /* + * Set MVP bit (possibly again). Do it + * here to catch CPUs that have no TCs + * bound to the VPE at reset. In that + * case, a TC must be bound to the VPE + * before we can set VPEControl[MVP] + */ + write_vpe_c0_vpeconf0( + read_vpe_c0_vpeconf0() | + VPECONF0_MVP); + } cpu++; } printk(" %d", tc); -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 18:02:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 18:02:43 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39875 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2DIQCi (ORCPT ); Mon, 9 Apr 2012 18:02:38 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHH31-0005z2-T9; Mon, 09 Apr 2012 11:02:31 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Leonid Yegoshin Subject: [PATCH] Fix FPU flag race condition. Date: Mon, 9 Apr 2012 11:02:25 -0500 Message-Id: <1333987345-716-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32903 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2250 Lines: 74 From: "Steven J. Hill" Subject: [PATCH] Fix race condition with FPU thread task flag during context Signed-off-by: Leonid Yegoshin Signed-off-by: Steven J. Hill --- arch/mips/include/asm/switch_to.h | 6 ++++-- arch/mips/kernel/r4k_switch.S | 12 +++--------- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h index 5d33621..4f8ddba8 100644 --- a/arch/mips/include/asm/switch_to.h +++ b/arch/mips/include/asm/switch_to.h @@ -22,7 +22,7 @@ struct task_struct; * switch_to(n) should switch tasks to task nr n, first * checking that n isn't the current task, in which case it does nothing. */ -extern asmlinkage void *resume(void *last, void *next, void *next_ti); +extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu); extern unsigned int ll_bit; extern struct task_struct *ll_task; @@ -66,11 +66,13 @@ do { \ #define switch_to(prev, next, last) \ do { \ + u32 __usedfpu; \ __mips_mt_fpaff_switch_to(prev); \ if (cpu_has_dsp) \ __save_dsp(prev); \ __clear_software_ll_bit(); \ - (last) = resume(prev, next, task_thread_info(next)); \ + __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \ + (last) = resume(prev, next, task_thread_info(next), __usedfpu); \ } while (0) #define finish_arch_switch(prev) \ diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 9414f93..a675752 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -41,7 +41,7 @@ /* * task_struct *resume(task_struct *prev, task_struct *next, - * struct thread_info *next_ti) + * struct thread_info *next_ti, u32 __usedfpu) */ .align 5 LEAF(resume) @@ -53,16 +53,10 @@ /* * check if we need to save FPU registers */ - PTR_L t3, TASK_THREAD_INFO(a0) - LONG_L t0, TI_FLAGS(t3) - li t1, _TIF_USEDFPU - and t2, t0, t1 - beqz t2, 1f - nor t1, zero, t1 - and t0, t0, t1 - LONG_S t0, TI_FLAGS(t3) + beqz a3, 1f + PTR_L t3, TASK_THREAD_INFO(a0) /* * clear saved user stack CU1 bit */ -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 18:04:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 18:04:39 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39880 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903628Ab2DIQEe (ORCPT ); Mon, 9 Apr 2012 18:04:34 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHH4t-0005zJ-Vk; Mon, 09 Apr 2012 11:04:27 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Leonid Yegoshin Subject: [PATCH] Add MIPS64R2 core support. Date: Mon, 9 Apr 2012 11:04:21 -0500 Message-Id: <1333987461-822-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32904 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4118 Lines: 129 From: "Steven J. Hill" Signed-off-by: Leonid Yegoshin Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 29 +++++++++++++++++++++++------ arch/mips/include/asm/cpu.h | 2 +- arch/mips/kernel/cpu-probe.c | 4 ++++ arch/mips/kernel/traps.c | 1 + 4 files changed, 29 insertions(+), 7 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 991de91..fae33f3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -282,6 +282,7 @@ config MIPS_MALTA select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_CPU_MIPS64_R1 + select SYS_HAS_CPU_MIPS64_R2 select SYS_HAS_CPU_NEVADA select SYS_HAS_CPU_RM7000 select SYS_HAS_EARLY_PRINTK @@ -1761,6 +1762,22 @@ config 64BIT endchoice +config 64BIT_PHYS_ADDR + bool "Kernel supports 64 bit physical addresses" if EXPERIMENTAL + depends on 64BIT + help + Defines 64 bit physical addresses in kernel. + Increases page table sizes. + + It is an alternative for HIGHMEM usage of huge physical memory. + Requires 64bit capable CPU and 64 bit kernel code model. + + Note: without this option kernel can support up to 4GB physical + memory for 4KB pages and up to 64GB for 64KB pages. + +config ARCH_PHYS_ADDR_T_64BIT + def_bool 64BIT_PHYS_ADDR + choice prompt "Kernel page size" default PAGE_SIZE_4KB @@ -2038,12 +2055,6 @@ config SB1_PASS_2_1_WORKAROUNDS depends on CPU_SB1 && CPU_SB1_PASS_2 default y -config 64BIT_PHYS_ADDR - bool - -config ARCH_PHYS_ADDR_T_64BIT - def_bool 64BIT_PHYS_ADDR - config CPU_HAS_SMARTMIPS depends on SYS_SUPPORTS_SMARTMIPS bool "Support for the SmartMIPS ASE" @@ -2488,6 +2499,7 @@ config TRAD_SIGNALS config MIPS32_COMPAT bool "Kernel support for Linux/MIPS 32-bit binary compatibility" depends on 64BIT + default y if CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL help Select this option if you want Linux/MIPS 32-bit binary compatibility. Since all software available for Linux/MIPS is @@ -2506,6 +2518,7 @@ config SYSVIPC_COMPAT config MIPS32_O32 bool "Kernel support for o32 binaries" depends on MIPS32_COMPAT + default y if CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL help Select this option if you want to run o32 binaries. These are pure 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of @@ -2524,6 +2537,10 @@ config MIPS32_N32 If unsure, say N. +comment "64bit kernel, but support of 32bit applications is disabled!" + depends on 64BIT && !MIPS32_O32 && !MIPS32_N32 + depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL + config BINFMT_ELF32 bool default y if MIPS32_O32 || MIPS32_N32 diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 242a401..ef6ee50 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -268,7 +268,7 @@ enum cpu_type_enum { /* * MIPS64 class processors */ - CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, + CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, CPU_XLR, CPU_XLP, diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0a3e3f6..9b0d4cd 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -821,6 +821,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_5KC; __cpu_name[cpu] = "MIPS 5Kc"; break; + case PRID_IMP_5KE: + c->cputype = CPU_5KE; + __cpu_name[cpu] = "MIPS 5KE"; + break; case PRID_IMP_20KC: c->cputype = CPU_20KC; __cpu_name[cpu] = "MIPS 20Kc"; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b88e63d..c42286c 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1351,6 +1351,7 @@ static inline void parity_protection_init(void) break; case CPU_5KC: + case CPU_5KE: write_c0_ecc(0x80000000); back_to_back_c0_hazard(); /* Set the PE bit (bit 31) in the c0_errctl register. */ -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 18:06:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 18:06:54 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39885 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903628Ab2DIQGr (ORCPT ); Mon, 9 Apr 2012 18:06:47 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHH73-0005zb-7q; Mon, 09 Apr 2012 11:06:41 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" , Chris Dearman Subject: [PATCH] Add new GIC clocksource. Date: Mon, 9 Apr 2012 11:06:34 -0500 Message-Id: <1333987594-950-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32905 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9254 Lines: 336 From: "Steven J. Hill" Add new clocksource that uses the counter present on the GIC controller. Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 21 ++++++++- arch/mips/include/asm/gic.h | 3 ++ arch/mips/include/asm/time.h | 8 ++-- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/csrc-gic.c | 49 +++++++++++++++++++++ arch/mips/kernel/irq-gic.c | 3 +- arch/mips/mti-malta/malta-time.c | 88 +++++++++++++++++++++++++++----------- 7 files changed, 141 insertions(+), 32 deletions(-) create mode 100644 arch/mips/kernel/csrc-gic.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fae33f3..3a8d277 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -264,7 +264,6 @@ config MIPS_MALTA select BOOT_ELF32 select BOOT_RAW select CEVT_R4K - select CSRC_R4K select DMA_NONCOHERENT select GENERIC_ISA_DMA select HAVE_PCSPKR_PLATFORM @@ -863,6 +862,24 @@ source "arch/mips/netlogic/Kconfig" endmenu +menu "Clock source" + depends on MIPS_MALTA || MIPS_SEAD3 + +comment "Select one or more precise CPU clock source kernel modules below:" + +config CSRC_R4K + bool "R4K count/compare counter" + default y if !CSRC_GIC + help + Use the R4K count/compare counter for the kernel clock source. + +config CSRC_GIC + bool "GIC global counter (ROC-it or similar system controller)" + help + Use the GIC global counter for the kernel clock source. + +endmenu + config RWSEM_GENERIC_SPINLOCK bool default y @@ -2031,7 +2048,7 @@ config MIPS_APSP_KSPD config MIPS_CMP bool "MIPS CMP framework support" depends on SYS_SUPPORTS_MIPS_CMP - select SYNC_R4K + select SYNC_R4K if CSRC_R4K select SYS_SUPPORTS_SMP select SYS_SUPPORTS_SCHED_SMT if SMP select WEAK_ORDERING diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 991b659..7583417 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -13,6 +13,8 @@ #undef GICISBYTELITTLEENDIAN +extern unsigned long _gic_base; + /* Constants */ #define GIC_POL_POS 1 #define GIC_POL_NEG 0 @@ -345,6 +347,7 @@ extern void gic_init(unsigned long gic_base_addr, unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, unsigned int intrmap_size, unsigned int irqbase); +extern void gic_clocksource_init(unsigned int); extern unsigned int gic_get_int(void); extern void gic_send_ipi(unsigned int intr); extern unsigned int plat_ipi_call_int_xlate(unsigned int); diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index bc14447..96a6c8c 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -77,11 +77,11 @@ extern int init_r4k_clocksource(void); static inline int init_mips_clocksource(void) { -#ifdef CONFIG_CSRC_R4K - return init_r4k_clocksource(); -#else + extern int gic_present; + + if (!gic_present) + return init_r4k_clocksource(); return 0; -#endif } static inline void clockevent_set_clock(struct clock_event_device *cd, diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 0c6877e..1b9af57 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o +obj-$(CONFIG_CSRC_GIC) += csrc-gic.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o obj-$(CONFIG_STACKTRACE) += stacktrace.o diff --git a/arch/mips/kernel/csrc-gic.c b/arch/mips/kernel/csrc-gic.c new file mode 100644 index 0000000..82f09c4 --- /dev/null +++ b/arch/mips/kernel/csrc-gic.c @@ -0,0 +1,49 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 MIPS Technologies, Inc. + */ +#include +#include + +#include +#include + +static cycle_t gic_hpt_read(struct clocksource *cs) +{ + unsigned int hi, hi2, lo; + + do { + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi); + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo); + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2); + } while (hi2 != hi); + + return (((cycle_t) hi) << 32) + lo; +} + +static struct clocksource gic_clocksource = { + .name = "GIC", + .read = gic_hpt_read, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void __init gic_clocksource_init(unsigned int frequency) +{ + unsigned int config, bits; + + /* Calculate the clocksource mask. */ + GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), config); + bits = 32 + ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> + (GIC_SH_CONFIG_COUNTBITS_SHF - 2)); + + /* Set clocksource mask. */ + gic_clocksource.mask = CLOCKSOURCE_MASK(bits); + + /* Calculate a somewhat reasonable rating value. */ + gic_clocksource.rating = 200 + frequency / 10000000; + + clocksource_register_hz(&gic_clocksource, frequency); +} diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 275b163..191a255 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -20,7 +20,8 @@ #include #include -static unsigned long _gic_base; + +unsigned long _gic_base; static unsigned int _irqbase; static unsigned int gic_irq_flags[GIC_NUM_INTRS]; #define GIC_IRQ_FLAG_EDGE 0x0001 diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 115f5bc..c9b2eaa 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include @@ -50,6 +51,10 @@ unsigned long cpu_khz; static int mips_cpu_timer_irq; static int mips_cpu_perf_irq; extern int cp0_perfcount_irq; +#ifdef CONFIG_CSRC_GIC +static int gic_frequency; +extern int gic_present; +#endif static void mips_timer_dispatch(void) { @@ -61,16 +66,23 @@ static void mips_perf_dispatch(void) do_IRQ(mips_cpu_perf_irq); } +static unsigned int freqround(unsigned int freq, unsigned int amount) +{ + freq += amount; + freq -= freq % (amount*2); + return freq; +} + /* - * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect + * Estimate CPU (and GIC) frequencies */ -static unsigned int __init estimate_cpu_frequency(void) +static void __init estimate_frequencies(void) { - unsigned int prid = read_c0_prid() & 0xffff00; - unsigned int count; - unsigned long flags; - unsigned int start; + unsigned int count, start; +#ifdef CONFIG_CSRC_GIC + unsigned int giccount = 0, gicstart = 0; +#endif local_irq_save(flags); @@ -80,25 +92,34 @@ static unsigned int __init estimate_cpu_frequency(void) /* Start r4k counter. */ start = read_c0_count(); +#ifdef CONFIG_CSRC_GIC + if (gic_present) + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart); +#endif /* Read counter exactly on falling edge of update flag */ while (CMOS_READ(RTC_REG_A) & RTC_UIP); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - count = read_c0_count() - start; - + count = read_c0_count(); +#ifdef CONFIG_CSRC_GIC + if (gic_present) + GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount); +#endif /* restore interrupts */ local_irq_restore(flags); - mips_hpt_frequency = count; - if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && - (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) - count *= 2; - - count += 5000; /* round */ - count -= count%10000; + count -= start; +#ifdef CONFIG_CSRC_GIC + if (gic_present) + giccount -= gicstart; +#endif - return count; + mips_hpt_frequency = count; +#ifdef CONFIG_CSRC_GIC + if (gic_present) + gic_frequency = giccount; +#endif } void read_persistent_clock(struct timespec *ts) @@ -144,22 +165,39 @@ unsigned int __cpuinit get_c0_compare_int(void) void __init plat_time_init(void) { - unsigned int est_freq; - - /* Set Data mode - binary. */ - CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - - est_freq = estimate_cpu_frequency(); + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int freq; - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, - (est_freq%1000000)*100/1000000); + estimate_frequencies(); - cpu_khz = est_freq / 1000; + freq = mips_hpt_frequency; + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + freq *= 2; + freq = freqround(freq, 5000); + printk("CPU frequency %d.%02d MHz\n", freq/1000000, + (freq%1000000)*100/1000000); + cpu_khz = freq / 1000; + +#ifdef CONFIG_CSRC_GIC + if (gic_present) { + freq = gic_frequency; + freq = freqround(freq, 5000); + printk("GIC frequency %d.%02d MHz\n", freq/1000000, + (freq%1000000)*100/1000000); + } +#endif mips_scroll_message(); + #ifdef CONFIG_I8253 /* Only Malta has a PIT */ setup_pit_timer(); #endif +#ifdef CONFIG_CSRC_GIC + if (gic_present) + gic_clocksource_init(gic_frequency); +#endif + plat_perf_setup(); } -- 1.7.9.6 From sjhill@mips.com Mon Apr 9 18:11:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2012 18:12:13 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:39891 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903692Ab2DIQLp (ORCPT ); Mon, 9 Apr 2012 18:11:45 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SHHBo-000601-Fa; Mon, 09 Apr 2012 11:11:36 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: "Steven J. Hill" Subject: [PATCH] Update MALTA config files. Date: Mon, 9 Apr 2012 11:11:29 -0500 Message-Id: <1333987889-1069-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.6 X-archive-position: 32906 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 235459 Lines: 9111 From: "Steven J. Hill" Update all the MIPS Technologies MALTA configuration files. This patch will pick up all the new configuratin options added from the previous patches. Signed-off-by: Steven J. Hill --- arch/mips/configs/malta_defconfig | 1762 ++++++++++++++++++++++++++++++++- arch/mips/configs/maltaaprp_defconfig | 1716 ++++++++++++++++++++++++++++++++ arch/mips/configs/maltasmtc_defconfig | 1721 ++++++++++++++++++++++++++++++++ arch/mips/configs/maltasmvp_defconfig | 1751 ++++++++++++++++++++++++++++++++ arch/mips/configs/maltaup_defconfig | 1711 ++++++++++++++++++++++++++++++++ 5 files changed, 8632 insertions(+), 29 deletions(-) create mode 100644 arch/mips/configs/maltaaprp_defconfig create mode 100644 arch/mips/configs/maltasmtc_defconfig create mode 100644 arch/mips/configs/maltasmvp_defconfig create mode 100644 arch/mips/configs/maltaup_defconfig diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 5527abb..5c5350d 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -1,58 +1,467 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/mips 3.3.0 Kernel Configuration +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_ZONE_DMA=y +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LANTIQ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set CONFIG_MIPS_MALTA=y +# CONFIG_MIPS_SEAD3 is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set + +# +# Clock source +# + +# +# Select one or more precise CPU clock source kernel modules below: +# +CONFIG_CSRC_R4K=y +# CONFIG_CSRC_GIC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_BOOT_RAW=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_I8259=y +CONFIG_MIPS_BONITO64=y +CONFIG_MIPS_MSC=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y +CONFIG_ISA_DMA_API=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_GIC=y +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_BOARD_SCACHE=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT_DISABLED is not set CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_MIPS_MT=y +# CONFIG_SCHED_SMT is not set +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_MIPS_MT_FPAFF=y +# CONFIG_MIPS_VPE_LOADER is not set +# CONFIG_MIPS_CMP is not set +# CONFIG_CPU_HAS_SMARTMIPS is not set +# CONFIG_CPU_MICROMIPS is not set +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SYS_SUPPORTS_MIPS_CMP=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_2=y +CONFIG_NR_CPUS=2 +CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_FORCED_THREADING=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=15 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y +CONFIG_USER_NS=y CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y CONFIG_PCI=y -CONFIG_PM=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +CONFIG_MMU=y +CONFIG_I8253=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_RAPIDIO is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +# CONFIG_PM_RUNTIME is not set +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_NET=y + +# +# Networking options +# CONFIG_PACKET=y CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y +# CONFIG_NET_IPGRE_DEMUX is not set CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set CONFIG_SYN_COOKIES=y CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y @@ -60,60 +469,125 @@ CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set CONFIG_IPV6_MROUTE=y +# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set CONFIG_IPV6_PIMSM_V2=y CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +# CONFIG_NETFILTER_NETLINK_ACCT is not set CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m CONFIG_NF_CT_PROTO_UDPLITE=m CONFIG_NF_CONNTRACK_AMANDA=m CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_CT is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_CPU is not set CONFIG_NETFILTER_XT_MATCH_DCCP=m +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +CONFIG_NETFILTER_XT_MATCH_ECN=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -121,12 +595,25 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_IP_SET is not set CONFIG_IP_VS=m CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# CONFIG_IP_VS_PROTO_TCP=y CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y CONFIG_IP_VS_PROTO_ESP=y CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# CONFIG_IP_VS_RR=m CONFIG_IP_VS_WRR=m CONFIG_IP_VS_LC=m @@ -137,23 +624,51 @@ CONFIG_IP_VS_DH=m CONFIG_IP_VS_SH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS application helper +# CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +# CONFIG_IP_VS_PE_SIP is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m +# CONFIG_IP_NF_MATCH_RPFILTER is not set CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -162,6 +677,11 @@ CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -172,6 +692,7 @@ CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m +# CONFIG_IP6_NF_MATCH_RPFILTER is not set CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_TARGET_LOG=m @@ -201,37 +722,78 @@ CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m CONFIG_BRIDGE_EBT_NFLOG=m +# CONFIG_IP_DCCP is not set CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set CONFIG_ATALK=m CONFIG_DEV_APPLETALK=m CONFIG_IPDDP=m CONFIG_IPDDP_ENCAP=y CONFIG_IPDDP_DECAP=y +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set CONFIG_PHONET=m +# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m CONFIG_NET_SCH_TBF=m CONFIG_NET_SCH_GRED=m CONFIG_NET_SCH_DSMARK=m CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_FW=m CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m CONFIG_NET_CLS_FLOW=m +# CONFIG_NET_EMATCH is not set CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y CONFIG_NET_ACT_GACT=m @@ -242,66 +804,373 @@ CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m CONFIG_NET_ACT_SKBEDIT=m +# CONFIG_NET_ACT_CSUM is not set CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_BQL=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set +CONFIG_MAC80211_RC_DEFAULT="pid" CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set CONFIG_RFKILL=m +# CONFIG_RFKILL_INPUT is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set CONFIG_CONNECTOR=m CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set CONFIG_MTD_OOPS=m +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 CONFIG_MTD_UBI_GLUEBI=m +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y CONFIG_BLK_DEV_FD=m +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set CONFIG_BLK_DEV_UMEM=m +# CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set CONFIG_ATA_OVER_ETH=m -# CONFIG_MISC_DEVICES is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_PHANTOM is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# + +# +# Altera FPGA firmware download module +# +CONFIG_HAVE_IDE=y CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +CONFIG_IDE_ATAPI=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_PCIBUS_ORDER=y +# CONFIG_BLK_DEV_OFFBOARD is not set CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set CONFIG_BLK_DEV_PIIX=y +# CONFIG_BLK_DEV_IT8172 is not set CONFIG_BLK_DEV_IT8213=m +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set CONFIG_BLK_DEV_TC86C001=m +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +CONFIG_SCSI_MOD=m CONFIG_RAID_ATTRS=m CONFIG_SCSI=m +CONFIG_SCSI_DMA=y CONFIG_SCSI_TGT=m +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# CONFIG_BLK_DEV_SD=m CONFIG_CHR_DEV_ST=m CONFIG_CHR_DEV_OSST=m CONFIG_BLK_DEV_SR=m CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m CONFIG_SCSI_FC_ATTRS=m +# CONFIG_SCSI_FC_TGT_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=m +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_BE2ISCSI is not set CONFIG_BLK_DEV_3W_XXXX_RAID=m +# CONFIG_SCSI_HPSA is not set CONFIG_SCSI_3W_9XXX=m +# CONFIG_SCSI_3W_SAS is not set CONFIG_SCSI_ACARD=m CONFIG_SCSI_AACRAID=m CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 CONFIG_AIC7XXX_RESET_DELAY_MS=15000 # CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m @@ -309,22 +1178,185 @@ CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m CONFIG_MD_RAID10=m CONFIG_MD_RAID456=m +# CONFIG_MULTICORE_RAID456 is not set CONFIG_MD_MULTIPATH=m CONFIG_MD_FAULTY=m CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m +# CONFIG_DM_THIN_PROVISIONING is not set CONFIG_DM_MIRROR=m +# CONFIG_DM_RAID is not set +# CONFIG_DM_LOG_USERSPACE is not set CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m +# CONFIG_DM_MULTIPATH_QL is not set +# CONFIG_DM_MULTIPATH_ST is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set CONFIG_NETDEVICES=y -CONFIG_IFB=m -CONFIG_DUMMY=m +CONFIG_NET_CORE=y CONFIG_BONDING=m -CONFIG_MACVLAN=m +CONFIG_DUMMY=m CONFIG_EQUALIZER=m +# CONFIG_NET_FC is not set +CONFIG_MII=y +CONFIG_IFB=m +# CONFIG_NET_TEAM is not set +CONFIG_MACVLAN=m +# CONFIG_MACVTAP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set CONFIG_TUN=m CONFIG_VETH=m +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +CONFIG_MDIO=m +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_NET_VENDOR_ADAPTEC=y +# CONFIG_ADAPTEC_STARFIRE is not set +CONFIG_NET_VENDOR_ALTEON=y +# CONFIG_ACENIC is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +CONFIG_PCNET32=y +CONFIG_NET_VENDOR_ATHEROS=y +# CONFIG_ATL2 is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2X is not set +CONFIG_NET_VENDOR_BROCADE=y +# CONFIG_BNA is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_CHELSIO_T1 is not set +CONFIG_CHELSIO_T3=m +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_ENIC is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_DEC=y +# CONFIG_NET_TULIP is not set +CONFIG_NET_VENDOR_DLINK=y +# CONFIG_DL2K is not set +# CONFIG_SUNDANCE is not set +CONFIG_NET_VENDOR_EMULEX=y +# CONFIG_BE2NET is not set +CONFIG_NET_VENDOR_EXAR=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +CONFIG_NET_VENDOR_HP=y +# CONFIG_HP100 is not set +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +CONFIG_NET_VENDOR_I825XX=y +# CONFIG_ZNET is not set +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +CONFIG_NET_VENDOR_MARVELL=y +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_MLX4_EN is not set +# CONFIG_MLX4_CORE is not set +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8851_MLL is not set +# CONFIG_KSZ884X_PCI is not set +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_MYRI10GE is not set +# CONFIG_FEALNX is not set +CONFIG_NET_VENDOR_NATSEMI=y +# CONFIG_NATSEMI is not set +# CONFIG_NS83820 is not set +CONFIG_NET_VENDOR_8390=y +CONFIG_AX88796=m +# CONFIG_AX88796_93CX6 is not set +# CONFIG_NE2K_PCI is not set +CONFIG_NET_VENDOR_NVIDIA=y +# CONFIG_FORCEDETH is not set +CONFIG_NET_VENDOR_OKI=y +# CONFIG_PCH_GBE is not set +# CONFIG_ETHOC is not set +CONFIG_NET_PACKET_ENGINE=y +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_QLOGIC=y +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +CONFIG_NETXEN_NIC=m +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R8169 is not set +CONFIG_NET_VENDOR_RDC=y +# CONFIG_R6040 is not set +CONFIG_NET_VENDOR_SEEQ=y +# CONFIG_SEEQ8005 is not set +CONFIG_NET_VENDOR_SILAN=y +# CONFIG_SC92031 is not set +CONFIG_NET_VENDOR_SIS=y +# CONFIG_SIS900 is not set +# CONFIG_SIS190 is not set +# CONFIG_SFC is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_SMC91X is not set +# CONFIG_EPIC100 is not set +# CONFIG_SMSC911X is not set +# CONFIG_SMSC9420 is not set +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +CONFIG_NET_VENDOR_SUN=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NIU is not set +CONFIG_NET_VENDOR_TEHUTI=y +# CONFIG_TEHUTI is not set +CONFIG_NET_VENDOR_TI=y +# CONFIG_TLAN is not set +CONFIG_NET_VENDOR_TOSHIBA=y +CONFIG_TC35815=m +CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLIB=m + +# +# MII PHY device drivers +# CONFIG_MARVELL_PHY=m CONFIG_DAVICOM_PHY=m CONFIG_QSEMI_PHY=m @@ -335,17 +1367,28 @@ CONFIG_SMSC_PHY=m CONFIG_BROADCOM_PHY=m CONFIG_ICPLUS_PHY=m CONFIG_REALTEK_PHY=m +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set CONFIG_MDIO_BITBANG=m -CONFIG_NET_ETHERNET=y -CONFIG_AX88796=m -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -CONFIG_TC35815=m -CONFIG_CHELSIO_T3=m -CONFIG_NETXEN_NIC=m +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_AIRO is not set CONFIG_ATMEL=m CONFIG_PCI_ATMEL=m CONFIG_PRISM54=m +# CONFIG_RTL8180 is not set +# CONFIG_ADM8211 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +# CONFIG_ATH_COMMON is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_BRCMFMAC is not set CONFIG_HOSTAP=m CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y @@ -353,40 +1396,384 @@ CONFIG_HOSTAP_PLX=m CONFIG_HOSTAP_PCI=m CONFIG_IPW2100=m CONFIG_IPW2100_MONITOR=y +# CONFIG_IPW2100_DEBUG is not set CONFIG_IPW2200=m CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_RADIOTAP=y CONFIG_IPW2200_PROMISCUOUS=y CONFIG_IPW2200_QOS=y +# CONFIG_IPW2200_DEBUG is not set +CONFIG_LIBIPW=m +# CONFIG_LIBIPW_DEBUG is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWL4965 is not set +# CONFIG_IWL3945 is not set CONFIG_LIBERTAS=m +# CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_MESH is not set CONFIG_HERMES=m +# CONFIG_HERMES_PRISM is not set +CONFIG_HERMES_CACHE_FW_ON_INIT=y CONFIG_PLX_HERMES=m CONFIG_TMD_HERMES=m CONFIG_NORTEL_HERMES=m +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set +# CONFIG_RTL8192CE is not set +# CONFIG_RTL8192SE is not set +# CONFIG_RTL8192DE is not set +# CONFIG_WL1251 is not set +# CONFIG_WL12XX_MENU is not set +# CONFIG_MWIFIEX is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MFD_HSU is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_STUB_POULSBO is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_WMT_GE_ROPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# CONFIG_FB_CIRRUS=y +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# # CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y CONFIG_HID=m -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_IDE_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +# CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_XHCI=y +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set CONFIG_UIO=m CONFIG_UIO_CIF=m +# CONFIG_UIO_PDRV is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_UIO_PCI_GENERIC is not set +# CONFIG_UIO_NETX is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_I8253=y +CONFIG_CLKEVT_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_CLKBLD_I8253=y +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set CONFIG_REISERFS_PROC_INFO=y CONFIG_REISERFS_FS_XATTR=y CONFIG_REISERFS_FS_POSIX_ACL=y @@ -394,42 +1781,139 @@ CONFIG_REISERFS_FS_SECURITY=y CONFIG_JFS_FS=m CONFIG_JFS_POSIX_ACL=y CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set CONFIG_XFS_FS=m CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y -CONFIG_AUTOFS_FS=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS4_FS is not set CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# CONFIG_ISO9660_FS=m CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set CONFIG_AFFS_FS=m CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set CONFIG_BFS_FS=m CONFIG_EFS_FS=m CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set CONFIG_VXFS_FS=m CONFIG_MINIX_FS=m +CONFIG_MINIX_FS_NATIVE_ENDIAN=y +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_PSTORE is not set CONFIG_SYSV_FS=m CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set CONFIG_ROOT_NFS=y CONFIG_NFSD=y CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_737=m CONFIG_NLS_CODEPAGE_775=m @@ -467,27 +1951,247 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m -# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_NLS_UTF8=m + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_ASYNC_RAID6_TEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_DEBUG_ZBOOT is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# # CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_BITREVERSE=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_GENERIC_PCI_IOMAP=y +# CONFIG_CRC_CCITT is not set CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set diff --git a/arch/mips/configs/maltaaprp_defconfig b/arch/mips/configs/maltaaprp_defconfig new file mode 100644 index 0000000..022bd65 --- /dev/null +++ b/arch/mips/configs/maltaaprp_defconfig @@ -0,0 +1,1716 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/mips 3.3.0 Kernel Configuration +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_ZONE_DMA=y +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LANTIQ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +CONFIG_MIPS_MALTA=y +# CONFIG_MIPS_SEAD3 is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set + +# +# Clock source +# + +# +# Select one or more precise CPU clock source kernel modules below: +# +CONFIG_CSRC_R4K=y +# CONFIG_CSRC_GIC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_BOOT_RAW=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_I8259=y +CONFIG_MIPS_BONITO64=y +CONFIG_MIPS_MSC=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y +CONFIG_ISA_DMA_API=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_GIC=y +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_BOARD_SCACHE=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_MIPS_MT=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_MIPS_VPE_LOADER=y +CONFIG_MIPS_VPE_LOADER_TOM=y +CONFIG_MIPS_VPE_APSP_API=y +# CONFIG_MIPS_APSP_KSPD is not set +# CONFIG_MIPS_CMP is not set +# CONFIG_CPU_HAS_SMARTMIPS is not set +# CONFIG_CPU_MICROMIPS is not set +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_SYS_SUPPORTS_MIPS_CMP=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="aprp" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_FORCED_THREADING=y + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +CONFIG_MMU=y +CONFIG_I8253=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_RAPIDIO is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +# CONFIG_PM_RUNTIME is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CLS_U32_MARK is not set +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_CSUM is not set +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +CONFIG_BQL=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=m + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_PHANTOM is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# + +# +# Altera FPGA firmware download module +# +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IDE_PROC_FS is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +CONFIG_BLK_DEV_PIIX=y +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +CONFIG_MII=y +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PHYLIB is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_TR is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MFD_HSU is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_STUB_POULSBO is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_WMT_GE_ROPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +# CONFIG_FB_MATROX_MILLENIUM is not set +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_MV is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_OT200 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_I8253=y +CONFIG_CLKEVT_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_CLKBLD_I8253=y +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_DEBUG_ZBOOT is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_GENERIC_PCI_IOMAP=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set diff --git a/arch/mips/configs/maltasmtc_defconfig b/arch/mips/configs/maltasmtc_defconfig new file mode 100644 index 0000000..ca2969a --- /dev/null +++ b/arch/mips/configs/maltasmtc_defconfig @@ -0,0 +1,1721 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/mips 3.3.0 Kernel Configuration +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_ZONE_DMA=y +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LANTIQ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +CONFIG_MIPS_MALTA=y +# CONFIG_MIPS_SEAD3 is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set + +# +# Clock source +# + +# +# Select one or more precise CPU clock source kernel modules below: +# +# CONFIG_CSRC_R4K is not set +CONFIG_CSRC_GIC=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_BOOT_RAW=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_I8259=y +CONFIG_MIPS_BONITO64=y +CONFIG_MIPS_MSC=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y +CONFIG_ISA_DMA_API=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_GIC=y +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_BOARD_SCACHE=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT_DISABLED is not set +# CONFIG_MIPS_MT_SMP is not set +CONFIG_MIPS_MT_SMTC=y +CONFIG_MIPS_MT=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +# CONFIG_MIPS_MT_FPAFF is not set +# CONFIG_MIPS_VPE_LOADER is not set +# CONFIG_MIPS_MT_SMTC_IM_BACKSTOP is not set +# CONFIG_MIPS_MT_SMTC_IRQAFF is not set +# CONFIG_MIPS_CMP is not set +# CONFIG_CPU_HAS_SMARTMIPS is not set +# CONFIG_CPU_MICROMIPS is not set +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SYS_SUPPORTS_MIPS_CMP=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_8=y +CONFIG_NR_CPUS=9 +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_48=y +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=48 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="smtc" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_FORCED_THREADING=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +CONFIG_MMU=y +CONFIG_I8253=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_RAPIDIO is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +# CONFIG_PM_RUNTIME is not set +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CLS_U32_MARK is not set +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_CSUM is not set +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_BQL=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=m + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_PHANTOM is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# + +# +# Altera FPGA firmware download module +# +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IDE_PROC_FS is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +CONFIG_BLK_DEV_PIIX=y +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +CONFIG_MII=y +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PHYLIB is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_TR is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MFD_HSU is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_STUB_POULSBO is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_WMT_GE_ROPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +# CONFIG_FB_MATROX_MILLENIUM is not set +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_MV is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_OT200 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_I8253=y +CONFIG_CLKEVT_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_CLKBLD_I8253=y +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_SMTC_IDLE_HOOK_DEBUG is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_DEBUG_ZBOOT is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_GENERIC_PCI_IOMAP=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig new file mode 100644 index 0000000..97a76b9 --- /dev/null +++ b/arch/mips/configs/maltasmvp_defconfig @@ -0,0 +1,1751 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/mips 3.3.0 Kernel Configuration +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_ZONE_DMA=y +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LANTIQ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +CONFIG_MIPS_MALTA=y +# CONFIG_MIPS_SEAD3 is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set + +# +# Clock source +# + +# +# Select one or more precise CPU clock source kernel modules below: +# +CONFIG_CSRC_R4K=y +CONFIG_CSRC_GIC=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_BOOT_RAW=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_I8259=y +CONFIG_MIPS_BONITO64=y +CONFIG_MIPS_MSC=y +CONFIG_SYNC_R4K=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y +CONFIG_ISA_DMA_API=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_GIC=y +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_WEAK_ORDERING=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_BOARD_SCACHE=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT_DISABLED is not set +CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_MIPS_MT=y +CONFIG_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_MIPS_MT_FPAFF=y +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MIPS_CMP=y +# CONFIG_CPU_HAS_SMARTMIPS is not set +# CONFIG_CPU_MICROMIPS is not set +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SYS_SUPPORTS_MIPS_CMP=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_2=y +CONFIG_NR_CPUS=8 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="cmp" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_FORCED_THREADING=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +CONFIG_MMU=y +CONFIG_I8253=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_RAPIDIO is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +# CONFIG_PM_RUNTIME is not set +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +CONFIG_NET_SCH_INGRESS=m +# CONFIG_NET_SCH_PLUG is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CLS_U32_MARK is not set +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_CSUM is not set +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_BQL=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=m + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_PHANTOM is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# + +# +# Altera FPGA firmware download module +# +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IDE_PROC_FS is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +CONFIG_BLK_DEV_PIIX=y +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +CONFIG_MII=y +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PHYLIB is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_TR is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MFD_HSU is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_STUB_POULSBO is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_WMT_GE_ROPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +CONFIG_FB_MATROX=y +# CONFIG_FB_MATROX_MILLENIUM is not set +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_OT200 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_I8253=y +CONFIG_CLKEVT_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_CLKBLD_I8253=y +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTI