From ddaney.cavm@gmail.com Thu Mar 1 01:57:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Mar 2012 01:57:23 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:38135 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903792Ab2CAA5Q (ORCPT ); Thu, 1 Mar 2012 01:57:16 +0100 Received: by ghbf11 with SMTP id f11so16291ghb.36 for ; Wed, 29 Feb 2012 16:57:10 -0800 (PST) Received-SPF: pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.115.105 as permitted sender) client-ip=10.236.115.105; Authentication-Results: mr.google.com; spf=pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.115.105 as permitted sender) smtp.mail=ddaney.cavm@gmail.com; dkim=pass header.i=ddaney.cavm@gmail.com Received: from mr.google.com ([10.236.115.105]) by 10.236.115.105 with SMTP id d69mr3867440yhh.89.1330563430273 (num_hops = 1); Wed, 29 Feb 2012 16:57:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=PfD6qaTj1g4qWYZ3Z9cQLOW+nS4BpGLqbpVi5hAf5QY=; b=fj6eZnfvnmo1SWE6InvK2E1O4SCeAbPeyoY1sita2jTBjlamVSgZ/BL1WwmBV6Psgi KqcKYrecHIMQw52Aj6DM2sBRHUsfbkl/La8WHU+oHXRHbRmCMeckNRoJTiHWIXKimtsA DfSCsvxFaWUuzseBvHlieCa7nzN8HVdPczJIM= Received: by 10.236.115.105 with SMTP id d69mr3046257yhh.89.1330563430229; Wed, 29 Feb 2012 16:57:10 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id h30sm509495yhk.4.2012.02.29.16.57.09 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 29 Feb 2012 16:57:09 -0800 (PST) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q210v7Vb014115; Wed, 29 Feb 2012 16:57:07 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q210v57m014114; Wed, 29 Feb 2012 16:57:05 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v6 0/5] MIPS: Octeon: Use Device Tree. Date: Wed, 29 Feb 2012 16:56:57 -0800 Message-Id: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 32585 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5045 Lines: 122 From: David Daney This code has now had extensive testing, it is running on more than 10 different boards and SOC combinations. The patches in this set are all in the arch/mips tree and should probably be merged by Ralf. They do depend on this libfdt patch: http://marc.info/?l=linux-kernel&m=133054335203615 New in v6: o Device Tree bindings updated based on feedback and more actual use. o Use of irq_domain support added to recent kernels. New in v5: o New irq triggering mode constants. o Boot protocol to pass flattened device tree from bootloader. This protocol may change based on attempts to arrive at a common protocol for all MIPS boards. New in v4: o Cleanup and error checking suggested by Sergei Shtylyov. o Use device tree passed by bootloader if present. New in v3: o More updates to device tree bindings, and perhaps more importantly descriptions/definitions of the bindings o Cleanup and style improvements as suggested by Grant Likley. o Omitted all the driver changes, as they are unchanged from the last set, and at this stage the patches are just an RFC. New in v2: o Changed many device tree bindings. They should be closer to the standard naming scheme now. o Editing of the template device tree is done in the flattened form using libfdt. o Standard platform driver functions used in preference to the of_platform variety. v1: Background: The Octeon family of SOCs has a variety of on-chip controllers for Ethernet, MDIO, I2C, and several other I/O devices. These chips are used on boards with a great variety of different configurations. To date, the configuration and bus topology information has been hard coded in the drivers and support code. To facilitate supporting new chips and boards, we are using the Device Tree to encode the configuration information. The migration from the legacy approach to the device tree is as follows: o A device tree template is statically linked into the kernel image. Based on SOC type and board type, legacy configuration probing code is used to prune and patch the device tree template. o New SOCs and boards will directly use a device tree passed by the bootloader. David Daney (5): MIPS: Octeon: Add device tree source files. MIPS: Don't define early_init_devtree() and device_tree_init() in prom.c for CPU_CAVIUM_OCTEON MIPS: Octeon: Add irq handlers for GPIO interrupts. MIPS: Octeon: Setup irq_domains for interrupts. MIPS: Octeon: Initialize and fixup device tree. .../bindings/ata/cavium-compact-flash.txt | 30 + .../bindings/gpio/cavium-octeon-gpio.txt | 48 ++ .../devicetree/bindings/i2c/cavium-i2c.txt | 34 ++ .../devicetree/bindings/mips/cavium/bootbus.txt | 126 ++++ .../devicetree/bindings/mips/cavium/ciu.txt | 26 + .../devicetree/bindings/mips/cavium/ciu2.txt | 27 + .../devicetree/bindings/mips/cavium/dma-engine.txt | 21 + .../devicetree/bindings/mips/cavium/uctl.txt | 47 ++ .../devicetree/bindings/net/cavium-mdio.txt | 27 + .../devicetree/bindings/net/cavium-mix.txt | 40 ++ .../devicetree/bindings/net/cavium-pip.txt | 98 +++ .../devicetree/bindings/serial/cavium-uart.txt | 19 + arch/mips/Kconfig | 3 + arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 16 + arch/mips/cavium-octeon/octeon-irq.c | 395 +++++++++++-- arch/mips/cavium-octeon/octeon-platform.c | 523 ++++++++++++++++- arch/mips/cavium-octeon/octeon_3xxx.dts | 571 ++++++++++++++++++ arch/mips/cavium-octeon/octeon_68xx.dts | 625 ++++++++++++++++++++ arch/mips/cavium-octeon/setup.c | 45 ++ arch/mips/kernel/prom.c | 2 + 21 files changed, 2661 insertions(+), 64 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/cavium-compact-flash.txt create mode 100644 Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt create mode 100644 Documentation/devicetree/bindings/i2c/cavium-i2c.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/bootbus.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu2.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/dma-engine.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/uctl.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mdio.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mix.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-pip.txt create mode 100644 Documentation/devicetree/bindings/serial/cavium-uart.txt create mode 100644 arch/mips/cavium-octeon/.gitignore create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Mar 1 01:57:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Mar 2012 01:57:47 +0100 (CET) Received: from mail-yx0-f177.google.com ([209.85.213.177]:32809 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903793Ab2CAA5Q (ORCPT ); Thu, 1 Mar 2012 01:57:16 +0100 Received: by yenm10 with SMTP id m10so15172yen.36 for ; Wed, 29 Feb 2012 16:57:10 -0800 (PST) Received-SPF: pass (google.com: domain of ddaney.cavm@gmail.com designates 10.100.212.4 as permitted sender) client-ip=10.100.212.4; Authentication-Results: mr.google.com; spf=pass (google.com: domain of ddaney.cavm@gmail.com designates 10.100.212.4 as permitted sender) smtp.mail=ddaney.cavm@gmail.com; dkim=pass header.i=ddaney.cavm@gmail.com Received: from mr.google.com ([10.100.212.4]) by 10.100.212.4 with SMTP id k4mr1243418ang.35.1330563430517 (num_hops = 1); Wed, 29 Feb 2012 16:57:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=wAGQX8lcMO9izpgUahDOm4Axwj1rxFTJWe9QkEmdyNE=; b=ad/67eeit0xyZD5m78t/mbx6pAjVC0iBK4Tw5DE1gakM4J0FM7i7+3EVB1zRRq2g/E rmS6TDBIAxYpxE+2AgQA1CKnDeqJsEg998rQeMW0jtUdVCCfAC+dS6BK/nFZzjou4FkO GwYPW76IjXgTmL4P+EL/q8uBRf8CVWfzwMgnU= Received: by 10.100.212.4 with SMTP id k4mr976793ang.35.1330563430465; Wed, 29 Feb 2012 16:57:10 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id j22sm354117ann.0.2012.02.29.16.57.09 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 29 Feb 2012 16:57:09 -0800 (PST) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q210v8w3014123; Wed, 29 Feb 2012 16:57:08 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q210v8ol014122; Wed, 29 Feb 2012 16:57:08 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v6 2/5] MIPS: Don't define early_init_devtree() and device_tree_init() in prom.c for CPU_CAVIUM_OCTEON Date: Wed, 29 Feb 2012 16:56:59 -0800 Message-Id: <1330563422-14078-3-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 32586 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 921 Lines: 33 From: David Daney This code is not common enough to be in a shared file, so OCTEON defines it's own versions. When the last of this target specific code is moved out, we can remove all of this. Signed-off-by: David Daney --- arch/mips/kernel/prom.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 558b539..4aaa5c0 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -60,6 +60,7 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start, } #endif +#ifndef CONFIG_CPU_CAVIUM_OCTEON void __init early_init_devtree(void *params) { /* Setup flat device-tree pointer */ @@ -95,3 +96,4 @@ void __init device_tree_init(void) /* free the space reserved for the dt blob */ free_mem_mach(base, size); } +#endif /* !CONFIG_CPU_CAVIUM_OCTEON */ -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Mar 1 01:57:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Mar 2012 01:58:11 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:41104 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903794Ab2CAA5Q (ORCPT ); Thu, 1 Mar 2012 01:57:16 +0100 Received: by ghbf11 with SMTP id f11so16299ghb.36 for ; Wed, 29 Feb 2012 16:57:10 -0800 (PST) Received-SPF: pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.92.228 as permitted sender) client-ip=10.236.92.228; Authentication-Results: mr.google.com; spf=pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.92.228 as permitted sender) smtp.mail=ddaney.cavm@gmail.com; dkim=pass header.i=ddaney.cavm@gmail.com Received: from mr.google.com ([10.236.92.228]) by 10.236.92.228 with SMTP id j64mr4105233yhf.31.1330563430727 (num_hops = 1); Wed, 29 Feb 2012 16:57:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=8oA3MH0FCG4p3ml6PpgOLfRwU2MZmgDxS4VbiGiN5R8=; b=sK+ldApNPh8xk9lY3JkVfcnheQNprFseOFS+x3+WTf4fn+eUXfrFsOvoMFOxT+sH+t KLDBXAMdwNuUh6Drg9XALp4m9iLyl5WgyJ5AB5XsyF6Yy1d4LNThEGyW1LkqQhKuqev9 7CpNAjA5u6LXsfucc8WkohkTuNFX0dhGBeVWs= Received: by 10.236.92.228 with SMTP id j64mr3221386yhf.31.1330563430680; Wed, 29 Feb 2012 16:57:10 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id b73sm425196yhj.22.2012.02.29.16.57.09 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 29 Feb 2012 16:57:09 -0800 (PST) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q210v8iV014128; Wed, 29 Feb 2012 16:57:08 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q210v8Ci014126; Wed, 29 Feb 2012 16:57:08 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v6 3/5] MIPS: Octeon: Add irq handlers for GPIO interrupts. Date: Wed, 29 Feb 2012 16:57:00 -0800 Message-Id: <1330563422-14078-4-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 32587 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4892 Lines: 155 From: David Daney This is needed for follow-on on patches for Octeon to use the Device Tree to configure GPIO interrupts. Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 96 +++++++++++++++++++++++++++++++++- 1 files changed, 95 insertions(+), 1 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index ffd4ae6..bdcedd3 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -505,6 +505,72 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) } } +static void octeon_irq_gpio_setup(struct irq_data *data) +{ + union cvmx_gpio_bit_cfgx cfg; + int bit = data->irq - OCTEON_IRQ_GPIO0; + u32 t = irqd_get_trigger_type(data); + + cfg.u64 = 0; + cfg.s.int_en = 1; + cfg.s.int_type = (t & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) != 0; + cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0; + + /* 1 uS glitch filter*/ + cfg.s.fil_cnt = 7; + cfg.s.fil_sel = 3; + + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), cfg.u64); +} + +static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data) +{ + octeon_irq_gpio_setup(data); + octeon_irq_ciu_enable_v2(data); +} + +static void octeon_irq_ciu_enable_gpio(struct irq_data *data) +{ + octeon_irq_gpio_setup(data); + octeon_irq_ciu_enable(data); +} + +static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t) +{ + u32 current_type = irqd_get_trigger_type(data); + + /* If the type has been set, don't change it */ + if (current_type && current_type != t) + return -EINVAL; + + irqd_set_trigger_type(data, t); + return IRQ_SET_MASK_OK; +} + +static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data) +{ + int bit = data->irq - OCTEON_IRQ_GPIO0; + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0); + + octeon_irq_ciu_disable_all_v2(data); +} + +static void octeon_irq_ciu_disable_gpio(struct irq_data *data) +{ + int bit = data->irq - OCTEON_IRQ_GPIO0; + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0); + + octeon_irq_ciu_disable_all(data); +} + +static void octeon_irq_ciu_gpio_ack(struct irq_data *data) +{ + int bit = data->irq - OCTEON_IRQ_GPIO0; + u64 mask = 1ull << bit; + + cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); +} + #ifdef CONFIG_SMP static void octeon_irq_cpu_offline_ciu(struct irq_data *data) @@ -717,6 +783,31 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = { .flags = IRQCHIP_ONOFFLINE_ENABLED, }; +static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = { + .name = "CIU-GPIO", + .irq_enable = octeon_irq_ciu_enable_gpio_v2, + .irq_disable = octeon_irq_ciu_disable_gpio_v2, + .irq_ack = octeon_irq_ciu_gpio_ack, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_v2, + .irq_set_type = octeon_irq_ciu_gpio_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, +#endif +}; + +static struct irq_chip octeon_irq_chip_ciu_gpio = { + .name = "CIU-GPIO", + .irq_enable = octeon_irq_ciu_enable_gpio, + .irq_disable = octeon_irq_ciu_disable_gpio, + .irq_mask = octeon_irq_dummy_mask, + .irq_ack = octeon_irq_ciu_gpio_ack, + .irq_set_type = octeon_irq_ciu_gpio_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity, +#endif +}; + /* * Watchdog interrupts are special. They are associated with a single * core, so we hardwire the affinity to that core. @@ -890,6 +981,7 @@ static void __init octeon_irq_init_ciu(void) struct irq_chip *chip_edge; struct irq_chip *chip_mbox; struct irq_chip *chip_wd; + struct irq_chip *chip_gpio; octeon_irq_init_ciu_percpu(); octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; @@ -904,6 +996,7 @@ static void __init octeon_irq_init_ciu(void) chip_edge = &octeon_irq_chip_ciu_edge_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; + chip_gpio = &octeon_irq_chip_ciu_gpio_v2; } else { octeon_irq_ip2 = octeon_irq_ip2_v1; octeon_irq_ip3 = octeon_irq_ip3_v1; @@ -911,6 +1004,7 @@ static void __init octeon_irq_init_ciu(void) chip_edge = &octeon_irq_chip_ciu_edge; chip_mbox = &octeon_irq_chip_ciu_mbox; chip_wd = &octeon_irq_chip_ciu_wd; + chip_gpio = &octeon_irq_chip_ciu_gpio; } octeon_irq_ip4 = octeon_irq_ip4_mask; @@ -921,7 +1015,7 @@ static void __init octeon_irq_init_ciu(void) for (i = 0; i < 16; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Mar 1 01:57:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Mar 2012 01:58:36 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:41930 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903795Ab2CAA5R (ORCPT ); Thu, 1 Mar 2012 01:57:17 +0100 Received: by ggnf2 with SMTP id f2so16414ggn.36 for ; Wed, 29 Feb 2012 16:57:11 -0800 (PST) Received-SPF: pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.178.65 as permitted sender) client-ip=10.236.178.65; Authentication-Results: mr.google.com; spf=pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.178.65 as permitted sender) smtp.mail=ddaney.cavm@gmail.com; dkim=pass header.i=ddaney.cavm@gmail.com Received: from mr.google.com ([10.236.178.65]) by 10.236.178.65 with SMTP id e41mr3866023yhm.130.1330563431025 (num_hops = 1); Wed, 29 Feb 2012 16:57:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=lQxZpzwBnAGyJ0BcDtGBBWNINpXQMPoUW36rNL0OK6M=; b=MIHd2iOZe4npSRPvtYSLYMeHJBbYGwdJ8wWbvmM1AL7joYYlZYEiRsT4WolLsrIMKF p5+7/jVXvLLSTaOUo8eAsGoa5pGNJuqNixv9yZmv74Hz76O80q6IMgvKJ7khGzfulD/0 4LCFLAq25zpX6oqiKFj0rfSQTfGMwz0+kS4Kk= Received: by 10.236.178.65 with SMTP id e41mr3033176yhm.130.1330563430969; Wed, 29 Feb 2012 16:57:10 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id e45sm517793yhk.2.2012.02.29.16.57.09 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 29 Feb 2012 16:57:09 -0800 (PST) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q210v8Or014132; Wed, 29 Feb 2012 16:57:08 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q210v839014131; Wed, 29 Feb 2012 16:57:08 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. Date: Wed, 29 Feb 2012 16:57:01 -0800 Message-Id: <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 32588 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 15607 Lines: 402 From: David Daney Select IRQ_DOMAIN so the core irq_domain code and supply irq_create_of_mapping(). Signed-off-by: David Daney --- arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/octeon-irq.c | 301 +++++++++++++++++++++++++++------- 2 files changed, 239 insertions(+), 63 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ce30e2f..01344ae 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1432,6 +1432,7 @@ config CPU_CAVIUM_OCTEON select WEAK_ORDERING select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES + select IRQ_DOMAIN help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index bdcedd3..e9f2f6c 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -3,14 +3,16 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks + * Copyright (C) 2004-2008, 2009, 2010, 2011, 2012 Cavium Networks */ #include +#include #include #include #include #include +#include #include @@ -42,20 +44,27 @@ struct octeon_core_chip_data { static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; -static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, + unsigned int line, + unsigned int bit, + struct irq_domain *domain, struct irq_chip *chip, irq_flow_handler_t handler) { + struct irq_data *irqd; union octeon_ciu_chip_data cd; irq_set_chip_and_handler(irq, chip, handler); - cd.l = 0; cd.s.line = line; cd.s.bit = bit; irq_set_chip_data(irq, cd.p); octeon_irq_ciu_to_irq[line][bit] = irq; + + irqd = irq_get_irq_data(irq); + irqd->hwirq = line << 6 | bit; + irqd->domain = domain; } static int octeon_coreid_for_cpu(int cpu) @@ -855,6 +864,107 @@ static struct irq_chip octeon_irq_chip_ciu_wd = { .irq_mask = octeon_irq_dummy_mask, }; +static int octeon_irq_gpio_xlat(struct irq_domain *d, + struct device_node *node, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + unsigned int irq; + unsigned int type; + unsigned int ciu = 0, bit = 0; + unsigned int pin; + unsigned int trigger; + bool set_edge_handler = false; + + if (d->of_node != node) + return -EINVAL; + + if (intsize < 2) + return -EINVAL; + + pin = intspec[0]; + if (pin >= 16) + return -EINVAL; + + trigger = intspec[1]; + + switch (trigger) { + case 1: + type = IRQ_TYPE_EDGE_RISING; + set_edge_handler = true; + break; + case 2: + type = IRQ_TYPE_EDGE_FALLING; + set_edge_handler = true; + break; + case 4: + type = IRQ_TYPE_LEVEL_HIGH; + break; + case 8: + type = IRQ_TYPE_LEVEL_LOW; + break; + default: + pr_err("Error: (%s) Invalid irq trigger specification: %x\n", + node->name, + trigger); + type = IRQ_TYPE_LEVEL_LOW; + break; + } + *out_type = type; + *out_hwirq = ((unsigned long)d->host_data) + pin; + + ciu = *out_hwirq >> 6; + bit = *out_hwirq & 0x3f; + + irq = octeon_irq_ciu_to_irq[ciu][bit]; + + if (set_edge_handler) + __irq_set_handler(irq, handle_edge_irq, 0, NULL); + + return 0; +} + +static int octeon_irq_ciu_xlat(struct irq_domain *d, + struct device_node *node, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + unsigned int ciu, bit; + + ciu = intspec[0]; + bit = intspec[1]; + + if (ciu > 1 || bit > 63) + return -EINVAL; + + if (octeon_irq_ciu_to_irq[ciu][bit] == 0) + return -EINVAL; + + *out_hwirq = (ciu << 6) | bit; + *out_type = 0; + + return 0; +} +static int octeon_irq_dummy_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw) +{ + return 0; +} + +static struct irq_domain_ops octeon_irq_domain_ciu_ops = { + .map = octeon_irq_dummy_map, + .xlate = octeon_irq_ciu_xlat, +}; + +static struct irq_domain_ops octeon_irq_domain_gpio_ops = { + .map = octeon_irq_dummy_map, + .xlate = octeon_irq_gpio_xlat, +}; + static void octeon_irq_ip2_v1(void) { const unsigned long core_id = cvmx_get_core_num(); @@ -982,6 +1092,10 @@ static void __init octeon_irq_init_ciu(void) struct irq_chip *chip_mbox; struct irq_chip *chip_wd; struct irq_chip *chip_gpio; + struct device_node *gpio_node; + struct device_node *ciu_node; + struct irq_domain *gpio_domain; + struct irq_domain *ciu_domain; octeon_irq_init_ciu_percpu(); octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; @@ -1011,83 +1125,144 @@ static void __init octeon_irq_init_ciu(void) /* Mips internal */ octeon_irq_init_core(); + gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); + ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); + /* gpio domain host_data is the base hwirq number. */ + gpio_domain = irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, (void *)16); + ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); + /* CIU_0 */ for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, + ciu_domain, chip, handle_level_irq); + for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, + gpio_domain, chip_gpio, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, + ciu_domain, chip_mbox, handle_percpu_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, + ciu_domain, chip_mbox, handle_percpu_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, + ciu_domain, chip, handle_level_irq); for (i = 0; i < 4; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, + ciu_domain, chip, handle_level_irq); for (i = 0; i < 4; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, + ciu_domain, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, + ciu_domain, chip, handle_level_irq); for (i = 0; i < 2; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, + ciu_domain, chip_edge, handle_edge_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, + ciu_domain, chip_edge, handle_edge_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, + ciu_domain, chip_edge, handle_edge_irq); for (i = 0; i < 4; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, + ciu_domain, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, + ciu_domain, chip, handle_level_irq); /* CIU_1 */ for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq); - - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, + ciu_domain, chip_wd, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, + ciu_domain, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, + ciu_domain, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, + ciu_domain, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, + ciu_domain, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, + ciu_domain, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, + ciu_domain, chip, handle_level_irq); /* Enable the CIU lines */ set_c0_status(STATUSF_IP3 | STATUSF_IP2); -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Mar 1 01:57:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Mar 2012 01:59:01 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:53457 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903796Ab2CAA5R (ORCPT ); Thu, 1 Mar 2012 01:57:17 +0100 Received: by ghbf11 with SMTP id f11so16303ghb.36 for ; Wed, 29 Feb 2012 16:57:11 -0800 (PST) Received-SPF: pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.155.226 as permitted sender) client-ip=10.236.155.226; Authentication-Results: mr.google.com; spf=pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.155.226 as permitted sender) smtp.mail=ddaney.cavm@gmail.com; dkim=pass header.i=ddaney.cavm@gmail.com Received: from mr.google.com ([10.236.155.226]) by 10.236.155.226 with SMTP id j62mr3971934yhk.49.1330563431253 (num_hops = 1); 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[64.2.3.195]) by mx.google.com with ESMTPS id o68sm456387yhk.16.2012.02.29.16.57.09 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 29 Feb 2012 16:57:09 -0800 (PST) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q210v8Eo014136; Wed, 29 Feb 2012 16:57:08 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q210v8E5014135; Wed, 29 Feb 2012 16:57:08 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v6 5/5] MIPS: Octeon: Initialize and fixup device tree. Date: Wed, 29 Feb 2012 16:57:02 -0800 Message-Id: <1330563422-14078-6-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 32589 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 19223 Lines: 652 From: David Daney Signed-off-by: David Daney --- arch/mips/Kconfig | 2 + arch/mips/cavium-octeon/Makefile | 3 + arch/mips/cavium-octeon/octeon-platform.c | 523 ++++++++++++++++++++++++++++- arch/mips/cavium-octeon/setup.c | 45 +++ 4 files changed, 572 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 01344ae..f694bdd 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1433,6 +1433,8 @@ config CPU_CAVIUM_OCTEON select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES select IRQ_DOMAIN + select USE_OF + select LIBFDT help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 1e37522..bc96e29 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -9,6 +9,9 @@ # Copyright (C) 2005-2009 Cavium Networks # +CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt +CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt + obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o obj-y += dma-octeon.o flash_setup.o obj-y += octeon-memcpy.o diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index cd61d72..2754bc2 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004-2010 Cavium Networks + * Copyright (C) 2004-2011 Cavium Networks * Copyright (C) 2008 Wind River Systems */ @@ -13,10 +13,16 @@ #include #include #include +#include #include +#include +#include +#include #include #include +#include +#include static struct octeon_cf_data octeon_cf_data; @@ -440,6 +446,521 @@ device_initcall(octeon_ohci_device_init); #endif /* CONFIG_USB */ +static struct of_device_id __initdata octeon_ids[] = { + { .compatible = "simple-bus", }, + { .compatible = "cavium,octeon-6335-uctl", }, + { .compatible = "cavium,octeon-3860-bootbus", }, + { .compatible = "cavium,mdio-mux", }, + { .compatible = "gpio-leds", }, + {}, +}; + +static bool __init octeon_has_88e1145(void) +{ + return !OCTEON_IS_MODEL(OCTEON_CN52XX) && + !OCTEON_IS_MODEL(OCTEON_CN6XXX) && + !OCTEON_IS_MODEL(OCTEON_CN56XX); +} + +static void __init octeon_fdt_set_phy(int eth, int phy_addr) +{ + const __be32 *phy_handle; + const __be32 *alt_phy_handle; + const __be32 *reg; + u32 phandle; + int phy; + int alt_phy; + const char *p; + int current_len; + char new_name[20]; + + phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); + if (!phy_handle) + return; + + phandle = be32_to_cpup(phy_handle); + phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); + + alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); + if (alt_phy_handle) { + u32 alt_phandle = be32_to_cpup(alt_phy_handle); + alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); + } else { + alt_phy = -1; + } + + if (phy_addr < 0 || phy < 0) { + /* Delete the PHY things */ + fdt_nop_property(initial_boot_params, eth, "phy-handle"); + /* This one may fail */ + fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle"); + if (phy >= 0) + fdt_nop_node(initial_boot_params, phy); + if (alt_phy >= 0) + fdt_nop_node(initial_boot_params, alt_phy); + return; + } + + if (phy_addr >= 256 && alt_phy > 0) { + const struct fdt_property *phy_prop; + struct fdt_property *alt_prop; + u32 phy_handle_name; + + /* Use the alt phy node instead.*/ + phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL); + phy_handle_name = phy_prop->nameoff; + fdt_nop_node(initial_boot_params, phy); + fdt_nop_property(initial_boot_params, eth, "phy-handle"); + alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); + alt_prop->nameoff = phy_handle_name; + phy = alt_phy; + } + + phy_addr &= 0xff; + + if (octeon_has_88e1145()) { + fdt_nop_property(initial_boot_params, phy, "marvell,reg-init"); + memset(new_name, 0, sizeof(new_name)); + strcpy(new_name, "marvell,88e1145"); + p = fdt_getprop(initial_boot_params, phy, "compatible", + ¤t_len); + if (p && current_len >= strlen(new_name)) + fdt_setprop_inplace(initial_boot_params, phy, + "compatible", new_name, current_len); + } + + reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); + if (phy_addr == be32_to_cpup(reg)) + return; + + fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); + + snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr); + + p = fdt_get_name(initial_boot_params, phy, ¤t_len); + if (p && current_len == strlen(new_name)) + fdt_set_name(initial_boot_params, phy, new_name); + else + pr_err("Error: could not rename ethernet phy: <%s>", p); +} + +static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) +{ + u8 new_mac[6]; + u64 mac = *pmac; + int r; + + new_mac[0] = (mac >> 40) & 0xff; + new_mac[1] = (mac >> 32) & 0xff; + new_mac[2] = (mac >> 24) & 0xff; + new_mac[3] = (mac >> 16) & 0xff; + new_mac[4] = (mac >> 8) & 0xff; + new_mac[5] = mac & 0xff; + + r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", + new_mac, sizeof(new_mac)); + + if (r) { + pr_err("Setting \"local-mac-address\" failed %d", r); + return; + } + *pmac = mac + 1; +} + +static void __init octeon_fdt_rm_ethernet(int node) +{ + const __be32 *phy_handle; + + phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); + if (phy_handle) { + u32 ph = be32_to_cpup(phy_handle); + int p = fdt_node_offset_by_phandle(initial_boot_params, ph); + if (p >= 0) + fdt_nop_node(initial_boot_params, p); + } + fdt_nop_node(initial_boot_params, node); +} + +static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac) +{ + char name_buffer[20]; + int eth; + int phy_addr; + int ipd_port; + + snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); + eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); + if (eth < 0) + return; + if (p > max) { + pr_debug("Deleting port %x:%x\n", i, p); + octeon_fdt_rm_ethernet(eth); + return; + } + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + ipd_port = (0x100 * i) + (0x10 * p) + 0x800; + else + ipd_port = 16 * i + p; + + phy_addr = cvmx_helper_board_get_mii_address(ipd_port); + octeon_fdt_set_phy(eth, phy_addr); + octeon_fdt_set_mac_addr(eth, pmac); +} + +static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) +{ + char name_buffer[20]; + int iface; + int p; + int count; + + count = cvmx_helper_interface_enumerate(idx); + + snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); + iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); + if (iface < 0) + return; + + for (p = 0; p < 16; p++) + octeon_fdt_pip_port(iface, idx, p, count - 1, pmac); +} + +int __init octeon_prune_device_tree(void) +{ + int i, max_port, uart_mask; + const char *pip_path; + const char *alias_prop; + char name_buffer[20]; + int aliases; + u64 mac_addr_base; + + if (fdt_check_header(initial_boot_params)) + panic("Corrupt Device Tree."); + + aliases = fdt_path_offset(initial_boot_params, "/aliases"); + if (aliases < 0) { + pr_err("Error: No /aliases node in device tree."); + return -EINVAL; + } + + + mac_addr_base = + ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | + ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | + ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | + ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | + ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | + (octeon_bootinfo->mac_addr_base[5] & 0xffull); + + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) + max_port = 2; + else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) + max_port = 1; + else + max_port = 0; + + if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) + max_port = 0; + + for (i = 0; i < 2; i++) { + int mgmt; + snprintf(name_buffer, sizeof(name_buffer), + "mix%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + if (alias_prop) { + mgmt = fdt_path_offset(initial_boot_params, alias_prop); + if (mgmt < 0) + continue; + if (i >= max_port) { + pr_debug("Deleting mix%d\n", i); + octeon_fdt_rm_ethernet(mgmt); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } else { + int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); + octeon_fdt_set_phy(mgmt, phy_addr); + octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); + } + } + } + + pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); + if (pip_path) { + int pip = fdt_path_offset(initial_boot_params, pip_path); + if (pip >= 0) + for (i = 0; i <= 4; i++) + octeon_fdt_pip_iface(pip, i, &mac_addr_base); + } + + /* I2C */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN68XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 2; + else + max_port = 1; + + for (i = 0; i < 2; i++) { + int i2c; + snprintf(name_buffer, sizeof(name_buffer), + "twsi%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + i2c = fdt_path_offset(initial_boot_params, alias_prop); + if (i2c < 0) + continue; + if (i >= max_port) { + pr_debug("Deleting twsi%d\n", i); + fdt_nop_node(initial_boot_params, i2c); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + } + + /* SMI/MDIO */ + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + max_port = 4; + else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 2; + else + max_port = 1; + + for (i = 0; i < 2; i++) { + int i2c; + snprintf(name_buffer, sizeof(name_buffer), + "smi%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + i2c = fdt_path_offset(initial_boot_params, alias_prop); + if (i2c < 0) + continue; + if (i >= max_port) { + pr_debug("Deleting smi%d\n", i); + fdt_nop_node(initial_boot_params, i2c); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + } + + /* Serial */ + uart_mask = 3; + + /* Right now CN52XX is the only chip with a third uart */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) + uart_mask |= 4; /* uart2 */ + + for (i = 0; i < 3; i++) { + int uart; + snprintf(name_buffer, sizeof(name_buffer), + "uart%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + uart = fdt_path_offset(initial_boot_params, alias_prop); + if (uart_mask & (1 << i)) + continue; + pr_debug("Deleting uart%d\n", i); + fdt_nop_node(initial_boot_params, uart); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + + /* Compact Flash */ + alias_prop = fdt_getprop(initial_boot_params, aliases, + "cf0", NULL); + if (alias_prop) { + union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; + unsigned long base_ptr, region_base, region_size; + unsigned long region1_base = 0; + unsigned long region1_size = 0; + int cs, bootbus; + bool is_16bit = false; + bool is_true_ide = false; + __be32 new_reg[6]; + __be32 *ranges; + int len; + + int cf = fdt_path_offset(initial_boot_params, alias_prop); + base_ptr = 0; + if (octeon_bootinfo->major_version == 1 + && octeon_bootinfo->minor_version >= 1) { + if (octeon_bootinfo->compact_flash_common_base_addr) + base_ptr = octeon_bootinfo->compact_flash_common_base_addr; + } else { + base_ptr = 0x1d000800; + } + + if (!base_ptr) + goto no_cf; + + /* Find CS0 region. */ + for (cs = 0; cs < 8; cs++) { + mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); + region_base = mio_boot_reg_cfg.s.base << 16; + region_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (mio_boot_reg_cfg.s.en && base_ptr >= region_base + && base_ptr < region_base + region_size) { + is_16bit = mio_boot_reg_cfg.s.width; + break; + } + } + if (cs >= 7) { + /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ + goto no_cf; + } + + if (!(base_ptr & 0xfffful)) { + /* + * Boot loader signals availability of DMA (true_ide + * mode) by setting low order bits of base_ptr to + * zero. + */ + + /* Asume that CS1 immediately follows. */ + mio_boot_reg_cfg.u64 = + cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); + region1_base = mio_boot_reg_cfg.s.base << 16; + region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (!mio_boot_reg_cfg.s.en) + goto no_cf; + is_true_ide = true; + + } else { + fdt_nop_property(initial_boot_params, cf, "cavium,true-ide"); + fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); + if (!is_16bit) { + __be32 width = cpu_to_be32(8); + fdt_setprop_inplace(initial_boot_params, cf, + "cavium,bus-width", &width, sizeof(width)); + } + } + new_reg[0] = cpu_to_be32(cs); + new_reg[1] = cpu_to_be32(0); + new_reg[2] = cpu_to_be32(0x10000); + new_reg[3] = cpu_to_be32(cs + 1); + new_reg[4] = cpu_to_be32(0); + new_reg[5] = cpu_to_be32(0x10000); + fdt_setprop_inplace(initial_boot_params, cf, + "reg", new_reg, sizeof(new_reg)); + + bootbus = fdt_parent_offset(initial_boot_params, cf); + if (bootbus < 0) + goto no_cf; + ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); + if (!ranges || len < (5 * 8 * sizeof(__be32))) + goto no_cf; + + ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); + ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); + ranges[(cs * 5) + 4] = cpu_to_be32(region_size); + if (is_true_ide) { + cs++; + ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); + ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); + ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); + } + goto end_cf; +no_cf: + fdt_nop_node(initial_boot_params, cf); + +end_cf: + ; + } + + /* 8 char LED */ + alias_prop = fdt_getprop(initial_boot_params, aliases, + "led0", NULL); + if (alias_prop) { + union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; + unsigned long base_ptr, region_base, region_size; + int cs, bootbus; + __be32 new_reg[6]; + __be32 *ranges; + int len; + int led = fdt_path_offset(initial_boot_params, alias_prop); + + base_ptr = octeon_bootinfo->led_display_base_addr; + if (base_ptr == 0) + goto no_led; + /* Find CS0 region. */ + for (cs = 0; cs < 8; cs++) { + mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); + region_base = mio_boot_reg_cfg.s.base << 16; + region_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (mio_boot_reg_cfg.s.en && base_ptr >= region_base + && base_ptr < region_base + region_size) + break; + } + + if (cs > 7) + goto no_led; + + new_reg[0] = cpu_to_be32(cs); + new_reg[1] = cpu_to_be32(0x20); + new_reg[2] = cpu_to_be32(0x20); + new_reg[3] = cpu_to_be32(cs); + new_reg[4] = cpu_to_be32(0); + new_reg[5] = cpu_to_be32(0x20); + fdt_setprop_inplace(initial_boot_params, led, + "reg", new_reg, sizeof(new_reg)); + + bootbus = fdt_parent_offset(initial_boot_params, led); + if (bootbus < 0) + goto no_led; + ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); + if (!ranges || len < (5 * 8 * sizeof(__be32))) + goto no_led; + + ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); + ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); + ranges[(cs * 5) + 4] = cpu_to_be32(region_size); + goto end_led; + +no_led: + fdt_nop_node(initial_boot_params, led); +end_led: + ; + } + + /* OHCI/UHCI USB */ + alias_prop = fdt_getprop(initial_boot_params, aliases, + "uctl", NULL); + if (alias_prop) { + int uctl = fdt_path_offset(initial_boot_params, alias_prop); + + if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || + octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { + pr_debug("Deleting uctl\n"); + fdt_nop_node(initial_boot_params, uctl); + fdt_nop_property(initial_boot_params, aliases, "uctl"); + } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || + octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { + /* Missing "refclk-type" defaults to crystal. */ + fdt_nop_property(initial_boot_params, uctl, "refclk-type"); + } + } + + return 0; +} + +static int __init octeon_publish_devices(void) +{ + return of_platform_bus_probe(NULL, octeon_ids, NULL); +} +device_initcall(octeon_publish_devices); + MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Platform driver for Octeon SOC"); diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 260b273..03e8be0 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include @@ -775,3 +777,46 @@ void prom_free_prom_memory(void) } #endif } + +int octeon_prune_device_tree(void); + +extern const char __dtb_octeon_3xxx_begin; +extern const char __dtb_octeon_3xxx_end; +extern const char __dtb_octeon_68xx_begin; +extern const char __dtb_octeon_68xx_end; +void __init device_tree_init(void) +{ + int dt_size; + struct boot_param_header *fdt; + bool do_prune; + + if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { + fdt = phys_to_virt(octeon_bootinfo->fdt_addr); + if (fdt_check_header(fdt)) + panic("Corrupt Device Tree passed to kernel."); + dt_size = be32_to_cpu(fdt->totalsize); + do_prune = false; + } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { + fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin; + dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin; + do_prune = true; + } else { + fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin; + dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; + do_prune = true; + } + + /* Copy the default tree from init memory. */ + initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); + if (initial_boot_params == NULL) + panic("Could not allocate initial_boot_params\n"); + memcpy(initial_boot_params, fdt, dt_size); + + if (do_prune) { + octeon_prune_device_tree(); + pr_info("Using internal Device Tree.\n"); + } else { + pr_info("Using passed Device Tree.\n"); + } + unflatten_device_tree(); +} -- 1.7.2.3 From ddaney.cavm@gmail.com Thu Mar 1 01:57:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Mar 2012 01:59:29 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:51822 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903797Ab2CAA5R (ORCPT ); Thu, 1 Mar 2012 01:57:17 +0100 Received: by yhjj52 with SMTP id j52so15878yhj.36 for ; Wed, 29 Feb 2012 16:57:11 -0800 (PST) Received-SPF: pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.184.8 as permitted sender) client-ip=10.236.184.8; Authentication-Results: mr.google.com; spf=pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.184.8 as permitted sender) smtp.mail=ddaney.cavm@gmail.com; dkim=pass header.i=ddaney.cavm@gmail.com Received: from mr.google.com ([10.236.184.8]) by 10.236.184.8 with SMTP id r8mr3908566yhm.110.1330563431555 (num_hops = 1); Wed, 29 Feb 2012 16:57:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=NGPBw1MGWLG7RxItUxm9ALgL5VfJlJFIoNN+YUg7Axc=; b=Y/w1Ie+6uYWVXX9AT4cH0ZFe24zehDJe3lWr8NAs/V4+kxDPIWJymAlPxhpMODVUeK GDqmaOeu0NWxjuoowd04x1Sc/AiqhYJTQ1+5JwGWqUMCdezPe7jtoSvKYEdZVU+GfWlQ yiLTrWDsHz/T4lvCzT01b57EAOeWRBwlMiQcg= Received: by 10.236.184.8 with SMTP id r8mr3064900yhm.110.1330563431464; Wed, 29 Feb 2012 16:57:11 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id n24sm465469yhj.13.2012.02.29.16.57.09 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 29 Feb 2012 16:57:09 -0800 (PST) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q210v7Nd014119; Wed, 29 Feb 2012 16:57:07 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q210v7Yf014118; Wed, 29 Feb 2012 16:57:07 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v6 1/5] MIPS: Octeon: Add device tree source files. Date: Wed, 29 Feb 2012 16:56:58 -0800 Message-Id: <1330563422-14078-2-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> X-archive-position: 32590 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 55609 Lines: 1904 From: David Daney The two device tree files octeon_3xxx.dts and octeon_68xx.dts are trimmed by code in a subsequent patch to reflect the hardware actually present on the board. To this end several properties that are not part of the declared bindings are added to aid in trimming off unwanted nodes. Since the device tree and the code that trims it are bound into the kernel binary, these 'marker' properties never escape into the wild, and are purely an implementation detail of the kernel early boot process. This is done for backwards compatibility with existing boards (identified by a board type enumeration value by their bootloaders). New boards will always pass a device tree from the bootloader, the built-in trees are ignored in this case. Signed-off-by: David Daney --- .../bindings/ata/cavium-compact-flash.txt | 30 + .../bindings/gpio/cavium-octeon-gpio.txt | 48 ++ .../devicetree/bindings/i2c/cavium-i2c.txt | 34 ++ .../devicetree/bindings/mips/cavium/bootbus.txt | 126 ++++ .../devicetree/bindings/mips/cavium/ciu.txt | 26 + .../devicetree/bindings/mips/cavium/ciu2.txt | 27 + .../devicetree/bindings/mips/cavium/dma-engine.txt | 21 + .../devicetree/bindings/mips/cavium/uctl.txt | 47 ++ .../devicetree/bindings/net/cavium-mdio.txt | 27 + .../devicetree/bindings/net/cavium-mix.txt | 40 ++ .../devicetree/bindings/net/cavium-pip.txt | 98 +++ .../devicetree/bindings/serial/cavium-uart.txt | 19 + arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 13 + arch/mips/cavium-octeon/octeon_3xxx.dts | 571 ++++++++++++++++++ arch/mips/cavium-octeon/octeon_68xx.dts | 625 ++++++++++++++++++++ 16 files changed, 1754 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/cavium-compact-flash.txt create mode 100644 Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt create mode 100644 Documentation/devicetree/bindings/i2c/cavium-i2c.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/bootbus.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu2.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/dma-engine.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/uctl.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mdio.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mix.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-pip.txt create mode 100644 Documentation/devicetree/bindings/serial/cavium-uart.txt create mode 100644 arch/mips/cavium-octeon/.gitignore create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt new file mode 100644 index 0000000..93986a5 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt @@ -0,0 +1,30 @@ +* Compact Flash + +The Cavium Compact Flash device is connected to the Octeon Boot Bus, +and is thus a child of the Boot Bus device. It can read and write +industry standard compact flash devices. + +Properties: +- compatible: "cavium,ebt3000-compact-flash"; + + Compatibility with many Cavium evaluation boards. + +- reg: The base address of the the CF chip select banks. Depending on + the device configuration, there may be one or two banks. + +- cavium,bus-width: The width of the connection to the CF devices. Valid + values are 8 and 16. + +- cavium,true-ide: Optional, if present the CF connection is in True IDE mode. + +- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected + to this device. + +Example: + compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt new file mode 100644 index 0000000..21b989a --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt @@ -0,0 +1,48 @@ +* General Purpose Input Output (GPIO) bus. + +Properties: +- compatible: "cavium,octeon-3860-gpio" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the GPIO unit's register bank. + +- gpio-controller: This is a GPIO controller. + +- #gpio-cells: Must be <2>. The first cell is the GPIO pin. + +- interrupt-controller: The GPIO controller is also an interrupt + controller, any of its pins may be configured as an interrupt + source. + +- #interrupt-cells: Must be <2>. The first cell is the GPIO pin + connected to the interrupt source. The second cell is the interrupt + triggering protocol and may have one of four values: + 1 - edge triggered on the rising edge. + 2 - edge triggered on the falling edge + 4 - level triggered active high. + 8 - level triggered active low. + +- interrupts: Interrupt routing for pin 0. The remaining pins are + also routed, but in a manner that can be derived from the pin0 + routing, so they are not specified. + +Example: + + gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>; + }; diff --git a/Documentation/devicetree/bindings/i2c/cavium-i2c.txt b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt new file mode 100644 index 0000000..dced82e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt @@ -0,0 +1,34 @@ +* Two Wire Serial Interface (TWSI) / I2C + +- compatible: "cavium,octeon-3860-twsi" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the TWSI/I2C bus controller register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. I2C addresses have no size component. + +- interrupts: A single interrupt specifier. + +- clock-frequency: The I2C bus clock rate in Hz. + +Example: + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt new file mode 100644 index 0000000..6581478 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt @@ -0,0 +1,126 @@ +* Boot Bus + +The Octeon Boot Bus is a configurable parallel bus with 8 chip +selects. Each chip select is independently configurable. + +Properties: +- compatible: "cavium,octeon-3860-bootbus" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the Boot Bus' register bank. + +- #address-cells: Must be <2>. The first cell is the chip select + within the bootbus. The second cell is the offset from the chip select. + +- #size-cells: Must be <1>. + +- ranges: There must be one one triplet of (child-bus-address, + parent-bus-address, length) for each active chip select. If the + length element for any triplet is zero, the chip select is disabled, + making it inactive. + +The configuration parameters for each chip select are stored in child +nodes. + +Configuration Properties: +- compatible: "cavium,octeon-3860-bootbus-config" + +- cavium,cs-index: A single cell indicating the chip select that + corresponds to this configuration. + +- cavium,t-adr: A cell specifying the ADR timing (in nS). + +- cavium,t-ce: A cell specifying the CE timing (in nS). + +- cavium,t-oe: A cell specifying the OE timing (in nS). + +- cavium,t-we: A cell specifying the WE timing (in nS). + +- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). + +- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). + +- cavium,t-pause: A cell specifying the PAUSE timing (in nS). + +- cavium,t-wait: A cell specifying the WAIT timing (in nS). + +- cavium,t-page: A cell specifying the PAGE timing (in nS). + +- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS). + +- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1 + = 2 bytes, 2 = 4 bytes, 3 = 8 bytes). + +- cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected. + +- cavium,page-mode: Optional. If present, page mode (PAGEM) is selected. + +- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of + the bus for this chip select. + +- cavium,ale-mode: Optional. If present, ALE mode is selected. + +- cavium,sam-mode: Optional. If present, SAM mode is selected. + +- cavium,or-mode: Optional. If present, OR mode is selected. + +Example: + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0x0 0x1d020000 0x10000>, + <5 0 0x0 0x1d040000 0x10000>, + <6 0 0x0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <20>; + cavium,t-ce = <60>; + cavium,t-oe = <60>; + cavium,t-we = <45>; + cavium,t-rd-hld = <35>; + cavium,t-wr-hld = <45>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <35>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + . + . + . + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <270>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <70>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + . + . + . + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt new file mode 100644 index 0000000..2c2d074 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu.txt @@ -0,0 +1,26 @@ +* Central Interrupt Unit + +Properties: +- compatible: "cavium,octeon-3860-ciu" + + Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is the bank within + the CIU and may have a value of 0 or 1. The second cell is the bit + within the bank and may have a value between 0 and 63. + +Example: + interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt new file mode 100644 index 0000000..0ec7ba8 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt @@ -0,0 +1,27 @@ +* Central Interrupt Unit + +Properties: +- compatible: "cavium,octeon-6880-ciu2" + + Compatibility with 68XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is the bank within + the CIU and may have a value between 0 and 63. The second cell is + the bit within the bank and may also have a value between 0 and 63. + +Example: + interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0..63) + * 2) Bit within the register (0..63) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt new file mode 100644 index 0000000..cb4291e --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt @@ -0,0 +1,21 @@ +* DMA Engine. + +The Octeon DMA Engine transfers between the Boot Bus and main memory. +The DMA Engine will be refered to by phandle by any device that is +connected to it. + +Properties: +- compatible: "cavium,octeon-5750-bootbus-dma" + + Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. + +- reg: The base address of the DMA Engine's register bank. + +- interrupts: A single interrupt specifier. + +Example: + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt new file mode 100644 index 0000000..5dabe02 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/uctl.txt @@ -0,0 +1,47 @@ +* UCTL USB controller glue + +Properties: +- compatible: "cavium,octeon-6335-uctl" + + Compatibility with all cn6XXX SOCs. + +- reg: The base address of the UCTL register bank. + +- #address-cells: Must be <2>. + +- #size-cells: Must be <2>. + +- ranges: Empty to signify direct mapping of the children. + +- refclk-frequency: A single cell containing the reference clock + frequency in Hz. + +- refclk-type: A string describing the reference clock connection + either "crystal" or "external". + +Example: + uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <24000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + }; + diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt new file mode 100644 index 0000000..04cb749 --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-mdio.txt @@ -0,0 +1,27 @@ +* System Management Interface (SMI) / MDIO + +Properties: +- compatible: "cavium,octeon-3860-mdio" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the MDIO bus controller register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. MDIO addresses have no size component. + +Typically an MDIO bus might have several children. + +Example: + mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + ethernet-phy@0 { + ... + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt new file mode 100644 index 0000000..e4f9d3c --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-mix.txt @@ -0,0 +1,40 @@ +* MIX Ethernet controller. + +Properties: +- compatible: "cavium,octeon-5750-mix" + + Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX + devices. + +- reg: The base addresses of four separate register banks. The first + bank contains the MIX registers. The second bank the corresponding + AGL registers. The third bank are the AGL registers shared by all + MIX devices present. The fourth bank is the AGL_PRT_CTL shared by + all MIX devices present. + +- cell-index: A single cell specifying which portion of the shared + register banks corresponds to this MIX device. + +- interrupts: Two interrupt specifiers. The first is the MIX + interrupt routing and the second the routing for the AGL interrupts. + +- mac-address: Optional, the MAC address to assign to the device. + +- local-mac-address: Optional, the MAC address to assign to the device + if mac-address is not specified. + +- phy-handle: Optional, a phandle for the PHY device connected to this device. + +Example: + ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 0f b7 10 63 54 ]; + phy-handle = <&phy1>; + }; + diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt new file mode 100644 index 0000000..d4c53ba --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-pip.txt @@ -0,0 +1,98 @@ +* PIP Ethernet nexus. + +The PIP Ethernet nexus can control several data packet input/output +devices. The devices have a two level grouping scheme. There may be +several interfaces, and each interface may have several ports. These +ports might be an individual Ethernet PHY. + + +Properties for the PIP nexus: +- compatible: "cavium,octeon-3860-pip" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the PIP's register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. + +Properties for PIP interfaces which is a child the PIP nexus: +- compatible: "cavium,octeon-3860-pip-interface" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The interface number. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. + +Properties for PIP port which is a child the PIP interface: +- compatible: "cavium,octeon-3860-pip-port" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The port number within the interface group. + +- mac-address: Optional, the MAC address to assign to the device. + +- local-mac-address: Optional, the MAC address to assign to the device + if mac-address is not specified. + +- phy-handle: Optional, a phandle for the PHY device connected to this device. + +Example: + + pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 60 ]; + phy-handle = <&phy2>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 61 ]; + phy-handle = <&phy3>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 62 ]; + phy-handle = <&phy4>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 63 ]; + phy-handle = <&phy5>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 64 ]; + phy-handle = <&phy6>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/serial/cavium-uart.txt b/Documentation/devicetree/bindings/serial/cavium-uart.txt new file mode 100644 index 0000000..87a6c37 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cavium-uart.txt @@ -0,0 +1,19 @@ +* Universal Asynchronous Receiver/Transmitter (UART) + +- compatible: "cavium,octeon-3860-uart" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the UART register bank. + +- interrupts: A single interrupt specifier. + +- current-speed: Optional, the current bit rate in bits per second. + +Example: + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + current-speed = <115200>; + interrupts = <0 35>; + }; diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore new file mode 100644 index 0000000..39c9686 --- /dev/null +++ b/arch/mips/cavium-octeon/.gitignore @@ -0,0 +1,2 @@ +*.dtb.S +*.dtb diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 19eb043..1e37522 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -15,3 +15,16 @@ obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o + +DTS_FILES = octeon_3xxx.dts octeon_68xx.dts +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) + +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) + +$(obj)/%.dtb: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) + +# Let's keep the .dtb files around in case we want to look at them. +.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES)) + +clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES)) diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts new file mode 100644 index 0000000..e0fb0e3 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_3xxx.dts @@ -0,0 +1,571 @@ +/dts-v1/; +/* + * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + compatible = "cavium,octeon-3860"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu: interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>; /* <0 17> <0 18> <0 19> + <0 20> <0 21> <0 22> <0 23> + <0 24> <0 25> <0 26> <0 27> + <0 28> <0 29> <0 30> <0 31>; */ + }; + + smi0: mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + phy0: ethernet-phy@0 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + + phy6: ethernet-phy@6 { + reg = <6>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000001900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001900 0x0 0x40>; + + phy100: ethernet-phy@1 { + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy101: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy102: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy103: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupts = <0 62>, <1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + mix1: ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + cavium,alt-phy-handle = <&phy100>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + cavium,alt-phy-handle = <&phy101>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + cavium,alt-phy-handle = <&phy102>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy5>; + cavium,alt-phy-handle = <&phy103>; + }; + ethernet@4 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x4>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@5 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x5>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@6 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x6>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@7 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x7>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@8 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x8>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@9 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x9>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@a { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xa>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@b { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xb>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@c { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xc>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@d { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xd>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@e { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xe>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@f { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xf>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy6>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy7>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy8>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy9>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupts = <0 59>; + clock-frequency = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 34>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 35>; + }; + + uart2: serial@1180000000400 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000400 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <1 16>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0x0 0x1d020000 0x10000>, + <5 0 0x0 0x1d040000 0x10000>, + <6 0 0x0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <20>; + cavium,t-ce = <60>; + cavium,t-oe = <60>; + cavium,t-we = <45>; + cavium,t-rd-hld = <35>; + cavium,t-wr-hld = <45>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <35>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <320>; + cavium,t-ce = <320>; + cavium,t-oe = <320>; + cavium,t-we = <320>; + cavium,t-rd-hld = <320>; + cavium,t-wr-hld = <320>; + cavium,t-pause = <320>; + cavium,t-wait = <320>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@5 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <5>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <30>; + cavium,t-pause = <0>; + cavium,t-wait = <30>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <16>; + }; + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <270>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <70>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + led0: led-display@4,0 { + compatible = "avago,hdsp-253x"; + reg = <4 0x20 0x20>, <4 0 0x20>; + }; + + cf0: compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; + }; + + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; + dma1: dma-engine@1180000000108 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000108 0x0 0x8>; + interrupts = <0 63>; + }; + + uctl: uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <12000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + }; + }; + + aliases { + mix0 = &mix0; + mix1 = &mix1; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + twsi0 = &twsi0; + twsi1 = &twsi1; + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + flash0 = &flash0; + cf0 = &cf0; + uctl = &uctl; + led0 = &led0; + }; + }; diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts new file mode 100644 index 0000000..bde6b23 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_68xx.dts @@ -0,0 +1,625 @@ +/dts-v1/; +/* + * OCTEON 68XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + compatible = "cavium,octeon-6880"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu2>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu2: interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 7) + * 2) Bit within the register (0..63) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pins connect to 16 consecutive CUI bits */ + interrupts = <7 0>; /* <7 1> <7 2> <7 3> + <7 4> <7 5> <7 6> <7 7> + <7 8> <7 9> <7 10> <7 11> + <7 12> <7 13> <7 14> <7 15>; */ + }; + + smi0: mdio@1180000003800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003800 0x0 0x40>; + + phy0: ethernet-phy@6 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <6>; + }; + + phy1: ethernet-phy@1 { + cavium,qlm-trim = "4,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy2: ethernet-phy@2 { + cavium,qlm-trim = "4,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + cavium,qlm-trim = "4,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + cavium,qlm-trim = "4,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000003880 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003880 0x0 0x40>; + + phy41: ethernet-phy@1 { + cavium,qlm-trim = "0,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy42: ethernet-phy@2 { + cavium,qlm-trim = "0,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy43: ethernet-phy@3 { + cavium,qlm-trim = "0,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy44: ethernet-phy@4 { + cavium,qlm-trim = "0,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi2: mdio@1180000003900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003900 0x0 0x40>; + + phy21: ethernet-phy@1 { + cavium,qlm-trim = "2,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy22: ethernet-phy@2 { + cavium,qlm-trim = "2,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy23: ethernet-phy@3 { + cavium,qlm-trim = "2,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy24: ethernet-phy@4 { + cavium,qlm-trim = "2,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi3: mdio@1180000003980 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003980 0x0 0x40>; + + phy11: ethernet-phy@1 { + cavium,qlm-trim = "3,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy12: ethernet-phy@2 { + cavium,qlm-trim = "3,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy13: ethernet-phy@3 { + cavium,qlm-trim = "3,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy14: ethernet-phy@4 { + cavium,qlm-trim = "3,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupts = <6 40>, <6 32>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@4 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + }; + }; + + interface@3 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy11>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy12>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy13>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy14>; + }; + }; + + interface@2 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy21>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy22>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy23>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy24>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy41>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy42>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy43>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy44>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <3 32>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupts = <3 33>; + clock-frequency = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <3 36>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <3 37>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0 0x1d020000 0x10000>, + <5 0 0 0x1d040000 0x10000>, + <6 0 0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <10>; + cavium,t-ce = <50>; + cavium,t-oe = <50>; + cavium,t-we = <35>; + cavium,t-rd-hld = <25>; + cavium,t-wr-hld = <35>; + cavium,t-pause = <0>; + cavium,t-wait = <300>; + cavium,t-page = <25>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <320>; + cavium,t-ce = <320>; + cavium,t-oe = <320>; + cavium,t-we = <320>; + cavium,t-rd-hld = <320>; + cavium,t-wr-hld = <320>; + cavium,t-pause = <320>; + cavium,t-wait = <320>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@5 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <5>; + cavium,t-adr = <0>; + cavium,t-ce = <300>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <300>; + cavium,t-pause = <0>; + cavium,t-wait = <300>; + cavium,t-page = <310>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <16>; + }; + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <0>; + cavium,t-ce = <30>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <30>; + cavium,t-pause = <0>; + cavium,t-wait = <30>; + cavium,t-page = <310>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0 0x200000>; + read-only; + }; + partition@200000 { + label = "kernel"; + reg = <0x200000 0x200000>; + }; + partition@400000 { + label = "cramfs"; + reg = <0x400000 0x3fe000>; + }; + partition@7fe000 { + label = "environment"; + reg = <0x7fe000 0x2000>; + read-only; + }; + }; + + led0: led-display@4,0 { + compatible = "avago,hdsp-253x"; + reg = <4 0x20 0x20>, <4 0 0x20>; + }; + + compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; + }; + + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; + dma1: dma-engine@1180000000108 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000108 0x0 0x8>; + interrupts = <0 63>; + }; + + uctl: uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <12000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <3 44>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <3 44>; + big-endian-regs; + }; + }; + }; + + aliases { + mix0 = &mix0; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + smi2 = &smi2; + smi3 = &smi3; + twsi0 = &twsi0; + twsi1 = &twsi1; + uart0 = &uart0; + uart1 = &uart1; + uctl = &uctl; + led0 = &led0; + flash0 = &flash0; + }; + }; -- 1.7.2.3 From veli-pekka.peltola@bluegiga.com Thu Mar 1 20:46:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Mar 2012 20:46:20 +0100 (CET) Received: from bluegiga.fi ([194.100.31.45]:33826 "EHLO darkblue.bluegiga.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903704Ab2CATqQ (ORCPT ); Thu, 1 Mar 2012 20:46:16 +0100 Received: from bluegiga.com ([10.1.1.102]) by darkblue.bluegiga.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 1 Mar 2012 21:46:13 +0200 Received: by bluegiga.com (sSMTP sendmail emulation); Thu, 01 Mar 2012 21:46:07 +0200 From: Veli-Pekka Peltola To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org, Veli-Pekka Peltola , Russell King , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org Subject: [PATCH] mm: module_alloc: check if size is 0 Date: Thu, 1 Mar 2012 21:45:19 +0200 Message-Id: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com> X-Mailer: git-send-email 1.7.5.4 X-OriginalArrivalTime: 01 Mar 2012 19:46:13.0597 (UTC) FILETIME=[F58988D0:01CCF7E3] X-archive-position: 32591 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: veli-pekka.peltola@bluegiga.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2553 Lines: 71 After commit de7d2b567d040e3b67fe7121945982f14343213d (mm/vmalloc.c: report more vmalloc failures) users will get a warning if vmalloc_node_range() is called with size 0. This happens if module's init size equals to 0. This patch changes ARM, MIPS and x86 module_alloc() to return NULL before calling vmalloc_node_range() that would also return NULL and print a warning. Signed-off-by: Veli-Pekka Peltola Cc: Russell King Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org --- I found this with ARM but after checking out various implementations of module_alloc() I thought it would be better to fix all at once. One way to replicate the warning: compile kernel with CONFIG_KALLSYMS=n insmod module without init, I used usb-common.ko arch/arm/kernel/module.c | 4 ++-- arch/mips/kernel/module.c | 4 ++-- arch/x86/kernel/module.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 1e9be5d..d44d212 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -39,8 +39,8 @@ #ifdef CONFIG_MMU void *module_alloc(unsigned long size) { - return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, - GFP_KERNEL, PAGE_KERNEL_EXEC, -1, + return size == 0 ? NULL : __vmalloc_node_range(size, 1, MODULES_VADDR, + MODULES_END, GFP_KERNEL, PAGE_KERNEL_EXEC, -1, __builtin_return_address(0)); } #endif diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index a5066b1..cd768e9 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -47,8 +47,8 @@ static DEFINE_SPINLOCK(dbe_lock); #ifdef MODULE_START void *module_alloc(unsigned long size) { - return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, - GFP_KERNEL, PAGE_KERNEL, -1, + return size == 0 ? NULL : __vmalloc_node_range(size, 1, MODULE_START, + MODULE_END, GFP_KERNEL, PAGE_KERNEL, -1, __builtin_return_address(0)); } #endif diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c index 925179f..bff6118 100644 --- a/arch/x86/kernel/module.c +++ b/arch/x86/kernel/module.c @@ -38,7 +38,7 @@ void *module_alloc(unsigned long size) { - if (PAGE_ALIGN(size) > MODULES_LEN) + if (size == 0 || PAGE_ALIGN(size) > MODULES_LEN) return NULL; return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC, -- 1.7.5.4 From hpa@zytor.com Thu Mar 1 21:47:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Mar 2012 21:47:56 +0100 (CET) Received: from terminus.zytor.com ([198.137.202.10]:44063 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903701Ab2CAUrw (ORCPT ); Thu, 1 Mar 2012 21:47:52 +0100 Received: from tazenda.hos.anvin.org ([IPv6:2001:470:861f::feed:face:f00d]) (authenticated bits=0) by mail.zytor.com (8.14.5/8.14.5) with ESMTP id q21Kl373015685 (version=TLSv1/SSLv3 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=OK); Thu, 1 Mar 2012 12:47:04 -0800 Message-ID: <4F4FE041.1000507@zytor.com> Date: Thu, 01 Mar 2012 12:46:57 -0800 From: "H. Peter Anvin" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.1) Gecko/20120209 Thunderbird/10.0.1 MIME-Version: 1.0 To: Veli-Pekka Peltola CC: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org, Russell King , Thomas Gleixner , Ingo Molnar , x86@kernel.org Subject: Re: [PATCH] mm: module_alloc: check if size is 0 References: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com> In-Reply-To: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-archive-position: 32592 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@zytor.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1954 Lines: 60 On 03/01/2012 11:45 AM, Veli-Pekka Peltola wrote: > diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c > index 1e9be5d..d44d212 100644 > --- a/arch/arm/kernel/module.c > +++ b/arch/arm/kernel/module.c > @@ -39,8 +39,8 @@ > #ifdef CONFIG_MMU > void *module_alloc(unsigned long size) > { > - return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, > - GFP_KERNEL, PAGE_KERNEL_EXEC, -1, > + return size == 0 ? NULL : __vmalloc_node_range(size, 1, MODULES_VADDR, > + MODULES_END, GFP_KERNEL, PAGE_KERNEL_EXEC, -1, > __builtin_return_address(0)); > } > #endif > diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c > index a5066b1..cd768e9 100644 > --- a/arch/mips/kernel/module.c > +++ b/arch/mips/kernel/module.c > @@ -47,8 +47,8 @@ static DEFINE_SPINLOCK(dbe_lock); > #ifdef MODULE_START > void *module_alloc(unsigned long size) > { > - return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, > - GFP_KERNEL, PAGE_KERNEL, -1, > + return size == 0 ? NULL : __vmalloc_node_range(size, 1, MODULE_START, > + MODULE_END, GFP_KERNEL, PAGE_KERNEL, -1, > __builtin_return_address(0)); > } > #endif > diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c > index 925179f..bff6118 100644 > --- a/arch/x86/kernel/module.c > +++ b/arch/x86/kernel/module.c > @@ -38,7 +38,7 @@ > > void *module_alloc(unsigned long size) > { > - if (PAGE_ALIGN(size) > MODULES_LEN) > + if (size == 0 || PAGE_ALIGN(size) > MODULES_LEN) > return NULL; > return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, > GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC, Looks good stylistically but really awkward technically. I would like to suggest using the idiom: if (!size) return NULL; ... consistently; combined with the PAGE_ALIGN() clause for x86 is fine too. -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. From robherring2@gmail.com Fri Mar 2 15:23:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Mar 2012 15:23:31 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:56107 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903737Ab2CBOXJ (ORCPT ); Fri, 2 Mar 2012 15:23:09 +0100 Received: by ghbf11 with SMTP id f11so837610ghb.36 for ; Fri, 02 Mar 2012 06:23:02 -0800 (PST) Received-SPF: pass (google.com: domain of robherring2@gmail.com designates 10.236.116.195 as permitted sender) client-ip=10.236.116.195; Authentication-Results: mr.google.com; spf=pass (google.com: domain of robherring2@gmail.com designates 10.236.116.195 as permitted sender) smtp.mail=robherring2@gmail.com; dkim=pass header.i=robherring2@gmail.com Received: from mr.google.com ([10.236.116.195]) by 10.236.116.195 with SMTP id g43mr13782042yhh.26.1330698182625 (num_hops = 1); Fri, 02 Mar 2012 06:23:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=4hfuThRi/kCO0bjufdgD/iQnIXhehSTrnlpnpcxM0KM=; b=fxc+iwBD3zy7HPx/j18oiupFZcSe5N3f1qlysZ26FzGwWHR45Wo+KyPnPV2l4R8Spq HmmN2IgC91E8sVyy0dtoFa8iPxy5IRCF9y3sze4h/e+XYMQKkYDc/HlvSWDpwQfD/Vzn NY/oSilBhnzd65R7y7deGSSHldaz5Zn8TGf7IENJCC6v0sKNytpkR3prO/YMYGFVnFUx eGSfTq5KmTQCex8SVcE1Lg85CCLt7N9FKjAlJnMwB/wFpFkyA2b0B6VzSiXtH/ikpHXC rhK5KoPW1p+yBfLn1z6xvv8DUqjqjQZDarxI7uBJwi68QQXpL5wmm2IM8c48RlBql060 2Nvw== Received: by 10.236.116.195 with SMTP id g43mr10908491yhh.26.1330698182530; Fri, 02 Mar 2012 06:23:02 -0800 (PST) Received: from [192.168.1.103] (65-36-72-55.dyn.grandenetworks.net. [65.36.72.55]) by mx.google.com with ESMTPS id n72sm14162268yhh.21.2012.03.02.06.23.00 (version=SSLv3 cipher=OTHER); Fri, 02 Mar 2012 06:23:01 -0800 (PST) Message-ID: <4F50D7C2.7080204@gmail.com> Date: Fri, 02 Mar 2012 08:22:58 -0600 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring , linux-kernel@vger.kernel.org, David Daney Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> In-Reply-To: <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32593 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 16759 Lines: 420 David, On 02/29/2012 06:57 PM, David Daney wrote: > From: David Daney > > Select IRQ_DOMAIN so the core irq_domain code and supply > irq_create_of_mapping(). > > Signed-off-by: David Daney > --- > arch/mips/Kconfig | 1 + > arch/mips/cavium-octeon/octeon-irq.c | 301 +++++++++++++++++++++++++++------- > 2 files changed, 239 insertions(+), 63 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index ce30e2f..01344ae 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1432,6 +1432,7 @@ config CPU_CAVIUM_OCTEON > select WEAK_ORDERING > select CPU_SUPPORTS_HIGHMEM > select CPU_SUPPORTS_HUGEPAGES > + select IRQ_DOMAIN IIRC, Grant has a patch cued up that enables IRQ_DOMAIN for all of MIPS. > help > The Cavium Octeon processor is a highly integrated chip containing > many ethernet hardware widgets for networking tasks. The processor > diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c > index bdcedd3..e9f2f6c 100644 > --- a/arch/mips/cavium-octeon/octeon-irq.c > +++ b/arch/mips/cavium-octeon/octeon-irq.c > @@ -3,14 +3,16 @@ > * License. See the file "COPYING" in the main directory of this archive > * for more details. > * > - * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks > + * Copyright (C) 2004-2008, 2009, 2010, 2011, 2012 Cavium Networks > */. > > #include > +#include > #include > #include > #include > #include > +#include > > #include > > @@ -42,20 +44,27 @@ struct octeon_core_chip_data { > > static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; > > -static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, > +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, > + unsigned int line, > + unsigned int bit, > + struct irq_domain *domain, > struct irq_chip *chip, > irq_flow_handler_t handler) > { > + struct irq_data *irqd; > union octeon_ciu_chip_data cd; > > irq_set_chip_and_handler(irq, chip, handler); > - > cd.l = 0; > cd.s.line = line; > cd.s.bit = bit; > > irq_set_chip_data(irq, cd.p); > octeon_irq_ciu_to_irq[line][bit] = irq; > + > + irqd = irq_get_irq_data(irq); > + irqd->hwirq = line << 6 | bit; > + irqd->domain = domain; I think the domain code will set these. > } > > static int octeon_coreid_for_cpu(int cpu) > @@ -855,6 +864,107 @@ static struct irq_chip octeon_irq_chip_ciu_wd = { > .irq_mask = octeon_irq_dummy_mask, > }; > > +static int octeon_irq_gpio_xlat(struct irq_domain *d, > + struct device_node *node, > + const u32 *intspec, > + unsigned int intsize, > + unsigned long *out_hwirq, > + unsigned int *out_type) > +{ > + unsigned int irq; > + unsigned int type; > + unsigned int ciu = 0, bit = 0; > + unsigned int pin; > + unsigned int trigger; > + bool set_edge_handler = false; > + > + if (d->of_node != node) > + return -EINVAL; > + > + if (intsize < 2) > + return -EINVAL; > + > + pin = intspec[0]; > + if (pin >= 16) > + return -EINVAL; > + > + trigger = intspec[1]; > + > + switch (trigger) { > + case 1: > + type = IRQ_TYPE_EDGE_RISING; > + set_edge_handler = true; > + break; > + case 2: > + type = IRQ_TYPE_EDGE_FALLING; > + set_edge_handler = true; > + break; > + case 4: > + type = IRQ_TYPE_LEVEL_HIGH; > + break; > + case 8: > + type = IRQ_TYPE_LEVEL_LOW; > + break; > + default: > + pr_err("Error: (%s) Invalid irq trigger specification: %x\n", > + node->name, > + trigger); > + type = IRQ_TYPE_LEVEL_LOW; > + break; > + } > + *out_type = type; > + *out_hwirq = ((unsigned long)d->host_data) + pin; > + > + ciu = *out_hwirq >> 6; > + bit = *out_hwirq & 0x3f; > + > + irq = octeon_irq_ciu_to_irq[ciu][bit]; > + > + if (set_edge_handler) > + __irq_set_handler(irq, handle_edge_irq, 0, NULL); > + > + return 0; > +} > + > +static int octeon_irq_ciu_xlat(struct irq_domain *d, > + struct device_node *node, > + const u32 *intspec, > + unsigned int intsize, > + unsigned long *out_hwirq, > + unsigned int *out_type) > +{ > + unsigned int ciu, bit; > + > + ciu = intspec[0]; > + bit = intspec[1]; > + > + if (ciu > 1 || bit > 63) > + return -EINVAL; > + > + if (octeon_irq_ciu_to_irq[ciu][bit] == 0) > + return -EINVAL; > + > + *out_hwirq = (ciu << 6) | bit; > + *out_type = 0; > + > + return 0; > +} > +static int octeon_irq_dummy_map(struct irq_domain *d, > + unsigned int virq, irq_hw_number_t hw) > +{ > + return 0; > +} > + > +static struct irq_domain_ops octeon_irq_domain_ciu_ops = { > + .map = octeon_irq_dummy_map, > + .xlate = octeon_irq_ciu_xlat, > +}; > + > +static struct irq_domain_ops octeon_irq_domain_gpio_ops = { > + .map = octeon_irq_dummy_map, > + .xlate = octeon_irq_gpio_xlat, > +}; > + > static void octeon_irq_ip2_v1(void) > { > const unsigned long core_id = cvmx_get_core_num(); > @@ -982,6 +1092,10 @@ static void __init octeon_irq_init_ciu(void) > struct irq_chip *chip_mbox; > struct irq_chip *chip_wd; > struct irq_chip *chip_gpio; > + struct device_node *gpio_node; > + struct device_node *ciu_node; > + struct irq_domain *gpio_domain; > + struct irq_domain *ciu_domain; > > octeon_irq_init_ciu_percpu(); > octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; > @@ -1011,83 +1125,144 @@ static void __init octeon_irq_init_ciu(void) > /* Mips internal */ > octeon_irq_init_core(); > > + gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); > + ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); > + /* gpio domain host_data is the base hwirq number. */ > + gpio_domain = irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, (void *)16); It would be better to define a struct here rather than casting a data value to a ptr. > + ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); > + > /* CIU_0 */ > for (i = 0; i < 16; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, > + ciu_domain, chip, handle_level_irq); > + > for (i = 0; i < 16; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, > + gpio_domain, chip_gpio, handle_level_irq); > > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, > + ciu_domain, chip_mbox, handle_percpu_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, > + ciu_domain, chip_mbox, handle_percpu_irq); > > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, > + ciu_domain, chip, handle_level_irq); > > for (i = 0; i < 4; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, > + ciu_domain, chip, handle_level_irq); > for (i = 0; i < 4; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, > + ciu_domain, chip, handle_level_irq); > > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, > + ciu_domain, chip, handle_level_irq); > > for (i = 0; i < 2; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, > + ciu_domain, chip_edge, handle_edge_irq); > > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, > + ciu_domain, chip_edge, handle_edge_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, > + ciu_domain, chip_edge, handle_edge_irq); > > for (i = 0; i < 4; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, > + ciu_domain, chip_edge, handle_edge_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, > + ciu_domain, chip, handle_level_irq); > > /* CIU_1 */ > for (i = 0; i < 16; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, > + ciu_domain, chip_wd, handle_level_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, > + ciu_domain, chip, handle_level_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, > + ciu_domain, chip, handle_level_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, > + ciu_domain, chip, handle_level_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, > + ciu_domain, chip_edge, handle_edge_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, > + ciu_domain, chip, handle_level_irq); > Can all these calls be moved into the .map function somehow? edge vs. level should be driven by dts. Rob > /* Enable the CIU lines */ > set_c0_status(STATUSF_IP3 | STATUSF_IP2); From david.daney@cavium.com Fri Mar 2 19:04:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Mar 2012 19:04:12 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10729 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903737Ab2CBSEE (ORCPT ); Fri, 2 Mar 2012 19:04:04 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 02 Mar 2012 10:05:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 2 Mar 2012 10:03:59 -0800 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 2 Mar 2012 10:03:59 -0800 Message-ID: <4F510B8E.3070201@cavium.com> Date: Fri, 02 Mar 2012 10:03:58 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Rob Herring CC: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring , linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> In-Reply-To: <4F50D7C2.7080204@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Mar 2012 18:03:59.0537 (UTC) FILETIME=[D7C40210:01CCF89E] X-archive-position: 32594 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4244 Lines: 130 On 03/02/2012 06:22 AM, Rob Herring wrote: [...] >> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig >> index ce30e2f..01344ae 100644 >> --- a/arch/mips/Kconfig >> +++ b/arch/mips/Kconfig >> @@ -1432,6 +1432,7 @@ config CPU_CAVIUM_OCTEON >> select WEAK_ORDERING >> select CPU_SUPPORTS_HIGHMEM >> select CPU_SUPPORTS_HUGEPAGES >> + select IRQ_DOMAIN > > IIRC, Grant has a patch cued up that enables IRQ_DOMAIN for all of MIPS. > Indeed, I now see it in linux-next. I will remove this one. >> help >> The Cavium Octeon processor is a highly integrated chip containing >> many ethernet hardware widgets for networking tasks. The processor >> diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c >> index bdcedd3..e9f2f6c 100644 >> --- a/arch/mips/cavium-octeon/octeon-irq.c >> +++ b/arch/mips/cavium-octeon/octeon-irq.c [...] >> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, >> + unsigned int line, >> + unsigned int bit, >> + struct irq_domain *domain, >> struct irq_chip *chip, >> irq_flow_handler_t handler) >> { >> + struct irq_data *irqd; >> union octeon_ciu_chip_data cd; >> >> irq_set_chip_and_handler(irq, chip, handler); >> - >> cd.l = 0; >> cd.s.line = line; >> cd.s.bit = bit; >> >> irq_set_chip_data(irq, cd.p); >> octeon_irq_ciu_to_irq[line][bit] = irq; >> + >> + irqd = irq_get_irq_data(irq); >> + irqd->hwirq = line<< 6 | bit; >> + irqd->domain = domain; > > I think the domain code will set these. It is my understanding that the domain code only does this for: o irq_domain_add_legacy() o irq_create_direct_mapping() o irq_create_mapping() We use none of those. So I do it here. If there is a better way, I am open to suggestions. [...] >> @@ -982,6 +1092,10 @@ static void __init octeon_irq_init_ciu(void) >> struct irq_chip *chip_mbox; >> struct irq_chip *chip_wd; >> struct irq_chip *chip_gpio; >> + struct device_node *gpio_node; >> + struct device_node *ciu_node; >> + struct irq_domain *gpio_domain; >> + struct irq_domain *ciu_domain; >> >> octeon_irq_init_ciu_percpu(); >> octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; >> @@ -1011,83 +1125,144 @@ static void __init octeon_irq_init_ciu(void) >> /* Mips internal */ >> octeon_irq_init_core(); >> >> + gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); >> + ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); >> + /* gpio domain host_data is the base hwirq number. */ >> + gpio_domain = irq_domain_add_linear(gpio_node, 16,&octeon_irq_domain_gpio_ops, (void *)16); > > It would be better to define a struct here rather than casting a data > value to a ptr. You mean allocate storage for the data somewhere and then pass a pointer to it? If so, I could, but it would just be adding code and data size just to satisfy some coding style thing... Or do you want a union of the pointer and my int? That would use the same amount of storage, but add more source code to gain what? [...] >> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, >> + ciu_domain, chip, handle_level_irq); >> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, >> + ciu_domain, chip, handle_level_irq); >> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, >> + ciu_domain, chip, handle_level_irq); >> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, >> + ciu_domain, chip, handle_level_irq); >> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, >> + ciu_domain, chip, handle_level_irq); >> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, >> + ciu_domain, chip, handle_level_irq); >> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, >> + ciu_domain, chip, handle_level_irq); >> > > Can all these calls be moved into the .map function somehow? > No, the non-OF code using the OCTEON_IRQ_* symbols doesn't use irq_domain, so the .map function would never be used. > edge vs. level should be driven by dts. > We may have to disagree on this point. Because: 1) edge vs. level can be accurately probed, as we do here. 2) The dts doesnt contain the information. David Daney From grant.likely@secretlab.ca Fri Mar 2 20:03:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Mar 2012 20:03:10 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:62972 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903742Ab2CBTDE (ORCPT ); Fri, 2 Mar 2012 20:03:04 +0100 Received: by dakp5 with SMTP id p5so2755716dak.36 for ; Fri, 02 Mar 2012 11:02:58 -0800 (PST) Received-SPF: pass (google.com: domain of grant.likely@secretlab.ca designates 10.68.224.225 as permitted sender) client-ip=10.68.224.225; Authentication-Results: mr.google.com; spf=pass (google.com: domain of grant.likely@secretlab.ca designates 10.68.224.225 as permitted sender) smtp.mail=grant.likely@secretlab.ca Received: from mr.google.com ([10.68.224.225]) by 10.68.224.225 with SMTP id rf1mr20237470pbc.133.1330714978045 (num_hops = 1); Fri, 02 Mar 2012 11:02:58 -0800 (PST) MIME-Version: 1.0 Received: by 10.68.224.225 with SMTP id rf1mr16882332pbc.133.1330714977911; Fri, 02 Mar 2012 11:02:57 -0800 (PST) Received: from localhost (S0106d8b37715ee14.cg.shawcable.net. [68.146.14.168]) by mx.google.com with ESMTPS id l8sm5693912pbi.0.2012.03.02.11.02.55 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 02 Mar 2012 11:02:56 -0800 (PST) Received: by localhost (Postfix, from userid 1000) id 969B33E1C63; Fri, 2 Mar 2012 13:02:54 -0600 (CST) From: Grant Likely Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. To: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney In-Reply-To: <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> Date: Fri, 02 Mar 2012 12:02:54 -0700 Message-Id: <20120302190254.969B33E1C63@localhost> X-Gm-Message-State: ALoCoQnIzqCz7oS0g2lOG51R7U8miKxxa0YBiU6SgEeMhx1wkFtgA53tN3SeS7isRCrUVMyRRne0 X-archive-position: 32595 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 17021 Lines: 420 On Wed, 29 Feb 2012 16:57:01 -0800, David Daney wrote: > From: David Daney > > Select IRQ_DOMAIN so the core irq_domain code and supply > irq_create_of_mapping(). > > Signed-off-by: David Daney > --- > arch/mips/Kconfig | 1 + > arch/mips/cavium-octeon/octeon-irq.c | 301 +++++++++++++++++++++++++++------- > 2 files changed, 239 insertions(+), 63 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index ce30e2f..01344ae 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1432,6 +1432,7 @@ config CPU_CAVIUM_OCTEON > select WEAK_ORDERING > select CPU_SUPPORTS_HIGHMEM > select CPU_SUPPORTS_HUGEPAGES > + select IRQ_DOMAIN > help > The Cavium Octeon processor is a highly integrated chip containing > many ethernet hardware widgets for networking tasks. The processor > diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c > index bdcedd3..e9f2f6c 100644 > --- a/arch/mips/cavium-octeon/octeon-irq.c > +++ b/arch/mips/cavium-octeon/octeon-irq.c > @@ -3,14 +3,16 @@ > * License. See the file "COPYING" in the main directory of this archive > * for more details. > * > - * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks > + * Copyright (C) 2004-2008, 2009, 2010, 2011, 2012 Cavium Networks > */ > > #include > +#include > #include > #include > #include > #include > +#include > > #include > > @@ -42,20 +44,27 @@ struct octeon_core_chip_data { > > static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; > > -static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, > +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, > + unsigned int line, > + unsigned int bit, > + struct irq_domain *domain, > struct irq_chip *chip, > irq_flow_handler_t handler) > { > + struct irq_data *irqd; > union octeon_ciu_chip_data cd; > > irq_set_chip_and_handler(irq, chip, handler); > - > cd.l = 0; > cd.s.line = line; > cd.s.bit = bit; > > irq_set_chip_data(irq, cd.p); > octeon_irq_ciu_to_irq[line][bit] = irq; > + > + irqd = irq_get_irq_data(irq); > + irqd->hwirq = line << 6 | bit; irqdomain sets up hwirq for you. Don't set it manually because it will mess up irqdomain mappings. > + irqd->domain = domain; Ditto here; irqdomain manages the domain pointer internally. > } > > static int octeon_coreid_for_cpu(int cpu) > @@ -855,6 +864,107 @@ static struct irq_chip octeon_irq_chip_ciu_wd = { > .irq_mask = octeon_irq_dummy_mask, > }; > > +static int octeon_irq_gpio_xlat(struct irq_domain *d, > + struct device_node *node, > + const u32 *intspec, > + unsigned int intsize, > + unsigned long *out_hwirq, > + unsigned int *out_type) > +{ > + unsigned int irq; > + unsigned int type; > + unsigned int ciu = 0, bit = 0; > + unsigned int pin; > + unsigned int trigger; > + bool set_edge_handler = false; > + > + if (d->of_node != node) > + return -EINVAL; > + > + if (intsize < 2) > + return -EINVAL; > + > + pin = intspec[0]; > + if (pin >= 16) > + return -EINVAL; > + > + trigger = intspec[1]; > + > + switch (trigger) { > + case 1: > + type = IRQ_TYPE_EDGE_RISING; > + set_edge_handler = true; > + break; > + case 2: > + type = IRQ_TYPE_EDGE_FALLING; > + set_edge_handler = true; > + break; > + case 4: > + type = IRQ_TYPE_LEVEL_HIGH; > + break; > + case 8: > + type = IRQ_TYPE_LEVEL_LOW; > + break; > + default: > + pr_err("Error: (%s) Invalid irq trigger specification: %x\n", > + node->name, > + trigger); > + type = IRQ_TYPE_LEVEL_LOW; > + break; > + } > + *out_type = type; > + *out_hwirq = ((unsigned long)d->host_data) + pin; > + > + ciu = *out_hwirq >> 6; > + bit = *out_hwirq & 0x3f; > + > + irq = octeon_irq_ciu_to_irq[ciu][bit]; Again; this is overstepping onto irqdomain responsibility. Don't set up the irq in the xlate routine; only parse the date and if you need to store extra data like 'set_edge_handler' (using the hwirq number as the key). The irq setup must be done in the .map callback which will be passed the actual irq number to be used. > + > + if (set_edge_handler) > + __irq_set_handler(irq, handle_edge_irq, 0, NULL); > + > + return 0; > +} > + > +static int octeon_irq_ciu_xlat(struct irq_domain *d, > + struct device_node *node, > + const u32 *intspec, > + unsigned int intsize, > + unsigned long *out_hwirq, > + unsigned int *out_type) > +{ > + unsigned int ciu, bit; > + > + ciu = intspec[0]; > + bit = intspec[1]; > + > + if (ciu > 1 || bit > 63) > + return -EINVAL; > + > + if (octeon_irq_ciu_to_irq[ciu][bit] == 0) > + return -EINVAL; > + > + *out_hwirq = (ciu << 6) | bit; > + *out_type = 0; > + > + return 0; > +} > +static int octeon_irq_dummy_map(struct irq_domain *d, > + unsigned int virq, irq_hw_number_t hw) > +{ > + return 0; > +} > + > +static struct irq_domain_ops octeon_irq_domain_ciu_ops = { > + .map = octeon_irq_dummy_map, > + .xlate = octeon_irq_ciu_xlat, > +}; > + > +static struct irq_domain_ops octeon_irq_domain_gpio_ops = { > + .map = octeon_irq_dummy_map, > + .xlate = octeon_irq_gpio_xlat, > +}; > + > static void octeon_irq_ip2_v1(void) > { > const unsigned long core_id = cvmx_get_core_num(); > @@ -982,6 +1092,10 @@ static void __init octeon_irq_init_ciu(void) > struct irq_chip *chip_mbox; > struct irq_chip *chip_wd; > struct irq_chip *chip_gpio; > + struct device_node *gpio_node; > + struct device_node *ciu_node; > + struct irq_domain *gpio_domain; > + struct irq_domain *ciu_domain; > > octeon_irq_init_ciu_percpu(); > octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; > @@ -1011,83 +1125,144 @@ static void __init octeon_irq_init_ciu(void) > /* Mips internal */ > octeon_irq_init_core(); > > + gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); > + ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); > + /* gpio domain host_data is the base hwirq number. */ > + gpio_domain = irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, (void *)16); > + ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); > + > /* CIU_0 */ > for (i = 0; i < 16; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, > + ciu_domain, chip, handle_level_irq); > + > for (i = 0; i < 16; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, > + gpio_domain, chip_gpio, handle_level_irq); > > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, > + ciu_domain, chip_mbox, handle_percpu_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, > + ciu_domain, chip_mbox, handle_percpu_irq); > > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, > + ciu_domain, chip, handle_level_irq); > > for (i = 0; i < 4; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, > + ciu_domain, chip, handle_level_irq); > for (i = 0; i < 4; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, > + ciu_domain, chip, handle_level_irq); > > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, > + ciu_domain, chip, handle_level_irq); > > for (i = 0; i < 2; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, > + ciu_domain, chip_edge, handle_edge_irq); > > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, > + ciu_domain, chip_edge, handle_edge_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, > + ciu_domain, chip_edge, handle_edge_irq); > > for (i = 0; i < 4; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, > + ciu_domain, chip_edge, handle_edge_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, > + ciu_domain, chip, handle_level_irq); > > /* CIU_1 */ > for (i = 0; i < 16; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq); > - > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq); > - octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, > + ciu_domain, chip_wd, handle_level_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, > + ciu_domain, chip, handle_level_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, > + ciu_domain, chip, handle_level_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, > + ciu_domain, chip, handle_level_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, > + ciu_domain, chip_edge, handle_edge_irq); > + > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, > + ciu_domain, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, > + ciu_domain, chip, handle_level_irq); > > /* Enable the CIU lines */ > set_c0_status(STATUSF_IP3 | STATUSF_IP2); > -- > 1.7.2.3 > -- email sent from notmuch.vim plugin From grant.likely@secretlab.ca Fri Mar 2 20:07:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Mar 2012 20:07:59 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:48995 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903744Ab2CBTHx (ORCPT ); Fri, 2 Mar 2012 20:07:53 +0100 Received: by pbbro2 with SMTP id ro2so3086149pbb.36 for ; Fri, 02 Mar 2012 11:07:46 -0800 (PST) Received-SPF: pass (google.com: domain of grant.likely@secretlab.ca designates 10.68.203.73 as permitted sender) client-ip=10.68.203.73; Authentication-Results: mr.google.com; spf=pass (google.com: domain of grant.likely@secretlab.ca designates 10.68.203.73 as permitted sender) smtp.mail=grant.likely@secretlab.ca Received: from mr.google.com ([10.68.203.73]) by 10.68.203.73 with SMTP id ko9mr19508266pbc.130.1330715266811 (num_hops = 1); Fri, 02 Mar 2012 11:07:46 -0800 (PST) MIME-Version: 1.0 Received: by 10.68.203.73 with SMTP id ko9mr16281973pbc.130.1330715266675; Fri, 02 Mar 2012 11:07:46 -0800 (PST) Received: from localhost (S0106d8b37715ee14.cg.shawcable.net. [68.146.14.168]) by mx.google.com with ESMTPS id g3sm5678693pbt.41.2012.03.02.11.07.45 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 02 Mar 2012 11:07:45 -0800 (PST) Received: by localhost (Postfix, from userid 1000) id 571E03E1C63; Fri, 2 Mar 2012 13:07:44 -0600 (CST) From: Grant Likely Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. To: David Daney , Rob Herring Cc: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Rob Herring , linux-kernel@vger.kernel.org In-Reply-To: <4F510B8E.3070201@cavium.com> References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> Date: Fri, 02 Mar 2012 12:07:44 -0700 Message-Id: <20120302190744.571E03E1C63@localhost> X-Gm-Message-State: ALoCoQnnrE+cHXqSuvV7ois99yw/yg0c1G9yutriSn+iMCI28BHZvndNjU4M6Wx2WVhMUaTAj0yK X-archive-position: 32596 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2230 Lines: 69 On Fri, 02 Mar 2012 10:03:58 -0800, David Daney wrote: > On 03/02/2012 06:22 AM, Rob Herring wrote: > [...] > >> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > >> index ce30e2f..01344ae 100644 > >> --- a/arch/mips/Kconfig > >> +++ b/arch/mips/Kconfig > >> @@ -1432,6 +1432,7 @@ config CPU_CAVIUM_OCTEON > >> select WEAK_ORDERING > >> select CPU_SUPPORTS_HIGHMEM > >> select CPU_SUPPORTS_HUGEPAGES > >> + select IRQ_DOMAIN > > > > IIRC, Grant has a patch cued up that enables IRQ_DOMAIN for all of MIPS. > > > > Indeed, I now see it in linux-next. I will remove this one. > > >> help > >> The Cavium Octeon processor is a highly integrated chip containing > >> many ethernet hardware widgets for networking tasks. The processor > >> diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c > >> index bdcedd3..e9f2f6c 100644 > >> --- a/arch/mips/cavium-octeon/octeon-irq.c > >> +++ b/arch/mips/cavium-octeon/octeon-irq.c > [...] > >> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, > >> + unsigned int line, > >> + unsigned int bit, > >> + struct irq_domain *domain, > >> struct irq_chip *chip, > >> irq_flow_handler_t handler) > >> { > >> + struct irq_data *irqd; > >> union octeon_ciu_chip_data cd; > >> > >> irq_set_chip_and_handler(irq, chip, handler); > >> - > >> cd.l = 0; > >> cd.s.line = line; > >> cd.s.bit = bit; > >> > >> irq_set_chip_data(irq, cd.p); > >> octeon_irq_ciu_to_irq[line][bit] = irq; > >> + > >> + irqd = irq_get_irq_data(irq); > >> + irqd->hwirq = line<< 6 | bit; > >> + irqd->domain = domain; > > > > I think the domain code will set these. > > It is my understanding that the domain code only does this for: > > o irq_domain_add_legacy() > > o irq_create_direct_mapping() > > o irq_create_mapping() > > We use none of those. So I do it here. > > If there is a better way, I am open to suggestions. irq_create_mapping is called by irq_create_of_mapping() which is in turn called by irq_of_parse_and-map(). irq_domain always manages the hwirq and domain values. Driver code cannot manipulate them manually. g. From david.daney@cavium.com Fri Mar 2 20:29:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Mar 2012 20:30:00 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13537 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903743Ab2CBT3y (ORCPT ); Fri, 2 Mar 2012 20:29:54 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 02 Mar 2012 11:31:36 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 2 Mar 2012 11:29:53 -0800 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 2 Mar 2012 11:29:52 -0800 Message-ID: <4F511FB0.5070901@cavium.com> Date: Fri, 02 Mar 2012 11:29:52 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Grant Likely CC: Rob Herring , David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> <20120302190744.571E03E1C63@localhost> In-Reply-To: <20120302190744.571E03E1C63@localhost> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Mar 2012 19:29:52.0992 (UTC) FILETIME=[D776D600:01CCF8AA] X-archive-position: 32597 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2691 Lines: 84 On 03/02/2012 11:07 AM, Grant Likely wrote: > On Fri, 02 Mar 2012 10:03:58 -0800, David Daney wrote: >> On 03/02/2012 06:22 AM, Rob Herring wrote: >> [...] >>>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig >>>> index ce30e2f..01344ae 100644 >>>> --- a/arch/mips/Kconfig >>>> +++ b/arch/mips/Kconfig >>>> @@ -1432,6 +1432,7 @@ config CPU_CAVIUM_OCTEON >>>> select WEAK_ORDERING >>>> select CPU_SUPPORTS_HIGHMEM >>>> select CPU_SUPPORTS_HUGEPAGES >>>> + select IRQ_DOMAIN >>> >>> IIRC, Grant has a patch cued up that enables IRQ_DOMAIN for all of MIPS. >>> >> >> Indeed, I now see it in linux-next. I will remove this one. >> >>>> help >>>> The Cavium Octeon processor is a highly integrated chip containing >>>> many ethernet hardware widgets for networking tasks. The processor >>>> diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c >>>> index bdcedd3..e9f2f6c 100644 >>>> --- a/arch/mips/cavium-octeon/octeon-irq.c >>>> +++ b/arch/mips/cavium-octeon/octeon-irq.c >> [...] >>>> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, >>>> + unsigned int line, >>>> + unsigned int bit, >>>> + struct irq_domain *domain, >>>> struct irq_chip *chip, >>>> irq_flow_handler_t handler) >>>> { >>>> + struct irq_data *irqd; >>>> union octeon_ciu_chip_data cd; >>>> >>>> irq_set_chip_and_handler(irq, chip, handler); >>>> - >>>> cd.l = 0; >>>> cd.s.line = line; >>>> cd.s.bit = bit; >>>> >>>> irq_set_chip_data(irq, cd.p); >>>> octeon_irq_ciu_to_irq[line][bit] = irq; >>>> + >>>> + irqd = irq_get_irq_data(irq); >>>> + irqd->hwirq = line<< 6 | bit; >>>> + irqd->domain = domain; >>> >>> I think the domain code will set these. >> >> It is my understanding that the domain code only does this for: >> >> o irq_domain_add_legacy() >> >> o irq_create_direct_mapping() >> >> o irq_create_mapping() >> >> We use none of those. So I do it here. >> >> If there is a better way, I am open to suggestions. > > irq_create_mapping is called by irq_create_of_mapping() which is > in turn called by irq_of_parse_and-map(). irq_domain always > manages the hwirq and domain values. Driver code cannot manipulate > them manually. > I really must be missing something. Given: 1) I must have a mapping between hwirq and irq that I control so that non-OF code using the OCTEON_IRQ_* constants continues to work. 2) irq_create_mapping() will allocate a random irq value if none is already assigned to the hwirq. Therefore: To avoid having random irq values assigned, I must manually assign them. David Daney From robherring2@gmail.com Sat Mar 3 20:35:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Mar 2012 20:36:01 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:32778 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903626Ab2CCTfn (ORCPT ); Sat, 3 Mar 2012 20:35:43 +0100 Received: by yhjj52 with SMTP id j52so1330241yhj.36 for ; Sat, 03 Mar 2012 11:35:37 -0800 (PST) Received-SPF: pass (google.com: domain of robherring2@gmail.com designates 10.101.190.10 as permitted sender) client-ip=10.101.190.10; Authentication-Results: mr.google.com; spf=pass (google.com: domain of robherring2@gmail.com designates 10.101.190.10 as permitted sender) smtp.mail=robherring2@gmail.com; dkim=pass header.i=robherring2@gmail.com Received: from mr.google.com ([10.101.190.10]) by 10.101.190.10 with SMTP id s10mr6052645anp.75.1330803337007 (num_hops = 1); Sat, 03 Mar 2012 11:35:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=dRbGCB1NcdLoq34QaKa5F8r/syyjpDlttvpLxgI4mtQ=; b=RvyelmpPiEtML2yWa7oNbMYM4EtyHJsJmpO5IJa9P5g+49NaSvdtG2NjiqJrOArfUu POdoZ5f1e1zDDxP0aBZGamJmvmocSP1dda0hkRTn1a0VuuC2/iZ1RgWzB+o0P9IvTT+O RNIQ53jkLNA0SP+hzSyeF7nmYi+H8zcOzjf/3CVGuCYezNIBiFYC4CJmBGvG9xeQAoSv pXLlVnY0xNOaqs9Y2EDb9BmFDXxNUM3KGb8WKPj3h7pOxS3xTLWEKxG8HaBctDhKd8lC UJQMCCbnK1ghCHQTnidTr8x1gu+vONJ8yaPJ22T0Mwza61RpIT72l20dJ6WA1h2q2KKB yB0Q== Received: by 10.101.190.10 with SMTP id s10mr4807987anp.75.1330803336943; Sat, 03 Mar 2012 11:35:36 -0800 (PST) Received: from [192.168.1.103] (65-36-72-55.dyn.grandenetworks.net. [65.36.72.55]) by mx.google.com with ESMTPS id r7sm4696444yhm.9.2012.03.03.11.35.34 (version=SSLv3 cipher=OTHER); Sat, 03 Mar 2012 11:35:35 -0800 (PST) Message-ID: <4F527285.1020500@gmail.com> Date: Sat, 03 Mar 2012 13:35:33 -0600 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: David Daney CC: Grant Likely , David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> <20120302190744.571E03E1C63@localhost> <4F511FB0.5070901@cavium.com> In-Reply-To: <4F511FB0.5070901@cavium.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32598 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3461 Lines: 102 On 03/02/2012 01:29 PM, David Daney wrote: > On 03/02/2012 11:07 AM, Grant Likely wrote: >> On Fri, 02 Mar 2012 10:03:58 -0800, David >> Daney wrote: >>> On 03/02/2012 06:22 AM, Rob Herring wrote: >>> [...] >>>>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig >>>>> index ce30e2f..01344ae 100644 >>>>> --- a/arch/mips/Kconfig >>>>> +++ b/arch/mips/Kconfig >>>>> @@ -1432,6 +1432,7 @@ config CPU_CAVIUM_OCTEON >>>>> select WEAK_ORDERING >>>>> select CPU_SUPPORTS_HIGHMEM >>>>> select CPU_SUPPORTS_HUGEPAGES >>>>> + select IRQ_DOMAIN >>>> >>>> IIRC, Grant has a patch cued up that enables IRQ_DOMAIN for all of >>>> MIPS. >>>> >>> >>> Indeed, I now see it in linux-next. I will remove this one. >>> >>>>> help >>>>> The Cavium Octeon processor is a highly integrated chip >>>>> containing >>>>> many ethernet hardware widgets for networking tasks. The >>>>> processor >>>>> diff --git a/arch/mips/cavium-octeon/octeon-irq.c >>>>> b/arch/mips/cavium-octeon/octeon-irq.c >>>>> index bdcedd3..e9f2f6c 100644 >>>>> --- a/arch/mips/cavium-octeon/octeon-irq.c >>>>> +++ b/arch/mips/cavium-octeon/octeon-irq.c >>> [...] >>>>> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, >>>>> + unsigned int line, >>>>> + unsigned int bit, >>>>> + struct irq_domain *domain, >>>>> struct irq_chip *chip, >>>>> irq_flow_handler_t handler) >>>>> { >>>>> + struct irq_data *irqd; >>>>> union octeon_ciu_chip_data cd; >>>>> >>>>> irq_set_chip_and_handler(irq, chip, handler); >>>>> - >>>>> cd.l = 0; >>>>> cd.s.line = line; >>>>> cd.s.bit = bit; >>>>> >>>>> irq_set_chip_data(irq, cd.p); >>>>> octeon_irq_ciu_to_irq[line][bit] = irq; >>>>> + >>>>> + irqd = irq_get_irq_data(irq); >>>>> + irqd->hwirq = line<< 6 | bit; >>>>> + irqd->domain = domain; >>>> >>>> I think the domain code will set these. >>> >>> It is my understanding that the domain code only does this for: >>> >>> o irq_domain_add_legacy() >>> >>> o irq_create_direct_mapping() >>> >>> o irq_create_mapping() >>> >>> We use none of those. So I do it here. >>> >>> If there is a better way, I am open to suggestions. >> >> irq_create_mapping is called by irq_create_of_mapping() which is >> in turn called by irq_of_parse_and-map(). irq_domain always >> manages the hwirq and domain values. Driver code cannot manipulate >> them manually. >> > > I really must be missing something. > > Given: > > 1) I must have a mapping between hwirq and irq that I control so that > non-OF code using the OCTEON_IRQ_* constants continues to work. Those defines are what you need to work to get rid of. > 2) irq_create_mapping() will allocate a random irq value if none is > already assigned to the hwirq. > > Therefore: To avoid having random irq values assigned, I must manually > assign them. > So you should be using legacy domain if you need to maintain fixed hwirq to linux irq numbers. "linear" is a bit confusing as it doesn't mean linear 1:1 irq number assignment, but linear search. Ultimately, for DT boot you should use of_irq_init to scan the dts, and then create a linear domain for each interrupt controller node. You may need to decide on linear vs. legacy at runtime based on having a DT node pointer or not. Rob From robherring2@gmail.com Sat Mar 3 20:38:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Mar 2012 20:39:05 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:50509 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903626Ab2CCTis (ORCPT ); Sat, 3 Mar 2012 20:38:48 +0100 Received: by ghbf11 with SMTP id f11so1336246ghb.36 for ; Sat, 03 Mar 2012 11:38:42 -0800 (PST) Received-SPF: pass (google.com: domain of robherring2@gmail.com designates 10.236.138.110 as permitted sender) client-ip=10.236.138.110; Authentication-Results: mr.google.com; spf=pass (google.com: domain of robherring2@gmail.com designates 10.236.138.110 as permitted sender) smtp.mail=robherring2@gmail.com; dkim=pass header.i=robherring2@gmail.com Received: from mr.google.com ([10.236.138.110]) by 10.236.138.110 with SMTP id z74mr19583983yhi.114.1330803522000 (num_hops = 1); Sat, 03 Mar 2012 11:38:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=67dJ4scwfsu6oIP2mhnG3bPd5KUxXZD928kVdvrBvE0=; b=Zdk4ZSKqDn0oQKEYgabZC/4YSfwcDzYxnt0orGLioazc4XIxN5XHU8+doAbIiYVQ90 kCqlbyaPhHOSqDHuyCcAvV1eHWFZAtGF628zECPKWaUdZyyfWnbhxCmmaxU9tffWBaSr DDtIdHoB6UwqpbxQtTeWvpVW9Xwx28A5hIJ2PLMoQHoRsjhRfIjj18+gH+dnNsddXOVX a6clsjGuc+4UU9TMguk/FzyEUDIhTcbecZHuSvpLZ2IkC5+3RkxXyt73bvjiM9bf3T7D 1qC8gK/9jtnZiHKEX/WFqk4QPgYGwq7MHSiRTvnw0n0stmT40j9n1mDp5UD9oJA3WlvN MCUQ== Received: by 10.236.138.110 with SMTP id z74mr15549220yhi.114.1330803521954; Sat, 03 Mar 2012 11:38:41 -0800 (PST) Received: from [192.168.1.103] (65-36-72-55.dyn.grandenetworks.net. [65.36.72.55]) by mx.google.com with ESMTPS id n24sm24948368yhj.13.2012.03.03.11.38.40 (version=SSLv3 cipher=OTHER); Sat, 03 Mar 2012 11:38:41 -0800 (PST) Message-ID: <4F52733F.4030807@gmail.com> Date: Sat, 03 Mar 2012 13:38:39 -0600 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: David Daney CC: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring , linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> In-Reply-To: <4F510B8E.3070201@cavium.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32599 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5136 Lines: 156 On 03/02/2012 12:03 PM, David Daney wrote: > On 03/02/2012 06:22 AM, Rob Herring wrote: > [...] >>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig >>> index ce30e2f..01344ae 100644 >>> --- a/arch/mips/Kconfig >>> +++ b/arch/mips/Kconfig >>> @@ -1432,6 +1432,7 @@ config CPU_CAVIUM_OCTEON >>> select WEAK_ORDERING >>> select CPU_SUPPORTS_HIGHMEM >>> select CPU_SUPPORTS_HUGEPAGES >>> + select IRQ_DOMAIN >> >> IIRC, Grant has a patch cued up that enables IRQ_DOMAIN for all of MIPS. >> > > Indeed, I now see it in linux-next. I will remove this one. > >>> help >>> The Cavium Octeon processor is a highly integrated chip >>> containing >>> many ethernet hardware widgets for networking tasks. The >>> processor >>> diff --git a/arch/mips/cavium-octeon/octeon-irq.c >>> b/arch/mips/cavium-octeon/octeon-irq.c >>> index bdcedd3..e9f2f6c 100644 >>> --- a/arch/mips/cavium-octeon/octeon-irq.c >>> +++ b/arch/mips/cavium-octeon/octeon-irq.c > [...] >>> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, >>> + unsigned int line, >>> + unsigned int bit, >>> + struct irq_domain *domain, >>> struct irq_chip *chip, >>> irq_flow_handler_t handler) >>> { >>> + struct irq_data *irqd; >>> union octeon_ciu_chip_data cd; >>> >>> irq_set_chip_and_handler(irq, chip, handler); >>> - >>> cd.l = 0; >>> cd.s.line = line; >>> cd.s.bit = bit; >>> >>> irq_set_chip_data(irq, cd.p); >>> octeon_irq_ciu_to_irq[line][bit] = irq; >>> + >>> + irqd = irq_get_irq_data(irq); >>> + irqd->hwirq = line<< 6 | bit; >>> + irqd->domain = domain; >> >> I think the domain code will set these. > > It is my understanding that the domain code only does this for: > > o irq_domain_add_legacy() > > o irq_create_direct_mapping() > > o irq_create_mapping() > > We use none of those. So I do it here. > > If there is a better way, I am open to suggestions. How do you convert local h/w irq controller numbers in the dts to linux irq #'s? > > [...] >>> @@ -982,6 +1092,10 @@ static void __init octeon_irq_init_ciu(void) >>> struct irq_chip *chip_mbox; >>> struct irq_chip *chip_wd; >>> struct irq_chip *chip_gpio; >>> + struct device_node *gpio_node; >>> + struct device_node *ciu_node; >>> + struct irq_domain *gpio_domain; >>> + struct irq_domain *ciu_domain; >>> >>> octeon_irq_init_ciu_percpu(); >>> octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; >>> @@ -1011,83 +1125,144 @@ static void __init octeon_irq_init_ciu(void) >>> /* Mips internal */ >>> octeon_irq_init_core(); >>> >>> + gpio_node = of_find_compatible_node(NULL, NULL, >>> "cavium,octeon-3860-gpio"); >>> + ciu_node = of_find_compatible_node(NULL, NULL, >>> "cavium,octeon-3860-ciu"); >>> + /* gpio domain host_data is the base hwirq number. */ >>> + gpio_domain = irq_domain_add_linear(gpio_node, >>> 16,&octeon_irq_domain_gpio_ops, (void *)16); >> >> It would be better to define a struct here rather than casting a data >> value to a ptr. > > You mean allocate storage for the data somewhere and then pass a pointer > to it? > > If so, I could, but it would just be adding code and data size just to > satisfy some coding style thing... > > Or do you want a union of the pointer and my int? That would use the > same amount of storage, but add more source code to gain what? The former. It's better style, less error prone and easily expanded if more data is needed in the future. > > [...] >>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, >>> + ciu_domain, chip, handle_level_irq); >>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, >>> + ciu_domain, chip, handle_level_irq); >>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, >>> + ciu_domain, chip, handle_level_irq); >>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, >>> + ciu_domain, chip, handle_level_irq); >>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, >>> + ciu_domain, chip, handle_level_irq); >>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, >>> + ciu_domain, chip, handle_level_irq); >>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, >>> + ciu_domain, chip, handle_level_irq); >>> >> >> Can all these calls be moved into the .map function somehow? >> > > No, the non-OF code using the OCTEON_IRQ_* symbols doesn't use > irq_domain, so the .map function would never be used. > .map is called for legacy domains during domain add. > >> edge vs. level should be driven by dts. >> > > We may have to disagree on this point. Because: > > 1) edge vs. level can be accurately probed, as we do here. Looks like you are just hard coding it here. Where do you read something that tells you the interrupt is level or edge? Rob > > 2) The dts doesnt contain the information. > > > David Daney From david.s.daney@gmail.com Sun Mar 4 06:09:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 04 Mar 2012 06:09:59 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:50049 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903560Ab2CDFJm (ORCPT ); Sun, 4 Mar 2012 06:09:42 +0100 Received: by pbbro2 with SMTP id ro2so4621297pbb.36 for ; Sat, 03 Mar 2012 21:09:34 -0800 (PST) Received-SPF: pass (google.com: domain of david.s.daney@gmail.com designates 10.68.196.201 as permitted sender) client-ip=10.68.196.201; Authentication-Results: mr.google.com; spf=pass (google.com: domain of david.s.daney@gmail.com designates 10.68.196.201 as permitted sender) smtp.mail=david.s.daney@gmail.com; dkim=pass header.i=david.s.daney@gmail.com Received: from mr.google.com ([10.68.196.201]) by 10.68.196.201 with SMTP id io9mr18776822pbc.86.1330837774925 (num_hops = 1); Sat, 03 Mar 2012 21:09:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=b0ZBgfZ7Cd9zLy9EM1B6lH1OmCMvscw+fml6YPtfejA=; b=TlLj1pV7hu7nvDE7V6AuKPV27F2IXnhvgb815g+EuSIdLTqLxf77Y0r9uky6Y0nPjW 3PTV6kSwUHrmtug8mu12OC3bgyUR0/1+H0hywui8DKjxA70g//PgZZ7xgd/+g2iGboTF 9PdGm57aP7r9sGS8tHs4TSRIFRSS2QFwi2VGi/dPba58rmsfEk1m5o3OTl2v4YP9k2PI qP2ksrGKA6/nY5GUXYjLjFAhNkZ/sb1zBkeR9cOQVP1pOypWuMJiwWKr2I+mYMfPolJZ pe0ynZVsYkmiR5aW5YXkVb/qn7c/QsHUPs0ukj1AlZ6K+9k3mb0deUJwyhshgo0I31my mabQ== Received: by 10.68.196.201 with SMTP id io9mr16192682pbc.86.1330837774858; Sat, 03 Mar 2012 21:09:34 -0800 (PST) Received: from dd_xps.caveonetworks.com (adsl-67-127-190-10.dsl.pltn13.pacbell.net. [67.127.190.10]) by mx.google.com with ESMTPS id 3sm9537705pbx.66.2012.03.03.21.09.33 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 03 Mar 2012 21:09:34 -0800 (PST) Message-ID: <4F52F90C.5060306@gmail.com> Date: Sat, 03 Mar 2012 21:09:32 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.1) Gecko/20120216 Thunderbird/10.0.1 MIME-Version: 1.0 To: Rob Herring CC: David Daney , Grant Likely , David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> <20120302190744.571E03E1C63@localhost> <4F511FB0.5070901@cavium.com> <4F527285.1020500@gmail.com> In-Reply-To: <4F527285.1020500@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32600 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.s.daney@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3332 Lines: 89 On 03/03/2012 11:35 AM, Rob Herring wrote: > On 03/02/2012 01:29 PM, David Daney wrote: >> On 03/02/2012 11:07 AM, Grant Likely wrote: >>> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, >>> + unsigned int line, >>> + unsigned int bit, >>> + struct irq_domain *domain, >>> struct irq_chip *chip, >>> irq_flow_handler_t handler) >>> { >>> + struct irq_data *irqd; >>> union octeon_ciu_chip_data cd; >>> >>> irq_set_chip_and_handler(irq, chip, handler); >>> - >>> cd.l = 0; >>> cd.s.line = line; >>> cd.s.bit = bit; >>> >>> irq_set_chip_data(irq, cd.p); >>> octeon_irq_ciu_to_irq[line][bit] = irq; >>> + >>> + irqd = irq_get_irq_data(irq); >>> + irqd->hwirq = line<< 6 | bit; >>> + irqd->domain = domain; >>>>> I think the domain code will set these. >>>> It is my understanding that the domain code only does this for: >>>> >>>> o irq_domain_add_legacy() >>>> >>>> o irq_create_direct_mapping() >>>> >>>> o irq_create_mapping() >>>> >>>> We use none of those. So I do it here. >>>> >>>> If there is a better way, I am open to suggestions. >>> irq_create_mapping is called by irq_create_of_mapping() which is >>> in turn called by irq_of_parse_and-map(). irq_domain always >>> manages the hwirq and domain values. Driver code cannot manipulate >>> them manually. >>> >> I really must be missing something. >> >> Given: >> >> 1) I must have a mapping between hwirq and irq that I control so that >> non-OF code using the OCTEON_IRQ_* constants continues to work. > Those defines are what you need to work to get rid of. We are not starting from a blank slate here. There is a lot of in-tree code using these symbols. We cannot make them disappear with wishful thinking. The first step is a switch to irq_domains using the existing mappings. After we do that, I have patches to transition some drivers to use the OF mapping via irq_domains. After those are merged, we can work toward getting rid of OCTEON_IRQ_*. But I think it must be the last step in the process, not the first. > >> 2) irq_create_mapping() will allocate a random irq value if none is >> already assigned to the hwirq. >> >> Therefore: To avoid having random irq values assigned, I must manually >> assign them. >> > So you should be using legacy domain if you need to maintain fixed hwirq > to linux irq numbers. "linear" is a bit confusing as it doesn't mean > linear 1:1 irq number assignment, but linear search. My reading of Grant's code in linux-next directly contradicts this statement. There is no code in irqdomain.c, that I can see, that allows me to have an arbitrary mapping of irq <--> hwirq values. > > Ultimately, for DT boot you should use of_irq_init to scan the dts, and > then create a linear domain for each interrupt controller node. You may > need to decide on linear vs. legacy at runtime based on having a DT node > pointer or not. Perhaps, but we need to take the first step before gradually arriving at some Ultimate Solution. We will also need to handle irq controllers with 2^20 sparsely populated hwirq values, so linear domains will probably be out of the question there. David Daney From david.s.daney@gmail.com Sun Mar 4 06:41:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 04 Mar 2012 06:41:44 +0100 (CET) Received: from mail-pz0-f48.google.com ([209.85.210.48]:52112 "EHLO mail-pz0-f48.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903560Ab2CDFlZ (ORCPT ); Sun, 4 Mar 2012 06:41:25 +0100 Received: by dadp13 with SMTP id p13so3139769dad.35 for ; Sat, 03 Mar 2012 21:41:18 -0800 (PST) Received-SPF: pass (google.com: domain of david.s.daney@gmail.com designates 10.68.201.135 as permitted sender) client-ip=10.68.201.135; Authentication-Results: mr.google.com; spf=pass (google.com: domain of david.s.daney@gmail.com designates 10.68.201.135 as permitted sender) smtp.mail=david.s.daney@gmail.com; dkim=pass header.i=david.s.daney@gmail.com Received: from mr.google.com ([10.68.201.135]) by 10.68.201.135 with SMTP id ka7mr34236018pbc.145.1330839678739 (num_hops = 1); Sat, 03 Mar 2012 21:41:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=S47M9lTqW+jvLz/MwzOCvcmPKQ/biFHDD6cr7d4jVFw=; b=JC/dpqmudkOGESEoDY2CmTks2YmL3ZA46NBo05+OhBSxt8OL0vqWIkRAQcS2nzdBTL /MGOc8L/wZ3G8EEtdMBwDzl0yVZelWLKxVqmak+by5D6qewZwHzxXVVvoDTB7J95obA6 /jdV/9W8Pdnr8lbMFG8wVS4D8dx2KqH6hnfTiGUyKYBmwf5/pE257q8SZLF+Kaxchn8x qvHfgIl//JimK+ZgdEVe490wd2oQC1buTLwuw6gy6NjSZVGx6rUIJcmB8ihTwTRopZHV Scx0WurZbm57kqqZpSp+X5WYV3PSBbARiuNWHqnw5j/isQbv90cqvvimyEGeyBUdg4kR ytKg== Received: by 10.68.201.135 with SMTP id ka7mr29053266pbc.145.1330839678666; Sat, 03 Mar 2012 21:41:18 -0800 (PST) Received: from dd_xps.caveonetworks.com (adsl-67-127-190-10.dsl.pltn13.pacbell.net. [67.127.190.10]) by mx.google.com with ESMTPS id q10sm9633983pbb.10.2012.03.03.21.41.17 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 03 Mar 2012 21:41:18 -0800 (PST) Message-ID: <4F53007C.2030106@gmail.com> Date: Sat, 03 Mar 2012 21:41:16 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.1) Gecko/20120216 Thunderbird/10.0.1 MIME-Version: 1.0 To: Rob Herring CC: David Daney , David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring , linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> <4F52733F.4030807@gmail.com> In-Reply-To: <4F52733F.4030807@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32601 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.s.daney@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2700 Lines: 74 On 03/03/2012 11:38 AM, Rob Herring wrote: > On 03/02/2012 12:03 PM, David Daney wrote: >> + >> + irqd = irq_get_irq_data(irq); >> + irqd->hwirq = line<< 6 | bit; >> + irqd->domain = domain; >>> I think the domain code will set these. >> It is my understanding that the domain code only does this for: >> >> o irq_domain_add_legacy() >> >> o irq_create_direct_mapping() >> >> o irq_create_mapping() >> >> We use none of those. So I do it here. >> >> If there is a better way, I am open to suggestions. > How do you convert local h/w irq controller numbers in the dts to linux > irq #'s? With the calls to octeon_irq_set_ciu_mapping() ... [...] >>>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, >>>> + ciu_domain, chip, handle_level_irq); >>>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, >>>> + ciu_domain, chip, handle_level_irq); >>>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, >>>> + ciu_domain, chip, handle_level_irq); >>>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, >>>> + ciu_domain, chip, handle_level_irq); >>>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, >>>> + ciu_domain, chip, handle_level_irq); >>>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, >>>> + ciu_domain, chip, handle_level_irq); >>>> + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, >>>> + ciu_domain, chip, handle_level_irq); >>>> >>>> [...] >>> edge vs. level should be driven by dts. >>> >> We may have to disagree on this point. Because: >> >> 1) edge vs. level can be accurately probed, as we do here. > Looks like you are just hard coding it here. Where do you read something > that tells you the interrupt is level or edge? We probe for the type of interrupt controller by reading the SOC identifier number, although we can get the same information from the dts. Once we know the type of interrupt controller, the level vs. edge is known a priori, and that knowlege is encoded in all these octeon_irq_set_ciu_mapping() calls. And on top of this... >> 2) The dts doesn't contain the information. >> So it is kind of a moot point. It is not some sort of generic interrupt controller that can be configured in different ways, each line has certain properties endowed upon it by the chip designers, and once a line is assigned a particular configuration, it is never changed in future generations. For external devices attached to the GPIO interrupt lines, things are different, we can only know the triggering via the dts, and lo and behold... it is there and we use it. David Daney From arend@broadcom.com Tue Mar 6 14:28:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Mar 2012 14:28:13 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:1978 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903668Ab2CFN2G (ORCPT ); Tue, 6 Mar 2012 14:28:06 +0100 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 06 Mar 2012 05:37:10 -0800 X-Server-Uuid: 72204117-5C29-4314-8910-60DB108979CB Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Tue, 6 Mar 2012 05:27:33 -0800 Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.17.16.106]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id F3B92BC394; Tue, 6 Mar 2012 05:27:32 -0800 (PST) Received: from [10.0.2.15] (unknown [10.176.68.152]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 1585C207C0; Tue, 6 Mar 2012 05:27:30 -0800 (PST) Message-ID: <4F5610C2.3030101@broadcom.com> Date: Tue, 6 Mar 2012 14:27:30 +0100 From: "Arend van Spriel" User-Agent: Mozilla/5.0 (X11; Linux i686; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: "Hauke Mehrtens" cc: "linville@tuxdriver.com" , "zajec5@gmail.com" , "b43-dev@lists.infradead.org" , "linux-mips@linux-mips.org" , "linux-wireless@vger.kernel.org" , "m@bues.ch" , "ralf@linux-mips.org" Subject: Re: [PATCH v2 07/11] bcma: add support for sprom not found on the device References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> <1330386974-4056-8-git-send-email-hauke@hauke-m.de> In-Reply-To: <1330386974-4056-8-git-send-email-hauke@hauke-m.de> X-WSS-ID: 6348CC8C4GW1029987-01-01 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32602 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arend@broadcom.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1150 Lines: 38 On 02/28/2012 12:56 AM, Hauke Mehrtens wrote: > if (!bus->drv_cc.core) > return -EOPNOTSUPP; > > - if (!(bus->drv_cc.capabilities& BCMA_CC_CAP_SPROM)) > - return -ENOENT; > - > - if (bus->drv_cc.core->id.rev>= 32) { > - sromctrl = bcma_read32(bus->drv_cc.core, BCMA_CC_SROM_CONTROL); > - if (!(sromctrl& BCMA_CC_SROM_CONTROL_PRESENT)) > - return -ENOENT; > + if (!bcma_is_sprom_available(bus)) { > + /* > + * Maybe there is no SPROM on the device? > + * Now we ask the arch code if there is some sprom > + * available for this device in some other storage. > + */ > + err = bcma_fill_sprom_with_fallback(bus,&bus->sprom); > + if (err) { > + pr_warn("Using fallback SPROM failed (err %d)\n", err); Hi Hauke, I just noticed in this patch that the code continues when sprom fallback fails. Does that make sense? I have corrected it in my OTP patch. So if you agree or disagree you can comment on that patch. > + } else { > + pr_debug("Using SPROM revision %d provided by" > + " platform.\n", bus->sprom.revision); > + return 0; > + } > } > > sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), Gr. AvS From miloody@gmail.com Tue Mar 6 14:48:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Mar 2012 14:48:24 +0100 (CET) Received: from mail-tul01m020-f177.google.com ([209.85.214.177]:64925 "EHLO mail-tul01m020-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903665Ab2CFNsK (ORCPT ); Tue, 6 Mar 2012 14:48:10 +0100 Received: by obbta2 with SMTP id ta2so7508429obb.36 for ; Tue, 06 Mar 2012 05:48:04 -0800 (PST) Received-SPF: pass (google.com: domain of miloody@gmail.com designates 10.182.15.70 as permitted sender) client-ip=10.182.15.70; Authentication-Results: mr.google.com; spf=pass (google.com: domain of miloody@gmail.com designates 10.182.15.70 as permitted sender) smtp.mail=miloody@gmail.com; dkim=pass header.i=miloody@gmail.com Received: from mr.google.com ([10.182.15.70]) by 10.182.15.70 with SMTP id v6mr10417190obc.13.1331041684527 (num_hops = 1); Tue, 06 Mar 2012 05:48:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=ruY6QyM8qKEfKMjUXvooYdJHMNupAm8WNlkwEK6lVhw=; b=Lp5zOEz2ueDyqPCE3QYlLsXdJvgKosuHus9QM2XxMPpaanIviUiS2CooO991g1xNcg WiaJgWGfU6XZe2JVo4LV2OLrnPWDjoz3FN51dNh455NdX78RPFU7W1BtrXs6LkULo7k8 AlMugHYLhnLqCHg6v9MbISsKN7hOOasHI0LI0tWVzZoIBaZOR4R/gOHgfmdktP+EafVk LcimFHgpD2kM8h96a5ZfnqR3Un1Y7kpuTWRW9OFyETjtvraUT5ZXK9ga+BgRyasr+11o FSjGaha4/6URunA4+hgy6QpMTy5uab3otUo+PmbLrYIoLJHtdOhH8mzlXQGD7GvYloER X4/Q== MIME-Version: 1.0 Received: by 10.182.15.70 with SMTP id v6mr8946946obc.13.1331041684469; Tue, 06 Mar 2012 05:48:04 -0800 (PST) Received: by 10.60.141.201 with HTTP; Tue, 6 Mar 2012 05:48:04 -0800 (PST) Date: Tue, 6 Mar 2012 21:48:04 +0800 Message-ID: Subject: some questions about mips timer From: loody To: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 32603 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 157 Lines: 8 hi all: I have some questions about mips_hpt_frequency: 1. is mips_hpt_frequency == mips cpu frequency? 2. what does "hpt" mean? -- Appreciate your help, From ffainelli@freebox.fr Tue Mar 6 15:01:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Mar 2012 15:02:15 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:53990 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903665Ab2CFOBv (ORCPT ); Tue, 6 Mar 2012 15:01:51 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id A117E3C27E; Tue, 6 Mar 2012 15:01:50 +0100 (CET) X-Virus-Scanned: amavisd-new at localhost Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hkIUsNOP-rn9; Tue, 6 Mar 2012 15:01:50 +0100 (CET) Received: from zmc.proxad.net (zmc.proxad.net [212.27.53.206]) by zmc.proxad.net (Postfix) with ESMTP id 6A0C436E7F; Tue, 6 Mar 2012 15:01:50 +0100 (CET) Date: Tue, 6 Mar 2012 15:01:50 +0100 (CET) From: Florian Fainelli Reply-To: Florian Fainelli To: loody Cc: Linux MIPS Mailing List Message-ID: <160192556.459513.1331042510355.JavaMail.root@zmc> In-Reply-To: Subject: Re: some questions about mips timer MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Originating-IP: [213.36.7.13] X-Mailer: Zimbra 7.1.4_GA_2555 (ZimbraWebClient - FF3.0 (Linux)/7.1.4_GA_2555) X-archive-position: 32604 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ffainelli@freebox.fr Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 241 Lines: 14 Hi, ----- Mail original ----- > hi all: > I have some questions about mips_hpt_frequency: > 1. is mips_hpt_frequency == mips cpu frequency? No, it is usually cpu frequency / 2. > 2. what does "hpt" mean? High-precision timer. -- Florian From ralf@linux-mips.org Tue Mar 6 20:08:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Mar 2012 20:08:35 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:38414 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903662Ab2CFTIa (ORCPT ); Tue, 6 Mar 2012 20:08:30 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q26J8SZB024838; Tue, 6 Mar 2012 20:08:28 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q26J8QXd024837; Tue, 6 Mar 2012 20:08:26 +0100 Date: Tue, 6 Mar 2012 20:08:26 +0100 From: Ralf Baechle To: Paul Gortmaker Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 0/5] MIPS: module.h usage cleanup. Message-ID: <20120306190826.GJ4519@linux-mips.org> References: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32605 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1095 Lines: 24 On Tue, Feb 28, 2012 at 02:24:43PM -0500, Paul Gortmaker wrote: > Hi Ralf, > > Not a lot to see here, really. MIPS had usages of module.h tucked > away in a couple asm files, and that was masking some of the other > implicit users, plus preventing MIPS from getting the full benefit > of not having to feed module.h to cpp 35,000 times. > > I've left the two drivers/serial commits separate, in case there > is a desire to have them go in via Greg's trees, but they are a > required dependency for the arch/mips fixes, so I think it makes > sense they stay together with the other changes here. > > I will have some arch independent module.h cleanups (in fs and lib) > that will require me to create a module.h tree for 3.4, so I can > carry this there if required. But this lot is all self-contained > to MIPS and so I'd be fine with (and actually prefer) this going in > via the MIPS tree. No strong preference - either way, let me know. Haven't received any comment and the patches are trivial so I'm going to queue them hopeing that Alan Cox (not on cc ...) doesn't mind ... Ralf From paul.gortmaker@windriver.com Tue Mar 6 20:20:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Mar 2012 20:20:52 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:39697 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903657Ab2CFTUq (ORCPT ); Tue, 6 Mar 2012 20:20:46 +0100 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q26JKd68023581 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Tue, 6 Mar 2012 11:20:39 -0800 (PST) Received: from [128.224.146.65] (128.224.146.65) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server id 14.1.255.0; Tue, 6 Mar 2012 11:20:38 -0800 Message-ID: <4F566384.5050501@windriver.com> Date: Tue, 6 Mar 2012 14:20:36 -0500 From: Paul Gortmaker User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.27) Gecko/20120216 Thunderbird/3.1.19 MIME-Version: 1.0 To: Ralf Baechle CC: Subject: Re: [PATCH 0/5] MIPS: module.h usage cleanup. References: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> <20120306190826.GJ4519@linux-mips.org> In-Reply-To: <20120306190826.GJ4519@linux-mips.org> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [128.224.146.65] X-archive-position: 32606 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1408 Lines: 34 On 12-03-06 02:08 PM, Ralf Baechle wrote: > On Tue, Feb 28, 2012 at 02:24:43PM -0500, Paul Gortmaker wrote: > >> Hi Ralf, >> >> Not a lot to see here, really. MIPS had usages of module.h tucked >> away in a couple asm files, and that was masking some of the other >> implicit users, plus preventing MIPS from getting the full benefit >> of not having to feed module.h to cpp 35,000 times. >> >> I've left the two drivers/serial commits separate, in case there >> is a desire to have them go in via Greg's trees, but they are a >> required dependency for the arch/mips fixes, so I think it makes >> sense they stay together with the other changes here. >> >> I will have some arch independent module.h cleanups (in fs and lib) >> that will require me to create a module.h tree for 3.4, so I can >> carry this there if required. But this lot is all self-contained >> to MIPS and so I'd be fine with (and actually prefer) this going in >> via the MIPS tree. No strong preference - either way, let me know. > > Haven't received any comment and the patches are trivial so I'm going > to queue them hopeing that Alan Cox (not on cc ...) doesn't mind ... I stuck them in linux-next for additional sanity testing above the defconfig builds that I did and nothing caught fire. I'll back them out from my for-next branch now that I know you've got them queued via the mips for-next. Thanks! Paul. > > Ralf From ralf@linux-mips.org Tue Mar 6 20:57:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Mar 2012 20:57:09 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:33427 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903663Ab2CFT5F (ORCPT ); Tue, 6 Mar 2012 20:57:05 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q26Jv2G6027978; Tue, 6 Mar 2012 20:57:02 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q26Jv0AZ027977; Tue, 6 Mar 2012 20:57:00 +0100 Date: Tue, 6 Mar 2012 20:57:00 +0100 From: Ralf Baechle To: Grant Likely Cc: linux-kernel@vger.kernel.org, Rob Herring , Thomas Gleixner , linux-mips@linux-mips.org Subject: Re: [PATCH] irq_domain/mips: Allow irq_domain on MIPS Message-ID: <20120306195700.GK4519@linux-mips.org> References: <1330100995-19823-1-git-send-email-grant.likely@secretlab.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1330100995-19823-1-git-send-email-grant.likely@secretlab.ca> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32607 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 431 Lines: 15 On Fri, Feb 24, 2012 at 09:29:55AM -0700, Grant Likely wrote: > This patch makes IRQ_DOMAIN usable on MIPS. It uses an ugly workaround > to preserve current behaviour so that MIPS has time to add irq_domain > registration to the irq controller drivers. The workaround will be > removed in Linux v3.6 Looking good, Ack. Is there any good example for the changes that need to be done to irq controller drivers? Thanks, Ralf From ralf@linux-mips.org Tue Mar 6 21:13:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Mar 2012 21:13:14 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37948 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903662Ab2CFUNK (ORCPT ); Tue, 6 Mar 2012 21:13:10 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q26KD5Uu028943; Tue, 6 Mar 2012 21:13:05 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q26KD1CO028937; Tue, 6 Mar 2012 21:13:01 +0100 Date: Tue, 6 Mar 2012 21:13:01 +0100 From: Ralf Baechle To: David Daney Cc: Greg Kroah-Hartman , linux-mips@linux-mips.org, devel@driverdev.osuosl.org, David Daney , Florian Fainelli Subject: Re: [PATCH] staging/octeon: Fix PHY binding in octeon-ethernet driver. Message-ID: <20120306201301.GL4519@linux-mips.org> References: <1330024771-25396-1-git-send-email-ddaney.cavm@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1330024771-25396-1-git-send-email-ddaney.cavm@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32608 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 714 Lines: 17 On Thu, Feb 23, 2012 at 11:19:31AM -0800, David Daney wrote: > Date: Thu, 23 Feb 2012 11:19:31 -0800 > From: David Daney > To: Greg Kroah-Hartman > Cc: linux-mips@linux-mips.org, devel@driverdev.osuosl.org, David Daney > , Florian Fainelli > Subject: [PATCH] staging/octeon: Fix PHY binding in octeon-ethernet driver. > > From: David Daney > > Commit d6c25be (mdio-octeon: use an unique MDIO bus name.) changed the > names used to refer to MDIO buses. The ethernet driver must be > changed to match, so that the PHY drivers can be attached. No objections heared, so applied. Ralf From ralf@linux-mips.org Tue Mar 6 21:27:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Mar 2012 21:27:20 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:54391 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903662Ab2CFU1P (ORCPT ); Tue, 6 Mar 2012 21:27:15 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q26KRD2L029705; Tue, 6 Mar 2012 21:27:13 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q26KRC1L029704; Tue, 6 Mar 2012 21:27:12 +0100 Date: Tue, 6 Mar 2012 21:27:12 +0100 From: Ralf Baechle To: Florian Fainelli Cc: loody , Linux MIPS Mailing List Subject: Re: some questions about mips timer Message-ID: <20120306202712.GM4519@linux-mips.org> References: <160192556.459513.1331042510355.JavaMail.root@zmc> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <160192556.459513.1331042510355.JavaMail.root@zmc> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32609 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 943 Lines: 26 On Tue, Mar 06, 2012 at 03:01:50PM +0100, Florian Fainelli wrote: > > hi all: > > I have some questions about mips_hpt_frequency: > > 1. is mips_hpt_frequency == mips cpu frequency? > > No, it is usually cpu frequency / 2. The architecture specification leaves the counter clock rate up up to the implementation and only says the clock rate is a function of the pipeline clock. In all reality this means the counter is running at the full or half frequency. Just don't build on it, clock := pipeline_clock * next_weeks_lottery_number % 42 would by compliant ;-) On some CPUs the frequency can even be selected through a configuration bitstream at reset time so you can't always count on a fixed relation between CPU clock and count rate. Some older CPU manuals contain a confusing wording saying the counter increments at half (or full) instruction issue rate. That just means the pipeline clock, no reason to be confused. Ralf From ddaney.cavm@gmail.com Tue Mar 6 21:33:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Mar 2012 21:34:09 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:45894 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903657Ab2CFUdx (ORCPT ); Tue, 6 Mar 2012 21:33:53 +0100 Received: by ghbf11 with SMTP id f11so2765612ghb.36 for ; Tue, 06 Mar 2012 12:33:47 -0800 (PST) Received-SPF: pass (google.com: domain of ddaney.cavm@gmail.com designates 10.60.4.106 as permitted sender) client-ip=10.60.4.106; Authentication-Results: mr.google.com; spf=pass (google.com: domain of ddaney.cavm@gmail.com designates 10.60.4.106 as permitted sender) smtp.mail=ddaney.cavm@gmail.com; dkim=pass header.i=ddaney.cavm@gmail.com Received: from mr.google.com ([10.60.4.106]) by 10.60.4.106 with SMTP id j10mr9743044oej.47.1331066027145 (num_hops = 1); Tue, 06 Mar 2012 12:33:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=5ABuA5uQ3aS3SpgjTH4heFBWxsxfvaTPNSJAg3xjWYg=; b=nbHIo2Wig7ojbruPhzlNGXgtIVfN8dWhhuCWxVr/IF/8EXnfPJ4repAaonxE/275zE io63HM+huhCRHQtR7EUucvE8zO+coAu3SnypJiYP2yLMP7LxEZ4ADpgweFXhJVSFw4/3 4Nf4zu4YQSfDmQf4ThBVVhTDAcvru9/S1LATyZF/ofC3DcwowBVoZquP3isEPZQRi+pS MpzoR04LPVMsCLXut5N9MVTomq3VZw84cYa7OrLSiTHOToAW6OvvDyOZ4QkkBSjXVtYs 3sc8TUK39YiyDhAThgu62ewnE62uHY/FIbo9W7JVl8gBEEY6CilChsZC+i2YpQHBxsu3 pGEA== Received: by 10.60.4.106 with SMTP id j10mr8581465oej.47.1331066027111; Tue, 06 Mar 2012 12:33:47 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id n1sm1088988oen.8.2012.03.06.12.33.45 (version=SSLv3 cipher=OTHER); Tue, 06 Mar 2012 12:33:46 -0800 (PST) Message-ID: <4F5674A8.3040605@gmail.com> Date: Tue, 06 Mar 2012 12:33:44 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Ralf Baechle CC: Florian Fainelli , loody , Linux MIPS Mailing List Subject: Re: some questions about mips timer References: <160192556.459513.1331042510355.JavaMail.root@zmc> <20120306202712.GM4519@linux-mips.org> In-Reply-To: <20120306202712.GM4519@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32610 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1166 Lines: 32 On 03/06/2012 12:27 PM, Ralf Baechle wrote: > On Tue, Mar 06, 2012 at 03:01:50PM +0100, Florian Fainelli wrote: > >>> hi all: >>> I have some questions about mips_hpt_frequency: >>> 1. is mips_hpt_frequency == mips cpu frequency? >> >> No, it is usually cpu frequency / 2. > > The architecture specification leaves the counter clock rate up up to the > implementation and only says the clock rate is a function of the pipeline > clock. In all reality this means the counter is running at the full or > half frequency. Just don't build on it, > > clock := pipeline_clock * next_weeks_lottery_number % 42 > > would by compliant ;-) > > On some CPUs the frequency can even be selected through a configuration > bitstream at reset time so you can't always count on a fixed relation > between CPU clock and count rate. > > Some older CPU manuals contain a confusing wording saying the counter > increments at half (or full) instruction issue rate. That just means the > pipeline clock, no reason to be confused. > If you have a v2 or later ISA, you can use 'rdhwr x, $3' to find the ratio between the clock rate and the increment rate of the timer. David Daney From ddaney.cavm@gmail.com Wed Mar 7 00:08:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Mar 2012 00:08:54 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:61035 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903662Ab2CFXIh (ORCPT ); Wed, 7 Mar 2012 00:08:37 +0100 Received: by yhjj52 with SMTP id j52so2863435yhj.36 for ; Tue, 06 Mar 2012 15:08:30 -0800 (PST) Received-SPF: pass (google.com: domain of ddaney.cavm@gmail.com designates 10.60.12.8 as permitted sender) client-ip=10.60.12.8; Authentication-Results: mr.google.com; spf=pass (google.com: domain of ddaney.cavm@gmail.com designates 10.60.12.8 as permitted sender) smtp.mail=ddaney.cavm@gmail.com; dkim=pass header.i=ddaney.cavm@gmail.com Received: from mr.google.com ([10.60.12.8]) by 10.60.12.8 with SMTP id u8mr12060860oeb.60.1331075310725 (num_hops = 1); Tue, 06 Mar 2012 15:08:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=Ad1pMW43YCX/dGNCiBMbKZu+xhagVyKRn8lRoV27V1M=; b=PA6AcduShsWyxAT77B8zEgEhbPDzmg3CslDQOPrF8m1uolcX/XL5RucA48kBXMufdx gRgRb93dkH765vb/+9LWhjLmMPrvS8Ligv9b+avJ3U4Q7xaEurebQXg8zhJxUlP/o9Qg /len/y77peoe/ytUQquj3HmAPasFcKEJMGLRdSkV4THe9fPSDykbkXGWkYY6+DFCYb/a lgi+mLnxbUYIqhhiX/y39XXz44jL6Gpb6N7RtNP8ua4dyDpBnAUr7tO6Ta316l+xAfjp SInRKl2SXDLDHf2MXBPquP0bFSaeMKbfTIrKfZcZOizF56wAivrldfh5PpypPebGSNFU brkQ== Received: by 10.60.12.8 with SMTP id u8mr10425743oeb.60.1331075310663; Tue, 06 Mar 2012 15:08:30 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id vy18sm19223436obc.8.2012.03.06.15.08.29 (version=SSLv3 cipher=OTHER); Tue, 06 Mar 2012 15:08:30 -0800 (PST) Message-ID: <4F5698EC.1080502@gmail.com> Date: Tue, 06 Mar 2012 15:08:28 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Ralf Baechle CC: Grant Likely , linux-kernel@vger.kernel.org, Rob Herring , Thomas Gleixner , linux-mips@linux-mips.org Subject: Re: [PATCH] irq_domain/mips: Allow irq_domain on MIPS References: <1330100995-19823-1-git-send-email-grant.likely@secretlab.ca> <20120306195700.GK4519@linux-mips.org> In-Reply-To: <20120306195700.GK4519@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32611 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1117 Lines: 35 On 03/06/2012 11:57 AM, Ralf Baechle wrote: > On Fri, Feb 24, 2012 at 09:29:55AM -0700, Grant Likely wrote: > >> This patch makes IRQ_DOMAIN usable on MIPS. It uses an ugly workaround >> to preserve current behaviour so that MIPS has time to add irq_domain >> registration to the irq controller drivers. The workaround will be >> removed in Linux v3.6 > > Looking good, Ack. > > Is there any good example for the changes that need to be done to > irq controller drivers? > Well it only affects things that have USE_OF, so most mips things will not need to do anything as they don't USE_OF. But for those that do USE_OF, you have to call one or more of the irq_domain_add_*() functions. Slightly off topic: My OCTEON patch set tries to do this, but hasn't met with quite as much enthusiasm as I would have liked... David Daney > Thanks, > > Ralf > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ > From antonynpavlov@gmail.com Wed Mar 7 09:19:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Mar 2012 09:20:11 +0100 (CET) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:34148 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901171Ab2CGITz (ORCPT ); Wed, 7 Mar 2012 09:19:55 +0100 Received: by lagy4 with SMTP id y4so9289587lag.36 for ; Wed, 07 Mar 2012 00:19:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=zRsfJqxctb4U+s/tBt+a0lrEHa893vFHoH5xG+pZyBQ=; b=MpbIMrFWClwoCn2iz5ySRDwOrGQHoNCvlUy5PHMiq0zl5QIj8MCXDVS4keV5S6pSk9 87/5Anl6BWCRIz+3JZgmfeR8C7pmvS6S4AHQWzGos8tpFglce+amqVW6fo/fCKXbltcL VOYbEETGcQLdCsN5qCxCctwGwMwmN8Y6aD/CcgFf93jTokcIq5SnyF/siU8l0R9um4Sv XEWAwAyQNWGZ1vtH0O+qz8Qxz6VX0P7FDgiPrZaBLOGbIn3zVLLOKxgcYSwmFix5ZJ8f MxT0QCAnTl2accITCfywayIcbkPWzjihvI2EyOpmGC4FiwTpUovWPqwP+aM43fQS9zlE QR1A== Received: by 10.112.85.136 with SMTP id h8mr375245lbz.72.1331108389317; Wed, 07 Mar 2012 00:19:49 -0800 (PST) Received: from quince.NIISI (t35.niisi.ras.ru. [193.232.173.35]) by mx.google.com with ESMTPS id k10sm32361667lbu.1.2012.03.07.00.19.48 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Mar 2012 00:19:48 -0800 (PST) From: Antony Pavlov To: Ralf Baechle Cc: Lars-Peter Clausen , linux-mips@linux-mips.org, Antony Pavlov Subject: [PATCH] MIPS: JZ4740: fix the JZ4740_IRQ_DMA macro Date: Wed, 7 Mar 2012 12:19:43 +0400 Message-Id: <1331108383-11308-1-git-send-email-antonynpavlov@gmail.com> X-Mailer: git-send-email 1.7.8.3 X-archive-position: 32612 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: antonynpavlov@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 690 Lines: 21 Signed-off-by: Antony Pavlov --- arch/mips/include/asm/mach-jz4740/irq.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h index a865c98..5ad1a9c 100644 --- a/arch/mips/include/asm/mach-jz4740/irq.h +++ b/arch/mips/include/asm/mach-jz4740/irq.h @@ -45,7 +45,7 @@ #define JZ4740_IRQ_LCD JZ4740_IRQ(30) /* 2nd-level interrupts */ -#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X)) +#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (x)) #define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x)) #define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x)) -- 1.7.8.3 From veli-pekka.peltola@bluegiga.com Wed Mar 7 14:10:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Mar 2012 14:10:48 +0100 (CET) Received: from bluegiga.fi ([194.100.31.45]:16222 "EHLO darkblue.bluegiga.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903683Ab2CGNKm (ORCPT ); Wed, 7 Mar 2012 14:10:42 +0100 Received: from bluegiga.com ([10.1.1.102]) by darkblue.bluegiga.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 7 Mar 2012 15:10:38 +0200 Received: by bluegiga.com (sSMTP sendmail emulation); Wed, 07 Mar 2012 15:10:34 +0200 From: Veli-Pekka Peltola To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org, Veli-Pekka Peltola , Russell King , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org Subject: [PATCH v2] mm: module_alloc: check if size is 0 Date: Wed, 7 Mar 2012 15:09:28 +0200 Message-Id: <1331125768-25454-1-git-send-email-veli-pekka.peltola@bluegiga.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com> References: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com> X-OriginalArrivalTime: 07 Mar 2012 13:10:38.0247 (UTC) FILETIME=[B0A50B70:01CCFC63] X-archive-position: 32613 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: veli-pekka.peltola@bluegiga.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2393 Lines: 70 After commit de7d2b567d040e3b67fe7121945982f14343213d (mm/vmalloc.c: report more vmalloc failures) users will get a warning if vmalloc_node_range() is called with size 0. This happens if module's init size equals to 0. This patch changes ARM, MIPS and x86 module_alloc() to return NULL before calling vmalloc_node_range() that would also return NULL and print a warning. Signed-off-by: Veli-Pekka Peltola Cc: Russell King Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org --- I found this with ARM but after checking out various implementations of module_alloc() I thought it would be better to fix all at once. One way to replicate the warning: compile kernel with CONFIG_KALLSYMS=n insmod a module without init, I used usb-common.ko Changes since v1: - changed style as hpa suggested arch/arm/kernel/module.c | 2 ++ arch/mips/kernel/module.c | 2 ++ arch/x86/kernel/module.c | 2 +- 3 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 1e9be5d..17648e2 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -39,6 +39,8 @@ #ifdef CONFIG_MMU void *module_alloc(unsigned long size) { + if (!size) + return NULL; return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, GFP_KERNEL, PAGE_KERNEL_EXEC, -1, __builtin_return_address(0)); diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index a5066b1..1a51de1 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -47,6 +47,8 @@ static DEFINE_SPINLOCK(dbe_lock); #ifdef MODULE_START void *module_alloc(unsigned long size) { + if (!size) + return NULL; return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, GFP_KERNEL, PAGE_KERNEL, -1, __builtin_return_address(0)); diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c index 925179f..fd44d69 100644 --- a/arch/x86/kernel/module.c +++ b/arch/x86/kernel/module.c @@ -38,7 +38,7 @@ void *module_alloc(unsigned long size) { - if (PAGE_ALIGN(size) > MODULES_LEN) + if (!size || PAGE_ALIGN(size) > MODULES_LEN) return NULL; return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC, -- 1.7.5.4 From ralf@linux-mips.org Wed Mar 7 15:07:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Mar 2012 15:08:10 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59582 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903687Ab2CGOHk (ORCPT ); Wed, 7 Mar 2012 15:07:40 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q27E7dun024532; Wed, 7 Mar 2012 15:07:39 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q27E7c7w024524; Wed, 7 Mar 2012 15:07:38 +0100 Date: Wed, 7 Mar 2012 15:07:37 +0100 From: Ralf Baechle To: Antony Pavlov Cc: Lars-Peter Clausen , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: JZ4740: fix the JZ4740_IRQ_DMA macro Message-ID: <20120307140737.GC15155@linux-mips.org> References: <1331108383-11308-1-git-send-email-antonynpavlov@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1331108383-11308-1-git-send-email-antonynpavlov@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32614 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 89 Lines: 5 On Wed, Mar 07, 2012 at 12:19:43PM +0400, Antony Pavlov wrote: Thanks, applied! Ralf From macro@codesourcery.com Tue Mar 6 21:29:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Mar 2012 16:54:30 +0100 (CET) Received: from relay1.mentorg.com ([192.94.38.131]:44012 "EHLO relay1.mentorg.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903657Ab2CFU3M (ORCPT ); Tue, 6 Mar 2012 21:29:12 +0100 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1S510M-000768-9N from Maciej_Rozycki@mentor.com ; Tue, 06 Mar 2012 12:29:06 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 6 Mar 2012 12:29:05 -0800 Received: from [172.30.11.135] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Tue, 6 Mar 2012 20:29:03 +0000 Date: Tue, 6 Mar 2012 20:28:54 +0000 From: "Maciej W. Rozycki" To: Ralf Baechle CC: "Maciej W. Rozycki" , Subject: [ping][PATCH] Handle COP3 Unusable exception as COP1X for FP emulation Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-OriginalArrivalTime: 06 Mar 2012 20:29:05.0942 (UTC) FILETIME=[C6D6FB60:01CCFBD7] X-archive-position: 32615 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@codesourcery.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2716 Lines: 76 Our FP emulator is hardcoded for the MIPS IV FP instruction set and does not match the FP ISA with the general ISA. However for the few MIPS IV FP instructions that use the COP1X major opcode it relies on the Coprocessor Unusable exception to be delivered as a COP1 rather than COP3 exception. This includes indexed transfer (LDXC1, etc.) and FP multiply-accumulate (MADD.D, etc.) instructions. All the MIPS I and MIPS II processors and some newer chips that do not implement the FPU use the COP3 exception however. Therefore I believe the kernel should follow and redirect any COP3 Unusable traps to the emulator unless an actual FPU part or core is present. This is a change that implements it. Any minor opcode encodings that are not recognised as valid FP instructions are rejected by the emulator and will result in a SIGILL signal being delivered as they currently do. We do not support vendor-specific coprocessor 3 implementations supported with MIPS I and MIPS II ISA processors; we never set CP0.Status.CU3. If matching between the CPU and the FPU ISA is considered required one day, this can still be done in the emulator itself. I think the CpU exception dispatcher is not the right place to do this anyway, as there are further differences between MIPS I, MIPS II, MIPS III, MIPS IV and MIPS32 FP ISAs. Corresponding explanation of this implementation is included within the change itself. Signed-off-by: Maciej W. Rozycki --- Ralf, Any progress with this change? Maciej patch-3.2.0-rc4-do-cpu-cop3-1 diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index c6fc6a0..b86eb3d 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1066,6 +1066,24 @@ asmlinkage void do_cpu(struct pt_regs *regs) return; + case 3: + /* + * Old (MIPS I and MIPS II) processors will set this code + * for COP1X opcode instructions that replaced the original + * COP3 space. We don't limit COP1 space instructions in + * the emulator according to the CPU ISA, so we want to + * treat COP1X instructions consistently regardless of which + * code the CPU chose. Therefore we redirect this trap to + * the FP emulator too. + * + * Then some newer FPU-less processors use this code + * erroneously too, so they are covered by this choice + * as well. + */ + if (raw_cpu_has_fpu) + break; + /* Fall through. */ + case 1: if (used_math()) /* Using the FPU again. */ own_fpu(1); @@ -1089,9 +1107,6 @@ asmlinkage void do_cpu(struct pt_regs *regs) case 2: raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); return; - - case 3: - break; } force_sig(SIGILL, current); From ralf@linux-mips.org Wed Mar 7 17:44:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Mar 2012 17:45:01 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:45379 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903689Ab2CGQoy (ORCPT ); Wed, 7 Mar 2012 17:44:54 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q27Gip9W032729; Wed, 7 Mar 2012 17:44:52 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q27Gin89032728; Wed, 7 Mar 2012 17:44:49 +0100 Date: Wed, 7 Mar 2012 17:44:49 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: "Maciej W. Rozycki" , linux-mips@linux-mips.org Subject: Re: [ping][PATCH] Handle COP3 Unusable exception as COP1X for FP emulation Message-ID: <20120307164448.GA32101@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32616 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 495 Lines: 15 On Tue, Mar 06, 2012 at 08:28:54PM +0000, Maciej W. Rozycki wrote: > Subject: [ping][PATCH] Handle COP3 Unusable exception as COP1X for FP The list's spam filter ate both this and your your original posting and thus the patch also didn't make it to patchwork, whoops... I've modified the offending test to avoid this from repeating and would like to encourageusers who experience problems posting to contact me off the list. The patch itself looks good and I've applied it. Thanks! Ralf From macro@codesourcery.com Wed Mar 7 20:40:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Mar 2012 20:40:15 +0100 (CET) Received: from relay1.mentorg.com ([192.94.38.131]:51858 "EHLO relay1.mentorg.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903691Ab2CGTkJ (ORCPT ); Wed, 7 Mar 2012 20:40:09 +0100 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1S5MiV-0003gy-4t from Maciej_Rozycki@mentor.com ; Wed, 07 Mar 2012 11:40:07 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 7 Mar 2012 11:39:59 -0800 Received: from [172.30.11.135] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Wed, 7 Mar 2012 19:40:05 +0000 Date: Wed, 7 Mar 2012 19:39:56 +0000 From: "Maciej W. Rozycki" To: Ralf Baechle CC: "Maciej W. Rozycki" , Subject: Re: [ping][PATCH] Handle COP3 Unusable exception as COP1X for FP emulation In-Reply-To: <20120307164448.GA32101@linux-mips.org> Message-ID: References: <20120307164448.GA32101@linux-mips.org> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-OriginalArrivalTime: 07 Mar 2012 19:39:59.0406 (UTC) FILETIME=[14FB04E0:01CCFC9A] X-archive-position: 32617 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@codesourcery.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 128 Lines: 7 On Wed, 7 Mar 2012, Ralf Baechle wrote: > The patch itself looks good and I've applied it. Thanks for your review. Maciej From bhelgaas@google.com Wed Mar 7 23:32:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Mar 2012 23:33:01 +0100 (CET) Received: from mail-lpp01m010-f73.google.com ([209.85.215.73]:40938 "EHLO mail-lpp01m010-f73.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903688Ab2CGWcq (ORCPT ); Wed, 7 Mar 2012 23:32:46 +0100 Received: by laah2 with SMTP id h2so219602laa.0 for ; Wed, 07 Mar 2012 14:32:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=pFi8IOaM0Mg3d1z6XWls3pdXdM4Wb5twPWGg8IPxZVI=; b=A+hZuYmuZWwwZMUYaMQ8TruyoyJRBufHWAiDBzFLtDei/hNTMEYcE6XYcp/3oriCiN EazMZQRl5w3WBT3U412nEymPk0ltFkTesaocx6nsCxDQKNsaqncoOtX6kjrMmOT3WDKM qEfNCrogjUd8oYk+UVqQ2ercXGL9KWxZ0OXxa9m9rMaD2qZe6DJB6jhaYRHFWwCQhJsk UXYiT/F3FCQKeeo1nggXW7Zz+hNef+3T2rgVta1PHWYmUEhQhRbaFVNovs8vfEpZ662P 7IySzcktr5jQvt8ZtdW2KIvXTewX/XQlnN0l9P7+LlzMJ54Pq0SRK0/JLZjek/Y8oIW3 b5pw== Received: by 10.14.203.134 with SMTP id f6mr1436191eeo.0.1331159560735; Wed, 07 Mar 2012 14:32:40 -0800 (PST) Received: by 10.14.203.134 with SMTP id f6mr1436170eeo.0.1331159560627; Wed, 07 Mar 2012 14:32:40 -0800 (PST) Received: from hpza10.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id y56si17197286eea.1.2012.03.07.14.32.40 (version=TLSv1/SSLv3 cipher=AES128-SHA); Wed, 07 Mar 2012 14:32:40 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by hpza10.eem.corp.google.com (Postfix) with ESMTP id 483C720004E; Wed, 7 Mar 2012 14:32:40 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id A9DA7180146; Wed, 7 Mar 2012 14:32:39 -0800 (PST) Subject: [PATCH v3 07/34] mips/PCI: replace pci_probe_only with pci_flags To: Jesse Barnes From: Bjorn Helgaas Cc: linux-arch@vger.kernel.org, linux-pci@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org Date: Wed, 07 Mar 2012 15:32:39 -0700 Message-ID: <20120307223239.25669.48116.stgit@bhelgaas.mtv.corp.google.com> In-Reply-To: <20120307222436.25669.52282.stgit@bhelgaas.mtv.corp.google.com> References: <20120307222436.25669.52282.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQnjSaXBsLv/JNL+zOxz17/7MMcxUW4M8k0kwnhxMWG/yxNCIzreahWcOQ8y9galJAjF9G0v95WPi/IdotXTTjPhGHaa77SIIEoQYD/krHADdjHmPQtAohrwzDnsJVKRRoQ4RzI1MbumeWvnOX4XfMV4QdOWvvAN8fPKhAkqf8tkRYP7Rhw= X-archive-position: 32618 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5018 Lines: 152 Some architectures (alpha, mips, powerpc) have an arch-specific "pci_probe_only" flag. Others use PCI_PROBE_ONLY in pci_flags for the same purpose. This moves mips to the pci_flags approach so generic code can use the same test across all architectures. CC: Ralf Baechle CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas --- arch/mips/include/asm/pci.h | 3 +-- arch/mips/pci/pci-bcm1480.c | 2 +- arch/mips/pci/pci-ip27.c | 2 +- arch/mips/pci/pci-lantiq.c | 3 ++- arch/mips/pci/pci-sb1250.c | 2 +- arch/mips/pci/pci-xlr.c | 2 +- arch/mips/pci/pci.c | 13 +++++-------- 7 files changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 576397c..1e4fa3d 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -92,6 +92,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, #include #include #include +#include struct pci_dev; @@ -145,8 +146,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) #define arch_setup_msi_irqs arch_setup_msi_irqs #endif -extern int pci_probe_only; - extern char * (*pcibios_plat_setup)(char *str); #endif /* _ASM_PCI_H */ diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index af8c319..37b52dc 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -204,7 +204,7 @@ static int __init bcm1480_pcibios_init(void) uint64_t reg; /* CFE will assign PCI resources */ - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); /* Avoid ISA compat ranges. */ PCIBIOS_MIN_IO = 0x00008000UL; diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 193e949..0fbe4c0 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -50,7 +50,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) bridge_t *bridge; int slot; - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); printk("a bridge\n"); diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index be1e1af..030c77e 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -270,7 +270,8 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev) { struct ltq_pci_data *ltq_pci_data = (struct ltq_pci_data *) pdev->dev.platform_data; - pci_probe_only = 0; + + pci_clear_flags(PCI_PROBE_ONLY); ltq_pci_irq_map = ltq_pci_data->irq; ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); ltq_pci_mapped_cfg = diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 1711e8e..dd97f3a 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -213,7 +213,7 @@ static int __init sb1250_pcibios_init(void) uint64_t reg; /* CFE will assign PCI resources */ - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); /* Avoid ISA compat ranges. */ PCIBIOS_MIN_IO = 0x00008000UL; diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 3d701a9..1644805 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -292,7 +292,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) static int __init pcibios_init(void) { /* PSB assigns PCI resources */ - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); /* Extend IO port for memory mapped io */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index aec2b11..2a11045 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -20,12 +20,9 @@ #include /* - * Indicate whether we respect the PCI setup left by the firmware. - * - * Make this long-lived so that we know when shutting down - * whether we probed only or not. + * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource + * assignments. */ -int pci_probe_only; #define PCI_ASSIGN_ALL_BUSSES 1 @@ -92,7 +89,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) if (!hose->iommu) PCI_DMA_BUS_IS_PHYS = 1; - if (hose->get_busno && pci_probe_only) + if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) next_busno = (*hose->get_busno)(); pci_add_resource(&resources, hose->mem_resource); @@ -115,7 +112,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) need_domain_info = 1; } - if (!pci_probe_only) { + if (!pci_has_flag(PCI_PROBE_ONLY)) { pci_bus_size_bridges(bus); pci_bus_assign_resources(bus); pci_enable_bridges(bus); @@ -282,7 +279,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) struct list_head *ln; struct pci_dev *dev = bus->self; - if (pci_probe_only && dev && + if (pci_has_flag(PCI_PROBE_ONLY) && dev && (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { pci_read_bridge_bases(bus); pcibios_fixup_device_resources(dev, bus); From bhelgaas@google.com Wed Mar 7 23:32:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Mar 2012 23:33:37 +0100 (CET) Received: from mail-gy0-f201.google.com ([209.85.160.201]:47950 "EHLO mail-gy0-f201.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903700Ab2CGWcv (ORCPT ); Wed, 7 Mar 2012 23:32:51 +0100 Received: by ghbg15 with SMTP id g15so844108ghb.0 for ; Wed, 07 Mar 2012 14:32:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=+1Tg68MUrUdkYJBPf4zZzIhJOCahvnx2JOmPQ3BE2v4=; b=jV+gRFxUxQ2LdKfGf37aSgyV2gVsyAhqMajHTtuiV+jwfLTmS5BdB8XFQg2FKIfPGV ALX9QXxEPP0tF7PYdeUYaqAlTv01eru6AyZI8NvpsXbCzKOJvDjeQGVVoxHdnDK0MU75 U2TJlIHvBiZDxiJenKkTzgF8Ff6V68auurGRKy+8WArkU9O2sJf7wriqtsNehPKYuM/u N3TCHCM/wB+pDJrds2iVYTruTKvulgjOPT2Ani4D2BOvC7ERsd2MQpJsKd4BfoKs7T7A tpiCw+irU73bxJv5qWopJ90RC/Kf7CKkaPlJKT8Z46GfKv4/FUnmvgj+Te6QUPm8WfSR aIAQ== Received: by 10.101.112.3 with SMTP id p3mr1488077anm.0.1331159565359; Wed, 07 Mar 2012 14:32:45 -0800 (PST) Received: by 10.101.112.3 with SMTP id p3mr1488055anm.0.1331159565214; Wed, 07 Mar 2012 14:32:45 -0800 (PST) Received: from wpzn4.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id e44si13396157yhk.0.2012.03.07.14.32.45 (version=TLSv1/SSLv3 cipher=AES128-SHA); Wed, 07 Mar 2012 14:32:45 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by wpzn4.hot.corp.google.com (Postfix) with ESMTP id 1D92A1E004D; Wed, 7 Mar 2012 14:32:45 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id C1C1B180146; Wed, 7 Mar 2012 14:32:44 -0800 (PST) Subject: [PATCH v3 08/34] mips/PCI: removed unused pci_probe configurability To: Jesse Barnes From: Bjorn Helgaas Cc: linux-arch@vger.kernel.org, linux-pci@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org Date: Wed, 07 Mar 2012 15:32:44 -0700 Message-ID: <20120307223244.25669.85258.stgit@bhelgaas.mtv.corp.google.com> In-Reply-To: <20120307222436.25669.52282.stgit@bhelgaas.mtv.corp.google.com> References: <20120307222436.25669.52282.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQmg8AXmo33Fge+vxlvmsDIOqMyPnuAokI4CCGuAD0FwPfItJLXOGK6ISqfU/OIqYQbM/dwPuwQHgqQgdh4C+IP33RMoor3spv2grhppFcqtTK1Ngb7FwJyg1lO7LwVnNi/4zvItuqSoLhFmURTLBVMYGN+UFThB/n4VGPRyOGfX5HP/Vl0= X-archive-position: 32619 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1018 Lines: 37 We never assign anything other than PCI_ASSIGN_ALL_BUSSES to pci_probe, so just remove the indirection. If configurability is required in the future, please use the pci_flags/PCI_REASSIGN_ALL_BUS functionality as is done for powerpc. CC: Ralf Baechle CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas --- arch/mips/pci/pci.c | 6 +----- 1 files changed, 1 insertions(+), 5 deletions(-) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 2a11045..19f6d19 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -24,10 +24,6 @@ * assignments. */ -#define PCI_ASSIGN_ALL_BUSSES 1 - -unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; - /* * The PCI controller list. */ @@ -238,7 +234,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) unsigned int pcibios_assign_all_busses(void) { - return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; + return 1; } int pcibios_enable_device(struct pci_dev *dev, int mask) From macro@codesourcery.com Mon Dec 12 22:07:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Mar 2012 10:39:33 +0100 (CET) Received: from relay1.mentorg.com ([192.94.38.131]:56829 "EHLO relay1.mentorg.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903738Ab1LLVHv (ORCPT ); Mon, 12 Dec 2011 22:07:51 +0100 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1RaD6B-0003aM-Tt from Maciej_Rozycki@mentor.com ; Mon, 12 Dec 2011 13:07:47 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 12 Dec 2011 13:07:47 -0800 Received: from [172.30.7.78] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Mon, 12 Dec 2011 21:07:44 +0000 Date: Mon, 12 Dec 2011 21:07:35 +0000 From: "Maciej W. Rozycki" To: Ralf Baechle CC: "Maciej W. Rozycki" , Subject: [PATCH] Handle COP3 Unusable exception as COP1X for FP emulation Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-OriginalArrivalTime: 12 Dec 2011 21:07:47.0246 (UTC) FILETIME=[19551CE0:01CCB912] X-archive-position: 32620 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@codesourcery.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2848 Lines: 78 Our FP emulator is hardcoded for the MIPS IV FP instruction set and does not match the FP ISA with the general ISA. However for the few MIPS IV FP instructions that use the COP1X major opcode it relies on the Coprocessor Unusable exception to be delivered as a COP1 rather than COP3 exception. This includes indexed transfer (LDXC1, etc.) and FP multiply-accumulate (MADD.D, etc.) instructions. All the MIPS I and MIPS II processors and some newer chips that do not implement the FPU use the COP3 exception however. Therefore I believe the kernel should follow and redirect any COP3 Unusable traps to the emulator unless an actual FPU part or core is present. This is a change that implements it. Any minor opcode encodings that are not recognised as valid FP instructions are rejected by the emulator and will result in a SIGILL signal being delivered as they currently do. We do not support vendor-specific coprocessor 3 implementations supported with MIPS I and MIPS II ISA processors; we never set CP0.Status.CU3. If matching between the CPU and the FPU ISA is considered required one day, this can still be done in the emulator itself. I think the CpU exception dispatcher is not the right place to do this anyway, as there are further differences between MIPS I, MIPS II, MIPS III, MIPS IV and MIPS32 FP ISAs. Corresponding explanation of this implementation is included within the change itself. Signed-off-by: Maciej W. Rozycki --- Ralf, Please apply at your earliest convenience and backport as you see fit, unless you have any questions or comments. Feedback from anyone else is welcome as well. Maciej patch-3.2.0-rc4-do-cpu-cop3-1 diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index c6fc6a0..b86eb3d 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1066,6 +1066,24 @@ asmlinkage void do_cpu(struct pt_regs *regs) return; + case 3: + /* + * Old (MIPS I and MIPS II) processors will set this code + * for COP1X opcode instructions that replaced the original + * COP3 space. We don't limit COP1 space instructions in + * the emulator according to the CPU ISA, so we want to + * treat COP1X instructions consistently regardless of which + * code the CPU chose. Therefore we redirect this trap to + * the FP emulator too. + * + * Then some newer FPU-less processors use this code + * erroneously too, so they are covered by this choice + * as well. + */ + if (raw_cpu_has_fpu) + break; + /* Fall through. */ + case 1: if (used_math()) /* Using the FPU again. */ own_fpu(1); @@ -1089,9 +1107,6 @@ asmlinkage void do_cpu(struct pt_regs *regs) case 2: raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); return; - - case 3: - break; } force_sig(SIGILL, current); From grant.likely@secretlab.ca Fri Mar 9 02:33:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 02:33:42 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:46589 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903692Ab2CIBdd (ORCPT ); Fri, 9 Mar 2012 02:33:33 +0100 Received: by iaky10 with SMTP id y10so1866009iak.36 for ; Thu, 08 Mar 2012 17:33:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:subject:to:cc:in-reply-to:references:date:message-id :x-gm-message-state; bh=w0rlf8839gitIxtqSw1lIosDGI82MZLGqFfeJaw73ck=; b=d4iDv+XFgZB8n+i4Zprf8GjaRalrulDguiEwI8vnInamXFg8H60OSq79ihdxZ+Z7Oq I30eAZl0zIONw1Ri+hB+RlzZXwp7SyX+wFo27uQXe9XAVlShAwMnobAXM8MdlF/nLKLg MH+20+VPk2V+9tWV6prUCnv5Hsyx5cvPoFUBbQQfa9qBDcTy+//wr4QtRWeeM8S5pYae 23UwLbC2nRtPt3lLhu6U5AeOl8eta61a0FymyTZzJSZib/phIftZ8R+k7asRh0/HXAi8 DxFT3ok1daJxqyw5sX4/xwpUoyYEAx+wdTOMaW+OOIqKi7qy0DdOMs5SmsBcJm1Yxvns Wdiw== Received: by 10.50.194.233 with SMTP id hz9mr27377igc.11.1331256806924; Thu, 08 Mar 2012 17:33:26 -0800 (PST) Received: from localhost (S0106d8b37715ee14.cg.shawcable.net. [68.146.14.168]) by mx.google.com with ESMTPS id pr8sm365115igb.6.2012.03.08.17.33.24 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 08 Mar 2012 17:33:25 -0800 (PST) Received: by localhost (Postfix, from userid 1000) id 64DF53E0901; Thu, 8 Mar 2012 18:33:24 -0700 (MST) From: Grant Likely Subject: Re: [PATCH v6 2/2] of: Make of_find_node_by_path() traverse /aliases for relative paths. To: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, Rob Herring Cc: linux-kernel@vger.kernel.org, David Daney In-Reply-To: <1330543264-18103-3-git-send-email-ddaney.cavm@gmail.com> References: <1330543264-18103-1-git-send-email-ddaney.cavm@gmail.com> <1330543264-18103-3-git-send-email-ddaney.cavm@gmail.com> Date: Thu, 08 Mar 2012 18:33:24 -0700 Message-Id: <20120309013324.64DF53E0901@localhost> X-Gm-Message-State: ALoCoQk2FWc2wsBkoCwGB23aCj4G7Fs6c17+BZ+wRxUoAi7SdSEVa0hdL0kmsj0epJhIuWyXIN3b X-archive-position: 32621 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4169 Lines: 142 On Wed, 29 Feb 2012 11:21:04 -0800, David Daney wrote: > From: David Daney > > Currently all paths passed to of_find_node_by_path() must begin with a > '/', indicating a full path to the desired node. > > Augment the look-up code so that if a path does *not* begin with '/', > the path is used as the name of an /aliases property. The value of > this alias is then used as the full node path to be found. > > Signed-off-by: David Daney > --- > drivers/of/base.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-- > 1 files changed, 62 insertions(+), 3 deletions(-) > > diff --git a/drivers/of/base.c b/drivers/of/base.c > index 5806449..0bbe47c 100644 > --- a/drivers/of/base.c > +++ b/drivers/of/base.c > @@ -365,22 +365,81 @@ EXPORT_SYMBOL(of_get_next_child); > > /** > * of_find_node_by_path - Find a node matching a full OF path > - * @path: The full path to match > + * @path: Either the full path to match, or if the path does not > + * start with '/', the name of a property of the /aliases > + * node (an alias). In the case of an alias, the node > + * matching the alias' value will be returned. > * > * Returns a node pointer with refcount incremented, use > * of_node_put() on it when done. > */ > struct device_node *of_find_node_by_path(const char *path) > { > - struct device_node *np = allnodes; > + struct device_node *np = NULL; > + struct device_node *aliases = NULL; > + char *alias = NULL; > + char *new_path = NULL; > + char *ps; > > read_lock(&devtree_lock); > - for (; np; np = np->allnext) { > + > + /* > + * The following code has three possibilities: > + * 1) '/' at start of string; path == ps; (based at root) > + * 2) '/' at offset in string; path < ps; (relative to alias) > + * 3) '/' not found; ps == NULL; (alias only) > + * > + * If ps != path, then it is either a pure alias (ps == NULL), > + * or an alias with a relative path (path < ps). Either way, > + * look up the path pointed to by the alias. > + */ > + ps = strchr(path, '/'); > + if (path != ps) { > + aliases = of_find_node_by_path("/aliases"); > + if (!aliases) > + goto out; > + > + /* > + * Duplicate the alias part of the string so it can be > + * NULL terminated. > + */ > + alias = kstrndup(path, > + ps ? (ps - path) : strlen(path), GFP_KERNEL); > + if (!alias) > + goto out; > + path = of_get_property(aliases, alias, NULL); > + if (!path || path[0] != '/') > + goto out; All the aliases are already decoded at boot time now. See of_alias_scan(). Instead of open-coding this, you can add an of_alias_lookup() function something like this (untested): const char *of_alias_lookup(const char *alias) { struct alias_prop *app; list_for_each_entry(app, &aliases_lookup, link) { if (strcmp(app->alias, alias)) return app->np->full_name; } return NULL; } Then most of the above code disappears. It can instead look like: ps = strchr(path, '/'); if (path != ps) { char alias[ps - path + 1]; strncpy(alias, path, ps - path); alias[ps - path] = '\0'; path = of_alias_lookup(alias); if (path && ps) /* Don't forget to free this */ path = kasprintf(GFP_KERNEL, "%s%s", path, ps); if (!path) return NULL; } g. > + > + /* If ps is not NULL, then there is a relative path to append */ > + if (ps) { > + new_path = kzalloc(strlen(path) + strlen(ps) + 1, > + GFP_KERNEL); > + if (!new_path) > + goto out; > + > + sprintf(new_path, "%s%s", path, ps); > + path = new_path; > + } > + } > + > + /* > + * At this point, path now points to the full unaliased path > + * to a node, regardless of whether or not it started with an > + * alias. > + */ > + > + for (np = allnodes; np; np = np->allnext) { > if (np->full_name && (of_node_cmp(np->full_name, path) == 0) > && of_node_get(np)) > break; > } > +out: > + if (aliases) > + of_node_put(aliases); > read_unlock(&devtree_lock); > + kfree(alias); > + kfree(new_path); > return np; > } > EXPORT_SYMBOL(of_find_node_by_path); > -- > 1.7.2.3 > -- email sent from notmuch.vim plugin From grant.likely@secretlab.ca Fri Mar 9 06:57:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 06:57:20 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:63652 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903554Ab2CIF5O (ORCPT ); Fri, 9 Mar 2012 06:57:14 +0100 Received: by iaky10 with SMTP id y10so2163019iak.36 for ; Thu, 08 Mar 2012 21:57:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:subject:to:cc:in-reply-to:references:date:message-id :x-gm-message-state; bh=1eFwJkmi3K14bhFU7Tr2XdRcewgUhCTmu79I16XM5ag=; b=BM/wU7oPLpsqp2Br27K1ukdtzH/W+Zq5idoYujB1XF2BG4S2bKj7SVeKExJiPvqp61 oZKFWaDZMPcTvVGRDU3eFHb/zZ6Kg0fVwNJ7g/1kCXM1J/0ROoQQf+NuRckU6/9fRwSt /w4JSZWqeEbAlCROz3itGtacM/LEpOUGQMRcxyChtYPdbWEA8GqCZiJxs2F6vDb2dJIi oG25vZKqSInw4ch24hJPH9QPCdoDQBN52VaGd0dVfLElEcg49k3VqEDCd8r119Keb51U XhGcjgsWkTBEDH24hZ9Wr0+yoL81ykoQZr0FN/tPR+vRyAyDo1CFiaM7VkfTXm603uq5 gppQ== Received: by 10.42.73.136 with SMTP id s8mr1228750icj.10.1331272627746; Thu, 08 Mar 2012 21:57:07 -0800 (PST) Received: from localhost (S0106d8b37715ee14.cg.shawcable.net. [68.146.14.168]) by mx.google.com with ESMTPS id k3sm697737igq.1.2012.03.08.21.57.05 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 08 Mar 2012 21:57:06 -0800 (PST) Received: by localhost (Postfix, from userid 1000) id 465823E0901; Thu, 8 Mar 2012 22:57:04 -0700 (MST) From: Grant Likely Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. To: David Daney , Rob Herring Cc: David Daney , David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" In-Reply-To: <4F52F90C.5060306@gmail.com> References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> <20120302190744.571E03E1C63@localhost> <4F511FB0.5070901@cavium.com> <4F527285.1020500@gmail.com> <4F52F90C.5060306@gmail.com> Date: Thu, 08 Mar 2012 22:57:04 -0700 Message-Id: <20120309055704.465823E0901@localhost> X-Gm-Message-State: ALoCoQnV8Dehe6wBl+naPpriFXIU+p4HNF1Mi3ACE6aNCnkHagjSGIY2bwHZ8/DgRLeA1EBHS0cY X-archive-position: 32622 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3690 Lines: 91 On Sat, 03 Mar 2012 21:09:32 -0800, David Daney wrote: > On 03/03/2012 11:35 AM, Rob Herring wrote: > > On 03/02/2012 01:29 PM, David Daney wrote: > >> On 03/02/2012 11:07 AM, Grant Likely wrote: > >>> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, > >>> + unsigned int line, > >>> + unsigned int bit, > >>> + struct irq_domain *domain, > >>> struct irq_chip *chip, > >>> irq_flow_handler_t handler) > >>> { > >>> + struct irq_data *irqd; > >>> union octeon_ciu_chip_data cd; > >>> > >>> irq_set_chip_and_handler(irq, chip, handler); > >>> - > >>> cd.l = 0; > >>> cd.s.line = line; > >>> cd.s.bit = bit; > >>> > >>> irq_set_chip_data(irq, cd.p); > >>> octeon_irq_ciu_to_irq[line][bit] = irq; > >>> + > >>> + irqd = irq_get_irq_data(irq); > >>> + irqd->hwirq = line<< 6 | bit; > >>> + irqd->domain = domain; > >>>>> I think the domain code will set these. > >>>> It is my understanding that the domain code only does this for: > >>>> > >>>> o irq_domain_add_legacy() > >>>> > >>>> o irq_create_direct_mapping() > >>>> > >>>> o irq_create_mapping() > >>>> > >>>> We use none of those. So I do it here. > >>>> > >>>> If there is a better way, I am open to suggestions. > >>> irq_create_mapping is called by irq_create_of_mapping() which is > >>> in turn called by irq_of_parse_and-map(). irq_domain always > >>> manages the hwirq and domain values. Driver code cannot manipulate > >>> them manually. > >>> > >> I really must be missing something. > >> > >> Given: > >> > >> 1) I must have a mapping between hwirq and irq that I control so that > >> non-OF code using the OCTEON_IRQ_* constants continues to work. > > Those defines are what you need to work to get rid of. > > We are not starting from a blank slate here. There is a lot of in-tree > code using these symbols. We cannot make them disappear with wishful > thinking. > > The first step is a switch to irq_domains using the existing mappings. > > After we do that, I have patches to transition some drivers to use the > OF mapping via irq_domains. After those are merged, we can work toward > getting rid of OCTEON_IRQ_*. But I think it must be the last step in > the process, not the first. > > > >> 2) irq_create_mapping() will allocate a random irq value if none is > >> already assigned to the hwirq. > >> > >> Therefore: To avoid having random irq values assigned, I must manually > >> assign them. > >> > > So you should be using legacy domain if you need to maintain fixed hwirq > > to linux irq numbers. "linear" is a bit confusing as it doesn't mean > > linear 1:1 irq number assignment, but linear search. > > My reading of Grant's code in linux-next directly contradicts this > statement. There is no code in irqdomain.c, that I can see, that allows > me to have an arbitrary mapping of irq <--> hwirq values. There are 4 kinds of mappings available; legacy, linear, radix and nomap. Ignore nomap and radix; you don't want them. legacy maps a contiguous range of hwirq numbers to a contiguous range of linux irq numbers. To preserve the exising #define mappings but still add DT support, this is the one that you want. The downside is that it requires all the irq_descs to be allocated ahead of time (which probably isn't a problem for you). The linear map has a linear reverse map lookup table that allows arbitrary irq <--> hwirq mappings. This mapping is preferred, but it doesn't work if you need to preserve #defined irq mappings. g. From dedekind1@gmail.com Fri Mar 9 12:26:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 12:26:18 +0100 (CET) Received: from mga03.intel.com ([143.182.124.21]:32397 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903567Ab2CIL0K (ORCPT ); Fri, 9 Mar 2012 12:26:10 +0100 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 09 Mar 2012 03:26:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="116785661" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by azsmga001.ch.intel.com with ESMTP; 09 Mar 2012 03:26:02 -0800 Received: from [10.237.72.167] (sauron.fi.intel.com [10.237.72.167]) by linux.intel.com (Postfix) with ESMTP id C4EA72C8001; Fri, 9 Mar 2012 03:25:58 -0800 (PST) Message-ID: <1331292517.29445.6.camel@sauron.fi.intel.com> Subject: Re: [PATCH V2 1/3] MTD: MIPS: lantiq: use module_platform_driver inside lantiq map driver From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Date: Fri, 09 Mar 2012 13:28:37 +0200 In-Reply-To: <1330013024-13622-1-git-send-email-blogic@openwrt.org> References: <1330013024-13622-1-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3 (3.2.3-1.fc16) Content-Transfer-Encoding: 7bit Mime-Version: 1.0 X-archive-position: 32623 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 335 Lines: 13 On Thu, 2012-02-23 at 17:03 +0100, John Crispin wrote: > Reduce boilerplate code by converting driver to module_platform_driver. > > Signed-off-by: John Crispin > Cc: linux-mtd@lists.infradead.org This is not an independent patch - do you want to merge it via the mips tree? -- Best Regards, Artem Bityutskiy From blogic@openwrt.org Fri Mar 9 12:30:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 12:30:09 +0100 (CET) Received: from nbd.name ([46.4.11.11]:33275 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903589Ab2CILaG (ORCPT ); Fri, 9 Mar 2012 12:30:06 +0100 Message-ID: <4F59E99D.7090409@openwrt.org> Date: Fri, 09 Mar 2012 12:29:33 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.20) Gecko/20110820 Icedove/3.1.12 MIME-Version: 1.0 To: dedekind1@gmail.com CC: Ralf Baechle , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: Re: [PATCH V2 1/3] MTD: MIPS: lantiq: use module_platform_driver inside lantiq map driver References: <1330013024-13622-1-git-send-email-blogic@openwrt.org> <1331292517.29445.6.camel@sauron.fi.intel.com> In-Reply-To: <1331292517.29445.6.camel@sauron.fi.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-archive-position: 32624 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 411 Lines: 10 On 09/03/12 12:28, Artem Bityutskiy wrote: > On Thu, 2012-02-23 at 17:03 +0100, John Crispin wrote: >> Reduce boilerplate code by converting driver to module_platform_driver. >> >> Signed-off-by: John Crispin >> Cc: linux-mtd@lists.infradead.org > This is not an independent patch - do you want to merge it via the mips > tree? > via MIPS, sorry for not putting the info in the commit text From dedekind1@gmail.com Fri Mar 9 12:35:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 12:35:45 +0100 (CET) Received: from mga03.intel.com ([143.182.124.21]:11149 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903567Ab2CILfi (ORCPT ); Fri, 9 Mar 2012 12:35:38 +0100 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 09 Mar 2012 03:35:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="116788455" Received: from blue.fi.intel.com ([10.237.72.50]) by azsmga001.ch.intel.com with ESMTP; 09 Mar 2012 03:35:30 -0800 From: Artem Bityutskiy To: Ralf Baechle Cc: John Crispin , MTD Maling List , linux-mips@linux-mips.org Subject: [PATCH] MIPS: Kbuild: remove -Werror Date: Fri, 9 Mar 2012 13:35:47 +0200 Message-Id: <1331292947-14913-1-git-send-email-dedekind1@gmail.com> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 32625 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1343 Lines: 37 From: Artem Bityutskiy MIPS does not build with the standard W=1 Kbuild switch with - tested with gcc-4.6 by me and gcc-4.5 by John Crispin. The reason is that MIPS adds -Werror build option. This patch removes the option to make W=1 work. I do compile-tests for various architecture before accepting MTD patches and I have scripts which build before applying the patch, then after, and then compare 2 build logs and report about new warnings. I use W=1 to see more warnings in the logs diff. And from my perspective all platforms should build with W=1. The other way would be to fix all warnings, but there are false positives, and it is too difficult to maintain the code warning-free, so it is easier to just remove -Werror. Signed-off-by: Artem Bityutskiy --- arch/mips/Kbuild | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild index 7dd65cf..0d37730 100644 --- a/arch/mips/Kbuild +++ b/arch/mips/Kbuild @@ -1,8 +1,3 @@ -# Fail on warnings - also for files referenced in subdirs -# -Werror can be disabled for specific files using: -# CFLAGS_ := -Wno-error -subdir-ccflags-y := -Werror - # platform specific definitions include arch/mips/Kbuild.platforms obj-y := $(platform-y) -- 1.7.9.1 From thomas@codesourcery.com Fri Mar 9 17:39:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 17:39:52 +0100 (CET) Received: from relay1.mentorg.com ([192.94.38.131]:37041 "EHLO relay1.mentorg.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903692Ab2CIQjs (ORCPT ); Fri, 9 Mar 2012 17:39:48 +0100 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1S62r1-0004Vy-43 from Thomas_Schwinge@mentor.com ; Fri, 09 Mar 2012 08:39:43 -0800 Received: from SVR-ORW-FEM-03.mgc.mentorg.com ([147.34.97.39]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 9 Mar 2012 08:39:42 -0800 Received: from build6-lucid-cs (147.34.91.1) by svr-orw-fem-03.mgc.mentorg.com (147.34.97.39) with Microsoft SMTP Server id 14.1.289.1; Fri, 9 Mar 2012 08:39:42 -0800 Received: by build6-lucid-cs (Postfix, from userid 49978) id 0F184E6281; Fri, 9 Mar 2012 08:39:41 -0800 (PST) From: Thomas Schwinge CC: Thomas Schwinge , Paul Mundt , , , , Subject: [PATCH 5/7] USB: r8a66597-hcd: restore big-endian operation. Date: Fri, 9 Mar 2012 17:38:51 +0100 Message-ID: <1331311133-26937-5-git-send-email-thomas@codesourcery.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1331311133-26937-1-git-send-email-thomas@codesourcery.com> References: <1331311133-26937-1-git-send-email-thomas@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain X-OriginalArrivalTime: 09 Mar 2012 16:39:42.0413 (UTC) FILETIME=[3A605FD0:01CCFE13] To: unlisted-recipients:; (no To-header on input) X-archive-position: 32626 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas@codesourcery.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1704 Lines: 47 On SH, as of 37b7a97884ba64bf7d403351ac2a9476ab4f1bba we have to use the endianess-agnostic I/O accessor functions. This driver is also enabled in ARM's viper_defconfig as well as MIPS' bcm47xx_defconfig and fuloong2e_defconfig -- I suppose none of these are operating in big-endian mode, or this issue should already have been noticed before. The device is now recognized correctly for both litte-endian and big-endian sh7785lcr, but I have not tested this any further, as the board is situated in a remote data center. Signed-off-by: Thomas Schwinge Cc: Paul Mundt Cc: linux-sh@vger.kernel.org Cc: linux-usb@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org --- drivers/usb/host/r8a66597.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h index f28782d..c2ea6d1 100644 --- a/drivers/usb/host/r8a66597.h +++ b/drivers/usb/host/r8a66597.h @@ -170,7 +170,7 @@ static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597, static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) { - return ioread16(r8a66597->reg + offset); + return __raw_readw(r8a66597->reg + offset); } static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, @@ -198,7 +198,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, unsigned long offset) { - iowrite16(val, r8a66597->reg + offset); + __raw_writew(val, r8a66597->reg + offset); } static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, -- 1.7.4.1 From david.daney@cavium.com Fri Mar 9 18:59:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 18:59:10 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4512 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903694Ab2CIR7F (ORCPT ); Fri, 9 Mar 2012 18:59:05 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 09 Mar 2012 10:00:46 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 9 Mar 2012 09:59:02 -0800 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 9 Mar 2012 09:59:02 -0800 Message-ID: <4F5A44E5.6090300@cavium.com> Date: Fri, 09 Mar 2012 09:59:01 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Grant Likely CC: David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 2/2] of: Make of_find_node_by_path() traverse /aliases for relative paths. References: <1330543264-18103-1-git-send-email-ddaney.cavm@gmail.com> <1330543264-18103-3-git-send-email-ddaney.cavm@gmail.com> <20120309013324.64DF53E0901@localhost> In-Reply-To: <20120309013324.64DF53E0901@localhost> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 09 Mar 2012 17:59:02.0350 (UTC) FILETIME=[4F851EE0:01CCFE1E] X-archive-position: 32627 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 981 Lines: 26 On 03/08/2012 05:33 PM, Grant Likely wrote: > On Wed, 29 Feb 2012 11:21:04 -0800, David Daney wrote: >> From: David Daney >> >> Currently all paths passed to of_find_node_by_path() must begin with a >> '/', indicating a full path to the desired node. >> >> Augment the look-up code so that if a path does *not* begin with '/', >> the path is used as the name of an /aliases property. The value of >> this alias is then used as the full node path to be found. >> >> Signed-off-by: David Daney [...] > > All the aliases are already decoded at boot time now. See > of_alias_scan(). Instead of open-coding this, you can add an > of_alias_lookup() function something like this (untested): > After objections from davem, and a bit of thought, I already indicated on a different branch of this thread that we should drop this patch. I have improved my code so that it is no longer needed. Thanks, David Daney From grant.likely@secretlab.ca Fri Mar 9 19:01:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 19:01:18 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:65449 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903694Ab2CISBL convert rfc822-to-8bit (ORCPT ); Fri, 9 Mar 2012 19:01:11 +0100 Received: by yhjj52 with SMTP id j52so1147529yhj.36 for ; Fri, 09 Mar 2012 10:01:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type :content-transfer-encoding:x-gm-message-state; bh=qjXetQX6KOfYkEmilxKxnED4S9C7sPVgRJexXz8hjg4=; b=KkwfKHjLK3YNsP+oObuo6qMfEX5KnmP5daEpKR+khdz0UgbRxZh/w1LvbaD4SM9Ik+ rL62tX7+e0p+V2ND05PvLrWO9mJwz8jangBSd7NR2cIC4k6imDCrYpQjnQMcrnF9z/6c ioEkRbak6zvL/8DDNE97Ei48ZtAKN01Sgpk7POFru8yUwOxRzpe0cRQeP3ikQLJ7Q7wk r46j0TWFP0YID417lOG8AvSzmk/DW/fvv9LohQth6zZhtLhqSFQ/AXECLsbcOxAckZQx NRtcivCBa4GBPvWQ/cp2VjReieygfr7E4Al80rfelBsYiswNeV+hOA7s8EccSSaEkcqa NlIw== Received: by 10.60.19.33 with SMTP id b1mr1267013oee.35.1331316065475; Fri, 09 Mar 2012 10:01:05 -0800 (PST) MIME-Version: 1.0 Received: by 10.60.18.233 with HTTP; Fri, 9 Mar 2012 10:00:44 -0800 (PST) In-Reply-To: <4F5A44E5.6090300@cavium.com> References: <1330543264-18103-1-git-send-email-ddaney.cavm@gmail.com> <1330543264-18103-3-git-send-email-ddaney.cavm@gmail.com> <20120309013324.64DF53E0901@localhost> <4F5A44E5.6090300@cavium.com> From: Grant Likely Date: Fri, 9 Mar 2012 11:00:44 -0700 X-Google-Sender-Auth: jg2eqENf0lkFyUH8GIpARVebLUg Message-ID: Subject: Re: [PATCH v6 2/2] of: Make of_find_node_by_path() traverse /aliases for relative paths. To: David Daney Cc: David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-Gm-Message-State: ALoCoQkzyaFTIp+5Q8SMexZP568ijNlD6DtaYXIjPKELKcwEfYXfQfS8+YYYzsx0ww7Xci49HlCO X-archive-position: 32628 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1085 Lines: 31 On Fri, Mar 9, 2012 at 10:59 AM, David Daney wrote: > On 03/08/2012 05:33 PM, Grant Likely wrote: >> >> On Wed, 29 Feb 2012 11:21:04 -0800, David Daney >>  wrote: >>> >>> From: David Daney >>> >>> Currently all paths passed to of_find_node_by_path() must begin with a >>> '/', indicating a full path to the desired node. >>> >>> Augment the look-up code so that if a path does *not* begin with '/', >>> the path is used as the name of an /aliases property.  The value of >>> this alias is then used as the full node path to be found. >>> >>> Signed-off-by: David Daney > > [...] > >> >> All the aliases are already decoded at boot time now.  See >> of_alias_scan().  Instead of open-coding this, you can add an >> of_alias_lookup() function something like this (untested): >> > > After objections from davem, and a bit of thought, I already indicated on a > different branch of this thread that we should drop this patch. > > I have improved my code so that it is no longer needed. Okay. From ddaney.cavm@gmail.com Fri Mar 9 19:45:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 19:46:17 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:44724 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903596Ab2CISp7 (ORCPT ); Fri, 9 Mar 2012 19:45:59 +0100 Received: by yhjj52 with SMTP id j52so1180579yhj.36 for ; Fri, 09 Mar 2012 10:45:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=g5YJMxyCorhWDGcQ7gL4PK0G/RrCcrvq4G6cZdSf1ec=; b=oLtuxzFXy/hBdKgJLpUUZvl17n9QjblojkOzLDiyU0aqdYkHvq2Xf8Y3ZNIh0MuHmd QntKx49aJd7x8tMpHR4Nq53t7t9fz1kQbTMspGZlcyZH9g9jRnTySef1mG4c+yWsNiWq A/VAJ+5R+km0IunE1p8SobL3/ve/bbdxdZYIAEGHVlQf7j3eLwhfufoNMXOeSWeUzyoJ jzQBGgitXNmlkefUP96NFdtHRAyOoNnDBK+4zoOzbQnIQMkg5YyIv272ioEb+qRPqAwb cZdUVMAO0IWyF0yoSMDNuIfOjCuvCYqexeDX+jQljOvjFskpzpZ3kBsz8ovNUMzdmHwd zSlA== Received: by 10.236.161.232 with SMTP id w68mr3659580yhk.56.1331318753773; Fri, 09 Mar 2012 10:45:53 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id z27sm15951812yhh.8.2012.03.09.10.45.51 (version=SSLv3 cipher=OTHER); Fri, 09 Mar 2012 10:45:52 -0800 (PST) Message-ID: <4F5A4FDE.1030305@gmail.com> Date: Fri, 09 Mar 2012 10:45:50 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Grant Likely CC: David Daney , Rob Herring , David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> <20120302190744.571E03E1C63@localhost> <4F511FB0.5070901@cavium.com> <4F527285.1020500@gmail.com> <4F52F90C.5060306@gmail.com> <20120309055704.465823E0901@localhost> In-Reply-To: <20120309055704.465823E0901@localhost> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32629 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5152 Lines: 132 On 03/08/2012 09:57 PM, Grant Likely wrote: > On Sat, 03 Mar 2012 21:09:32 -0800, David Daney wrote: >> On 03/03/2012 11:35 AM, Rob Herring wrote: >>> On 03/02/2012 01:29 PM, David Daney wrote: >>>> On 03/02/2012 11:07 AM, Grant Likely wrote: >>>>> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, >>>>> + unsigned int line, >>>>> + unsigned int bit, >>>>> + struct irq_domain *domain, >>>>> struct irq_chip *chip, >>>>> irq_flow_handler_t handler) >>>>> { >>>>> + struct irq_data *irqd; >>>>> union octeon_ciu_chip_data cd; >>>>> >>>>> irq_set_chip_and_handler(irq, chip, handler); >>>>> - >>>>> cd.l = 0; >>>>> cd.s.line = line; >>>>> cd.s.bit = bit; >>>>> >>>>> irq_set_chip_data(irq, cd.p); >>>>> octeon_irq_ciu_to_irq[line][bit] = irq; >>>>> + >>>>> + irqd = irq_get_irq_data(irq); >>>>> + irqd->hwirq = line<< 6 | bit; >>>>> + irqd->domain = domain; >>>>>>> I think the domain code will set these. >>>>>> It is my understanding that the domain code only does this for: >>>>>> >>>>>> o irq_domain_add_legacy() >>>>>> >>>>>> o irq_create_direct_mapping() >>>>>> >>>>>> o irq_create_mapping() >>>>>> >>>>>> We use none of those. So I do it here. >>>>>> >>>>>> If there is a better way, I am open to suggestions. >>>>> irq_create_mapping is called by irq_create_of_mapping() which is >>>>> in turn called by irq_of_parse_and-map(). irq_domain always >>>>> manages the hwirq and domain values. Driver code cannot manipulate >>>>> them manually. >>>>> >>>> I really must be missing something. >>>> >>>> Given: >>>> >>>> 1) I must have a mapping between hwirq and irq that I control so that >>>> non-OF code using the OCTEON_IRQ_* constants continues to work. >>> Those defines are what you need to work to get rid of. >> >> We are not starting from a blank slate here. There is a lot of in-tree >> code using these symbols. We cannot make them disappear with wishful >> thinking. >> >> The first step is a switch to irq_domains using the existing mappings. >> >> After we do that, I have patches to transition some drivers to use the >> OF mapping via irq_domains. After those are merged, we can work toward >> getting rid of OCTEON_IRQ_*. But I think it must be the last step in >> the process, not the first. >>> >>>> 2) irq_create_mapping() will allocate a random irq value if none is >>>> already assigned to the hwirq. >>>> >>>> Therefore: To avoid having random irq values assigned, I must manually >>>> assign them. >>>> >>> So you should be using legacy domain if you need to maintain fixed hwirq >>> to linux irq numbers. "linear" is a bit confusing as it doesn't mean >>> linear 1:1 irq number assignment, but linear search. >> >> My reading of Grant's code in linux-next directly contradicts this >> statement. There is no code in irqdomain.c, that I can see, that allows >> me to have an arbitrary mapping of irq<--> hwirq values. > > There are 4 kinds of mappings available; legacy, linear, radix and nomap. > Yes, I had discovered that. > Ignore nomap and radix; you don't want them. > > legacy maps a contiguous range of hwirq numbers to a contiguous range of > linux irq numbers. To preserve the exising #define mappings but still add > DT support, this is the one that you want. This is precisely the point that you and Rob seem to have missed in the last three or four back-and-forths about this. Probably I have not explained well enough why legacy will not work. We have three different interrupt controllers (although only one is currently in-tree). hwirq to irq mapping for them is more or less as follows: irq hwirqCIU hwirqCIU2 hwirqCIU3 ---------------------------------------------------------------------- OCTEON_IRQ_USB0 56 81 934562 OCTEON_IRQ_TWSI 45 224 100543 OCTEON_IRQ_UART0 34 228 4572 . . . Now what we notice here is that there is no possible 1:1 linearly increasing mapping possible for the irq and *all* three hwirq sets. We want a single binary that contains support for all three interrupt controllers, so the OCTEON_IRQ_* values have to be the same for all three interrupt controllers. Because of this, legacy mapping is *impossible*. Since the possible ranges of the hwirq values is very large and quite sparse, probably the radix mapping will be required. Also to support non-OF drivers and architecture specific code for the near future, I really think the existing IRQ values *must* be preserved. Therefore, as I said above, we need a way for my SOC/board code to specify the mapping. Perhaps we need to add an optional function to struct irq_domain_ops that would allow the default mapping to be overridden on a per irq_domain basis. Otherwise, I think I will have to keep poking into the internal irq_domain data structures to get the mappings I want. What do you think? David Daney From robherring2@gmail.com Fri Mar 9 22:07:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 22:07:49 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:54806 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903697Ab2CIVHc (ORCPT ); Fri, 9 Mar 2012 22:07:32 +0100 Received: by yhjj52 with SMTP id j52so1350184yhj.36 for ; Fri, 09 Mar 2012 13:07:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=4cL/jcbef1SL8AJZt3eHTs3vz/PDOdDTxoMQJmyfUgE=; b=f4xyGY9h4ibFJTRro6RYx19b3KIgEM3WzUx1R+N22dt67V0qYc6rFgJn7JhTatdDB9 OP6ENqOXaSmXFv7i0XQLNRZ5kGD7LcW0/JunzrFyHTXCRi49De0sSXGPsrWd+YXMe/MF FkgO9eEIVXoCctH24iFdNmpsgUFxYIo96SECJlito0pABFJlZOYrQ4UiRGaoEGSGvTL9 atlelVmKrvlCYBOYGs59TINEv0pyDoCLmvx2UZ1ezavvJBdk7mKbMWhveq1tFT7QqmQ+ atBACrnWUVnoem/1oc1PgGZZ6KUP1H5TsYJq7jLt0454LPBHmRunZn2nscU5UH9ypRjh cYgw== Received: by 10.236.155.168 with SMTP id j28mr4355600yhk.16.1331327246471; Fri, 09 Mar 2012 13:07:26 -0800 (PST) Received: from [172.17.28.11] ([173.226.190.126]) by mx.google.com with ESMTPS id g7sm16931067yhm.5.2012.03.09.13.07.24 (version=SSLv3 cipher=OTHER); Fri, 09 Mar 2012 13:07:25 -0800 (PST) Message-ID: <4F5A710A.1000408@gmail.com> Date: Fri, 09 Mar 2012 15:07:22 -0600 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: David Daney CC: Grant Likely , David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> <20120302190744.571E03E1C63@localhost> <4F511FB0.5070901@cavium.com> <4F527285.1020500@gmail.com> <4F52F90C.5060306@gmail.com> <20120309055704.465823E0901@localhost> <4F5A4FDE.1030305@gmail.com> In-Reply-To: <4F5A4FDE.1030305@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32630 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6307 Lines: 165 On 03/09/2012 12:45 PM, David Daney wrote: > On 03/08/2012 09:57 PM, Grant Likely wrote: >> On Sat, 03 Mar 2012 21:09:32 -0800, David >> Daney wrote: >>> On 03/03/2012 11:35 AM, Rob Herring wrote: >>>> On 03/02/2012 01:29 PM, David Daney wrote: >>>>> On 03/02/2012 11:07 AM, Grant Likely wrote: >>>>>> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq, >>>>>> + unsigned int line, >>>>>> + unsigned int bit, >>>>>> + struct irq_domain *domain, >>>>>> struct irq_chip *chip, >>>>>> irq_flow_handler_t handler) >>>>>> { >>>>>> + struct irq_data *irqd; >>>>>> union octeon_ciu_chip_data cd; >>>>>> >>>>>> irq_set_chip_and_handler(irq, chip, handler); >>>>>> - >>>>>> cd.l = 0; >>>>>> cd.s.line = line; >>>>>> cd.s.bit = bit; >>>>>> >>>>>> irq_set_chip_data(irq, cd.p); >>>>>> octeon_irq_ciu_to_irq[line][bit] = irq; >>>>>> + >>>>>> + irqd = irq_get_irq_data(irq); >>>>>> + irqd->hwirq = line<< 6 | bit; >>>>>> + irqd->domain = domain; >>>>>>>> I think the domain code will set these. >>>>>>> It is my understanding that the domain code only does this for: >>>>>>> >>>>>>> o irq_domain_add_legacy() >>>>>>> >>>>>>> o irq_create_direct_mapping() >>>>>>> >>>>>>> o irq_create_mapping() >>>>>>> >>>>>>> We use none of those. So I do it here. >>>>>>> >>>>>>> If there is a better way, I am open to suggestions. >>>>>> irq_create_mapping is called by irq_create_of_mapping() which is >>>>>> in turn called by irq_of_parse_and-map(). irq_domain always >>>>>> manages the hwirq and domain values. Driver code cannot manipulate >>>>>> them manually. >>>>>> >>>>> I really must be missing something. >>>>> >>>>> Given: >>>>> >>>>> 1) I must have a mapping between hwirq and irq that I control so that >>>>> non-OF code using the OCTEON_IRQ_* constants continues to work. >>>> Those defines are what you need to work to get rid of. >>> >>> We are not starting from a blank slate here. There is a lot of in-tree >>> code using these symbols. We cannot make them disappear with wishful >>> thinking. >>> >>> The first step is a switch to irq_domains using the existing mappings. >>> >>> After we do that, I have patches to transition some drivers to use the >>> OF mapping via irq_domains. After those are merged, we can work toward >>> getting rid of OCTEON_IRQ_*. But I think it must be the last step in >>> the process, not the first. >>>> >>>>> 2) irq_create_mapping() will allocate a random irq value if none is >>>>> already assigned to the hwirq. >>>>> >>>>> Therefore: To avoid having random irq values assigned, I must manually >>>>> assign them. >>>>> >>>> So you should be using legacy domain if you need to maintain fixed >>>> hwirq >>>> to linux irq numbers. "linear" is a bit confusing as it doesn't mean >>>> linear 1:1 irq number assignment, but linear search. >>> >>> My reading of Grant's code in linux-next directly contradicts this >>> statement. There is no code in irqdomain.c, that I can see, that allows >>> me to have an arbitrary mapping of irq<--> hwirq values. >> >> There are 4 kinds of mappings available; legacy, linear, radix and nomap. >> > > Yes, I had discovered that. > >> Ignore nomap and radix; you don't want them. >> >> legacy maps a contiguous range of hwirq numbers to a contiguous range of >> linux irq numbers. To preserve the exising #define mappings but still >> add >> DT support, this is the one that you want. > > This is precisely the point that you and Rob seem to have missed in the > last three or four back-and-forths about this. > > Probably I have not explained well enough why legacy will not work. > > We have three different interrupt controllers (although only one is > currently in-tree). hwirq to irq mapping for them is more or less as > follows: I'll just repeat what others have said: if it's not upstream it doesn't exist. We have no knowledge about out of tree h/w to understand what you need > irq hwirqCIU hwirqCIU2 hwirqCIU3 > ---------------------------------------------------------------------- > OCTEON_IRQ_USB0 56 81 934562 > OCTEON_IRQ_TWSI 45 224 100543 > OCTEON_IRQ_UART0 34 228 4572 > . > . > . How many actual hwirqs in each case and what is the range? So for CIU3, it seems you would need to use a radix tree. CIU2 is probably borderline depending on what is the max number. But because you don't yet have code in tree for either yet, you can use a linear domain for now. It shouldn't be hard to switch from linear to radix later. > Now what we notice here is that there is no possible 1:1 linearly > increasing mapping possible for the irq and *all* three hwirq sets. We > want a single binary that contains support for all three interrupt > controllers, so the OCTEON_IRQ_* values have to be the same for all > three interrupt controllers. Because of this, legacy mapping is > *impossible*. OCTEON_IRQ_* values need to go. You may not have to do that now, but certainly before doing support for CIU2 and CIU3 you do. Those platforms should be DT only. > > Since the possible ranges of the hwirq values is very large and quite > sparse, probably the radix mapping will be required. > Yes. You're not the only one with this issue. > Also to support non-OF drivers and architecture specific code for the > near future, I really think the existing IRQ values *must* be preserved. > For a legacy boot yes. But when you boot with DT, you should not need them. This is certainly possible as several ARM platforms do this. You need to start with minimal set of drivers enabled for DT and add them back in 1 by 1. Rob > Therefore, as I said above, we need a way for my SOC/board code to > specify the mapping. > > Perhaps we need to add an optional function to struct irq_domain_ops > that would allow the default mapping to be overridden on a per > irq_domain basis. > > Otherwise, I think I will have to keep poking into the internal > irq_domain data structures to get the mappings I want. > > What do you think? > > David Daney From grant.likely@secretlab.ca Fri Mar 9 23:04:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Mar 2012 23:04:58 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:41135 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903697Ab2CIWEt (ORCPT ); Fri, 9 Mar 2012 23:04:49 +0100 Received: by iaky10 with SMTP id y10so3427445iak.36 for ; Fri, 09 Mar 2012 14:04:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:subject:to:cc:in-reply-to:references:date:message-id :x-gm-message-state; bh=VqDMMEGoTAtp4h+Ky+eHRtsmRlKuCSYckzTYpLMZ4tY=; b=IrbpUIXI+1alVu6nNUeT9SWu2DqUzuCI989110s6DA7ZMyrkqrrVfSipSoDs8AwRjA mtMbm7duqGRm/7/ELfZHJ5hssGARzgn7K42EVGw8kWObORKZ7KwaZwfJkOG+BPe/uolA t4W7QlOS0ECU7M+vDmvrBc6IrW4PnoAnCBkvc0lD+3anmX1Sk+XdBRyTM8gbvHPHkWNv LWvWQQYG2vCKJor6JelrGBW09Y6UjwrRKZo8jp+iP8+UXkMDHsBtiKdbbm7pKZuGSfiL iQ3ezG0vVQSmoGAM7Yw4vZIKYet0afKGHVORM5kZKFhbloPlTYaItS37IdlhPVT6Xv2Z oXwg== Received: by 10.50.186.198 with SMTP id fm6mr5735276igc.40.1331330683244; Fri, 09 Mar 2012 14:04:43 -0800 (PST) Received: from localhost (S0106d8b37715ee14.cg.shawcable.net. [68.146.14.168]) by mx.google.com with ESMTPS id df2sm5618545igb.0.2012.03.09.14.04.40 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 09 Mar 2012 14:04:41 -0800 (PST) Received: by localhost (Postfix, from userid 1000) id 073653E0880; Fri, 9 Mar 2012 15:04:40 -0700 (MST) From: Grant Likely Subject: Re: [PATCH v4] spi: add Broadcom BCM63xx SPI controller driver To: Florian Fainelli , ralf@linux-mips.org Cc: Tanguy Bouzeloc , linux-mips@linux-mips.org, Florian Fainelli , spi-devel-general@lists.sourceforge.net In-Reply-To: <1328091249-10389-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-10-git-send-email-florian@openwrt.org> <1328091249-10389-1-git-send-email-florian@openwrt.org> Date: Fri, 09 Mar 2012 15:04:39 -0700 Message-Id: <20120309220440.073653E0880@localhost> X-Gm-Message-State: ALoCoQnu8Kj1CdZlGmp3AfmIH43HX1kbJkTpnqYjnX6D+X/BNAytn4yfZax+7dVS09PknoMc4cAQ X-archive-position: 32631 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 16653 Lines: 579 On Wed, 1 Feb 2012 11:14:09 +0100, Florian Fainelli wrote: > This patch adds support for the SPI controller found on the Broadcom BCM63xx > SoCs. > > Signed-off-by: Tanguy Bouzeloc > Signed-off-by: Florian Fainelli > Acked-by: Grant Likely Applied, thanks. In v3.4, the spi subsystem is gaining core support for spi message queues. You should look at migrating this driver to use it in the v3.5 timeframe. g. > --- > Changes since v3: > - changed bcm_spi_readb to use readb accessor instead of readw > - fixed multiple __dev{init,exit} annotations > > Changes since v2: > - reworked bcm63xx_spi_setup_transfer to choose closest spi transfer > frequency > - removed invalid 25Mhz frequency > - fixed some minor checkpatch issues > > Changes since v1: > - switched to the devm_* API which frees resources automatically > - switched to dev_pm_ops > - use module_platform_driver > - remove MODULE_VERSION() > - fixed return value when clock is not present using PTR_ERR() > - fixed probe() error path to disable clock in case of failure > > drivers/spi/Kconfig | 6 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-bcm63xx.c | 486 +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 493 insertions(+), 0 deletions(-) > create mode 100644 drivers/spi/spi-bcm63xx.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index 3f9a47e..16818ac 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -94,6 +94,12 @@ config SPI_AU1550 > If you say yes to this option, support will be included for the > PSC SPI controller found on Au1550, Au1200 and Au1300 series. > > +config SPI_BCM63XX > + tristate "Broadcom BCM63xx SPI controller" > + depends on BCM63XX > + help > + Enable support for the SPI controller on the Broadcom BCM63xx SoCs. > + > config SPI_BITBANG > tristate "Utilities for Bitbanging SPI masters" > help > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 61c3261..be38f73 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.o > obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o > obj-$(CONFIG_SPI_ATH79) += spi-ath79.o > obj-$(CONFIG_SPI_AU1550) += spi-au1550.o > +obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o > obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o > obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o > obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o > diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c > new file mode 100644 > index 0000000..f01b264 > --- /dev/null > +++ b/drivers/spi/spi-bcm63xx.c > @@ -0,0 +1,486 @@ > +/* > + * Broadcom BCM63xx SPI controller support > + * > + * Copyright (C) 2009-2011 Florian Fainelli > + * Copyright (C) 2010 Tanguy Bouzeloc > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the > + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define PFX KBUILD_MODNAME > +#define DRV_VER "0.1.2" > + > +struct bcm63xx_spi { > + spinlock_t lock; > + int stopping; > + struct completion done; > + > + void __iomem *regs; > + int irq; > + > + /* Platform data */ > + u32 speed_hz; > + unsigned fifo_size; > + > + /* Data buffers */ > + const unsigned char *tx_ptr; > + unsigned char *rx_ptr; > + > + /* data iomem */ > + u8 __iomem *tx_io; > + const u8 __iomem *rx_io; > + > + int remaining_bytes; > + > + struct clk *clk; > + struct platform_device *pdev; > +}; > + > +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, > + unsigned int offset) > +{ > + return bcm_readb(bs->regs + bcm63xx_spireg(offset)); > +} > + > +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, > + unsigned int offset) > +{ > + return bcm_readw(bs->regs + bcm63xx_spireg(offset)); > +} > + > +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, > + u8 value, unsigned int offset) > +{ > + bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); > +} > + > +static inline void bcm_spi_writew(struct bcm63xx_spi *bs, > + u16 value, unsigned int offset) > +{ > + bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); > +} > + > +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { > + { 20000000, SPI_CLK_20MHZ }, > + { 12500000, SPI_CLK_12_50MHZ }, > + { 6250000, SPI_CLK_6_250MHZ }, > + { 3125000, SPI_CLK_3_125MHZ }, > + { 1563000, SPI_CLK_1_563MHZ }, > + { 781000, SPI_CLK_0_781MHZ }, > + { 391000, SPI_CLK_0_391MHZ } > +}; > + > +static int bcm63xx_spi_setup_transfer(struct spi_device *spi, > + struct spi_transfer *t) > +{ > + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); > + u8 bits_per_word; > + u8 clk_cfg, reg; > + u32 hz; > + int i; > + > + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; > + hz = (t) ? t->speed_hz : spi->max_speed_hz; > + if (bits_per_word != 8) { > + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", > + __func__, bits_per_word); > + return -EINVAL; > + } > + > + if (spi->chip_select > spi->master->num_chipselect) { > + dev_err(&spi->dev, "%s, unsupported slave %d\n", > + __func__, spi->chip_select); > + return -EINVAL; > + } > + > + /* Find the closest clock configuration */ > + for (i = 0; i < SPI_CLK_MASK; i++) { > + if (hz <= bcm63xx_spi_freq_table[i][0]) { > + clk_cfg = bcm63xx_spi_freq_table[i][1]; > + break; > + } > + } > + > + /* No matching configuration found, default to lowest */ > + if (i == SPI_CLK_MASK) > + clk_cfg = SPI_CLK_0_391MHZ; > + > + /* clear existing clock configuration bits of the register */ > + reg = bcm_spi_readb(bs, SPI_CLK_CFG); > + reg &= ~SPI_CLK_MASK; > + reg |= clk_cfg; > + > + bcm_spi_writeb(bs, reg, SPI_CLK_CFG); > + dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", > + clk_cfg, hz); > + > + return 0; > +} > + > +/* the spi->mode bits understood by this driver: */ > +#define MODEBITS (SPI_CPOL | SPI_CPHA) > + > +static int bcm63xx_spi_setup(struct spi_device *spi) > +{ > + struct bcm63xx_spi *bs; > + int ret; > + > + bs = spi_master_get_devdata(spi->master); > + > + if (bs->stopping) > + return -ESHUTDOWN; > + > + if (!spi->bits_per_word) > + spi->bits_per_word = 8; > + > + if (spi->mode & ~MODEBITS) { > + dev_err(&spi->dev, "%s, unsupported mode bits %x\n", > + __func__, spi->mode & ~MODEBITS); > + return -EINVAL; > + } > + > + ret = bcm63xx_spi_setup_transfer(spi, NULL); > + if (ret < 0) { > + dev_err(&spi->dev, "setup: unsupported mode bits %x\n", > + spi->mode & ~MODEBITS); > + return ret; > + } > + > + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", > + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0); > + > + return 0; > +} > + > +/* Fill the TX FIFO with as many bytes as possible */ > +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs) > +{ > + u8 size; > + > + /* Fill the Tx FIFO with as many bytes as possible */ > + size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes : > + bs->fifo_size; > + memcpy_toio(bs->tx_io, bs->tx_ptr, size); > + bs->remaining_bytes -= size; > +} > + > +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) > +{ > + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); > + u16 msg_ctl; > + u16 cmd; > + > + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", > + t->tx_buf, t->rx_buf, t->len); > + > + /* Transmitter is inhibited */ > + bs->tx_ptr = t->tx_buf; > + bs->rx_ptr = t->rx_buf; > + init_completion(&bs->done); > + > + if (t->tx_buf) { > + bs->remaining_bytes = t->len; > + bcm63xx_spi_fill_tx_fifo(bs); > + } > + > + /* Enable the command done interrupt which > + * we use to determine completion of a command */ > + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); > + > + /* Fill in the Message control register */ > + msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); > + > + if (t->rx_buf && t->tx_buf) > + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT); > + else if (t->rx_buf) > + msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT); > + else if (t->tx_buf) > + msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT); > + > + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); > + > + /* Issue the transfer */ > + cmd = SPI_CMD_START_IMMEDIATE; > + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); > + cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); > + bcm_spi_writew(bs, cmd, SPI_CMD); > + wait_for_completion(&bs->done); > + > + /* Disable the CMD_DONE interrupt */ > + bcm_spi_writeb(bs, 0, SPI_INT_MASK); > + > + return t->len - bs->remaining_bytes; > +} > + > +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m) > +{ > + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); > + struct spi_transfer *t; > + int ret = 0; > + > + if (unlikely(list_empty(&m->transfers))) > + return -EINVAL; > + > + if (bs->stopping) > + return -ESHUTDOWN; > + > + list_for_each_entry(t, &m->transfers, transfer_list) { > + ret += bcm63xx_txrx_bufs(spi, t); > + } > + > + m->complete(m->context); > + > + return ret; > +} > + > +/* This driver supports single master mode only. Hence > + * CMD_DONE is the only interrupt we care about > + */ > +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) > +{ > + struct spi_master *master = (struct spi_master *)dev_id; > + struct bcm63xx_spi *bs = spi_master_get_devdata(master); > + u8 intr; > + u16 cmd; > + > + /* Read interupts and clear them immediately */ > + intr = bcm_spi_readb(bs, SPI_INT_STATUS); > + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); > + bcm_spi_writeb(bs, 0, SPI_INT_MASK); > + > + /* A tansfer completed */ > + if (intr & SPI_INTR_CMD_DONE) { > + u8 rx_tail; > + > + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); > + > + /* Read out all the data */ > + if (rx_tail) > + memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail); > + > + /* See if there is more data to send */ > + if (bs->remaining_bytes > 0) { > + bcm63xx_spi_fill_tx_fifo(bs); > + > + /* Start the transfer */ > + bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT, > + SPI_MSG_CTL); > + cmd = bcm_spi_readw(bs, SPI_CMD); > + cmd |= SPI_CMD_START_IMMEDIATE; > + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); > + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); > + bcm_spi_writew(bs, cmd, SPI_CMD); > + } else { > + complete(&bs->done); > + } > + } > + > + return IRQ_HANDLED; > +} > + > + > +static int __devinit bcm63xx_spi_probe(struct platform_device *pdev) > +{ > + struct resource *r; > + struct device *dev = &pdev->dev; > + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data; > + int irq; > + struct spi_master *master; > + struct clk *clk; > + struct bcm63xx_spi *bs; > + int ret; > + > + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!r) { > + dev_err(dev, "no iomem\n"); > + ret = -ENXIO; > + goto out; > + } > + > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) { > + dev_err(dev, "no irq\n"); > + ret = -ENXIO; > + goto out; > + } > + > + clk = clk_get(dev, "spi"); > + if (IS_ERR(clk)) { > + dev_err(dev, "no clock for device\n"); > + ret = PTR_ERR(clk); > + goto out; > + } > + > + master = spi_alloc_master(dev, sizeof(*bs)); > + if (!master) { > + dev_err(dev, "out of memory\n"); > + ret = -ENOMEM; > + goto out_clk; > + } > + > + bs = spi_master_get_devdata(master); > + init_completion(&bs->done); > + > + platform_set_drvdata(pdev, master); > + bs->pdev = pdev; > + > + if (!devm_request_mem_region(&pdev->dev, r->start, > + resource_size(r), PFX)) { > + dev_err(dev, "iomem request failed\n"); > + ret = -ENXIO; > + goto out_err; > + } > + > + bs->regs = devm_ioremap_nocache(&pdev->dev, r->start, > + resource_size(r)); > + if (!bs->regs) { > + dev_err(dev, "unable to ioremap regs\n"); > + ret = -ENOMEM; > + goto out_err; > + } > + > + bs->irq = irq; > + bs->clk = clk; > + bs->fifo_size = pdata->fifo_size; > + > + ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, > + pdev->name, master); > + if (ret) { > + dev_err(dev, "unable to request irq\n"); > + goto out_err; > + } > + > + master->bus_num = pdata->bus_num; > + master->num_chipselect = pdata->num_chipselect; > + master->setup = bcm63xx_spi_setup; > + master->transfer = bcm63xx_transfer; > + bs->speed_hz = pdata->speed_hz; > + bs->stopping = 0; > + bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); > + bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); > + spin_lock_init(&bs->lock); > + > + /* Initialize hardware */ > + clk_enable(bs->clk); > + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); > + > + /* register and we are done */ > + ret = spi_register_master(master); > + if (ret) { > + dev_err(dev, "spi register failed\n"); > + goto out_clk_disable; > + } > + > + dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n", > + r->start, irq, bs->fifo_size, DRV_VER); > + > + return 0; > + > +out_clk_disable: > + clk_disable(clk); > +out_err: > + platform_set_drvdata(pdev, NULL); > + spi_master_put(master); > +out_clk: > + clk_put(clk); > +out: > + return ret; > +} > + > +static int __devexit bcm63xx_spi_remove(struct platform_device *pdev) > +{ > + struct spi_master *master = platform_get_drvdata(pdev); > + struct bcm63xx_spi *bs = spi_master_get_devdata(master); > + > + /* reset spi block */ > + bcm_spi_writeb(bs, 0, SPI_INT_MASK); > + spin_lock(&bs->lock); > + bs->stopping = 1; > + > + /* HW shutdown */ > + clk_disable(bs->clk); > + clk_put(bs->clk); > + > + spin_unlock(&bs->lock); > + platform_set_drvdata(pdev, 0); > + spi_unregister_master(master); > + > + return 0; > +} > + > +#ifdef CONFIG_PM > +static int bcm63xx_spi_suspend(struct device *dev) > +{ > + struct spi_master *master = > + platform_get_drvdata(to_platform_device(dev)); > + struct bcm63xx_spi *bs = spi_master_get_devdata(master); > + > + clk_disable(bs->clk); > + > + return 0; > +} > + > +static int bcm63xx_spi_resume(struct device *dev) > +{ > + struct spi_master *master = > + platform_get_drvdata(to_platform_device(dev)); > + struct bcm63xx_spi *bs = spi_master_get_devdata(master); > + > + clk_enable(bs->clk); > + > + return 0; > +} > + > +static const struct dev_pm_ops bcm63xx_spi_pm_ops = { > + .suspend = bcm63xx_spi_suspend, > + .resume = bcm63xx_spi_resume, > +}; > + > +#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) > +#else > +#define BCM63XX_SPI_PM_OPS NULL > +#endif > + > +static struct platform_driver bcm63xx_spi_driver = { > + .driver = { > + .name = "bcm63xx-spi", > + .owner = THIS_MODULE, > + .pm = BCM63XX_SPI_PM_OPS, > + }, > + .probe = bcm63xx_spi_probe, > + .remove = __devexit_p(bcm63xx_spi_remove), > +}; > + > +module_platform_driver(bcm63xx_spi_driver); > + > +MODULE_ALIAS("platform:bcm63xx_spi"); > +MODULE_AUTHOR("Florian Fainelli "); > +MODULE_AUTHOR("Tanguy Bouzeloc "); > +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); > +MODULE_LICENSE("GPL"); > -- > 1.7.5.4 > > > ------------------------------------------------------------------------------ > Keep Your Developer Skills Current with LearnDevNow! > The most comprehensive online learning library for Microsoft developers > is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, > Metro Style Apps, more. Free future releases when you subscribe now! > http://p.sf.net/sfu/learndevnow-d2d > _______________________________________________ > spi-devel-general mailing list > spi-devel-general@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/spi-devel-general -- Grant Likely, B.Sc, P.Eng. Secret Lab Technologies,Ltd. From ddaney.cavm@gmail.com Sat Mar 10 01:08:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Mar 2012 01:08:48 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:54677 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903696Ab2CJAIa (ORCPT ); Sat, 10 Mar 2012 01:08:30 +0100 Received: by ggnk1 with SMTP id k1so1525600ggn.36 for ; Fri, 09 Mar 2012 16:08:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=kjGahSZ2ptaX/nh0kHU+K1pCoYD/akNAjKYCToUzPC8=; b=rcGha562hfioZCmDvp73sSBD2EmZ14ioM5h0fJVzFzAXwvIKoA8XHwl3E/AT+/PyF5 Zni2pv97MEj6NtjeEo/j6A0UhwIw3gldG7Q/sGPSgyEnGJAJ6byQX29vTmbqPyZif3W4 +sbvvS2hAS0uON6pvfDFinkblfK2vVsmPpJrcmnaDp1BlbcX6eo3mdNehmpteTuzHypd beqxcixs7/XBZpvO/vpCGrXXxlAw8fJvP+iRTGa8/FozNz02Iv5r3RJjwCMk42TkGbqj 65X2G6urWJiJtqeMPFtJroZFQHtWEwmDrPuYbcWMSMjYoj2tzobJOu8Vk5uZ2nVB0RXg oRVQ== Received: by 10.236.126.168 with SMTP id b28mr4836920yhi.88.1331338104357; Fri, 09 Mar 2012 16:08:24 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id l2sm12123679anq.12.2012.03.09.16.08.22 (version=SSLv3 cipher=OTHER); Fri, 09 Mar 2012 16:08:23 -0800 (PST) Message-ID: <4F5A9B75.8090301@gmail.com> Date: Fri, 09 Mar 2012 16:08:21 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Rob Herring CC: Grant Likely , David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> <20120302190744.571E03E1C63@localhost> <4F511FB0.5070901@cavium.com> <4F527285.1020500@gmail.com> <4F52F90C.5060306@gmail.com> <20120309055704.465823E0901@localhost> <4F5A4FDE.1030305@gmail.com> <4F5A710A.1000408@gmail.com> In-Reply-To: <4F5A710A.1000408@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32637 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3468 Lines: 97 On 03/09/2012 01:07 PM, Rob Herring wrote: > On 03/09/2012 12:45 PM, David Daney wrote: [...] >> >> Probably I have not explained well enough why legacy will not work. >> >> We have three different interrupt controllers (although only one is >> currently in-tree). hwirq to irq mapping for them is more or less as >> follows: > > I'll just repeat what others have said: if it's not upstream it doesn't > exist. > > We have no knowledge about out of tree h/w to understand what you need > >> irq hwirqCIU hwirqCIU2 hwirqCIU3 >> ---------------------------------------------------------------------- >> OCTEON_IRQ_USB0 56 81 934562 >> OCTEON_IRQ_TWSI 45 224 100543 >> OCTEON_IRQ_UART0 34 228 4572 >> . >> . >> . > > How many actual hwirqs in each case and what is the range? > > So for CIU3, it seems you would need to use a radix tree. CIU2 is > probably borderline depending on what is the max number. But because you > don't yet have code in tree for either yet, you can use a linear domain > for now. It shouldn't be hard to switch from linear to radix later. > >> Now what we notice here is that there is no possible 1:1 linearly >> increasing mapping possible for the irq and *all* three hwirq sets. We >> want a single binary that contains support for all three interrupt >> controllers, so the OCTEON_IRQ_* values have to be the same for all >> three interrupt controllers. Because of this, legacy mapping is >> *impossible*. > > OCTEON_IRQ_* values need to go. You may not have to do that now, but > certainly before doing support for CIU2 and CIU3 you do. Those platforms > should be DT only. > >> >> Since the possible ranges of the hwirq values is very large and quite >> sparse, probably the radix mapping will be required. >> > > Yes. You're not the only one with this issue. > >> Also to support non-OF drivers and architecture specific code for the >> near future, I really think the existing IRQ values *must* be preserved. >> > > For a legacy boot yes. But when you boot with DT, you should not need > them. It is not a matter of how the system is booted, rather what all the drivers are expecting... > This is certainly possible as several ARM platforms do this. You > need to start with minimal set of drivers enabled for DT and add them > back in 1 by 1. > What I don't understand about this is what happens during the transition? What if a shared interrupt were referred from one non-OF driver by its symbolic OCTEON_IRQ_? value, and from a second driver by its hwirq value extracted from the DT? In that case you would be referring to the same interrupt line by two different irq values, clearly that should be prevented. At a minimum, the change made for each converted driver would have to include: removing the OCTEON_IRQ_? values, Maintain a list of hwirqs that are outside of the domain and report this by the.map() function, and then update this list. David Daney > Rob > >> Therefore, as I said above, we need a way for my SOC/board code to >> specify the mapping. >> >> Perhaps we need to add an optional function to struct irq_domain_ops >> that would allow the default mapping to be overridden on a per >> irq_domain basis. >> >> Otherwise, I think I will have to keep poking into the internal >> irq_domain data structures to get the mappings I want. >> >> What do you think? >> >> David Daney > > From sshtylyov@mvista.com Sat Mar 10 12:04:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Mar 2012 12:04:12 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:62571 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903700Ab2CJLEI (ORCPT ); Sat, 10 Mar 2012 12:04:08 +0100 Received: by bkcjk13 with SMTP id jk13so2351086bkc.36 for ; Sat, 10 Mar 2012 03:04:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=Py4cfCsQ8h9x5CYtD2v2fv47xtGnNm8ewYCF81NZUks=; b=hD7H3oLlmJdHBm9PlhGoA6qrXy/LTTdUrxw6BTG6tFD2jYv+ixTzKmqPjOO1VB/B7O dnHMeE54AgWPIxR0dsE07DcNUSuyJY2IfhdG8X/5evBYA3Se76Nr9ESragNt1bG7db2l 5Y+eDGPJx82nN+CijHDPFu6vRDcr1lSyaVQN4c5Iy7FDWpuHWaZdVcV8i6irHUDY+0A/ 4EZhXlVYO9D4NjBuGbXCeUiPBw5BRACRkrpgiyGldc4TddoCtohcAwsZvSjHwDH21eId FDN5qS4QlXJZE8Dr8tOGNjlH5XpmAo/v1u5GzBvpdob/tJFM8W2W0+bJhfKII0wicJ1J reaQ== Received: by 10.204.156.133 with SMTP id x5mr2142048bkw.86.1331377441470; Sat, 10 Mar 2012 03:04:01 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-94-226.pppoe.mtu-net.ru. [91.79.94.226]) by mx.google.com with ESMTPS id u14sm13995397bkp.2.2012.03.10.03.03.58 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 10 Mar 2012 03:03:59 -0800 (PST) Message-ID: <4F5B34CE.5040900@mvista.com> Date: Sat, 10 Mar 2012 15:02:38 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Thomas Schwinge CC: unlisted-recipients:; Paul Mundt , linux-sh@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org Subject: Re: [PATCH 5/7] USB: r8a66597-hcd: restore big-endian operation. References: <1331311133-26937-1-git-send-email-thomas@codesourcery.com> <1331311133-26937-5-git-send-email-thomas@codesourcery.com> In-Reply-To: <1331311133-26937-5-git-send-email-thomas@codesourcery.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQl0nk6RxU2JF1I5YdLaiimQzTAiBe8pKpK5TeI7h5La0a6CCC0mv13kj/My60qg0wOKCdfg X-archive-position: 32640 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 906 Lines: 27 Hello. On 09-03-2012 20:38, Thomas Schwinge wrote: > On SH, as of 37b7a97884ba64bf7d403351ac2a9476ab4f1bba we have to use the Please also specify the summary of thta commit in parens. > endianess-agnostic I/O accessor functions. > This driver is also enabled in ARM's viper_defconfig as well as MIPS' > bcm47xx_defconfig and fuloong2e_defconfig -- I suppose none of these are > operating in big-endian mode, or this issue should already have been noticed > before. > The device is now recognized correctly for both litte-endian and big-endian > sh7785lcr, but I have not tested this any further, as the board is situated in > a remote data center. > Signed-off-by: Thomas Schwinge > Cc: Paul Mundt > Cc: linux-sh@vger.kernel.org > Cc: linux-usb@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-mips@linux-mips.org WBR, Sergei From robherring2@gmail.com Sat Mar 10 17:20:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Mar 2012 17:20:46 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:56746 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903703Ab2CJQU2 (ORCPT ); Sat, 10 Mar 2012 17:20:28 +0100 Received: by ghbf11 with SMTP id f11so1847420ghb.36 for ; Sat, 10 Mar 2012 08:20:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=Mf2dm1FlCI3fX4+V3CxuHtCGZDD0aJ70eEdzoUmcd10=; b=VysIuJMTuW3g2x56ygKyX2XrGOo8apqUedV/3PSqnaibkAxKMW9rAkYTGqV1b54vvV WL3oFbxRcj4p+oSFH5vOiwPAtzFs/CGQeSGJkzTBAs82ZzeKymzsLe8Jbuim9SIOlkHi ggRdFEnuMy3VNRO/EdPpSoHLhUo/AqH7rKIneQVMqE828OFAKMxtu4WpFqellC+UkEM3 lDQcGnUCxLoimk0EPJkDG0DyZNiByQVyfQSHg8ezSO+FceHVi5M/9UhOH2af+Ld/IzgS EDKxqTni1Wu3MbIQbXQgxSRgjDJuA70wkZjSvhm5hRR100QJ8c5E33fk9kLQb9j3AYde qNDw== Received: by 10.236.184.167 with SMTP id s27mr7640593yhm.8.1331396422372; Sat, 10 Mar 2012 08:20:22 -0800 (PST) Received: from [192.168.1.103] (65-36-72-55.dyn.grandenetworks.net. [65.36.72.55]) by mx.google.com with ESMTPS id h30sm23718915yhk.4.2012.03.10.08.20.20 (version=SSLv3 cipher=OTHER); Sat, 10 Mar 2012 08:20:21 -0800 (PST) Message-ID: <4F5B7F39.50106@gmail.com> Date: Sat, 10 Mar 2012 10:20:09 -0600 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: David Daney CC: Grant Likely , David Daney , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "devicetree-discuss@lists.ozlabs.org" , Rob Herring , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts. References: <1330563422-14078-1-git-send-email-ddaney.cavm@gmail.com> <1330563422-14078-5-git-send-email-ddaney.cavm@gmail.com> <4F50D7C2.7080204@gmail.com> <4F510B8E.3070201@cavium.com> <20120302190744.571E03E1C63@localhost> <4F511FB0.5070901@cavium.com> <4F527285.1020500@gmail.com> <4F52F90C.5060306@gmail.com> <20120309055704.465823E0901@localhost> <4F5A4FDE.1030305@gmail.com> <4F5A710A.1000408@gmail.com> <4F5A9B75.8090301@gmail.com> In-Reply-To: <4F5A9B75.8090301@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32641 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3652 Lines: 88 On 03/09/2012 06:08 PM, David Daney wrote: > On 03/09/2012 01:07 PM, Rob Herring wrote: >> On 03/09/2012 12:45 PM, David Daney wrote: > [...] >>> >>> Probably I have not explained well enough why legacy will not work. >>> >>> We have three different interrupt controllers (although only one is >>> currently in-tree). hwirq to irq mapping for them is more or less as >>> follows: >> >> I'll just repeat what others have said: if it's not upstream it doesn't >> exist. >> >> We have no knowledge about out of tree h/w to understand what you need >> >>> irq hwirqCIU hwirqCIU2 hwirqCIU3 >>> ---------------------------------------------------------------------- >>> OCTEON_IRQ_USB0 56 81 934562 >>> OCTEON_IRQ_TWSI 45 224 100543 >>> OCTEON_IRQ_UART0 34 228 4572 >>> . >>> . >>> . >> >> How many actual hwirqs in each case and what is the range? >> >> So for CIU3, it seems you would need to use a radix tree. CIU2 is >> probably borderline depending on what is the max number. But because you >> don't yet have code in tree for either yet, you can use a linear domain >> for now. It shouldn't be hard to switch from linear to radix later. >> >>> Now what we notice here is that there is no possible 1:1 linearly >>> increasing mapping possible for the irq and *all* three hwirq sets. We >>> want a single binary that contains support for all three interrupt >>> controllers, so the OCTEON_IRQ_* values have to be the same for all >>> three interrupt controllers. Because of this, legacy mapping is >>> *impossible*. >> >> OCTEON_IRQ_* values need to go. You may not have to do that now, but >> certainly before doing support for CIU2 and CIU3 you do. Those platforms >> should be DT only. >> >>> >>> Since the possible ranges of the hwirq values is very large and quite >>> sparse, probably the radix mapping will be required. >>> >> >> Yes. You're not the only one with this issue. >> >>> Also to support non-OF drivers and architecture specific code for the >>> near future, I really think the existing IRQ values *must* be preserved. >>> >> >> For a legacy boot yes. But when you boot with DT, you should not need >> them. > > It is not a matter of how the system is booted, rather what all the > drivers are expecting... > >> This is certainly possible as several ARM platforms do this. You >> need to start with minimal set of drivers enabled for DT and add them >> back in 1 by 1. >> > > What I don't understand about this is what happens during the transition? > > What if a shared interrupt were referred from one non-OF driver by its > symbolic OCTEON_IRQ_? value, and from a second driver by its hwirq value > extracted from the DT? In that case you would be referring to the same > interrupt line by two different irq values, clearly that should be > prevented. > > At a minimum, the change made for each converted driver would have to > include: removing the OCTEON_IRQ_? values, Maintain a list of hwirqs > that are outside of the domain and report this by the.map() function, > and then update this list. Drivers should only deal with Linux irq numbers and should only get them as a resource passed into the driver probe. This is true with or without DT. I only see 2 drivers directly using OCTEON_IRQ defines: ethernet and watchdog. Fix them. The serial setup code needs to use resources as well. The other place you will see irq defines is platform device declarations (i2c is an example in your case). For DT boot, you would not register the static devices and the devices should be created dynamically. Rob From hauke@hauke-m.de Sun Mar 11 21:08:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Mar 2012 21:08:51 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:42513 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903716Ab2CKUIo (ORCPT ); Sun, 11 Mar 2012 21:08:44 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 943AF8F68; Sun, 11 Mar 2012 21:08:43 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zqnh6vgcng7r; Sun, 11 Mar 2012 21:08:30 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id B07AC8F60; Sun, 11 Mar 2012 21:08:29 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 0/7] USB: OHCI/EHCI: generic platform driver Date: Sun, 11 Mar 2012 21:08:18 +0100 Message-Id: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32642 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2948 Lines: 68 This EHCI/OHCI platform driver should replace the simple EHCI and OHCI platform drivers. It was developed to be used for the USB core of the Broadcom SoCs supported by ssb and bcma, but it should also work for other devices. Drivers like ehci-ath79.c, ehci-xls.c and ehci-ixp4xx.c should be relative easy be ported to this EHCI driver. And drivers like ohci-ath79.c, ohci-ppc-soc.c, ohci-sh.c and ohci-xls.c should be easy be ported to the this OHCI driver. I am unable to test the suspend and resume part, as my SoC does not support this, but most of the platform driver do not support suspend/resume too. The code here should work, but was never runtime tested. This also contains patches adding USB support for the SoCs based on ssb and bcma and converts the ath79 code to use the generic usb driver. v3: * add patches for bcma and ssb usb driver again * add patch to convert ath79 to use the generic platform driver v2: * split include/linux/usb/hci_driver.h into include/linux /usb/ehci_pdriver.h and include/linux/usb/ohci_pdriver.h * remove flags from include/linux/usb/{e,o}ehci_pdriver.h * add kernel doc * add some more options into the structs to activate hardware quirks. Hauke Mehrtens (7): USB: OHCI: Add a generic platform device driver USB: EHCI: Add a generic platform device driver bcma: scan for extra address space USB: Add driver for the bcma bus USB: Add driver for the ssb bus USB: OHCI: remove old SSB OHCI driver USB: use generic platform driver on ath79 arch/mips/ath79/dev-usb.c | 31 +++- drivers/bcma/scan.c | 18 ++- drivers/usb/host/Kconfig | 74 +++++---- drivers/usb/host/Makefile | 2 + drivers/usb/host/bcma-hcd.c | 334 ++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ehci-ath79.c | 208 ------------------------ drivers/usb/host/ehci-hcd.c | 10 +- drivers/usb/host/ehci-platform.c | 198 ++++++++++++++++++++++ drivers/usb/host/ohci-ath79.c | 151 ----------------- drivers/usb/host/ohci-hcd.c | 31 +--- drivers/usb/host/ohci-platform.c | 194 ++++++++++++++++++++++ drivers/usb/host/ohci-ssb.c | 260 ----------------------------- drivers/usb/host/ssb-hcd.c | 279 +++++++++++++++++++++++++++++++ include/linux/bcma/bcma.h | 1 + include/linux/usb/ehci_pdriver.h | 46 ++++++ include/linux/usb/ohci_pdriver.h | 38 +++++ 16 files changed, 1189 insertions(+), 686 deletions(-) create mode 100644 drivers/usb/host/bcma-hcd.c delete mode 100644 drivers/usb/host/ehci-ath79.c create mode 100644 drivers/usb/host/ehci-platform.c delete mode 100644 drivers/usb/host/ohci-ath79.c create mode 100644 drivers/usb/host/ohci-platform.c delete mode 100644 drivers/usb/host/ohci-ssb.c create mode 100644 drivers/usb/host/ssb-hcd.c create mode 100644 include/linux/usb/ehci_pdriver.h create mode 100644 include/linux/usb/ohci_pdriver.h -- 1.7.5.4 From hauke@hauke-m.de Sun Mar 11 21:08:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Mar 2012 21:09:17 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:42519 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903717Ab2CKUIp (ORCPT ); Sun, 11 Mar 2012 21:08:45 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 9CE768F60; Sun, 11 Mar 2012 21:08:45 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EaYXB7fFSwO0; Sun, 11 Mar 2012 21:08:30 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 3B11B8F61; Sun, 11 Mar 2012 21:08:30 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 1/7] USB: OHCI: Add a generic platform device driver Date: Sun, 11 Mar 2012 21:08:19 +0100 Message-Id: <1331496505-18697-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32643 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8240 Lines: 300 This adds a generic driver for platform devices. It works like the PCI driver and is based on it. This is for devices which do not have an own bus but their OHCI controller works like a PCI controller. It will be used for the Broadcom bcma and ssb USB OHCI controller. Acked-by: Alan Stern Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 10 ++ drivers/usb/host/ohci-hcd.c | 5 + drivers/usb/host/ohci-platform.c | 194 ++++++++++++++++++++++++++++++++++++++ include/linux/usb/ohci_pdriver.h | 38 ++++++++ 4 files changed, 247 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ohci-platform.c create mode 100644 include/linux/usb/ohci_pdriver.h diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 353cdd4..4fe564c 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -393,6 +393,16 @@ config USB_CNS3XXX_OHCI Enable support for the CNS3XXX SOC's on-chip OHCI controller. It is needed for low-speed USB 1.0 device support. +config USB_OHCI_HCD_PLATFORM + bool "OHCI driver for a platform device" + depends on USB_OHCI_HCD && EXPERIMENTAL + default n + ---help--- + Adds an OHCI host driver for a generic platform device, which + provieds a memory space and an irq. + + If unsure, say N. + config USB_OHCI_BIG_ENDIAN_DESC bool depends on USB_OHCI_HCD diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 34b9edd..50fbbf9 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1121,6 +1121,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_xls_driver #endif +#ifdef CONFIG_USB_OHCI_HCD_PLATFORM +#include "ohci-platform.c" +#define PLATFORM_DRIVER ohci_platform_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c new file mode 100644 index 0000000..ec5c679 --- /dev/null +++ b/drivers/usb/host/ohci-platform.c @@ -0,0 +1,194 @@ +/* + * Generic platform ohci driver + * + * Copyright 2007 Michael Buesch + * Copyright 2011-2012 Hauke Mehrtens + * + * Derived from the OCHI-SSB driver + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include + +static int ohci_platform_reset(struct usb_hcd *hcd) +{ + struct platform_device *pdev = to_platform_device(hcd->self.controller); + struct usb_ohci_pdata *pdata = pdev->dev.platform_data; + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int err; + + if (pdata->big_endian_desc) + ohci->flags |= OHCI_QUIRK_BE_DESC; + if (pdata->big_endian_mmio) + ohci->flags |= OHCI_QUIRK_BE_MMIO; + if (pdata->no_big_frame_no) + ohci->flags |= OHCI_QUIRK_FRAME_NO; + + ohci_hcd_init(ohci); + err = ohci_init(ohci); + + return err; +} + +static int ohci_platform_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int err; + + err = ohci_run(ohci); + if (err < 0) { + ohci_err(ohci, "can't start\n"); + ohci_stop(hcd); + } + + return err; +} + +static const struct hc_driver ohci_platform_hc_driver = { + .description = hcd_name, + .product_desc = "Generic Platform OHCI Controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + + .irq = ohci_irq, + .flags = HCD_MEMORY | HCD_USB11, + + .reset = ohci_platform_reset, + .start = ohci_platform_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + + .get_frame_number = ohci_get_frame, + + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, +#ifdef CONFIG_PM + .bus_suspend = ohci_bus_suspend, + .bus_resume = ohci_bus_resume, +#endif + + .start_port_reset = ohci_start_port_reset, +}; + +static int __devinit ohci_platform_probe(struct platform_device *dev) +{ + struct usb_hcd *hcd; + struct resource *res_mem; + int irq; + int err = -ENOMEM; + + BUG_ON(!dev->dev.platform_data); + + if (usb_disabled()) + return -ENODEV; + + irq = platform_get_irq(dev, 0); + if (irq < 0) { + pr_err("no irq provieded"); + return irq; + } + + res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res_mem) { + pr_err("no memory recourse provieded"); + return -ENXIO; + } + + hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev, + dev_name(&dev->dev)); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = res_mem->start; + hcd->rsrc_len = resource_size(res_mem); + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_err("controller already in use"); + err = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) + goto err_release_region; + err = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (err) + goto err_iounmap; + + platform_set_drvdata(dev, hcd); + + return err; + +err_iounmap: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return err; +} + +static int __devexit ohci_platform_remove(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + platform_set_drvdata(dev, NULL); + + return 0; +} + +#ifdef CONFIG_PM + +static int ohci_platform_suspend(struct device *dev) +{ + return 0; +} + +static int ohci_platform_resume(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + + ohci_finish_controller_resume(hcd); + return 0; +} + +#else /* !CONFIG_PM */ +#define ohci_platform_suspend NULL +#define ohci_platform_resume NULL +#endif /* CONFIG_PM */ + +static const struct platform_device_id ohci_platform_table[] = { + { "ohci-platform", 0 }, + { } +}; +MODULE_DEVICE_TABLE(platform, ohci_platform_table); + +static const struct dev_pm_ops ohci_platform_pm_ops = { + .suspend = ohci_platform_suspend, + .resume = ohci_platform_resume, +}; + +static struct platform_driver ohci_platform_driver = { + .id_table = ohci_platform_table, + .probe = ohci_platform_probe, + .remove = __devexit_p(ohci_platform_remove), + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .owner = THIS_MODULE, + .name = "ohci-platform", + .pm = &ohci_platform_pm_ops, + } +}; diff --git a/include/linux/usb/ohci_pdriver.h b/include/linux/usb/ohci_pdriver.h new file mode 100644 index 0000000..2808f2a --- /dev/null +++ b/include/linux/usb/ohci_pdriver.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2012 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __USB_CORE_OHCI_PDRIVER_H +#define __USB_CORE_OHCI_PDRIVER_H + +/** + * struct usb_ohci_pdata - platform_data for generic ohci driver + * + * @big_endian_desc: BE descriptors + * @big_endian_mmio: BE registers + * @no_big_frame_no: no big endian frame_no shift + * + * These are general configuration options for the OHCI controller. All of + * these options are activating more or less workarounds for some hardware. + */ +struct usb_ohci_pdata { + unsigned big_endian_desc:1; + unsigned big_endian_mmio:1; + unsigned no_big_frame_no:1; +}; + +#endif /* __USB_CORE_OHCI_PDRIVER_H */ -- 1.7.5.4 From hauke@hauke-m.de Sun Mar 11 21:08:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Mar 2012 21:09:45 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:42536 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903719Ab2CKUI7 (ORCPT ); Sun, 11 Mar 2012 21:08:59 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 0102D8F61; Sun, 11 Mar 2012 21:08:59 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id j-302iorJS63; Sun, 11 Mar 2012 21:08:44 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 8BF8F8F62; Sun, 11 Mar 2012 21:08:30 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 2/7] USB: EHCI: Add a generic platform device driver Date: Sun, 11 Mar 2012 21:08:20 +0100 Message-Id: <1331496505-18697-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32644 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9037 Lines: 312 This adds a generic driver for platform devices. It works like the PCI driver and is based on it. This is for devices which do not have an own bus but their EHCI controller works like a PCI controller. It will be used for the Broadcom bcma and ssb USB EHCI controller. Acked-by: Alan Stern Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 10 ++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-platform.c | 198 ++++++++++++++++++++++++++++++++++++++ include/linux/usb/ehci_pdriver.h | 46 +++++++++ 4 files changed, 259 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-platform.c create mode 100644 include/linux/usb/ehci_pdriver.h diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 4fe564c..0edc445 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -403,6 +403,16 @@ config USB_OHCI_HCD_PLATFORM If unsure, say N. +config USB_EHCI_HCD_PLATFORM + bool "Generic EHCI driver for a platform device" + depends on USB_EHCI_HCD && EXPERIMENTAL + default n + ---help--- + Adds an EHCI host driver for a generic platform device, which + provieds a memory space and an irq. + + If unsure, say N. + config USB_OHCI_BIG_ENDIAN_DESC bool depends on USB_OHCI_HCD diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index a007a9f..afe0984 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1376,6 +1376,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_mv_driver #endif +#ifdef CONFIG_USB_EHCI_HCD_PLATFORM +#include "ehci-platform.c" +#define PLATFORM_DRIVER ehci_platform_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c new file mode 100644 index 0000000..d238b4e2 --- /dev/null +++ b/drivers/usb/host/ehci-platform.c @@ -0,0 +1,198 @@ +/* + * Generic platform ehci driver + * + * Copyright 2007 Steven Brown + * Copyright 2010-2012 Hauke Mehrtens + * + * Derived from the ohci-ssb driver + * Copyright 2007 Michael Buesch + * + * Derived from the EHCI-PCI driver + * Copyright (c) 2000-2004 by David Brownell + * + * Derived from the ohci-pci driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include + +static int ehci_platform_reset(struct usb_hcd *hcd) +{ + struct platform_device *pdev = to_platform_device(hcd->self.controller); + struct usb_ehci_pdata *pdata = pdev->dev.platform_data; + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int retval; + + hcd->has_tt = pdata->has_tt; + ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug; + ehci->big_endian_desc = pdata->big_endian_desc; + ehci->big_endian_mmio = pdata->big_endian_mmio; + + ehci->caps = hcd->regs + pdata->caps_offset; + retval = ehci_setup(hcd); + if (retval) + return retval; + + if (pdata->port_power_on) + ehci_port_power(ehci, 1); + if (pdata->port_power_off) + ehci_port_power(ehci, 0); + + return 0; +} + +static const struct hc_driver ehci_platform_hc_driver = { + .description = hcd_name, + .product_desc = "Generic Platform EHCI Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + .reset = ehci_platform_reset, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +#if defined(CONFIG_PM) + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, +#endif + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .update_device = ehci_update_device, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int __devinit ehci_platform_probe(struct platform_device *dev) +{ + struct usb_hcd *hcd; + struct resource *res_mem; + int irq; + int err = -ENOMEM; + + BUG_ON(!dev->dev.platform_data); + + if (usb_disabled()) + return -ENODEV; + + irq = platform_get_irq(dev, 0); + if (irq < 0) { + pr_err("no irq provieded"); + return irq; + } + res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res_mem) { + pr_err("no memory recourse provieded"); + return -ENXIO; + } + + hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev, + dev_name(&dev->dev)); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = res_mem->start; + hcd->rsrc_len = resource_size(res_mem); + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_err("controller already in use"); + err = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) + goto err_release_region; + err = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (err) + goto err_iounmap; + + platform_set_drvdata(dev, hcd); + + return err; + +err_iounmap: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return err; +} + +static int __devexit ehci_platform_remove(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + platform_set_drvdata(dev, NULL); + + return 0; +} + +#ifdef CONFIG_PM + +static int ehci_platform_suspend(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + bool wakeup = device_may_wakeup(dev); + + ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), wakeup); + return 0; +} + +static int ehci_platform_resume(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + + ehci_prepare_ports_for_controller_resume(hcd_to_ehci(hcd)); + return 0; +} + +#else /* !CONFIG_PM */ +#define ehci_platform_suspend NULL +#define ehci_platform_resume NULL +#endif /* CONFIG_PM */ + +static const struct platform_device_id ehci_platform_table[] = { + { "ehci-platform", 0 }, + { } +}; +MODULE_DEVICE_TABLE(platform, ehci_platform_table); + +static const struct dev_pm_ops ehci_platform_pm_ops = { + .suspend = ehci_platform_suspend, + .resume = ehci_platform_resume, +}; + +static struct platform_driver ehci_platform_driver = { + .id_table = ehci_platform_table, + .probe = ehci_platform_probe, + .remove = __devexit_p(ehci_platform_remove), + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .owner = THIS_MODULE, + .name = "ehci-platform", + .pm = &ehci_platform_pm_ops, + } +}; diff --git a/include/linux/usb/ehci_pdriver.h b/include/linux/usb/ehci_pdriver.h new file mode 100644 index 0000000..b693529 --- /dev/null +++ b/include/linux/usb/ehci_pdriver.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2012 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __USB_CORE_EHCI_PDRIVER_H +#define __USB_CORE_EHCI_PDRIVER_H + +/** + * struct usb_ehci_pdata - platform_data for generic ehci driver + * + * @caps_offset: offset of the EHCI Capability Registers to the start of + * the io memory region provided to the driver. + * @has_tt: set to 1 if TT is integrated in root hub. + * @port_power_on: set to 1 if the controller needs a power up after + * initialization. + * @port_power_off: set to 1 if the controller needs to be powered down + * after initialization. + * + * These are general configuration options for the EHCI controller. All of + * these options are activating more or less workarounds for some hardware. + */ +struct usb_ehci_pdata { + int caps_offset; + unsigned has_tt:1; + unsigned has_synopsys_hc_bug:1; + unsigned big_endian_desc:1; + unsigned big_endian_mmio:1; + unsigned port_power_on:1; + unsigned port_power_off:1; +}; + +#endif /* __USB_CORE_EHCI_PDRIVER_H */ -- 1.7.5.4 From hauke@hauke-m.de Sun Mar 11 21:09:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Mar 2012 21:10:09 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:42541 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903720Ab2CKUJA (ORCPT ); Sun, 11 Mar 2012 21:09:00 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 8A8D28F62; Sun, 11 Mar 2012 21:09:00 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zZ3kZcVTQp9V; Sun, 11 Mar 2012 21:08:46 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 192598F63; Sun, 11 Mar 2012 21:08:31 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, Hauke Mehrtens , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , linux-wireless@vger.kernel.org Subject: [PATCH 3/7] bcma: scan for extra address space Date: Sun, 11 Mar 2012 21:08:21 +0100 Message-Id: <1331496505-18697-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32645 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1880 Lines: 65 Some cores like the USB core have two address spaces. In the USB host controller one address space is used for the OHCI and the other for the EHCI controller interface. The USB controller is the only core I found with two address spaces. This code is based on the AI scan function ai_scan() in shared/aiutils.c i the Broadcom SDK. CC: RafaÅ‚ MiÅ‚ecki CC: linux-wireless@vger.kernel.org Signed-off-by: Hauke Mehrtens --- drivers/bcma/scan.c | 18 +++++++++++++++++- include/linux/bcma/bcma.h | 1 + 2 files changed, 18 insertions(+), 1 deletions(-) diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c index 3a2f672..3c2eeed 100644 --- a/drivers/bcma/scan.c +++ b/drivers/bcma/scan.c @@ -286,6 +286,22 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, return -EILSEQ; } + + /* First Slave Address Descriptor should be port 0: + * the main register space for the core + */ + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); + if (tmp <= 0) { + /* Try again to see if it is a bridge */ + tmp = bcma_erom_get_addr_desc(bus, eromptr, + SCAN_ADDR_TYPE_BRIDGE, 0); + if (tmp > 0) { + pr_info("found bridge"); + return -ENXIO; + } + } + core->addr = tmp; + /* get & parse slave ports */ for (i = 0; i < ports[1]; i++) { for (j = 0; ; j++) { @@ -298,7 +314,7 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, break; } else { if (i == 0 && j == 0) - core->addr = tmp; + core->addr1 = tmp; } } } diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 83c209f..7fe41e1 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -138,6 +138,7 @@ struct bcma_device { u8 core_index; u32 addr; + u32 addr1; u32 wrap; void __iomem *io_addr; -- 1.7.5.4 From hauke@hauke-m.de Sun Mar 11 21:09:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Mar 2012 21:10:32 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:42555 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903716Ab2CKUJP (ORCPT ); Sun, 11 Mar 2012 21:09:15 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 5CCA28F68; Sun, 11 Mar 2012 21:09:15 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HRm3Io+kIuLh; Sun, 11 Mar 2012 21:08:59 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 94C298F64; Sun, 11 Mar 2012 21:08:31 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 4/7] USB: Add driver for the bcma bus Date: Sun, 11 Mar 2012 21:08:22 +0100 Message-Id: <1331496505-18697-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32646 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 10489 Lines: 388 This adds a USB driver using the generic platform device driver for the USB controller found on the Broadcom bcma bus. The bcma bus just exposes one device which serves the OHCI and the EHCI controller at the same time. This driver probes for this USB controller and creates and registers two new platform devices which will be probed by the new generic platform device driver. This makes it possible to use the EHCI and the OCHI controller on the bcma bus at the same time. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 12 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/bcma-hcd.c | 334 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 347 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/bcma-hcd.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0edc445..598e6a0 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -633,3 +633,15 @@ config USB_PXA168_EHCI help Enable support for Marvell PXA168 SoC's on-chip EHCI host controller + +config USB_HCD_BCMA + tristate "BCMA usb host driver" + depends on BCMA && EXPERIMENTAL + select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD + select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD + help + Enbale support for the EHCI and OCHI host controller on an bcma bus. + It converts the bcma driver into two platform device drivers + for ehci and ohci. + + If unsure, say N. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 7ca290f..f2c2846 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -37,3 +37,4 @@ obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o obj-$(CONFIG_MIPS_ALCHEMY) += alchemy-common.o +obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o diff --git a/drivers/usb/host/bcma-hcd.c b/drivers/usb/host/bcma-hcd.c new file mode 100644 index 0000000..8685e2e --- /dev/null +++ b/drivers/usb/host/bcma-hcd.c @@ -0,0 +1,334 @@ +/* + * Broadcom specific Advanced Microcontroller Bus + * Broadcom USB-core driver (BCMA bus glue) + * + * Copyright 2011 Hauke Mehrtens + * + * Based on ssb-ohci driver + * Copyright 2007 Michael Buesch + * + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Derived from the USBcore related parts of Broadcom-SB + * Copyright 2005-2011 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include +#include +#include +#include +#include + +MODULE_AUTHOR("Hauke Mehrtens"); +MODULE_DESCRIPTION("Common USB driver for BCMA Bus"); +MODULE_LICENSE("GPL"); + +struct bcma_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; +}; + +/* Wait for bitmask in a register to get set or cleared. + * timeout is in units of ten-microseconds. + */ +static int bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask, + int timeout) +{ + int i; + u32 val; + + for (i = 0; i < timeout; i++) { + val = bcma_read32(dev, reg); + if ((val & bitmask) == bitmask) + return 0; + udelay(10); + } + + return -ETIMEDOUT; +} + +static void __devinit bcma_hcd_4716wa(struct bcma_device *dev) +{ +#ifdef CONFIG_BCMA_DRIVER_MIPS + /* Work around for 4716 failures. */ + if (dev->bus->chipinfo.id == 0x4716) { + u32 tmp; + + tmp = bcma_cpu_clock(&dev->bus->drv_mips); + if (tmp >= 480000000) + tmp = 0x1846b; /* set CDR to 0x11(fast) */ + else if (tmp == 453000000) + tmp = 0x1046b; /* set CDR to 0x10(slow) */ + else + tmp = 0; + + /* Change Shim mdio control reg to fix host not acking at + * high frequencies + */ + if (tmp) { + bcma_write32(dev, 0x524, 0x1); /* write sel to enable */ + udelay(500); + + bcma_write32(dev, 0x524, tmp); + udelay(500); + bcma_write32(dev, 0x524, 0x4ab); + udelay(500); + bcma_read32(dev, 0x528); + bcma_write32(dev, 0x528, 0x80000000); + } + } +#endif /* CONFIG_BCMA_DRIVER_MIPS */ +} + +/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ +static void __devinit bcma_hcd_init_chip(struct bcma_device *dev) +{ + u32 tmp; + + /* + * USB 2.0 special considerations: + * + * 1. Since the core supports both OHCI and EHCI functions, it must + * only be reset once. + * + * 2. In addition to the standard SI reset sequence, the Host Control + * Register must be programmed to bring the USB core and various + * phy components out of reset. + */ + if (!bcma_core_is_enabled(dev)) { + bcma_core_enable(dev, 0); + mdelay(10); + if (dev->id.rev >= 5) { + /* Enable Misc PLL */ + tmp = bcma_read32(dev, 0x1e0); + tmp |= 0x100; + bcma_write32(dev, 0x1e0, tmp); + if (bcma_wait_bits(dev, 0x1e0, 1 << 24, 100)) + printk(KERN_EMERG "Failed to enable misc PPL!\n"); + + /* Take out of resets */ + bcma_write32(dev, 0x200, 0x4ff); + udelay(25); + bcma_write32(dev, 0x200, 0x6ff); + udelay(25); + + /* Make sure digital and AFE are locked in USB PHY */ + bcma_write32(dev, 0x524, 0x6b); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0xab); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0x2b); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0x10ab); + udelay(50); + tmp = bcma_read32(dev, 0x524); + + if (bcma_wait_bits(dev, 0x528, 0xc000, 10000)) { + tmp = bcma_read32(dev, 0x528); + printk(KERN_EMERG + "USB20H mdio_rddata 0x%08x\n", tmp); + } + bcma_write32(dev, 0x528, 0x80000000); + tmp = bcma_read32(dev, 0x314); + udelay(265); + bcma_write32(dev, 0x200, 0x7ff); + udelay(10); + + /* Take USB and HSIC out of non-driving modes */ + bcma_write32(dev, 0x510, 0); + } else { + bcma_write32(dev, 0x200, 0x7ff); + + udelay(1); + } + + bcma_hcd_4716wa(dev); + } +} + +static const struct usb_ehci_pdata ehci_pdata = { +}; + +static const struct usb_ohci_pdata ohci_pdata = { +}; + +static struct platform_device * __devinit +bcma_hcd_create_pdev(struct bcma_device *dev, bool ohci, u32 addr) +{ + struct platform_device *hci_dev; + struct resource hci_res[2]; + int ret = -ENOMEM; + + memset(hci_res, 0, sizeof(hci_res)); + + hci_res[0].start = addr; + hci_res[0].end = hci_res[0].start + 0x1000 - 1; + hci_res[0].flags = IORESOURCE_MEM; + + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + + hci_dev = platform_device_alloc(ohci ? "ohci-platform" : + "ehci-platform" , 0); + if (!hci_dev) + return NULL; + + hci_dev->dev.parent = &dev->dev; + hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask; + + ret = platform_device_add_resources(hci_dev, hci_res, + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; + if (ohci) + ret = platform_device_add_data(hci_dev, &ohci_pdata, + sizeof(ohci_pdata)); + else + ret = platform_device_add_data(hci_dev, &ehci_pdata, + sizeof(ehci_pdata)); + if (ret) + goto err_alloc; + ret = platform_device_add(hci_dev); + if (ret) + goto err_alloc; + + return hci_dev; + +err_alloc: + platform_device_put(hci_dev); + return ERR_PTR(ret); +} + +static int __devinit bcma_hcd_probe(struct bcma_device *dev) +{ + int err; + u16 chipid_top; + u32 ohci_addr; + struct bcma_hcd_device *usb_dev; + struct bcma_chipinfo *chipinfo; + + chipinfo = &dev->bus->chipinfo; + /* USBcores are only connected on embedded devices. */ + chipid_top = (chipinfo->id & 0xFF00); + if (chipid_top != 0x4700 && chipid_top != 0x5300) + return -ENODEV; + + /* TODO: Probably need checks here; is the core connected? */ + + if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + + usb_dev = kzalloc(sizeof(struct bcma_hcd_device), GFP_KERNEL); + if (!usb_dev) + return -ENOMEM; + + bcma_hcd_init_chip(dev); + + /* In AI chips EHCI is addrspace 0, OHCI is 1 */ + ohci_addr = dev->addr1; + if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749) + && chipinfo->rev == 0) + ohci_addr = 0x18009000; + + usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, true, ohci_addr); + if (IS_ERR(usb_dev->ohci_dev)) { + err = PTR_ERR(usb_dev->ohci_dev); + goto err_free_usb_dev; + } + + usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, false, dev->addr); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; + } + + bcma_set_drvdata(dev, usb_dev); + return 0; + +err_unregister_ohci_dev: + platform_device_unregister(usb_dev->ohci_dev); +err_free_usb_dev: + kfree(usb_dev); + return err; +} + +static void __devexit bcma_hcd_remove(struct bcma_device *dev) +{ + struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); + struct platform_device *ohci_dev = usb_dev->ohci_dev; + struct platform_device *ehci_dev = usb_dev->ehci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); + + bcma_core_disable(dev, 0); +} + +static void bcma_hcd_shutdown(struct bcma_device *dev) +{ + bcma_core_disable(dev, 0); +} + +#ifdef CONFIG_PM + +static int bcma_hcd_suspend(struct bcma_device *dev, pm_message_t state) +{ + bcma_core_disable(dev, 0); + + return 0; +} + +static int bcma_hcd_resume(struct bcma_device *dev) +{ + bcma_core_enable(dev, 0); + + return 0; +} + +#else /* !CONFIG_PM */ +#define bcma_hcd_suspend NULL +#define bcma_hcd_resume NULL +#endif /* CONFIG_PM */ + +static const struct bcma_device_id bcma_hcd_table[] __devinitconst = { + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS), + BCMA_CORETABLE_END +}; +MODULE_DEVICE_TABLE(bcma, bcma_hcd_table); + +static struct bcma_driver bcma_hcd_driver = { + .name = KBUILD_MODNAME, + .id_table = bcma_hcd_table, + .probe = bcma_hcd_probe, + .remove = __devexit_p(bcma_hcd_remove), + .shutdown = bcma_hcd_shutdown, + .suspend = bcma_hcd_suspend, + .resume = bcma_hcd_resume, +}; + +static int __init bcma_hcd_init(void) +{ + return bcma_driver_register(&bcma_hcd_driver); +} +module_init(bcma_hcd_init); + +static void __exit bcma_hcd_exit(void) +{ + bcma_driver_unregister(&bcma_hcd_driver); +} +module_exit(bcma_hcd_exit); -- 1.7.5.4 From hauke@hauke-m.de Sun Mar 11 21:09:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Mar 2012 21:10:56 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:42559 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2CKUJR (ORCPT ); Sun, 11 Mar 2012 21:09:17 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 6F22F8F61; Sun, 11 Mar 2012 21:09:17 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kKLiWA1FxU2M; Sun, 11 Mar 2012 21:09:00 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 03EC28F65; Sun, 11 Mar 2012 21:08:31 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 5/7] USB: Add driver for the ssb bus Date: Sun, 11 Mar 2012 21:08:23 +0100 Message-Id: <1331496505-18697-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32647 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9398 Lines: 337 This adds a USB driver using the generic platform device driver for the USB controller found on the Broadcom ssb bus. The ssb bus just exposes one device which serves the OHCI and the EHCI controller at the same time. This driver probes for this USB controller and creates and registers two new platform devices which will be probed by the new generic platform device driver. This makes it possible to use the EHCI and the OCHI controller on the ssb bus at the same time. The old ssb OHCI USB driver will be removed in the next step as this driver also provide an OHCI driver and an EHCI for the cores supporting it. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 12 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ssb-hcd.c | 279 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 292 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ssb-hcd.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 598e6a0..eab27d5 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -645,3 +645,15 @@ config USB_HCD_BCMA for ehci and ohci. If unsure, say N. + +config USB_HCD_SSB + tristate "SSB usb host driver" + depends on SSB && EXPERIMENTAL + select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD + select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD + help + Enbale support for the EHCI and OCHI host controller on an bcma bus. + It converts the bcma driver into two platform device drivers + for ehci and ohci. + + If unsure, say N. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f2c2846..9c52966 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o obj-$(CONFIG_MIPS_ALCHEMY) += alchemy-common.o obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o +obj-$(CONFIG_USB_HCD_SSB) += ssb-hcd.o diff --git a/drivers/usb/host/ssb-hcd.c b/drivers/usb/host/ssb-hcd.c new file mode 100644 index 0000000..d375d1a --- /dev/null +++ b/drivers/usb/host/ssb-hcd.c @@ -0,0 +1,279 @@ +/* + * Sonics Silicon Backplane + * Broadcom USB-core driver (SSB bus glue) + * + * Copyright 2011 Hauke Mehrtens + * + * Based on ssb-ohci driver + * Copyright 2007 Michael Buesch + * + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Derived from the USBcore related parts of Broadcom-SB + * Copyright 2005-2011 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include +#include +#include +#include +#include + +MODULE_AUTHOR("Hauke Mehrtens"); +MODULE_DESCRIPTION("Common USB driver for SSB Bus"); +MODULE_LICENSE("GPL"); + +#define SSB_HCD_TMSLOW_HOSTMODE (1 << 29) + +struct ssb_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; + + u32 enable_flags; +}; + +static void __devinit ssb_hcd_5354wa(struct ssb_device *dev) +{ +#ifdef CONFIG_SSB_DRIVER_MIPS + /* Work around for 5354 failures */ + if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { + /* Change syn01 reg */ + ssb_write32(dev, 0x894, 0x00fe00fe); + + /* Change syn03 reg */ + ssb_write32(dev, 0x89c, ssb_read32(dev, 0x89c) | 0x1); + } +#endif +} + +static void __devinit ssb_hcd_usb20wa(struct ssb_device *dev) +{ + if (dev->id.coreid == SSB_DEV_USB20_HOST) { + /* + * USB 2.0 special considerations: + * + * In addition to the standard SSB reset sequence, the Host + * Control Register must be programmed to bring the USB core + * and various phy components out of reset. + */ + ssb_write32(dev, 0x200, 0x7ff); + + /* Change Flush control reg */ + ssb_write32(dev, 0x400, ssb_read32(dev, 0x400) & ~8); + ssb_read32(dev, 0x400); + + /* Change Shim control reg */ + ssb_write32(dev, 0x304, ssb_read32(dev, 0x304) & ~0x100); + ssb_read32(dev, 0x304); + + udelay(1); + + ssb_hcd_5354wa(dev); + } +} + +/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ +static u32 __devinit ssb_hcd_init_chip(struct ssb_device *dev) +{ + u32 flags = 0; + + if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) + /* Put the device into host-mode. */ + flags |= SSB_HCD_TMSLOW_HOSTMODE; + + ssb_device_enable(dev, flags); + + ssb_hcd_usb20wa(dev); + + return flags; +} + +static const struct usb_ehci_pdata ehci_pdata = { +}; + +static const struct usb_ohci_pdata ohci_pdata = { +}; + +static struct platform_device * __devinit +ssb_hcd_create_pdev(struct ssb_device *dev, bool ohci, u32 addr, u32 len) +{ + struct platform_device *hci_dev; + struct resource hci_res[2]; + int ret = -ENOMEM; + + memset(hci_res, 0, sizeof(hci_res)); + + hci_res[0].start = addr; + hci_res[0].end = hci_res[0].start + len - 1; + hci_res[0].flags = IORESOURCE_MEM; + + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + + hci_dev = platform_device_alloc(ohci ? "ohci-platform" : + "ehci-platform" , 0); + if (!hci_dev) + return NULL; + + hci_dev->dev.parent = dev->dev; + hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask; + + ret = platform_device_add_resources(hci_dev, hci_res, + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; + if (ohci) + ret = platform_device_add_data(hci_dev, &ohci_pdata, + sizeof(ohci_pdata)); + else + ret = platform_device_add_data(hci_dev, &ehci_pdata, + sizeof(ehci_pdata)); + if (ret) + goto err_alloc; + ret = platform_device_add(hci_dev); + if (ret) + goto err_alloc; + + return hci_dev; + +err_alloc: + platform_device_put(hci_dev); + return ERR_PTR(ret); +} + +static int __devinit ssb_hcd_probe(struct ssb_device *dev, + const struct ssb_device_id *id) +{ + int err, tmp; + int start, len; + u16 chipid_top; + u16 coreid = dev->id.coreid; + struct ssb_hcd_device *usb_dev; + + /* USBcores are only connected on embedded devices. */ + chipid_top = (dev->bus->chip_id & 0xFF00); + if (chipid_top != 0x4700 && chipid_top != 0x5300) + return -ENODEV; + + /* TODO: Probably need checks here; is the core connected? */ + + if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + + usb_dev = kzalloc(sizeof(struct ssb_hcd_device), GFP_KERNEL); + if (!usb_dev) + return -ENOMEM; + + /* We currently always attach SSB_DEV_USB11_HOSTDEV + * as HOST OHCI. If we want to attach it as Client device, + * we must branch here and call into the (yet to + * be written) Client mode driver. Same for remove(). */ + usb_dev->enable_flags = ssb_hcd_init_chip(dev); + + tmp = ssb_read32(dev, SSB_ADMATCH0); + + start = ssb_admatch_base(tmp); + len = (coreid == SSB_DEV_USB20_HOST) ? 0x800 : ssb_admatch_size(tmp); + usb_dev->ohci_dev = ssb_hcd_create_pdev(dev, true, start, len); + if (IS_ERR(usb_dev->ohci_dev)) { + err = PTR_ERR(usb_dev->ohci_dev); + goto err_free_usb_dev; + } + + if (coreid == SSB_DEV_USB20_HOST) { + start = ssb_admatch_base(tmp) + 0x800; /* ehci core offset */ + usb_dev->ehci_dev = ssb_hcd_create_pdev(dev, false, start, len); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; + } + } + + ssb_set_drvdata(dev, usb_dev); + return 0; + +err_unregister_ohci_dev: + platform_device_unregister(usb_dev->ohci_dev); +err_free_usb_dev: + kfree(usb_dev); + return err; +} + +static void __devexit ssb_hcd_remove(struct ssb_device *dev) +{ + struct ssb_hcd_device *usb_dev = ssb_get_drvdata(dev); + struct platform_device *ohci_dev = usb_dev->ohci_dev; + struct platform_device *ehci_dev = usb_dev->ehci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); + + ssb_device_disable(dev, 0); +} + +static void __devexit ssb_hcd_shutdown(struct ssb_device *dev) +{ + ssb_device_disable(dev, 0); +} + +#ifdef CONFIG_PM + +static int ssb_hcd_suspend(struct ssb_device *dev, pm_message_t state) +{ + ssb_device_disable(dev, 0); + + return 0; +} + +static int ssb_hcd_resume(struct ssb_device *dev) +{ + struct ssb_hcd_device *usb_dev = ssb_get_drvdata(dev); + + ssb_device_enable(dev, usb_dev->enable_flags); + + return 0; +} + +#else /* !CONFIG_PM */ +#define ssb_hcd_suspend NULL +#define ssb_hcd_resume NULL +#endif /* CONFIG_PM */ + +static const struct ssb_device_id ssb_hcd_table[] __devinitconst = { + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV), + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV), + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), + SSB_DEVTABLE_END +}; +MODULE_DEVICE_TABLE(ssb, ssb_hcd_table); + +static struct ssb_driver ssb_hcd_driver = { + .name = KBUILD_MODNAME, + .id_table = ssb_hcd_table, + .probe = ssb_hcd_probe, + .remove = __devexit_p(ssb_hcd_remove), + .shutdown = ssb_hcd_shutdown, + .suspend = ssb_hcd_suspend, + .resume = ssb_hcd_resume, +}; + +static int __init ssb_hcd_init(void) +{ + return ssb_driver_register(&ssb_hcd_driver); +} +module_init(ssb_hcd_init); + +static void __exit ssb_hcd_exit(void) +{ + ssb_driver_unregister(&ssb_hcd_driver); +} +module_exit(ssb_hcd_exit); -- 1.7.5.4 From hauke@hauke-m.de Sun Mar 11 21:09:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Mar 2012 21:11:22 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:42576 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903724Ab2CKUJc (ORCPT ); Sun, 11 Mar 2012 21:09:32 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 7FB618F62; Sun, 11 Mar 2012 21:09:32 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bKQOmEdBOOz2; Sun, 11 Mar 2012 21:09:15 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 5F5F68F66; Sun, 11 Mar 2012 21:08:32 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 6/7] USB: OHCI: remove old SSB OHCI driver Date: Sun, 11 Mar 2012 21:08:24 +0100 Message-Id: <1331496505-18697-7-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32648 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9433 Lines: 364 This is now replaced by the new ssb USB driver, which also supports devices with an EHCI controller. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 13 -- drivers/usb/host/ohci-hcd.c | 21 +---- drivers/usb/host/ohci-ssb.c | 260 ------------------------------------------- 3 files changed, 1 insertions(+), 293 deletions(-) delete mode 100644 drivers/usb/host/ohci-ssb.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index eab27d5..665fb89 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -360,19 +360,6 @@ config USB_OHCI_HCD_PCI Enables support for PCI-bus plug-in USB controller cards. If unsure, say Y. -config USB_OHCI_HCD_SSB - bool "OHCI support for Broadcom SSB OHCI core" - depends on USB_OHCI_HCD && (SSB = y || SSB = USB_OHCI_HCD) && EXPERIMENTAL - default n - ---help--- - Support for the Sonics Silicon Backplane (SSB) attached - Broadcom USB OHCI core. - - This device is present in some embedded devices with - Broadcom based SSB bus. - - If unsure, say N. - config USB_OHCI_SH bool "OHCI support for SuperH USB controller" depends on USB_OHCI_HCD && SUPERH diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 50fbbf9..a2f4d4e 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1081,11 +1081,6 @@ MODULE_LICENSE ("GPL"); #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver #endif -#ifdef CONFIG_USB_OHCI_HCD_SSB -#include "ohci-ssb.c" -#define SSB_OHCI_DRIVER ssb_ohci_driver -#endif - #ifdef CONFIG_MFD_SM501 #include "ohci-sm501.c" #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver @@ -1134,8 +1129,7 @@ MODULE_LICENSE ("GPL"); !defined(SA1111_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && \ !defined(SM501_OHCI_DRIVER) && \ - !defined(TMIO_OHCI_DRIVER) && \ - !defined(SSB_OHCI_DRIVER) + !defined(TMIO_OHCI_DRIVER) #error "missing bus glue for ohci-hcd" #endif @@ -1201,12 +1195,6 @@ static int __init ohci_hcd_mod_init(void) goto error_pci; #endif -#ifdef SSB_OHCI_DRIVER - retval = ssb_driver_register(&SSB_OHCI_DRIVER); - if (retval) - goto error_ssb; -#endif - #ifdef SM501_OHCI_DRIVER retval = platform_driver_register(&SM501_OHCI_DRIVER); if (retval < 0) @@ -1230,10 +1218,6 @@ static int __init ohci_hcd_mod_init(void) platform_driver_unregister(&SM501_OHCI_DRIVER); error_sm501: #endif -#ifdef SSB_OHCI_DRIVER - ssb_driver_unregister(&SSB_OHCI_DRIVER); - error_ssb: -#endif #ifdef PCI_DRIVER pci_unregister_driver(&PCI_DRIVER); error_pci: @@ -1281,9 +1265,6 @@ static void __exit ohci_hcd_mod_exit(void) #ifdef SM501_OHCI_DRIVER platform_driver_unregister(&SM501_OHCI_DRIVER); #endif -#ifdef SSB_OHCI_DRIVER - ssb_driver_unregister(&SSB_OHCI_DRIVER); -#endif #ifdef PCI_DRIVER pci_unregister_driver(&PCI_DRIVER); #endif diff --git a/drivers/usb/host/ohci-ssb.c b/drivers/usb/host/ohci-ssb.c deleted file mode 100644 index 5ba1859..0000000 --- a/drivers/usb/host/ohci-ssb.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Sonics Silicon Backplane - * Broadcom USB-core OHCI driver - * - * Copyright 2007 Michael Buesch - * - * Derived from the OHCI-PCI driver - * Copyright 1999 Roman Weissgaerber - * Copyright 2000-2002 David Brownell - * Copyright 1999 Linus Torvalds - * Copyright 1999 Gregory P. Smith - * - * Derived from the USBcore related parts of Broadcom-SB - * Copyright 2005 Broadcom Corporation - * - * Licensed under the GNU/GPL. See COPYING for details. - */ -#include - - -#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29) - -struct ssb_ohci_device { - struct ohci_hcd ohci; /* _must_ be at the beginning. */ - - u32 enable_flags; -}; - -static inline -struct ssb_ohci_device *hcd_to_ssb_ohci(struct usb_hcd *hcd) -{ - return (struct ssb_ohci_device *)(hcd->hcd_priv); -} - - -static int ssb_ohci_reset(struct usb_hcd *hcd) -{ - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - struct ohci_hcd *ohci = &ohcidev->ohci; - int err; - - ohci_hcd_init(ohci); - err = ohci_init(ohci); - - return err; -} - -static int ssb_ohci_start(struct usb_hcd *hcd) -{ - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - struct ohci_hcd *ohci = &ohcidev->ohci; - int err; - - err = ohci_run(ohci); - if (err < 0) { - ohci_err(ohci, "can't start\n"); - ohci_stop(hcd); - } - - return err; -} - -static const struct hc_driver ssb_ohci_hc_driver = { - .description = "ssb-usb-ohci", - .product_desc = "SSB OHCI Controller", - .hcd_priv_size = sizeof(struct ssb_ohci_device), - - .irq = ohci_irq, - .flags = HCD_MEMORY | HCD_USB11, - - .reset = ssb_ohci_reset, - .start = ssb_ohci_start, - .stop = ohci_stop, - .shutdown = ohci_shutdown, - - .urb_enqueue = ohci_urb_enqueue, - .urb_dequeue = ohci_urb_dequeue, - .endpoint_disable = ohci_endpoint_disable, - - .get_frame_number = ohci_get_frame, - - .hub_status_data = ohci_hub_status_data, - .hub_control = ohci_hub_control, -#ifdef CONFIG_PM - .bus_suspend = ohci_bus_suspend, - .bus_resume = ohci_bus_resume, -#endif - - .start_port_reset = ohci_start_port_reset, -}; - -static void ssb_ohci_detach(struct ssb_device *dev) -{ - struct usb_hcd *hcd = ssb_get_drvdata(dev); - - if (hcd->driver->shutdown) - hcd->driver->shutdown(hcd); - usb_remove_hcd(hcd); - iounmap(hcd->regs); - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); - usb_put_hcd(hcd); - ssb_device_disable(dev, 0); -} - -static int ssb_ohci_attach(struct ssb_device *dev) -{ - struct ssb_ohci_device *ohcidev; - struct usb_hcd *hcd; - int err = -ENOMEM; - u32 tmp, flags = 0; - - if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || - dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) - return -EOPNOTSUPP; - - if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) { - /* Put the device into host-mode. */ - flags |= SSB_OHCI_TMSLOW_HOSTMODE; - ssb_device_enable(dev, flags); - } else if (dev->id.coreid == SSB_DEV_USB20_HOST) { - /* - * USB 2.0 special considerations: - * - * In addition to the standard SSB reset sequence, the Host - * Control Register must be programmed to bring the USB core - * and various phy components out of reset. - */ - ssb_device_enable(dev, 0); - ssb_write32(dev, 0x200, 0x7ff); - - /* Change Flush control reg */ - tmp = ssb_read32(dev, 0x400); - tmp &= ~8; - ssb_write32(dev, 0x400, tmp); - tmp = ssb_read32(dev, 0x400); - - /* Change Shim control reg */ - tmp = ssb_read32(dev, 0x304); - tmp &= ~0x100; - ssb_write32(dev, 0x304, tmp); - tmp = ssb_read32(dev, 0x304); - - udelay(1); - - /* Work around for 5354 failures */ - if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { - /* Change syn01 reg */ - tmp = 0x00fe00fe; - ssb_write32(dev, 0x894, tmp); - - /* Change syn03 reg */ - tmp = ssb_read32(dev, 0x89c); - tmp |= 0x1; - ssb_write32(dev, 0x89c, tmp); - } - } else - ssb_device_enable(dev, 0); - - hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev, - dev_name(dev->dev)); - if (!hcd) - goto err_dev_disable; - ohcidev = hcd_to_ssb_ohci(hcd); - ohcidev->enable_flags = flags; - - tmp = ssb_read32(dev, SSB_ADMATCH0); - hcd->rsrc_start = ssb_admatch_base(tmp); - hcd->rsrc_len = ssb_admatch_size(tmp); - hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); - if (!hcd->regs) - goto err_put_hcd; - err = usb_add_hcd(hcd, dev->irq, IRQF_SHARED); - if (err) - goto err_iounmap; - - ssb_set_drvdata(dev, hcd); - - return err; - -err_iounmap: - iounmap(hcd->regs); -err_put_hcd: - usb_put_hcd(hcd); -err_dev_disable: - ssb_device_disable(dev, flags); - return err; -} - -static int ssb_ohci_probe(struct ssb_device *dev, - const struct ssb_device_id *id) -{ - int err; - u16 chipid_top; - - /* USBcores are only connected on embedded devices. */ - chipid_top = (dev->bus->chip_id & 0xFF00); - if (chipid_top != 0x4700 && chipid_top != 0x5300) - return -ENODEV; - - /* TODO: Probably need checks here; is the core connected? */ - - if (usb_disabled()) - return -ENODEV; - - /* We currently always attach SSB_DEV_USB11_HOSTDEV - * as HOST OHCI. If we want to attach it as Client device, - * we must branch here and call into the (yet to - * be written) Client mode driver. Same for remove(). */ - - err = ssb_ohci_attach(dev); - - return err; -} - -static void ssb_ohci_remove(struct ssb_device *dev) -{ - ssb_ohci_detach(dev); -} - -#ifdef CONFIG_PM - -static int ssb_ohci_suspend(struct ssb_device *dev, pm_message_t state) -{ - ssb_device_disable(dev, 0); - - return 0; -} - -static int ssb_ohci_resume(struct ssb_device *dev) -{ - struct usb_hcd *hcd = ssb_get_drvdata(dev); - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - - ssb_device_enable(dev, ohcidev->enable_flags); - - ohci_finish_controller_resume(hcd); - return 0; -} - -#else /* !CONFIG_PM */ -#define ssb_ohci_suspend NULL -#define ssb_ohci_resume NULL -#endif /* CONFIG_PM */ - -static const struct ssb_device_id ssb_ohci_table[] = { - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), - SSB_DEVTABLE_END -}; -MODULE_DEVICE_TABLE(ssb, ssb_ohci_table); - -static struct ssb_driver ssb_ohci_driver = { - .name = KBUILD_MODNAME, - .id_table = ssb_ohci_table, - .probe = ssb_ohci_probe, - .remove = ssb_ohci_remove, - .suspend = ssb_ohci_suspend, - .resume = ssb_ohci_resume, -}; -- 1.7.5.4 From hauke@hauke-m.de Sun Mar 11 21:09:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Mar 2012 21:11:48 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:42581 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903723Ab2CKUJf (ORCPT ); Sun, 11 Mar 2012 21:09:35 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id B1B318F61; Sun, 11 Mar 2012 21:09:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c8716hg2WYLU; Sun, 11 Mar 2012 21:09:17 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id B3CDF8F67; Sun, 11 Mar 2012 21:08:32 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, Hauke Mehrtens , Gabor Juhos , Imre Kaloz Subject: [PATCH 7/7] USB: use generic platform driver on ath79 Date: Sun, 11 Mar 2012 21:08:25 +0100 Message-Id: <1331496505-18697-8-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32649 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 14471 Lines: 553 The ath79 usb driver doesn't do anything special and is now converted to the generic ehci and ohci driver. This was tested on a TP-Link TL-WR1043ND (AR9132) CC: Gabor Juhos CC: Imre Kaloz CC: linux-mips@linux-mips.org CC: Ralf Baechle Signed-off-by: Hauke Mehrtens --- arch/mips/ath79/dev-usb.c | 31 +++++- drivers/usb/host/Kconfig | 17 ---- drivers/usb/host/ehci-ath79.c | 208 ----------------------------------------- drivers/usb/host/ehci-hcd.c | 5 - drivers/usb/host/ohci-ath79.c | 151 ----------------------------- drivers/usb/host/ohci-hcd.c | 5 - 6 files changed, 25 insertions(+), 392 deletions(-) delete mode 100644 drivers/usb/host/ehci-ath79.c delete mode 100644 drivers/usb/host/ohci-ath79.c diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index 002d6d2..36e9570 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include @@ -36,14 +38,19 @@ static struct resource ath79_ohci_resources[] = { }; static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); + +static struct usb_ohci_pdata ath79_ohci_pdata = { +}; + static struct platform_device ath79_ohci_device = { - .name = "ath79-ohci", + .name = "ohci-platform", .id = -1, .resource = ath79_ohci_resources, .num_resources = ARRAY_SIZE(ath79_ohci_resources), .dev = { .dma_mask = &ath79_ohci_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &ath79_ohci_pdata, }, }; @@ -60,8 +67,20 @@ static struct resource ath79_ehci_resources[] = { }; static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); + +static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { + .has_synopsys_hc_bug = 1, + .port_power_off = 1, +}; + +static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { + .caps_offset = 0x100, + .has_tt = 1, + .port_power_off = 1, +}; + static struct platform_device ath79_ehci_device = { - .name = "ath79-ehci", + .name = "ehci-platform", .id = -1, .resource = ath79_ehci_resources, .num_resources = ARRAY_SIZE(ath79_ehci_resources), @@ -101,7 +120,7 @@ static void __init ath79_usb_setup(void) ath79_ehci_resources[0].start = AR71XX_EHCI_BASE; ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1; - ath79_ehci_device.name = "ar71xx-ehci"; + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; platform_device_register(&ath79_ehci_device); } @@ -142,7 +161,7 @@ static void __init ar724x_usb_setup(void) ath79_ehci_resources[0].start = AR724X_EHCI_BASE; ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1; - ath79_ehci_device.name = "ar724x-ehci"; + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -159,7 +178,7 @@ static void __init ar913x_usb_setup(void) ath79_ehci_resources[0].start = AR913X_EHCI_BASE; ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1; - ath79_ehci_device.name = "ar913x-ehci"; + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -176,7 +195,7 @@ static void __init ar933x_usb_setup(void) ath79_ehci_resources[0].start = AR933X_EHCI_BASE; ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; - ath79_ehci_device.name = "ar933x-ehci"; + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 665fb89..41c38e8 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -217,15 +217,6 @@ config USB_CNS3XXX_EHCI It is needed for high-speed (480Mbit/sec) USB 2.0 device support. -config USB_EHCI_ATH79 - bool "EHCI support for AR7XXX/AR9XXX SoCs" - depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X) - select USB_EHCI_ROOT_HUB_TT - default y - ---help--- - Enables support for the built-in EHCI controller present - on the Atheros AR7XXX/AR9XXX SoCs. - config USB_OXU210HP_HCD tristate "OXU210HP HCD support" depends on USB @@ -311,14 +302,6 @@ config USB_OHCI_HCD_OMAP3 Enables support for the on-chip OHCI controller on OMAP3 and later chips. -config USB_OHCI_ATH79 - bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs" - depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X) - default y - help - Enables support for the built-in OHCI controller present on the - Atheros AR71XX/AR7240 SoCs. - config USB_OHCI_HCD_PPC_SOC bool "OHCI support for on-chip PPC USB controller" depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c deleted file mode 100644 index f1424f9..0000000 --- a/drivers/usb/host/ehci-ath79.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Bus Glue for Atheros AR7XXX/AR9XXX built-in EHCI controller. - * - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * Parts of this file are based on Atheros' 2.6.15 BSP - * Copyright (C) 2007 Atheros Communications, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include - -enum { - EHCI_ATH79_IP_V1 = 0, - EHCI_ATH79_IP_V2, -}; - -static const struct platform_device_id ehci_ath79_id_table[] = { - { - .name = "ar71xx-ehci", - .driver_data = EHCI_ATH79_IP_V1, - }, - { - .name = "ar724x-ehci", - .driver_data = EHCI_ATH79_IP_V2, - }, - { - .name = "ar913x-ehci", - .driver_data = EHCI_ATH79_IP_V2, - }, - { - .name = "ar933x-ehci", - .driver_data = EHCI_ATH79_IP_V2, - }, - { - /* terminating entry */ - }, -}; - -MODULE_DEVICE_TABLE(platform, ehci_ath79_id_table); - -static int ehci_ath79_init(struct usb_hcd *hcd) -{ - struct ehci_hcd *ehci = hcd_to_ehci(hcd); - struct platform_device *pdev = to_platform_device(hcd->self.controller); - const struct platform_device_id *id; - int ret; - - id = platform_get_device_id(pdev); - if (!id) { - dev_err(hcd->self.controller, "missing device id\n"); - return -EINVAL; - } - - switch (id->driver_data) { - case EHCI_ATH79_IP_V1: - ehci->has_synopsys_hc_bug = 1; - - ehci->caps = hcd->regs; - ehci->regs = hcd->regs + - HC_LENGTH(ehci, - ehci_readl(ehci, &ehci->caps->hc_capbase)); - break; - - case EHCI_ATH79_IP_V2: - hcd->has_tt = 1; - - ehci->caps = hcd->regs + 0x100; - ehci->regs = hcd->regs + 0x100 + - HC_LENGTH(ehci, - ehci_readl(ehci, &ehci->caps->hc_capbase)); - break; - - default: - BUG(); - } - - dbg_hcs_params(ehci, "reset"); - dbg_hcc_params(ehci, "reset"); - ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); - ehci->sbrn = 0x20; - - ehci_reset(ehci); - - ret = ehci_init(hcd); - if (ret) - return ret; - - ehci_port_power(ehci, 0); - - return 0; -} - -static const struct hc_driver ehci_ath79_hc_driver = { - .description = hcd_name, - .product_desc = "Atheros built-in EHCI controller", - .hcd_priv_size = sizeof(struct ehci_hcd), - .irq = ehci_irq, - .flags = HCD_MEMORY | HCD_USB2, - - .reset = ehci_ath79_init, - .start = ehci_run, - .stop = ehci_stop, - .shutdown = ehci_shutdown, - - .urb_enqueue = ehci_urb_enqueue, - .urb_dequeue = ehci_urb_dequeue, - .endpoint_disable = ehci_endpoint_disable, - .endpoint_reset = ehci_endpoint_reset, - - .get_frame_number = ehci_get_frame, - - .hub_status_data = ehci_hub_status_data, - .hub_control = ehci_hub_control, - - .relinquish_port = ehci_relinquish_port, - .port_handed_over = ehci_port_handed_over, - - .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -}; - -static int ehci_ath79_probe(struct platform_device *pdev) -{ - struct usb_hcd *hcd; - struct resource *res; - int irq; - int ret; - - if (usb_disabled()) - return -ENODEV; - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) { - dev_dbg(&pdev->dev, "no IRQ specified\n"); - return -ENODEV; - } - irq = res->start; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_dbg(&pdev->dev, "no base address specified\n"); - return -ENODEV; - } - - hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev, - dev_name(&pdev->dev)); - if (!hcd) - return -ENOMEM; - - hcd->rsrc_start = res->start; - hcd->rsrc_len = resource_size(res); - - if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { - dev_dbg(&pdev->dev, "controller already in use\n"); - ret = -EBUSY; - goto err_put_hcd; - } - - hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); - if (!hcd->regs) { - dev_dbg(&pdev->dev, "error mapping memory\n"); - ret = -EFAULT; - goto err_release_region; - } - - ret = usb_add_hcd(hcd, irq, IRQF_SHARED); - if (ret) - goto err_iounmap; - - return 0; - -err_iounmap: - iounmap(hcd->regs); - -err_release_region: - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -err_put_hcd: - usb_put_hcd(hcd); - return ret; -} - -static int ehci_ath79_remove(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - - usb_remove_hcd(hcd); - iounmap(hcd->regs); - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); - usb_put_hcd(hcd); - - return 0; -} - -static struct platform_driver ehci_ath79_driver = { - .probe = ehci_ath79_probe, - .remove = ehci_ath79_remove, - .id_table = ehci_ath79_id_table, - .driver = { - .owner = THIS_MODULE, - .name = "ath79-ehci", - } -}; - -MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ehci"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index afe0984..b417926 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1351,11 +1351,6 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER s5p_ehci_driver #endif -#ifdef CONFIG_USB_EHCI_ATH79 -#include "ehci-ath79.c" -#define PLATFORM_DRIVER ehci_ath79_driver -#endif - #ifdef CONFIG_SPARC_LEON #include "ehci-grlib.c" #define PLATFORM_DRIVER ehci_grlib_driver diff --git a/drivers/usb/host/ohci-ath79.c b/drivers/usb/host/ohci-ath79.c deleted file mode 100644 index 18d574d..0000000 --- a/drivers/usb/host/ohci-ath79.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * OHCI HCD (Host Controller Driver) for USB. - * - * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller. - * - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * Parts of this file are based on Atheros' 2.6.15 BSP - * Copyright (C) 2007 Atheros Communications, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include - -static int __devinit ohci_ath79_start(struct usb_hcd *hcd) -{ - struct ohci_hcd *ohci = hcd_to_ohci(hcd); - int ret; - - ret = ohci_init(ohci); - if (ret < 0) - return ret; - - ret = ohci_run(ohci); - if (ret < 0) - goto err; - - return 0; - -err: - ohci_stop(hcd); - return ret; -} - -static const struct hc_driver ohci_ath79_hc_driver = { - .description = hcd_name, - .product_desc = "Atheros built-in OHCI controller", - .hcd_priv_size = sizeof(struct ohci_hcd), - - .irq = ohci_irq, - .flags = HCD_USB11 | HCD_MEMORY, - - .start = ohci_ath79_start, - .stop = ohci_stop, - .shutdown = ohci_shutdown, - - .urb_enqueue = ohci_urb_enqueue, - .urb_dequeue = ohci_urb_dequeue, - .endpoint_disable = ohci_endpoint_disable, - - /* - * scheduling support - */ - .get_frame_number = ohci_get_frame, - - /* - * root hub support - */ - .hub_status_data = ohci_hub_status_data, - .hub_control = ohci_hub_control, - .start_port_reset = ohci_start_port_reset, -}; - -static int ohci_ath79_probe(struct platform_device *pdev) -{ - struct usb_hcd *hcd; - struct resource *res; - int irq; - int ret; - - if (usb_disabled()) - return -ENODEV; - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) { - dev_dbg(&pdev->dev, "no IRQ specified\n"); - return -ENODEV; - } - irq = res->start; - - hcd = usb_create_hcd(&ohci_ath79_hc_driver, &pdev->dev, - dev_name(&pdev->dev)); - if (!hcd) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_dbg(&pdev->dev, "no base address specified\n"); - ret = -ENODEV; - goto err_put_hcd; - } - hcd->rsrc_start = res->start; - hcd->rsrc_len = resource_size(res); - - if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { - dev_dbg(&pdev->dev, "controller already in use\n"); - ret = -EBUSY; - goto err_put_hcd; - } - - hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); - if (!hcd->regs) { - dev_dbg(&pdev->dev, "error mapping memory\n"); - ret = -EFAULT; - goto err_release_region; - } - - ohci_hcd_init(hcd_to_ohci(hcd)); - - ret = usb_add_hcd(hcd, irq, 0); - if (ret) - goto err_stop_hcd; - - return 0; - -err_stop_hcd: - iounmap(hcd->regs); -err_release_region: - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -err_put_hcd: - usb_put_hcd(hcd); - return ret; -} - -static int ohci_ath79_remove(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - - usb_remove_hcd(hcd); - iounmap(hcd->regs); - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); - usb_put_hcd(hcd); - - return 0; -} - -static struct platform_driver ohci_hcd_ath79_driver = { - .probe = ohci_ath79_probe, - .remove = ohci_ath79_remove, - .shutdown = usb_hcd_platform_shutdown, - .driver = { - .name = "ath79-ohci", - .owner = THIS_MODULE, - }, -}; - -MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ohci"); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index a2f4d4e..813714d 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1106,11 +1106,6 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver #endif -#ifdef CONFIG_USB_OHCI_ATH79 -#include "ohci-ath79.c" -#define PLATFORM_DRIVER ohci_hcd_ath79_driver -#endif - #ifdef CONFIG_CPU_XLR #include "ohci-xls.c" #define PLATFORM_DRIVER ohci_xls_driver -- 1.7.5.4 From julian.calaby@gmail.com Sun Mar 11 22:59:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Mar 2012 23:00:00 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:38050 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901163Ab2CKV7p convert rfc822-to-8bit (ORCPT ); Sun, 11 Mar 2012 22:59:45 +0100 Received: by iaky10 with SMTP id y10so7126118iak.36 for ; Sun, 11 Mar 2012 14:59:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=OQHb3MNBb4Q8EbluyT6wBsi3kZDex1UyDKeu3c5X4IA=; b=jKmbXeqjHVxc7hbJ9v+Z3KJcx6kbJtiY/5cbmvwt1mXUiFG+9Z8y0HuWXu77NOmpHA gP7EysyKEVsDg3/Q/PhtS4Sdvgk6XtY0t+NZO2xofg/XA0QKgy4HfguEuSmbGFv9rkpe cGuzwDxLZrjFvv1elqEZVT/AhXVOlLO4PMB1tbJVnZs5Gvli6M1DGq/JZSAlULeqciud zpDftmfyB06XZ2xDlxjB53AI0mDflWVV/uwkZ71Y8u74GKYEWwDik4fkBin9jPw8Gk/s wElWmHrZ/J9u73U5aFm/UvpAfpY8i20v/WU+qRkzBbBF+Oph8O0DbdoEChLOtjxIi+VI tXTA== Received: by 10.43.48.65 with SMTP id uv1mr12835034icb.57.1331503178208; Sun, 11 Mar 2012 14:59:38 -0700 (PDT) MIME-Version: 1.0 Received: by 10.42.239.197 with HTTP; Sun, 11 Mar 2012 14:59:18 -0700 (PDT) In-Reply-To: <1331496505-18697-4-git-send-email-hauke@hauke-m.de> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> <1331496505-18697-4-git-send-email-hauke@hauke-m.de> From: Julian Calaby Date: Mon, 12 Mar 2012 08:59:18 +1100 Message-ID: Subject: Re: [PATCH 3/7] bcma: scan for extra address space To: Hauke Mehrtens Cc: gregkh@linuxfoundation.org, stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, =?ISO-8859-2?Q?Rafa=B3_Mi=B3ecki?= , linux-wireless@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32650 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julian.calaby@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3312 Lines: 86 Hi Hauke, On Mon, Mar 12, 2012 at 07:08, Hauke Mehrtens wrote: > Some cores like the USB core have two address spaces. In the USB host > controller one address space is used for the OHCI and the other for the > EHCI controller interface. The USB controller is the only core I found > with two address spaces. This code is based on the AI scan function > ai_scan() in shared/aiutils.c i the Broadcom SDK. > > CC: RafaÅ‚ MiÅ‚ecki > CC: linux-wireless@vger.kernel.org > Signed-off-by: Hauke Mehrtens > --- >  drivers/bcma/scan.c       |   18 +++++++++++++++++- >  include/linux/bcma/bcma.h |    1 + >  2 files changed, 18 insertions(+), 1 deletions(-) > > diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c > index 3a2f672..3c2eeed 100644 > --- a/drivers/bcma/scan.c > +++ b/drivers/bcma/scan.c > @@ -286,6 +286,22 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, >                        return -EILSEQ; >        } > > + > +       /* First Slave Address Descriptor should be port 0: > +        * the main register space for the core > +        */ > +       tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); > +       if (tmp <= 0) { > +               /* Try again to see if it is a bridge */ > +               tmp = bcma_erom_get_addr_desc(bus, eromptr, > +                                             SCAN_ADDR_TYPE_BRIDGE, 0); > +               if (tmp > 0) { > +                       pr_info("found bridge"); > +                       return -ENXIO; > +               } Should this do something if the second bcma_erom_get_addr_desc() call returns an error? We seem to be putting any errors from that call into the addr member of the core structure below. > +       } > +       core->addr = tmp; > + >        /* get & parse slave ports */ >        for (i = 0; i < ports[1]; i++) { >                for (j = 0; ; j++) { > @@ -298,7 +314,7 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, >                                break; >                        } else { >                                if (i == 0 && j == 0) > -                                       core->addr = tmp; > +                                       core->addr1 = tmp; >                        } >                } >        } > diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h > index 83c209f..7fe41e1 100644 > --- a/include/linux/bcma/bcma.h > +++ b/include/linux/bcma/bcma.h > @@ -138,6 +138,7 @@ struct bcma_device { >        u8 core_index; > >        u32 addr; > +       u32 addr1; >        u32 wrap; > >        void __iomem *io_addr; > -- > 1.7.5.4 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-wireless" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at  http://vger.kernel.org/majordomo-info.html -- Julian Calaby Email: julian.calaby@gmail.com Profile: http://www.google.com/profiles/julian.calaby/ .Plan: http://sites.google.com/site/juliancalaby/ From hauke@hauke-m.de Mon Mar 12 00:34:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Mar 2012 00:34:40 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:43439 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903599Ab2CKXed (ORCPT ); Mon, 12 Mar 2012 00:34:33 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 0BE7E8F61; Mon, 12 Mar 2012 00:34:33 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lNiQ5NWhBr51; Mon, 12 Mar 2012 00:34:18 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 33B258F60; Mon, 12 Mar 2012 00:34:18 +0100 (CET) Message-ID: <4F5D3679.3090900@hauke-m.de> Date: Mon, 12 Mar 2012 00:34:17 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Julian Calaby CC: gregkh@linuxfoundation.org, stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , linux-wireless@vger.kernel.org Subject: Re: [PATCH 3/7] bcma: scan for extra address space References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> <1331496505-18697-4-git-send-email-hauke@hauke-m.de> In-Reply-To: X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32651 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3295 Lines: 87 On 03/11/2012 10:59 PM, Julian Calaby wrote: > Hi Hauke, > > On Mon, Mar 12, 2012 at 07:08, Hauke Mehrtens wrote: >> Some cores like the USB core have two address spaces. In the USB host >> controller one address space is used for the OHCI and the other for the >> EHCI controller interface. The USB controller is the only core I found >> with two address spaces. This code is based on the AI scan function >> ai_scan() in shared/aiutils.c i the Broadcom SDK. >> >> CC: RafaÅ‚ MiÅ‚ecki >> CC: linux-wireless@vger.kernel.org >> Signed-off-by: Hauke Mehrtens >> --- >> drivers/bcma/scan.c | 18 +++++++++++++++++- >> include/linux/bcma/bcma.h | 1 + >> 2 files changed, 18 insertions(+), 1 deletions(-) >> >> diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c >> index 3a2f672..3c2eeed 100644 >> --- a/drivers/bcma/scan.c >> +++ b/drivers/bcma/scan.c >> @@ -286,6 +286,22 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, >> return -EILSEQ; >> } >> >> + >> + /* First Slave Address Descriptor should be port 0: >> + * the main register space for the core >> + */ >> + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); >> + if (tmp <= 0) { >> + /* Try again to see if it is a bridge */ >> + tmp = bcma_erom_get_addr_desc(bus, eromptr, >> + SCAN_ADDR_TYPE_BRIDGE, 0); >> + if (tmp > 0) { >> + pr_info("found bridge"); >> + return -ENXIO; >> + } > > Should this do something if the second bcma_erom_get_addr_desc() call > returns an error? We seem to be putting any errors from that call into > the addr member of the core structure below. Yes that's true, we should handle that error. If tmp <= 0 the description entry was malformed and something went wrong and we should handle it, a correctly found bridge should just be ignored. I will fix this, should I resend the hole series or just this patch? > >> + } >> + core->addr = tmp; >> + >> /* get & parse slave ports */ >> for (i = 0; i < ports[1]; i++) { >> for (j = 0; ; j++) { >> @@ -298,7 +314,7 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, >> break; >> } else { >> if (i == 0 && j == 0) >> - core->addr = tmp; >> + core->addr1 = tmp; >> } >> } >> } >> diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h >> index 83c209f..7fe41e1 100644 >> --- a/include/linux/bcma/bcma.h >> +++ b/include/linux/bcma/bcma.h >> @@ -138,6 +138,7 @@ struct bcma_device { >> u8 core_index; >> >> u32 addr; >> + u32 addr1; >> u32 wrap; >> >> void __iomem *io_addr; >> -- >> 1.7.5.4 >> >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-wireless" in >> the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html > > > From julian.calaby@gmail.com Mon Mar 12 02:31:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Mar 2012 02:31:36 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:55519 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903603Ab2CLBbU convert rfc822-to-8bit (ORCPT ); Mon, 12 Mar 2012 02:31:20 +0100 Received: by iaky10 with SMTP id y10so7395992iak.36 for ; Sun, 11 Mar 2012 18:31:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=REfPJsNXoXD0Jyksyq1s+4vcw7uYZPzw96m36+CKYN8=; b=iskjAI0n2TM1QGYnnuhp6vjdqnZvV7Le+3hbBegIGUoFhRwHSFZVOdJPUD1O6qnZDC 5xg5ukZoOpEAtnJjTa7ArYPy9uQr0YgQDHFXvmuiFaB9w0oyS6Xa2mzvKh6sOvGVRtAg ZPcqoC5awhGfhNVYYD36a2IktPp2UkgfoxWZCyKIK2oTldc+cdUH6ujzaa+0xcE8jb95 IijnGPpC4GwStqNMDIqdylnrU48rmFNT/sYCBL0B1PGm4YeofBpa7x8wJkXDgHy+nPU5 zNAh8oNpPCY/ztkVeirB3AjwlGWuLwYzSL/yzorviS2VpT6achHvY/3MdR5cVy61do4Z Efig== Received: by 10.50.222.170 with SMTP id qn10mr5981008igc.57.1331515874214; Sun, 11 Mar 2012 18:31:14 -0700 (PDT) MIME-Version: 1.0 Received: by 10.42.239.197 with HTTP; Sun, 11 Mar 2012 18:30:54 -0700 (PDT) In-Reply-To: <4F5D3679.3090900@hauke-m.de> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> <1331496505-18697-4-git-send-email-hauke@hauke-m.de> <4F5D3679.3090900@hauke-m.de> From: Julian Calaby Date: Mon, 12 Mar 2012 12:30:54 +1100 Message-ID: Subject: Re: [PATCH 3/7] bcma: scan for extra address space To: Hauke Mehrtens Cc: gregkh@linuxfoundation.org, stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, =?ISO-8859-2?Q?Rafa=B3_Mi=B3ecki?= , linux-wireless@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32652 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julian.calaby@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2643 Lines: 63 Hi Hauke, On Mon, Mar 12, 2012 at 10:34, Hauke Mehrtens wrote: > On 03/11/2012 10:59 PM, Julian Calaby wrote: >> Hi Hauke, >> >> On Mon, Mar 12, 2012 at 07:08, Hauke Mehrtens wrote: >>> Some cores like the USB core have two address spaces. In the USB host >>> controller one address space is used for the OHCI and the other for the >>> EHCI controller interface. The USB controller is the only core I found >>> with two address spaces. This code is based on the AI scan function >>> ai_scan() in shared/aiutils.c i the Broadcom SDK. >>> >>> CC: RafaÅ‚ MiÅ‚ecki >>> CC: linux-wireless@vger.kernel.org >>> Signed-off-by: Hauke Mehrtens >>> --- >>>  drivers/bcma/scan.c       |   18 +++++++++++++++++- >>>  include/linux/bcma/bcma.h |    1 + >>>  2 files changed, 18 insertions(+), 1 deletions(-) >>> >>> diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c >>> index 3a2f672..3c2eeed 100644 >>> --- a/drivers/bcma/scan.c >>> +++ b/drivers/bcma/scan.c >>> @@ -286,6 +286,22 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, >>>                        return -EILSEQ; >>>        } >>> >>> + >>> +       /* First Slave Address Descriptor should be port 0: >>> +        * the main register space for the core >>> +        */ >>> +       tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); >>> +       if (tmp <= 0) { >>> +               /* Try again to see if it is a bridge */ >>> +               tmp = bcma_erom_get_addr_desc(bus, eromptr, >>> +                                             SCAN_ADDR_TYPE_BRIDGE, 0); >>> +               if (tmp > 0) { >>> +                       pr_info("found bridge"); >>> +                       return -ENXIO; >>> +               } >> >> Should this do something if the second bcma_erom_get_addr_desc() call >> returns an error? We seem to be putting any errors from that call into >> the addr member of the core structure below. > Yes that's true, we should handle that error. If tmp <= 0 the > description entry was malformed and something went wrong and we should > handle it, a correctly found bridge should just be ignored. > > I will fix this, should I resend the hole series or just this patch? I'm not sure the rest of the series made it to linux-wireless, so maybe you should resend everything. Thanks, -- Julian Calaby Email: julian.calaby@gmail.com Profile: http://www.google.com/profiles/julian.calaby/ .Plan: http://sites.google.com/site/juliancalaby/ From florian@openwrt.org Mon Mar 12 09:26:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Mar 2012 09:26:43 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:57863 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903605Ab2CLI01 (ORCPT ); Mon, 12 Mar 2012 09:26:27 +0100 Received: by eaak13 with SMTP id k13so1058132eaa.36 for ; Mon, 12 Mar 2012 01:26:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=l4uZEszjRydjNa5DZF7zggS9m3BWd9R6b37IkLWiPQA=; b=orS/l8mRdEZAimkHl+iUqlTxD+9XEYNZxzIBwV80zPZAgqmVyJGt/BUKRbfeDrCVfa IvfEfRoQTqG5TZPTLEScK8z5kvQzGV/09QkeZx/rYZ2bVq7pU30sQCD5lPQHr7Hbjdn3 LXRknPn8I8D7pE1bjjPGo8omtFZ0mZt+K4k0xwE6L9INbbE1fQ/AI/rK8bMZRMoNXUcB R+10wNmtHpyl/VoWWuxbPjHUsvi9sSn83qlXEl1Tq6TISD/L6jvwH9OrjPJn4bzQDT5U HAqWOeSRsa16ktZrnwiVk7iqJquZaJceeDnYc7dkw+HdEBVCFkFFZOpiqpwfXeKFqoat ocrg== Received: by 10.14.194.134 with SMTP id m6mr1684953een.4.1331540781945; Mon, 12 Mar 2012 01:26:21 -0700 (PDT) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id y11sm47281892eem.3.2012.03.12.01.26.18 (version=SSLv3 cipher=OTHER); Mon, 12 Mar 2012 01:26:19 -0700 (PDT) Message-ID: <4F5DB2F4.5080408@openwrt.org> Date: Mon, 12 Mar 2012 09:25:24 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Grant Likely CC: ralf@linux-mips.org, Tanguy Bouzeloc , linux-mips@linux-mips.org, spi-devel-general@lists.sourceforge.net Subject: Re: [PATCH v4] spi: add Broadcom BCM63xx SPI controller driver References: <1328019048-5892-10-git-send-email-florian@openwrt.org> <1328091249-10389-1-git-send-email-florian@openwrt.org> <20120309220440.073653E0880@localhost> In-Reply-To: <20120309220440.073653E0880@localhost> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 32653 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 17304 Lines: 582 Hi Grant, Le 03/09/12 23:04, Grant Likely a écrit : > On Wed, 1 Feb 2012 11:14:09 +0100, Florian Fainelli wrote: >> This patch adds support for the SPI controller found on the Broadcom BCM63xx >> SoCs. >> >> Signed-off-by: Tanguy Bouzeloc >> Signed-off-by: Florian Fainelli >> Acked-by: Grant Likely > Applied, thanks. > > In v3.4, the spi subsystem is gaining core support for spi message queues. > You should look at migrating this driver to use it in the v3.5 timeframe. Thanks! I will follow up with a patch taking advantage of the generic spi message queuing. > > g. > >> --- >> Changes since v3: >> - changed bcm_spi_readb to use readb accessor instead of readw >> - fixed multiple __dev{init,exit} annotations >> >> Changes since v2: >> - reworked bcm63xx_spi_setup_transfer to choose closest spi transfer >> frequency >> - removed invalid 25Mhz frequency >> - fixed some minor checkpatch issues >> >> Changes since v1: >> - switched to the devm_* API which frees resources automatically >> - switched to dev_pm_ops >> - use module_platform_driver >> - remove MODULE_VERSION() >> - fixed return value when clock is not present using PTR_ERR() >> - fixed probe() error path to disable clock in case of failure >> >> drivers/spi/Kconfig | 6 + >> drivers/spi/Makefile | 1 + >> drivers/spi/spi-bcm63xx.c | 486 +++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 493 insertions(+), 0 deletions(-) >> create mode 100644 drivers/spi/spi-bcm63xx.c >> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig >> index 3f9a47e..16818ac 100644 >> --- a/drivers/spi/Kconfig >> +++ b/drivers/spi/Kconfig >> @@ -94,6 +94,12 @@ config SPI_AU1550 >> If you say yes to this option, support will be included for the >> PSC SPI controller found on Au1550, Au1200 and Au1300 series. >> >> +config SPI_BCM63XX >> + tristate "Broadcom BCM63xx SPI controller" >> + depends on BCM63XX >> + help >> + Enable support for the SPI controller on the Broadcom BCM63xx SoCs. >> + >> config SPI_BITBANG >> tristate "Utilities for Bitbanging SPI masters" >> help >> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile >> index 61c3261..be38f73 100644 >> --- a/drivers/spi/Makefile >> +++ b/drivers/spi/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.o >> obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o >> obj-$(CONFIG_SPI_ATH79) += spi-ath79.o >> obj-$(CONFIG_SPI_AU1550) += spi-au1550.o >> +obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o >> obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o >> obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o >> obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o >> diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c >> new file mode 100644 >> index 0000000..f01b264 >> --- /dev/null >> +++ b/drivers/spi/spi-bcm63xx.c >> @@ -0,0 +1,486 @@ >> +/* >> + * Broadcom BCM63xx SPI controller support >> + * >> + * Copyright (C) 2009-2011 Florian Fainelli >> + * Copyright (C) 2010 Tanguy Bouzeloc >> + * >> + * This program is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License >> + * as published by the Free Software Foundation; either version 2 >> + * of the License, or (at your option) any later version. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * You should have received a copy of the GNU General Public License >> + * along with this program; if not, write to the >> + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> + >> +#define PFX KBUILD_MODNAME >> +#define DRV_VER "0.1.2" >> + >> +struct bcm63xx_spi { >> + spinlock_t lock; >> + int stopping; >> + struct completion done; >> + >> + void __iomem *regs; >> + int irq; >> + >> + /* Platform data */ >> + u32 speed_hz; >> + unsigned fifo_size; >> + >> + /* Data buffers */ >> + const unsigned char *tx_ptr; >> + unsigned char *rx_ptr; >> + >> + /* data iomem */ >> + u8 __iomem *tx_io; >> + const u8 __iomem *rx_io; >> + >> + int remaining_bytes; >> + >> + struct clk *clk; >> + struct platform_device *pdev; >> +}; >> + >> +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, >> + unsigned int offset) >> +{ >> + return bcm_readb(bs->regs + bcm63xx_spireg(offset)); >> +} >> + >> +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, >> + unsigned int offset) >> +{ >> + return bcm_readw(bs->regs + bcm63xx_spireg(offset)); >> +} >> + >> +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, >> + u8 value, unsigned int offset) >> +{ >> + bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); >> +} >> + >> +static inline void bcm_spi_writew(struct bcm63xx_spi *bs, >> + u16 value, unsigned int offset) >> +{ >> + bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); >> +} >> + >> +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { >> + { 20000000, SPI_CLK_20MHZ }, >> + { 12500000, SPI_CLK_12_50MHZ }, >> + { 6250000, SPI_CLK_6_250MHZ }, >> + { 3125000, SPI_CLK_3_125MHZ }, >> + { 1563000, SPI_CLK_1_563MHZ }, >> + { 781000, SPI_CLK_0_781MHZ }, >> + { 391000, SPI_CLK_0_391MHZ } >> +}; >> + >> +static int bcm63xx_spi_setup_transfer(struct spi_device *spi, >> + struct spi_transfer *t) >> +{ >> + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); >> + u8 bits_per_word; >> + u8 clk_cfg, reg; >> + u32 hz; >> + int i; >> + >> + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; >> + hz = (t) ? t->speed_hz : spi->max_speed_hz; >> + if (bits_per_word != 8) { >> + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", >> + __func__, bits_per_word); >> + return -EINVAL; >> + } >> + >> + if (spi->chip_select> spi->master->num_chipselect) { >> + dev_err(&spi->dev, "%s, unsupported slave %d\n", >> + __func__, spi->chip_select); >> + return -EINVAL; >> + } >> + >> + /* Find the closest clock configuration */ >> + for (i = 0; i< SPI_CLK_MASK; i++) { >> + if (hz<= bcm63xx_spi_freq_table[i][0]) { >> + clk_cfg = bcm63xx_spi_freq_table[i][1]; >> + break; >> + } >> + } >> + >> + /* No matching configuration found, default to lowest */ >> + if (i == SPI_CLK_MASK) >> + clk_cfg = SPI_CLK_0_391MHZ; >> + >> + /* clear existing clock configuration bits of the register */ >> + reg = bcm_spi_readb(bs, SPI_CLK_CFG); >> + reg&= ~SPI_CLK_MASK; >> + reg |= clk_cfg; >> + >> + bcm_spi_writeb(bs, reg, SPI_CLK_CFG); >> + dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", >> + clk_cfg, hz); >> + >> + return 0; >> +} >> + >> +/* the spi->mode bits understood by this driver: */ >> +#define MODEBITS (SPI_CPOL | SPI_CPHA) >> + >> +static int bcm63xx_spi_setup(struct spi_device *spi) >> +{ >> + struct bcm63xx_spi *bs; >> + int ret; >> + >> + bs = spi_master_get_devdata(spi->master); >> + >> + if (bs->stopping) >> + return -ESHUTDOWN; >> + >> + if (!spi->bits_per_word) >> + spi->bits_per_word = 8; >> + >> + if (spi->mode& ~MODEBITS) { >> + dev_err(&spi->dev, "%s, unsupported mode bits %x\n", >> + __func__, spi->mode& ~MODEBITS); >> + return -EINVAL; >> + } >> + >> + ret = bcm63xx_spi_setup_transfer(spi, NULL); >> + if (ret< 0) { >> + dev_err(&spi->dev, "setup: unsupported mode bits %x\n", >> + spi->mode& ~MODEBITS); >> + return ret; >> + } >> + >> + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", >> + __func__, spi->mode& MODEBITS, spi->bits_per_word, 0); >> + >> + return 0; >> +} >> + >> +/* Fill the TX FIFO with as many bytes as possible */ >> +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs) >> +{ >> + u8 size; >> + >> + /* Fill the Tx FIFO with as many bytes as possible */ >> + size = bs->remaining_bytes< bs->fifo_size ? bs->remaining_bytes : >> + bs->fifo_size; >> + memcpy_toio(bs->tx_io, bs->tx_ptr, size); >> + bs->remaining_bytes -= size; >> +} >> + >> +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) >> +{ >> + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); >> + u16 msg_ctl; >> + u16 cmd; >> + >> + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", >> + t->tx_buf, t->rx_buf, t->len); >> + >> + /* Transmitter is inhibited */ >> + bs->tx_ptr = t->tx_buf; >> + bs->rx_ptr = t->rx_buf; >> + init_completion(&bs->done); >> + >> + if (t->tx_buf) { >> + bs->remaining_bytes = t->len; >> + bcm63xx_spi_fill_tx_fifo(bs); >> + } >> + >> + /* Enable the command done interrupt which >> + * we use to determine completion of a command */ >> + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); >> + >> + /* Fill in the Message control register */ >> + msg_ctl = (t->len<< SPI_BYTE_CNT_SHIFT); >> + >> + if (t->rx_buf&& t->tx_buf) >> + msg_ctl |= (SPI_FD_RW<< SPI_MSG_TYPE_SHIFT); >> + else if (t->rx_buf) >> + msg_ctl |= (SPI_HD_R<< SPI_MSG_TYPE_SHIFT); >> + else if (t->tx_buf) >> + msg_ctl |= (SPI_HD_W<< SPI_MSG_TYPE_SHIFT); >> + >> + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); >> + >> + /* Issue the transfer */ >> + cmd = SPI_CMD_START_IMMEDIATE; >> + cmd |= (0<< SPI_CMD_PREPEND_BYTE_CNT_SHIFT); >> + cmd |= (spi->chip_select<< SPI_CMD_DEVICE_ID_SHIFT); >> + bcm_spi_writew(bs, cmd, SPI_CMD); >> + wait_for_completion(&bs->done); >> + >> + /* Disable the CMD_DONE interrupt */ >> + bcm_spi_writeb(bs, 0, SPI_INT_MASK); >> + >> + return t->len - bs->remaining_bytes; >> +} >> + >> +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m) >> +{ >> + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); >> + struct spi_transfer *t; >> + int ret = 0; >> + >> + if (unlikely(list_empty(&m->transfers))) >> + return -EINVAL; >> + >> + if (bs->stopping) >> + return -ESHUTDOWN; >> + >> + list_for_each_entry(t,&m->transfers, transfer_list) { >> + ret += bcm63xx_txrx_bufs(spi, t); >> + } >> + >> + m->complete(m->context); >> + >> + return ret; >> +} >> + >> +/* This driver supports single master mode only. Hence >> + * CMD_DONE is the only interrupt we care about >> + */ >> +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) >> +{ >> + struct spi_master *master = (struct spi_master *)dev_id; >> + struct bcm63xx_spi *bs = spi_master_get_devdata(master); >> + u8 intr; >> + u16 cmd; >> + >> + /* Read interupts and clear them immediately */ >> + intr = bcm_spi_readb(bs, SPI_INT_STATUS); >> + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); >> + bcm_spi_writeb(bs, 0, SPI_INT_MASK); >> + >> + /* A tansfer completed */ >> + if (intr& SPI_INTR_CMD_DONE) { >> + u8 rx_tail; >> + >> + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); >> + >> + /* Read out all the data */ >> + if (rx_tail) >> + memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail); >> + >> + /* See if there is more data to send */ >> + if (bs->remaining_bytes> 0) { >> + bcm63xx_spi_fill_tx_fifo(bs); >> + >> + /* Start the transfer */ >> + bcm_spi_writew(bs, SPI_HD_W<< SPI_MSG_TYPE_SHIFT, >> + SPI_MSG_CTL); >> + cmd = bcm_spi_readw(bs, SPI_CMD); >> + cmd |= SPI_CMD_START_IMMEDIATE; >> + cmd |= (0<< SPI_CMD_PREPEND_BYTE_CNT_SHIFT); >> + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); >> + bcm_spi_writew(bs, cmd, SPI_CMD); >> + } else { >> + complete(&bs->done); >> + } >> + } >> + >> + return IRQ_HANDLED; >> +} >> + >> + >> +static int __devinit bcm63xx_spi_probe(struct platform_device *pdev) >> +{ >> + struct resource *r; >> + struct device *dev =&pdev->dev; >> + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data; >> + int irq; >> + struct spi_master *master; >> + struct clk *clk; >> + struct bcm63xx_spi *bs; >> + int ret; >> + >> + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + if (!r) { >> + dev_err(dev, "no iomem\n"); >> + ret = -ENXIO; >> + goto out; >> + } >> + >> + irq = platform_get_irq(pdev, 0); >> + if (irq< 0) { >> + dev_err(dev, "no irq\n"); >> + ret = -ENXIO; >> + goto out; >> + } >> + >> + clk = clk_get(dev, "spi"); >> + if (IS_ERR(clk)) { >> + dev_err(dev, "no clock for device\n"); >> + ret = PTR_ERR(clk); >> + goto out; >> + } >> + >> + master = spi_alloc_master(dev, sizeof(*bs)); >> + if (!master) { >> + dev_err(dev, "out of memory\n"); >> + ret = -ENOMEM; >> + goto out_clk; >> + } >> + >> + bs = spi_master_get_devdata(master); >> + init_completion(&bs->done); >> + >> + platform_set_drvdata(pdev, master); >> + bs->pdev = pdev; >> + >> + if (!devm_request_mem_region(&pdev->dev, r->start, >> + resource_size(r), PFX)) { >> + dev_err(dev, "iomem request failed\n"); >> + ret = -ENXIO; >> + goto out_err; >> + } >> + >> + bs->regs = devm_ioremap_nocache(&pdev->dev, r->start, >> + resource_size(r)); >> + if (!bs->regs) { >> + dev_err(dev, "unable to ioremap regs\n"); >> + ret = -ENOMEM; >> + goto out_err; >> + } >> + >> + bs->irq = irq; >> + bs->clk = clk; >> + bs->fifo_size = pdata->fifo_size; >> + >> + ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, >> + pdev->name, master); >> + if (ret) { >> + dev_err(dev, "unable to request irq\n"); >> + goto out_err; >> + } >> + >> + master->bus_num = pdata->bus_num; >> + master->num_chipselect = pdata->num_chipselect; >> + master->setup = bcm63xx_spi_setup; >> + master->transfer = bcm63xx_transfer; >> + bs->speed_hz = pdata->speed_hz; >> + bs->stopping = 0; >> + bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); >> + bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); >> + spin_lock_init(&bs->lock); >> + >> + /* Initialize hardware */ >> + clk_enable(bs->clk); >> + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); >> + >> + /* register and we are done */ >> + ret = spi_register_master(master); >> + if (ret) { >> + dev_err(dev, "spi register failed\n"); >> + goto out_clk_disable; >> + } >> + >> + dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n", >> + r->start, irq, bs->fifo_size, DRV_VER); >> + >> + return 0; >> + >> +out_clk_disable: >> + clk_disable(clk); >> +out_err: >> + platform_set_drvdata(pdev, NULL); >> + spi_master_put(master); >> +out_clk: >> + clk_put(clk); >> +out: >> + return ret; >> +} >> + >> +static int __devexit bcm63xx_spi_remove(struct platform_device *pdev) >> +{ >> + struct spi_master *master = platform_get_drvdata(pdev); >> + struct bcm63xx_spi *bs = spi_master_get_devdata(master); >> + >> + /* reset spi block */ >> + bcm_spi_writeb(bs, 0, SPI_INT_MASK); >> + spin_lock(&bs->lock); >> + bs->stopping = 1; >> + >> + /* HW shutdown */ >> + clk_disable(bs->clk); >> + clk_put(bs->clk); >> + >> + spin_unlock(&bs->lock); >> + platform_set_drvdata(pdev, 0); >> + spi_unregister_master(master); >> + >> + return 0; >> +} >> + >> +#ifdef CONFIG_PM >> +static int bcm63xx_spi_suspend(struct device *dev) >> +{ >> + struct spi_master *master = >> + platform_get_drvdata(to_platform_device(dev)); >> + struct bcm63xx_spi *bs = spi_master_get_devdata(master); >> + >> + clk_disable(bs->clk); >> + >> + return 0; >> +} >> + >> +static int bcm63xx_spi_resume(struct device *dev) >> +{ >> + struct spi_master *master = >> + platform_get_drvdata(to_platform_device(dev)); >> + struct bcm63xx_spi *bs = spi_master_get_devdata(master); >> + >> + clk_enable(bs->clk); >> + >> + return 0; >> +} >> + >> +static const struct dev_pm_ops bcm63xx_spi_pm_ops = { >> + .suspend = bcm63xx_spi_suspend, >> + .resume = bcm63xx_spi_resume, >> +}; >> + >> +#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) >> +#else >> +#define BCM63XX_SPI_PM_OPS NULL >> +#endif >> + >> +static struct platform_driver bcm63xx_spi_driver = { >> + .driver = { >> + .name = "bcm63xx-spi", >> + .owner = THIS_MODULE, >> + .pm = BCM63XX_SPI_PM_OPS, >> + }, >> + .probe = bcm63xx_spi_probe, >> + .remove = __devexit_p(bcm63xx_spi_remove), >> +}; >> + >> +module_platform_driver(bcm63xx_spi_driver); >> + >> +MODULE_ALIAS("platform:bcm63xx_spi"); >> +MODULE_AUTHOR("Florian Fainelli"); >> +MODULE_AUTHOR("Tanguy Bouzeloc"); >> +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); >> +MODULE_LICENSE("GPL"); >> -- >> 1.7.5.4 >> >> >> ------------------------------------------------------------------------------ >> Keep Your Developer Skills Current with LearnDevNow! >> The most comprehensive online learning library for Microsoft developers >> is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, >> Metro Style Apps, more. Free future releases when you subscribe now! >> http://p.sf.net/sfu/learndevnow-d2d >> _______________________________________________ >> spi-devel-general mailing list >> spi-devel-general@lists.sourceforge.net >> https://lists.sourceforge.net/lists/listinfo/spi-devel-general From stern@rowland.harvard.edu Mon Mar 12 15:28:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Mar 2012 15:28:33 +0100 (CET) Received: from iolanthe.rowland.org ([192.131.102.54]:44884 "HELO iolanthe.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1903614Ab2CLO2Z (ORCPT ); Mon, 12 Mar 2012 15:28:25 +0100 Received: (qmail 1237 invoked by uid 2102); 12 Mar 2012 10:28:22 -0400 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 12 Mar 2012 10:28:22 -0400 Date: Mon, 12 Mar 2012 10:28:22 -0400 (EDT) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: Hauke Mehrtens cc: gregkh@linuxfoundation.org, , , , Subject: Re: [PATCH 6/7] USB: OHCI: remove old SSB OHCI driver In-Reply-To: <1331496505-18697-7-git-send-email-hauke@hauke-m.de> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32654 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1648 Lines: 47 On Sun, 11 Mar 2012, Hauke Mehrtens wrote: > This is now replaced by the new ssb USB driver, which also supports > devices with an EHCI controller. > > Signed-off-by: Hauke Mehrtens > --- > drivers/usb/host/Kconfig | 13 -- > drivers/usb/host/ohci-hcd.c | 21 +---- > drivers/usb/host/ohci-ssb.c | 260 ------------------------------------------- > 3 files changed, 1 insertions(+), 293 deletions(-) > delete mode 100644 drivers/usb/host/ohci-ssb.c > > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig > index eab27d5..665fb89 100644 > --- a/drivers/usb/host/Kconfig > +++ b/drivers/usb/host/Kconfig > @@ -360,19 +360,6 @@ config USB_OHCI_HCD_PCI > Enables support for PCI-bus plug-in USB controller cards. > If unsure, say Y. > > -config USB_OHCI_HCD_SSB > - bool "OHCI support for Broadcom SSB OHCI core" > - depends on USB_OHCI_HCD && (SSB = y || SSB = USB_OHCI_HCD) && EXPERIMENTAL > - default n > - ---help--- > - Support for the Sonics Silicon Backplane (SSB) attached > - Broadcom USB OHCI core. > - > - This device is present in some embedded devices with > - Broadcom based SSB bus. > - > - If unsure, say N. > - I don't like the idea of removing this section entirely. It will leave people wondering what happened to their driver. Instead, for the next few kernel releases, how about leaving this section in place and causing it to select USB_OHCI_HCD_PLATFORM? Maybe also add a line to the help section explaining that from now on, this driver has been replaced by the generic OHCI platform driver. And likewise for the SSB EHCI driver, of course. Alan Stern From linville@tuxdriver.com Mon Mar 12 18:47:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Mar 2012 18:47:28 +0100 (CET) Received: from charlotte.tuxdriver.com ([70.61.120.58]:48687 "EHLO smtp.tuxdriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903607Ab2CLRrV (ORCPT ); Mon, 12 Mar 2012 18:47:21 +0100 Received: from uucp by smtp.tuxdriver.com with local-rmail (Exim 4.63) (envelope-from ) id 1S79Kr-0003t1-Uy; Mon, 12 Mar 2012 13:47:06 -0400 Received: from linville-8530p.local (linville-8530p.local [127.0.0.1]) by linville-8530p.local (8.14.4/8.14.4) with ESMTP id q2CHfHqh022284; Mon, 12 Mar 2012 13:41:17 -0400 Received: (from linville@localhost) by linville-8530p.local (8.14.4/8.14.4/Submit) id q2CHfE4U022263; Mon, 12 Mar 2012 13:41:14 -0400 Date: Mon, 12 Mar 2012 13:41:14 -0400 From: "John W. Linville" To: Julian Calaby Cc: Hauke Mehrtens , gregkh@linuxfoundation.org, stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= , linux-wireless@vger.kernel.org Subject: Re: [PATCH 3/7] bcma: scan for extra address space Message-ID: <20120312174113.GC2778@tuxdriver.com> References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> <1331496505-18697-4-git-send-email-hauke@hauke-m.de> <4F5D3679.3090900@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32655 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linville@tuxdriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 498 Lines: 15 On Mon, Mar 12, 2012 at 12:30:54PM +1100, Julian Calaby wrote: > Hi Hauke, > > On Mon, Mar 12, 2012 at 10:34, Hauke Mehrtens wrote: > > I will fix this, should I resend the hole series or just this patch? > > I'm not sure the rest of the series made it to linux-wireless, so > maybe you should resend everything. FWIW, this was the only one I saw... -- John W. Linville Someday the world will need a hero, and you linville@tuxdriver.com might be all we have. Be ready. From florian@openwrt.org Mon Mar 12 18:59:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Mar 2012 19:00:17 +0100 (CET) Received: from mail-ee0-f49.google.com ([74.125.83.49]:43024 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903607Ab2CLR75 (ORCPT ); Mon, 12 Mar 2012 18:59:57 +0100 Received: by eekb45 with SMTP id b45so1575926eek.36 for ; Mon, 12 Mar 2012 10:59:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=krrrIeZEoK84wf8W9pCPEJm1+SRSZXAkuPT4wSctbWQ=; b=AGZO6QQFRVr7IMH7hF8AoA7XhyI1E3+krzm0B6o0PGQRw48bGSD4yaqcGka2g0I/L/ TwJOnCX/bSMOg2VlyYmUPxpifpVQ1e5GrygMfGHnNkHDZ6TQVDvSHA1QSWNXi7SmXrMp hYQZSUGWWei/pAEN33FNfJfRAhe/09Q4gGjNXCrxBlm/yIrpNNGQfZOp+c4oMPHeSvwa L6KAtdj9m52xe2BqEKumxwleglvHKNN04srZE+I5uPQRREaG+qPi/87txFlM1WZy+fTg B1RZY6iK8T3PPno0Qsultr+Fez2rWWk2UVAYaFc9wHTmmya4Wm1Y4g4RCiBl8SZvCKZ5 ZJYw== Received: by 10.213.114.7 with SMTP id c7mr985680ebq.144.1331575191806; Mon, 12 Mar 2012 10:59:51 -0700 (PDT) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id r44sm14965613eef.2.2012.03.12.10.59.49 (version=SSLv3 cipher=OTHER); Mon, 12 Mar 2012 10:59:49 -0700 (PDT) Message-ID: <4F5E395F.9020603@openwrt.org> Date: Mon, 12 Mar 2012 18:58:55 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: "John W. Linville" CC: Julian Calaby , Hauke Mehrtens , gregkh@linuxfoundation.org, stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , linux-wireless@vger.kernel.org Subject: Re: [PATCH 3/7] bcma: scan for extra address space References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> <1331496505-18697-4-git-send-email-hauke@hauke-m.de> <4F5D3679.3090900@hauke-m.de> <20120312174113.GC2778@tuxdriver.com> In-Reply-To: <20120312174113.GC2778@tuxdriver.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 32656 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 567 Lines: 19 Le 03/12/12 18:41, John W. Linville a écrit : > On Mon, Mar 12, 2012 at 12:30:54PM +1100, Julian Calaby wrote: >> Hi Hauke, >> >> On Mon, Mar 12, 2012 at 10:34, Hauke Mehrtens wrote: > >>> I will fix this, should I resend the hole series or just this patch? >> >> I'm not sure the rest of the series made it to linux-wireless, so >> maybe you should resend everything. > > FWIW, this was the only one I saw... For some reasons I received it from linux-mips-bounces using another email account, but only patch 3 CC'd linux-wireless. -- Florian From hauke@hauke-m.de Mon Mar 12 21:48:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Mar 2012 21:48:27 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:46742 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903609Ab2CLUsV (ORCPT ); Mon, 12 Mar 2012 21:48:21 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id B8FC58F61; Mon, 12 Mar 2012 21:48:19 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LFUMMMykI914; Mon, 12 Mar 2012 21:47:49 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 137BC8F60; Mon, 12 Mar 2012 21:47:34 +0100 (CET) Message-ID: <4F5E60E2.3080203@hauke-m.de> Date: Mon, 12 Mar 2012 21:47:30 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Florian Fainelli CC: "John W. Linville" , Julian Calaby , gregkh@linuxfoundation.org, stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , linux-wireless@vger.kernel.org Subject: Re: [PATCH 3/7] bcma: scan for extra address space References: <1331496505-18697-1-git-send-email-hauke@hauke-m.de> <1331496505-18697-4-git-send-email-hauke@hauke-m.de> <4F5D3679.3090900@hauke-m.de> <20120312174113.GC2778@tuxdriver.com> <4F5E395F.9020603@openwrt.org> In-Reply-To: <4F5E395F.9020603@openwrt.org> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32657 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 802 Lines: 24 On 03/12/2012 06:58 PM, Florian Fainelli wrote: > > > Le 03/12/12 18:41, John W. Linville a écrit : >> On Mon, Mar 12, 2012 at 12:30:54PM +1100, Julian Calaby wrote: >>> Hi Hauke, >>> >>> On Mon, Mar 12, 2012 at 10:34, Hauke Mehrtens wrote: >> >>>> I will fix this, should I resend the hole series or just this patch? >>> >>> I'm not sure the rest of the series made it to linux-wireless, so >>> maybe you should resend everything. >> >> FWIW, this was the only one I saw... > > For some reasons I received it from linux-mips-bounces using another > email account, but only patch 3 CC'd linux-wireless. Sorry for the confusion. I didn't send all patches to linux-wireless as the others are just touching usb and mips. The next round will go completely to linux-wireless. Hauke From hauke@hauke-m.de Mon Mar 12 21:51:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Mar 2012 21:51:09 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:46789 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903609Ab2CLUvD (ORCPT ); Mon, 12 Mar 2012 21:51:03 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id AF2E28F61; Mon, 12 Mar 2012 21:51:02 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HWolDuQ-qkvJ; Mon, 12 Mar 2012 21:50:49 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id E9C4C8F60; Mon, 12 Mar 2012 21:50:48 +0100 (CET) Message-ID: <4F5E61A8.20903@hauke-m.de> Date: Mon, 12 Mar 2012 21:50:48 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Alan Stern CC: gregkh@linuxfoundation.org, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org Subject: Re: [PATCH 6/7] USB: OHCI: remove old SSB OHCI driver References: In-Reply-To: X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32658 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1777 Lines: 49 On 03/12/2012 03:28 PM, Alan Stern wrote: > On Sun, 11 Mar 2012, Hauke Mehrtens wrote: > >> This is now replaced by the new ssb USB driver, which also supports >> devices with an EHCI controller. >> >> Signed-off-by: Hauke Mehrtens >> --- >> drivers/usb/host/Kconfig | 13 -- >> drivers/usb/host/ohci-hcd.c | 21 +---- >> drivers/usb/host/ohci-ssb.c | 260 ------------------------------------------- >> 3 files changed, 1 insertions(+), 293 deletions(-) >> delete mode 100644 drivers/usb/host/ohci-ssb.c >> >> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig >> index eab27d5..665fb89 100644 >> --- a/drivers/usb/host/Kconfig >> +++ b/drivers/usb/host/Kconfig >> @@ -360,19 +360,6 @@ config USB_OHCI_HCD_PCI >> Enables support for PCI-bus plug-in USB controller cards. >> If unsure, say Y. >> >> -config USB_OHCI_HCD_SSB >> - bool "OHCI support for Broadcom SSB OHCI core" >> - depends on USB_OHCI_HCD && (SSB = y || SSB = USB_OHCI_HCD) && EXPERIMENTAL >> - default n >> - ---help--- >> - Support for the Sonics Silicon Backplane (SSB) attached >> - Broadcom USB OHCI core. >> - >> - This device is present in some embedded devices with >> - Broadcom based SSB bus. >> - >> - If unsure, say N. >> - > > I don't like the idea of removing this section entirely. It will leave > people wondering what happened to their driver. > > Instead, for the next few kernel releases, how about leaving this > section in place and causing it to select USB_OHCI_HCD_PLATFORM? Maybe > also add a line to the help section explaining that from now on, this > driver has been replaced by the generic OHCI platform driver. > > And likewise for the SSB EHCI driver, of course. That sounds good, I will change that. Hauke From dhowells@redhat.com Tue Mar 13 00:38:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Mar 2012 00:39:08 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:61844 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903614Ab2CLXiz (ORCPT ); Tue, 13 Mar 2012 00:38:55 +0100 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q2CNckrM020838 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 12 Mar 2012 19:38:46 -0400 Received: from warthog.procyon.org.uk ([10.3.112.12]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q2CNcc8I015473; Mon, 12 Mar 2012 19:38:39 -0400 Organization: Red Hat UK Ltd. Registered Address: Red Hat UK Ltd, Amberley Place, 107-111 Peascod Street, Windsor, Berkshire, SI4 1TE, United Kingdom. Registered in England and Wales under Company Registration No. 3798903 From: David Howells Subject: [PATCH 15/35] Disintegrate asm/system.h for MIPS [ver #2] To: paul.gortmaker@windriver.com, hpa@zytor.com Cc: torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, arnd@arndb.de, David Howells , linux-mips@linux-mips.org Date: Mon, 12 Mar 2012 23:38:37 +0000 Message-ID: <20120312233837.13888.87741.stgit@warthog.procyon.org.uk> In-Reply-To: <20120312233602.13888.27659.stgit@warthog.procyon.org.uk> References: <20120312233602.13888.27659.stgit@warthog.procyon.org.uk> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-archive-position: 32659 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhowells@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 46814 Lines: 1572 Disintegrate asm/system.h for MIPS. Signed-off-by: David Howells cc: linux-mips@linux-mips.org --- arch/mips/cavium-octeon/setup.c | 1 arch/mips/cavium-octeon/smp.c | 1 arch/mips/dec/ecc-berr.c | 1 arch/mips/dec/kn01-berr.c | 1 arch/mips/dec/kn02xa-berr.c | 1 arch/mips/dec/wbflush.c | 1 arch/mips/emma/markeins/irq.c | 1 arch/mips/fw/arc/misc.c | 1 arch/mips/include/asm/atomic.h | 2 arch/mips/include/asm/cmpxchg.h | 124 +++++++++++++ arch/mips/include/asm/dma.h | 1 arch/mips/include/asm/exec.h | 17 ++ arch/mips/include/asm/mach-au1x00/au1000_dma.h | 1 arch/mips/include/asm/processor.h | 7 + arch/mips/include/asm/setup.h | 11 + arch/mips/include/asm/switch_to.h | 85 +++++++++ arch/mips/include/asm/system.h | 236 ------------------------ arch/mips/include/asm/txx9/jmr3927.h | 1 arch/mips/kernel/cpu-bugs64.c | 1 arch/mips/kernel/cpu-probe.c | 1 arch/mips/kernel/irq-rm7000.c | 1 arch/mips/kernel/irq-rm9000.c | 1 arch/mips/kernel/irq.c | 1 arch/mips/kernel/irq_cpu.c | 1 arch/mips/kernel/mips-mt.c | 1 arch/mips/kernel/process.c | 1 arch/mips/kernel/ptrace.c | 1 arch/mips/kernel/ptrace32.c | 1 arch/mips/kernel/rtlx.c | 1 arch/mips/kernel/setup.c | 1 arch/mips/kernel/signal.c | 1 arch/mips/kernel/signal32.c | 1 arch/mips/kernel/signal_n32.c | 1 arch/mips/kernel/smp-bmips.c | 1 arch/mips/kernel/smp-cmp.c | 1 arch/mips/kernel/smp-mt.c | 1 arch/mips/kernel/smp.c | 1 arch/mips/kernel/smtc-proc.c | 1 arch/mips/kernel/smtc.c | 1 arch/mips/kernel/spram.c | 1 arch/mips/kernel/syscall.c | 1 arch/mips/kernel/traps.c | 1 arch/mips/kernel/unaligned.c | 1 arch/mips/kernel/vpe.c | 1 arch/mips/lasat/reset.c | 1 arch/mips/math-emu/dsemul.c | 1 arch/mips/mipssim/sim_smtc.c | 1 arch/mips/mm/c-octeon.c | 1 arch/mips/mm/c-r3k.c | 1 arch/mips/mm/c-r4k.c | 1 arch/mips/mm/c-tx39.c | 1 arch/mips/mm/fault.c | 1 arch/mips/mm/page.c | 1 arch/mips/mm/sc-ip22.c | 1 arch/mips/mm/sc-mips.c | 1 arch/mips/mm/sc-r5k.c | 1 arch/mips/mm/tlb-r3k.c | 1 arch/mips/mm/tlb-r4k.c | 1 arch/mips/mm/tlb-r8k.c | 1 arch/mips/mm/tlbex.c | 1 arch/mips/mti-malta/malta-init.c | 1 arch/mips/netlogic/common/irq.c | 1 arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c | 1 arch/mips/pmc-sierra/msp71xx/msp_irq_per.c | 1 arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c | 1 arch/mips/pmc-sierra/yosemite/irq.c | 1 arch/mips/pmc-sierra/yosemite/prom.c | 1 arch/mips/powertv/asic/irq_asic.c | 1 arch/mips/powertv/init.c | 1 arch/mips/rb532/irq.c | 1 arch/mips/sgi-ip22/ip22-berr.c | 1 arch/mips/sgi-ip22/ip22-reset.c | 1 arch/mips/sgi-ip22/ip28-berr.c | 1 arch/mips/sgi-ip27/ip27-irq.c | 1 arch/mips/sgi-ip27/ip27-reset.c | 1 arch/mips/sgi-ip32/ip32-irq.c | 1 arch/mips/sgi-ip32/ip32-reset.c | 1 arch/mips/sibyte/bcm1480/irq.c | 1 arch/mips/sibyte/common/sb_tbprof.c | 1 arch/mips/sibyte/sb1250/bus_watcher.c | 1 arch/mips/sibyte/sb1250/irq.c | 1 arch/mips/sni/reset.c | 1 arch/mips/vr41xx/common/irq.c | 1 arch/mips/vr41xx/common/pmu.c | 1 84 files changed, 250 insertions(+), 309 deletions(-) create mode 100644 arch/mips/include/asm/exec.h create mode 100644 arch/mips/include/asm/switch_to.h diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 260b273..d3a9f012 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index b1535fe..599a6db 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c index 7abce66..5abf4e8 100644 --- a/arch/mips/dec/ecc-berr.c +++ b/arch/mips/dec/ecc-berr.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c index 94d23b4..44d8a87 100644 --- a/arch/mips/dec/kn01-berr.c +++ b/arch/mips/dec/kn01-berr.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c index 07ca540..ebb73c5 100644 --- a/arch/mips/dec/kn02xa-berr.c +++ b/arch/mips/dec/kn02xa-berr.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/dec/wbflush.c b/arch/mips/dec/wbflush.c index 925c052..46ef903 100644 --- a/arch/mips/dec/wbflush.c +++ b/arch/mips/dec/wbflush.c @@ -17,7 +17,6 @@ #include #include -#include #include static void wbflush_kn01(void); diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index 7798887..b5f0825 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -27,7 +27,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/fw/arc/misc.c b/arch/mips/fw/arc/misc.c index 29627fb..7cf80ca 100644 --- a/arch/mips/fw/arc/misc.c +++ b/arch/mips/fw/arc/misc.c @@ -17,7 +17,6 @@ #include #include #include -#include VOID ArcHalt(VOID) diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 1d93f81..3f4c5cb 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -18,8 +18,8 @@ #include #include #include +#include #include -#include #define ATOMIC_INIT(i) { (i) } diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index d8d1c28..285a41f 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -9,6 +9,130 @@ #define __ASM_CMPXCHG_H #include +#include + +static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) +{ + __u32 retval; + + smp_mb__before_llsc(); + + if (kernel_uses_llsc && R10000_LLSC_WAR) { + unsigned long dummy; + + __asm__ __volatile__( + " .set mips3 \n" + "1: ll %0, %3 # xchg_u32 \n" + " .set mips0 \n" + " move %2, %z4 \n" + " .set mips3 \n" + " sc %2, %1 \n" + " beqzl %2, 1b \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } else if (kernel_uses_llsc) { + unsigned long dummy; + + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %0, %3 # xchg_u32 \n" + " .set mips0 \n" + " move %2, %z4 \n" + " .set mips3 \n" + " sc %2, %1 \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } while (unlikely(!dummy)); + } else { + unsigned long flags; + + raw_local_irq_save(flags); + retval = *m; + *m = val; + raw_local_irq_restore(flags); /* implies memory barrier */ + } + + smp_llsc_mb(); + + return retval; +} + +#ifdef CONFIG_64BIT +static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) +{ + __u64 retval; + + smp_mb__before_llsc(); + + if (kernel_uses_llsc && R10000_LLSC_WAR) { + unsigned long dummy; + + __asm__ __volatile__( + " .set mips3 \n" + "1: lld %0, %3 # xchg_u64 \n" + " move %2, %z4 \n" + " scd %2, %1 \n" + " beqzl %2, 1b \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } else if (kernel_uses_llsc) { + unsigned long dummy; + + do { + __asm__ __volatile__( + " .set mips3 \n" + " lld %0, %3 # xchg_u64 \n" + " move %2, %z4 \n" + " scd %2, %1 \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } while (unlikely(!dummy)); + } else { + unsigned long flags; + + raw_local_irq_save(flags); + retval = *m; + *m = val; + raw_local_irq_restore(flags); /* implies memory barrier */ + } + + smp_llsc_mb(); + + return retval; +} +#else +extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val); +#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels +#endif + +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + switch (size) { + case 4: + return __xchg_u32(ptr, x); + case 8: + return __xchg_u64(ptr, x); + } + + return x; +} + +#define xchg(ptr, x) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \ + \ + ((__typeof__(*(ptr))) \ + __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \ +}) #define __HAVE_ARCH_CMPXCHG 1 diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h index 2d47da6..f5097f6 100644 --- a/arch/mips/include/asm/dma.h +++ b/arch/mips/include/asm/dma.h @@ -15,7 +15,6 @@ #include /* need byte IO */ #include /* And spinlocks */ #include -#include #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER diff --git a/arch/mips/include/asm/exec.h b/arch/mips/include/asm/exec.h new file mode 100644 index 0000000..c1f6afa --- /dev/null +++ b/arch/mips/include/asm/exec.h @@ -0,0 +1,17 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics + * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#ifndef _ASM_EXEC_H +#define _ASM_EXEC_H + +extern unsigned long arch_align_stack(unsigned long sp); + +#endif /* _ASM_EXEC_H */ diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h index 59f5b55..ba4cf0e 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h +++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h @@ -33,7 +33,6 @@ #include /* need byte IO */ #include /* And spinlocks */ #include -#include #define NUM_AU1000_DMA_CHANNELS 8 diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index c104f10..20e9dcf 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -19,7 +19,6 @@ #include #include #include -#include /* * Return current * instruction pointer ("program counter"). @@ -356,6 +355,12 @@ unsigned long get_wchan(struct task_struct *p); #define ARCH_HAS_PREFETCHW #define prefetchw(x) __builtin_prefetch((x), 1, 1) +/* + * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP + * systems. + */ +#define __ARCH_WANT_UNLOCKED_CTXSW + #endif #endif /* _ASM_PROCESSOR_H */ diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index 50511aa..6dce6d8 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -5,6 +5,17 @@ #ifdef __KERNEL__ extern void setup_early_printk(void); + +extern void set_handler(unsigned long offset, void *addr, unsigned long len); +extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); + +typedef void (*vi_handler_t)(void); +extern void *set_vi_handler(int n, vi_handler_t addr); + +extern void *set_except_vector(int n, void *addr); +extern unsigned long ebase; +extern void per_cpu_trap_init(void); + #endif /* __KERNEL__ */ #endif /* __SETUP_H */ diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h new file mode 100644 index 0000000..5d33621 --- /dev/null +++ b/arch/mips/include/asm/switch_to.h @@ -0,0 +1,85 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics + * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#ifndef _ASM_SWITCH_TO_H +#define _ASM_SWITCH_TO_H + +#include +#include +#include + +struct task_struct; + +/* + * switch_to(n) should switch tasks to task nr n, first + * checking that n isn't the current task, in which case it does nothing. + */ +extern asmlinkage void *resume(void *last, void *next, void *next_ti); + +extern unsigned int ll_bit; +extern struct task_struct *ll_task; + +#ifdef CONFIG_MIPS_MT_FPAFF + +/* + * Handle the scheduler resume end of FPU affinity management. We do this + * inline to try to keep the overhead down. If we have been forced to run on + * a "CPU" with an FPU because of a previous high level of FP computation, + * but did not actually use the FPU during the most recent time-slice (CU1 + * isn't set), we undo the restriction on cpus_allowed. + * + * We're not calling set_cpus_allowed() here, because we have no need to + * force prompt migration - we're already switching the current CPU to a + * different thread. + */ + +#define __mips_mt_fpaff_switch_to(prev) \ +do { \ + struct thread_info *__prev_ti = task_thread_info(prev); \ + \ + if (cpu_has_fpu && \ + test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \ + (!(KSTK_STATUS(prev) & ST0_CU1))) { \ + clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \ + prev->cpus_allowed = prev->thread.user_cpus_allowed; \ + } \ + next->thread.emulated_fp = 0; \ +} while(0) + +#else +#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) +#endif + +#define __clear_software_ll_bit() \ +do { \ + if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \ + ll_bit = 0; \ +} while (0) + +#define switch_to(prev, next, last) \ +do { \ + __mips_mt_fpaff_switch_to(prev); \ + if (cpu_has_dsp) \ + __save_dsp(prev); \ + __clear_software_ll_bit(); \ + (last) = resume(prev, next, task_thread_info(next)); \ +} while (0) + +#define finish_arch_switch(prev) \ +do { \ + if (cpu_has_dsp) \ + __restore_dsp(current); \ + if (cpu_has_userlocal) \ + write_c0_userlocal(current_thread_info()->tp_value); \ + __restore_watch(); \ +} while (0) + +#endif /* _ASM_SWITCH_TO_H */ diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index 6018c80..a7f4057 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -1,235 +1,5 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle - * Copyright (C) 1996 by Paul M. Antoine - * Copyright (C) 1999 Silicon Graphics - * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. - */ -#ifndef _ASM_SYSTEM_H -#define _ASM_SYSTEM_H - -#include -#include -#include - -#include +/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */ #include #include -#include -#include -#include -#include - - -/* - * switch_to(n) should switch tasks to task nr n, first - * checking that n isn't the current task, in which case it does nothing. - */ -extern asmlinkage void *resume(void *last, void *next, void *next_ti); - -struct task_struct; - -extern unsigned int ll_bit; -extern struct task_struct *ll_task; - -#ifdef CONFIG_MIPS_MT_FPAFF - -/* - * Handle the scheduler resume end of FPU affinity management. We do this - * inline to try to keep the overhead down. If we have been forced to run on - * a "CPU" with an FPU because of a previous high level of FP computation, - * but did not actually use the FPU during the most recent time-slice (CU1 - * isn't set), we undo the restriction on cpus_allowed. - * - * We're not calling set_cpus_allowed() here, because we have no need to - * force prompt migration - we're already switching the current CPU to a - * different thread. - */ - -#define __mips_mt_fpaff_switch_to(prev) \ -do { \ - struct thread_info *__prev_ti = task_thread_info(prev); \ - \ - if (cpu_has_fpu && \ - test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \ - (!(KSTK_STATUS(prev) & ST0_CU1))) { \ - clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \ - prev->cpus_allowed = prev->thread.user_cpus_allowed; \ - } \ - next->thread.emulated_fp = 0; \ -} while(0) - -#else -#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) -#endif - -#define __clear_software_ll_bit() \ -do { \ - if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \ - ll_bit = 0; \ -} while (0) - -#define switch_to(prev, next, last) \ -do { \ - __mips_mt_fpaff_switch_to(prev); \ - if (cpu_has_dsp) \ - __save_dsp(prev); \ - __clear_software_ll_bit(); \ - (last) = resume(prev, next, task_thread_info(next)); \ -} while (0) - -#define finish_arch_switch(prev) \ -do { \ - if (cpu_has_dsp) \ - __restore_dsp(current); \ - if (cpu_has_userlocal) \ - write_c0_userlocal(current_thread_info()->tp_value); \ - __restore_watch(); \ -} while (0) - -static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) -{ - __u32 retval; - - smp_mb__before_llsc(); - - if (kernel_uses_llsc && R10000_LLSC_WAR) { - unsigned long dummy; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %3 # xchg_u32 \n" - " .set mips0 \n" - " move %2, %z4 \n" - " .set mips3 \n" - " sc %2, %1 \n" - " beqzl %2, 1b \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } else if (kernel_uses_llsc) { - unsigned long dummy; - - do { - __asm__ __volatile__( - " .set mips3 \n" - " ll %0, %3 # xchg_u32 \n" - " .set mips0 \n" - " move %2, %z4 \n" - " .set mips3 \n" - " sc %2, %1 \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } while (unlikely(!dummy)); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - *m = val; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_llsc_mb(); - - return retval; -} - -#ifdef CONFIG_64BIT -static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) -{ - __u64 retval; - - smp_mb__before_llsc(); - - if (kernel_uses_llsc && R10000_LLSC_WAR) { - unsigned long dummy; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %3 # xchg_u64 \n" - " move %2, %z4 \n" - " scd %2, %1 \n" - " beqzl %2, 1b \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } else if (kernel_uses_llsc) { - unsigned long dummy; - - do { - __asm__ __volatile__( - " .set mips3 \n" - " lld %0, %3 # xchg_u64 \n" - " move %2, %z4 \n" - " scd %2, %1 \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } while (unlikely(!dummy)); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - *m = val; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_llsc_mb(); - - return retval; -} -#else -extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val); -#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels -#endif - -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - switch (size) { - case 4: - return __xchg_u32(ptr, x); - case 8: - return __xchg_u64(ptr, x); - } - - return x; -} - -#define xchg(ptr, x) \ -({ \ - BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \ - \ - ((__typeof__(*(ptr))) \ - __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \ -}) - -extern void set_handler(unsigned long offset, void *addr, unsigned long len); -extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); - -typedef void (*vi_handler_t)(void); -extern void *set_vi_handler(int n, vi_handler_t addr); - -extern void *set_except_vector(int n, void *addr); -extern unsigned long ebase; -extern void per_cpu_trap_init(void); - -/* - * See include/asm-ia64/system.h; prevents deadlock on SMP - * systems. - */ -#define __ARCH_WANT_UNLOCKED_CTXSW - -extern unsigned long arch_align_stack(unsigned long sp); - -#endif /* _ASM_SYSTEM_H */ +#include +#include diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h index a409c44..8808d7f 100644 --- a/arch/mips/include/asm/txx9/jmr3927.h +++ b/arch/mips/include/asm/txx9/jmr3927.h @@ -12,7 +12,6 @@ #include #include -#include #include /* CS */ diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c index f305ca1..bc794f7 100644 --- a/arch/mips/kernel/cpu-bugs64.c +++ b/arch/mips/kernel/cpu-bugs64.c @@ -16,7 +16,6 @@ #include #include #include -#include static char bug64hit[] __initdata = "reliable operation impossible!\n%s"; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0bab464..5099201 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index a8a8977..b0662cf 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c @@ -16,7 +16,6 @@ #include #include -#include static inline void unmask_rm7k_irq(struct irq_data *d) { diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index 38874a4..1282b9a 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c @@ -17,7 +17,6 @@ #include #include -#include static inline void unmask_rm9k_irq(struct irq_data *d) { diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 7f50318..a5aa43d 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -23,7 +23,6 @@ #include #include -#include #include #ifdef CONFIG_KGDB diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 191eb52..972263b 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -35,7 +35,6 @@ #include #include #include -#include static inline void unmask_mips_irq(struct irq_data *d) { diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c index c23d11f..7f3376b 100644 --- a/arch/mips/kernel/mips-mt.c +++ b/arch/mips/kernel/mips-mt.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 7955409..5bfaea8 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 7786b60..7c24c29 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index 32644b4..a3b0178 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index a9d801d..b8c18dc 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 058e964..c504b21 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -31,7 +31,6 @@ #include #include #include -#include #include struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index f852400..185ca00 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "signal-common.h" diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index aae9866..e5ee38e 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index ee24d81..ae29e89 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index d5e950a..ca67356 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index fe30951..e7e03ec 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ce9e286..ff17868 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 32c1e95..a37b082 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/kernel/smtc-proc.c b/arch/mips/kernel/smtc-proc.c index 928a5a6..145771c 100644 --- a/arch/mips/kernel/smtc-proc.c +++ b/arch/mips/kernel/smtc-proc.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 0a42ff3..c4f75bb 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 1821d12..6af08d8 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index d027657..b08220c 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -37,6 +37,7 @@ #include #include #include +#include /* * For historic reasons the pipe(2) syscall on MIPS has an unusual calling diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d79ae54..cfdaaa4 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -45,7 +45,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index aedb894..9c58bdf 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -85,7 +85,6 @@ #include #include #include -#include #define STR(x) __STR(x) #define __STR(x) #x diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index bfa12a4..f6f9152 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -49,7 +49,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c index b1e7a89..e21f0b9 100644 --- a/arch/mips/lasat/reset.c +++ b/arch/mips/lasat/reset.c @@ -21,7 +21,6 @@ #include #include -#include #include #include "picvue.h" diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 3c4a8c5..384a3b0 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mipssim/sim_smtc.c b/arch/mips/mipssim/sim_smtc.c index 9150639..3c104ab 100644 --- a/arch/mips/mipssim/sim_smtc.c +++ b/arch/mips/mipssim/sim_smtc.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index cf7895d..1f9ca07 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 0765583..031c4c2 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 4f9eb0b..f62d64f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include /* for run_uncached() */ diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index a43c197c..87d23ca 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 69ebd58..c14f6df 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -22,7 +22,6 @@ #include #include -#include #include #include #include /* For VMALLOC_END */ diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 36272f7..cc0b626 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c index a6bd11f..1eb708e 100644 --- a/arch/mips/mm/sc-ip22.c +++ b/arch/mips/mm/sc-ip22.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 9cca8de..93d937b 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mm/sc-r5k.c b/arch/mips/mm/sc-r5k.c index ae1e533..8d90ff2 100644 --- a/arch/mips/mm/sc-r5k.c +++ b/arch/mips/mm/sc-r5k.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index ed1fa46..a63d1ed 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 2dc6253..d2572cb 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -18,7 +18,6 @@ #include #include #include -#include #include extern void build_tlb_refill_handler(void); diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c index 3d95f76..91c2499 100644 --- a/arch/mips/mm/tlb-r8k.c +++ b/arch/mips/mm/tlb-r8k.c @@ -17,7 +17,6 @@ #include #include #include -#include extern void build_tlb_refill_handler(void); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index e06370f..0bc485b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * TLB load/store/modify handlers. diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 4b988b9..27a6cdb 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c index 49a4f6c..e52bfcb 100644 --- a/arch/mips/netlogic/common/irq.c +++ b/arch/mips/netlogic/common/irq.c @@ -43,7 +43,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c index c4fa2d7..2e6f7ca 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c @@ -16,7 +16,6 @@ #include #include -#include #include #include diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c index 98fd009..598b6a6 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c @@ -16,7 +16,6 @@ #include #include -#include #include #include diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c index 5bbcc47..83a1c5e 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c @@ -16,7 +16,6 @@ #include #include -#include #include #include diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c index 25bbbf4..6590812 100644 --- a/arch/mips/pmc-sierra/yosemite/irq.c +++ b/arch/mips/pmc-sierra/yosemite/irq.c @@ -44,7 +44,6 @@ #include #include #include -#include #include /* Hypertransport specific */ diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c index dcc926e..6a2754c 100644 --- a/arch/mips/pmc-sierra/yosemite/prom.c +++ b/arch/mips/pmc-sierra/yosemite/prom.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c index 7fb97fb..fa9ae95 100644 --- a/arch/mips/powertv/asic/irq_asic.c +++ b/arch/mips/powertv/asic/irq_asic.c @@ -17,7 +17,6 @@ #include #include -#include #include diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c index 8355228..1cf5abb 100644 --- a/arch/mips/powertv/init.c +++ b/arch/mips/powertv/init.c @@ -26,7 +26,6 @@ #include #include -#include #include #include diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c index 7c6db74..f298430 100644 --- a/arch/mips/rb532/irq.c +++ b/arch/mips/rb532/irq.c @@ -42,7 +42,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/sgi-ip22/ip22-berr.c b/arch/mips/sgi-ip22/ip22-berr.c index 911d399..3f6ccd5 100644 --- a/arch/mips/sgi-ip22/ip22-berr.c +++ b/arch/mips/sgi-ip22/ip22-berr.c @@ -9,7 +9,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c index 45b6694..20363d2 100644 --- a/arch/mips/sgi-ip22/ip22-reset.c +++ b/arch/mips/sgi-ip22/ip22-reset.c @@ -18,7 +18,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip22/ip28-berr.c b/arch/mips/sgi-ip22/ip28-berr.c index 88c684e..0626555 100644 --- a/arch/mips/sgi-ip22/ip28-berr.c +++ b/arch/mips/sgi-ip22/ip28-berr.c @@ -11,7 +11,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 2364223..69a939a 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/sgi-ip27/ip27-reset.c b/arch/mips/sgi-ip27/ip27-reset.c index c170761..f347bc6 100644 --- a/arch/mips/sgi-ip27/ip27-reset.c +++ b/arch/mips/sgi-ip27/ip27-reset.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index a092860..e7d5054 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index 9b95d80..1f823da 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 09740d6..215713e 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index 48853ab..e8c4538 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -53,7 +53,6 @@ #define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT #endif -#include #include #define SBPROF_TB_MAJOR 240 diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c index 45274bd..86e6e54 100644 --- a/arch/mips/sibyte/sb1250/bus_watcher.c +++ b/arch/mips/sibyte/sb1250/bus_watcher.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 76ee045..340aaf6 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -26,7 +26,6 @@ #include #include -#include #include #include diff --git a/arch/mips/sni/reset.c b/arch/mips/sni/reset.c index 79f8d70..244f942 100644 --- a/arch/mips/sni/reset.c +++ b/arch/mips/sni/reset.c @@ -5,7 +5,6 @@ */ #include #include -#include #include /* diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index fad2bef..ae0e4ee 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c @@ -22,7 +22,6 @@ #include #include -#include #include typedef struct irq_cascade { diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index 692b4e8..9fbf5f0 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -30,7 +30,6 @@ #include #include #include -#include #define PMU_TYPE1_BASE 0x0b0000a0UL #define PMU_TYPE1_SIZE 0x0eUL From hauke@hauke-m.de Tue Mar 13 01:05:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Mar 2012 01:05:31 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47474 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903616Ab2CMAFX (ORCPT ); Tue, 13 Mar 2012 01:05:23 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 13FA38F68; Tue, 13 Mar 2012 01:05:23 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id l4TC8tuLcxUB; Tue, 13 Mar 2012 01:05:09 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 46EC58F60; Tue, 13 Mar 2012 01:05:09 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH v4 0/7] USB: OHCI/EHCI: generic platform driver Date: Tue, 13 Mar 2012 01:04:46 +0100 Message-Id: <1331597093-425-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32660 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3172 Lines: 75 This EHCI/OHCI platform driver should replace the simple EHCI and OHCI platform drivers. It was developed to be used for the USB core of the Broadcom SoCs supported by ssb and bcma, but it should also work for other devices. Drivers like ehci-ath79.c, ehci-xls.c and ehci-ixp4xx.c should be relative easy be ported to this EHCI driver. And drivers like ohci-ath79.c, ohci-ppc-soc.c, ohci-sh.c and ohci-xls.c should be easy be ported to the this OHCI driver. I am unable to test the suspend and resume part, as my SoC does not support this, but most of the platform driver do not support suspend/resume too. The code here should work, but was never runtime tested. This also contains patches adding USB support for the SoCs based on ssb and bcma and converts the ath79 code to use the generic usb driver. This patch series is based on the usb tree and should go through it to Linus. v4: * handle error when searching for a bridge on bcma * leave old Kconfig options and mark them deprecated and select the new driver v3: * add patches for bcma and ssb usb driver again * add patch to convert ath79 to use the generic platform driver v2: * split include/linux/usb/hci_driver.h into include/linux /usb/ehci_pdriver.h and include/linux/usb/ohci_pdriver.h * remove flags from include/linux/usb/{e,o}ehci_pdriver.h * add kernel doc * add some more options into the structs to activate hardware quirks. Hauke Mehrtens (7): USB: OHCI: Add a generic platform device driver USB: EHCI: Add a generic platform device driver bcma: scan for extra address space USB: Add driver for the bcma bus USB: Add driver for the ssb bus USB: OHCI: remove old SSB OHCI driver USB: use generic platform driver on ath79 arch/mips/ath79/dev-usb.c | 31 +++- drivers/bcma/scan.c | 19 ++- drivers/usb/host/Kconfig | 63 +++++++- drivers/usb/host/Makefile | 2 + drivers/usb/host/bcma-hcd.c | 334 ++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ehci-ath79.c | 208 ------------------------ drivers/usb/host/ehci-hcd.c | 10 +- drivers/usb/host/ehci-platform.c | 198 ++++++++++++++++++++++ drivers/usb/host/ohci-ath79.c | 151 ----------------- drivers/usb/host/ohci-hcd.c | 31 +--- drivers/usb/host/ohci-platform.c | 194 ++++++++++++++++++++++ drivers/usb/host/ohci-ssb.c | 260 ----------------------------- drivers/usb/host/ssb-hcd.c | 279 +++++++++++++++++++++++++++++++ include/linux/bcma/bcma.h | 1 + include/linux/usb/ehci_pdriver.h | 46 ++++++ include/linux/usb/ohci_pdriver.h | 38 +++++ 16 files changed, 1206 insertions(+), 659 deletions(-) create mode 100644 drivers/usb/host/bcma-hcd.c delete mode 100644 drivers/usb/host/ehci-ath79.c create mode 100644 drivers/usb/host/ehci-platform.c delete mode 100644 drivers/usb/host/ohci-ath79.c create mode 100644 drivers/usb/host/ohci-platform.c delete mode 100644 drivers/usb/host/ohci-ssb.c create mode 100644 drivers/usb/host/ssb-hcd.c create mode 100644 include/linux/usb/ehci_pdriver.h create mode 100644 include/linux/usb/ohci_pdriver.h -- 1.7.5.4 From hauke@hauke-m.de Tue Mar 13 01:05:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Mar 2012 01:05:58 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47482 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903614Ab2CMAFZ (ORCPT ); Tue, 13 Mar 2012 01:05:25 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 22F2E8F60; Tue, 13 Mar 2012 01:05:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MBpclNva9B2o; Tue, 13 Mar 2012 01:05:10 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id B11488F61; Tue, 13 Mar 2012 01:05:09 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH v4 1/7] USB: OHCI: Add a generic platform device driver Date: Tue, 13 Mar 2012 01:04:47 +0100 Message-Id: <1331597093-425-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331597093-425-1-git-send-email-hauke@hauke-m.de> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32661 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8248 Lines: 300 This adds a generic driver for platform devices. It works like the PCI driver and is based on it. This is for devices which do not have an own bus but their OHCI controller works like a PCI controller. It will be used for the Broadcom bcma and ssb USB OHCI controller. Acked-by: Alan Stern Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 10 ++ drivers/usb/host/ohci-hcd.c | 5 + drivers/usb/host/ohci-platform.c | 194 ++++++++++++++++++++++++++++++++++++++ include/linux/usb/ohci_pdriver.h | 38 ++++++++ 4 files changed, 247 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ohci-platform.c create mode 100644 include/linux/usb/ohci_pdriver.h diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 353cdd4..fd521f3 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -393,6 +393,16 @@ config USB_CNS3XXX_OHCI Enable support for the CNS3XXX SOC's on-chip OHCI controller. It is needed for low-speed USB 1.0 device support. +config USB_OHCI_HCD_PLATFORM + bool "Generic OHCI driver for a platform device" + depends on USB_OHCI_HCD && EXPERIMENTAL + default n + ---help--- + Adds an OHCI host driver for a generic platform device, which + provieds a memory space and an irq. + + If unsure, say N. + config USB_OHCI_BIG_ENDIAN_DESC bool depends on USB_OHCI_HCD diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 34b9edd..50fbbf9 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1121,6 +1121,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_xls_driver #endif +#ifdef CONFIG_USB_OHCI_HCD_PLATFORM +#include "ohci-platform.c" +#define PLATFORM_DRIVER ohci_platform_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c new file mode 100644 index 0000000..ec5c679 --- /dev/null +++ b/drivers/usb/host/ohci-platform.c @@ -0,0 +1,194 @@ +/* + * Generic platform ohci driver + * + * Copyright 2007 Michael Buesch + * Copyright 2011-2012 Hauke Mehrtens + * + * Derived from the OCHI-SSB driver + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include + +static int ohci_platform_reset(struct usb_hcd *hcd) +{ + struct platform_device *pdev = to_platform_device(hcd->self.controller); + struct usb_ohci_pdata *pdata = pdev->dev.platform_data; + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int err; + + if (pdata->big_endian_desc) + ohci->flags |= OHCI_QUIRK_BE_DESC; + if (pdata->big_endian_mmio) + ohci->flags |= OHCI_QUIRK_BE_MMIO; + if (pdata->no_big_frame_no) + ohci->flags |= OHCI_QUIRK_FRAME_NO; + + ohci_hcd_init(ohci); + err = ohci_init(ohci); + + return err; +} + +static int ohci_platform_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int err; + + err = ohci_run(ohci); + if (err < 0) { + ohci_err(ohci, "can't start\n"); + ohci_stop(hcd); + } + + return err; +} + +static const struct hc_driver ohci_platform_hc_driver = { + .description = hcd_name, + .product_desc = "Generic Platform OHCI Controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + + .irq = ohci_irq, + .flags = HCD_MEMORY | HCD_USB11, + + .reset = ohci_platform_reset, + .start = ohci_platform_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + + .get_frame_number = ohci_get_frame, + + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, +#ifdef CONFIG_PM + .bus_suspend = ohci_bus_suspend, + .bus_resume = ohci_bus_resume, +#endif + + .start_port_reset = ohci_start_port_reset, +}; + +static int __devinit ohci_platform_probe(struct platform_device *dev) +{ + struct usb_hcd *hcd; + struct resource *res_mem; + int irq; + int err = -ENOMEM; + + BUG_ON(!dev->dev.platform_data); + + if (usb_disabled()) + return -ENODEV; + + irq = platform_get_irq(dev, 0); + if (irq < 0) { + pr_err("no irq provieded"); + return irq; + } + + res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res_mem) { + pr_err("no memory recourse provieded"); + return -ENXIO; + } + + hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev, + dev_name(&dev->dev)); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = res_mem->start; + hcd->rsrc_len = resource_size(res_mem); + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_err("controller already in use"); + err = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) + goto err_release_region; + err = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (err) + goto err_iounmap; + + platform_set_drvdata(dev, hcd); + + return err; + +err_iounmap: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return err; +} + +static int __devexit ohci_platform_remove(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + platform_set_drvdata(dev, NULL); + + return 0; +} + +#ifdef CONFIG_PM + +static int ohci_platform_suspend(struct device *dev) +{ + return 0; +} + +static int ohci_platform_resume(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + + ohci_finish_controller_resume(hcd); + return 0; +} + +#else /* !CONFIG_PM */ +#define ohci_platform_suspend NULL +#define ohci_platform_resume NULL +#endif /* CONFIG_PM */ + +static const struct platform_device_id ohci_platform_table[] = { + { "ohci-platform", 0 }, + { } +}; +MODULE_DEVICE_TABLE(platform, ohci_platform_table); + +static const struct dev_pm_ops ohci_platform_pm_ops = { + .suspend = ohci_platform_suspend, + .resume = ohci_platform_resume, +}; + +static struct platform_driver ohci_platform_driver = { + .id_table = ohci_platform_table, + .probe = ohci_platform_probe, + .remove = __devexit_p(ohci_platform_remove), + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .owner = THIS_MODULE, + .name = "ohci-platform", + .pm = &ohci_platform_pm_ops, + } +}; diff --git a/include/linux/usb/ohci_pdriver.h b/include/linux/usb/ohci_pdriver.h new file mode 100644 index 0000000..2808f2a --- /dev/null +++ b/include/linux/usb/ohci_pdriver.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2012 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __USB_CORE_OHCI_PDRIVER_H +#define __USB_CORE_OHCI_PDRIVER_H + +/** + * struct usb_ohci_pdata - platform_data for generic ohci driver + * + * @big_endian_desc: BE descriptors + * @big_endian_mmio: BE registers + * @no_big_frame_no: no big endian frame_no shift + * + * These are general configuration options for the OHCI controller. All of + * these options are activating more or less workarounds for some hardware. + */ +struct usb_ohci_pdata { + unsigned big_endian_desc:1; + unsigned big_endian_mmio:1; + unsigned no_big_frame_no:1; +}; + +#endif /* __USB_CORE_OHCI_PDRIVER_H */ -- 1.7.5.4 From hauke@hauke-m.de Tue Mar 13 01:05:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Mar 2012 01:06:23 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47502 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903621Ab2CMAFj (ORCPT ); Tue, 13 Mar 2012 01:05:39 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 06F198F6A; Tue, 13 Mar 2012 01:05:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZHHjA1-hHAWF; Tue, 13 Mar 2012 01:05:23 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 0FAE78F62; Tue, 13 Mar 2012 01:05:10 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH v4 2/7] USB: EHCI: Add a generic platform device driver Date: Tue, 13 Mar 2012 01:04:48 +0100 Message-Id: <1331597093-425-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331597093-425-1-git-send-email-hauke@hauke-m.de> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32662 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9035 Lines: 312 This adds a generic driver for platform devices. It works like the PCI driver and is based on it. This is for devices which do not have an own bus but their EHCI controller works like a PCI controller. It will be used for the Broadcom bcma and ssb USB EHCI controller. Acked-by: Alan Stern Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 10 ++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-platform.c | 198 ++++++++++++++++++++++++++++++++++++++ include/linux/usb/ehci_pdriver.h | 46 +++++++++ 4 files changed, 259 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-platform.c create mode 100644 include/linux/usb/ehci_pdriver.h diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index fd521f3..5f46342 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -403,6 +403,16 @@ config USB_OHCI_HCD_PLATFORM If unsure, say N. +config USB_EHCI_HCD_PLATFORM + bool "Generic EHCI driver for a platform device" + depends on USB_EHCI_HCD && EXPERIMENTAL + default n + ---help--- + Adds an EHCI host driver for a generic platform device, which + provieds a memory space and an irq. + + If unsure, say N. + config USB_OHCI_BIG_ENDIAN_DESC bool depends on USB_OHCI_HCD diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index a007a9f..afe0984 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1376,6 +1376,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_mv_driver #endif +#ifdef CONFIG_USB_EHCI_HCD_PLATFORM +#include "ehci-platform.c" +#define PLATFORM_DRIVER ehci_platform_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c new file mode 100644 index 0000000..d238b4e2 --- /dev/null +++ b/drivers/usb/host/ehci-platform.c @@ -0,0 +1,198 @@ +/* + * Generic platform ehci driver + * + * Copyright 2007 Steven Brown + * Copyright 2010-2012 Hauke Mehrtens + * + * Derived from the ohci-ssb driver + * Copyright 2007 Michael Buesch + * + * Derived from the EHCI-PCI driver + * Copyright (c) 2000-2004 by David Brownell + * + * Derived from the ohci-pci driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include + +static int ehci_platform_reset(struct usb_hcd *hcd) +{ + struct platform_device *pdev = to_platform_device(hcd->self.controller); + struct usb_ehci_pdata *pdata = pdev->dev.platform_data; + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int retval; + + hcd->has_tt = pdata->has_tt; + ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug; + ehci->big_endian_desc = pdata->big_endian_desc; + ehci->big_endian_mmio = pdata->big_endian_mmio; + + ehci->caps = hcd->regs + pdata->caps_offset; + retval = ehci_setup(hcd); + if (retval) + return retval; + + if (pdata->port_power_on) + ehci_port_power(ehci, 1); + if (pdata->port_power_off) + ehci_port_power(ehci, 0); + + return 0; +} + +static const struct hc_driver ehci_platform_hc_driver = { + .description = hcd_name, + .product_desc = "Generic Platform EHCI Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + .reset = ehci_platform_reset, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +#if defined(CONFIG_PM) + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, +#endif + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .update_device = ehci_update_device, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int __devinit ehci_platform_probe(struct platform_device *dev) +{ + struct usb_hcd *hcd; + struct resource *res_mem; + int irq; + int err = -ENOMEM; + + BUG_ON(!dev->dev.platform_data); + + if (usb_disabled()) + return -ENODEV; + + irq = platform_get_irq(dev, 0); + if (irq < 0) { + pr_err("no irq provieded"); + return irq; + } + res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res_mem) { + pr_err("no memory recourse provieded"); + return -ENXIO; + } + + hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev, + dev_name(&dev->dev)); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = res_mem->start; + hcd->rsrc_len = resource_size(res_mem); + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_err("controller already in use"); + err = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) + goto err_release_region; + err = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (err) + goto err_iounmap; + + platform_set_drvdata(dev, hcd); + + return err; + +err_iounmap: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return err; +} + +static int __devexit ehci_platform_remove(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + platform_set_drvdata(dev, NULL); + + return 0; +} + +#ifdef CONFIG_PM + +static int ehci_platform_suspend(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + bool wakeup = device_may_wakeup(dev); + + ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), wakeup); + return 0; +} + +static int ehci_platform_resume(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + + ehci_prepare_ports_for_controller_resume(hcd_to_ehci(hcd)); + return 0; +} + +#else /* !CONFIG_PM */ +#define ehci_platform_suspend NULL +#define ehci_platform_resume NULL +#endif /* CONFIG_PM */ + +static const struct platform_device_id ehci_platform_table[] = { + { "ehci-platform", 0 }, + { } +}; +MODULE_DEVICE_TABLE(platform, ehci_platform_table); + +static const struct dev_pm_ops ehci_platform_pm_ops = { + .suspend = ehci_platform_suspend, + .resume = ehci_platform_resume, +}; + +static struct platform_driver ehci_platform_driver = { + .id_table = ehci_platform_table, + .probe = ehci_platform_probe, + .remove = __devexit_p(ehci_platform_remove), + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .owner = THIS_MODULE, + .name = "ehci-platform", + .pm = &ehci_platform_pm_ops, + } +}; diff --git a/include/linux/usb/ehci_pdriver.h b/include/linux/usb/ehci_pdriver.h new file mode 100644 index 0000000..1894f42 --- /dev/null +++ b/include/linux/usb/ehci_pdriver.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2012 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __USB_CORE_EHCI_PDRIVER_H +#define __USB_CORE_EHCI_PDRIVER_H + +/** + * struct usb_ehci_pdata - platform_data for generic ehci driver + * + * @caps_offset: offset of the EHCI Capability Registers to the start of + * the io memory region provided to the driver. + * @has_tt: set to 1 if TT is integrated in root hub. + * @port_power_on: set to 1 if the controller needs a power up after + * initialization. + * @port_power_off: set to 1 if the controller needs to be powered down + * after initialization. + * + * These are general configuration options for the EHCI controller. All of + * these options are activating more or less workarounds for some hardware. + */ +struct usb_ehci_pdata { + int caps_offset; + unsigned has_tt:1; + unsigned has_synopsys_hc_bug:1; + unsigned big_endian_desc:1; + unsigned big_endian_mmio:1; + unsigned port_power_on:1; + unsigned port_power_off:1; +}; + +#endif /* __USB_CORE_EHCI_PDRIVER_H */ -- 1.7.5.4 From hauke@hauke-m.de Tue Mar 13 01:05:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Mar 2012 01:06:48 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47507 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903622Ab2CMAFk (ORCPT ); Tue, 13 Mar 2012 01:05:40 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 551BC8F62; Tue, 13 Mar 2012 01:05:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id N5THlFwgBZ0c; Tue, 13 Mar 2012 01:05:25 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 6C2C98F63; Tue, 13 Mar 2012 01:05:10 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, Hauke Mehrtens , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Subject: [PATCH v4 3/7] bcma: scan for extra address space Date: Tue, 13 Mar 2012 01:04:49 +0100 Message-Id: <1331597093-425-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331597093-425-1-git-send-email-hauke@hauke-m.de> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32663 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1915 Lines: 66 Some cores like the USB core have two address spaces. In the USB host controller one address space is used for the OHCI and the other for the EHCI controller interface. The USB controller is the only core I found with two address spaces. This code is based on the AI scan function ai_scan() in shared/aiutils.c in the Broadcom SDK. CC: RafaÅ‚ MiÅ‚ecki CC: linux-wireless@vger.kernel.org Signed-off-by: Hauke Mehrtens --- drivers/bcma/scan.c | 19 ++++++++++++++++++- include/linux/bcma/bcma.h | 1 + 2 files changed, 19 insertions(+), 1 deletions(-) diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c index 3a2f672..1fa10ed 100644 --- a/drivers/bcma/scan.c +++ b/drivers/bcma/scan.c @@ -286,6 +286,23 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, return -EILSEQ; } + /* First Slave Address Descriptor should be port 0: + * the main register space for the core + */ + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); + if (tmp <= 0) { + /* Try again to see if it is a bridge */ + tmp = bcma_erom_get_addr_desc(bus, eromptr, + SCAN_ADDR_TYPE_BRIDGE, 0); + if (tmp <= 0) { + return -EILSEQ; + } else { + pr_info("Bridge found\n"); + return -ENXIO; + } + } + core->addr = tmp; + /* get & parse slave ports */ for (i = 0; i < ports[1]; i++) { for (j = 0; ; j++) { @@ -298,7 +315,7 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, break; } else { if (i == 0 && j == 0) - core->addr = tmp; + core->addr1 = tmp; } } } diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 83c209f..7fe41e1 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -138,6 +138,7 @@ struct bcma_device { u8 core_index; u32 addr; + u32 addr1; u32 wrap; void __iomem *io_addr; -- 1.7.5.4 From hauke@hauke-m.de Tue Mar 13 01:05:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Mar 2012 01:07:10 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47519 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903706Ab2CMAFz (ORCPT ); Tue, 13 Mar 2012 01:05:55 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id E596A8F68; Tue, 13 Mar 2012 01:05:54 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Y5Rji0TB2URv; Tue, 13 Mar 2012 01:05:39 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id CEFCB8F64; Tue, 13 Mar 2012 01:05:10 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH v4 4/7] USB: Add driver for the bcma bus Date: Tue, 13 Mar 2012 01:04:50 +0100 Message-Id: <1331597093-425-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331597093-425-1-git-send-email-hauke@hauke-m.de> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32664 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 10494 Lines: 388 This adds a USB driver using the generic platform device driver for the USB controller found on the Broadcom bcma bus. The bcma bus just exposes one device which serves the OHCI and the EHCI controller at the same time. This driver probes for this USB controller and creates and registers two new platform devices which will be probed by the new generic platform device driver. This makes it possible to use the EHCI and the OCHI controller on the bcma bus at the same time. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 12 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/bcma-hcd.c | 334 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 347 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/bcma-hcd.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 5f46342..678261d 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -633,3 +633,15 @@ config USB_PXA168_EHCI help Enable support for Marvell PXA168 SoC's on-chip EHCI host controller + +config USB_HCD_BCMA + tristate "BCMA usb host driver" + depends on BCMA && EXPERIMENTAL + select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD + select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD + help + Enbale support for the EHCI and OCHI host controller on an bcma bus. + It converts the bcma driver into two platform device drivers + for ehci and ohci. + + If unsure, say N. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 7ca290f..f2c2846 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -37,3 +37,4 @@ obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o obj-$(CONFIG_MIPS_ALCHEMY) += alchemy-common.o +obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o diff --git a/drivers/usb/host/bcma-hcd.c b/drivers/usb/host/bcma-hcd.c new file mode 100644 index 0000000..afec047 --- /dev/null +++ b/drivers/usb/host/bcma-hcd.c @@ -0,0 +1,334 @@ +/* + * Broadcom specific Advanced Microcontroller Bus + * Broadcom USB-core driver (BCMA bus glue) + * + * Copyright 2011-2012 Hauke Mehrtens + * + * Based on ssb-ohci driver + * Copyright 2007 Michael Buesch + * + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Derived from the USBcore related parts of Broadcom-SB + * Copyright 2005-2011 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include +#include +#include +#include +#include + +MODULE_AUTHOR("Hauke Mehrtens"); +MODULE_DESCRIPTION("Common USB driver for BCMA Bus"); +MODULE_LICENSE("GPL"); + +struct bcma_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; +}; + +/* Wait for bitmask in a register to get set or cleared. + * timeout is in units of ten-microseconds. + */ +static int bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask, + int timeout) +{ + int i; + u32 val; + + for (i = 0; i < timeout; i++) { + val = bcma_read32(dev, reg); + if ((val & bitmask) == bitmask) + return 0; + udelay(10); + } + + return -ETIMEDOUT; +} + +static void __devinit bcma_hcd_4716wa(struct bcma_device *dev) +{ +#ifdef CONFIG_BCMA_DRIVER_MIPS + /* Work around for 4716 failures. */ + if (dev->bus->chipinfo.id == 0x4716) { + u32 tmp; + + tmp = bcma_cpu_clock(&dev->bus->drv_mips); + if (tmp >= 480000000) + tmp = 0x1846b; /* set CDR to 0x11(fast) */ + else if (tmp == 453000000) + tmp = 0x1046b; /* set CDR to 0x10(slow) */ + else + tmp = 0; + + /* Change Shim mdio control reg to fix host not acking at + * high frequencies + */ + if (tmp) { + bcma_write32(dev, 0x524, 0x1); /* write sel to enable */ + udelay(500); + + bcma_write32(dev, 0x524, tmp); + udelay(500); + bcma_write32(dev, 0x524, 0x4ab); + udelay(500); + bcma_read32(dev, 0x528); + bcma_write32(dev, 0x528, 0x80000000); + } + } +#endif /* CONFIG_BCMA_DRIVER_MIPS */ +} + +/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ +static void __devinit bcma_hcd_init_chip(struct bcma_device *dev) +{ + u32 tmp; + + /* + * USB 2.0 special considerations: + * + * 1. Since the core supports both OHCI and EHCI functions, it must + * only be reset once. + * + * 2. In addition to the standard SI reset sequence, the Host Control + * Register must be programmed to bring the USB core and various + * phy components out of reset. + */ + if (!bcma_core_is_enabled(dev)) { + bcma_core_enable(dev, 0); + mdelay(10); + if (dev->id.rev >= 5) { + /* Enable Misc PLL */ + tmp = bcma_read32(dev, 0x1e0); + tmp |= 0x100; + bcma_write32(dev, 0x1e0, tmp); + if (bcma_wait_bits(dev, 0x1e0, 1 << 24, 100)) + printk(KERN_EMERG "Failed to enable misc PPL!\n"); + + /* Take out of resets */ + bcma_write32(dev, 0x200, 0x4ff); + udelay(25); + bcma_write32(dev, 0x200, 0x6ff); + udelay(25); + + /* Make sure digital and AFE are locked in USB PHY */ + bcma_write32(dev, 0x524, 0x6b); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0xab); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0x2b); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0x10ab); + udelay(50); + tmp = bcma_read32(dev, 0x524); + + if (bcma_wait_bits(dev, 0x528, 0xc000, 10000)) { + tmp = bcma_read32(dev, 0x528); + printk(KERN_EMERG + "USB20H mdio_rddata 0x%08x\n", tmp); + } + bcma_write32(dev, 0x528, 0x80000000); + tmp = bcma_read32(dev, 0x314); + udelay(265); + bcma_write32(dev, 0x200, 0x7ff); + udelay(10); + + /* Take USB and HSIC out of non-driving modes */ + bcma_write32(dev, 0x510, 0); + } else { + bcma_write32(dev, 0x200, 0x7ff); + + udelay(1); + } + + bcma_hcd_4716wa(dev); + } +} + +static const struct usb_ehci_pdata ehci_pdata = { +}; + +static const struct usb_ohci_pdata ohci_pdata = { +}; + +static struct platform_device * __devinit +bcma_hcd_create_pdev(struct bcma_device *dev, bool ohci, u32 addr) +{ + struct platform_device *hci_dev; + struct resource hci_res[2]; + int ret = -ENOMEM; + + memset(hci_res, 0, sizeof(hci_res)); + + hci_res[0].start = addr; + hci_res[0].end = hci_res[0].start + 0x1000 - 1; + hci_res[0].flags = IORESOURCE_MEM; + + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + + hci_dev = platform_device_alloc(ohci ? "ohci-platform" : + "ehci-platform" , 0); + if (!hci_dev) + return NULL; + + hci_dev->dev.parent = &dev->dev; + hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask; + + ret = platform_device_add_resources(hci_dev, hci_res, + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; + if (ohci) + ret = platform_device_add_data(hci_dev, &ohci_pdata, + sizeof(ohci_pdata)); + else + ret = platform_device_add_data(hci_dev, &ehci_pdata, + sizeof(ehci_pdata)); + if (ret) + goto err_alloc; + ret = platform_device_add(hci_dev); + if (ret) + goto err_alloc; + + return hci_dev; + +err_alloc: + platform_device_put(hci_dev); + return ERR_PTR(ret); +} + +static int __devinit bcma_hcd_probe(struct bcma_device *dev) +{ + int err; + u16 chipid_top; + u32 ohci_addr; + struct bcma_hcd_device *usb_dev; + struct bcma_chipinfo *chipinfo; + + chipinfo = &dev->bus->chipinfo; + /* USBcores are only connected on embedded devices. */ + chipid_top = (chipinfo->id & 0xFF00); + if (chipid_top != 0x4700 && chipid_top != 0x5300) + return -ENODEV; + + /* TODO: Probably need checks here; is the core connected? */ + + if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + + usb_dev = kzalloc(sizeof(struct bcma_hcd_device), GFP_KERNEL); + if (!usb_dev) + return -ENOMEM; + + bcma_hcd_init_chip(dev); + + /* In AI chips EHCI is addrspace 0, OHCI is 1 */ + ohci_addr = dev->addr1; + if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749) + && chipinfo->rev == 0) + ohci_addr = 0x18009000; + + usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, true, ohci_addr); + if (IS_ERR(usb_dev->ohci_dev)) { + err = PTR_ERR(usb_dev->ohci_dev); + goto err_free_usb_dev; + } + + usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, false, dev->addr); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; + } + + bcma_set_drvdata(dev, usb_dev); + return 0; + +err_unregister_ohci_dev: + platform_device_unregister(usb_dev->ohci_dev); +err_free_usb_dev: + kfree(usb_dev); + return err; +} + +static void __devexit bcma_hcd_remove(struct bcma_device *dev) +{ + struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); + struct platform_device *ohci_dev = usb_dev->ohci_dev; + struct platform_device *ehci_dev = usb_dev->ehci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); + + bcma_core_disable(dev, 0); +} + +static void bcma_hcd_shutdown(struct bcma_device *dev) +{ + bcma_core_disable(dev, 0); +} + +#ifdef CONFIG_PM + +static int bcma_hcd_suspend(struct bcma_device *dev, pm_message_t state) +{ + bcma_core_disable(dev, 0); + + return 0; +} + +static int bcma_hcd_resume(struct bcma_device *dev) +{ + bcma_core_enable(dev, 0); + + return 0; +} + +#else /* !CONFIG_PM */ +#define bcma_hcd_suspend NULL +#define bcma_hcd_resume NULL +#endif /* CONFIG_PM */ + +static const struct bcma_device_id bcma_hcd_table[] __devinitconst = { + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS), + BCMA_CORETABLE_END +}; +MODULE_DEVICE_TABLE(bcma, bcma_hcd_table); + +static struct bcma_driver bcma_hcd_driver = { + .name = KBUILD_MODNAME, + .id_table = bcma_hcd_table, + .probe = bcma_hcd_probe, + .remove = __devexit_p(bcma_hcd_remove), + .shutdown = bcma_hcd_shutdown, + .suspend = bcma_hcd_suspend, + .resume = bcma_hcd_resume, +}; + +static int __init bcma_hcd_init(void) +{ + return bcma_driver_register(&bcma_hcd_driver); +} +module_init(bcma_hcd_init); + +static void __exit bcma_hcd_exit(void) +{ + bcma_driver_unregister(&bcma_hcd_driver); +} +module_exit(bcma_hcd_exit); -- 1.7.5.4 From hauke@hauke-m.de Tue Mar 13 01:05:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Mar 2012 01:07:33 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47525 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903627Ab2CMAF5 (ORCPT ); Tue, 13 Mar 2012 01:05:57 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id F036F8F62; Tue, 13 Mar 2012 01:05:56 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RORXbNpToi10; Tue, 13 Mar 2012 01:05:40 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 355EC8F65; Tue, 13 Mar 2012 01:05:11 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH v4 5/7] USB: Add driver for the ssb bus Date: Tue, 13 Mar 2012 01:04:51 +0100 Message-Id: <1331597093-425-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331597093-425-1-git-send-email-hauke@hauke-m.de> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32665 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9403 Lines: 337 This adds a USB driver using the generic platform device driver for the USB controller found on the Broadcom ssb bus. The ssb bus just exposes one device which serves the OHCI and the EHCI controller at the same time. This driver probes for this USB controller and creates and registers two new platform devices which will be probed by the new generic platform device driver. This makes it possible to use the EHCI and the OCHI controller on the ssb bus at the same time. The old ssb OHCI USB driver will be removed in the next step as this driver also provide an OHCI driver and an EHCI for the cores supporting it. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 12 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ssb-hcd.c | 279 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 292 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ssb-hcd.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 678261d..e251441 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -645,3 +645,15 @@ config USB_HCD_BCMA for ehci and ohci. If unsure, say N. + +config USB_HCD_SSB + tristate "SSB usb host driver" + depends on SSB && EXPERIMENTAL + select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD + select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD + help + Enbale support for the EHCI and OCHI host controller on an bcma bus. + It converts the bcma driver into two platform device drivers + for ehci and ohci. + + If unsure, say N. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f2c2846..9c52966 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o obj-$(CONFIG_MIPS_ALCHEMY) += alchemy-common.o obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o +obj-$(CONFIG_USB_HCD_SSB) += ssb-hcd.o diff --git a/drivers/usb/host/ssb-hcd.c b/drivers/usb/host/ssb-hcd.c new file mode 100644 index 0000000..c2e7343 --- /dev/null +++ b/drivers/usb/host/ssb-hcd.c @@ -0,0 +1,279 @@ +/* + * Sonics Silicon Backplane + * Broadcom USB-core driver (SSB bus glue) + * + * Copyright 2011-2012 Hauke Mehrtens + * + * Based on ssb-ohci driver + * Copyright 2007 Michael Buesch + * + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Derived from the USBcore related parts of Broadcom-SB + * Copyright 2005-2011 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include +#include +#include +#include +#include + +MODULE_AUTHOR("Hauke Mehrtens"); +MODULE_DESCRIPTION("Common USB driver for SSB Bus"); +MODULE_LICENSE("GPL"); + +#define SSB_HCD_TMSLOW_HOSTMODE (1 << 29) + +struct ssb_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; + + u32 enable_flags; +}; + +static void __devinit ssb_hcd_5354wa(struct ssb_device *dev) +{ +#ifdef CONFIG_SSB_DRIVER_MIPS + /* Work around for 5354 failures */ + if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { + /* Change syn01 reg */ + ssb_write32(dev, 0x894, 0x00fe00fe); + + /* Change syn03 reg */ + ssb_write32(dev, 0x89c, ssb_read32(dev, 0x89c) | 0x1); + } +#endif +} + +static void __devinit ssb_hcd_usb20wa(struct ssb_device *dev) +{ + if (dev->id.coreid == SSB_DEV_USB20_HOST) { + /* + * USB 2.0 special considerations: + * + * In addition to the standard SSB reset sequence, the Host + * Control Register must be programmed to bring the USB core + * and various phy components out of reset. + */ + ssb_write32(dev, 0x200, 0x7ff); + + /* Change Flush control reg */ + ssb_write32(dev, 0x400, ssb_read32(dev, 0x400) & ~8); + ssb_read32(dev, 0x400); + + /* Change Shim control reg */ + ssb_write32(dev, 0x304, ssb_read32(dev, 0x304) & ~0x100); + ssb_read32(dev, 0x304); + + udelay(1); + + ssb_hcd_5354wa(dev); + } +} + +/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ +static u32 __devinit ssb_hcd_init_chip(struct ssb_device *dev) +{ + u32 flags = 0; + + if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) + /* Put the device into host-mode. */ + flags |= SSB_HCD_TMSLOW_HOSTMODE; + + ssb_device_enable(dev, flags); + + ssb_hcd_usb20wa(dev); + + return flags; +} + +static const struct usb_ehci_pdata ehci_pdata = { +}; + +static const struct usb_ohci_pdata ohci_pdata = { +}; + +static struct platform_device * __devinit +ssb_hcd_create_pdev(struct ssb_device *dev, bool ohci, u32 addr, u32 len) +{ + struct platform_device *hci_dev; + struct resource hci_res[2]; + int ret = -ENOMEM; + + memset(hci_res, 0, sizeof(hci_res)); + + hci_res[0].start = addr; + hci_res[0].end = hci_res[0].start + len - 1; + hci_res[0].flags = IORESOURCE_MEM; + + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + + hci_dev = platform_device_alloc(ohci ? "ohci-platform" : + "ehci-platform" , 0); + if (!hci_dev) + return NULL; + + hci_dev->dev.parent = dev->dev; + hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask; + + ret = platform_device_add_resources(hci_dev, hci_res, + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; + if (ohci) + ret = platform_device_add_data(hci_dev, &ohci_pdata, + sizeof(ohci_pdata)); + else + ret = platform_device_add_data(hci_dev, &ehci_pdata, + sizeof(ehci_pdata)); + if (ret) + goto err_alloc; + ret = platform_device_add(hci_dev); + if (ret) + goto err_alloc; + + return hci_dev; + +err_alloc: + platform_device_put(hci_dev); + return ERR_PTR(ret); +} + +static int __devinit ssb_hcd_probe(struct ssb_device *dev, + const struct ssb_device_id *id) +{ + int err, tmp; + int start, len; + u16 chipid_top; + u16 coreid = dev->id.coreid; + struct ssb_hcd_device *usb_dev; + + /* USBcores are only connected on embedded devices. */ + chipid_top = (dev->bus->chip_id & 0xFF00); + if (chipid_top != 0x4700 && chipid_top != 0x5300) + return -ENODEV; + + /* TODO: Probably need checks here; is the core connected? */ + + if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + + usb_dev = kzalloc(sizeof(struct ssb_hcd_device), GFP_KERNEL); + if (!usb_dev) + return -ENOMEM; + + /* We currently always attach SSB_DEV_USB11_HOSTDEV + * as HOST OHCI. If we want to attach it as Client device, + * we must branch here and call into the (yet to + * be written) Client mode driver. Same for remove(). */ + usb_dev->enable_flags = ssb_hcd_init_chip(dev); + + tmp = ssb_read32(dev, SSB_ADMATCH0); + + start = ssb_admatch_base(tmp); + len = (coreid == SSB_DEV_USB20_HOST) ? 0x800 : ssb_admatch_size(tmp); + usb_dev->ohci_dev = ssb_hcd_create_pdev(dev, true, start, len); + if (IS_ERR(usb_dev->ohci_dev)) { + err = PTR_ERR(usb_dev->ohci_dev); + goto err_free_usb_dev; + } + + if (coreid == SSB_DEV_USB20_HOST) { + start = ssb_admatch_base(tmp) + 0x800; /* ehci core offset */ + usb_dev->ehci_dev = ssb_hcd_create_pdev(dev, false, start, len); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; + } + } + + ssb_set_drvdata(dev, usb_dev); + return 0; + +err_unregister_ohci_dev: + platform_device_unregister(usb_dev->ohci_dev); +err_free_usb_dev: + kfree(usb_dev); + return err; +} + +static void __devexit ssb_hcd_remove(struct ssb_device *dev) +{ + struct ssb_hcd_device *usb_dev = ssb_get_drvdata(dev); + struct platform_device *ohci_dev = usb_dev->ohci_dev; + struct platform_device *ehci_dev = usb_dev->ehci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); + + ssb_device_disable(dev, 0); +} + +static void __devexit ssb_hcd_shutdown(struct ssb_device *dev) +{ + ssb_device_disable(dev, 0); +} + +#ifdef CONFIG_PM + +static int ssb_hcd_suspend(struct ssb_device *dev, pm_message_t state) +{ + ssb_device_disable(dev, 0); + + return 0; +} + +static int ssb_hcd_resume(struct ssb_device *dev) +{ + struct ssb_hcd_device *usb_dev = ssb_get_drvdata(dev); + + ssb_device_enable(dev, usb_dev->enable_flags); + + return 0; +} + +#else /* !CONFIG_PM */ +#define ssb_hcd_suspend NULL +#define ssb_hcd_resume NULL +#endif /* CONFIG_PM */ + +static const struct ssb_device_id ssb_hcd_table[] __devinitconst = { + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV), + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV), + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), + SSB_DEVTABLE_END +}; +MODULE_DEVICE_TABLE(ssb, ssb_hcd_table); + +static struct ssb_driver ssb_hcd_driver = { + .name = KBUILD_MODNAME, + .id_table = ssb_hcd_table, + .probe = ssb_hcd_probe, + .remove = __devexit_p(ssb_hcd_remove), + .shutdown = ssb_hcd_shutdown, + .suspend = ssb_hcd_suspend, + .resume = ssb_hcd_resume, +}; + +static int __init ssb_hcd_init(void) +{ + return ssb_driver_register(&ssb_hcd_driver); +} +module_init(ssb_hcd_init); + +static void __exit ssb_hcd_exit(void) +{ + ssb_driver_unregister(&ssb_hcd_driver); +} +module_exit(ssb_hcd_exit); -- 1.7.5.4 From hauke@hauke-m.de Tue Mar 13 01:06:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Mar 2012 01:07:59 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47535 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903617Ab2CMAGL (ORCPT ); Tue, 13 Mar 2012 01:06:11 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id F0B1F8F6B; Tue, 13 Mar 2012 01:06:10 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id X84JUjy292fG; Tue, 13 Mar 2012 01:05:55 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 91E448F66; Tue, 13 Mar 2012 01:05:11 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH v4 6/7] USB: OHCI: remove old SSB OHCI driver Date: Tue, 13 Mar 2012 01:04:52 +0100 Message-Id: <1331597093-425-7-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331597093-425-1-git-send-email-hauke@hauke-m.de> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32666 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9390 Lines: 361 This is now replaced by the new ssb USB driver, which also supports devices with an EHCI controller. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 7 +- drivers/usb/host/ohci-hcd.c | 21 +---- drivers/usb/host/ohci-ssb.c | 260 ------------------------------------------- 3 files changed, 7 insertions(+), 281 deletions(-) delete mode 100644 drivers/usb/host/ohci-ssb.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index e251441..0619884 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -361,10 +361,15 @@ config USB_OHCI_HCD_PCI If unsure, say Y. config USB_OHCI_HCD_SSB - bool "OHCI support for Broadcom SSB OHCI core" + bool "OHCI support for Broadcom SSB OHCI core (DEPRECATED)" depends on USB_OHCI_HCD && (SSB = y || SSB = USB_OHCI_HCD) && EXPERIMENTAL + select USB_HCD_SSB + select USB_OHCI_HCD_PLATFORM default n ---help--- + This option is deprecated now and the driver was removed, use + USB_HCD_SSB and USB_OHCI_HCD_PLATFORM instead. + Support for the Sonics Silicon Backplane (SSB) attached Broadcom USB OHCI core. diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 50fbbf9..a2f4d4e 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1081,11 +1081,6 @@ MODULE_LICENSE ("GPL"); #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver #endif -#ifdef CONFIG_USB_OHCI_HCD_SSB -#include "ohci-ssb.c" -#define SSB_OHCI_DRIVER ssb_ohci_driver -#endif - #ifdef CONFIG_MFD_SM501 #include "ohci-sm501.c" #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver @@ -1134,8 +1129,7 @@ MODULE_LICENSE ("GPL"); !defined(SA1111_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && \ !defined(SM501_OHCI_DRIVER) && \ - !defined(TMIO_OHCI_DRIVER) && \ - !defined(SSB_OHCI_DRIVER) + !defined(TMIO_OHCI_DRIVER) #error "missing bus glue for ohci-hcd" #endif @@ -1201,12 +1195,6 @@ static int __init ohci_hcd_mod_init(void) goto error_pci; #endif -#ifdef SSB_OHCI_DRIVER - retval = ssb_driver_register(&SSB_OHCI_DRIVER); - if (retval) - goto error_ssb; -#endif - #ifdef SM501_OHCI_DRIVER retval = platform_driver_register(&SM501_OHCI_DRIVER); if (retval < 0) @@ -1230,10 +1218,6 @@ static int __init ohci_hcd_mod_init(void) platform_driver_unregister(&SM501_OHCI_DRIVER); error_sm501: #endif -#ifdef SSB_OHCI_DRIVER - ssb_driver_unregister(&SSB_OHCI_DRIVER); - error_ssb: -#endif #ifdef PCI_DRIVER pci_unregister_driver(&PCI_DRIVER); error_pci: @@ -1281,9 +1265,6 @@ static void __exit ohci_hcd_mod_exit(void) #ifdef SM501_OHCI_DRIVER platform_driver_unregister(&SM501_OHCI_DRIVER); #endif -#ifdef SSB_OHCI_DRIVER - ssb_driver_unregister(&SSB_OHCI_DRIVER); -#endif #ifdef PCI_DRIVER pci_unregister_driver(&PCI_DRIVER); #endif diff --git a/drivers/usb/host/ohci-ssb.c b/drivers/usb/host/ohci-ssb.c deleted file mode 100644 index 5ba1859..0000000 --- a/drivers/usb/host/ohci-ssb.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Sonics Silicon Backplane - * Broadcom USB-core OHCI driver - * - * Copyright 2007 Michael Buesch - * - * Derived from the OHCI-PCI driver - * Copyright 1999 Roman Weissgaerber - * Copyright 2000-2002 David Brownell - * Copyright 1999 Linus Torvalds - * Copyright 1999 Gregory P. Smith - * - * Derived from the USBcore related parts of Broadcom-SB - * Copyright 2005 Broadcom Corporation - * - * Licensed under the GNU/GPL. See COPYING for details. - */ -#include - - -#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29) - -struct ssb_ohci_device { - struct ohci_hcd ohci; /* _must_ be at the beginning. */ - - u32 enable_flags; -}; - -static inline -struct ssb_ohci_device *hcd_to_ssb_ohci(struct usb_hcd *hcd) -{ - return (struct ssb_ohci_device *)(hcd->hcd_priv); -} - - -static int ssb_ohci_reset(struct usb_hcd *hcd) -{ - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - struct ohci_hcd *ohci = &ohcidev->ohci; - int err; - - ohci_hcd_init(ohci); - err = ohci_init(ohci); - - return err; -} - -static int ssb_ohci_start(struct usb_hcd *hcd) -{ - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - struct ohci_hcd *ohci = &ohcidev->ohci; - int err; - - err = ohci_run(ohci); - if (err < 0) { - ohci_err(ohci, "can't start\n"); - ohci_stop(hcd); - } - - return err; -} - -static const struct hc_driver ssb_ohci_hc_driver = { - .description = "ssb-usb-ohci", - .product_desc = "SSB OHCI Controller", - .hcd_priv_size = sizeof(struct ssb_ohci_device), - - .irq = ohci_irq, - .flags = HCD_MEMORY | HCD_USB11, - - .reset = ssb_ohci_reset, - .start = ssb_ohci_start, - .stop = ohci_stop, - .shutdown = ohci_shutdown, - - .urb_enqueue = ohci_urb_enqueue, - .urb_dequeue = ohci_urb_dequeue, - .endpoint_disable = ohci_endpoint_disable, - - .get_frame_number = ohci_get_frame, - - .hub_status_data = ohci_hub_status_data, - .hub_control = ohci_hub_control, -#ifdef CONFIG_PM - .bus_suspend = ohci_bus_suspend, - .bus_resume = ohci_bus_resume, -#endif - - .start_port_reset = ohci_start_port_reset, -}; - -static void ssb_ohci_detach(struct ssb_device *dev) -{ - struct usb_hcd *hcd = ssb_get_drvdata(dev); - - if (hcd->driver->shutdown) - hcd->driver->shutdown(hcd); - usb_remove_hcd(hcd); - iounmap(hcd->regs); - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); - usb_put_hcd(hcd); - ssb_device_disable(dev, 0); -} - -static int ssb_ohci_attach(struct ssb_device *dev) -{ - struct ssb_ohci_device *ohcidev; - struct usb_hcd *hcd; - int err = -ENOMEM; - u32 tmp, flags = 0; - - if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || - dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) - return -EOPNOTSUPP; - - if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) { - /* Put the device into host-mode. */ - flags |= SSB_OHCI_TMSLOW_HOSTMODE; - ssb_device_enable(dev, flags); - } else if (dev->id.coreid == SSB_DEV_USB20_HOST) { - /* - * USB 2.0 special considerations: - * - * In addition to the standard SSB reset sequence, the Host - * Control Register must be programmed to bring the USB core - * and various phy components out of reset. - */ - ssb_device_enable(dev, 0); - ssb_write32(dev, 0x200, 0x7ff); - - /* Change Flush control reg */ - tmp = ssb_read32(dev, 0x400); - tmp &= ~8; - ssb_write32(dev, 0x400, tmp); - tmp = ssb_read32(dev, 0x400); - - /* Change Shim control reg */ - tmp = ssb_read32(dev, 0x304); - tmp &= ~0x100; - ssb_write32(dev, 0x304, tmp); - tmp = ssb_read32(dev, 0x304); - - udelay(1); - - /* Work around for 5354 failures */ - if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { - /* Change syn01 reg */ - tmp = 0x00fe00fe; - ssb_write32(dev, 0x894, tmp); - - /* Change syn03 reg */ - tmp = ssb_read32(dev, 0x89c); - tmp |= 0x1; - ssb_write32(dev, 0x89c, tmp); - } - } else - ssb_device_enable(dev, 0); - - hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev, - dev_name(dev->dev)); - if (!hcd) - goto err_dev_disable; - ohcidev = hcd_to_ssb_ohci(hcd); - ohcidev->enable_flags = flags; - - tmp = ssb_read32(dev, SSB_ADMATCH0); - hcd->rsrc_start = ssb_admatch_base(tmp); - hcd->rsrc_len = ssb_admatch_size(tmp); - hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); - if (!hcd->regs) - goto err_put_hcd; - err = usb_add_hcd(hcd, dev->irq, IRQF_SHARED); - if (err) - goto err_iounmap; - - ssb_set_drvdata(dev, hcd); - - return err; - -err_iounmap: - iounmap(hcd->regs); -err_put_hcd: - usb_put_hcd(hcd); -err_dev_disable: - ssb_device_disable(dev, flags); - return err; -} - -static int ssb_ohci_probe(struct ssb_device *dev, - const struct ssb_device_id *id) -{ - int err; - u16 chipid_top; - - /* USBcores are only connected on embedded devices. */ - chipid_top = (dev->bus->chip_id & 0xFF00); - if (chipid_top != 0x4700 && chipid_top != 0x5300) - return -ENODEV; - - /* TODO: Probably need checks here; is the core connected? */ - - if (usb_disabled()) - return -ENODEV; - - /* We currently always attach SSB_DEV_USB11_HOSTDEV - * as HOST OHCI. If we want to attach it as Client device, - * we must branch here and call into the (yet to - * be written) Client mode driver. Same for remove(). */ - - err = ssb_ohci_attach(dev); - - return err; -} - -static void ssb_ohci_remove(struct ssb_device *dev) -{ - ssb_ohci_detach(dev); -} - -#ifdef CONFIG_PM - -static int ssb_ohci_suspend(struct ssb_device *dev, pm_message_t state) -{ - ssb_device_disable(dev, 0); - - return 0; -} - -static int ssb_ohci_resume(struct ssb_device *dev) -{ - struct usb_hcd *hcd = ssb_get_drvdata(dev); - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - - ssb_device_enable(dev, ohcidev->enable_flags); - - ohci_finish_controller_resume(hcd); - return 0; -} - -#else /* !CONFIG_PM */ -#define ssb_ohci_suspend NULL -#define ssb_ohci_resume NULL -#endif /* CONFIG_PM */ - -static const struct ssb_device_id ssb_ohci_table[] = { - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), - SSB_DEVTABLE_END -}; -MODULE_DEVICE_TABLE(ssb, ssb_ohci_table); - -static struct ssb_driver ssb_ohci_driver = { - .name = KBUILD_MODNAME, - .id_table = ssb_ohci_table, - .probe = ssb_ohci_probe, - .remove = ssb_ohci_remove, - .suspend = ssb_ohci_suspend, - .resume = ssb_ohci_resume, -}; -- 1.7.5.4 From hauke@hauke-m.de Tue Mar 13 01:06:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Mar 2012 01:08:24 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47541 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903709Ab2CMAGN (ORCPT ); Tue, 13 Mar 2012 01:06:13 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 440468F66; Tue, 13 Mar 2012 01:06:13 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ja616G6+tnK1; Tue, 13 Mar 2012 01:05:57 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id E4E128F67; Tue, 13 Mar 2012 01:05:11 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, Hauke Mehrtens , Gabor Juhos , Imre Kaloz Subject: [PATCH v4 7/7] USB: use generic platform driver on ath79 Date: Tue, 13 Mar 2012 01:04:53 +0100 Message-Id: <1331597093-425-8-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331597093-425-1-git-send-email-hauke@hauke-m.de> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32667 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 14543 Lines: 555 The ath79 usb driver doesn't do anything special and is now converted to the generic ehci and ohci driver. This was tested on a TP-Link TL-WR1043ND (AR9132) CC: Gabor Juhos CC: Imre Kaloz CC: linux-mips@linux-mips.org CC: Ralf Baechle Signed-off-by: Hauke Mehrtens --- arch/mips/ath79/dev-usb.c | 31 +++++- drivers/usb/host/Kconfig | 12 ++- drivers/usb/host/ehci-ath79.c | 208 ----------------------------------------- drivers/usb/host/ehci-hcd.c | 5 - drivers/usb/host/ohci-ath79.c | 151 ----------------------------- drivers/usb/host/ohci-hcd.c | 5 - 6 files changed, 35 insertions(+), 377 deletions(-) delete mode 100644 drivers/usb/host/ehci-ath79.c delete mode 100644 drivers/usb/host/ohci-ath79.c diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index 002d6d2..36e9570 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include @@ -36,14 +38,19 @@ static struct resource ath79_ohci_resources[] = { }; static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); + +static struct usb_ohci_pdata ath79_ohci_pdata = { +}; + static struct platform_device ath79_ohci_device = { - .name = "ath79-ohci", + .name = "ohci-platform", .id = -1, .resource = ath79_ohci_resources, .num_resources = ARRAY_SIZE(ath79_ohci_resources), .dev = { .dma_mask = &ath79_ohci_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &ath79_ohci_pdata, }, }; @@ -60,8 +67,20 @@ static struct resource ath79_ehci_resources[] = { }; static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); + +static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { + .has_synopsys_hc_bug = 1, + .port_power_off = 1, +}; + +static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { + .caps_offset = 0x100, + .has_tt = 1, + .port_power_off = 1, +}; + static struct platform_device ath79_ehci_device = { - .name = "ath79-ehci", + .name = "ehci-platform", .id = -1, .resource = ath79_ehci_resources, .num_resources = ARRAY_SIZE(ath79_ehci_resources), @@ -101,7 +120,7 @@ static void __init ath79_usb_setup(void) ath79_ehci_resources[0].start = AR71XX_EHCI_BASE; ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1; - ath79_ehci_device.name = "ar71xx-ehci"; + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; platform_device_register(&ath79_ehci_device); } @@ -142,7 +161,7 @@ static void __init ar724x_usb_setup(void) ath79_ehci_resources[0].start = AR724X_EHCI_BASE; ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1; - ath79_ehci_device.name = "ar724x-ehci"; + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -159,7 +178,7 @@ static void __init ar913x_usb_setup(void) ath79_ehci_resources[0].start = AR913X_EHCI_BASE; ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1; - ath79_ehci_device.name = "ar913x-ehci"; + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -176,7 +195,7 @@ static void __init ar933x_usb_setup(void) ath79_ehci_resources[0].start = AR933X_EHCI_BASE; ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; - ath79_ehci_device.name = "ar933x-ehci"; + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0619884..33bd0ac 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -218,11 +218,15 @@ config USB_CNS3XXX_EHCI support. config USB_EHCI_ATH79 - bool "EHCI support for AR7XXX/AR9XXX SoCs" + bool "EHCI support for AR7XXX/AR9XXX SoCs (DEPRECATED)" depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X) select USB_EHCI_ROOT_HUB_TT + select USB_EHCI_HCD_PLATFORM default y ---help--- + This option is deprecated now and the driver was removed, use + USB_EHCI_HCD_PLATFORM instead. + Enables support for the built-in EHCI controller present on the Atheros AR7XXX/AR9XXX SoCs. @@ -312,10 +316,14 @@ config USB_OHCI_HCD_OMAP3 OMAP3 and later chips. config USB_OHCI_ATH79 - bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs" + bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs (DEPRECATED)" depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X) + select USB_OHCI_HCD_PLATFORM default y help + This option is deprecated now and the driver was removed, use + USB_OHCI_HCD_PLATFORM instead. + Enables support for the built-in OHCI controller present on the Atheros AR71XX/AR7240 SoCs. diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c deleted file mode 100644 index f1424f9..0000000 --- a/drivers/usb/host/ehci-ath79.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Bus Glue for Atheros AR7XXX/AR9XXX built-in EHCI controller. - * - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * Parts of this file are based on Atheros' 2.6.15 BSP - * Copyright (C) 2007 Atheros Communications, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include - -enum { - EHCI_ATH79_IP_V1 = 0, - EHCI_ATH79_IP_V2, -}; - -static const struct platform_device_id ehci_ath79_id_table[] = { - { - .name = "ar71xx-ehci", - .driver_data = EHCI_ATH79_IP_V1, - }, - { - .name = "ar724x-ehci", - .driver_data = EHCI_ATH79_IP_V2, - }, - { - .name = "ar913x-ehci", - .driver_data = EHCI_ATH79_IP_V2, - }, - { - .name = "ar933x-ehci", - .driver_data = EHCI_ATH79_IP_V2, - }, - { - /* terminating entry */ - }, -}; - -MODULE_DEVICE_TABLE(platform, ehci_ath79_id_table); - -static int ehci_ath79_init(struct usb_hcd *hcd) -{ - struct ehci_hcd *ehci = hcd_to_ehci(hcd); - struct platform_device *pdev = to_platform_device(hcd->self.controller); - const struct platform_device_id *id; - int ret; - - id = platform_get_device_id(pdev); - if (!id) { - dev_err(hcd->self.controller, "missing device id\n"); - return -EINVAL; - } - - switch (id->driver_data) { - case EHCI_ATH79_IP_V1: - ehci->has_synopsys_hc_bug = 1; - - ehci->caps = hcd->regs; - ehci->regs = hcd->regs + - HC_LENGTH(ehci, - ehci_readl(ehci, &ehci->caps->hc_capbase)); - break; - - case EHCI_ATH79_IP_V2: - hcd->has_tt = 1; - - ehci->caps = hcd->regs + 0x100; - ehci->regs = hcd->regs + 0x100 + - HC_LENGTH(ehci, - ehci_readl(ehci, &ehci->caps->hc_capbase)); - break; - - default: - BUG(); - } - - dbg_hcs_params(ehci, "reset"); - dbg_hcc_params(ehci, "reset"); - ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); - ehci->sbrn = 0x20; - - ehci_reset(ehci); - - ret = ehci_init(hcd); - if (ret) - return ret; - - ehci_port_power(ehci, 0); - - return 0; -} - -static const struct hc_driver ehci_ath79_hc_driver = { - .description = hcd_name, - .product_desc = "Atheros built-in EHCI controller", - .hcd_priv_size = sizeof(struct ehci_hcd), - .irq = ehci_irq, - .flags = HCD_MEMORY | HCD_USB2, - - .reset = ehci_ath79_init, - .start = ehci_run, - .stop = ehci_stop, - .shutdown = ehci_shutdown, - - .urb_enqueue = ehci_urb_enqueue, - .urb_dequeue = ehci_urb_dequeue, - .endpoint_disable = ehci_endpoint_disable, - .endpoint_reset = ehci_endpoint_reset, - - .get_frame_number = ehci_get_frame, - - .hub_status_data = ehci_hub_status_data, - .hub_control = ehci_hub_control, - - .relinquish_port = ehci_relinquish_port, - .port_handed_over = ehci_port_handed_over, - - .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -}; - -static int ehci_ath79_probe(struct platform_device *pdev) -{ - struct usb_hcd *hcd; - struct resource *res; - int irq; - int ret; - - if (usb_disabled()) - return -ENODEV; - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) { - dev_dbg(&pdev->dev, "no IRQ specified\n"); - return -ENODEV; - } - irq = res->start; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_dbg(&pdev->dev, "no base address specified\n"); - return -ENODEV; - } - - hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev, - dev_name(&pdev->dev)); - if (!hcd) - return -ENOMEM; - - hcd->rsrc_start = res->start; - hcd->rsrc_len = resource_size(res); - - if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { - dev_dbg(&pdev->dev, "controller already in use\n"); - ret = -EBUSY; - goto err_put_hcd; - } - - hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); - if (!hcd->regs) { - dev_dbg(&pdev->dev, "error mapping memory\n"); - ret = -EFAULT; - goto err_release_region; - } - - ret = usb_add_hcd(hcd, irq, IRQF_SHARED); - if (ret) - goto err_iounmap; - - return 0; - -err_iounmap: - iounmap(hcd->regs); - -err_release_region: - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -err_put_hcd: - usb_put_hcd(hcd); - return ret; -} - -static int ehci_ath79_remove(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - - usb_remove_hcd(hcd); - iounmap(hcd->regs); - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); - usb_put_hcd(hcd); - - return 0; -} - -static struct platform_driver ehci_ath79_driver = { - .probe = ehci_ath79_probe, - .remove = ehci_ath79_remove, - .id_table = ehci_ath79_id_table, - .driver = { - .owner = THIS_MODULE, - .name = "ath79-ehci", - } -}; - -MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ehci"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index afe0984..b417926 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1351,11 +1351,6 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER s5p_ehci_driver #endif -#ifdef CONFIG_USB_EHCI_ATH79 -#include "ehci-ath79.c" -#define PLATFORM_DRIVER ehci_ath79_driver -#endif - #ifdef CONFIG_SPARC_LEON #include "ehci-grlib.c" #define PLATFORM_DRIVER ehci_grlib_driver diff --git a/drivers/usb/host/ohci-ath79.c b/drivers/usb/host/ohci-ath79.c deleted file mode 100644 index 18d574d..0000000 --- a/drivers/usb/host/ohci-ath79.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * OHCI HCD (Host Controller Driver) for USB. - * - * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller. - * - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * Parts of this file are based on Atheros' 2.6.15 BSP - * Copyright (C) 2007 Atheros Communications, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include - -static int __devinit ohci_ath79_start(struct usb_hcd *hcd) -{ - struct ohci_hcd *ohci = hcd_to_ohci(hcd); - int ret; - - ret = ohci_init(ohci); - if (ret < 0) - return ret; - - ret = ohci_run(ohci); - if (ret < 0) - goto err; - - return 0; - -err: - ohci_stop(hcd); - return ret; -} - -static const struct hc_driver ohci_ath79_hc_driver = { - .description = hcd_name, - .product_desc = "Atheros built-in OHCI controller", - .hcd_priv_size = sizeof(struct ohci_hcd), - - .irq = ohci_irq, - .flags = HCD_USB11 | HCD_MEMORY, - - .start = ohci_ath79_start, - .stop = ohci_stop, - .shutdown = ohci_shutdown, - - .urb_enqueue = ohci_urb_enqueue, - .urb_dequeue = ohci_urb_dequeue, - .endpoint_disable = ohci_endpoint_disable, - - /* - * scheduling support - */ - .get_frame_number = ohci_get_frame, - - /* - * root hub support - */ - .hub_status_data = ohci_hub_status_data, - .hub_control = ohci_hub_control, - .start_port_reset = ohci_start_port_reset, -}; - -static int ohci_ath79_probe(struct platform_device *pdev) -{ - struct usb_hcd *hcd; - struct resource *res; - int irq; - int ret; - - if (usb_disabled()) - return -ENODEV; - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) { - dev_dbg(&pdev->dev, "no IRQ specified\n"); - return -ENODEV; - } - irq = res->start; - - hcd = usb_create_hcd(&ohci_ath79_hc_driver, &pdev->dev, - dev_name(&pdev->dev)); - if (!hcd) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_dbg(&pdev->dev, "no base address specified\n"); - ret = -ENODEV; - goto err_put_hcd; - } - hcd->rsrc_start = res->start; - hcd->rsrc_len = resource_size(res); - - if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { - dev_dbg(&pdev->dev, "controller already in use\n"); - ret = -EBUSY; - goto err_put_hcd; - } - - hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); - if (!hcd->regs) { - dev_dbg(&pdev->dev, "error mapping memory\n"); - ret = -EFAULT; - goto err_release_region; - } - - ohci_hcd_init(hcd_to_ohci(hcd)); - - ret = usb_add_hcd(hcd, irq, 0); - if (ret) - goto err_stop_hcd; - - return 0; - -err_stop_hcd: - iounmap(hcd->regs); -err_release_region: - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -err_put_hcd: - usb_put_hcd(hcd); - return ret; -} - -static int ohci_ath79_remove(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - - usb_remove_hcd(hcd); - iounmap(hcd->regs); - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); - usb_put_hcd(hcd); - - return 0; -} - -static struct platform_driver ohci_hcd_ath79_driver = { - .probe = ohci_ath79_probe, - .remove = ohci_ath79_remove, - .shutdown = usb_hcd_platform_shutdown, - .driver = { - .name = "ath79-ohci", - .owner = THIS_MODULE, - }, -}; - -MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ohci"); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index a2f4d4e..813714d 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1106,11 +1106,6 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver #endif -#ifdef CONFIG_USB_OHCI_ATH79 -#include "ohci-ath79.c" -#define PLATFORM_DRIVER ohci_hcd_ath79_driver -#endif - #ifdef CONFIG_CPU_XLR #include "ohci-xls.c" #define PLATFORM_DRIVER ohci_xls_driver -- 1.7.5.4 From Narendra.Puttaswamy@lantiq.com Wed Mar 14 10:10:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:10:37 +0100 (CET) Received: from smtp2.infineon.com ([217.10.60.23]:14027 "EHLO smtp2.infineon.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903646Ab2CNJKc convert rfc822-to-8bit (ORCPT ); Wed, 14 Mar 2012 10:10:32 +0100 X-SBRS: None Received: from unknown (HELO mucxv003.muc.infineon.com) ([172.23.11.20]) by smtp2.infineon.com with ESMTP/TLS/ADH-AES256-SHA; 14 Mar 2012 10:10:37 +0100 Received: from MUCSE595.eu.infineon.com (mucse595.eu.infineon.com [172.23.7.84]) by mucxv003.muc.infineon.com (Postfix) with ESMTPS for ; Wed, 14 Mar 2012 10:10:25 +0100 (CET) Received: from MUCSE501.eu.infineon.com ([169.254.7.124]) by MUCSE595.eu.infineon.com ([172.23.7.84]) with mapi id 14.01.0355.002; Wed, 14 Mar 2012 10:10:21 +0100 From: To: Subject: Sys exception behavior Thread-Topic: Sys exception behavior Thread-Index: Ac0Bwkc/JegQZ0JMTaOUxImXNJieyg== Date: Wed, 14 Mar 2012 09:10:20 +0000 Message-ID: <93D430A75FD60048911C7ED0A8F56E830AF688@MUCSE501.eu.infineon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.8.248] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 32668 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Narendra.Puttaswamy@lantiq.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 412 Lines: 6 Soon after "syscall" instruction is executed in the user mode, does the processor ensure that it raises an exception with the appropriate exception code (sys) set in Cause register *irrespective* of other high priority exception (for example, an interrupt) that may have occurred at that time. Looking into the source code of scall32-o32.S file, I infer the above. Can somebody please confirm the behavior? From juhosg@openwrt.org Wed Mar 14 10:23:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:23:14 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34753 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903648Ab2CNJXH (ORCPT ); Wed, 14 Mar 2012 10:23:07 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 0420E23C00C4; Wed, 14 Mar 2012 09:52:38 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH 0/2] MIPS: ath79: small fixes Date: Wed, 14 Mar 2012 11:28:34 +0100 Message-Id: <1331720916-4015-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 32669 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 493 Lines: 17 This patch-set contains a fix and a cleanup for ath79. Both patch was submitted to the list already, this is a rebased version of them. Gabor Juhos (1): MIPS: ath79: fix AR933X WMAC reset code Thomas Meyer (1): MIPS: ath79: Use kmemdup rather than duplicating its implementation arch/mips/ath79/dev-gpio-buttons.c | 4 +--- arch/mips/ath79/dev-leds-gpio.c | 4 +--- arch/mips/ath79/dev-wmac.c | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-) -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:23:40 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34755 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903649Ab2CNJXI (ORCPT ); Wed, 14 Mar 2012 10:23:08 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id A9A2023C00C1; Wed, 14 Mar 2012 09:52:42 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org, Thomas Meyer Subject: [PATCH 2/2] MIPS: ath79: Use kmemdup rather than duplicating its implementation Date: Wed, 14 Mar 2012 11:28:36 +0100 Message-Id: <1331720916-4015-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331720916-4015-1-git-send-email-juhosg@openwrt.org> References: <1331720916-4015-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32670 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1470 Lines: 50 From: Thomas Meyer The semantic patch that makes this change is available in scripts/coccinelle/api/memdup.cocci. Signed-off-by: Thomas Meyer arch/mips/ath79/dev-gpio-buttons.c | 4 +--- arch/mips/ath79/dev-leds-gpio.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/mips/ath79/dev-gpio-buttons.c b/arch/mips/ath79/dev-gpio-buttons.c index 4b0168a..366b35f 100644 --- a/arch/mips/ath79/dev-gpio-buttons.c +++ b/arch/mips/ath79/dev-gpio-buttons.c @@ -25,12 +25,10 @@ void __init ath79_register_gpio_keys_polled(int id, struct gpio_keys_button *p; int err; - p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); + p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL); if (!p) return; - memcpy(p, buttons, nbuttons * sizeof(*p)); - pdev = platform_device_alloc("gpio-keys-polled", id); if (!pdev) goto err_free_buttons; diff --git a/arch/mips/ath79/dev-leds-gpio.c b/arch/mips/ath79/dev-leds-gpio.c index cdade68..dcb1deb 100644 --- a/arch/mips/ath79/dev-leds-gpio.c +++ b/arch/mips/ath79/dev-leds-gpio.c @@ -24,12 +24,10 @@ void __init ath79_register_leds_gpio(int id, struct gpio_led *p; int err; - p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); + p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL); if (!p) return; - memcpy(p, leds, num_leds * sizeof(*p)); - pdev = platform_device_alloc("leds-gpio", id); if (!pdev) goto err_free_leds; -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:24:05 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34758 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903652Ab2CNJXI (ORCPT ); Wed, 14 Mar 2012 10:23:08 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 71F4F23C00C9; Wed, 14 Mar 2012 09:52:41 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org, stable@vger.kernel.org Subject: [PATCH 1/2] MIPS: ath79: fix AR933X WMAC reset code Date: Wed, 14 Mar 2012 11:28:35 +0100 Message-Id: <1331720916-4015-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331720916-4015-1-git-send-email-juhosg@openwrt.org> References: <1331720916-4015-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32671 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 803 Lines: 28 The current code puts the built-in WMAC device of the AR933X SoCs into reset instead of starting it. This causes a hard lock on AR933X based boards when the wireless driver tries to access the device. Signed-off-by: Gabor Juhos Cc: stable@vger.kernel.org arch/mips/ath79/dev-wmac.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c index e215070..9c717bf 100644 --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c @@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void) static int ar933x_wmac_reset(void) { - ath79_device_reset_clear(AR933X_RESET_WMAC); ath79_device_reset_set(AR933X_RESET_WMAC); + ath79_device_reset_clear(AR933X_RESET_WMAC); return 0; } -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:24:30 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34860 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903648Ab2CNJXr (ORCPT ); Wed, 14 Mar 2012 10:23:47 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 9F69023C00C4; Wed, 14 Mar 2012 09:53:22 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v5 0/7] MIPS: ath79: cleanup AR724X PCI support code Date: Wed, 14 Mar 2012 11:29:20 +0100 Message-Id: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32672 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1515 Lines: 34 This patch-set contains patches to clean up the recently introduced code for the AR724X PCI controller. This is required to allow to add support for the AR71XX PCI controller. Changes since v4: -fix build failure if PCI support is disabled. Gabor Juhos (7): MIPS: ath79: separate common PCI code MIPS: ath79: rename pci-ath724x.h MIPS: ath79: make ath724x_pcibios_init visible for external code MIPS: ath79: add a common PCI registration function MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name MIPS: ath79: replace ath724x to ar724x MIPS: ath79: use io-accessor macros in pci-ar724x.c arch/mips/ath79/Makefile | 1 + arch/mips/ath79/mach-ubnt-xm.c | 7 +- arch/mips/ath79/pci.c | 56 +++++++ .../asm/mach-ath79/pci-ath724x.h => ath79/pci.h} | 16 ++- .../asm/mach-ath79/{pci-ath724x.h => pci.h} | 17 +- arch/mips/pci/Makefile | 2 +- arch/mips/pci/pci-ar724x.c | 149 +++++++++++++++++ arch/mips/pci/pci-ath724x.c | 174 -------------------- 8 files changed, 230 insertions(+), 192 deletions(-) create mode 100644 arch/mips/ath79/pci.c copy arch/mips/{include/asm/mach-ath79/pci-ath724x.h => ath79/pci.h} (53%) rename arch/mips/include/asm/mach-ath79/{pci-ath724x.h => pci.h} (53%) create mode 100644 arch/mips/pci/pci-ar724x.c delete mode 100644 arch/mips/pci/pci-ath724x.c -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:24:52 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34863 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903706Ab2CNJXr (ORCPT ); Wed, 14 Mar 2012 10:23:47 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id C653823C00C9; Wed, 14 Mar 2012 09:53:22 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v5 1/7] MIPS: ath79: separate common PCI code Date: Wed, 14 Mar 2012 11:29:21 +0100 Message-Id: <1331720967-4049-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> References: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32673 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4048 Lines: 154 The 'pcibios_map_irq' and 'pcibios_plat_dev_init' are common functions and only instance one of them can be present in a single kernel. Currently these functions can be built only if the CONFIG_SOC_AR724X option is selected. However the ath79 platform contain support for the AR71XX SoCs,. The AR71XX SoCs have a differnet PCI controller, and those will require a different code. Move the common PCI code into a separeate file in order to be able to use that with other SoCs as well. Signed-off-by: Gabor Juhos Acked-by: René Bolldorf --- v5: - no changes v4: - add an Acked-by tag from René v3: - no changes v2: - no changes arch/mips/ath79/Makefile | 1 + arch/mips/ath79/pci.c | 46 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/pci/pci-ath724x.c | 34 ------------------------------- 3 files changed, 47 insertions(+), 34 deletions(-) create mode 100644 arch/mips/ath79/pci.c diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 3b911e09..221a76a9 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -11,6 +11,7 @@ obj-y := prom.o setup.o irq.o common.o clock.o gpio.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_PCI) += pci.o # # Devices diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c new file mode 100644 index 0000000..8db076e --- /dev/null +++ b/arch/mips/ath79/pci.c @@ -0,0 +1,46 @@ +/* + * Atheros AR71XX/AR724X specific PCI setup code + * + * Copyright (C) 2011 René Bolldorf + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +static struct ath724x_pci_data *pci_data; +static int pci_data_size; + +void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) +{ + pci_data = data; + pci_data_size = size; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) +{ + unsigned int devfn = dev->devfn; + int irq = -1; + + if (devfn > pci_data_size - 1) + return irq; + + irq = pci_data[devfn].irq; + + return irq; +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + unsigned int devfn = dev->devfn; + + if (devfn > pci_data_size - 1) + return PCIBIOS_DEVICE_NOT_FOUND; + + dev->dev.platform_data = pci_data[devfn].pdata; + + return PCIBIOS_SUCCESSFUL; +} diff --git a/arch/mips/pci/pci-ath724x.c b/arch/mips/pci/pci-ath724x.c index a4dd24a..1e810be 100644 --- a/arch/mips/pci/pci-ath724x.c +++ b/arch/mips/pci/pci-ath724x.c @@ -9,7 +9,6 @@ */ #include -#include #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) @@ -19,8 +18,6 @@ #define ATH724X_PCI_MEM_SIZE 0x08000000 static DEFINE_SPINLOCK(ath724x_pci_lock); -static struct ath724x_pci_data *pci_data; -static int pci_data_size; static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t *value) @@ -133,37 +130,6 @@ static struct pci_controller ath724x_pci_controller = { .mem_resource = &ath724x_mem_resource, }; -void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) -{ - pci_data = data; - pci_data_size = size; -} - -int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) -{ - unsigned int devfn = dev->devfn; - int irq = -1; - - if (devfn > pci_data_size - 1) - return irq; - - irq = pci_data[devfn].irq; - - return irq; -} - -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - unsigned int devfn = dev->devfn; - - if (devfn > pci_data_size - 1) - return PCIBIOS_DEVICE_NOT_FOUND; - - dev->dev.platform_data = pci_data[devfn].pdata; - - return PCIBIOS_SUCCESSFUL; -} - static int __init ath724x_pcibios_init(void) { register_pci_controller(&ath724x_pci_controller); -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:25:18 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34866 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903707Ab2CNJXr (ORCPT ); Wed, 14 Mar 2012 10:23:47 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id E887A23C00C4; Wed, 14 Mar 2012 09:53:22 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v5 2/7] MIPS: ath79: rename pci-ath724x.h Date: Wed, 14 Mar 2012 11:29:22 +0100 Message-Id: <1331720967-4049-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> References: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32674 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1725 Lines: 57 The declared function in this header file is used by the ath79 platform code only. Move the header to the platform directory. Signed-off-by: Gabor Juhos Acked-by: René Bolldorf --- v5: - no changes v4: - add an Acked-by tag from René v3: - move include "pci.h" out of the #ifdef CONFIG_PCI section v2: - no changes arch/mips/ath79/mach-ubnt-xm.c | 2 +- arch/mips/ath79/pci.c | 2 +- .../asm/mach-ath79/pci-ath724x.h => ath79/pci.h} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename arch/mips/{include/asm/mach-ath79/pci-ath724x.h => ath79/pci.h} (100%) diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c index 3c311a5..a043500 100644 --- a/arch/mips/ath79/mach-ubnt-xm.c +++ b/arch/mips/ath79/mach-ubnt-xm.c @@ -15,13 +15,13 @@ #ifdef CONFIG_PCI #include -#include #endif /* CONFIG_PCI */ #include "machtypes.h" #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" +#include "pci.h" #define UBNT_XM_GPIO_LED_L1 0 #define UBNT_XM_GPIO_LED_L2 1 diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 8db076e..4957428 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -9,7 +9,7 @@ */ #include -#include +#include "pci.h" static struct ath724x_pci_data *pci_data; static int pci_data_size; diff --git a/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/arch/mips/ath79/pci.h similarity index 100% rename from arch/mips/include/asm/mach-ath79/pci-ath724x.h rename to arch/mips/ath79/pci.h -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:25:41 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34870 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903708Ab2CNJXr (ORCPT ); Wed, 14 Mar 2012 10:23:47 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 170F723C00C9; Wed, 14 Mar 2012 09:53:23 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org, =?UTF-8?q?Ren=C3=A9=20Bolldorf?= Subject: [PATCH v5 3/7] MIPS: ath79: make ath724x_pcibios_init visible for external code Date: Wed, 14 Mar 2012 11:29:23 +0100 Message-Id: <1331720967-4049-4-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> References: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32675 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1921 Lines: 63 Signed-off-by: René Bolldorf Signed-off-by: Gabor Juhos --- v5: - fix build error if PCI support is disabled v4: - add a sob tag v3: - no changes v2: - fix a typo in my e-mail address arch/mips/include/asm/mach-ath79/pci.h | 20 ++++++++++++++++++++ arch/mips/pci/pci-ath724x.c | 3 ++- 2 files changed, 22 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/mach-ath79/pci.h diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h new file mode 100644 index 0000000..e0c4b53 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/pci.h @@ -0,0 +1,20 @@ +/* + * Atheros 724x PCI support + * + * Copyright (C) 2011 René Bolldorf + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_PCI_H +#define __ASM_MACH_ATH79_PCI_H + +#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) +int ath724x_pcibios_init(void); +#else +static inline int ath724x_pcibios_init(void) { return 0; } +#endif + +#endif /* __ASM_MACH_ATH79_PCI_H */ diff --git a/arch/mips/pci/pci-ath724x.c b/arch/mips/pci/pci-ath724x.c index 1e810be..be01b7f 100644 --- a/arch/mips/pci/pci-ath724x.c +++ b/arch/mips/pci/pci-ath724x.c @@ -9,6 +9,7 @@ */ #include +#include #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) @@ -130,7 +131,7 @@ static struct pci_controller ath724x_pci_controller = { .mem_resource = &ath724x_mem_resource, }; -static int __init ath724x_pcibios_init(void) +int __init ath724x_pcibios_init(void) { register_pci_controller(&ath724x_pci_controller); -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:26:05 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34873 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903709Ab2CNJXs (ORCPT ); Wed, 14 Mar 2012 10:23:48 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 47EB323C00C4; Wed, 14 Mar 2012 09:53:23 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v5 4/7] MIPS: ath79: add a common PCI registration function Date: Wed, 14 Mar 2012 11:29:24 +0100 Message-Id: <1331720967-4049-5-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> References: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32676 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2430 Lines: 87 The current code unconditionally registers the AR724X specific PCI controller, even if the kernel is running on a different SoC. Add a common function for PCI controller registration, and only register the AR724X PCI controller if the kernel is running on an AR724X SoC. Signed-off-by: Gabor Juhos --- v5: - no changes v4: - simplify ath79_register_pci function v3: - fix compile error if CONFIG_PCI is not defined - add __init annotation to ath79_register_pci v2: - no changes arch/mips/ath79/mach-ubnt-xm.c | 1 + arch/mips/ath79/pci.c | 10 ++++++++++ arch/mips/ath79/pci.h | 6 ++++++ arch/mips/pci/pci-ath724x.c | 2 -- 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c index a043500..edbc093 100644 --- a/arch/mips/ath79/mach-ubnt-xm.c +++ b/arch/mips/ath79/mach-ubnt-xm.c @@ -111,6 +111,7 @@ static void __init ubnt_xm_init(void) ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); #endif /* CONFIG_PCI */ + ath79_register_pci(); } MIPS_MACHINE(ATH79_MACH_UBNT_XM, diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 4957428..855a69d 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -9,6 +9,8 @@ */ #include +#include +#include #include "pci.h" static struct ath724x_pci_data *pci_data; @@ -44,3 +46,11 @@ int pcibios_plat_dev_init(struct pci_dev *dev) return PCIBIOS_SUCCESSFUL; } + +int __init ath79_register_pci(void) +{ + if (soc_is_ar724x()) + return ath724x_pcibios_init(); + + return -ENODEV; +} diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h index 454885f..787fac2 100644 --- a/arch/mips/ath79/pci.h +++ b/arch/mips/ath79/pci.h @@ -18,4 +18,10 @@ struct ath724x_pci_data { void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); +#ifdef CONFIG_PCI +int ath79_register_pci(void); +#else +static inline int ath79_register_pci(void) { return 0; } +#endif + #endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ diff --git a/arch/mips/pci/pci-ath724x.c b/arch/mips/pci/pci-ath724x.c index be01b7f..ebefc16 100644 --- a/arch/mips/pci/pci-ath724x.c +++ b/arch/mips/pci/pci-ath724x.c @@ -137,5 +137,3 @@ int __init ath724x_pcibios_init(void) return PCIBIOS_SUCCESSFUL; } - -arch_initcall(ath724x_pcibios_init); -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:26:29 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34875 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903711Ab2CNJXs (ORCPT ); Wed, 14 Mar 2012 10:23:48 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 706FE23C00C9; Wed, 14 Mar 2012 09:53:23 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v5 5/7] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name Date: Wed, 14 Mar 2012 11:29:25 +0100 Message-Id: <1331720967-4049-6-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> References: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32677 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1083 Lines: 33 Signed-off-by: Gabor Juhos Acked-by: René Bolldorf --- v5: - no changes v4: - add an Acked-by tag from René v3: - no changes v2: - no changes arch/mips/pci/Makefile | 2 +- arch/mips/pci/{pci-ath724x.c => pci-ar724x.c} | 0 2 files changed, 1 insertions(+), 1 deletions(-) rename arch/mips/pci/{pci-ath724x.c => pci-ar724x.c} (100%) diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c3ac4b0..172277c 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ ops-bcm63xx.o obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o -obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o +obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o # # These are still pretty much in the old state, watch, go blind. diff --git a/arch/mips/pci/pci-ath724x.c b/arch/mips/pci/pci-ar724x.c similarity index 100% rename from arch/mips/pci/pci-ath724x.c rename to arch/mips/pci/pci-ar724x.c -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:26:54 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34877 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903712Ab2CNJXs (ORCPT ); Wed, 14 Mar 2012 10:23:48 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 9874223C00C4; Wed, 14 Mar 2012 09:53:23 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v5 6/7] MIPS: ath79: replace ath724x to ar724x Date: Wed, 14 Mar 2012 11:29:26 +0100 Message-Id: <1331720967-4049-7-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> References: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32678 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8736 Lines: 272 Replace the 'ath724x' to 'ar724x' in function, variable and structure names to reflect the name of the real SoC. Signed-off-by: Gabor Juhos Acked-by: René Bolldorf --- v5: - update due to changes in a previous patch v4: - add an Acked-by tag from René - refreshed due to the changes in a previous patch v3: - no changes v2: - no changes arch/mips/ath79/mach-ubnt-xm.c | 4 +- arch/mips/ath79/pci.c | 6 ++-- arch/mips/ath79/pci.h | 10 +++--- arch/mips/include/asm/mach-ath79/pci.h | 4 +- arch/mips/pci/pci-ar724x.c | 62 ++++++++++++++++---------------- 5 files changed, 43 insertions(+), 43 deletions(-) diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c index edbc093..3266ee0 100644 --- a/arch/mips/ath79/mach-ubnt-xm.c +++ b/arch/mips/ath79/mach-ubnt-xm.c @@ -84,7 +84,7 @@ static struct ath79_spi_platform_data ubnt_xm_spi_data = { #ifdef CONFIG_PCI static struct ath9k_platform_data ubnt_xm_eeprom_data; -static struct ath724x_pci_data ubnt_xm_pci_data[] = { +static struct ar724x_pci_data ubnt_xm_pci_data[] = { { .irq = UBNT_XM_PCI_IRQ, .pdata = &ubnt_xm_eeprom_data, @@ -108,7 +108,7 @@ static void __init ubnt_xm_init(void) memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, sizeof(ubnt_xm_eeprom_data.eeprom_data)); - ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); + ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); #endif /* CONFIG_PCI */ ath79_register_pci(); diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 855a69d..72281fb 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -13,10 +13,10 @@ #include #include "pci.h" -static struct ath724x_pci_data *pci_data; +static struct ar724x_pci_data *pci_data; static int pci_data_size; -void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) +void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) { pci_data = data; pci_data_size = size; @@ -50,7 +50,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) int __init ath79_register_pci(void) { if (soc_is_ar724x()) - return ath724x_pcibios_init(); + return ar724x_pcibios_init(); return -ENODEV; } diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h index 787fac2..e0601c4 100644 --- a/arch/mips/ath79/pci.h +++ b/arch/mips/ath79/pci.h @@ -8,15 +8,15 @@ * by the Free Software Foundation. */ -#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H -#define __ASM_MACH_ATH79_PCI_ATH724X_H +#ifndef _ATH79_PCI_H +#define _ATH79_PCI_H -struct ath724x_pci_data { +struct ar724x_pci_data { int irq; void *pdata; }; -void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); +void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); #ifdef CONFIG_PCI int ath79_register_pci(void); @@ -24,4 +24,4 @@ int ath79_register_pci(void); static inline int ath79_register_pci(void) { return 0; } #endif -#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ +#endif /* _ATH79_PCI_H */ diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h index e0c4b53..6d7a837 100644 --- a/arch/mips/include/asm/mach-ath79/pci.h +++ b/arch/mips/include/asm/mach-ath79/pci.h @@ -12,9 +12,9 @@ #define __ASM_MACH_ATH79_PCI_H #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) -int ath724x_pcibios_init(void); +int ar724x_pcibios_init(void); #else -static inline int ath724x_pcibios_init(void) { return 0; } +static inline int ar724x_pcibios_init(void) { return 0; } #endif #endif /* __ASM_MACH_ATH79_PCI_H */ diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index ebefc16..772d12c 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -14,13 +14,13 @@ #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) -#define ATH724X_PCI_DEV_BASE 0x14000000 -#define ATH724X_PCI_MEM_BASE 0x10000000 -#define ATH724X_PCI_MEM_SIZE 0x08000000 +#define AR724X_PCI_DEV_BASE 0x14000000 +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x08000000 -static DEFINE_SPINLOCK(ath724x_pci_lock); +static DEFINE_SPINLOCK(ar724x_pci_lock); -static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, +static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t *value) { unsigned long flags, addr, tval, mask; @@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, if (where & (size - 1)) return PCIBIOS_BAD_REGISTER_NUMBER; - spin_lock_irqsave(&ath724x_pci_lock, flags); + spin_lock_irqsave(&ar724x_pci_lock, flags); switch (size) { case 1: addr = where & ~3; mask = 0xff000000 >> ((where % 4) * 8); - tval = reg_read(ATH724X_PCI_DEV_BASE + addr); + tval = reg_read(AR724X_PCI_DEV_BASE + addr); tval = tval & ~mask; *value = (tval >> ((4 - (where % 4))*8)); break; case 2: addr = where & ~3; mask = 0xffff0000 >> ((where % 4)*8); - tval = reg_read(ATH724X_PCI_DEV_BASE + addr); + tval = reg_read(AR724X_PCI_DEV_BASE + addr); tval = tval & ~mask; *value = (tval >> ((4 - (where % 4))*8)); break; case 4: - *value = reg_read(ATH724X_PCI_DEV_BASE + where); + *value = reg_read(AR724X_PCI_DEV_BASE + where); break; default: - spin_unlock_irqrestore(&ath724x_pci_lock, flags); + spin_unlock_irqrestore(&ar724x_pci_lock, flags); return PCIBIOS_BAD_REGISTER_NUMBER; } - spin_unlock_irqrestore(&ath724x_pci_lock, flags); + spin_unlock_irqrestore(&ar724x_pci_lock, flags); return PCIBIOS_SUCCESSFUL; } -static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, +static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t value) { unsigned long flags, tval, addr, mask; @@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, if (where & (size - 1)) return PCIBIOS_BAD_REGISTER_NUMBER; - spin_lock_irqsave(&ath724x_pci_lock, flags); + spin_lock_irqsave(&ar724x_pci_lock, flags); switch (size) { case 1: - addr = (ATH724X_PCI_DEV_BASE + where) & ~3; + addr = (AR724X_PCI_DEV_BASE + where) & ~3; mask = 0xff000000 >> ((where % 4)*8); tval = reg_read(addr); tval = tval & ~mask; @@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, reg_write(addr, tval); break; case 2: - addr = (ATH724X_PCI_DEV_BASE + where) & ~3; + addr = (AR724X_PCI_DEV_BASE + where) & ~3; mask = 0xffff0000 >> ((where % 4)*8); tval = reg_read(addr); tval = tval & ~mask; @@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, reg_write(addr, tval); break; case 4: - reg_write((ATH724X_PCI_DEV_BASE + where), value); + reg_write((AR724X_PCI_DEV_BASE + where), value); break; default: - spin_unlock_irqrestore(&ath724x_pci_lock, flags); + spin_unlock_irqrestore(&ar724x_pci_lock, flags); return PCIBIOS_BAD_REGISTER_NUMBER; } - spin_unlock_irqrestore(&ath724x_pci_lock, flags); + spin_unlock_irqrestore(&ar724x_pci_lock, flags); return PCIBIOS_SUCCESSFUL; } -static struct pci_ops ath724x_pci_ops = { - .read = ath724x_pci_read, - .write = ath724x_pci_write, +static struct pci_ops ar724x_pci_ops = { + .read = ar724x_pci_read, + .write = ar724x_pci_write, }; -static struct resource ath724x_io_resource = { +static struct resource ar724x_io_resource = { .name = "PCI IO space", .start = 0, .end = 0, .flags = IORESOURCE_IO, }; -static struct resource ath724x_mem_resource = { +static struct resource ar724x_mem_resource = { .name = "PCI memory space", - .start = ATH724X_PCI_MEM_BASE, - .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, + .start = AR724X_PCI_MEM_BASE, + .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1, .flags = IORESOURCE_MEM, }; -static struct pci_controller ath724x_pci_controller = { - .pci_ops = &ath724x_pci_ops, - .io_resource = &ath724x_io_resource, - .mem_resource = &ath724x_mem_resource, +static struct pci_controller ar724x_pci_controller = { + .pci_ops = &ar724x_pci_ops, + .io_resource = &ar724x_io_resource, + .mem_resource = &ar724x_mem_resource, }; -int __init ath724x_pcibios_init(void) +int __init ar724x_pcibios_init(void) { - register_pci_controller(&ath724x_pci_controller); + register_pci_controller(&ar724x_pci_controller); return PCIBIOS_SUCCESSFUL; } -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:23:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:27:16 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34880 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903713Ab2CNJXs (ORCPT ); Wed, 14 Mar 2012 10:23:48 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id BD96923C00C9; Wed, 14 Mar 2012 09:53:23 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v5 7/7] MIPS: ath79: use io-accessor macros in pci-ar724x.c Date: Wed, 14 Mar 2012 11:29:27 +0100 Message-Id: <1331720967-4049-8-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> References: <1331720967-4049-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32679 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3850 Lines: 130 Signed-off-by: Gabor Juhos Acked-by: René Bolldorf --- v5: - no changes v4: - add an Acked-by tag from René v3: - no changes v2: - no changes arch/mips/pci/pci-ar724x.c | 38 ++++++++++++++++++++++++-------------- 1 files changed, 24 insertions(+), 14 deletions(-) diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 772d12c..22f5e5b 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -11,19 +11,19 @@ #include #include -#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) -#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) - -#define AR724X_PCI_DEV_BASE 0x14000000 +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 #define AR724X_PCI_MEM_BASE 0x10000000 #define AR724X_PCI_MEM_SIZE 0x08000000 static DEFINE_SPINLOCK(ar724x_pci_lock); +static void __iomem *ar724x_pci_devcfg_base; static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t *value) { unsigned long flags, addr, tval, mask; + void __iomem *base; if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; @@ -31,25 +31,27 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, if (where & (size - 1)) return PCIBIOS_BAD_REGISTER_NUMBER; + base = ar724x_pci_devcfg_base; + spin_lock_irqsave(&ar724x_pci_lock, flags); switch (size) { case 1: addr = where & ~3; mask = 0xff000000 >> ((where % 4) * 8); - tval = reg_read(AR724X_PCI_DEV_BASE + addr); + tval = __raw_readl(base + addr); tval = tval & ~mask; *value = (tval >> ((4 - (where % 4))*8)); break; case 2: addr = where & ~3; mask = 0xffff0000 >> ((where % 4)*8); - tval = reg_read(AR724X_PCI_DEV_BASE + addr); + tval = __raw_readl(base + addr); tval = tval & ~mask; *value = (tval >> ((4 - (where % 4))*8)); break; case 4: - *value = reg_read(AR724X_PCI_DEV_BASE + where); + *value = __raw_readl(base + where); break; default: spin_unlock_irqrestore(&ar724x_pci_lock, flags); @@ -66,6 +68,7 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t value) { unsigned long flags, tval, addr, mask; + void __iomem *base; if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; @@ -73,27 +76,29 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, if (where & (size - 1)) return PCIBIOS_BAD_REGISTER_NUMBER; + base = ar724x_pci_devcfg_base; + spin_lock_irqsave(&ar724x_pci_lock, flags); switch (size) { case 1: - addr = (AR724X_PCI_DEV_BASE + where) & ~3; + addr = where & ~3; mask = 0xff000000 >> ((where % 4)*8); - tval = reg_read(addr); + tval = __raw_readl(base + addr); tval = tval & ~mask; tval |= (value << ((4 - (where % 4))*8)) & mask; - reg_write(addr, tval); + __raw_writel(tval, base + addr); break; case 2: - addr = (AR724X_PCI_DEV_BASE + where) & ~3; + addr = where & ~3; mask = 0xffff0000 >> ((where % 4)*8); - tval = reg_read(addr); + tval = __raw_readl(base + addr); tval = tval & ~mask; tval |= (value << ((4 - (where % 4))*8)) & mask; - reg_write(addr, tval); + __raw_writel(tval, base + addr); break; case 4: - reg_write((AR724X_PCI_DEV_BASE + where), value); + __raw_writel(value, (base + where)); break; default: spin_unlock_irqrestore(&ar724x_pci_lock, flags); @@ -133,6 +138,11 @@ static struct pci_controller ar724x_pci_controller = { int __init ar724x_pcibios_init(void) { + ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, + AR724X_PCI_CFG_SIZE); + if (ar724x_pci_devcfg_base == NULL) + return -ENOMEM; + register_pci_controller(&ar724x_pci_controller); return PCIBIOS_SUCCESSFUL; -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:30:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:30:38 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42599 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903713Ab2CNJae (ORCPT ); Wed, 14 Mar 2012 10:30:34 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 1640423C00CA; Wed, 14 Mar 2012 10:00:08 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 01/12] MIPS: ath79: remove superfluous alignment checks from pci-ar724x.c Date: Wed, 14 Mar 2012 11:36:03 +0100 Message-Id: <1331721374-4144-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32680 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1034 Lines: 38 The alignment of the 'where' parameters are checked in the core PCI code already. Signed-off-by: Gabor Juhos --- v3: - no changes v2: - no changes arch/mips/pci/pci-ar724x.c | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-) diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 22f5e5b..342bf4a 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -28,9 +28,6 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; - if (where & (size - 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - base = ar724x_pci_devcfg_base; spin_lock_irqsave(&ar724x_pci_lock, flags); @@ -73,9 +70,6 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; - if (where & (size - 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - base = ar724x_pci_devcfg_base; spin_lock_irqsave(&ar724x_pci_lock, flags); -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:30:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:30:59 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42609 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903715Ab2CNJah (ORCPT ); Wed, 14 Mar 2012 10:30:37 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id DE2A723C00C9; Wed, 14 Mar 2012 10:00:07 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 00/12] MIPS: ath79: AR724X PCI fixes and AR71XX PCI support Date: Wed, 14 Mar 2012 11:36:02 +0100 Message-Id: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 32681 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1691 Lines: 41 This patch set fixes some errors in the AR724X specific PCI code, and adds support for the PCI Host controller of the AR71XX SoCs. This depends the following patch set: v5 of 'MIPS: ath79: cleanup AR724X PCI support code' Changes since v2: - fix build error if PCI is disabled Gabor Juhos (12): MIPS: ath79: remove superfluous alignment checks from pci-ar724x.c MIPS: ath79: fix broken ar724x_pci_{read,write} functions MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCs MIPS: ath79: fix a wrong IRQ number MIPS: ath79: add PCI IRQ handling code for AR724X SoCs MIPS: ath79: get rid of some ifdefs in mach-ubnt-xm.c MIPS: ath79: allow to use board specific pci_plat_dev_init functions MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs MIPS: ath79: allow to use SoC specific PCI IRQ maps MIPS: ath79: remove ar724x_pci_add_data function MIPS: ath79: register PCI controller on the PB44 board MIPS: ath79: update copyright headers of PCI related files arch/mips/ath79/Kconfig | 1 + arch/mips/ath79/mach-pb44.c | 2 + arch/mips/ath79/mach-ubnt-xm.c | 42 ++-- arch/mips/ath79/pci.c | 97 +++++++-- arch/mips/ath79/pci.h | 19 +- arch/mips/include/asm/mach-ath79/irq.h | 6 +- arch/mips/include/asm/mach-ath79/pci.h | 14 +- arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-ar71xx.c | 375 ++++++++++++++++++++++++++++++++ arch/mips/pci/pci-ar724x.c | 211 +++++++++++++++--- 10 files changed, 689 insertions(+), 79 deletions(-) create mode 100644 arch/mips/pci/pci-ar71xx.c -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:30:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:31:22 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42615 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903717Ab2CNJaj (ORCPT ); Wed, 14 Mar 2012 10:30:39 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 5C24023C00CC; Wed, 14 Mar 2012 10:00:08 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 02/12] MIPS: ath79: fix broken ar724x_pci_{read,write} functions Date: Wed, 14 Mar 2012 11:36:04 +0100 Message-Id: <1331721374-4144-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32682 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9783 Lines: 220 The current ar724x_pci_{read,write} functions are broken. Due to that, pci_read_config_byte returns with bogus values, and pci_write_config_{byte,word} unconditionally clears the accessed PCI configuration registers instead of changing the value of them. The patch fixes the broken functions, thus the PCI configuration space can be accessed correctly. Signed-off-by: Gabor Juhos --- v3: - no changes v2: - no changes Output of 'lspci -vv' without the patch: 00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless Network Adapter (PCI-Express) (rev 01) Subsystem: Atheros Communications Inc. Device a091 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- arch/mips/pci/pci-ar724x.c | 52 ++++++++++++++++++++++---------------------- 1 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 342bf4a..bb4f216 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -22,8 +22,9 @@ static void __iomem *ar724x_pci_devcfg_base; static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t *value) { - unsigned long flags, addr, tval, mask; + unsigned long flags; void __iomem *base; + u32 data; if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; @@ -31,24 +32,22 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, base = ar724x_pci_devcfg_base; spin_lock_irqsave(&ar724x_pci_lock, flags); + data = __raw_readl(base + (where & ~3)); switch (size) { case 1: - addr = where & ~3; - mask = 0xff000000 >> ((where % 4) * 8); - tval = __raw_readl(base + addr); - tval = tval & ~mask; - *value = (tval >> ((4 - (where % 4))*8)); + if (where & 1) + data >>= 8; + if (where & 2) + data >>= 16; + data &= 0xff; break; case 2: - addr = where & ~3; - mask = 0xffff0000 >> ((where % 4)*8); - tval = __raw_readl(base + addr); - tval = tval & ~mask; - *value = (tval >> ((4 - (where % 4))*8)); + if (where & 2) + data >>= 16; + data &= 0xffff; break; case 4: - *value = __raw_readl(base + where); break; default: spin_unlock_irqrestore(&ar724x_pci_lock, flags); @@ -57,6 +56,7 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, } spin_unlock_irqrestore(&ar724x_pci_lock, flags); + *value = data; return PCIBIOS_SUCCESSFUL; } @@ -64,8 +64,10 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t value) { - unsigned long flags, tval, addr, mask; + unsigned long flags; void __iomem *base; + u32 data; + int s; if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; @@ -73,26 +75,21 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, base = ar724x_pci_devcfg_base; spin_lock_irqsave(&ar724x_pci_lock, flags); + data = __raw_readl(base + (where & ~3)); switch (size) { case 1: - addr = where & ~3; - mask = 0xff000000 >> ((where % 4)*8); - tval = __raw_readl(base + addr); - tval = tval & ~mask; - tval |= (value << ((4 - (where % 4))*8)) & mask; - __raw_writel(tval, base + addr); + s = ((where & 3) * 8); + data &= ~(0xff << s); + data |= ((value & 0xff) << s); break; case 2: - addr = where & ~3; - mask = 0xffff0000 >> ((where % 4)*8); - tval = __raw_readl(base + addr); - tval = tval & ~mask; - tval |= (value << ((4 - (where % 4))*8)) & mask; - __raw_writel(tval, base + addr); + s = ((where & 2) * 8); + data &= ~(0xffff << s); + data |= ((value & 0xffff) << s); break; case 4: - __raw_writel(value, (base + where)); + data = value; break; default: spin_unlock_irqrestore(&ar724x_pci_lock, flags); @@ -100,6 +97,9 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_BAD_REGISTER_NUMBER; } + __raw_writel(data, base + (where & ~3)); + /* flush write */ + __raw_readl(base + (where & ~3)); spin_unlock_irqrestore(&ar724x_pci_lock, flags); return PCIBIOS_SUCCESSFUL; -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:30:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:31:45 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42626 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903712Ab2CNJan (ORCPT ); Wed, 14 Mar 2012 10:30:43 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 904A923C00D5; Wed, 14 Mar 2012 10:00:08 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 03/12] MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCs Date: Wed, 14 Mar 2012 11:36:05 +0100 Message-Id: <1331721374-4144-4-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32683 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4303 Lines: 135 The PCI controller of the AR724X SoCs has a hardware bag. If the BAR0 register of the PCI device is set to the proper base address, the memory address space of the device is not accessible. When the device driver tries to access the memory address space of the PCI device, it leads to data bus error, similiar to this: Data bus error, epc == 801f69a0, ra == 801f698c Oops[#1]: Cpu 0 $ 0 : 00000000 00000061 deadbeef 000000ff $ 4 : 00000000 000000ff 00000014 00000000 $ 8 : ff000000 fffffffc 00000000 00000000 $12 : 000001f5 00000006 00000000 6e637920 $16 : 81ca4000 81ca0260 81ca4000 804d70f0 $20 : fffffff4 0000002b 803ad4c4 00000000 $24 : 00000003 00000000 $28 : 81c20000 81c21c60 00000000 801f698c Hi : 00000000 Lo : 00000000 epc : 801f69a0 ath9k_hw_init+0xd0/0xa70 Not tainted ra : 801f698c ath9k_hw_init+0xbc/0xa70 Status: 1000c103 KERNEL EXL IE Cause : 1080001c PrId : 00019374 (MIPS 24Kc) Modules linked in: Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000) Stack : 00000000 00000000 00000000 00000000 81c21c78 81ca0260 00000000 804d70f0 81ca0260 81c21cc0 81ca0e80 81ca0260 81ca4000 804d70f0 fffffff4 0000002b 803ad4c4 00000000 00000000 801e3ae8 81c9d080 81ca0e80 b0000000 800b9b9c 00000008 81c9d000 8031aeb0 802d38a0 00000000 81c14c00 81c14c60 00000000 81ca0e80 81ca0260 b0000000 801f08a4 81c9c820 81c21d48 81c9c820 80144320 ... Call Trace: [<801f69a0>] ath9k_hw_init+0xd0/0xa70 [<801e3ae8>] ath9k_init_device+0x174/0x680 [<801f08a4>] ath_pci_probe+0x27c/0x380 [<8019e490>] pci_device_probe+0x74/0x9c [<801bfadc>] driver_probe_device+0x9c/0x1b4 [<801bfcb0>] __driver_attach+0xbc/0xc4 [<801bea0c>] bus_for_each_dev+0x5c/0x98 [<801bf394>] bus_add_driver+0x1d0/0x2a4 [<801c0364>] driver_register+0x8c/0x16c [<8019e72c>] __pci_register_driver+0x4c/0xe4 [<803d3d40>] ath9k_init+0x3c/0x88 [<80060930>] do_one_initcall+0x3c/0x1cc [<803c297c>] kernel_init+0xa4/0x138 [<80063c04>] kernel_thread_helper+0x10/0x18 Signed-off-by: Gabor Juhos --- v3: - no changes v2: - apply the workaround on AR7240 only - remove unrelated defines arch/mips/pci/pci-ar724x.c | 36 +++++++++++++++++++++++++++++++++++- 1 files changed, 35 insertions(+), 1 deletions(-) diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index bb4f216..07b7e30 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -9,6 +9,7 @@ */ #include +#include #include #define AR724X_PCI_CFG_BASE 0x14000000 @@ -16,9 +17,14 @@ #define AR724X_PCI_MEM_BASE 0x10000000 #define AR724X_PCI_MEM_SIZE 0x08000000 +#define AR7240_BAR0_WAR_VALUE 0xffff + static DEFINE_SPINLOCK(ar724x_pci_lock); static void __iomem *ar724x_pci_devcfg_base; +static u32 ar724x_pci_bar0_value; +static bool ar724x_pci_bar0_is_cached; + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t *value) { @@ -56,7 +62,14 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, } spin_unlock_irqrestore(&ar724x_pci_lock, flags); - *value = data; + + if (where == PCI_BASE_ADDRESS_0 && size == 4 && + ar724x_pci_bar0_is_cached) { + /* use the cached value */ + *value = ar724x_pci_bar0_value; + } else { + *value = data; + } return PCIBIOS_SUCCESSFUL; } @@ -72,6 +85,27 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; + if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) { + if (value != 0xffffffff) { + /* + * WAR for a hw issue. If the BAR0 register of the + * device is set to the proper base address, the + * memory space of the device is not accessible. + * + * Cache the intended value so it can be read back, + * and write a SoC specific constant value to the + * BAR0 register in order to make the device memory + * accessible. + */ + ar724x_pci_bar0_is_cached = true; + ar724x_pci_bar0_value = value; + + value = AR7240_BAR0_WAR_VALUE; + } else { + ar724x_pci_bar0_is_cached = false; + } + } + base = ar724x_pci_devcfg_base; spin_lock_irqsave(&ar724x_pci_lock, flags); -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:30:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:32:08 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42632 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903719Ab2CNJao (ORCPT ); Wed, 14 Mar 2012 10:30:44 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id AD9D023C00D6; Wed, 14 Mar 2012 10:00:08 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 04/12] MIPS: ath79: fix a wrong IRQ number Date: Wed, 14 Mar 2012 11:36:06 +0100 Message-Id: <1331721374-4144-5-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32684 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2351 Lines: 78 The Ubiquiti XM board setup code uses an invalid IRQ number, because it if above of NR_IRQS. This leads to failed 'request_irq' calls: ath9k 0000:00:00.0: request_irq failed ath9k: probe of 0000:00:00.0 failed with error -22 Preserve some IRQ numbers for the built-in IRQ controller of PCI host controllers in the AR71XX/AR724X SoCs, and use the correct IRQ number in the board setup code. Signed-off-by: Gabor Juhos --- v3: - no changes v2: - no changes The IRQ controller code is also missing, that will be added in a separate patch. arch/mips/ath79/mach-ubnt-xm.c | 5 +++-- arch/mips/include/asm/mach-ath79/irq.h | 6 +++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c index 3266ee0..0d95b67 100644 --- a/arch/mips/ath79/mach-ubnt-xm.c +++ b/arch/mips/ath79/mach-ubnt-xm.c @@ -17,6 +17,8 @@ #include #endif /* CONFIG_PCI */ +#include + #include "machtypes.h" #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" @@ -33,7 +35,6 @@ #define UBNT_XM_KEYS_POLL_INTERVAL 20 #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) -#define UBNT_XM_PCI_IRQ 48 #define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { @@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_xm_eeprom_data; static struct ar724x_pci_data ubnt_xm_pci_data[] = { { - .irq = UBNT_XM_PCI_IRQ, + .irq = ATH79_PCI_IRQ(0), .pdata = &ubnt_xm_eeprom_data, }, }; diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 519958f..6ae2646 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -10,11 +10,15 @@ #define __ASM_MACH_ATH79_IRQ_H #define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 40 +#define NR_IRQS 46 #define ATH79_MISC_IRQ_BASE 8 #define ATH79_MISC_IRQ_COUNT 32 +#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT) +#define ATH79_PCI_IRQ_COUNT 6 +#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x)) + #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:30:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:32:30 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42641 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903711Ab2CNJas (ORCPT ); Wed, 14 Mar 2012 10:30:48 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id C9A3523C00D9; Wed, 14 Mar 2012 10:00:08 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 05/12] MIPS: ath79: add PCI IRQ handling code for AR724X SoCs Date: Wed, 14 Mar 2012 11:36:07 +0100 Message-Id: <1331721374-4144-6-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32685 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5787 Lines: 218 The PCI Host Controller of the AR724x SoC has a built-in IRQ controller. The current code does not supports that, so the IRQ lines wired to this controller are not usable. This leads to failed 'request_irq' calls: ath9k 0000:00:00.0: request_irq failed ath9k: probe of 0000:00:00.0 failed with error -89 This patch adds support for the IRQ controller in order to make PCI IRQs work. Signed-off-by: Gabor Juhos --- v3: - update due to a change in a previous patch v2: - move the interrupt controller related defines from the workaround patch arch/mips/ath79/pci.c | 3 +- arch/mips/include/asm/mach-ath79/pci.h | 4 +- arch/mips/pci/pci-ar724x.c | 118 +++++++++++++++++++++++++++++++- 3 files changed, 120 insertions(+), 5 deletions(-) diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 72281fb..14f981c2 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -10,6 +10,7 @@ #include #include +#include #include #include "pci.h" @@ -50,7 +51,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) int __init ath79_register_pci(void) { if (soc_is_ar724x()) - return ar724x_pcibios_init(); + return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); return -ENODEV; } diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h index 6d7a837..2eb0181 100644 --- a/arch/mips/include/asm/mach-ath79/pci.h +++ b/arch/mips/include/asm/mach-ath79/pci.h @@ -12,9 +12,9 @@ #define __ASM_MACH_ATH79_PCI_H #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) -int ar724x_pcibios_init(void); +int ar724x_pcibios_init(int irq); #else -static inline int ar724x_pcibios_init(void) { return 0; } +static inline int ar724x_pcibios_init(int irq) { return 0; } #endif #endif /* __ASM_MACH_ATH79_PCI_H */ diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 07b7e30..04f433a 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -8,19 +8,32 @@ * by the Free Software Foundation. */ +#include #include #include +#include #include #define AR724X_PCI_CFG_BASE 0x14000000 #define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + #define AR724X_PCI_MEM_BASE 0x10000000 #define AR724X_PCI_MEM_SIZE 0x08000000 +#define AR724X_PCI_REG_INT_STATUS 0x4c +#define AR724X_PCI_REG_INT_MASK 0x50 + +#define AR724X_PCI_INT_DEV0 BIT(14) + +#define AR724X_PCI_IRQ_COUNT 1 + #define AR7240_BAR0_WAR_VALUE 0xffff static DEFINE_SPINLOCK(ar724x_pci_lock); static void __iomem *ar724x_pci_devcfg_base; +static void __iomem *ar724x_pci_ctrl_base; static u32 ar724x_pci_bar0_value; static bool ar724x_pci_bar0_is_cached; @@ -164,14 +177,115 @@ static struct pci_controller ar724x_pci_controller = { .mem_resource = &ar724x_mem_resource, }; -int __init ar724x_pcibios_init(void) +static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *base; + u32 pending; + + base = ar724x_pci_ctrl_base; + + pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & + __raw_readl(base + AR724X_PCI_REG_INT_MASK); + + if (pending & AR724X_PCI_INT_DEV0) + generic_handle_irq(ATH79_PCI_IRQ(0)); + + else + spurious_interrupt(); +} + +static void ar724x_pci_irq_unmask(struct irq_data *d) +{ + void __iomem *base; + u32 t; + + base = ar724x_pci_ctrl_base; + + switch (d->irq) { + case ATH79_PCI_IRQ(0): + t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); + __raw_writel(t | AR724X_PCI_INT_DEV0, + base + AR724X_PCI_REG_INT_MASK); + /* flush write */ + __raw_readl(base + AR724X_PCI_REG_INT_MASK); + } +} + +static void ar724x_pci_irq_mask(struct irq_data *d) +{ + void __iomem *base; + u32 t; + + base = ar724x_pci_ctrl_base; + + switch (d->irq) { + case ATH79_PCI_IRQ(0): + t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); + __raw_writel(t & ~AR724X_PCI_INT_DEV0, + base + AR724X_PCI_REG_INT_MASK); + + /* flush write */ + __raw_readl(base + AR724X_PCI_REG_INT_MASK); + + t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); + __raw_writel(t | AR724X_PCI_INT_DEV0, + base + AR724X_PCI_REG_INT_STATUS); + + /* flush write */ + __raw_readl(base + AR724X_PCI_REG_INT_STATUS); + } +} + +static struct irq_chip ar724x_pci_irq_chip = { + .name = "AR724X PCI ", + .irq_mask = ar724x_pci_irq_mask, + .irq_unmask = ar724x_pci_irq_unmask, + .irq_mask_ack = ar724x_pci_irq_mask, +}; + +static void __init ar724x_pci_irq_init(int irq) +{ + void __iomem *base; + int i; + + base = ar724x_pci_ctrl_base; + + __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); + __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); + + BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); + + for (i = ATH79_PCI_IRQ_BASE; + i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, + handle_level_irq); + + irq_set_chained_handler(irq, ar724x_pci_irq_handler); +} + +int __init ar724x_pcibios_init(int irq) { + int ret; + + ret = -ENOMEM; + ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, AR724X_PCI_CFG_SIZE); if (ar724x_pci_devcfg_base == NULL) - return -ENOMEM; + goto err; + ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE, + AR724X_PCI_CTRL_SIZE); + if (ar724x_pci_ctrl_base == NULL) + goto err_unmap_devcfg; + + ar724x_pci_irq_init(irq); register_pci_controller(&ar724x_pci_controller); return PCIBIOS_SUCCESSFUL; + +err_unmap_devcfg: + iounmap(ar724x_pci_devcfg_base); +err: + return ret; } -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:30:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:32:56 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42645 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2CNJat (ORCPT ); Wed, 14 Mar 2012 10:30:49 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id F00E223C00DA; Wed, 14 Mar 2012 10:00:08 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 06/12] MIPS: ath79: get rid of some ifdefs in mach-ubnt-xm.c Date: Wed, 14 Mar 2012 11:36:08 +0100 Message-Id: <1331721374-4144-7-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32686 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1680 Lines: 64 Remove a superfluous ifdef around an include. Also reorganize the board setup code a bit, so another ifdef can be removed. Signed-off-by: Gabor Juhos --- v3: - no changes v2: - no changes arch/mips/ath79/mach-ubnt-xm.c | 23 ++++++++++++----------- 1 files changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c index 0d95b67..1e6b986 100644 --- a/arch/mips/ath79/mach-ubnt-xm.c +++ b/arch/mips/ath79/mach-ubnt-xm.c @@ -12,10 +12,7 @@ #include #include - -#ifdef CONFIG_PCI #include -#endif /* CONFIG_PCI */ #include @@ -91,6 +88,17 @@ static struct ar724x_pci_data ubnt_xm_pci_data[] = { .pdata = &ubnt_xm_eeprom_data, }, }; + +static void __init ubnt_xm_pci_init(void) +{ + memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, + sizeof(ubnt_xm_eeprom_data.eeprom_data)); + + ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); + ath79_register_pci(); +} +#else +static inline void ubnt_xm_pci_init(void) {} #endif /* CONFIG_PCI */ static void __init ubnt_xm_init(void) @@ -105,14 +113,7 @@ static void __init ubnt_xm_init(void) ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, ARRAY_SIZE(ubnt_xm_spi_info)); -#ifdef CONFIG_PCI - memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, - sizeof(ubnt_xm_eeprom_data.eeprom_data)); - - ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); -#endif /* CONFIG_PCI */ - - ath79_register_pci(); + ubnt_xm_pci_init(); } MIPS_MACHINE(ATH79_MACH_UBNT_XM, -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:30:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:33:28 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42661 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903723Ab2CNJax (ORCPT ); Wed, 14 Mar 2012 10:30:53 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 69D2323C00E0; Wed, 14 Mar 2012 10:00:09 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org, Imre Kaloz Subject: [PATCH v3 08/12] MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs Date: Wed, 14 Mar 2012 11:36:10 +0100 Message-Id: <1331721374-4144-9-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32687 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 12393 Lines: 443 The Atheros AR71XX SoCs have a built-in PCI Host Controller. This patch adds a driver for that, and modifies the relevant files in order to allow to register the PCI controller from board specific setup. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- v3: - fix build error if PCI is disabled v2: - add missing pci-ar71xx.c arch/mips/ath79/Kconfig | 1 + arch/mips/include/asm/mach-ath79/pci.h | 6 + arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-ar71xx.c | 375 ++++++++++++++++++++++++++++++++ 4 files changed, 383 insertions(+), 0 deletions(-) create mode 100644 arch/mips/pci/pci-ar71xx.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index e0fae8f..bc6edad 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -52,6 +52,7 @@ endmenu config SOC_AR71XX select USB_ARCH_HAS_EHCI select USB_ARCH_HAS_OHCI + select HW_HAS_PCI def_bool n config SOC_AR724X diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h index 2eb0181..b12b087 100644 --- a/arch/mips/include/asm/mach-ath79/pci.h +++ b/arch/mips/include/asm/mach-ath79/pci.h @@ -11,6 +11,12 @@ #ifndef __ASM_MACH_ATH79_PCI_H #define __ASM_MACH_ATH79_PCI_H +#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX) +int ar71xx_pcibios_init(void); +#else +static inline int ar71xx_pcibios_init(void) { return 0; } +#endif + #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) int ar724x_pcibios_init(int irq); #else diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 172277c..b1c0a1c 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ ops-bcm63xx.o obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o +obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o # diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c new file mode 100644 index 0000000..1552522 --- /dev/null +++ b/arch/mips/pci/pci-ar71xx.c @@ -0,0 +1,375 @@ +/* + * Atheros AR71xx PCI host controller driver + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x08000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR71XX_PCI_REG_CRP_AD_CBE 0x00 +#define AR71XX_PCI_REG_CRP_WRDATA 0x04 +#define AR71XX_PCI_REG_CRP_RDDATA 0x08 +#define AR71XX_PCI_REG_CFG_AD 0x0c +#define AR71XX_PCI_REG_CFG_CBE 0x10 +#define AR71XX_PCI_REG_CFG_WRDATA 0x14 +#define AR71XX_PCI_REG_CFG_RDDATA 0x18 +#define AR71XX_PCI_REG_PCI_ERR 0x1c +#define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20 +#define AR71XX_PCI_REG_AHB_ERR 0x24 +#define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28 + +#define AR71XX_PCI_CRP_CMD_WRITE 0x00010000 +#define AR71XX_PCI_CRP_CMD_READ 0x00000000 +#define AR71XX_PCI_CFG_CMD_READ 0x0000000a +#define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b + +#define AR71XX_PCI_INT_CORE BIT(4) +#define AR71XX_PCI_INT_DEV2 BIT(2) +#define AR71XX_PCI_INT_DEV1 BIT(1) +#define AR71XX_PCI_INT_DEV0 BIT(0) + +#define AR71XX_PCI_IRQ_COUNT 5 + +static DEFINE_SPINLOCK(ar71xx_pci_lock); +static void __iomem *ar71xx_pcicfg_base; + +/* Byte lane enable bits */ +static const u8 ar71xx_pci_ble_table[4][4] = { + {0x0, 0xf, 0xf, 0xf}, + {0xe, 0xd, 0xb, 0x7}, + {0xc, 0xf, 0x3, 0xf}, + {0xf, 0xf, 0xf, 0xf}, +}; + +static const u32 ar71xx_pci_read_mask[8] = { + 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 +}; + +static inline u32 ar71xx_pci_get_ble(int where, int size, int local) +{ + u32 t; + + t = ar71xx_pci_ble_table[size & 3][where & 3]; + BUG_ON(t == 0xf); + t <<= (local) ? 20 : 4; + + return t; +} + +static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, + int where) +{ + u32 ret; + + if (!bus->number) { + /* type 0 */ + ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) | + (where & ~3); + } else { + /* type 1 */ + ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) | + (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; + } + + return ret; +} + +static int ar71xx_pci_check_error(int quiet) +{ + void __iomem *base = ar71xx_pcicfg_base; + u32 pci_err; + u32 ahb_err; + + pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; + if (pci_err) { + if (!quiet) { + u32 addr; + + addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); + pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", + "PCI", pci_err, addr); + } + + /* clear PCI error status */ + __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); + } + + ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; + if (ahb_err) { + if (!quiet) { + u32 addr; + + addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); + pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", + "AHB", ahb_err, addr); + } + + /* clear AHB error status */ + __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); + } + + return !!(ahb_err | pci_err); +} + +static inline void ar71xx_pci_local_write(int where, int size, u32 value) +{ + void __iomem *base = ar71xx_pcicfg_base; + u32 ad_cbe; + + value = value << (8 * (where & 3)); + + ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3); + ad_cbe |= ar71xx_pci_get_ble(where, size, 1); + + __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); + __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); +} + +static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, + unsigned int devfn, + int where, int size, u32 cmd) +{ + void __iomem *base = ar71xx_pcicfg_base; + u32 addr; + + addr = ar71xx_pci_bus_addr(bus, devfn, where); + + __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); + __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), + base + AR71XX_PCI_REG_CFG_CBE); + + return ar71xx_pci_check_error(1); +} + +static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + void __iomem *base = ar71xx_pcicfg_base; + unsigned long flags; + u32 data; + int err; + int ret; + + ret = PCIBIOS_SUCCESSFUL; + data = ~0; + + spin_lock_irqsave(&ar71xx_pci_lock, flags); + + err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, + AR71XX_PCI_CFG_CMD_READ); + if (err) + ret = PCIBIOS_DEVICE_NOT_FOUND; + else + data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); + + spin_unlock_irqrestore(&ar71xx_pci_lock, flags); + + *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7]; + + return ret; +} + +static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + void __iomem *base = ar71xx_pcicfg_base; + unsigned long flags; + int err; + int ret; + + value = value << (8 * (where & 3)); + ret = PCIBIOS_SUCCESSFUL; + + spin_lock_irqsave(&ar71xx_pci_lock, flags); + + err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, + AR71XX_PCI_CFG_CMD_WRITE); + if (err) + ret = PCIBIOS_DEVICE_NOT_FOUND; + else + __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); + + spin_unlock_irqrestore(&ar71xx_pci_lock, flags); + + return ret; +} + +static struct pci_ops ar71xx_pci_ops = { + .read = ar71xx_pci_read_config, + .write = ar71xx_pci_write_config, +}; + +static struct resource ar71xx_pci_io_resource = { + .name = "PCI IO space", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO, +}; + +static struct resource ar71xx_pci_mem_resource = { + .name = "PCI memory space", + .start = AR71XX_PCI_MEM_BASE, + .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM +}; + +static struct pci_controller ar71xx_pci_controller = { + .pci_ops = &ar71xx_pci_ops, + .mem_resource = &ar71xx_pci_mem_resource, + .io_resource = &ar71xx_pci_io_resource, +}; + +static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *base = ath79_reset_base; + u32 pending; + + pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & + __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); + + if (pending & AR71XX_PCI_INT_DEV0) + generic_handle_irq(ATH79_PCI_IRQ(0)); + + else if (pending & AR71XX_PCI_INT_DEV1) + generic_handle_irq(ATH79_PCI_IRQ(1)); + + else if (pending & AR71XX_PCI_INT_DEV2) + generic_handle_irq(ATH79_PCI_IRQ(2)); + + else if (pending & AR71XX_PCI_INT_CORE) + generic_handle_irq(ATH79_PCI_IRQ(4)); + + else + spurious_interrupt(); +} + +static void ar71xx_pci_irq_unmask(struct irq_data *d) +{ + unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; + void __iomem *base = ath79_reset_base; + u32 t; + + t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); + __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); +} + +static void ar71xx_pci_irq_mask(struct irq_data *d) +{ + unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; + void __iomem *base = ath79_reset_base; + u32 t; + + t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); +} + +static struct irq_chip ar71xx_pci_irq_chip = { + .name = "AR71XX PCI", + .irq_mask = ar71xx_pci_irq_mask, + .irq_unmask = ar71xx_pci_irq_unmask, + .irq_mask_ack = ar71xx_pci_irq_mask, +}; + +static __init void ar71xx_pci_irq_init(void) +{ + void __iomem *base = ath79_reset_base; + int i; + + __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); + __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); + + BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); + + for (i = ATH79_PCI_IRQ_BASE; + i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, + handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler); +} + +static __init void ar71xx_pci_reset(void) +{ + void __iomem *ddr_base = ath79_ddr_base; + + ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); + mdelay(100); + + ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); + mdelay(100); + + __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); + __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); + __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); + __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); + __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); + __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); + __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); + __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); + + mdelay(100); +} + +__init int ar71xx_pcibios_init(void) +{ + u32 t; + + ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); + if (ar71xx_pcicfg_base == NULL) + return -ENOMEM; + + ar71xx_pci_reset(); + + /* setup COMMAND register */ + t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE + | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; + ar71xx_pci_local_write(PCI_COMMAND, 4, t); + + /* clear bus errors */ + ar71xx_pci_check_error(1); + + ar71xx_pci_irq_init(); + + register_pci_controller(&ar71xx_pci_controller); + + return 0; +} -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:30:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:33:53 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42668 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903713Ab2CNJa4 (ORCPT ); Wed, 14 Mar 2012 10:30:56 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 3600A23C00DD; Wed, 14 Mar 2012 10:00:09 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 07/12] MIPS: ath79: allow to use board specific pci_plat_dev_init functions Date: Wed, 14 Mar 2012 11:36:09 +0100 Message-Id: <1331721374-4144-8-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32688 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4585 Lines: 148 Th current implementation causes NULL pointer dereference if 'pci_data' is not set: pci 0000:00:00.0: BAR 0: assigned [mem 0x10000000-0x1000ffff 64bit] pci 0000:00:00.0: BAR 0: set to [mem 0x10000000-0x1000ffff 64bit] (PCI address [0x10000000-0x1000ffff]) CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 802daca0, ra == 802e78a4 Oops[#1]: Cpu 0 $ 0 : 00000000 80420000 00000000 00000000 $ 4 : 00000000 00000000 00000001 00000001 $ 8 : 00000001 0000032c 81c54700 00000001 $12 : 0000032d 0000000f 00000000 ffffffff $16 : 81c14c00 00000001 802dac74 80195f98 $20 : 802ea050 00000000 00000000 00000000 $24 : 00000003 800617f0 $28 : 81c20000 81c21e70 00000000 802e78a4 Hi : 00000000 Lo : 4190ab00 epc : 802daca0 0x802daca0 Not tainted ra : 802e78a4 0x802e78a4 Status: 1000c003 KERNEL EXL IE Cause : 00800008 BadVA : 00000000 PrId : 00019374 (MIPS 24Kc) Modules linked in: Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000) Stack : 00000000 8027d5d8 802e8ae0 00000000 01000000 802e8b5c 81c50600 00000000 802ff290 00000000 80420000 802ea0bc 00000000 00000000 80420000 802ff290 80420000 80060930 33390000 00000000 00002308 80140a80 00000028 802d0000 00000000 800ba024 802ff004 802ff0c8 802ff290 00000000 00000000 00000000 00000000 802d897c 01234567 7f827068 00000000 0045f798 00460000 00000000 This can be avoided by calling the 'ar724x_pci_add_data' function from the board specific setup code. However it makes no sense to use that function for every board, especially when the board does not needs to set the platform_data field of any PCI device. The patch allows the board setup code to specify a board specific function if that is required. Signed-off-by: Gabor Juhos --- v3: - no changes v2: - no changes The pci_irq_map function can throw another NULL pointer dereference, that will be fixed in a subsequent patch. arch/mips/ath79/mach-ubnt-xm.c | 13 ++++++++++++- arch/mips/ath79/pci.c | 14 ++++++++------ arch/mips/ath79/pci.h | 4 +++- 3 files changed, 23 insertions(+), 8 deletions(-) diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c index 1e6b986..ca47ba5 100644 --- a/arch/mips/ath79/mach-ubnt-xm.c +++ b/arch/mips/ath79/mach-ubnt-xm.c @@ -85,16 +85,27 @@ static struct ath9k_platform_data ubnt_xm_eeprom_data; static struct ar724x_pci_data ubnt_xm_pci_data[] = { { .irq = ATH79_PCI_IRQ(0), - .pdata = &ubnt_xm_eeprom_data, }, }; +static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 0: + dev->dev.platform_data = &ubnt_xm_eeprom_data; + break; + } + + return 0; +} + static void __init ubnt_xm_pci_init(void) { memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, sizeof(ubnt_xm_eeprom_data.eeprom_data)); ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); + ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); ath79_register_pci(); } #else diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 14f981c2..2b4c730 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -14,6 +14,7 @@ #include #include "pci.h" +static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); static struct ar724x_pci_data *pci_data; static int pci_data_size; @@ -38,14 +39,15 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) int pcibios_plat_dev_init(struct pci_dev *dev) { - unsigned int devfn = dev->devfn; - - if (devfn > pci_data_size - 1) - return PCIBIOS_DEVICE_NOT_FOUND; + if (ath79_pci_plat_dev_init) + return ath79_pci_plat_dev_init(dev); - dev->dev.platform_data = pci_data[devfn].pdata; + return 0; +} - return PCIBIOS_SUCCESSFUL; +void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) +{ + ath79_pci_plat_dev_init = func; } int __init ath79_register_pci(void) diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h index e0601c4..de30e15 100644 --- a/arch/mips/ath79/pci.h +++ b/arch/mips/ath79/pci.h @@ -13,14 +13,16 @@ struct ar724x_pci_data { int irq; - void *pdata; }; void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); #ifdef CONFIG_PCI +void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); int ath79_register_pci(void); #else +static inline void +ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} static inline int ath79_register_pci(void) { return 0; } #endif -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:31:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:34:17 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42702 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903726Ab2CNJbA (ORCPT ); Wed, 14 Mar 2012 10:31:00 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 9EFF623C00E3; Wed, 14 Mar 2012 10:00:09 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 09/12] MIPS: ath79: allow to use SoC specific PCI IRQ maps Date: Wed, 14 Mar 2012 11:36:11 +0100 Message-Id: <1331721374-4144-10-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32689 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4318 Lines: 166 The PCI controllers in the AR71XX and in the AR724X SoCs are different, and both of them uses different IRQ wiring. The patch modifies the 'pcibios_map_irq' function in order to allow to use different IRQ maps for the different SoCs. The patch also adds a function, which lets the board setup code to override the default IRQ map. Signed-off-by: Gabor Juhos --- v3: - no changes v2: - no changes arch/mips/ath79/pci.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++--- arch/mips/ath79/pci.h | 9 ++++++ 2 files changed, 77 insertions(+), 4 deletions(-) diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 2b4c730..365a8b6 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -8,6 +8,7 @@ * by the Free Software Foundation. */ +#include #include #include #include @@ -15,9 +16,35 @@ #include "pci.h" static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); +static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; +static unsigned ath79_pci_nr_irqs __initdata; static struct ar724x_pci_data *pci_data; static int pci_data_size; +static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { + { + .slot = 17, + .pin = 1, + .irq = ATH79_PCI_IRQ(0), + }, { + .slot = 18, + .pin = 1, + .irq = ATH79_PCI_IRQ(1), + }, { + .slot = 19, + .pin = 1, + .irq = ATH79_PCI_IRQ(2), + } +}; + +static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { + { + .slot = 0, + .pin = 1, + .irq = ATH79_PCI_IRQ(0), + } +}; + void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) { pci_data = data; @@ -26,13 +53,40 @@ void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) { - unsigned int devfn = dev->devfn; int irq = -1; + int i; + + if (ath79_pci_nr_irqs == 0 || + ath79_pci_irq_map == NULL) { + if (soc_is_ar71xx()) { + ath79_pci_irq_map = ar71xx_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); + } else if (soc_is_ar724x()) { + ath79_pci_irq_map = ar724x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); + } else { + pr_crit("pci %s: invalid irq map\n", + pci_name((struct pci_dev *) dev)); + return irq; + } + } + + for (i = 0; i < ath79_pci_nr_irqs; i++) { + const struct ath79_pci_irq *entry; - if (devfn > pci_data_size - 1) - return irq; + entry = &ath79_pci_irq_map[i]; + if (entry->slot == slot && entry->pin == pin) { + irq = entry->irq; + break; + } + } - irq = pci_data[devfn].irq; + if (irq < 0) + pr_crit("pci %s: no irq found for pin %u\n", + pci_name((struct pci_dev *) dev), pin); + else + pr_info("pci %s: using irq %d for pin %u\n", + pci_name((struct pci_dev *) dev), irq, pin); return irq; } @@ -45,6 +99,13 @@ int pcibios_plat_dev_init(struct pci_dev *dev) return 0; } +void __init ath79_pci_set_irq_map(unsigned nr_irqs, + const struct ath79_pci_irq *map) +{ + ath79_pci_nr_irqs = nr_irqs; + ath79_pci_irq_map = map; +} + void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) { ath79_pci_plat_dev_init = func; @@ -52,6 +113,9 @@ void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) int __init ath79_register_pci(void) { + if (soc_is_ar71xx()) + return ar71xx_pcibios_init(); + if (soc_is_ar724x()) return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h index de30e15..a5c4e58 100644 --- a/arch/mips/ath79/pci.h +++ b/arch/mips/ath79/pci.h @@ -15,13 +15,22 @@ struct ar724x_pci_data { int irq; }; +struct ath79_pci_irq { + u8 slot; + u8 pin; + int irq; +}; + void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); #ifdef CONFIG_PCI +void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); int ath79_register_pci(void); #else static inline void +ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {} +static inline void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} static inline int ath79_register_pci(void) { return 0; } #endif -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:31:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:34:41 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42716 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903727Ab2CNJbE (ORCPT ); Wed, 14 Mar 2012 10:31:04 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id BDBA123C00EE; Wed, 14 Mar 2012 10:00:09 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 10/12] MIPS: ath79: remove ar724x_pci_add_data function Date: Wed, 14 Mar 2012 11:36:12 +0100 Message-Id: <1331721374-4144-11-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32690 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2624 Lines: 90 The variables set by this function are not used anymore. Remove the function and the relevant variables as well. Signed-off-by: Gabor Juhos --- v3: - no changes v2: - no changes arch/mips/ath79/mach-ubnt-xm.c | 7 ------- arch/mips/ath79/pci.c | 8 -------- arch/mips/ath79/pci.h | 6 ------ 3 files changed, 0 insertions(+), 21 deletions(-) diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c index ca47ba5..4a3c606 100644 --- a/arch/mips/ath79/mach-ubnt-xm.c +++ b/arch/mips/ath79/mach-ubnt-xm.c @@ -82,12 +82,6 @@ static struct ath79_spi_platform_data ubnt_xm_spi_data = { #ifdef CONFIG_PCI static struct ath9k_platform_data ubnt_xm_eeprom_data; -static struct ar724x_pci_data ubnt_xm_pci_data[] = { - { - .irq = ATH79_PCI_IRQ(0), - }, -}; - static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) { switch (PCI_SLOT(dev->devfn)) { @@ -104,7 +98,6 @@ static void __init ubnt_xm_pci_init(void) memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, sizeof(ubnt_xm_eeprom_data.eeprom_data)); - ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); ath79_register_pci(); } diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 365a8b6..253a382 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -18,8 +18,6 @@ static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; static unsigned ath79_pci_nr_irqs __initdata; -static struct ar724x_pci_data *pci_data; -static int pci_data_size; static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { { @@ -45,12 +43,6 @@ static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { } }; -void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) -{ - pci_data = data; - pci_data_size = size; -} - int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) { int irq = -1; diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h index a5c4e58..5ebed21 100644 --- a/arch/mips/ath79/pci.h +++ b/arch/mips/ath79/pci.h @@ -11,18 +11,12 @@ #ifndef _ATH79_PCI_H #define _ATH79_PCI_H -struct ar724x_pci_data { - int irq; -}; - struct ath79_pci_irq { u8 slot; u8 pin; int irq; }; -void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); - #ifdef CONFIG_PCI void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:31:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:35:04 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42741 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903728Ab2CNJbJ (ORCPT ); Wed, 14 Mar 2012 10:31:09 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id DC82123C00EF; Wed, 14 Mar 2012 10:00:09 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org Subject: [PATCH v3 11/12] MIPS: ath79: register PCI controller on the PB44 board Date: Wed, 14 Mar 2012 11:36:13 +0100 Message-Id: <1331721374-4144-12-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32691 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 892 Lines: 34 The PB44 reference board has two miniPCI slots. Register the PCI controller to make those usable. Signed-off-by: Gabor Juhos --- v3: - no changes v2: - no changes arch/mips/ath79/mach-pb44.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index fe9701a..c5f0ea5 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -19,6 +19,7 @@ #include "dev-leds-gpio.h" #include "dev-spi.h" #include "dev-usb.h" +#include "pci.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 @@ -114,6 +115,7 @@ static void __init pb44_init(void) ath79_register_spi(&pb44_spi_data, pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); ath79_register_usb(); + ath79_register_pci(); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:31:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:35:28 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:42756 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903730Ab2CNJbL (ORCPT ); Wed, 14 Mar 2012 10:31:11 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 125E823C00CA; Wed, 14 Mar 2012 10:00:10 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, juhosg@openwrt.org, Imre Kaloz Subject: =?UTF-8?q?=5BPATCH=20v3=2012/12=5D=20MIPS=3A=20ath79=3A=20update=20copyright=20headers=20of=20PCI=20related=20files?= Date: Wed, 14 Mar 2012 11:36:14 +0100 Message-Id: <1331721374-4144-13-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> References: <1331721374-4144-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32692 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3143 Lines: 84 Add copyright records according to the recent changes in the PCI code. Also fix up the descriptions. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Just in case if someone is curious about why 2008 and 2009 years are present in this change: The recent PCI specific changes were based on an existing code which can be found in the OpenWrt repository, and we are working on that since 2008. --- v3: - no changes v2: - no changes arch/mips/ath79/pci.c | 4 ++++ arch/mips/ath79/pci.h | 4 +++- arch/mips/include/asm/mach-ath79/pci.h | 4 +++- arch/mips/pci/pci-ar724x.c | 3 ++- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 253a382..bc40070 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -2,6 +2,10 @@ * Atheros AR71XX/AR724X specific PCI setup code * * Copyright (C) 2011 René Bolldorf + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h index 5ebed21..51c6625 100644 --- a/arch/mips/ath79/pci.h +++ b/arch/mips/ath79/pci.h @@ -1,7 +1,9 @@ /* - * Atheros 724x PCI support + * Atheros AR71XX/AR724X PCI support * * Copyright (C) 2011 René Bolldorf + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h index b12b087..4f2222d 100644 --- a/arch/mips/include/asm/mach-ath79/pci.h +++ b/arch/mips/include/asm/mach-ath79/pci.h @@ -1,7 +1,9 @@ /* - * Atheros 724x PCI support + * Atheros AR71XX/AR724X PCI support * * Copyright (C) 2011 René Bolldorf + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 04f433a..414a745 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -1,7 +1,8 @@ /* - * Atheros 724x PCI support + * Atheros AR724X PCI host controller driver * * Copyright (C) 2011 René Bolldorf + * Copyright (C) 2009-2011 Gabor Juhos * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:40:08 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34292 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903727Ab2CNJkB (ORCPT ); Wed, 14 Mar 2012 10:40:01 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 29D4F23C00C4; Wed, 14 Mar 2012 10:09:30 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 01/13] MIPS: ath79: add early_printk support for AR934X Date: Wed, 14 Mar 2012 11:45:19 +0100 Message-Id: <1331721931-4334-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32693 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1968 Lines: 56 The patch allows to see kernel messages on AR934X SoCs in early boot stage. Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/early_printk.c | 3 +++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 6 +++++- 2 files changed, 8 insertions(+), 1 deletions(-) diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c index 6a51ced..dc938cb 100644 --- a/arch/mips/ath79/early_printk.c +++ b/arch/mips/ath79/early_printk.c @@ -71,6 +71,9 @@ static void prom_putchar_init(void) case REV_ID_MAJOR_AR7241: case REV_ID_MAJOR_AR7242: case REV_ID_MAJOR_AR913X: + case REV_ID_MAJOR_AR9341: + case REV_ID_MAJOR_AR9342: + case REV_ID_MAJOR_AR9344: _prom_putchar = prom_putchar_ar71xx; break; diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 2f0becb..b7df674 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -1,10 +1,11 @@ /* * Atheros AR71XX/AR724X/AR913X SoC register definitions * + * Copyright (C) 2010-2011 Jaiganesh Narayanan * Copyright (C) 2008-2010 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -249,6 +250,9 @@ #define REV_ID_MAJOR_AR7242 0x1100 #define REV_ID_MAJOR_AR9330 0x0110 #define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 #define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_AR7130 0x0 -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:40:32 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34303 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903729Ab2CNJkC (ORCPT ); Wed, 14 Mar 2012 10:40:02 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id DEB4223C00C1; Wed, 14 Mar 2012 10:09:29 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 00/13] MIPS: ath79: add initial support for the Atheros AR934X SoCs Date: Wed, 14 Mar 2012 11:45:18 +0100 Message-Id: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 32694 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2318 Lines: 50 This patch set adds initial support for the Atheros AR934X SoCs. This depends on the following patch set: v3 of 'MIPS: ath79: AR724X PCI fixes and AR71XX PCI support' Changes since v1: - the watchdog related patch is removed because that is in in upstream already - the USB support is removed, it will be reintroduced by a separate series Gabor Juhos (13): MIPS: ath79: add early_printk support for AR934X MIPS: ath79: sort case statements in ath79_detect_sys_type MIPS: ath79: add SoC detection code for AR934X MIPS: ath79: add clock initialization code for AR934X MIPS: ath79: add GPIO support code for AR934X MIPS: ath79: rework IP2/IP3 interrupt handling MIPS: ath79: add IRQ handling code for AR934X MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set} MIPS: ath79: register UART device for AR934X SoCs MIPS: ath79: add WMAC registration code for AR934X MIPS: ath79: add PCI_AR724X Kconfig symbol MIPS: ath79: add PCI registration code for AR934X MIPS: ath79: add initial support for the Atheros DB120 board arch/mips/ath79/Kconfig | 24 ++++- arch/mips/ath79/Makefile | 1 + arch/mips/ath79/clock.c | 81 +++++++++++++ arch/mips/ath79/common.c | 9 ++- arch/mips/ath79/dev-common.c | 3 +- arch/mips/ath79/dev-wmac.c | 30 +++++- arch/mips/ath79/early_printk.c | 3 + arch/mips/ath79/gpio.c | 47 +++++++- arch/mips/ath79/irq.c | 147 +++++++++++++++++++---- arch/mips/ath79/mach-db120.c | 153 ++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + arch/mips/ath79/pci.c | 13 ++- arch/mips/ath79/setup.c | 45 +++++-- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 91 ++++++++++++++- arch/mips/include/asm/mach-ath79/ath79.h | 23 ++++ arch/mips/include/asm/mach-ath79/irq.h | 6 +- arch/mips/include/asm/mach-ath79/pci.h | 2 +- arch/mips/pci/Makefile | 2 +- 18 files changed, 635 insertions(+), 46 deletions(-) create mode 100644 arch/mips/ath79/mach-db120.c -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:40:54 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34322 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903730Ab2CNJkG (ORCPT ); Wed, 14 Mar 2012 10:40:06 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 553C723C00C9; Wed, 14 Mar 2012 10:09:30 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 02/13] MIPS: ath79: sort case statements in ath79_detect_sys_type Date: Wed, 14 Mar 2012 11:45:20 +0100 Message-Id: <1331721931-4334-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32695 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1395 Lines: 56 Sort the case statements alphabetically in order to improve readability. Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/setup.c | 24 ++++++++++++------------ 1 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 80a7d40..24dfedf 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -116,18 +116,6 @@ static void __init ath79_detect_sys_type(void) rev = id & AR724X_REV_ID_REVISION_MASK; break; - case REV_ID_MAJOR_AR9330: - ath79_soc = ATH79_SOC_AR9330; - chip = "9330"; - rev = id & AR933X_REV_ID_REVISION_MASK; - break; - - case REV_ID_MAJOR_AR9331: - ath79_soc = ATH79_SOC_AR9331; - chip = "9331"; - rev = id & AR933X_REV_ID_REVISION_MASK; - break; - case REV_ID_MAJOR_AR913X: minor = id & AR913X_REV_ID_MINOR_MASK; rev = id >> AR913X_REV_ID_REVISION_SHIFT; @@ -145,6 +133,18 @@ static void __init ath79_detect_sys_type(void) } break; + case REV_ID_MAJOR_AR9330: + ath79_soc = ATH79_SOC_AR9330; + chip = "9330"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9331: + ath79_soc = ATH79_SOC_AR9331; + chip = "9331"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + default: panic("ath79: unknown SoC, id:0x%08x", id); } -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:41:21 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34334 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903731Ab2CNJkH (ORCPT ); Wed, 14 Mar 2012 10:40:07 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 82AC723C00CA; Wed, 14 Mar 2012 10:09:30 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 03/13] MIPS: ath79: add SoC detection code for AR934X Date: Wed, 14 Mar 2012 11:45:21 +0100 Message-Id: <1331721931-4334-4-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32696 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3579 Lines: 128 Also add 'soc_is_ar934[124x]' helper functions and a Kconfig symbol for the AR934X SoCs. Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/Kconfig | 4 ++++ arch/mips/ath79/setup.c | 21 ++++++++++++++++++++- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++ 4 files changed, 49 insertions(+), 1 deletions(-) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index bc6edad..7db8e89 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -69,6 +69,10 @@ config SOC_AR933X select USB_ARCH_HAS_EHCI def_bool n +config SOC_AR934X + select USB_ARCH_HAS_EHCI + def_bool n + config ATH79_DEV_GPIO_BUTTONS def_bool n diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 24dfedf..60d212e 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -1,10 +1,11 @@ /* * Atheros AR71XX/AR724X/AR913X specific setup * + * Copyright (C) 2010-2011 Jaiganesh Narayanan * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type(void) rev = id & AR933X_REV_ID_REVISION_MASK; break; + case REV_ID_MAJOR_AR9341: + ath79_soc = ATH79_SOC_AR9341; + chip = "9341"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9342: + ath79_soc = ATH79_SOC_AR9342; + chip = "9342"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9344: + ath79_soc = ATH79_SOC_AR9344; + chip = "9344"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + default: panic("ath79: unknown SoC, id:0x%08x", id); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index b7df674..4e3c55d 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -271,6 +271,8 @@ #define AR724X_REV_ID_REVISION_MASK 0x3 +#define AR934X_REV_ID_REVISION_MASK 0xf + /* * SPI block */ diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h index 6d0c6c9..4f248c3 100644 --- a/arch/mips/include/asm/mach-ath79/ath79.h +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -29,6 +29,9 @@ enum ath79_soc_type { ATH79_SOC_AR9132, ATH79_SOC_AR9330, ATH79_SOC_AR9331, + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, }; extern enum ath79_soc_type ath79_soc; @@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void) ath79_soc == ATH79_SOC_AR9331); } +static inline int soc_is_ar9341(void) +{ + return (ath79_soc == ATH79_SOC_AR9341); +} + +static inline int soc_is_ar9342(void) +{ + return (ath79_soc == ATH79_SOC_AR9342); +} + +static inline int soc_is_ar9344(void) +{ + return (ath79_soc == ATH79_SOC_AR9344); +} + +static inline int soc_is_ar934x(void) +{ + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); +} + extern void __iomem *ath79_ddr_base; extern void __iomem *ath79_pll_base; extern void __iomem *ath79_reset_base; -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:41:46 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34357 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903728Ab2CNJkL (ORCPT ); Wed, 14 Mar 2012 10:40:11 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id A8CB223C00CC; Wed, 14 Mar 2012 10:09:30 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 04/13] MIPS: ath79: add clock initialization code for AR934X Date: Wed, 14 Mar 2012 11:45:22 +0100 Message-Id: <1331721931-4334-5-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32697 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7359 Lines: 198 Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++ 2 files changed, 134 insertions(+), 0 deletions(-) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index 54d0eb4..b91ad3e 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -1,8 +1,11 @@ /* * Atheros AR71XX/AR724X/AR913X common routines * + * Copyright (C) 2010-2011 Jaiganesh Narayanan * Copyright (C) 2011 Gabor Juhos * + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation. @@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(void) ath79_uart_clk.rate = ath79_ref_clk.rate; } +static void __init ar934x_clocks_init(void) +{ + u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; + u32 cpu_pll, ddr_pll; + u32 bootstrap; + + bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); + if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) + ath79_ref_clk.rate = 40 * 1000 * 1000; + else + ath79_ref_clk.rate = 25 * 1000 * 1000; + + pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); + out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; + ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_REFDIV_MASK; + nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & + AR934X_PLL_CPU_CONFIG_NINT_MASK; + frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_CPU_CONFIG_NFRAC_MASK; + + cpu_pll = nint * ath79_ref_clk.rate / ref_div; + cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); + cpu_pll /= (1 << out_div); + + pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); + out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; + ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_REFDIV_MASK; + nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & + AR934X_PLL_DDR_CONFIG_NINT_MASK; + frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_DDR_CONFIG_NFRAC_MASK; + + ddr_pll = nint * ath79_ref_clk.rate / ref_div; + ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); + ddr_pll /= (1 << out_div); + + clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); + + postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & + AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; + + if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) + ath79_cpu_clk.rate = ath79_ref_clk.rate; + else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) + ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); + else + ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & + AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; + + if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) + ath79_ddr_clk.rate = ath79_ref_clk.rate; + else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) + ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); + else + ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & + AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; + + if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) + ath79_ahb_clk.rate = ath79_ref_clk.rate; + else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) + ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); + else + ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); + + ath79_wdt_clk.rate = ath79_ref_clk.rate; + ath79_uart_clk.rate = ath79_ref_clk.rate; +} + void __init ath79_clocks_init(void) { if (soc_is_ar71xx()) @@ -173,6 +252,8 @@ void __init ath79_clocks_init(void) ar913x_clocks_init(); else if (soc_is_ar933x()) ar933x_clocks_init(); + else if (soc_is_ar934x()) + ar934x_clocks_init(); else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 4e3c55d..bc1c345 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -151,6 +151,41 @@ #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + /* * USB_CONFIG block */ @@ -186,6 +221,8 @@ #define AR933X_RESET_REG_RESET_MODULE 0x1c #define AR933X_RESET_REG_BOOTSTRAP 0xac +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 + #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) #define MISC_INT_TIMER3 BIT(9) @@ -242,6 +279,22 @@ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + #define REV_ID_MAJOR_MASK 0xfff0 #define REV_ID_MAJOR_AR71XX 0x00a0 #define REV_ID_MAJOR_AR913X 0x00b0 -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:42:09 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34363 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903733Ab2CNJkM (ORCPT ); Wed, 14 Mar 2012 10:40:12 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id DE93923C00D5; Wed, 14 Mar 2012 10:09:30 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 05/13] MIPS: ath79: add GPIO support code for AR934X Date: Wed, 14 Mar 2012 11:45:23 +0100 Message-Id: <1331721931-4334-6-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32698 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3196 Lines: 102 Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + 2 files changed, 47 insertions(+), 1 deletions(-) diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c index a2f8ca6..29054f2 100644 --- a/arch/mips/ath79/gpio.c +++ b/arch/mips/ath79/gpio.c @@ -1,9 +1,12 @@ /* * Atheros AR71XX/AR724X/AR913X GPIO API support * - * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation. @@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(struct gpio_chip *chip, return 0; } +static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + +static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + if (value) + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + static struct gpio_chip ath79_gpio_chip = { .label = "ath79", .get = ath79_gpio_get_value, @@ -155,11 +194,17 @@ void __init ath79_gpio_init(void) ath79_gpio_count = AR913X_GPIO_COUNT; else if (soc_is_ar933x()) ath79_gpio_count = AR933X_GPIO_COUNT; + else if (soc_is_ar934x()) + ath79_gpio_count = AR934X_GPIO_COUNT; else BUG(); ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); ath79_gpio_chip.ngpio = ath79_gpio_count; + if (soc_is_ar934x()) { + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; + } err = gpiochip_add(&ath79_gpio_chip); if (err) diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index bc1c345..1a9234b 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -367,5 +367,6 @@ #define AR724X_GPIO_COUNT 18 #define AR913X_GPIO_COUNT 22 #define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 #endif /* __ASM_MACH_AR71XX_REGS_H */ -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:42:32 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34383 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903734Ab2CNJkN (ORCPT ); Wed, 14 Mar 2012 10:40:13 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 2EB2523C00D6; Wed, 14 Mar 2012 10:09:31 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 06/13] MIPS: ath79: rework IP2/IP3 interrupt handling Date: Wed, 14 Mar 2012 11:45:24 +0100 Message-Id: <1331721931-4334-7-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32699 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4435 Lines: 156 The current implementation assumes that flushing the DDR writeback buffer is required for IP2/IP3 interrupts, however this is not true for all SoCs. Use SoC specific IP2/IP3 handlers instead of flushing the buffers in the dispatcher code. Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/irq.c | 92 ++++++++++++++++++++++++++++++++++++++----------- 1 files changed, 72 insertions(+), 20 deletions(-) diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index 1b073de..9f87ade 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -1,7 +1,7 @@ /* * Atheros AR71xx/AR724x/AR913x specific interrupt handling * - * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * * Parts of this file are based on Atheros' 2.6.15 BSP @@ -23,8 +23,8 @@ #include #include "common.h" -static unsigned int ath79_ip2_flush_reg; -static unsigned int ath79_ip3_flush_reg; +static void (*ath79_ip2_handler)(void); +static void (*ath79_ip3_handler)(void); static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) { @@ -152,10 +152,8 @@ asmlinkage void plat_irq_dispatch(void) if (pending & STATUSF_IP7) do_IRQ(ATH79_CPU_IRQ_TIMER); - else if (pending & STATUSF_IP2) { - ath79_ddr_wb_flush(ath79_ip2_flush_reg); - do_IRQ(ATH79_CPU_IRQ_IP2); - } + else if (pending & STATUSF_IP2) + ath79_ip2_handler(); else if (pending & STATUSF_IP4) do_IRQ(ATH79_CPU_IRQ_GE0); @@ -163,10 +161,8 @@ asmlinkage void plat_irq_dispatch(void) else if (pending & STATUSF_IP5) do_IRQ(ATH79_CPU_IRQ_GE1); - else if (pending & STATUSF_IP3) { - ath79_ddr_wb_flush(ath79_ip3_flush_reg); - do_IRQ(ATH79_CPU_IRQ_USB); - } + else if (pending & STATUSF_IP3) + ath79_ip3_handler(); else if (pending & STATUSF_IP6) do_IRQ(ATH79_CPU_IRQ_MISC); @@ -175,22 +171,78 @@ asmlinkage void plat_irq_dispatch(void) spurious_interrupt(); } +/* + * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for + * these devices typically allocate coherent DMA memory, however the + * DMA controller may still have some unsynchronized data in the FIFO. + * Issue a flush in the handlers to ensure that the driver sees + * the update. + */ +static void ar71xx_ip2_handler(void) +{ + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); + do_IRQ(ATH79_CPU_IRQ_IP2); +} + +static void ar724x_ip2_handler(void) +{ + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); + do_IRQ(ATH79_CPU_IRQ_IP2); +} + +static void ar913x_ip2_handler(void) +{ + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); + do_IRQ(ATH79_CPU_IRQ_IP2); +} + +static void ar933x_ip2_handler(void) +{ + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); + do_IRQ(ATH79_CPU_IRQ_IP2); +} + +static void ar71xx_ip3_handler(void) +{ + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); + do_IRQ(ATH79_CPU_IRQ_USB); +} + +static void ar724x_ip3_handler(void) +{ + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); + do_IRQ(ATH79_CPU_IRQ_USB); +} + +static void ar913x_ip3_handler(void) +{ + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); + do_IRQ(ATH79_CPU_IRQ_USB); +} + +static void ar933x_ip3_handler(void) +{ + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); + do_IRQ(ATH79_CPU_IRQ_USB); +} + void __init arch_init_irq(void) { if (soc_is_ar71xx()) { - ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; - ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB; + ath79_ip2_handler = ar71xx_ip2_handler; + ath79_ip3_handler = ar71xx_ip3_handler; } else if (soc_is_ar724x()) { - ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; - ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB; + ath79_ip2_handler = ar724x_ip2_handler; + ath79_ip3_handler = ar724x_ip3_handler; } else if (soc_is_ar913x()) { - ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; - ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; + ath79_ip2_handler = ar913x_ip2_handler; + ath79_ip3_handler = ar913x_ip3_handler; } else if (soc_is_ar933x()) { - ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC; - ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB; - } else + ath79_ip2_handler = ar933x_ip2_handler; + ath79_ip3_handler = ar933x_ip3_handler; + } else { BUG(); + } cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; mips_cpu_irq_init(); -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:42:59 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34420 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903735Ab2CNJkT (ORCPT ); Wed, 14 Mar 2012 10:40:19 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 6372423C00D9; Wed, 14 Mar 2012 10:09:31 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 07/13] MIPS: ath79: add IRQ handling code for AR934X Date: Wed, 14 Mar 2012 11:45:25 +0100 Message-Id: <1331721931-4334-8-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32700 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6205 Lines: 196 Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++ arch/mips/include/asm/mach-ath79/irq.h | 6 ++- 3 files changed, 83 insertions(+), 3 deletions(-) diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index 9f87ade..90d09fc 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -1,10 +1,11 @@ /* * Atheros AR71xx/AR724x/AR913x specific interrupt handling * + * Copyright (C) 2010-2011 Jaiganesh Narayanan * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(void) if (soc_is_ar71xx() || soc_is_ar913x()) ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; - else if (soc_is_ar724x() || soc_is_ar933x()) + else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; else BUG(); @@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(void) irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); } +static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) +{ + u32 status; + + disable_irq_nosync(irq); + + status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); + + if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { + ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE); + generic_handle_irq(ATH79_IP2_IRQ(0)); + } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { + ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC); + generic_handle_irq(ATH79_IP2_IRQ(1)); + } else { + spurious_interrupt(); + } + + enable_irq(irq); +} + +static void ar934x_ip2_irq_init(void) +{ + int i; + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &dummy_irq_chip, + handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); +} + asmlinkage void plat_irq_dispatch(void) { unsigned long pending; @@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void) do_IRQ(ATH79_CPU_IRQ_IP2); } +static void ar934x_ip2_handler(void) +{ + do_IRQ(ATH79_CPU_IRQ_IP2); +} + static void ar71xx_ip3_handler(void) { ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); @@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void) do_IRQ(ATH79_CPU_IRQ_USB); } +static void ar934x_ip3_handler(void) +{ + ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB); + do_IRQ(ATH79_CPU_IRQ_USB); +} + void __init arch_init_irq(void) { if (soc_is_ar71xx()) { @@ -240,6 +285,9 @@ void __init arch_init_irq(void) } else if (soc_is_ar933x()) { ath79_ip2_handler = ar933x_ip2_handler; ath79_ip3_handler = ar933x_ip3_handler; + } else if (soc_is_ar934x()) { + ath79_ip2_handler = ar934x_ip2_handler; + ath79_ip3_handler = ar934x_ip3_handler; } else { BUG(); } @@ -247,4 +295,7 @@ void __init arch_init_irq(void) cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; mips_cpu_irq_init(); ath79_misc_irq_init(); + + if (soc_is_ar934x()) + ar934x_ip2_irq_init(); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 1a9234b..d6af4eb 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -92,6 +92,12 @@ #define AR933X_DDR_REG_FLUSH_USB 0x84 #define AR933X_DDR_REG_FLUSH_WMAC 0x88 +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + /* * PLL block */ @@ -222,6 +228,7 @@ #define AR933X_RESET_REG_BOOTSTRAP 0xac #define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) @@ -295,6 +302,24 @@ #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) #define AR934X_BOOTSTRAP_DDR1 BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + #define REV_ID_MAJOR_MASK 0xfff0 #define REV_ID_MAJOR_AR71XX 0x00a0 #define REV_ID_MAJOR_AR913X 0x00b0 diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 6ae2646..0968f69 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -10,7 +10,7 @@ #define __ASM_MACH_ATH79_IRQ_H #define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 46 +#define NR_IRQS 48 #define ATH79_MISC_IRQ_BASE 8 #define ATH79_MISC_IRQ_COUNT 32 @@ -19,6 +19,10 @@ #define ATH79_PCI_IRQ_COUNT 6 #define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x)) +#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT) +#define ATH79_IP2_IRQ_COUNT 2 +#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) + #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:43:23 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34432 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903736Ab2CNJkV (ORCPT ); Wed, 14 Mar 2012 10:40:21 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 90DA523C00DA; Wed, 14 Mar 2012 10:09:31 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 08/13] MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set} Date: Wed, 14 Mar 2012 11:45:26 +0100 Message-Id: <1331721931-4334-9-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32701 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2059 Lines: 60 Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/common.c | 9 ++++++++- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + 2 files changed, 9 insertions(+), 1 deletions(-) diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c index f0fda98..5a4adfc 100644 --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c @@ -1,9 +1,12 @@ /* * Atheros AR71XX/AR724X/AR913X common routines * - * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation. @@ -67,6 +70,8 @@ void ath79_device_reset_set(u32 mask) reg = AR913X_RESET_REG_RESET_MODULE; else if (soc_is_ar933x()) reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; else BUG(); @@ -91,6 +96,8 @@ void ath79_device_reset_clear(u32 mask) reg = AR913X_RESET_REG_RESET_MODULE; else if (soc_is_ar933x()) reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index d6af4eb..32abbf9 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -227,6 +227,7 @@ #define AR933X_RESET_REG_RESET_MODULE 0x1c #define AR933X_RESET_REG_BOOTSTRAP 0xac +#define AR934X_RESET_REG_RESET_MODULE 0x1c #define AR934X_RESET_REG_BOOTSTRAP 0xb0 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:43:48 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34460 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903727Ab2CNJk0 (ORCPT ); Wed, 14 Mar 2012 10:40:26 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id C231023C00DD; Wed, 14 Mar 2012 10:09:31 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 09/13] MIPS: ath79: register UART device for AR934X SoCs Date: Wed, 14 Mar 2012 11:45:27 +0100 Message-Id: <1331721931-4334-10-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32702 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 717 Lines: 25 Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/dev-common.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c index f4956f8..45efc63 100644 --- a/arch/mips/ath79/dev-common.c +++ b/arch/mips/ath79/dev-common.c @@ -89,7 +89,8 @@ void __init ath79_register_uart(void) if (soc_is_ar71xx() || soc_is_ar724x() || - soc_is_ar913x()) { + soc_is_ar913x() || + soc_is_ar934x()) { ath79_uart_data[0].uartclk = clk_get_rate(clk); platform_device_register(&ath79_uart_device); } else if (soc_is_ar933x()) { -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:44:12 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34471 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903740Ab2CNJk3 (ORCPT ); Wed, 14 Mar 2012 10:40:29 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id EB33323C00E0; Wed, 14 Mar 2012 10:09:31 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 10/13] MIPS: ath79: add WMAC registration code for AR934X Date: Wed, 14 Mar 2012 11:45:28 +0100 Message-Id: <1331721931-4334-11-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32703 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3733 Lines: 118 Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/Kconfig | 2 +- arch/mips/ath79/dev-wmac.c | 30 ++++++++++++++++++++++- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++ 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 7db8e89..5fa3d7b 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -86,7 +86,7 @@ config ATH79_DEV_USB def_bool n config ATH79_DEV_WMAC - depends on (SOC_AR913X || SOC_AR933X) + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) def_bool n endif diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c index 9c717bf..d6d893c 100644 --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c @@ -1,9 +1,12 @@ /* * Atheros AR913X/AR933X SoC built-in WMAC device support * + * Copyright (C) 2010-2011 Jaiganesh Narayanan * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * + * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation. @@ -26,8 +29,7 @@ static struct resource ath79_wmac_resources[] = { /* .start and .end fields are filled dynamically */ .flags = IORESOURCE_MEM, }, { - .start = ATH79_CPU_IRQ_IP2, - .end = ATH79_CPU_IRQ_IP2, + /* .start and .end fields are filled dynamically */ .flags = IORESOURCE_IRQ, }, }; @@ -53,6 +55,8 @@ static void __init ar913x_wmac_setup(void) ath79_wmac_resources[0].start = AR913X_WMAC_BASE; ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; + ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; + ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; } @@ -79,6 +83,8 @@ static void __init ar933x_wmac_setup(void) ath79_wmac_resources[0].start = AR933X_WMAC_BASE; ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; + ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; + ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); if (t & AR933X_BOOTSTRAP_REF_CLK_40) @@ -92,12 +98,32 @@ static void __init ar933x_wmac_setup(void) ath79_wmac_data.external_reset = ar933x_wmac_reset; } +static void ar934x_wmac_setup(void) +{ + u32 t; + + ath79_wmac_device.name = "ar934x_wmac"; + + ath79_wmac_resources[0].start = AR934X_WMAC_BASE; + ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); + + t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); + if (t & AR934X_BOOTSTRAP_REF_CLK_40) + ath79_wmac_data.is_clk_25mhz = false; + else + ath79_wmac_data.is_clk_25mhz = true; +} + void __init ath79_register_wmac(u8 *cal_data) { if (soc_is_ar913x()) ar913x_wmac_setup(); else if (soc_is_ar933x()) ar933x_wmac_setup(); + else if (soc_is_ar934x()) + ar934x_wmac_setup(); else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 32abbf9..1caa78a 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -61,6 +61,9 @@ #define AR933X_EHCI_BASE 0x1b000000 #define AR933X_EHCI_SIZE 0x1000 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 + /* * DDR_CTRL block */ -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:44:36 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34510 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903742Ab2CNJkc (ORCPT ); Wed, 14 Mar 2012 10:40:32 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 38FDB23C00E3; Wed, 14 Mar 2012 10:09:32 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 11/13] MIPS: ath79: add PCI_AR724X Kconfig symbol Date: Wed, 14 Mar 2012 11:45:29 +0100 Message-Id: <1331721931-4334-12-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32704 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2067 Lines: 68 The AR724X specific PCI code can be used for the AR934X SoCs, however it can be selected only if SOC_AR724X is set. Introduce a new Kconfig symbol in order to be able to use the code for AR934X as well. Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - update due to changes in a previous patch arch/mips/ath79/Kconfig | 4 ++++ arch/mips/include/asm/mach-ath79/pci.h | 2 +- arch/mips/pci/Makefile | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 5fa3d7b..123cc37 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -59,6 +59,7 @@ config SOC_AR724X select USB_ARCH_HAS_EHCI select USB_ARCH_HAS_OHCI select HW_HAS_PCI + select PCI_AR724X if PCI def_bool n config SOC_AR913X @@ -73,6 +74,9 @@ config SOC_AR934X select USB_ARCH_HAS_EHCI def_bool n +config PCI_AR724X + def_bool n + config ATH79_DEV_GPIO_BUTTONS def_bool n diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h index 4f2222d..7868f7f 100644 --- a/arch/mips/include/asm/mach-ath79/pci.h +++ b/arch/mips/include/asm/mach-ath79/pci.h @@ -19,7 +19,7 @@ int ar71xx_pcibios_init(void); static inline int ar71xx_pcibios_init(void) { return 0; } #endif -#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) +#if defined(CONFIG_PCI_AR724X) int ar724x_pcibios_init(int irq); #else static inline int ar724x_pcibios_init(int irq) { return 0; } diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index b1c0a1c..43c5138 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ ops-bcm63xx.o obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o -obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o +obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o # # These are still pretty much in the old state, watch, go blind. -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:44:58 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34533 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903744Ab2CNJkk (ORCPT ); Wed, 14 Mar 2012 10:40:40 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 8F84423C00EF; Wed, 14 Mar 2012 10:09:32 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 13/13] MIPS: ath79: add initial support for the Atheros DB120 board Date: Wed, 14 Mar 2012 11:45:31 +0100 Message-Id: <1331721931-4334-14-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32705 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7476 Lines: 237 Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - remove USB controller registration, it will be added by a separate patch-set Ralf, The mach-db120.c file is licensed under the Clear BSD license. That is based on the modified BSD license and the FSF's [1] site states that it is compatible with both the GPLv2 and GPLv3. However if you have concerns about the copyright we can resubmit this file under the ISC license [2]. The ISC license is already used upstream by the ath6kl and ath9k drivers. Thanks, Gabor 1. http://www.gnu.org/licenses/license-list.html#clearbsd 2. http://www.gnu.org/licenses/license-list.html#ISC arch/mips/ath79/Kconfig | 12 +++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/mach-db120.c | 153 ++++++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + 4 files changed, 167 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/mach-db120.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index ea28e89..f44feee 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -26,6 +26,18 @@ config ATH79_MACH_AP81 Say 'Y' here if you want your kernel to support the Atheros AP81 reference board. +config ATH79_MACH_DB120 + bool "Atheros DB120 reference board" + select SOC_AR934X + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help + Say 'Y' here if you want your kernel to support the + Atheros DB120 reference board. + config ATH79_MACH_PB44 bool "Atheros PB44 reference board" select SOC_AR71XX diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 221a76a9..2b54d98 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -28,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o # obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o +obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o diff --git a/arch/mips/ath79/mach-db120.c b/arch/mips/ath79/mach-db120.c new file mode 100644 index 0000000..9370f14 --- /dev/null +++ b/arch/mips/ath79/mach-db120.c @@ -0,0 +1,153 @@ +/* + * Atheros DB120 reference board support + * + * Copyright (c) 2011 Qualcomm Atheros + * Copyright (c) 2011 Gabor Juhos + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of Qualcomm Atheros nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "machtypes.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "pci.h" + +#define DB120_GPIO_LED_WLAN_5G 12 +#define DB120_GPIO_LED_WLAN_2G 13 +#define DB120_GPIO_LED_STATUS 14 +#define DB120_GPIO_LED_WPS 15 + +#define DB120_GPIO_BTN_WPS 16 + +#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) + +#define DB120_WMAC_CALDATA_OFFSET 0x1000 +#define DB120_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led db120_leds_gpio[] __initdata = { + { + .name = "db120:green:status", + .gpio = DB120_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "db120:green:wps", + .gpio = DB120_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "db120:green:wlan-5g", + .gpio = DB120_GPIO_LED_WLAN_5G, + .active_low = 1, + }, + { + .name = "db120:green:wlan-2g", + .gpio = DB120_GPIO_LED_WLAN_2G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button db120_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, + .gpio = DB120_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct spi_board_info db120_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "s25sl064a", + } +}; + +static struct ath79_spi_platform_data db120_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + +#ifdef CONFIG_PCI +static struct ath9k_platform_data db120_ath9k_data; + +static int db120_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 0: + dev->dev.platform_data = &db120_ath9k_data; + break; + } + + return 0; +} + +static void __init db120_pci_init(u8 *eeprom) +{ + memcpy(db120_ath9k_data.eeprom_data, eeprom, + sizeof(db120_ath9k_data.eeprom_data)); + + ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); + ath79_register_pci(); +} +#else +static inline void db120_pci_init(void) {} +#endif /* CONFIG_PCI */ + +static void __init db120_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), + db120_leds_gpio); + ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, + ARRAY_SIZE(db120_gpio_keys), + db120_gpio_keys); + ath79_register_spi(&db120_spi_data, db120_spi_info, + ARRAY_SIZE(db120_spi_info)); + ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); + db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", + db120_setup); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index 9a1f382..af92e5c 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -18,6 +18,7 @@ enum ath79_mach_type { ATH79_MACH_GENERIC = 0, ATH79_MACH_AP121, /* Atheros AP121 reference board */ ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ ATH79_MACH_PB44, /* Atheros PB44 reference board */ ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ }; -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 10:40:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 10:45:23 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34541 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903745Ab2CNJkl (ORCPT ); Wed, 14 Mar 2012 10:40:41 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 67DB623C00EE; Wed, 14 Mar 2012 10:09:32 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2 12/13] MIPS: ath79: add PCI registration code for AR934X Date: Wed, 14 Mar 2012 11:45:30 +0100 Message-Id: <1331721931-4334-13-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> X-archive-position: 32706 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1776 Lines: 62 Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2: - no changes arch/mips/ath79/Kconfig | 2 ++ arch/mips/ath79/pci.c | 13 ++++++++++++- 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 123cc37..ea28e89 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -72,6 +72,8 @@ config SOC_AR933X config SOC_AR934X select USB_ARCH_HAS_EHCI + select HW_HAS_PCI + select PCI_AR724X if PCI def_bool n config PCI_AR724X diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index bc40070..ca83abd 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) if (soc_is_ar71xx()) { ath79_pci_irq_map = ar71xx_pci_irq_map; ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); - } else if (soc_is_ar724x()) { + } else if (soc_is_ar724x() || + soc_is_ar9342() || + soc_is_ar9344()) { ath79_pci_irq_map = ar724x_pci_irq_map; ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); } else { @@ -115,5 +118,13 @@ int __init ath79_register_pci(void) if (soc_is_ar724x()) return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); + if (soc_is_ar9342() || soc_is_ar9344()) { + u32 bootstrap; + + bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); + if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) + return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); + } + return -ENODEV; } -- 1.7.2.1 From rodrigue@qca.qualcomm.com Wed Mar 14 19:33:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 19:33:26 +0100 (CET) Received: from wolverine01.qualcomm.com ([199.106.114.254]:14345 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903740Ab2CNSdS (ORCPT ); Wed, 14 Mar 2012 19:33:18 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=qca.qualcomm.com; i=rodrigue@qca.qualcomm.com; q=dns/txt; s=qcdkim; t=1331749998; x=1363285998; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; z=Date:=20Wed,=2014=20Mar=202012=2011:33:11=20-0700|From: =20"Luis=20R.=20Rodriguez"=20 |To:=20Gabor=20Juhos=20|CC:=20Ralf=20 Baechle=20,=20,=0D=0A=09|Subject:=20Re:=20[P ATCH=20v2=2013/13]=20MIPS:=20ath79:=20add=20initial=20sup port=20for=20the=0D=0A=20Atheros=20DB120=20board |Message-ID:=20<20120314183311.GA8265@tux>|References:=20 <1331721931-4334-1-git-send-email-juhosg@openwrt.org>=0D =0A=20<1331721931-4334-14-git-send-email-juhosg@openwrt.o rg>|MIME-Version:=201.0|In-Reply-To:=20<1331721931-4334-1 4-git-send-email-juhosg@openwrt.org>; bh=W4OyubaSdzc9bicabu63KleprHXSLgu5gGS8/v7ioJA=; b=t++TmE/G3QGCvYUui5udegwqWjZT2CTHWAMGoZfrPNEnmAwbNcQu0cTp PeiHaumeDD9iIYMvwOC+ZH5JmkE3/BBLSZKqFu0xrFZzxegnrmr9sVxqb RRIeNx3MLBVvfGtjSR1Dg+IUhD6+NiEsx60sIAkkF1oHMmEnuONsuM1IS s=; X-IronPort-AV: E=McAfee;i="5400,1158,6648"; a="172463732" Received: from ironmsg02-l.qualcomm.com ([172.30.48.16]) by wolverine01.qualcomm.com with ESMTP; 14 Mar 2012 11:33:14 -0700 X-IronPort-AV: E=Sophos;i="4.73,584,1325491200"; d="scan'208";a="119711349" Received: from nasanexhc07.na.qualcomm.com ([172.30.39.190]) by ironmsg02-L.qualcomm.com with ESMTP/TLS/AES128-SHA; 14 Mar 2012 11:33:14 -0700 Received: from tux (172.30.39.5) by qcmail1.qualcomm.com (172.30.39.190) with Microsoft SMTP Server (TLS) id 14.1.339.1; Wed, 14 Mar 2012 11:33:12 -0700 Received: by tux (sSMTP sendmail emulation); Wed, 14 Mar 2012 11:33:11 -0700 Date: Wed, 14 Mar 2012 11:33:11 -0700 From: "Luis R. Rodriguez" To: Gabor Juhos CC: Ralf Baechle , , Subject: Re: [PATCH v2 13/13] MIPS: ath79: add initial support for the Atheros DB120 board Message-ID: <20120314183311.GA8265@tux> References: <1331721931-4334-1-git-send-email-juhosg@openwrt.org> <1331721931-4334-14-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1331721931-4334-14-git-send-email-juhosg@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [172.30.39.5] X-archive-position: 32707 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rodrigue@qca.qualcomm.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 985 Lines: 29 On Wed, Mar 14, 2012 at 11:45:31AM +0100, Gabor Juhos wrote: > Signed-off-by: Gabor Juhos > Acked-by: Luis R. Rodriguez > --- > v2: - remove USB controller registration, it will be added > by a separate patch-set > > Ralf, > > The mach-db120.c file is licensed under the Clear BSD license. That > is based on the modified BSD license and the FSF's [1] site states > that it is compatible with both the GPLv2 and GPLv3. > > However if you have concerns about the copyright we can resubmit > this file under the ISC license [2]. The ISC license is already > used upstream by the ath6kl and ath9k drivers. > > Thanks, > Gabor > > 1. http://www.gnu.org/licenses/license-list.html#clearbsd > 2. http://www.gnu.org/licenses/license-list.html#ISC Gabor, please resubmit under the ISC license. The patch has been pending since December and I really do not want to wait any longer. You can just resubmit this one single patch. Luis From juhosg@openwrt.org Wed Mar 14 20:33:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 20:34:03 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:35162 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903740Ab2CNTd5 (ORCPT ); Wed, 14 Mar 2012 20:33:57 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 9C6CE23C00DA; Wed, 14 Mar 2012 20:03:30 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , mcgrof@infradead.org, juhosg@openwrt.org Subject: [PATCH v2.1 13/13] MIPS: ath79: add initial support for the Atheros DB120 board Date: Wed, 14 Mar 2012 21:39:35 +0100 Message-Id: <1331757575-10161-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 32708 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6164 Lines: 211 Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez --- v2.1: - use ISC license v2: - remove USB controller registration, it will be added by a separate patch-set Ralf, Here is the ISC licensed version of the patch. Feel free to use this if you are not satisfied with the ClearBSD version. Thanks, Gabor arch/mips/ath79/Kconfig | 12 ++++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/mach-db120.c | 134 ++++++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + 4 files changed, 148 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/mach-db120.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index ea28e89..f44feee 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -26,6 +26,18 @@ config ATH79_MACH_AP81 Say 'Y' here if you want your kernel to support the Atheros AP81 reference board. +config ATH79_MACH_DB120 + bool "Atheros DB120 reference board" + select SOC_AR934X + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help + Say 'Y' here if you want your kernel to support the + Atheros DB120 reference board. + config ATH79_MACH_PB44 bool "Atheros PB44 reference board" select SOC_AR71XX diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 221a76a9..2b54d98 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -28,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o # obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o +obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o diff --git a/arch/mips/ath79/mach-db120.c b/arch/mips/ath79/mach-db120.c new file mode 100644 index 0000000..1983e4d --- /dev/null +++ b/arch/mips/ath79/mach-db120.c @@ -0,0 +1,134 @@ +/* + * Atheros DB120 reference board support + * + * Copyright (c) 2011 Qualcomm Atheros + * Copyright (c) 2011 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include + +#include "machtypes.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "pci.h" + +#define DB120_GPIO_LED_WLAN_5G 12 +#define DB120_GPIO_LED_WLAN_2G 13 +#define DB120_GPIO_LED_STATUS 14 +#define DB120_GPIO_LED_WPS 15 + +#define DB120_GPIO_BTN_WPS 16 + +#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) + +#define DB120_WMAC_CALDATA_OFFSET 0x1000 +#define DB120_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led db120_leds_gpio[] __initdata = { + { + .name = "db120:green:status", + .gpio = DB120_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "db120:green:wps", + .gpio = DB120_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "db120:green:wlan-5g", + .gpio = DB120_GPIO_LED_WLAN_5G, + .active_low = 1, + }, + { + .name = "db120:green:wlan-2g", + .gpio = DB120_GPIO_LED_WLAN_2G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button db120_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, + .gpio = DB120_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct spi_board_info db120_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "s25sl064a", + } +}; + +static struct ath79_spi_platform_data db120_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + +#ifdef CONFIG_PCI +static struct ath9k_platform_data db120_ath9k_data; + +static int db120_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 0: + dev->dev.platform_data = &db120_ath9k_data; + break; + } + + return 0; +} + +static void __init db120_pci_init(u8 *eeprom) +{ + memcpy(db120_ath9k_data.eeprom_data, eeprom, + sizeof(db120_ath9k_data.eeprom_data)); + + ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); + ath79_register_pci(); +} +#else +static inline void db120_pci_init(void) {} +#endif /* CONFIG_PCI */ + +static void __init db120_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), + db120_leds_gpio); + ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, + ARRAY_SIZE(db120_gpio_keys), + db120_gpio_keys); + ath79_register_spi(&db120_spi_data, db120_spi_info, + ARRAY_SIZE(db120_spi_info)); + ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); + db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", + db120_setup); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index 9a1f382..af92e5c 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -18,6 +18,7 @@ enum ath79_mach_type { ATH79_MACH_GENERIC = 0, ATH79_MACH_AP121, /* Atheros AP121 reference board */ ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ ATH79_MACH_PB44, /* Atheros PB44 reference board */ ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ }; -- 1.7.2.1 From juhosg@openwrt.org Wed Mar 14 20:51:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Mar 2012 20:51:50 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:52061 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903740Ab2CNTvo (ORCPT ); Wed, 14 Mar 2012 20:51:44 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from [192.168.254.129] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 8680723C00BA; Wed, 14 Mar 2012 20:21:16 +0100 (CET) Message-ID: <4F60F6CF.1010007@openwrt.org> Date: Wed, 14 Mar 2012 20:51:43 +0100 From: Gabor Juhos MIME-Version: 1.0 To: Hauke Mehrtens CC: gregkh@linuxfoundation.org, stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, Imre Kaloz Subject: Re: [PATCH v4 7/7] USB: use generic platform driver on ath79 References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> <1331597093-425-8-git-send-email-hauke@hauke-m.de> In-Reply-To: <1331597093-425-8-git-send-email-hauke@hauke-m.de> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=ISO-8859-2 Content-Transfer-Encoding: 8bit X-archive-position: 32709 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 461 Lines: 12 2012.03.13. 1:04 keltezéssel, Hauke Mehrtens írta: > The ath79 usb driver doesn't do anything special and is now converted > to the generic ehci and ohci driver. > This was tested on a TP-Link TL-WR1043ND (AR9132) > > CC: Gabor Juhos > CC: Imre Kaloz > CC: linux-mips@linux-mips.org > CC: Ralf Baechle > Signed-off-by: Hauke Mehrtens Acked-by: Gabor Juhos From cmetcalf@tilera.com Thu Mar 15 02:24:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 02:24:26 +0100 (CET) Received: from usmamail.tilera.com ([206.83.70.75]:49142 "EHLO USMAMAIL.TILERA.COM" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903750Ab2COBYS (ORCPT ); Thu, 15 Mar 2012 02:24:18 +0100 Received: from [192.168.1.104] (24.34.76.130) by USMAExch2.tad.internal.tilera.com (10.3.0.33) with Microsoft SMTP Server id 14.0.694.0; Wed, 14 Mar 2012 21:24:10 -0400 Message-ID: <4F6144B8.5010601@tilera.com> Date: Wed, 14 Mar 2012 21:24:08 -0400 From: Chris Metcalf User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Arnd Bergmann , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , , "David S. Miller" , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , , "Eric W. Biederman" , Christoph Hellwig , Lucas De Marchi , Dmitry Torokhov , Andrew Morton , "J. Bruce Fields" , NeilBrown , , , , , Subject: Re: [PATCH v3] ipc: provide generic compat versions of IPC syscalls References: <201112091536.pB9Fa5f7002738@farm-0002.internal.tilera.com> <201112091903.pB9J39pd031553@farm-0002.internal.tilera.com> <20111209134852.f5b5bcbc.akpm@linux-foundation.org> <1690400.7yOAjHVqTH@wuerfel> <201112122148.pBCLmPH0023959@farm-0002.internal.tilera.com> In-Reply-To: <201112122148.pBCLmPH0023959@farm-0002.internal.tilera.com> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-archive-position: 32710 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cmetcalf@tilera.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 12978 Lines: 386 Somewhat belatedly, I'm looking to push this through the "tile" tree. Andrew Morton has been keeping it in his tree but I figure I should push it since it directly affects "tile" and currently no one else. However, it would be nice if anyone could provide a Reviewed-by or Acked-by on the patch. Thanks! On 12/9/2011 10:29 AM, Chris Metcalf wrote: > When using the "compat" APIs, architectures will generally want to > be able to make direct syscalls to msgsnd(), shmctl(), etc., and > in the kernel we would want them to be handled directly by > compat_sys_xxx() functions, as is true for other compat syscalls. > > However, for historical reasons, several of the existing compat IPC > syscalls do not do this. semctl() expects a pointer to the fourth > argument, instead of the fourth argument itself. msgsnd(), msgrcv() > and shmat() expect arguments in different order. > > This change adds an ARCH_WANT_OLD_COMPAT_IPC config option that can be > set to preserve this behavior for ports that use it (x86, sparc, powerpc, > s390, and mips). No actual semantics are changed for those architectures, > and there is only a minimal amount of code refactoring in ipc/compat.c. > > Newer architectures like tile (and perhaps future architectures such > as arm64 and unicore64) should not select this option, and thus can > avoid having any IPC-specific code at all in their architecture-specific > compat layer. In the same vein, if this option is not selected, IPC_64 > mode is assumed, since that's what the headers expect. > > The workaround code in "tile" for msgsnd() and msgrcv() is removed > with this change; it also fixes the bug that shmat() and semctl() were > not being properly handled. > > Signed-off-by: Chris Metcalf > --- > arch/Kconfig | 3 ++ > arch/mips/Kconfig | 1 + > arch/powerpc/Kconfig | 1 + > arch/s390/Kconfig | 1 + > arch/sparc/Kconfig | 1 + > arch/tile/include/asm/compat.h | 11 ------ > arch/tile/kernel/compat.c | 43 ------------------------ > arch/x86/Kconfig | 1 + > include/linux/compat.h | 12 ++++++- > ipc/compat.c | 70 ++++++++++++++++++++++++++++++++++++--- > 10 files changed, 83 insertions(+), 61 deletions(-) > > diff --git a/arch/Kconfig b/arch/Kconfig > index 4b0669c..dfb1e07 100644 > --- a/arch/Kconfig > +++ b/arch/Kconfig > @@ -181,4 +181,7 @@ config HAVE_RCU_TABLE_FREE > config ARCH_HAVE_NMI_SAFE_CMPXCHG > bool > > +config ARCH_WANT_OLD_COMPAT_IPC > + bool > + > source "kernel/gcov/Kconfig" > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index d46f1da..ad2af82 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -2420,6 +2420,7 @@ config MIPS32_COMPAT > config COMPAT > bool > depends on MIPS32_COMPAT > + select ARCH_WANT_OLD_COMPAT_IPC > default y > > config SYSVIPC_COMPAT > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig > index 951e18f..e2be710 100644 > --- a/arch/powerpc/Kconfig > +++ b/arch/powerpc/Kconfig > @@ -146,6 +146,7 @@ config COMPAT > bool > default y if PPC64 > select COMPAT_BINFMT_ELF > + select ARCH_WANT_OLD_COMPAT_IPC > > config SYSVIPC_COMPAT > bool > diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig > index 373679b..2fc3bca 100644 > --- a/arch/s390/Kconfig > +++ b/arch/s390/Kconfig > @@ -221,6 +221,7 @@ config COMPAT > prompt "Kernel support for 31 bit emulation" > depends on 64BIT > select COMPAT_BINFMT_ELF > + select ARCH_WANT_OLD_COMPAT_IPC > help > Select this option if you want to enable your system kernel to > handle system-calls from ELF binaries for 31 bit ESA. This option > diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig > index f92602e..846cb5c 100644 > --- a/arch/sparc/Kconfig > +++ b/arch/sparc/Kconfig > @@ -577,6 +577,7 @@ config COMPAT > depends on SPARC64 > default y > select COMPAT_BINFMT_ELF > + select ARCH_WANT_OLD_COMPAT_IPC > > config SYSVIPC_COMPAT > bool > diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h > index bf95f55..4b4b289 100644 > --- a/arch/tile/include/asm/compat.h > +++ b/arch/tile/include/asm/compat.h > @@ -242,17 +242,6 @@ long compat_sys_fallocate(int fd, int mode, > long compat_sys_sched_rr_get_interval(compat_pid_t pid, > struct compat_timespec __user *interval); > > -/* Versions of compat functions that differ from generic Linux. */ > -struct compat_msgbuf; > -long tile_compat_sys_msgsnd(int msqid, > - struct compat_msgbuf __user *msgp, > - size_t msgsz, int msgflg); > -long tile_compat_sys_msgrcv(int msqid, > - struct compat_msgbuf __user *msgp, > - size_t msgsz, long msgtyp, int msgflg); > -long tile_compat_sys_ptrace(compat_long_t request, compat_long_t pid, > - compat_long_t addr, compat_long_t data); > - > /* Tilera Linux syscalls that don't have "compat" versions. */ > #define compat_sys_flush_cache sys_flush_cache > > diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c > index bf5e9d7..d67459b 100644 > --- a/arch/tile/kernel/compat.c > +++ b/arch/tile/kernel/compat.c > @@ -16,7 +16,6 @@ > #define __SYSCALL_COMPAT > > #include > -#include > #include > #include > #include > @@ -95,52 +94,10 @@ long compat_sys_sched_rr_get_interval(compat_pid_t pid, > return ret; > } > > -/* > - * The usual compat_sys_msgsnd() and _msgrcv() seem to be assuming > - * some different calling convention than our normal 32-bit tile code. > - */ > - > -/* Already defined in ipc/compat.c, but we need it here. */ > -struct compat_msgbuf { > - compat_long_t mtype; > - char mtext[1]; > -}; > - > -long tile_compat_sys_msgsnd(int msqid, > - struct compat_msgbuf __user *msgp, > - size_t msgsz, int msgflg) > -{ > - compat_long_t mtype; > - > - if (get_user(mtype, &msgp->mtype)) > - return -EFAULT; > - return do_msgsnd(msqid, mtype, msgp->mtext, msgsz, msgflg); > -} > - > -long tile_compat_sys_msgrcv(int msqid, > - struct compat_msgbuf __user *msgp, > - size_t msgsz, long msgtyp, int msgflg) > -{ > - long err, mtype; > - > - err = do_msgrcv(msqid, &mtype, msgp->mtext, msgsz, msgtyp, msgflg); > - if (err < 0) > - goto out; > - > - if (put_user(mtype, &msgp->mtype)) > - err = -EFAULT; > - out: > - return err; > -} > - > /* Provide the compat syscall number to call mapping. */ > #undef __SYSCALL > #define __SYSCALL(nr, call) [nr] = (call), > > -/* The generic versions of these don't work for Tile. */ > -#define compat_sys_msgrcv tile_compat_sys_msgrcv > -#define compat_sys_msgsnd tile_compat_sys_msgsnd > - > /* See comments in sys.c */ > #define compat_sys_fadvise64_64 sys32_fadvise64_64 > #define compat_sys_readahead sys32_readahead > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index cb9a104..0e1f474 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -2131,6 +2131,7 @@ config IA32_AOUT > config COMPAT > def_bool y > depends on IA32_EMULATION > + select ARCH_WANT_OLD_COMPAT_IPC > > config COMPAT_FOR_U64_ALIGNMENT > def_bool COMPAT > diff --git a/include/linux/compat.h b/include/linux/compat.h > index 66ed067..f295dae 100644 > --- a/include/linux/compat.h > +++ b/include/linux/compat.h > @@ -224,6 +224,7 @@ struct compat_sysinfo; > struct compat_sysctl_args; > struct compat_kexec_segment; > struct compat_mq_attr; > +struct compat_msgbuf; > > extern void compat_exit_robust_list(struct task_struct *curr); > > @@ -234,13 +235,22 @@ asmlinkage long > compat_sys_get_robust_list(int pid, compat_uptr_t __user *head_ptr, > compat_size_t __user *len_ptr); > > +#ifdef CONFIG_ARCH_WANT_OLD_COMPAT_IPC > long compat_sys_semctl(int first, int second, int third, void __user *uptr); > long compat_sys_msgsnd(int first, int second, int third, void __user *uptr); > long compat_sys_msgrcv(int first, int second, int msgtyp, int third, > int version, void __user *uptr); > -long compat_sys_msgctl(int first, int second, void __user *uptr); > long compat_sys_shmat(int first, int second, compat_uptr_t third, int version, > void __user *uptr); > +#else > +long compat_sys_semctl(int semid, int semnum, int cmd, int arg); > +long compat_sys_msgsnd(int msqid, struct compat_msgbuf __user *msgp, > + size_t msgsz, int msgflg); > +long compat_sys_msgrcv(int msqid, struct compat_msgbuf __user *msgp, > + size_t msgsz, long msgtyp, int msgflg); > +long compat_sys_shmat(int shmid, compat_uptr_t shmaddr, int shmflg); > +#endif > +long compat_sys_msgctl(int first, int second, void __user *uptr); > long compat_sys_shmctl(int first, int second, void __user *uptr); > long compat_sys_semtimedop(int semid, struct sembuf __user *tsems, > unsigned nsems, const struct compat_timespec __user *timeout); > diff --git a/ipc/compat.c b/ipc/compat.c > index 845a287..a6df704 100644 > --- a/ipc/compat.c > +++ b/ipc/compat.c > @@ -27,6 +27,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -117,6 +118,7 @@ extern int sem_ctls[]; > > static inline int compat_ipc_parse_version(int *cmd) > { > +#ifdef CONFIG_ARCH_WANT_OLD_COMPAT_IPC > int version = *cmd & IPC_64; > > /* this is tricky: architectures that have support for the old > @@ -128,6 +130,10 @@ static inline int compat_ipc_parse_version(int *cmd) > *cmd &= ~IPC_64; > #endif > return version; > +#else > + /* With the asm-generic APIs, we always use the 64-bit versions. */ > + return IPC_64; > +#endif > } > > static inline int __get_compat_ipc64_perm(struct ipc64_perm *p64, > @@ -232,10 +238,9 @@ static inline int put_compat_semid_ds(struct semid64_ds *s, > return err; > } > > -long compat_sys_semctl(int first, int second, int third, void __user *uptr) > +static long do_compat_semctl(int first, int second, int third, u32 pad) > { > union semun fourth; > - u32 pad; > int err, err2; > struct semid64_ds s64; > struct semid64_ds __user *up64; > @@ -243,10 +248,6 @@ long compat_sys_semctl(int first, int second, int third, void __user *uptr) > > memset(&s64, 0, sizeof(s64)); > > - if (!uptr) > - return -EINVAL; > - if (get_user(pad, (u32 __user *) uptr)) > - return -EFAULT; > if ((third & (~IPC_64)) == SETVAL) > fourth.val = (int) pad; > else > @@ -305,6 +306,18 @@ long compat_sys_semctl(int first, int second, int third, void __user *uptr) > return err; > } > > +#ifdef CONFIG_ARCH_WANT_OLD_COMPAT_IPC > +long compat_sys_semctl(int first, int second, int third, void __user *uptr) > +{ > + u32 pad; > + > + if (!uptr) > + return -EINVAL; > + if (get_user(pad, (u32 __user *) uptr)) > + return -EFAULT; > + return do_compat_semctl(first, second, third, pad); > +} > + > long compat_sys_msgsnd(int first, int second, int third, void __user *uptr) > { > struct compat_msgbuf __user *up = uptr; > @@ -353,6 +366,37 @@ long compat_sys_msgrcv(int first, int second, int msgtyp, int third, > out: > return err; > } > +#else > +long compat_sys_semctl(int semid, int semnum, int cmd, int arg) > +{ > + return do_compat_semctl(semid, semnum, cmd, arg); > +} > + > +long compat_sys_msgsnd(int msqid, struct compat_msgbuf __user *msgp, > + size_t msgsz, int msgflg) > +{ > + compat_long_t mtype; > + > + if (get_user(mtype, &msgp->mtype)) > + return -EFAULT; > + return do_msgsnd(msqid, mtype, msgp->mtext, msgsz, msgflg); > +} > + > +long compat_sys_msgrcv(int msqid, struct compat_msgbuf __user *msgp, > + size_t msgsz, long msgtyp, int msgflg) > +{ > + long err, mtype; > + > + err = do_msgrcv(msqid, &mtype, msgp->mtext, msgsz, msgtyp, msgflg); > + if (err < 0) > + goto out; > + > + if (put_user(mtype, &msgp->mtype)) > + err = -EFAULT; > + out: > + return err; > +} > +#endif > > static inline int get_compat_msqid64(struct msqid64_ds *m64, > struct compat_msqid64_ds __user *up64) > @@ -470,6 +514,7 @@ long compat_sys_msgctl(int first, int second, void __user *uptr) > return err; > } > > +#ifdef CONFIG_ARCH_WANT_OLD_COMPAT_IPC > long compat_sys_shmat(int first, int second, compat_uptr_t third, int version, > void __user *uptr) > { > @@ -485,6 +530,19 @@ long compat_sys_shmat(int first, int second, compat_uptr_t third, int version, > uaddr = compat_ptr(third); > return put_user(raddr, uaddr); > } > +#else > +long compat_sys_shmat(int shmid, compat_uptr_t shmaddr, int shmflg) > +{ > + unsigned long ret; > + long err; > + > + err = do_shmat(shmid, compat_ptr(shmaddr), shmflg, &ret); > + if (err) > + return err; > + force_successful_syscall_return(); > + return (long)ret; > +} > +#endif > > static inline int get_compat_shmid64_ds(struct shmid64_ds *s64, > struct compat_shmid64_ds __user *up64) -- Chris Metcalf, Tilera Corp. http://www.tilera.com From arnd@arndb.de Thu Mar 15 17:26:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 17:26:09 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.126.171]:55143 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903652Ab2COQ0F (ORCPT ); Thu, 15 Mar 2012 17:26:05 +0100 Received: from klappe2.localnet (deibp9eh1--blueice3n2.emea.ibm.com [195.212.29.180]) by mrelayeu.kundenserver.de (node=mreu3) with ESMTP (Nemesis) id 0MU8aj-1RiC9E1YrB-00QnET; Thu, 15 Mar 2012 17:25:34 +0100 From: Arnd Bergmann To: Chris Metcalf Subject: Re: [PATCH v3] ipc: provide generic compat versions of IPC syscalls Date: Thu, 15 Mar 2012 16:25:32 +0000 User-Agent: KMail/1.12.2 (Linux/3.3.0-rc1; KDE/4.3.2; x86_64; ; ) Cc: Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, "David S. Miller" , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, "Eric W. Biederman" , Christoph Hellwig , Lucas De Marchi , Dmitry Torokhov , Andrew Morton , "J. Bruce Fields" , NeilBrown , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org References: <201112091536.pB9Fa5f7002738@farm-0002.internal.tilera.com> <201112122148.pBCLmPH0023959@farm-0002.internal.tilera.com> <4F6144B8.5010601@tilera.com> In-Reply-To: <4F6144B8.5010601@tilera.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201203151625.32199.arnd@arndb.de> X-Provags-ID: V02:K0:P922dHs4wgmggE20Dch8pBF3qhCaJX1GxSiX7E9IPrx qxDSkpPXcAq2EXTxEFd4VS8+lQXRvQe06szjqLZYCxPQrSdSSb l9QB9361pLH6sbIInR7ci1YdIR0GFrkf2PUZdmdRjzaUgS77Nc ZaAVNKopiv8vF4f9dnx2tq46V9gq066lzoPTcWSUx9b+gwNqdA de2VQRmPfA1z+FE7Ta4Qdl8cky3gzfiTZBfsEafrVJXz+Cfq+/ dJMEI/ZAKIBN6gp9qySJhIVnoYtKmisNitvEF8Kph1ldmZKLkY GIBgwG2rcENWEk1Gg11WEJjfkVe7/rrHRvJbeeipdKo2GOeEwf trtVmexyROrYsqycmwL0= X-archive-position: 32711 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arnd@arndb.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 483 Lines: 14 On Thursday 15 March 2012, Chris Metcalf wrote: > > Somewhat belatedly, I'm looking to push this through the "tile" tree. > Andrew Morton has been keeping it in his tree but I figure I should push it > since it directly affects "tile" and currently no one else. Sounds good. > However, it would be nice if anyone could provide a Reviewed-by or Acked-by > on the patch. Thanks! As the main author of ipc/compat.c in its current form, Reviewed-by: Arnd Bergmann From gregkh@linuxfoundation.org Thu Mar 15 20:44:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 20:44:42 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:51856 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903659Ab2COToh (ORCPT ); Thu, 15 Mar 2012 20:44:37 +0100 Received: by dakp5 with SMTP id p5so4611534dak.36 for ; Thu, 15 Mar 2012 12:44:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=n40gh3vva+zRGHFg+rfRyUBoUPFk30ur54yCeuNxKT0=; b=mFxeKX6K4IynK3qIDkDvDsdjVTpWh4Q1T40rnOjSQkt+JkQ/Y+lE2Om1r8MXylsM0r iYJMcEbvmw+ZPS5u0v90OWcdm5WPTHohPyR36I/5aO20IOt+TjNzWTsWSGkOxTX1r5V/ 45yOjmHPAKnWpuobWKBXeQlSpAhGKQ9htDoWBuEdH4xsjesH8S0Q00JG/P+pnEQQyfkE gAWc7Mq0IOcbAWMCNkv41CYPxXMDcG3V8R/CDO4hM5ogCQs8Dnkya2DZ+K4WLSyJKWeQ G1rVWUFs6Kv3p/y2sjPxZFcgRyVgXVPZzYCfGUzPGS3E9sIInSUvpAwn24Aa8Exhos3D 83zg== Received: by 10.68.226.225 with SMTP id rv1mr7475690pbc.44.1331840670519; Thu, 15 Mar 2012 12:44:30 -0700 (PDT) Received: from localhost (c-76-121-69-168.hsd1.wa.comcast.net. [76.121.69.168]) by mx.google.com with ESMTPS id d10sm2511320pbr.59.2012.03.15.12.44.27 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 15 Mar 2012 12:44:28 -0700 (PDT) Date: Thu, 15 Mar 2012 12:44:26 -0700 From: Greg KH To: Hauke Mehrtens Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org Subject: Re: [PATCH v4 4/7] USB: Add driver for the bcma bus Message-ID: <20120315194426.GA30682@kroah.com> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> <1331597093-425-5-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1331597093-425-5-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQnXhA51SW5lEZTUn6EI7UqDvFw6TAZSl1RHe3NEyai9i1GEgoF9gD8GWimEPMb6TxWqyu0q X-archive-position: 32712 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 807 Lines: 19 On Tue, Mar 13, 2012 at 01:04:50AM +0100, Hauke Mehrtens wrote: > This adds a USB driver using the generic platform device driver for the > USB controller found on the Broadcom bcma bus. The bcma bus just > exposes one device which serves the OHCI and the EHCI controller at the > same time. This driver probes for this USB controller and creates and > registers two new platform devices which will be probed by the new > generic platform device driver. This makes it possible to use the EHCI > and the OCHI controller on the bcma bus at the same time. > > Signed-off-by: Hauke Mehrtens > --- > drivers/usb/host/Kconfig | 12 ++ This patch fails to apply here, and I can't seem to figure out what tree you made this against to fix it up by hand on my end. Any thoughts? greg k-h From gregkh@linuxfoundation.org Thu Mar 15 20:45:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 20:45:08 +0100 (CET) Received: from mail-yx0-f177.google.com ([209.85.213.177]:45511 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903663Ab2COTpE (ORCPT ); Thu, 15 Mar 2012 20:45:04 +0100 Received: by yenm10 with SMTP id m10so3917342yen.36 for ; Thu, 15 Mar 2012 12:44:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:content-transfer-encoding :in-reply-to:user-agent:x-gm-message-state; bh=GW2eMifo69Tj7HQy6g74Zd/2DYYNUPCmu0WKBZFO2hQ=; b=CDmTbWkJykuqnrcV1lr7SuDlkNfZCq2m/yVuPlgO5xrMzyb9jqjRniDwxvBMXLfB1t QyYBqXlVXsYlgxx+caCRg1XNzXmBQpp+eXuUMS6noqSO/fG6Y1pAUKrqZbWfeTXi8O2y vdd17cwdhmr6BcLv5Q2YewLThy+PC9Bmd0CzxsMHnvTvkFhJE474JqCvXbqCTB/ugsHS 027MBC9EJaE5RUdShUaM3AZzan7cVcWbBgPpgIqtf+71Ar7e8iHQ2bdset5VnQX/PgI3 ivAdys1vfRnUXVSJUGhVX3QDkLlC/nsWCp8n8pzCrpZCanW2N0es/sRyil9gI7Q+ltQ8 1yrg== Received: by 10.68.131.104 with SMTP id ol8mr6011721pbb.112.1331840697952; Thu, 15 Mar 2012 12:44:57 -0700 (PDT) Received: from localhost (c-76-121-69-168.hsd1.wa.comcast.net. [76.121.69.168]) by mx.google.com with ESMTPS id k2sm2523431pba.28.2012.03.15.12.44.55 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 15 Mar 2012 12:44:56 -0700 (PDT) Date: Thu, 15 Mar 2012 12:44:53 -0700 From: Greg KH To: Hauke Mehrtens Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= Subject: Re: [PATCH v4 3/7] bcma: scan for extra address space Message-ID: <20120315194453.GB30682@kroah.com> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> <1331597093-425-4-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1331597093-425-4-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQnUfIyIF8fyZvqCqdwJ6SMxWqceyaQQB1N5eIMjGbcL9ZA4U3xgGV+0a/WtU7UtuekrqdLj X-archive-position: 32713 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 843 Lines: 23 On Tue, Mar 13, 2012 at 01:04:49AM +0100, Hauke Mehrtens wrote: > Some cores like the USB core have two address spaces. In the USB host > controller one address space is used for the OHCI and the other for the > EHCI controller interface. The USB controller is the only core I found > with two address spaces. This code is based on the AI scan function > ai_scan() in shared/aiutils.c in the Broadcom SDK. > > CC: RafaÅ‚ MiÅ‚ecki > CC: linux-wireless@vger.kernel.org > Signed-off-by: Hauke Mehrtens > --- > drivers/bcma/scan.c | 19 ++++++++++++++++++- > include/linux/bcma/bcma.h | 1 + > 2 files changed, 19 insertions(+), 1 deletions(-) Is this required for the 4/7 patch? If so, can I get an ack from the BCMA developers so that I can take this through the USB tree? thanks, greg k-h From gregkh@linuxfoundation.org Thu Mar 15 20:47:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 20:47:21 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:52178 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903659Ab2COTrR (ORCPT ); Thu, 15 Mar 2012 20:47:17 +0100 Received: by dakp5 with SMTP id p5so4615012dak.36 for ; Thu, 15 Mar 2012 12:47:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=k5Ku08/UcrAQCCnU8BkIWMfq9Fz+harLQ4xERaBlm7c=; b=SQtYguOEe6SsQbheEksAQH00whb1mD6nXJpHETaeuZZsu3Dbz3Zr0VYhaKbPZz6gWl uzScx3JXWf8x2KRsSd3cP6Wk4UvAE+O5K6QFmQquCcWHa65U/cw0vQ1L4Kklxn7SAkI6 RynY9zbJSwXg5a1rwVV3OvWATOuGw0pudWkdWOEBe7kO0M+irMzvJgVsUBfj59scw24n /pzp12oRMnzhigm7L4AkxiGxE5vFU8a65y8wb+JSerm08xWWKbQIdzkgYCAzQEtIhB+l /5XqVaC512KVvM4mZI/GtuGDeZgG252c6jSX0sd9eSxYMJ/vFUM595U+lmSN2spTCvVL 4NsA== Received: by 10.68.234.131 with SMTP id ue3mr7550806pbc.5.1331840831521; Thu, 15 Mar 2012 12:47:11 -0700 (PDT) Received: from localhost (c-76-121-69-168.hsd1.wa.comcast.net. [76.121.69.168]) by mx.google.com with ESMTPS id s10sm2531613pbp.14.2012.03.15.12.47.08 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 15 Mar 2012 12:47:09 -0700 (PDT) Date: Thu, 15 Mar 2012 12:47:07 -0700 From: Greg KH To: Hauke Mehrtens Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org Subject: Re: [PATCH v4 0/7] USB: OHCI/EHCI: generic platform driver Message-ID: <20120315194707.GA8079@kroah.com> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1331597093-425-1-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQkOF++YNaTFRWa4ajhIuHEiWdK+AIxQfiCMTN2wyzzrlUUNZpKVuXyMCjZAVAzJZOrx0/6i X-archive-position: 32714 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1231 Lines: 30 On Tue, Mar 13, 2012 at 01:04:46AM +0100, Hauke Mehrtens wrote: > This EHCI/OHCI platform driver should replace the simple EHCI and OHCI > platform drivers. It was developed to be used for the USB core of the > Broadcom SoCs supported by ssb and bcma, but it should also work for > other devices. > > Drivers like ehci-ath79.c, ehci-xls.c and ehci-ixp4xx.c should be > relative easy be ported to this EHCI driver. > And drivers like ohci-ath79.c, ohci-ppc-soc.c, ohci-sh.c and ohci-xls.c > should be easy be ported to the this OHCI driver. > > I am unable to test the suspend and resume part, as my SoC does not > support this, but most of the platform driver do not support > suspend/resume too. The code here should work, but was never runtime > tested. > > This also contains patches adding USB support for the SoCs based on ssb > and bcma and converts the ath79 code to use the generic usb driver. > > This patch series is based on the usb tree and should go through it to Linus. I've applied patches 1, 2, and 7 of this series. 3 and 4 I've commented on, and I'm guessing 5 and 6 depend on 3 and 4. Care to refresh the remaining ones and get the BCMA developers ack so that I can take them? thanks, greg k-h From dhowells@redhat.com Thu Mar 15 21:58:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 21:58:29 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:22303 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903681Ab2COU6T (ORCPT ); Thu, 15 Mar 2012 21:58:19 +0100 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q2FKwBOY008163 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 15 Mar 2012 16:58:11 -0400 Received: from warthog.procyon.org.uk ([10.3.112.12]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q2FKw4wV026255; Thu, 15 Mar 2012 16:58:06 -0400 Organization: Red Hat UK Ltd. Registered Address: Red Hat UK Ltd, Amberley Place, 107-111 Peascod Street, Windsor, Berkshire, SI4 1TE, United Kingdom. Registered in England and Wales under Company Registration No. 3798903 From: David Howells Subject: [PATCH 18/38] Disintegrate asm/system.h for MIPS [ver #3] To: paul.gortmaker@windriver.com Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, arnd@arndb.de, David Howells , linux-mips@linux-mips.org Date: Thu, 15 Mar 2012 20:58:04 +0000 Message-ID: <20120315205804.28759.36973.stgit@warthog.procyon.org.uk> In-Reply-To: <20120315205514.28759.58969.stgit@warthog.procyon.org.uk> References: <20120315205514.28759.58969.stgit@warthog.procyon.org.uk> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-archive-position: 32715 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhowells@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 46814 Lines: 1572 Disintegrate asm/system.h for MIPS. Signed-off-by: David Howells cc: linux-mips@linux-mips.org --- arch/mips/cavium-octeon/setup.c | 1 arch/mips/cavium-octeon/smp.c | 1 arch/mips/dec/ecc-berr.c | 1 arch/mips/dec/kn01-berr.c | 1 arch/mips/dec/kn02xa-berr.c | 1 arch/mips/dec/wbflush.c | 1 arch/mips/emma/markeins/irq.c | 1 arch/mips/fw/arc/misc.c | 1 arch/mips/include/asm/atomic.h | 2 arch/mips/include/asm/cmpxchg.h | 124 +++++++++++++ arch/mips/include/asm/dma.h | 1 arch/mips/include/asm/exec.h | 17 ++ arch/mips/include/asm/mach-au1x00/au1000_dma.h | 1 arch/mips/include/asm/processor.h | 7 + arch/mips/include/asm/setup.h | 11 + arch/mips/include/asm/switch_to.h | 85 +++++++++ arch/mips/include/asm/system.h | 236 ------------------------ arch/mips/include/asm/txx9/jmr3927.h | 1 arch/mips/kernel/cpu-bugs64.c | 1 arch/mips/kernel/cpu-probe.c | 1 arch/mips/kernel/irq-rm7000.c | 1 arch/mips/kernel/irq-rm9000.c | 1 arch/mips/kernel/irq.c | 1 arch/mips/kernel/irq_cpu.c | 1 arch/mips/kernel/mips-mt.c | 1 arch/mips/kernel/process.c | 1 arch/mips/kernel/ptrace.c | 1 arch/mips/kernel/ptrace32.c | 1 arch/mips/kernel/rtlx.c | 1 arch/mips/kernel/setup.c | 1 arch/mips/kernel/signal.c | 1 arch/mips/kernel/signal32.c | 1 arch/mips/kernel/signal_n32.c | 1 arch/mips/kernel/smp-bmips.c | 1 arch/mips/kernel/smp-cmp.c | 1 arch/mips/kernel/smp-mt.c | 1 arch/mips/kernel/smp.c | 1 arch/mips/kernel/smtc-proc.c | 1 arch/mips/kernel/smtc.c | 1 arch/mips/kernel/spram.c | 1 arch/mips/kernel/syscall.c | 1 arch/mips/kernel/traps.c | 1 arch/mips/kernel/unaligned.c | 1 arch/mips/kernel/vpe.c | 1 arch/mips/lasat/reset.c | 1 arch/mips/math-emu/dsemul.c | 1 arch/mips/mipssim/sim_smtc.c | 1 arch/mips/mm/c-octeon.c | 1 arch/mips/mm/c-r3k.c | 1 arch/mips/mm/c-r4k.c | 1 arch/mips/mm/c-tx39.c | 1 arch/mips/mm/fault.c | 1 arch/mips/mm/page.c | 1 arch/mips/mm/sc-ip22.c | 1 arch/mips/mm/sc-mips.c | 1 arch/mips/mm/sc-r5k.c | 1 arch/mips/mm/tlb-r3k.c | 1 arch/mips/mm/tlb-r4k.c | 1 arch/mips/mm/tlb-r8k.c | 1 arch/mips/mm/tlbex.c | 1 arch/mips/mti-malta/malta-init.c | 1 arch/mips/netlogic/common/irq.c | 1 arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c | 1 arch/mips/pmc-sierra/msp71xx/msp_irq_per.c | 1 arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c | 1 arch/mips/pmc-sierra/yosemite/irq.c | 1 arch/mips/pmc-sierra/yosemite/prom.c | 1 arch/mips/powertv/asic/irq_asic.c | 1 arch/mips/powertv/init.c | 1 arch/mips/rb532/irq.c | 1 arch/mips/sgi-ip22/ip22-berr.c | 1 arch/mips/sgi-ip22/ip22-reset.c | 1 arch/mips/sgi-ip22/ip28-berr.c | 1 arch/mips/sgi-ip27/ip27-irq.c | 1 arch/mips/sgi-ip27/ip27-reset.c | 1 arch/mips/sgi-ip32/ip32-irq.c | 1 arch/mips/sgi-ip32/ip32-reset.c | 1 arch/mips/sibyte/bcm1480/irq.c | 1 arch/mips/sibyte/common/sb_tbprof.c | 1 arch/mips/sibyte/sb1250/bus_watcher.c | 1 arch/mips/sibyte/sb1250/irq.c | 1 arch/mips/sni/reset.c | 1 arch/mips/vr41xx/common/irq.c | 1 arch/mips/vr41xx/common/pmu.c | 1 84 files changed, 250 insertions(+), 309 deletions(-) create mode 100644 arch/mips/include/asm/exec.h create mode 100644 arch/mips/include/asm/switch_to.h diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 260b273..d3a9f012 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index b1535fe..599a6db 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c index 7abce66..5abf4e8 100644 --- a/arch/mips/dec/ecc-berr.c +++ b/arch/mips/dec/ecc-berr.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c index 94d23b4..44d8a87 100644 --- a/arch/mips/dec/kn01-berr.c +++ b/arch/mips/dec/kn01-berr.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c index 07ca540..ebb73c5 100644 --- a/arch/mips/dec/kn02xa-berr.c +++ b/arch/mips/dec/kn02xa-berr.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/dec/wbflush.c b/arch/mips/dec/wbflush.c index 925c052..46ef903 100644 --- a/arch/mips/dec/wbflush.c +++ b/arch/mips/dec/wbflush.c @@ -17,7 +17,6 @@ #include #include -#include #include static void wbflush_kn01(void); diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index 7798887..b5f0825 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -27,7 +27,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/fw/arc/misc.c b/arch/mips/fw/arc/misc.c index 29627fb..7cf80ca 100644 --- a/arch/mips/fw/arc/misc.c +++ b/arch/mips/fw/arc/misc.c @@ -17,7 +17,6 @@ #include #include #include -#include VOID ArcHalt(VOID) diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 1d93f81..3f4c5cb 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -18,8 +18,8 @@ #include #include #include +#include #include -#include #define ATOMIC_INIT(i) { (i) } diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index d8d1c28..285a41f 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -9,6 +9,130 @@ #define __ASM_CMPXCHG_H #include +#include + +static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) +{ + __u32 retval; + + smp_mb__before_llsc(); + + if (kernel_uses_llsc && R10000_LLSC_WAR) { + unsigned long dummy; + + __asm__ __volatile__( + " .set mips3 \n" + "1: ll %0, %3 # xchg_u32 \n" + " .set mips0 \n" + " move %2, %z4 \n" + " .set mips3 \n" + " sc %2, %1 \n" + " beqzl %2, 1b \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } else if (kernel_uses_llsc) { + unsigned long dummy; + + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %0, %3 # xchg_u32 \n" + " .set mips0 \n" + " move %2, %z4 \n" + " .set mips3 \n" + " sc %2, %1 \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } while (unlikely(!dummy)); + } else { + unsigned long flags; + + raw_local_irq_save(flags); + retval = *m; + *m = val; + raw_local_irq_restore(flags); /* implies memory barrier */ + } + + smp_llsc_mb(); + + return retval; +} + +#ifdef CONFIG_64BIT +static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) +{ + __u64 retval; + + smp_mb__before_llsc(); + + if (kernel_uses_llsc && R10000_LLSC_WAR) { + unsigned long dummy; + + __asm__ __volatile__( + " .set mips3 \n" + "1: lld %0, %3 # xchg_u64 \n" + " move %2, %z4 \n" + " scd %2, %1 \n" + " beqzl %2, 1b \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } else if (kernel_uses_llsc) { + unsigned long dummy; + + do { + __asm__ __volatile__( + " .set mips3 \n" + " lld %0, %3 # xchg_u64 \n" + " move %2, %z4 \n" + " scd %2, %1 \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } while (unlikely(!dummy)); + } else { + unsigned long flags; + + raw_local_irq_save(flags); + retval = *m; + *m = val; + raw_local_irq_restore(flags); /* implies memory barrier */ + } + + smp_llsc_mb(); + + return retval; +} +#else +extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val); +#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels +#endif + +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + switch (size) { + case 4: + return __xchg_u32(ptr, x); + case 8: + return __xchg_u64(ptr, x); + } + + return x; +} + +#define xchg(ptr, x) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \ + \ + ((__typeof__(*(ptr))) \ + __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \ +}) #define __HAVE_ARCH_CMPXCHG 1 diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h index 2d47da6..f5097f6 100644 --- a/arch/mips/include/asm/dma.h +++ b/arch/mips/include/asm/dma.h @@ -15,7 +15,6 @@ #include /* need byte IO */ #include /* And spinlocks */ #include -#include #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER diff --git a/arch/mips/include/asm/exec.h b/arch/mips/include/asm/exec.h new file mode 100644 index 0000000..c1f6afa --- /dev/null +++ b/arch/mips/include/asm/exec.h @@ -0,0 +1,17 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics + * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#ifndef _ASM_EXEC_H +#define _ASM_EXEC_H + +extern unsigned long arch_align_stack(unsigned long sp); + +#endif /* _ASM_EXEC_H */ diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h index 59f5b55..ba4cf0e 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h +++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h @@ -33,7 +33,6 @@ #include /* need byte IO */ #include /* And spinlocks */ #include -#include #define NUM_AU1000_DMA_CHANNELS 8 diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index c104f10..20e9dcf 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -19,7 +19,6 @@ #include #include #include -#include /* * Return current * instruction pointer ("program counter"). @@ -356,6 +355,12 @@ unsigned long get_wchan(struct task_struct *p); #define ARCH_HAS_PREFETCHW #define prefetchw(x) __builtin_prefetch((x), 1, 1) +/* + * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP + * systems. + */ +#define __ARCH_WANT_UNLOCKED_CTXSW + #endif #endif /* _ASM_PROCESSOR_H */ diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index 50511aa..6dce6d8 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -5,6 +5,17 @@ #ifdef __KERNEL__ extern void setup_early_printk(void); + +extern void set_handler(unsigned long offset, void *addr, unsigned long len); +extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); + +typedef void (*vi_handler_t)(void); +extern void *set_vi_handler(int n, vi_handler_t addr); + +extern void *set_except_vector(int n, void *addr); +extern unsigned long ebase; +extern void per_cpu_trap_init(void); + #endif /* __KERNEL__ */ #endif /* __SETUP_H */ diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h new file mode 100644 index 0000000..5d33621 --- /dev/null +++ b/arch/mips/include/asm/switch_to.h @@ -0,0 +1,85 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics + * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#ifndef _ASM_SWITCH_TO_H +#define _ASM_SWITCH_TO_H + +#include +#include +#include + +struct task_struct; + +/* + * switch_to(n) should switch tasks to task nr n, first + * checking that n isn't the current task, in which case it does nothing. + */ +extern asmlinkage void *resume(void *last, void *next, void *next_ti); + +extern unsigned int ll_bit; +extern struct task_struct *ll_task; + +#ifdef CONFIG_MIPS_MT_FPAFF + +/* + * Handle the scheduler resume end of FPU affinity management. We do this + * inline to try to keep the overhead down. If we have been forced to run on + * a "CPU" with an FPU because of a previous high level of FP computation, + * but did not actually use the FPU during the most recent time-slice (CU1 + * isn't set), we undo the restriction on cpus_allowed. + * + * We're not calling set_cpus_allowed() here, because we have no need to + * force prompt migration - we're already switching the current CPU to a + * different thread. + */ + +#define __mips_mt_fpaff_switch_to(prev) \ +do { \ + struct thread_info *__prev_ti = task_thread_info(prev); \ + \ + if (cpu_has_fpu && \ + test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \ + (!(KSTK_STATUS(prev) & ST0_CU1))) { \ + clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \ + prev->cpus_allowed = prev->thread.user_cpus_allowed; \ + } \ + next->thread.emulated_fp = 0; \ +} while(0) + +#else +#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) +#endif + +#define __clear_software_ll_bit() \ +do { \ + if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \ + ll_bit = 0; \ +} while (0) + +#define switch_to(prev, next, last) \ +do { \ + __mips_mt_fpaff_switch_to(prev); \ + if (cpu_has_dsp) \ + __save_dsp(prev); \ + __clear_software_ll_bit(); \ + (last) = resume(prev, next, task_thread_info(next)); \ +} while (0) + +#define finish_arch_switch(prev) \ +do { \ + if (cpu_has_dsp) \ + __restore_dsp(current); \ + if (cpu_has_userlocal) \ + write_c0_userlocal(current_thread_info()->tp_value); \ + __restore_watch(); \ +} while (0) + +#endif /* _ASM_SWITCH_TO_H */ diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index 6018c80..a7f4057 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -1,235 +1,5 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle - * Copyright (C) 1996 by Paul M. Antoine - * Copyright (C) 1999 Silicon Graphics - * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. - */ -#ifndef _ASM_SYSTEM_H -#define _ASM_SYSTEM_H - -#include -#include -#include - -#include +/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */ #include #include -#include -#include -#include -#include - - -/* - * switch_to(n) should switch tasks to task nr n, first - * checking that n isn't the current task, in which case it does nothing. - */ -extern asmlinkage void *resume(void *last, void *next, void *next_ti); - -struct task_struct; - -extern unsigned int ll_bit; -extern struct task_struct *ll_task; - -#ifdef CONFIG_MIPS_MT_FPAFF - -/* - * Handle the scheduler resume end of FPU affinity management. We do this - * inline to try to keep the overhead down. If we have been forced to run on - * a "CPU" with an FPU because of a previous high level of FP computation, - * but did not actually use the FPU during the most recent time-slice (CU1 - * isn't set), we undo the restriction on cpus_allowed. - * - * We're not calling set_cpus_allowed() here, because we have no need to - * force prompt migration - we're already switching the current CPU to a - * different thread. - */ - -#define __mips_mt_fpaff_switch_to(prev) \ -do { \ - struct thread_info *__prev_ti = task_thread_info(prev); \ - \ - if (cpu_has_fpu && \ - test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \ - (!(KSTK_STATUS(prev) & ST0_CU1))) { \ - clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \ - prev->cpus_allowed = prev->thread.user_cpus_allowed; \ - } \ - next->thread.emulated_fp = 0; \ -} while(0) - -#else -#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) -#endif - -#define __clear_software_ll_bit() \ -do { \ - if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \ - ll_bit = 0; \ -} while (0) - -#define switch_to(prev, next, last) \ -do { \ - __mips_mt_fpaff_switch_to(prev); \ - if (cpu_has_dsp) \ - __save_dsp(prev); \ - __clear_software_ll_bit(); \ - (last) = resume(prev, next, task_thread_info(next)); \ -} while (0) - -#define finish_arch_switch(prev) \ -do { \ - if (cpu_has_dsp) \ - __restore_dsp(current); \ - if (cpu_has_userlocal) \ - write_c0_userlocal(current_thread_info()->tp_value); \ - __restore_watch(); \ -} while (0) - -static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) -{ - __u32 retval; - - smp_mb__before_llsc(); - - if (kernel_uses_llsc && R10000_LLSC_WAR) { - unsigned long dummy; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %3 # xchg_u32 \n" - " .set mips0 \n" - " move %2, %z4 \n" - " .set mips3 \n" - " sc %2, %1 \n" - " beqzl %2, 1b \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } else if (kernel_uses_llsc) { - unsigned long dummy; - - do { - __asm__ __volatile__( - " .set mips3 \n" - " ll %0, %3 # xchg_u32 \n" - " .set mips0 \n" - " move %2, %z4 \n" - " .set mips3 \n" - " sc %2, %1 \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } while (unlikely(!dummy)); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - *m = val; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_llsc_mb(); - - return retval; -} - -#ifdef CONFIG_64BIT -static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) -{ - __u64 retval; - - smp_mb__before_llsc(); - - if (kernel_uses_llsc && R10000_LLSC_WAR) { - unsigned long dummy; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %3 # xchg_u64 \n" - " move %2, %z4 \n" - " scd %2, %1 \n" - " beqzl %2, 1b \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } else if (kernel_uses_llsc) { - unsigned long dummy; - - do { - __asm__ __volatile__( - " .set mips3 \n" - " lld %0, %3 # xchg_u64 \n" - " move %2, %z4 \n" - " scd %2, %1 \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } while (unlikely(!dummy)); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - *m = val; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_llsc_mb(); - - return retval; -} -#else -extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val); -#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels -#endif - -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - switch (size) { - case 4: - return __xchg_u32(ptr, x); - case 8: - return __xchg_u64(ptr, x); - } - - return x; -} - -#define xchg(ptr, x) \ -({ \ - BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \ - \ - ((__typeof__(*(ptr))) \ - __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \ -}) - -extern void set_handler(unsigned long offset, void *addr, unsigned long len); -extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); - -typedef void (*vi_handler_t)(void); -extern void *set_vi_handler(int n, vi_handler_t addr); - -extern void *set_except_vector(int n, void *addr); -extern unsigned long ebase; -extern void per_cpu_trap_init(void); - -/* - * See include/asm-ia64/system.h; prevents deadlock on SMP - * systems. - */ -#define __ARCH_WANT_UNLOCKED_CTXSW - -extern unsigned long arch_align_stack(unsigned long sp); - -#endif /* _ASM_SYSTEM_H */ +#include +#include diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h index a409c44..8808d7f 100644 --- a/arch/mips/include/asm/txx9/jmr3927.h +++ b/arch/mips/include/asm/txx9/jmr3927.h @@ -12,7 +12,6 @@ #include #include -#include #include /* CS */ diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c index f305ca1..bc794f7 100644 --- a/arch/mips/kernel/cpu-bugs64.c +++ b/arch/mips/kernel/cpu-bugs64.c @@ -16,7 +16,6 @@ #include #include #include -#include static char bug64hit[] __initdata = "reliable operation impossible!\n%s"; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0bab464..5099201 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index a8a8977..b0662cf 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c @@ -16,7 +16,6 @@ #include #include -#include static inline void unmask_rm7k_irq(struct irq_data *d) { diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index 38874a4..1282b9a 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c @@ -17,7 +17,6 @@ #include #include -#include static inline void unmask_rm9k_irq(struct irq_data *d) { diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 7f50318..a5aa43d 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -23,7 +23,6 @@ #include #include -#include #include #ifdef CONFIG_KGDB diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 191eb52..972263b 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -35,7 +35,6 @@ #include #include #include -#include static inline void unmask_mips_irq(struct irq_data *d) { diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c index c23d11f..7f3376b 100644 --- a/arch/mips/kernel/mips-mt.c +++ b/arch/mips/kernel/mips-mt.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 7955409..5bfaea8 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 7786b60..7c24c29 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index 32644b4..a3b0178 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index a9d801d..b8c18dc 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 058e964..c504b21 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -31,7 +31,6 @@ #include #include #include -#include #include struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index f852400..185ca00 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "signal-common.h" diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index aae9866..e5ee38e 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index ee24d81..ae29e89 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index d5e950a..ca67356 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index fe30951..e7e03ec 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ce9e286..ff17868 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 32c1e95..a37b082 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/kernel/smtc-proc.c b/arch/mips/kernel/smtc-proc.c index 928a5a6..145771c 100644 --- a/arch/mips/kernel/smtc-proc.c +++ b/arch/mips/kernel/smtc-proc.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 0a42ff3..c4f75bb 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 1821d12..6af08d8 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index d027657..b08220c 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -37,6 +37,7 @@ #include #include #include +#include /* * For historic reasons the pipe(2) syscall on MIPS has an unusual calling diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d79ae54..cfdaaa4 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -45,7 +45,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index aedb894..9c58bdf 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -85,7 +85,6 @@ #include #include #include -#include #define STR(x) __STR(x) #define __STR(x) #x diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index bfa12a4..f6f9152 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -49,7 +49,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c index b1e7a89..e21f0b9 100644 --- a/arch/mips/lasat/reset.c +++ b/arch/mips/lasat/reset.c @@ -21,7 +21,6 @@ #include #include -#include #include #include "picvue.h" diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 3c4a8c5..384a3b0 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mipssim/sim_smtc.c b/arch/mips/mipssim/sim_smtc.c index 9150639..3c104ab 100644 --- a/arch/mips/mipssim/sim_smtc.c +++ b/arch/mips/mipssim/sim_smtc.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index cf7895d..1f9ca07 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 0765583..031c4c2 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 4f9eb0b..f62d64f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include /* for run_uncached() */ diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index a43c197c..87d23ca 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 69ebd58..c14f6df 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -22,7 +22,6 @@ #include #include -#include #include #include #include /* For VMALLOC_END */ diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 36272f7..cc0b626 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c index a6bd11f..1eb708e 100644 --- a/arch/mips/mm/sc-ip22.c +++ b/arch/mips/mm/sc-ip22.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 9cca8de..93d937b 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mm/sc-r5k.c b/arch/mips/mm/sc-r5k.c index ae1e533..8d90ff2 100644 --- a/arch/mips/mm/sc-r5k.c +++ b/arch/mips/mm/sc-r5k.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index ed1fa46..a63d1ed 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 2dc6253..d2572cb 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -18,7 +18,6 @@ #include #include #include -#include #include extern void build_tlb_refill_handler(void); diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c index 3d95f76..91c2499 100644 --- a/arch/mips/mm/tlb-r8k.c +++ b/arch/mips/mm/tlb-r8k.c @@ -17,7 +17,6 @@ #include #include #include -#include extern void build_tlb_refill_handler(void); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index e06370f..0bc485b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * TLB load/store/modify handlers. diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 4b988b9..27a6cdb 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c index 49a4f6c..e52bfcb 100644 --- a/arch/mips/netlogic/common/irq.c +++ b/arch/mips/netlogic/common/irq.c @@ -43,7 +43,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c index c4fa2d7..2e6f7ca 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c @@ -16,7 +16,6 @@ #include #include -#include #include #include diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c index 98fd009..598b6a6 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c @@ -16,7 +16,6 @@ #include #include -#include #include #include diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c index 5bbcc47..83a1c5e 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c @@ -16,7 +16,6 @@ #include #include -#include #include #include diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c index 25bbbf4..6590812 100644 --- a/arch/mips/pmc-sierra/yosemite/irq.c +++ b/arch/mips/pmc-sierra/yosemite/irq.c @@ -44,7 +44,6 @@ #include #include #include -#include #include /* Hypertransport specific */ diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c index dcc926e..6a2754c 100644 --- a/arch/mips/pmc-sierra/yosemite/prom.c +++ b/arch/mips/pmc-sierra/yosemite/prom.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c index 7fb97fb..fa9ae95 100644 --- a/arch/mips/powertv/asic/irq_asic.c +++ b/arch/mips/powertv/asic/irq_asic.c @@ -17,7 +17,6 @@ #include #include -#include #include diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c index 8355228..1cf5abb 100644 --- a/arch/mips/powertv/init.c +++ b/arch/mips/powertv/init.c @@ -26,7 +26,6 @@ #include #include -#include #include #include diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c index 7c6db74..f298430 100644 --- a/arch/mips/rb532/irq.c +++ b/arch/mips/rb532/irq.c @@ -42,7 +42,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/sgi-ip22/ip22-berr.c b/arch/mips/sgi-ip22/ip22-berr.c index 911d399..3f6ccd5 100644 --- a/arch/mips/sgi-ip22/ip22-berr.c +++ b/arch/mips/sgi-ip22/ip22-berr.c @@ -9,7 +9,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c index 45b6694..20363d2 100644 --- a/arch/mips/sgi-ip22/ip22-reset.c +++ b/arch/mips/sgi-ip22/ip22-reset.c @@ -18,7 +18,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip22/ip28-berr.c b/arch/mips/sgi-ip22/ip28-berr.c index 88c684e..0626555 100644 --- a/arch/mips/sgi-ip22/ip28-berr.c +++ b/arch/mips/sgi-ip22/ip28-berr.c @@ -11,7 +11,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 2364223..69a939a 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/sgi-ip27/ip27-reset.c b/arch/mips/sgi-ip27/ip27-reset.c index c170761..f347bc6 100644 --- a/arch/mips/sgi-ip27/ip27-reset.c +++ b/arch/mips/sgi-ip27/ip27-reset.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index a092860..e7d5054 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index 9b95d80..1f823da 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 09740d6..215713e 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index 48853ab..e8c4538 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -53,7 +53,6 @@ #define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT #endif -#include #include #define SBPROF_TB_MAJOR 240 diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c index 45274bd..86e6e54 100644 --- a/arch/mips/sibyte/sb1250/bus_watcher.c +++ b/arch/mips/sibyte/sb1250/bus_watcher.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 76ee045..340aaf6 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -26,7 +26,6 @@ #include #include -#include #include #include diff --git a/arch/mips/sni/reset.c b/arch/mips/sni/reset.c index 79f8d70..244f942 100644 --- a/arch/mips/sni/reset.c +++ b/arch/mips/sni/reset.c @@ -5,7 +5,6 @@ */ #include #include -#include #include /* diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index fad2bef..ae0e4ee 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c @@ -22,7 +22,6 @@ #include #include -#include #include typedef struct irq_cascade { diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index 692b4e8..9fbf5f0 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -30,7 +30,6 @@ #include #include #include -#include #define PMU_TYPE1_BASE 0x0b0000a0UL #define PMU_TYPE1_SIZE 0x0eUL From hauke@hauke-m.de Thu Mar 15 23:40:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 23:40:32 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:33494 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903667Ab2COWk1 (ORCPT ); Thu, 15 Mar 2012 23:40:27 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 545D18F61; Thu, 15 Mar 2012 23:40:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2BR6SpsGM2ey; Thu, 15 Mar 2012 23:40:12 +0100 (CET) Received: from [192.168.1.195] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 6EA078F60; Thu, 15 Mar 2012 23:40:12 +0100 (CET) Message-ID: <4F626FCB.6010103@hauke-m.de> Date: Thu, 15 Mar 2012 23:40:11 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Greg KH CC: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org Subject: Re: [PATCH v4 4/7] USB: Add driver for the bcma bus References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> <1331597093-425-5-git-send-email-hauke@hauke-m.de> <20120315194426.GA30682@kroah.com> In-Reply-To: <20120315194426.GA30682@kroah.com> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32716 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1071 Lines: 27 On 03/15/2012 08:44 PM, Greg KH wrote: > On Tue, Mar 13, 2012 at 01:04:50AM +0100, Hauke Mehrtens wrote: >> This adds a USB driver using the generic platform device driver for the >> USB controller found on the Broadcom bcma bus. The bcma bus just >> exposes one device which serves the OHCI and the EHCI controller at the >> same time. This driver probes for this USB controller and creates and >> registers two new platform devices which will be probed by the new >> generic platform device driver. This makes it possible to use the EHCI >> and the OCHI controller on the bcma bus at the same time. >> >> Signed-off-by: Hauke Mehrtens >> --- >> drivers/usb/host/Kconfig | 12 ++ > > This patch fails to apply here, and I can't seem to figure out what tree > you made this against to fix it up by hand on my end. > > Any thoughts? > > greg k-h This patch was against git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git#master, but I will rebase it onto usb/usb-next and send a new version of the patches you have not applied. Hauke From hauke@hauke-m.de Thu Mar 15 23:43:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 23:43:50 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:33530 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903667Ab2COWno (ORCPT ); Thu, 15 Mar 2012 23:43:44 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 2C9BF8F61; Thu, 15 Mar 2012 23:43:44 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xxu-Z8z3IgFW; Thu, 15 Mar 2012 23:43:31 +0100 (CET) Received: from [192.168.1.195] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id C11F48F60; Thu, 15 Mar 2012 23:43:30 +0100 (CET) Message-ID: <4F627092.7030207@hauke-m.de> Date: Thu, 15 Mar 2012 23:43:30 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Greg KH , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= CC: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org Subject: Re: [PATCH v4 3/7] bcma: scan for extra address space References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> <1331597093-425-4-git-send-email-hauke@hauke-m.de> <20120315194453.GB30682@kroah.com> In-Reply-To: <20120315194453.GB30682@kroah.com> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32717 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1056 Lines: 32 On 03/15/2012 08:44 PM, Greg KH wrote: > On Tue, Mar 13, 2012 at 01:04:49AM +0100, Hauke Mehrtens wrote: >> Some cores like the USB core have two address spaces. In the USB host >> controller one address space is used for the OHCI and the other for the >> EHCI controller interface. The USB controller is the only core I found >> with two address spaces. This code is based on the AI scan function >> ai_scan() in shared/aiutils.c in the Broadcom SDK. >> >> CC: RafaÅ‚ MiÅ‚ecki >> CC: linux-wireless@vger.kernel.org >> Signed-off-by: Hauke Mehrtens >> --- >> drivers/bcma/scan.c | 19 ++++++++++++++++++- >> include/linux/bcma/bcma.h | 1 + >> 2 files changed, 19 insertions(+), 1 deletions(-) > > Is this required for the 4/7 patch? > > If so, can I get an ack from the BCMA developers so that I can take this > through the USB tree? > > thanks, > > greg k-h Hi RafaÅ‚, could you give me an ack for this patch please. This patch is only required for the patch "Add driver for the bcma bus". Hauke From hauke@hauke-m.de Thu Mar 15 23:50:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 23:50:50 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:33575 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903667Ab2COWuq (ORCPT ); Thu, 15 Mar 2012 23:50:46 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 7F11F8F65; Thu, 15 Mar 2012 23:50:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AJ+W3vlcsmsJ; Thu, 15 Mar 2012 23:50:32 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id AE9438F60; Thu, 15 Mar 2012 23:50:31 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, zajec5@gmail.com, Hauke Mehrtens Subject: [PATCH v5 0/4] USB: OHCI/EHCI: generic platform driver Date: Thu, 15 Mar 2012 23:49:55 +0100 Message-Id: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32718 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2340 Lines: 62 This EHCI/OHCI platform driver should replace the simple EHCI and OHCI platform drivers. It was developed to be used for the USB core of the Broadcom SoCs supported by ssb and bcma, but it should also work for other devices. Drivers like ehci-ath79.c, ehci-xls.c and ehci-ixp4xx.c should be relative easy be ported to this EHCI driver. And drivers like ohci-ath79.c, ohci-ppc-soc.c, ohci-sh.c and ohci-xls.c should be easy be ported to the this OHCI driver. I am unable to test the suspend and resume part, as my SoC does not support this, but most of the platform driver do not support suspend/resume too. The code here should work, but was never runtime tested. This also contains patches adding USB support for the SoCs based on ssb and bcma and converts the ath79 code to use the generic usb driver. This patch series is based on the usb tree and should go through it to Linus. v5: * removed the patches already applied to usb/usb-next * rebase onto usb/usb-next v4: * handle error when searching for a bridge on bcma * leave old Kconfig options and mark them deprecated and select the new driver v3: * add patches for bcma and ssb usb driver again * add patch to convert ath79 to use the generic platform driver v2: * split include/linux/usb/hci_driver.h into include/linux /usb/ehci_pdriver.h and include/linux/usb/ohci_pdriver.h * remove flags from include/linux/usb/{e,o}ehci_pdriver.h * add kernel doc * add some more options into the structs to activate hardware quirks. Hauke Mehrtens (4): bcma: scan for extra address space USB: Add driver for the bcma bus USB: Add driver for the ssb bus USB: OHCI: remove old SSB OHCI driver drivers/bcma/scan.c | 19 +++- drivers/usb/host/Kconfig | 31 ++++- drivers/usb/host/Makefile | 2 + drivers/usb/host/bcma-hcd.c | 334 +++++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ohci-hcd.c | 21 +--- drivers/usb/host/ohci-ssb.c | 260 --------------------------------- drivers/usb/host/ssb-hcd.c | 279 ++++++++++++++++++++++++++++++++++++ include/linux/bcma/bcma.h | 1 + 8 files changed, 665 insertions(+), 282 deletions(-) create mode 100644 drivers/usb/host/bcma-hcd.c delete mode 100644 drivers/usb/host/ohci-ssb.c create mode 100644 drivers/usb/host/ssb-hcd.c -- 1.7.5.4 From hauke@hauke-m.de Thu Mar 15 23:50:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 23:51:18 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:33583 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903681Ab2COWus (ORCPT ); Thu, 15 Mar 2012 23:50:48 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id C46568F60; Thu, 15 Mar 2012 23:50:47 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IH7-UDZGRdTd; Thu, 15 Mar 2012 23:50:32 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 26E0E8F61; Thu, 15 Mar 2012 23:50:32 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, zajec5@gmail.com, Hauke Mehrtens Subject: [PATCH v5 1/4] bcma: scan for extra address space Date: Thu, 15 Mar 2012 23:49:56 +0100 Message-Id: <1331851799-5968-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> References: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32719 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1915 Lines: 66 Some cores like the USB core have two address spaces. In the USB host controller one address space is used for the OHCI and the other for the EHCI controller interface. The USB controller is the only core I found with two address spaces. This code is based on the AI scan function ai_scan() in shared/aiutils.c in the Broadcom SDK. CC: RafaÅ‚ MiÅ‚ecki CC: linux-wireless@vger.kernel.org Signed-off-by: Hauke Mehrtens --- drivers/bcma/scan.c | 19 ++++++++++++++++++- include/linux/bcma/bcma.h | 1 + 2 files changed, 19 insertions(+), 1 deletions(-) diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c index 3a2f672..1fa10ed 100644 --- a/drivers/bcma/scan.c +++ b/drivers/bcma/scan.c @@ -286,6 +286,23 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, return -EILSEQ; } + /* First Slave Address Descriptor should be port 0: + * the main register space for the core + */ + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); + if (tmp <= 0) { + /* Try again to see if it is a bridge */ + tmp = bcma_erom_get_addr_desc(bus, eromptr, + SCAN_ADDR_TYPE_BRIDGE, 0); + if (tmp <= 0) { + return -EILSEQ; + } else { + pr_info("Bridge found\n"); + return -ENXIO; + } + } + core->addr = tmp; + /* get & parse slave ports */ for (i = 0; i < ports[1]; i++) { for (j = 0; ; j++) { @@ -298,7 +315,7 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, break; } else { if (i == 0 && j == 0) - core->addr = tmp; + core->addr1 = tmp; } } } diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 83c209f..7fe41e1 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -138,6 +138,7 @@ struct bcma_device { u8 core_index; u32 addr; + u32 addr1; u32 wrap; void __iomem *io_addr; -- 1.7.5.4 From hauke@hauke-m.de Thu Mar 15 23:51:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 23:51:42 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:33603 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903680Ab2COWvC (ORCPT ); Thu, 15 Mar 2012 23:51:02 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 746808F67; Thu, 15 Mar 2012 23:51:02 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kKmewYmtZ4N1; Thu, 15 Mar 2012 23:50:46 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 9AC7F8F62; Thu, 15 Mar 2012 23:50:32 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, zajec5@gmail.com, Hauke Mehrtens Subject: [PATCH v5 2/4] USB: Add driver for the bcma bus Date: Thu, 15 Mar 2012 23:49:57 +0100 Message-Id: <1331851799-5968-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> References: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32720 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 10494 Lines: 388 This adds a USB driver using the generic platform device driver for the USB controller found on the Broadcom bcma bus. The bcma bus just exposes one device which serves the OHCI and the EHCI controller at the same time. This driver probes for this USB controller and creates and registers two new platform devices which will be probed by the new generic platform device driver. This makes it possible to use the EHCI and the OCHI controller on the bcma bus at the same time. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 12 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/bcma-hcd.c | 334 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 347 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/bcma-hcd.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index f788eb8..57d16b1 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -638,3 +638,15 @@ config USB_OCTEON_OHCI config USB_OCTEON2_COMMON bool default y if USB_OCTEON_EHCI || USB_OCTEON_OHCI + +config USB_HCD_BCMA + tristate "BCMA usb host driver" + depends on BCMA && EXPERIMENTAL + select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD + select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD + help + Enbale support for the EHCI and OCHI host controller on an bcma bus. + It converts the bcma driver into two platform device drivers + for ehci and ohci. + + If unsure, say N. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 0982bcc..11b3de0 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -41,3 +41,4 @@ obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o obj-$(CONFIG_MIPS_ALCHEMY) += alchemy-common.o +obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o diff --git a/drivers/usb/host/bcma-hcd.c b/drivers/usb/host/bcma-hcd.c new file mode 100644 index 0000000..afec047 --- /dev/null +++ b/drivers/usb/host/bcma-hcd.c @@ -0,0 +1,334 @@ +/* + * Broadcom specific Advanced Microcontroller Bus + * Broadcom USB-core driver (BCMA bus glue) + * + * Copyright 2011-2012 Hauke Mehrtens + * + * Based on ssb-ohci driver + * Copyright 2007 Michael Buesch + * + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Derived from the USBcore related parts of Broadcom-SB + * Copyright 2005-2011 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include +#include +#include +#include +#include + +MODULE_AUTHOR("Hauke Mehrtens"); +MODULE_DESCRIPTION("Common USB driver for BCMA Bus"); +MODULE_LICENSE("GPL"); + +struct bcma_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; +}; + +/* Wait for bitmask in a register to get set or cleared. + * timeout is in units of ten-microseconds. + */ +static int bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask, + int timeout) +{ + int i; + u32 val; + + for (i = 0; i < timeout; i++) { + val = bcma_read32(dev, reg); + if ((val & bitmask) == bitmask) + return 0; + udelay(10); + } + + return -ETIMEDOUT; +} + +static void __devinit bcma_hcd_4716wa(struct bcma_device *dev) +{ +#ifdef CONFIG_BCMA_DRIVER_MIPS + /* Work around for 4716 failures. */ + if (dev->bus->chipinfo.id == 0x4716) { + u32 tmp; + + tmp = bcma_cpu_clock(&dev->bus->drv_mips); + if (tmp >= 480000000) + tmp = 0x1846b; /* set CDR to 0x11(fast) */ + else if (tmp == 453000000) + tmp = 0x1046b; /* set CDR to 0x10(slow) */ + else + tmp = 0; + + /* Change Shim mdio control reg to fix host not acking at + * high frequencies + */ + if (tmp) { + bcma_write32(dev, 0x524, 0x1); /* write sel to enable */ + udelay(500); + + bcma_write32(dev, 0x524, tmp); + udelay(500); + bcma_write32(dev, 0x524, 0x4ab); + udelay(500); + bcma_read32(dev, 0x528); + bcma_write32(dev, 0x528, 0x80000000); + } + } +#endif /* CONFIG_BCMA_DRIVER_MIPS */ +} + +/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ +static void __devinit bcma_hcd_init_chip(struct bcma_device *dev) +{ + u32 tmp; + + /* + * USB 2.0 special considerations: + * + * 1. Since the core supports both OHCI and EHCI functions, it must + * only be reset once. + * + * 2. In addition to the standard SI reset sequence, the Host Control + * Register must be programmed to bring the USB core and various + * phy components out of reset. + */ + if (!bcma_core_is_enabled(dev)) { + bcma_core_enable(dev, 0); + mdelay(10); + if (dev->id.rev >= 5) { + /* Enable Misc PLL */ + tmp = bcma_read32(dev, 0x1e0); + tmp |= 0x100; + bcma_write32(dev, 0x1e0, tmp); + if (bcma_wait_bits(dev, 0x1e0, 1 << 24, 100)) + printk(KERN_EMERG "Failed to enable misc PPL!\n"); + + /* Take out of resets */ + bcma_write32(dev, 0x200, 0x4ff); + udelay(25); + bcma_write32(dev, 0x200, 0x6ff); + udelay(25); + + /* Make sure digital and AFE are locked in USB PHY */ + bcma_write32(dev, 0x524, 0x6b); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0xab); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0x2b); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0x10ab); + udelay(50); + tmp = bcma_read32(dev, 0x524); + + if (bcma_wait_bits(dev, 0x528, 0xc000, 10000)) { + tmp = bcma_read32(dev, 0x528); + printk(KERN_EMERG + "USB20H mdio_rddata 0x%08x\n", tmp); + } + bcma_write32(dev, 0x528, 0x80000000); + tmp = bcma_read32(dev, 0x314); + udelay(265); + bcma_write32(dev, 0x200, 0x7ff); + udelay(10); + + /* Take USB and HSIC out of non-driving modes */ + bcma_write32(dev, 0x510, 0); + } else { + bcma_write32(dev, 0x200, 0x7ff); + + udelay(1); + } + + bcma_hcd_4716wa(dev); + } +} + +static const struct usb_ehci_pdata ehci_pdata = { +}; + +static const struct usb_ohci_pdata ohci_pdata = { +}; + +static struct platform_device * __devinit +bcma_hcd_create_pdev(struct bcma_device *dev, bool ohci, u32 addr) +{ + struct platform_device *hci_dev; + struct resource hci_res[2]; + int ret = -ENOMEM; + + memset(hci_res, 0, sizeof(hci_res)); + + hci_res[0].start = addr; + hci_res[0].end = hci_res[0].start + 0x1000 - 1; + hci_res[0].flags = IORESOURCE_MEM; + + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + + hci_dev = platform_device_alloc(ohci ? "ohci-platform" : + "ehci-platform" , 0); + if (!hci_dev) + return NULL; + + hci_dev->dev.parent = &dev->dev; + hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask; + + ret = platform_device_add_resources(hci_dev, hci_res, + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; + if (ohci) + ret = platform_device_add_data(hci_dev, &ohci_pdata, + sizeof(ohci_pdata)); + else + ret = platform_device_add_data(hci_dev, &ehci_pdata, + sizeof(ehci_pdata)); + if (ret) + goto err_alloc; + ret = platform_device_add(hci_dev); + if (ret) + goto err_alloc; + + return hci_dev; + +err_alloc: + platform_device_put(hci_dev); + return ERR_PTR(ret); +} + +static int __devinit bcma_hcd_probe(struct bcma_device *dev) +{ + int err; + u16 chipid_top; + u32 ohci_addr; + struct bcma_hcd_device *usb_dev; + struct bcma_chipinfo *chipinfo; + + chipinfo = &dev->bus->chipinfo; + /* USBcores are only connected on embedded devices. */ + chipid_top = (chipinfo->id & 0xFF00); + if (chipid_top != 0x4700 && chipid_top != 0x5300) + return -ENODEV; + + /* TODO: Probably need checks here; is the core connected? */ + + if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + + usb_dev = kzalloc(sizeof(struct bcma_hcd_device), GFP_KERNEL); + if (!usb_dev) + return -ENOMEM; + + bcma_hcd_init_chip(dev); + + /* In AI chips EHCI is addrspace 0, OHCI is 1 */ + ohci_addr = dev->addr1; + if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749) + && chipinfo->rev == 0) + ohci_addr = 0x18009000; + + usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, true, ohci_addr); + if (IS_ERR(usb_dev->ohci_dev)) { + err = PTR_ERR(usb_dev->ohci_dev); + goto err_free_usb_dev; + } + + usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, false, dev->addr); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; + } + + bcma_set_drvdata(dev, usb_dev); + return 0; + +err_unregister_ohci_dev: + platform_device_unregister(usb_dev->ohci_dev); +err_free_usb_dev: + kfree(usb_dev); + return err; +} + +static void __devexit bcma_hcd_remove(struct bcma_device *dev) +{ + struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); + struct platform_device *ohci_dev = usb_dev->ohci_dev; + struct platform_device *ehci_dev = usb_dev->ehci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); + + bcma_core_disable(dev, 0); +} + +static void bcma_hcd_shutdown(struct bcma_device *dev) +{ + bcma_core_disable(dev, 0); +} + +#ifdef CONFIG_PM + +static int bcma_hcd_suspend(struct bcma_device *dev, pm_message_t state) +{ + bcma_core_disable(dev, 0); + + return 0; +} + +static int bcma_hcd_resume(struct bcma_device *dev) +{ + bcma_core_enable(dev, 0); + + return 0; +} + +#else /* !CONFIG_PM */ +#define bcma_hcd_suspend NULL +#define bcma_hcd_resume NULL +#endif /* CONFIG_PM */ + +static const struct bcma_device_id bcma_hcd_table[] __devinitconst = { + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS), + BCMA_CORETABLE_END +}; +MODULE_DEVICE_TABLE(bcma, bcma_hcd_table); + +static struct bcma_driver bcma_hcd_driver = { + .name = KBUILD_MODNAME, + .id_table = bcma_hcd_table, + .probe = bcma_hcd_probe, + .remove = __devexit_p(bcma_hcd_remove), + .shutdown = bcma_hcd_shutdown, + .suspend = bcma_hcd_suspend, + .resume = bcma_hcd_resume, +}; + +static int __init bcma_hcd_init(void) +{ + return bcma_driver_register(&bcma_hcd_driver); +} +module_init(bcma_hcd_init); + +static void __exit bcma_hcd_exit(void) +{ + bcma_driver_unregister(&bcma_hcd_driver); +} +module_exit(bcma_hcd_exit); -- 1.7.5.4 From hauke@hauke-m.de Thu Mar 15 23:51:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 23:52:07 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:33608 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903706Ab2COWvE (ORCPT ); Thu, 15 Mar 2012 23:51:04 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 7D0BD8F60; Thu, 15 Mar 2012 23:51:04 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CzLCxeTWm-0g; Thu, 15 Mar 2012 23:50:48 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 0CADF8F63; Thu, 15 Mar 2012 23:50:33 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, zajec5@gmail.com, Hauke Mehrtens Subject: [PATCH v5 3/4] USB: Add driver for the ssb bus Date: Thu, 15 Mar 2012 23:49:58 +0100 Message-Id: <1331851799-5968-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> References: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9403 Lines: 337 This adds a USB driver using the generic platform device driver for the USB controller found on the Broadcom ssb bus. The ssb bus just exposes one device which serves the OHCI and the EHCI controller at the same time. This driver probes for this USB controller and creates and registers two new platform devices which will be probed by the new generic platform device driver. This makes it possible to use the EHCI and the OCHI controller on the ssb bus at the same time. The old ssb OHCI USB driver will be removed in the next step as this driver also provide an OHCI driver and an EHCI for the cores supporting it. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 12 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ssb-hcd.c | 279 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 292 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ssb-hcd.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 57d16b1..2fc5637 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -650,3 +650,15 @@ config USB_HCD_BCMA for ehci and ohci. If unsure, say N. + +config USB_HCD_SSB + tristate "SSB usb host driver" + depends on SSB && EXPERIMENTAL + select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD + select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD + help + Enbale support for the EHCI and OCHI host controller on an bcma bus. + It converts the bcma driver into two platform device drivers + for ehci and ohci. + + If unsure, say N. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 11b3de0..9e0a89c 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -42,3 +42,4 @@ obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o obj-$(CONFIG_MIPS_ALCHEMY) += alchemy-common.o obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o +obj-$(CONFIG_USB_HCD_SSB) += ssb-hcd.o diff --git a/drivers/usb/host/ssb-hcd.c b/drivers/usb/host/ssb-hcd.c new file mode 100644 index 0000000..c2e7343 --- /dev/null +++ b/drivers/usb/host/ssb-hcd.c @@ -0,0 +1,279 @@ +/* + * Sonics Silicon Backplane + * Broadcom USB-core driver (SSB bus glue) + * + * Copyright 2011-2012 Hauke Mehrtens + * + * Based on ssb-ohci driver + * Copyright 2007 Michael Buesch + * + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Derived from the USBcore related parts of Broadcom-SB + * Copyright 2005-2011 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include +#include +#include +#include +#include + +MODULE_AUTHOR("Hauke Mehrtens"); +MODULE_DESCRIPTION("Common USB driver for SSB Bus"); +MODULE_LICENSE("GPL"); + +#define SSB_HCD_TMSLOW_HOSTMODE (1 << 29) + +struct ssb_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; + + u32 enable_flags; +}; + +static void __devinit ssb_hcd_5354wa(struct ssb_device *dev) +{ +#ifdef CONFIG_SSB_DRIVER_MIPS + /* Work around for 5354 failures */ + if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { + /* Change syn01 reg */ + ssb_write32(dev, 0x894, 0x00fe00fe); + + /* Change syn03 reg */ + ssb_write32(dev, 0x89c, ssb_read32(dev, 0x89c) | 0x1); + } +#endif +} + +static void __devinit ssb_hcd_usb20wa(struct ssb_device *dev) +{ + if (dev->id.coreid == SSB_DEV_USB20_HOST) { + /* + * USB 2.0 special considerations: + * + * In addition to the standard SSB reset sequence, the Host + * Control Register must be programmed to bring the USB core + * and various phy components out of reset. + */ + ssb_write32(dev, 0x200, 0x7ff); + + /* Change Flush control reg */ + ssb_write32(dev, 0x400, ssb_read32(dev, 0x400) & ~8); + ssb_read32(dev, 0x400); + + /* Change Shim control reg */ + ssb_write32(dev, 0x304, ssb_read32(dev, 0x304) & ~0x100); + ssb_read32(dev, 0x304); + + udelay(1); + + ssb_hcd_5354wa(dev); + } +} + +/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ +static u32 __devinit ssb_hcd_init_chip(struct ssb_device *dev) +{ + u32 flags = 0; + + if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) + /* Put the device into host-mode. */ + flags |= SSB_HCD_TMSLOW_HOSTMODE; + + ssb_device_enable(dev, flags); + + ssb_hcd_usb20wa(dev); + + return flags; +} + +static const struct usb_ehci_pdata ehci_pdata = { +}; + +static const struct usb_ohci_pdata ohci_pdata = { +}; + +static struct platform_device * __devinit +ssb_hcd_create_pdev(struct ssb_device *dev, bool ohci, u32 addr, u32 len) +{ + struct platform_device *hci_dev; + struct resource hci_res[2]; + int ret = -ENOMEM; + + memset(hci_res, 0, sizeof(hci_res)); + + hci_res[0].start = addr; + hci_res[0].end = hci_res[0].start + len - 1; + hci_res[0].flags = IORESOURCE_MEM; + + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + + hci_dev = platform_device_alloc(ohci ? "ohci-platform" : + "ehci-platform" , 0); + if (!hci_dev) + return NULL; + + hci_dev->dev.parent = dev->dev; + hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask; + + ret = platform_device_add_resources(hci_dev, hci_res, + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; + if (ohci) + ret = platform_device_add_data(hci_dev, &ohci_pdata, + sizeof(ohci_pdata)); + else + ret = platform_device_add_data(hci_dev, &ehci_pdata, + sizeof(ehci_pdata)); + if (ret) + goto err_alloc; + ret = platform_device_add(hci_dev); + if (ret) + goto err_alloc; + + return hci_dev; + +err_alloc: + platform_device_put(hci_dev); + return ERR_PTR(ret); +} + +static int __devinit ssb_hcd_probe(struct ssb_device *dev, + const struct ssb_device_id *id) +{ + int err, tmp; + int start, len; + u16 chipid_top; + u16 coreid = dev->id.coreid; + struct ssb_hcd_device *usb_dev; + + /* USBcores are only connected on embedded devices. */ + chipid_top = (dev->bus->chip_id & 0xFF00); + if (chipid_top != 0x4700 && chipid_top != 0x5300) + return -ENODEV; + + /* TODO: Probably need checks here; is the core connected? */ + + if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + + usb_dev = kzalloc(sizeof(struct ssb_hcd_device), GFP_KERNEL); + if (!usb_dev) + return -ENOMEM; + + /* We currently always attach SSB_DEV_USB11_HOSTDEV + * as HOST OHCI. If we want to attach it as Client device, + * we must branch here and call into the (yet to + * be written) Client mode driver. Same for remove(). */ + usb_dev->enable_flags = ssb_hcd_init_chip(dev); + + tmp = ssb_read32(dev, SSB_ADMATCH0); + + start = ssb_admatch_base(tmp); + len = (coreid == SSB_DEV_USB20_HOST) ? 0x800 : ssb_admatch_size(tmp); + usb_dev->ohci_dev = ssb_hcd_create_pdev(dev, true, start, len); + if (IS_ERR(usb_dev->ohci_dev)) { + err = PTR_ERR(usb_dev->ohci_dev); + goto err_free_usb_dev; + } + + if (coreid == SSB_DEV_USB20_HOST) { + start = ssb_admatch_base(tmp) + 0x800; /* ehci core offset */ + usb_dev->ehci_dev = ssb_hcd_create_pdev(dev, false, start, len); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; + } + } + + ssb_set_drvdata(dev, usb_dev); + return 0; + +err_unregister_ohci_dev: + platform_device_unregister(usb_dev->ohci_dev); +err_free_usb_dev: + kfree(usb_dev); + return err; +} + +static void __devexit ssb_hcd_remove(struct ssb_device *dev) +{ + struct ssb_hcd_device *usb_dev = ssb_get_drvdata(dev); + struct platform_device *ohci_dev = usb_dev->ohci_dev; + struct platform_device *ehci_dev = usb_dev->ehci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); + + ssb_device_disable(dev, 0); +} + +static void __devexit ssb_hcd_shutdown(struct ssb_device *dev) +{ + ssb_device_disable(dev, 0); +} + +#ifdef CONFIG_PM + +static int ssb_hcd_suspend(struct ssb_device *dev, pm_message_t state) +{ + ssb_device_disable(dev, 0); + + return 0; +} + +static int ssb_hcd_resume(struct ssb_device *dev) +{ + struct ssb_hcd_device *usb_dev = ssb_get_drvdata(dev); + + ssb_device_enable(dev, usb_dev->enable_flags); + + return 0; +} + +#else /* !CONFIG_PM */ +#define ssb_hcd_suspend NULL +#define ssb_hcd_resume NULL +#endif /* CONFIG_PM */ + +static const struct ssb_device_id ssb_hcd_table[] __devinitconst = { + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV), + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV), + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), + SSB_DEVTABLE_END +}; +MODULE_DEVICE_TABLE(ssb, ssb_hcd_table); + +static struct ssb_driver ssb_hcd_driver = { + .name = KBUILD_MODNAME, + .id_table = ssb_hcd_table, + .probe = ssb_hcd_probe, + .remove = __devexit_p(ssb_hcd_remove), + .shutdown = ssb_hcd_shutdown, + .suspend = ssb_hcd_suspend, + .resume = ssb_hcd_resume, +}; + +static int __init ssb_hcd_init(void) +{ + return ssb_driver_register(&ssb_hcd_driver); +} +module_init(ssb_hcd_init); + +static void __exit ssb_hcd_exit(void) +{ + ssb_driver_unregister(&ssb_hcd_driver); +} +module_exit(ssb_hcd_exit); -- 1.7.5.4 From hauke@hauke-m.de Thu Mar 15 23:51:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Mar 2012 23:52:32 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:33625 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903707Ab2COWvT (ORCPT ); Thu, 15 Mar 2012 23:51:19 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id BB9058F68; Thu, 15 Mar 2012 23:51:18 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id b6-dguTbkeWi; Thu, 15 Mar 2012 23:51:02 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 711028F64; Thu, 15 Mar 2012 23:50:33 +0100 (CET) From: Hauke Mehrtens To: gregkh@linuxfoundation.org Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, zajec5@gmail.com, Hauke Mehrtens Subject: [PATCH v5 4/4] USB: OHCI: remove old SSB OHCI driver Date: Thu, 15 Mar 2012 23:49:59 +0100 Message-Id: <1331851799-5968-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> References: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32722 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9390 Lines: 361 This is now replaced by the new ssb USB driver, which also supports devices with an EHCI controller. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 7 +- drivers/usb/host/ohci-hcd.c | 21 +---- drivers/usb/host/ohci-ssb.c | 260 ------------------------------------------- 3 files changed, 7 insertions(+), 281 deletions(-) delete mode 100644 drivers/usb/host/ohci-ssb.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 2fc5637..00b6fc8 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -373,10 +373,15 @@ config USB_OHCI_HCD_PCI If unsure, say Y. config USB_OHCI_HCD_SSB - bool "OHCI support for Broadcom SSB OHCI core" + bool "OHCI support for Broadcom SSB OHCI core (DEPRECATED)" depends on USB_OHCI_HCD && (SSB = y || SSB = USB_OHCI_HCD) && EXPERIMENTAL + select USB_HCD_SSB + select USB_OHCI_HCD_PLATFORM default n ---help--- + This option is deprecated now and the driver was removed, use + USB_HCD_SSB and USB_OHCI_HCD_PLATFORM instead. + Support for the Sonics Silicon Backplane (SSB) attached Broadcom USB OHCI core. diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index cd5e382..4f9e293 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1081,11 +1081,6 @@ MODULE_LICENSE ("GPL"); #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver #endif -#ifdef CONFIG_USB_OHCI_HCD_SSB -#include "ohci-ssb.c" -#define SSB_OHCI_DRIVER ssb_ohci_driver -#endif - #ifdef CONFIG_MFD_SM501 #include "ohci-sm501.c" #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver @@ -1129,8 +1124,7 @@ MODULE_LICENSE ("GPL"); !defined(SA1111_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && \ !defined(SM501_OHCI_DRIVER) && \ - !defined(TMIO_OHCI_DRIVER) && \ - !defined(SSB_OHCI_DRIVER) + !defined(TMIO_OHCI_DRIVER) #error "missing bus glue for ohci-hcd" #endif @@ -1196,12 +1190,6 @@ static int __init ohci_hcd_mod_init(void) goto error_pci; #endif -#ifdef SSB_OHCI_DRIVER - retval = ssb_driver_register(&SSB_OHCI_DRIVER); - if (retval) - goto error_ssb; -#endif - #ifdef SM501_OHCI_DRIVER retval = platform_driver_register(&SM501_OHCI_DRIVER); if (retval < 0) @@ -1225,10 +1213,6 @@ static int __init ohci_hcd_mod_init(void) platform_driver_unregister(&SM501_OHCI_DRIVER); error_sm501: #endif -#ifdef SSB_OHCI_DRIVER - ssb_driver_unregister(&SSB_OHCI_DRIVER); - error_ssb: -#endif #ifdef PCI_DRIVER pci_unregister_driver(&PCI_DRIVER); error_pci: @@ -1276,9 +1260,6 @@ static void __exit ohci_hcd_mod_exit(void) #ifdef SM501_OHCI_DRIVER platform_driver_unregister(&SM501_OHCI_DRIVER); #endif -#ifdef SSB_OHCI_DRIVER - ssb_driver_unregister(&SSB_OHCI_DRIVER); -#endif #ifdef PCI_DRIVER pci_unregister_driver(&PCI_DRIVER); #endif diff --git a/drivers/usb/host/ohci-ssb.c b/drivers/usb/host/ohci-ssb.c deleted file mode 100644 index 5ba1859..0000000 --- a/drivers/usb/host/ohci-ssb.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Sonics Silicon Backplane - * Broadcom USB-core OHCI driver - * - * Copyright 2007 Michael Buesch - * - * Derived from the OHCI-PCI driver - * Copyright 1999 Roman Weissgaerber - * Copyright 2000-2002 David Brownell - * Copyright 1999 Linus Torvalds - * Copyright 1999 Gregory P. Smith - * - * Derived from the USBcore related parts of Broadcom-SB - * Copyright 2005 Broadcom Corporation - * - * Licensed under the GNU/GPL. See COPYING for details. - */ -#include - - -#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29) - -struct ssb_ohci_device { - struct ohci_hcd ohci; /* _must_ be at the beginning. */ - - u32 enable_flags; -}; - -static inline -struct ssb_ohci_device *hcd_to_ssb_ohci(struct usb_hcd *hcd) -{ - return (struct ssb_ohci_device *)(hcd->hcd_priv); -} - - -static int ssb_ohci_reset(struct usb_hcd *hcd) -{ - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - struct ohci_hcd *ohci = &ohcidev->ohci; - int err; - - ohci_hcd_init(ohci); - err = ohci_init(ohci); - - return err; -} - -static int ssb_ohci_start(struct usb_hcd *hcd) -{ - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - struct ohci_hcd *ohci = &ohcidev->ohci; - int err; - - err = ohci_run(ohci); - if (err < 0) { - ohci_err(ohci, "can't start\n"); - ohci_stop(hcd); - } - - return err; -} - -static const struct hc_driver ssb_ohci_hc_driver = { - .description = "ssb-usb-ohci", - .product_desc = "SSB OHCI Controller", - .hcd_priv_size = sizeof(struct ssb_ohci_device), - - .irq = ohci_irq, - .flags = HCD_MEMORY | HCD_USB11, - - .reset = ssb_ohci_reset, - .start = ssb_ohci_start, - .stop = ohci_stop, - .shutdown = ohci_shutdown, - - .urb_enqueue = ohci_urb_enqueue, - .urb_dequeue = ohci_urb_dequeue, - .endpoint_disable = ohci_endpoint_disable, - - .get_frame_number = ohci_get_frame, - - .hub_status_data = ohci_hub_status_data, - .hub_control = ohci_hub_control, -#ifdef CONFIG_PM - .bus_suspend = ohci_bus_suspend, - .bus_resume = ohci_bus_resume, -#endif - - .start_port_reset = ohci_start_port_reset, -}; - -static void ssb_ohci_detach(struct ssb_device *dev) -{ - struct usb_hcd *hcd = ssb_get_drvdata(dev); - - if (hcd->driver->shutdown) - hcd->driver->shutdown(hcd); - usb_remove_hcd(hcd); - iounmap(hcd->regs); - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); - usb_put_hcd(hcd); - ssb_device_disable(dev, 0); -} - -static int ssb_ohci_attach(struct ssb_device *dev) -{ - struct ssb_ohci_device *ohcidev; - struct usb_hcd *hcd; - int err = -ENOMEM; - u32 tmp, flags = 0; - - if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || - dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) - return -EOPNOTSUPP; - - if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) { - /* Put the device into host-mode. */ - flags |= SSB_OHCI_TMSLOW_HOSTMODE; - ssb_device_enable(dev, flags); - } else if (dev->id.coreid == SSB_DEV_USB20_HOST) { - /* - * USB 2.0 special considerations: - * - * In addition to the standard SSB reset sequence, the Host - * Control Register must be programmed to bring the USB core - * and various phy components out of reset. - */ - ssb_device_enable(dev, 0); - ssb_write32(dev, 0x200, 0x7ff); - - /* Change Flush control reg */ - tmp = ssb_read32(dev, 0x400); - tmp &= ~8; - ssb_write32(dev, 0x400, tmp); - tmp = ssb_read32(dev, 0x400); - - /* Change Shim control reg */ - tmp = ssb_read32(dev, 0x304); - tmp &= ~0x100; - ssb_write32(dev, 0x304, tmp); - tmp = ssb_read32(dev, 0x304); - - udelay(1); - - /* Work around for 5354 failures */ - if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { - /* Change syn01 reg */ - tmp = 0x00fe00fe; - ssb_write32(dev, 0x894, tmp); - - /* Change syn03 reg */ - tmp = ssb_read32(dev, 0x89c); - tmp |= 0x1; - ssb_write32(dev, 0x89c, tmp); - } - } else - ssb_device_enable(dev, 0); - - hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev, - dev_name(dev->dev)); - if (!hcd) - goto err_dev_disable; - ohcidev = hcd_to_ssb_ohci(hcd); - ohcidev->enable_flags = flags; - - tmp = ssb_read32(dev, SSB_ADMATCH0); - hcd->rsrc_start = ssb_admatch_base(tmp); - hcd->rsrc_len = ssb_admatch_size(tmp); - hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); - if (!hcd->regs) - goto err_put_hcd; - err = usb_add_hcd(hcd, dev->irq, IRQF_SHARED); - if (err) - goto err_iounmap; - - ssb_set_drvdata(dev, hcd); - - return err; - -err_iounmap: - iounmap(hcd->regs); -err_put_hcd: - usb_put_hcd(hcd); -err_dev_disable: - ssb_device_disable(dev, flags); - return err; -} - -static int ssb_ohci_probe(struct ssb_device *dev, - const struct ssb_device_id *id) -{ - int err; - u16 chipid_top; - - /* USBcores are only connected on embedded devices. */ - chipid_top = (dev->bus->chip_id & 0xFF00); - if (chipid_top != 0x4700 && chipid_top != 0x5300) - return -ENODEV; - - /* TODO: Probably need checks here; is the core connected? */ - - if (usb_disabled()) - return -ENODEV; - - /* We currently always attach SSB_DEV_USB11_HOSTDEV - * as HOST OHCI. If we want to attach it as Client device, - * we must branch here and call into the (yet to - * be written) Client mode driver. Same for remove(). */ - - err = ssb_ohci_attach(dev); - - return err; -} - -static void ssb_ohci_remove(struct ssb_device *dev) -{ - ssb_ohci_detach(dev); -} - -#ifdef CONFIG_PM - -static int ssb_ohci_suspend(struct ssb_device *dev, pm_message_t state) -{ - ssb_device_disable(dev, 0); - - return 0; -} - -static int ssb_ohci_resume(struct ssb_device *dev) -{ - struct usb_hcd *hcd = ssb_get_drvdata(dev); - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - - ssb_device_enable(dev, ohcidev->enable_flags); - - ohci_finish_controller_resume(hcd); - return 0; -} - -#else /* !CONFIG_PM */ -#define ssb_ohci_suspend NULL -#define ssb_ohci_resume NULL -#endif /* CONFIG_PM */ - -static const struct ssb_device_id ssb_ohci_table[] = { - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), - SSB_DEVTABLE_END -}; -MODULE_DEVICE_TABLE(ssb, ssb_ohci_table); - -static struct ssb_driver ssb_ohci_driver = { - .name = KBUILD_MODNAME, - .id_table = ssb_ohci_table, - .probe = ssb_ohci_probe, - .remove = ssb_ohci_remove, - .suspend = ssb_ohci_suspend, - .resume = ssb_ohci_resume, -}; -- 1.7.5.4 From gregkh@linuxfoundation.org Fri Mar 16 00:35:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Mar 2012 00:35:47 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:56394 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903667Ab2COXfl (ORCPT ); Fri, 16 Mar 2012 00:35:41 +0100 Received: by dakp5 with SMTP id p5so4896429dak.36 for ; Thu, 15 Mar 2012 16:35:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=12AILZrReOcmh46TXwULypFnX1IKk5Ag8SU68hJ67Fs=; b=pLuMcdYWCPgcU0v7TDTfrIj9unqaDfMhZBDZ4U6At1E7a2ax670VHsi7KfJHIadYex aRfgADtDaVZ2+0kcYNdFRUNzmzUHRGNcsQQojDUooqIOVyjPjkaA/iSebSfJVD6yYfzH JnUz2wAy61/5+jOR2ahD4paFGHANRgugemAjnwtLCjCRiBU8vpRe9ao6jwQbhJFH7B2A 0G6+nLBl8hlQRlE5/MqW/Ftgd+BMYn6/cxod4DLH5kqFi4LBMS63ys76kYcmMkD+BMCe KKUGwyVoHGCQtdssNllqQIB5eWaH08/IfFPASt8NTjPuEJUbI3yjOq4SseVkX8L00LY1 kdDg== Received: by 10.68.130.103 with SMTP id od7mr8237348pbb.66.1331854534450; Thu, 15 Mar 2012 16:35:34 -0700 (PDT) Received: from localhost (c-76-121-69-168.hsd1.wa.comcast.net. [76.121.69.168]) by mx.google.com with ESMTPS id d10sm2854922pbr.59.2012.03.15.16.35.32 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 15 Mar 2012 16:35:33 -0700 (PDT) Date: Thu, 15 Mar 2012 16:35:31 -0700 From: Greg KH To: Hauke Mehrtens Cc: stern@rowland.harvard.edu, linux-mips@linux-mips.org, ralf@linux-mips.org, m@bues.ch, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org Subject: Re: [PATCH v4 4/7] USB: Add driver for the bcma bus Message-ID: <20120315233531.GA2052@kroah.com> References: <1331597093-425-1-git-send-email-hauke@hauke-m.de> <1331597093-425-5-git-send-email-hauke@hauke-m.de> <20120315194426.GA30682@kroah.com> <4F626FCB.6010103@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4F626FCB.6010103@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQlHE0dGzS11y8r20MKNBaNu0APSj6Bep1SMidddg6dmYyUoGLx9gsVY5YwwPV4qI4oCOgIu X-archive-position: 32723 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1270 Lines: 31 On Thu, Mar 15, 2012 at 11:40:11PM +0100, Hauke Mehrtens wrote: > On 03/15/2012 08:44 PM, Greg KH wrote: > > On Tue, Mar 13, 2012 at 01:04:50AM +0100, Hauke Mehrtens wrote: > >> This adds a USB driver using the generic platform device driver for the > >> USB controller found on the Broadcom bcma bus. The bcma bus just > >> exposes one device which serves the OHCI and the EHCI controller at the > >> same time. This driver probes for this USB controller and creates and > >> registers two new platform devices which will be probed by the new > >> generic platform device driver. This makes it possible to use the EHCI > >> and the OCHI controller on the bcma bus at the same time. > >> > >> Signed-off-by: Hauke Mehrtens > >> --- > >> drivers/usb/host/Kconfig | 12 ++ > > > > This patch fails to apply here, and I can't seem to figure out what tree > > you made this against to fix it up by hand on my end. > > > > Any thoughts? > > > > greg k-h > > This patch was against > git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git#master, but > I will rebase it onto usb/usb-next and send a new version of the patches > you have not applied. Thanks, master tracks Linus's tree, which is not good to send patches against :) greg k-h From xiangfu@openmobilefree.net Fri Mar 16 09:54:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Mar 2012 09:54:53 +0100 (CET) Received: from mail-wi0-f171.google.com ([209.85.212.171]:62506 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901172Ab2CPIyt (ORCPT ); Fri, 16 Mar 2012 09:54:49 +0100 Received: by wibhj13 with SMTP id hj13so390864wib.6 for ; Fri, 16 Mar 2012 01:54:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:organization:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=7P9rO672wMRoR88BjKPOosa8a6dT2CJyXJxVjm37s2o=; b=jdd1v4SG8KJ1ziuSM/oC0A5IfAOLjB+NmNxPpkh0bslkTxdiGwfPiR18SPfg2uwQ9a zj237dHCtM+qbtDfJ3SOk7jR+ZqH03SU9c62+vTjM/wAByvMieoqzylrHHTswkgjhFGA W030SIgIyhFuBR4I7tN3vm5/hao1X1c/NV39sycRx5yXHHuD1bB3bUXKtgh0muUqbOJB ThnSXUdO2WI7v/ZbdjW6PaKvDruTRWxrv2+fICKVKTcLdIzYMuNxPBOBT6hY087l1wet TJ48HubwrHpjGde/w9fbemxkwWUDwoQ2fcJQo6SlAZiTp2AfKu5CZA4KEfHzXbX33LSa Zx/Q== Received: by 10.180.105.69 with SMTP id gk5mr38721728wib.3.1331888084136; Fri, 16 Mar 2012 01:54:44 -0700 (PDT) Received: from [10.8.0.6] (fidelio.qi-hardware.com. [213.239.211.82]) by mx.google.com with ESMTPS id fl2sm19740427wib.4.2012.03.16.01.54.36 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 16 Mar 2012 01:54:43 -0700 (PDT) Message-ID: <4F62FFA6.4040101@openmobilefree.net> Date: Fri, 16 Mar 2012 16:53:58 +0800 From: Xiangfu Liu Organization: http://www.openmobilefree.net User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: john stultz CC: Matt Turner , linux-mips@linux-mips.org, rtc-linux@googlegroups.com Subject: Re: select() to /dev/rtc0 to wait for clock tick timed out References: <1313777242.2970.131.camel@work-vm> <1313783990.2970.136.camel@work-vm> <4EFD76F9.50204@openmobilefree.net> In-Reply-To: <4EFD76F9.50204@openmobilefree.net> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQnePO+VQ2IApFOH4mMNLUlsfV4nnXJfObf8CVN3jE9Hw4ctR9zWBYv4kGOfb5/ErIwxerNU X-archive-position: 32724 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: xiangfu@openmobilefree.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 916 Lines: 30 Hi After I update kernel to linux v3.2.1. the problem still there. Please give me some advice, how to fix this issue? Thanks On 12/30/2011 04:31 PM, Xiangfu Liu wrote: > Hi John Stultz > > I meet the same problem on MIPS jz4740, here is the step I try to find out the problem: > > 1. when I direct run 'hwclock' it will give > "select() to /dev/rtc0 to wait for clock tick timed out" > attachment 'hwclock.time.out' is the strace log > > 2. run 'rtctest' program. it works fine. the output is here[1] > > 3. after 'rtctest', run 'hwclock' again. then it works fine > attachment 'hwclock.wors' is the strace log > > without 'rtctest' run first. 'hwclock' never works. > the hwclock works fine in 2.6.27.6, failed under '3.0.0' > > Please give me some tips how to fix this problem. shoule I modify the driver code > or is that relate to 'CONFIG_RTC_INTF_DEV_UIE_EMUL'? > > thanks in advance. > xiangfu From arend@broadcom.com Fri Mar 16 10:06:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Mar 2012 10:06:09 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:2275 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901172Ab2CPJGB (ORCPT ); Fri, 16 Mar 2012 10:06:01 +0100 Received: from [10.9.200.133] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 16 Mar 2012 02:14:58 -0700 X-Server-Uuid: B730DE51-FC43-4C83-941F-F1F78A914BDD Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 16 Mar 2012 02:05:09 -0700 Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.17.16.106]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 30524BC395; Fri, 16 Mar 2012 02:05:46 -0700 (PDT) Received: from [10.0.2.15] (unknown [10.176.68.152]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 92186207C0; Fri, 16 Mar 2012 02:05:44 -0700 (PDT) Message-ID: <4F630267.5050909@broadcom.com> Date: Fri, 16 Mar 2012 10:05:43 +0100 From: "Arend van Spriel" User-Agent: Mozilla/5.0 (X11; Linux i686; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: "Hauke Mehrtens" cc: "gregkh@linuxfoundation.org" , "stern@rowland.harvard.edu" , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "m@bues.ch" , "linux-usb@vger.kernel.org" , "linux-wireless@vger.kernel.org" , "zajec5@gmail.com" Subject: Re: [PATCH v5 4/4] USB: OHCI: remove old SSB OHCI driver References: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> <1331851799-5968-5-git-send-email-hauke@hauke-m.de> In-Reply-To: <1331851799-5968-5-git-send-email-hauke@hauke-m.de> X-WSS-ID: 637DDB183E05310984-01-01 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32725 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arend@broadcom.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1411 Lines: 39 On 03/15/2012 11:49 PM, Hauke Mehrtens wrote: > This is now replaced by the new ssb USB driver, which also supports > devices with an EHCI controller. > > Signed-off-by: Hauke Mehrtens > --- > drivers/usb/host/Kconfig | 7 +- > drivers/usb/host/ohci-hcd.c | 21 +---- > drivers/usb/host/ohci-ssb.c | 260 ------------------------------------------- > 3 files changed, 7 insertions(+), 281 deletions(-) > delete mode 100644 drivers/usb/host/ohci-ssb.c > > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig > index 2fc5637..00b6fc8 100644 > --- a/drivers/usb/host/Kconfig > +++ b/drivers/usb/host/Kconfig > @@ -373,10 +373,15 @@ config USB_OHCI_HCD_PCI > If unsure, say Y. > > config USB_OHCI_HCD_SSB > - bool "OHCI support for Broadcom SSB OHCI core" > + bool "OHCI support for Broadcom SSB OHCI core (DEPRECATED)" > depends on USB_OHCI_HCD&& (SSB = y || SSB = USB_OHCI_HCD)&& EXPERIMENTAL > + select USB_HCD_SSB > + select USB_OHCI_HCD_PLATFORM > default n > ---help--- > + This option is deprecated now and the driver was removed, use > + USB_HCD_SSB and USB_OHCI_HCD_PLATFORM instead. > + > Support for the Sonics Silicon Backplane (SSB) attached > Broadcom USB OHCI core. Looks fine as it helps transitioning old .config files. Should the select statements be mentioned in the help section, ie. 'using' iso 'use'. Gr. AvS From xiangfu@openmobilefree.net Fri Mar 16 10:58:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Mar 2012 10:58:25 +0100 (CET) Received: from mail-wi0-f177.google.com ([209.85.212.177]:46766 "EHLO mail-wi0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901172Ab2CPJ6V (ORCPT ); Fri, 16 Mar 2012 10:58:21 +0100 Received: by wibhj13 with SMTP id hj13so473857wib.6 for ; Fri, 16 Mar 2012 02:58:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=SR1ZhDh5cDeefmLR/+bnTWNWKHslMgRtjhFMJKW0Lkk=; b=imAe3mgBQyGvkM7AcCfrmPi8MEOfknHlzPLxrHxMg+YbMNwhBMCwBzhEBpNEvkM5nH p/i/orWSdqFzyKFf1pVJsQzcEfMfzqMsw5saxL5bLXau1iYzkOlw3EwEuI1rTVcB5jk7 KFvf4fDgi1VIH5+JdpFerpx/NVhYiMVFQTWiSFJNAxWui1OcbvOau3OLxdMOfH8ZkUJy GcTzJpJuXbo1zYefaxmqzkxvBHxHHSxOo5JpjTV7gnKXFMn5a0WF+6B3CLLRdxEusnoB M/Tq3v1AhgrmqD1L5CSh9c7T0utl3LHo32vaXI7U3ZiSW+UXWGlVBOy+8MVEGPrW5voY TpPA== Received: by 10.180.107.162 with SMTP id hd2mr33884117wib.8.1331891895207; Fri, 16 Mar 2012 02:58:15 -0700 (PDT) Received: from localhost.localdomain (fidelio.qi-hardware.com. [213.239.211.82]) by mx.google.com with ESMTPS id e6sm12445536wix.8.2012.03.16.02.57.57 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 16 Mar 2012 02:58:14 -0700 (PDT) From: Xiangfu To: lars@metafoo.de Cc: linux-mips@linux-mips.org, discussion@lists.en.qi-hardware.com, Xiangfu Subject: [PATCH] rtc: jz4740 fix hwclock give time out Date: Fri, 16 Mar 2012 17:55:12 +0800 Message-Id: <1331891712-25269-1-git-send-email-xiangfu@openmobilefree.net> X-Mailer: git-send-email 1.7.5.4 X-Gm-Message-State: ALoCoQkVw4e+XNRagQG9xNfC1esp9Vo0jCWCI+KZ0NrrV5JiWuQUCnWRF7LxrSlNf9HSb9zYk2HW X-archive-position: 32726 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: xiangfu@openmobilefree.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 671 Lines: 30 --- Hi Lars This patch fix the hwclock give time out error. I am not sure is this patch good please review. give some feedback. thanks More info: http://www.linux-mips.org/archives/linux-mips/2011-12/msg00191.html Xiangfu drivers/rtc/rtc-jz4740.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index b647363..50c5df0 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -280,6 +280,8 @@ static int __devinit jz4740_rtc_probe(struct platform_device *pdev) } } + jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ, 1); + return 0; err_free_irq: -- 1.7.5.4 From hauke@hauke-m.de Fri Mar 16 16:36:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Mar 2012 16:36:03 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:36672 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903689Ab2CPPgA (ORCPT ); Fri, 16 Mar 2012 16:36:00 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 577348F61; Fri, 16 Mar 2012 16:35:59 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Zg7ploNB+Jy6; Fri, 16 Mar 2012 16:35:45 +0100 (CET) Received: from [134.102.24.159] (eduroam-pool6-0159.wlan.uni-bremen.de [134.102.24.159]) by hauke-m.de (Postfix) with ESMTPSA id BD59F8F60; Fri, 16 Mar 2012 16:35:44 +0100 (CET) Message-ID: <4F635DCF.7060101@hauke-m.de> Date: Fri, 16 Mar 2012 16:35:43 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.27) Gecko/20120216 Lightning/1.0b2 Thunderbird/3.1.19 MIME-Version: 1.0 To: Arend van Spriel CC: "gregkh@linuxfoundation.org" , "stern@rowland.harvard.edu" , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "m@bues.ch" , "linux-usb@vger.kernel.org" , "linux-wireless@vger.kernel.org" , "zajec5@gmail.com" Subject: Re: [PATCH v5 4/4] USB: OHCI: remove old SSB OHCI driver References: <1331851799-5968-1-git-send-email-hauke@hauke-m.de> <1331851799-5968-5-git-send-email-hauke@hauke-m.de> <4F630267.5050909@broadcom.com> In-Reply-To: <4F630267.5050909@broadcom.com> X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32727 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1788 Lines: 48 On 03/16/2012 10:05 AM, Arend van Spriel wrote: > On 03/15/2012 11:49 PM, Hauke Mehrtens wrote: >> This is now replaced by the new ssb USB driver, which also supports >> devices with an EHCI controller. >> >> Signed-off-by: Hauke Mehrtens >> --- >> drivers/usb/host/Kconfig | 7 +- >> drivers/usb/host/ohci-hcd.c | 21 +---- >> drivers/usb/host/ohci-ssb.c | 260 >> ------------------------------------------- >> 3 files changed, 7 insertions(+), 281 deletions(-) >> delete mode 100644 drivers/usb/host/ohci-ssb.c >> >> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig >> index 2fc5637..00b6fc8 100644 >> --- a/drivers/usb/host/Kconfig >> +++ b/drivers/usb/host/Kconfig >> @@ -373,10 +373,15 @@ config USB_OHCI_HCD_PCI >> If unsure, say Y. >> >> config USB_OHCI_HCD_SSB >> - bool "OHCI support for Broadcom SSB OHCI core" >> + bool "OHCI support for Broadcom SSB OHCI core (DEPRECATED)" >> depends on USB_OHCI_HCD&& (SSB = y || SSB = USB_OHCI_HCD)&& >> EXPERIMENTAL >> + select USB_HCD_SSB >> + select USB_OHCI_HCD_PLATFORM >> default n >> ---help--- >> + This option is deprecated now and the driver was removed, use >> + USB_HCD_SSB and USB_OHCI_HCD_PLATFORM instead. >> + >> Support for the Sonics Silicon Backplane (SSB) attached >> Broadcom USB OHCI core. > > Looks fine as it helps transitioning old .config files. Should the > select statements be mentioned in the help section, ie. 'using' iso 'use'. I think "use" is better as USB_OHCI_HCD_SSB will be removed in some time and it should not be used any more. If someone generated the config or a base config with some other script it should be changed to USB_HCD_SSB and USB_OHCI_HCD_PLATFORM. Hauke Hauke From john.stultz@linaro.org Sat Mar 17 02:11:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Mar 2012 02:11:14 +0100 (CET) Received: from e8.ny.us.ibm.com ([32.97.182.138]:40964 "EHLO e8.ny.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903715Ab2CQBLJ (ORCPT ); Sat, 17 Mar 2012 02:11:09 +0100 Received: from /spool/local by e8.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 16 Mar 2012 21:11:02 -0400 Received: from d01dlp01.pok.ibm.com (9.56.224.56) by e8.ny.us.ibm.com (192.168.1.108) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 16 Mar 2012 21:11:01 -0400 Received: from d01relay04.pok.ibm.com (d01relay04.pok.ibm.com [9.56.227.236]) by d01dlp01.pok.ibm.com (Postfix) with ESMTP id D851B38C8054 for ; Fri, 16 Mar 2012 21:11:00 -0400 (EDT) Received: from d01av02.pok.ibm.com (d01av02.pok.ibm.com [9.56.224.216]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q2H1B0Cp251840 for ; Fri, 16 Mar 2012 21:11:00 -0400 Received: from d01av02.pok.ibm.com (loopback [127.0.0.1]) by d01av02.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q2H1B0hL023367 for ; Fri, 16 Mar 2012 22:11:00 -0300 Received: from [9.76.207.219] (sig-9-76-207-219.mts.ibm.com [9.76.207.219]) by d01av02.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q2H1AuI8023169; Fri, 16 Mar 2012 22:10:58 -0300 Message-ID: <4F63E4A0.3010603@linaro.org> Date: Fri, 16 Mar 2012 18:10:56 -0700 From: John Stultz User-Agent: Mozilla/5.0 (X11; Linux i686; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Xiangfu Liu CC: Matt Turner , linux-mips@linux-mips.org, jz47xx-kernel@lists.en.qi-hardware.com, rtc-linux@googlegroups.com Subject: Re: select() to /dev/rtc0 to wait for clock tick timed out References: <1313777242.2970.131.camel@work-vm> <1313783990.2970.136.camel@work-vm> <4EFD76F9.50204@openmobilefree.net> In-Reply-To: <4EFD76F9.50204@openmobilefree.net> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Content-Scanned: Fidelis XPS MAILER x-cbid: 12031701-9360-0000-0000-0000049E35DD X-archive-position: 32729 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john.stultz@linaro.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1692 Lines: 61 On 12/30/2011 12:31 AM, Xiangfu Liu wrote: > I meet the same problem on MIPS jz4740, here is the step I try to find > out the problem: > > 1. when I direct run 'hwclock' it will give > "select() to /dev/rtc0 to wait for clock tick timed out" > attachment 'hwclock.time.out' is the strace log > > 2. run 'rtctest' program. it works fine. the output is here[1] > > 3. after 'rtctest', run 'hwclock' again. then it works fine > attachment 'hwclock.wors' is the strace log > > without 'rtctest' run first. 'hwclock' never works. > the hwclock works fine in 2.6.27.6, failed under '3.0.0' > > Please give me some tips how to fix this problem. shoule I modify the > driver code > or is that relate to 'CONFIG_RTC_INTF_DEV_UIE_EMUL'? Sorry I missed this email originally, and thank you for pinging me. Is CONFIG_RTC_INTF_DEV_UIE_EMUL set in the config you're seeing this with? Does disabling it change the behavior? Just a shot in the dark, but does the following help at all? thanks -john Signed-off-by: John Stultz diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index 05ab227..c6c81ba 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -171,7 +171,8 @@ static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) { struct jz4740_rtc *rtc = dev_get_drvdata(dev); - return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable); + return jz4740_rtc_ctrl_set_bits(rtc, + JZ_RTC_CTRL_AE |JZ_RTC_CTRL_AF_IRQ, enable); } static struct rtc_class_ops jz4740_rtc_ops = { From xiangfu@openmobilefree.net Sun Mar 18 08:03:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 18 Mar 2012 08:03:33 +0100 (CET) Received: from mail-wi0-f177.google.com ([209.85.212.177]:50175 "EHLO mail-wi0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903554Ab2CRHD3 (ORCPT ); Sun, 18 Mar 2012 08:03:29 +0100 Received: by wibhj13 with SMTP id hj13so2244447wib.6 for ; Sun, 18 Mar 2012 00:03:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:organization:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=5kvqAU0oCjt2dy+5tD0GXDvD3t3bxhbqhA3KxyTWDVQ=; b=X+cUbGiKMi/iHscNSQP8DQp9iB/XG9XwJUEYpBtpB8gYimBAlQ0A4VqRvKeWddR8OB qdKxhGGXIdSlL1wlAS7H6HQMjJT0GcquwGDZB+rBeiCoZDHzINGx3Lpy7F/nj9LjK/+c dirp/IVvsQT/0++8lopS7ZypCkIsYyMVMheSkDrkYFa1XBXefrOuzeGqhcaO/sfoa0hr Bh7gLQQo7i98Pon8j2P5Ijij0EJ9H4mMlrKhYwpMHjHDMDQUkm6jUb0LbhD7z0sF88Nb f56E5jDR0ccKwvoizHlxKivAgqQlTvfpWD/4wgy756jpw1qmfMxkrNsPlSMYIkXj9Xdw QV0w== Received: by 10.180.97.41 with SMTP id dx9mr10645355wib.9.1332054203274; Sun, 18 Mar 2012 00:03:23 -0700 (PDT) Received: from [10.8.0.6] (fidelio.qi-hardware.com. [213.239.211.82]) by mx.google.com with ESMTPS id b3sm14144659wib.4.2012.03.18.00.03.16 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 18 Mar 2012 00:03:22 -0700 (PDT) Message-ID: <4F6588AC.1010809@openmobilefree.net> Date: Sun, 18 Mar 2012 15:03:08 +0800 From: Xiangfu Liu Organization: http://www.openmobilefree.net User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Stultz CC: Matt Turner , linux-mips@linux-mips.org, jz47xx-kernel@lists.en.qi-hardware.com, rtc-linux@googlegroups.com, Lars-Peter Clausen Subject: Re: select() to /dev/rtc0 to wait for clock tick timed out References: <1313777242.2970.131.camel@work-vm> <1313783990.2970.136.camel@work-vm> <4EFD76F9.50204@openmobilefree.net> <4F63E4A0.3010603@linaro.org> In-Reply-To: <4F63E4A0.3010603@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkFFfoFsNyc49pzRA3Vq9fIDpDfOcbj+748HKkwF0QwujP/vB2S6Yf17aTicXyk4jaEzd+d X-archive-position: 32730 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: xiangfu@openmobilefree.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2202 Lines: 72 Hi John Thanks for reply. the patch is not working. I found a work around. checkout this patch: http://projects.qi-hardware.com/index.php/p/openwrt-xburst/source/tree/5a49fe26a5cefe0b1f8dcff1315cf3f2e12bc8f6/target/linux/xburst/patches-3.2/0029-rtc-jz4740-fix-hwclock-give-time-out.patch after apply this patch. the hwclock worksf ine again. but it is may not a good patch. Please take a look give me some advice. Thanks John Xiangfu On 03/17/2012 09:10 AM, John Stultz wrote: > On 12/30/2011 12:31 AM, Xiangfu Liu wrote: >> I meet the same problem on MIPS jz4740, here is the step I try to find out the problem: >> >> 1. when I direct run 'hwclock' it will give >> "select() to /dev/rtc0 to wait for clock tick timed out" >> attachment 'hwclock.time.out' is the strace log >> >> 2. run 'rtctest' program. it works fine. the output is here[1] >> >> 3. after 'rtctest', run 'hwclock' again. then it works fine >> attachment 'hwclock.wors' is the strace log >> >> without 'rtctest' run first. 'hwclock' never works. >> the hwclock works fine in 2.6.27.6, failed under '3.0.0' >> >> Please give me some tips how to fix this problem. shoule I modify the driver code >> or is that relate to 'CONFIG_RTC_INTF_DEV_UIE_EMUL'? > > Sorry I missed this email originally, and thank you for pinging me. > > Is CONFIG_RTC_INTF_DEV_UIE_EMUL set in the config you're seeing this with? Does disabling it change the behavior? > > Just a shot in the dark, but does the following help at all? > thanks > -john > > Signed-off-by: John Stultz > > diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c > > index 05ab227..c6c81ba 100644 > > --- a/drivers/rtc/rtc-jz4740.c > > +++ b/drivers/rtc/rtc-jz4740.c > > @@ -171,7 +171,8 @@ static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) > > static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) > > { > > struct jz4740_rtc *rtc = dev_get_drvdata(dev); > > - return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable); > > + return jz4740_rtc_ctrl_set_bits(rtc, > > + JZ_RTC_CTRL_AE |JZ_RTC_CTRL_AF_IRQ, enable); > > } > > > > static struct rtc_class_ops jz4740_rtc_ops = { > > > > From veli-pekka.peltola@bluegiga.com Mon Mar 19 16:36:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Mar 2012 16:36:21 +0100 (CET) Received: from bluegiga.fi ([194.100.31.45]:32562 "EHLO darkblue.bluegiga.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903696Ab2CSPgO (ORCPT ); Mon, 19 Mar 2012 16:36:14 +0100 Received: from [10.1.1.75] ([10.1.1.75]) by darkblue.bluegiga.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 19 Mar 2012 17:36:08 +0200 Message-ID: <4F675260.2010205@bluegiga.com> Date: Mon, 19 Mar 2012 17:36:00 +0200 From: Veli-Pekka Peltola User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org, Russell King , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org Subject: Re: [PATCH v2] mm: module_alloc: check if size is 0 References: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com> <1331125768-25454-1-git-send-email-veli-pekka.peltola@bluegiga.com> In-Reply-To: <1331125768-25454-1-git-send-email-veli-pekka.peltola@bluegiga.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 19 Mar 2012 15:36:08.0835 (UTC) FILETIME=[01700D30:01CD05E6] X-archive-position: 32731 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: veli-pekka.peltola@bluegiga.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2773 Lines: 78 Hi, On 03/07/2012 03:09 PM, Veli-Pekka Peltola wrote: > After commit de7d2b567d040e3b67fe7121945982f14343213d (mm/vmalloc.c: report > more vmalloc failures) users will get a warning if vmalloc_node_range() is > called with size 0. This happens if module's init size equals to 0. This > patch changes ARM, MIPS and x86 module_alloc() to return NULL before calling > vmalloc_node_range() that would also return NULL and print a warning. > > Signed-off-by: Veli-Pekka Peltola > Cc: Russell King > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: "H. Peter Anvin" > Cc: x86@kernel.org > --- > I found this with ARM but after checking out various implementations of > module_alloc() I thought it would be better to fix all at once. > > One way to replicate the warning: > compile kernel with CONFIG_KALLSYMS=n > insmod a module without init, I used usb-common.ko > > Changes since v1: > - changed style as hpa suggested > > arch/arm/kernel/module.c | 2 ++ > arch/mips/kernel/module.c | 2 ++ > arch/x86/kernel/module.c | 2 +- > 3 files changed, 5 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c > index 1e9be5d..17648e2 100644 > --- a/arch/arm/kernel/module.c > +++ b/arch/arm/kernel/module.c > @@ -39,6 +39,8 @@ > #ifdef CONFIG_MMU > void *module_alloc(unsigned long size) > { > + if (!size) > + return NULL; > return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, > GFP_KERNEL, PAGE_KERNEL_EXEC, -1, > __builtin_return_address(0)); > diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c > index a5066b1..1a51de1 100644 > --- a/arch/mips/kernel/module.c > +++ b/arch/mips/kernel/module.c > @@ -47,6 +47,8 @@ static DEFINE_SPINLOCK(dbe_lock); > #ifdef MODULE_START > void *module_alloc(unsigned long size) > { > + if (!size) > + return NULL; > return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, > GFP_KERNEL, PAGE_KERNEL, -1, > __builtin_return_address(0)); > diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c > index 925179f..fd44d69 100644 > --- a/arch/x86/kernel/module.c > +++ b/arch/x86/kernel/module.c > @@ -38,7 +38,7 @@ > > void *module_alloc(unsigned long size) > { > - if (PAGE_ALIGN(size)> MODULES_LEN) > + if (!size || PAGE_ALIGN(size)> MODULES_LEN) > return NULL; > return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, > GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC, Any comments on this? Should I split all architectures to separate patches? I just tested 3.3 on ARM and x86, both printed a warning and call trace without this patch. -- Veli-Pekka Peltola From m.szyprowski@samsung.com Tue Mar 20 08:24:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Mar 2012 08:25:05 +0100 (CET) Received: from mailout3.w1.samsung.com ([210.118.77.13]:60591 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903601Ab2CTHY5 (ORCPT ); Tue, 20 Mar 2012 08:24:57 +0100 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: TEXT/PLAIN Received: from euspt2 ([210.118.77.13]) by mailout3.w1.samsung.com (Sun Java(tm) System Messaging Server 6.3-8.04 (built Jul 29 2009; 32bit)) with ESMTP id <0M1600EZT9X76R40@mailout3.w1.samsung.com> for linux-mips@linux-mips.org; Tue, 20 Mar 2012 07:24:43 +0000 (GMT) Received: from linux.samsung.com ([106.116.38.10]) by spt2.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0M16007EE9XAS4@spt2.w1.samsung.com> for linux-mips@linux-mips.org; Tue, 20 Mar 2012 07:24:47 +0000 (GMT) Received: from mcdsrvbld02.digital.local (unknown [106.116.37.23]) by linux.samsung.com (Postfix) with ESMTP id 5AD4D270051; Tue, 20 Mar 2012 08:38:41 +0100 (CET) Date: Tue, 20 Mar 2012 08:24:43 +0100 From: Marek Szyprowski Subject: [GIT PULL] DMA-mapping framework updates for 3.4 To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , FUJITA Tomonori , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Marek Szyprowski , Kyungmin Park , Andrzej Pietrasiewicz Message-id: <1332228283-29077-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 32732 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.szyprowski@samsung.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4422 Lines: 96 Hi Linus, Please pull the dma-mapping framework updates for v3.4 since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7: Linux 3.3 with the top-most commit e749a9f707f1102735e02338fa564be86be3bb69 common: DMA-mapping: add NON-CONSISTENT attribute from the git repository at: git://git.infradead.org/users/kmpark/linux-samsung dma-mapping-next Those patches introduce a new alloc method (with support for memory attributes) in dma_map_ops structure, which will later replace dma_alloc_coherent and dma_alloc_writecombine functions. Thanks! Best regards Marek Szyprowski Samsung Poland R&D Center Patch summary: Andrzej Pietrasiewicz (9): X86: adapt for dma_map_ops changes MIPS: adapt for dma_map_ops changes PowerPC: adapt for dma_map_ops changes IA64: adapt for dma_map_ops changes SPARC: adapt for dma_map_ops changes Alpha: adapt for dma_map_ops changes SH: adapt for dma_map_ops changes Microblaze: adapt for dma_map_ops changes Unicore32: adapt for dma_map_ops changes Marek Szyprowski (6): common: dma-mapping: introduce alloc_attrs and free_attrs methods Hexagon: adapt for dma_map_ops changes common: dma-mapping: remove old alloc_coherent and free_coherent methods common: dma-mapping: introduce mmap method common: DMA-mapping: add WRITE_COMBINE attribute common: DMA-mapping: add NON-CONSISTENT attribute Documentation/DMA-attributes.txt | 19 +++++++++++++++++++ arch/alpha/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/alpha/kernel/pci-noop.c | 10 ++++++---- arch/alpha/kernel/pci_iommu.c | 10 ++++++---- arch/hexagon/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/hexagon/kernel/dma.c | 9 +++++---- arch/ia64/hp/common/sba_iommu.c | 11 ++++++----- arch/ia64/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/ia64/kernel/pci-swiotlb.c | 9 +++++---- arch/ia64/sn/pci/pci_dma.c | 9 +++++---- arch/microblaze/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/microblaze/kernel/dma.c | 10 ++++++---- arch/mips/cavium-octeon/dma-octeon.c | 16 ++++++++-------- arch/mips/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/mips/mm/dma-default.c | 8 ++++---- arch/powerpc/include/asm/dma-mapping.h | 24 ++++++++++++++++-------- arch/powerpc/kernel/dma-iommu.c | 10 ++++++---- arch/powerpc/kernel/dma-swiotlb.c | 4 ++-- arch/powerpc/kernel/dma.c | 10 ++++++---- arch/powerpc/kernel/ibmebus.c | 10 ++++++---- arch/powerpc/kernel/vio.c | 14 ++++++++------ arch/powerpc/platforms/cell/iommu.c | 16 +++++++++------- arch/powerpc/platforms/ps3/system-bus.c | 13 +++++++------ arch/sh/include/asm/dma-mapping.h | 28 ++++++++++++++++++---------- arch/sh/kernel/dma-nommu.c | 4 ++-- arch/sh/mm/consistent.c | 6 ++++-- arch/sparc/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/sparc/kernel/iommu.c | 10 ++++++---- arch/sparc/kernel/ioport.c | 18 ++++++++++-------- arch/sparc/kernel/pci_sun4v.c | 9 +++++---- arch/unicore32/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/unicore32/mm/dma-swiotlb.c | 4 ++-- arch/x86/include/asm/dma-mapping.h | 26 ++++++++++++++++---------- arch/x86/kernel/amd_gart_64.c | 11 ++++++----- arch/x86/kernel/pci-calgary_64.c | 9 +++++---- arch/x86/kernel/pci-dma.c | 3 ++- arch/x86/kernel/pci-nommu.c | 6 +++--- arch/x86/kernel/pci-swiotlb.c | 12 +++++++----- arch/x86/xen/pci-swiotlb-xen.c | 4 ++-- drivers/iommu/amd_iommu.c | 10 ++++++---- drivers/iommu/intel-iommu.c | 9 +++++---- drivers/xen/swiotlb-xen.c | 5 +++-- include/linux/dma-attrs.h | 2 ++ include/linux/dma-mapping.h | 13 +++++++++---- include/linux/swiotlb.h | 6 ++++-- include/xen/swiotlb-xen.h | 6 ++++-- lib/swiotlb.c | 5 +++-- 47 files changed, 338 insertions(+), 206 deletions(-) From khlebnikov@openvz.org Wed Mar 21 07:57:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Mar 2012 07:57:24 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:65200 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903609Ab2CUG5K (ORCPT ); Wed, 21 Mar 2012 07:57:10 +0100 Received: by bkcjk13 with SMTP id jk13so830554bkc.36 for ; Tue, 20 Mar 2012 23:57:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=z3EAZZR5A4YKqn52+p/sy8ERgiu2SfjKsuXn7KyuHEE=; b=KfCFI/BOJBJuQMwaYKHP0u4npyuuMLqv2erozPusHtBW9+jcVjM5hOAvpzFCRzydW7 q/pXVLfvZTB1VvEyIx0XDaGeRcx0H/i8f6jgKoqEwPK7v8vNJ2P1KqyQ3lzqqIFIlP4g jtizXZ6HMoc8eWsMn1lKVF+KVIVUSaCzY2VwrwLnpcF2RzI2IQVdlIq7dK5elPp7dsns beqpzy/HUZBXWpaiXf0jn6pKyZLxd5IPAV8UNES7gsgTJexn32RwpitkPCDGrVWg41zr jfmT6Al+zqoUGsXu91skjzKmpk7gL2kpeyI6eSTGYdQzvP+mdmhXzvt0BubZSmpkn+RJ TLHQ== Received: by 10.204.150.78 with SMTP id x14mr1012375bkv.114.1332313024885; Tue, 20 Mar 2012 23:57:04 -0700 (PDT) Received: from localhost (95-25-247-196.broadband.corbina.ru. [95.25.247.196]) by mx.google.com with ESMTPS id o7sm1377701bkw.16.2012.03.20.23.57.03 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Mar 2012 23:57:04 -0700 (PDT) Subject: [PATCH 12/16] mm/mips: use vm_flags_t for vma flags To: Andrew Morton From: Konstantin Khlebnikov Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org Date: Wed, 21 Mar 2012 10:57:02 +0400 Message-ID: <20120321065702.13852.81639.stgit@zurg> In-Reply-To: <20120321065140.13852.52315.stgit@zurg> References: <20120321065140.13852.52315.stgit@zurg> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-archive-position: 32733 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khlebnikov@openvz.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2477 Lines: 67 Signed-off-by: Konstantin Khlebnikov Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/mm/c-r3k.c | 2 +- arch/mips/mm/c-r4k.c | 6 +++--- arch/mips/mm/c-tx39.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 0765583..0ae0684 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -239,7 +239,7 @@ static void r3k_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) { unsigned long kaddr = KSEG0ADDR(pfn << PAGE_SHIFT); - int exec = vma->vm_flags & VM_EXEC; + int exec = (vma->vm_flags & VM_EXEC) != VM_NONE; struct mm_struct *mm = vma->vm_mm; pgd_t *pgdp; pud_t *pudp; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c97087d..94b2b89 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -394,7 +394,7 @@ static void r4k__flush_cache_vunmap(void) static inline void local_r4k_flush_cache_range(void * args) { struct vm_area_struct *vma = args; - int exec = vma->vm_flags & VM_EXEC; + int exec = (vma->vm_flags & VM_EXEC) != VM_NONE; if (!(has_valid_asid(vma->vm_mm))) return; @@ -407,7 +407,7 @@ static inline void local_r4k_flush_cache_range(void * args) static void r4k_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - int exec = vma->vm_flags & VM_EXEC; + int exec = (vma->vm_flags & VM_EXEC) != VM_NONE; if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) r4k_on_each_cpu(local_r4k_flush_cache_range, vma); @@ -457,7 +457,7 @@ static inline void local_r4k_flush_cache_page(void *args) struct vm_area_struct *vma = fcp_args->vma; unsigned long addr = fcp_args->addr; struct page *page = pfn_to_page(fcp_args->pfn); - int exec = vma->vm_flags & VM_EXEC; + int exec = (vma->vm_flags & VM_EXEC) != VM_NONE; struct mm_struct *mm = vma->vm_mm; int map_coherent = 0; pgd_t *pgdp; diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index a43c197c..1227670 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -169,7 +169,7 @@ static void tx39_flush_cache_range(struct vm_area_struct *vma, static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn) { - int exec = vma->vm_flags & VM_EXEC; + int exec = (vma->vm_flags & VM_EXEC) != VM_NONE; struct mm_struct *mm = vma->vm_mm; pgd_t *pgdp; pud_t *pudp; From m.szyprowski@samsung.com Wed Mar 21 14:43:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Mar 2012 14:44:11 +0100 (CET) Received: from mailout4.w1.samsung.com ([210.118.77.14]:28749 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903745Ab2CUNn6 (ORCPT ); Wed, 21 Mar 2012 14:43:58 +0100 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; charset=us-ascii Received: from euspt1 ([210.118.77.14]) by mailout4.w1.samsung.com (Sun Java(tm) System Messaging Server 6.3-8.04 (built Jul 29 2009; 32bit)) with ESMTP id <0M1800DADM54OF90@mailout4.w1.samsung.com> for linux-mips@linux-mips.org; Wed, 21 Mar 2012 13:43:52 +0000 (GMT) Received: from linux.samsung.com ([106.116.38.10]) by spt1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0M18008O5M51Q1@spt1.w1.samsung.com> for linux-mips@linux-mips.org; Wed, 21 Mar 2012 13:43:50 +0000 (GMT) Received: from AMDC159 (unknown [106.116.37.153]) by linux.samsung.com (Postfix) with ESMTP id 94D2B270055; Wed, 21 Mar 2012 14:43:57 +0100 (CET) Date: Wed, 21 Mar 2012 14:43:46 +0100 From: Marek Szyprowski Subject: RE: [GIT PULL] DMA-mapping framework updates for 3.4 In-reply-to: <1332228283-29077-1-git-send-email-m.szyprowski@samsung.com> To: Marek Szyprowski , 'Linus Torvalds' Cc: linux-kernel@vger.kernel.org, 'Benjamin Herrenschmidt' , 'Thomas Gleixner' , 'Andrew Morton' , 'Arnd Bergmann' , 'FUJITA Tomonori' , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, 'Jonathan Corbet' , 'Kyungmin Park' , Andrzej Pietrasiewicz Message-id: <079801cd0768$a3623d10$ea26b730$%szyprowski@samsung.com> Organization: SPRC X-Mailer: Microsoft Office Outlook 12.0 Content-language: pl Thread-index: Ac0Gaoh/WBn+OB0fQva36xRWNNJUlQA5kGmQ References: <1332228283-29077-1-git-send-email-m.szyprowski@samsung.com> X-archive-position: 32734 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.szyprowski@samsung.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2346 Lines: 56 Hello, On Tuesday, March 20, 2012 8:25 AM Marek Szyprowski wrote: > Hi Linus, > > Please pull the dma-mapping framework updates for v3.4 since commit > c16fa4f2ad19908a47c63d8fa436a1178438c7e7: > > Linux 3.3 > > with the top-most commit e749a9f707f1102735e02338fa564be86be3bb69 > > common: DMA-mapping: add NON-CONSISTENT attribute > > from the git repository at: > > git://git.infradead.org/users/kmpark/linux-samsung dma-mapping-next > > Those patches introduce a new alloc method (with support for memory > attributes) in dma_map_ops structure, which will later replace > dma_alloc_coherent and dma_alloc_writecombine functions. I've been pointed out that this summary is quite short and misses the main rationale for the proposed changes. A few limitations have been identified in the current dma-mapping design and its implementations for various architectures. There exist more than one function for allocating and freeing the buffers: currently these 3 are used dma_{alloc, free}_coherent, dma_{alloc,free}_writecombine, dma_{alloc,free}_noncoherent. For most of the systems these calls are almost equivalent and can be interchanged. For others, especially the truly non-coherent ones (like ARM), the difference can be easily noticed in overall driver performance. Sadly not all architectures provide implementations for all of them, so the drivers might need to be adapted and cannot be easily shared between different architectures. The provided patches unify all these functions and hide the differences under the already existing dma attributes concept. The thread with more references is available here: http://www.spinics.net/lists/linux-sh/msg09777.html These patches are also a prerequisite for unifying DMA-mapping implementation on ARM architecture with the common one provided by dma_map_ops structure and extending it with IOMMU support. More information is available in the following thread: http://thread.gmane.org/gmane.linux.kernel.cross-arch/12819 More works on dma-mapping framework are planned, especially in the area of buffer sharing and managing the shared mappings (together with the recently introduced dma_buf interface: commit d15bd7ee445d0702ad801fdaece348fdb79e6581 "dma-buf: Introduce dma buffer sharing mechanism" ). Best regards -- Marek Szyprowski Samsung Poland R&D Center From dedekind1@gmail.com Wed Mar 21 14:58:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Mar 2012 14:59:02 +0100 (CET) Received: from mga03.intel.com ([143.182.124.21]:61469 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901173Ab2CUN6z (ORCPT ); Wed, 21 Mar 2012 14:58:55 +0100 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 21 Mar 2012 06:58:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="asc'?scan'208";a="121512624" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by azsmga001.ch.intel.com with ESMTP; 21 Mar 2012 06:58:46 -0700 Received: from [10.237.72.167] (sauron.fi.intel.com [10.237.72.167]) by linux.intel.com (Postfix) with ESMTP id 979592C8001; Wed, 21 Mar 2012 06:58:43 -0700 (PDT) Message-ID: <1332338496.14983.7.camel@sauron.fi.intel.com> Subject: Re: [PATCH] MIPS: Kbuild: remove -Werror From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, MTD Maling List , John Crispin Date: Wed, 21 Mar 2012 16:01:36 +0200 In-Reply-To: <1331292947-14913-1-git-send-email-dedekind1@gmail.com> References: <1331292947-14913-1-git-send-email-dedekind1@gmail.com> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-8fUx/z2EktEUi1++CT0s" X-Mailer: Evolution 3.2.3 (3.2.3-1.fc16) Mime-Version: 1.0 X-archive-position: 32735 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1519 Lines: 45 --=-8fUx/z2EktEUi1++CT0s Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2012-03-09 at 13:35 +0200, Artem Bityutskiy wrote: > From: Artem Bityutskiy >=20 > MIPS does not build with the standard W=3D1 Kbuild switch with - tested w= ith > gcc-4.6 by me and gcc-4.5 by John Crispin. The reason is that MIPS adds Hi Ralf, what's the fate of this patch? --=20 Best Regards, Artem Bityutskiy --=-8fUx/z2EktEUi1++CT0s Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPad9AAAoJECmIfjd9wqK0gvwP/RIFHMvlayHuShAnh9Ingceh rX/qO7QN1yEGZEnIol05Jsbo0wCtsltRDJklGhpsiEIr3TQdnQzu+6V5hYG85S/n 78CodPiRysw4K1trsyb7DUGhWHAI/rU2wuv//UAcCgQ/rdTkBGjgTtLkpx8vlg03 es+2+nAIAgI1szQjwXqTmBDxPACwmYRq/+S9/bruysNR9xEtRnNkJ30YDkAMT/yZ 2oYStUi8elJtX+Ec4X5lSoT3YmycXRH2TIs5WbaVY/Y7Pf4ZXEvX1VFZunWowokT wnVh7R8lV5/nmGGRNplFWJy3j2EpHVFb2SimxcrGeTfq9Qoh7tc49QTX5PBq/CqR Ne+Tahjjdi6QweFGYBYqVCUeypeh4+wO6dAYHh1eh+aDGb4DWVurNsTR9ESPuxXw Rv5gHEU1WythsvFs8jQoV+QjmzMGwRngIqyvk6SS0STvpot2h4WIw+pmM3W3jcwE r52FbH5p22z+Y8MhBmT49qpKYsp5/dOaLy4o9BcEJyeQoNI6Vt9fDxyYckFYR0Zy GpAgH+Gg26DFYjl4maA+RPU9mamkbWRaLykhoU60G9eH9AMZWQIyVDfRb7Th3jaH eqKAQHNZfPqp3L824S7A6FeTTDtblPRZW87LkBAYXWBs+CQdhvjAGQdfaoR4AgAt aP6xjcZsMsjQLaEqb2e2 =/UiI -----END PGP SIGNATURE----- --=-8fUx/z2EktEUi1++CT0s-- From raghavendra.kt@linux.vnet.ibm.com Thu Mar 22 10:56:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Mar 2012 10:56:29 +0100 (CET) Received: from e23smtp06.au.ibm.com ([202.81.31.148]:52863 "EHLO e23smtp06.au.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903627Ab2CVJ4T (ORCPT ); Thu, 22 Mar 2012 10:56:19 +0100 Received: from /spool/local by e23smtp06.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 22 Mar 2012 09:51:29 +1000 Received: from d23relay03.au.ibm.com (202.81.31.245) by e23smtp06.au.ibm.com (202.81.31.212) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Thu, 22 Mar 2012 09:51:23 +1000 Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay03.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q2M9tkY2987184; Thu, 22 Mar 2012 20:55:46 +1100 Received: from d23av04.au.ibm.com (loopback [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q2M9tj7W005777; Thu, 22 Mar 2012 20:55:46 +1100 Received: from [9.124.158.167] ([9.124.158.167]) by d23av04.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q2M9tQSH005396; Thu, 22 Mar 2012 20:55:43 +1100 From: Raghavendra K T To: Ingo Molnar , "H. Peter Anvin" Cc: Linus Torvalds , Ralf Baechle , Chris Metcalf , Thomas Gleixner , x86@kernel.org, Chris Zankel , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Date: Thu, 22 Mar 2012 15:25:08 +0530 Message-Id: <20120322095502.30866.75756.sendpatchset@codeblue> Subject: [PATCH 1/1] config: simplify INLINE_SPIN_UNLOCK x-cbid: 12032123-7014-0000-0000-000000C50D9E X-archive-position: 32736 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghavendra.kt@linux.vnet.ibm.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5550 Lines: 145 From: Raghavendra K T Patch simplifies current INLINE_SPIN_UNLOCK. compile tested on x86_64 Change log: get rid of INLINE_SPIN_UNLOCK entirely replacing it with UNINLINE_SPIN_UNLOCK instead with the reverse meaning. whover wants to uninline the spinlocks (like spinlock debugging, paravirt etc all just do select UNINLINE_SPIN_UNLOCK Suggested-by: Linus Torvalds Signed-off-by: Raghavendra K T --- Please refer : https://lkml.org/lkml/2012/3/21/357 arch/mips/configs/db1300_defconfig | 2 +- arch/tile/configs/tilegx_defconfig | 2 +- arch/tile/configs/tilepro_defconfig | 2 +- arch/xtensa/configs/iss_defconfig | 2 +- include/linux/spinlock_api_smp.h | 2 +- kernel/Kconfig.locks | 4 ++-- kernel/Kconfig.preempt | 1 + kernel/spinlock.c | 2 +- lib/Kconfig.debug | 1 + 9 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig index c38b190..3590ab5 100644 --- a/arch/mips/configs/db1300_defconfig +++ b/arch/mips/configs/db1300_defconfig @@ -133,7 +133,7 @@ CONFIG_BLK_DEV_BSG=y CONFIG_IOSCHED_NOOP=y CONFIG_DEFAULT_NOOP=y CONFIG_DEFAULT_IOSCHED="noop" -CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_UNINLINE_SPIN_UNLOCK is not set CONFIG_INLINE_SPIN_UNLOCK_IRQ=y CONFIG_INLINE_READ_UNLOCK=y CONFIG_INLINE_READ_UNLOCK_IRQ=y diff --git a/arch/tile/configs/tilegx_defconfig b/arch/tile/configs/tilegx_defconfig index dafdbba..db93926 100644 --- a/arch/tile/configs/tilegx_defconfig +++ b/arch/tile/configs/tilegx_defconfig @@ -187,7 +187,7 @@ CONFIG_PADATA=y # CONFIG_INLINE_SPIN_LOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK_IRQ is not set # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_UNINLINE_SPIN_UNLOCK is not set # CONFIG_INLINE_SPIN_UNLOCK_BH is not set CONFIG_INLINE_SPIN_UNLOCK_IRQ=y # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set diff --git a/arch/tile/configs/tilepro_defconfig b/arch/tile/configs/tilepro_defconfig index 6f05f96..a039032 100644 --- a/arch/tile/configs/tilepro_defconfig +++ b/arch/tile/configs/tilepro_defconfig @@ -153,7 +153,7 @@ CONFIG_DEFAULT_IOSCHED="noop" # CONFIG_INLINE_SPIN_LOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK_IRQ is not set # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_UNINLINE_SPIN_UNLOCK is not set # CONFIG_INLINE_SPIN_UNLOCK_BH is not set CONFIG_INLINE_SPIN_UNLOCK_IRQ=y # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set diff --git a/arch/xtensa/configs/iss_defconfig b/arch/xtensa/configs/iss_defconfig index f932b30..ddab37b 100644 --- a/arch/xtensa/configs/iss_defconfig +++ b/arch/xtensa/configs/iss_defconfig @@ -113,7 +113,7 @@ CONFIG_DEFAULT_IOSCHED="noop" # CONFIG_INLINE_SPIN_LOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK_IRQ is not set # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_UNINLINE_SPIN_UNLOCK is not set # CONFIG_INLINE_SPIN_UNLOCK_BH is not set CONFIG_INLINE_SPIN_UNLOCK_IRQ=y # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set diff --git a/include/linux/spinlock_api_smp.h b/include/linux/spinlock_api_smp.h index e253ccd..51df117 100644 --- a/include/linux/spinlock_api_smp.h +++ b/include/linux/spinlock_api_smp.h @@ -67,7 +67,7 @@ _raw_spin_unlock_irqrestore(raw_spinlock_t *lock, unsigned long flags) #define _raw_spin_trylock_bh(lock) __raw_spin_trylock_bh(lock) #endif -#ifdef CONFIG_INLINE_SPIN_UNLOCK +#ifndef CONFIG_UNINLINE_SPIN_UNLOCK #define _raw_spin_unlock(lock) __raw_spin_unlock(lock) #endif diff --git a/kernel/Kconfig.locks b/kernel/Kconfig.locks index 5068e2a..2251882 100644 --- a/kernel/Kconfig.locks +++ b/kernel/Kconfig.locks @@ -124,8 +124,8 @@ config INLINE_SPIN_LOCK_IRQSAVE def_bool !DEBUG_SPINLOCK && !GENERIC_LOCKBREAK && \ ARCH_INLINE_SPIN_LOCK_IRQSAVE -config INLINE_SPIN_UNLOCK - def_bool !DEBUG_SPINLOCK && (!PREEMPT || ARCH_INLINE_SPIN_UNLOCK) +config UNINLINE_SPIN_UNLOCK + bool config INLINE_SPIN_UNLOCK_BH def_bool !DEBUG_SPINLOCK && ARCH_INLINE_SPIN_UNLOCK_BH diff --git a/kernel/Kconfig.preempt b/kernel/Kconfig.preempt index 24e7cb0..3f9c974 100644 --- a/kernel/Kconfig.preempt +++ b/kernel/Kconfig.preempt @@ -36,6 +36,7 @@ config PREEMPT_VOLUNTARY config PREEMPT bool "Preemptible Kernel (Low-Latency Desktop)" select PREEMPT_COUNT + select UNINLINE_SPIN_UNLOCK if !ARCH_INLINE_SPIN_UNLOCK help This option reduces the latency of the kernel by making all kernel code (that is not executing in a critical section) diff --git a/kernel/spinlock.c b/kernel/spinlock.c index 84c7d96..5cdd806 100644 --- a/kernel/spinlock.c +++ b/kernel/spinlock.c @@ -163,7 +163,7 @@ void __lockfunc _raw_spin_lock_bh(raw_spinlock_t *lock) EXPORT_SYMBOL(_raw_spin_lock_bh); #endif -#ifndef CONFIG_INLINE_SPIN_UNLOCK +#ifdef CONFIG_UNINLINE_SPIN_UNLOCK void __lockfunc _raw_spin_unlock(raw_spinlock_t *lock) { __raw_spin_unlock(lock); diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 8745ac7..286b8af 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -495,6 +495,7 @@ config RT_MUTEX_TESTER config DEBUG_SPINLOCK bool "Spinlock and rw-lock debugging: basic checks" depends on DEBUG_KERNEL + select UNINLINE_SPIN_UNLOCK help Say Y here and build SMP to catch missing spinlock initialization and certain other kinds of spinlock errors commonly made. This is From raghavendra.kt@linux.vnet.ibm.com Fri Mar 23 07:24:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Mar 2012 07:24:59 +0100 (CET) Received: from e28smtp09.in.ibm.com ([122.248.162.9]:33587 "EHLO e28smtp09.in.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903747Ab2CWGYx (ORCPT ); Fri, 23 Mar 2012 07:24:53 +0100 Received: from /spool/local by e28smtp09.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 23 Mar 2012 11:54:42 +0530 Received: from d28relay04.in.ibm.com (9.184.220.61) by e28smtp09.in.ibm.com (192.168.1.139) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 23 Mar 2012 11:54:38 +0530 Received: from d28av05.in.ibm.com (d28av05.in.ibm.com [9.184.220.67]) by d28relay04.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q2N6OZsJ4505622; Fri, 23 Mar 2012 11:54:36 +0530 Received: from d28av05.in.ibm.com (loopback [127.0.0.1]) by d28av05.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q2NBt3IL023394; Fri, 23 Mar 2012 22:55:04 +1100 Received: from [9.77.196.243] ([9.77.196.243]) by d28av05.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q2NBsxcP023171; Fri, 23 Mar 2012 22:55:00 +1100 Message-ID: <4F6C170A.4070305@linux.vnet.ibm.com> Date: Fri, 23 Mar 2012 11:54:10 +0530 From: Raghavendra K T Organization: IBM User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.1) Gecko/20120216 Thunderbird/10.0.1 MIME-Version: 1.0 To: Linus Torvalds CC: Raghavendra K T , Ingo Molnar , "H. Peter Anvin" , Ralf Baechle , Chris Metcalf , Thomas Gleixner , x86@kernel.org, Chris Zankel , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/1] config: simplify INLINE_SPIN_UNLOCK References: <20120322095502.30866.75756.sendpatchset@codeblue> In-Reply-To: <20120322095502.30866.75756.sendpatchset@codeblue> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit x-cbid: 12032306-2674-0000-0000-000003CF0D5D X-archive-position: 32737 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghavendra.kt@linux.vnet.ibm.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 850 Lines: 24 On 03/22/2012 03:25 PM, Raghavendra K T wrote: > From: Raghavendra K T > > Patch simplifies current INLINE_SPIN_UNLOCK. compile tested on x86_64 > > Change log: > get rid of INLINE_SPIN_UNLOCK entirely replacing it with UNINLINE_SPIN_UNLOCK > instead with the reverse meaning. > > whover wants to uninline the spinlocks (like spinlock debugging, paravirt etc > all just do select UNINLINE_SPIN_UNLOCK typo: Whoever wants to uninline the spinlocks (like spinlock debugging, paravirt etc) just do select UNINLINE_SPIN_UNLOCK. > > Suggested-by: Linus Torvalds > Signed-off-by: Raghavendra K T > --- > Please refer : https://lkml.org/lkml/2012/3/21/357 Linus, Please let me know if this is what you were looking for or Did I really mess it up :( From mingo@kernel.org Fri Mar 23 09:43:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Mar 2012 09:43:30 +0100 (CET) Received: from mail-we0-f177.google.com ([74.125.82.177]:56338 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903740Ab2CWInM (ORCPT ); Fri, 23 Mar 2012 09:43:12 +0100 Received: by werp11 with SMTP id p11so3022278wer.36 for ; Fri, 23 Mar 2012 01:43:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=y9/YuVmbfW6KZQKV9opavUw4Z09nAKTjX1L1hhla8KU=; b=mcG60m9Hvx+1R/I9lhBkReSLEWOCi6SIIl0G1RIXy0ZwT1656Y3jr4ps60okvzGBI1 uGUvpf9Gb9oJdeoU/V6g4GSUKAfmS1FFU9oVb4lLfdivmcYgU2l35AavJ+1k7r57iqXM yunJqeRM5HfTjrN6SaFgBMDg4Q2Jpn1L2Yvd+7pGQ4X60DN4n/QzObhrptZ3vXi0Mhbd p9CoTKNsjMnHyCTqinFt1zL6EtjRMcC5gWTSVI9mepHW5meEZfa4DzfFi0WT32M0bmFi uQXt5jtiwK7aGGt0o1yvSe2yjRhyaWFL0pM5e9og/wNut2pSy4pR2MeWuFrBRftV9tPZ xkzA== Received: by 10.180.82.136 with SMTP id i8mr4395514wiy.19.1332492187290; Fri, 23 Mar 2012 01:43:07 -0700 (PDT) Received: from gmail.com (54033750.catv.pool.telekom.hu. [84.3.55.80]) by mx.google.com with ESMTPS id ff9sm12141362wib.2.2012.03.23.01.43.06 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 23 Mar 2012 01:43:06 -0700 (PDT) Date: Fri, 23 Mar 2012 09:43:04 +0100 From: Ingo Molnar To: Raghavendra K T Cc: Linus Torvalds , Ingo Molnar , "H. Peter Anvin" , Ralf Baechle , Chris Metcalf , Thomas Gleixner , x86@kernel.org, Chris Zankel , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/1] config: simplify INLINE_SPIN_UNLOCK Message-ID: <20120323084304.GD2886@gmail.com> References: <20120322095502.30866.75756.sendpatchset@codeblue> <4F6C170A.4070305@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4F6C170A.4070305@linux.vnet.ibm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32738 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@kernel.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1053 Lines: 33 * Raghavendra K T wrote: > On 03/22/2012 03:25 PM, Raghavendra K T wrote: > >From: Raghavendra K T > > > >Patch simplifies current INLINE_SPIN_UNLOCK. compile tested on x86_64 > > > >Change log: > >get rid of INLINE_SPIN_UNLOCK entirely replacing it with UNINLINE_SPIN_UNLOCK > >instead with the reverse meaning. > > > >whover wants to uninline the spinlocks (like spinlock debugging, paravirt etc > >all just do select UNINLINE_SPIN_UNLOCK > typo: > Whoever wants to uninline the spinlocks (like spinlock debugging, > paravirt etc) just do select UNINLINE_SPIN_UNLOCK. > > > > >Suggested-by: Linus Torvalds > >Signed-off-by: Raghavendra K T > >--- > > Please refer : https://lkml.org/lkml/2012/3/21/357 > > Linus, Please let me know if this is what you were looking for or > Did I really mess it up :( Looks sane to me at first sight - will process it once the merge window calms down a bit. Thanks, Ingo From torvalds@linux-foundation.org Fri Mar 23 16:53:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Mar 2012 16:53:47 +0100 (CET) Received: from mail-wg0-f43.google.com ([74.125.82.43]:41401 "EHLO mail-wg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903645Ab2CWPxa (ORCPT ); Fri, 23 Mar 2012 16:53:30 +0100 Received: by wgbdr12 with SMTP id dr12so1964615wgb.24 for ; Fri, 23 Mar 2012 08:53:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type; bh=VPhYLDJPneZ0P6gUrHlX4wNILCSqKg2JnH1/69P/D1E=; b=NZ1TIEjBRDu84cRGMu9AJcr8oIA7vPg2SYucnn4kUBpZkzS38aiADGwL6Js3Fs4yKa NA8SIsRh7xKB8Ga/t7pMuS5/Y3p7/g2UZLOC4ii2jD5nSn3t+eyHnXzOF3CQVm2LlI6D YC1/V8JW/AdPi8DluT+fts3aOnv5Q0lydA4mMzy+DmxSPrEbfStKN83UP+K3/csXF/4r 9gfQbwpSD1KSbNPxK2JnKltkXbk5IEXMl2+JQjwErr8VGvImAA6CDxpAnXHkbOqXz/Sr ymyLdjRcqgLPRBEqGsAjP5U7QdKBdVwRUmHP46cg6RW7Exjnk+cmgIiz2DNaNve06yJ7 ZobQ== Received: by 10.180.96.228 with SMTP id dv4mr7691118wib.14.1332518005089; Fri, 23 Mar 2012 08:53:25 -0700 (PDT) MIME-Version: 1.0 Received: by 10.180.103.163 with HTTP; Fri, 23 Mar 2012 08:53:04 -0700 (PDT) In-Reply-To: <4F6C170A.4070305@linux.vnet.ibm.com> References: <20120322095502.30866.75756.sendpatchset@codeblue> <4F6C170A.4070305@linux.vnet.ibm.com> From: Linus Torvalds Date: Fri, 23 Mar 2012 08:53:04 -0700 X-Google-Sender-Auth: 6YL5vu6hVji0V6UpdjbHWigOhqc Message-ID: Subject: Re: [PATCH 1/1] config: simplify INLINE_SPIN_UNLOCK To: Raghavendra K T Cc: Ingo Molnar , "H. Peter Anvin" , Ralf Baechle , Chris Metcalf , Thomas Gleixner , x86@kernel.org, Chris Zankel , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 32739 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: torvalds@linux-foundation.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 468 Lines: 12 On Thu, Mar 22, 2012 at 11:24 PM, Raghavendra K T wrote: > > Linus, Please let me know if this is what you were looking for or Did I > really mess it up :( Yeah, this was what I was looking for. It seems much simpler to me, and allows the individual odd config options to just do the "select uninline" instead of having to have some complex logic about other config options in the inlining option itself. Linus From yinghai@kernel.org Fri Mar 23 20:58:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Mar 2012 20:59:06 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:54650 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903743Ab2CWT6t (ORCPT ); Fri, 23 Mar 2012 20:58:49 +0100 Received: by ghbf11 with SMTP id f11so3521549ghb.36 for ; Fri, 23 Mar 2012 12:58:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=d4YsueQhxRnHc0UWeewTYDSgCMltmgm8o+XEUQCQFcQ=; b=uRzh3y5RNpiCTk0MpNHuneU+6ZSL/iQ5XxqDxBr3B3+j2+lM7gUOdNvupVmzd+dIN5 rxL5ZQIetXkYAs/4Cr7pRtBhy58CoGCGPBBQX1lmBBM7wKNcm2MPLjjsfMh11MFCwNd5 ZjlNw1mdQwMS4jgJ/8+/iq8sl/ttTJ5tQ+MjbQARgoYZ3ya3gQzhEu2pKoDqozn0yFph hWMam3aRMdLYb1VoQs9TkXvGxlSg7Ni4F/NO42nYdppBZSjgAZ4TVI2sQ6yTqrBXtXFm b6C8Q6jbmtAsExy7SI9sJg3PNa5GNTDCswOVyVvbdgOSgP+CP2d5h498Y1pmR8RkIw8K dqEQ== MIME-Version: 1.0 Received: by 10.68.222.227 with SMTP id qp3mr31685216pbc.137.1332532722275; Fri, 23 Mar 2012 12:58:42 -0700 (PDT) Received: by 10.142.154.20 with HTTP; Fri, 23 Mar 2012 12:58:42 -0700 (PDT) In-Reply-To: <20120322144817.796e3a8a@jbarnes-desktop> References: <20120322144817.796e3a8a@jbarnes-desktop> Date: Fri, 23 Mar 2012 12:58:42 -0700 X-Google-Sender-Auth: r5SIuiDvAq_Wo13YggsR-nTyK3o Message-ID: Subject: Re: [git pull] PCI changes (including maintainer change) From: Yinghai Lu To: Jesse Barnes , Ralf Baechle , Linus Torvalds , Benjamin Herrenschmidt , Paul Mackerras , Bjorn Helgaas , Grant Likely , Rob Herring Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, devicetree-discuss@lists.ozlabs.org Content-Type: multipart/mixed; boundary=047d7b2eded39014da04bbee73ee X-archive-position: 32740 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yinghai@kernel.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 37992 Lines: 517 --047d7b2eded39014da04bbee73ee Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On Thu, Mar 22, 2012 at 2:48 PM, Jesse Barnes wr= ote: > The following changes since commit > 4f262acfde22b63498b5e4f165e53d3bb4e96400: > > =A0Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm (201= 2-03-07 08:33:03 -0800) > > are available in the git repository at: > > =A0git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci linux-next > > This pull has some good cleanups from Bjorn and Yinghai, as well as > some more code from Yinghai to better handle resource re-allocation > when enabled. > > There's also a new initcall_debug feature from Arjan which will print > out quirk timing information to help identify slow quirks for fixing or > refinement (Yinghai sent in a few patches to do just that once the new > debug code landed). > > Beyond that, I'm handing off PCI maintainership to Bjorn Helgaas. =A0He's > been a core PCI and Linux contributor for some time now, and has kindly > volunteered to take over. =A0I just don't feel I have the time for PCI > review and work that it deserves lately (I've taken on some other > projects), and haven't been as responsive lately as I'd like, so I > approached Bjorn asking if he'd like to manage things. =A0He's going to > give it a try, and I'm confident he'll do at least as well as I have in > keeping the tree managed, patches flowing, and keeping things stable. > There are some merge conflicts. Hope attached patch could help Linus a little bit. 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