From zumeng.chen@windriver.com Wed Feb 1 09:53:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Feb 2012 09:53:31 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:54626 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903548Ab2BAIxX (ORCPT ); Wed, 1 Feb 2012 09:53:23 +0100 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q118qsAu018788 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Wed, 1 Feb 2012 00:52:54 -0800 (PST) Received: from [128.224.162.181] (128.224.162.181) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server id 14.1.255.0; Wed, 1 Feb 2012 00:52:53 -0800 Message-ID: <4F28FCFC.4000601@windriver.com> Date: Wed, 1 Feb 2012 16:51:08 +0800 From: Zumeng Chen User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.24) Gecko/20111108 Lightning/1.0b2 Thunderbird/3.1.16 MIME-Version: 1.0 To: Hugh Dickins CC: , , , , , , Subject: Re: [PATCH 1/1] mm: msync: fix issues of sys_msync on tmpfs References: <1327036719-1965-1-git-send-email-zumeng.chen@windriver.com> In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 32380 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zumeng.chen@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5084 Lines: 132 于 2012年01月22日 04:53, Hugh Dickins 写道: > On Fri, 20 Jan 2012, Zumeng Chen wrote: > >> This patch fixes two issues as follows: > Two issues? You write of a cache aliasing issue, I don't see a second. Hi Hugh, I'm very sorry for delay reply due to the Spring Festival holiday. Yes, I missed one due to just a cosmetic one :-) >> For some filesystem with fsync == noop_fsync, there is not so much thing >> to do, so sys_msync just passes by for all arches but some CPUs. >> >> For some CPUs with cache aliases(dmesg|grep alias), it maybe has an issue, >> which reported by msync test suites in ltp-full when the memory of memset >> used by msync01 runs into cache alias randomly. >> >> Consider the following scenario used by msync01 in ltp-full: >> fildes = open(TEMPFILE, O_RDWR | O_CREAT, 0666))< 0); >> .../* initialization fildes by write(fildes); */ >> addr = mmap(0, page_sz, PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, >> fildes, 0); >> /* set buf with memset */ >> memset(addr + OFFSET_1, 1, BUF_SIZE); >> >> /* msync the addr before using, or MS_SYNC*/ >> msync(addr, page_sz, MS_ASYNC) > Actually, that MS_ASYNC msync() does nothing at all but validate its > arguments these days, even on filesystems with an effective fsync(). > We write out dirty pages to disk in good time, msync() or not. You are absolutely right here, although MS_SYNC is still failure in ltp's msync01. >> /* Tries to read fildes */ >> lseek(fildes, (off_t) OFFSET_1, SEEK_SET) != (off_t) OFFSET_1) { >> nread = read(fildes, read_buf, sizeof(read_buf)); > My grasp of cache aliasing issues is very poor, please excuse me if I'm > wrong; but I don't think a patch to msync() should be necessary at all > (and ltp's msync01 test is testing nothing more than args to msync()). Agreed, you are right. It is not a good way to fix this issue in mm level. > In the case of tmpfs, that read() system call above should route through > to mm/shmem.c do_shmem_file_read(), which contains these same lines as > the more common mm/filemap.c do_generic_file_read(): > > /* If users can be writing to this page using arbitrary > * virtual addresses, take care about potential aliasing > * before reading the page on the kernel side. > */ > if (mapping_writably_mapped(mapping)) > flush_dcache_page(page); Yes, this is good start here, thanks Hugh. > The mapping_writably_mapped() test ought to be succeeding in this case > (please check with printk's, perhaps some change has messed that up), > so flush_dcache_page(page) should be called, and any aliasing issues > resolved before the data is copied back to userspace. I guess we have to flush from INDEX_BASE to waysize instead of only current page passed from msync. > I assume your problem is on MIPS, since you copied Ralf and linux-mips: > if the MIPS flush_dcache_page() is not working right, then you'll need > to follow up with them. Since some MIPS CPUs have cache alias, so we have to flush_dcache_range instead of flush_dcache_page to avoid cache alias. I'll send to Ralf for more knowledges. Regards, Zumeng > Hugh > >> /* Then test the result */ >> if (read_buf[count] != 1) { >> >> The test result is random too for CPUs with cache alias. So in this >> situation, we have to flush the related vma to make sure the read is >> correct. >> >> Signed-off-by: Zumeng Chen >> --- >> mm/msync.c | 30 ++++++++++++++++++++++++++++++ >> 1 files changed, 30 insertions(+), 0 deletions(-) >> >> diff --git a/mm/msync.c b/mm/msync.c >> index 632df45..0021a7e 100644 >> --- a/mm/msync.c >> +++ b/mm/msync.c >> @@ -13,6 +13,14 @@ >> #include >> #include >> #include >> +#include >> + >> +/* Cache aliases should be taken into accounts when msync. */ >> +#ifdef cpu_has_dc_aliases >> +#define CPU_HAS_CACHE_ALIAS cpu_has_dc_aliases >> +#else >> +#define CPU_HAS_CACHE_ALIAS 0 >> +#endif >> >> /* >> * MS_SYNC syncs the entire file - including mappings. >> @@ -78,6 +86,28 @@ SYSCALL_DEFINE3(msync, unsigned long, start, size_t, len, int, flags) >> } >> file = vma->vm_file; >> start = vma->vm_end; >> + >> + /* >> + * For some filesystems with fsync == noop_fsync, msync just >> + * passes by but some CPUs. >> + * For CPUs with cache alias, msync has to flush the related >> + * vma explicitly to make sure data coherency between memory >> + * and cache, which includes MS_SYNC or MS_ASYNC. That is to >> + * say, cache aliases should not be an async factor, so does >> + * msync on other arches without cache aliases. >> + */ >> + if (file&& file->f_op&& file->f_op->fsync == noop_fsync) { >> + if (CPU_HAS_CACHE_ALIAS) >> + flush_cache_range(vma, vma->vm_start, >> + vma->vm_end); >> + if (start>= end) { >> + error = 0; >> + goto out_unlock; >> + } >> + vma = find_vma(mm, start); >> + continue; >> + } >> + >> if ((flags& MS_SYNC)&& file&& >> (vma->vm_flags& VM_SHARED)) { >> get_file(file); >> -- >> 1.7.0.4 From florian@openwrt.org Wed Feb 1 11:14:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Feb 2012 11:14:43 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:57561 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903548Ab2BAKOg (ORCPT ); Wed, 1 Feb 2012 11:14:36 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 1081C447306; Wed, 1 Feb 2012 11:14:36 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id l9IZ-ZENd36p; Wed, 1 Feb 2012 11:14:35 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 7E8F24451A7; Wed, 1 Feb 2012 11:14:35 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, spi-devel-general@lists.sourceforge.net, Florian Fainelli , Tanguy Bouzeloc Subject: [PATCH v4] spi: add Broadcom BCM63xx SPI controller driver Date: Wed, 1 Feb 2012 11:14:09 +0100 Message-Id: <1328091249-10389-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-10-git-send-email-florian@openwrt.org> References: <1328019048-5892-10-git-send-email-florian@openwrt.org> X-archive-position: 32381 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 14640 Lines: 555 This patch adds support for the SPI controller found on the Broadcom BCM63xx SoCs. Signed-off-by: Tanguy Bouzeloc Signed-off-by: Florian Fainelli Acked-by: Grant Likely --- Changes since v3: - changed bcm_spi_readb to use readb accessor instead of readw - fixed multiple __dev{init,exit} annotations Changes since v2: - reworked bcm63xx_spi_setup_transfer to choose closest spi transfer frequency - removed invalid 25Mhz frequency - fixed some minor checkpatch issues Changes since v1: - switched to the devm_* API which frees resources automatically - switched to dev_pm_ops - use module_platform_driver - remove MODULE_VERSION() - fixed return value when clock is not present using PTR_ERR() - fixed probe() error path to disable clock in case of failure drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/spi-bcm63xx.c | 486 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 493 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/spi-bcm63xx.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3f9a47e..16818ac 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -94,6 +94,12 @@ config SPI_AU1550 If you say yes to this option, support will be included for the PSC SPI controller found on Au1550, Au1200 and Au1300 series. +config SPI_BCM63XX + tristate "Broadcom BCM63xx SPI controller" + depends on BCM63XX + help + Enable support for the SPI controller on the Broadcom BCM63xx SoCs. + config SPI_BITBANG tristate "Utilities for Bitbanging SPI masters" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 61c3261..be38f73 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.o obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o obj-$(CONFIG_SPI_ATH79) += spi-ath79.o obj-$(CONFIG_SPI_AU1550) += spi-au1550.o +obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c new file mode 100644 index 0000000..f01b264 --- /dev/null +++ b/drivers/spi/spi-bcm63xx.c @@ -0,0 +1,486 @@ +/* + * Broadcom BCM63xx SPI controller support + * + * Copyright (C) 2009-2011 Florian Fainelli + * Copyright (C) 2010 Tanguy Bouzeloc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PFX KBUILD_MODNAME +#define DRV_VER "0.1.2" + +struct bcm63xx_spi { + spinlock_t lock; + int stopping; + struct completion done; + + void __iomem *regs; + int irq; + + /* Platform data */ + u32 speed_hz; + unsigned fifo_size; + + /* Data buffers */ + const unsigned char *tx_ptr; + unsigned char *rx_ptr; + + /* data iomem */ + u8 __iomem *tx_io; + const u8 __iomem *rx_io; + + int remaining_bytes; + + struct clk *clk; + struct platform_device *pdev; +}; + +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, + unsigned int offset) +{ + return bcm_readb(bs->regs + bcm63xx_spireg(offset)); +} + +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, + unsigned int offset) +{ + return bcm_readw(bs->regs + bcm63xx_spireg(offset)); +} + +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, + u8 value, unsigned int offset) +{ + bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); +} + +static inline void bcm_spi_writew(struct bcm63xx_spi *bs, + u16 value, unsigned int offset) +{ + bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); +} + +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { + { 20000000, SPI_CLK_20MHZ }, + { 12500000, SPI_CLK_12_50MHZ }, + { 6250000, SPI_CLK_6_250MHZ }, + { 3125000, SPI_CLK_3_125MHZ }, + { 1563000, SPI_CLK_1_563MHZ }, + { 781000, SPI_CLK_0_781MHZ }, + { 391000, SPI_CLK_0_391MHZ } +}; + +static int bcm63xx_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) +{ + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); + u8 bits_per_word; + u8 clk_cfg, reg; + u32 hz; + int i; + + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; + hz = (t) ? t->speed_hz : spi->max_speed_hz; + if (bits_per_word != 8) { + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", + __func__, bits_per_word); + return -EINVAL; + } + + if (spi->chip_select > spi->master->num_chipselect) { + dev_err(&spi->dev, "%s, unsupported slave %d\n", + __func__, spi->chip_select); + return -EINVAL; + } + + /* Find the closest clock configuration */ + for (i = 0; i < SPI_CLK_MASK; i++) { + if (hz <= bcm63xx_spi_freq_table[i][0]) { + clk_cfg = bcm63xx_spi_freq_table[i][1]; + break; + } + } + + /* No matching configuration found, default to lowest */ + if (i == SPI_CLK_MASK) + clk_cfg = SPI_CLK_0_391MHZ; + + /* clear existing clock configuration bits of the register */ + reg = bcm_spi_readb(bs, SPI_CLK_CFG); + reg &= ~SPI_CLK_MASK; + reg |= clk_cfg; + + bcm_spi_writeb(bs, reg, SPI_CLK_CFG); + dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", + clk_cfg, hz); + + return 0; +} + +/* the spi->mode bits understood by this driver: */ +#define MODEBITS (SPI_CPOL | SPI_CPHA) + +static int bcm63xx_spi_setup(struct spi_device *spi) +{ + struct bcm63xx_spi *bs; + int ret; + + bs = spi_master_get_devdata(spi->master); + + if (bs->stopping) + return -ESHUTDOWN; + + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + if (spi->mode & ~MODEBITS) { + dev_err(&spi->dev, "%s, unsupported mode bits %x\n", + __func__, spi->mode & ~MODEBITS); + return -EINVAL; + } + + ret = bcm63xx_spi_setup_transfer(spi, NULL); + if (ret < 0) { + dev_err(&spi->dev, "setup: unsupported mode bits %x\n", + spi->mode & ~MODEBITS); + return ret; + } + + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0); + + return 0; +} + +/* Fill the TX FIFO with as many bytes as possible */ +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs) +{ + u8 size; + + /* Fill the Tx FIFO with as many bytes as possible */ + size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes : + bs->fifo_size; + memcpy_toio(bs->tx_io, bs->tx_ptr, size); + bs->remaining_bytes -= size; +} + +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) +{ + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); + u16 msg_ctl; + u16 cmd; + + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", + t->tx_buf, t->rx_buf, t->len); + + /* Transmitter is inhibited */ + bs->tx_ptr = t->tx_buf; + bs->rx_ptr = t->rx_buf; + init_completion(&bs->done); + + if (t->tx_buf) { + bs->remaining_bytes = t->len; + bcm63xx_spi_fill_tx_fifo(bs); + } + + /* Enable the command done interrupt which + * we use to determine completion of a command */ + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); + + /* Fill in the Message control register */ + msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); + + if (t->rx_buf && t->tx_buf) + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT); + else if (t->rx_buf) + msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT); + else if (t->tx_buf) + msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT); + + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); + + /* Issue the transfer */ + cmd = SPI_CMD_START_IMMEDIATE; + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); + cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); + bcm_spi_writew(bs, cmd, SPI_CMD); + wait_for_completion(&bs->done); + + /* Disable the CMD_DONE interrupt */ + bcm_spi_writeb(bs, 0, SPI_INT_MASK); + + return t->len - bs->remaining_bytes; +} + +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m) +{ + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); + struct spi_transfer *t; + int ret = 0; + + if (unlikely(list_empty(&m->transfers))) + return -EINVAL; + + if (bs->stopping) + return -ESHUTDOWN; + + list_for_each_entry(t, &m->transfers, transfer_list) { + ret += bcm63xx_txrx_bufs(spi, t); + } + + m->complete(m->context); + + return ret; +} + +/* This driver supports single master mode only. Hence + * CMD_DONE is the only interrupt we care about + */ +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) +{ + struct spi_master *master = (struct spi_master *)dev_id; + struct bcm63xx_spi *bs = spi_master_get_devdata(master); + u8 intr; + u16 cmd; + + /* Read interupts and clear them immediately */ + intr = bcm_spi_readb(bs, SPI_INT_STATUS); + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); + bcm_spi_writeb(bs, 0, SPI_INT_MASK); + + /* A tansfer completed */ + if (intr & SPI_INTR_CMD_DONE) { + u8 rx_tail; + + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); + + /* Read out all the data */ + if (rx_tail) + memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail); + + /* See if there is more data to send */ + if (bs->remaining_bytes > 0) { + bcm63xx_spi_fill_tx_fifo(bs); + + /* Start the transfer */ + bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT, + SPI_MSG_CTL); + cmd = bcm_spi_readw(bs, SPI_CMD); + cmd |= SPI_CMD_START_IMMEDIATE; + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); + bcm_spi_writew(bs, cmd, SPI_CMD); + } else { + complete(&bs->done); + } + } + + return IRQ_HANDLED; +} + + +static int __devinit bcm63xx_spi_probe(struct platform_device *pdev) +{ + struct resource *r; + struct device *dev = &pdev->dev; + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data; + int irq; + struct spi_master *master; + struct clk *clk; + struct bcm63xx_spi *bs; + int ret; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(dev, "no iomem\n"); + ret = -ENXIO; + goto out; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "no irq\n"); + ret = -ENXIO; + goto out; + } + + clk = clk_get(dev, "spi"); + if (IS_ERR(clk)) { + dev_err(dev, "no clock for device\n"); + ret = PTR_ERR(clk); + goto out; + } + + master = spi_alloc_master(dev, sizeof(*bs)); + if (!master) { + dev_err(dev, "out of memory\n"); + ret = -ENOMEM; + goto out_clk; + } + + bs = spi_master_get_devdata(master); + init_completion(&bs->done); + + platform_set_drvdata(pdev, master); + bs->pdev = pdev; + + if (!devm_request_mem_region(&pdev->dev, r->start, + resource_size(r), PFX)) { + dev_err(dev, "iomem request failed\n"); + ret = -ENXIO; + goto out_err; + } + + bs->regs = devm_ioremap_nocache(&pdev->dev, r->start, + resource_size(r)); + if (!bs->regs) { + dev_err(dev, "unable to ioremap regs\n"); + ret = -ENOMEM; + goto out_err; + } + + bs->irq = irq; + bs->clk = clk; + bs->fifo_size = pdata->fifo_size; + + ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, + pdev->name, master); + if (ret) { + dev_err(dev, "unable to request irq\n"); + goto out_err; + } + + master->bus_num = pdata->bus_num; + master->num_chipselect = pdata->num_chipselect; + master->setup = bcm63xx_spi_setup; + master->transfer = bcm63xx_transfer; + bs->speed_hz = pdata->speed_hz; + bs->stopping = 0; + bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); + bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); + spin_lock_init(&bs->lock); + + /* Initialize hardware */ + clk_enable(bs->clk); + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); + + /* register and we are done */ + ret = spi_register_master(master); + if (ret) { + dev_err(dev, "spi register failed\n"); + goto out_clk_disable; + } + + dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n", + r->start, irq, bs->fifo_size, DRV_VER); + + return 0; + +out_clk_disable: + clk_disable(clk); +out_err: + platform_set_drvdata(pdev, NULL); + spi_master_put(master); +out_clk: + clk_put(clk); +out: + return ret; +} + +static int __devexit bcm63xx_spi_remove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct bcm63xx_spi *bs = spi_master_get_devdata(master); + + /* reset spi block */ + bcm_spi_writeb(bs, 0, SPI_INT_MASK); + spin_lock(&bs->lock); + bs->stopping = 1; + + /* HW shutdown */ + clk_disable(bs->clk); + clk_put(bs->clk); + + spin_unlock(&bs->lock); + platform_set_drvdata(pdev, 0); + spi_unregister_master(master); + + return 0; +} + +#ifdef CONFIG_PM +static int bcm63xx_spi_suspend(struct device *dev) +{ + struct spi_master *master = + platform_get_drvdata(to_platform_device(dev)); + struct bcm63xx_spi *bs = spi_master_get_devdata(master); + + clk_disable(bs->clk); + + return 0; +} + +static int bcm63xx_spi_resume(struct device *dev) +{ + struct spi_master *master = + platform_get_drvdata(to_platform_device(dev)); + struct bcm63xx_spi *bs = spi_master_get_devdata(master); + + clk_enable(bs->clk); + + return 0; +} + +static const struct dev_pm_ops bcm63xx_spi_pm_ops = { + .suspend = bcm63xx_spi_suspend, + .resume = bcm63xx_spi_resume, +}; + +#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) +#else +#define BCM63XX_SPI_PM_OPS NULL +#endif + +static struct platform_driver bcm63xx_spi_driver = { + .driver = { + .name = "bcm63xx-spi", + .owner = THIS_MODULE, + .pm = BCM63XX_SPI_PM_OPS, + }, + .probe = bcm63xx_spi_probe, + .remove = __devexit_p(bcm63xx_spi_remove), +}; + +module_platform_driver(bcm63xx_spi_driver); + +MODULE_ALIAS("platform:bcm63xx_spi"); +MODULE_AUTHOR("Florian Fainelli "); +MODULE_AUTHOR("Tanguy Bouzeloc "); +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); +MODULE_LICENSE("GPL"); -- 1.7.5.4 From mbizon@freebox.fr Wed Feb 1 12:22:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Feb 2012 12:22:27 +0100 (CET) Received: from smtp4-g21.free.fr ([212.27.42.4]:45730 "EHLO smtp4-g21.free.fr" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2BALWR (ORCPT ); Wed, 1 Feb 2012 12:22:17 +0100 Received: from [192.168.108.17] (unknown [213.36.7.13]) by smtp4-g21.free.fr (Postfix) with ESMTP id CA5194C8379; Wed, 1 Feb 2012 12:22:10 +0100 (CET) Subject: Re: [PATCH v4] spi: add Broadcom BCM63xx SPI controller driver From: Maxime Bizon Reply-To: mbizon@freebox.fr To: Florian Fainelli Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, spi-devel-general@lists.sourceforge.net, Tanguy Bouzeloc In-Reply-To: <1328091249-10389-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-10-git-send-email-florian@openwrt.org> <1328091249-10389-1-git-send-email-florian@openwrt.org> Content-Type: text/plain; charset="ANSI_X3.4-1968" Organization: Freebox Date: Wed, 01 Feb 2012 12:22:09 +0100 Message-ID: <1328095329.4936.21.camel@sakura.staff.proxad.net> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 Content-Transfer-Encoding: 7bit X-archive-position: 32382 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1141 Lines: 45 On Wed, 2012-02-01 at 11:14 +0100, Florian Fainelli wrote: Hi Florian, > +struct bcm63xx_spi { > + spinlock_t lock; this lock is never actually used it is referenced only once in device removal path > + int stopping; this can be removed by changing device removal path to first call spi_unregister_master. that way the spi stack cannot call spi_transfer anymore and we don't need to abort these calls. > +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) > +{ > [...] > + bcm_spi_writew(bs, cmd, SPI_CMD); > + wait_for_completion(&bs->done); > + bcm63xx_txrx_bufs() is called by bcm63xx_transfer(), and according to Documentation/spi/spi-summary: master->transfer(struct spi_device *spi, struct spi_message *message) This must not sleep. Its responsibility is arrange that the transfer happens and its complete() callback is issued. The two will normally happen later, after other transfers complete, and if the controller is idle it will need to be kickstarted. So we cannot do a synchronous wait here, this must be pushed to a workqueue or kthread. -- Maxime From jayachandranc@netlogicmicro.com Thu Feb 2 15:38:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:39:03 +0100 (CET) Received: from smtpgw1.netlogicmicro.com ([12.203.210.53]:46713 "EHLO smtpgw1.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904104Ab2BBOi4 (ORCPT ); Thu, 2 Feb 2012 15:38:56 +0100 Received: from pps.filterd (smtpgw1 [127.0.0.1]) by smtpgw1.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12EaoPp002226; Thu, 2 Feb 2012 06:38:49 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw1.netlogicmicro.com with ESMTP id 12hfu7nyfc-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:38:49 -0800 From: Jayachandran C To: , CC: Jayachandran C Subject: [PATCH 00/11] Netlogic XLR/XLP fixes and updates. Date: Thu, 2 Feb 2012 20:12:54 +0530 Message-ID: X-Mailer: git-send-email 1.7.5.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32383 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3203 Lines: 71 Here are the updates to Netlogic code for the next kernel. The changes include fixes to the current code and new features. * Fixes for the current code XLR PCI irq fix, XLP TLB size fix, XLP smp boot sequence fixup, remove unused code in XLR PCI. * New features XLR platform USB code, XLR platform NAND/NOR flash support, XLR oprofile driver, XLP initial PCI support and XLP USB support. Let me know if there are any comments or concerns. Thanks, JC. Ganesan Ramalingam (3): MIPS: Netlogic: Platform NAND/NOR flash support MIPS: Netlogic: XLP PCIe controller support. MIPS: Netlogic: USB support for XLP Jayachandran C (7): MIPS: Netlogic: Fix PCIX irq on XLR chips MIPS: Netlogic: platform changes for XLS USB. MIPS: Netlogic: Remove unused pcibios_fixups MIPS: Netlogic: Update comments in smpboot.S MIPS: Netlogic: SMP wakeup code update MIPS: Netlogic: Fix TLB size of boot CPU. MIPS: Netlogic: Remove NETLOGIC_ prefix Madhusudan Bhat (1): MIPS: Netlogic: Oprofile driver for XLR/XLS arch/mips/Kconfig | 3 +- .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 4 +- arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 5 +- arch/mips/include/asm/netlogic/xlp-hal/pcibus.h | 76 ++++++ arch/mips/include/asm/netlogic/xlp-hal/pic.h | 4 + arch/mips/include/asm/netlogic/xlp-hal/usb.h | 64 +++++ arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 14 +- arch/mips/include/asm/netlogic/xlr/bridge.h | 104 ++++++++ arch/mips/include/asm/netlogic/xlr/flash.h | 55 +++++ arch/mips/include/asm/netlogic/xlr/gpio.h | 59 +++--- arch/mips/netlogic/common/smpboot.S | 159 ++++++++----- arch/mips/netlogic/xlp/Makefile | 1 + arch/mips/netlogic/xlp/nlm_hal.c | 40 ++++ arch/mips/netlogic/xlp/platform.c | 2 +- arch/mips/netlogic/xlp/setup.c | 8 +- arch/mips/netlogic/xlp/usb-init.c | 125 ++++++++++ arch/mips/netlogic/xlr/Makefile | 2 +- arch/mips/netlogic/xlr/platform-flash.c | 220 +++++++++++++++++ arch/mips/netlogic/xlr/platform.c | 89 +++++++ arch/mips/netlogic/xlr/setup.c | 2 +- arch/mips/oprofile/Makefile | 1 + arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 29 +++ arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-xlp.c | 247 ++++++++++++++++++++ arch/mips/pci/pci-xlr.c | 6 +- 26 files changed, 1222 insertions(+), 99 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/usb.h create mode 100644 arch/mips/include/asm/netlogic/xlr/bridge.h create mode 100644 arch/mips/include/asm/netlogic/xlr/flash.h create mode 100644 arch/mips/netlogic/xlp/usb-init.c create mode 100644 arch/mips/netlogic/xlr/platform-flash.c create mode 100644 arch/mips/pci/pci-xlp.c -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:39:28 +0100 (CET) Received: from smtpgw2.netlogicmicro.com ([12.203.210.54]:52718 "EHLO smtpgw2.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904106Ab2BBOjH (ORCPT ); Thu, 2 Feb 2012 15:39:07 +0100 Received: from pps.filterd (smtpgw2 [127.0.0.1]) by smtpgw2.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12Ed04u028767; Thu, 2 Feb 2012 06:39:00 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw2.netlogicmicro.com with ESMTP id 11pcrwt2a6-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:00 -0800 From: Jayachandran C To: , CC: Jayachandran C Subject: [PATCH 01/11] MIPS: Netlogic: Fix PCIX irq on XLR chips Date: Thu, 2 Feb 2012 20:12:55 +0530 Message-ID: <451f6dd7ce79b388d0f1d2266be8afe90daef99a.1328189941.git.jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32384 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 592 Lines: 23 The correct irq is PIC_PCIX_IRQ Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlr.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 3d701a9..0148001 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -327,7 +327,7 @@ static int __init pcibios_init(void) } } else { /* XLR PCI controller ACK */ - irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack); + irq_set_handler_data(PIC_PCIX_IRQ, xlr_pci_ack); } return 0; -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:39:55 +0100 (CET) Received: from smtpgw1.netlogicmicro.com ([12.203.210.53]:46747 "EHLO smtpgw1.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904108Ab2BBOjN (ORCPT ); Thu, 2 Feb 2012 15:39:13 +0100 Received: from pps.filterd (smtpgw1 [127.0.0.1]) by smtpgw1.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12EaoPq002226; Thu, 2 Feb 2012 06:39:07 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw1.netlogicmicro.com with ESMTP id 12hfu7nyfh-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:07 -0800 From: Jayachandran C To: , CC: Jayachandran C Subject: [PATCH 02/11] MIPS: Netlogic: platform changes for XLS USB. Date: Thu, 2 Feb 2012 20:12:56 +0530 Message-ID: <0d464a65285476cd74024a5fae81f8f302df1bb0.1328189941.git.jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32385 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3673 Lines: 123 Add USB initialization code, setup resources and add USB platform driver in mips/netlogic/xlr/platform.c. Add USB support for XLR/XLS platform in Kconfig. Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 2 + arch/mips/netlogic/xlr/platform.c | 89 +++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c4c1312..baabbe5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -780,6 +780,8 @@ config NLM_XLR_BOARD select ZONE_DMA if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK + select USB_ARCH_HAS_OHCI if USB_SUPPORT + select USB_ARCH_HAS_EHCI if USB_SUPPORT help Support for systems based on Netlogic XLR and XLS processors. Say Y here if you have a XLR or XLS based board. diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c index eab64b4..cb0ab63 100644 --- a/arch/mips/netlogic/xlr/platform.c +++ b/arch/mips/netlogic/xlr/platform.c @@ -97,3 +97,92 @@ static int __init nlm_uart_init(void) } arch_initcall(nlm_uart_init); + +#ifdef CONFIG_USB +/* Platform USB devices, only on XLS chips */ +static u64 xls_usb_dmamask = ~(u32)0; +#define USB_PLATFORM_DEV(n, i, irq) \ + { \ + .name = n, \ + .id = i, \ + .num_resources = 2, \ + .dev = { \ + .dma_mask = &xls_usb_dmamask, \ + .coherent_dma_mask = 0xffffffff, \ + }, \ + .resource = (struct resource[]) { \ + { \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }, \ + } + +static struct platform_device xls_usb_ehci_device = + USB_PLATFORM_DEV("ehci-xls", 0, PIC_USB_IRQ); +static struct platform_device xls_usb_ohci_device_0 = + USB_PLATFORM_DEV("ohci-xls-0", 1, PIC_USB_IRQ); +static struct platform_device xls_usb_ohci_device_1 = + USB_PLATFORM_DEV("ohci-xls-1", 2, PIC_USB_IRQ); + +static struct platform_device *xls_platform_devices[] = { + &xls_usb_ehci_device, + &xls_usb_ohci_device_0, + &xls_usb_ohci_device_1, +}; + +int xls_platform_usb_init(void) +{ + uint64_t usb_mmio, gpio_mmio; + unsigned long memres; + uint32_t val; + + if (!nlm_chip_is_xls()) + return 0; + + gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); + usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_1_OFFSET); + + /* Clear Rogue Phy INTs */ + nlm_write_reg(usb_mmio, 49, 0x10000000); + /* Enable all interrupts */ + nlm_write_reg(usb_mmio, 50, 0x1f000000); + + /* Enable ports */ + nlm_write_reg(usb_mmio, 1, 0x07000500); + + val = nlm_read_reg(gpio_mmio, 21); + if (((val >> 22) & 0x01) == 0) { + pr_info("Detected USB Device mode - Not supported!\n"); + nlm_write_reg(usb_mmio, 0, 0x01000000); + return 0; + } + + pr_info("Detected USB Host mode - Adding XLS USB devices.\n"); + /* Clear reset, host mode */ + nlm_write_reg(usb_mmio, 0, 0x02000000); + + /* Memory resource for various XLS usb ports */ + usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET); + memres = CPHYSADDR((unsigned long)usb_mmio); + xls_usb_ehci_device.resource[0].start = memres; + xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1; + + memres += 0x400; + xls_usb_ohci_device_0.resource[0].start = memres; + xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1; + + memres += 0x400; + xls_usb_ohci_device_1.resource[0].start = memres; + xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1; + + return platform_add_devices(xls_platform_devices, + ARRAY_SIZE(xls_platform_devices)); +} + +arch_initcall(xls_platform_usb_init); +#endif -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:40:20 +0100 (CET) Received: from smtpgw2.netlogicmicro.com ([12.203.210.54]:52723 "EHLO smtpgw2.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904109Ab2BBOjP (ORCPT ); Thu, 2 Feb 2012 15:39:15 +0100 Received: from pps.filterd (smtpgw2 [127.0.0.1]) by smtpgw2.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12Ed9ZI029370; Thu, 2 Feb 2012 06:39:09 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw2.netlogicmicro.com with ESMTP id 11pcrwt2a7-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:09 -0800 From: Jayachandran C To: , CC: Jayachandran C Subject: [PATCH 03/11] MIPS: Netlogic: Remove unused pcibios_fixups Date: Thu, 2 Feb 2012 20:12:57 +0530 Message-ID: <0cf4db092acfd521440f8d75dfffbe143060a5f6.1328189941.git.jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32386 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 539 Lines: 23 This global is unneeded, and seems to be carried over from ancient code. Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlr.c | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 0148001..7dc1de2 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -334,7 +334,3 @@ static int __init pcibios_init(void) } arch_initcall(pcibios_init); - -struct pci_fixup pcibios_fixups[] = { - {0} -}; -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:40:46 +0100 (CET) Received: from smtpgw1.netlogicmicro.com ([12.203.210.53]:46752 "EHLO smtpgw1.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904107Ab2BBOjS (ORCPT ); Thu, 2 Feb 2012 15:39:18 +0100 Received: from pps.filterd (smtpgw1 [127.0.0.1]) by smtpgw1.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12EWTJ2028910; Thu, 2 Feb 2012 06:39:11 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw1.netlogicmicro.com with ESMTP id 12hfu7nyfm-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:11 -0800 From: Jayachandran C To: , CC: Jayachandran C Subject: [PATCH 04/11] MIPS: Netlogic: Update comments in smpboot.S Date: Thu, 2 Feb 2012 20:12:58 +0530 Message-ID: X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32387 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6680 Lines: 225 No change in logic, comments update and whitespace cleanup. * A few comments in the file were in assembler style and the rest int C style, convert all of them to C style. * Mark workarounds for Ax silicon with a macro XLP_AX_WORKAROUND * Whitespace fixes - use tabs consistently * rename __config_lsu macro to xlp_config_lsu Signed-off-by: Jayachandran C --- arch/mips/netlogic/common/smpboot.S | 112 +++++++++++++++++++---------------- 1 files changed, 61 insertions(+), 51 deletions(-) diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index c138b1a..bfe9060 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -54,28 +54,36 @@ XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ SYS_CPU_NONCOHERENT_MODE * 4 -.macro __config_lsu - li t0, LSU_DEFEATURE - mfcr t1, t0 +#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */ - lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */ - or t1, t1, t2 - li t2, ~0xe /* S1RCM */ +/* Enable XLP features and workarounds in the LSU */ +.macro xlp_config_lsu + li t0, LSU_DEFEATURE + mfcr t1, t0 + + lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */ + or t1, t1, t2 +#ifdef XLP_AX_WORKAROUND + li t2, ~0xe /* S1RCM */ and t1, t1, t2 +#endif mtcr t1, t0 - li t0, SCHED_DEFEATURE - lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */ - mtcr t1, t0 +#ifdef XLP_AX_WORKAROUND + li t0, SCHED_DEFEATURE + lui t1, 0x0100 /* Disable BRU accepting ALU ops */ + mtcr t1, t0 +#endif .endm /* - * The cores can come start when they are woken up. This is also the NMI - * entry, so check that first. + * This is the code that will be copied to the reset entry point for + * XLR and XLP. The XLP cores start here when they are woken up. This + * is also the NMI entry point. * - * The data corresponding to reset is stored at RESET_DATA_PHYS location, - * this will have the thread mask (used when core is woken up) and the - * current NMI handler in case we reached here for an NMI. + * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS + * location, this will have the thread mask (used when core is woken up) + * and the current NMI handler in case we reached here for an NMI. * * When a core or thread is newly woken up, it loops in a 'wait'. When * the CPU really needs waking up, we send an NMI to it, with the NMI @@ -89,12 +97,12 @@ FEXPORT(nlm_reset_entry) dmtc0 k0, $22, 6 dmtc0 k1, $22, 7 - mfc0 k0, CP0_STATUS - li k1, 0x80000 - and k1, k0, k1 - beqz k1, 1f /* go to real reset entry */ + mfc0 k0, CP0_STATUS + li k1, 0x80000 + and k1, k0, k1 + beqz k1, 1f /* go to real reset entry */ nop - li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ + li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ ld k0, BOOT_NMI_HANDLER(k1) jr k0 nop @@ -114,21 +122,23 @@ FEXPORT(nlm_reset_entry) li t2, SYS_CPU_COHERENT_BASE(0) add t2, t2, t3 /* t2 <- SYS offset for node */ lw t1, 0(t2) - and t1, t1, t0 - sw t1, 0(t2) + and t1, t1, t0 + sw t1, 0(t2) /* read back to ensure complete */ - lw t1, 0(t2) + lw t1, 0(t2) sync /* Configure LSU on Non-0 Cores. */ - __config_lsu + xlp_config_lsu + /* FALL THROUGH */ /* * Wake up sibling threads from the initial thread in * a core. */ EXPORT(nlm_boot_siblings) + /* Enable hw threads by writing to MAP_THREADMODE of the core */ li t0, CKSEG1ADDR(RESET_DATA_PHYS) lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) @@ -139,24 +149,24 @@ EXPORT(nlm_boot_siblings) /* * The new hardware thread starts at the next instruction * For all the cases other than core 0 thread 0, we will - * jump to the secondary wait function. - */ + * jump to the secondary wait function. + */ mfc0 v0, CP0_EBASE, 1 andi v0, 0x7f /* v0 <- node/core */ -#if 1 - /* A0 errata - Write MMU_SETUP after changing thread mode register. */ + /* Init MMU in the first thread after changing THREAD_MODE + * register (Ax Errata?) + */ andi v1, v0, 0x3 /* v1 <- thread id */ bnez v1, 2f nop - li t0, MMU_SETUP - li t1, 0 - mtcr t1, t0 + li t0, MMU_SETUP + li t1, 0 + mtcr t1, t0 ehb -#endif -2: beqz v0, 4f +2: beqz v0, 4f /* boot cpu (cpuid == 0)? */ nop /* setup status reg */ @@ -183,9 +193,9 @@ EXPORT(nlm_boot_siblings) * For the boot CPU, we have to restore registers and * return */ -4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ +4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ li t1, 0xfadebeef - dmtc0 t1, $4, 2 /* restore SP from UserLocal */ + dmtc0 t1, $4, 2 /* restore SP from UserLocal */ PTR_SUBU sp, t0, PT_SIZE RESTORE_ALL jr ra @@ -193,7 +203,7 @@ EXPORT(nlm_boot_siblings) EXPORT(nlm_reset_entry_end) FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ - __config_lsu + xlp_config_lsu dmtc0 sp, $4, 2 /* SP saved in UserLocal */ SAVE_ALL sync @@ -234,36 +244,36 @@ END(nlm_boot_secondary_cpus) */ __CPUINIT NESTED(nlm_rmiboot_preboot, 16, sp) - mfc0 t0, $15, 1 # read ebase - andi t0, 0x1f # t0 has the processor_id() - andi t2, t0, 0x3 # thread no - sll t0, 2 # offset in cpu array + mfc0 t0, $15, 1 /* read ebase */ + andi t0, 0x1f /* t0 has the processor_id() */ + andi t2, t0, 0x3 /* thread num */ + sll t0, 2 /* offset in cpu array */ - PTR_LA t1, nlm_cpu_ready # mark CPU ready + PTR_LA t1, nlm_cpu_ready /* mark CPU ready */ PTR_ADDU t1, t0 li t3, 1 sw t3, 0(t1) - bnez t2, 1f # skip thread programming - nop # for non zero hw threads + bnez t2, 1f /* skip thread programming */ + nop /* for thread id != 0 */ /* - * MMU setup only for first thread in core + * XLR MMU setup only for first thread in core */ li t0, 0x400 mfcr t1, t0 - li t2, 6 # XLR thread mode mask + li t2, 6 /* XLR thread mode mask */ nor t3, t2, zero - and t2, t1, t2 # t2 - current thread mode + and t2, t1, t2 /* t2 - current thread mode */ li v0, CKSEG1ADDR(RESET_DATA_PHYS) - lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode + lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */ sll v1, 1 - beq v1, t2, 1f # same as request value - nop # nothing to do */ + beq v1, t2, 1f /* same as request value */ + nop /* nothing to do */ - and t2, t1, t3 # mask out old thread mode - or t1, t2, v1 # put in new value - mtcr t1, t0 # update core control + and t2, t1, t3 /* mask out old thread mode */ + or t1, t2, v1 /* put in new value */ + mtcr t1, t0 /* update core control */ 1: wait j 1b -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:41:12 +0100 (CET) Received: from smtpgw2.netlogicmicro.com ([12.203.210.54]:52724 "EHLO smtpgw2.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904110Ab2BBOjU (ORCPT ); Thu, 2 Feb 2012 15:39:20 +0100 Received: from pps.filterd (smtpgw2 [127.0.0.1]) by smtpgw2.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12EcpTm028764; Thu, 2 Feb 2012 06:39:13 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw2.netlogicmicro.com with ESMTP id 11pcrwt2a8-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:13 -0800 From: Jayachandran C To: , CC: Jayachandran C Subject: [PATCH 05/11] MIPS: Netlogic: SMP wakeup code update Date: Thu, 2 Feb 2012 20:12:59 +0530 Message-ID: X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32388 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3108 Lines: 115 Update for core intialization code. Initialize status register after receiving NMI for CPU wakeup. Add the low level L1D flush code before enabling threads in core. Also convert the ehb to _ehb so that it works under more GCC versions. Signed-off-by: Jayachandran C --- .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 4 +- arch/mips/netlogic/common/smpboot.S | 47 +++++++++++++++++-- 2 files changed, 45 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h index bf7d41d..7b63a6b 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h @@ -47,7 +47,9 @@ #define CPU_BLOCKID_MAP 10 #define LSU_DEFEATURE 0x304 -#define LSU_CERRLOG_REGID 0x09 +#define LSU_DEBUG_ADDR 0x305 +#define LSU_DEBUG_DATA0 0x306 +#define LSU_CERRLOG_REGID 0x309 #define SCHED_DEFEATURE 0x700 /* Offsets of interest from the 'MAP' Block */ diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index bfe9060..aa86590 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -77,6 +77,38 @@ .endm /* + * Low level L1 d-cache flush for core, needs to be called before + * threads are enabled + */ +.macro xlp_flush_l1_dcache + li t0, LSU_DEBUG_DATA0 + li t1, LSU_DEBUG_ADDR + li t2, 0 /* index */ + li t3, 0x200 /* loop count, 512 sets */ +1: + sll v0, t2, 5 + mtcr zero, t0 + ori v1, v0, 0x3 /* way0 | write_enable | write_active */ + mtcr v1, t1 +2: + mfcr v1, t1 + andi v1, 0x1 /* wait for write_active == 0 */ + bnez v1, 2b + nop + mtcr zero, t0 + ori v1, v0, 0x7 /* way1 | write_enable | write_active */ + mtcr v1, t1 +3: + mfcr v1, t1 + andi v1, 0x1 /* wait for write_active == 0 */ + bnez v1, 3b + nop + addi t2, 1 + bne t3, t2, 1b + nop +.endm + +/* * This is the code that will be copied to the reset entry point for * XLR and XLP. The XLP cores start here when they are woken up. This * is also the NMI entry point. @@ -138,6 +170,8 @@ FEXPORT(nlm_reset_entry) * a core. */ EXPORT(nlm_boot_siblings) + /* core L1D flush before enable threads */ + xlp_flush_l1_dcache /* Enable hw threads by writing to MAP_THREADMODE of the core */ li t0, CKSEG1ADDR(RESET_DATA_PHYS) lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ @@ -164,16 +198,13 @@ EXPORT(nlm_boot_siblings) li t0, MMU_SETUP li t1, 0 mtcr t1, t0 - ehb + _ehb 2: beqz v0, 4f /* boot cpu (cpuid == 0)? */ nop /* setup status reg */ - mfc0 t1, CP0_STATUS - li t0, ST0_BEV - or t1, t0 - xor t1, t0 + move t1, zero #ifdef CONFIG_64BIT ori t1, ST0_KX #endif @@ -220,6 +251,12 @@ FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ __CPUINIT NESTED(nlm_boot_secondary_cpus, 16, sp) + /* Initialize CP0 Status */ + move t1, zero +#ifdef CONFIG_64BIT + ori t1, ST0_KX +#endif + mtc0 t1, CP0_STATUS PTR_LA t1, nlm_next_sp PTR_L sp, 0(t1) PTR_LA t1, nlm_next_gp -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:41:37 +0100 (CET) Received: from smtpgw1.netlogicmicro.com ([12.203.210.53]:46754 "EHLO smtpgw1.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904111Ab2BBOjW (ORCPT ); Thu, 2 Feb 2012 15:39:22 +0100 Received: from pps.filterd (smtpgw1 [127.0.0.1]) by smtpgw1.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12EM67V012889; Thu, 2 Feb 2012 06:39:16 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw1.netlogicmicro.com with ESMTP id 12hfu7nyfp-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:16 -0800 From: Jayachandran C To: , CC: Jayachandran C Subject: [PATCH 06/11] MIPS: Netlogic: Fix TLB size of boot CPU. Date: Thu, 2 Feb 2012 20:13:00 +0530 Message-ID: <8f6783d1c4c5cd731448bac40a547a1f2b5f8e45.1328189941.git.jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32389 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1398 Lines: 42 Starting other threads in the core will change the number of TLB entries of a CPU. Re-calculate current_cpu_data.tlbsize on the boot cpu after enabling and waking up other threads. The secondary CPUs do not need this logic because the threads are enabled on the secondary cores at wakeup and before cpu_probe. Signed-off-by: Jayachandran C --- arch/mips/netlogic/xlp/setup.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index acb677a..b3df7c2 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -82,8 +82,10 @@ void __init prom_free_prom_memory(void) void xlp_mmu_init(void) { + /* enable extended TLB and Large Fixed TLB */ write_c0_config6(read_c0_config6() | 0x24); - current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; + + /* set page mask of Fixed TLB in config7 */ write_c0_config7(PM_DEFAULT_MASK >> (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); } @@ -100,6 +102,10 @@ void __init prom_init(void) nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); #ifdef CONFIG_SMP nlm_wakeup_secondary_cpus(0xffffffff); + + /* update TLB size after waking up threads */ + current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; + register_smp_ops(&nlm_smp_ops); #endif } -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:41:59 +0100 (CET) Received: from smtpgw2.netlogicmicro.com ([12.203.210.54]:52726 "EHLO smtpgw2.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904104Ab2BBOjY (ORCPT ); Thu, 2 Feb 2012 15:39:24 +0100 Received: from pps.filterd (smtpgw2 [127.0.0.1]) by smtpgw2.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12EdIgK029399; Thu, 2 Feb 2012 06:39:18 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw2.netlogicmicro.com with ESMTP id 11pcrwt2a9-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:18 -0800 From: Jayachandran C To: , CC: Jayachandran C Subject: [PATCH 07/11] MIPS: Netlogic: Remove NETLOGIC_ prefix Date: Thu, 2 Feb 2012 20:13:01 +0530 Message-ID: <1b5af3a93c9e4ff3721b233c7c897825ff783d4b.1328189941.git.jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3575 Lines: 102 Remove NETLOGIC_ prefix from gpio register definitions, this will bring it in-line with the other Netlogic headers. Having NETLOGIC prefix here is misleading because these are XLR/XLS specific register definitions. Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlr/gpio.h | 59 +++++++++++++++-------------- arch/mips/netlogic/xlr/setup.c | 2 +- 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h index 51f6ad4..8492e83 100644 --- a/arch/mips/include/asm/netlogic/xlr/gpio.h +++ b/arch/mips/include/asm/netlogic/xlr/gpio.h @@ -35,39 +35,40 @@ #ifndef _ASM_NLM_GPIO_H #define _ASM_NLM_GPIO_H -#define NETLOGIC_GPIO_INT_EN_REG 0 -#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 -#define NETLOGIC_GPIO_IO_DIR_REG 2 -#define NETLOGIC_GPIO_IO_DATA_WR_REG 3 -#define NETLOGIC_GPIO_IO_DATA_RD_REG 4 +#define GPIO_INT_EN_REG 0 +#define GPIO_INPUT_INVERSION_REG 1 +#define GPIO_IO_DIR_REG 2 +#define GPIO_IO_DATA_WR_REG 3 +#define GPIO_IO_DATA_RD_REG 4 -#define NETLOGIC_GPIO_SWRESET_REG 8 -#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 -#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 -#define NETLOGIC_GPIO_DRAM1_RESET_REG 11 -#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 -#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 -#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 -#define NETLOGIC_GPIO_DRAM2_RESET_REG 15 -#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 +#define GPIO_SWRESET_REG 8 +#define GPIO_DRAM1_CNTRL_REG 9 +#define GPIO_DRAM1_RATIO_REG 10 +#define GPIO_DRAM1_RESET_REG 11 +#define GPIO_DRAM1_STATUS_REG 12 +#define GPIO_DRAM2_CNTRL_REG 13 +#define GPIO_DRAM2_RATIO_REG 14 +#define GPIO_DRAM2_RESET_REG 15 +#define GPIO_DRAM2_STATUS_REG 16 -#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 -#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 -#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 -#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 +#define GPIO_PWRON_RESET_CFG_REG 21 +#define GPIO_BIST_ALL_GO_STATUS_REG 24 +#define GPIO_BIST_CPU_GO_STATUS_REG 25 +#define GPIO_BIST_DEV_GO_STATUS_REG 26 -#define NETLOGIC_GPIO_FUSE_BANK_REG 35 -#define NETLOGIC_GPIO_CPU_RESET_REG 40 -#define NETLOGIC_GPIO_RNG_REG 43 +#define GPIO_FUSE_BANK_REG 35 +#define GPIO_CPU_RESET_REG 40 +#define GPIO_RNG_REG 43 -#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 -#define NETLOGIC_GPIO_LED_BITMAP 0x1700000 -#define NETLOGIC_GPIO_LED_0_SHIFT 20 -#define NETLOGIC_GPIO_LED_1_SHIFT 24 +#define PWRON_RESET_PCMCIA_BOOT 17 -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 +#define GPIO_LED_BITMAP 0x1700000 +#define GPIO_LED_0_SHIFT 20 +#define GPIO_LED_1_SHIFT 24 + +#define GPIO_LED_OUTPUT_CODE_RESET 0x01 +#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 +#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 +#define GPIO_LED_OUTPUT_CODE_MAIN 0x04 #endif diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index c9d066d..81b1d31 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -85,7 +85,7 @@ static void nlm_linux_exit(void) gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ - nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1); + nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1); for ( ; ; ) cpu_wait(); } -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:42:25 +0100 (CET) Received: from smtpgw1.netlogicmicro.com ([12.203.210.53]:46755 "EHLO smtpgw1.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904112Ab2BBOj0 (ORCPT ); Thu, 2 Feb 2012 15:39:26 +0100 Received: from pps.filterd (smtpgw1 [127.0.0.1]) by smtpgw1.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12EWTJ3028910; Thu, 2 Feb 2012 06:39:20 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw1.netlogicmicro.com with ESMTP id 12hfu7nyfs-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:20 -0800 From: Jayachandran C To: , CC: Ganesan Ramalingam , Jayachandran C Subject: [PATCH 08/11] MIPS: Netlogic: Platform NAND/NOR flash support Date: Thu, 2 Feb 2012 20:13:02 +0530 Message-ID: X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 13916 Lines: 425 From: Ganesan Ramalingam Changes to add support for the boot NOR flash on XLR boards and the boot NAND/NOR flash drivers on the XLS boards. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlr/bridge.h | 104 +++++++++++++ arch/mips/include/asm/netlogic/xlr/flash.h | 55 +++++++ arch/mips/netlogic/xlr/Makefile | 2 +- arch/mips/netlogic/xlr/platform-flash.c | 220 +++++++++++++++++++++++++++ 4 files changed, 380 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/xlr/bridge.h create mode 100644 arch/mips/include/asm/netlogic/xlr/flash.h create mode 100644 arch/mips/netlogic/xlr/platform-flash.c diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h new file mode 100644 index 0000000..f34727d --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/bridge.h @@ -0,0 +1,104 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _ASM_NLM_BRIDGE_H_ +#define _ASM_NLM_BRIDGE_H_ + +#define BRIDGE_DRAM_0_BAR 0 +#define BRIDGE_DRAM_1_BAR 1 +#define BRIDGE_DRAM_2_BAR 2 +#define BRIDGE_DRAM_3_BAR 3 +#define BRIDGE_DRAM_4_BAR 4 +#define BRIDGE_DRAM_5_BAR 5 +#define BRIDGE_DRAM_6_BAR 6 +#define BRIDGE_DRAM_7_BAR 7 +#define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8 +#define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9 +#define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10 +#define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11 +#define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12 +#define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13 +#define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14 +#define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15 +#define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16 +#define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17 +#define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18 +#define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19 +#define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20 +#define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21 +#define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22 +#define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23 +#define BRIDGE_CFG_BAR 24 +#define BRIDGE_PHNX_IO_BAR 25 +#define BRIDGE_FLASH_BAR 26 +#define BRIDGE_SRAM_BAR 27 +#define BRIDGE_HTMEM_BAR 28 +#define BRIDGE_HTINT_BAR 29 +#define BRIDGE_HTPIC_BAR 30 +#define BRIDGE_HTSM_BAR 31 +#define BRIDGE_HTIO_BAR 32 +#define BRIDGE_HTCFG_BAR 33 +#define BRIDGE_PCIXCFG_BAR 34 +#define BRIDGE_PCIXMEM_BAR 35 +#define BRIDGE_PCIXIO_BAR 36 +#define BRIDGE_DEVICE_MASK 37 +#define BRIDGE_AERR_INTR_LOG1 38 +#define BRIDGE_AERR_INTR_LOG2 39 +#define BRIDGE_AERR_INTR_LOG3 40 +#define BRIDGE_AERR_DEV_STAT 41 +#define BRIDGE_AERR1_LOG1 42 +#define BRIDGE_AERR1_LOG2 43 +#define BRIDGE_AERR1_LOG3 44 +#define BRIDGE_AERR1_DEV_STAT 45 +#define BRIDGE_AERR_INTR_EN 46 +#define BRIDGE_AERR_UPG 47 +#define BRIDGE_AERR_CLEAR 48 +#define BRIDGE_AERR1_CLEAR 49 +#define BRIDGE_SBE_COUNTS 50 +#define BRIDGE_DBE_COUNTS 51 +#define BRIDGE_BITERR_INT_EN 52 + +#define BRIDGE_SYS2IO_CREDITS 53 +#define BRIDGE_EVNT_CNT_CTRL1 54 +#define BRIDGE_EVNT_COUNTER1 55 +#define BRIDGE_EVNT_CNT_CTRL2 56 +#define BRIDGE_EVNT_COUNTER2 57 +#define BRIDGE_RESERVED1 58 + +#define BRIDGE_DEFEATURE 59 +#define BRIDGE_SCRATCH0 60 +#define BRIDGE_SCRATCH1 61 +#define BRIDGE_SCRATCH2 62 +#define BRIDGE_SCRATCH3 63 + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h new file mode 100644 index 0000000..63c6208 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/flash.h @@ -0,0 +1,55 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _ASM_NLM_FLASH_H_ +#define _ASM_NLM_FLASH_H_ + +#define FLASH_CSBASE_ADDR(cs) (cs) +#define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) +#define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) +#define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) +#define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) + +#define FLASH_INT_MASK 0x50 +#define FLASH_INT_STATUS 0x60 +#define FLASH_ERROR_STATUS 0x70 +#define FLASH_ERROR_ADDR 0x80 + +#define FLASH_NAND_CLE(cs) (0x90 + (cs)) +#define FLASH_NAND_ALE(cs) (0xa0 + (cs)) + +#define FLASH_NAND_CSDEV_PARAM 0x000041e6 +#define FLASH_NAND_CSTIME_PARAMA 0x4f400e22 +#define FLASH_NAND_CSTIME_PARAMB 0x000083cf + +#endif diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile index f01e4d7..c287dea 100644 --- a/arch/mips/netlogic/xlr/Makefile +++ b/arch/mips/netlogic/xlr/Makefile @@ -1,2 +1,2 @@ -obj-y += setup.o platform.o +obj-y += setup.o platform.o platform-flash.o obj-$(CONFIG_SMP) += wakeup.o diff --git a/arch/mips/netlogic/xlr/platform-flash.c b/arch/mips/netlogic/xlr/platform-flash.c new file mode 100644 index 0000000..087e12f --- /dev/null +++ b/arch/mips/netlogic/xlr/platform-flash.c @@ -0,0 +1,220 @@ +/* + * Copyright 2011, Netlogic Microsystems. + * Copyright 2004, Matt Porter + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* + * Default NOR partition layout + */ +static struct mtd_partition xlr_nor_parts[] = { + { + .name = "User FS", + .offset = 0x800000, + .size = MTDPART_SIZ_FULL, + } +}; + +/* + * Default NAND partition layout + */ +static struct mtd_partition xlr_nand_parts[] = { + { + .name = "Root Filesystem", + .offset = 64 * 64 * 2048, + .size = 432 * 64 * 2048, + }, + { + .name = "Home Filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +/* Use PHYSMAP flash for NOR */ +struct physmap_flash_data xlr_nor_data = { + .width = 2, + .parts = xlr_nor_parts, + .nr_parts = ARRAY_SIZE(xlr_nor_parts), +}; + +static struct resource xlr_nor_res[] = { + { + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device xlr_nor_dev = { + .name = "physmap-flash", + .dev = { + .platform_data = &xlr_nor_data, + }, + .num_resources = ARRAY_SIZE(xlr_nor_res), + .resource = xlr_nor_res, +}; + +const char *xlr_part_probes[] = { "cmdlinepart", NULL }; + +/* + * Use "gen_nand" driver for NAND flash + * + * There seems to be no way to store a private pointer containing + * platform specific info in gen_nand drivier. We will use a global + * struct for now, since we currently have only one NAND chip per board. + */ +struct xlr_nand_flash_priv { + int cs; + uint64_t flash_mmio; +}; + +static struct xlr_nand_flash_priv nand_priv; + +static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CLE) + nlm_write_reg(nand_priv.flash_mmio, + FLASH_NAND_CLE(nand_priv.cs), cmd); + else if (ctrl & NAND_ALE) + nlm_write_reg(nand_priv.flash_mmio, + FLASH_NAND_ALE(nand_priv.cs), cmd); +} + +struct platform_nand_data xlr_nand_data = { + .chip = { + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(xlr_nand_parts), + .chip_delay = 5, + .partitions = xlr_nand_parts, + .part_probe_types = xlr_part_probes, + }, + .ctrl = { + .cmd_ctrl = xlr_nand_ctrl, + }, +}; + +static struct resource xlr_nand_res[] = { + { + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device xlr_nand_dev = { + .name = "gen_nand", + .id = -1, + .num_resources = ARRAY_SIZE(xlr_nand_res), + .resource = xlr_nand_res, + .dev = { + .platform_data = &xlr_nand_data, + } +}; + +/* + * XLR/XLS supports upto 8 devices on its FLASH interface. The value in + * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the + * flash devices. + * Under this, each flash device has an offset and size given by the + * CSBASE_ADDR and CSBASE_MASK registers for the device. + * + * The CSBASE_ registers are expected to be setup by the bootloader. + */ +static void setup_flash_resource(uint64_t flash_mmio, + uint64_t flash_map_base, int cs, struct resource *res) +{ + u32 base, mask; + + base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); + mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); + + res->start = flash_map_base + ((unsigned long)base << 16); + res->end = res->start + (mask + 1) * 64 * 1024; +} + +static int __init xlr_flash_init(void) +{ + uint64_t gpio_mmio, flash_mmio, flash_map_base; + u32 gpio_resetcfg, flash_bar; + int cs, boot_nand, boot_nor; + + /* Flash address bits 39:24 is in bridge flash BAR */ + flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR); + flash_map_base = (flash_bar & 0xffff0000) << 8; + + gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); + flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET); + + /* Get the chip reset config */ + gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG); + + /* Check for boot flash type */ + boot_nor = boot_nand = 0; + if (nlm_chip_is_xls()) { + /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */ + if (gpio_resetcfg & (1 << 16)) + boot_nand = 1; + + /* check boot from PCMCIA, (GPIO reset reg bit 15 */ + if ((gpio_resetcfg & (1 << 15)) == 0) + boot_nor = 1; /* not set, booted from NOR */ + } else { /* XLR */ + /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */ + if ((gpio_resetcfg & (1 << 16)) == 0) + boot_nor = 1; /* not set, booted from NOR */ + } + + /* boot flash at chip select 0 */ + cs = 0; + + if (boot_nand) { + nand_priv.cs = cs; + nand_priv.flash_mmio = flash_mmio; + setup_flash_resource(flash_mmio, flash_map_base, cs, + xlr_nand_res); + + /* Initialize NAND flash at CS 0 */ + nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs), + FLASH_NAND_CSDEV_PARAM); + nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs), + FLASH_NAND_CSTIME_PARAMA); + nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs), + FLASH_NAND_CSTIME_PARAMB); + + pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res); + return platform_device_register(&xlr_nand_dev); + } + + if (boot_nor) { + setup_flash_resource(flash_mmio, flash_map_base, cs, + xlr_nor_res); + pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res); + return platform_device_register(&xlr_nor_dev); + } + return 0; +} + +arch_initcall(xlr_flash_init); -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:42:50 +0100 (CET) Received: from smtpgw2.netlogicmicro.com ([12.203.210.54]:52727 "EHLO smtpgw2.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904113Ab2BBOj3 (ORCPT ); Thu, 2 Feb 2012 15:39:29 +0100 Received: from pps.filterd (smtpgw2 [127.0.0.1]) by smtpgw2.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12EcpTn028764; Thu, 2 Feb 2012 06:39:22 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw2.netlogicmicro.com with ESMTP id 11pcrwt2aa-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:22 -0800 From: Jayachandran C To: , CC: Madhusudan Bhat , Jayachandran C Subject: [PATCH 09/11] MIPS: Netlogic: Oprofile driver for XLR/XLS Date: Thu, 2 Feb 2012 20:13:03 +0530 Message-ID: <582a2958190922eb91bb514c31cbfcf1d20b87ca.1328189941.git.jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32392 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3860 Lines: 121 From: Madhusudan Bhat Add support for XLR and XLS processors in MIPS Oprofile code. These processors are multi-threaded and have two counters per core. Each counter can track either all the events in the core (global mode), or events in just one thread. We use the counters in the global mode, and use only the first thread in each core to handle the configuration etc. Signed-off-by: Madhusudan Bhat Signed-off-by: Jayachandran C --- arch/mips/oprofile/Makefile | 1 + arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 0 deletions(-) diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index 29f2f13..e851d10 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -14,5 +14,6 @@ oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o +oprofile-$(CONFIG_CPU_XLR) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index d1f2d4c..0c01142 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -89,6 +89,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_R10000: case CPU_R12000: case CPU_R14000: + case CPU_XLR: lmodel = &op_model_mipsxx_ops; break; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..15cbc34 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -31,8 +31,22 @@ #define M_COUNTER_OVERFLOW (1UL << 31) +/* Netlogic XLR specific, count events in all threads in a core */ +#define M_PERFCTL_COUNT_ALL_THREADS (1UL << 13) + static int (*save_perf_irq)(void); +/* + * XLR has only one set of counters per core. Designate the + * first hardware thread in the core for setup and init. + * Skip CPUs with non-zero hardware thread id (4 hwt per core) + */ +#ifdef CONFIG_CPU_XLR +#define oprofile_skip_cpu(c) ((cpu_logical_map(c) & 0x3) != 0) +#else +#define oprofile_skip_cpu(c) 0 +#endif + #ifdef CONFIG_MIPS_MT_SMP static int cpu_has_mipsmt_pertccounters; #define WHAT (M_TC_EN_VPE | \ @@ -152,6 +166,8 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr) reg.control[i] |= M_PERFCTL_USER; if (ctr[i].exl) reg.control[i] |= M_PERFCTL_EXL; + if (current_cpu_type() == CPU_XLR) + reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS; reg.counter[i] = 0x80000000 - ctr[i].count; } } @@ -162,6 +178,9 @@ static void mipsxx_cpu_setup(void *args) { unsigned int counters = op_model_mipsxx_ops.num_counters; + if (oprofile_skip_cpu(smp_processor_id())) + return; + switch (counters) { case 4: w_c0_perfctrl3(0); @@ -183,6 +202,9 @@ static void mipsxx_cpu_start(void *args) { unsigned int counters = op_model_mipsxx_ops.num_counters; + if (oprofile_skip_cpu(smp_processor_id())) + return; + switch (counters) { case 4: w_c0_perfctrl3(WHAT | reg.control[3]); @@ -200,6 +222,9 @@ static void mipsxx_cpu_stop(void *args) { unsigned int counters = op_model_mipsxx_ops.num_counters; + if (oprofile_skip_cpu(smp_processor_id())) + return; + switch (counters) { case 4: w_c0_perfctrl3(0); @@ -365,6 +390,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/sb1"; break; + case CPU_XLR: + op_model_mipsxx_ops.cpu_type = "mips/xlr"; + break; + default: printk(KERN_ERR "Profiling unsupported for this CPU\n"); -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:43:17 +0100 (CET) Received: from smtpgw1.netlogicmicro.com ([12.203.210.53]:46756 "EHLO smtpgw1.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904115Ab2BBOjb (ORCPT ); Thu, 2 Feb 2012 15:39:31 +0100 Received: from pps.filterd (smtpgw1 [127.0.0.1]) by smtpgw1.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12EM67W012889; Thu, 2 Feb 2012 06:39:25 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw1.netlogicmicro.com with ESMTP id 12hfu7nyfu-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:25 -0800 From: Jayachandran C To: , CC: Ganesan Ramalingam , Jayachandran C Subject: [PATCH 10/11] MIPS: Netlogic: XLP PCIe controller support. Date: Thu, 2 Feb 2012 20:13:04 +0530 Message-ID: <0cf5927c0d043919d424eef38615f76e3e1e6683.1328189941.git.jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 14680 Lines: 453 From: Ganesan Ramalingam Adds support for the XLP on-chip PCIe controller. On XLP, the on-chip devices(including the 4 PCIe links) appear in the PCIe configuration space of the XLP as PCI devices. The changes are to initialize and register the PCIe controller, enable hardware byte swap in the PCIe IO and MEM space, and to enable PCIe interrupts. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 1 - arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 3 + arch/mips/include/asm/netlogic/xlp-hal/pcibus.h | 76 +++++++ arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 8 +- arch/mips/netlogic/xlp/nlm_hal.c | 16 ++ arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-xlp.c | 247 +++++++++++++++++++++++ 7 files changed, 349 insertions(+), 3 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h create mode 100644 arch/mips/pci/pci-xlp.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index baabbe5..7d77ac7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -794,7 +794,6 @@ config NLM_XLP_BOARD select SYS_HAS_CPU_XLP select SYS_SUPPORTS_SMP select HW_HAS_PCI - select SWAP_IO_SPACE select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select 64BIT_PHYS_ADDR diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h index 86cc339..ece86f1 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h @@ -36,6 +36,9 @@ #define __NLM_HAL_IOMAP_H__ #define XLP_DEFAULT_IO_BASE 0x18000000 +#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE +#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000 + #define NMI_BASE 0xbfc00000 #define XLP_IO_CLK 133333333 diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h new file mode 100644 index 0000000..b4e6d51 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h @@ -0,0 +1,76 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NLM_HAL_PCIBUS_H__ +#define __NLM_HAL_PCIBUS_H__ + +/* PCIE Memory and IO regions */ +#define PCIE_MEM_BASE 0xd0000000ULL +#define PCIE_MEM_LIMIT 0xdfffffffULL +#define PCIE_IO_BASE 0x14000000ULL +#define PCIE_IO_LIMIT 0x15ffffffULL + +#define PCIE_BRIDGE_CMD 0x1 +#define PCIE_BRIDGE_MSI_CAP 0x14 +#define PCIE_BRIDGE_MSI_ADDRL 0x15 +#define PCIE_BRIDGE_MSI_ADDRH 0x16 +#define PCIE_BRIDGE_MSI_DATA 0x17 + +/* XLP Global PCIE configuration space registers */ +#define PCIE_BYTE_SWAP_MEM_BASE 0x247 +#define PCIE_BYTE_SWAP_MEM_LIM 0x248 +#define PCIE_BYTE_SWAP_IO_BASE 0x249 +#define PCIE_BYTE_SWAP_IO_LIM 0x24A +#define PCIE_MSI_STATUS 0x25A +#define PCIE_MSI_EN 0x25B +#define PCIE_INT_EN0 0x261 + +/* PCIE_MSI_EN */ +#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF + +/* PCIE_INT_EN0 */ +#define PCIE_MSI_INT_EN (1 << 9) + +#ifndef __ASSEMBLY__ + +#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_get_pcie_base(node, inst) \ + nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) +#define nlm_get_pcie_regbase(node, inst) \ + (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) + +int xlp_pcie_link_irt(int link); +#endif +#endif /* __NLM_HAL_PCIBUS_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index 1540588..dc6e98e 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -35,8 +35,12 @@ #ifndef _NLM_HAL_XLP_H #define _NLM_HAL_XLP_H -#define PIC_UART_0_IRQ 17 -#define PIC_UART_1_IRQ 18 +#define PIC_UART_0_IRQ 17 +#define PIC_UART_1_IRQ 18 +#define PIC_PCIE_LINK_0_IRQ 19 +#define PIC_PCIE_LINK_1_IRQ 20 +#define PIC_PCIE_LINK_2_IRQ 21 +#define PIC_PCIE_LINK_3_IRQ 22 #ifndef __ASSEMBLY__ diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c index 9428e71..3a4a172 100644 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ b/arch/mips/netlogic/xlp/nlm_hal.c @@ -69,6 +69,14 @@ int nlm_irq_to_irt(int irq) return PIC_IRT_UART_0_INDEX; case PIC_UART_1_IRQ: return PIC_IRT_UART_1_INDEX; + case PIC_PCIE_LINK_0_IRQ: + return PIC_IRT_PCIE_LINK_0_INDEX; + case PIC_PCIE_LINK_1_IRQ: + return PIC_IRT_PCIE_LINK_1_INDEX; + case PIC_PCIE_LINK_2_IRQ: + return PIC_IRT_PCIE_LINK_2_INDEX; + case PIC_PCIE_LINK_3_IRQ: + return PIC_IRT_PCIE_LINK_3_INDEX; default: return -1; } @@ -81,6 +89,14 @@ int nlm_irt_to_irq(int irt) return PIC_UART_0_IRQ; case PIC_IRT_UART_1_INDEX: return PIC_UART_1_IRQ; + case PIC_IRT_PCIE_LINK_0_INDEX: + return PIC_PCIE_LINK_0_IRQ; + case PIC_IRT_PCIE_LINK_1_INDEX: + return PIC_PCIE_LINK_1_IRQ; + case PIC_IRT_PCIE_LINK_2_INDEX: + return PIC_PCIE_LINK_2_IRQ; + case PIC_IRT_PCIE_LINK_3_INDEX: + return PIC_PCIE_LINK_3_IRQ; default: return -1; } diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c3ac4b0..44cdf55 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o obj-$(CONFIG_CPU_XLR) += pci-xlr.o +obj-$(CONFIG_CPU_XLP) += pci-xlp.o ifdef CONFIG_PCI_MSI obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c new file mode 100644 index 0000000..7bb84ba --- /dev/null +++ b/arch/mips/pci/pci-xlp.c @@ -0,0 +1,247 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include + +static void *pci_config_base; + +#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) + +/* PCI ops */ +static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, + int where) +{ + u32 data; + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + data = *cfgaddr; + return data; +} + +static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, + int where, u32 data) +{ + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + *cfgaddr = data; +} + +static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + + +static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + pci_cfg_write_32bit(bus, devfn, where, data); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops nlm_pci_ops = { + .read = nlm_pcibios_read, + .write = nlm_pcibios_write +}; + +static struct resource nlm_pci_mem_resource = { + .name = "XLP PCI MEM", + .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ + .end = 0xdfffffffUL, + .flags = IORESOURCE_MEM, +}; + +static struct resource nlm_pci_io_resource = { + .name = "XLP IO MEM", + .start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */ + .end = 0x17ffffffUL, + .flags = IORESOURCE_IO, +}; + +struct pci_controller nlm_pci_controller = { + .index = 0, + .pci_ops = &nlm_pci_ops, + .mem_resource = &nlm_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &nlm_pci_io_resource, + .io_offset = 0x00000000UL, +}; + +static int get_irq_vector(const struct pci_dev *dev) +{ + /* + * For XLP PCIe, there is an IRQ per Link, find out which + * link the device is on to assign interrupts + */ + if (dev->bus->self == NULL) + return 0; + + switch (dev->bus->self->devfn) { + case 0x8: + return PIC_PCIE_LINK_0_IRQ; + case 0x9: + return PIC_PCIE_LINK_1_IRQ; + case 0xa: + return PIC_PCIE_LINK_2_IRQ; + case 0xb: + return PIC_PCIE_LINK_3_IRQ; + } + WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); + return 0; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return get_irq_vector(dev); +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static int xlp_enable_pci_bswap(void) +{ + uint64_t pciebase, sysbase; + int node, i; + u32 reg; + + /* Chip-0 so node set to 0 */ + node = 0; + sysbase = nlm_get_bridge_regbase(node); + /* + * Enable byte swap in hardware. Program each link's PCIe SWAP regions + * from the link's address ranges. + */ + for (i = 0; i < 4; i++) { + pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i)); + if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) + continue; + + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); + + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, reg); + + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); + + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg); + } + return 0; +} + +static int __init pcibios_init(void) +{ + /* Firmware assigns PCI resources */ + pci_probe_only = 1; + pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); + + /* Extend IO port for memory mapped io */ + ioport_resource.start = 0; + ioport_resource.end = ~0; + + xlp_enable_pci_bswap(); + set_io_port_base(CKSEG1); + nlm_pci_controller.io_map_base = CKSEG1; + + register_pci_controller(&nlm_pci_controller); + pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource, + &nlm_pci_mem_resource); + + return 0; +} +arch_initcall(pcibios_init); -- 1.7.5.4 From jayachandranc@netlogicmicro.com Thu Feb 2 15:39:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 15:43:44 +0100 (CET) Received: from smtpgw2.netlogicmicro.com ([12.203.210.54]:52728 "EHLO smtpgw2.netlogicmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904116Ab2BBOje (ORCPT ); Thu, 2 Feb 2012 15:39:34 +0100 Received: from pps.filterd (smtpgw2 [127.0.0.1]) by smtpgw2.netlogicmicro.com (8.14.5/8.14.5) with SMTP id q12Ed9ZJ029370; Thu, 2 Feb 2012 06:39:27 -0800 Received: from hqcas02.netlogicmicro.com (hqcas02.netlogicmicro.com [10.65.50.15]) by smtpgw2.netlogicmicro.com with ESMTP id 11pcrwt2ah-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Thu, 02 Feb 2012 06:39:27 -0800 From: Jayachandran C To: , CC: Ganesan Ramalingam , Jayachandran C Subject: [PATCH 11/11] MIPS: Netlogic: USB support for XLP Date: Thu, 2 Feb 2012 20:13:05 +0530 Message-ID: <5360c071d54ce6c5217b53fc41e4672a680ff3f4.1328189941.git.jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.7.0.77] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.6.7361,1.0.211,0.0.0000 definitions=2012-01-28_02:2012-01-27,2012-01-28,1970-01-01 signatures=0 X-archive-position: 32394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 12253 Lines: 339 From: Ganesan Ramalingam The XLP USB controller appears as a device on the internal SoC PCIe bus, the block has 2 EHCI blocks and 4 OHCI blocks. Change are to: * Add files netlogic/xlp/usb-init.c and asm/netlogic/xlp-hal/usb.h to initialize the USB controller and define PCI fixups. The PCI fixups are to setup interrupts and DMA mask. * Update include/asm/xlp-hal/{iomap.h,pic.h,xlp.h} to add interrupt mapping for EHCI/OHCI interrupts. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 2 +- arch/mips/include/asm/netlogic/xlp-hal/pic.h | 4 + arch/mips/include/asm/netlogic/xlp-hal/usb.h | 64 ++++++++++++ arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 6 + arch/mips/netlogic/xlp/Makefile | 1 + arch/mips/netlogic/xlp/nlm_hal.c | 24 +++++ arch/mips/netlogic/xlp/platform.c | 2 +- arch/mips/netlogic/xlp/usb-init.c | 125 ++++++++++++++++++++++++ 8 files changed, 226 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/usb.h create mode 100644 arch/mips/netlogic/xlp/usb-init.c diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h index ece86f1..2c63f97 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h @@ -132,7 +132,7 @@ #define PCI_DEVICE_ID_NLM_PIC 0x1003 #define PCI_DEVICE_ID_NLM_PCIE 0x1004 #define PCI_DEVICE_ID_NLM_EHCI 0x1007 -#define PCI_DEVICE_ID_NLM_ILK 0x1008 +#define PCI_DEVICE_ID_NLM_OHCI 0x1008 #define PCI_DEVICE_ID_NLM_NAE 0x1009 #define PCI_DEVICE_ID_NLM_POE 0x100A #define PCI_DEVICE_ID_NLM_FMN 0x100B diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h index b6628f7..ad8b802 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h @@ -201,7 +201,11 @@ #define PIC_NUM_USB_IRTS 6 #define PIC_IRT_USB_0_INDEX 115 #define PIC_IRT_EHCI_0_INDEX 115 +#define PIC_IRT_OHCI_0_INDEX 116 +#define PIC_IRT_OHCI_1_INDEX 117 #define PIC_IRT_EHCI_1_INDEX 118 +#define PIC_IRT_OHCI_2_INDEX 119 +#define PIC_IRT_OHCI_3_INDEX 120 #define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX) /* 115 to 120 */ #define PIC_IRT_GDX_INDEX 121 diff --git a/arch/mips/include/asm/netlogic/xlp-hal/usb.h b/arch/mips/include/asm/netlogic/xlp-hal/usb.h new file mode 100644 index 0000000..4052be4 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/usb.h @@ -0,0 +1,64 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NLM_HAL_USB_H__ +#define __NLM_HAL_USB_H__ + +#define USB_CTL_0 0x01 +#define USB_PHY_0 0x0A +#define USB_PHY_RESET 0x01 +#define USB_PHY_PORT_RESET_0 0x10 +#define USB_PHY_PORT_RESET_1 0x20 +#define USB_CONTROLLER_RESET 0x01 +#define USB_INT_STATUS 0x0E +#define USB_INT_EN 0x0F +#define USB_PHY_INTERRUPT_EN 0x01 +#define USB_OHCI_INTERRUPT_EN 0x02 +#define USB_OHCI_INTERRUPT1_EN 0x04 +#define USB_OHCI_INTERRUPT2_EN 0x08 +#define USB_CTRL_INTERRUPT_EN 0x10 + +#ifndef __ASSEMBLY__ + +#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_get_usb_pcibase(node, inst) \ + nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst)) +#define nlm_get_usb_hcd_base(node, inst) \ + nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst)) +#define nlm_get_usb_regbase(node, inst) \ + (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) + +#endif +#endif /* __NLM_HAL_USB_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index dc6e98e..3921a31 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -41,6 +41,12 @@ #define PIC_PCIE_LINK_1_IRQ 20 #define PIC_PCIE_LINK_2_IRQ 21 #define PIC_PCIE_LINK_3_IRQ 22 +#define PIC_EHCI_0_IRQ 23 +#define PIC_EHCI_1_IRQ 24 +#define PIC_OHCI_0_IRQ 25 +#define PIC_OHCI_1_IRQ 26 +#define PIC_OHCI_2_IRQ 27 +#define PIC_OHCI_3_IRQ 28 #ifndef __ASSEMBLY__ diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile index b93ed83..5bd24b6 100644 --- a/arch/mips/netlogic/xlp/Makefile +++ b/arch/mips/netlogic/xlp/Makefile @@ -1,2 +1,3 @@ obj-y += setup.o platform.o nlm_hal.o obj-$(CONFIG_SMP) += wakeup.o +obj-$(CONFIG_USB) += usb-init.o diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c index 3a4a172..fad2cae 100644 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ b/arch/mips/netlogic/xlp/nlm_hal.c @@ -77,6 +77,18 @@ int nlm_irq_to_irt(int irq) return PIC_IRT_PCIE_LINK_2_INDEX; case PIC_PCIE_LINK_3_IRQ: return PIC_IRT_PCIE_LINK_3_INDEX; + case PIC_EHCI_0_IRQ: + return PIC_IRT_EHCI_0_INDEX; + case PIC_EHCI_1_IRQ: + return PIC_IRT_EHCI_1_INDEX; + case PIC_OHCI_0_IRQ: + return PIC_IRT_OHCI_0_INDEX; + case PIC_OHCI_1_IRQ: + return PIC_IRT_OHCI_1_INDEX; + case PIC_OHCI_2_IRQ: + return PIC_IRT_OHCI_2_INDEX; + case PIC_OHCI_3_IRQ: + return PIC_IRT_OHCI_3_INDEX; default: return -1; } @@ -97,6 +109,18 @@ int nlm_irt_to_irq(int irt) return PIC_PCIE_LINK_2_IRQ; case PIC_IRT_PCIE_LINK_3_INDEX: return PIC_PCIE_LINK_3_IRQ; + case PIC_IRT_EHCI_0_INDEX: + return PIC_EHCI_0_IRQ; + case PIC_IRT_EHCI_1_INDEX: + return PIC_EHCI_1_IRQ; + case PIC_IRT_OHCI_0_INDEX: + return PIC_OHCI_0_IRQ; + case PIC_IRT_OHCI_1_INDEX: + return PIC_OHCI_1_IRQ; + case PIC_IRT_OHCI_2_INDEX: + return PIC_OHCI_2_IRQ; + case PIC_IRT_OHCI_3_INDEX: + return PIC_OHCI_3_IRQ; default: return -1; } diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c index 1f5e4cb..2c510d5 100644 --- a/arch/mips/netlogic/xlp/platform.c +++ b/arch/mips/netlogic/xlp/platform.c @@ -53,7 +53,7 @@ static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset) { - return nlm_read_reg(p->iobase, offset); + return nlm_read_reg(p->iobase, offset); } static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value) diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c new file mode 100644 index 0000000..81ce206 --- /dev/null +++ b/arch/mips/netlogic/xlp/usb-init.c @@ -0,0 +1,125 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static void nlm_usb_intr_en(int node, int port) +{ + uint32_t val; + uint64_t port_addr; + + port_addr = nlm_get_usb_regbase(node, port); + val = nlm_read_usb_reg(port_addr, USB_INT_EN); + val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | + USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN | + USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN; + nlm_write_usb_reg(port_addr, USB_INT_EN, val); +} + +static void nlm_usb_hw_reset(int node, int port) +{ + uint64_t port_addr; + uint32_t val; + + /* reset USB phy */ + port_addr = nlm_get_usb_regbase(node, port); + val = nlm_read_usb_reg(port_addr, USB_PHY_0); + val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1); + nlm_write_usb_reg(port_addr, USB_PHY_0, val); + + mdelay(100); + val = nlm_read_usb_reg(port_addr, USB_CTL_0); + val &= ~(USB_CONTROLLER_RESET); + val |= 0x4; + nlm_write_usb_reg(port_addr, USB_CTL_0, val); +} + +static int __init nlm_platform_usb_init(void) +{ + pr_info("Initializing USB Interface\n"); + nlm_usb_hw_reset(0, 0); + nlm_usb_hw_reset(0, 3); + + /* Enable PHY interrupts */ + nlm_usb_intr_en(0, 0); + nlm_usb_intr_en(0, 3); + + return 0; +} + +arch_initcall(nlm_platform_usb_init); + +static u64 xlp_usb_dmamask = ~(u32)0; + +/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */ +static void nlm_usb_fixup_final(struct pci_dev *dev) +{ + dev->dev.dma_mask = &xlp_usb_dmamask, + dev->dev.coherent_dma_mask = DMA_BIT_MASK(64); + switch (dev->devfn) { + case 0x10: + dev->irq = PIC_EHCI_0_IRQ; + break; + case 0x11: + dev->irq = PIC_OHCI_0_IRQ; + break; + case 0x12: + dev->irq = PIC_OHCI_1_IRQ; + break; + case 0x13: + dev->irq = PIC_EHCI_1_IRQ; + break; + case 0x14: + dev->irq = PIC_OHCI_2_IRQ; + break; + case 0x15: + dev->irq = PIC_OHCI_3_IRQ; + break; + } + + return 0; +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI, + nlm_usb_fixup_final); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI, + nlm_usb_fixup_final); -- 1.7.5.4 From jonas.gorski@gmail.com Thu Feb 2 21:53:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Feb 2012 21:53:13 +0100 (CET) Received: from mail-ee0-f49.google.com ([74.125.83.49]:57463 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904172Ab2BBUxH (ORCPT ); Thu, 2 Feb 2012 21:53:07 +0100 Received: by eeke50 with SMTP id e50so960688eek.36 for ; Thu, 02 Feb 2012 12:53:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=E3Ds6aSjv9ScZRlOTBF01PWW8fBnkmfzTEA0277ZOTg=; b=QvAOu1DRYdp3TgrerMiZLcYZeeuBs1WkZOlFnKJMNLg2qamrZiKylrdOgc/IEpOHWL TF2ejha/lcUNvuXVa1Xba0aGZcIiXdVvOfnuV82/KqQsWj+nKOu1Z+zb/56ud77sn/uN D8HE4FgOhWfwspE0Ks77jDUr//dzv1p+G+DaY= Received: by 10.14.131.13 with SMTP id l13mr1376434eei.45.1328215981802; Thu, 02 Feb 2012 12:53:01 -0800 (PST) Received: from shaker64.lan (dslb-088-073-058-217.pools.arcor-ip.net. [88.73.58.217]) by mx.google.com with ESMTPS id x4sm13350636eeb.4.2012.02.02.12.53.00 (version=SSLv3 cipher=OTHER); Thu, 02 Feb 2012 12:53:00 -0800 (PST) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli Subject: [PATCH] MIPS: BCM63XX: add missing include for bcm63xx_gpio.h Date: Thu, 2 Feb 2012 21:52:11 +0100 Message-Id: <1328215931-24817-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 32395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2173 Lines: 46 bcm63xx_gpio.h uses macros defined in bcm63xx_cpu.h without including it, leading to the following build failure: CC [M] drivers/mmc/core/cd-gpio.o In file included from arch/mips/include/asm/mach-bcm63xx/gpio.h:4:0, from arch/mips/include/asm/gpio.h:4, from include/linux/gpio.h:30, from drivers/mmc/core/cd-gpio.c:12: arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h: In function 'bcm63xx_gpio_count': arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:10:2: error: implicit declaration of function 'bcm63xx_get_cpu_id' arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: error: 'BCM6358_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: note: each undeclared identifier is reported only once for each function it appears in arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:13:7: error: 'BCM6338_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:15:7: error: 'BCM6345_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:17:7: error: 'BCM6368_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:19:7: error: 'BCM6348_CPU_ID' undeclared (first use in this function) make[7]: *** [drivers/mmc/core/cd-gpio.o] Error 1 Signed-off-by: Jonas Gorski --- Looking at the file's history, it looks like the problem was there from the beginning. So it probably should go into all supported (stable) versions up to 3.3-rc2, even if this particular build failure popped up first in 3.3. arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 3d5de96..1d7dd96 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -2,6 +2,7 @@ #define BCM63XX_GPIO_H #include +#include int __init bcm63xx_gpio_init(void); -- 1.7.2.5 From xiyou.wangcong@gmail.com Fri Feb 3 08:52:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Feb 2012 08:52:17 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:56951 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903616Ab2BCHwK (ORCPT ); Fri, 3 Feb 2012 08:52:10 +0100 Received: by dakp5 with SMTP id p5so3044254dak.36 for ; Thu, 02 Feb 2012 23:52:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=3byXzL6v/3lk8hnRfA2/8uhQTFQGHdoE1vLhJGnOfI8=; b=PxA/OXoo0MTEu53w3OpMEW9u87+U9v15eK746Y58djvbWRqwwgbpWjN9CWXUjNf1xj RoOYnCHS1rrVKmu+XadU8kUAlEFaRN4XgetOzVY6kc1Rrn0WYNuj8xuG6TRYkb4iROGe WbZ+H8BD/IhYGrc90+at19QDkXM581GenhhEw= Received: by 10.68.130.40 with SMTP id ob8mr15334346pbb.106.1328255523391; Thu, 02 Feb 2012 23:52:03 -0800 (PST) Received: from cr0.redhat.com ([180.129.255.55]) by mx.google.com with ESMTPS id j5sm11238601pbe.1.2012.02.02.23.51.56 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 02 Feb 2012 23:52:02 -0800 (PST) From: Cong Wang To: linux-kernel@vger.kernel.org Cc: Andrew Morton , WANG Cong , Ralf Baechle , David Daney , Hillf Danton , linux-mips@linux-mips.org Subject: [Patch] mips: do not redefine BUILD_BUG() Date: Fri, 3 Feb 2012 15:51:40 +0800 Message-Id: <1328255503-17575-1-git-send-email-xiyou.wangcong@gmail.com> X-Mailer: git-send-email 1.7.7.6 X-archive-position: 32396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: xiyou.wangcong@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1024 Lines: 29 On mips, we got include/linux/kernel.h:717:1: error: "BUILD_BUG" redefined arch/mips/include/asm/page.h:43:1: error: this is the location of the previous definition make[3]: *** [arch/mips/sgi-ip27/ip27-console.o] Error 1 make[2]: *** [arch/mips/sgi-ip27] Error 2 make[1]: *** [arch/mips] Error 2 make: *** [sub-make] Error 2 use generic BUILD_BUG() instead of re-defining one. Signed-off-by: WANG Cong --- diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index d417909..e14121a 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -39,9 +39,7 @@ #define HPAGE_MASK (~(HPAGE_SIZE - 1)) #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) #else /* !CONFIG_HUGETLB_PAGE */ -# ifndef BUILD_BUG -# define BUILD_BUG() do { extern void __build_bug(void); __build_bug(); } while (0) -# endif +#include #define HPAGE_SHIFT ({BUILD_BUG(); 0; }) #define HPAGE_SIZE ({BUILD_BUG(); 0; }) #define HPAGE_MASK ({BUILD_BUG(); 0; }) From sshtylyov@mvista.com Fri Feb 3 11:26:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Feb 2012 11:27:00 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:36368 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903878Ab2BCK0x (ORCPT ); Fri, 3 Feb 2012 11:26:53 +0100 Received: by bke5 with SMTP id 5so3709412bke.36 for ; Fri, 03 Feb 2012 02:26:46 -0800 (PST) Received: by 10.204.136.197 with SMTP id s5mr3214501bkt.9.1328264806434; Fri, 03 Feb 2012 02:26:46 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-86-184.pppoe.mtu-net.ru. [91.79.86.184]) by mx.google.com with ESMTPS id d2sm15516991bky.11.2012.02.03.02.26.44 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 03 Feb 2012 02:26:45 -0800 (PST) Message-ID: <4F2BB61F.8010708@mvista.com> Date: Fri, 03 Feb 2012 14:25:35 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:9.0) Gecko/20111222 Thunderbird/9.0.1 MIME-Version: 1.0 To: Jonas Gorski CC: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli Subject: Re: [PATCH] MIPS: BCM63XX: add missing include for bcm63xx_gpio.h References: <1328215931-24817-1-git-send-email-jonas.gorski@gmail.com> In-Reply-To: <1328215931-24817-1-git-send-email-jonas.gorski@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1846 Lines: 35 Hello. On 03-02-2012 0:52, Jonas Gorski wrote: > bcm63xx_gpio.h uses macros defined in bcm63xx_cpu.h without including it, > leading to the following build failure: > CC [M] drivers/mmc/core/cd-gpio.o > In file included from arch/mips/include/asm/mach-bcm63xx/gpio.h:4:0, > from arch/mips/include/asm/gpio.h:4, > from include/linux/gpio.h:30, > from drivers/mmc/core/cd-gpio.c:12: > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h: In function 'bcm63xx_gpio_count': > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:10:2: error: implicit declaration of function 'bcm63xx_get_cpu_id' > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: error: 'BCM6358_CPU_ID' undeclared (first use in this function) > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: note: each undeclared identifier is reported only once for each function it appears in > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:13:7: error: 'BCM6338_CPU_ID' undeclared (first use in this function) > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:15:7: error: 'BCM6345_CPU_ID' undeclared (first use in this function) > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:17:7: error: 'BCM6368_CPU_ID' undeclared (first use in this function) > arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:19:7: error: 'BCM6348_CPU_ID' undeclared (first use in this function) > make[7]: *** [drivers/mmc/core/cd-gpio.o] Error 1 > Signed-off-by: Jonas Gorski > --- > Looking at the file's history, it looks like the problem was there from > the beginning. So it probably should go into all supported (stable) > versions up to 3.3-rc2, even if this particular build failure popped up > first in 3.3. You should then addd "Cc: stable@vger.kernel.org" line after your signoff. WBR, Sergei From sshtylyov@mvista.com Fri Feb 3 11:30:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Feb 2012 11:31:04 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:50667 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903878Ab2BCKa6 (ORCPT ); Fri, 3 Feb 2012 11:30:58 +0100 Received: by bke5 with SMTP id 5so3712740bke.36 for ; Fri, 03 Feb 2012 02:30:52 -0800 (PST) Received: by 10.204.136.220 with SMTP id s28mr3154982bkt.59.1328265052467; Fri, 03 Feb 2012 02:30:52 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-86-184.pppoe.mtu-net.ru. [91.79.86.184]) by mx.google.com with ESMTPS id bw9sm15575186bkb.8.2012.02.03.02.30.50 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 03 Feb 2012 02:30:51 -0800 (PST) Message-ID: <4F2BB715.8090803@mvista.com> Date: Fri, 03 Feb 2012 14:29:41 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:9.0) Gecko/20111222 Thunderbird/9.0.1 MIME-Version: 1.0 To: Cong Wang CC: linux-kernel@vger.kernel.org, Andrew Morton , Ralf Baechle , David Daney , Hillf Danton , linux-mips@linux-mips.org Subject: Re: [Patch] mips: do not redefine BUILD_BUG() References: <1328255503-17575-1-git-send-email-xiyou.wangcong@gmail.com> In-Reply-To: <1328255503-17575-1-git-send-email-xiyou.wangcong@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1258 Lines: 41 Hello. On 03-02-2012 11:51, Cong Wang wrote: > On mips, we got > include/linux/kernel.h:717:1: error: "BUILD_BUG" redefined > arch/mips/include/asm/page.h:43:1: error: this is the location of the previous definition > make[3]: *** [arch/mips/sgi-ip27/ip27-console.o] Error 1 > make[2]: *** [arch/mips/sgi-ip27] Error 2 > make[1]: *** [arch/mips] Error 2 > make: *** [sub-make] Error 2 > use generic BUILD_BUG() instead of re-defining one. > Signed-off-by: WANG Cong > --- > diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h > index d417909..e14121a 100644 > --- a/arch/mips/include/asm/page.h > +++ b/arch/mips/include/asm/page.h > @@ -39,9 +39,7 @@ > #define HPAGE_MASK (~(HPAGE_SIZE - 1)) > #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) > #else /* !CONFIG_HUGETLB_PAGE */ > -# ifndef BUILD_BUG Not clear why we get the error if we're protected with #ifndef... > -# define BUILD_BUG() do { extern void __build_bug(void); __build_bug(); } while (0) > -# endif > +#include Do not do #include among the #define's... > #define HPAGE_SHIFT ({BUILD_BUG(); 0; }) > #define HPAGE_SIZE ({BUILD_BUG(); 0; }) > #define HPAGE_MASK ({BUILD_BUG(); 0; }) WBR, Sergei From geert@linux-m68k.org Fri Feb 3 11:42:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Feb 2012 11:42:41 +0100 (CET) Received: from mail-ww0-f41.google.com ([74.125.82.41]:41127 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903879Ab2BCKme convert rfc822-to-8bit (ORCPT ); Fri, 3 Feb 2012 11:42:34 +0100 Received: by wgbdt11 with SMTP id dt11so1074375wgb.0 for ; Fri, 03 Feb 2012 02:42:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=FVgMbIA1FVppaAdeKfcL31nWUi6EVATjhJvJRaP7aLg=; b=Cjo8tALm0wxf3FKmRHeEtVYOcB+0a2TEC5o2ArPfWSb1JJ8BilwOTlbF22gAKXsGIY xG8eHAroOPRZWVRj+He2CLbJQpdwlm2B4gm1z6vgofGjJn2IyT9ioK84iHCShB2lAzEK iZZygAW6CgPsTWAvslv1OUca/UVMtyfwB+USQ= MIME-Version: 1.0 Received: by 10.180.92.226 with SMTP id cp2mr10534461wib.10.1328265749371; Fri, 03 Feb 2012 02:42:29 -0800 (PST) Received: by 10.223.102.80 with HTTP; Fri, 3 Feb 2012 02:42:29 -0800 (PST) In-Reply-To: <4F2BB715.8090803@mvista.com> References: <1328255503-17575-1-git-send-email-xiyou.wangcong@gmail.com> <4F2BB715.8090803@mvista.com> Date: Fri, 3 Feb 2012 11:42:29 +0100 X-Google-Sender-Auth: 0VIJ_JdIqTzDV-8ukczOExntKlU Message-ID: Subject: Re: [Patch] mips: do not redefine BUILD_BUG() From: Geert Uytterhoeven To: Sergei Shtylyov Cc: Cong Wang , linux-kernel@vger.kernel.org, Andrew Morton , Ralf Baechle , David Daney , Hillf Danton , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1012 Lines: 27 On Fri, Feb 3, 2012 at 11:29, Sergei Shtylyov wrote: >> include/linux/kernel.h:717:1: error: "BUILD_BUG" redefined >> arch/mips/include/asm/page.h:43:1: error: this is the location of the >> previous definition >> --- a/arch/mips/include/asm/page.h >> +++ b/arch/mips/include/asm/page.h >> @@ -39,9 +39,7 @@ >>  #define HPAGE_MASK    (~(HPAGE_SIZE - 1)) >>  #define HUGETLB_PAGE_ORDER    (HPAGE_SHIFT - PAGE_SHIFT) >>  #else /* !CONFIG_HUGETLB_PAGE */ >> -# ifndef BUILD_BUG > >   Not clear why we get the error if we're protected with #ifndef... Because this is the first definition. It's redefined later. Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.                                 -- Linus Torvalds From jonas.gorski@gmail.com Fri Feb 3 12:17:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Feb 2012 12:17:32 +0100 (CET) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:39484 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903884Ab2BCLRZ convert rfc822-to-8bit (ORCPT ); Fri, 3 Feb 2012 12:17:25 +0100 Received: by laam7 with SMTP id m7so2113889laa.36 for ; Fri, 03 Feb 2012 03:17:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=ZT5Z2iInb47N6i9bZiu8CsSG4PBQ94Ce8tALgv3rSe8=; b=LG1Yv6gi3T+BNQ+Gw68P1JG1QenKksIfUlDYSBvqzVKJ0fvS/EuegIwNUZ/lb8JXXB CY7aoWVPxsBuAyctra9AnzwOB3wruOsgzwUPXFhcVcWcb5OUsSU3L8oQCTSvKRRKi6dk Ual1FcuJPl1dO+8tDhEl09GhNIRFYcg6AVEes= Received: by 10.112.9.40 with SMTP id w8mr1686893lba.103.1328267840267; Fri, 03 Feb 2012 03:17:20 -0800 (PST) MIME-Version: 1.0 Received: by 10.112.22.2 with HTTP; Fri, 3 Feb 2012 03:17:00 -0800 (PST) In-Reply-To: <4F2BB61F.8010708@mvista.com> References: <1328215931-24817-1-git-send-email-jonas.gorski@gmail.com> <4F2BB61F.8010708@mvista.com> From: Jonas Gorski Date: Fri, 3 Feb 2012 12:17:00 +0100 Message-ID: Subject: Re: [PATCH] MIPS: BCM63XX: add missing include for bcm63xx_gpio.h To: Sergei Shtylyov Cc: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 379 Lines: 11 Hi, On 3 February 2012 11:25, Sergei Shtylyov wrote: >   You should then addd "Cc: stable@vger.kernel.org" line after your signoff. Hrm, somehow I misremember this is supposed to be done only after the patch got accepted. You are (mostly) right, only the address is now stable@kernel.org :) I'll resend shortly. a bit more confused than usually, Jonas From c.jayachandran@gmail.com Fri Feb 3 12:29:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Feb 2012 12:29:46 +0100 (CET) Received: from mail-we0-f177.google.com ([74.125.82.177]:43562 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903883Ab2BCL3l (ORCPT ); Fri, 3 Feb 2012 12:29:41 +0100 Received: by wera10 with SMTP id a10so3404906wer.36 for ; Fri, 03 Feb 2012 03:29:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=q4abndwuLrxTOJPahU7gyauY+DqKZm/cDKKOyG9CswU=; b=LJ57cOvpvqGHmRTnLiZxDEj5NrYqdxoIFqGYPjiqyjDpYU5pdiHU6z9jyfcyIGtxzs VAJSGsLd7frK7VgEXFnEopkaNwBQQyigW5dNHuyhm5AC7K0+czUM8hgKLVIr5rIC19Si jMbOcavPV08vWCbGh8xWyJsuwMcX4SJtGummg= MIME-Version: 1.0 Received: by 10.216.131.29 with SMTP id l29mr578553wei.48.1328268575573; Fri, 03 Feb 2012 03:29:35 -0800 (PST) Received: by 10.216.0.134 with HTTP; Fri, 3 Feb 2012 03:29:35 -0800 (PST) In-Reply-To: <1328255503-17575-1-git-send-email-xiyou.wangcong@gmail.com> References: <1328255503-17575-1-git-send-email-xiyou.wangcong@gmail.com> Date: Fri, 3 Feb 2012 16:59:35 +0530 Message-ID: Subject: Re: [Patch] mips: do not redefine BUILD_BUG() From: "Jayachandran C." To: Cong Wang Cc: linux-kernel@vger.kernel.org, Andrew Morton , Ralf Baechle , David Daney , Hillf Danton , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 32401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: c.jayachandran@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 772 Lines: 23 On Fri, Feb 3, 2012 at 1:21 PM, Cong Wang wrote: > On mips, we got > > include/linux/kernel.h:717:1: error: "BUILD_BUG" redefined > arch/mips/include/asm/page.h:43:1: error: this is the location of the previous definition > make[3]: *** [arch/mips/sgi-ip27/ip27-console.o] Error 1 > make[2]: *** [arch/mips/sgi-ip27] Error 2 > make[1]: *** [arch/mips] Error 2 > make: *** [sub-make] Error 2 > > use generic BUILD_BUG() instead of re-defining one. > > Signed-off-by: WANG Cong This is already fixed in linux-mips.org repository: commit 2f5d5510507626ee799b6d1304d154569b6dfe05 Author: Ralf Baechle Date: Mon Jan 16 12:38:05 2012 +0100 MIPS: Remove temporary kludge from JC. From sshtylyov@mvista.com Fri Feb 3 12:35:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Feb 2012 12:36:04 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:42931 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903943Ab2BCLf5 (ORCPT ); Fri, 3 Feb 2012 12:35:57 +0100 Received: by bke5 with SMTP id 5so3770970bke.36 for ; Fri, 03 Feb 2012 03:35:51 -0800 (PST) Received: by 10.204.152.208 with SMTP id h16mr3430140bkw.6.1328268951437; Fri, 03 Feb 2012 03:35:51 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-86-184.pppoe.mtu-net.ru. [91.79.86.184]) by mx.google.com with ESMTPS id ga13sm16108930bkc.5.2012.02.03.03.35.48 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 03 Feb 2012 03:35:50 -0800 (PST) Message-ID: <4F2BC64F.3070306@mvista.com> Date: Fri, 03 Feb 2012 15:34:39 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:9.0) Gecko/20111222 Thunderbird/9.0.1 MIME-Version: 1.0 To: Jonas Gorski CC: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli Subject: Re: [PATCH] MIPS: BCM63XX: add missing include for bcm63xx_gpio.h References: <1328215931-24817-1-git-send-email-jonas.gorski@gmail.com> <4F2BB61F.8010708@mvista.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32402 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 468 Lines: 17 Hello. On 03-02-2012 15:17, Jonas Gorski wrote: >> You should then addd "Cc: stable@vger.kernel.org" line after your signoff. > Hrm, somehow I misremember this is supposed to be done only after the > patch got accepted. You are (mostly) right, only the address is now > stable@kernel.org :) I'll resend shortly. I heard the contrary -- that it was stable@kernel.org and now stable@vger.kernel.org. > a bit more confused than usually, > Jonas WBR, Sergei From grant.likely@secretlab.ca Sat Feb 4 00:16:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 04 Feb 2012 00:17:00 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:37876 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904199Ab2BCXQz convert rfc822-to-8bit (ORCPT ); Sat, 4 Feb 2012 00:16:55 +0100 Received: by pbdx9 with SMTP id x9so3927753pbd.36 for ; Fri, 03 Feb 2012 15:16:48 -0800 (PST) Received: by 10.68.74.69 with SMTP id r5mr21595490pbv.118.1328311008129; Fri, 03 Feb 2012 15:16:48 -0800 (PST) MIME-Version: 1.0 Received: by 10.68.224.170 with HTTP; Fri, 3 Feb 2012 15:16:28 -0800 (PST) In-Reply-To: <20111026073348.GB2915@opensource.wolfsonmicro.com> References: <1319528012-19006-1-git-send-email-broonie@opensource.wolfsonmicro.com> <20111026073348.GB2915@opensource.wolfsonmicro.com> From: Grant Likely Date: Fri, 3 Feb 2012 16:16:28 -0700 X-Google-Sender-Auth: QCaMiBSYY2kFLeomBBCgc9xFG4c Message-ID: Subject: Re: [PATCH] gpiolib/arches: Centralise bolierplate asm/gpio.h To: Mark Brown Cc: Mike Frysinger , Russell King , Haavard Skinnemoen , Hans-Christian Egtvedt , Geert Uytterhoeven , Ralf Baechle , Paul Mundt , Guan Xuetao , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 32403 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1548 Lines: 36 On Wed, Oct 26, 2011 at 1:33 AM, Mark Brown wrote: > On Tue, Oct 25, 2011 at 07:44:14PM -0400, Mike Frysinger wrote: > >> i don't think this is generally how asm-generic is handled. instead, how about: >> - move the duplicate code to asm-generic/gpio.h >> - have the arches which merely need asm-generic/gpio.h add "generic-y >> += gpio.h" to their include/asm/Kbuild >> - for arches which need to override these common funcs in some way, >> add #ifdef protection to the asm-generic/gpio.h > >> and it seems like with slightly more work, this path allow you to >> merge most of arch/sh/include/asm/gpio.h. and it has the advantage of >> not needing new Kconfig symbols. > > That's really not how gpiolib is currently handled, unfortunately - > trying to transition over to that model in one patch would be way too > much. > > The goal here from that point of view is to make transitioning to > something more sensible easier by getting rid of the boilerplate code, > it makes doing the more invasive changes like you're suggesting much > easier as we're only dealing with the architectures that are actually > doing something. It also means that we're able to immediately work on > turning on gpiolib on random architectures which is a definite win. I had picked up this patch, but I've dropped again from gpio/next since there are still a lot of drivers including asm/gpio.h. It caused build breakage on linux-next with allmodconfig. g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. From jonas.gorski@gmail.com Sat Feb 4 11:08:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 04 Feb 2012 11:08:38 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:35340 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903604Ab2BDKIb (ORCPT ); Sat, 4 Feb 2012 11:08:31 +0100 Received: by bkcjk13 with SMTP id jk13so18648bkc.36 for ; Sat, 04 Feb 2012 02:08:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=5DbAKFYwy9Pcg1BtxsGhRbHPD1tUZtU03iH+TQ8Jsrc=; b=i5r7zPKtsJ/1IEUu/VPcf7UAJ1qqjhOPGM6uDS8gdo230BqkkPGYbYw07gmGvmMuCB tzXt9ygtBWg+mxcW5j+wInsghXbJaQ4N4ZcQxhulukddzgh3DUjpSiR1CetNOhhx7Ivq gHmbuKmmSxfBs7nQpQ5t1gJUZwe9N1KLrGUYE= Received: by 10.204.9.198 with SMTP id m6mr4960192bkm.74.1328350105851; Sat, 04 Feb 2012 02:08:25 -0800 (PST) Received: from shaker64.lan (dslb-088-073-058-217.pools.arcor-ip.net. [88.73.58.217]) by mx.google.com with ESMTPS id ez5sm24774605bkc.15.2012.02.04.02.08.24 (version=SSLv3 cipher=OTHER); Sat, 04 Feb 2012 02:08:24 -0800 (PST) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli , stable@vger.kernel.org Subject: [PATCH V2] MIPS: BCM63XX: add missing include for bcm63xx_gpio.h Date: Sat, 4 Feb 2012 11:07:37 +0100 Message-Id: <1328350057-10797-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 32404 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2200 Lines: 50 bcm63xx_gpio.h uses macros defined in bcm63xx_cpu.h without including it, leading to the following build failure: CC [M] drivers/mmc/core/cd-gpio.o In file included from arch/mips/include/asm/mach-bcm63xx/gpio.h:4:0, from arch/mips/include/asm/gpio.h:4, from include/linux/gpio.h:30, from drivers/mmc/core/cd-gpio.c:12: arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h: In function 'bcm63xx_gpio_count': arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:10:2: error: implicit declaration of function 'bcm63xx_get_cpu_id' arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: error: 'BCM6358_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:11:7: note: each undeclared identifier is reported only once for each function it appears in arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:13:7: error: 'BCM6338_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:15:7: error: 'BCM6345_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:17:7: error: 'BCM6368_CPU_ID' undeclared (first use in this function) arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h:19:7: error: 'BCM6348_CPU_ID' undeclared (first use in this function) make[7]: *** [drivers/mmc/core/cd-gpio.o] Error 1 Signed-off-by: Jonas Gorski Cc: stable@vger.kernel.org --- V1 -> V2 * added cc to stable This is also needed for all supported stable versions. The include is missing from the beginning, breaking any driver using linux/gpio.h (but they don't seem to be used often used on bcm63xx). arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 3d5de96..1d7dd96 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -2,6 +2,7 @@ #define BCM63XX_GPIO_H #include +#include int __init bcm63xx_gpio_init(void); -- 1.7.2.5 From broonie@opensource.wolfsonmicro.com Sat Feb 4 16:54:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 04 Feb 2012 16:54:59 +0100 (CET) Received: from opensource.wolfsonmicro.com ([80.75.67.52]:52410 "EHLO opensource.wolfsonmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903613Ab2BDPyx (ORCPT ); Sat, 4 Feb 2012 16:54:53 +0100 Received: from finisterre.wolfsonmicro.main (host86-159-130-17.range86-159.btcentralplus.com [86.159.130.17]) by opensource.wolfsonmicro.com (Postfix) with ESMTPSA id 64B5C1101E4; Sat, 4 Feb 2012 15:54:46 +0000 (GMT) Received: from broonie by finisterre.wolfsonmicro.main with local (Exim 4.77) (envelope-from ) id 1Rthwq-0004pJ-A2; Sat, 04 Feb 2012 15:54:44 +0000 From: Mark Brown To: Guan Xuetao , Russell King , Ralf Baechle , Paul Mundt , Geert Uytterhoeven , Mike Frysinger , Haavard Skinnemoen , Hans-Christian Egtvedt , Grant Likely Cc: linux-arch@vger.kernel.org, linux-mips@linux-mips.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, Mark Brown Subject: [PATCH] gpiolib/arches: Centralise bolierplate asm/gpio.h Date: Sat, 4 Feb 2012 15:54:39 +0000 Message-Id: <1328370879-18523-1-git-send-email-broonie@opensource.wolfsonmicro.com> X-Mailer: git-send-email 1.7.9.rc1 X-archive-position: 32405 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: broonie@opensource.wolfsonmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 17985 Lines: 694 Rather than requiring architectures that use gpiolib but don't have any need to define anything custom to copy an asm/gpio.h provide a Kconfig symbol which architectures must select in order to include gpio.h and for other architectures just provide the trivial implementation directly. This makes it much easier to do gpiolib updates and is also a step towards making gpiolib APIs available on every architecture. For architectures with existing boilerplate code leave a stub header in place which warns on direct inclusion of asm/gpio.h and includes linux/gpio.h to catch code that's doing this. Direct inclusion of asm/gpio.h has long been deprecated. Signed-off-by: Mark Brown --- Build tested on x86 which is one of the affected architectures. arch/alpha/include/asm/gpio.h | 59 ++---------------------------- arch/arm/Kconfig | 1 + arch/avr32/Kconfig | 1 + arch/blackfin/Kconfig | 1 + arch/ia64/include/asm/gpio.h | 59 ++---------------------------- arch/m68k/Kconfig.cpu | 1 + arch/microblaze/include/asm/gpio.h | 57 ++--------------------------- arch/mips/Kconfig | 1 + arch/openrisc/include/asm/gpio.h | 69 ++--------------------------------- arch/powerpc/include/asm/gpio.h | 57 ++--------------------------- arch/sh/Kconfig | 1 + arch/sparc/include/asm/gpio.h | 40 ++------------------- arch/unicore32/Kconfig | 1 + arch/x86/include/asm/gpio.h | 57 ++--------------------------- arch/xtensa/include/asm/gpio.h | 60 ++----------------------------- drivers/gpio/Kconfig | 8 ++++ include/linux/gpio.h | 34 +++++++++++++++++ 17 files changed, 81 insertions(+), 426 deletions(-) diff --git a/arch/alpha/include/asm/gpio.h b/arch/alpha/include/asm/gpio.h index 7dc6a63..b3799d8 100644 --- a/arch/alpha/include/asm/gpio.h +++ b/arch/alpha/include/asm/gpio.h @@ -1,55 +1,4 @@ -/* - * Generic GPIO API implementation for Alpha. - * - * A stright copy of that for PowerPC which was: - * - * Copyright (c) 2007-2008 MontaVista Software, Inc. - * - * Author: Anton Vorontsov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef _ASM_ALPHA_GPIO_H -#define _ASM_ALPHA_GPIO_H - -#include -#include - -#ifdef CONFIG_GPIOLIB - -/* - * We don't (yet) implement inlined/rapid versions for on-chip gpios. - * Just call gpiolib. - */ -static inline int gpio_get_value(unsigned int gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned int gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned int gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned int gpio) -{ - return __gpio_to_irq(gpio); -} - -static inline int irq_to_gpio(unsigned int irq) -{ - return -EINVAL; -} - -#endif /* CONFIG_GPIOLIB */ - -#endif /* _ASM_ALPHA_GPIO_H */ +#ifndef __LINUX_GPIO_H +#warning Include linux/gpio.h instead of asm/gpio.h +#include +#endif diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a48aecc..dcf4187 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1,6 +1,7 @@ config ARM bool default y + select ARCH_HAVE_CUSTOM_GPIO_H select HAVE_AOUT select HAVE_DMA_API_DEBUG select HAVE_IDE if PCI || ISA || PCMCIA diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index 197e96f..b2e3e58 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -10,6 +10,7 @@ config AVR32 select GENERIC_IRQ_PROBE select HARDIRQS_SW_RESEND select GENERIC_IRQ_SHOW + select ARCH_HAVE_CUSTOM_GPIO_H select ARCH_HAVE_NMI_SAFE_CMPXCHG help AVR32 is a high-performance 32-bit RISC microprocessor core, diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index abe5a9e..c45ecdc 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -31,6 +31,7 @@ config BLACKFIN select HAVE_KERNEL_LZO if RAMKERNEL select HAVE_OPROFILE select HAVE_PERF_EVENTS + select ARCH_HAVE_CUSTOM_GPIO_H select ARCH_WANT_OPTIONAL_GPIOLIB select HAVE_GENERIC_HARDIRQS select GENERIC_ATOMIC64 diff --git a/arch/ia64/include/asm/gpio.h b/arch/ia64/include/asm/gpio.h index 590a20d..b3799d8 100644 --- a/arch/ia64/include/asm/gpio.h +++ b/arch/ia64/include/asm/gpio.h @@ -1,55 +1,4 @@ -/* - * Generic GPIO API implementation for IA-64. - * - * A stright copy of that for PowerPC which was: - * - * Copyright (c) 2007-2008 MontaVista Software, Inc. - * - * Author: Anton Vorontsov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef _ASM_IA64_GPIO_H -#define _ASM_IA64_GPIO_H - -#include -#include - -#ifdef CONFIG_GPIOLIB - -/* - * We don't (yet) implement inlined/rapid versions for on-chip gpios. - * Just call gpiolib. - */ -static inline int gpio_get_value(unsigned int gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned int gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned int gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned int gpio) -{ - return __gpio_to_irq(gpio); -} - -static inline int irq_to_gpio(unsigned int irq) -{ - return -EINVAL; -} - -#endif /* CONFIG_GPIOLIB */ - -#endif /* _ASM_IA64_GPIO_H */ +#ifndef __LINUX_GPIO_H +#warning Include linux/gpio.h instead of asm/gpio.h +#include +#endif diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu index 8a9c767..8941af1 100644 --- a/arch/m68k/Kconfig.cpu +++ b/arch/m68k/Kconfig.cpu @@ -24,6 +24,7 @@ config COLDFIRE bool "Coldfire CPU family support" select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB + select ARCH_HAVE_CUSTOM_GPIO_H select CPU_HAS_NO_BITFIELDS select CPU_HAS_NO_MULDIV64 select GENERIC_CSUM diff --git a/arch/microblaze/include/asm/gpio.h b/arch/microblaze/include/asm/gpio.h index 2b2c18b..b3799d8 100644 --- a/arch/microblaze/include/asm/gpio.h +++ b/arch/microblaze/include/asm/gpio.h @@ -1,53 +1,4 @@ -/* - * Generic GPIO API implementation for PowerPC. - * - * Copyright (c) 2007-2008 MontaVista Software, Inc. - * - * Author: Anton Vorontsov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef _ASM_MICROBLAZE_GPIO_H -#define _ASM_MICROBLAZE_GPIO_H - -#include -#include - -#ifdef CONFIG_GPIOLIB - -/* - * We don't (yet) implement inlined/rapid versions for on-chip gpios. - * Just call gpiolib. - */ -static inline int gpio_get_value(unsigned int gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned int gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned int gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned int gpio) -{ - return __gpio_to_irq(gpio); -} - -static inline int irq_to_gpio(unsigned int irq) -{ - return -EINVAL; -} - -#endif /* CONFIG_GPIOLIB */ - -#endif /* _ASM_MICROBLAZE_GPIO_H */ +#ifndef __LINUX_GPIO_H +#warning Include linux/gpio.h instead of asm/gpio.h +#include +#endif diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c4c1312..4918404 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -8,6 +8,7 @@ config MIPS select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_ARCH_KGDB + select ARCH_HAVE_CUSTOM_GPIO_H select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_TRACE_MCOUNT_TEST select HAVE_DYNAMIC_FTRACE diff --git a/arch/openrisc/include/asm/gpio.h b/arch/openrisc/include/asm/gpio.h index 0b0d174..b3799d8 100644 --- a/arch/openrisc/include/asm/gpio.h +++ b/arch/openrisc/include/asm/gpio.h @@ -1,65 +1,4 @@ -/* - * OpenRISC Linux - * - * Linux architectural port borrowing liberally from similar works of - * others. All original copyrights apply as per the original source - * declaration. - * - * OpenRISC implementation: - * Copyright (C) 2003 Matjaz Breskvar - * Copyright (C) 2010-2011 Jonas Bonn - * et al. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __ASM_OPENRISC_GPIO_H -#define __ASM_OPENRISC_GPIO_H - -#include -#include - -#ifdef CONFIG_GPIOLIB - -/* - * OpenRISC (or1k) does not have on-chip GPIO's so there is not really - * any standardized implementation that makes sense here. If passing - * through gpiolib becomes a bottleneck then it may make sense, on a - * case-by-case basis, to implement these inlined/rapid versions. - * - * Just call gpiolib. - */ -static inline int gpio_get_value(unsigned int gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned int gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned int gpio) -{ - return __gpio_cansleep(gpio); -} - -/* - * Not implemented, yet. - */ -static inline int gpio_to_irq(unsigned int gpio) -{ - return -ENOSYS; -} - -static inline int irq_to_gpio(unsigned int irq) -{ - return -EINVAL; -} - -#endif /* CONFIG_GPIOLIB */ - -#endif /* __ASM_OPENRISC_GPIO_H */ +#ifndef __LINUX_GPIO_H +#warning Include linux/gpio.h instead of asm/gpio.h +#include +#endif diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h index 38762ed..b3799d8 100644 --- a/arch/powerpc/include/asm/gpio.h +++ b/arch/powerpc/include/asm/gpio.h @@ -1,53 +1,4 @@ -/* - * Generic GPIO API implementation for PowerPC. - * - * Copyright (c) 2007-2008 MontaVista Software, Inc. - * - * Author: Anton Vorontsov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __ASM_POWERPC_GPIO_H -#define __ASM_POWERPC_GPIO_H - -#include -#include - -#ifdef CONFIG_GPIOLIB - -/* - * We don't (yet) implement inlined/rapid versions for on-chip gpios. - * Just call gpiolib. - */ -static inline int gpio_get_value(unsigned int gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned int gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned int gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned int gpio) -{ - return __gpio_to_irq(gpio); -} - -static inline int irq_to_gpio(unsigned int irq) -{ - return -EINVAL; -} - -#endif /* CONFIG_GPIOLIB */ - -#endif /* __ASM_POWERPC_GPIO_H */ +#ifndef __LINUX_GPIO_H +#warning Include linux/gpio.h instead of asm/gpio.h +#include +#endif diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 3c8db65..f15181d 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -12,6 +12,7 @@ config SUPERH select HAVE_DMA_ATTRS select HAVE_IRQ_WORK select HAVE_PERF_EVENTS + select ARCH_HAVE_CUSTOM_GPIO_H select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A) select PERF_USE_VMALLOC select HAVE_KERNEL_GZIP diff --git a/arch/sparc/include/asm/gpio.h b/arch/sparc/include/asm/gpio.h index a0e3ac0..b3799d8 100644 --- a/arch/sparc/include/asm/gpio.h +++ b/arch/sparc/include/asm/gpio.h @@ -1,36 +1,4 @@ -#ifndef __ASM_SPARC_GPIO_H -#define __ASM_SPARC_GPIO_H - -#include -#include - -#ifdef CONFIG_GPIOLIB - -static inline int gpio_get_value(unsigned int gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned int gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned int gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned int gpio) -{ - return -ENOSYS; -} - -static inline int irq_to_gpio(unsigned int irq) -{ - return -EINVAL; -} - -#endif /* CONFIG_GPIOLIB */ - -#endif /* __ASM_SPARC_GPIO_H */ +#ifndef __LINUX_GPIO_H +#warning Include linux/gpio.h instead of asm/gpio.h +#include +#endif diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig index eeb8054..7ff6d10 100644 --- a/arch/unicore32/Kconfig +++ b/arch/unicore32/Kconfig @@ -8,6 +8,7 @@ config UNICORE32 select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_LZO select HAVE_KERNEL_LZMA + select ARCH_HAVE_CUSTOM_GPIO_H select GENERIC_FIND_FIRST_BIT select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 91d915a..b3799d8 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -1,53 +1,4 @@ -/* - * Generic GPIO API implementation for x86. - * - * Derived from the generic GPIO API for powerpc: - * - * Copyright (c) 2007-2008 MontaVista Software, Inc. - * - * Author: Anton Vorontsov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef _ASM_X86_GPIO_H -#define _ASM_X86_GPIO_H - -#include - -#ifdef CONFIG_GPIOLIB - -/* - * Just call gpiolib. - */ -static inline int gpio_get_value(unsigned int gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned int gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned int gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned int gpio) -{ - return __gpio_to_irq(gpio); -} - -static inline int irq_to_gpio(unsigned int irq) -{ - return -EINVAL; -} - -#endif /* CONFIG_GPIOLIB */ - -#endif /* _ASM_X86_GPIO_H */ +#ifndef __LINUX_GPIO_H +#warning Include linux/gpio.h instead of asm/gpio.h +#include +#endif diff --git a/arch/xtensa/include/asm/gpio.h b/arch/xtensa/include/asm/gpio.h index a8c9fc4..b3799d8 100644 --- a/arch/xtensa/include/asm/gpio.h +++ b/arch/xtensa/include/asm/gpio.h @@ -1,56 +1,4 @@ -/* - * Generic GPIO API implementation for xtensa. - * - * Stolen from x86, which is derived from the generic GPIO API for powerpc: - * - * Copyright (c) 2007-2008 MontaVista Software, Inc. - * - * Author: Anton Vorontsov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef _ASM_XTENSA_GPIO_H -#define _ASM_XTENSA_GPIO_H - -#include - -#ifdef CONFIG_GPIOLIB - -/* - * Just call gpiolib. - */ -static inline int gpio_get_value(unsigned int gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned int gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned int gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned int gpio) -{ - return __gpio_to_irq(gpio); -} - -/* - * Not implemented, yet. - */ -static inline int irq_to_gpio(unsigned int irq) -{ - return -EINVAL; -} - -#endif /* CONFIG_GPIOLIB */ - -#endif /* _ASM_XTENSA_GPIO_H */ +#ifndef __LINUX_GPIO_H +#warning Include linux/gpio.h instead of asm/gpio.h +#include +#endif diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d0c4118..81befc0 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -2,6 +2,14 @@ # GPIO infrastructure and drivers # +config ARCH_HAVE_CUSTOM_GPIO_H + bool + help + Selecting this config option from the architecture Kconfig allows + the architecture to provide a custom asm/gpio.h implementation + overriding the default implementations. New uses of this are + strongly discouraged. + config ARCH_WANT_OPTIONAL_GPIOLIB bool help diff --git a/include/linux/gpio.h b/include/linux/gpio.h index 38ac48b..3149f68 100644 --- a/include/linux/gpio.h +++ b/include/linux/gpio.h @@ -1,6 +1,8 @@ #ifndef __LINUX_GPIO_H #define __LINUX_GPIO_H +#include + /* see Documentation/gpio.txt */ /* make these flag values available regardless of GPIO kconfig options */ @@ -27,7 +29,39 @@ struct gpio { }; #ifdef CONFIG_GENERIC_GPIO + +#ifdef CONFIG_ARCH_HAVE_CUSTOM_GPIO_H #include +#else + +#include + +static inline int gpio_get_value(unsigned int gpio) +{ + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned int gpio, int value) +{ + __gpio_set_value(gpio, value); +} + +static inline int gpio_cansleep(unsigned int gpio) +{ + return __gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned int gpio) +{ + return __gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned int irq) +{ + return -EINVAL; +} + +#endif #else -- 1.7.9.rc1 From sam@ravnborg.org Sat Feb 4 18:06:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 04 Feb 2012 18:06:44 +0100 (CET) Received: from smtp.snhosting.dk ([87.238.248.203]:31167 "EHLO smtp.domainteam.dk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903615Ab2BDRGj (ORCPT ); Sat, 4 Feb 2012 18:06:39 +0100 Received: from merkur.ravnborg.org (unknown [188.228.89.252]) by smtp.domainteam.dk (Postfix) with ESMTPA id 11E3FF18D1; Sat, 4 Feb 2012 18:06:33 +0100 (CET) Date: Sat, 4 Feb 2012 18:06:32 +0100 From: Sam Ravnborg To: Mark Brown Cc: Guan Xuetao , Russell King , Ralf Baechle , Paul Mundt , Geert Uytterhoeven , Mike Frysinger , Haavard Skinnemoen , Hans-Christian Egtvedt , Grant Likely , linux-arch@vger.kernel.org, linux-mips@linux-mips.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org Subject: Re: [PATCH] gpiolib/arches: Centralise bolierplate asm/gpio.h Message-ID: <20120204170632.GA3615@merkur.ravnborg.org> References: <1328370879-18523-1-git-send-email-broonie@opensource.wolfsonmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1328370879-18523-1-git-send-email-broonie@opensource.wolfsonmicro.com> User-Agent: Mutt/1.5.18 (2008-05-17) X-archive-position: 32406 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 793 Lines: 25 On Sat, Feb 04, 2012 at 03:54:39PM +0000, Mark Brown wrote: > Rather than requiring architectures that use gpiolib but don't have any > need to define anything custom to copy an asm/gpio.h provide a Kconfig > symbol which architectures must select in order to include gpio.h and > for other architectures just provide the trivial implementation directly. Hi Mark. There is an even simpler solution. For each arch that uses asm-generic/gpio.h add a line to arch/$ARCH/include/asm/Kbuild like this: generic-y += gpio.h This will then make this arch pick up the asm-generic version when you do #include . And you avoid the kconfig games. iFor the archs which require their own asm/gpio.h file - just add it to the asm/ dir - and do not add the generic-y assignment. Sam From broonie@opensource.wolfsonmicro.com Sat Feb 4 18:21:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 04 Feb 2012 18:21:32 +0100 (CET) Received: from opensource.wolfsonmicro.com ([80.75.67.52]:59340 "EHLO opensource.wolfsonmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903615Ab2BDRV2 (ORCPT ); Sat, 4 Feb 2012 18:21:28 +0100 Received: from finisterre.wolfsonmicro.main (host86-159-130-17.range86-159.btcentralplus.com [86.159.130.17]) by opensource.wolfsonmicro.com (Postfix) with ESMTPSA id 2B01C1104A0; Sat, 4 Feb 2012 17:21:22 +0000 (GMT) Received: from broonie by finisterre.wolfsonmicro.main with local (Exim 4.77) (envelope-from ) id 1RtjIe-0002b8-1i; Sat, 04 Feb 2012 17:21:20 +0000 Date: Sat, 4 Feb 2012 17:21:19 +0000 From: Mark Brown To: Sam Ravnborg Cc: Guan Xuetao , Russell King , Ralf Baechle , Paul Mundt , Geert Uytterhoeven , Mike Frysinger , Haavard Skinnemoen , Hans-Christian Egtvedt , Grant Likely , linux-arch@vger.kernel.org, linux-mips@linux-mips.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org Subject: Re: [PATCH] gpiolib/arches: Centralise bolierplate asm/gpio.h Message-ID: <20120204172119.GF8042@opensource.wolfsonmicro.com> References: <1328370879-18523-1-git-send-email-broonie@opensource.wolfsonmicro.com> <20120204170632.GA3615@merkur.ravnborg.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="bGR76rFJjkSxVeRa" Content-Disposition: inline In-Reply-To: <20120204170632.GA3615@merkur.ravnborg.org> X-Cookie: You will be married within a year. User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32407 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: broonie@opensource.wolfsonmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1718 Lines: 47 --bGR76rFJjkSxVeRa Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Feb 04, 2012 at 06:06:32PM +0100, Sam Ravnborg wrote: > There is an even simpler solution. > For each arch that uses asm-generic/gpio.h add a line > to arch/$ARCH/include/asm/Kbuild like this: > generic-y += gpio.h > This will then make this arch pick up the asm-generic version when > you do #include . > And you avoid the kconfig games. Hrm, that would work but it does mean we still need to go round and manually enable GPIO support on all architectures which is what I had been trying to get away from. It is a lot simpler though so it should be much easier to persuade the architecture maintainers to do that. --bGR76rFJjkSxVeRa Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJPLWkJAAoJEBus8iNuMP3dTScP/i6Yc7ptakuyKbKi5j+iVa1s i6ySBMtkLmgcj1bHdwDBjfFp93c7IMqhKRXFNw4zYcud5dOkOPLEMajOQhv1Tlag Mdc1QNjxW7DFCLYAwcWi3aMrWRglq+fYz0iqz+EhMeDstFK3kZLYpDPyYH8dAGSY uifbi4XIil4sLtWvKy8WDcccxhOAdZt443XatGY6VekmsiNBvEvbrW27cQbR6QOV Zw21nrqMIHF1t2MWsMWCFpQX5ZAeg4CFb/E3csaKWwc0QE6f717P/28TQUO704L1 Gvv8Jpt4cpxTJkd590jW2VVg9mCWTi2DynTBMEO0yyvtwIGtK2NeFjwZTi5Nqgh2 0bihITOW3xTYaJYDnpydNI1tpIr+mqxlEi8WDEnnCdB5T9MUPSmB0QdVJyoTO2eg tBghAVG1YyjVamsRtZAnMO70ysEsphvQK+h086z8+8veyzl76+iMQryr8onRYO9O gzqD7NZyT2/c+XKBnwOrDbBUWho3HmZtMp2maoYwOwX+Eg6pXA/QoRBvMadReY+D BvoCgXpT1R2YPfsTE4SOerW911chlqkwwgR/5NPOMieIY3z3L/ITNVzC61A5JajU r1tzEwzhRwSNUPNZcMx1lPsXq72WvJbA3jH4yJ+XF37xpITVDp9x5WDkFET72CAp nrOiab4BJ8JUs/fRUlTM =oVcL -----END PGP SIGNATURE----- --bGR76rFJjkSxVeRa-- From linux@arm.linux.org.uk Sat Feb 4 18:42:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 04 Feb 2012 18:42:19 +0100 (CET) Received: from caramon.arm.linux.org.uk ([78.32.30.218]:34917 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903613Ab2BDRmN (ORCPT ); Sat, 4 Feb 2012 18:42:13 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=caramon; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=v+sk/DkWDb4m0c2kbhSCAjLrgnicRmt4XWIw3Cha6I4=; b=ANouVT5pWWW5o4+G+bE58/dXIU3e78jVVI02z6gapi+QDTddfgi1RO2xpzlsKIHLO8D6R0hrfZTlmH5W/K1XWriH4B69orq6zRWAAAY14JK3QsL8/HIahVGrxh9Ep9FAFoElHDiX0chMAFPiK5cZ2z2QyB5tAJKClDlCM1m9Nxc=; Received: from n2100.arm.linux.org.uk ([2002:4e20:1eda:1:214:fdff:fe10:4f86]:56925) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1Rtjbx-00032m-K9; Sat, 04 Feb 2012 17:41:18 +0000 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1Rtjbw-0004qP-4b; Sat, 04 Feb 2012 17:41:16 +0000 Date: Sat, 4 Feb 2012 17:41:15 +0000 From: Russell King - ARM Linux To: Sam Ravnborg Cc: Mark Brown , Guan Xuetao , Ralf Baechle , Paul Mundt , Geert Uytterhoeven , Mike Frysinger , Haavard Skinnemoen , Hans-Christian Egtvedt , Grant Likely , linux-arch@vger.kernel.org, linux-mips@linux-mips.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org Subject: Re: [PATCH] gpiolib/arches: Centralise bolierplate asm/gpio.h Message-ID: <20120204174115.GX889@n2100.arm.linux.org.uk> References: <1328370879-18523-1-git-send-email-broonie@opensource.wolfsonmicro.com> <20120204170632.GA3615@merkur.ravnborg.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120204170632.GA3615@merkur.ravnborg.org> User-Agent: Mutt/1.5.19 (2009-01-05) X-archive-position: 32408 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux@arm.linux.org.uk Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1901 Lines: 49 On Sat, Feb 04, 2012 at 06:06:32PM +0100, Sam Ravnborg wrote: > On Sat, Feb 04, 2012 at 03:54:39PM +0000, Mark Brown wrote: > > Rather than requiring architectures that use gpiolib but don't have any > > need to define anything custom to copy an asm/gpio.h provide a Kconfig > > symbol which architectures must select in order to include gpio.h and > > for other architectures just provide the trivial implementation directly. > > Hi Mark. > > There is an even simpler solution. > > For each arch that uses asm-generic/gpio.h add a line > to arch/$ARCH/include/asm/Kbuild like this: > > > generic-y += gpio.h > > This will then make this arch pick up the asm-generic version when > you do #include . You're assuming that asm-generic/gpio.h was invented to be a replacement for an architecture asm/gpio.h. Unfortunately, things aren't that simple. It would have been a lot better if asm-generic/gpio.h was tacked on the bottom of linux/gpio.h - because that's what it really is. It's core code features, not platform stuff. What's platform specific about asm/gpio.h is the number of GPIOs in the system, and whether it wants to intercept the gpio_xxx() functions to provide fast access to on-chip GPIOs. What I'd suggest is moving asm-generic/gpio.h to linux/gpiolib.h, and making asm-generic/gpio.h include that as a patch until stuff is fixed for its new location. That should result in a proper asm-generic/gpio.h being: /* The trivial gpiolib dispatchers */ #define gpio_get_value __gpio_get_value #define gpio_set_value __gpio_set_value #define gpio_cansleep __gpio_cansleep #define gpio_to_irq __gpio_to_irq and nothing else. Alternatively, instead of linux/gpiolib.h, put it in linux/gpio.h instead, but that gets more icky because of the mess of asm/gpio.h includes (which I've been banging on for years about in ARM patches and they're _still_ coming.) From broonie@opensource.wolfsonmicro.com Mon Feb 6 12:37:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Feb 2012 12:37:38 +0100 (CET) Received: from opensource.wolfsonmicro.com ([80.75.67.52]:54747 "EHLO opensource.wolfsonmicro.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903649Ab2BFLh1 (ORCPT ); Mon, 6 Feb 2012 12:37:27 +0100 Received: from finisterre.wolfsonmicro.main (unknown [87.246.78.26]) by opensource.wolfsonmicro.com (Postfix) with ESMTPSA id E7672110520; Mon, 6 Feb 2012 11:37:20 +0000 (GMT) Received: from broonie by finisterre.wolfsonmicro.main with local (Exim 4.77) (envelope-from ) id 1RuMsq-0005Pn-AK; Mon, 06 Feb 2012 11:37:20 +0000 Date: Mon, 6 Feb 2012 11:37:20 +0000 From: Mark Brown To: Russell King - ARM Linux Cc: Sam Ravnborg , Guan Xuetao , Ralf Baechle , Paul Mundt , Geert Uytterhoeven , Mike Frysinger , Haavard Skinnemoen , Hans-Christian Egtvedt , Grant Likely , linux-arch@vger.kernel.org, linux-mips@linux-mips.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org Subject: Re: [PATCH] gpiolib/arches: Centralise bolierplate asm/gpio.h Message-ID: <20120206113720.GG3070@opensource.wolfsonmicro.com> References: <1328370879-18523-1-git-send-email-broonie@opensource.wolfsonmicro.com> <20120204170632.GA3615@merkur.ravnborg.org> <20120204174115.GX889@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="PpAOPzA3dXsRhoo+" Content-Disposition: inline In-Reply-To: <20120204174115.GX889@n2100.arm.linux.org.uk> X-Cookie: Many pages make a thick book. User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32409 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: broonie@opensource.wolfsonmicro.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2168 Lines: 52 --PpAOPzA3dXsRhoo+ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Feb 04, 2012 at 05:41:15PM +0000, Russell King - ARM Linux wrote: > What's platform specific about asm/gpio.h is the number of GPIOs in > the system, and whether it wants to intercept the gpio_xxx() functions > to provide fast access to on-chip GPIOs. Plus the fact that it might be a completely non-standard API, and might totally override the gpiolib implementation. > What I'd suggest is moving asm-generic/gpio.h to linux/gpiolib.h, and > making asm-generic/gpio.h include that as a patch until stuff is fixed > for its new location. That should result in a proper asm-generic/gpio.h > being: > Alternatively, instead of linux/gpiolib.h, put it in linux/gpio.h instead, > but that gets more icky because of the mess of asm/gpio.h includes (which > I've been banging on for years about in ARM patches and they're _still_ > coming.) Yeah, though it is a bit neater if it's all in gpio.h and everyone is using gpiolib. Perhaps something like the warnings I added on inclusion of asm/gpio.h without linux/gpio.h would help, though I certainly wouldn't expect it to solve anything. --PpAOPzA3dXsRhoo+ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJPL7tpAAoJEBus8iNuMP3d12YQAJa6Z9EArDWj12yuaVLeGewd 3nUgd+GTaayJJo+I47NOMHevebKyErQd/y68c3YWmVXZdOi0kKZCLEupFGh1jf5B V5EphiOXY06SsHqrQXy67US1Mpf4ms2MQozBkvCEkZoF2LkwdOoZj9TCutnwquQs UD7SkQ0QQaIRehc5Y4+XM7KseFcCmyvK/mqEnRGfE9xNIln2JeStF3yifdjXeOzj +6cHi9pN5Tw25mVARelZZmx7vCA9rAoNC8tVNWet9GtOWNRiEVbBlGoNeukeMdUT iYgPCeX/IOYBivJiULQijvOMAG0FfNr3DmrAGVgeSGPRPRILX53RaqsVDXT74zme CFFuz3BhtGpE8WkjiLAPNd84I8IGsvKgQKX/KQhatUbxjf7HvfAauJ2YxFEpjNps 5UDmO5MfgsEAZ0zZXPfi67/kXjuhkPJ4PzYiwIE9MvWjLlWdEhEqmrPYVVjRwge8 nZR2P9oJRMj5k5pQ1gwe37fgabFwXe09JR1K4yKT5rpaiihiEX2HfU9I8Gm5kJGY +TQv44fnozuKj+i6SSgiDK2ljrnlZMAO8XCSemKOHtSoi67Wx40QOzw87QBMGw6H p5MDrmcw6Z1J65uXiJJTzf+FSkVc99RogMEL8nhIROIVv91TxR17/m1QPRMiVzvM WyCUwqMjTqqMAqum/gOz =ZpPo -----END PGP SIGNATURE----- --PpAOPzA3dXsRhoo+-- From mst@redhat.com Tue Feb 7 07:59:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Feb 2012 07:59:44 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:9162 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903684Ab2BGG7d (ORCPT ); Tue, 7 Feb 2012 07:59:33 +0100 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q176xNKV004556 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 7 Feb 2012 01:59:24 -0500 Received: from redhat.com (vpn-203-175.tlv.redhat.com [10.35.203.175]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id q176xF17030728; Tue, 7 Feb 2012 01:59:16 -0500 Date: Tue, 7 Feb 2012 08:59:18 +0200 From: "Michael S. Tsirkin" To: Linus Torvalds Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Arnd Bergmann , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [GIT PULL] fixups for generic pci_iomap Message-ID: <20120207065917.GA24577@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-archive-position: 32410 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1718 Lines: 47 The following changes since commit 0a9626575400879d1d5e6bc8768188b938d7c501: Merge tag 'driver-core-3.3-rc1-bugfixes' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core (2012-01-28 18:20:48 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git for-linus for you to fetch changes up to 1e05b62ae4bd4c1209229de367b0989b39644f88: sh: use the the PCI channels's io_map_base (2012-01-31 23:21:19 +0200) These changes have been on linux-next for a couple of weeks, I have also tested them on x86 and built on sh and mips. ---------------------------------------------------------------- arch: fix ioport mapping on mips,sh Kevin Cernekee reported that recent cleanup that replaced pci_iomap with a generic function failed to take into account the differences in io port handling on mips and sh architectures. Rather than revert the changes reintroducing the code duplication, this patchset fixes this by adding ability for architectures to override ioport mapping for pci devices. Signed-off-by: Michael S. Tsirkin ---------------------------------------------------------------- Michael S. Tsirkin (3): lib: add NO_GENERIC_PCI_IOPORT_MAP mips: use the the PCI controller's io_map_base sh: use the the PCI channels's io_map_base arch/mips/Kconfig | 1 + arch/mips/lib/iomap-pci.c | 4 ++-- arch/sh/Kconfig | 1 + arch/sh/drivers/pci/pci.c | 4 ++-- include/asm-generic/pci_iomap.h | 10 ++++++++++ lib/Kconfig | 3 +++ lib/pci_iomap.c | 2 +- 7 files changed, 20 insertions(+), 5 deletions(-) -- MST From standby24x7@gmail.com Wed Feb 8 13:53:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Feb 2012 13:54:00 +0100 (CET) Received: from i118-21-156-233.s30.a048.ap.plala.or.jp ([118.21.156.233]:52827 "EHLO rinabert.homeip.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903687Ab2BHMxx (ORCPT ); Wed, 8 Feb 2012 13:53:53 +0100 Received: from rinabert.homeip.net (localhost [127.0.0.1]) by rinabert.homeip.net (8.14.5/8.14.5) with ESMTP id q18Crgvi002574; Wed, 8 Feb 2012 21:53:43 +0900 Received: (from iida@localhost) by rinabert.homeip.net (8.14.5/8.14.5/Submit) id q18CrVXx002567; Wed, 8 Feb 2012 21:53:31 +0900 From: Masanari Iida To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: trivial@kernel.org, linux-kernel@vger.kernel.org, standby24x7@gmail.com Subject: [PATCH] [trivial] mips: Fix typo in traps.c Date: Wed, 8 Feb 2012 21:53:14 +0900 Message-Id: <1328705594-2533-1-git-send-email-standby24x7@gmail.com> X-Mailer: git-send-email 1.7.6.5 X-archive-position: 32411 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: standby24x7@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6433 Content-Length: 735 Lines: 24 Correct spelling "Schedulier" to "Scheduler" in arch/mips/kernel/traps.c Signed-off-by: Masanari Iida --- arch/mips/kernel/traps.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index cc4a3f1..d79ae54 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1135,7 +1135,7 @@ asmlinkage void do_mt(struct pt_regs *regs) printk(KERN_DEBUG "YIELD Scheduler Exception\n"); break; case 5: - printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); + printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); break; default: printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", -- 1.7.6.5 From ralf@linux-mips.org Wed Feb 8 15:50:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Feb 2012 15:50:35 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:49425 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1904225Ab2BHOuY (ORCPT ); Wed, 8 Feb 2012 15:50:24 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q18EoF12012640; Wed, 8 Feb 2012 15:50:15 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q18EoA3h012636; Wed, 8 Feb 2012 15:50:10 +0100 Date: Wed, 8 Feb 2012 15:50:10 +0100 From: Ralf Baechle To: Masanari Iida Cc: linux-mips@linux-mips.org, trivial@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] [trivial] mips: Fix typo in traps.c Message-ID: <20120208145009.GA11213@linux-mips.org> References: <1328705594-2533-1-git-send-email-standby24x7@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1328705594-2533-1-git-send-email-standby24x7@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32412 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6513 Content-Length: 25 Lines: 3 Thanks, applied. Ralf From amwang@redhat.com Fri Feb 10 06:41:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Feb 2012 06:41:50 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:16731 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903258Ab2BJFll (ORCPT ); Fri, 10 Feb 2012 06:41:41 +0100 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q1A5fTiF031052 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 10 Feb 2012 00:41:29 -0500 Received: from cr0.redhat.com (vpn-244-44.nrt.redhat.com [10.64.244.44]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id q1A5eVkW021917; Fri, 10 Feb 2012 00:41:22 -0500 From: Cong Wang To: linux-kernel@vger.kernel.org Cc: Andrew Morton , Cong Wang , Ralf Baechle , Jayachandran C , "David S. Miller" , Jiri Kosina , Kevin Cernekee , David Daney , Peter Zijlstra , linux-mips@linux-mips.org Subject: [PATCH 04/60] mips: remove the second argument of k[un]map_atomic() Date: Fri, 10 Feb 2012 13:39:25 +0800 Message-Id: <1328852421-19678-5-git-send-email-amwang@redhat.com> In-Reply-To: <1328852421-19678-1-git-send-email-amwang@redhat.com> References: <1328852421-19678-1-git-send-email-amwang@redhat.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-archive-position: 32413 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: amwang@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1714 Lines: 61 Signed-off-by: Cong Wang --- arch/mips/mm/c-r4k.c | 4 ++-- arch/mips/mm/init.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 4f9eb0b..c97087d 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -498,7 +498,7 @@ static inline void local_r4k_flush_cache_page(void *args) if (map_coherent) vaddr = kmap_coherent(page, addr); else - vaddr = kmap_atomic(page, KM_USER0); + vaddr = kmap_atomic(page); addr = (unsigned long)vaddr; } @@ -521,7 +521,7 @@ static inline void local_r4k_flush_cache_page(void *args) if (map_coherent) kunmap_coherent(); else - kunmap_atomic(vaddr, KM_USER0); + kunmap_atomic(vaddr); } } diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 3b3ffd4..1a85ba9 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -207,21 +207,21 @@ void copy_user_highpage(struct page *to, struct page *from, { void *vfrom, *vto; - vto = kmap_atomic(to, KM_USER1); + vto = kmap_atomic(to); if (cpu_has_dc_aliases && page_mapped(from) && !Page_dcache_dirty(from)) { vfrom = kmap_coherent(from, vaddr); copy_page(vto, vfrom); kunmap_coherent(); } else { - vfrom = kmap_atomic(from, KM_USER0); + vfrom = kmap_atomic(from); copy_page(vto, vfrom); - kunmap_atomic(vfrom, KM_USER0); + kunmap_atomic(vfrom); } if ((!cpu_has_ic_fills_f_dc) || pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) flush_data_cache_page((unsigned long)vto); - kunmap_atomic(vto, KM_USER1); + kunmap_atomic(vto); /* Make sure this page is cleared on other CPU's too before using it */ smp_wmb(); } -- 1.7.7.6 From amwang@redhat.com Fri Feb 10 06:49:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Feb 2012 06:49:35 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:34606 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903545Ab2BJFt2 (ORCPT ); Fri, 10 Feb 2012 06:49:28 +0100 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q1A5mxLF032714 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 10 Feb 2012 00:49:00 -0500 Received: from cr0.redhat.com (vpn-244-44.nrt.redhat.com [10.64.244.44]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id q1A5eVlR021917; Fri, 10 Feb 2012 00:48:44 -0500 From: Cong Wang To: linux-kernel@vger.kernel.org Cc: Andrew Morton , Cong Wang , Stephen Warren , Russell King , David Howells , Ralf Baechle , Koichi Yasutake , Kyle McMartin , Helge Deller , "James E.J. Bottomley" , Benjamin Herrenschmidt , Paul Mackerras , "David S. Miller" , Chris Metcalf , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Nicolas Pitre , James Bottomley , Paul Gortmaker , Konrad Rzeszutek Wilk , linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, sparclinux@vger.kernel.org Subject: [PATCH 59/60] highmem: kill all __kmap_atomic() [swarren@nvidia.com: highmem: Fix ARM build break due to __kmap_atomic rename] Date: Fri, 10 Feb 2012 13:40:20 +0800 Message-Id: <1328852421-19678-60-git-send-email-amwang@redhat.com> In-Reply-To: <1328852421-19678-1-git-send-email-amwang@redhat.com> References: <1328852421-19678-1-git-send-email-amwang@redhat.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-archive-position: 32414 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: amwang@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9916 Lines: 302 Signed-off-by: Stephen Warren Signed-off-by: Cong Wang --- arch/arm/include/asm/highmem.h | 2 +- arch/arm/mm/highmem.c | 4 ++-- arch/frv/include/asm/highmem.h | 2 +- arch/frv/mm/highmem.c | 4 ++-- arch/mips/include/asm/highmem.h | 2 +- arch/mips/mm/highmem.c | 4 ++-- arch/mn10300/include/asm/highmem.h | 2 +- arch/parisc/include/asm/cacheflush.h | 2 +- arch/powerpc/include/asm/highmem.h | 2 +- arch/sparc/include/asm/highmem.h | 2 +- arch/sparc/mm/highmem.c | 4 ++-- arch/tile/include/asm/highmem.h | 2 +- arch/tile/mm/highmem.c | 4 ++-- arch/x86/include/asm/highmem.h | 2 +- arch/x86/mm/highmem_32.c | 4 ++-- include/linux/highmem.h | 11 +++-------- 16 files changed, 24 insertions(+), 29 deletions(-) diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h index a4edd19..8c5e828 100644 --- a/arch/arm/include/asm/highmem.h +++ b/arch/arm/include/asm/highmem.h @@ -57,7 +57,7 @@ static inline void *kmap_high_get(struct page *page) #ifdef CONFIG_HIGHMEM extern void *kmap(struct page *page); extern void kunmap(struct page *page); -extern void *__kmap_atomic(struct page *page); +extern void *kmap_atomic(struct page *page); extern void __kunmap_atomic(void *kvaddr); extern void *kmap_atomic_pfn(unsigned long pfn); extern struct page *kmap_atomic_to_page(const void *ptr); diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c index 807c057..5a21505 100644 --- a/arch/arm/mm/highmem.c +++ b/arch/arm/mm/highmem.c @@ -36,7 +36,7 @@ void kunmap(struct page *page) } EXPORT_SYMBOL(kunmap); -void *__kmap_atomic(struct page *page) +void *kmap_atomic(struct page *page) { unsigned int idx; unsigned long vaddr; @@ -81,7 +81,7 @@ void *__kmap_atomic(struct page *page) return (void *)vaddr; } -EXPORT_SYMBOL(__kmap_atomic); +EXPORT_SYMBOL(kmap_atomic); void __kunmap_atomic(void *kvaddr) { diff --git a/arch/frv/include/asm/highmem.h b/arch/frv/include/asm/highmem.h index a8d6565..716956a 100644 --- a/arch/frv/include/asm/highmem.h +++ b/arch/frv/include/asm/highmem.h @@ -157,7 +157,7 @@ static inline void kunmap_atomic_primary(void *kvaddr, enum km_type type) pagefault_enable(); } -void *__kmap_atomic(struct page *page); +void *kmap_atomic(struct page *page); void __kunmap_atomic(void *kvaddr); #endif /* !__ASSEMBLY__ */ diff --git a/arch/frv/mm/highmem.c b/arch/frv/mm/highmem.c index fd7fcd4..31902c9 100644 --- a/arch/frv/mm/highmem.c +++ b/arch/frv/mm/highmem.c @@ -37,7 +37,7 @@ struct page *kmap_atomic_to_page(void *ptr) return virt_to_page(ptr); } -void *__kmap_atomic(struct page *page) +void *kmap_atomic(struct page *page) { unsigned long paddr; int type; @@ -64,7 +64,7 @@ void *__kmap_atomic(struct page *page) return NULL; } } -EXPORT_SYMBOL(__kmap_atomic); +EXPORT_SYMBOL(kmap_atomic); void __kunmap_atomic(void *kvaddr) { diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h index 77e6440..2d91888 100644 --- a/arch/mips/include/asm/highmem.h +++ b/arch/mips/include/asm/highmem.h @@ -47,7 +47,7 @@ extern void kunmap_high(struct page *page); extern void *kmap(struct page *page); extern void kunmap(struct page *page); -extern void *__kmap_atomic(struct page *page); +extern void *kmap_atomic(struct page *page); extern void __kunmap_atomic(void *kvaddr); extern void *kmap_atomic_pfn(unsigned long pfn); extern struct page *kmap_atomic_to_page(void *ptr); diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c index 3634c7e..aff5705 100644 --- a/arch/mips/mm/highmem.c +++ b/arch/mips/mm/highmem.c @@ -41,7 +41,7 @@ EXPORT_SYMBOL(kunmap); * kmaps are appropriate for short, tight code paths only. */ -void *__kmap_atomic(struct page *page) +void *kmap_atomic(struct page *page) { unsigned long vaddr; int idx, type; @@ -62,7 +62,7 @@ void *__kmap_atomic(struct page *page) return (void*) vaddr; } -EXPORT_SYMBOL(__kmap_atomic); +EXPORT_SYMBOL(kmap_atomic); void __kunmap_atomic(void *kvaddr) { diff --git a/arch/mn10300/include/asm/highmem.h b/arch/mn10300/include/asm/highmem.h index bfe2d88..7c137cd 100644 --- a/arch/mn10300/include/asm/highmem.h +++ b/arch/mn10300/include/asm/highmem.h @@ -70,7 +70,7 @@ static inline void kunmap(struct page *page) * be used in IRQ contexts, so in some (very limited) cases we need * it. */ -static inline unsigned long __kmap_atomic(struct page *page) +static inline unsigned long kmap_atomic(struct page *page) { unsigned long vaddr; int idx, type; diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h index da601dd..9f21ab0 100644 --- a/arch/parisc/include/asm/cacheflush.h +++ b/arch/parisc/include/asm/cacheflush.h @@ -140,7 +140,7 @@ static inline void *kmap(struct page *page) #define kunmap(page) kunmap_parisc(page_address(page)) -static inline void *__kmap_atomic(struct page *page) +static inline void *kmap_atomic(struct page *page) { pagefault_disable(); return page_address(page); diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h index dbc2640..caaf6e0 100644 --- a/arch/powerpc/include/asm/highmem.h +++ b/arch/powerpc/include/asm/highmem.h @@ -79,7 +79,7 @@ static inline void kunmap(struct page *page) kunmap_high(page); } -static inline void *__kmap_atomic(struct page *page) +static inline void *kmap_atomic(struct page *page) { return kmap_atomic_prot(page, kmap_prot); } diff --git a/arch/sparc/include/asm/highmem.h b/arch/sparc/include/asm/highmem.h index 3d7afbb..3b6e00d 100644 --- a/arch/sparc/include/asm/highmem.h +++ b/arch/sparc/include/asm/highmem.h @@ -70,7 +70,7 @@ static inline void kunmap(struct page *page) kunmap_high(page); } -extern void *__kmap_atomic(struct page *page); +extern void *kmap_atomic(struct page *page); extern void __kunmap_atomic(void *kvaddr); extern struct page *kmap_atomic_to_page(void *vaddr); diff --git a/arch/sparc/mm/highmem.c b/arch/sparc/mm/highmem.c index 77140a0..055c66c 100644 --- a/arch/sparc/mm/highmem.c +++ b/arch/sparc/mm/highmem.c @@ -30,7 +30,7 @@ #include #include -void *__kmap_atomic(struct page *page) +void *kmap_atomic(struct page *page) { unsigned long vaddr; long idx, type; @@ -64,7 +64,7 @@ void *__kmap_atomic(struct page *page) return (void*) vaddr; } -EXPORT_SYMBOL(__kmap_atomic); +EXPORT_SYMBOL(kmap_atomic); void __kunmap_atomic(void *kvaddr) { diff --git a/arch/tile/include/asm/highmem.h b/arch/tile/include/asm/highmem.h index b2a6c5d..fc8429a 100644 --- a/arch/tile/include/asm/highmem.h +++ b/arch/tile/include/asm/highmem.h @@ -59,7 +59,7 @@ void *kmap_fix_kpte(struct page *page, int finished); /* This macro is used only in map_new_virtual() to map "page". */ #define kmap_prot page_to_kpgprot(page) -void *__kmap_atomic(struct page *page); +void *kmap_atomic(struct page *page); void __kunmap_atomic(void *kvaddr); void *kmap_atomic_pfn(unsigned long pfn); void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot); diff --git a/arch/tile/mm/highmem.c b/arch/tile/mm/highmem.c index 31dbbd9..ef8e5a6 100644 --- a/arch/tile/mm/highmem.c +++ b/arch/tile/mm/highmem.c @@ -224,12 +224,12 @@ void *kmap_atomic_prot(struct page *page, pgprot_t prot) } EXPORT_SYMBOL(kmap_atomic_prot); -void *__kmap_atomic(struct page *page) +void *kmap_atomic(struct page *page) { /* PAGE_NONE is a magic value that tells us to check immutability. */ return kmap_atomic_prot(page, PAGE_NONE); } -EXPORT_SYMBOL(__kmap_atomic); +EXPORT_SYMBOL(kmap_atomic); void __kunmap_atomic(void *kvaddr) { diff --git a/arch/x86/include/asm/highmem.h b/arch/x86/include/asm/highmem.h index 3bd0402..302a323 100644 --- a/arch/x86/include/asm/highmem.h +++ b/arch/x86/include/asm/highmem.h @@ -61,7 +61,7 @@ void *kmap(struct page *page); void kunmap(struct page *page); void *kmap_atomic_prot(struct page *page, pgprot_t prot); -void *__kmap_atomic(struct page *page); +void *kmap_atomic(struct page *page); void __kunmap_atomic(void *kvaddr); void *kmap_atomic_pfn(unsigned long pfn); void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot); diff --git a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c index f4f29b1..6f31ee5 100644 --- a/arch/x86/mm/highmem_32.c +++ b/arch/x86/mm/highmem_32.c @@ -51,11 +51,11 @@ void *kmap_atomic_prot(struct page *page, pgprot_t prot) } EXPORT_SYMBOL(kmap_atomic_prot); -void *__kmap_atomic(struct page *page) +void *kmap_atomic(struct page *page) { return kmap_atomic_prot(page, kmap_prot); } -EXPORT_SYMBOL(__kmap_atomic); +EXPORT_SYMBOL(kmap_atomic); /* * This is the same as kmap_atomic() but can map memory that doesn't diff --git a/include/linux/highmem.h b/include/linux/highmem.h index 284ec55..6549ed7 100644 --- a/include/linux/highmem.h +++ b/include/linux/highmem.h @@ -55,12 +55,12 @@ static inline void kunmap(struct page *page) { } -static inline void *__kmap_atomic(struct page *page) +static inline void *kmap_atomic(struct page *page) { pagefault_disable(); return page_address(page); } -#define kmap_atomic_prot(page, prot) __kmap_atomic(page) +#define kmap_atomic_prot(page, prot) kmap_atomic(page) static inline void __kunmap_atomic(void *addr) { @@ -121,15 +121,10 @@ static inline void kmap_atomic_idx_pop(void) #define NARG_(_2, _1, n, ...) n #define NARG(...) NARG_(__VA_ARGS__, 2, 1, :) -static inline void *kmap_atomic(struct page *page) -{ - return __kmap_atomic(page); -} - static inline void __deprecated *kmap_atomic_deprecated(struct page *page, enum km_type km) { - return __kmap_atomic(page); + return kmap_atomic(page); } #define kmap_atomic1(...) kmap_atomic(__VA_ARGS__) -- 1.7.7.6 From florian@openwrt.org Fri Feb 10 14:43:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Feb 2012 14:43:55 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:60936 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903554Ab2BJNnt (ORCPT ); Fri, 10 Feb 2012 14:43:49 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id C731146278D; Fri, 10 Feb 2012 14:43:48 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8NGCCeY7HFPd; Fri, 10 Feb 2012 14:43:48 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 6A46B4626DF; Fri, 10 Feb 2012 14:43:48 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, david.daney@cavium.com, Florian Fainelli Subject: [PATCH] MIPS: perf: remove unused counters_per_cpu_to_total function Date: Fri, 10 Feb 2012 14:42:53 +0100 Message-Id: <1328881373-16716-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32415 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1106 Lines: 34 This function is currently unused and causes a build error: cc1: warnings being treated as errors arch/mips/kernel/perf_event_mipsxx.c:166: error: 'counters_per_cpu_to_total' defined but not used make[2]: *** [arch/mips/kernel/perf_event_mipsxx.o] Error 1 make[2]: *** Waiting for unfinished jobs.... It was first introduced in commit: 82091564: MIPS: perf: Add support for 64-bit perf counters. and is applicable to 3.2 onwards. Signed-off-by: Florian Fainelli --- arch/mips/kernel/perf_event_mipsxx.c | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index e3b897a..25e8fae 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -162,11 +162,6 @@ static unsigned int counters_total_to_per_cpu(unsigned int counters) return counters >> vpe_shift(); } -static unsigned int counters_per_cpu_to_total(unsigned int counters) -{ - return counters << vpe_shift(); -} - #else /* !CONFIG_MIPS_MT_SMP */ #define vpe_id() 0 -- 1.7.5.4 From m.szyprowski@samsung.com Fri Feb 10 19:32:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Feb 2012 19:32:57 +0100 (CET) Received: from mailout4.w1.samsung.com ([210.118.77.14]:49758 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903592Ab2BJScw (ORCPT ); Fri, 10 Feb 2012 19:32:52 +0100 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: TEXT/PLAIN Received: from euspt1 ([210.118.77.14]) by mailout4.w1.samsung.com (Sun Java(tm) System Messaging Server 6.3-8.04 (built Jul 29 2009; 32bit)) with ESMTP id <0LZ6004RLWUDSW80@mailout4.w1.samsung.com> for linux-mips@linux-mips.org; Fri, 10 Feb 2012 18:32:37 +0000 (GMT) Received: from linux.samsung.com ([106.116.38.10]) by spt1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LZ600EE5WUC1A@spt1.w1.samsung.com> for linux-mips@linux-mips.org; Fri, 10 Feb 2012 18:32:37 +0000 (GMT) Received: from mcdsrvbld02.digital.local (unknown [106.116.37.23]) by linux.samsung.com (Postfix) with ESMTP id 69BA927006A; Fri, 10 Feb 2012 19:49:47 +0100 (CET) Date: Fri, 10 Feb 2012 19:32:17 +0100 From: Marek Szyprowski Subject: [PULL REQUEST] DMA-mapping framework redesign preparation patches To: Stephen Rothwell Cc: linux-kernel@vger.kernel.org, linux-next@vger.kernel.org, Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , FUJITA Tomonori , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Marek Szyprowski , Kyungmin Park , Andrzej Pietrasiewicz Message-id: <1328898737-15854-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.7.8.3 X-archive-position: 32416 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.szyprowski@samsung.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4317 Lines: 88 Hi Stephen, Our patches with DMA-mapping framework redesign proposal have been hanging for over a month with just a few comments. We would like to go further in the development, but first I would like to ask You to give them a try in the linux-next kernel. For everyone interested in this patch series, here is the relevant thread: https://lkml.org/lkml/2011/12/23/97 If there are any problems with our git tree, please contact Marek Szyprowski or alternatively Kyungmin Park . The following changes since commit 62aa2b537c6f5957afd98e29f96897419ed5ebab: Linux 3.3-rc2 (2012-01-31 13:31:54 -0800) are available in the git repository at: git://git.infradead.org/users/kmpark/linux-samsung dma-mapping-next Andrzej Pietrasiewicz (9): X86: adapt for dma_map_ops changes MIPS: adapt for dma_map_ops changes PowerPC: adapt for dma_map_ops changes IA64: adapt for dma_map_ops changes SPARC: adapt for dma_map_ops changes Alpha: adapt for dma_map_ops changes SH: adapt for dma_map_ops changes Microblaze: adapt for dma_map_ops changes Unicore32: adapt for dma_map_ops changes Marek Szyprowski (5): common: dma-mapping: introduce alloc_attrs and free_attrs methods common: dma-mapping: remove old alloc_coherent and free_coherent methods common: dma-mapping: introduce mmap method common: DMA-mapping: add WRITE_COMBINE attribute common: DMA-mapping: add NON-CONSISTENT attribute Documentation/DMA-attributes.txt | 19 +++++++++++++++++++ arch/alpha/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/alpha/kernel/pci-noop.c | 10 ++++++---- arch/alpha/kernel/pci_iommu.c | 10 ++++++---- arch/ia64/hp/common/sba_iommu.c | 11 ++++++----- arch/ia64/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/ia64/kernel/pci-swiotlb.c | 9 +++++---- arch/ia64/sn/pci/pci_dma.c | 9 +++++---- arch/microblaze/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/microblaze/kernel/dma.c | 10 ++++++---- arch/mips/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/mips/mm/dma-default.c | 8 ++++---- arch/powerpc/include/asm/dma-mapping.h | 24 ++++++++++++++++-------- arch/powerpc/kernel/dma-iommu.c | 10 ++++++---- arch/powerpc/kernel/dma-swiotlb.c | 4 ++-- arch/powerpc/kernel/dma.c | 10 ++++++---- arch/powerpc/kernel/ibmebus.c | 10 ++++++---- arch/powerpc/platforms/cell/iommu.c | 16 +++++++++------- arch/powerpc/platforms/ps3/system-bus.c | 13 +++++++------ arch/sh/include/asm/dma-mapping.h | 28 ++++++++++++++++++---------- arch/sh/kernel/dma-nommu.c | 4 ++-- arch/sh/mm/consistent.c | 6 ++++-- arch/sparc/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/sparc/kernel/iommu.c | 10 ++++++---- arch/sparc/kernel/ioport.c | 18 ++++++++++-------- arch/sparc/kernel/pci_sun4v.c | 9 +++++---- arch/unicore32/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/unicore32/mm/dma-swiotlb.c | 4 ++-- arch/x86/include/asm/dma-mapping.h | 26 ++++++++++++++++---------- arch/x86/kernel/amd_gart_64.c | 11 ++++++----- arch/x86/kernel/pci-calgary_64.c | 9 +++++---- arch/x86/kernel/pci-dma.c | 3 ++- arch/x86/kernel/pci-nommu.c | 6 +++--- arch/x86/kernel/pci-swiotlb.c | 12 +++++++----- arch/x86/xen/pci-swiotlb-xen.c | 4 ++-- drivers/iommu/amd_iommu.c | 10 ++++++---- drivers/iommu/intel-iommu.c | 9 +++++---- drivers/xen/swiotlb-xen.c | 5 +++-- include/linux/dma-attrs.h | 2 ++ include/linux/dma-mapping.h | 13 +++++++++---- include/linux/swiotlb.h | 6 ++++-- include/xen/swiotlb-xen.h | 6 ++++-- lib/swiotlb.c | 5 +++-- 43 files changed, 305 insertions(+), 182 deletions(-) Best regards Marek Szyprowski Samsung Poland R&D Center From sfr@canb.auug.org.au Mon Feb 13 01:22:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Feb 2012 10:26:58 +0100 (CET) Received: from haggis.pcug.org.au ([203.10.76.10]:47906 "EHLO members.tip.net.au" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904876Ab2BMAWL (ORCPT ); Mon, 13 Feb 2012 01:22:11 +0100 Received: from canb.auug.org.au (ibmaus65.lnk.telstra.net [165.228.126.9]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by members.tip.net.au (Postfix) with ESMTPSA id 174101640D7; Mon, 13 Feb 2012 11:21:50 +1100 (EST) Date: Mon, 13 Feb 2012 11:21:45 +1100 From: Stephen Rothwell To: Marek Szyprowski Cc: linux-kernel@vger.kernel.org, linux-next@vger.kernel.org, Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , FUJITA Tomonori , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Kyungmin Park , Andrzej Pietrasiewicz Subject: Re: [PULL REQUEST] DMA-mapping framework redesign preparation patches Message-Id: <20120213112145.4b8990c739d297cd30714d52@canb.auug.org.au> In-Reply-To: <1328898737-15854-1-git-send-email-m.szyprowski@samsung.com> References: <1328898737-15854-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: Sylpheed 3.2.0beta5 (GTK+ 2.24.9; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg="PGP-SHA256"; boundary="Signature=_Mon__13_Feb_2012_11_21_45_+1100_8oMlxM5sQu=KHg4V" X-archive-position: 32417 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sfr@canb.auug.org.au Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3639 Lines: 88 --Signature=_Mon__13_Feb_2012_11_21_45_+1100_8oMlxM5sQu=KHg4V Content-Type: text/plain; charset=US-ASCII Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Marek, On Fri, 10 Feb 2012 19:32:17 +0100 Marek Szyprowski wrote: > > Our patches with DMA-mapping framework redesign proposal have been > hanging for over a month with just a few comments. We would like to go > further in the development, but first I would like to ask You to give > them a try in the linux-next kernel. >=20 > For everyone interested in this patch series, here is the relevant > thread: https://lkml.org/lkml/2011/12/23/97 >=20 > If there are any problems with our git tree, please contact Marek=20 > Szyprowski or alternatively Kyungmin Park > . >=20 > The following changes since commit 62aa2b537c6f5957afd98e29f96897419ed5eb= ab: >=20 > Linux 3.3-rc2 (2012-01-31 13:31:54 -0800) >=20 > are available in the git repository at: > git://git.infradead.org/users/kmpark/linux-samsung dma-mapping-next I have added this from today. Thanks for adding your subsystem tree as a participant of linux-next. As you may know, this is not a judgment of your code. The purpose of linux-next is for integration testing and to lower the impact of conflicts between subsystems in the next merge window.=20 You will need to ensure that the patches/commits in your tree/series have been: * submitted under GPL v2 (or later) and include the Contributor's Signed-off-by, * posted to the relevant mailing list, * reviewed by you (or another maintainer of your subsystem tree), * successfully unit tested, and=20 * destined for the current or next Linux merge window. Basically, this should be just what you would send to Linus (or ask him to fetch). It is allowed to be rebased if you deem it necessary. --=20 Cheers, Stephen Rothwell=20 sfr@canb.auug.org.au Legal Stuff: By participating in linux-next, your subsystem tree contributions are public and will be included in the linux-next trees. You may be sent e-mail messages indicating errors or other issues when the patches/commits from your subsystem tree are merged and tested in linux-next. These messages may also be cross-posted to the linux-next mailing list, the linux-kernel mailing list, etc. The linux-next tree project and IBM (my employer) make no warranties regarding the linux-next project, the testing procedures, the results, the e-mails, etc. If you don't agree to these ground rules, let me know and I'll remove your tree from participation in linux-next. --Signature=_Mon__13_Feb_2012_11_21_45_+1100_8oMlxM5sQu=KHg4V Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBCAAGBQJPOFeZAAoJEECxmPOUX5FEGasQAJRfELGvaG157f04fLOp5cZ+ BExY8MINAksS9ksXnf+o7emW9FWZFTLZT3pJ7Gnx8j/Po+kYnITOStRQLl6K8h3Y +cZmYubikIrZyPJCVYBZUTH0Gi/5VrTCx/rbolS2ai67WicKa7qzPOJ5D/oaeCdY CiOWMIgyaNbESpoR/l32Ta4XMJG0aDIV6bWlBpmKZVSzmpOFh40StsbQ3Ej6UUfo b+lo7IhOegjvNWITbiuIRDe9bAk5ONW2UU1z5sOWq/aELytRbSw1bNifvJlQF1VG AD+VNjEMrYNKg9soRpaZaIqAN1wb8a+I3//iaSL9kVstPo+D5uJLjAIEWBsgUO+N Duu3l8/GNL9tb1EvDXrt4d+H8zaow9P11rGHb2e6x9ndLZDmijjcYLQa1R/ektxo Z7kZIJNvi6rGlAurojo+q5gjnIP4aDDjZNMJ4pCayn5+YCLfDvu6jcK7od5S5dEM fbmVkAAysd8ajciJdN0Yj9Vv/oZ2/ARaQjAMVZtOBNTj5JR/WdRPeYZ0y71a4hSX RYNdeiQC3AhYufvXe5YCP7e+MvzMRHW336Rjyd+AMNjYx/cs6JZSOVgz6qKTWX6H oWde9Tl8A70eoN3/LtS7kC+WX228gPd9qPn5sHxyiKVV87OxwNaDP3kZqS1k3b3r 4gyxILj3Uf7TanB2Wbsh =mWBa -----END PGP SIGNATURE----- --Signature=_Mon__13_Feb_2012_11_21_45_+1100_8oMlxM5sQu=KHg4V-- From m.szyprowski@samsung.com Mon Feb 13 11:36:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Feb 2012 11:36:29 +0100 (CET) Received: from mailout3.w1.samsung.com ([210.118.77.13]:51630 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904179Ab2BMKgV (ORCPT ); Mon, 13 Feb 2012 11:36:21 +0100 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: TEXT/PLAIN Received: from euspt2 ([210.118.77.13]) by mailout3.w1.samsung.com (Sun Java(tm) System Messaging Server 6.3-8.04 (built Jul 29 2009; 32bit)) with ESMTP id <0LZB00EBPUSD5340@mailout3.w1.samsung.com> for linux-mips@linux-mips.org; Mon, 13 Feb 2012 10:36:13 +0000 (GMT) Received: from linux.samsung.com ([106.116.38.10]) by spt2.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LZB00BABUSCGJ@spt2.w1.samsung.com> for linux-mips@linux-mips.org; Mon, 13 Feb 2012 10:36:13 +0000 (GMT) Received: from mcdsrvbld02.digital.local (unknown [106.116.37.23]) by linux.samsung.com (Postfix) with ESMTP id D0A5427004F; Mon, 13 Feb 2012 11:53:46 +0100 (CET) Date: Mon, 13 Feb 2012 11:35:28 +0100 From: Marek Szyprowski Subject: [PATCH 03/14 v2] MIPS: adapt for dma_map_ops changes In-reply-to: <1324643253-3024-4-git-send-email-m.szyprowski@samsung.com> To: linux-kernel@vger.kernel.org Cc: Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , Stephen Rothwell , FUJITA Tomonori , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Marek Szyprowski , Kyungmin Park , Andrzej Pietrasiewicz Message-id: <1329129329-25205-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.7.8.3 References: <1324643253-3024-4-git-send-email-m.szyprowski@samsung.com> X-archive-position: 32418 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.szyprowski@samsung.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5657 Lines: 154 From: Andrzej Pietrasiewicz Adapt core MIPS architecture code for dma_map_ops changes: replace alloc/free_coherent with generic alloc/free methods. Signed-off-by: Andrzej Pietrasiewicz [added missing changes to arch/mips/cavium-octeon/dma-octeon.c] Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park --- arch/mips/cavium-octeon/dma-octeon.c | 16 ++++++++-------- arch/mips/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/mips/mm/dma-default.c | 8 ++++---- 3 files changed, 24 insertions(+), 18 deletions(-) diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index b6bb92c..df70600 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -157,7 +157,7 @@ static void octeon_dma_sync_sg_for_device(struct device *dev, } static void *octeon_dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp) + dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs) { void *ret; @@ -184,7 +184,7 @@ static void *octeon_dma_alloc_coherent(struct device *dev, size_t size, /* Don't invoke OOM killer */ gfp |= __GFP_NORETRY; - ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp); + ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp, attrs); mb(); @@ -192,14 +192,14 @@ static void *octeon_dma_alloc_coherent(struct device *dev, size_t size, } static void octeon_dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) + void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs) { int order = get_order(size); if (dma_release_from_coherent(dev, order, vaddr)) return; - swiotlb_free_coherent(dev, size, vaddr, dma_handle); + swiotlb_free_coherent(dev, size, vaddr, dma_handle, attrs); } static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr) @@ -240,8 +240,8 @@ EXPORT_SYMBOL(dma_to_phys); static struct octeon_dma_map_ops octeon_linear_dma_map_ops = { .dma_map_ops = { - .alloc_coherent = octeon_dma_alloc_coherent, - .free_coherent = octeon_dma_free_coherent, + .alloc = octeon_dma_alloc_coherent, + .free = octeon_dma_free_coherent, .map_page = octeon_dma_map_page, .unmap_page = swiotlb_unmap_page, .map_sg = octeon_dma_map_sg, @@ -325,8 +325,8 @@ void __init plat_swiotlb_setup(void) #ifdef CONFIG_PCI static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = { .dma_map_ops = { - .alloc_coherent = octeon_dma_alloc_coherent, - .free_coherent = octeon_dma_free_coherent, + .alloc = octeon_dma_alloc_coherent, + .free = octeon_dma_free_coherent, .map_page = octeon_dma_map_page, .unmap_page = swiotlb_unmap_page, .map_sg = octeon_dma_map_sg, diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index 7aa37dd..cbd41f5 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -57,25 +57,31 @@ dma_set_mask(struct device *dev, u64 mask) extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction); -static inline void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp) +#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) + +static inline void *dma_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp, + struct dma_attrs *attrs) { void *ret; struct dma_map_ops *ops = get_dma_ops(dev); - ret = ops->alloc_coherent(dev, size, dma_handle, gfp); + ret = ops->alloc(dev, size, dma_handle, gfp, NULL); debug_dma_alloc_coherent(dev, size, *dma_handle, ret); return ret; } -static inline void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL) + +static inline void dma_free_attrs(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle, + struct dma_attrs *attrs) { struct dma_map_ops *ops = get_dma_ops(dev); - ops->free_coherent(dev, size, vaddr, dma_handle); + ops->free(dev, size, vaddr, dma_handle, NULL); debug_dma_free_coherent(dev, size, vaddr, dma_handle); } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 4608491..3fab204 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -98,7 +98,7 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size, EXPORT_SYMBOL(dma_alloc_noncoherent); static void *mips_dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, gfp_t gfp) + dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) { void *ret; @@ -132,7 +132,7 @@ void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, EXPORT_SYMBOL(dma_free_noncoherent); static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_handle) + dma_addr_t dma_handle, struct dma_attrs *attrs) { unsigned long addr = (unsigned long) vaddr; int order = get_order(size); @@ -323,8 +323,8 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, EXPORT_SYMBOL(dma_cache_sync); static struct dma_map_ops mips_default_dma_map_ops = { - .alloc_coherent = mips_dma_alloc_coherent, - .free_coherent = mips_dma_free_coherent, + .alloc = mips_dma_alloc_coherent, + .free = mips_dma_free_coherent, .map_page = mips_dma_map_page, .unmap_page = mips_dma_unmap_page, .map_sg = mips_dma_map_sg, -- 1.7.1.569.g6f426 From m.szyprowski@samsung.com Mon Feb 13 11:37:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Feb 2012 11:37:12 +0100 (CET) Received: from mailout1.w1.samsung.com ([210.118.77.11]:30365 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904198Ab2BMKhD (ORCPT ); Mon, 13 Feb 2012 11:37:03 +0100 Received: from euspt2 (mailout1.w1.samsung.com [210.118.77.11]) by mailout1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTP id <0LZB002CAUTKMW@mailout1.w1.samsung.com> for linux-mips@linux-mips.org; Mon, 13 Feb 2012 10:36:56 +0000 (GMT) Received: from linux.samsung.com ([106.116.38.10]) by spt2.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LZB005QTUTJXL@spt2.w1.samsung.com> for linux-mips@linux-mips.org; Mon, 13 Feb 2012 10:36:56 +0000 (GMT) Received: from mcdsrvbld02.digital.local (unknown [106.116.37.23]) by linux.samsung.com (Postfix) with ESMTP id EBB3227004F; Mon, 13 Feb 2012 11:54:29 +0100 (CET) Date: Mon, 13 Feb 2012 11:36:45 +0100 From: Marek Szyprowski Subject: [PATCH 04/14 v2] PowerPC: adapt for dma_map_ops changes In-reply-to: <1324643253-3024-5-git-send-email-m.szyprowski@samsung.com> To: linux-kernel@vger.kernel.org Cc: Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , Stephen Rothwell , FUJITA Tomonori , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Marek Szyprowski , Kyungmin Park , Andrzej Pietrasiewicz Message-id: <1329129405-25609-1-git-send-email-m.szyprowski@samsung.com> MIME-version: 1.0 X-Mailer: git-send-email 1.7.8.3 Content-type: TEXT/PLAIN Content-transfer-encoding: 7BIT References: <1324643253-3024-5-git-send-email-m.szyprowski@samsung.com> X-archive-position: 32419 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.szyprowski@samsung.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 13221 Lines: 349 From: Andrzej Pietrasiewicz Adapt core PowerPC architecture code for dma_map_ops changes: replace alloc/free_coherent with generic alloc/free methods. Signed-off-by: Andrzej Pietrasiewicz Signed-off-by: Marek Szyprowski [added missing changes to arch/powerpc/kernel/vio.c] Signed-off-by: Kyungmin Park Reviewed-by: David Gibson --- arch/powerpc/include/asm/dma-mapping.h | 24 ++++++++++++++++-------- arch/powerpc/kernel/dma-iommu.c | 10 ++++++---- arch/powerpc/kernel/dma-swiotlb.c | 4 ++-- arch/powerpc/kernel/dma.c | 10 ++++++---- arch/powerpc/kernel/ibmebus.c | 10 ++++++---- arch/powerpc/kernel/vio.c | 14 ++++++++------ arch/powerpc/platforms/cell/iommu.c | 16 +++++++++------- arch/powerpc/platforms/ps3/system-bus.c | 13 +++++++------ 8 files changed, 60 insertions(+), 41 deletions(-) diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h index dd70fac..62678e3 100644 --- a/arch/powerpc/include/asm/dma-mapping.h +++ b/arch/powerpc/include/asm/dma-mapping.h @@ -22,9 +22,11 @@ /* Some dma direct funcs must be visible for use in other dma_ops */ extern void *dma_direct_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag); + dma_addr_t *dma_handle, gfp_t flag, + struct dma_attrs *attrs); extern void dma_direct_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); + void *vaddr, dma_addr_t dma_handle, + struct dma_attrs *attrs); #ifdef CONFIG_NOT_COHERENT_CACHE @@ -130,23 +132,29 @@ static inline int dma_supported(struct device *dev, u64 mask) extern int dma_set_mask(struct device *dev, u64 dma_mask); -static inline void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag) +#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) + +static inline void *dma_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag, + struct dma_attrs *attrs) { struct dma_map_ops *dma_ops = get_dma_ops(dev); void *cpu_addr; BUG_ON(!dma_ops); - cpu_addr = dma_ops->alloc_coherent(dev, size, dma_handle, flag); + cpu_addr = dma_ops->alloc(dev, size, dma_handle, flag, attrs); debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); return cpu_addr; } -static inline void dma_free_coherent(struct device *dev, size_t size, - void *cpu_addr, dma_addr_t dma_handle) +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL) + +static inline void dma_free_attrs(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_handle, + struct dma_attrs *attrs) { struct dma_map_ops *dma_ops = get_dma_ops(dev); @@ -154,7 +162,7 @@ static inline void dma_free_coherent(struct device *dev, size_t size, debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); - dma_ops->free_coherent(dev, size, cpu_addr, dma_handle); + dma_ops->free(dev, size, cpu_addr, dma_handle, attrs); } static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c index 3f6464b..bcfdcd2 100644 --- a/arch/powerpc/kernel/dma-iommu.c +++ b/arch/powerpc/kernel/dma-iommu.c @@ -17,7 +17,8 @@ * to the dma address (mapping) of the first page. */ static void *dma_iommu_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag) + dma_addr_t *dma_handle, gfp_t flag, + struct dma_attrs *attrs) { return iommu_alloc_coherent(dev, get_iommu_table_base(dev), size, dma_handle, dev->coherent_dma_mask, flag, @@ -25,7 +26,8 @@ static void *dma_iommu_alloc_coherent(struct device *dev, size_t size, } static void dma_iommu_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) + void *vaddr, dma_addr_t dma_handle, + struct dma_attrs *attrs) { iommu_free_coherent(get_iommu_table_base(dev), size, vaddr, dma_handle); } @@ -105,8 +107,8 @@ static u64 dma_iommu_get_required_mask(struct device *dev) } struct dma_map_ops dma_iommu_ops = { - .alloc_coherent = dma_iommu_alloc_coherent, - .free_coherent = dma_iommu_free_coherent, + .alloc = dma_iommu_alloc_coherent, + .free = dma_iommu_free_coherent, .map_sg = dma_iommu_map_sg, .unmap_sg = dma_iommu_unmap_sg, .dma_supported = dma_iommu_dma_supported, diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c index 1ebc918..4ab88da 100644 --- a/arch/powerpc/kernel/dma-swiotlb.c +++ b/arch/powerpc/kernel/dma-swiotlb.c @@ -47,8 +47,8 @@ static u64 swiotlb_powerpc_get_required(struct device *dev) * for everything else. */ struct dma_map_ops swiotlb_dma_ops = { - .alloc_coherent = dma_direct_alloc_coherent, - .free_coherent = dma_direct_free_coherent, + .alloc = dma_direct_alloc_coherent, + .free = dma_direct_free_coherent, .map_sg = swiotlb_map_sg_attrs, .unmap_sg = swiotlb_unmap_sg_attrs, .dma_supported = swiotlb_dma_supported, diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c index 7d0233c..b1ec983 100644 --- a/arch/powerpc/kernel/dma.c +++ b/arch/powerpc/kernel/dma.c @@ -26,7 +26,8 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag) + dma_addr_t *dma_handle, gfp_t flag, + struct dma_attrs *attrs) { void *ret; #ifdef CONFIG_NOT_COHERENT_CACHE @@ -54,7 +55,8 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size, } void dma_direct_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) + void *vaddr, dma_addr_t dma_handle, + struct dma_attrs *attrs) { #ifdef CONFIG_NOT_COHERENT_CACHE __dma_free_coherent(size, vaddr); @@ -150,8 +152,8 @@ static inline void dma_direct_sync_single(struct device *dev, #endif struct dma_map_ops dma_direct_ops = { - .alloc_coherent = dma_direct_alloc_coherent, - .free_coherent = dma_direct_free_coherent, + .alloc = dma_direct_alloc_coherent, + .free = dma_direct_free_coherent, .map_sg = dma_direct_map_sg, .unmap_sg = dma_direct_unmap_sg, .dma_supported = dma_direct_dma_supported, diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c index d39ae60..716d918 100644 --- a/arch/powerpc/kernel/ibmebus.c +++ b/arch/powerpc/kernel/ibmebus.c @@ -65,7 +65,8 @@ static struct of_device_id __initdata ibmebus_matches[] = { static void *ibmebus_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, - gfp_t flag) + gfp_t flag, + struct dma_attrs *attrs) { void *mem; @@ -77,7 +78,8 @@ static void *ibmebus_alloc_coherent(struct device *dev, static void ibmebus_free_coherent(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_handle) + dma_addr_t dma_handle, + struct dma_attrs *attrs) { kfree(vaddr); } @@ -136,8 +138,8 @@ static u64 ibmebus_dma_get_required_mask(struct device *dev) } static struct dma_map_ops ibmebus_dma_ops = { - .alloc_coherent = ibmebus_alloc_coherent, - .free_coherent = ibmebus_free_coherent, + .alloc = ibmebus_alloc_coherent, + .free = ibmebus_free_coherent, .map_sg = ibmebus_map_sg, .unmap_sg = ibmebus_unmap_sg, .dma_supported = ibmebus_dma_supported, diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c index 8b08629..2d49c32 100644 --- a/arch/powerpc/kernel/vio.c +++ b/arch/powerpc/kernel/vio.c @@ -487,7 +487,8 @@ static void vio_cmo_balance(struct work_struct *work) } static void *vio_dma_iommu_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag) + dma_addr_t *dma_handle, gfp_t flag, + struct dma_attrs *attrs) { struct vio_dev *viodev = to_vio_dev(dev); void *ret; @@ -497,7 +498,7 @@ static void *vio_dma_iommu_alloc_coherent(struct device *dev, size_t size, return NULL; } - ret = dma_iommu_ops.alloc_coherent(dev, size, dma_handle, flag); + ret = dma_iommu_ops.alloc(dev, size, dma_handle, flag, attrs); if (unlikely(ret == NULL)) { vio_cmo_dealloc(viodev, roundup(size, PAGE_SIZE)); atomic_inc(&viodev->cmo.allocs_failed); @@ -507,11 +508,12 @@ static void *vio_dma_iommu_alloc_coherent(struct device *dev, size_t size, } static void vio_dma_iommu_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) + void *vaddr, dma_addr_t dma_handle, + struct dma_attrs *attrs) { struct vio_dev *viodev = to_vio_dev(dev); - dma_iommu_ops.free_coherent(dev, size, vaddr, dma_handle); + dma_iommu_ops.free(dev, size, vaddr, dma_handle, attrs); vio_cmo_dealloc(viodev, roundup(size, PAGE_SIZE)); } @@ -612,8 +614,8 @@ static u64 vio_dma_get_required_mask(struct device *dev) } struct dma_map_ops vio_dma_mapping_ops = { - .alloc_coherent = vio_dma_iommu_alloc_coherent, - .free_coherent = vio_dma_iommu_free_coherent, + .alloc = vio_dma_iommu_alloc_coherent, + .free = vio_dma_iommu_free_coherent, .map_sg = vio_dma_iommu_map_sg, .unmap_sg = vio_dma_iommu_unmap_sg, .map_page = vio_dma_iommu_map_page, diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c index ae9fc7b..b9f509a 100644 --- a/arch/powerpc/platforms/cell/iommu.c +++ b/arch/powerpc/platforms/cell/iommu.c @@ -564,7 +564,8 @@ static struct iommu_table *cell_get_iommu_table(struct device *dev) /* A coherent allocation implies strong ordering */ static void *dma_fixed_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag) + dma_addr_t *dma_handle, gfp_t flag, + struct dma_attrs *attrs) { if (iommu_fixed_is_weak) return iommu_alloc_coherent(dev, cell_get_iommu_table(dev), @@ -572,18 +573,19 @@ static void *dma_fixed_alloc_coherent(struct device *dev, size_t size, device_to_mask(dev), flag, dev_to_node(dev)); else - return dma_direct_ops.alloc_coherent(dev, size, dma_handle, - flag); + return dma_direct_ops.alloc(dev, size, dma_handle, flag, + attrs); } static void dma_fixed_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) + void *vaddr, dma_addr_t dma_handle, + struct dma_attrs *attrs) { if (iommu_fixed_is_weak) iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr, dma_handle); else - dma_direct_ops.free_coherent(dev, size, vaddr, dma_handle); + dma_direct_ops.free(dev, size, vaddr, dma_handle, attrs); } static dma_addr_t dma_fixed_map_page(struct device *dev, struct page *page, @@ -642,8 +644,8 @@ static int dma_fixed_dma_supported(struct device *dev, u64 mask) static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask); struct dma_map_ops dma_iommu_fixed_ops = { - .alloc_coherent = dma_fixed_alloc_coherent, - .free_coherent = dma_fixed_free_coherent, + .alloc = dma_fixed_alloc_coherent, + .free = dma_fixed_free_coherent, .map_sg = dma_fixed_map_sg, .unmap_sg = dma_fixed_unmap_sg, .dma_supported = dma_fixed_dma_supported, diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c index 880eb9c..5606fe3 100644 --- a/arch/powerpc/platforms/ps3/system-bus.c +++ b/arch/powerpc/platforms/ps3/system-bus.c @@ -515,7 +515,8 @@ core_initcall(ps3_system_bus_init); * to the dma address (mapping) of the first page. */ static void * ps3_alloc_coherent(struct device *_dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag) + dma_addr_t *dma_handle, gfp_t flag, + struct dma_attrs *attrs) { int result; struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev); @@ -552,7 +553,7 @@ clean_none: } static void ps3_free_coherent(struct device *_dev, size_t size, void *vaddr, - dma_addr_t dma_handle) + dma_addr_t dma_handle, struct dma_attrs *attrs) { struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev); @@ -701,8 +702,8 @@ static u64 ps3_dma_get_required_mask(struct device *_dev) } static struct dma_map_ops ps3_sb_dma_ops = { - .alloc_coherent = ps3_alloc_coherent, - .free_coherent = ps3_free_coherent, + .alloc = ps3_alloc_coherent, + .free = ps3_free_coherent, .map_sg = ps3_sb_map_sg, .unmap_sg = ps3_sb_unmap_sg, .dma_supported = ps3_dma_supported, @@ -712,8 +713,8 @@ static struct dma_map_ops ps3_sb_dma_ops = { }; static struct dma_map_ops ps3_ioc0_dma_ops = { - .alloc_coherent = ps3_alloc_coherent, - .free_coherent = ps3_free_coherent, + .alloc = ps3_alloc_coherent, + .free = ps3_free_coherent, .map_sg = ps3_ioc0_map_sg, .unmap_sg = ps3_ioc0_unmap_sg, .dma_supported = ps3_dma_supported, -- 1.7.1.569.g6f426 From m.szyprowski@samsung.com Mon Feb 13 11:40:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Feb 2012 11:40:24 +0100 (CET) Received: from mailout1.w1.samsung.com ([210.118.77.11]:30830 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904308Ab2BMKkT (ORCPT ); Mon, 13 Feb 2012 11:40:19 +0100 Received: from euspt2 (mailout1.w1.samsung.com [210.118.77.11]) by mailout1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTP id <0LZB002B3UZ1IE@mailout1.w1.samsung.com> for linux-mips@linux-mips.org; Mon, 13 Feb 2012 10:40:13 +0000 (GMT) Received: from linux.samsung.com ([106.116.38.10]) by spt2.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LZB005GLUZ1Y4@spt2.w1.samsung.com> for linux-mips@linux-mips.org; Mon, 13 Feb 2012 10:40:13 +0000 (GMT) Received: from mcdsrvbld02.digital.local (unknown [106.116.37.23]) by linux.samsung.com (Postfix) with ESMTP id C2C7327004F; Mon, 13 Feb 2012 11:57:47 +0100 (CET) Date: Mon, 13 Feb 2012 11:40:05 +0100 From: Marek Szyprowski Subject: [PATCH] Hexagon: adapt for dma_map_ops changes In-reply-to: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com> To: linux-kernel@vger.kernel.org Cc: Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , Stephen Rothwell , FUJITA Tomonori , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Marek Szyprowski , Kyungmin Park , Andrzej Pietrasiewicz , linux-hexagon@vger.kernel.org Message-id: <1329129605-27355-1-git-send-email-m.szyprowski@samsung.com> MIME-version: 1.0 X-Mailer: git-send-email 1.7.8.3 Content-type: TEXT/PLAIN Content-transfer-encoding: 7BIT References: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com> X-archive-position: 32420 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.szyprowski@samsung.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3488 Lines: 105 Adapt core Hexagon architecture code for dma_map_ops changes: replace alloc/free_coherent with generic alloc/free methods. Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park --- Hello, This patch adds Hexagon architecture to the DMA-mapping framework redesign preparation patches. For more information please refer to the following thread: https://lkml.org/lkml/2011/12/23/97 Best regards Marek Szyprowski Samsung Poland R&D Center --- arch/hexagon/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/hexagon/kernel/dma.c | 9 +++++---- 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/arch/hexagon/include/asm/dma-mapping.h b/arch/hexagon/include/asm/dma-mapping.h index 448b224..233ed3d 100644 --- a/arch/hexagon/include/asm/dma-mapping.h +++ b/arch/hexagon/include/asm/dma-mapping.h @@ -71,29 +71,35 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) return (dma_addr == bad_dma_address); } -static inline void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag) +#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) + +static inline void *dma_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag, + struct dma_attrs *attrs) { void *ret; struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!dma_ops); - ret = ops->alloc_coherent(dev, size, dma_handle, flag); + ret = ops->alloc(dev, size, dma_handle, flag, attrs); debug_dma_alloc_coherent(dev, size, *dma_handle, ret); return ret; } -static inline void dma_free_coherent(struct device *dev, size_t size, - void *cpu_addr, dma_addr_t dma_handle) +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL) + +static inline void dma_free_attrs(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_handle, + struct dma_attrs *attrs) { struct dma_map_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->free_coherent(dev, size, cpu_addr, dma_handle); + dma_ops->free(dev, size, cpu_addr, dma_handle, attrs); debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); } diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c index e711ace..3730221 100644 --- a/arch/hexagon/kernel/dma.c +++ b/arch/hexagon/kernel/dma.c @@ -54,7 +54,8 @@ static struct gen_pool *coherent_pool; /* Allocates from a pool of uncached memory that was reserved at boot time */ void *hexagon_dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_addr, gfp_t flag) + dma_addr_t *dma_addr, gfp_t flag, + struct dma_attrs *attrs) { void *ret; @@ -81,7 +82,7 @@ void *hexagon_dma_alloc_coherent(struct device *dev, size_t size, } static void hexagon_free_coherent(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_addr) + dma_addr_t dma_addr, struct dma_attrs *attrs) { gen_pool_free(coherent_pool, (unsigned long) vaddr, size); } @@ -202,8 +203,8 @@ static void hexagon_sync_single_for_device(struct device *dev, } struct dma_map_ops hexagon_dma_ops = { - .alloc_coherent = hexagon_dma_alloc_coherent, - .free_coherent = hexagon_free_coherent, + .alloc = hexagon_dma_alloc_coherent, + .free = hexagon_free_coherent, .map_sg = hexagon_map_sg, .map_page = hexagon_map_page, .sync_single_for_cpu = hexagon_sync_single_for_cpu, -- 1.7.1.569.g6f426 From sshtylyov@mvista.com Mon Feb 13 11:43:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Feb 2012 11:43:08 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:46342 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904262Ab2BMKnB (ORCPT ); Mon, 13 Feb 2012 11:43:01 +0100 Received: by bkcjk13 with SMTP id jk13so4941364bkc.36 for ; Mon, 13 Feb 2012 02:42:55 -0800 (PST) Received: by 10.204.133.219 with SMTP id g27mr6895244bkt.47.1329129772722; Mon, 13 Feb 2012 02:42:52 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-92-216.pppoe.mtu-net.ru. [91.79.92.216]) by mx.google.com with ESMTPS id x20sm44878826bka.9.2012.02.13.02.42.49 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 13 Feb 2012 02:42:51 -0800 (PST) Message-ID: <4F38E8E1.3070004@mvista.com> Date: Mon, 13 Feb 2012 14:41:37 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0) Gecko/20120129 Thunderbird/10.0 MIME-Version: 1.0 To: Marek Szyprowski CC: linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , Stephen Rothwell , FUJITA Tomonori , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Kyungmin Park , Andrzej Pietrasiewicz Subject: Re: [PATCH 03/14 v2] MIPS: adapt for dma_map_ops changes References: <1324643253-3024-4-git-send-email-m.szyprowski@samsung.com> <1329129329-25205-1-git-send-email-m.szyprowski@samsung.com> In-Reply-To: <1329129329-25205-1-git-send-email-m.szyprowski@samsung.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQl/Rww8b5Z4OLdydnfAbPadgXRIbSl8B3mT4WtjQlmGw4ciU8XFBnPlsnSxACKIAC1qz+hk X-archive-position: 32421 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2084 Lines: 61 Hello. On 13-02-2012 14:35, Marek Szyprowski wrote: > From: Andrzej Pietrasiewicz > Adapt core MIPS architecture code for dma_map_ops changes: replace > alloc/free_coherent with generic alloc/free methods. > Signed-off-by: Andrzej Pietrasiewicz > [added missing changes to arch/mips/cavium-octeon/dma-octeon.c] > Signed-off-by: Marek Szyprowski > Signed-off-by: Kyungmin Park [...] > diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h > index 7aa37dd..cbd41f5 100644 > --- a/arch/mips/include/asm/dma-mapping.h > +++ b/arch/mips/include/asm/dma-mapping.h > @@ -57,25 +57,31 @@ dma_set_mask(struct device *dev, u64 mask) > extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, > enum dma_data_direction direction); > > -static inline void *dma_alloc_coherent(struct device *dev, size_t size, > - dma_addr_t *dma_handle, gfp_t gfp) > +#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) > + > +static inline void *dma_alloc_attrs(struct device *dev, size_t size, > + dma_addr_t *dma_handle, gfp_t gfp, > + struct dma_attrs *attrs) > { > void *ret; > struct dma_map_ops *ops = get_dma_ops(dev); > > - ret = ops->alloc_coherent(dev, size, dma_handle, gfp); > + ret = ops->alloc(dev, size, dma_handle, gfp, NULL); Not 'attrs' instead of NULL? > > debug_dma_alloc_coherent(dev, size, *dma_handle, ret); > > return ret; > } > > -static inline void dma_free_coherent(struct device *dev, size_t size, > - void *vaddr, dma_addr_t dma_handle) > +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL) > + > +static inline void dma_free_attrs(struct device *dev, size_t size, > + void *vaddr, dma_addr_t dma_handle, > + struct dma_attrs *attrs) > { > struct dma_map_ops *ops = get_dma_ops(dev); > > - ops->free_coherent(dev, size, vaddr, dma_handle); > + ops->free(dev, size, vaddr, dma_handle, NULL); Same here... WBR, Sergei From m.szyprowski@samsung.com Mon Feb 13 13:42:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Feb 2012 13:42:36 +0100 (CET) Received: from mailout4.w1.samsung.com ([210.118.77.14]:28895 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901163Ab2BMMma (ORCPT ); Mon, 13 Feb 2012 13:42:30 +0100 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: TEXT/PLAIN Received: from euspt1 ([210.118.77.14]) by mailout4.w1.samsung.com (Sun Java(tm) System Messaging Server 6.3-8.04 (built Jul 29 2009; 32bit)) with ESMTP id <0LZC00IW40MNCY50@mailout4.w1.samsung.com> for linux-mips@linux-mips.org; Mon, 13 Feb 2012 12:42:23 +0000 (GMT) Received: from linux.samsung.com ([106.116.38.10]) by spt1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LZC00DUY0MMLE@spt1.w1.samsung.com> for linux-mips@linux-mips.org; Mon, 13 Feb 2012 12:42:23 +0000 (GMT) Received: from mcdsrvbld02.digital.local (unknown [106.116.37.23]) by linux.samsung.com (Postfix) with ESMTP id 60FDC270054; Mon, 13 Feb 2012 13:59:58 +0100 (CET) Date: Mon, 13 Feb 2012 13:41:55 +0100 From: Marek Szyprowski Subject: [PATCH 03/14 v3] MIPS: adapt for dma_map_ops changes In-reply-to: <4F38E8E1.3070004@mvista.com> To: linux-kernel@vger.kernel.org Cc: Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , Stephen Rothwell , FUJITA Tomonori , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Marek Szyprowski , Kyungmin Park , Andrzej Pietrasiewicz Message-id: <1329136915-24824-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.7.8.3 References: <4F38E8E1.3070004@mvista.com> X-archive-position: 32422 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.szyprowski@samsung.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5699 Lines: 155 From: Andrzej Pietrasiewicz Adapt core MIPS architecture code for dma_map_ops changes: replace alloc/free_coherent with generic alloc/free methods. Signed-off-by: Andrzej Pietrasiewicz [added missing changes to arch/mips/cavium-octeon/dma-octeon.c, fixed attrs argument in dma-mapping.h] Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park --- arch/mips/cavium-octeon/dma-octeon.c | 16 ++++++++-------- arch/mips/include/asm/dma-mapping.h | 18 ++++++++++++------ arch/mips/mm/dma-default.c | 8 ++++---- 3 files changed, 24 insertions(+), 18 deletions(-) diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index b6bb92c..df70600 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -157,7 +157,7 @@ static void octeon_dma_sync_sg_for_device(struct device *dev, } static void *octeon_dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp) + dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs) { void *ret; @@ -184,7 +184,7 @@ static void *octeon_dma_alloc_coherent(struct device *dev, size_t size, /* Don't invoke OOM killer */ gfp |= __GFP_NORETRY; - ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp); + ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp, attrs); mb(); @@ -192,14 +192,14 @@ static void *octeon_dma_alloc_coherent(struct device *dev, size_t size, } static void octeon_dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) + void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs) { int order = get_order(size); if (dma_release_from_coherent(dev, order, vaddr)) return; - swiotlb_free_coherent(dev, size, vaddr, dma_handle); + swiotlb_free_coherent(dev, size, vaddr, dma_handle, attrs); } static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr) @@ -240,8 +240,8 @@ EXPORT_SYMBOL(dma_to_phys); static struct octeon_dma_map_ops octeon_linear_dma_map_ops = { .dma_map_ops = { - .alloc_coherent = octeon_dma_alloc_coherent, - .free_coherent = octeon_dma_free_coherent, + .alloc = octeon_dma_alloc_coherent, + .free = octeon_dma_free_coherent, .map_page = octeon_dma_map_page, .unmap_page = swiotlb_unmap_page, .map_sg = octeon_dma_map_sg, @@ -325,8 +325,8 @@ void __init plat_swiotlb_setup(void) #ifdef CONFIG_PCI static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = { .dma_map_ops = { - .alloc_coherent = octeon_dma_alloc_coherent, - .free_coherent = octeon_dma_free_coherent, + .alloc = octeon_dma_alloc_coherent, + .free = octeon_dma_free_coherent, .map_page = octeon_dma_map_page, .unmap_page = swiotlb_unmap_page, .map_sg = octeon_dma_map_sg, diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index 7aa37dd..be39a12 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -57,25 +57,31 @@ dma_set_mask(struct device *dev, u64 mask) extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction); -static inline void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp) +#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) + +static inline void *dma_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp, + struct dma_attrs *attrs) { void *ret; struct dma_map_ops *ops = get_dma_ops(dev); - ret = ops->alloc_coherent(dev, size, dma_handle, gfp); + ret = ops->alloc(dev, size, dma_handle, gfp, attrs); debug_dma_alloc_coherent(dev, size, *dma_handle, ret); return ret; } -static inline void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL) + +static inline void dma_free_attrs(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle, + struct dma_attrs *attrs) { struct dma_map_ops *ops = get_dma_ops(dev); - ops->free_coherent(dev, size, vaddr, dma_handle); + ops->free(dev, size, vaddr, dma_handle, attrs); debug_dma_free_coherent(dev, size, vaddr, dma_handle); } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 4608491..3fab204 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -98,7 +98,7 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size, EXPORT_SYMBOL(dma_alloc_noncoherent); static void *mips_dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, gfp_t gfp) + dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) { void *ret; @@ -132,7 +132,7 @@ void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, EXPORT_SYMBOL(dma_free_noncoherent); static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_handle) + dma_addr_t dma_handle, struct dma_attrs *attrs) { unsigned long addr = (unsigned long) vaddr; int order = get_order(size); @@ -323,8 +323,8 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, EXPORT_SYMBOL(dma_cache_sync); static struct dma_map_ops mips_default_dma_map_ops = { - .alloc_coherent = mips_dma_alloc_coherent, - .free_coherent = mips_dma_free_coherent, + .alloc = mips_dma_alloc_coherent, + .free = mips_dma_free_coherent, .map_page = mips_dma_map_page, .unmap_page = mips_dma_unmap_page, .map_sg = mips_dma_map_sg, -- 1.7.1.569.g6f426 From matt@console-pimps.org Tue Feb 14 12:42:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Feb 2012 12:42:52 +0100 (CET) Received: from arkanian.console-pimps.org ([212.110.184.194]:36682 "EHLO arkanian.console-pimps.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903621Ab2BNLmr (ORCPT ); Tue, 14 Feb 2012 12:42:47 +0100 Received: by arkanian.console-pimps.org (Postfix, from userid 1002) id D8C40C000D; Tue, 14 Feb 2012 11:42:44 +0000 (GMT) Received: from localhost (02dddf07.bb.sky.com [2.221.223.7]) by arkanian.console-pimps.org (Postfix) with ESMTPSA id D7982C000F; Tue, 14 Feb 2012 11:42:43 +0000 (GMT) From: Matt Fleming To: linux-arch@vger.kernel.org Cc: Oleg Nesterov , Andrew Morton , linux-kernel@vger.kernel.org, Matt Fleming , Al Viro , David Daney , linux-mips@linux-mips.org Subject: [PATCH 19/40] MIPS: Use set_current_blocked() and block_sigmask() Date: Tue, 14 Feb 2012 11:40:52 +0000 Message-Id: <1329219673-28711-20-git-send-email-matt@console-pimps.org> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1329219673-28711-1-git-send-email-matt@console-pimps.org> References: <1329219673-28711-1-git-send-email-matt@console-pimps.org> X-archive-position: 32424 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matt@console-pimps.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6245 Lines: 181 From: Matt Fleming As described in e6fa16ab ("signal: sigprocmask() should do retarget_shared_pending()") the modification of current->blocked is incorrect as we need to check whether the signal we're about to block is pending in the shared queue. Also, use the new helper function introduced in commit 5e6292c0f28f ("signal: add block_sigmask() for adding sigmask to current->blocked") which centralises the code for updating current->blocked after successfully delivering a signal and reduces the amount of duplicate code across architectures. In the past some architectures got this code wrong, so using this helper function should stop that from happening again. Cc: Oleg Nesterov Acked-by: Ralf Baechle Cc: Al Viro Cc: David Daney Cc: linux-mips@linux-mips.org Signed-off-by: Matt Fleming --- arch/mips/kernel/signal.c | 27 +++++---------------------- arch/mips/kernel/signal32.c | 20 ++++---------------- arch/mips/kernel/signal_n32.c | 10 ++-------- 3 files changed, 11 insertions(+), 46 deletions(-) diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index f852400..76084cc 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -256,11 +256,8 @@ asmlinkage int sys_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -285,11 +282,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -361,10 +355,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = blocked; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&blocked); sig = restore_sigcontext(®s, &frame->sf_sc); if (sig < 0) @@ -400,10 +391,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&set); sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext); if (sig < 0) @@ -579,12 +567,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info, if (ret) return ret; - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked, sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + block_sigmask(ka, sig); return ret; } diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index aae9866..902a889 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -290,11 +290,8 @@ asmlinkage int sys32_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -318,11 +315,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -488,10 +482,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = blocked; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&blocked); sig = restore_sigcontext32(®s, &frame->sf_sc); if (sig < 0) @@ -529,10 +520,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&set); sig = restore_sigcontext32(®s, &frame->rs_uc.uc_mcontext); if (sig < 0) diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index ee24d81..30fc7ff 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -94,11 +94,8 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) sigset_from_compat(&newset, &uset); sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -122,10 +119,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&set); sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext); if (sig < 0) -- 1.7.4.4 From venki@google.com Tue Feb 14 23:50:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Feb 2012 23:50:19 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:65036 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903656Ab2BNWuM (ORCPT ); Tue, 14 Feb 2012 23:50:12 +0100 Received: by pbcun1 with SMTP id un1so1015281pbc.36 for ; Tue, 14 Feb 2012 14:50:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=gamma; h=mime-version:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=yOhserrUfvkY3ZIJV3xIijVCgGVNyG2k9fouDdZjnZU=; b=wXjRMQrcRlvP18w5yv/Nnie/YSIPcaUazUGD35WW280QmzLqWaH9MwmCL9E+qhzxoG kfCVhuudaBpOtVIehr2zKS3uduYgdhirqQSx96NH6AnfUr3q7dk+SUm5l4Lz3ZHjU2kE Gu31lQOFEzY5JBWHt2ImGdox896QzAd5VodD8= MIME-Version: 1.0 Received: by 10.68.229.33 with SMTP id sn1mr62871765pbc.60.1329259805433; Tue, 14 Feb 2012 14:50:05 -0800 (PST) Received: by 10.68.229.33 with SMTP id sn1mr62871692pbc.60.1329259805260; Tue, 14 Feb 2012 14:50:05 -0800 (PST) Received: from tippy.mtv.corp.google.com (tippy.mtv.corp.google.com [172.18.96.130]) by mx.google.com with ESMTPS id y9sm6426972pbi.3.2012.02.14.14.50.03 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 14 Feb 2012 14:50:04 -0800 (PST) From: Venkatesh Pallipadi To: Rusty Russell Cc: Tony Luck , "Srivatsa S. Bhat" , Andrew Morton , KOSAKI Motohiro , KOSAKI Motohiro , Mike Travis , "Paul E. McKenney" , "Rafael J. Wysocki" , Paul Gortmaker , linux-kernel@vger.kernel.org, Richard Kuo , linux-hexagon@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Jeff Dike , Richard Weinberger , user-mode-linux-devel@lists.sourceforge.net Subject: [PATCH 0/3] Cleanup raw handling of online/possible map Date: Tue, 14 Feb 2012 14:49:41 -0800 Message-Id: <1329259784-20592-1-git-send-email-venki@google.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <87wr7pbwbz.fsf@rustcorp.com.au> References: <87wr7pbwbz.fsf@rustcorp.com.au> X-Gm-Message-State: ALoCoQml0hcSZ/cyBnHtJW8mrgvObgDBbcWx+nvbV6v53pqA69kOfqW017ZFwl+4VWleF+5KhOSz5rBBDuGsgMEEynNPtetnzYyJcAwegt2Ue7/AUrKxLPyd7Lq7FuaPtpSQ6VCBA9X19FUjcaahtl6s819YeGdnnu+k8ZaVB539od8GIDhHZXc= X-archive-position: 32425 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: venki@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 244 Lines: 10 > Yes, and the other architectures. Here are the patches for other instances I see in plain git grep. I have been brave (foolish) enough to send this without any testing. So, this comes with 'use it at your own risk' tag :-). Thanks, Venki From venki@google.com Tue Feb 14 23:51:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Feb 2012 23:51:36 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:38438 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903642Ab2BNWv3 (ORCPT ); Tue, 14 Feb 2012 23:51:29 +0100 Received: by pbcun1 with SMTP id un1so1016178pbc.36 for ; Tue, 14 Feb 2012 14:51:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=gamma; h=mime-version:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=XAsB5hnmXB+Qf6KfuZDjgJq+WUymHIeH20EJzRyKaac=; b=xBtXYpikdxlxwNGBu2hE0NCgMAUI8CsaJnLvGCgJy3EuBDz51hMwc6465hHgdNU7jN HWfv+t91/UROSfAmIwdoq7OR+ixMtIHsU79cGa5ot1Dc0TCvtaPXaFFjlME18CAUJ/Cz to54oGIIkkHlytfgWFenPaldooLylGW/JeSH8= MIME-Version: 1.0 Received: by 10.68.229.33 with SMTP id sn1mr62880246pbc.60.1329259883184; Tue, 14 Feb 2012 14:51:23 -0800 (PST) Received: by 10.68.229.33 with SMTP id sn1mr62880172pbc.60.1329259883001; Tue, 14 Feb 2012 14:51:23 -0800 (PST) Received: from tippy.mtv.corp.google.com (tippy.mtv.corp.google.com [172.18.96.130]) by mx.google.com with ESMTPS id y9sm6426972pbi.3.2012.02.14.14.51.21 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 14 Feb 2012 14:51:22 -0800 (PST) From: Venkatesh Pallipadi To: Rusty Russell Cc: Tony Luck , "Srivatsa S. Bhat" , Andrew Morton , KOSAKI Motohiro , KOSAKI Motohiro , Mike Travis , "Paul E. McKenney" , "Rafael J. Wysocki" , Paul Gortmaker , linux-kernel@vger.kernel.org, Richard Kuo , linux-hexagon@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Jeff Dike , Richard Weinberger , user-mode-linux-devel@lists.sourceforge.net, Venkatesh Pallipadi Subject: [PATCH 1/3] hexagon: Avoid raw handling of cpu_possible_map Date: Tue, 14 Feb 2012 14:49:42 -0800 Message-Id: <1329259784-20592-2-git-send-email-venki@google.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1329259784-20592-1-git-send-email-venki@google.com> References: <87wr7pbwbz.fsf@rustcorp.com.au> <1329259784-20592-1-git-send-email-venki@google.com> X-Gm-Message-State: ALoCoQlNKWsVbuGa9NjmIPvNJ2gBZoJ3UNJAOzZDBVtboUWiKhpF11poxnkfDZjrOYEstU/kgVyL8/yf8SQ1bFIeSOqXu4tHs7bOYR+ako3T7ZX1gYPEA6ZGmIIoW8stCE5uVheHKgdT8rezP5b4BrAmovD4F9UFNMOhEjEWeUCSfot773h3dj0= X-archive-position: 32426 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: venki@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 506 Lines: 21 Use set_cpu_possible instead. Signed-off-by: Venkatesh Pallipadi --- arch/hexagon/kernel/smp.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c index c871a2c..8962705 100644 --- a/arch/hexagon/kernel/smp.c +++ b/arch/hexagon/kernel/smp.c @@ -272,5 +272,5 @@ void smp_start_cpus(void) int i; for (i = 0; i < NR_CPUS; i++) - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); } -- 1.7.7.3 From venki@google.com Tue Feb 14 23:51:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Feb 2012 23:51:57 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:50788 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903721Ab2BNWvd (ORCPT ); Tue, 14 Feb 2012 23:51:33 +0100 Received: by mail-pw0-f49.google.com with SMTP id un1so1016177pbc.36 for ; Tue, 14 Feb 2012 14:51:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=gamma; h=mime-version:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=psl136/XZoyJUs945OjqLnHMlnq03KdyDx6J2qaidGA=; b=xavVDcD7kNYyy+rkAjVPpSxw+x9UtQ3AGtWg/yABe3QfvKN3JswCLkSP0UCuFzFEsS PHEBoou99wvUW8MM43yfXxwJ9Luw7BhFYkGQyj80H1TJMyd2xIXxM4JZqqItzHhN9EzF pKof4Z9zOX6AJJSCwSbEg0ahmh5fnsg3v9KWM= MIME-Version: 1.0 Received: by 10.68.212.130 with SMTP id nk2mr63046465pbc.69.1329259892080; Tue, 14 Feb 2012 14:51:32 -0800 (PST) Received: by 10.68.212.130 with SMTP id nk2mr63046390pbc.69.1329259891972; Tue, 14 Feb 2012 14:51:31 -0800 (PST) Received: from tippy.mtv.corp.google.com (tippy.mtv.corp.google.com [172.18.96.130]) by mx.google.com with ESMTPS id y9sm6426972pbi.3.2012.02.14.14.51.30 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 14 Feb 2012 14:51:31 -0800 (PST) From: Venkatesh Pallipadi To: Rusty Russell Cc: Tony Luck , "Srivatsa S. Bhat" , Andrew Morton , KOSAKI Motohiro , KOSAKI Motohiro , Mike Travis , "Paul E. McKenney" , "Rafael J. Wysocki" , Paul Gortmaker , linux-kernel@vger.kernel.org, Richard Kuo , linux-hexagon@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Jeff Dike , Richard Weinberger , user-mode-linux-devel@lists.sourceforge.net, Venkatesh Pallipadi Subject: [PATCH 2/3] mips: Avoid raw handling of cpu_possible_map/cpu_online_map Date: Tue, 14 Feb 2012 14:49:43 -0800 Message-Id: <1329259784-20592-3-git-send-email-venki@google.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1329259784-20592-1-git-send-email-venki@google.com> References: <87wr7pbwbz.fsf@rustcorp.com.au> <1329259784-20592-1-git-send-email-venki@google.com> X-Gm-Message-State: ALoCoQn8VYe2VZG/u6zSMdUsiiMEkvnyzpGfikt1n7sa0D1VCngMKELhXZIybcI4kW1ApZNbHXaDqBHI0nN2pCdq2NUVybxkoJDw2iSfuI+5HFXcEk5O3S1WYk57Q86DkNn1VkAlFYuJpeGHKs3GUFLEPMm9JzFa7uNpxY3DtOeLTK73GW1lznA= X-archive-position: 32427 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: venki@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4563 Lines: 145 Use set_cpu_* and init_cpu_* variants instead. Signed-off-by: Venkatesh Pallipadi --- arch/mips/cavium-octeon/smp.c | 2 +- arch/mips/kernel/smp.c | 4 ++-- arch/mips/netlogic/xlr/smp.c | 4 ++-- arch/mips/pmc-sierra/yosemite/smp.c | 4 ++-- arch/mips/sgi-ip27/ip27-smp.c | 2 +- arch/mips/sibyte/bcm1480/smp.c | 5 ++--- arch/mips/sibyte/sb1250/smp.c | 5 ++--- 7 files changed, 12 insertions(+), 14 deletions(-) diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index efcfff4..5cce09c 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -268,7 +268,7 @@ static int octeon_cpu_disable(void) spin_lock(&smp_reserve_lock); - cpu_clear(cpu, cpu_online_map); + set_cpu_online(cpu, false); cpu_clear(cpu, cpu_callin_map); local_irq_disable(); fixup_irqs(); diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 32c1e95..28777ff 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -148,7 +148,7 @@ static void stop_this_cpu(void *dummy) /* * Remove this CPU: */ - cpu_clear(smp_processor_id(), cpu_online_map); + set_cpu_online(smp_processor_id(), false); for (;;) { if (cpu_wait) (*cpu_wait)(); /* Wait if available. */ @@ -248,7 +248,7 @@ int __cpuinit __cpu_up(unsigned int cpu) while (!cpu_isset(cpu, cpu_callin_map)) udelay(100); - cpu_set(cpu, cpu_online_map); + set_cpu_online(cpu, true); return 0; } diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c index 080284d..8084221 100644 --- a/arch/mips/netlogic/xlr/smp.c +++ b/arch/mips/netlogic/xlr/smp.c @@ -154,7 +154,7 @@ void __init nlm_smp_setup(void) cpu_set(boot_cpu, phys_cpu_present_map); __cpu_number_map[boot_cpu] = 0; __cpu_logical_map[0] = boot_cpu; - cpu_set(0, cpu_possible_map); + set_cpu_possible(0, true); num_cpus = 1; for (i = 0; i < NR_CPUS; i++) { @@ -166,7 +166,7 @@ void __init nlm_smp_setup(void) cpu_set(i, phys_cpu_present_map); __cpu_number_map[i] = num_cpus; __cpu_logical_map[num_cpus] = i; - cpu_set(num_cpus, cpu_possible_map); + set_cpu_possible(num_cpus, true); ++num_cpus; } } diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c index 2608752..b2b23eb 100644 --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -155,10 +155,10 @@ static void __init yos_smp_setup(void) { int i; - cpus_clear(cpu_possible_map); + init_cpu_possible(cpumask_of(0)); for (i = 0; i < 2; i++) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = i; __cpu_logical_map[i] = i; } diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c index c6851df..735b43b 100644 --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c @@ -76,7 +76,7 @@ static int do_cpumask(cnodeid_t cnode, nasid_t nasid, int highest) /* Only let it join in if it's marked enabled */ if ((acpu->cpu_info.flags & KLINFO_ENABLE) && (tot_cpus_found != NR_CPUS)) { - cpu_set(cpuid, cpu_possible_map); + set_cpu_possible(cpuid, true); alloc_cpupda(cpuid, tot_cpus_found); cpus_found++; tot_cpus_found++; diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c index d667875..63d2211 100644 --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -147,14 +147,13 @@ static void __init bcm1480_smp_setup(void) { int i, num; - cpus_clear(cpu_possible_map); - cpu_set(0, cpu_possible_map); + init_cpu_possible(cpumask_of(0)); __cpu_number_map[0] = 0; __cpu_logical_map[0] = 0; for (i = 1, num = 0; i < NR_CPUS; i++) { if (cfe_cpu_stop(i) == 0) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = ++num; __cpu_logical_map[num] = i; } diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c index 38e7f6b..77f0df5 100644 --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c @@ -135,14 +135,13 @@ static void __init sb1250_smp_setup(void) { int i, num; - cpus_clear(cpu_possible_map); - cpu_set(0, cpu_possible_map); + init_cpu_possible(cpumask_of(0)); __cpu_number_map[0] = 0; __cpu_logical_map[0] = 0; for (i = 1, num = 0; i < NR_CPUS; i++) { if (cfe_cpu_stop(i) == 0) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = ++num; __cpu_logical_map[num] = i; } -- 1.7.7.3 From venki@google.com Tue Feb 14 23:52:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Feb 2012 23:53:03 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:58142 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903642Ab2BNWw4 (ORCPT ); Tue, 14 Feb 2012 23:52:56 +0100 Received: by pbcun1 with SMTP id un1so1017264pbc.36 for ; Tue, 14 Feb 2012 14:52:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=gamma; h=mime-version:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=G1uOMzHgzzP7ZeAyvXYF0gGf+HQmOoIOsfXAlX0EVpI=; b=y8rVfgFMJ803msfIH96qh8JPSFAMFr1rbrxpWvullywNL2bM8yd92VHKIEjiMTKi/C +0YwQDFfXaCWYnGqGrrnjWaZXmJVO+uXuc3OjN2jqV+1Zdmj8CN3bkq3sBea4rc8NxG2 M+9aw25Ejr0Tgbzaqiin8DoWQbr63wU5yueM4= MIME-Version: 1.0 Received: by 10.68.231.201 with SMTP id ti9mr63646675pbc.73.1329259970617; Tue, 14 Feb 2012 14:52:50 -0800 (PST) Received: by 10.68.231.201 with SMTP id ti9mr63646609pbc.73.1329259970460; Tue, 14 Feb 2012 14:52:50 -0800 (PST) Received: from tippy.mtv.corp.google.com (tippy.mtv.corp.google.com [172.18.96.130]) by mx.google.com with ESMTPS id y9sm6426972pbi.3.2012.02.14.14.52.48 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 14 Feb 2012 14:52:49 -0800 (PST) From: Venkatesh Pallipadi To: Rusty Russell Cc: Tony Luck , "Srivatsa S. Bhat" , Andrew Morton , KOSAKI Motohiro , KOSAKI Motohiro , Mike Travis , "Paul E. McKenney" , "Rafael J. Wysocki" , Paul Gortmaker , linux-kernel@vger.kernel.org, Richard Kuo , linux-hexagon@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Jeff Dike , Richard Weinberger , user-mode-linux-devel@lists.sourceforge.net, Venkatesh Pallipadi Subject: [PATCH 3/3] um: Avoid raw handling of cpu_online_map Date: Tue, 14 Feb 2012 14:49:44 -0800 Message-Id: <1329259784-20592-4-git-send-email-venki@google.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1329259784-20592-1-git-send-email-venki@google.com> References: <87wr7pbwbz.fsf@rustcorp.com.au> <1329259784-20592-1-git-send-email-venki@google.com> X-Gm-Message-State: ALoCoQkpJpCkjOUXzOq5LnZnamNu3ej5wSfHFgQSi6glhLrvZDc0yUVz3et2KHtUarlC6Eef6yvz5zYcOHzonfSqAwBKQ6giQA1BkXnzQk7AYy22T1f3Ek261a+MJ5CbrYep742/cB4uLSiSokeKQUHsKwpHr0EkAVTMTBWgED8HJnnNmkbn2X4= X-archive-position: 32428 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: venki@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1578 Lines: 57 Use init_cpu_online and set_cpu_online instead. Signed-off-by: Venkatesh Pallipadi --- arch/um/kernel/skas/process.c | 2 +- arch/um/kernel/smp.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/um/kernel/skas/process.c b/arch/um/kernel/skas/process.c index 2e9852c..5daa0f5 100644 --- a/arch/um/kernel/skas/process.c +++ b/arch/um/kernel/skas/process.c @@ -41,7 +41,7 @@ static int __init start_kernel_proc(void *unused) cpu_tasks[0].pid = pid; cpu_tasks[0].task = current; #ifdef CONFIG_SMP - cpu_online_map = cpumask_of_cpu(0); + init_cpu_online(cpumask_of(0)); #endif start_kernel(); return 0; diff --git a/arch/um/kernel/smp.c b/arch/um/kernel/smp.c index 155206a..b5d2ca9 100644 --- a/arch/um/kernel/smp.c +++ b/arch/um/kernel/smp.c @@ -76,7 +76,7 @@ static int idle_proc(void *cpup) cpu_relax(); notify_cpu_starting(cpu); - cpu_set(cpu, cpu_online_map); + set_cpu_online(cpu, true); default_idle(); return 0; } @@ -110,8 +110,8 @@ void smp_prepare_cpus(unsigned int maxcpus) for (i = 0; i < ncpus; ++i) set_cpu_possible(i, true); - cpu_clear(me, cpu_online_map); - cpu_set(me, cpu_online_map); + set_cpu_online(me, false); + set_cpu_online(me, true); cpu_set(me, cpu_callin_map); err = os_pipe(cpu_data[me].ipi_pipe, 1, 1); @@ -138,7 +138,7 @@ void smp_prepare_cpus(unsigned int maxcpus) void smp_prepare_boot_cpu(void) { - cpu_set(smp_processor_id(), cpu_online_map); + set_cpu_online(smp_processor_id(), true); } int __cpu_up(unsigned int cpu) -- 1.7.7.3 From rusty@rustcorp.com.au Wed Feb 15 06:00:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Feb 2012 06:00:24 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:59829 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903646Ab2BOFAQ (ORCPT ); Wed, 15 Feb 2012 06:00:16 +0100 Received: by ozlabs.org (Postfix, from userid 1011) id D5C081007D4; Wed, 15 Feb 2012 16:00:11 +1100 (EST) From: Rusty Russell CC: Tony Luck , Fenghua Yu , linux-ia64@vger.kernel.org CC: Ralf Baechle , linux-mips@linux-mips.org CC: Chris Metcalf CC: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org To: linux-kernel@vger.kernel.org Message-ID: <1329281884.8121.rusty@rustcorp.com.au> Date: Wed, 15 Feb 2012 15:28:04 +1030 Subject: [PATCH 11/12] documentation: remove references to cpu_*_map. X-archive-position: 32429 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rusty@rustcorp.com.au Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8274 Lines: 183 From: Rusty Russell This has been obsolescent for a while, fix documentation and misc comments. Signed-off-by: Rusty Russell --- Documentation/cpu-hotplug.txt | 22 +++++++++++----------- arch/ia64/kernel/acpi.c | 2 +- arch/mips/cavium-octeon/smp.c | 2 +- arch/mips/pmc-sierra/yosemite/smp.c | 2 +- arch/mips/sibyte/bcm1480/smp.c | 2 +- arch/tile/kernel/setup.c | 2 +- arch/x86/xen/enlighten.c | 2 +- init/Kconfig | 4 ++-- 8 files changed, 19 insertions(+), 19 deletions(-) diff --git a/Documentation/cpu-hotplug.txt b/Documentation/cpu-hotplug.txt --- a/Documentation/cpu-hotplug.txt +++ b/Documentation/cpu-hotplug.txt @@ -47,7 +47,7 @@ maxcpus=n Restrict boot time cpus to other cpus later online, read FAQ's for more info. additional_cpus=n (*) Use this to limit hotpluggable cpus. This option sets - cpu_possible_map = cpu_present_map + additional_cpus + cpu_possible_mask = cpu_present_mask + additional_cpus cede_offline={"off","on"} Use this option to disable/enable putting offlined processors to an extended H_CEDE state on @@ -64,11 +64,11 @@ should only rely on this to count the # on the apicid values in those tables for disabled apics. In the event BIOS doesn't mark such hot-pluggable cpus as disabled entries, one could use this parameter "additional_cpus=x" to represent those cpus in the -cpu_possible_map. +cpu_possible_mask. possible_cpus=n [s390,x86_64] use this to set hotpluggable cpus. This option sets possible_cpus bits in - cpu_possible_map. Thus keeping the numbers of bits set + cpu_possible_mask. Thus keeping the numbers of bits set constant even if the machine gets rebooted. CPU maps and such @@ -76,7 +76,7 @@ CPU maps and such [More on cpumaps and primitive to manipulate, please check include/linux/cpumask.h that has more descriptive text.] -cpu_possible_map: Bitmap of possible CPUs that can ever be available in the +cpu_possible_mask: Bitmap of possible CPUs that can ever be available in the system. This is used to allocate some boot time memory for per_cpu variables that aren't designed to grow/shrink as CPUs are made available or removed. Once set during boot time discovery phase, the map is static, i.e no bits @@ -84,13 +84,13 @@ are added or removed anytime. Trimming upfront can save some boot time memory. See below for how we use heuristics in x86_64 case to keep this under check. -cpu_online_map: Bitmap of all CPUs currently online. Its set in __cpu_up() +cpu_online_mask: Bitmap of all CPUs currently online. Its set in __cpu_up() after a cpu is available for kernel scheduling and ready to receive interrupts from devices. Its cleared when a cpu is brought down using __cpu_disable(), before which all OS services including interrupts are migrated to another target CPU. -cpu_present_map: Bitmap of CPUs currently present in the system. Not all +cpu_present_mask: Bitmap of CPUs currently present in the system. Not all of them may be online. When physical hotplug is processed by the relevant subsystem (e.g ACPI) can change and new bit either be added or removed from the map depending on the event is hot-add/hot-remove. There are currently @@ -99,22 +99,22 @@ at which time hotplug is disabled. You really dont need to manipulate any of the system cpu maps. They should be read-only for most use. When setting up per-cpu resources almost always use -cpu_possible_map/for_each_possible_cpu() to iterate. +cpu_possible_mask/for_each_possible_cpu() to iterate. Never use anything other than cpumask_t to represent bitmap of CPUs. #include - for_each_possible_cpu - Iterate over cpu_possible_map - for_each_online_cpu - Iterate over cpu_online_map - for_each_present_cpu - Iterate over cpu_present_map + for_each_possible_cpu - Iterate over cpu_possible_mask + for_each_online_cpu - Iterate over cpu_online_mask + for_each_present_cpu - Iterate over cpu_present_mask for_each_cpu_mask(x,mask) - Iterate over some random collection of cpu mask. #include get_online_cpus() and put_online_cpus(): The above calls are used to inhibit cpu hotplug operations. While the -cpu_hotplug.refcount is non zero, the cpu_online_map will not change. +cpu_hotplug.refcount is non zero, the cpu_online_mask will not change. If you merely need to avoid cpus going away, you could also use preempt_disable() and preempt_enable() for those sections. Just remember the critical section cannot call any diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c --- a/arch/ia64/kernel/acpi.c +++ b/arch/ia64/kernel/acpi.c @@ -840,7 +840,7 @@ static __init int setup_additional_cpus( early_param("additional_cpus", setup_additional_cpus); /* - * cpu_possible_map should be static, it cannot change as CPUs + * cpu_possible_mask should be static, it cannot change as CPUs * are onlined, or offlined. The reason is per-cpu data-structures * are allocated by some modules at init time, and dont expect to * do this dynamically on cpu arrival/departure. diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -78,7 +78,7 @@ static inline void octeon_send_ipi_mask( } /** - * Detect available CPUs, populate cpu_possible_map + * Detect available CPUs, populate cpu_possible_mask */ static void octeon_smp_hotplug_setup(void) { diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -146,7 +146,7 @@ static void __cpuinit yos_boot_secondary } /* - * Detect available CPUs, populate cpu_possible_map before smp_init + * Detect available CPUs, populate cpu_possible_mask before smp_init * * We don't want to start the secondary CPU yet nor do we have a nice probing * feature in PMON so we just assume presence of the secondary core. diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -138,7 +138,7 @@ static void __cpuinit bcm1480_boot_secon /* * Use CFE to find out how many CPUs are available, setting up - * cpu_possible_map and the logical/physical mappings. + * cpu_possible_mask and the logical/physical mappings. * XXXKW will the boot CPU ever not be physical 0? * * Common setup before any secondaries are started diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c --- a/arch/tile/kernel/setup.c +++ b/arch/tile/kernel/setup.c @@ -1100,7 +1100,7 @@ EXPORT_SYMBOL(hash_for_home_map); /* * cpu_cacheable_map lists all the cpus whose caches the hypervisor can - * flush on our behalf. It is set to cpu_possible_map OR'ed with + * flush on our behalf. It is set to cpu_possible_mask OR'ed with * hash_for_home_map, and it is what should be passed to * hv_flush_remote() to flush all caches. Note that if there are * dedicated hypervisor driver tiles that have authorized use of their diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -876,7 +876,7 @@ void xen_setup_shared_info(void) xen_setup_mfn_list_list(); } -/* This is called once we have the cpu_possible_map */ +/* This is called once we have the cpu_possible_mask */ void xen_setup_vcpu_info_placement(void) { int cpu; diff --git a/init/Kconfig b/init/Kconfig --- a/init/Kconfig +++ b/init/Kconfig @@ -1423,8 +1423,8 @@ endif # MODULES config INIT_ALL_POSSIBLE bool help - Back when each arch used to define their own cpu_online_map and - cpu_possible_map, some of them chose to initialize cpu_possible_map + Back when each arch used to define their own cpu_online_mask and + cpu_possible_mask, some of them chose to initialize cpu_possible_mask with all 1s, and others with all 0s. When they were centralised, it was better to provide this option than to break all the archs and have several arch maintainers pursuing me down dark alleys. From rusty@rustcorp.com.au Wed Feb 15 06:00:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Feb 2012 06:00:53 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:58135 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903644Ab2BOFAQ (ORCPT ); Wed, 15 Feb 2012 06:00:16 +0100 Received: by ozlabs.org (Postfix, from userid 1011) id 372EE1007D8; Wed, 15 Feb 2012 16:00:12 +1100 (EST) From: Rusty Russell CC: linux-kernel@vger.kernel.org To: Ralf Baechle , linux-mips@linux-mips.org Message-ID: <1329281884.26321.rusty@rustcorp.com.au> Date: Wed, 15 Feb 2012 15:28:04 +1030 Subject: [PATCH 4/12] arch/mips: remove references to cpu_*_map. X-archive-position: 32430 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rusty@rustcorp.com.au Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9466 Lines: 297 From: Rusty Russell This has been obsolescent for a while; time for the final push. Also took the chance to get rid of old cpus_* in favor of cpumask_*. Signed-off-by: Rusty Russell Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/cavium-octeon/smp.c | 2 +- arch/mips/kernel/mips-mt-fpaff.c | 2 +- arch/mips/kernel/proc.c | 2 +- arch/mips/kernel/smp-bmips.c | 2 +- arch/mips/kernel/smp.c | 27 ++++++++++++--------------- arch/mips/kernel/smtc.c | 2 +- arch/mips/mm/c-octeon.c | 6 +++--- arch/mips/netlogic/common/smp.c | 6 +++--- arch/mips/pmc-sierra/yosemite/smp.c | 6 +++--- arch/mips/sgi-ip27/ip27-smp.c | 2 +- arch/mips/sibyte/bcm1480/smp.c | 5 ++--- arch/mips/sibyte/sb1250/smp.c | 7 +++---- 12 files changed, 32 insertions(+), 37 deletions(-) diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -268,7 +268,7 @@ static int octeon_cpu_disable(void) spin_lock(&smp_reserve_lock); - cpu_clear(cpu, cpu_online_map); + set_cpu_online(cpu, false); cpu_clear(cpu, cpu_callin_map); local_irq_disable(); fixup_irqs(); diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c --- a/arch/mips/kernel/mips-mt-fpaff.c +++ b/arch/mips/kernel/mips-mt-fpaff.c @@ -173,7 +173,7 @@ asmlinkage long mipsmt_sys_sched_getaffi if (retval) goto out_unlock; - cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map); + cpumask_and(&mask, &p->thread.user_cpus_allowed, cpu_possible_mask); out_unlock: read_unlock(&tasklist_lock); diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -25,7 +25,7 @@ static int show_cpuinfo(struct seq_file int i; #ifdef CONFIG_SMP - if (!cpu_isset(n, cpu_online_map)) + if (!cpu_online(n)) return 0; #endif diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -319,7 +319,7 @@ static int bmips_cpu_disable(void) pr_info("SMP: CPU%d is offline\n", cpu); - cpu_clear(cpu, cpu_online_map); + set_cpu_online(cpu, false); cpu_clear(cpu, cpu_callin_map); local_flush_tlb_all(); diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -148,7 +148,7 @@ static void stop_this_cpu(void *dummy) /* * Remove this CPU: */ - cpu_clear(smp_processor_id(), cpu_online_map); + set_cpu_online(smp_processor_id(), false); for (;;) { if (cpu_wait) (*cpu_wait)(); /* Wait if available. */ @@ -174,7 +174,7 @@ void __init smp_prepare_cpus(unsigned in mp_ops->prepare_cpus(max_cpus); set_cpu_sibling_map(0); #ifndef CONFIG_HOTPLUG_CPU - init_cpu_present(&cpu_possible_map); + init_cpu_present(cpu_possible_mask); #endif } @@ -248,7 +248,7 @@ int __cpuinit __cpu_up(unsigned int cpu) while (!cpu_isset(cpu, cpu_callin_map)) udelay(100); - cpu_set(cpu, cpu_online_map); + set_cpu_online(cpu, true); return 0; } @@ -320,13 +320,12 @@ void flush_tlb_mm(struct mm_struct *mm) if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { smp_on_other_tlbs(flush_tlb_mm_ipi, mm); } else { - cpumask_t mask = cpu_online_map; unsigned int cpu; - cpu_clear(smp_processor_id(), mask); - for_each_cpu_mask(cpu, mask) - if (cpu_context(cpu, mm)) + for_each_online_cpu(cpu) { + if (cpu != smp_processor_id() && cpu_context(cpu, mm)) cpu_context(cpu, mm) = 0; + } } local_flush_tlb_mm(mm); @@ -360,13 +359,12 @@ void flush_tlb_range(struct vm_area_stru smp_on_other_tlbs(flush_tlb_range_ipi, &fd); } else { - cpumask_t mask = cpu_online_map; unsigned int cpu; - cpu_clear(smp_processor_id(), mask); - for_each_cpu_mask(cpu, mask) - if (cpu_context(cpu, mm)) + for_each_online_cpu(cpu) { + if (cpu != smp_processor_id() && cpu_context(cpu, mm)) cpu_context(cpu, mm) = 0; + } } local_flush_tlb_range(vma, start, end); preempt_enable(); @@ -407,13 +405,12 @@ void flush_tlb_page(struct vm_area_struc smp_on_other_tlbs(flush_tlb_page_ipi, &fd); } else { - cpumask_t mask = cpu_online_map; unsigned int cpu; - cpu_clear(smp_processor_id(), mask); - for_each_cpu_mask(cpu, mask) - if (cpu_context(cpu, vma->vm_mm)) + for_each_online_cpu(cpu) { + if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) cpu_context(cpu, vma->vm_mm) = 0; + } } local_flush_tlb_page(vma, page); preempt_enable(); diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -292,7 +292,7 @@ static void smtc_configure_tlb(void) * possibly leave some TCs/VPEs as "slave" processors. * * Use c0_MVPConf0 to find out how many TCs are available, setting up - * cpu_possible_map and the logical/physical mappings. + * cpu_possible_mask and the logical/physical mappings. */ int __init smtc_build_cpu_map(int start_cpu_slot) diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -81,9 +81,9 @@ static void octeon_flush_icache_all_core if (vma) mask = *mm_cpumask(vma->vm_mm); else - mask = cpu_online_map; - cpu_clear(cpu, mask); - for_each_cpu_mask(cpu, mask) + mask = *cpu_online_mask; + cpumask_clear(&mask, cpu); + for_each_cpu(cpu, &mask) octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); preempt_enable(); diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -165,7 +165,7 @@ void __init nlm_smp_setup(void) cpu_set(boot_cpu, phys_cpu_present_map); __cpu_number_map[boot_cpu] = 0; __cpu_logical_map[0] = boot_cpu; - cpu_set(0, cpu_possible_map); + set_cpu_possible(0, true); num_cpus = 1; for (i = 0; i < NR_CPUS; i++) { @@ -177,14 +177,14 @@ void __init nlm_smp_setup(void) cpu_set(i, phys_cpu_present_map); __cpu_number_map[i] = num_cpus; __cpu_logical_map[num_cpus] = i; - cpu_set(num_cpus, cpu_possible_map); + set_cpu_possible(num_cpus, true); ++num_cpus; } } pr_info("Phys CPU present map: %lx, possible map %lx\n", (unsigned long)phys_cpu_present_map.bits[0], - (unsigned long)cpu_possible_map.bits[0]); + (unsigned long)cpumask_bits(cpu_possible_mask)[0]); pr_info("Detected %i Slave CPU(s)\n", num_cpus); nlm_set_nmi_handler(nlm_boot_secondary_cpus); diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -155,10 +155,10 @@ static void __init yos_smp_setup(void) { int i; - cpus_clear(cpu_possible_map); + init_cpu_possible(cpu_none_mask); for (i = 0; i < 2; i++) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = i; __cpu_logical_map[i] = i; } @@ -169,7 +169,7 @@ static void __init yos_prepare_cpus(unsi /* * Be paranoid. Enable the IPI only if we're really about to go SMP. */ - if (cpus_weight(cpu_possible_map)) + if (num_possible_cpus()) set_c0_status(STATUSF_IP5); } diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c @@ -76,7 +76,7 @@ static int do_cpumask(cnodeid_t cnode, n /* Only let it join in if it's marked enabled */ if ((acpu->cpu_info.flags & KLINFO_ENABLE) && (tot_cpus_found != NR_CPUS)) { - cpu_set(cpuid, cpu_possible_map); + set_cpu_possible(cpuid, true); alloc_cpupda(cpuid, tot_cpus_found); cpus_found++; tot_cpus_found++; diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -147,14 +147,13 @@ static void __init bcm1480_smp_setup(voi { int i, num; - cpus_clear(cpu_possible_map); - cpu_set(0, cpu_possible_map); + init_cpu_possible(cpumask_of(0)); __cpu_number_map[0] = 0; __cpu_logical_map[0] = 0; for (i = 1, num = 0; i < NR_CPUS; i++) { if (cfe_cpu_stop(i) == 0) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = ++num; __cpu_logical_map[num] = i; } diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c @@ -126,7 +126,7 @@ static void __cpuinit sb1250_boot_second /* * Use CFE to find out how many CPUs are available, setting up - * cpu_possible_map and the logical/physical mappings. + * cpu_possible_mask and the logical/physical mappings. * XXXKW will the boot CPU ever not be physical 0? * * Common setup before any secondaries are started @@ -135,14 +135,13 @@ static void __init sb1250_smp_setup(void { int i, num; - cpus_clear(cpu_possible_map); - cpu_set(0, cpu_possible_map); + init_cpu_possible(cpumask_of(0)); __cpu_number_map[0] = 0; __cpu_logical_map[0] = 0; for (i = 1, num = 0; i < NR_CPUS; i++) { if (cfe_cpu_stop(i) == 0) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = ++num; __cpu_logical_map[num] = i; } From srivatsa.bhat@linux.vnet.ibm.com Wed Feb 15 10:20:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Feb 2012 10:20:42 +0100 (CET) Received: from e23smtp09.au.ibm.com ([202.81.31.142]:51519 "EHLO e23smtp09.au.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903645Ab2BOJUe (ORCPT ); Wed, 15 Feb 2012 10:20:34 +0100 Received: from /spool/local by e23smtp09.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 15 Feb 2012 10:11:36 +1000 Received: from d23relay04.au.ibm.com (202.81.31.246) by e23smtp09.au.ibm.com (202.81.31.206) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Wed, 15 Feb 2012 10:11:33 +1000 Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay04.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q1F9EwJI3289116; Wed, 15 Feb 2012 20:15:03 +1100 Received: from d23av04.au.ibm.com (loopback [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q1F9K6AN013885; Wed, 15 Feb 2012 20:20:06 +1100 Received: from srivatsabhat.in.ibm.com (srivatsabhat.in.ibm.com [9.124.35.180]) by d23av04.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q1F9K3eB013769; Wed, 15 Feb 2012 20:20:03 +1100 Message-ID: <4F3B78C2.7040709@linux.vnet.ibm.com> Date: Wed, 15 Feb 2012 14:50:02 +0530 From: "Srivatsa S. Bhat" User-Agent: Mozilla/5.0 (X11; Linux i686; rv:9.0) Gecko/20111222 Thunderbird/9.0 MIME-Version: 1.0 To: Rusty Russell CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Venkatesh Pallipadi , "akpm@linux-foundation.org" Subject: Re: [PATCH 4/12] arch/mips: remove references to cpu_*_map. References: <1329281884.26321.rusty@rustcorp.com.au> In-Reply-To: <1329281884.26321.rusty@rustcorp.com.au> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit x-cbid: 12021500-3568-0000-0000-000001372DF8 X-archive-position: 32431 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: srivatsa.bhat@linux.vnet.ibm.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4427 Lines: 150 On 02/15/2012 10:28 AM, Rusty Russell wrote: > From: Rusty Russell > > This has been obsolescent for a while; time for the final push. > > Also took the chance to get rid of old cpus_* in favor of cpumask_*. > > Signed-off-by: Rusty Russell > Cc: Ralf Baechle > Cc: linux-mips@linux-mips.org > --- [...] > diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c > --- a/arch/mips/kernel/smp.c > +++ b/arch/mips/kernel/smp.c > @@ -148,7 +148,7 @@ static void stop_this_cpu(void *dummy) > /* > * Remove this CPU: > */ > - cpu_clear(smp_processor_id(), cpu_online_map); > + set_cpu_online(smp_processor_id(), false); > for (;;) { > if (cpu_wait) > (*cpu_wait)(); /* Wait if available. */ > @@ -174,7 +174,7 @@ void __init smp_prepare_cpus(unsigned in > mp_ops->prepare_cpus(max_cpus); > set_cpu_sibling_map(0); > #ifndef CONFIG_HOTPLUG_CPU > - init_cpu_present(&cpu_possible_map); > + init_cpu_present(cpu_possible_mask); > #endif > } > > @@ -248,7 +248,7 @@ int __cpuinit __cpu_up(unsigned int cpu) > while (!cpu_isset(cpu, cpu_callin_map)) > udelay(100); > > - cpu_set(cpu, cpu_online_map); > + set_cpu_online(cpu, true); > > return 0; > } > @@ -320,13 +320,12 @@ void flush_tlb_mm(struct mm_struct *mm) > if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { > smp_on_other_tlbs(flush_tlb_mm_ipi, mm); > } else { > - cpumask_t mask = cpu_online_map; > unsigned int cpu; > > - cpu_clear(smp_processor_id(), mask); > - for_each_cpu_mask(cpu, mask) > - if (cpu_context(cpu, mm)) > + for_each_online_cpu(cpu) { > + if (cpu != smp_processor_id() && cpu_context(cpu, mm)) > cpu_context(cpu, mm) = 0; > + } Strictly speaking, this one is not a mere cleanup. It causes a subtle change in behaviour: earlier, it used to iterate over a local copy of cpu_online_mask, which wouldn't change. However, with this patch, it will iterate directly over cpu_online_mask, which can change underneath. (The preempt_disable() won't stop new CPUs from coming in.. it only prevents CPUs from going offline, that too provided that we use stop_machine stuff for CPU offline, which we do currently.) > } > local_flush_tlb_mm(mm); > > @@ -360,13 +359,12 @@ void flush_tlb_range(struct vm_area_stru > > smp_on_other_tlbs(flush_tlb_range_ipi, &fd); > } else { > - cpumask_t mask = cpu_online_map; > unsigned int cpu; > > - cpu_clear(smp_processor_id(), mask); > - for_each_cpu_mask(cpu, mask) > - if (cpu_context(cpu, mm)) > + for_each_online_cpu(cpu) { > + if (cpu != smp_processor_id() && cpu_context(cpu, mm)) > cpu_context(cpu, mm) = 0; > + } > } Same here. > local_flush_tlb_range(vma, start, end); > preempt_enable(); > @@ -407,13 +405,12 @@ void flush_tlb_page(struct vm_area_struc > > smp_on_other_tlbs(flush_tlb_page_ipi, &fd); > } else { > - cpumask_t mask = cpu_online_map; > unsigned int cpu; > > - cpu_clear(smp_processor_id(), mask); > - for_each_cpu_mask(cpu, mask) > - if (cpu_context(cpu, vma->vm_mm)) > + for_each_online_cpu(cpu) { > + if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) > cpu_context(cpu, vma->vm_mm) = 0; > + } > } And here too. > local_flush_tlb_page(vma, page); > preempt_enable(); > diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c > --- a/arch/mips/kernel/smtc.c > +++ b/arch/mips/kernel/smtc.c > @@ -292,7 +292,7 @@ static void smtc_configure_tlb(void) > * possibly leave some TCs/VPEs as "slave" processors. > * > * Use c0_MVPConf0 to find out how many TCs are available, setting up > - * cpu_possible_map and the logical/physical mappings. > + * cpu_possible_mask and the logical/physical mappings. > */ > > int __init smtc_build_cpu_map(int start_cpu_slot) > diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c > --- a/arch/mips/mm/c-octeon.c > +++ b/arch/mips/mm/c-octeon.c > @@ -81,9 +81,9 @@ static void octeon_flush_icache_all_core > if (vma) > mask = *mm_cpumask(vma->vm_mm); > else > - mask = cpu_online_map; > - cpu_clear(cpu, mask); > - for_each_cpu_mask(cpu, mask) > + mask = *cpu_online_mask; > + cpumask_clear(&mask, cpu); This should be cpumask_clear_cpu(cpu, &mask); > + for_each_cpu(cpu, &mask) > octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); > > preempt_enable(); Regards, Srivatsa S. Bhat From srivatsa.bhat@linux.vnet.ibm.com Wed Feb 15 10:29:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Feb 2012 10:29:40 +0100 (CET) Received: from e28smtp08.in.ibm.com ([122.248.162.8]:56504 "EHLO e28smtp08.in.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903643Ab2BOJ3b (ORCPT ); Wed, 15 Feb 2012 10:29:31 +0100 Received: from /spool/local by e28smtp08.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 15 Feb 2012 14:59:23 +0530 Received: from d28relay04.in.ibm.com (9.184.220.61) by e28smtp08.in.ibm.com (192.168.1.138) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Wed, 15 Feb 2012 14:59:20 +0530 Received: from d28av04.in.ibm.com (d28av04.in.ibm.com [9.184.220.66]) by d28relay04.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q1F9TJmh3018874; Wed, 15 Feb 2012 14:59:19 +0530 Received: from d28av04.in.ibm.com (loopback [127.0.0.1]) by d28av04.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q1F9TIS1003982; Wed, 15 Feb 2012 20:29:18 +1100 Received: from srivatsabhat.in.ibm.com (srivatsabhat.in.ibm.com [9.124.35.180]) by d28av04.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q1F9TIBa003957; Wed, 15 Feb 2012 20:29:18 +1100 Message-ID: <4F3B7AED.1070309@linux.vnet.ibm.com> Date: Wed, 15 Feb 2012 14:59:17 +0530 From: "Srivatsa S. Bhat" User-Agent: Mozilla/5.0 (X11; Linux i686; rv:9.0) Gecko/20111222 Thunderbird/9.0 MIME-Version: 1.0 To: Rusty Russell CC: linux-kernel@vger.kernel.org, Tony Luck , Fenghua Yu , linux-ia64@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Chris Metcalf , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Venkatesh Pallipadi , "akpm@linux-foundation.org" Subject: Re: [PATCH 11/12] documentation: remove references to cpu_*_map. References: <1329281884.8121.rusty@rustcorp.com.au> In-Reply-To: <1329281884.8121.rusty@rustcorp.com.au> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit x-cbid: 12021509-2000-0000-0000-0000066BA06E X-archive-position: 32432 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: srivatsa.bhat@linux.vnet.ibm.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 337 Lines: 18 On 02/15/2012 10:28 AM, Rusty Russell wrote: > From: Rusty Russell > > This has been obsolescent for a while, fix documentation and > misc comments. > > Signed-off-by: Rusty Russell > --- Reviewed-by: Srivatsa S. Bhat Regards, Srivatsa S. Bhat From danny.kukawka@bisect.de Wed Feb 15 20:19:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Feb 2012 20:20:08 +0100 (CET) Received: from wp188.webpack.hosteurope.de ([80.237.132.195]:49130 "EHLO wp188.webpack.hosteurope.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903658Ab2BOTT7 (ORCPT ); Wed, 15 Feb 2012 20:19:59 +0100 Received: from nat.nue.novell.com ([195.135.221.2] helo=g231.suse.de); authenticated by wp188.webpack.hosteurope.de running ExIM with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) id 1RxkOO-0001nD-3Y; Wed, 15 Feb 2012 20:19:52 +0100 From: Danny Kukawka To: Ralf Baechle Cc: Danny Kukawka , Kevin Cernekee , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH] arch/mips/kernel/smp-bmips.c included linux/init.h twice Date: Wed, 15 Feb 2012 20:19:49 +0100 Message-Id: <1329333589-31828-1-git-send-email-danny.kukawka@bisect.de> X-Mailer: git-send-email 1.7.8.3 X-bounce-key: webpack.hosteurope.de;danny.kukawka@bisect.de;1329333599;1877811c; X-archive-position: 32433 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: danny.kukawka@bisect.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 623 Lines: 23 arch/mips/kernel/smp-bmips.c included 'linux/init.h' twice, remove the duplicate. Signed-off-by: Danny Kukawka --- arch/mips/kernel/smp-bmips.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 58fe71a..64978e9 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include -- 1.7.8.3 From rusty@rustcorp.com.au Thu Feb 16 02:51:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Feb 2012 02:51:24 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:41386 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903661Ab2BPBvR (ORCPT ); Thu, 16 Feb 2012 02:51:17 +0100 Received: by ozlabs.org (Postfix, from userid 1011) id 8B9DB1007D4; Thu, 16 Feb 2012 12:51:13 +1100 (EST) From: Rusty Russell To: "Srivatsa S. Bhat" Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Venkatesh Pallipadi , "akpm\@linux-foundation.org" Subject: Re: [PATCH 4/12] arch/mips: remove references to cpu_*_map. In-Reply-To: <4F3B78C2.7040709@linux.vnet.ibm.com> References: <1329281884.26321.rusty@rustcorp.com.au> <4F3B78C2.7040709@linux.vnet.ibm.com> User-Agent: Notmuch/0.6.1-1 (http://notmuchmail.org) Emacs/23.3.1 (i686-pc-linux-gnu) Date: Thu, 16 Feb 2012 10:29:24 +1030 Message-ID: <87hayrbqcj.fsf@rustcorp.com.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-archive-position: 32434 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rusty@rustcorp.com.au Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1296 Lines: 34 On Wed, 15 Feb 2012 14:50:02 +0530, "Srivatsa S. Bhat" wrote: > > - cpu_clear(smp_processor_id(), mask); > > - for_each_cpu_mask(cpu, mask) > > - if (cpu_context(cpu, mm)) > > + for_each_online_cpu(cpu) { > > + if (cpu != smp_processor_id() && cpu_context(cpu, mm)) > > cpu_context(cpu, mm) = 0; > > + } > > > Strictly speaking, this one is not a mere cleanup. It causes a subtle change in > behaviour: earlier, it used to iterate over a local copy of cpu_online_mask, which > wouldn't change. However, with this patch, it will iterate directly over > cpu_online_mask, which can change underneath. (The preempt_disable() won't stop > new CPUs from coming in.. it only prevents CPUs from going offline, that too > provided that we use stop_machine stuff for CPU offline, which we do currently.) There's a preempt_disable() around this whole function, so online_mask can't change. Same with the others. > > + mask = *cpu_online_mask; > > + cpumask_clear(&mask, cpu); > > > This should be cpumask_clear_cpu(cpu, &mask); Good catch. I copied the bitmask ops, and continually regret it. I've rolled all these together with your fixes, added your ia64 patch, and am rebasing to -next now, so I can hand this all across to akpm. Thanks, Rusty. From rusty@rustcorp.com.au Thu Feb 16 04:51:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Feb 2012 04:52:08 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:40437 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903662Ab2BPDv7 (ORCPT ); Thu, 16 Feb 2012 04:51:59 +0100 Received: by ozlabs.org (Postfix, from userid 1011) id 96B2A1007D7; Thu, 16 Feb 2012 14:51:54 +1100 (EST) From: Rusty Russell CC: Tony Luck , Fenghua Yu , linux-ia64@vger.kernel.org CC: Ralf Baechle , linux-mips@linux-mips.org CC: Chris Metcalf CC: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org To: linux-kernel@vger.kernel.org Message-ID: <1329364286.25917.rusty@rustcorp.com.au> Date: Thu, 16 Feb 2012 14:21:26 +1030 CC: Andrew Morton Subject: [PATCH 4/5] documentation: remove references to cpu_*_map. X-archive-position: 32435 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rusty@rustcorp.com.au Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8274 Lines: 183 From: Rusty Russell This has been obsolescent for a while, fix documentation and misc comments. Signed-off-by: Rusty Russell --- Documentation/cpu-hotplug.txt | 22 +++++++++++----------- arch/ia64/kernel/acpi.c | 2 +- arch/mips/cavium-octeon/smp.c | 2 +- arch/mips/pmc-sierra/yosemite/smp.c | 2 +- arch/mips/sibyte/bcm1480/smp.c | 2 +- arch/tile/kernel/setup.c | 2 +- arch/x86/xen/enlighten.c | 2 +- init/Kconfig | 4 ++-- 8 files changed, 19 insertions(+), 19 deletions(-) diff --git a/Documentation/cpu-hotplug.txt b/Documentation/cpu-hotplug.txt --- a/Documentation/cpu-hotplug.txt +++ b/Documentation/cpu-hotplug.txt @@ -47,7 +47,7 @@ maxcpus=n Restrict boot time cpus to other cpus later online, read FAQ's for more info. additional_cpus=n (*) Use this to limit hotpluggable cpus. This option sets - cpu_possible_map = cpu_present_map + additional_cpus + cpu_possible_mask = cpu_present_mask + additional_cpus cede_offline={"off","on"} Use this option to disable/enable putting offlined processors to an extended H_CEDE state on @@ -64,11 +64,11 @@ should only rely on this to count the # on the apicid values in those tables for disabled apics. In the event BIOS doesn't mark such hot-pluggable cpus as disabled entries, one could use this parameter "additional_cpus=x" to represent those cpus in the -cpu_possible_map. +cpu_possible_mask. possible_cpus=n [s390,x86_64] use this to set hotpluggable cpus. This option sets possible_cpus bits in - cpu_possible_map. Thus keeping the numbers of bits set + cpu_possible_mask. Thus keeping the numbers of bits set constant even if the machine gets rebooted. CPU maps and such @@ -76,7 +76,7 @@ CPU maps and such [More on cpumaps and primitive to manipulate, please check include/linux/cpumask.h that has more descriptive text.] -cpu_possible_map: Bitmap of possible CPUs that can ever be available in the +cpu_possible_mask: Bitmap of possible CPUs that can ever be available in the system. This is used to allocate some boot time memory for per_cpu variables that aren't designed to grow/shrink as CPUs are made available or removed. Once set during boot time discovery phase, the map is static, i.e no bits @@ -84,13 +84,13 @@ are added or removed anytime. Trimming upfront can save some boot time memory. See below for how we use heuristics in x86_64 case to keep this under check. -cpu_online_map: Bitmap of all CPUs currently online. Its set in __cpu_up() +cpu_online_mask: Bitmap of all CPUs currently online. Its set in __cpu_up() after a cpu is available for kernel scheduling and ready to receive interrupts from devices. Its cleared when a cpu is brought down using __cpu_disable(), before which all OS services including interrupts are migrated to another target CPU. -cpu_present_map: Bitmap of CPUs currently present in the system. Not all +cpu_present_mask: Bitmap of CPUs currently present in the system. Not all of them may be online. When physical hotplug is processed by the relevant subsystem (e.g ACPI) can change and new bit either be added or removed from the map depending on the event is hot-add/hot-remove. There are currently @@ -99,22 +99,22 @@ at which time hotplug is disabled. You really dont need to manipulate any of the system cpu maps. They should be read-only for most use. When setting up per-cpu resources almost always use -cpu_possible_map/for_each_possible_cpu() to iterate. +cpu_possible_mask/for_each_possible_cpu() to iterate. Never use anything other than cpumask_t to represent bitmap of CPUs. #include - for_each_possible_cpu - Iterate over cpu_possible_map - for_each_online_cpu - Iterate over cpu_online_map - for_each_present_cpu - Iterate over cpu_present_map + for_each_possible_cpu - Iterate over cpu_possible_mask + for_each_online_cpu - Iterate over cpu_online_mask + for_each_present_cpu - Iterate over cpu_present_mask for_each_cpu_mask(x,mask) - Iterate over some random collection of cpu mask. #include get_online_cpus() and put_online_cpus(): The above calls are used to inhibit cpu hotplug operations. While the -cpu_hotplug.refcount is non zero, the cpu_online_map will not change. +cpu_hotplug.refcount is non zero, the cpu_online_mask will not change. If you merely need to avoid cpus going away, you could also use preempt_disable() and preempt_enable() for those sections. Just remember the critical section cannot call any diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c --- a/arch/ia64/kernel/acpi.c +++ b/arch/ia64/kernel/acpi.c @@ -840,7 +840,7 @@ static __init int setup_additional_cpus( early_param("additional_cpus", setup_additional_cpus); /* - * cpu_possible_map should be static, it cannot change as CPUs + * cpu_possible_mask should be static, it cannot change as CPUs * are onlined, or offlined. The reason is per-cpu data-structures * are allocated by some modules at init time, and dont expect to * do this dynamically on cpu arrival/departure. diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -78,7 +78,7 @@ static inline void octeon_send_ipi_mask( } /** - * Detect available CPUs, populate cpu_possible_map + * Detect available CPUs, populate cpu_possible_mask */ static void octeon_smp_hotplug_setup(void) { diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -146,7 +146,7 @@ static void __cpuinit yos_boot_secondary } /* - * Detect available CPUs, populate cpu_possible_map before smp_init + * Detect available CPUs, populate cpu_possible_mask before smp_init * * We don't want to start the secondary CPU yet nor do we have a nice probing * feature in PMON so we just assume presence of the secondary core. diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -138,7 +138,7 @@ static void __cpuinit bcm1480_boot_secon /* * Use CFE to find out how many CPUs are available, setting up - * cpu_possible_map and the logical/physical mappings. + * cpu_possible_mask and the logical/physical mappings. * XXXKW will the boot CPU ever not be physical 0? * * Common setup before any secondaries are started diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c --- a/arch/tile/kernel/setup.c +++ b/arch/tile/kernel/setup.c @@ -1100,7 +1100,7 @@ EXPORT_SYMBOL(hash_for_home_map); /* * cpu_cacheable_map lists all the cpus whose caches the hypervisor can - * flush on our behalf. It is set to cpu_possible_map OR'ed with + * flush on our behalf. It is set to cpu_possible_mask OR'ed with * hash_for_home_map, and it is what should be passed to * hv_flush_remote() to flush all caches. Note that if there are * dedicated hypervisor driver tiles that have authorized use of their diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -876,7 +876,7 @@ void xen_setup_shared_info(void) xen_setup_mfn_list_list(); } -/* This is called once we have the cpu_possible_map */ +/* This is called once we have the cpu_possible_mask */ void xen_setup_vcpu_info_placement(void) { int cpu; diff --git a/init/Kconfig b/init/Kconfig --- a/init/Kconfig +++ b/init/Kconfig @@ -1423,8 +1423,8 @@ endif # MODULES config INIT_ALL_POSSIBLE bool help - Back when each arch used to define their own cpu_online_map and - cpu_possible_map, some of them chose to initialize cpu_possible_map + Back when each arch used to define their own cpu_online_mask and + cpu_possible_mask, some of them chose to initialize cpu_possible_mask with all 1s, and others with all 0s. When they were centralised, it was better to provide this option than to break all the archs and have several arch maintainers pursuing me down dark alleys. From rusty@rustcorp.com.au Thu Feb 16 04:51:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Feb 2012 04:52:37 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:43678 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903661Ab2BPDv7 (ORCPT ); Thu, 16 Feb 2012 04:51:59 +0100 Received: by ozlabs.org (Postfix, from userid 1011) id 590AC1007D4; Thu, 16 Feb 2012 14:51:54 +1100 (EST) From: Rusty Russell CC: Russell King , linux-arm-kernel@lists.infradead.org CC: Richard Kuo , linux-hexagon@vger.kernel.org CC: Ralf Baechle , linux-mips@linux-mips.org CC: Kyle McMartin , Helge Deller , "James E.J. Bottomley" , linux-parisc@vger.kernel.org CC: Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev@lists.ozlabs.org CC: Paul Mundt , linux-sh@vger.kernel.org CC: "David S. Miller" , sparclinux@vger.kernel.org CC: Chris Metcalf CC: Jeff Dike , Richard Weinberger , user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net To: linux-kernel@vger.kernel.org Message-ID: <1329364286.9720.rusty@rustcorp.com.au> Date: Thu, 16 Feb 2012 14:21:26 +1030 CC: Andrew Morton Subject: [PATCH 1/5] remove references to cpu_*_map in arch/ X-archive-position: 32436 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rusty@rustcorp.com.au Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 17856 Lines: 548 From: Rusty Russell This has been obsolescent for a while; time for the final push. In adjacent context, replaced old cpus_* with cpumask_*. Signed-off-by: Rusty Russell Acked-by: David S. Miller (arch/sparc) Acked-by: Chris Metcalf (arch/tile) Cc: user-mode-linux-devel@lists.sourceforge.net Cc: Russell King Cc: linux-arm-kernel@lists.infradead.org Cc: Richard Kuo Cc: linux-hexagon@vger.kernel.org Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: Kyle McMartin Cc: Helge Deller Cc: "James E.J. Bottomley" Cc: linux-parisc@vger.kernel.org Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Cc: Paul Mundt Cc: linux-sh@vger.kernel.org Cc: sparclinux@vger.kernel.org --- arch/arm/kernel/kprobes.c | 4 ++-- arch/arm/kernel/smp.c | 7 ++++--- arch/hexagon/kernel/smp.c | 8 ++++---- arch/mips/cavium-octeon/smp.c | 2 +- arch/mips/kernel/mips-mt-fpaff.c | 2 +- arch/mips/kernel/proc.c | 2 +- arch/mips/kernel/smp-bmips.c | 2 +- arch/mips/kernel/smp.c | 27 ++++++++++++--------------- arch/mips/kernel/smtc.c | 2 +- arch/mips/mm/c-octeon.c | 6 +++--- arch/mips/netlogic/common/smp.c | 6 +++--- arch/mips/pmc-sierra/yosemite/smp.c | 6 +++--- arch/mips/sgi-ip27/ip27-smp.c | 2 +- arch/mips/sibyte/bcm1480/smp.c | 5 ++--- arch/mips/sibyte/sb1250/smp.c | 7 +++---- arch/parisc/kernel/smp.c | 3 +-- arch/powerpc/platforms/wsp/smp.c | 2 +- arch/sh/kernel/smp.c | 2 +- arch/sh/kernel/topology.c | 2 +- arch/sparc/kernel/leon_kernel.c | 6 +++--- arch/tile/kernel/setup.c | 6 +++--- arch/um/kernel/skas/process.c | 2 +- arch/um/kernel/smp.c | 9 ++++----- 23 files changed, 57 insertions(+), 63 deletions(-) diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c --- a/arch/arm/kernel/kprobes.c +++ b/arch/arm/kernel/kprobes.c @@ -127,7 +127,7 @@ void __kprobes arch_arm_kprobe(struct kp flush_insns(addr, sizeof(u16)); } else if (addr & 2) { /* A 32-bit instruction spanning two words needs special care */ - stop_machine(set_t32_breakpoint, (void *)addr, &cpu_online_map); + stop_machine(set_t32_breakpoint, (void *)addr, cpu_online_mask); } else { /* Word aligned 32-bit instruction can be written atomically */ u32 bkp = KPROBE_THUMB32_BREAKPOINT_INSTRUCTION; @@ -190,7 +190,7 @@ int __kprobes __arch_disarm_kprobe(void void __kprobes arch_disarm_kprobe(struct kprobe *p) { - stop_machine(__arch_disarm_kprobe, p, &cpu_online_map); + stop_machine(__arch_disarm_kprobe, p, cpu_online_mask); } void __kprobes arch_remove_kprobe(struct kprobe *p) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -359,7 +359,7 @@ void __init smp_prepare_cpus(unsigned in * re-initialize the map in platform_smp_prepare_cpus() if * present != possible (e.g. physical hotplug). */ - init_cpu_present(&cpu_possible_map); + init_cpu_present(cpu_possible_mask); /* * Initialise the SCU if there are more than one CPU @@ -577,8 +577,9 @@ void smp_send_stop(void) unsigned long timeout; if (num_online_cpus() > 1) { - cpumask_t mask = cpu_online_map; - cpu_clear(smp_processor_id(), mask); + struct cpumask mask; + cpumask_copy(&mask, cpu_online_mask); + cpumask_clear_cpu(smp_processor_id(), &mask); smp_cross_call(&mask, IPI_CPU_STOP); } diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c --- a/arch/hexagon/kernel/smp.c +++ b/arch/hexagon/kernel/smp.c @@ -36,7 +36,7 @@ #define BASE_IPI_IRQ 26 /* - * cpu_possible_map needs to be filled out prior to setup_per_cpu_areas + * cpu_possible_mask needs to be filled out prior to setup_per_cpu_areas * (which is prior to any of our smp_prepare_cpu crap), in order to set * up the... per_cpu areas. */ @@ -211,7 +211,7 @@ int __cpuinit __cpu_up(unsigned int cpu) stack_start = ((void *) thread) + THREAD_SIZE; __vmstart(start_secondary, stack_start); - while (!cpu_isset(cpu, cpu_online_map)) + while (!cpu_online(cpu)) barrier(); return 0; @@ -232,7 +232,7 @@ void __init smp_prepare_cpus(unsigned in /* Right now, let's just fake it. */ for (i = 0; i < max_cpus; i++) - cpu_set(i, cpu_present_map); + set_cpu_present(i, true); /* Also need to register the interrupts for IPI */ if (max_cpus > 1) @@ -272,5 +272,5 @@ void smp_start_cpus(void) int i; for (i = 0; i < NR_CPUS; i++) - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); } diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -268,7 +268,7 @@ static int octeon_cpu_disable(void) spin_lock(&smp_reserve_lock); - cpu_clear(cpu, cpu_online_map); + set_cpu_online(cpu, false); cpu_clear(cpu, cpu_callin_map); local_irq_disable(); fixup_irqs(); diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c --- a/arch/mips/kernel/mips-mt-fpaff.c +++ b/arch/mips/kernel/mips-mt-fpaff.c @@ -173,7 +173,7 @@ asmlinkage long mipsmt_sys_sched_getaffi if (retval) goto out_unlock; - cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map); + cpumask_and(&mask, &p->thread.user_cpus_allowed, cpu_possible_mask); out_unlock: read_unlock(&tasklist_lock); diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -25,7 +25,7 @@ static int show_cpuinfo(struct seq_file int i; #ifdef CONFIG_SMP - if (!cpu_isset(n, cpu_online_map)) + if (!cpu_online(n)) return 0; #endif diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -319,7 +319,7 @@ static int bmips_cpu_disable(void) pr_info("SMP: CPU%d is offline\n", cpu); - cpu_clear(cpu, cpu_online_map); + set_cpu_online(cpu, false); cpu_clear(cpu, cpu_callin_map); local_flush_tlb_all(); diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -148,7 +148,7 @@ static void stop_this_cpu(void *dummy) /* * Remove this CPU: */ - cpu_clear(smp_processor_id(), cpu_online_map); + set_cpu_online(smp_processor_id(), false); for (;;) { if (cpu_wait) (*cpu_wait)(); /* Wait if available. */ @@ -174,7 +174,7 @@ void __init smp_prepare_cpus(unsigned in mp_ops->prepare_cpus(max_cpus); set_cpu_sibling_map(0); #ifndef CONFIG_HOTPLUG_CPU - init_cpu_present(&cpu_possible_map); + init_cpu_present(cpu_possible_mask); #endif } @@ -248,7 +248,7 @@ int __cpuinit __cpu_up(unsigned int cpu) while (!cpu_isset(cpu, cpu_callin_map)) udelay(100); - cpu_set(cpu, cpu_online_map); + set_cpu_online(cpu, true); return 0; } @@ -320,13 +320,12 @@ void flush_tlb_mm(struct mm_struct *mm) if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { smp_on_other_tlbs(flush_tlb_mm_ipi, mm); } else { - cpumask_t mask = cpu_online_map; unsigned int cpu; - cpu_clear(smp_processor_id(), mask); - for_each_cpu_mask(cpu, mask) - if (cpu_context(cpu, mm)) + for_each_online_cpu(cpu) { + if (cpu != smp_processor_id() && cpu_context(cpu, mm)) cpu_context(cpu, mm) = 0; + } } local_flush_tlb_mm(mm); @@ -360,13 +359,12 @@ void flush_tlb_range(struct vm_area_stru smp_on_other_tlbs(flush_tlb_range_ipi, &fd); } else { - cpumask_t mask = cpu_online_map; unsigned int cpu; - cpu_clear(smp_processor_id(), mask); - for_each_cpu_mask(cpu, mask) - if (cpu_context(cpu, mm)) + for_each_online_cpu(cpu) { + if (cpu != smp_processor_id() && cpu_context(cpu, mm)) cpu_context(cpu, mm) = 0; + } } local_flush_tlb_range(vma, start, end); preempt_enable(); @@ -407,13 +405,12 @@ void flush_tlb_page(struct vm_area_struc smp_on_other_tlbs(flush_tlb_page_ipi, &fd); } else { - cpumask_t mask = cpu_online_map; unsigned int cpu; - cpu_clear(smp_processor_id(), mask); - for_each_cpu_mask(cpu, mask) - if (cpu_context(cpu, vma->vm_mm)) + for_each_online_cpu(cpu) { + if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) cpu_context(cpu, vma->vm_mm) = 0; + } } local_flush_tlb_page(vma, page); preempt_enable(); diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -292,7 +292,7 @@ static void smtc_configure_tlb(void) * possibly leave some TCs/VPEs as "slave" processors. * * Use c0_MVPConf0 to find out how many TCs are available, setting up - * cpu_possible_map and the logical/physical mappings. + * cpu_possible_mask and the logical/physical mappings. */ int __init smtc_build_cpu_map(int start_cpu_slot) diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -81,9 +81,9 @@ static void octeon_flush_icache_all_core if (vma) mask = *mm_cpumask(vma->vm_mm); else - mask = cpu_online_map; - cpu_clear(cpu, mask); - for_each_cpu_mask(cpu, mask) + mask = *cpu_online_mask; + cpumask_clear_cpu(cpu, &mask); + for_each_cpu(cpu, &mask) octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); preempt_enable(); diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -165,7 +165,7 @@ void __init nlm_smp_setup(void) cpu_set(boot_cpu, phys_cpu_present_map); __cpu_number_map[boot_cpu] = 0; __cpu_logical_map[0] = boot_cpu; - cpu_set(0, cpu_possible_map); + set_cpu_possible(0, true); num_cpus = 1; for (i = 0; i < NR_CPUS; i++) { @@ -177,14 +177,14 @@ void __init nlm_smp_setup(void) cpu_set(i, phys_cpu_present_map); __cpu_number_map[i] = num_cpus; __cpu_logical_map[num_cpus] = i; - cpu_set(num_cpus, cpu_possible_map); + set_cpu_possible(num_cpus, true); ++num_cpus; } } pr_info("Phys CPU present map: %lx, possible map %lx\n", (unsigned long)phys_cpu_present_map.bits[0], - (unsigned long)cpu_possible_map.bits[0]); + (unsigned long)cpumask_bits(cpu_possible_mask)[0]); pr_info("Detected %i Slave CPU(s)\n", num_cpus); nlm_set_nmi_handler(nlm_boot_secondary_cpus); diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -155,10 +155,10 @@ static void __init yos_smp_setup(void) { int i; - cpus_clear(cpu_possible_map); + init_cpu_possible(cpu_none_mask); for (i = 0; i < 2; i++) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = i; __cpu_logical_map[i] = i; } @@ -169,7 +169,7 @@ static void __init yos_prepare_cpus(unsi /* * Be paranoid. Enable the IPI only if we're really about to go SMP. */ - if (cpus_weight(cpu_possible_map)) + if (num_possible_cpus()) set_c0_status(STATUSF_IP5); } diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c @@ -76,7 +76,7 @@ static int do_cpumask(cnodeid_t cnode, n /* Only let it join in if it's marked enabled */ if ((acpu->cpu_info.flags & KLINFO_ENABLE) && (tot_cpus_found != NR_CPUS)) { - cpu_set(cpuid, cpu_possible_map); + set_cpu_possible(cpuid, true); alloc_cpupda(cpuid, tot_cpus_found); cpus_found++; tot_cpus_found++; diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -147,14 +147,13 @@ static void __init bcm1480_smp_setup(voi { int i, num; - cpus_clear(cpu_possible_map); - cpu_set(0, cpu_possible_map); + init_cpu_possible(cpumask_of(0)); __cpu_number_map[0] = 0; __cpu_logical_map[0] = 0; for (i = 1, num = 0; i < NR_CPUS; i++) { if (cfe_cpu_stop(i) == 0) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = ++num; __cpu_logical_map[num] = i; } diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c @@ -126,7 +126,7 @@ static void __cpuinit sb1250_boot_second /* * Use CFE to find out how many CPUs are available, setting up - * cpu_possible_map and the logical/physical mappings. + * cpu_possible_mask and the logical/physical mappings. * XXXKW will the boot CPU ever not be physical 0? * * Common setup before any secondaries are started @@ -135,14 +135,13 @@ static void __init sb1250_smp_setup(void { int i, num; - cpus_clear(cpu_possible_map); - cpu_set(0, cpu_possible_map); + init_cpu_possible(cpumask_of(0)); __cpu_number_map[0] = 0; __cpu_logical_map[0] = 0; for (i = 1, num = 0; i < NR_CPUS; i++) { if (cfe_cpu_stop(i) == 0) { - cpu_set(i, cpu_possible_map); + set_cpu_possible(i, true); __cpu_number_map[i] = ++num; __cpu_logical_map[num] = i; } diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c --- a/arch/parisc/kernel/smp.c +++ b/arch/parisc/kernel/smp.c @@ -291,8 +291,7 @@ smp_cpu_init(int cpunum) mb(); /* Well, support 2.4 linux scheme as well. */ - if (cpu_isset(cpunum, cpu_online_map)) - { + if (cpu_online(cpunum)) { extern void machine_halt(void); /* arch/parisc.../process.c */ printk(KERN_CRIT "CPU#%d already initialized!\n", cpunum); diff --git a/arch/powerpc/platforms/wsp/smp.c b/arch/powerpc/platforms/wsp/smp.c --- a/arch/powerpc/platforms/wsp/smp.c +++ b/arch/powerpc/platforms/wsp/smp.c @@ -71,7 +71,7 @@ int __devinit smp_a2_kick_cpu(int nr) static int __init smp_a2_probe(void) { - return cpus_weight(cpu_possible_map); + return num_possible_cpus(); } static struct smp_ops_t a2_smp_ops = { diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c --- a/arch/sh/kernel/smp.c +++ b/arch/sh/kernel/smp.c @@ -63,7 +63,7 @@ void __init smp_prepare_cpus(unsigned in mp_ops->prepare_cpus(max_cpus); #ifndef CONFIG_HOTPLUG_CPU - init_cpu_present(&cpu_possible_map); + init_cpu_present(cpu_possible_mask); #endif } diff --git a/arch/sh/kernel/topology.c b/arch/sh/kernel/topology.c --- a/arch/sh/kernel/topology.c +++ b/arch/sh/kernel/topology.c @@ -27,7 +27,7 @@ static cpumask_t cpu_coregroup_map(unsig * Presently all SH-X3 SMP cores are multi-cores, so just keep it * simple until we have a method for determining topology.. */ - return cpu_possible_map; + return *cpu_possible_mask; } const struct cpumask *cpu_coregroup_mask(unsigned int cpu) diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c --- a/arch/sparc/kernel/leon_kernel.c +++ b/arch/sparc/kernel/leon_kernel.c @@ -104,11 +104,11 @@ static int irq_choose_cpu(const struct c { cpumask_t mask; - cpus_and(mask, cpu_online_map, *affinity); - if (cpus_equal(mask, cpu_online_map) || cpus_empty(mask)) + cpumask_and(&mask, cpu_online_mask, affinity); + if (cpumask_equal(&mask, cpu_online_mask) || cpumask_empty(&mask)) return boot_cpu_id; else - return first_cpu(mask); + return cpumask_first(&mask); } #else #define irq_choose_cpu(affinity) boot_cpu_id diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c --- a/arch/tile/kernel/setup.c +++ b/arch/tile/kernel/setup.c @@ -1186,7 +1186,7 @@ static void __init setup_cpu_maps(void) sizeof(cpu_lotar_map)); if (rc < 0) { pr_err("warning: no HV_INQ_TILES_LOTAR; using AVAIL\n"); - cpu_lotar_map = cpu_possible_map; + cpu_lotar_map = *cpu_possible_mask; } #if CHIP_HAS_CBOX_HOME_MAP() @@ -1196,9 +1196,9 @@ static void __init setup_cpu_maps(void) sizeof(hash_for_home_map)); if (rc < 0) early_panic("hv_inquire_tiles(HFH_CACHE) failed: rc %d\n", rc); - cpumask_or(&cpu_cacheable_map, &cpu_possible_map, &hash_for_home_map); + cpumask_or(&cpu_cacheable_map, cpu_possible_mask, &hash_for_home_map); #else - cpu_cacheable_map = cpu_possible_map; + cpu_cacheable_map = *cpu_possible_mask; #endif } diff --git a/arch/um/kernel/skas/process.c b/arch/um/kernel/skas/process.c --- a/arch/um/kernel/skas/process.c +++ b/arch/um/kernel/skas/process.c @@ -41,7 +41,7 @@ static int __init start_kernel_proc(void cpu_tasks[0].pid = pid; cpu_tasks[0].task = current; #ifdef CONFIG_SMP - cpu_online_map = cpumask_of_cpu(0); + init_cpu_online(get_cpu_mask(0)); #endif start_kernel(); return 0; diff --git a/arch/um/kernel/smp.c b/arch/um/kernel/smp.c --- a/arch/um/kernel/smp.c +++ b/arch/um/kernel/smp.c @@ -76,7 +76,7 @@ static int idle_proc(void *cpup) cpu_relax(); notify_cpu_starting(cpu); - cpu_set(cpu, cpu_online_map); + set_cpu_online(cpu, true); default_idle(); return 0; } @@ -110,8 +110,7 @@ void smp_prepare_cpus(unsigned int maxcp for (i = 0; i < ncpus; ++i) set_cpu_possible(i, true); - cpu_clear(me, cpu_online_map); - cpu_set(me, cpu_online_map); + set_cpu_online(me, true); cpu_set(me, cpu_callin_map); err = os_pipe(cpu_data[me].ipi_pipe, 1, 1); @@ -138,13 +137,13 @@ void smp_prepare_cpus(unsigned int maxcp void smp_prepare_boot_cpu(void) { - cpu_set(smp_processor_id(), cpu_online_map); + set_cpu_online(smp_processor_id(), true); } int __cpu_up(unsigned int cpu) { cpu_set(cpu, smp_commenced_mask); - while (!cpu_isset(cpu, cpu_online_map)) + while (!cpu_online(cpu)) mb(); return 0; } From blogic@openwrt.org Fri Feb 17 11:33:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:33:24 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36877 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901165Ab2BQKdR (ORCPT ); Fri, 17 Feb 2012 11:33:17 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 0/6] MIPS: lantiq: use managed gpios Date: Fri, 17 Feb 2012 11:32:45 +0100 Message-Id: <1329474771-20874-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 X-archive-position: 32437 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1183 Lines: 27 3.2 introduced devm_request_gpio to allow devres to manage our gpios. This series adds a new struct device pointer to our gpio_request wrapper and ocnverts from gpio_request to devm_gpio_request. John Crispin (6): MIPS: lantiq: remove redunant ltq_gpio_request() declaration and add device parameter MIPS: lantiq: use devm_request_gpio inside xway gpio driver MIPS: lantiq: use devm_request_gpio inside falcon gpio driver NET: MIPS: lantiq: convert etop to managed gpio MIPS: lantiq: convert pci to managed gpio MIPS: lantiq: convert gpio_stp to managed gpio .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 4 +--- arch/mips/include/asm/mach-lantiq/lantiq.h | 4 ++++ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 --- arch/mips/lantiq/falcon/gpio.c | 4 ++-- arch/mips/lantiq/xway/gpio.c | 4 ++-- arch/mips/lantiq/xway/gpio_stp.c | 13 ++++++++----- arch/mips/pci/pci-lantiq.c | 18 ++++++++++-------- drivers/net/ethernet/lantiq_etop.c | 9 ++++++--- 8 files changed, 33 insertions(+), 26 deletions(-) -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:33:49 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36879 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901169Ab2BQKdR (ORCPT ); Fri, 17 Feb 2012 11:33:17 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 1/6] MIPS: lantiq: remove redunant ltq_gpio_request() declaration and add device parameter Date: Fri, 17 Feb 2012 11:32:46 +0100 Message-Id: <1329474771-20874-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474771-20874-1-git-send-email-blogic@openwrt.org> References: <1329474771-20874-1-git-send-email-blogic@openwrt.org> X-archive-position: 32438 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2621 Lines: 59 3.2 introduced devm_request_gpio() to allow managed gpios. The devres api requires a struct device pointer to work. Add a parameter to ltq_gpio_request() so that managed gpios can work. Signed-off-by: John Crispin --- .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 4 +--- arch/mips/include/asm/mach-lantiq/lantiq.h | 4 ++++ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 --- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h index 8ac509a..1a4b836 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -141,9 +141,7 @@ static inline void ltq_sys1_w32_mask(u32 c, u32 s, u32 r) ltq_sys1_w32((ltq_sys1_r32(r) & ~(c)) | (s), r); } -/* gpio_request wrapper to help configure the pin */ -extern int ltq_gpio_request(unsigned int pin, unsigned int mux, - unsigned int dir, const char *name); +/* gpio wrapper to help configure the pin muxing */ extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); /* to keep the irq code generic we need to define these to 0 as falcon diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index bf05854..d90eef3 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -39,6 +39,10 @@ extern unsigned int ltq_get_soc_type(void); /* spinlock all ebu i/o */ extern spinlock_t ebu_lock; +/* request a non-gpio and set the PIO config */ +extern int ltq_gpio_request(struct device *dev, unsigned int pin, + unsigned int mux, unsigned int dir, const char *name); + /* some irq helpers */ extern void ltq_disable_irq(struct irq_data *data); extern void ltq_mask_and_ack_irq(struct irq_data *data); diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 9d0afeb..4213926 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -167,9 +167,6 @@ static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) ltq_cgu_w32((ltq_cgu_r32(r) & ~(c)) | (s), r); } -/* request a non-gpio and set the PIO config */ -extern int ltq_gpio_request(unsigned int pin, unsigned int mux, - unsigned int dir, const char *name); extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); extern void ltq_cgu_enable(unsigned int clk); -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:34:11 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36882 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903684Ab2BQKdS (ORCPT ); Fri, 17 Feb 2012 11:33:18 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 2/6] MIPS: lantiq: use devm_request_gpio inside xway gpio driver Date: Fri, 17 Feb 2012 11:32:47 +0100 Message-Id: <1329474771-20874-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474771-20874-1-git-send-email-blogic@openwrt.org> References: <1329474771-20874-1-git-send-email-blogic@openwrt.org> X-archive-position: 32439 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 908 Lines: 31 Start using the devm_request_gpio() api inside our xway gpio_request wrapper. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/gpio.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c index 14ff7c7..54ec6c9 100644 --- a/arch/mips/lantiq/xway/gpio.c +++ b/arch/mips/lantiq/xway/gpio.c @@ -50,14 +50,14 @@ int irq_to_gpio(unsigned int gpio) } EXPORT_SYMBOL(irq_to_gpio); -int ltq_gpio_request(unsigned int pin, unsigned int mux, +int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, unsigned int dir, const char *name) { int id = 0; if (pin >= (MAX_PORTS * PINS_PER_PORT)) return -EINVAL; - if (gpio_request(pin, name)) { + if (devm_gpio_request(dev, pin, name)) { pr_err("failed to setup lantiq gpio: %s\n", name); return -EBUSY; } -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:34:35 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36884 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903685Ab2BQKdS (ORCPT ); Fri, 17 Feb 2012 11:33:18 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 3/6] MIPS: lantiq: use devm_request_gpio inside falcon gpio driver Date: Fri, 17 Feb 2012 11:32:48 +0100 Message-Id: <1329474771-20874-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474771-20874-1-git-send-email-blogic@openwrt.org> References: <1329474771-20874-1-git-send-email-blogic@openwrt.org> X-archive-position: 32440 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1042 Lines: 32 Start using the devm_request_gpio() api inside our falcon gpio_request wrapper. Signed-off-by: John Crispin --- arch/mips/lantiq/falcon/gpio.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c index 3eebd51..b7611d7 100644 --- a/arch/mips/lantiq/falcon/gpio.c +++ b/arch/mips/lantiq/falcon/gpio.c @@ -97,7 +97,7 @@ int ltq_gpio_mux_set(unsigned int pin, unsigned int mux) } EXPORT_SYMBOL(ltq_gpio_mux_set); -int ltq_gpio_request(unsigned int pin, unsigned int mux, +int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, unsigned int dir, const char *name) { int port = pin / 100; @@ -106,7 +106,7 @@ int ltq_gpio_request(unsigned int pin, unsigned int mux, if (offset >= PINS_PER_PORT || port >= MAX_PORTS) return -EINVAL; - if (gpio_request(pin, name)) { + if (devm_gpio_request(dev, pin, name)) { pr_err("failed to setup lantiq gpio: %s\n", name); return -EBUSY; } -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:34:58 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36887 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903686Ab2BQKdT (ORCPT ); Fri, 17 Feb 2012 11:33:19 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , netdev@vger.kernel.org Subject: [PATCH 4/6] NET: MIPS: lantiq: convert etop to managed gpio Date: Fri, 17 Feb 2012 11:32:49 +0100 Message-Id: <1329474771-20874-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474771-20874-1-git-send-email-blogic@openwrt.org> References: <1329474771-20874-1-git-send-email-blogic@openwrt.org> X-archive-position: 32441 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1256 Lines: 41 ltq_gpio_request() now uses devres to manage the gpios. We need to pass a struct device pointer to make it work. Signed-off-by: John Crispin Cc: netdev@vger.kernel.org --- This patch should go via MIPS with the rest of the series. drivers/net/ethernet/lantiq_etop.c | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index 66ec54a..80ce6d9 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -292,9 +292,6 @@ ltq_etop_gbit_init(void) { ltq_pmu_enable(PMU_SWITCH); - ltq_gpio_request(42, 2, 1, "MDIO"); - ltq_gpio_request(43, 2, 1, "MDC"); - ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); /** Disable MDIO auto polling mode */ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); @@ -873,6 +870,12 @@ ltq_etop_probe(struct platform_device *pdev) err = -ENOMEM; goto err_out; } + if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") || + ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) { + dev_err(&pdev->dev, "failed to request MDIO gpios\n"); + err = -ENOMEM; + goto err_out; + } } dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:35:20 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36890 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903687Ab2BQKdU (ORCPT ); Fri, 17 Feb 2012 11:33:20 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 5/6] MIPS: lantiq: convert pci to managed gpio Date: Fri, 17 Feb 2012 11:32:50 +0100 Message-Id: <1329474771-20874-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474771-20874-1-git-send-email-blogic@openwrt.org> References: <1329474771-20874-1-git-send-email-blogic@openwrt.org> X-archive-position: 32442 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2171 Lines: 66 ltq_gpio_request() now uses devres to manage the gpios. We need to pass a struct device pointer to make it work. Signed-off-by: John Crispin --- arch/mips/pci/pci-lantiq.c | 18 ++++++++++-------- 1 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 3bf42c8..47b5d8e 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -150,24 +150,26 @@ static u32 ltq_calc_bar11mask(void) return bar11mask; } -static void ltq_pci_setup_gpio(int gpio) +static void ltq_pci_setup_gpio(struct device *dev) { + struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data; int i; for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { - if (gpio & (1 << i)) { - ltq_gpio_request(ltq_pci_gpio_map[i].pin, + if (conf->gpio & (1 << i)) { + ltq_gpio_request(dev, ltq_pci_gpio_map[i].pin, ltq_pci_gpio_map[i].mux, ltq_pci_gpio_map[i].dir, ltq_pci_gpio_map[i].name); } } - ltq_gpio_request(21, 0, 1, "pci-reset"); - ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; + ltq_gpio_request(dev, 21, 0, 1, "pci-reset"); + ltq_pci_req_mask = (conf->gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; } -static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) +static int __devinit ltq_pci_startup(struct device *dev) { u32 temp_buffer; + struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data; /* set clock to 33Mhz */ if (ltq_is_ar9()) { @@ -190,7 +192,7 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) } /* setup pci clock and gpis used by pci */ - ltq_pci_setup_gpio(conf->gpio); + ltq_pci_setup_gpio(dev); /* enable auto-switching between PCI and EBU */ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); @@ -275,7 +277,7 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev) ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); ltq_pci_controller.io_map_base = (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); - ltq_pci_startup(ltq_pci_data); + ltq_pci_startup(&pdev->dev); register_pci_controller(<q_pci_controller); return 0; -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:35:47 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36893 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903688Ab2BQKdU (ORCPT ); Fri, 17 Feb 2012 11:33:20 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 6/6] MIPS: lantiq: convert gpio_stp to managed gpio Date: Fri, 17 Feb 2012 11:32:51 +0100 Message-Id: <1329474771-20874-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474771-20874-1-git-send-email-blogic@openwrt.org> References: <1329474771-20874-1-git-send-email-blogic@openwrt.org> X-archive-position: 32443 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1372 Lines: 42 ltq_gpio_request() now uses devres to manage the gpios. We need to pass a struct device pointer to make it work. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/gpio_stp.c | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index cb6f170..e6b4809 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -80,11 +80,6 @@ static struct gpio_chip ltq_stp_chip = { static int ltq_stp_hw_init(void) { - /* the 3 pins used to control the external stp */ - ltq_gpio_request(4, 2, 1, "stp-st"); - ltq_gpio_request(5, 2, 1, "stp-d"); - ltq_gpio_request(6, 2, 1, "stp-sh"); - /* sane defaults */ ltq_stp_w32(0, LTQ_STP_AR); ltq_stp_w32(0, LTQ_STP_CPU0); @@ -133,6 +128,14 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to remap STP memory\n"); return -ENOMEM; } + + /* the 3 pins used to control the external stp */ + if (ltq_gpio_request(&pdev->dev, 4, 2, 1, "stp-st") || + ltq_gpio_request(&pdev->dev, 5, 2, 1, "stp-d") || + ltq_gpio_request(&pdev->dev, 6, 2, 1, "stp-sh")) { + dev_err(&pdev->dev, "failed to request needed gpios\n"); + return -EBUSY; + } ret = gpiochip_add(<q_stp_chip); if (!ret) ret = ltq_stp_hw_init(); -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:36:10 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36925 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2BQKdg (ORCPT ); Fri, 17 Feb 2012 11:33:36 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 0/9] MIPS: lantiq: convert to clkdev api Date: Fri, 17 Feb 2012 11:33:11 +0100 Message-Id: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 X-archive-position: 32444 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2359 Lines: 49 arch/mips/lantiq/* used its own functions to handle some clocks and the clock gating. This series changes the code to use clkdev api instead. This change also allows us to merge the clock code for all xway socs into a single file. John Crispin (9): MIPS: add clkdev.h MIPS: lantiq: convert to clkdev api MIPS: lantiq: convert xway to clkdev api MIPS: lantiq: convert falcon to clkdev api MIPS: lantiq: convert dma driver to clkdev api MIPS: lantiq: convert gpio_stp driver to clkdev api SERIAL: MIPS: lantiq: convert serial driver to clkdev api NET: MIPS: lantiq: convert etop driver to clkdev api WDT: MIPS: lantiq: convert watchdog driver to clkdev api arch/mips/Kconfig | 3 +- arch/mips/include/asm/clkdev.h | 25 ++ .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 8 +- arch/mips/include/asm/mach-lantiq/lantiq.h | 17 +- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 13 - arch/mips/lantiq/clk.c | 85 +++---- arch/mips/lantiq/clk.h | 59 ++++- arch/mips/lantiq/falcon/Makefile | 2 +- arch/mips/lantiq/falcon/clk.c | 44 ---- arch/mips/lantiq/falcon/sysctrl.c | 131 ++++++---- arch/mips/lantiq/prom.c | 1 - arch/mips/lantiq/xway/Makefile | 6 +- arch/mips/lantiq/xway/clk-ase.c | 48 ---- arch/mips/lantiq/xway/clk-xway.c | 223 ---------------- arch/mips/lantiq/xway/clk.c | 266 ++++++++++++++++++++ arch/mips/lantiq/xway/dma.c | 5 +- arch/mips/lantiq/xway/gpio_stp.c | 6 +- arch/mips/lantiq/xway/sysctrl.c | 106 +++++++- drivers/net/ethernet/lantiq_etop.c | 27 ++- drivers/tty/serial/lantiq.c | 2 +- drivers/watchdog/lantiq_wdt.c | 2 +- 21 files changed, 603 insertions(+), 476 deletions(-) create mode 100644 arch/mips/include/asm/clkdev.h delete mode 100644 arch/mips/lantiq/falcon/clk.c delete mode 100644 arch/mips/lantiq/xway/clk-ase.c delete mode 100644 arch/mips/lantiq/xway/clk-xway.c create mode 100644 arch/mips/lantiq/xway/clk.c -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:36:34 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36934 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903694Ab2BQKdg (ORCPT ); Fri, 17 Feb 2012 11:33:36 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 1/9] MIPS: add clkdev.h Date: Fri, 17 Feb 2012 11:33:12 +0100 Message-Id: <1329474800-20979-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474800-20979-1-git-send-email-blogic@openwrt.org> References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-archive-position: 32445 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1145 Lines: 44 For clkdev to work on MIPS we need this file include/linux/clkdev.h:#include Signed-off-by: John Crispin --- arch/mips/include/asm/clkdev.h | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/clkdev.h diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h new file mode 100644 index 0000000..2624754 --- /dev/null +++ b/arch/mips/include/asm/clkdev.h @@ -0,0 +1,25 @@ +/* + * based on arch/arm/include/asm/clkdev.h + * + * Copyright (C) 2008 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Helper for the clk API to assist looking up a struct clk. + */ +#ifndef __ASM_CLKDEV_H +#define __ASM_CLKDEV_H + +#include + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) +{ + return kzalloc(size, GFP_KERNEL); +} + +#endif -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:36:59 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36936 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903696Ab2BQKdh (ORCPT ); Fri, 17 Feb 2012 11:33:37 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 2/9] MIPS: lantiq: convert to clkdev api Date: Fri, 17 Feb 2012 11:33:13 +0100 Message-Id: <1329474800-20979-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474800-20979-1-git-send-email-blogic@openwrt.org> References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-archive-position: 32446 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7474 Lines: 292 Add clk_activate/clk_deactivate and add better error paths to the clk api functions. Signed-off-by: John Crispin --- arch/mips/Kconfig | 3 +- arch/mips/include/asm/mach-lantiq/lantiq.h | 17 ++---- arch/mips/lantiq/clk.c | 85 +++++++++++---------------- arch/mips/lantiq/clk.h | 59 ++++++++++++++++++- arch/mips/lantiq/prom.c | 1 - 5 files changed, 97 insertions(+), 68 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c4c1312..b106c9e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -228,7 +228,8 @@ config LANTIQ select ARCH_REQUIRE_GPIOLIB select SWAP_IO_SPACE select BOOT_RAW - select HAVE_CLK + select HAVE_MACH_CLKDEV + select CLKDEV_LOOKUP select MIPS_MACHINE config LASAT diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index d90eef3..895a346 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -9,6 +9,7 @@ #define _LANTIQ_H__ #include +#include #include /* generic reg access */ @@ -24,18 +25,6 @@ static inline void ltq_w32_mask(u32 c, u32 s, volatile void __iomem *r) extern unsigned int ltq_get_cpu_ver(void); extern unsigned int ltq_get_soc_type(void); -/* clock speeds */ -#define CLOCK_60M 60000000 -#define CLOCK_83M 83333333 -#define CLOCK_100M 100000000 -#define CLOCK_111M 111111111 -#define CLOCK_133M 133333333 -#define CLOCK_167M 166666667 -#define CLOCK_200M 200000000 -#define CLOCK_266M 266666666 -#define CLOCK_333M 333333333 -#define CLOCK_400M 400000000 - /* spinlock all ebu i/o */ extern spinlock_t ebu_lock; @@ -48,6 +37,10 @@ extern void ltq_disable_irq(struct irq_data *data); extern void ltq_mask_and_ack_irq(struct irq_data *data); extern void ltq_enable_irq(struct irq_data *data); +/* clock handling */ +extern int clk_activate(struct clk *clk); +extern void clk_deactivate(struct clk *clk); + /* find out what caused the last cpu reset */ extern int ltq_reset_cause(void); diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index 39eef7f..66d1a60 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -24,35 +25,6 @@ #include "clk.h" #include "prom.h" -struct clk { - const char *name; - unsigned long rate; - unsigned long (*get_rate) (void); -}; - -static struct clk *cpu_clk; -static int cpu_clk_cnt; - -/* lantiq socs have 3 static clocks */ -static struct clk cpu_clk_generic[] = { - { - .name = "cpu", - .get_rate = ltq_get_cpu_hz, - }, { - .name = "fpi", - .get_rate = ltq_get_fpi_hz, - }, { - .name = "io", - .get_rate = ltq_get_io_region_clock, - }, -}; - -void clk_init(void) -{ - cpu_clk = cpu_clk_generic; - cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic); -} - static inline int clk_good(struct clk *clk) { return clk && !IS_ERR(clk); @@ -61,7 +33,7 @@ static inline int clk_good(struct clk *clk) unsigned long clk_get_rate(struct clk *clk) { if (unlikely(!clk_good(clk))) - return 0; + return -1; if (clk->rate != 0) return clk->rate; @@ -69,40 +41,53 @@ unsigned long clk_get_rate(struct clk *clk) if (clk->get_rate != NULL) return clk->get_rate(); - return 0; + return -1; } EXPORT_SYMBOL(clk_get_rate); -struct clk *clk_get(struct device *dev, const char *id) +int clk_enable(struct clk *clk) { - int i; + if (unlikely(!clk_good(clk))) + return -1; - for (i = 0; i < cpu_clk_cnt; i++) - if (!strcmp(id, cpu_clk[i].name)) - return &cpu_clk[i]; - BUG(); - return ERR_PTR(-ENOENT); + if (clk->enable) + return clk->enable(clk); + + return -1; } -EXPORT_SYMBOL(clk_get); +EXPORT_SYMBOL(clk_enable); -void clk_put(struct clk *clk) +void clk_disable(struct clk *clk) { - /* not used */ + if (unlikely(!clk_good(clk))) + return; + + if (clk->disable) + clk->disable(clk); } -EXPORT_SYMBOL(clk_put); +EXPORT_SYMBOL(clk_disable); -int clk_enable(struct clk *clk) +int clk_activate(struct clk *clk) { - /* not used */ - return 0; + if (unlikely(!clk_good(clk))) + return -1; + + if (clk->activate) + return clk->activate(clk); + + return -1; } -EXPORT_SYMBOL(clk_enable); +EXPORT_SYMBOL(clk_activate); -void clk_disable(struct clk *clk) +void clk_deactivate(struct clk *clk) { - /* not used */ + if (unlikely(!clk_good(clk))) + return; + + if (clk->deactivate) + clk->deactivate(clk); } -EXPORT_SYMBOL(clk_disable); +EXPORT_SYMBOL(clk_deactivate); static inline u32 ltq_get_counter_resolution(void) { @@ -126,7 +111,7 @@ void __init plat_time_init(void) ltq_soc_init(); - clk = clk_get(0, "cpu"); + clk = clk_get_sys("cpu", NULL); mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); write_c0_compare(read_c0_count()); pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h index 3328925..1179bb3 100644 --- a/arch/mips/lantiq/clk.h +++ b/arch/mips/lantiq/clk.h @@ -9,10 +9,61 @@ #ifndef _LTQ_CLK_H__ #define _LTQ_CLK_H__ -extern void clk_init(void); +#include -extern unsigned long ltq_get_cpu_hz(void); -extern unsigned long ltq_get_fpi_hz(void); -extern unsigned long ltq_get_io_region_clock(void); +/* clock speeds */ +#define CLOCK_60M 60000000 +#define CLOCK_62_5M 62500000 +#define CLOCK_83M 83333333 +#define CLOCK_83_5M 83500000 +#define CLOCK_98_304M 98304000 +#define CLOCK_100M 100000000 +#define CLOCK_111M 111111111 +#define CLOCK_125M 125000000 +#define CLOCK_133M 133333333 +#define CLOCK_150M 150000000 +#define CLOCK_166M 166666666 +#define CLOCK_167M 166666667 +#define CLOCK_196_608M 196608000 +#define CLOCK_200M 200000000 +#define CLOCK_250M 250000000 +#define CLOCK_266M 266666666 +#define CLOCK_300M 300000000 +#define CLOCK_333M 333333333 +#define CLOCK_393M 393215332 +#define CLOCK_400M 400000000 +#define CLOCK_500M 500000000 +#define CLOCK_600M 600000000 + +struct clk { + struct clk_lookup cl; + unsigned long rate; + unsigned long (*get_rate) (void); + unsigned int module; + unsigned int bits; + int (*enable) (struct clk *clk); + void (*disable) (struct clk *clk); + int (*activate) (struct clk *clk); + void (*deactivate) (struct clk *clk); + void (*reboot) (struct clk *clk); +}; + +static inline void clkdev_add_static(const char *dev, unsigned long rate) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.clk = clk; + clk->rate = rate; + clkdev_add(&clk->cl); +} + +extern unsigned long ltq_danube_cpu_hz(void); +extern unsigned long ltq_danube_fpi_hz(void); +extern unsigned long ltq_danube_io_region_clock(void); + +extern unsigned long ltq_vr9_cpu_hz(void); +extern unsigned long ltq_vr9_fpi_hz(void); +extern unsigned long ltq_vr9_io_region_clock(void); #endif diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index ee63a33..b002bc7 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -103,7 +103,6 @@ EXPORT_SYMBOL(ltq_remap_resource); void __init prom_init(void) { ltq_soc_detect(&soc_info); - clk_init(); snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", soc_info.name, soc_info.rev_type); soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:37:24 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36938 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903697Ab2BQKdi (ORCPT ); Fri, 17 Feb 2012 11:33:38 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 3/9] MIPS: lantiq: convert xway to clkdev api Date: Fri, 17 Feb 2012 11:33:14 +0100 Message-Id: <1329474800-20979-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474800-20979-1-git-send-email-blogic@openwrt.org> References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-archive-position: 32447 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 20889 Lines: 772 Unify xway/ase clock code and add clkdev hooks to sysctrl.c Signed-off-by: John Crispin --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 13 - arch/mips/lantiq/xway/Makefile | 6 +- arch/mips/lantiq/xway/clk-ase.c | 48 ---- arch/mips/lantiq/xway/clk-xway.c | 223 ---------------- arch/mips/lantiq/xway/clk.c | 266 ++++++++++++++++++++ arch/mips/lantiq/xway/sysctrl.c | 106 +++++++- 6 files changed, 366 insertions(+), 296 deletions(-) delete mode 100644 arch/mips/lantiq/xway/clk-ase.c delete mode 100644 arch/mips/lantiq/xway/clk-xway.c create mode 100644 arch/mips/lantiq/xway/clk.c diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 4213926..6dfb65e 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -81,15 +81,6 @@ #define LTQ_PMU_BASE_ADDR 0x1F102000 #define LTQ_PMU_SIZE 0x1000 -#define PMU_DMA 0x0020 -#define PMU_EPHY 0x0080 -#define PMU_USB 0x8041 -#define PMU_LED 0x0800 -#define PMU_GPT 0x1000 -#define PMU_PPE 0x2000 -#define PMU_FPI 0x4000 -#define PMU_SWITCH 0x10000000 - /* ETOP - ethernet */ #define LTQ_ETOP_BASE_ADDR 0x1E180000 #define LTQ_ETOP_SIZE 0x40000 @@ -167,10 +158,6 @@ static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) ltq_cgu_w32((ltq_cgu_r32(r) & ~(c)) | (s), r); } -extern void ltq_pmu_enable(unsigned int module); -extern void ltq_pmu_disable(unsigned int module); -extern void ltq_cgu_enable(unsigned int clk); - static inline int ltq_is_ase(void) { return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE); diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 6678402..4dcb96f 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,7 +1,7 @@ -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o -obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o +obj-$(CONFIG_SOC_XWAY) += prom-xway.o +obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c deleted file mode 100644 index 6522583..0000000 --- a/arch/mips/lantiq/xway/clk-ase.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include - -/* cgu registers */ -#define LTQ_CGU_SYS 0x0010 - -unsigned int ltq_get_io_region_clock(void) -{ - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_io_region_clock); - -unsigned int ltq_get_fpi_bus_clock(int fpi) -{ - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_fpi_bus_clock); - -unsigned int ltq_get_cpu_hz(void) -{ - if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) - return CLOCK_266M; - else - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_cpu_hz); - -unsigned int ltq_get_fpi_hz(void) -{ - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c deleted file mode 100644 index 696b1a3..0000000 --- a/arch/mips/lantiq/xway/clk-xway.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include - -static unsigned int ltq_ram_clocks[] = { - CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; -#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] - -#define BASIC_FREQUENCY_1 35328000 -#define BASIC_FREQUENCY_2 36000000 -#define BASIS_REQUENCY_USB 12000000 - -#define GET_BITS(x, msb, lsb) \ - (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) - -#define LTQ_CGU_PLL0_CFG 0x0004 -#define LTQ_CGU_PLL1_CFG 0x0008 -#define LTQ_CGU_PLL2_CFG 0x000C -#define LTQ_CGU_SYS 0x0010 -#define LTQ_CGU_UPDATE 0x0014 -#define LTQ_CGU_IF_CLK 0x0018 -#define LTQ_CGU_OSC_CON 0x001C -#define LTQ_CGU_SMD 0x0020 -#define LTQ_CGU_CT1SR 0x0028 -#define LTQ_CGU_CT2SR 0x002C -#define LTQ_CGU_PCMCR 0x0030 -#define LTQ_CGU_PCI_CR 0x0034 -#define LTQ_CGU_PD_PC 0x0038 -#define LTQ_CGU_FMR 0x003C - -#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) -#define CGU_PLL0_BYPASS \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) -#define CGU_PLL0_CFG_DSMSEL \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) -#define CGU_PLL0_CFG_FRAC_EN \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) -#define CGU_PLL1_SRC \ - (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) -#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ - (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) -#define CGU_SYS_FPI_SEL (1 << 6) -#define CGU_SYS_DDR_SEL 0x3 -#define CGU_PLL0_SRC (1 << 29) - -#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) -#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) -#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) -#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) -#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) - -static unsigned int ltq_get_pll0_fdiv(void); - -static inline unsigned int get_input_clock(int pll) -{ - switch (pll) { - case 0: - if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) - return BASIS_REQUENCY_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_FREQUENCY_1; - else - return BASIC_FREQUENCY_2; - case 1: - if (CGU_PLL1_SRC) - return BASIS_REQUENCY_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_FREQUENCY_1; - else - return BASIC_FREQUENCY_2; - case 2: - switch (CGU_PLL2_SRC) { - case 0: - return ltq_get_pll0_fdiv(); - case 1: - return CGU_PLL2_PHASE_DIVIDER_ENABLE ? - BASIC_FREQUENCY_1 : - BASIC_FREQUENCY_2; - case 2: - return BASIS_REQUENCY_USB; - } - default: - return 0; - } -} - -static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) -{ - u64 res, clock = get_input_clock(pll); - - res = num * clock; - do_div(res, den); - return res; -} - -static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 10) + K; - unsigned int den = (M + 1) << 10; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 11) + K + 512; - unsigned int den = (M + 1) << 11; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = K >= 512 ? - ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; - unsigned int den = (M + 1) << 12; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, - unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) -{ - if (!dsmsel) - return mash_dsm(pll, M, N, K); - else if (!phase_div_en) - return mash_dsm(pll, M, N, K); - else - return ssff_dsm_2(pll, M, N, K); -} - -static inline unsigned int ltq_get_pll0_fosc(void) -{ - if (CGU_PLL0_BYPASS) - return get_input_clock(0); - else - return !CGU_PLL0_CFG_FRAC_EN - ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, - CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE) - : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, - CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE); -} - -static unsigned int ltq_get_pll0_fdiv(void) -{ - unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; - - return (ltq_get_pll0_fosc() + (div >> 1)) / div; -} - -unsigned int ltq_get_io_region_clock(void) -{ - unsigned int ret = ltq_get_pll0_fosc(); - - switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { - default: - case 0: - return (ret + 1) / 2; - case 1: - return (ret * 2 + 2) / 5; - case 2: - return (ret + 1) / 3; - case 3: - return (ret + 2) / 4; - } -} -EXPORT_SYMBOL(ltq_get_io_region_clock); - -unsigned int ltq_get_fpi_bus_clock(int fpi) -{ - unsigned int ret = ltq_get_io_region_clock(); - - if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) - ret >>= 1; - return ret; -} -EXPORT_SYMBOL(ltq_get_fpi_bus_clock); - -unsigned int ltq_get_cpu_hz(void) -{ - switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { - case 0: - return CLOCK_333M; - case 4: - return DDR_HZ; - case 8: - return DDR_HZ << 1; - default: - return DDR_HZ >> 1; - } -} -EXPORT_SYMBOL(ltq_get_cpu_hz); - -unsigned int ltq_get_fpi_hz(void) -{ - unsigned int ddr_clock = DDR_HZ; - - if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) - return ddr_clock >> 1; - return ddr_clock; -} -EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c new file mode 100644 index 0000000..88a1017 --- /dev/null +++ b/arch/mips/lantiq/xway/clk.c @@ -0,0 +1,266 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "../clk.h" + +static unsigned int ltq_ram_clocks[] = { + CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; +#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] + +#define BASIC_FREQUENCY_1 35328000 +#define BASIC_FREQUENCY_2 36000000 +#define BASIS_REQUENCY_USB 12000000 + +#define GET_BITS(x, msb, lsb) \ + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) + +/* legacy xway clock */ +#define LTQ_CGU_PLL0_CFG 0x0004 +#define LTQ_CGU_PLL1_CFG 0x0008 +#define LTQ_CGU_PLL2_CFG 0x000C +#define LTQ_CGU_SYS 0x0010 +#define LTQ_CGU_UPDATE 0x0014 +#define LTQ_CGU_IF_CLK 0x0018 +#define LTQ_CGU_OSC_CON 0x001C +#define LTQ_CGU_SMD 0x0020 +#define LTQ_CGU_CT1SR 0x0028 +#define LTQ_CGU_CT2SR 0x002C +#define LTQ_CGU_PCMCR 0x0030 +#define LTQ_CGU_PCI_CR 0x0034 +#define LTQ_CGU_PD_PC 0x0038 +#define LTQ_CGU_FMR 0x003C + +#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) +#define CGU_PLL0_BYPASS \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) +#define CGU_PLL0_CFG_DSMSEL \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) +#define CGU_PLL0_CFG_FRAC_EN \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) +#define CGU_PLL1_SRC \ + (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) +#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) +#define CGU_SYS_FPI_SEL (1 << 6) +#define CGU_SYS_DDR_SEL 0x3 +#define CGU_PLL0_SRC (1 << 29) + +#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) +#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) +#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) +#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) +#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) + +/* vr9 clock */ +#define LTQ_CGU_SYS_VR9 0x0c +#define LTQ_CGU_IF_CLK_VR9 0x24 + + +static unsigned int ltq_get_pll0_fdiv(void); + +static inline unsigned int get_input_clock(int pll) +{ + switch (pll) { + case 0: + if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 1: + if (CGU_PLL1_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 2: + switch (CGU_PLL2_SRC) { + case 0: + return ltq_get_pll0_fdiv(); + case 1: + return CGU_PLL2_PHASE_DIVIDER_ENABLE ? + BASIC_FREQUENCY_1 : + BASIC_FREQUENCY_2; + case 2: + return BASIS_REQUENCY_USB; + } + default: + return 0; + } +} + +static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) +{ + u64 res, clock = get_input_clock(pll); + + res = num * clock; + do_div(res, den); + return res; +} + +static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = ((N + 1) << 10) + K; + unsigned int den = (M + 1) << 10; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = ((N + 1) << 11) + K + 512; + unsigned int den = (M + 1) << 11; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = K >= 512 ? + ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; + unsigned int den = (M + 1) << 12; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, + unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) +{ + if (!dsmsel) + return mash_dsm(pll, M, N, K); + else if (!phase_div_en) + return mash_dsm(pll, M, N, K); + else + return ssff_dsm_2(pll, M, N, K); +} + +static inline unsigned int ltq_get_pll0_fosc(void) +{ + if (CGU_PLL0_BYPASS) + return get_input_clock(0); + else + return !CGU_PLL0_CFG_FRAC_EN + ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, + CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE) + : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, + CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE); +} + +static unsigned int ltq_get_pll0_fdiv(void) +{ + unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; + + return (ltq_get_pll0_fosc() + (div >> 1)) / div; +} + +unsigned long ltq_danube_io_region_clock(void) +{ + unsigned int ret = ltq_get_pll0_fosc(); + + switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { + default: + case 0: + return (ret + 1) / 2; + case 1: + return (ret * 2 + 2) / 5; + case 2: + return (ret + 1) / 3; + case 3: + return (ret + 2) / 4; + } +} + +unsigned long ltq_danube_fpi_bus_clock(int fpi) +{ + unsigned long ret = ltq_danube_io_region_clock(); + + if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) + ret >>= 1; + return ret; +} + +unsigned long ltq_danube_cpu_hz(void) +{ + switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { + case 0: + return CLOCK_333M; + case 4: + return DDR_HZ; + case 8: + return DDR_HZ << 1; + default: + return DDR_HZ >> 1; + } +} + +unsigned long ltq_danube_fpi_hz(void) +{ + unsigned long ddr_clock = DDR_HZ; + + if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) + return ddr_clock >> 1; + return ddr_clock; +} + +unsigned long ltq_vr9_cpu_hz(void) +{ + long clks[] = { + CLOCK_600M, CLOCK_500M, CLOCK_393M, CLOCK_333M, + CLOCK_125M, CLOCK_125M, CLOCK_196_608M, CLOCK_166M, + CLOCK_125M, CLOCK_125M }; + int val = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf; + + if (val > 9) + panic("bad cpu speed"); + if (val == 2) + panic("missing workaround"); + return clks[val]; +} + +unsigned long ltq_vr9_fpi_hz(void) +{ + long clks[] = { + CLOCK_62_5M, CLOCK_62_5M, CLOCK_83_5M, CLOCK_125M, + CLOCK_125M, CLOCK_125M, CLOCK_167M, CLOCK_200M, + CLOCK_250M, CLOCK_300M, CLOCK_62_5M, CLOCK_98_304M, + CLOCK_150M, CLOCK_196_608M }; + int val = ((ltq_cgu_r32(LTQ_CGU_IF_CLK_VR9) >> 25) & 0xf); + + if (val > 13) + panic("bad fpi speed"); + return clks[val]; +} + +unsigned long ltq_vr9_io_region_clock(void) +{ + return ltq_vr9_fpi_hz() / 2; +} + +unsigned long ltq_vr9_fpi_bus_clock(int fpi) +{ + return ltq_vr9_fpi_hz(); +} diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 38c122f..879c89a 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -8,17 +8,48 @@ #include #include +#include #include +#include "../clk.h" #include "../devices.h" /* clock control register */ #define LTQ_CGU_IFCCR 0x0018 +/* system clock register */ +#define LTQ_CGU_SYS 0x0010 /* the enable / disable registers */ #define LTQ_PMU_PWDCR 0x1C #define LTQ_PMU_PWDSR 0x20 +#define LTQ_PMU_PWDCR1 0x24 +#define LTQ_PMU_PWDSR1 0x28 + +#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR)) +#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR)) + +/* CGU - clock generation unit */ +#define CGU_EPHY 0x10 + +/* PMU - power management unit */ +#define PMU_DMA 0x0020 +#define PMU_SPI 0x0100 +#define PMU_EPHY 0x0080 +#define PMU_USB 0x8041 +#define PMU_STP 0x0800 +#define PMU_GPT 0x1000 +#define PMU_PPE 0x2000 +#define PMU_FPI 0x4000 +#define PMU_SWITCH 0x10000000 +#define PMU_AHBS 0x2000 +#define PMU_AHBM 0x8000 +#define PMU_PCIE_CLK 0x80000000 + +#define PMU1_PCIE_PHY 0x0001 +#define PMU1_PCIE_CTL 0x0002 +#define PMU1_PCIE_MSI 0x0020 +#define PMU1_PCIE_PDI 0x0010 #define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) #define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) @@ -36,28 +67,63 @@ void __iomem *ltq_cgu_membase; void __iomem *ltq_ebu_membase; static void __iomem *ltq_pmu_membase; -void ltq_cgu_enable(unsigned int clk) +static int ltq_cgu_enable(struct clk *clk) { - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR); + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR); + return 0; } -void ltq_pmu_enable(unsigned int module) +static void ltq_cgu_disable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR); +} + +static int ltq_pmu_enable(struct clk *clk) { int err = 1000000; - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); - do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); + ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits, + PWDCR(clk->module)); + do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits)); if (!err) panic("activating PMU module failed!"); + + return 0; } -EXPORT_SYMBOL(ltq_pmu_enable); -void ltq_pmu_disable(unsigned int module) +static void ltq_pmu_disable(struct clk *clk) { - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR); +} + +static inline void clkdev_add_pmu(const char *dev, const char *con, + unsigned int module, unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_pmu_enable; + clk->disable = ltq_pmu_disable; + clk->module = module; + clk->bits = bits; + clkdev_add(&clk->cl); +} + +static inline void clkdev_add_cgu(const char *con, unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = "fpi"; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_cgu_enable; + clk->disable = ltq_cgu_disable; + clk->bits = bits; + clkdev_add(&clk->cl); } -EXPORT_SYMBOL(ltq_pmu_disable); void __init ltq_soc_init(void) { @@ -75,4 +141,26 @@ void __init ltq_soc_init(void) /* make sure to unprotect the memory region where flash is located */ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); + + /* add our clocks */ + if (ltq_is_ase()) { + if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) + clkdev_add_static("cpu", CLOCK_266M); + else + clkdev_add_static("cpu", CLOCK_133M); + clkdev_add_static("fpi", CLOCK_133M); + clkdev_add_static("io", CLOCK_133M); + clkdev_add_cgu("ephycgu", CGU_EPHY), + clkdev_add_pmu("fpi", "ephy", 0, PMU_EPHY); + } else { + clkdev_add_static("cpu", ltq_danube_cpu_hz()); + clkdev_add_static("fpi", ltq_danube_fpi_hz()); + clkdev_add_static("io", ltq_danube_io_region_clock()); + if (ltq_is_ar9()) + clkdev_add_pmu("fpi", "switch", 0, PMU_SWITCH); + } + clkdev_add_pmu("fpi", "dma", 0, PMU_DMA); + clkdev_add_pmu("fpi", "stp", 0, PMU_STP); + clkdev_add_pmu("fpi", "spi", 0, PMU_SPI); + clkdev_add_pmu("fpi", "ppe", 0, PMU_PPE); } -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:37:52 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36942 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903698Ab2BQKdi (ORCPT ); Fri, 17 Feb 2012 11:33:38 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 4/9] MIPS: lantiq: convert falcon to clkdev api Date: Fri, 17 Feb 2012 11:33:15 +0100 Message-Id: <1329474800-20979-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474800-20979-1-git-send-email-blogic@openwrt.org> References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-archive-position: 32448 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8716 Lines: 293 Unify prom/clock code and add clkdev hooks to sysctrl.c Signed-off-by: John Crispin --- .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 8 +- arch/mips/lantiq/falcon/Makefile | 2 +- arch/mips/lantiq/falcon/clk.c | 44 ------- arch/mips/lantiq/falcon/sysctrl.c | 131 ++++++++++++-------- 4 files changed, 82 insertions(+), 103 deletions(-) delete mode 100644 arch/mips/lantiq/falcon/clk.c diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h index 1a4b836..59c4f56 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -95,6 +95,7 @@ /* Activation Status Register */ #define ACTS_ASC1_ACT 0x00000800 +#define ACTS_I2C_ACT 0x00004000 #define ACTS_P0 0x00010000 #define ACTS_P1 0x00010000 #define ACTS_P2 0x00020000 @@ -106,13 +107,6 @@ #define ACTS_PADCTRL3 0x00200000 #define ACTS_PADCTRL4 0x00400000 -extern void ltq_sysctl_activate(int module, unsigned int mask); -extern void ltq_sysctl_deactivate(int module, unsigned int mask); -extern void ltq_sysctl_clken(int module, unsigned int mask); -extern void ltq_sysctl_clkdis(int module, unsigned int mask); -extern void ltq_sysctl_reboot(int module, unsigned int mask); -extern int ltq_gpe_is_activated(unsigned int mask); - /* global register ranges */ extern void __iomem *ltq_ebu_membase; extern void __iomem *ltq_sys1_membase; diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile index 56b22eb..3634154 100644 --- a/arch/mips/lantiq/falcon/Makefile +++ b/arch/mips/lantiq/falcon/Makefile @@ -1,2 +1,2 @@ -obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o +obj-y := prom.o reset.o sysctrl.o devices.o gpio.o obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c deleted file mode 100644 index afe1b52..0000000 --- a/arch/mips/lantiq/falcon/clk.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Thomas Langer - * Copyright (C) 2011 John Crispin - */ - -#include -#include - -#include - -#include "devices.h" - -/* CPU0 Clock Control Register */ -#define LTQ_SYS1_CPU0CC 0x0040 -/* clock divider bit */ -#define LTQ_CPU0CC_CPUDIV 0x0001 - -unsigned int -ltq_get_io_region_clock(void) -{ - return CLOCK_200M; -} -EXPORT_SYMBOL(ltq_get_io_region_clock); - -unsigned int -ltq_get_cpu_hz(void) -{ - if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) - return CLOCK_200M; - else - return CLOCK_400M; -} -EXPORT_SYMBOL(ltq_get_cpu_hz); - -unsigned int -ltq_get_fpi_hz(void) -{ - return CLOCK_100M; -} -EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c index 905a142..08eca20 100644 --- a/arch/mips/lantiq/falcon/sysctrl.c +++ b/arch/mips/lantiq/falcon/sysctrl.c @@ -9,11 +9,13 @@ #include #include +#include #include #include #include "devices.h" +#include "../clk.h" /* infrastructure control register */ #define SYS1_INFRAC 0x00bc @@ -38,6 +40,10 @@ #define LTQ_SYSCTL_DEACT 0x0028 /* reboot Register */ #define LTQ_SYSCTL_RBT 0x002c +/* CPU0 Clock Control Register */ +#define LTQ_SYS1_CPU0CC 0x0040 +/* clock divider bit */ +#define LTQ_CPU0CC_CPUDIV 0x0001 static struct resource ltq_sysctl_res[] = { MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), @@ -64,79 +70,67 @@ void __iomem *ltq_ebu_membase; #define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) static inline void -ltq_sysctl_wait(int module, unsigned int mask, +ltq_sysctl_wait(struct clk *clk, unsigned int test, unsigned int reg) { int err = 1000000; - do {} while (--err && ((ltq_reg_r32(module, reg) - & mask) != test)); + do {} while (--err && ((ltq_reg_r32(clk->module, reg) + & clk->bits) != test)); if (!err) - pr_err("module de/activation failed %d %08X %08X\n", - module, mask, test); + pr_err("module de/activation failed %d %08X %08X %08X\n", + clk->module, clk->bits, test, + ltq_reg_r32(clk->module, reg) & clk->bits); } -void -ltq_sysctl_activate(int module, unsigned int mask) +static int +ltq_sysctl_activate(struct clk *clk) { - if (module > SYSCTL_SYSGPE) - return; - - ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); - ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT); - ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); + return 0; } -EXPORT_SYMBOL(ltq_sysctl_activate); -void -ltq_sysctl_deactivate(int module, unsigned int mask) +static void +ltq_sysctl_deactivate(struct clk *clk) { - if (module > SYSCTL_SYSGPE) - return; - - ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); - ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT); - ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT); + ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS); } -EXPORT_SYMBOL(ltq_sysctl_deactivate); -void -ltq_sysctl_clken(int module, unsigned int mask) +static int +ltq_sysctl_clken(struct clk *clk) { - if (module > SYSCTL_SYSGPE) - return; - - ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); - ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS); + return 0; } -EXPORT_SYMBOL(ltq_sysctl_clken); -void -ltq_sysctl_clkdis(int module, unsigned int mask) +static void +ltq_sysctl_clkdis(struct clk *clk) { - if (module > SYSCTL_SYSGPE) - return; - - ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); - ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); + ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS); } -EXPORT_SYMBOL(ltq_sysctl_clkdis); -void -ltq_sysctl_reboot(int module, unsigned int mask) +static void +ltq_sysctl_reboot(struct clk *clk) { unsigned int act; - - if (module > SYSCTL_SYSGPE) - return; - - act = ltq_reg_r32(module, LTQ_SYSCTL_ACT); - if ((~act & mask) != 0) - ltq_sysctl_activate(module, ~act & mask); - ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT); - ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); + unsigned int bits; + + act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT); + bits = ~act & clk->bits; + if (bits != 0) { + ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS); + } + ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); } -EXPORT_SYMBOL(ltq_sysctl_reboot); /* enable the ONU core */ static void @@ -167,6 +161,24 @@ ltq_gpe_enable(void) udelay(1); } +static inline void +clkdev_add_sys(const char *dev, unsigned int module, + unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = NULL; + clk->cl.clk = clk; + clk->module = module; + clk->activate = ltq_sysctl_activate; + clk->deactivate = ltq_sysctl_deactivate; + clk->enable = ltq_sysctl_clken; + clk->disable = ltq_sysctl_clkdis; + clk->reboot = ltq_sysctl_reboot; + clkdev_add(&clk->cl); +} + void __init ltq_soc_init(void) { @@ -180,4 +192,21 @@ ltq_soc_init(void) ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); ltq_gpe_enable(); + + /* get our 3 static rates for cpu, fpi and io clocks */ + if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) + clkdev_add_static("cpu", CLOCK_200M); + else + clkdev_add_static("cpu", CLOCK_400M); + clkdev_add_static("fpi", CLOCK_100M); + clkdev_add_static("io", CLOCK_200M); + + /* add our clock domains */ + clkdev_add_sys("gpio0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0); + clkdev_add_sys("gpio1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); + clkdev_add_sys("gpio2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2); + clkdev_add_sys("gpio3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3); + clkdev_add_sys("gpio4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4); + clkdev_add_sys("i2c", SYSCTL_SYS1, ACTS_I2C_ACT); + clkdev_add_sys("asc-debug", SYSCTL_SYS1, ACTS_ASC1_ACT); } -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:38:19 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36944 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903699Ab2BQKdj (ORCPT ); Fri, 17 Feb 2012 11:33:39 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 5/9] MIPS: lantiq: convert dma driver to clkdev api Date: Fri, 17 Feb 2012 11:33:16 +0100 Message-Id: <1329474800-20979-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474800-20979-1-git-send-email-blogic@openwrt.org> References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-archive-position: 32449 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 994 Lines: 40 Update from old pmu_{dis,en}able() to ckldev api. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/dma.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index 6cf883b..ed04da9 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -216,6 +217,7 @@ EXPORT_SYMBOL_GPL(ltq_dma_init_port); int __init ltq_dma_init(void) { + struct clk *clk; int i; /* remap dma register range */ @@ -224,7 +226,8 @@ ltq_dma_init(void) panic("Failed to remap dma memory"); /* power up and reset the dma engine */ - ltq_pmu_enable(PMU_DMA); + clk = clk_get_sys("fpi", "dma"); + clk_enable(clk); ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); /* disable all interrupts */ -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:38:43 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36946 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903700Ab2BQKdj (ORCPT ); Fri, 17 Feb 2012 11:33:39 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 6/9] MIPS: lantiq: convert gpio_stp driver to clkdev api Date: Fri, 17 Feb 2012 11:33:17 +0100 Message-Id: <1329474800-20979-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474800-20979-1-git-send-email-blogic@openwrt.org> References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-archive-position: 32450 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 967 Lines: 41 Update from old pmu_{dis,en}able() to ckldev api. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/gpio_stp.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index e6b4809..c9bf38b 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include @@ -80,6 +81,8 @@ static struct gpio_chip ltq_stp_chip = { static int ltq_stp_hw_init(void) { + struct clk *clk; + /* sane defaults */ ltq_stp_w32(0, LTQ_STP_AR); ltq_stp_w32(0, LTQ_STP_CPU0); @@ -105,7 +108,8 @@ static int ltq_stp_hw_init(void) */ ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0); - ltq_pmu_enable(PMU_LED); + clk = clk_get_sys("fpi", "stp"); + clk_enable(clk); return 0; } -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:39:06 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36948 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903701Ab2BQKdk (ORCPT ); Fri, 17 Feb 2012 11:33:40 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , linux-serial@vger.kernel.org Subject: [PATCH 7/9] SERIAL: MIPS: lantiq: convert serial driver to clkdev api Date: Fri, 17 Feb 2012 11:33:18 +0100 Message-Id: <1329474800-20979-8-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474800-20979-1-git-send-email-blogic@openwrt.org> References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-archive-position: 32451 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 735 Lines: 26 Update from old pmu_{dis,en}able() to ckldev api. Signed-off-by: John Crispin Cc: linux-serial@vger.kernel.org --- This patch should go via MIPS with the rest of the series. drivers/tty/serial/lantiq.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index 96c1cac..136dae8 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -686,7 +686,7 @@ lqasc_probe(struct platform_device *pdev) if (lqasc_port[pdev->id] != NULL) return -EBUSY; - clk = clk_get(&pdev->dev, "fpi"); + clk = clk_get_sys("fpi", NULL); if (IS_ERR(clk)) { pr_err("failed to get fpi clk\n"); return -ENOENT; -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:39:28 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36951 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903702Ab2BQKdl (ORCPT ); Fri, 17 Feb 2012 11:33:41 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , netdev@vger.kernel.org Subject: [PATCH 8/9] NET: MIPS: lantiq: convert etop driver to clkdev api Date: Fri, 17 Feb 2012 11:33:19 +0100 Message-Id: <1329474800-20979-9-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474800-20979-1-git-send-email-blogic@openwrt.org> References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-archive-position: 32452 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2325 Lines: 86 Update from old pmu_{dis,en}able() to ckldev api. Signed-off-by: John Crispin Cc: netdev@vger.kernel.org --- This patch should go via MIPS with the rest of the series. drivers/net/ethernet/lantiq_etop.c | 27 ++++++++++++++++++++++----- 1 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index 80ce6d9..fa2580b 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -36,6 +36,7 @@ #include #include #include +#include #include @@ -278,10 +279,18 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) static void ltq_etop_hw_exit(struct net_device *dev) { + struct clk *clk; struct ltq_etop_priv *priv = netdev_priv(dev); int i; - ltq_pmu_disable(PMU_PPE); + clk = clk_get_sys("ppe", NULL); + clk_disable(clk); + + if (ltq_has_gbit()) { + clk = clk_get_sys("fpi", "switch"); + clk_disable(clk); + } + for (i = 0; i < MAX_DMA_CHAN; i++) if (IS_TX(i) || IS_RX(i)) ltq_etop_free_channel(dev, &priv->ch[i]); @@ -290,7 +299,10 @@ ltq_etop_hw_exit(struct net_device *dev) static void ltq_etop_gbit_init(void) { - ltq_pmu_enable(PMU_SWITCH); + struct clk *clk; + + clk = clk_get_sys("fpi", "switch"); + clk_enable(clk); ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); /** Disable MDIO auto polling mode */ @@ -312,8 +324,10 @@ ltq_etop_hw_init(struct net_device *dev) unsigned int mii_mode = priv->pldata->mii_mode; int err = 0; int i; + struct clk *clk; - ltq_pmu_enable(PMU_PPE); + clk = clk_get_sys("fpi", "ppe"); + clk_enable(clk); if (ltq_has_gbit()) { ltq_etop_gbit_init(); @@ -334,11 +348,14 @@ ltq_etop_hw_init(struct net_device *dev) default: if (ltq_is_ase()) { - ltq_pmu_enable(PMU_EPHY); + clk = clk_get_sys("fpi", "ephy"); + clk_enable(clk); + /* disable external MII */ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); /* enable clock for internal PHY */ - ltq_cgu_enable(CGU_EPHY); + clk = clk_get_sys("fpi", "ephycgu"); + clk_enable(clk); /* we need to write this magic to the internal phy to make it work */ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:33:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:39:52 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36954 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901165Ab2BQKdm (ORCPT ); Fri, 17 Feb 2012 11:33:42 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , linux-watchdog@vger.kernel.org Subject: [PATCH 9/9] WDT: MIPS: lantiq: convert watchdog driver to clkdev api Date: Fri, 17 Feb 2012 11:33:20 +0100 Message-Id: <1329474800-20979-10-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474800-20979-1-git-send-email-blogic@openwrt.org> References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> X-archive-position: 32453 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 765 Lines: 26 Update from old pmu_{dis,en}able() to ckldev api. Signed-off-by: John Crispin Cc: linux-watchdog@vger.kernel.org --- This patch should go via MIPS with the rest of the series. drivers/watchdog/lantiq_wdt.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c index 9c8b10c..05646b8 100644 --- a/drivers/watchdog/lantiq_wdt.c +++ b/drivers/watchdog/lantiq_wdt.c @@ -206,7 +206,7 @@ ltq_wdt_probe(struct platform_device *pdev) } /* we do not need to enable the clock as it is always running */ - clk = clk_get(&pdev->dev, "io"); + clk = clk_get_sys("io", NULL); WARN_ON(!clk); ltq_io_region_clk_rate = clk_get_rate(clk); clk_put(clk); -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:34:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:40:15 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36975 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2BQKeG (ORCPT ); Fri, 17 Feb 2012 11:34:06 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 1/3] MIPS: lantiq: unify xway prom code Date: Fri, 17 Feb 2012 11:33:50 +0100 Message-Id: <1329474832-21095-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 X-archive-position: 32454 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5952 Lines: 238 The xway prom-ase.c and prom-xway.c files are redundant. Unify the 2 files. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/Makefile | 5 +-- arch/mips/lantiq/xway/prom-ase.c | 48 ---------------------- arch/mips/lantiq/xway/prom-xway.c | 64 ------------------------------ arch/mips/lantiq/xway/prom.c | 79 +++++++++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+), 116 deletions(-) delete mode 100644 arch/mips/lantiq/xway/prom-ase.c delete mode 100644 arch/mips/lantiq/xway/prom-xway.c create mode 100644 arch/mips/lantiq/xway/prom.c diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 4dcb96f..89f0a11 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,7 +1,4 @@ -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o - -obj-$(CONFIG_SOC_XWAY) += prom-xway.o -obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o +obj-y := prom.o sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c deleted file mode 100644 index 3f86a3b..0000000 --- a/arch/mips/lantiq/xway/prom-ase.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include - -#include - -#include "devices.h" -#include "../prom.h" - -#define SOC_AMAZON_SE "Amazon_SE" - -#define PART_SHIFT 12 -#define PART_MASK 0x0FFFFFFF -#define REV_SHIFT 28 -#define REV_MASK 0xF0000000 - -void __init ltq_soc_detect(struct ltq_soc_info *i) -{ - i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; - i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; - sprintf(i->rev_type, "1.%d", i->rev); - switch (i->partnum) { - case SOC_ID_AMAZON_SE: - i->name = SOC_AMAZON_SE; - i->type = SOC_TYPE_AMAZON_SE; - break; - - default: - unreachable(); - break; - } -} - -void __init ltq_soc_setup(void) -{ - ltq_register_ase_asc(); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c deleted file mode 100644 index d823a92..0000000 --- a/arch/mips/lantiq/xway/prom-xway.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include - -#include - -#include "devices.h" -#include "../prom.h" - -#define SOC_DANUBE "Danube" -#define SOC_TWINPASS "Twinpass" -#define SOC_AR9 "AR9" - -#define PART_SHIFT 12 -#define PART_MASK 0x0FFFFFFF -#define REV_SHIFT 28 -#define REV_MASK 0xF0000000 - -void __init ltq_soc_detect(struct ltq_soc_info *i) -{ - i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; - i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; - sprintf(i->rev_type, "1.%d", i->rev); - switch (i->partnum) { - case SOC_ID_DANUBE1: - case SOC_ID_DANUBE2: - i->name = SOC_DANUBE; - i->type = SOC_TYPE_DANUBE; - break; - - case SOC_ID_TWINPASS: - i->name = SOC_TWINPASS; - i->type = SOC_TYPE_DANUBE; - break; - - case SOC_ID_ARX188: - case SOC_ID_ARX168: - case SOC_ID_ARX182: - i->name = SOC_AR9; - i->type = SOC_TYPE_AR9; - break; - - default: - unreachable(); - break; - } -} - -void __init ltq_soc_setup(void) -{ - ltq_register_asc(0); - ltq_register_asc(1); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c new file mode 100644 index 0000000..0929acb --- /dev/null +++ b/arch/mips/lantiq/xway/prom.c @@ -0,0 +1,79 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "../prom.h" +#include "devices.h" + +#define SOC_DANUBE "Danube" +#define SOC_TWINPASS "Twinpass" +#define SOC_AR9 "AR9" +#define SOC_VR9 "VR9" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFFFFF +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + +#define SOC_AMAZON_SE "Amazon_SE" + +void __init ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); + switch (i->partnum) { + case SOC_ID_DANUBE1: + case SOC_ID_DANUBE2: + i->name = SOC_DANUBE; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_TWINPASS: + i->name = SOC_TWINPASS; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_ARX188: + case SOC_ID_ARX168: + case SOC_ID_ARX182: + i->name = SOC_AR9; + i->type = SOC_TYPE_AR9; + break; + + case SOC_ID_AMAZON_SE: + i->name = SOC_AMAZON_SE; + i->type = SOC_TYPE_AMAZON_SE; +#ifdef CONFIG_PCI + panic("ase is only supported for non pci kernels"); +#endif + break; + + default: + unreachable(); + break; + } +} + +void __init ltq_soc_setup(void) +{ + if (ltq_is_ase()) { + ltq_register_ase_asc(); + } else { + ltq_register_asc(0); + ltq_register_asc(1); + } + ltq_register_gpio(); + ltq_register_wdt(); +} -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:34:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:40:41 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36979 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903723Ab2BQKeH (ORCPT ); Fri, 17 Feb 2012 11:34:07 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 2/3] MIPS: lantiq: add vr9 support Date: Fri, 17 Feb 2012 11:33:51 +0100 Message-Id: <1329474832-21095-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474832-21095-1-git-send-email-blogic@openwrt.org> References: <1329474832-21095-1-git-send-email-blogic@openwrt.org> X-archive-position: 32455 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2278 Lines: 62 VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9. This patch adds the clkdev init code and SoC detection for the VR9. Signed-off-by: John Crispin --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 1 + arch/mips/lantiq/xway/prom.c | 5 +++++ arch/mips/lantiq/xway/sysctrl.c | 10 ++++++++++ 3 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 6dfb65e..8e0fa6c 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -21,6 +21,7 @@ #define SOC_ID_ARX188 0x16C #define SOC_ID_ARX168 0x16D #define SOC_ID_ARX182 0x16F +#define SOC_ID_VRX288 0x1C0 /* SoC Types */ #define SOC_TYPE_DANUBE 0x01 diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c index 0929acb..53b627c 100644 --- a/arch/mips/lantiq/xway/prom.c +++ b/arch/mips/lantiq/xway/prom.c @@ -60,6 +60,11 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) #endif break; + case SOC_ID_VRX288: + i->name = SOC_VR9; + i->type = SOC_TYPE_VR9; + break; + default: unreachable(); break; diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 879c89a..18bff5a 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -152,6 +152,16 @@ void __init ltq_soc_init(void) clkdev_add_static("io", CLOCK_133M); clkdev_add_cgu("ephycgu", CGU_EPHY), clkdev_add_pmu("fpi", "ephy", 0, PMU_EPHY); + } else if (ltq_is_vr9()) { + clkdev_add_static("cpu", ltq_vr9_cpu_hz()); + clkdev_add_static("fpi", ltq_vr9_fpi_hz()); + clkdev_add_static("io", ltq_vr9_io_region_clock()); + clkdev_add_pmu("pcie-phy", NULL, 1, PMU1_PCIE_PHY); + clkdev_add_pmu("pcie-bus", NULL, 0, PMU_PCIE_CLK); + clkdev_add_pmu("pcie-msi", NULL, 1, PMU1_PCIE_MSI); + clkdev_add_pmu("pcie-pdi", NULL, 1, PMU1_PCIE_PDI); + clkdev_add_pmu("pcie-ctl", NULL, 1, PMU1_PCIE_CTL); + clkdev_add_pmu("ahb", NULL, 0, PMU_AHBM | PMU_AHBS); } else { clkdev_add_static("cpu", ltq_danube_cpu_hz()); clkdev_add_static("fpi", ltq_danube_fpi_hz()); -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 11:34:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 11:41:04 +0100 (CET) Received: from nbd.name ([46.4.11.11]:36982 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901169Ab2BQKeH (ORCPT ); Fri, 17 Feb 2012 11:34:07 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 3/3] MIPS: lantiq: make use of module_platform_driver() Date: Fri, 17 Feb 2012 11:33:52 +0100 Message-Id: <1329474832-21095-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1329474832-21095-1-git-send-email-blogic@openwrt.org> References: <1329474832-21095-1-git-send-email-blogic@openwrt.org> X-archive-position: 32456 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3179 Lines: 123 Reduce boilerplate code. Signed-off-by: John Crispin --- drivers/mtd/maps/lantiq-flash.c | 20 ++------------------ drivers/net/ethernet/lantiq_etop.c | 20 ++------------------ drivers/watchdog/lantiq_wdt.c | 17 ++--------------- 3 files changed, 6 insertions(+), 51 deletions(-) diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c index 7b889de..e22436d 100644 --- a/drivers/mtd/maps/lantiq-flash.c +++ b/drivers/mtd/maps/lantiq-flash.c @@ -203,6 +203,7 @@ ltq_mtd_remove(struct platform_device *pdev) } static struct platform_driver ltq_mtd_driver = { + .probe = ltq_mtd_probe, .remove = __devexit_p(ltq_mtd_remove), .driver = { .name = "ltq_nor", @@ -210,24 +211,7 @@ static struct platform_driver ltq_mtd_driver = { }, }; -static int __init -init_ltq_mtd(void) -{ - int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); - - if (ret) - pr_err("ltq_nor: error registering platform driver"); - return ret; -} - -static void __exit -exit_ltq_mtd(void) -{ - platform_driver_unregister(<q_mtd_driver); -} - -module_init(init_ltq_mtd); -module_exit(exit_ltq_mtd); +module_platform_driver(ltq_mtd_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("John Crispin "); diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index fa2580b..4cfc314 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -943,6 +943,7 @@ ltq_etop_remove(struct platform_device *pdev) } static struct platform_driver ltq_mii_driver = { + .probe = ltq_etop_probe, .remove = __devexit_p(ltq_etop_remove), .driver = { .name = "ltq_etop", @@ -950,24 +951,7 @@ static struct platform_driver ltq_mii_driver = { }, }; -int __init -init_ltq_etop(void) -{ - int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); - - if (ret) - pr_err("ltq_etop: Error registering platfom driver!"); - return ret; -} - -static void __exit -exit_ltq_etop(void) -{ - platform_driver_unregister(<q_mii_driver); -} - -module_init(init_ltq_etop); -module_exit(exit_ltq_etop); +module_platform_driver(ltq_mii_driver); MODULE_AUTHOR("John Crispin "); MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c index 05646b8..572ac60 100644 --- a/drivers/watchdog/lantiq_wdt.c +++ b/drivers/watchdog/lantiq_wdt.c @@ -227,6 +227,7 @@ ltq_wdt_remove(struct platform_device *pdev) static struct platform_driver ltq_wdt_driver = { + .probe = ltq_wdt_probe, .remove = __devexit_p(ltq_wdt_remove), .driver = { .name = "ltq_wdt", @@ -234,21 +235,7 @@ static struct platform_driver ltq_wdt_driver = { }, }; -static int __init -init_ltq_wdt(void) -{ - return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); -} - -static void __exit -exit_ltq_wdt(void) -{ - return platform_driver_unregister(<q_wdt_driver); -} - -module_init(init_ltq_wdt); -module_exit(exit_ltq_wdt); - +module_platform_driver(ltq_wdt_driver); module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); -- 1.7.7.1 From blogic@openwrt.org Fri Feb 17 13:24:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 13:24:30 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47225 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901169Ab2BQMYY (ORCPT ); Fri, 17 Feb 2012 13:24:24 +0100 Message-ID: <4F3E46F0.5010701@openwrt.org> Date: Fri, 17 Feb 2012 13:24:16 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.20) Gecko/20110820 Icedove/3.1.12 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 4/6] NET: MIPS: lantiq: convert etop to managed gpio References: <1329474771-20874-1-git-send-email-blogic@openwrt.org> <1329474771-20874-5-git-send-email-blogic@openwrt.org> In-Reply-To: <1329474771-20874-5-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32457 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 514 Lines: 19 > ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); > @@ -873,6 +870,12 @@ ltq_etop_probe(struct platform_device *pdev) > err = -ENOMEM; > goto err_out; > } > + if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") || > + ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) { > + dev_err(&pdev->dev, "failed to request MDIO gpios\n"); > + err = -ENOMEM; -EBUSY should go here instead of -ENOMEM > + goto err_out; > + } > } > > dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); From sshtylyov@mvista.com Fri Feb 17 17:40:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 17:40:06 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:56689 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903691Ab2BQQkA (ORCPT ); Fri, 17 Feb 2012 17:40:00 +0100 Received: by bkcjk13 with SMTP id jk13so4337038bkc.36 for ; Fri, 17 Feb 2012 08:39:54 -0800 (PST) Received: by 10.204.152.208 with SMTP id h16mr4715011bkw.6.1329496794466; Fri, 17 Feb 2012 08:39:54 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id x22sm23653492bkw.11.2012.02.17.08.39.52 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 17 Feb 2012 08:39:53 -0800 (PST) Message-ID: <4F3E90C4.8010904@mvista.com> Date: Fri, 17 Feb 2012 20:39:16 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:10.0.1) Gecko/20120208 Thunderbird/10.0.1 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org, linux-serial@vger.kernel.org Subject: Re: [PATCH 7/9] SERIAL: MIPS: lantiq: convert serial driver to clkdev api References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> <1329474800-20979-8-git-send-email-blogic@openwrt.org> In-Reply-To: <1329474800-20979-8-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQnxnJSazOEP8ifgbM1kOCc4uuQ68PWKW1ULZtDqu8pby104lqNotBK0rvoxslkFFxVuWpZN X-archive-position: 32458 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 843 Lines: 30 Hello. On 02/17/2012 01:33 PM, John Crispin wrote: > Update from old pmu_{dis,en}able() to ckldev api. The comment doesn't match the essence of patch. > Signed-off-by: John Crispin > Cc: linux-serial@vger.kernel.org > --- > This patch should go via MIPS with the rest of the series. > drivers/tty/serial/lantiq.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c > index 96c1cac..136dae8 100644 > --- a/drivers/tty/serial/lantiq.c > +++ b/drivers/tty/serial/lantiq.c > @@ -686,7 +686,7 @@ lqasc_probe(struct platform_device *pdev) > if (lqasc_port[pdev->id] != NULL) > return -EBUSY; > > - clk = clk_get(&pdev->dev, "fpi"); > + clk = clk_get_sys("fpi", NULL); Why not just clk_get(&pdev->dev, NULL)? WBR, Sergei From sshtylyov@mvista.com Fri Feb 17 17:41:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 17:41:49 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:60337 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903688Ab2BQQlm (ORCPT ); Fri, 17 Feb 2012 17:41:42 +0100 Received: by bkcjk13 with SMTP id jk13so4339428bkc.36 for ; Fri, 17 Feb 2012 08:41:37 -0800 (PST) Received: by 10.204.9.205 with SMTP id m13mr4440618bkm.68.1329496897082; Fri, 17 Feb 2012 08:41:37 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id bw9sm23694525bkb.8.2012.02.17.08.41.34 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 17 Feb 2012 08:41:35 -0800 (PST) Message-ID: <4F3E9129.9040704@mvista.com> Date: Fri, 17 Feb 2012 20:40:57 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:10.0.1) Gecko/20120208 Thunderbird/10.0.1 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH 9/9] WDT: MIPS: lantiq: convert watchdog driver to clkdev api References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> <1329474800-20979-10-git-send-email-blogic@openwrt.org> In-Reply-To: <1329474800-20979-10-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkPAsX0QL9uzL9/HDDXdCqobyNyx1hPtvHvLZZACOTo1leu+EmXrYEdaPGcQdrCD2aVGNP5 X-archive-position: 32459 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 861 Lines: 30 Hello. On 02/17/2012 01:33 PM, John Crispin wrote: > Update from old pmu_{dis,en}able() to ckldev api. Again, you're doing something different. > Signed-off-by: John Crispin > Cc: linux-watchdog@vger.kernel.org > --- > This patch should go via MIPS with the rest of the series. > > drivers/watchdog/lantiq_wdt.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c > index 9c8b10c..05646b8 100644 > --- a/drivers/watchdog/lantiq_wdt.c > +++ b/drivers/watchdog/lantiq_wdt.c > @@ -206,7 +206,7 @@ ltq_wdt_probe(struct platform_device *pdev) > } > > /* we do not need to enable the clock as it is always running */ > - clk = clk_get(&pdev->dev, "io"); > + clk = clk_get_sys("io", NULL); Why not clk_get(&pdev->dev, NULL)? WBR, Sergei From sshtylyov@mvista.com Fri Feb 17 17:44:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 17:44:07 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:61233 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903691Ab2BQQoD (ORCPT ); Fri, 17 Feb 2012 17:44:03 +0100 Received: by bkcjk13 with SMTP id jk13so4342670bkc.36 for ; Fri, 17 Feb 2012 08:43:58 -0800 (PST) Received: by 10.204.152.208 with SMTP id h16mr4721323bkw.6.1329497037967; Fri, 17 Feb 2012 08:43:57 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id e17sm23641316bkz.13.2012.02.17.08.43.55 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 17 Feb 2012 08:43:57 -0800 (PST) Message-ID: <4F3E91B5.5080603@mvista.com> Date: Fri, 17 Feb 2012 20:43:17 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:10.0.1) Gecko/20120208 Thunderbird/10.0.1 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 2/3] MIPS: lantiq: add vr9 support References: <1329474832-21095-1-git-send-email-blogic@openwrt.org> <1329474832-21095-2-git-send-email-blogic@openwrt.org> In-Reply-To: <1329474832-21095-2-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkLn8fiwiGcf5LrS3hSVNeXMxPRy8q1wS3vp11WeJL2haAfdDVNXkUBA77Fly9qoVXkl/ge X-archive-position: 32460 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2475 Lines: 68 Hello. On 02/17/2012 01:33 PM, John Crispin wrote: > VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9. > This patch adds the clkdev init code and SoC detection for the VR9. > Signed-off-by: John Crispin > --- > .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 1 + > arch/mips/lantiq/xway/prom.c | 5 +++++ > arch/mips/lantiq/xway/sysctrl.c | 10 ++++++++++ > 3 files changed, 16 insertions(+), 0 deletions(-) > diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h > index 6dfb65e..8e0fa6c 100644 > --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h > +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h > @@ -21,6 +21,7 @@ > #define SOC_ID_ARX188 0x16C > #define SOC_ID_ARX168 0x16D > #define SOC_ID_ARX182 0x16F > +#define SOC_ID_VRX288 0x1C0 Use tabs to indent the value as above. > diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c > index 0929acb..53b627c 100644 > --- a/arch/mips/lantiq/xway/prom.c > +++ b/arch/mips/lantiq/xway/prom.c > @@ -60,6 +60,11 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) > #endif > break; > > + case SOC_ID_VRX288: > + i->name = SOC_VR9; > + i->type = SOC_TYPE_VR9; > + break; > + > default: > unreachable(); > break; > diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c > index 879c89a..18bff5a 100644 > --- a/arch/mips/lantiq/xway/sysctrl.c > +++ b/arch/mips/lantiq/xway/sysctrl.c > @@ -152,6 +152,16 @@ void __init ltq_soc_init(void) > clkdev_add_static("io", CLOCK_133M); > clkdev_add_cgu("ephycgu", CGU_EPHY), > clkdev_add_pmu("fpi", "ephy", 0, PMU_EPHY); > + } else if (ltq_is_vr9()) { Where is this defined? > + clkdev_add_static("cpu", ltq_vr9_cpu_hz()); > + clkdev_add_static("fpi", ltq_vr9_fpi_hz()); > + clkdev_add_static("io", ltq_vr9_io_region_clock()); > + clkdev_add_pmu("pcie-phy", NULL, 1, PMU1_PCIE_PHY); > + clkdev_add_pmu("pcie-bus", NULL, 0, PMU_PCIE_CLK); > + clkdev_add_pmu("pcie-msi", NULL, 1, PMU1_PCIE_MSI); > + clkdev_add_pmu("pcie-pdi", NULL, 1, PMU1_PCIE_PDI); > + clkdev_add_pmu("pcie-ctl", NULL, 1, PMU1_PCIE_CTL); > + clkdev_add_pmu("ahb", NULL, 0, PMU_AHBM | PMU_AHBS); > } else { > clkdev_add_static("cpu", ltq_danube_cpu_hz()); > clkdev_add_static("fpi", ltq_danube_fpi_hz()); WBR, Sergei From blogic@openwrt.org Fri Feb 17 17:47:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 17:47:52 +0100 (CET) Received: from nbd.name ([46.4.11.11]:48189 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903688Ab2BQQrr (ORCPT ); Fri, 17 Feb 2012 17:47:47 +0100 Message-ID: <4F3E84AA.9080204@openwrt.org> Date: Fri, 17 Feb 2012 17:47:38 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.20) Gecko/20110820 Icedove/3.1.12 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH 9/9] WDT: MIPS: lantiq: convert watchdog driver to clkdev api References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> <1329474800-20979-10-git-send-email-blogic@openwrt.org> <4F3E9129.9040704@mvista.com> In-Reply-To: <4F3E9129.9040704@mvista.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32461 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 420 Lines: 21 Hi Sergei, > ( The comment doesn't match the essence of patch. ) > Again, you're doing something different. > sorry > Why not clk_get(&pdev->dev, NULL)? > > WBR, Sergei > > clk_get_sys uses the clkdev lookup table, which is added by this series. it makes the clock code consistent throughout the lantiq related files. we use clk connections other places, which we cannot reference with clk_get that easily John From blogic@openwrt.org Fri Feb 17 17:47:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 17:48:14 +0100 (CET) Received: from nbd.name ([46.4.11.11]:48200 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2BQQrz (ORCPT ); Fri, 17 Feb 2012 17:47:55 +0100 Message-ID: <4F3E84B3.1030201@openwrt.org> Date: Fri, 17 Feb 2012 17:47:47 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.20) Gecko/20110820 Icedove/3.1.12 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , linux-mips@linux-mips.org, linux-serial@vger.kernel.org Subject: Re: [PATCH 7/9] SERIAL: MIPS: lantiq: convert serial driver to clkdev api References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> <1329474800-20979-8-git-send-email-blogic@openwrt.org> <4F3E90C4.8010904@mvista.com> In-Reply-To: <4F3E90C4.8010904@mvista.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32462 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 379 Lines: 19 Hi Sergei, > The comment doesn't match the essence of patch. > sorry > Why not just clk_get(&pdev->dev, NULL)? > > WBR, Sergei > clk_get_sys uses the clkdev lookup table, which is added by this series. it makes the clock code consistent throughout the lantiq related files. we use clk connections other places, which we cannot reference with clk_get that easily John From blogic@openwrt.org Fri Feb 17 17:50:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 17:50:54 +0100 (CET) Received: from nbd.name ([46.4.11.11]:49320 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903688Ab2BQQus (ORCPT ); Fri, 17 Feb 2012 17:50:48 +0100 Message-ID: <4F3E8560.7020309@openwrt.org> Date: Fri, 17 Feb 2012 17:50:40 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.20) Gecko/20110820 Icedove/3.1.12 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 2/3] MIPS: lantiq: add vr9 support References: <1329474832-21095-1-git-send-email-blogic@openwrt.org> <1329474832-21095-2-git-send-email-blogic@openwrt.org> <4F3E91B5.5080603@mvista.com> In-Reply-To: <4F3E91B5.5080603@mvista.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32463 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 372 Lines: 19 >> +#define SOC_ID_VRX288 0x1C0 > > Use tabs to indent the value as above. > i would have expected checkpatch.pl to complain about this one ?! >> + } else if (ltq_is_vr9()) { > > Where is this defined? > was added around 3.1 with the rest of the soc detection code. you can find it in arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h thx, John From sshtylyov@mvista.com Fri Feb 17 17:54:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 17:54:27 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:38289 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903690Ab2BQQyX (ORCPT ); Fri, 17 Feb 2012 17:54:23 +0100 Received: by bkcjk13 with SMTP id jk13so4358075bkc.36 for ; Fri, 17 Feb 2012 08:54:18 -0800 (PST) Received: by 10.204.13.82 with SMTP id b18mr4629721bka.88.1329497658428; Fri, 17 Feb 2012 08:54:18 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id ez5sm23661825bkc.15.2012.02.17.08.54.16 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 17 Feb 2012 08:54:17 -0800 (PST) Message-ID: <4F3E9423.2000502@mvista.com> Date: Fri, 17 Feb 2012 20:53:39 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:10.0.1) Gecko/20120208 Thunderbird/10.0.1 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org, linux-serial@vger.kernel.org Subject: Re: [PATCH 7/9] SERIAL: MIPS: lantiq: convert serial driver to clkdev api References: <1329474800-20979-1-git-send-email-blogic@openwrt.org> <1329474800-20979-8-git-send-email-blogic@openwrt.org> <4F3E90C4.8010904@mvista.com> <4F3E84B3.1030201@openwrt.org> In-Reply-To: <4F3E84B3.1030201@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQk4KrOiXNKklPo2Xd6oNoyHJqZ7H5iAWfSYNRmlkTYlFc4kYodQc0GQjoon/ify8IoEi9hs X-archive-position: 32464 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 783 Lines: 28 Hello. On 02/17/2012 07:47 PM, John Crispin wrote: >> The comment doesn't match the essence of patch. > sorry >> Why not just clk_get(&pdev->dev, NULL)? >> WBR, Sergei > clk_get_sys uses the clkdev lookup table, which is added by this series. clk_get() does the same, indirectly. > it makes the clock code consistent throughout the lantiq related files. > we use clk connections other places, which we cannot reference with > clk_get that easily clkdev assumes you don't need to use connection ID if the clock is bound to be matched by device ID via the lookup table. clk_get() is a common case when using clkdev, that's why your use of clk_get_sys() stands out as something unusual. I'll have to have a look at your lookup tables... > John WBR, Sergei From alcooperx@gmail.com Fri Feb 17 22:14:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Feb 2012 22:14:04 +0100 (CET) Received: from mail-vx0-f177.google.com ([209.85.220.177]:52595 "EHLO mail-vx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903696Ab2BQVOA (ORCPT ); Fri, 17 Feb 2012 22:14:00 +0100 Received: by vcbf1 with SMTP id f1so3346191vcb.36 for ; Fri, 17 Feb 2012 13:13:54 -0800 (PST) Received-SPF: pass (google.com: domain of alcooperx@gmail.com designates 10.52.29.241 as permitted sender) client-ip=10.52.29.241; Authentication-Results: mr.google.com; spf=pass (google.com: domain of alcooperx@gmail.com designates 10.52.29.241 as permitted sender) smtp.mail=alcooperx@gmail.com; dkim=pass header.i=alcooperx@gmail.com Received: from mr.google.com ([10.52.29.241]) by 10.52.29.241 with SMTP id n17mr4914223vdh.123.1329513234604 (num_hops = 1); Fri, 17 Feb 2012 13:13:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; bh=LppqU253m/LCE42418D3LZxx/9PAq2ucoAFMMsp94FY=; b=YgycvGy01Gwe5cjj2q0V8L2ZiYMO4r4VDGzZL6I0enewXyFwKnb5pfZtqPshsPTmWP MVVQjkysofpy7CN5YpOtkhs5FVYLewY1cg9QSYAq/uMHgaNJMn2SQraxI6feuQJQ9gA2 RaFYMZJQlf3lIG+MIWdrBhAuUIyPEIeiVhiyg= MIME-Version: 1.0 Received: by 10.52.29.241 with SMTP id n17mr3962855vdh.123.1329513234564; Fri, 17 Feb 2012 13:13:54 -0800 (PST) Received: by 10.220.89.12 with HTTP; Fri, 17 Feb 2012 13:13:54 -0800 (PST) Date: Fri, 17 Feb 2012 16:13:54 -0500 Message-ID: Subject: Stack unwind across signal frame From: Alan Cooper To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 32465 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 927 Lines: 20 I'm seeing a problem on both 2.6.37 and 3.3 MIPS kernels where I can't unwind through a MIPS signal frame. It looks like this is caused by the VDSO code that was added 2/2010. When the unwinder tries to find the frame info for the caller of the signal handler (the trampoline in VDSO), it can't find the eh_frame info because the address is in the VDSO area and stops unwinding. It looks like other platforms solve this by adding the eh_frame info for the VDSO area so the lookup works. This problem ends up breaking pthread cleanup for C++ programs because the cleanup is done using a class with the expectation that the destructor will be called when the thread gets canceled by a cancel signal. This seems like a big problem for all current MIPS kernels so I was wondering if I'm missing something? If this is correct, then it seems like the best solution would be to add the VDSO eh_frame info to MIPS. Thanks Al Cooper From daniel.schwierzeck@googlemail.com Sat Feb 18 00:02:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 18 Feb 2012 00:03:04 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:55575 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903696Ab2BQXC6 (ORCPT ); Sat, 18 Feb 2012 00:02:58 +0100 Received: by eaai1 with SMTP id i1so1555783eaa.36 for ; Fri, 17 Feb 2012 15:02:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=BlBM68LqsaffaL5juZBo/Kid123MzpTnrNRnbd665mg=; b=dJfSmCyVTxvEWigLIV0BM8do0WTJ7FgKBhpPXMuP/v05343C7T+zFBguUCHqphNN0P gbhY4tE/7pgv/jBtSqdELme6kDlwLkSG2PMqDcELW7c/4lJdRtmjmkwEEoDGmYId+G1a 4vgBwWral8aWo7P6kdkaEM7/n0JmMG/EwzH/Q= Received: by 10.213.26.198 with SMTP id f6mr1511402ebc.25.1329519772372; Fri, 17 Feb 2012 15:02:52 -0800 (PST) Received: from [192.168.100.100] (dslb-188-106-254-057.pools.arcor-ip.net. [188.106.254.57]) by mx.google.com with ESMTPS id y14sm14552266eef.10.2012.02.17.15.02.50 (version=SSLv3 cipher=OTHER); Fri, 17 Feb 2012 15:02:51 -0800 (PST) Message-ID: <4F3EDC99.2070106@googlemail.com> Date: Sat, 18 Feb 2012 00:02:49 +0100 From: Daniel Schwierzeck User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 3/3] MIPS: lantiq: make use of module_platform_driver() References: <1329474832-21095-1-git-send-email-blogic@openwrt.org> <1329474832-21095-3-git-send-email-blogic@openwrt.org> In-Reply-To: <1329474832-21095-3-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32466 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: daniel.schwierzeck@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4077 Lines: 147 Am 17.02.2012 11:33, schrieb John Crispin: > Reduce boilerplate code. > > Signed-off-by: John Crispin > --- > drivers/mtd/maps/lantiq-flash.c | 20 ++------------------ > drivers/net/ethernet/lantiq_etop.c | 20 ++------------------ > drivers/watchdog/lantiq_wdt.c | 17 ++--------------- > 3 files changed, 6 insertions(+), 51 deletions(-) > > diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c > index 7b889de..e22436d 100644 > --- a/drivers/mtd/maps/lantiq-flash.c > +++ b/drivers/mtd/maps/lantiq-flash.c > @@ -203,6 +203,7 @@ ltq_mtd_remove(struct platform_device *pdev) > } > > static struct platform_driver ltq_mtd_driver = { > + .probe = ltq_mtd_probe, you also need to change __init to __devinit at ltq_mtd_probe. Compiling with CONFIG_DEBUG_SECTION_MISMATCH shows following warning: WARNING: drivers/mtd/maps/built-in.o(.data+0x0): Section mismatch in reference from the variable ltq_mtd_driver to the function .init.text:ltq_mtd_probe() The variable ltq_mtd_driver references the function __init ltq_mtd_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console > .remove = __devexit_p(ltq_mtd_remove), > .driver = { > .name = "ltq_nor", > @@ -210,24 +211,7 @@ static struct platform_driver ltq_mtd_driver = { > }, > }; > > -static int __init > -init_ltq_mtd(void) > -{ > - int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); > - > - if (ret) > - pr_err("ltq_nor: error registering platform driver"); > - return ret; > -} > - > -static void __exit > -exit_ltq_mtd(void) > -{ > - platform_driver_unregister(<q_mtd_driver); > -} > - > -module_init(init_ltq_mtd); > -module_exit(exit_ltq_mtd); > +module_platform_driver(ltq_mtd_driver); > > MODULE_LICENSE("GPL"); > MODULE_AUTHOR("John Crispin"); > diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c > index fa2580b..4cfc314 100644 > --- a/drivers/net/ethernet/lantiq_etop.c > +++ b/drivers/net/ethernet/lantiq_etop.c > @@ -943,6 +943,7 @@ ltq_etop_remove(struct platform_device *pdev) > } > > static struct platform_driver ltq_mii_driver = { > + .probe = ltq_etop_probe, dito > .remove = __devexit_p(ltq_etop_remove), > .driver = { > .name = "ltq_etop", > @@ -950,24 +951,7 @@ static struct platform_driver ltq_mii_driver = { > }, > }; > > -int __init > -init_ltq_etop(void) > -{ > - int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); > - > - if (ret) > - pr_err("ltq_etop: Error registering platfom driver!"); > - return ret; > -} > - > -static void __exit > -exit_ltq_etop(void) > -{ > - platform_driver_unregister(<q_mii_driver); > -} > - > -module_init(init_ltq_etop); > -module_exit(exit_ltq_etop); > +module_platform_driver(ltq_mii_driver); > > MODULE_AUTHOR("John Crispin"); > MODULE_DESCRIPTION("Lantiq SoC ETOP"); > diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c > index 05646b8..572ac60 100644 > --- a/drivers/watchdog/lantiq_wdt.c > +++ b/drivers/watchdog/lantiq_wdt.c > @@ -227,6 +227,7 @@ ltq_wdt_remove(struct platform_device *pdev) > > > static struct platform_driver ltq_wdt_driver = { > + .probe = ltq_wdt_probe, dito > .remove = __devexit_p(ltq_wdt_remove), > .driver = { > .name = "ltq_wdt", > @@ -234,21 +235,7 @@ static struct platform_driver ltq_wdt_driver = { > }, > }; > > -static int __init > -init_ltq_wdt(void) > -{ > - return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); > -} > - > -static void __exit > -exit_ltq_wdt(void) > -{ > - return platform_driver_unregister(<q_wdt_driver); > -} > - > -module_init(init_ltq_wdt); > -module_exit(exit_ltq_wdt); > - > +module_platform_driver(ltq_wdt_driver); > module_param(nowayout, int, 0); > MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); > -- Best regards, Daniel From dhillf@gmail.com Sat Feb 18 08:12:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 18 Feb 2012 08:12:33 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:62432 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901167Ab2BRHM2 (ORCPT ); Sat, 18 Feb 2012 08:12:28 +0100 Received: by vbbfs19 with SMTP id fs19so3553857vbb.36 for ; Fri, 17 Feb 2012 23:12:22 -0800 (PST) Received-SPF: pass (google.com: domain of dhillf@gmail.com designates 10.52.28.167 as permitted sender) client-ip=10.52.28.167; Authentication-Results: mr.google.com; spf=pass (google.com: domain of dhillf@gmail.com designates 10.52.28.167 as permitted sender) smtp.mail=dhillf@gmail.com; dkim=pass header.i=dhillf@gmail.com Received: from mr.google.com ([10.52.28.167]) by 10.52.28.167 with SMTP id c7mr5583953vdh.96.1329549142676 (num_hops = 1); Fri, 17 Feb 2012 23:12:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=vWOHIIWiSdQweA71n8SaZ1RMGpd4ClwjynZvQ0+SxAI=; b=bJNOL5qZzplGl4aBddsMYYai7VcM70WO1OmY61ZLUgNh17/BcidhgNdgBbAWzkRtHD Mc66HB7X4xwuiEZMS6xgDlh5r5R2BaeocD4iQimrDP0xbblu1IPSUYucARD7HIpUBBZ+ ssEZu2Iyp1XQdDt9WyrYs67vn1DAdETESguL0= MIME-Version: 1.0 Received: by 10.52.28.167 with SMTP id c7mr4525908vdh.96.1329549142627; Fri, 17 Feb 2012 23:12:22 -0800 (PST) Received: by 10.220.68.77 with HTTP; Fri, 17 Feb 2012 23:12:22 -0800 (PST) In-Reply-To: References: Date: Sat, 18 Feb 2012 15:12:22 +0800 Message-ID: Subject: Re: Stack unwind across signal frame From: Hillf Danton To: Alan Cooper Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 32467 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 554 Lines: 11 On Sat, Feb 18, 2012 at 5:13 AM, Alan Cooper wrote: > This problem ends up breaking pthread cleanup for C++ programs because > the cleanup is done using a class with the expectation that the > destructor will be called when the thread gets canceled by a cancel > signal. This seems like a big problem for all current MIPS kernels so > I was wondering if I'm missing something? > > If this is correct, then it seems like the best solution would be to > add the VDSO eh_frame info to MIPS. > Feel free to send a patch after testing;) From david.s.daney@gmail.com Sat Feb 18 18:06:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 18 Feb 2012 18:06:04 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:55011 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901351Ab2BRRGA (ORCPT ); Sat, 18 Feb 2012 18:06:00 +0100 Received: by pbcun1 with SMTP id un1so5694934pbc.36 for ; Sat, 18 Feb 2012 09:05:54 -0800 (PST) Received-SPF: pass (google.com: domain of david.s.daney@gmail.com designates 10.68.195.73 as permitted sender) client-ip=10.68.195.73; Authentication-Results: mr.google.com; spf=pass (google.com: domain of david.s.daney@gmail.com designates 10.68.195.73 as permitted sender) smtp.mail=david.s.daney@gmail.com; dkim=pass header.i=david.s.daney@gmail.com Received: from mr.google.com ([10.68.195.73]) by 10.68.195.73 with SMTP id ic9mr43382716pbc.72.1329584754020 (num_hops = 1); Sat, 18 Feb 2012 09:05:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=ofjvcW+huBFnj4YUG9kHeehWp+pd/TGS3sKdPTgy0Wk=; b=UAh1tx8YOKYypGYY/wdBezVVbG1fdYpvuVYjdlObAQPeBuNEb5yYl06Gc2IG2VGt3f ONBC0/xnTfCv5Thl+asNdV4xyH9awb91SSRnVFm1OsXwrZxZOP2GabS1aQ7CgXe92b75 DnF+VzclYkSDlUv1rDiZEYRiNBSKsM9GBQBAE= Received: by 10.68.195.73 with SMTP id ic9mr35456479pbc.72.1329584753984; Sat, 18 Feb 2012 09:05:53 -0800 (PST) Received: from dd_xps.caveonetworks.com (ppp-67-124-89-155.dsl.pltn13.pacbell.net. [67.124.89.155]) by mx.google.com with ESMTPS id y5sm8301394pbk.45.2012.02.18.09.05.52 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 18 Feb 2012 09:05:53 -0800 (PST) Message-ID: <4F3FDA70.9060304@gmail.com> Date: Sat, 18 Feb 2012 09:05:52 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.1) Gecko/20120209 Thunderbird/10.0.1 MIME-Version: 1.0 To: Alan Cooper CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: Stack unwind across signal frame References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32468 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.s.daney@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1743 Lines: 42 On 02/17/2012 01:13 PM, Alan Cooper wrote: > I'm seeing a problem on both 2.6.37 and 3.3 MIPS kernels where I can't > unwind through a MIPS signal frame. You don't tell us the version of the unwinder (likely from libgcc) you are using. There was a lot of work in this area four or five years ago, I didn't take the time to do the required archaeology to determine the exact patch, but likely you are missing this. > It looks like this is caused by > the VDSO code that was added 2/2010. Some CPUs have errata necessitating a different signal frame layout, on these CPUs, you wouldn't be able to unwind either, even pre mips-vdso. > When the unwinder tries to find > the frame info for the caller of the signal handler (the trampoline in > VDSO), it can't find the eh_frame info because the address is in the > VDSO area and stops unwinding. It looks like other platforms solve > this by adding the eh_frame info for the VDSO area so the lookup > works. That's right. However all 'modern' GCCs and GDBs can unwind through signal frames on all 2.4.x and later kernels. I would recommend upgrading your GCC to 4.6.2, and see if you obtain better results. > This problem ends up breaking pthread cleanup for C++ programs because > the cleanup is done using a class with the expectation that the > destructor will be called when the thread gets canceled by a cancel > signal. This seems like a big problem for all current MIPS kernels so > I was wondering if I'm missing something? A modern libgcc I think. > > If this is correct, then it seems like the best solution would be to > add the VDSO eh_frame info to MIPS. Having a correct eh_frame in the vdso, would be nice, but is not the highest priority for me. David Daney From hauke@hauke-m.de Sun Feb 19 19:33:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:33:04 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35768 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903554Ab2BSSdA (ORCPT ); Sun, 19 Feb 2012 19:33:00 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 8B0B88F6C; Sun, 19 Feb 2012 19:32:59 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HFfEjTq3Uxbh; Sun, 19 Feb 2012 19:32:46 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 218478F60; Sun, 19 Feb 2012 19:32:46 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 00/11] ssb/bcma/BCM47XX: sprom fixes and extensions Date: Sun, 19 Feb 2012 19:32:14 +0100 Message-Id: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32469 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2187 Lines: 47 This patch series fixes some errors in the sprom structures and extends it to contain members for all sprom values for sprom version 1 to 9. This was done by looking into the open source part of the Broadcom SDK. This also adds a fallback sprom registration method to bcma. It also contains some small fixes for the bcma47xx arch code and a rewrite of the code to provide the sprom from flash. It now also provides sprom from flash for devices using bcma to control the system bus. This patch series is based on wireles-testing. I think it is the best way to merge this through John's wireless tree as the changes in the sprom struct should be used in further patches extending the pci sprom parsing and the usage of struct sprom by the brcmsmac driver. Hauke Mehrtens (11): ssb: sprom fix some sizes / signedness ssb: remove 5GHz antenna gain from sprom ssb: fix per path sprom vars ssb: add ccode ssb: add some missing sprom attributes bcma: export bcma_find_core bcma: add support for sprom not found on the device. MIPS: BCM47XX: return number of written bytes in nvram_getenv MIPS: BCM47XX: fix signature of nvram_parse_macaddr MIPS: BCM47XX: move and extend sprom parsing MIPS: BCM47XX: provide sprom to bcma bus arch/mips/bcm47xx/Makefile | 2 +- arch/mips/bcm47xx/nvram.c | 3 +- arch/mips/bcm47xx/setup.c | 188 ++------- arch/mips/bcm47xx/sprom.c | 618 ++++++++++++++++++++++++++ arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 3 + arch/mips/include/asm/mach-bcm47xx/nvram.h | 2 +- drivers/bcma/main.c | 3 +- drivers/bcma/sprom.c | 75 +++- drivers/net/wireless/b43legacy/phy.c | 2 +- drivers/ssb/pci.c | 40 +-- drivers/ssb/pcmcia.c | 12 +- drivers/ssb/sdio.c | 12 +- include/linux/bcma/bcma.h | 7 + include/linux/ssb/ssb.h | 102 ++++- 14 files changed, 844 insertions(+), 225 deletions(-) create mode 100644 arch/mips/bcm47xx/sprom.c -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:33:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:33:25 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35778 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903555Ab2BSSdC (ORCPT ); Sun, 19 Feb 2012 19:33:02 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id D14E18F60; Sun, 19 Feb 2012 19:33:01 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GqQ1B5dmdfRJ; Sun, 19 Feb 2012 19:32:47 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id D79698F61; Sun, 19 Feb 2012 19:32:46 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 01/11] ssb: sprom fix some sizes / signedness Date: Sun, 19 Feb 2012 19:32:15 +0100 Message-Id: <1329676345-15856-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32470 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2462 Lines: 58 Some parts of the sprom struct are bigger than needed. The leddc and maxpwr values are just 8 bit long and not 16. rxpo2g and rxpo5g are signed I got these information for the open source part of the Braodcom SDK covering sprom version 1 to 9. rxpo2g contained a negative number on my bcm5354 based device, this cased an error and Broadcom SDK says this is signed. Signed-off-by: Hauke Mehrtens --- include/linux/ssb/ssb.h | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index bbc2612..f169621 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -33,8 +33,8 @@ struct ssb_sprom { u8 et1mdcport; /* MDIO for enet1 */ u16 board_rev; /* Board revision number from SPROM. */ u8 country_code; /* Country Code */ - u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */ - u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */ u16 pa0b0; @@ -53,10 +53,10 @@ struct ssb_sprom { u8 gpio1; /* GPIO pin 1 */ u8 gpio2; /* GPIO pin 2 */ u8 gpio3; /* GPIO pin 3 */ - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ u8 itssi_a; /* Idle TSSI Target for A-PHY */ u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ u8 tri2g; /* 2.4GHz TX isolation */ @@ -67,8 +67,8 @@ struct ssb_sprom { u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ - u8 rxpo2g; /* 2GHz RX power offset */ - u8 rxpo5g; /* 5GHz RX power offset */ + s8 rxpo2g; /* 2GHz RX power offset */ + s8 rxpo5g; /* 5GHz RX power offset */ u8 rssisav2g; /* 2GHz RSSI params */ u8 rssismc2g; u8 rssismf2g; -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:33:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:33:50 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35796 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903561Ab2BSSdP (ORCPT ); Sun, 19 Feb 2012 19:33:15 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 09D378F61; Sun, 19 Feb 2012 19:33:15 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cPLHWNryp4eP; Sun, 19 Feb 2012 19:33:00 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 4CB078F62; Sun, 19 Feb 2012 19:32:47 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 02/11] ssb: remove 5GHz antenna gain from sprom Date: Sun, 19 Feb 2012 19:32:16 +0100 Message-Id: <1329676345-15856-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32471 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6718 Lines: 166 There is no 2.4 GHz or 5GHz antenna gain stored in sprom. The sprom just stores the gain values for antenna 1 and 2 or 1 to 4 for more recent sprom versions. On old devices antenna 2 was used for 5 GHz wifi. Signed-off-by: Hauke Mehrtens --- drivers/net/wireless/b43legacy/phy.c | 2 +- drivers/ssb/pci.c | 40 ++++++++++++---------------------- drivers/ssb/pcmcia.c | 12 +++------ drivers/ssb/sdio.c | 12 +++------ include/linux/ssb/ssb.h | 7 +----- 5 files changed, 24 insertions(+), 49 deletions(-) diff --git a/drivers/net/wireless/b43legacy/phy.c b/drivers/net/wireless/b43legacy/phy.c index 96faaef..9503341 100644 --- a/drivers/net/wireless/b43legacy/phy.c +++ b/drivers/net/wireless/b43legacy/phy.c @@ -1860,7 +1860,7 @@ void b43legacy_phy_xmitpower(struct b43legacy_wldev *dev) * which accounts for the factor of 4 */ #define REG_MAX_PWR 20 max_pwr = min(REG_MAX_PWR * 4 - - dev->dev->bus->sprom.antenna_gain.ghz24.a0 + - dev->dev->bus->sprom.antenna_gain.a0 - 0x6, max_pwr); /* find the desired power in Q5.2 - power_level is in dBm diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c index befa89e..9d8e39d 100644 --- a/drivers/ssb/pci.c +++ b/drivers/ssb/pci.c @@ -390,20 +390,12 @@ static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); /* Extract the antenna gain values. */ - gain = r123_extract_antgain(out->revision, in, - SSB_SPROM1_AGAIN_BG, - SSB_SPROM1_AGAIN_BG_SHIFT); - out->antenna_gain.ghz24.a0 = gain; - out->antenna_gain.ghz24.a1 = gain; - out->antenna_gain.ghz24.a2 = gain; - out->antenna_gain.ghz24.a3 = gain; - gain = r123_extract_antgain(out->revision, in, - SSB_SPROM1_AGAIN_A, - SSB_SPROM1_AGAIN_A_SHIFT); - out->antenna_gain.ghz5.a0 = gain; - out->antenna_gain.ghz5.a1 = gain; - out->antenna_gain.ghz5.a2 = gain; - out->antenna_gain.ghz5.a3 = gain; + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_BG, + SSB_SPROM1_AGAIN_BG_SHIFT); + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_A, + SSB_SPROM1_AGAIN_A_SHIFT); } /* Revs 4 5 and 8 have partially shared layout */ @@ -504,16 +496,14 @@ static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) } /* Extract the antenna gain values. */ - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01, + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01, SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT); - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01, + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01, SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT); - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23, + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23, SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT); - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23, + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23, SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT); - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, - sizeof(out->antenna_gain.ghz5)); sprom_extract_r458(out, in); @@ -602,16 +592,14 @@ static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in) SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0); /* Extract the antenna gain values. */ - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01, + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01, SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT); - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01, + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01, SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT); - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23, + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23, SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT); - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23, + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23, SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT); - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, - sizeof(out->antenna_gain.ghz5)); /* Extract cores power info info */ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) { diff --git a/drivers/ssb/pcmcia.c b/drivers/ssb/pcmcia.c index c821c6b..fbafed5 100644 --- a/drivers/ssb/pcmcia.c +++ b/drivers/ssb/pcmcia.c @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev, case SSB_PCMCIA_CIS_ANTGAIN: GOTO_ERROR_ON(tuple->TupleDataLen != 2, "antg tpl size"); - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1]; - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1]; - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1]; - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1]; - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1]; - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1]; - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1]; - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1]; + sprom->antenna_gain.a0 = tuple->TupleData[1]; + sprom->antenna_gain.a1 = tuple->TupleData[1]; + sprom->antenna_gain.a2 = tuple->TupleData[1]; + sprom->antenna_gain.a3 = tuple->TupleData[1]; break; case SSB_PCMCIA_CIS_BFLAGS: GOTO_ERROR_ON((tuple->TupleDataLen != 3) && diff --git a/drivers/ssb/sdio.c b/drivers/ssb/sdio.c index 63fd709..b2d36f7 100644 --- a/drivers/ssb/sdio.c +++ b/drivers/ssb/sdio.c @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_bus *bus, case SSB_SDIO_CIS_ANTGAIN: GOTO_ERROR_ON(tuple->size != 2, "antg tpl size"); - sprom->antenna_gain.ghz24.a0 = tuple->data[1]; - sprom->antenna_gain.ghz24.a1 = tuple->data[1]; - sprom->antenna_gain.ghz24.a2 = tuple->data[1]; - sprom->antenna_gain.ghz24.a3 = tuple->data[1]; - sprom->antenna_gain.ghz5.a0 = tuple->data[1]; - sprom->antenna_gain.ghz5.a1 = tuple->data[1]; - sprom->antenna_gain.ghz5.a2 = tuple->data[1]; - sprom->antenna_gain.ghz5.a3 = tuple->data[1]; + sprom->antenna_gain.a0 = tuple->data[1]; + sprom->antenna_gain.a1 = tuple->data[1]; + sprom->antenna_gain.a2 = tuple->data[1]; + sprom->antenna_gain.a3 = tuple->data[1]; break; case SSB_SDIO_CIS_BFLAGS: GOTO_ERROR_ON((tuple->size != 3) && diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index f169621..1de5675 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -94,12 +94,7 @@ struct ssb_sprom { * on each band. Values in dBm/4 (Q5.2). Negative gain means the * loss in the connectors is bigger than the gain. */ struct { - struct { - s8 a0, a1, a2, a3; - } ghz24; /* 2.4GHz band */ - struct { - s8 a0, a1, a2, a3; - } ghz5; /* 5GHz band */ + s8 a0, a1, a2, a3; } antenna_gain; struct { -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:33:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:34:22 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35808 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903562Ab2BSSdQ (ORCPT ); Sun, 19 Feb 2012 19:33:16 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id DBD728F62; Sun, 19 Feb 2012 19:33:15 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id i26xLR3f+F0t; Sun, 19 Feb 2012 19:33:02 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id B13108F63; Sun, 19 Feb 2012 19:32:47 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 03/11] ssb: fix per path sprom vars Date: Sun, 19 Feb 2012 19:32:17 +0100 Message-Id: <1329676345-15856-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32472 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 766 Lines: 25 On sprom version 4 and 5 there are 4 values for pa_2g, pa_5gl, pa_5g and pa_5gh, for sprom version 8 and 9 there are only 3. Make the per path sprom store also work for older sprom versions. Signed-off-by: Hauke Mehrtens --- include/linux/ssb/ssb.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 1de5675..4928419 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -19,7 +19,7 @@ struct ssb_driver; struct ssb_sprom_core_pwr_info { u8 itssi_2g, itssi_5g; u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh; - u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3]; + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4]; }; struct ssb_sprom { -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:33:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:34:45 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35820 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903564Ab2BSSd3 (ORCPT ); Sun, 19 Feb 2012 19:33:29 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id A7C788F60; Sun, 19 Feb 2012 19:33:29 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eGuohHB+57WG; Sun, 19 Feb 2012 19:33:15 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 2920C8F64; Sun, 19 Feb 2012 19:32:48 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 04/11] ssb: add ccode Date: Sun, 19 Feb 2012 19:32:18 +0100 Message-Id: <1329676345-15856-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32473 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 790 Lines: 22 This member contains the country code encoded with two chars Signed-off-by: Hauke Mehrtens --- include/linux/ssb/ssb.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 4928419..44e486e 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -33,6 +33,7 @@ struct ssb_sprom { u8 et1mdcport; /* MDIO for enet1 */ u16 board_rev; /* Board revision number from SPROM. */ u8 country_code; /* Country Code */ + char ccode[2]; /* Country Code as two chars like EU or US */ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:33:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:35:09 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35828 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903565Ab2BSSdb (ORCPT ); Sun, 19 Feb 2012 19:33:31 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id CA95A8F63; Sun, 19 Feb 2012 19:33:30 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uqxQ0XaQMfKw; Sun, 19 Feb 2012 19:33:16 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 915AF8F65; Sun, 19 Feb 2012 19:32:48 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 05/11] ssb: add some missing sprom attributes Date: Sun, 19 Feb 2012 19:32:19 +0100 Message-Id: <1329676345-15856-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32474 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2522 Lines: 106 This patch extends the sprom struct to contain all sprom attributes found in sprom version 1 to 9. This was done accordingly to the open source part of the Braodcom SDK. Signed-off-by: Hauke Mehrtens --- include/linux/ssb/ssb.h | 76 ++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 75 insertions(+), 1 deletions(-) diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 44e486e..992c47a 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -32,6 +32,8 @@ struct ssb_sprom { u8 et0mdcport; /* MDIO for enet0 */ u8 et1mdcport; /* MDIO for enet1 */ u16 board_rev; /* Board revision number from SPROM. */ + u16 board_num; /* Board number number from SPROM. */ + u16 board_type; /* Board type number from SPROM. */ u8 country_code; /* Country Code */ char ccode[2]; /* Country Code as two chars like EU or US */ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ @@ -107,7 +109,79 @@ struct ssb_sprom { } ghz5; } fem; - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */ + u16 mcs2gpo[8]; + u16 mcs5gpo[8]; + u16 mcs5glpo[8]; + u16 mcs5ghpo[8]; + u8 opo; + + u8 rxgainerr2ga[3]; + u8 rxgainerr5gla[3]; + u8 rxgainerr5gma[3]; + u8 rxgainerr5gha[3]; + u8 rxgainerr5gua[3]; + + u8 noiselvl2ga[3]; + u8 noiselvl5gla[3]; + u8 noiselvl5gma[3]; + u8 noiselvl5gha[3]; + u8 noiselvl5gua[3]; + + u8 regrev; + u8 txchain; + u8 rxchain; + u8 antswitch; + u16 cddpo; + u16 stbcpo; + u16 bw40po; + u16 bwduppo; + + u8 tempthresh; + u8 tempoffset; + u16 rawtempsense; + u8 measpower; + u8 tempsense_slope; + u8 tempcorrx; + u8 tempsense_option; + u8 freqoffset_corr; + u8 iqcal_swp_dis; + u8 hw_iqcal_en; + u8 elna2g; + u8 elna5g; + u8 phycal_tempdelta; + u8 temps_period; + u8 temps_hysteresis; + u8 measpower1; + u8 measpower2; + u8 pcieingress_war; + + /* power per rate from sromrev 9 */ + u16 cckbw202gpo; + u16 cckbw20ul2gpo; + u32 legofdmbw202gpo; + u32 legofdmbw20ul2gpo; + u32 legofdmbw205glpo; + u32 legofdmbw20ul5glpo; + u32 legofdmbw205gmpo; + u32 legofdmbw20ul5gmpo; + u32 legofdmbw205ghpo; + u32 legofdmbw20ul5ghpo; + u32 mcsbw202gpo; + u32 mcsbw20ul2gpo; + u32 mcsbw402gpo; + u32 mcsbw205glpo; + u32 mcsbw20ul5glpo; + u32 mcsbw405glpo; + u32 mcsbw205gmpo; + u32 mcsbw20ul5gmpo; + u32 mcsbw405gmpo; + u32 mcsbw205ghpo; + u32 mcsbw20ul5ghpo; + u32 mcsbw405ghpo; + u16 mcs32po; + u16 legofdm40duppo; + u8 sar2g; + u8 sar5g; }; /* Information about the PCB the circuitry is soldered on. */ -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:33:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:35:31 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35842 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903555Ab2BSSdn (ORCPT ); Sun, 19 Feb 2012 19:33:43 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 4C8328F6E; Sun, 19 Feb 2012 19:33:43 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mdINB5Misq8k; Sun, 19 Feb 2012 19:33:29 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 0AFDB8F66; Sun, 19 Feb 2012 19:32:49 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 06/11] bcma: export bcma_find_core Date: Sun, 19 Feb 2012 19:32:20 +0100 Message-Id: <1329676345-15856-7-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32475 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1497 Lines: 45 This function is needed by the bcm47xx arch code to get the number of the ieee80211 core. Signed-off-by: Hauke Mehrtens --- drivers/bcma/main.c | 3 ++- include/linux/bcma/bcma.h | 1 + 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c index b8379b9..7e138ec 100644 --- a/drivers/bcma/main.c +++ b/drivers/bcma/main.c @@ -61,7 +61,7 @@ static struct bus_type bcma_bus_type = { .dev_attrs = bcma_device_attrs, }; -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) { struct bcma_device *core; @@ -71,6 +71,7 @@ static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) } return NULL; } +EXPORT_SYMBOL_GPL(bcma_find_core); static void bcma_release_core_dev(struct device *dev) { diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index b9f65fb..46bbd08 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -284,6 +284,7 @@ static inline void bcma_maskset16(struct bcma_device *cc, bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set); } +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid); extern bool bcma_core_is_enabled(struct bcma_device *core); extern void bcma_core_disable(struct bcma_device *core, u32 flags); extern int bcma_core_enable(struct bcma_device *core, u32 flags); -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:33:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:35:56 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35852 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903590Ab2BSSdp (ORCPT ); Sun, 19 Feb 2012 19:33:45 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 1C2918F70; Sun, 19 Feb 2012 19:33:45 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GHeDeJ3sBJEM; Sun, 19 Feb 2012 19:33:31 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 779EC8F67; Sun, 19 Feb 2012 19:32:49 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 07/11] bcma: add support for sprom not found on the device. Date: Sun, 19 Feb 2012 19:32:21 +0100 Message-Id: <1329676345-15856-8-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32476 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4122 Lines: 134 On SoCs the sprom is stored in the nvram in a special partition on the flash chip. The nvram contains the sprom for the main bus, but sometimes also for a pci devices using bcma. This patch makes it possible for the arch code to register a function to fetch the needed sprom from the nvram and provide it to the bcma code. Signed-off-by: Hauke Mehrtens --- drivers/bcma/sprom.c | 75 ++++++++++++++++++++++++++++++++++++++++----- include/linux/bcma/bcma.h | 6 +++ 2 files changed, 73 insertions(+), 8 deletions(-) diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c index ca77525..73c204d 100644 --- a/drivers/bcma/sprom.c +++ b/drivers/bcma/sprom.c @@ -14,6 +14,45 @@ #include #include +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out); + +/** + * bcma_arch_register_fallback_sprom - Registers a method providing a + * fallback SPROM if no SPROM is found. + * + * @sprom_callback: The callback function. + * + * With this function the architecture implementation may register a + * callback handler which fills the SPROM data structure. The fallback is + * used for PCI based BCMA devices, where no valid SPROM can be found + * in the shadow registers and to provide the SPROM for SoCs where BCMA is + * to controll the system bus. + * + * This function is useful for weird architectures that have a half-assed + * BCMA device hardwired to their PCI bus. + * + * This function is available for architecture code, only. So it is not + * exported. + */ +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus, + struct ssb_sprom *out)) +{ + if (get_fallback_sprom) + return -EEXIST; + get_fallback_sprom = sprom_callback; + + return 0; +} + +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus, + struct ssb_sprom *out) +{ + if (!get_fallback_sprom) + return -ENOENT; + + return get_fallback_sprom(bus, out); +} + /************************************************** * R/W ops. **************************************************/ @@ -246,23 +285,43 @@ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom) SSB_SROM8_FEM_ANTSWLUT_SHIFT); } +static bool bcma_is_sprom_available(struct bcma_bus *bus) +{ + u32 sromctrl; + + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM)) + return false; + + if (bus->drv_cc.core->id.rev >= 32) { + sromctrl = bcma_read32(bus->drv_cc.core, BCMA_CC_SROM_CONTROL); + return sromctrl & BCMA_CC_SROM_CONTROL_PRESENT; + } + return true; +} + int bcma_sprom_get(struct bcma_bus *bus) { u16 offset; u16 *sprom; - u32 sromctrl; int err = 0; if (!bus->drv_cc.core) return -EOPNOTSUPP; - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM)) - return -ENOENT; - - if (bus->drv_cc.core->id.rev >= 32) { - sromctrl = bcma_read32(bus->drv_cc.core, BCMA_CC_SROM_CONTROL); - if (!(sromctrl & BCMA_CC_SROM_CONTROL_PRESENT)) - return -ENOENT; + if (!bcma_is_sprom_available(bus)) { + /* + * Maybe there is no SPROM on the device? + * Now we ask the arch code if there is some sprom + * available for this device in some other storage. + */ + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom); + if (err) { + pr_warn("Using fallback SPROM failed (err %d)\n", err); + } else { + pr_debug("Using SPROM revision %d provided by" + " platform.\n", bus->sprom.revision); + return 0; + } } sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 46bbd08..5af9a07 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -176,6 +176,12 @@ int __bcma_driver_register(struct bcma_driver *drv, struct module *owner); extern void bcma_driver_unregister(struct bcma_driver *drv); +/* Set a fallback SPROM. + * See kdoc at the function definition for complete documentation. */ +extern int bcma_arch_register_fallback_sprom( + int (*sprom_callback)(struct bcma_bus *bus, + struct ssb_sprom *out)); + struct bcma_bus { /* The MMIO area. */ void __iomem *mmio; -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:33:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:36:20 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35865 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903592Ab2BSSd5 (ORCPT ); Sun, 19 Feb 2012 19:33:57 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 641268F73; Sun, 19 Feb 2012 19:33:57 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id epN5o04Ke8qu; Sun, 19 Feb 2012 19:33:43 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id E28468F68; Sun, 19 Feb 2012 19:32:49 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 08/11] MIPS: BCM47XX: return number of written bytes in nvram_getenv Date: Sun, 19 Feb 2012 19:32:22 +0100 Message-Id: <1329676345-15856-9-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32477 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 636 Lines: 23 Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/nvram.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index a84e3bb..d43ceff 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -107,8 +107,7 @@ int nvram_getenv(char *name, char *val, size_t val_len) value = eq + 1; if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0) { - snprintf(val, val_len, "%s", value); - return 0; + return snprintf(val, val_len, "%s", value); } } return NVRAM_ERR_ENVNOTFOUND; -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:33:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:36:43 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35873 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903593Ab2BSSd7 (ORCPT ); Sun, 19 Feb 2012 19:33:59 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id C9E728F68; Sun, 19 Feb 2012 19:33:58 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SZrtObMg0s+P; Sun, 19 Feb 2012 19:33:45 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 57F4B8F69; Sun, 19 Feb 2012 19:32:50 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 09/11] MIPS: BCM47XX: fix signature of nvram_parse_macaddr Date: Sun, 19 Feb 2012 19:32:23 +0100 Message-Id: <1329676345-15856-10-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32478 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 793 Lines: 23 Explicitly enforce an char array of 6 bytes for the mac address. Signed-off-by: Hauke Mehrtens --- arch/mips/include/asm/mach-bcm47xx/nvram.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h index 184d5ec..69ef3ef 100644 --- a/arch/mips/include/asm/mach-bcm47xx/nvram.h +++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h @@ -37,7 +37,7 @@ struct nvram_header { extern int nvram_getenv(char *name, char *val, size_t val_len); -static inline void nvram_parse_macaddr(char *buf, u8 *macaddr) +static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6]) { if (strchr(buf, ':')) sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:34:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:37:08 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35891 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903561Ab2BSSeN (ORCPT ); Sun, 19 Feb 2012 19:34:13 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id DF0AD8F79; Sun, 19 Feb 2012 19:34:12 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id s1dPYJTTKjpy; Sun, 19 Feb 2012 19:33:59 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 67EB78F6B; Sun, 19 Feb 2012 19:32:51 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 11/11] MIPS: BCM47XX: provide sprom to bcma bus Date: Sun, 19 Feb 2012 19:32:25 +0100 Message-Id: <1329676345-15856-12-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32479 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3129 Lines: 94 On SoCs the sprom is often stored in nvram in the flashchip. This patch registers a sprom fallback callback handler in bcma and provides the sprom needed for this device. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/setup.c | 39 +++++++++++++++++++++++++++++++++++---- 1 files changed, 35 insertions(+), 4 deletions(-) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 6b0dacd..6f8b073 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -3,7 +3,7 @@ * Copyright (C) 2006 Felix Fietkau * Copyright (C) 2006 Michael Buesch * Copyright (C) 2010 Waldemar Brodkorb - * Copyright (C) 2010-2011 Hauke Mehrtens + * Copyright (C) 2010-2012 Hauke Mehrtens * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -85,7 +85,7 @@ static void bcm47xx_machine_halt(void) } #ifdef CONFIG_BCM47XX_SSB -static int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +static int bcm47xx_get_sprom_ssb(struct ssb_bus *bus, struct ssb_sprom *out) { char prefix[10]; @@ -102,7 +102,7 @@ static int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) } static int bcm47xx_get_invariants(struct ssb_bus *bus, - struct ssb_init_invariants *iv) + struct ssb_init_invariants *iv) { char buf[20]; @@ -132,7 +132,7 @@ static void __init bcm47xx_register_ssb(void) char buf[100]; struct ssb_mipscore *mcore; - err = ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom); + err = ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom_ssb); if (err) printk(KERN_WARNING "bcm47xx: someone else already registered" " a ssb SPROM callback handler (err %d)\n", err); @@ -159,10 +159,41 @@ static void __init bcm47xx_register_ssb(void) #endif #ifdef CONFIG_BCM47XX_BCMA +static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out) +{ + char prefix[10]; + struct bcma_device *core; + + if (bus->hosttype == BCMA_HOSTTYPE_PCI) { + snprintf(prefix, sizeof(prefix), "pci/%u/%u/", + bus->host_pci->bus->number + 1, + PCI_SLOT(bus->host_pci->devfn)); + bcm47xx_fill_sprom(out, prefix); + return 0; + } else if (bus->hosttype == BCMA_HOSTTYPE_SOC) { + bcm47xx_fill_sprom_ethernet(out, NULL); + core = bcma_find_core(bus, BCMA_CORE_80211); + if (core) { + snprintf(prefix, sizeof(prefix), "sb/%u/", + core->core_index); + bcm47xx_fill_sprom(out, prefix); + } + return 0; + } else { + printk(KERN_WARNING "bcm47xx: unable to fill SPROM for given bustype.\n"); + return -EINVAL; + } +} + static void __init bcm47xx_register_bcma(void) { int err; + err = bcma_arch_register_fallback_sprom(&bcm47xx_get_sprom_bcma); + if (err) + printk(KERN_WARNING "bcm47xx: someone else already registered" + " a bcma SPROM callback handler (err %d)\n", err); + err = bcma_host_soc_register(&bcm47xx_bus.bcma); if (err) panic("Failed to initialize BCMA bus (err %d)", err); -- 1.7.5.4 From hauke@hauke-m.de Sun Feb 19 19:34:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:37:33 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:35896 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903594Ab2BSSeP (ORCPT ); Sun, 19 Feb 2012 19:34:15 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 981928F68; Sun, 19 Feb 2012 19:34:15 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id H4019RtjRnUM; Sun, 19 Feb 2012 19:33:57 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id BFC368F6A; Sun, 19 Feb 2012 19:32:50 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, Hauke Mehrtens Subject: [PATCH 10/11] MIPS: BCM47XX: move and extend sprom parsing Date: Sun, 19 Feb 2012 19:32:24 +0100 Message-Id: <1329676345-15856-11-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32480 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 33595 Lines: 826 Move the sprom parsing from nvram into sprom.c. There are all values needed for sprom version 1 to 9 read from nvram and there are more sanity checks added. This is based on the sprom parsing in the open source part of the Broadcom SDK. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/Makefile | 2 +- arch/mips/bcm47xx/setup.c | 151 +------- arch/mips/bcm47xx/sprom.c | 618 ++++++++++++++++++++++++++ arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 3 + 4 files changed, 623 insertions(+), 151 deletions(-) create mode 100644 arch/mips/bcm47xx/sprom.c diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile index 4add173..4389de1 100644 --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile @@ -3,5 +3,5 @@ # under Linux. # -obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o +obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o sprom.o obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index aab6b0c..6b0dacd 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -85,156 +85,7 @@ static void bcm47xx_machine_halt(void) } #ifdef CONFIG_BCM47XX_SSB -#define READ_FROM_NVRAM(_outvar, name, buf) \ - if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\ - sprom->_outvar = simple_strtoul(buf, NULL, 0); - -#define READ_FROM_NVRAM2(_outvar, name1, name2, buf) \ - if (nvram_getprefix(prefix, name1, buf, sizeof(buf)) >= 0 || \ - nvram_getprefix(prefix, name2, buf, sizeof(buf)) >= 0)\ - sprom->_outvar = simple_strtoul(buf, NULL, 0); - -static inline int nvram_getprefix(const char *prefix, char *name, - char *buf, int len) -{ - if (prefix) { - char key[100]; - - snprintf(key, sizeof(key), "%s%s", prefix, name); - return nvram_getenv(key, buf, len); - } - - return nvram_getenv(name, buf, len); -} - -static u32 nvram_getu32(const char *name, char *buf, int len) -{ - int rv; - char key[100]; - u16 var0, var1; - - snprintf(key, sizeof(key), "%s0", name); - rv = nvram_getenv(key, buf, len); - /* return 0 here so this looks like unset */ - if (rv < 0) - return 0; - var0 = simple_strtoul(buf, NULL, 0); - - snprintf(key, sizeof(key), "%s1", name); - rv = nvram_getenv(key, buf, len); - if (rv < 0) - return 0; - var1 = simple_strtoul(buf, NULL, 0); - return var1 << 16 | var0; -} - -static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) -{ - char buf[100]; - u32 boardflags; - - memset(sprom, 0, sizeof(struct ssb_sprom)); - - sprom->revision = 1; /* Fallback: Old hardware does not define this. */ - READ_FROM_NVRAM(revision, "sromrev", buf); - if (nvram_getprefix(prefix, "il0macaddr", buf, sizeof(buf)) >= 0 || - nvram_getprefix(prefix, "macaddr", buf, sizeof(buf)) >= 0) - nvram_parse_macaddr(buf, sprom->il0mac); - if (nvram_getprefix(prefix, "et0macaddr", buf, sizeof(buf)) >= 0) - nvram_parse_macaddr(buf, sprom->et0mac); - if (nvram_getprefix(prefix, "et1macaddr", buf, sizeof(buf)) >= 0) - nvram_parse_macaddr(buf, sprom->et1mac); - READ_FROM_NVRAM(et0phyaddr, "et0phyaddr", buf); - READ_FROM_NVRAM(et1phyaddr, "et1phyaddr", buf); - READ_FROM_NVRAM(et0mdcport, "et0mdcport", buf); - READ_FROM_NVRAM(et1mdcport, "et1mdcport", buf); - READ_FROM_NVRAM(board_rev, "boardrev", buf); - READ_FROM_NVRAM(country_code, "ccode", buf); - READ_FROM_NVRAM(ant_available_a, "aa5g", buf); - READ_FROM_NVRAM(ant_available_bg, "aa2g", buf); - READ_FROM_NVRAM(pa0b0, "pa0b0", buf); - READ_FROM_NVRAM(pa0b1, "pa0b1", buf); - READ_FROM_NVRAM(pa0b2, "pa0b2", buf); - READ_FROM_NVRAM(pa1b0, "pa1b0", buf); - READ_FROM_NVRAM(pa1b1, "pa1b1", buf); - READ_FROM_NVRAM(pa1b2, "pa1b2", buf); - READ_FROM_NVRAM(pa1lob0, "pa1lob0", buf); - READ_FROM_NVRAM(pa1lob2, "pa1lob1", buf); - READ_FROM_NVRAM(pa1lob1, "pa1lob2", buf); - READ_FROM_NVRAM(pa1hib0, "pa1hib0", buf); - READ_FROM_NVRAM(pa1hib2, "pa1hib1", buf); - READ_FROM_NVRAM(pa1hib1, "pa1hib2", buf); - READ_FROM_NVRAM2(gpio0, "ledbh0", "wl0gpio0", buf); - READ_FROM_NVRAM2(gpio1, "ledbh1", "wl0gpio1", buf); - READ_FROM_NVRAM2(gpio2, "ledbh2", "wl0gpio2", buf); - READ_FROM_NVRAM2(gpio3, "ledbh3", "wl0gpio3", buf); - READ_FROM_NVRAM2(maxpwr_bg, "maxp2ga0", "pa0maxpwr", buf); - READ_FROM_NVRAM2(maxpwr_al, "maxp5gla0", "pa1lomaxpwr", buf); - READ_FROM_NVRAM2(maxpwr_a, "maxp5ga0", "pa1maxpwr", buf); - READ_FROM_NVRAM2(maxpwr_ah, "maxp5gha0", "pa1himaxpwr", buf); - READ_FROM_NVRAM2(itssi_bg, "itt5ga0", "pa0itssit", buf); - READ_FROM_NVRAM2(itssi_a, "itt2ga0", "pa1itssit", buf); - READ_FROM_NVRAM(tri2g, "tri2g", buf); - READ_FROM_NVRAM(tri5gl, "tri5gl", buf); - READ_FROM_NVRAM(tri5g, "tri5g", buf); - READ_FROM_NVRAM(tri5gh, "tri5gh", buf); - READ_FROM_NVRAM(txpid2g[0], "txpid2ga0", buf); - READ_FROM_NVRAM(txpid2g[1], "txpid2ga1", buf); - READ_FROM_NVRAM(txpid2g[2], "txpid2ga2", buf); - READ_FROM_NVRAM(txpid2g[3], "txpid2ga3", buf); - READ_FROM_NVRAM(txpid5g[0], "txpid5ga0", buf); - READ_FROM_NVRAM(txpid5g[1], "txpid5ga1", buf); - READ_FROM_NVRAM(txpid5g[2], "txpid5ga2", buf); - READ_FROM_NVRAM(txpid5g[3], "txpid5ga3", buf); - READ_FROM_NVRAM(txpid5gl[0], "txpid5gla0", buf); - READ_FROM_NVRAM(txpid5gl[1], "txpid5gla1", buf); - READ_FROM_NVRAM(txpid5gl[2], "txpid5gla2", buf); - READ_FROM_NVRAM(txpid5gl[3], "txpid5gla3", buf); - READ_FROM_NVRAM(txpid5gh[0], "txpid5gha0", buf); - READ_FROM_NVRAM(txpid5gh[1], "txpid5gha1", buf); - READ_FROM_NVRAM(txpid5gh[2], "txpid5gha2", buf); - READ_FROM_NVRAM(txpid5gh[3], "txpid5gha3", buf); - READ_FROM_NVRAM(rxpo2g, "rxpo2g", buf); - READ_FROM_NVRAM(rxpo5g, "rxpo5g", buf); - READ_FROM_NVRAM(rssisav2g, "rssisav2g", buf); - READ_FROM_NVRAM(rssismc2g, "rssismc2g", buf); - READ_FROM_NVRAM(rssismf2g, "rssismf2g", buf); - READ_FROM_NVRAM(bxa2g, "bxa2g", buf); - READ_FROM_NVRAM(rssisav5g, "rssisav5g", buf); - READ_FROM_NVRAM(rssismc5g, "rssismc5g", buf); - READ_FROM_NVRAM(rssismf5g, "rssismf5g", buf); - READ_FROM_NVRAM(bxa5g, "bxa5g", buf); - READ_FROM_NVRAM(cck2gpo, "cck2gpo", buf); - - sprom->ofdm2gpo = nvram_getu32("ofdm2gpo", buf, sizeof(buf)); - sprom->ofdm5glpo = nvram_getu32("ofdm5glpo", buf, sizeof(buf)); - sprom->ofdm5gpo = nvram_getu32("ofdm5gpo", buf, sizeof(buf)); - sprom->ofdm5ghpo = nvram_getu32("ofdm5ghpo", buf, sizeof(buf)); - - READ_FROM_NVRAM(antenna_gain.ghz24.a0, "ag0", buf); - READ_FROM_NVRAM(antenna_gain.ghz24.a1, "ag1", buf); - READ_FROM_NVRAM(antenna_gain.ghz24.a2, "ag2", buf); - READ_FROM_NVRAM(antenna_gain.ghz24.a3, "ag3", buf); - memcpy(&sprom->antenna_gain.ghz5, &sprom->antenna_gain.ghz24, - sizeof(sprom->antenna_gain.ghz5)); - - if (nvram_getprefix(prefix, "boardflags", buf, sizeof(buf)) >= 0) { - boardflags = simple_strtoul(buf, NULL, 0); - if (boardflags) { - sprom->boardflags_lo = (boardflags & 0x0000FFFFU); - sprom->boardflags_hi = (boardflags & 0xFFFF0000U) >> 16; - } - } - if (nvram_getprefix(prefix, "boardflags2", buf, sizeof(buf)) >= 0) { - boardflags = simple_strtoul(buf, NULL, 0); - if (boardflags) { - sprom->boardflags2_lo = (boardflags & 0x0000FFFFU); - sprom->boardflags2_hi = (boardflags & 0xFFFF0000U) >> 16; - } - } -} - -int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +static int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) { char prefix[10]; diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c new file mode 100644 index 0000000..396f064 --- /dev/null +++ b/arch/mips/bcm47xx/sprom.c @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2006 Michael Buesch + * Copyright (C) 2010 Waldemar Brodkorb + * Copyright (C) 2010-2012 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +static void create_key(const char *prefix, const char *postfix, + const char *name, char *buf, int len) +{ + if (prefix && postfix) + snprintf(buf, len, "%s%s%s", prefix, name, postfix); + else if (prefix) + snprintf(buf, len, "%s%s", prefix, name); + else if (postfix) + snprintf(buf, len, "%s%s", name, postfix); + else + snprintf(buf, len, "%s", name); +} + +#define NVRAM_READ_VAL(type) \ +static void nvram_read_ ## type (const char *prefix, \ + const char *postfix, const char *name, \ + type *val, type allset) \ +{ \ + char buf[100]; \ + char key[40]; \ + int err; \ + type var; \ + \ + create_key(prefix, postfix, name, key, sizeof(key)); \ + \ + err = nvram_getenv(key, buf, sizeof(buf)); \ + if (err < 0) \ + return; \ + err = kstrto ## type (buf, 0, &var); \ + if (err) { \ + pr_warn("can not parse nvram name %s with value %s" \ + " got %i", key, buf, err); \ + return; \ + } \ + if (allset && var == allset) \ + return; \ + *val = var; \ +} + +NVRAM_READ_VAL(u8) +NVRAM_READ_VAL(s8) +NVRAM_READ_VAL(u16) +NVRAM_READ_VAL(u32) + +#undef NVRAM_READ_VAL + +static void nvram_read_u32_2(const char *prefix, const char *name, + u16 *val_lo, u16 *val_hi) +{ + char buf[100]; + char key[40]; + int err; + u32 val; + + create_key(prefix, NULL, name, key, sizeof(key)); + + err = nvram_getenv(key, buf, sizeof(buf)); + if (err < 0) + return; + err = kstrtou32(buf, 0, &val); + if (err) { + pr_warn("can not parse nvram name %s with value %s got %i", + key, buf, err); + return; + } + *val_lo = (val & 0x0000FFFFU); + *val_hi = (val & 0xFFFF0000U) >> 16; +} + +static void nvram_read_leddc(const char *prefix, const char *name, + u8 *leddc_on_time, u8 *leddc_off_time) +{ + char buf[100]; + char key[40]; + int err; + u32 val; + + create_key(prefix, NULL, name, key, sizeof(key)); + + err = nvram_getenv(key, buf, sizeof(buf)); + if (err < 0) + return; + err = kstrtou32(buf, 0, &val); + if (err) { + pr_warn("can not parse nvram name %s with value %s got %i", + key, buf, err); + return; + } + + if (val == 0xffff || val == 0xffffffff) + return; + + *leddc_on_time = val & 0xff; + *leddc_off_time = (val >> 16) & 0xff; +} + +static void nvram_read_macaddr(const char *prefix, const char *name, + u8 (*val)[6]) +{ + char buf[100]; + char key[40]; + int err; + + create_key(prefix, NULL, name, key, sizeof(key)); + + err = nvram_getenv(key, buf, sizeof(buf)); + if (err < 0) + return; + nvram_parse_macaddr(buf, *val); +} + +static void nvram_read_ccode(const char *prefix, const char *name, + char (*val)[2]) +{ + char buf[10]; + char key[40]; + int err; + + create_key(prefix, NULL, name, key, sizeof(key)); + + err = nvram_getenv(key, buf, sizeof(buf)); + if (err < 0) + return; + if (buf[0] == '0') + return; + if (strlen(buf) > 2) { + pr_warn("ccode is too long %s", buf); + return; + } + memcpy(val, buf, sizeof(val)); +} + +static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom, + const char *prefix) +{ + nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0); + nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0); + nvram_read_u8(prefix, NULL, "ledbh0", &sprom->gpio0, 0xff); + nvram_read_u8(prefix, NULL, "ledbh1", &sprom->gpio1, 0xff); + nvram_read_u8(prefix, NULL, "ledbh2", &sprom->gpio2, 0xff); + nvram_read_u8(prefix, NULL, "ledbh3", &sprom->gpio3, 0xff); + nvram_read_u8(prefix, NULL, "aa2g", &sprom->ant_available_bg, 0); + nvram_read_u8(prefix, NULL, "aa5g", &sprom->ant_available_a, 0); + nvram_read_s8(prefix, NULL, "ag0", &sprom->antenna_gain.a0, 0); + nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0); + nvram_read_ccode(prefix, "ccode", &sprom->ccode); +} + +static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom, + const char *prefix) +{ + nvram_read_u16(prefix, NULL, "pa0b0", &sprom->pa0b0, 0); + nvram_read_u16(prefix, NULL, "pa0b1", &sprom->pa0b1, 0); + nvram_read_u16(prefix, NULL, "pa0b2", &sprom->pa0b2, 0); + nvram_read_u8(prefix, NULL, "pa0itssit", &sprom->itssi_bg, 0); + nvram_read_u8(prefix, NULL, "pa0maxpwr", &sprom->maxpwr_bg, 0); + nvram_read_u16(prefix, NULL, "pa1b0", &sprom->pa1b0, 0); + nvram_read_u16(prefix, NULL, "pa1b1", &sprom->pa1b1, 0); + nvram_read_u16(prefix, NULL, "pa1b2", &sprom->pa1b2, 0); + nvram_read_u8(prefix, NULL, "pa1itssit", &sprom->itssi_a, 0); + nvram_read_u8(prefix, NULL, "pa1maxpwr", &sprom->maxpwr_a, 0); +} + +static void bcm47xx_fill_sprom_r1(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u16(prefix, NULL, "boardflags", &sprom->boardflags_lo, 0); + nvram_read_u8(prefix, NULL, "cc", &sprom->country_code, 0); +} + +static void bcm47xx_fill_sprom_r2389(struct ssb_sprom *sprom, + const char *prefix) +{ + nvram_read_u8(prefix, NULL, "opo", &sprom->opo, 0); + nvram_read_u16(prefix, NULL, "pa1lob0", &sprom->pa1lob0, 0); + nvram_read_u16(prefix, NULL, "pa1lob1", &sprom->pa1lob1, 0); + nvram_read_u16(prefix, NULL, "pa1lob2", &sprom->pa1lob2, 0); + nvram_read_u16(prefix, NULL, "pa1hib0", &sprom->pa1hib0, 0); + nvram_read_u16(prefix, NULL, "pa1hib1", &sprom->pa1hib1, 0); + nvram_read_u16(prefix, NULL, "pa1hib2", &sprom->pa1hib2, 0); + nvram_read_u8(prefix, NULL, "pa1lomaxpwr", &sprom->maxpwr_al, 0); + nvram_read_u8(prefix, NULL, "pa1himaxpwr", &sprom->maxpwr_ah, 0); +} + +static void bcm47xx_fill_sprom_r2(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, + &sprom->boardflags_hi); + nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0); +} + +static void bcm47xx_fill_sprom_r389(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u8(prefix, NULL, "bxa2g", &sprom->bxa2g, 0); + nvram_read_u8(prefix, NULL, "rssisav2g", &sprom->rssisav2g, 0); + nvram_read_u8(prefix, NULL, "rssismc2g", &sprom->rssismc2g, 0); + nvram_read_u8(prefix, NULL, "rssismf2g", &sprom->rssismf2g, 0); + nvram_read_u8(prefix, NULL, "bxa5g", &sprom->bxa5g, 0); + nvram_read_u8(prefix, NULL, "rssisav5g", &sprom->rssisav5g, 0); + nvram_read_u8(prefix, NULL, "rssismc5g", &sprom->rssismc5g, 0); + nvram_read_u8(prefix, NULL, "rssismf5g", &sprom->rssismf5g, 0); + nvram_read_u8(prefix, NULL, "tri2g", &sprom->tri2g, 0); + nvram_read_u8(prefix, NULL, "tri5g", &sprom->tri5g, 0); + nvram_read_u8(prefix, NULL, "tri5gl", &sprom->tri5gl, 0); + nvram_read_u8(prefix, NULL, "tri5gh", &sprom->tri5gh, 0); + nvram_read_s8(prefix, NULL, "rxpo2g", &sprom->rxpo2g, 0); + nvram_read_s8(prefix, NULL, "rxpo5g", &sprom->rxpo5g, 0); +} + +static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, + &sprom->boardflags_hi); + nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0); + nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0); + nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time, + &sprom->leddc_off_time); +} + +static void bcm47xx_fill_sprom_r4589(struct ssb_sprom *sprom, + const char *prefix) +{ + nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, + &sprom->boardflags_hi); + nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo, + &sprom->boardflags2_hi); + nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0); + nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0); + nvram_read_s8(prefix, NULL, "ag2", &sprom->antenna_gain.a2, 0); + nvram_read_s8(prefix, NULL, "ag3", &sprom->antenna_gain.a3, 0); + nvram_read_u8(prefix, NULL, "txchain", &sprom->txchain, 0xf); + nvram_read_u8(prefix, NULL, "rxchain", &sprom->rxchain, 0xf); + nvram_read_u8(prefix, NULL, "antswitch", &sprom->antswitch, 0xff); + nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time, + &sprom->leddc_off_time); +} + +static void bcm47xx_fill_sprom_r458(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u16(prefix, NULL, "cck2gpo", &sprom->cck2gpo, 0); + nvram_read_u32(prefix, NULL, "ofdm2gpo", &sprom->ofdm2gpo, 0); + nvram_read_u32(prefix, NULL, "ofdm5gpo", &sprom->ofdm5gpo, 0); + nvram_read_u32(prefix, NULL, "ofdm5glpo", &sprom->ofdm5glpo, 0); + nvram_read_u32(prefix, NULL, "ofdm5ghpo", &sprom->ofdm5ghpo, 0); + nvram_read_u16(prefix, NULL, "cddpo", &sprom->cddpo, 0); + nvram_read_u16(prefix, NULL, "stbcpo", &sprom->stbcpo, 0); + nvram_read_u16(prefix, NULL, "bw40po", &sprom->bw40po, 0); + nvram_read_u16(prefix, NULL, "bwduppo", &sprom->bwduppo, 0); + nvram_read_u16(prefix, NULL, "mcs2gpo0", &sprom->mcs2gpo[0], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo1", &sprom->mcs2gpo[1], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo2", &sprom->mcs2gpo[2], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo3", &sprom->mcs2gpo[3], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo4", &sprom->mcs2gpo[4], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo5", &sprom->mcs2gpo[5], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo6", &sprom->mcs2gpo[6], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo7", &sprom->mcs2gpo[7], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo0", &sprom->mcs5gpo[0], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo1", &sprom->mcs5gpo[1], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo2", &sprom->mcs5gpo[2], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo3", &sprom->mcs5gpo[3], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo4", &sprom->mcs5gpo[4], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo5", &sprom->mcs5gpo[5], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo6", &sprom->mcs5gpo[6], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo7", &sprom->mcs5gpo[7], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo0", &sprom->mcs5glpo[0], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo1", &sprom->mcs5glpo[1], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo2", &sprom->mcs5glpo[2], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo3", &sprom->mcs5glpo[3], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo4", &sprom->mcs5glpo[4], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo5", &sprom->mcs5glpo[5], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo6", &sprom->mcs5glpo[6], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo7", &sprom->mcs5glpo[7], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo0", &sprom->mcs5ghpo[0], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo1", &sprom->mcs5ghpo[1], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo2", &sprom->mcs5ghpo[2], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo3", &sprom->mcs5ghpo[3], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo4", &sprom->mcs5ghpo[4], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo5", &sprom->mcs5ghpo[5], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo6", &sprom->mcs5ghpo[6], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo7", &sprom->mcs5ghpo[7], 0); +} + +static void bcm47xx_fill_sprom_r45(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u8(prefix, NULL, "txpid2ga0", &sprom->txpid2g[0], 0); + nvram_read_u8(prefix, NULL, "txpid2ga1", &sprom->txpid2g[1], 0); + nvram_read_u8(prefix, NULL, "txpid2ga2", &sprom->txpid2g[2], 0); + nvram_read_u8(prefix, NULL, "txpid2ga3", &sprom->txpid2g[3], 0); + nvram_read_u8(prefix, NULL, "txpid5ga0", &sprom->txpid5g[0], 0); + nvram_read_u8(prefix, NULL, "txpid5ga1", &sprom->txpid5g[1], 0); + nvram_read_u8(prefix, NULL, "txpid5ga2", &sprom->txpid5g[2], 0); + nvram_read_u8(prefix, NULL, "txpid5ga3", &sprom->txpid5g[3], 0); + nvram_read_u8(prefix, NULL, "txpid5gla0", &sprom->txpid5gl[0], 0); + nvram_read_u8(prefix, NULL, "txpid5gla1", &sprom->txpid5gl[1], 0); + nvram_read_u8(prefix, NULL, "txpid5gla2", &sprom->txpid5gl[2], 0); + nvram_read_u8(prefix, NULL, "txpid5gla3", &sprom->txpid5gl[3], 0); + nvram_read_u8(prefix, NULL, "txpid5gha0", &sprom->txpid5gh[0], 0); + nvram_read_u8(prefix, NULL, "txpid5gha1", &sprom->txpid5gh[1], 0); + nvram_read_u8(prefix, NULL, "txpid5gha2", &sprom->txpid5gh[2], 0); + nvram_read_u8(prefix, NULL, "txpid5gha3", &sprom->txpid5gh[3], 0); +} + +static void bcm47xx_fill_sprom_r89(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u8(prefix, NULL, "tssipos2g", &sprom->fem.ghz2.tssipos, 0); + nvram_read_u8(prefix, NULL, "extpagain2g", + &sprom->fem.ghz2.extpa_gain, 0); + nvram_read_u8(prefix, NULL, "pdetrange2g", + &sprom->fem.ghz2.pdet_range, 0); + nvram_read_u8(prefix, NULL, "triso2g", &sprom->fem.ghz2.tr_iso, 0); + nvram_read_u8(prefix, NULL, "antswctl2g", &sprom->fem.ghz2.antswlut, 0); + nvram_read_u8(prefix, NULL, "tssipos5g", &sprom->fem.ghz5.tssipos, 0); + nvram_read_u8(prefix, NULL, "extpagain5g", + &sprom->fem.ghz5.extpa_gain, 0); + nvram_read_u8(prefix, NULL, "pdetrange5g", + &sprom->fem.ghz5.pdet_range, 0); + nvram_read_u8(prefix, NULL, "triso5g", &sprom->fem.ghz5.tr_iso, 0); + nvram_read_u8(prefix, NULL, "antswctl5g", &sprom->fem.ghz5.antswlut, 0); + nvram_read_u8(prefix, NULL, "tempthresh", &sprom->tempthresh, 0); + nvram_read_u8(prefix, NULL, "tempoffset", &sprom->tempoffset, 0); + nvram_read_u16(prefix, NULL, "rawtempsense", &sprom->rawtempsense, 0); + nvram_read_u8(prefix, NULL, "measpower", &sprom->measpower, 0); + nvram_read_u8(prefix, NULL, "tempsense_slope", + &sprom->tempsense_slope, 0); + nvram_read_u8(prefix, NULL, "tempcorrx", &sprom->tempcorrx, 0); + nvram_read_u8(prefix, NULL, "tempsense_option", + &sprom->tempsense_option, 0); + nvram_read_u8(prefix, NULL, "freqoffset_corr", + &sprom->freqoffset_corr, 0); + nvram_read_u8(prefix, NULL, "iqcal_swp_dis", &sprom->iqcal_swp_dis, 0); + nvram_read_u8(prefix, NULL, "hw_iqcal_en", &sprom->hw_iqcal_en, 0); + nvram_read_u8(prefix, NULL, "elna2g", &sprom->elna2g, 0); + nvram_read_u8(prefix, NULL, "elna5g", &sprom->elna5g, 0); + nvram_read_u8(prefix, NULL, "phycal_tempdelta", + &sprom->phycal_tempdelta, 0); + nvram_read_u8(prefix, NULL, "temps_period", &sprom->temps_period, 0); + nvram_read_u8(prefix, NULL, "temps_hysteresis", + &sprom->temps_hysteresis, 0); + nvram_read_u8(prefix, NULL, "measpower1", &sprom->measpower1, 0); + nvram_read_u8(prefix, NULL, "measpower2", &sprom->measpower2, 0); + nvram_read_u8(prefix, NULL, "rxgainerr2ga0", + &sprom->rxgainerr2ga[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr2ga1", + &sprom->rxgainerr2ga[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr2ga2", + &sprom->rxgainerr2ga[2], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gla0", + &sprom->rxgainerr5gla[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gla1", + &sprom->rxgainerr5gla[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gla2", + &sprom->rxgainerr5gla[2], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gma0", + &sprom->rxgainerr5gma[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gma1", + &sprom->rxgainerr5gma[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gma2", + &sprom->rxgainerr5gma[2], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gha0", + &sprom->rxgainerr5gha[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gha1", + &sprom->rxgainerr5gha[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gha2", + &sprom->rxgainerr5gha[2], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gua0", + &sprom->rxgainerr5gua[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gua1", + &sprom->rxgainerr5gua[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gua2", + &sprom->rxgainerr5gua[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl2ga0", &sprom->noiselvl2ga[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl2ga1", &sprom->noiselvl2ga[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl2ga2", &sprom->noiselvl2ga[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gla0", + &sprom->noiselvl5gla[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gla1", + &sprom->noiselvl5gla[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gla2", + &sprom->noiselvl5gla[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gma0", + &sprom->noiselvl5gma[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gma1", + &sprom->noiselvl5gma[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gma2", + &sprom->noiselvl5gma[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gha0", + &sprom->noiselvl5gha[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gha1", + &sprom->noiselvl5gha[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gha2", + &sprom->noiselvl5gha[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gua0", + &sprom->noiselvl5gua[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gua1", + &sprom->noiselvl5gua[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gua2", + &sprom->noiselvl5gua[2], 0); + nvram_read_u8(prefix, NULL, "pcieingress_war", + &sprom->pcieingress_war, 0); +} + +static void bcm47xx_fill_sprom_r9(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u16(prefix, NULL, "cckbw202gpo", &sprom->cckbw202gpo, 0); + nvram_read_u16(prefix, NULL, "cckbw20ul2gpo", &sprom->cckbw20ul2gpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw202gpo", + &sprom->legofdmbw202gpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw20ul2gpo", + &sprom->legofdmbw20ul2gpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw205glpo", + &sprom->legofdmbw205glpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw20ul5glpo", + &sprom->legofdmbw20ul5glpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw205gmpo", + &sprom->legofdmbw205gmpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw20ul5gmpo", + &sprom->legofdmbw20ul5gmpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw205ghpo", + &sprom->legofdmbw205ghpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw20ul5ghpo", + &sprom->legofdmbw20ul5ghpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw202gpo", &sprom->mcsbw202gpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw20ul2gpo", &sprom->mcsbw20ul2gpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw402gpo", &sprom->mcsbw402gpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw205glpo", &sprom->mcsbw205glpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw20ul5glpo", + &sprom->mcsbw20ul5glpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw405glpo", &sprom->mcsbw405glpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw205gmpo", &sprom->mcsbw205gmpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw20ul5gmpo", + &sprom->mcsbw20ul5gmpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw405gmpo", &sprom->mcsbw405gmpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw205ghpo", &sprom->mcsbw205ghpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw20ul5ghpo", + &sprom->mcsbw20ul5ghpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw405ghpo", &sprom->mcsbw405ghpo, 0); + nvram_read_u16(prefix, NULL, "mcs32po", &sprom->mcs32po, 0); + nvram_read_u16(prefix, NULL, "legofdm40duppo", + &sprom->legofdm40duppo, 0); + nvram_read_u8(prefix, NULL, "sar2g", &sprom->sar2g, 0); + nvram_read_u8(prefix, NULL, "sar5g", &sprom->sar5g, 0); +} + +static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom, + const char *prefix) +{ + char postfix[2]; + int i; + + for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) { + struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i]; + snprintf(postfix, sizeof(postfix), "%i", i); + nvram_read_u8(prefix, postfix, "maxp2ga", + &pwr_info->maxpwr_2g, 0); + nvram_read_u8(prefix, postfix, "itt2ga", + &pwr_info->itssi_2g, 0); + nvram_read_u8(prefix, postfix, "itt5ga", + &pwr_info->itssi_5g, 0); + nvram_read_u16(prefix, postfix, "pa2gw0a", + &pwr_info->pa_2g[0], 0); + nvram_read_u16(prefix, postfix, "pa2gw1a", + &pwr_info->pa_2g[1], 0); + nvram_read_u16(prefix, postfix, "pa2gw2a", + &pwr_info->pa_2g[2], 0); + nvram_read_u8(prefix, postfix, "maxp5ga", + &pwr_info->maxpwr_5g, 0); + nvram_read_u8(prefix, postfix, "maxp5gha", + &pwr_info->maxpwr_5gh, 0); + nvram_read_u8(prefix, postfix, "maxp5gla", + &pwr_info->maxpwr_5gl, 0); + nvram_read_u16(prefix, postfix, "pa5gw0a", + &pwr_info->pa_5g[0], 0); + nvram_read_u16(prefix, postfix, "pa5gw1a", + &pwr_info->pa_5g[1], 0); + nvram_read_u16(prefix, postfix, "pa5gw2a", + &pwr_info->pa_5g[2], 0); + nvram_read_u16(prefix, postfix, "pa5glw0a", + &pwr_info->pa_5gl[0], 0); + nvram_read_u16(prefix, postfix, "pa5glw1a", + &pwr_info->pa_5gl[1], 0); + nvram_read_u16(prefix, postfix, "pa5glw2a", + &pwr_info->pa_5gl[2], 0); + nvram_read_u16(prefix, postfix, "pa5ghw0a", + &pwr_info->pa_5gh[0], 0); + nvram_read_u16(prefix, postfix, "pa5ghw1a", + &pwr_info->pa_5gh[1], 0); + nvram_read_u16(prefix, postfix, "pa5ghw2a", + &pwr_info->pa_5gh[2], 0); + } +} + +static void bcm47xx_fill_sprom_path_r45(struct ssb_sprom *sprom, + const char *prefix) +{ + char postfix[2]; + int i; + + for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) { + struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i]; + snprintf(postfix, sizeof(postfix), "%i", i); + nvram_read_u16(prefix, postfix, "pa2gw3a", + &pwr_info->pa_2g[3], 0); + nvram_read_u16(prefix, postfix, "pa5gw3a", + &pwr_info->pa_5g[3], 0); + nvram_read_u16(prefix, postfix, "pa5glw3a", + &pwr_info->pa_5gl[3], 0); + nvram_read_u16(prefix, postfix, "pa5ghw3a", + &pwr_info->pa_5gh[3], 0); + } +} + +void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_macaddr(prefix, "et0macaddr", &sprom->et0mac); + nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0); + nvram_read_u8(prefix, NULL, "et0phyaddr", &sprom->et0phyaddr, 0); + + nvram_read_macaddr(prefix, "et1macaddr", &sprom->et1mac); + nvram_read_u8(prefix, NULL, "et1mdcport", &sprom->et1mdcport, 0); + nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0); + + nvram_read_macaddr(prefix, "macaddr", &sprom->il0mac); + nvram_read_macaddr(prefix, "il0macaddr", &sprom->il0mac); +} + +void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) +{ + memset(sprom, 0, sizeof(struct ssb_sprom)); + + bcm47xx_fill_sprom_ethernet(sprom, prefix); + + nvram_read_u8(prefix, NULL, "sromrev", &sprom->revision, 0); + + switch (sprom->revision) { + case 1: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r1(sprom, prefix); + break; + case 2: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r2389(sprom, prefix); + bcm47xx_fill_sprom_r2(sprom, prefix); + break; + case 3: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r2389(sprom, prefix); + bcm47xx_fill_sprom_r389(sprom, prefix); + bcm47xx_fill_sprom_r3(sprom, prefix); + break; + case 4: + case 5: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r4589(sprom, prefix); + bcm47xx_fill_sprom_r458(sprom, prefix); + bcm47xx_fill_sprom_r45(sprom, prefix); + bcm47xx_fill_sprom_path_r4589(sprom, prefix); + bcm47xx_fill_sprom_path_r45(sprom, prefix); + break; + case 8: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r2389(sprom, prefix); + bcm47xx_fill_sprom_r389(sprom, prefix); + bcm47xx_fill_sprom_r4589(sprom, prefix); + bcm47xx_fill_sprom_r458(sprom, prefix); + bcm47xx_fill_sprom_r89(sprom, prefix); + bcm47xx_fill_sprom_path_r4589(sprom, prefix); + break; + case 9: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r2389(sprom, prefix); + bcm47xx_fill_sprom_r389(sprom, prefix); + bcm47xx_fill_sprom_r4589(sprom, prefix); + bcm47xx_fill_sprom_r89(sprom, prefix); + bcm47xx_fill_sprom_r9(sprom, prefix); + bcm47xx_fill_sprom_path_r4589(sprom, prefix); + break; + default: + pr_warn("Unsupported SPROM revision %d detected. Will extract" + " v1\n", sprom->revision); + sprom->revision = 1; + bcm47xx_fill_sprom_r1(sprom, prefix); + } +} diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h index de95e07..5ecaf47 100644 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h @@ -44,4 +44,7 @@ union bcm47xx_bus { extern union bcm47xx_bus bcm47xx_bus; extern enum bcm47xx_bus_type bcm47xx_bus_type; +void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix); +void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, const char *prefix); + #endif /* __ASM_BCM47XX_H */ -- 1.7.5.4 From m@bues.ch Sun Feb 19 19:49:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 19:49:55 +0100 (CET) Received: from bues.ch ([80.190.117.144]:54985 "EHLO bues.ch" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903594Ab2BSStw (ORCPT ); Sun, 19 Feb 2012 19:49:52 +0100 Received: by bues.ch with esmtpsa (Exim 4.72) (envelope-from ) id 1RzBp9-0001lo-65; Sun, 19 Feb 2012 19:49:27 +0100 Date: Sun, 19 Feb 2012 19:49:23 +0100 From: Michael =?UTF-8?B?QsO8c2No?= To: Hauke Mehrtens Cc: linville@tuxdriver.com, zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com Subject: Re: [PATCH 04/11] ssb: add ccode Message-ID: <20120219194923.566f3fe8@milhouse> In-Reply-To: <1329676345-15856-5-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-5-git-send-email-hauke@hauke-m.de> X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.9; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 32481 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m@bues.ch Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 999 Lines: 30 On Sun, 19 Feb 2012 19:32:18 +0100 Hauke Mehrtens wrote: > This member contains the country code encoded with two chars > > Signed-off-by: Hauke Mehrtens > --- > include/linux/ssb/ssb.h | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h > index 4928419..44e486e 100644 > --- a/include/linux/ssb/ssb.h > +++ b/include/linux/ssb/ssb.h > @@ -33,6 +33,7 @@ struct ssb_sprom { > u8 et1mdcport; /* MDIO for enet1 */ > u16 board_rev; /* Board revision number from SPROM. */ > u8 country_code; /* Country Code */ > + char ccode[2]; /* Country Code as two chars like EU or US */ This usually is referred to as "alpha2". So we should name it like that, too. > u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ > u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ > u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ -- Greetings, Michael. From Larry.Finger@lwfinger.net Sun Feb 19 20:14:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 20:14:22 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:45974 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903594Ab2BSTOS (ORCPT ); Sun, 19 Feb 2012 20:14:18 +0100 Received: by iafj26 with SMTP id j26so8082504iaf.36 for ; Sun, 19 Feb 2012 11:14:12 -0800 (PST) Received-SPF: pass (google.com: domain of larry.finger@gmail.com designates 10.42.150.133 as permitted sender) client-ip=10.42.150.133; Authentication-Results: mr.google.com; spf=pass (google.com: domain of larry.finger@gmail.com designates 10.42.150.133 as permitted sender) smtp.mail=larry.finger@gmail.com; dkim=pass header.i=larry.finger@gmail.com Received: from mr.google.com ([10.42.150.133]) by 10.42.150.133 with SMTP id a5mr15838759icw.38.1329678852368 (num_hops = 1); Sun, 19 Feb 2012 11:14:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=eKJqMNdNLvCFEw5nWmbuPB6VaDur90ft8idZc7qqeSQ=; b=jTYs0xBAqtlXhDZA5p+2kZgkagWlD+Z+ZdJVsrq4/btFuKvoJ4bKddjk/4D6eu9lsb xaPi4Gz39FqzI/R62Trsjei8UTK0ysm9lAr/oGPvJvlb0THLfI1WFKLjkiXQjX+P6DUJ 7pT8+eSAeSI8yola7DJKAJ+THJLRrk+4ar8kE= Received: by 10.42.150.133 with SMTP id a5mr12706855icw.38.1329678852296; Sun, 19 Feb 2012 11:14:12 -0800 (PST) Received: from larrylap.site (CPE-75-81-36-228.kc.res.rr.com. [75.81.36.228]) by mx.google.com with ESMTPS id df2sm4976897igb.0.2012.02.19.11.14.10 (version=SSLv3 cipher=OTHER); Sun, 19 Feb 2012 11:14:11 -0800 (PST) Message-ID: <4F4149FC.50900@lwfinger.net> Date: Sun, 19 Feb 2012 13:14:04 -0600 From: Larry Finger User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0) Gecko/20120129 Thunderbird/10.0 MIME-Version: 1.0 To: Hauke Mehrtens CC: linville@tuxdriver.com, zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch Subject: Re: [PATCH 02/11] ssb: remove 5GHz antenna gain from sprom References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-3-git-send-email-hauke@hauke-m.de> In-Reply-To: <1329676345-15856-3-git-send-email-hauke@hauke-m.de> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 32482 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Larry.Finger@lwfinger.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 908 Lines: 22 On 02/19/2012 12:32 PM, Hauke Mehrtens wrote: > There is no 2.4 GHz or 5GHz antenna gain stored in sprom. The sprom > just stores the gain values for antenna 1 and 2 or 1 to 4 for more > recent sprom versions. On old devices antenna 2 was used for 5 GHz wifi. > > Signed-off-by: Hauke Mehrtens > --- > drivers/net/wireless/b43legacy/phy.c | 2 +- > drivers/ssb/pci.c | 40 ++++++++++++---------------------- > drivers/ssb/pcmcia.c | 12 +++------ > drivers/ssb/sdio.c | 12 +++------ > include/linux/ssb/ssb.h | 7 +----- > 5 files changed, 24 insertions(+), 49 deletions(-) After this patch, I get the warning drivers/ssb/pci.c: In function sprom_extract_r123: drivers/ssb/pci.c:334:5: warning: unused variable gain [-Wunused-variable] I am still testing, but all other patches compile OK. Larry From hauke@hauke-m.de Sun Feb 19 20:17:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 20:17:46 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:36171 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903594Ab2BSTRm (ORCPT ); Sun, 19 Feb 2012 20:17:42 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id B783F8F61; Sun, 19 Feb 2012 20:17:41 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZQWsLhITrtj8; Sun, 19 Feb 2012 20:17:28 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 3005F8F60; Sun, 19 Feb 2012 20:17:28 +0100 (CET) Message-ID: <4F414AC6.90709@hauke-m.de> Date: Sun, 19 Feb 2012 20:17:26 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Larry Finger CC: linville@tuxdriver.com, zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch Subject: Re: [PATCH 02/11] ssb: remove 5GHz antenna gain from sprom References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-3-git-send-email-hauke@hauke-m.de> <4F4149FC.50900@lwfinger.net> In-Reply-To: <4F4149FC.50900@lwfinger.net> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit X-archive-position: 32483 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1059 Lines: 28 On 02/19/2012 08:14 PM, Larry Finger wrote: > On 02/19/2012 12:32 PM, Hauke Mehrtens wrote: >> There is no 2.4 GHz or 5GHz antenna gain stored in sprom. The sprom >> just stores the gain values for antenna 1 and 2 or 1 to 4 for more >> recent sprom versions. On old devices antenna 2 was used for 5 GHz wifi. >> >> Signed-off-by: Hauke Mehrtens >> --- >> drivers/net/wireless/b43legacy/phy.c | 2 +- >> drivers/ssb/pci.c | 40 >> ++++++++++++---------------------- >> drivers/ssb/pcmcia.c | 12 +++------ >> drivers/ssb/sdio.c | 12 +++------ >> include/linux/ssb/ssb.h | 7 +----- >> 5 files changed, 24 insertions(+), 49 deletions(-) > > After this patch, I get the warning > > drivers/ssb/pci.c: In function sprom_extract_r123: > drivers/ssb/pci.c:334:5: warning: unused variable gain > [-Wunused-variable] > > I am still testing, but all other patches compile OK. Thanks for the info, I haven't see it. I will fix it in the next round. Hauke From hauke@hauke-m.de Sun Feb 19 20:28:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 20:28:56 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:36218 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903594Ab2BST2x (ORCPT ); Sun, 19 Feb 2012 20:28:53 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 8E73B8F61; Sun, 19 Feb 2012 20:28:52 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CeLvxo6oyga3; Sun, 19 Feb 2012 20:28:38 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id A44DF8F60; Sun, 19 Feb 2012 20:28:37 +0100 (CET) Message-ID: <4F414D63.1070409@hauke-m.de> Date: Sun, 19 Feb 2012 20:28:35 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: =?ISO-8859-1?Q?Michael_B=FCsch?= CC: linville@tuxdriver.com, zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com Subject: Re: [PATCH 04/11] ssb: add ccode References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-5-git-send-email-hauke@hauke-m.de> <20120219194923.566f3fe8@milhouse> In-Reply-To: <20120219194923.566f3fe8@milhouse> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 32484 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1119 Lines: 29 On 02/19/2012 07:49 PM, Michael Bsch wrote: > On Sun, 19 Feb 2012 19:32:18 +0100 > Hauke Mehrtens wrote: > >> This member contains the country code encoded with two chars >> >> Signed-off-by: Hauke Mehrtens >> --- >> include/linux/ssb/ssb.h | 1 + >> 1 files changed, 1 insertions(+), 0 deletions(-) >> >> diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h >> index 4928419..44e486e 100644 >> --- a/include/linux/ssb/ssb.h >> +++ b/include/linux/ssb/ssb.h >> @@ -33,6 +33,7 @@ struct ssb_sprom { >> u8 et1mdcport; /* MDIO for enet1 */ >> u16 board_rev; /* Board revision number from SPROM. */ >> u8 country_code; /* Country Code */ >> + char ccode[2]; /* Country Code as two chars like EU or US */ > > This usually is referred to as "alpha2". So we should name it like that, too. I can not find any references to "alpha2" in the spec, the broadcom code, ssb, bcma or b43. ccode was the name broadcom gave this value so I took it. http://bcm-v4.sipsolutions.net/SPROM wrongly maps ccode to country_code, but cc is stored into country_code in ssb. Hauke From m@bues.ch Sun Feb 19 20:50:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 20:50:45 +0100 (CET) Received: from bues.ch ([80.190.117.144]:55078 "EHLO bues.ch" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903594Ab2BSTul (ORCPT ); Sun, 19 Feb 2012 20:50:41 +0100 Received: by bues.ch with esmtpsa (Exim 4.72) (envelope-from ) id 1RzCm9-0001vz-DV; Sun, 19 Feb 2012 20:50:25 +0100 Date: Sun, 19 Feb 2012 20:50:16 +0100 From: Michael =?UTF-8?B?QsO8c2No?= To: Hauke Mehrtens Cc: linville@tuxdriver.com, zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com Subject: Re: [PATCH 04/11] ssb: add ccode Message-ID: <20120219205016.742a4bad@milhouse> In-Reply-To: <4F414D63.1070409@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-5-git-send-email-hauke@hauke-m.de> <20120219194923.566f3fe8@milhouse> <4F414D63.1070409@hauke-m.de> X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.9; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/3Vd8gdXC+SmlcdlAXIlH2O8"; protocol="application/pgp-signature" X-archive-position: 32485 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m@bues.ch Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1549 Lines: 41 --Sig_/3Vd8gdXC+SmlcdlAXIlH2O8 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Sun, 19 Feb 2012 20:28:35 +0100 Hauke Mehrtens wrote: > >> u8 country_code; /* Country Code */ > >> + char ccode[2]; /* Country Code as two chars like EU or US */ > >=20 > > This usually is referred to as "alpha2". So we should name it like that= , too. > I can not find any references to "alpha2" in the spec http://en.wikipedia.org/wiki/ISO_3166-1_alpha-2 --=20 Greetings, Michael. --Sig_/3Vd8gdXC+SmlcdlAXIlH2O8 Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJPQVJ4AAoJEPUyvh2QjYsOgNEQAMcX1ap8zLbbNOcG2gH+zZz9 9YzgeKgSyjkOIJ5mJYPIEStNMPWXWNZuf5D3lxCMZsnQt9pOeTMGR/QjHzmE4TqZ FZi33q/DSClvpsY5OyDlHPrLqtfjSdKsjd1L/ihoV2yBNNLKviPdpXQowZjgVvur K2ge+swi3eMIR8VEn7nbwyAGlc76SoPWpnpVdlgHxYLhz5CwRCYoa5W6rjEuTCxU d1z+696OpmrqhBS3cT/7GD3HIE6cXL1UknFD40uMAmcdWDKMWFuSbrbIA61YsIKH wrakpxRhY1lfEeMQ1fZGslSBIGYNR1LdVyveLcPwxPGSV+/86I1e4VAxo0OzlRfi NG5Z6CTC0TNZacKR7OZMEmqs7vp6f9LMG2UHvFVdWfL7RsTIIutXD4sjl3RGNHZ3 8MG6I9uqQTXY4BWwLqLQceKeMttAaXqePhRzh8NcAgkZx6uTay0wIff536TVMto5 qxhRU+4xTb+sdgUYo1YdH/VGqjMr0bS/UqeAjRCotp6EZIs3TPpVncDtRZq1UF1U ZPVbWNfALbr1V5iYPYYcEy93okNlfbUC416uMXTI9MmPg7XKTHVpFH0uKloJrJqU iMCpwTFGs4CZ0xZegz6YRMz0OamEwxxVVf4mfqQln/0XjJOErdoos8k/SjS5KtfV VgBbTcLIx8iVNrkZn6fC =ncAt -----END PGP SIGNATURE----- --Sig_/3Vd8gdXC+SmlcdlAXIlH2O8-- From hauke@hauke-m.de Sun Feb 19 21:02:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 21:02:09 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:36339 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903594Ab2BSUCF (ORCPT ); Sun, 19 Feb 2012 21:02:05 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 0D6908F61; Sun, 19 Feb 2012 21:02:05 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tUtydwpgOfHp; Sun, 19 Feb 2012 21:01:50 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 9C91C8F60; Sun, 19 Feb 2012 21:01:50 +0100 (CET) Message-ID: <4F41552D.2020109@hauke-m.de> Date: Sun, 19 Feb 2012 21:01:49 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: =?ISO-8859-1?Q?Michael_B=FCsch?= CC: linville@tuxdriver.com, zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com Subject: Re: [PATCH 04/11] ssb: add ccode References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-5-git-send-email-hauke@hauke-m.de> <20120219194923.566f3fe8@milhouse> <4F414D63.1070409@hauke-m.de> <20120219205016.742a4bad@milhouse> In-Reply-To: <20120219205016.742a4bad@milhouse> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 32486 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1415 Lines: 36 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 02/19/2012 08:50 PM, Michael Bsch wrote: > On Sun, 19 Feb 2012 20:28:35 +0100 Hauke Mehrtens > wrote: >>>> u8 country_code; /* Country Code */ + char ccode[2]; /* >>>> Country Code as two chars like EU or US */ >>> >>> This usually is referred to as "alpha2". So we should name it >>> like that, too. >> I can not find any references to "alpha2" in the spec > > http://en.wikipedia.org/wiki/ISO_3166-1_alpha-2 > OK, I will rename it. Hauke -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJPQVUWAAoJEIZ0px9YPRMyiJgP/i8PzgoVBhlPcUwdDwigbDVw oUcRWdLs6Elo1cvfao0Txu3ntB02bT7wKn262AYgRUUPerp2CmvF9jEXziSLFV5L /GEzkm2+yyM+dYNatL+6De9qNZGdzzJNR4lHZ/7aAFzE/0PY9Pg5OvY8cZdJDPb5 jQK97Vjdd1mfpFYpEJYUw24JOa/fF4+Ve/yHSjSJ3djf60h7i2GVWf/QBlQXNRc5 TEKb95wQUwXmGDjgkO41ZtmtN0XA506FzU5uy6kLFKTuiWM6EDcKQWhlfw+S90pR 7PpbyAvzLyZKpiOutV9SHgW0eimhFmEo9H7f3bwkBLDjkJKmEKrK3pqZ3pz8VQdK JfOijxPnd91UAPUkIvDv7aFgrAt+HCYYq5T6KFsLvk4kLLX36Sgoxe3f+htBd2Mj +as0i2xFBWniifAnPA1oWRGJsNvDAFDuix8XSaNqkz9RxCEZ+35KE4jw9rsqUwKJ vYPmKZsen9YmI72N82eT/nww31Ppkc4p9JdvHn8qsa3G/QjA/fYm3r7ymOrOcA4o Wb1MBx9584jukks1/HgVueUf77rj0q5A99bvuMuKpwrvtX0HlWBUdvG90oUJl5wL cF0almhAj2oB4DfHaaAseFlq52WRF2VSXS296VZ8k7EZfnFELxtHrDXC7ku9jaut 92sDSHze8ron+1PmclEm =BIVY -----END PGP SIGNATURE----- From netrolller.3d@gmail.com Sun Feb 19 23:16:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Feb 2012 23:16:53 +0100 (CET) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:58638 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903554Ab2BSWQu convert rfc822-to-8bit (ORCPT ); Sun, 19 Feb 2012 23:16:50 +0100 Received: by lahg1 with SMTP id g1so7127433lah.36 for ; Sun, 19 Feb 2012 14:16:44 -0800 (PST) Received-SPF: pass (google.com: domain of netrolller.3d@gmail.com designates 10.152.125.20 as permitted sender) client-ip=10.152.125.20; Authentication-Results: mr.google.com; spf=pass (google.com: domain of netrolller.3d@gmail.com designates 10.152.125.20 as permitted sender) smtp.mail=netrolller.3d@gmail.com; dkim=pass header.i=netrolller.3d@gmail.com Received: from mr.google.com ([10.152.125.20]) by 10.152.125.20 with SMTP id mm20mr13296693lab.6.1329689804494 (num_hops = 1); Sun, 19 Feb 2012 14:16:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=unAcuzRbWgAf8MFdIqAuNsEK4mQoY8AxOjIfgnvNT7Y=; b=le90sHib75pgisgdq1p9ey/nxXtlg5jzKkfTIJ9WffNY3HmI3S0U8399jVfL+jPoFF +ObUHUNrOgpyg+4/0QisX1Qni/FAvhp7TQwX+u4/F65S80oaFpM7BQCNZYVC8nTT9GJW bCFj7ulbkf1TwstO7MNaDJu5Ov34ClYT8+Tc4= Received: by 10.152.125.20 with SMTP id mm20mr11135692lab.6.1329689803342; Sun, 19 Feb 2012 14:16:43 -0800 (PST) MIME-Version: 1.0 Received: by 10.152.27.104 with HTTP; Sun, 19 Feb 2012 14:16:23 -0800 (PST) In-Reply-To: <1329676345-15856-6-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-6-git-send-email-hauke@hauke-m.de> From: =?ISO-8859-1?Q?G=E1bor_Stefanik?= Date: Sun, 19 Feb 2012 23:16:23 +0100 Message-ID: Subject: Re: [PATCH 05/11] ssb: add some missing sprom attributes To: Hauke Mehrtens Cc: linville@tuxdriver.com, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, b43-dev@lists.infradead.org, m@bues.ch, arend@broadcom.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 32487 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: netrolller.3d@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3621 Lines: 123 On Sun, Feb 19, 2012 at 7:32 PM, Hauke Mehrtens wrote: > This patch extends the sprom struct to contain all sprom attributes > found in sprom version 1 to 9. This was done accordingly to the open > source part of the Braodcom SDK. Typo. > > Signed-off-by: Hauke Mehrtens > --- > include/linux/ssb/ssb.h | 76 ++++++++++++++++++++++++++++++++++++++++++++++- > 1 files changed, 75 insertions(+), 1 deletions(-) > > diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h > index 44e486e..992c47a 100644 > --- a/include/linux/ssb/ssb.h > +++ b/include/linux/ssb/ssb.h > @@ -32,6 +32,8 @@ struct ssb_sprom { > u8 et0mdcport; /* MDIO for enet0 */ > u8 et1mdcport; /* MDIO for enet1 */ > u16 board_rev; /* Board revision number from SPROM. */ > + u16 board_num; /* Board number number from SPROM. */ Please remove the repeated repeated word. > + u16 board_type; /* Board type number from SPROM. */ > u8 country_code; /* Country Code */ > char ccode[2]; /* Country Code as two chars like EU or US */ > u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ > @@ -107,7 +109,79 @@ struct ssb_sprom { > } ghz5; > } fem; > > - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */ > + u16 mcs2gpo[8]; > + u16 mcs5gpo[8]; > + u16 mcs5glpo[8]; > + u16 mcs5ghpo[8]; > + u8 opo; > + > + u8 rxgainerr2ga[3]; > + u8 rxgainerr5gla[3]; > + u8 rxgainerr5gma[3]; > + u8 rxgainerr5gha[3]; > + u8 rxgainerr5gua[3]; > + > + u8 noiselvl2ga[3]; > + u8 noiselvl5gla[3]; > + u8 noiselvl5gma[3]; > + u8 noiselvl5gha[3]; > + u8 noiselvl5gua[3]; > + > + u8 regrev; > + u8 txchain; > + u8 rxchain; > + u8 antswitch; > + u16 cddpo; > + u16 stbcpo; > + u16 bw40po; > + u16 bwduppo; > + > + u8 tempthresh; > + u8 tempoffset; > + u16 rawtempsense; > + u8 measpower; > + u8 tempsense_slope; > + u8 tempcorrx; > + u8 tempsense_option; > + u8 freqoffset_corr; > + u8 iqcal_swp_dis; > + u8 hw_iqcal_en; > + u8 elna2g; > + u8 elna5g; > + u8 phycal_tempdelta; > + u8 temps_period; > + u8 temps_hysteresis; > + u8 measpower1; > + u8 measpower2; > + u8 pcieingress_war; > + > + /* power per rate from sromrev 9 */ > + u16 cckbw202gpo; > + u16 cckbw20ul2gpo; > + u32 legofdmbw202gpo; > + u32 legofdmbw20ul2gpo; > + u32 legofdmbw205glpo; > + u32 legofdmbw20ul5glpo; > + u32 legofdmbw205gmpo; > + u32 legofdmbw20ul5gmpo; > + u32 legofdmbw205ghpo; > + u32 legofdmbw20ul5ghpo; > + u32 mcsbw202gpo; > + u32 mcsbw20ul2gpo; > + u32 mcsbw402gpo; > + u32 mcsbw205glpo; > + u32 mcsbw20ul5glpo; > + u32 mcsbw405glpo; > + u32 mcsbw205gmpo; > + u32 mcsbw20ul5gmpo; > + u32 mcsbw405gmpo; > + u32 mcsbw205ghpo; > + u32 mcsbw20ul5ghpo; > + u32 mcsbw405ghpo; > + u16 mcs32po; > + u16 legofdm40duppo; > + u8 sar2g; > + u8 sar5g; > }; > > /* Information about the PCB the circuitry is soldered on. */ > -- > 1.7.5.4 > > > _______________________________________________ > b43-dev mailing list > b43-dev@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/b43-dev -- Vista: [V]iruses, [I]ntruders, [S]pyware, [T]rojans and [A]dware. :-) From mikael.starvik@axis.com Mon Feb 20 10:34:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Feb 2012 10:34:34 +0100 (CET) Received: from ra.se.axis.com ([195.60.68.13]:33795 "EHLO ra.se.axis.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903556Ab2BTJe2 convert rfc822-to-8bit (ORCPT ); Mon, 20 Feb 2012 10:34:28 +0100 Received: from localhost (localhost [127.0.0.1]) by ra.se.axis.com (Postfix) with ESMTP id 9D61216730C for ; Mon, 20 Feb 2012 10:34:22 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at ra.se.axis.com Received: from ra.se.axis.com ([127.0.0.1]) by localhost (ra.se.axis.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id aTXY57rIJBFe for ; Mon, 20 Feb 2012 10:34:22 +0100 (CET) Received: from seth.se.axis.com (seth.se.axis.com [10.0.2.172]) by ra.se.axis.com (Postfix) with ESMTP id 195141672C1 for ; Mon, 20 Feb 2012 10:34:22 +0100 (CET) Received: from xmail3.se.axis.com (xmail3.se.axis.com [10.0.5.75]) by seth.se.axis.com (Postfix) with ESMTP id 058EA3E0A5 for ; Mon, 20 Feb 2012 10:34:22 +0100 (CET) Received: from xmail3.se.axis.com ([10.0.5.75]) by xmail3.se.axis.com ([10.0.5.75]) with mapi; Mon, 20 Feb 2012 10:34:22 +0100 From: Mikael Starvik To: "linux-mips@linux-mips.org" Date: Mon, 20 Feb 2012 10:34:20 +0100 Subject: SMP MIPS and Linux 3.2 Thread-Topic: SMP MIPS and Linux 3.2 Thread-Index: AcznH9lfpXUbAgVmQ5aJnfIX4n0HcAIkubIw Message-ID: <4BEA3FF3CAA35E408EA55C7BE2E61D055C769FECBC@xmail3.se.axis.com> Accept-Language: sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: sv-SE Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 32488 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mikael.starvik@axis.com Precedence: bulk X-list: linux-mips Return-Path: Status: RO Content-Length: 640 Lines: 12 I'm running Linux 3.2 on a MIPS 34K with two VPEs (in MT_SMP configuration). It works fine in UP but with SMP it deadlocks during bootup (both CPUs gets idle). Typically like this: [ 0.090000] CPU revision is: 01019550 (MIPS 34Kc) [ 0.090000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. [ 0.090000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.170000] Brought up 2 CPUs I have tried to enable __ARCH_WANT_INTERRUPTS_ON_CTXSW but that didn't improve anything. Anyone else got this running or have any thoughts about what the problem may be? Best Regards /Mikael From sshtylyov@mvista.com Mon Feb 20 12:10:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Feb 2012 12:10:24 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:51291 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903555Ab2BTLKR (ORCPT ); Mon, 20 Feb 2012 12:10:17 +0100 Received: by bkcjk13 with SMTP id jk13so6371256bkc.36 for ; Mon, 20 Feb 2012 03:10:11 -0800 (PST) Received-SPF: pass (google.com: domain of sshtylyov@mvista.com designates 10.205.137.136 as permitted sender) client-ip=10.205.137.136; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sshtylyov@mvista.com designates 10.205.137.136 as permitted sender) smtp.mail=sshtylyov@mvista.com Received: from mr.google.com ([10.205.137.136]) by 10.205.137.136 with SMTP id io8mr11070912bkc.106.1329736211567 (num_hops = 1); Mon, 20 Feb 2012 03:10:11 -0800 (PST) Received: by 10.205.137.136 with SMTP id io8mr8954532bkc.106.1329736211355; Mon, 20 Feb 2012 03:10:11 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-78-89.pppoe.mtu-net.ru. [91.79.78.89]) by mx.google.com with ESMTPS id e13sm38364206bku.12.2012.02.20.03.10.09 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Feb 2012 03:10:10 -0800 (PST) Message-ID: <4F4229C7.1070107@mvista.com> Date: Mon, 20 Feb 2012 15:08:55 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: Hauke Mehrtens CC: linville@tuxdriver.com, zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch Subject: Re: [PATCH 11/11] MIPS: BCM47XX: provide sprom to bcma bus References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-12-git-send-email-hauke@hauke-m.de> In-Reply-To: <1329676345-15856-12-git-send-email-hauke@hauke-m.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQntviHJXerQJjHAC5Y9tyHCenMZbE/mfd3v2iTeKyiBaEfALhWYyMdgbExAsmeRNeF4EvTT X-archive-position: 32489 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1948 Lines: 65 Hello. On 19-02-2012 22:32, Hauke Mehrtens wrote: > On SoCs the sprom is often stored in nvram in the flashchip. This patch > registers a sprom fallback callback handler in bcma and provides the > sprom needed for this device. > Signed-off-by: Hauke Mehrtens > --- > arch/mips/bcm47xx/setup.c | 39 +++++++++++++++++++++++++++++++++++---- > 1 files changed, 35 insertions(+), 4 deletions(-) > diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c > index 6b0dacd..6f8b073 100644 > --- a/arch/mips/bcm47xx/setup.c > +++ b/arch/mips/bcm47xx/setup.c [...] > @@ -159,10 +159,41 @@ static void __init bcm47xx_register_ssb(void) > #endif > > #ifdef CONFIG_BCM47XX_BCMA > +static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out) > +{ > + char prefix[10]; > + struct bcma_device *core; > + > + if (bus->hosttype == BCMA_HOSTTYPE_PCI) { Why not *switch* statement? It seems more natural in this situation... > + snprintf(prefix, sizeof(prefix), "pci/%u/%u/", > + bus->host_pci->bus->number + 1, > + PCI_SLOT(bus->host_pci->devfn)); > + bcm47xx_fill_sprom(out, prefix); > + return 0; > + } else if (bus->hosttype == BCMA_HOSTTYPE_SOC) { > + bcm47xx_fill_sprom_ethernet(out, NULL); > + core = bcma_find_core(bus, BCMA_CORE_80211); > + if (core) { > + snprintf(prefix, sizeof(prefix), "sb/%u/", > + core->core_index); > + bcm47xx_fill_sprom(out, prefix); > + } > + return 0; > + } else { > + printk(KERN_WARNING "bcm47xx: unable to fill SPROM for given bustype.\n"); > + return -EINVAL; > + } > +} > + > static void __init bcm47xx_register_bcma(void) > { > int err; > > + err = bcma_arch_register_fallback_sprom(&bcm47xx_get_sprom_bcma); > + if (err) > + printk(KERN_WARNING "bcm47xx: someone else already registered" pr_warn(). And don't break the message to help grepping. > + " a bcma SPROM callback handler (err %d)\n", err); > + WBR, Sergei From n-a-zhubr@yandex.ru Mon Feb 20 20:07:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Feb 2012 20:07:52 +0100 (CET) Received: from forward10.mail.yandex.net ([77.88.61.49]:47681 "EHLO forward10.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903565Ab2BTTHp (ORCPT ); Mon, 20 Feb 2012 20:07:45 +0100 Received: from smtp8.mail.yandex.net (smtp8.mail.yandex.net [77.88.61.54]) by forward10.mail.yandex.net (Yandex) with ESMTP id DD4C11020EE9; Mon, 20 Feb 2012 23:07:23 +0400 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1329764843; bh=U/R5XbpG3r+JHUnzPXx1zuYexHX9mG3NbKVCkQ9QlHA=; h=Message-ID:Date:From:MIME-Version:To:Subject:Content-Type: Content-Transfer-Encoding; b=Fjrdp05POiwf1MESqOjeGN9bx0BTp/IG0GYy1vNirih1AY37mz9pygDhVrocN6JxW vu74CkpAaqJheetD+fkN/dH7IA310J/xEwKSPSuZObXvWqWptCWTxjnaZJebFLwjK+ CPSj82lV90+Swl+ms65doxoG76F2PQSrqxfPKcF8= Received: from smtp8.mail.yandex.net (localhost [127.0.0.1]) by smtp8.mail.yandex.net (Yandex) with ESMTP id B7E3B1B604C7; Mon, 20 Feb 2012 23:07:23 +0400 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1329764843; bh=U/R5XbpG3r+JHUnzPXx1zuYexHX9mG3NbKVCkQ9QlHA=; h=Message-ID:Date:From:MIME-Version:To:Subject:Content-Type: Content-Transfer-Encoding; b=Fjrdp05POiwf1MESqOjeGN9bx0BTp/IG0GYy1vNirih1AY37mz9pygDhVrocN6JxW vu74CkpAaqJheetD+fkN/dH7IA310J/xEwKSPSuZObXvWqWptCWTxjnaZJebFLwjK+ CPSj82lV90+Swl+ms65doxoG76F2PQSrqxfPKcF8= Received: from unknown (unknown [94.242.50.174]) by smtp8.mail.yandex.net (nwsmtp/Yandex) with ESMTP id 7Neq0pmo-7NeqalPf; Mon, 20 Feb 2012 23:07:23 +0400 X-Yandex-Spam: 1 Message-ID: <4F429B4C.9070600@yandex.ru> Date: Mon, 20 Feb 2012 23:13:16 +0400 From: Nikolai Zhubr User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; ru; rv:1.9.1.5) Gecko/20091204 Thunderbird/3.0 MIME-Version: 1.0 To: OpenWrt Development List , linux-mips@linux-mips.org Subject: kexec on mips Content-Type: text/plain; charset=KOI8-R; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32490 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n-a-zhubr@yandex.ru Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1618 Lines: 37 Hello all, I'm running both openwrt and debian on a mips-based wndr3800 netgear router/ap and I'm using kexec to arrange kind of dual-boot in a safe and comfortable manner. Now, I've found that the following is critical for kexec to actually work: --- arch/mips/kernel/machine_kexec.c.orig 2012-02-08 01:58:13.000000000 +0300 +++ arch/mips/kernel/machine_kexec.c 2012-02-20 22:19:11.000000000 +0300 @@ -52,7 +52,7 @@ reboot_code_buffer = (unsigned long)page_address(image->control_code_page); - kexec_start_address = image->start; + kexec_start_address = (unsigned long) phys_to_virt(image->start); kexec_indirection_page = (unsigned long) phys_to_virt(image->head & PAGE_MASK); I've found that in openwrt repository this change was present (among others) in a big patchset targeted for kernel 2.6.30 and now it is still present as a small separate patch for 2.6.38 (target/linux/generic/patches-2.6.38/303-mips_fix_kexec.patch) and maybe others. Meanwhile, the latest _stable_ openwrt for the moment (backfire 10.03.1) was released with kernel 2.6.32 without this patch so I had to dig through some forums to find the reason of kexec not working out-of-the-box. I've just now checked and the latest kernel.org's stable kernel (3.2.6) does not seem to include this either. Ok, since I know the secret already I'll fix it for myself anytime, but maybe some kind soul could just submit this _one_ line upstream? I'd say this feature is really handy in some cases. Thank you. (Please CC me, I'm not subscribed to linux-mips) Nikolai From tiejun.chen@windriver.com Tue Feb 21 03:12:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Feb 2012 03:12:32 +0100 (CET) Received: from mail1.windriver.com ([147.11.146.13]:51396 "EHLO mail1.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903695Ab2BUCM2 (ORCPT ); Tue, 21 Feb 2012 03:12:28 +0100 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail1.windriver.com (8.14.3/8.14.3) with ESMTP id q1L2CEc2016165 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Mon, 20 Feb 2012 18:12:15 -0800 (PST) Received: from [128.224.162.71] (128.224.162.71) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server id 14.1.255.0; Mon, 20 Feb 2012 18:12:14 -0800 Message-ID: <4F42FD60.4090201@windriver.com> Date: Tue, 21 Feb 2012 10:11:44 +0800 From: "tiejun.chen" User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 To: Mikael Starvik CC: "linux-mips@linux-mips.org" Subject: Re: SMP MIPS and Linux 3.2 References: <4BEA3FF3CAA35E408EA55C7BE2E61D055C769FECBC@xmail3.se.axis.com> In-Reply-To: <4BEA3FF3CAA35E408EA55C7BE2E61D055C769FECBC@xmail3.se.axis.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-archive-position: 32491 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiejun.chen@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1011 Lines: 21 Mikael Starvik wrote: > I'm running Linux 3.2 on a MIPS 34K with two VPEs (in MT_SMP configuration). It works fine in UP but with SMP it deadlocks during bootup (both CPUs gets idle). Typically like this: > > [��� 0.090000] CPU revision is: 01019550 (MIPS 34Kc) > [��� 0.090000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. > [��� 0.090000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes > [��� 0.170000] Brought up 2 CPUs > > > I have tried to enable __ARCH_WANT_INTERRUPTS_ON_CTXSW but that didn't improve anything. Anyone else got this running or have any thoughts about what the problem may be? > I think using git-bisect is the simplest way to figure out this if you already know one kernel version is fine for mips 34kc. Or did you try to pass 'nosmp' into the kernel command line? If good maybe you're hitting some locking issues. You can enable those Kconfig options to probe-to-debug these locking problem. Tiejun From ralf@linux-mips.org Tue Feb 21 11:34:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Feb 2012 11:35:02 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:41425 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903711Ab2BUKe6 (ORCPT ); Tue, 21 Feb 2012 11:34:58 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q1LAYuCM016140; Tue, 21 Feb 2012 11:34:56 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q1LAYtNe016139; Tue, 21 Feb 2012 11:34:55 +0100 Date: Tue, 21 Feb 2012 11:34:55 +0100 From: Ralf Baechle To: Mikael Starvik Cc: "linux-mips@linux-mips.org" Subject: Re: SMP MIPS and Linux 3.2 Message-ID: <20120221103455.GA13347@linux-mips.org> References: <4BEA3FF3CAA35E408EA55C7BE2E61D055C769FECBC@xmail3.se.axis.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4BEA3FF3CAA35E408EA55C7BE2E61D055C769FECBC@xmail3.se.axis.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32492 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 985 Lines: 20 On Mon, Feb 20, 2012 at 10:34:20AM +0100, Mikael Starvik wrote: > I'm running Linux 3.2 on a MIPS 34K with two VPEs (in MT_SMP configuration). It works fine in UP but with SMP it deadlocks during bootup (both CPUs gets idle). Typically like this: > > [ 0.090000] CPU revision is: 01019550 (MIPS 34Kc) > [ 0.090000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. > [ 0.090000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes > [ 0.170000] Brought up 2 CPUs > > > I have tried to enable __ARCH_WANT_INTERRUPTS_ON_CTXSW but that didn't > improve anything. Anyone else got this running or have any thoughts about > what the problem may be? It used to work ... Are you testing this on Malta? In my experience if a CPU hangs at this stage it often is because it does not receive a timer tick, so all changes to the timer code are candidates to be reviewed. Git bisect may be the way of least resistance here. Ralf From john@phrozen.org Tue Feb 21 16:33:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Feb 2012 16:33:25 +0100 (CET) Received: from nbd.name ([46.4.11.11]:49288 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903723Ab2BUPdS (ORCPT ); Tue, 21 Feb 2012 16:33:18 +0100 Message-ID: <4F43B932.9090103@phrozen.org> Date: Tue, 21 Feb 2012 16:33:06 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.20) Gecko/20110820 Icedove/3.1.12 MIME-Version: 1.0 To: Ralf Baechle CC: Mikael Starvik , "linux-mips@linux-mips.org" Subject: Re: SMP MIPS and Linux 3.2 References: <4BEA3FF3CAA35E408EA55C7BE2E61D055C769FECBC@xmail3.se.axis.com> <20120221103455.GA13347@linux-mips.org> In-Reply-To: <20120221103455.GA13347@linux-mips.org> X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32493 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2178 Lines: 64 Hi, i am getting this. looks like ralf is right and the timer irqs get lost. running with nosmp works like a charm. John CPU Clock: 333MHz Calibrating delay loop... 221.18 BogoMIPS (lpj=442368) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 CPU revision is: 0001954c (MIPS 34Kc) Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. Primary data cache 16kB, 4-way, VIPT, no aliases, linesize 32 bytes Brought up 2 CPUs INFO: rcu_sched detected stall on CPU 0 (t=15000 jiffies) INFO: rcu_sched detected stall on CPU 1 (t=15000 jiffies) Call Trace: [<802c310c>] dump_stack+0x8/0x34 [<8007e280>] print_cpu_stall+0x40/0xf0 [<8007e630>] __rcu_pending+0x110/0x270 [<8007fa44>] rcu_check_callbacks+0x78/0x180 [<80035234>] update_process_times+0x40/0x6c [<80069acc>] tick_handle_periodic+0x38/0x170 [<8000c8f4>] c0_compare_interrupt+0x78/0xbc [<80077740>] handle_irq_event_percpu+0x78/0x294 [<8007ba08>] handle_percpu_irq+0x8c/0xc0 [<80076dd0>] generic_handle_irq+0x40/0x50 [<80006650>] do_IRQ+0x18/0x28 [<80004aec>] ret_from_irq+0x0/0x4 [<8002e3c0>] __do_softirq+0x84/0x1ac [<8002e744>] do_softirq+0x78/0x80 [<8002e9f4>] irq_exit+0x80/0x8c [<80004aec>] ret_from_irq+0x0/0x4 [<80004ce0>] r4k_wait+0x20/0x40 [<800069d8>] cpu_idle+0x7c/0xa4 Call Trace: [<802c310c>] dump_stack+0x8/0x34 [<8007e280>] print_cpu_stall+0x40/0xf0 [<8007e630>] __rcu_pending+0x110/0x270 [<8007fae4>] rcu_check_callbacks+0x118/0x180 [<80035234>] update_process_times+0x40/0x6c [<80069acc>] tick_handle_periodic+0x38/0x170 [<8000c8f4>] c0_compare_interrupt+0x78/0xbc [<80077740>] handle_irq_event_percpu+0x78/0x294 [<8007ba08>] handle_percpu_irq+0x8c/0xc0 [<80076dd0>] generic_handle_irq+0x40/0x50 [<80006650>] do_IRQ+0x18/0x28 [<80004aec>] ret_from_irq+0x0/0x4 [<8006fcf0>] generic_exec_single+0x98/0xfc [<8006ff3c>] smp_call_function_single+0x1e8/0x1f0 [<800704e0>] smp_call_function+0x28/0x38 [<80070510>] on_each_cpu+0x20/0x64 [<800bbdac>] do_tune_cpucache+0x130/0x238 [<800bc09c>] enable_cpucache+0x60/0xf8 [<800bc4a0>] kmem_cache_create+0x36c/0x554 [<803705e0>] shmem_init+0x60/0xf8 [<80366998>] kernel_init+0x94/0x154 [<80006954>] kernel_thread_helper+0x10/0x18 From linville@tuxdriver.com Tue Feb 21 20:46:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Feb 2012 20:47:04 +0100 (CET) Received: from charlotte.tuxdriver.com ([70.61.120.58]:39460 "EHLO smtp.tuxdriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903730Ab2BUTq5 (ORCPT ); Tue, 21 Feb 2012 20:46:57 +0100 Received: from uucp by smtp.tuxdriver.com with local-rmail (Exim 4.63) (envelope-from ) id 1Rzvfk-0000eT-J9; Tue, 21 Feb 2012 14:46:48 -0500 Received: from linville-8530p.local (linville-8530p.local [127.0.0.1]) by linville-8530p.local (8.14.4/8.14.4) with ESMTP id q1LJbkJf027473; Tue, 21 Feb 2012 14:37:47 -0500 Received: (from linville@localhost) by linville-8530p.local (8.14.4/8.14.4/Submit) id q1LJbimR027471; Tue, 21 Feb 2012 14:37:44 -0500 Date: Tue, 21 Feb 2012 14:37:44 -0500 From: "John W. Linville" To: Hauke Mehrtens Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch Subject: Re: [PATCH 00/11] ssb/bcma/BCM47XX: sprom fixes and extensions Message-ID: <20120221193744.GB19354@tuxdriver.com> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32494 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linville@tuxdriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2511 Lines: 55 Has Ralf seen the arch/mips patches? On Sun, Feb 19, 2012 at 07:32:14PM +0100, Hauke Mehrtens wrote: > This patch series fixes some errors in the sprom structures and extends > it to contain members for all sprom values for sprom version 1 to 9. > This was done by looking into the open source part of the Broadcom SDK. > This also adds a fallback sprom registration method to bcma. > It also contains some small fixes for the bcma47xx arch code and a > rewrite of the code to provide the sprom from flash. It now also > provides sprom from flash for devices using bcma to control the system > bus. > > This patch series is based on wireles-testing. I think it is the best > way to merge this through John's wireless tree as the changes in the > sprom struct should be used in further patches extending the pci sprom > parsing and the usage of struct sprom by the brcmsmac driver. > > Hauke Mehrtens (11): > ssb: sprom fix some sizes / signedness > ssb: remove 5GHz antenna gain from sprom > ssb: fix per path sprom vars > ssb: add ccode > ssb: add some missing sprom attributes > bcma: export bcma_find_core > bcma: add support for sprom not found on the device. > MIPS: BCM47XX: return number of written bytes in nvram_getenv > MIPS: BCM47XX: fix signature of nvram_parse_macaddr > MIPS: BCM47XX: move and extend sprom parsing > MIPS: BCM47XX: provide sprom to bcma bus > > arch/mips/bcm47xx/Makefile | 2 +- > arch/mips/bcm47xx/nvram.c | 3 +- > arch/mips/bcm47xx/setup.c | 188 ++------- > arch/mips/bcm47xx/sprom.c | 618 ++++++++++++++++++++++++++ > arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 3 + > arch/mips/include/asm/mach-bcm47xx/nvram.h | 2 +- > drivers/bcma/main.c | 3 +- > drivers/bcma/sprom.c | 75 +++- > drivers/net/wireless/b43legacy/phy.c | 2 +- > drivers/ssb/pci.c | 40 +-- > drivers/ssb/pcmcia.c | 12 +- > drivers/ssb/sdio.c | 12 +- > include/linux/bcma/bcma.h | 7 + > include/linux/ssb/ssb.h | 102 ++++- > 14 files changed, 844 insertions(+), 225 deletions(-) > create mode 100644 arch/mips/bcm47xx/sprom.c > > -- > 1.7.5.4 > > -- John W. Linville Someday the world will need a hero, and you linville@tuxdriver.com might be all we have. Be ready. From hauke@hauke-m.de Tue Feb 21 20:52:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Feb 2012 20:52:45 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:41265 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903731Ab2BUTwj (ORCPT ); Tue, 21 Feb 2012 20:52:39 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 06BE38F61; Tue, 21 Feb 2012 20:52:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Vw8YbU0KLaDq; Tue, 21 Feb 2012 20:52:25 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 568788F60; Tue, 21 Feb 2012 20:52:25 +0100 (CET) Message-ID: <4F43F5F8.6050108@hauke-m.de> Date: Tue, 21 Feb 2012 20:52:24 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: "John W. Linville" CC: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch Subject: Re: [PATCH 00/11] ssb/bcma/BCM47XX: sprom fixes and extensions References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <20120221193744.GB19354@tuxdriver.com> In-Reply-To: <20120221193744.GB19354@tuxdriver.com> X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32495 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2581 Lines: 57 On 02/21/2012 08:37 PM, John W. Linville wrote: > Has Ralf seen the arch/mips patches? > I just send it to the mips list, I will send v2 of the patches explicitly to him and ask him. > On Sun, Feb 19, 2012 at 07:32:14PM +0100, Hauke Mehrtens wrote: >> This patch series fixes some errors in the sprom structures and extends >> it to contain members for all sprom values for sprom version 1 to 9. >> This was done by looking into the open source part of the Broadcom SDK. >> This also adds a fallback sprom registration method to bcma. >> It also contains some small fixes for the bcma47xx arch code and a >> rewrite of the code to provide the sprom from flash. It now also >> provides sprom from flash for devices using bcma to control the system >> bus. >> >> This patch series is based on wireles-testing. I think it is the best >> way to merge this through John's wireless tree as the changes in the >> sprom struct should be used in further patches extending the pci sprom >> parsing and the usage of struct sprom by the brcmsmac driver. >> >> Hauke Mehrtens (11): >> ssb: sprom fix some sizes / signedness >> ssb: remove 5GHz antenna gain from sprom >> ssb: fix per path sprom vars >> ssb: add ccode >> ssb: add some missing sprom attributes >> bcma: export bcma_find_core >> bcma: add support for sprom not found on the device. >> MIPS: BCM47XX: return number of written bytes in nvram_getenv >> MIPS: BCM47XX: fix signature of nvram_parse_macaddr >> MIPS: BCM47XX: move and extend sprom parsing >> MIPS: BCM47XX: provide sprom to bcma bus >> >> arch/mips/bcm47xx/Makefile | 2 +- >> arch/mips/bcm47xx/nvram.c | 3 +- >> arch/mips/bcm47xx/setup.c | 188 ++------- >> arch/mips/bcm47xx/sprom.c | 618 ++++++++++++++++++++++++++ >> arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 3 + >> arch/mips/include/asm/mach-bcm47xx/nvram.h | 2 +- >> drivers/bcma/main.c | 3 +- >> drivers/bcma/sprom.c | 75 +++- >> drivers/net/wireless/b43legacy/phy.c | 2 +- >> drivers/ssb/pci.c | 40 +-- >> drivers/ssb/pcmcia.c | 12 +- >> drivers/ssb/sdio.c | 12 +- >> include/linux/bcma/bcma.h | 7 + >> include/linux/ssb/ssb.h | 102 ++++- >> 14 files changed, 844 insertions(+), 225 deletions(-) >> create mode 100644 arch/mips/bcm47xx/sprom.c >> >> -- >> 1.7.5.4 >> >> > From mikael.starvik@axis.com Wed Feb 22 11:57:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Feb 2012 11:58:15 +0100 (CET) Received: from ra.se.axis.com ([195.60.68.13]:54732 "EHLO ra.se.axis.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903605Ab2BVK5w convert rfc822-to-8bit (ORCPT ); Wed, 22 Feb 2012 11:57:52 +0100 Received: from localhost (localhost [127.0.0.1]) by ra.se.axis.com (Postfix) with ESMTP id 669341672D4 for ; Wed, 22 Feb 2012 11:57:44 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at ra.se.axis.com Received: from ra.se.axis.com ([127.0.0.1]) by localhost (ra.se.axis.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id N9QsilNDLbto for ; Wed, 22 Feb 2012 11:57:43 +0100 (CET) Received: from thoth.se.axis.com (thoth.se.axis.com [10.0.2.173]) by ra.se.axis.com (Postfix) with ESMTP id 7E61F1672CA for ; Wed, 22 Feb 2012 11:57:43 +0100 (CET) Received: from xmail3.se.axis.com (xmail3.se.axis.com [10.0.5.75]) by thoth.se.axis.com (Postfix) with ESMTP id 6EE1A34083 for ; Wed, 22 Feb 2012 11:57:43 +0100 (CET) Received: from xmail3.se.axis.com ([10.0.5.75]) by xmail3.se.axis.com ([10.0.5.75]) with mapi; Wed, 22 Feb 2012 11:57:43 +0100 From: Mikael Starvik To: "linux-mips@linux-mips.org" Date: Wed, 22 Feb 2012 11:57:42 +0100 Subject: RE: SMP MIPS and Linux 3.2 Thread-Topic: SMP MIPS and Linux 3.2 Thread-Index: AcznH9lfpXUbAgVmQ5aJnfIX4n0HcAIkubIwAGd2VNA= Message-ID: <4BEA3FF3CAA35E408EA55C7BE2E61D055C76C25948@xmail3.se.axis.com> Accept-Language: sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: sv-SE Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 32496 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mikael.starvik@axis.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 881 Lines: 19 Found it! There are no calls to scheduler_ipi() from the MIPS parts in vanilla 3.2. /Mikael -----Original Message----- From: Mikael Starvik Sent: den 20 februari 2012 10:34 To: 'linux-mips@linux-mips.org' Subject: SMP MIPS and Linux 3.2 I'm running Linux 3.2 on a MIPS 34K with two VPEs (in MT_SMP configuration). It works fine in UP but with SMP it deadlocks during bootup (both CPUs gets idle). Typically like this: [ 0.090000] CPU revision is: 01019550 (MIPS 34Kc) [ 0.090000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. [ 0.090000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.170000] Brought up 2 CPUs I have tried to enable __ARCH_WANT_INTERRUPTS_ON_CTXSW but that didn't improve anything. Anyone else got this running or have any thoughts about what the problem may be? Best Regards /Mikael From bhelgaas@google.com Wed Feb 22 19:19:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Feb 2012 19:19:55 +0100 (CET) Received: from mail-gx0-f201.google.com ([209.85.161.201]:49635 "EHLO mail-gx0-f201.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903751Ab2BVSTp (ORCPT ); Wed, 22 Feb 2012 19:19:45 +0100 Received: by ggno5 with SMTP id o5so40206ggn.0 for ; Wed, 22 Feb 2012 10:19:38 -0800 (PST) Received-SPF: pass (google.com: domain of bhelgaas@google.com designates 10.236.131.104 as permitted sender) client-ip=10.236.131.104; Authentication-Results: mr.google.com; spf=pass (google.com: domain of bhelgaas@google.com designates 10.236.131.104 as permitted sender) smtp.mail=bhelgaas@google.com; dkim=pass header.i=bhelgaas@google.com Received: from mr.google.com ([10.236.131.104]) by 10.236.131.104 with SMTP id l68mr67899492yhi.3.1329934778681 (num_hops = 1); Wed, 22 Feb 2012 10:19:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=gamma; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=pFi8IOaM0Mg3d1z6XWls3pdXdM4Wb5twPWGg8IPxZVI=; b=NlMT4B+tStgQzRUxDVvoavu4YI2SdF+d0NzlUEC7oPCtPv/v8KQmnwQ49CgVLm5f6/ IYfDBNq9eku4CAzBrHlq1StPXP2CIaZBd4VkDVHn6ehofqYwRuA1EApeaio/9fehrKIM ontaWCDNPbEBZ6fGNm9G2VYwtmyzQHMjmRNoE= Received: by 10.236.131.104 with SMTP id l68mr48456758yhi.3.1329934778666; Wed, 22 Feb 2012 10:19:38 -0800 (PST) Received: by 10.236.131.104 with SMTP id l68mr48456731yhi.3.1329934778491; Wed, 22 Feb 2012 10:19:38 -0800 (PST) Received: from wpzn3.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id e44si15280575yhk.0.2012.02.22.10.19.38 (version=TLSv1/SSLv3 cipher=AES128-SHA); Wed, 22 Feb 2012 10:19:38 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by wpzn3.hot.corp.google.com (Postfix) with ESMTP id 539C410004D; Wed, 22 Feb 2012 10:19:38 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id 02D5D180085; Wed, 22 Feb 2012 10:19:38 -0800 (PST) Subject: [PATCH v1 07/11] mips/PCI: replace pci_probe_only with pci_flags To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: linux-arch@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle Date: Wed, 22 Feb 2012 11:19:38 -0700 Message-ID: <20120222181937.27513.62108.stgit@bhelgaas.mtv.corp.google.com> In-Reply-To: <20120222181556.27513.9413.stgit@bhelgaas.mtv.corp.google.com> References: <20120222181556.27513.9413.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlqnJ4YKvCNpJVtaEmfz2UakIrbZjvIntVWTIs9iq/UvrFAHUuwSin2qWosHdV2OrFHYlwATS/9jyYX/Qh6kbEE9IN5P6E1b3Qwgs//a/xW3a6JyRDIznYYTWYlHHpNotTT9WOlxwbHyUYrm3JRBsMTUn98p2lxdFbL11K2BFKbSEw4PC4= X-archive-position: 32497 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5018 Lines: 152 Some architectures (alpha, mips, powerpc) have an arch-specific "pci_probe_only" flag. Others use PCI_PROBE_ONLY in pci_flags for the same purpose. This moves mips to the pci_flags approach so generic code can use the same test across all architectures. CC: Ralf Baechle CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas --- arch/mips/include/asm/pci.h | 3 +-- arch/mips/pci/pci-bcm1480.c | 2 +- arch/mips/pci/pci-ip27.c | 2 +- arch/mips/pci/pci-lantiq.c | 3 ++- arch/mips/pci/pci-sb1250.c | 2 +- arch/mips/pci/pci-xlr.c | 2 +- arch/mips/pci/pci.c | 13 +++++-------- 7 files changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 576397c..1e4fa3d 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -92,6 +92,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, #include #include #include +#include struct pci_dev; @@ -145,8 +146,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) #define arch_setup_msi_irqs arch_setup_msi_irqs #endif -extern int pci_probe_only; - extern char * (*pcibios_plat_setup)(char *str); #endif /* _ASM_PCI_H */ diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index af8c319..37b52dc 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -204,7 +204,7 @@ static int __init bcm1480_pcibios_init(void) uint64_t reg; /* CFE will assign PCI resources */ - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); /* Avoid ISA compat ranges. */ PCIBIOS_MIN_IO = 0x00008000UL; diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 193e949..0fbe4c0 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -50,7 +50,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) bridge_t *bridge; int slot; - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); printk("a bridge\n"); diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index be1e1af..030c77e 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -270,7 +270,8 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev) { struct ltq_pci_data *ltq_pci_data = (struct ltq_pci_data *) pdev->dev.platform_data; - pci_probe_only = 0; + + pci_clear_flags(PCI_PROBE_ONLY); ltq_pci_irq_map = ltq_pci_data->irq; ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); ltq_pci_mapped_cfg = diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 1711e8e..dd97f3a 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -213,7 +213,7 @@ static int __init sb1250_pcibios_init(void) uint64_t reg; /* CFE will assign PCI resources */ - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); /* Avoid ISA compat ranges. */ PCIBIOS_MIN_IO = 0x00008000UL; diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 3d701a9..1644805 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -292,7 +292,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) static int __init pcibios_init(void) { /* PSB assigns PCI resources */ - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); /* Extend IO port for memory mapped io */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index aec2b11..2a11045 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -20,12 +20,9 @@ #include /* - * Indicate whether we respect the PCI setup left by the firmware. - * - * Make this long-lived so that we know when shutting down - * whether we probed only or not. + * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource + * assignments. */ -int pci_probe_only; #define PCI_ASSIGN_ALL_BUSSES 1 @@ -92,7 +89,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) if (!hose->iommu) PCI_DMA_BUS_IS_PHYS = 1; - if (hose->get_busno && pci_probe_only) + if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) next_busno = (*hose->get_busno)(); pci_add_resource(&resources, hose->mem_resource); @@ -115,7 +112,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) need_domain_info = 1; } - if (!pci_probe_only) { + if (!pci_has_flag(PCI_PROBE_ONLY)) { pci_bus_size_bridges(bus); pci_bus_assign_resources(bus); pci_enable_bridges(bus); @@ -282,7 +279,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) struct list_head *ln; struct pci_dev *dev = bus->self; - if (pci_probe_only && dev && + if (pci_has_flag(PCI_PROBE_ONLY) && dev && (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { pci_read_bridge_bases(bus); pcibios_fixup_device_resources(dev, bus); From bhelgaas@google.com Wed Feb 22 19:19:49 2012 Received: with ECARTIS (v1.0.0; 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bh=+1Tg68MUrUdkYJBPf4zZzIhJOCahvnx2JOmPQ3BE2v4=; b=Nn97a7sichbh/W2ZK+ZEVISHC7I6pjr3vV77bkyhE2V7wtA0RR/CzlsyulnFnIbtWr 2KzsCx00tYO5oSUq6XpJbKEDWvI3R+/SAMwCUnSOU2p5p8f4EMTDBv4VFJwZcsOCTvTt 85x1YVuvD2uX9p8pzbCyX4DLmtSRFcla8d/Jo= Received: by 10.236.192.164 with SMTP id i24mr48331804yhn.8.1329934783644; Wed, 22 Feb 2012 10:19:43 -0800 (PST) Received: by 10.236.192.164 with SMTP id i24mr48331781yhn.8.1329934783576; Wed, 22 Feb 2012 10:19:43 -0800 (PST) Received: from wpzn3.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id i36si2273774anp.0.2012.02.22.10.19.43 (version=TLSv1/SSLv3 cipher=AES128-SHA); Wed, 22 Feb 2012 10:19:43 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by wpzn3.hot.corp.google.com (Postfix) with ESMTP id 75897100052; Wed, 22 Feb 2012 10:19:43 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id 2B062180085; Wed, 22 Feb 2012 10:19:43 -0800 (PST) Subject: [PATCH v1 08/11] mips/PCI: removed unused pci_probe configurability To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: linux-arch@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle Date: Wed, 22 Feb 2012 11:19:43 -0700 Message-ID: <20120222181943.27513.19771.stgit@bhelgaas.mtv.corp.google.com> In-Reply-To: <20120222181556.27513.9413.stgit@bhelgaas.mtv.corp.google.com> References: <20120222181556.27513.9413.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQmgrbRztsnTkVjiI6fmwSsNFrAfRvMETG+jXjTV7yE4481telE1/RoVeek348w/mZZxXkdMDUsf2+DmwrQAD+QT7/DUnSmMb8NNBICzSjgT3Rus5e9GyAcygzie62oYUYMbPdhqt3HJjp1EvJWZWMAak3+TULzzpUT9SkuqdLURi6y+C9U= X-archive-position: 32498 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1018 Lines: 37 We never assign anything other than PCI_ASSIGN_ALL_BUSSES to pci_probe, so just remove the indirection. If configurability is required in the future, please use the pci_flags/PCI_REASSIGN_ALL_BUS functionality as is done for powerpc. CC: Ralf Baechle CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas --- arch/mips/pci/pci.c | 6 +----- 1 files changed, 1 insertions(+), 5 deletions(-) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 2a11045..19f6d19 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -24,10 +24,6 @@ * assignments. */ -#define PCI_ASSIGN_ALL_BUSSES 1 - -unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; - /* * The PCI controller list. */ @@ -238,7 +234,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) unsigned int pcibios_assign_all_busses(void) { - return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; + return 1; } int pcibios_enable_device(struct pci_dev *dev, int mask) From dengcheng.zhu@gmail.com Thu Feb 23 11:11:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 11:11:18 +0100 (CET) Received: from mail-tul01m020-f177.google.com ([209.85.214.177]:44398 "EHLO mail-tul01m020-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903617Ab2BWKLN convert rfc822-to-8bit (ORCPT ); Thu, 23 Feb 2012 11:11:13 +0100 Received: by obcuz6 with SMTP id uz6so1409180obc.36 for ; Thu, 23 Feb 2012 02:11:07 -0800 (PST) Received-SPF: pass (google.com: domain of dengcheng.zhu@gmail.com designates 10.182.86.201 as permitted sender) client-ip=10.182.86.201; Authentication-Results: mr.google.com; spf=pass (google.com: domain of dengcheng.zhu@gmail.com designates 10.182.86.201 as permitted sender) smtp.mail=dengcheng.zhu@gmail.com; dkim=pass header.i=dengcheng.zhu@gmail.com Received: from mr.google.com ([10.182.86.201]) by 10.182.86.201 with SMTP id r9mr270473obz.8.1329991867618 (num_hops = 1); Thu, 23 Feb 2012 02:11:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=0w8ZJVO532uu07Ef9DAjs4g0gUsg6uxJBsH6nLoTW50=; b=AhS9pDST0CAuHUJOxsYCf+5/bayqFPrBe6PyQ4yVZ9CLzXeYVG65/LyeF6pnVP3WRl w9hduAOnn8mYUSLSbgXNEzW6fSYmi4Y8yYrQK7dTeHG1dK4houYWx7O+bhs8htv0b0xr kd9lNhmwUBeGE+kzh6+Vz/GvMERgRaVn8Ovk0= MIME-Version: 1.0 Received: by 10.182.86.201 with SMTP id r9mr230712obz.8.1329991867525; Thu, 23 Feb 2012 02:11:07 -0800 (PST) Received: by 10.60.23.72 with HTTP; Thu, 23 Feb 2012 02:11:07 -0800 (PST) In-Reply-To: <4BEA3FF3CAA35E408EA55C7BE2E61D055C76C25948@xmail3.se.axis.com> References: <4BEA3FF3CAA35E408EA55C7BE2E61D055C76C25948@xmail3.se.axis.com> Date: Thu, 23 Feb 2012 18:11:07 +0800 Message-ID: Subject: Re: SMP MIPS and Linux 3.2 From: Deng-Cheng Zhu To: Mikael Starvik , raghu@mips.com Cc: "linux-mips@linux-mips.org" Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 32499 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1318 Lines: 35 I should have contacted the author (Raghu Gandham) of a fix for this issue to get it into the mainline. But it slipped out of my mind... The patch link is here: http://git.linux-mips.org/?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020 Hi, Raghu Do you know why it didn't happen? Deng-Cheng On Wed, Feb 22, 2012 at 6:57 PM, Mikael Starvik wrote: > > Found it! There are no calls to scheduler_ipi() from the MIPS parts in vanilla 3.2. > > /Mikael > > -----Original Message----- > From: Mikael Starvik > Sent: den 20 februari 2012 10:34 > To: 'linux-mips@linux-mips.org' > Subject: SMP MIPS and Linux 3.2 > > I'm running Linux 3.2 on a MIPS 34K with two VPEs (in MT_SMP configuration). It works fine in UP but with SMP it deadlocks during bootup (both CPUs gets idle). Typically like this: > > [ 0.090000] CPU revision is: 01019550 (MIPS 34Kc) [ 0.090000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. > [ 0.090000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.170000] Brought up 2 CPUs > > I have tried to enable __ARCH_WANT_INTERRUPTS_ON_CTXSW but that didn't improve anything. Anyone else got this running or have any thoughts about what the problem may be? > > Best Regards > /Mikael > From standby24x7@gmail.com Thu Feb 23 15:43:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 15:43:07 +0100 (CET) Received: from i118-21-156-233.s30.a048.ap.plala.or.jp ([118.21.156.233]:53375 "EHLO rinabert.homeip.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903629Ab2BWOnA (ORCPT ); Thu, 23 Feb 2012 15:43:00 +0100 Received: from rinabert.homeip.net (localhost [127.0.0.1]) by rinabert.homeip.net (8.14.5/8.14.5) with ESMTP id q1NEgmZ8001957; Thu, 23 Feb 2012 23:42:49 +0900 Received: (from root@localhost) by rinabert.homeip.net (8.14.5/8.14.5/Submit) id q1NEgauU001950; Thu, 23 Feb 2012 23:42:36 +0900 From: Masanari Iida To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: trivial@kernel.org, linux-kernel@vger.kernel.org, standby24x7@gmail.com Subject: [PATCH] [trivial] mips: Fix typo in arc/mips Date: Thu, 23 Feb 2012 23:42:19 +0900 Message-Id: <1330008139-1916-1-git-send-email-standby24x7@gmail.com> X-Mailer: git-send-email 1.7.6.5 X-archive-position: 32500 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: standby24x7@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3166 Lines: 94 Correct spelling "platfom" to "platform", "deactived" to "deactivated" and "deprectated" to "deprecated" in arch/mips directory. Signed-off-by: Masanari Iida --- arch/mips/kernel/mips-mt.c | 2 +- arch/mips/lantiq/xway/gpio.c | 2 +- arch/mips/lantiq/xway/gpio_ebu.c | 2 +- arch/mips/lantiq/xway/gpio_stp.c | 2 +- arch/mips/pci/pci-lantiq.c | 2 +- arch/mips/sni/pcimt.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c index c23d11f..b3b0b94 100644 --- a/arch/mips/kernel/mips-mt.c +++ b/arch/mips/kernel/mips-mt.c @@ -210,7 +210,7 @@ void mips_mt_set_cpuoptions(void) unsigned int nconfig7 = oconfig7; if (mt_opt_norps) { - printk("\"norps\" option deprectated: use \"rpsctl=\"\n"); + printk("\"norps\" option deprecated: use \"rpsctl=\"\n"); } if (mt_opt_rpsctl >= 0) { printk("34K return prediction stack override set to %d.\n", diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c index d2fa98f..c429a5b 100644 --- a/arch/mips/lantiq/xway/gpio.c +++ b/arch/mips/lantiq/xway/gpio.c @@ -188,7 +188,7 @@ int __init ltq_gpio_init(void) int ret = platform_driver_register(<q_gpio_driver); if (ret) - pr_info("ltq_gpio : Error registering platfom driver!"); + pr_info("ltq_gpio : Error registering platform driver!"); return ret; } diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c index b91c7f1..aae1717 100644 --- a/arch/mips/lantiq/xway/gpio_ebu.c +++ b/arch/mips/lantiq/xway/gpio_ebu.c @@ -119,7 +119,7 @@ static int __init ltq_ebu_init(void) int ret = platform_driver_register(<q_ebu_driver); if (ret) - pr_info("ltq_ebu : Error registering platfom driver!"); + pr_info("ltq_ebu : Error registering platform driver!"); return ret; } diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index ff9991c..fd07d87 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -150,7 +150,7 @@ int __init ltq_stp_init(void) int ret = platform_driver_register(<q_stp_driver); if (ret) - pr_info("ltq_stp: error registering platfom driver"); + pr_info("ltq_stp: error registering platform driver"); return ret; } diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index be1e1af..df3dca0 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -296,7 +296,7 @@ int __init pcibios_init(void) { int ret = platform_driver_register(<q_pci_driver); if (ret) - printk(KERN_INFO "ltq_pci: Error registering platfom driver!"); + printk(KERN_INFO "ltq_pci: Error registering platform driver!"); return ret; } diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index ed3b3d317..cdb1417 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c @@ -29,7 +29,7 @@ static void __init sni_pcimt_sc_init(void) scsiz = cacheconf & 7; if (scsiz == 0) { - printk("Second level cache is deactived.\n"); + printk("Second level cache is deactivated.\n"); return; } if (scsiz >= 6) { -- 1.7.6.5 From blogic@openwrt.org Thu Feb 23 17:02:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:02:23 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47245 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903629Ab2BWQCP (ORCPT ); Thu, 23 Feb 2012 17:02:15 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 2/6] MIPS: lantiq: use devm_request_gpio inside xway gpio driver Date: Thu, 23 Feb 2012 17:01:49 +0100 Message-Id: <1330012913-13293-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012913-13293-1-git-send-email-blogic@openwrt.org> References: <1330012913-13293-1-git-send-email-blogic@openwrt.org> X-archive-position: 32501 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 908 Lines: 31 Start using the devm_request_gpio() api inside our xway gpio_request wrapper. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/gpio.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c index 14ff7c7..54ec6c9 100644 --- a/arch/mips/lantiq/xway/gpio.c +++ b/arch/mips/lantiq/xway/gpio.c @@ -50,14 +50,14 @@ int irq_to_gpio(unsigned int gpio) } EXPORT_SYMBOL(irq_to_gpio); -int ltq_gpio_request(unsigned int pin, unsigned int mux, +int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, unsigned int dir, const char *name) { int id = 0; if (pin >= (MAX_PORTS * PINS_PER_PORT)) return -EINVAL; - if (gpio_request(pin, name)) { + if (devm_gpio_request(dev, pin, name)) { pr_err("failed to setup lantiq gpio: %s\n", name); return -EBUSY; } -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:02:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:02:53 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47247 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2BWQCP (ORCPT ); Thu, 23 Feb 2012 17:02:15 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 3/6] MIPS: lantiq: use devm_request_gpio inside falcon gpio driver Date: Thu, 23 Feb 2012 17:01:50 +0100 Message-Id: <1330012913-13293-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012913-13293-1-git-send-email-blogic@openwrt.org> References: <1330012913-13293-1-git-send-email-blogic@openwrt.org> X-archive-position: 32502 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1042 Lines: 32 Start using the devm_request_gpio() api inside our falcon gpio_request wrapper. Signed-off-by: John Crispin --- arch/mips/lantiq/falcon/gpio.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c index 3eebd51..b7611d7 100644 --- a/arch/mips/lantiq/falcon/gpio.c +++ b/arch/mips/lantiq/falcon/gpio.c @@ -97,7 +97,7 @@ int ltq_gpio_mux_set(unsigned int pin, unsigned int mux) } EXPORT_SYMBOL(ltq_gpio_mux_set); -int ltq_gpio_request(unsigned int pin, unsigned int mux, +int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, unsigned int dir, const char *name) { int port = pin / 100; @@ -106,7 +106,7 @@ int ltq_gpio_request(unsigned int pin, unsigned int mux, if (offset >= PINS_PER_PORT || port >= MAX_PORTS) return -EINVAL; - if (gpio_request(pin, name)) { + if (devm_gpio_request(dev, pin, name)) { pr_err("failed to setup lantiq gpio: %s\n", name); return -EBUSY; } -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:02:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:03:21 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47243 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903627Ab2BWQCP (ORCPT ); Thu, 23 Feb 2012 17:02:15 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 1/6] MIPS: lantiq: remove redunant ltq_gpio_request() declaration and add device parameter Date: Thu, 23 Feb 2012 17:01:48 +0100 Message-Id: <1330012913-13293-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 X-archive-position: 32503 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2621 Lines: 59 3.2 introduced devm_request_gpio() to allow managed gpios. The devres api requires a struct device pointer to work. Add a parameter to ltq_gpio_request() so that managed gpios can work. Signed-off-by: John Crispin --- .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 4 +--- arch/mips/include/asm/mach-lantiq/lantiq.h | 4 ++++ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 --- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h index 8ac509a..1a4b836 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -141,9 +141,7 @@ static inline void ltq_sys1_w32_mask(u32 c, u32 s, u32 r) ltq_sys1_w32((ltq_sys1_r32(r) & ~(c)) | (s), r); } -/* gpio_request wrapper to help configure the pin */ -extern int ltq_gpio_request(unsigned int pin, unsigned int mux, - unsigned int dir, const char *name); +/* gpio wrapper to help configure the pin muxing */ extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); /* to keep the irq code generic we need to define these to 0 as falcon diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index bf05854..d90eef3 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -39,6 +39,10 @@ extern unsigned int ltq_get_soc_type(void); /* spinlock all ebu i/o */ extern spinlock_t ebu_lock; +/* request a non-gpio and set the PIO config */ +extern int ltq_gpio_request(struct device *dev, unsigned int pin, + unsigned int mux, unsigned int dir, const char *name); + /* some irq helpers */ extern void ltq_disable_irq(struct irq_data *data); extern void ltq_mask_and_ack_irq(struct irq_data *data); diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 9d0afeb..4213926 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -167,9 +167,6 @@ static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) ltq_cgu_w32((ltq_cgu_r32(r) & ~(c)) | (s), r); } -/* request a non-gpio and set the PIO config */ -extern int ltq_gpio_request(unsigned int pin, unsigned int mux, - unsigned int dir, const char *name); extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); extern void ltq_cgu_enable(unsigned int clk); -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:02:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:03:49 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47249 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903632Ab2BWQCP (ORCPT ); Thu, 23 Feb 2012 17:02:15 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 5/6] MIPS: lantiq: convert pci to managed gpio Date: Thu, 23 Feb 2012 17:01:52 +0100 Message-Id: <1330012913-13293-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012913-13293-1-git-send-email-blogic@openwrt.org> References: <1330012913-13293-1-git-send-email-blogic@openwrt.org> X-archive-position: 32504 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2171 Lines: 66 ltq_gpio_request() now uses devres to manage the gpios. We need to pass a struct device pointer to make it work. Signed-off-by: John Crispin --- arch/mips/pci/pci-lantiq.c | 18 ++++++++++-------- 1 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 3bf42c8..47b5d8e 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -150,24 +150,26 @@ static u32 ltq_calc_bar11mask(void) return bar11mask; } -static void ltq_pci_setup_gpio(int gpio) +static void ltq_pci_setup_gpio(struct device *dev) { + struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data; int i; for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { - if (gpio & (1 << i)) { - ltq_gpio_request(ltq_pci_gpio_map[i].pin, + if (conf->gpio & (1 << i)) { + ltq_gpio_request(dev, ltq_pci_gpio_map[i].pin, ltq_pci_gpio_map[i].mux, ltq_pci_gpio_map[i].dir, ltq_pci_gpio_map[i].name); } } - ltq_gpio_request(21, 0, 1, "pci-reset"); - ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; + ltq_gpio_request(dev, 21, 0, 1, "pci-reset"); + ltq_pci_req_mask = (conf->gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; } -static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) +static int __devinit ltq_pci_startup(struct device *dev) { u32 temp_buffer; + struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data; /* set clock to 33Mhz */ if (ltq_is_ar9()) { @@ -190,7 +192,7 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) } /* setup pci clock and gpis used by pci */ - ltq_pci_setup_gpio(conf->gpio); + ltq_pci_setup_gpio(dev); /* enable auto-switching between PCI and EBU */ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); @@ -275,7 +277,7 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev) ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); ltq_pci_controller.io_map_base = (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); - ltq_pci_startup(ltq_pci_data); + ltq_pci_startup(&pdev->dev); register_pci_controller(<q_pci_controller); return 0; -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:02:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:04:14 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47251 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903633Ab2BWQCQ (ORCPT ); Thu, 23 Feb 2012 17:02:16 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , netdev@vger.kernel.org Subject: [PATCH V2 4/6] NET: MIPS: lantiq: convert etop to managed gpio Date: Thu, 23 Feb 2012 17:01:51 +0100 Message-Id: <1330012913-13293-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012913-13293-1-git-send-email-blogic@openwrt.org> References: <1330012913-13293-1-git-send-email-blogic@openwrt.org> X-archive-position: 32505 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1195 Lines: 39 ltq_gpio_request() now uses devres to manage the gpios. We need to pass a struct device pointer to make it work. Signed-off-by: John Crispin Cc: netdev@vger.kernel.org --- drivers/net/ethernet/lantiq_etop.c | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index 66ec54a..e5ec8b1 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -292,9 +292,6 @@ ltq_etop_gbit_init(void) { ltq_pmu_enable(PMU_SWITCH); - ltq_gpio_request(42, 2, 1, "MDIO"); - ltq_gpio_request(43, 2, 1, "MDC"); - ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); /** Disable MDIO auto polling mode */ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); @@ -873,6 +870,12 @@ ltq_etop_probe(struct platform_device *pdev) err = -ENOMEM; goto err_out; } + if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") || + ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) { + dev_err(&pdev->dev, "failed to request MDIO gpios\n"); + err = -EBUSY; + goto err_out; + } } dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:02:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:04:40 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47253 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903635Ab2BWQCQ (ORCPT ); Thu, 23 Feb 2012 17:02:16 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 6/6] MIPS: lantiq: convert gpio_stp to managed gpio Date: Thu, 23 Feb 2012 17:01:53 +0100 Message-Id: <1330012913-13293-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012913-13293-1-git-send-email-blogic@openwrt.org> References: <1330012913-13293-1-git-send-email-blogic@openwrt.org> X-archive-position: 32506 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1372 Lines: 42 ltq_gpio_request() now uses devres to manage the gpios. We need to pass a struct device pointer to make it work. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/gpio_stp.c | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index cb6f170..e6b4809 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -80,11 +80,6 @@ static struct gpio_chip ltq_stp_chip = { static int ltq_stp_hw_init(void) { - /* the 3 pins used to control the external stp */ - ltq_gpio_request(4, 2, 1, "stp-st"); - ltq_gpio_request(5, 2, 1, "stp-d"); - ltq_gpio_request(6, 2, 1, "stp-sh"); - /* sane defaults */ ltq_stp_w32(0, LTQ_STP_AR); ltq_stp_w32(0, LTQ_STP_CPU0); @@ -133,6 +128,14 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to remap STP memory\n"); return -ENOMEM; } + + /* the 3 pins used to control the external stp */ + if (ltq_gpio_request(&pdev->dev, 4, 2, 1, "stp-st") || + ltq_gpio_request(&pdev->dev, 5, 2, 1, "stp-d") || + ltq_gpio_request(&pdev->dev, 6, 2, 1, "stp-sh")) { + dev_err(&pdev->dev, "failed to request needed gpios\n"); + return -EBUSY; + } ret = gpiochip_add(<q_stp_chip); if (!ret) ret = ltq_stp_hw_init(); -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:05:07 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47346 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2BWQDc (ORCPT ); Thu, 23 Feb 2012 17:03:32 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 01/14] MIPS: add clkdev.h Date: Thu, 23 Feb 2012 17:03:00 +0100 Message-Id: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 X-archive-position: 32507 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1145 Lines: 44 For clkdev to work on MIPS we need this file include/linux/clkdev.h:#include Signed-off-by: John Crispin --- arch/mips/include/asm/clkdev.h | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/clkdev.h diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h new file mode 100644 index 0000000..2624754 --- /dev/null +++ b/arch/mips/include/asm/clkdev.h @@ -0,0 +1,25 @@ +/* + * based on arch/arm/include/asm/clkdev.h + * + * Copyright (C) 2008 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Helper for the clk API to assist looking up a struct clk. + */ +#ifndef __ASM_CLKDEV_H +#define __ASM_CLKDEV_H + +#include + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) +{ + return kzalloc(size, GFP_KERNEL); +} + +#endif -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:05:32 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47351 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903641Ab2BWQDc (ORCPT ); Thu, 23 Feb 2012 17:03:32 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 02/14] MIPS: lantiq: helper functions for SoC detection Date: Thu, 23 Feb 2012 17:03:01 +0100 Message-Id: <1330012993-13510-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32508 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1542 Lines: 54 Add additional functions for runtime soc detection. We need these for the serial driver. Signed-off-by: John Crispin --- .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 16 ++++++++++++++-- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 5 +++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h index 1a4b836..fd7f9fd 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -149,8 +149,20 @@ extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); #define LTQ_EIU_BASE_ADDR 0 #define LTQ_EBU_PCC_ISTAT 0 -#define ltq_is_ar9() 0 -#define ltq_is_vr9() 0 +static inline int ltq_is_ar9(void) +{ + return 0; +} + +static inline int ltq_is_vr9(void) +{ + return 0; +} + +static inline int ltq_is_falcon(void) +{ + return 1; +} #endif /* CONFIG_SOC_FALCON */ #endif /* _LTQ_XWAY_H__ */ diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 4213926..1b60181 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -186,5 +186,10 @@ static inline int ltq_is_vr9(void) return (ltq_get_soc_type() == SOC_TYPE_VR9); } +static inline int ltq_is_falcon(void) +{ + return 0; +} + #endif /* CONFIG_SOC_TYPE_XWAY */ #endif /* _LTQ_XWAY_H__ */ -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:06:04 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47354 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903642Ab2BWQDd (ORCPT ); Thu, 23 Feb 2012 17:03:33 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 03/14] MIPS: lantiq: convert to clkdev api Date: Thu, 23 Feb 2012 17:03:02 +0100 Message-Id: <1330012993-13510-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32509 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7681 Lines: 294 * Change setup from HAVE_CLK -> HAVE_MACH_CLKDEV/CLKDEV_LOOKUP * Add clk_activate/clk_deactivate * Add better error paths to the clk_*() functions * Change the way our static clocks are referenced Signed-off-by: John Crispin --- arch/mips/Kconfig | 3 +- arch/mips/include/asm/mach-lantiq/lantiq.h | 20 ++---- arch/mips/lantiq/clk.c | 96 +++++++++++++++------------ arch/mips/lantiq/clk.h | 52 ++++++++++++++- arch/mips/lantiq/prom.c | 1 - 5 files changed, 111 insertions(+), 61 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c4c1312..b106c9e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -228,7 +228,8 @@ config LANTIQ select ARCH_REQUIRE_GPIOLIB select SWAP_IO_SPACE select BOOT_RAW - select HAVE_CLK + select HAVE_MACH_CLKDEV + select CLKDEV_LOOKUP select MIPS_MACHINE config LASAT diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index d90eef3..52f1cdf 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -9,6 +9,7 @@ #define _LANTIQ_H__ #include +#include #include /* generic reg access */ @@ -24,18 +25,6 @@ static inline void ltq_w32_mask(u32 c, u32 s, volatile void __iomem *r) extern unsigned int ltq_get_cpu_ver(void); extern unsigned int ltq_get_soc_type(void); -/* clock speeds */ -#define CLOCK_60M 60000000 -#define CLOCK_83M 83333333 -#define CLOCK_100M 100000000 -#define CLOCK_111M 111111111 -#define CLOCK_133M 133333333 -#define CLOCK_167M 166666667 -#define CLOCK_200M 200000000 -#define CLOCK_266M 266666666 -#define CLOCK_333M 333333333 -#define CLOCK_400M 400000000 - /* spinlock all ebu i/o */ extern spinlock_t ebu_lock; @@ -48,6 +37,13 @@ extern void ltq_disable_irq(struct irq_data *data); extern void ltq_mask_and_ack_irq(struct irq_data *data); extern void ltq_enable_irq(struct irq_data *data); +/* clock handling */ +extern int clk_activate(struct clk *clk); +extern void clk_deactivate(struct clk *clk); +extern struct clk *clk_get_cpu(void); +extern struct clk *clk_get_fpi(void); +extern struct clk *clk_get_io(void); + /* find out what caused the last cpu reset */ extern int ltq_reset_cause(void); diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index 39eef7f..84a201e 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -24,33 +25,29 @@ #include "clk.h" #include "prom.h" -struct clk { - const char *name; - unsigned long rate; - unsigned long (*get_rate) (void); -}; +/* lantiq socs have 3 static clocks */ +static struct clk cpu_clk_generic[3]; -static struct clk *cpu_clk; -static int cpu_clk_cnt; +void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io) +{ + cpu_clk_generic[0].rate = cpu; + cpu_clk_generic[1].rate = fpi; + cpu_clk_generic[2].rate = io; +} -/* lantiq socs have 3 static clocks */ -static struct clk cpu_clk_generic[] = { - { - .name = "cpu", - .get_rate = ltq_get_cpu_hz, - }, { - .name = "fpi", - .get_rate = ltq_get_fpi_hz, - }, { - .name = "io", - .get_rate = ltq_get_io_region_clock, - }, -}; - -void clk_init(void) +struct clk *clk_get_cpu(void) +{ + return &cpu_clk_generic[0]; +} + +struct clk *clk_get_fpi(void) { - cpu_clk = cpu_clk_generic; - cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic); + return &cpu_clk_generic[1]; +} + +struct clk *clk_get_io(void) +{ + return &cpu_clk_generic[2]; } static inline int clk_good(struct clk *clk) @@ -73,36 +70,49 @@ unsigned long clk_get_rate(struct clk *clk) } EXPORT_SYMBOL(clk_get_rate); -struct clk *clk_get(struct device *dev, const char *id) +int clk_enable(struct clk *clk) { - int i; + if (unlikely(!clk_good(clk))) + return -1; + + if (clk->enable) + return clk->enable(clk); - for (i = 0; i < cpu_clk_cnt; i++) - if (!strcmp(id, cpu_clk[i].name)) - return &cpu_clk[i]; - BUG(); - return ERR_PTR(-ENOENT); + return -1; } -EXPORT_SYMBOL(clk_get); +EXPORT_SYMBOL(clk_enable); -void clk_put(struct clk *clk) +void clk_disable(struct clk *clk) { - /* not used */ + if (unlikely(!clk_good(clk))) + return; + + if (clk->disable) + clk->disable(clk); } -EXPORT_SYMBOL(clk_put); +EXPORT_SYMBOL(clk_disable); -int clk_enable(struct clk *clk) +int clk_activate(struct clk *clk) { - /* not used */ - return 0; + if (unlikely(!clk_good(clk))) + return -1; + + if (clk->activate) + return clk->activate(clk); + + return -1; } -EXPORT_SYMBOL(clk_enable); +EXPORT_SYMBOL(clk_activate); -void clk_disable(struct clk *clk) +void clk_deactivate(struct clk *clk) { - /* not used */ + if (unlikely(!clk_good(clk))) + return; + + if (clk->deactivate) + clk->deactivate(clk); } -EXPORT_SYMBOL(clk_disable); +EXPORT_SYMBOL(clk_deactivate); static inline u32 ltq_get_counter_resolution(void) { @@ -126,7 +136,7 @@ void __init plat_time_init(void) ltq_soc_init(); - clk = clk_get(0, "cpu"); + clk = clk_get_cpu(); mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); write_c0_compare(read_c0_count()); pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h index 3328925..d047768 100644 --- a/arch/mips/lantiq/clk.h +++ b/arch/mips/lantiq/clk.h @@ -9,10 +9,54 @@ #ifndef _LTQ_CLK_H__ #define _LTQ_CLK_H__ -extern void clk_init(void); +#include -extern unsigned long ltq_get_cpu_hz(void); -extern unsigned long ltq_get_fpi_hz(void); -extern unsigned long ltq_get_io_region_clock(void); +/* clock speeds */ +#define CLOCK_60M 60000000 +#define CLOCK_62_5M 62500000 +#define CLOCK_83M 83333333 +#define CLOCK_83_5M 83500000 +#define CLOCK_98_304M 98304000 +#define CLOCK_100M 100000000 +#define CLOCK_111M 111111111 +#define CLOCK_125M 125000000 +#define CLOCK_133M 133333333 +#define CLOCK_150M 150000000 +#define CLOCK_166M 166666666 +#define CLOCK_167M 166666667 +#define CLOCK_196_608M 196608000 +#define CLOCK_200M 200000000 +#define CLOCK_250M 250000000 +#define CLOCK_266M 266666666 +#define CLOCK_300M 300000000 +#define CLOCK_333M 333333333 +#define CLOCK_393M 393215332 +#define CLOCK_400M 400000000 +#define CLOCK_500M 500000000 +#define CLOCK_600M 600000000 + +struct clk { + struct clk_lookup cl; + unsigned long rate; + unsigned long (*get_rate) (void); + unsigned int module; + unsigned int bits; + int (*enable) (struct clk *clk); + void (*disable) (struct clk *clk); + int (*activate) (struct clk *clk); + void (*deactivate) (struct clk *clk); + void (*reboot) (struct clk *clk); +}; + +extern void clkdev_add_static(unsigned long cpu, unsigned long fpi, + unsigned long io); + +extern unsigned long ltq_danube_cpu_hz(void); +extern unsigned long ltq_danube_fpi_hz(void); +extern unsigned long ltq_danube_io_region_clock(void); + +extern unsigned long ltq_vr9_cpu_hz(void); +extern unsigned long ltq_vr9_fpi_hz(void); +extern unsigned long ltq_vr9_io_region_clock(void); #endif diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index ee63a33..b002bc7 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -103,7 +103,6 @@ EXPORT_SYMBOL(ltq_remap_resource); void __init prom_init(void) { ltq_soc_detect(&soc_info); - clk_init(); snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", soc_info.name, soc_info.rev_type); soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:06:34 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47356 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903656Ab2BWQDd (ORCPT ); Thu, 23 Feb 2012 17:03:33 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 04/14] MIPS: lantiq: convert xway to clkdev api Date: Thu, 23 Feb 2012 17:03:03 +0100 Message-Id: <1330012993-13510-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32510 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 19936 Lines: 731 Unify xway/ase clock code and add clkdev hooks to sysctrl.c Signed-off-by: John Crispin --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 13 -- arch/mips/lantiq/xway/Makefile | 6 +- arch/mips/lantiq/xway/clk-ase.c | 48 ---- arch/mips/lantiq/xway/clk-xway.c | 223 ------------------- arch/mips/lantiq/xway/clk.c | 227 ++++++++++++++++++++ arch/mips/lantiq/xway/sysctrl.c | 104 ++++++++- 6 files changed, 325 insertions(+), 296 deletions(-) delete mode 100644 arch/mips/lantiq/xway/clk-ase.c delete mode 100644 arch/mips/lantiq/xway/clk-xway.c create mode 100644 arch/mips/lantiq/xway/clk.c diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 1b60181..2208a9db 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -81,15 +81,6 @@ #define LTQ_PMU_BASE_ADDR 0x1F102000 #define LTQ_PMU_SIZE 0x1000 -#define PMU_DMA 0x0020 -#define PMU_EPHY 0x0080 -#define PMU_USB 0x8041 -#define PMU_LED 0x0800 -#define PMU_GPT 0x1000 -#define PMU_PPE 0x2000 -#define PMU_FPI 0x4000 -#define PMU_SWITCH 0x10000000 - /* ETOP - ethernet */ #define LTQ_ETOP_BASE_ADDR 0x1E180000 #define LTQ_ETOP_SIZE 0x40000 @@ -167,10 +158,6 @@ static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) ltq_cgu_w32((ltq_cgu_r32(r) & ~(c)) | (s), r); } -extern void ltq_pmu_enable(unsigned int module); -extern void ltq_pmu_disable(unsigned int module); -extern void ltq_cgu_enable(unsigned int clk); - static inline int ltq_is_ase(void) { return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE); diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 6678402..4dcb96f 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,7 +1,7 @@ -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o -obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o +obj-$(CONFIG_SOC_XWAY) += prom-xway.o +obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c deleted file mode 100644 index 6522583..0000000 --- a/arch/mips/lantiq/xway/clk-ase.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include - -/* cgu registers */ -#define LTQ_CGU_SYS 0x0010 - -unsigned int ltq_get_io_region_clock(void) -{ - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_io_region_clock); - -unsigned int ltq_get_fpi_bus_clock(int fpi) -{ - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_fpi_bus_clock); - -unsigned int ltq_get_cpu_hz(void) -{ - if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) - return CLOCK_266M; - else - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_cpu_hz); - -unsigned int ltq_get_fpi_hz(void) -{ - return CLOCK_133M; -} -EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c deleted file mode 100644 index 696b1a3..0000000 --- a/arch/mips/lantiq/xway/clk-xway.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include - -static unsigned int ltq_ram_clocks[] = { - CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; -#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] - -#define BASIC_FREQUENCY_1 35328000 -#define BASIC_FREQUENCY_2 36000000 -#define BASIS_REQUENCY_USB 12000000 - -#define GET_BITS(x, msb, lsb) \ - (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) - -#define LTQ_CGU_PLL0_CFG 0x0004 -#define LTQ_CGU_PLL1_CFG 0x0008 -#define LTQ_CGU_PLL2_CFG 0x000C -#define LTQ_CGU_SYS 0x0010 -#define LTQ_CGU_UPDATE 0x0014 -#define LTQ_CGU_IF_CLK 0x0018 -#define LTQ_CGU_OSC_CON 0x001C -#define LTQ_CGU_SMD 0x0020 -#define LTQ_CGU_CT1SR 0x0028 -#define LTQ_CGU_CT2SR 0x002C -#define LTQ_CGU_PCMCR 0x0030 -#define LTQ_CGU_PCI_CR 0x0034 -#define LTQ_CGU_PD_PC 0x0038 -#define LTQ_CGU_FMR 0x003C - -#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) -#define CGU_PLL0_BYPASS \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) -#define CGU_PLL0_CFG_DSMSEL \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) -#define CGU_PLL0_CFG_FRAC_EN \ - (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) -#define CGU_PLL1_SRC \ - (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) -#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ - (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) -#define CGU_SYS_FPI_SEL (1 << 6) -#define CGU_SYS_DDR_SEL 0x3 -#define CGU_PLL0_SRC (1 << 29) - -#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) -#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) -#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) -#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) -#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) - -static unsigned int ltq_get_pll0_fdiv(void); - -static inline unsigned int get_input_clock(int pll) -{ - switch (pll) { - case 0: - if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) - return BASIS_REQUENCY_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_FREQUENCY_1; - else - return BASIC_FREQUENCY_2; - case 1: - if (CGU_PLL1_SRC) - return BASIS_REQUENCY_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_FREQUENCY_1; - else - return BASIC_FREQUENCY_2; - case 2: - switch (CGU_PLL2_SRC) { - case 0: - return ltq_get_pll0_fdiv(); - case 1: - return CGU_PLL2_PHASE_DIVIDER_ENABLE ? - BASIC_FREQUENCY_1 : - BASIC_FREQUENCY_2; - case 2: - return BASIS_REQUENCY_USB; - } - default: - return 0; - } -} - -static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) -{ - u64 res, clock = get_input_clock(pll); - - res = num * clock; - do_div(res, den); - return res; -} - -static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 10) + K; - unsigned int den = (M + 1) << 10; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 11) + K + 512; - unsigned int den = (M + 1) << 11; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = K >= 512 ? - ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; - unsigned int den = (M + 1) << 12; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, - unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) -{ - if (!dsmsel) - return mash_dsm(pll, M, N, K); - else if (!phase_div_en) - return mash_dsm(pll, M, N, K); - else - return ssff_dsm_2(pll, M, N, K); -} - -static inline unsigned int ltq_get_pll0_fosc(void) -{ - if (CGU_PLL0_BYPASS) - return get_input_clock(0); - else - return !CGU_PLL0_CFG_FRAC_EN - ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, - CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE) - : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, - CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE); -} - -static unsigned int ltq_get_pll0_fdiv(void) -{ - unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; - - return (ltq_get_pll0_fosc() + (div >> 1)) / div; -} - -unsigned int ltq_get_io_region_clock(void) -{ - unsigned int ret = ltq_get_pll0_fosc(); - - switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { - default: - case 0: - return (ret + 1) / 2; - case 1: - return (ret * 2 + 2) / 5; - case 2: - return (ret + 1) / 3; - case 3: - return (ret + 2) / 4; - } -} -EXPORT_SYMBOL(ltq_get_io_region_clock); - -unsigned int ltq_get_fpi_bus_clock(int fpi) -{ - unsigned int ret = ltq_get_io_region_clock(); - - if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) - ret >>= 1; - return ret; -} -EXPORT_SYMBOL(ltq_get_fpi_bus_clock); - -unsigned int ltq_get_cpu_hz(void) -{ - switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { - case 0: - return CLOCK_333M; - case 4: - return DDR_HZ; - case 8: - return DDR_HZ << 1; - default: - return DDR_HZ >> 1; - } -} -EXPORT_SYMBOL(ltq_get_cpu_hz); - -unsigned int ltq_get_fpi_hz(void) -{ - unsigned int ddr_clock = DDR_HZ; - - if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) - return ddr_clock >> 1; - return ddr_clock; -} -EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c new file mode 100644 index 0000000..f3b50fc --- /dev/null +++ b/arch/mips/lantiq/xway/clk.c @@ -0,0 +1,227 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "../clk.h" + +static unsigned int ltq_ram_clocks[] = { + CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; +#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] + +#define BASIC_FREQUENCY_1 35328000 +#define BASIC_FREQUENCY_2 36000000 +#define BASIS_REQUENCY_USB 12000000 + +#define GET_BITS(x, msb, lsb) \ + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) + +/* legacy xway clock */ +#define LTQ_CGU_PLL0_CFG 0x0004 +#define LTQ_CGU_PLL1_CFG 0x0008 +#define LTQ_CGU_PLL2_CFG 0x000C +#define LTQ_CGU_SYS 0x0010 +#define LTQ_CGU_UPDATE 0x0014 +#define LTQ_CGU_IF_CLK 0x0018 +#define LTQ_CGU_OSC_CON 0x001C +#define LTQ_CGU_SMD 0x0020 +#define LTQ_CGU_CT1SR 0x0028 +#define LTQ_CGU_CT2SR 0x002C +#define LTQ_CGU_PCMCR 0x0030 +#define LTQ_CGU_PCI_CR 0x0034 +#define LTQ_CGU_PD_PC 0x0038 +#define LTQ_CGU_FMR 0x003C + +#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) +#define CGU_PLL0_BYPASS \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) +#define CGU_PLL0_CFG_DSMSEL \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) +#define CGU_PLL0_CFG_FRAC_EN \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) +#define CGU_PLL1_SRC \ + (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) +#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) +#define CGU_SYS_FPI_SEL (1 << 6) +#define CGU_SYS_DDR_SEL 0x3 +#define CGU_PLL0_SRC (1 << 29) + +#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) +#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) +#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) +#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) +#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) + +/* vr9 clock */ +#define LTQ_CGU_SYS_VR9 0x0c +#define LTQ_CGU_IF_CLK_VR9 0x24 + + +static unsigned int ltq_get_pll0_fdiv(void); + +static inline unsigned int get_input_clock(int pll) +{ + switch (pll) { + case 0: + if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 1: + if (CGU_PLL1_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 2: + switch (CGU_PLL2_SRC) { + case 0: + return ltq_get_pll0_fdiv(); + case 1: + return CGU_PLL2_PHASE_DIVIDER_ENABLE ? + BASIC_FREQUENCY_1 : + BASIC_FREQUENCY_2; + case 2: + return BASIS_REQUENCY_USB; + } + default: + return 0; + } +} + +static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) +{ + u64 res, clock = get_input_clock(pll); + + res = num * clock; + do_div(res, den); + return res; +} + +static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = ((N + 1) << 10) + K; + unsigned int den = (M + 1) << 10; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = ((N + 1) << 11) + K + 512; + unsigned int den = (M + 1) << 11; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = K >= 512 ? + ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; + unsigned int den = (M + 1) << 12; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, + unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) +{ + if (!dsmsel) + return mash_dsm(pll, M, N, K); + else if (!phase_div_en) + return mash_dsm(pll, M, N, K); + else + return ssff_dsm_2(pll, M, N, K); +} + +static inline unsigned int ltq_get_pll0_fosc(void) +{ + if (CGU_PLL0_BYPASS) + return get_input_clock(0); + else + return !CGU_PLL0_CFG_FRAC_EN + ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, + CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE) + : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, + CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE); +} + +static unsigned int ltq_get_pll0_fdiv(void) +{ + unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; + + return (ltq_get_pll0_fosc() + (div >> 1)) / div; +} + +unsigned long ltq_danube_io_region_clock(void) +{ + unsigned int ret = ltq_get_pll0_fosc(); + + switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { + default: + case 0: + return (ret + 1) / 2; + case 1: + return (ret * 2 + 2) / 5; + case 2: + return (ret + 1) / 3; + case 3: + return (ret + 2) / 4; + } +} + +unsigned long ltq_danube_fpi_bus_clock(int fpi) +{ + unsigned long ret = ltq_danube_io_region_clock(); + + if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) + ret >>= 1; + return ret; +} + +unsigned long ltq_danube_cpu_hz(void) +{ + switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { + case 0: + return CLOCK_333M; + case 4: + return DDR_HZ; + case 8: + return DDR_HZ << 1; + default: + return DDR_HZ >> 1; + } +} + +unsigned long ltq_danube_fpi_hz(void) +{ + unsigned long ddr_clock = DDR_HZ; + + if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) + return ddr_clock >> 1; + return ddr_clock; +} diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 38c122f..22d076e 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -8,17 +8,48 @@ #include #include +#include #include +#include "../clk.h" #include "../devices.h" /* clock control register */ #define LTQ_CGU_IFCCR 0x0018 +/* system clock register */ +#define LTQ_CGU_SYS 0x0010 /* the enable / disable registers */ #define LTQ_PMU_PWDCR 0x1C #define LTQ_PMU_PWDSR 0x20 +#define LTQ_PMU_PWDCR1 0x24 +#define LTQ_PMU_PWDSR1 0x28 + +#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR)) +#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR)) + +/* CGU - clock generation unit */ +#define CGU_EPHY 0x10 + +/* PMU - power management unit */ +#define PMU_DMA 0x0020 +#define PMU_SPI 0x0100 +#define PMU_EPHY 0x0080 +#define PMU_USB 0x8041 +#define PMU_STP 0x0800 +#define PMU_GPT 0x1000 +#define PMU_PPE 0x2000 +#define PMU_FPI 0x4000 +#define PMU_SWITCH 0x10000000 +#define PMU_AHBS 0x2000 +#define PMU_AHBM 0x8000 +#define PMU_PCIE_CLK 0x80000000 + +#define PMU1_PCIE_PHY 0x0001 +#define PMU1_PCIE_CTL 0x0002 +#define PMU1_PCIE_MSI 0x0020 +#define PMU1_PCIE_PDI 0x0010 #define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) #define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) @@ -36,28 +67,64 @@ void __iomem *ltq_cgu_membase; void __iomem *ltq_ebu_membase; static void __iomem *ltq_pmu_membase; -void ltq_cgu_enable(unsigned int clk) +static int ltq_cgu_enable(struct clk *clk) { - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR); + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR); + return 0; } -void ltq_pmu_enable(unsigned int module) +static void ltq_cgu_disable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR); +} + +static int ltq_pmu_enable(struct clk *clk) { int err = 1000000; - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); - do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); + ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits, + PWDCR(clk->module)); + do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits)); if (!err) panic("activating PMU module failed!"); + + return 0; } -EXPORT_SYMBOL(ltq_pmu_enable); -void ltq_pmu_disable(unsigned int module) +static void ltq_pmu_disable(struct clk *clk) { - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR); +} + +static inline void clkdev_add_pmu(const char *dev, const char *con, + unsigned int module, unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_pmu_enable; + clk->disable = ltq_pmu_disable; + clk->module = module; + clk->bits = bits; + clkdev_add(&clk->cl); +} + +static inline void clkdev_add_cgu(const char *dev, const char *con, + unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_cgu_enable; + clk->disable = ltq_cgu_disable; + clk->bits = bits; + clkdev_add(&clk->cl); } -EXPORT_SYMBOL(ltq_pmu_disable); void __init ltq_soc_init(void) { @@ -75,4 +142,23 @@ void __init ltq_soc_init(void) /* make sure to unprotect the memory region where flash is located */ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); + + /* add our clocks */ + clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); + clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); + clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI); + clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); + if (ltq_is_ase()) { + if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) + clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); + else + clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); + clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY), + clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); + } else { + clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), + ltq_danube_io_region_clock()); + if (ltq_is_ar9()) + clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); + } } -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:07:02 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47360 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903717Ab2BWQDe (ORCPT ); Thu, 23 Feb 2012 17:03:34 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 05/14] MIPS: lantiq: convert falcon to clkdev api Date: Thu, 23 Feb 2012 17:03:04 +0100 Message-Id: <1330012993-13510-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32511 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8721 Lines: 291 Unify sysctrl/clock code and add clkdev hooks to sysctrl.c Signed-off-by: John Crispin --- .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 8 +- arch/mips/lantiq/falcon/Makefile | 2 +- arch/mips/lantiq/falcon/clk.c | 44 ------- arch/mips/lantiq/falcon/sysctrl.c | 129 ++++++++++++-------- 4 files changed, 80 insertions(+), 103 deletions(-) delete mode 100644 arch/mips/lantiq/falcon/clk.c diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h index fd7f9fd..06f4c8f 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -95,6 +95,7 @@ /* Activation Status Register */ #define ACTS_ASC1_ACT 0x00000800 +#define ACTS_I2C_ACT 0x00004000 #define ACTS_P0 0x00010000 #define ACTS_P1 0x00010000 #define ACTS_P2 0x00020000 @@ -106,13 +107,6 @@ #define ACTS_PADCTRL3 0x00200000 #define ACTS_PADCTRL4 0x00400000 -extern void ltq_sysctl_activate(int module, unsigned int mask); -extern void ltq_sysctl_deactivate(int module, unsigned int mask); -extern void ltq_sysctl_clken(int module, unsigned int mask); -extern void ltq_sysctl_clkdis(int module, unsigned int mask); -extern void ltq_sysctl_reboot(int module, unsigned int mask); -extern int ltq_gpe_is_activated(unsigned int mask); - /* global register ranges */ extern void __iomem *ltq_ebu_membase; extern void __iomem *ltq_sys1_membase; diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile index 56b22eb..3634154 100644 --- a/arch/mips/lantiq/falcon/Makefile +++ b/arch/mips/lantiq/falcon/Makefile @@ -1,2 +1,2 @@ -obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o +obj-y := prom.o reset.o sysctrl.o devices.o gpio.o obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c deleted file mode 100644 index afe1b52..0000000 --- a/arch/mips/lantiq/falcon/clk.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 Thomas Langer - * Copyright (C) 2011 John Crispin - */ - -#include -#include - -#include - -#include "devices.h" - -/* CPU0 Clock Control Register */ -#define LTQ_SYS1_CPU0CC 0x0040 -/* clock divider bit */ -#define LTQ_CPU0CC_CPUDIV 0x0001 - -unsigned int -ltq_get_io_region_clock(void) -{ - return CLOCK_200M; -} -EXPORT_SYMBOL(ltq_get_io_region_clock); - -unsigned int -ltq_get_cpu_hz(void) -{ - if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) - return CLOCK_200M; - else - return CLOCK_400M; -} -EXPORT_SYMBOL(ltq_get_cpu_hz); - -unsigned int -ltq_get_fpi_hz(void) -{ - return CLOCK_100M; -} -EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c index 905a142..900f0e5 100644 --- a/arch/mips/lantiq/falcon/sysctrl.c +++ b/arch/mips/lantiq/falcon/sysctrl.c @@ -9,11 +9,13 @@ #include #include +#include #include #include #include "devices.h" +#include "../clk.h" /* infrastructure control register */ #define SYS1_INFRAC 0x00bc @@ -38,6 +40,10 @@ #define LTQ_SYSCTL_DEACT 0x0028 /* reboot Register */ #define LTQ_SYSCTL_RBT 0x002c +/* CPU0 Clock Control Register */ +#define LTQ_SYS1_CPU0CC 0x0040 +/* clock divider bit */ +#define LTQ_CPU0CC_CPUDIV 0x0001 static struct resource ltq_sysctl_res[] = { MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), @@ -64,79 +70,67 @@ void __iomem *ltq_ebu_membase; #define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) static inline void -ltq_sysctl_wait(int module, unsigned int mask, +ltq_sysctl_wait(struct clk *clk, unsigned int test, unsigned int reg) { int err = 1000000; - do {} while (--err && ((ltq_reg_r32(module, reg) - & mask) != test)); + do {} while (--err && ((ltq_reg_r32(clk->module, reg) + & clk->bits) != test)); if (!err) - pr_err("module de/activation failed %d %08X %08X\n", - module, mask, test); + pr_err("module de/activation failed %d %08X %08X %08X\n", + clk->module, clk->bits, test, + ltq_reg_r32(clk->module, reg) & clk->bits); } -void -ltq_sysctl_activate(int module, unsigned int mask) +static int +ltq_sysctl_activate(struct clk *clk) { - if (module > SYSCTL_SYSGPE) - return; - - ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); - ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT); - ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); + return 0; } -EXPORT_SYMBOL(ltq_sysctl_activate); -void -ltq_sysctl_deactivate(int module, unsigned int mask) +static void +ltq_sysctl_deactivate(struct clk *clk) { - if (module > SYSCTL_SYSGPE) - return; - - ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); - ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT); - ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT); + ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS); } -EXPORT_SYMBOL(ltq_sysctl_deactivate); -void -ltq_sysctl_clken(int module, unsigned int mask) +static int +ltq_sysctl_clken(struct clk *clk) { - if (module > SYSCTL_SYSGPE) - return; - - ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); - ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS); + return 0; } -EXPORT_SYMBOL(ltq_sysctl_clken); -void -ltq_sysctl_clkdis(int module, unsigned int mask) +static void +ltq_sysctl_clkdis(struct clk *clk) { - if (module > SYSCTL_SYSGPE) - return; - - ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); - ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); + ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS); } -EXPORT_SYMBOL(ltq_sysctl_clkdis); -void -ltq_sysctl_reboot(int module, unsigned int mask) +static void +ltq_sysctl_reboot(struct clk *clk) { unsigned int act; - - if (module > SYSCTL_SYSGPE) - return; - - act = ltq_reg_r32(module, LTQ_SYSCTL_ACT); - if ((~act & mask) != 0) - ltq_sysctl_activate(module, ~act & mask); - ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT); - ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); + unsigned int bits; + + act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT); + bits = ~act & clk->bits; + if (bits != 0) { + ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS); + } + ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); } -EXPORT_SYMBOL(ltq_sysctl_reboot); /* enable the ONU core */ static void @@ -167,6 +161,24 @@ ltq_gpe_enable(void) udelay(1); } +static inline void +clkdev_add_sys(const char *dev, unsigned int module, + unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = NULL; + clk->cl.clk = clk; + clk->module = module; + clk->activate = ltq_sysctl_activate; + clk->deactivate = ltq_sysctl_deactivate; + clk->enable = ltq_sysctl_clken; + clk->disable = ltq_sysctl_clkdis; + clk->reboot = ltq_sysctl_reboot; + clkdev_add(&clk->cl); +} + void __init ltq_soc_init(void) { @@ -180,4 +192,19 @@ ltq_soc_init(void) ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); ltq_gpe_enable(); + + /* get our 3 static rates for cpu, fpi and io clocks */ + if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) + clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M); + else + clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M); + + /* add our clock domains */ + clkdev_add_sys("falcon_gpio.0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0); + clkdev_add_sys("falcon_gpio.1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); + clkdev_add_sys("falcon_gpio.2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2); + clkdev_add_sys("falcon_gpio.3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3); + clkdev_add_sys("falcon_gpio.4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4); + clkdev_add_sys("ltq_asc.1", SYSCTL_SYS1, ACTS_ASC1_ACT); + clkdev_add_sys("falcon_i2c", SYSCTL_SYS1, ACTS_I2C_ACT); } -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:07:25 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47364 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903753Ab2BWQDe (ORCPT ); Thu, 23 Feb 2012 17:03:34 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 06/14] MIPS: lantiq: convert dma driver to clkdev api Date: Thu, 23 Feb 2012 17:03:05 +0100 Message-Id: <1330012993-13510-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32512 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1015 Lines: 41 Update from old pmu_{dis,en}able() to ckldev api. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/dma.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index 6cf883b..ce86529 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -216,6 +217,7 @@ EXPORT_SYMBOL_GPL(ltq_dma_init_port); int __init ltq_dma_init(void) { + struct clk *clk; int i; /* remap dma register range */ @@ -224,7 +226,9 @@ ltq_dma_init(void) panic("Failed to remap dma memory"); /* power up and reset the dma engine */ - ltq_pmu_enable(PMU_DMA); + clk = clk_get_sys("ltq_dma", NULL); + WARN_ON(!clk); + clk_enable(clk); ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); /* disable all interrupts */ -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:07:53 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47368 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903755Ab2BWQDe (ORCPT ); Thu, 23 Feb 2012 17:03:34 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 07/14] MIPS: lantiq: convert gpio_stp driver to clkdev api Date: Thu, 23 Feb 2012 17:03:06 +0100 Message-Id: <1330012993-13510-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32513 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1282 Lines: 54 Update from old pmu_{dis,en}able() to ckldev api. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/gpio_stp.c | 11 ++++++++--- 1 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index e6b4809..8e07958 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include @@ -78,8 +79,10 @@ static struct gpio_chip ltq_stp_chip = { .owner = THIS_MODULE, }; -static int ltq_stp_hw_init(void) +static int ltq_stp_hw_init(struct device *dev) { + struct clk *clk; + /* sane defaults */ ltq_stp_w32(0, LTQ_STP_AR); ltq_stp_w32(0, LTQ_STP_CPU0); @@ -105,7 +108,9 @@ static int ltq_stp_hw_init(void) */ ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0); - ltq_pmu_enable(PMU_LED); + clk = clk_get(dev, NULL); + WARN_ON(!clk); + clk_enable(clk); return 0; } @@ -138,7 +143,7 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev) } ret = gpiochip_add(<q_stp_chip); if (!ret) - ret = ltq_stp_hw_init(); + ret = ltq_stp_hw_init(&pdev->dev); return ret; } -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:08:19 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47370 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903756Ab2BWQDe (ORCPT ); Thu, 23 Feb 2012 17:03:34 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 08/14] MIPS: lantiq: convert falcon gpio to clkdev api Date: Thu, 23 Feb 2012 17:03:07 +0100 Message-Id: <1330012993-13510-8-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32514 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1972 Lines: 60 The falcon gpio clocks used to be enabled when registering the platform device. Move this code into the driver and use clkdev api. Signed-off-by: John Crispin --- arch/mips/lantiq/falcon/devices.c | 5 ----- arch/mips/lantiq/falcon/gpio.c | 9 +++++++++ 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c index 4f47b44..6cd7a88 100644 --- a/arch/mips/lantiq/falcon/devices.c +++ b/arch/mips/lantiq/falcon/devices.c @@ -111,9 +111,6 @@ falcon_register_gpio(void) falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res)); platform_device_register_simple("falcon_gpio", 2, falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res)); - ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); - ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 | - ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2); } void __init @@ -123,6 +120,4 @@ falcon_register_gpio_extra(void) falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res)); platform_device_register_simple("falcon_gpio", 4, falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); - ltq_sysctl_activate(SYSCTL_SYS1, - ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4); } diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c index b7611d7..89c9896 100644 --- a/arch/mips/lantiq/falcon/gpio.c +++ b/arch/mips/lantiq/falcon/gpio.c @@ -71,6 +71,7 @@ struct falcon_gpio_port { void __iomem *port; unsigned int irq_base; unsigned int chained_irq; + struct clk *clk; }; static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS]; @@ -332,6 +333,14 @@ falcon_gpio_probe(struct platform_device *pdev) goto err; } + gpio_port->clk = clk_get(&pdev->dev, NULL); + if (!gpio_port->clk) { + dev_err(&pdev->dev, "Could not get clock\n"); + ret = -ENOENT; + goto err; + } + clk_enable(gpio_port->clk); + if (irq > 0) { /* irq_chip support */ gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq; -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:08:44 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47373 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903759Ab2BWQDf (ORCPT ); Thu, 23 Feb 2012 17:03:35 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , linux-serial@vger.kernel.org Subject: [PATCH V2 09/14] SERIAL: MIPS: lantiq: convert serial driver to clkdev api Date: Thu, 23 Feb 2012 17:03:08 +0100 Message-Id: <1330012993-13510-9-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32515 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 667 Lines: 24 Reference the FPI clock via its new access function. Signed-off-by: John Crispin Cc: linux-serial@vger.kernel.org --- drivers/tty/serial/lantiq.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index 96c1cac..99fb70f 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -686,7 +686,7 @@ lqasc_probe(struct platform_device *pdev) if (lqasc_port[pdev->id] != NULL) return -EBUSY; - clk = clk_get(&pdev->dev, "fpi"); + clk = clk_get_fpi(); if (IS_ERR(clk)) { pr_err("failed to get fpi clk\n"); return -ENOENT; -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:03:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:09:09 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47376 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903754Ab2BWQDf (ORCPT ); Thu, 23 Feb 2012 17:03:35 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 10/14] MIPS: lantiq: convert falcon debug uart to clkdev api Date: Thu, 23 Feb 2012 17:03:09 +0100 Message-Id: <1330012993-13510-10-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32516 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3413 Lines: 112 On Falcon SoCs we have a secondary serial port that can be used to help debug the voice core. For the port to work several clocking bits need to be activated. We convert the code to clkdev api. Signed-off-by: John Crispin --- arch/mips/lantiq/falcon/prom.c | 11 +---------- drivers/tty/serial/lantiq.c | 23 ++++++++++++++++++++--- 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c index b50d6f9..2a4eea17 100644 --- a/arch/mips/lantiq/falcon/prom.c +++ b/arch/mips/lantiq/falcon/prom.c @@ -27,9 +27,6 @@ #define TYPE_SHIFT 26 #define TYPE_MASK 0x3C000000 -#define MUXC_SIF_RX_PIN 112 -#define MUXC_SIF_TX_PIN 113 - /* this parameter allows us enable/disable asc1 via commandline */ static int register_asc1; static int __init @@ -46,14 +43,8 @@ ltq_soc_setup(void) ltq_register_asc(0); ltq_register_wdt(); falcon_register_gpio(); - if (register_asc1) { + if (register_asc1) ltq_register_asc(1); - if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx")) - pr_err("failed to request asc1-rx"); - if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx")) - pr_err("failed to request asc1-tx"); - ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT); - } } void __init diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index 99fb70f..cf88afd 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -107,6 +107,9 @@ #define ASCFSTAT_TXFREEMASK 0x3F000000 #define ASCFSTAT_TXFREEOFF 24 +#define MUXC_SIF_RX_PIN 112 +#define MUXC_SIF_TX_PIN 113 + static void lqasc_tx_chars(struct uart_port *port); static struct ltq_uart_port *lqasc_port[MAXPORTS]; static struct uart_driver lqasc_reg; @@ -114,6 +117,7 @@ static DEFINE_SPINLOCK(ltq_asc_lock); struct ltq_uart_port { struct uart_port port; + struct clk *fpiclk; struct clk *clk; unsigned int tx_irq; unsigned int rx_irq; @@ -316,7 +320,7 @@ lqasc_startup(struct uart_port *port) struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); int retval; - port->uartclk = clk_get_rate(ltq_port->clk); + port->uartclk = clk_get_rate(ltq_port->fpiclk); ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), port->membase + LTQ_ASC_CLC); @@ -529,6 +533,19 @@ lqasc_request_port(struct uart_port *port) if (port->membase == NULL) return -ENOMEM; } + + if (ltq_is_falcon() && (port->line == 1)) { + struct ltq_uart_port *ltq_port = lqasc_port[pdev->id]; + if (ltq_gpio_request(&pdev->dev, MUXC_SIF_RX_PIN, + 3, 0, "asc1-rx") || + ltq_gpio_request(&pdev->dev, MUXC_SIF_TX_PIN, + 3, 1, "asc1-tx")) + return -EBUSY; + ltq_port->clk = clk_get(&pdev->dev, NULL); + if (!ltq_port->clk) + return -ENOENT; + clk_enable(ltq_port->clk); + } return 0; } @@ -630,7 +647,7 @@ lqasc_console_setup(struct console *co, char *options) port = <q_port->port; - port->uartclk = clk_get_rate(ltq_port->clk); + port->uartclk = clk_get_rate(ltq_port->fpiclk); if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); @@ -715,7 +732,7 @@ lqasc_probe(struct platform_device *pdev) port->irq = tx_irq; /* unused, just to be backward-compatibe */ port->mapbase = mmres->start; - ltq_port->clk = clk; + ltq_port->fpiclk = clk; ltq_port->tx_irq = tx_irq; ltq_port->rx_irq = rx_irq; -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:04:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:09:43 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47418 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903763Ab2BWQEE (ORCPT ); Thu, 23 Feb 2012 17:04:04 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , linux-mtd@lists.infradead.org Subject: [PATCH V2 1/3] MTD: MIPS: lantiq: use module_platform_driver inside lantiq map driver Date: Thu, 23 Feb 2012 17:03:42 +0100 Message-Id: <1330013024-13622-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 X-archive-position: 32517 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1530 Lines: 58 Reduce boilerplate code by converting driver to module_platform_driver. Signed-off-by: John Crispin Cc: linux-mtd@lists.infradead.org --- drivers/mtd/maps/lantiq-flash.c | 22 +++------------------- 1 files changed, 3 insertions(+), 19 deletions(-) diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c index 7b889de..395ebfe 100644 --- a/drivers/mtd/maps/lantiq-flash.c +++ b/drivers/mtd/maps/lantiq-flash.c @@ -107,7 +107,7 @@ ltq_copy_to(struct map_info *map, unsigned long to, spin_unlock_irqrestore(&ebu_lock, flags); } -static int __init +static int __devinit ltq_mtd_probe(struct platform_device *pdev) { struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev); @@ -203,6 +203,7 @@ ltq_mtd_remove(struct platform_device *pdev) } static struct platform_driver ltq_mtd_driver = { + .probe = ltq_mtd_probe, .remove = __devexit_p(ltq_mtd_remove), .driver = { .name = "ltq_nor", @@ -210,24 +211,7 @@ static struct platform_driver ltq_mtd_driver = { }, }; -static int __init -init_ltq_mtd(void) -{ - int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); - - if (ret) - pr_err("ltq_nor: error registering platform driver"); - return ret; -} - -static void __exit -exit_ltq_mtd(void) -{ - platform_driver_unregister(<q_mtd_driver); -} - -module_init(init_ltq_mtd); -module_exit(exit_ltq_mtd); +module_platform_driver(ltq_mtd_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("John Crispin "); -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:04:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:10:07 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47420 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903765Ab2BWQEE (ORCPT ); Thu, 23 Feb 2012 17:04:04 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , netdev@vger.kernel.org Subject: [PATCH V2 2/3] NET: MIPS: lantiq: use module_platform_driver inside lantiq ethernet driver Date: Thu, 23 Feb 2012 17:03:43 +0100 Message-Id: <1330013024-13622-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330013024-13622-1-git-send-email-blogic@openwrt.org> References: <1330013024-13622-1-git-send-email-blogic@openwrt.org> X-archive-position: 32518 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1514 Lines: 58 Reduce boilerplate code by converting driver to module_platform_driver. Signed-off-by: John Crispin Cc: netdev@vger.kernel.org --- drivers/net/ethernet/lantiq_etop.c | 22 +++------------------- 1 files changed, 3 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index 6b2e4b4..584794f 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -839,7 +839,7 @@ static const struct net_device_ops ltq_eth_netdev_ops = { .ndo_tx_timeout = ltq_etop_tx_timeout, }; -static int __init +static int __devinit ltq_etop_probe(struct platform_device *pdev) { struct net_device *dev; @@ -959,6 +959,7 @@ ltq_etop_remove(struct platform_device *pdev) } static struct platform_driver ltq_mii_driver = { + .probe = ltq_etop_probe, .remove = __devexit_p(ltq_etop_remove), .driver = { .name = "ltq_etop", @@ -966,24 +967,7 @@ static struct platform_driver ltq_mii_driver = { }, }; -int __init -init_ltq_etop(void) -{ - int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); - - if (ret) - pr_err("ltq_etop: Error registering platfom driver!"); - return ret; -} - -static void __exit -exit_ltq_etop(void) -{ - platform_driver_unregister(<q_mii_driver); -} - -module_init(init_ltq_etop); -module_exit(exit_ltq_etop); +module_platform_driver(ltq_mii_driver); MODULE_AUTHOR("John Crispin "); MODULE_DESCRIPTION("Lantiq SoC ETOP"); -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:04:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:10:35 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47425 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903766Ab2BWQEF (ORCPT ); Thu, 23 Feb 2012 17:04:05 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , linux-watchdog@vger.kernel.org Subject: [PATCH V2 3/3] WDT: MIPS: lantiq: use module_platform_driver inside lantiq watchdog driver Date: Thu, 23 Feb 2012 17:03:44 +0100 Message-Id: <1330013024-13622-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330013024-13622-1-git-send-email-blogic@openwrt.org> References: <1330013024-13622-1-git-send-email-blogic@openwrt.org> X-archive-position: 32519 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1441 Lines: 55 Reduce boilerplate code by converting driver to module_platform_driver. Signed-off-by: John Crispin Cc: linux-watchdog@vger.kernel.org --- drivers/watchdog/lantiq_wdt.c | 19 +++---------------- 1 files changed, 3 insertions(+), 16 deletions(-) diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c index fa4866b..70127b3 100644 --- a/drivers/watchdog/lantiq_wdt.c +++ b/drivers/watchdog/lantiq_wdt.c @@ -182,7 +182,7 @@ static struct miscdevice ltq_wdt_miscdev = { .fops = <q_wdt_fops, }; -static int __init +static int __devinit ltq_wdt_probe(struct platform_device *pdev) { struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -227,6 +227,7 @@ ltq_wdt_remove(struct platform_device *pdev) static struct platform_driver ltq_wdt_driver = { + .probe = ltq_wdt_probe, .remove = __devexit_p(ltq_wdt_remove), .driver = { .name = "ltq_wdt", @@ -234,21 +235,7 @@ static struct platform_driver ltq_wdt_driver = { }, }; -static int __init -init_ltq_wdt(void) -{ - return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); -} - -static void __exit -exit_ltq_wdt(void) -{ - return platform_driver_unregister(<q_wdt_driver); -} - -module_init(init_ltq_wdt); -module_exit(exit_ltq_wdt); - +module_platform_driver(ltq_wdt_driver); module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:05:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:10:57 +0100 (CET) Received: from nbd.name ([46.4.11.11]:60679 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903774Ab2BWQFL (ORCPT ); Thu, 23 Feb 2012 17:05:11 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH] MIPS: lantiq: add ipi handlers to make vsmp work Date: Thu, 23 Feb 2012 17:04:52 +0100 Message-Id: <1330013092-13815-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 X-archive-position: 32520 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3253 Lines: 119 Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work on lantiq SoCs. Signed-off-by: John Crispin --- arch/mips/lantiq/irq.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++ arch/mips/lantiq/prom.c | 5 ++++ 2 files changed, 66 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 3b8cea5..71648a8 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -51,6 +52,14 @@ #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) +/* our 2 ipi interrupts for VSMP */ +#define MIPS_CPU_IPI_RESCHED_IRQ 0 +#define MIPS_CPU_IPI_CALL_IRQ 1 + +#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) +int gic_present; +#endif + static unsigned short ltq_eiu_irq[MAX_EIU] = { LTQ_EIU_IR0, LTQ_EIU_IR1, @@ -216,6 +225,47 @@ static void ltq_hw5_irqdispatch(void) do_IRQ(MIPS_CPU_TIMER_IRQ); } +#ifdef CONFIG_MIPS_MT_SMP +void __init arch_init_ipiirq(int irq, struct irqaction *action) +{ + setup_irq(irq, action); + irq_set_handler(irq, handle_percpu_irq); +} + +static void ltq_sw0_irqdispatch(void) +{ + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); +} + +static void ltq_sw1_irqdispatch(void) +{ + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); +} +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) +{ + scheduler_ipi(); + return IRQ_HANDLED; +} + +static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) +{ + smp_call_function_interrupt(); + return IRQ_HANDLED; +} + +static struct irqaction irq_resched = { + .handler = ipi_resched_interrupt, + .flags = IRQF_PERCPU, + .name = "IPI_resched" +}; + +static struct irqaction irq_call = { + .handler = ipi_call_interrupt, + .flags = IRQF_PERCPU, + .name = "IPI_call" +}; +#endif + asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; @@ -310,6 +360,17 @@ void __init arch_init_irq(void) irq_set_chip_and_handler(i, <q_irq_type, handle_level_irq); +#if defined(CONFIG_MIPS_MT_SMP) + if (cpu_has_vint) { + pr_info("Setting up IPI vectored interrupts\n"); + set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch); + set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch); + } + arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ, + &irq_resched); + arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call); +#endif + #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index b002bc7..c68a4d2 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -108,4 +108,9 @@ void __init prom_init(void) soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; pr_info("SoC: %s\n", soc_info.sys_type); prom_init_cmdline(); + +#if defined(CONFIG_MIPS_MT_SMP) + if (register_vsmp_smp_ops()) + panic("failed to register_vsmp_smp_ops()"); +#endif } -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:19:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:20:03 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57479 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903755Ab2BWQT6 (ORCPT ); Thu, 23 Feb 2012 17:19:58 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 13/14] MIPS: lantiq: unify xway prom code Date: Thu, 23 Feb 2012 17:03:12 +0100 Message-Id: <1330012993-13510-13-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32521 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5952 Lines: 238 The xway prom-ase.c and prom-xway.c files are redundant. Unify the 2 files. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/Makefile | 5 +-- arch/mips/lantiq/xway/prom-ase.c | 48 ---------------------- arch/mips/lantiq/xway/prom-xway.c | 64 ------------------------------ arch/mips/lantiq/xway/prom.c | 79 +++++++++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+), 116 deletions(-) delete mode 100644 arch/mips/lantiq/xway/prom-ase.c delete mode 100644 arch/mips/lantiq/xway/prom-xway.c create mode 100644 arch/mips/lantiq/xway/prom.c diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 4dcb96f..89f0a11 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,7 +1,4 @@ -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o - -obj-$(CONFIG_SOC_XWAY) += prom-xway.o -obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o +obj-y := prom.o sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c deleted file mode 100644 index 3f86a3b..0000000 --- a/arch/mips/lantiq/xway/prom-ase.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include - -#include - -#include "devices.h" -#include "../prom.h" - -#define SOC_AMAZON_SE "Amazon_SE" - -#define PART_SHIFT 12 -#define PART_MASK 0x0FFFFFFF -#define REV_SHIFT 28 -#define REV_MASK 0xF0000000 - -void __init ltq_soc_detect(struct ltq_soc_info *i) -{ - i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; - i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; - sprintf(i->rev_type, "1.%d", i->rev); - switch (i->partnum) { - case SOC_ID_AMAZON_SE: - i->name = SOC_AMAZON_SE; - i->type = SOC_TYPE_AMAZON_SE; - break; - - default: - unreachable(); - break; - } -} - -void __init ltq_soc_setup(void) -{ - ltq_register_ase_asc(); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c deleted file mode 100644 index d823a92..0000000 --- a/arch/mips/lantiq/xway/prom-xway.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include - -#include - -#include "devices.h" -#include "../prom.h" - -#define SOC_DANUBE "Danube" -#define SOC_TWINPASS "Twinpass" -#define SOC_AR9 "AR9" - -#define PART_SHIFT 12 -#define PART_MASK 0x0FFFFFFF -#define REV_SHIFT 28 -#define REV_MASK 0xF0000000 - -void __init ltq_soc_detect(struct ltq_soc_info *i) -{ - i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; - i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; - sprintf(i->rev_type, "1.%d", i->rev); - switch (i->partnum) { - case SOC_ID_DANUBE1: - case SOC_ID_DANUBE2: - i->name = SOC_DANUBE; - i->type = SOC_TYPE_DANUBE; - break; - - case SOC_ID_TWINPASS: - i->name = SOC_TWINPASS; - i->type = SOC_TYPE_DANUBE; - break; - - case SOC_ID_ARX188: - case SOC_ID_ARX168: - case SOC_ID_ARX182: - i->name = SOC_AR9; - i->type = SOC_TYPE_AR9; - break; - - default: - unreachable(); - break; - } -} - -void __init ltq_soc_setup(void) -{ - ltq_register_asc(0); - ltq_register_asc(1); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c new file mode 100644 index 0000000..0929acb --- /dev/null +++ b/arch/mips/lantiq/xway/prom.c @@ -0,0 +1,79 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "../prom.h" +#include "devices.h" + +#define SOC_DANUBE "Danube" +#define SOC_TWINPASS "Twinpass" +#define SOC_AR9 "AR9" +#define SOC_VR9 "VR9" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFFFFF +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + +#define SOC_AMAZON_SE "Amazon_SE" + +void __init ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); + switch (i->partnum) { + case SOC_ID_DANUBE1: + case SOC_ID_DANUBE2: + i->name = SOC_DANUBE; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_TWINPASS: + i->name = SOC_TWINPASS; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_ARX188: + case SOC_ID_ARX168: + case SOC_ID_ARX182: + i->name = SOC_AR9; + i->type = SOC_TYPE_AR9; + break; + + case SOC_ID_AMAZON_SE: + i->name = SOC_AMAZON_SE; + i->type = SOC_TYPE_AMAZON_SE; +#ifdef CONFIG_PCI + panic("ase is only supported for non pci kernels"); +#endif + break; + + default: + unreachable(); + break; + } +} + +void __init ltq_soc_setup(void) +{ + if (ltq_is_ase()) { + ltq_register_ase_asc(); + } else { + ltq_register_asc(0); + ltq_register_asc(1); + } + ltq_register_gpio(); + ltq_register_wdt(); +} -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:20:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:20:28 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57484 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903761Ab2BWQUD (ORCPT ); Thu, 23 Feb 2012 17:20:03 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , netdev@vger.kernel.org Subject: [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api Date: Thu, 23 Feb 2012 17:03:10 +0100 Message-Id: <1330012993-13510-11-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32522 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3078 Lines: 116 Update from old pmu_{dis,en}able() to ckldev api. Signed-off-by: John Crispin Cc: netdev@vger.kernel.org --- drivers/net/ethernet/lantiq_etop.c | 47 ++++++++++++++++++++++++++++++----- 1 files changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index e5ec8b1..6b2e4b4 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -36,6 +36,7 @@ #include #include #include +#include #include @@ -148,6 +149,11 @@ struct ltq_etop_priv { int tx_free[MAX_DMA_CHAN >> 1]; spinlock_t lock; + + struct clk *clk_ppe; + struct clk *clk_switch; + struct clk *clk_ephy; + struct clk *clk_ephycgu; }; static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, @@ -281,16 +287,27 @@ ltq_etop_hw_exit(struct net_device *dev) struct ltq_etop_priv *priv = netdev_priv(dev); int i; - ltq_pmu_disable(PMU_PPE); + clk_disable(priv->clk_ppe); + + if (ltq_has_gbit()) + clk_disable(priv->clk_switch); + + if (ltq_is_ase()) { + clk_disable(priv->clk_ephy); + clk_disable(priv->clk_ephycgu); + } + for (i = 0; i < MAX_DMA_CHAN; i++) if (IS_TX(i) || IS_RX(i)) ltq_etop_free_channel(dev, &priv->ch[i]); } static void -ltq_etop_gbit_init(void) +ltq_etop_gbit_init(struct net_device *dev) { - ltq_pmu_enable(PMU_SWITCH); + struct ltq_etop_priv *priv = netdev_priv(dev); + + clk_enable(priv->clk_switch); ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); /** Disable MDIO auto polling mode */ @@ -313,10 +330,10 @@ ltq_etop_hw_init(struct net_device *dev) int err = 0; int i; - ltq_pmu_enable(PMU_PPE); + clk_enable(priv->clk_ppe); if (ltq_has_gbit()) { - ltq_etop_gbit_init(); + ltq_etop_gbit_init(dev); /* force the etops link to the gbit to MII */ mii_mode = PHY_INTERFACE_MODE_MII; } @@ -334,11 +351,11 @@ ltq_etop_hw_init(struct net_device *dev) default: if (ltq_is_ase()) { - ltq_pmu_enable(PMU_EPHY); + clk_enable(priv->clk_ephy); /* disable external MII */ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); /* enable clock for internal PHY */ - ltq_cgu_enable(CGU_EPHY); + clk_enable(priv->clk_ephycgu); /* we need to write this magic to the internal phy to make it work */ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); @@ -886,6 +903,22 @@ ltq_etop_probe(struct platform_device *pdev) priv->pdev = pdev; priv->pldata = dev_get_platdata(&pdev->dev); priv->netdev = dev; + + priv->clk_ppe = clk_get(&pdev->dev, NULL); + if (!priv->clk_ppe) + return -ENOENT; + if (ltq_has_gbit()) { + priv->clk_switch = clk_get(&pdev->dev, "switch"); + if (!priv->clk_switch) + return -ENOENT; + } + if (ltq_is_ase()) { + priv->clk_ephy = clk_get(&pdev->dev, "ephy"); + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); + if (!priv->clk_ephy || !priv->clk_ephycgu) + return -ENOENT; + } + spin_lock_init(&priv->lock); for (i = 0; i < MAX_DMA_CHAN; i++) { -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:20:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:20:53 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57492 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903762Ab2BWQUE (ORCPT ); Thu, 23 Feb 2012 17:20:04 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , linux-watchdog@vger.kernel.org Subject: [PATCH V2 12/14] WDT: MIPS: lantiq: convert watchdog driver to clkdev api Date: Thu, 23 Feb 2012 17:03:11 +0100 Message-Id: <1330012993-13510-12-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32523 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 702 Lines: 24 Refrence the IO region clock via its new access function. Signed-off-by: John Crispin Cc: linux-watchdog@vger.kernel.org --- drivers/watchdog/lantiq_wdt.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c index 9c8b10c..fa4866b 100644 --- a/drivers/watchdog/lantiq_wdt.c +++ b/drivers/watchdog/lantiq_wdt.c @@ -206,7 +206,7 @@ ltq_wdt_probe(struct platform_device *pdev) } /* we do not need to enable the clock as it is always running */ - clk = clk_get(&pdev->dev, "io"); + clk = clk_get_io(); WARN_ON(!clk); ltq_io_region_clk_rate = clk_get_rate(clk); clk_put(clk); -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:20:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:21:15 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57515 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903764Ab2BWQUN (ORCPT ); Thu, 23 Feb 2012 17:20:13 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Daniel Schwierzeck Subject: [PATCH V2 14/14] MIPS: lantiq: add vr9 support Date: Thu, 23 Feb 2012 17:03:13 +0100 Message-Id: <1330012993-13510-14-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1330012993-13510-1-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> X-archive-position: 32524 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4463 Lines: 167 VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9. This patch adds the clkdev init code and SoC detection for the VR9. Signed-off-by: John Crispin Signed-off-by: Daniel Schwierzeck --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + arch/mips/lantiq/xway/clk.c | 83 ++++++++++++++++++++ arch/mips/lantiq/xway/prom.c | 6 ++ arch/mips/lantiq/xway/sysctrl.c | 12 +++- 4 files changed, 103 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 2208a9db..efd238b 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -21,6 +21,9 @@ #define SOC_ID_ARX188 0x16C #define SOC_ID_ARX168 0x16D #define SOC_ID_ARX182 0x16F +#define SOC_ID_VRX288 0x1C0 /* VRX288 v1.1 */ +#define SOC_ID_VRX268 0x1C2 /* VRX268 v1.1 */ +#define SOC_ID_GRX288 0x1C9 /* GRX288 v1.1 */ /* SoC Types */ #define SOC_TYPE_DANUBE 0x01 diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c index f3b50fc..3635c9f 100644 --- a/arch/mips/lantiq/xway/clk.c +++ b/arch/mips/lantiq/xway/clk.c @@ -225,3 +225,86 @@ unsigned long ltq_danube_fpi_hz(void) return ddr_clock >> 1; return ddr_clock; } + +unsigned long ltq_vr9_cpu_hz(void) +{ + unsigned int cpu_sel; + unsigned long clk; + + cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf; + + switch (cpu_sel) { + case 0: + clk = CLOCK_600M; + break; + case 1: + clk = CLOCK_500M; + break; + case 2: + clk = CLOCK_393M; + break; + case 3: + clk = CLOCK_333M; + break; + case 5: + case 6: + clk = CLOCK_196_608M; + break; + case 7: + clk = CLOCK_167M; + break; + case 4: + case 8: + case 9: + clk = CLOCK_125M; + break; + default: + clk = 0; + break; + } + + return clk; +} + +unsigned long ltq_vr9_fpi_hz(void) +{ + unsigned int ocp_sel, cpu_clk; + unsigned long clk; + + cpu_clk = ltq_vr9_cpu_hz(); + ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3; + + switch (ocp_sel) { + case 0: + /* OCP ratio 1 */ + clk = cpu_clk; + break; + case 2: + /* OCP ratio 2 */ + clk = cpu_clk / 2; + break; + case 3: + /* OCP ratio 2.5 */ + clk = (cpu_clk * 2) / 5; + break; + case 4: + /* OCP ratio 3 */ + clk = cpu_clk / 3; + break; + default: + clk = 0; + break; + } + + return clk; +} + +unsigned long ltq_vr9_io_region_clock(void) +{ + return ltq_vr9_fpi_hz(); +} + +unsigned long ltq_vr9_fpi_bus_clock(int fpi) +{ + return ltq_vr9_fpi_hz(); +} diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c index 0929acb..b6f56b7 100644 --- a/arch/mips/lantiq/xway/prom.c +++ b/arch/mips/lantiq/xway/prom.c @@ -60,6 +60,12 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) #endif break; + case SOC_ID_VRX268: + case SOC_ID_VRX288: + i->name = SOC_VR9; + i->type = SOC_TYPE_VR9; + break; + default: unreachable(); break; diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 22d076e..ccf9223 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -147,7 +147,8 @@ void __init ltq_soc_init(void) clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI); - clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); + if (!ltq_is_vr9()) + clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); if (ltq_is_ase()) { if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); @@ -155,6 +156,15 @@ void __init ltq_soc_init(void) clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY), clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); + } else if (ltq_is_vr9()) { + clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), + ltq_vr9_io_region_clock()); + clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY); + clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK); + clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI); + clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI); + clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL); + clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); } else { clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), ltq_danube_io_region_clock()); -- 1.7.7.1 From blogic@openwrt.org Thu Feb 23 17:22:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:22:17 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57588 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2BWQWO (ORCPT ); Thu, 23 Feb 2012 17:22:14 +0100 Message-ID: <4F4667A8.9090704@openwrt.org> Date: Thu, 23 Feb 2012 17:22:00 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.20) Gecko/20110820 Icedove/3.1.12 MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: lantiq: add ipi handlers to make vsmp work References: <1330013092-13815-1-git-send-email-blogic@openwrt.org> In-Reply-To: <1330013092-13815-1-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32525 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 472 Lines: 16 On 23/02/12 17:04, John Crispin wrote: > Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work > on lantiq SoCs. > > Signed-off-by: John Crispin Hi Ralf, This patch sort of duplicates code from mti-malta I would welcome if this patch got merged as is. I promise to send a more geneirc fix in a later series, which will remove the code redundancy and make the ipi handlers available for other targets that have no gic. thx, John From john@phrozen.org Thu Feb 23 17:25:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 17:25:31 +0100 (CET) Received: from nbd.name ([46.4.11.11]:46797 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2BWQZ0 (ORCPT ); Thu, 23 Feb 2012 17:25:26 +0100 Message-ID: <4F466867.2070800@phrozen.org> Date: Thu, 23 Feb 2012 17:25:11 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.20) Gecko/20110820 Icedove/3.1.12 MIME-Version: 1.0 To: Deng-Cheng Zhu CC: Mikael Starvik , raghu@mips.com, "linux-mips@linux-mips.org" Subject: Re: SMP MIPS and Linux 3.2 References: <4BEA3FF3CAA35E408EA55C7BE2E61D055C76C25948@xmail3.se.axis.com> In-Reply-To: X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32526 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1669 Lines: 52 Hi, the proposed patch will only fix this problem for SoCs with gic_present=1 i have just sent a patch [1] that makes it work on lantiq 34kc socs that have gic_present=0 John [1] http://www.linux-mips.org/archives/linux-mips/2012-02/msg00140.html On 23/02/12 11:11, Deng-Cheng Zhu wrote: > I should have contacted the author (Raghu Gandham) of a fix for this > issue to get it into the mainline. But it slipped out of my mind... > > The patch link is here: > http://git.linux-mips.org/?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020 > > Hi, Raghu > > Do you know why it didn't happen? > > > Deng-Cheng > > On Wed, Feb 22, 2012 at 6:57 PM, Mikael Starvik wrote: >> >> Found it! There are no calls to scheduler_ipi() from the MIPS parts in vanilla 3.2. >> >> /Mikael >> >> -----Original Message----- >> From: Mikael Starvik >> Sent: den 20 februari 2012 10:34 >> To: 'linux-mips@linux-mips.org' >> Subject: SMP MIPS and Linux 3.2 >> >> I'm running Linux 3.2 on a MIPS 34K with two VPEs (in MT_SMP configuration). It works fine in UP but with SMP it deadlocks during bootup (both CPUs gets idle). Typically like this: >> >> [ 0.090000] CPU revision is: 01019550 (MIPS 34Kc) [ 0.090000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. >> [ 0.090000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.170000] Brought up 2 CPUs >> >> I have tried to enable __ARCH_WANT_INTERRUPTS_ON_CTXSW but that didn't improve anything. Anyone else got this running or have any thoughts about what the problem may be? >> >> Best Regards >> /Mikael >> > > From zajec5@gmail.com Thu Feb 23 19:14:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 19:14:26 +0100 (CET) Received: from mail-wi0-f177.google.com ([209.85.212.177]:57165 "EHLO mail-wi0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903629Ab2BWSOX convert rfc822-to-8bit (ORCPT ); Thu, 23 Feb 2012 19:14:23 +0100 Received: by wico1 with SMTP id o1so1185876wic.36 for ; Thu, 23 Feb 2012 10:14:17 -0800 (PST) Received-SPF: pass (google.com: domain of zajec5@gmail.com designates 10.216.139.147 as permitted sender) client-ip=10.216.139.147; Authentication-Results: mr.google.com; spf=pass (google.com: domain of zajec5@gmail.com designates 10.216.139.147 as permitted sender) smtp.mail=zajec5@gmail.com; dkim=pass header.i=zajec5@gmail.com Received: from mr.google.com ([10.216.139.147]) by 10.216.139.147 with SMTP id c19mr1502057wej.11.1330020857753 (num_hops = 1); Thu, 23 Feb 2012 10:14:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=FpBNnWKLBLd77dLhpimfJ2cGjbMI5uU8Knw6/XZEpLE=; b=paffGuJUkcck+BHYZf8CWRvyY4rDsPJOBniu9qtVTa0C1tNQlu/QtJfaWE7GE6iykt hLr6JR+bldAVHJb8NAPI+bTY11LJAVP1Vqv9myiSQ3nA3O1K3b0KSc2cYEKqNCNdCLas wedlCwVu7Iv6W8fa6ulWucRbVsxXxY8Hh+RO8= MIME-Version: 1.0 Received: by 10.216.139.147 with SMTP id c19mr1226952wej.11.1330020857691; Thu, 23 Feb 2012 10:14:17 -0800 (PST) Received: by 10.216.86.8 with HTTP; Thu, 23 Feb 2012 10:14:17 -0800 (PST) In-Reply-To: <1329676345-15856-2-git-send-email-hauke@hauke-m.de> References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-2-git-send-email-hauke@hauke-m.de> Date: Thu, 23 Feb 2012 19:14:17 +0100 Message-ID: Subject: Re: [PATCH 01/11] ssb: sprom fix some sizes / signedness From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: Hauke Mehrtens Cc: linville@tuxdriver.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32527 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zajec5@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1415 Lines: 25 2012/2/19 Hauke Mehrtens : > @@ -53,10 +53,10 @@ struct ssb_sprom { >        u8 gpio1;               /* GPIO pin 1 */ >        u8 gpio2;               /* GPIO pin 2 */ >        u8 gpio3;               /* GPIO pin 3 */ > -       u16 maxpwr_bg;          /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ > -       u16 maxpwr_al;          /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ > -       u16 maxpwr_a;           /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ > -       u16 maxpwr_ah;          /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ > +       u8 maxpwr_bg;           /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ > +       u8 maxpwr_al;           /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ > +       u8 maxpwr_a;            /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ > +       u8 maxpwr_ah;           /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ >        u8 itssi_a;             /* Idle TSSI Target for A-PHY */ >        u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */ >        u8 tri2g;               /* 2.4GHz TX isolation */ Just a note in case you're going to develop ssb/bcma/b43/brcm code. Please note we're trying to switch from properties you modified to struct ssb_sprom_core_pwr_info. The patch still looks fine. -- Rafał From ddaney.cavm@gmail.com Thu Feb 23 20:19:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 20:19:55 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:32782 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903635Ab2BWTTt (ORCPT ); Thu, 23 Feb 2012 20:19:49 +0100 Received: by ggnf2 with SMTP id f2so874022ggn.36 for ; Thu, 23 Feb 2012 11:19:43 -0800 (PST) Received-SPF: pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.80.4 as permitted sender) client-ip=10.236.80.4; Authentication-Results: mr.google.com; spf=pass (google.com: domain of ddaney.cavm@gmail.com designates 10.236.80.4 as permitted sender) smtp.mail=ddaney.cavm@gmail.com; dkim=pass header.i=ddaney.cavm@gmail.com Received: from mr.google.com ([10.236.80.4]) by 10.236.80.4 with SMTP id j4mr5330334yhe.120.1330024783770 (num_hops = 1); Thu, 23 Feb 2012 11:19:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=MvXCEvX6QBI/PM9ko/YHmn0LRck0OPAF5usErf6rxrM=; b=PtIXRwltOu1FL4lEZhlY9mgKC+b09CKhgxGh8Hxnf2922fwfjQ7wzSiU3sZeFmZm+M hSbc/7rtSdhyt2BDKAu1Uw/mdJu74me4f0feme4rwWDrPEE8MndwZ8ut94W2UG5iiROZ 2sOL5m6/MR0ytIpfYIO1Dq53yuK0Rl8TrI9iM= Received: by 10.236.80.4 with SMTP id j4mr4313302yhe.120.1330024783718; Thu, 23 Feb 2012 11:19:43 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id b73sm2214169yhj.22.2012.02.23.11.19.42 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 23 Feb 2012 11:19:42 -0800 (PST) Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id q1NJJe3M025437; Thu, 23 Feb 2012 11:19:40 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id q1NJJc8x025426; Thu, 23 Feb 2012 11:19:38 -0800 From: David Daney To: Greg Kroah-Hartman Cc: linux-mips@linux-mips.org, devel@driverdev.osuosl.org, David Daney , Florian Fainelli Subject: [PATCH] staging/octeon: Fix PHY binding in octeon-ethernet driver. Date: Thu, 23 Feb 2012 11:19:31 -0800 Message-Id: <1330024771-25396-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-archive-position: 32528 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1130 Lines: 31 From: David Daney Commit d6c25be (mdio-octeon: use an unique MDIO bus name.) changed the names used to refer to MDIO buses. The ethernet driver must be changed to match, so that the PHY drivers can be attached. Cc: Florian Fainelli Signed-off-by: David Daney --- drivers/staging/octeon/ethernet-mdio.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index 63800ba..e31949c 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -164,9 +164,9 @@ int cvm_oct_phy_setup_device(struct net_device *dev) int phy_addr = cvmx_helper_board_get_mii_address(priv->port); if (phy_addr != -1) { - char phy_id[20]; + char phy_id[MII_BUS_ID_SIZE + 3]; - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", phy_addr); + snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", phy_addr); priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0, PHY_INTERFACE_MODE_GMII); -- 1.7.2.3 From bhelgaas@google.com Thu Feb 23 20:43:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 20:43:54 +0100 (CET) Received: from mail-yw0-f73.google.com ([209.85.213.73]:38842 "EHLO mail-yw0-f73.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903753Ab2BWTno (ORCPT ); Thu, 23 Feb 2012 20:43:44 +0100 Received: by yhpp61 with SMTP id p61so199718yhp.0 for ; Thu, 23 Feb 2012 11:43:38 -0800 (PST) Received-SPF: pass (google.com: domain of bhelgaas@google.com designates 10.236.145.135 as permitted sender) client-ip=10.236.145.135; Authentication-Results: mr.google.com; spf=pass (google.com: domain of bhelgaas@google.com designates 10.236.145.135 as permitted sender) smtp.mail=bhelgaas@google.com; dkim=pass header.i=bhelgaas@google.com Received: from mr.google.com ([10.236.145.135]) by 10.236.145.135 with SMTP id p7mr5850480yhj.2.1330026218678 (num_hops = 1); Thu, 23 Feb 2012 11:43:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=gamma; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=pFi8IOaM0Mg3d1z6XWls3pdXdM4Wb5twPWGg8IPxZVI=; b=D8XcXwvkU2uQfqqtyWk43hlvAtIr60yujNlJXrN8ItuXbeAr6BY5yZNfmXiCMUSQr6 Ioshg6rN3WbV8W4dqPnIymlbrxaUU1s8Ap+a+GyJN5wl5hbPpJxuOFqE0pKCVOPZFEZM w6tBu3P7UNVhQnu6N6/rORNnoMeXGkuXUolTc= Received: by 10.236.145.135 with SMTP id p7mr4156747yhj.2.1330026218660; Thu, 23 Feb 2012 11:43:38 -0800 (PST) Received: by 10.236.145.135 with SMTP id p7mr4156731yhj.2.1330026218597; Thu, 23 Feb 2012 11:43:38 -0800 (PST) Received: from wpzn4.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id i36si679976anp.0.2012.02.23.11.43.38 (version=TLSv1/SSLv3 cipher=AES128-SHA); Thu, 23 Feb 2012 11:43:38 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by wpzn4.hot.corp.google.com (Postfix) with ESMTP id 6EAE81E004D; Thu, 23 Feb 2012 11:43:38 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id 2362E180059; Thu, 23 Feb 2012 11:43:38 -0800 (PST) Subject: [PATCH v2 07/12] mips/PCI: replace pci_probe_only with pci_flags To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: linux-arch@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle Date: Thu, 23 Feb 2012 12:43:38 -0700 Message-ID: <20120223194338.20708.45646.stgit@bhelgaas.mtv.corp.google.com> In-Reply-To: <20120223194209.20708.54480.stgit@bhelgaas.mtv.corp.google.com> References: <20120223194209.20708.54480.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlSyRCnR/JG91ajSYdWE9wcfhPjYbZaqVWtvc6OLQ7O3KOPLjKDPRcmqzoxLUsVSdQHh4FB8oj+kGHZcSv+atqe42uq14Xw1oZ/SLVj9WtorOFYauTjJdjt7bEQ7n1UkgxKArzTGkhkhsQSfaxuvTmQEqksw2gvbQiL3FUi5L46Wv3ko5s= X-archive-position: 32529 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5018 Lines: 152 Some architectures (alpha, mips, powerpc) have an arch-specific "pci_probe_only" flag. Others use PCI_PROBE_ONLY in pci_flags for the same purpose. This moves mips to the pci_flags approach so generic code can use the same test across all architectures. CC: Ralf Baechle CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas --- arch/mips/include/asm/pci.h | 3 +-- arch/mips/pci/pci-bcm1480.c | 2 +- arch/mips/pci/pci-ip27.c | 2 +- arch/mips/pci/pci-lantiq.c | 3 ++- arch/mips/pci/pci-sb1250.c | 2 +- arch/mips/pci/pci-xlr.c | 2 +- arch/mips/pci/pci.c | 13 +++++-------- 7 files changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 576397c..1e4fa3d 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -92,6 +92,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, #include #include #include +#include struct pci_dev; @@ -145,8 +146,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) #define arch_setup_msi_irqs arch_setup_msi_irqs #endif -extern int pci_probe_only; - extern char * (*pcibios_plat_setup)(char *str); #endif /* _ASM_PCI_H */ diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index af8c319..37b52dc 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -204,7 +204,7 @@ static int __init bcm1480_pcibios_init(void) uint64_t reg; /* CFE will assign PCI resources */ - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); /* Avoid ISA compat ranges. */ PCIBIOS_MIN_IO = 0x00008000UL; diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 193e949..0fbe4c0 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -50,7 +50,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) bridge_t *bridge; int slot; - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); printk("a bridge\n"); diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index be1e1af..030c77e 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -270,7 +270,8 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev) { struct ltq_pci_data *ltq_pci_data = (struct ltq_pci_data *) pdev->dev.platform_data; - pci_probe_only = 0; + + pci_clear_flags(PCI_PROBE_ONLY); ltq_pci_irq_map = ltq_pci_data->irq; ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); ltq_pci_mapped_cfg = diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 1711e8e..dd97f3a 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -213,7 +213,7 @@ static int __init sb1250_pcibios_init(void) uint64_t reg; /* CFE will assign PCI resources */ - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); /* Avoid ISA compat ranges. */ PCIBIOS_MIN_IO = 0x00008000UL; diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 3d701a9..1644805 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -292,7 +292,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) static int __init pcibios_init(void) { /* PSB assigns PCI resources */ - pci_probe_only = 1; + pci_set_flags(PCI_PROBE_ONLY); pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); /* Extend IO port for memory mapped io */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index aec2b11..2a11045 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -20,12 +20,9 @@ #include /* - * Indicate whether we respect the PCI setup left by the firmware. - * - * Make this long-lived so that we know when shutting down - * whether we probed only or not. + * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource + * assignments. */ -int pci_probe_only; #define PCI_ASSIGN_ALL_BUSSES 1 @@ -92,7 +89,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) if (!hose->iommu) PCI_DMA_BUS_IS_PHYS = 1; - if (hose->get_busno && pci_probe_only) + if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) next_busno = (*hose->get_busno)(); pci_add_resource(&resources, hose->mem_resource); @@ -115,7 +112,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) need_domain_info = 1; } - if (!pci_probe_only) { + if (!pci_has_flag(PCI_PROBE_ONLY)) { pci_bus_size_bridges(bus); pci_bus_assign_resources(bus); pci_enable_bridges(bus); @@ -282,7 +279,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) struct list_head *ln; struct pci_dev *dev = bus->self; - if (pci_probe_only && dev && + if (pci_has_flag(PCI_PROBE_ONLY) && dev && (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { pci_read_bridge_bases(bus); pcibios_fixup_device_resources(dev, bus); From bhelgaas@google.com Thu Feb 23 20:43:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 20:44:24 +0100 (CET) Received: from mail-bk0-f73.google.com ([209.85.214.73]:56770 "EHLO mail-bk0-f73.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903637Ab2BWTnt (ORCPT ); Thu, 23 Feb 2012 20:43:49 +0100 Received: by bkcji1 with SMTP id ji1so36720bkc.0 for ; Thu, 23 Feb 2012 11:43:44 -0800 (PST) Received-SPF: pass (google.com: domain of bhelgaas@google.com designates 10.14.186.9 as permitted sender) client-ip=10.14.186.9; Authentication-Results: mr.google.com; spf=pass (google.com: domain of bhelgaas@google.com designates 10.14.186.9 as permitted sender) smtp.mail=bhelgaas@google.com; dkim=pass header.i=bhelgaas@google.com Received: from mr.google.com ([10.14.186.9]) by 10.14.186.9 with SMTP id v9mr1504917eem.5.1330026224303 (num_hops = 1); Thu, 23 Feb 2012 11:43:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=gamma; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=+1Tg68MUrUdkYJBPf4zZzIhJOCahvnx2JOmPQ3BE2v4=; b=e/OSopWfcq4X8sQYJymOIFEaB/6pemq5TMiwbRUlf4rgJ4FTsmyR2QxR7hiA2BNTxf qgT5ksM5c4M1akN0lGK53Q4tSZ6nd5Ojg9Nj7zlJ4BGCHbbJKuAEwL4xj2KqwIMfIIPc iWznHEO0AeN8HYx37+eANlra2kZncBDJ8LiKU= Received: by 10.14.186.9 with SMTP id v9mr1285946eem.5.1330026224235; Thu, 23 Feb 2012 11:43:44 -0800 (PST) Received: by 10.14.186.9 with SMTP id v9mr1285927eem.5.1330026224078; Thu, 23 Feb 2012 11:43:44 -0800 (PST) Received: from hpza10.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id p49si1764747eef.0.2012.02.23.11.43.44 (version=TLSv1/SSLv3 cipher=AES128-SHA); Thu, 23 Feb 2012 11:43:44 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by hpza10.eem.corp.google.com (Postfix) with ESMTP id DBDF020004E; Thu, 23 Feb 2012 11:43:43 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id 45E5A180059; Thu, 23 Feb 2012 11:43:43 -0800 (PST) Subject: [PATCH v2 08/12] mips/PCI: removed unused pci_probe configurability To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: linux-arch@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle Date: Thu, 23 Feb 2012 12:43:43 -0700 Message-ID: <20120223194343.20708.34965.stgit@bhelgaas.mtv.corp.google.com> In-Reply-To: <20120223194209.20708.54480.stgit@bhelgaas.mtv.corp.google.com> References: <20120223194209.20708.54480.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkNRIQDzaoBS9AF0adhiZh47Y8o6XvFGSbK6GPCGYvwVFbwFyEb9WFjQksOubLuM3tC6HefgQkCKy6Fw9r3Qv/mQYu5zCg8XSfZSy5hOIxtM1jh6iqEFyc2GbzkJhUvdFTOi6RezdlezP4KpSfux1/3jQQXp6YRvO7HRbFsvqiArfEnJAo= X-archive-position: 32530 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1018 Lines: 37 We never assign anything other than PCI_ASSIGN_ALL_BUSSES to pci_probe, so just remove the indirection. If configurability is required in the future, please use the pci_flags/PCI_REASSIGN_ALL_BUS functionality as is done for powerpc. CC: Ralf Baechle CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas --- arch/mips/pci/pci.c | 6 +----- 1 files changed, 1 insertions(+), 5 deletions(-) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 2a11045..19f6d19 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -24,10 +24,6 @@ * assignments. */ -#define PCI_ASSIGN_ALL_BUSSES 1 - -unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; - /* * The PCI controller list. */ @@ -238,7 +234,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) unsigned int pcibios_assign_all_busses(void) { - return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; + return 1; } int pcibios_enable_device(struct pci_dev *dev, int mask) From bhelgaas@google.com Thu Feb 23 20:44:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 20:45:06 +0100 (CET) Received: from mail-qy0-f201.google.com ([209.85.216.201]:53737 "EHLO mail-qy0-f201.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903765Ab2BWTo6 (ORCPT ); Thu, 23 Feb 2012 20:44:58 +0100 Received: by qcse1 with SMTP id e1so16153qcs.0 for ; Thu, 23 Feb 2012 11:44:52 -0800 (PST) Received-SPF: pass (google.com: domain of bhelgaas@google.com designates 10.236.145.135 as permitted sender) client-ip=10.236.145.135; Authentication-Results: mr.google.com; spf=pass (google.com: domain of bhelgaas@google.com designates 10.236.145.135 as permitted sender) smtp.mail=bhelgaas@google.com; dkim=pass header.i=bhelgaas@google.com Received: from mr.google.com ([10.236.145.135]) by 10.236.145.135 with SMTP id p7mr5860537yhj.2.1330026292571 (num_hops = 1); Thu, 23 Feb 2012 11:44:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=gamma; h=subject:to:from:cc:date:message-id:user-agent:mime-version :content-type:content-transfer-encoding; bh=3v+Vq7jR52YAmjuiL3SApGgl5idh2KVHimKhDkvo7wk=; b=mpsIiIMdoScfD7MQit2gTQY4LDVQ9yGis/iW/cI3unwBOJ3+/fCErmH7KOOuTAdcEO qPpa7cPG6zkDDyDm8fF0iQzPG23u49M+kaoN1cuQBnv0R25ksCn3GKT3XB2sQWz17SW8 3l0QAWaVqqLwjYlISc1oxOS/g3A3w89+bcgpY= Received: by 10.236.145.135 with SMTP id p7mr4163925yhj.2.1330026292547; Thu, 23 Feb 2012 11:44:52 -0800 (PST) Received: by 10.236.145.135 with SMTP id p7mr4163910yhj.2.1330026292499; Thu, 23 Feb 2012 11:44:52 -0800 (PST) Received: from wpzn4.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id z63si1343749yhg.5.2012.02.23.11.44.52 (version=TLSv1/SSLv3 cipher=AES128-SHA); Thu, 23 Feb 2012 11:44:52 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by wpzn4.hot.corp.google.com (Postfix) with ESMTP id 649771E004D; Thu, 23 Feb 2012 11:44:52 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id 1FA24180059; Thu, 23 Feb 2012 11:44:52 -0800 (PST) Subject: [PATCH] mips/PCI: remove titan_ht_pcibios_fixup_bus() code that does nothing To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: linux-mips@linux-mips.org, Ralf Baechle Date: Thu, 23 Feb 2012 12:44:52 -0700 Message-ID: <20120223194452.21202.13905.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkjWe0Z5NDS/aV33CzZy9Sr1c7Kk+dNRmCBOZ9BhV503ujy4UDlJK2VbBHr6vz7h9tFloE/Yg8cYQ0vCJSm48DqnurqP35SHtdjZxwy1MYzSA8QOIukoZYff1kCCiWejnKT8MSwhuQAnsSLz5uvnhFLW/5uGsbP09zuzDLTurEbCQYluzY= X-archive-position: 32531 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 866 Lines: 31 This list traversal seems pointless. CC: Ralf Baechle CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas --- arch/mips/pmc-sierra/yosemite/ht-irq.c | 10 ---------- 1 files changed, 0 insertions(+), 10 deletions(-) diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c index 86b98e9..62ead66 100644 --- a/arch/mips/pmc-sierra/yosemite/ht-irq.c +++ b/arch/mips/pmc-sierra/yosemite/ht-irq.c @@ -35,16 +35,6 @@ */ void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus) { - struct pci_bus *current_bus = bus; - struct pci_dev *devices; - struct list_head *devices_link; - - list_for_each(devices_link, &(current_bus->devices)) { - devices = pci_dev_b(devices_link); - if (devices == NULL) - continue; - } - /* * PLX and SPKT related changes go here */ From hauke@hauke-m.de Thu Feb 23 22:27:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Feb 2012 22:27:49 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47129 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903629Ab2BWV1q (ORCPT ); Thu, 23 Feb 2012 22:27:46 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 82E278F61; Thu, 23 Feb 2012 22:27:45 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XTQJOohT5keX; Thu, 23 Feb 2012 22:27:31 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 3ACFD8F60; Thu, 23 Feb 2012 22:27:31 +0100 (CET) Message-ID: <4F46AF41.6060803@hauke-m.de> Date: Thu, 23 Feb 2012 22:27:29 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= CC: linville@tuxdriver.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch Subject: Re: [PATCH 01/11] ssb: sprom fix some sizes / signedness References: <1329676345-15856-1-git-send-email-hauke@hauke-m.de> <1329676345-15856-2-git-send-email-hauke@hauke-m.de> In-Reply-To: X-Enigmail-Version: 1.3.5 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 32532 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1659 Lines: 30 On 02/23/2012 07:14 PM, Rafał Miłecki wrote: > 2012/2/19 Hauke Mehrtens : >> @@ -53,10 +53,10 @@ struct ssb_sprom { >> u8 gpio1; /* GPIO pin 1 */ >> u8 gpio2; /* GPIO pin 2 */ >> u8 gpio3; /* GPIO pin 3 */ >> - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ >> - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ >> - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ >> - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ >> + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ >> + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ >> + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ >> + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ >> u8 itssi_a; /* Idle TSSI Target for A-PHY */ >> u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ >> u8 tri2g; /* 2.4GHz TX isolation */ > > Just a note in case you're going to develop ssb/bcma/b43/brcm code. > Please note we're trying to switch from properties you modified to > struct ssb_sprom_core_pwr_info. These vars are available in sprom 1-3,8,9 and the ones in struct ssb_sprom_core_pwr_info just for sprom 4,5,8,9. The old are probably not used by newer chips any more. I just found these because I generated my parsing code from broadcom open source code and got a compiler warning because of wrong sizes. > > The patch still looks fine. > From raghu@mips.com Fri Feb 24 08:53:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 08:54:01 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:35433 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903646Ab2BXHx5 convert rfc822-to-8bit (ORCPT ); Fri, 24 Feb 2012 08:53:57 +0100 Received: from exchdb01.mips.com (exchdb01.mips.com [192.168.36.67]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id q1O7rhv9013932; Thu, 23 Feb 2012 23:53:43 -0800 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([::1]) with mapi id 14.01.0270.001; Thu, 23 Feb 2012 23:53:39 -0800 From: "Gandham, Raghu" To: Deng-Cheng Zhu , Mikael Starvik CC: "linux-mips@linux-mips.org" Subject: RE: SMP MIPS and Linux 3.2 Thread-Topic: SMP MIPS and Linux 3.2 Thread-Index: AcznH9lfpXUbAgVmQ5aJnfIX4n0HcAIkubIwAGd2VNAAQXpygAAcmanw Date: Fri, 24 Feb 2012 07:53:38 +0000 Message-ID: <437D1CB836242C4498C8A7EAC739E10301232877FB@exchdb03.mips.com> References: <4BEA3FF3CAA35E408EA55C7BE2E61D055C76C25948@xmail3.se.axis.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: sFkYSjAgrIFyN6BKwCHfOA== Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 32533 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1810 Lines: 60 Hi Deng-Cheng, >Do you know why it didn't happen? I must have forgotten to upload this patch along with other patches I submitted a while ago. I will verify that this patch is valid as is and submit it. Raghu >-----Original Message----- >From: Deng-Cheng Zhu [mailto:dengcheng.zhu@gmail.com] >Sent: Thursday, February 23, 2012 2:11 AM >To: Mikael Starvik; Gandham, Raghu >Cc: linux-mips@linux-mips.org >Subject: Re: SMP MIPS and Linux 3.2 > >I should have contacted the author (Raghu Gandham) of a fix for this >issue to get it into the mainline. But it slipped out of my mind... > >The patch link is here: >http://git.linux-mips.org/?p=linux- >mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020 > >Hi, Raghu > >Do you know why it didn't happen? > > >Deng-Cheng > >On Wed, Feb 22, 2012 at 6:57 PM, Mikael Starvik > wrote: >> >> Found it! There are no calls to scheduler_ipi() from the MIPS parts in >vanilla 3.2. >> >> /Mikael >> >> -----Original Message----- >> From: Mikael Starvik >> Sent: den 20 februari 2012 10:34 >> To: 'linux-mips@linux-mips.org' >> Subject: SMP MIPS and Linux 3.2 >> >> I'm running Linux 3.2 on a MIPS 34K with two VPEs (in MT_SMP >configuration). It works fine in UP but with SMP it deadlocks during >bootup (both CPUs gets idle). Typically like this: >> >> [ 0.090000] CPU revision is: 01019550 (MIPS 34Kc) [ 0.090000] >Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. >> [ 0.090000] Primary data cache 32kB, 4-way, PIPT, no aliases, >linesize 32 bytes [ 0.170000] Brought up 2 CPUs >> >> I have tried to enable __ARCH_WANT_INTERRUPTS_ON_CTXSW but that didn't >improve anything. Anyone else got this running or have any thoughts >about what the problem may be? >> >> Best Regards >> /Mikael >> From davem@davemloft.net Fri Feb 24 09:28:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 09:28:26 +0100 (CET) Received: from shards.monkeyblade.net ([198.137.202.13]:43702 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903647Ab2BXI2T (ORCPT ); Fri, 24 Feb 2012 09:28:19 +0100 Received: from localhost (cpe-66-65-56-15.nyc.res.rr.com [66.65.56.15]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id q1O8SDJh013280 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NO); Fri, 24 Feb 2012 00:28:14 -0800 Date: Fri, 24 Feb 2012 03:28:12 -0500 (EST) Message-Id: <20120224.032812.10813781440356110.davem@davemloft.net> To: blogic@openwrt.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api From: David Miller In-Reply-To: <1330012993-13510-11-git-send-email-blogic@openwrt.org> References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> <1330012993-13510-11-git-send-email-blogic@openwrt.org> X-Mailer: Mew version 6.4 on Emacs 23.3 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (shards.monkeyblade.net [198.137.202.13]); Fri, 24 Feb 2012 00:28:16 -0800 (PST) X-archive-position: 32534 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 856 Lines: 25 From: John Crispin Date: Thu, 23 Feb 2012 17:03:10 +0100 > Update from old pmu_{dis,en}able() to ckldev api. > > Signed-off-by: John Crispin Come on guys, don't do crap like this. When you have a 14 patch series, and I only see one or two of them I have no idea what in the world you want me to do with these patches. Are they dependent upon the previous patches that weren't sent to me? Are they not and I can just apply them as-is? Could I apply them as-is, but you want them to go via the MIPS tree for some reason and just want my ACK? Nobody knows because you didn't bother to say one way or another and that is extremely irritating because as a result I have to ask you all of these stupid questions and write this rediculious email. I'm just ignoring every single one of these MIPS patches, sorry. From blogic@openwrt.org Fri Feb 24 09:40:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 09:40:58 +0100 (CET) Received: from nbd.name ([46.4.11.11]:48334 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903648Ab2BXIkw (ORCPT ); Fri, 24 Feb 2012 09:40:52 +0100 Message-ID: <4F474D02.1040306@openwrt.org> Date: Fri, 24 Feb 2012 09:40:34 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.20) Gecko/20110820 Icedove/3.1.12 MIME-Version: 1.0 To: David Miller CC: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> <1330012993-13510-11-git-send-email-blogic@openwrt.org> <20120224.032812.10813781440356110.davem@davemloft.net> In-Reply-To: <20120224.032812.10813781440356110.davem@davemloft.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32535 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1695 Lines: 50 On 24/02/12 09:28, David Miller wrote: > From: John Crispin > Date: Thu, 23 Feb 2012 17:03:10 +0100 > >> Update from old pmu_{dis,en}able() to ckldev api. >> >> Signed-off-by: John Crispin > Come on guys, don't do crap like this. > > When you have a 14 patch series, and I only see one or two of them > I have no idea what in the world you want me to do with these patches. > > Are they dependent upon the previous patches that weren't sent to me? > > Are they not and I can just apply them as-is? > > Could I apply them as-is, but you want them to go via the MIPS tree > for some reason and just want my ACK? > > Nobody knows because you didn't bother to say one way or another > and that is extremely irritating because as a result I have to > ask you all of these stupid questions and write this rediculious > email. > > I'm just ignoring every single one of these MIPS patches, sorry. Hi, you are right, totally stupid of me to waste other peoples time like this. I forgot the following things * mention that i would welcome a ack'ed by from you * mention that these patches should go via MIPS with the other patches in the series * I should have put in the commit messages, that you were CC'ed on, what the rest of the series does * on the last "fix locking issues" patch I also forgot to CC Ralf and MIPS One question if I may ask * do you want to be CC'ed for a full series even if only 1 patch relates to netdev or should I simply think more about the commit message so it is apparent what i expect ? again, sorry for wasting your time with stupidity ... I will clean up the mess I made during today ... hope you accept my apology, John From davem@davemloft.net Fri Feb 24 09:53:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 09:54:05 +0100 (CET) Received: from shards.monkeyblade.net ([198.137.202.13]:43856 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903647Ab2BXIx6 (ORCPT ); Fri, 24 Feb 2012 09:53:58 +0100 Received: from localhost (cpe-66-65-56-15.nyc.res.rr.com [66.65.56.15]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id q1O8rqkr015097 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NO); Fri, 24 Feb 2012 00:53:55 -0800 Date: Fri, 24 Feb 2012 03:53:52 -0500 (EST) Message-Id: <20120224.035352.619003522379818254.davem@davemloft.net> To: blogic@openwrt.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api From: David Miller In-Reply-To: <4F474D02.1040306@openwrt.org> References: <1330012993-13510-11-git-send-email-blogic@openwrt.org> <20120224.032812.10813781440356110.davem@davemloft.net> <4F474D02.1040306@openwrt.org> X-Mailer: Mew version 6.4 on Emacs 23.3 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (shards.monkeyblade.net [198.137.202.13]); Fri, 24 Feb 2012 00:53:56 -0800 (PST) X-archive-position: 32536 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 376 Lines: 11 From: John Crispin Date: Fri, 24 Feb 2012 09:40:34 +0100 > One question if I may ask > * do you want to be CC'ed for a full series even if only 1 patch relates > to netdev or should I simply think more about the commit message so it > is apparent what i expect ? Only post the networking patches and mention the situation at hand in this kind of case. From florian@openwrt.org Fri Feb 24 10:30:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 10:30:24 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:45649 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903647Ab2BXJaU (ORCPT ); Fri, 24 Feb 2012 10:30:20 +0100 Received: by bkcjk13 with SMTP id jk13so2378021bkc.36 for ; Fri, 24 Feb 2012 01:30:15 -0800 (PST) Received-SPF: pass (google.com: domain of f.fainelli@gmail.com designates 10.204.149.147 as permitted sender) client-ip=10.204.149.147; Authentication-Results: mr.google.com; spf=pass (google.com: domain of f.fainelli@gmail.com designates 10.204.149.147 as permitted sender) smtp.mail=f.fainelli@gmail.com; dkim=pass header.i=f.fainelli@gmail.com Received: from mr.google.com ([10.204.149.147]) by 10.204.149.147 with SMTP id t19mr680244bkv.124.1330075815275 (num_hops = 1); Fri, 24 Feb 2012 01:30:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=MYC//gsSD5oSZl9SlBNK5sxc0DL3iqXGDaqao88MkT0=; b=lJ+17O88iRFsAiMWlPeeUjdxqmcosG8o2XweR3hCwnQ1aMXqlRBAoiF7GvzgfsUGzo q4bcpoa7xgoG2wFpSkCCTReFx8qLEDwru4HgF6klxOGLmIqkIuRwNAYeoi7tuuHdExUP fGI/9zWJ/tOms+2ZEUyHwdLEtnIJ9ZkJdrbHs= Received: by 10.204.149.147 with SMTP id t19mr565891bkv.124.1330075815189; Fri, 24 Feb 2012 01:30:15 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id i2sm7448403bkd.10.2012.02.24.01.30.13 (version=SSLv3 cipher=OTHER); Fri, 24 Feb 2012 01:30:13 -0800 (PST) Message-ID: <4F47587D.5050303@openwrt.org> Date: Fri, 24 Feb 2012 10:29:33 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: David Daney CC: Greg Kroah-Hartman , linux-mips@linux-mips.org, devel@driverdev.osuosl.org, David Daney Subject: Re: [PATCH] staging/octeon: Fix PHY binding in octeon-ethernet driver. References: <1330024771-25396-1-git-send-email-ddaney.cavm@gmail.com> In-Reply-To: <1330024771-25396-1-git-send-email-ddaney.cavm@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 32537 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1259 Lines: 31 Le 02/23/12 20:19, David Daney a écrit : > From: David Daney > > Commit d6c25be (mdio-octeon: use an unique MDIO bus name.) changed the > names used to refer to MDIO buses. The ethernet driver must be > changed to match, so that the PHY drivers can be attached. > > Cc: Florian Fainelli > Signed-off-by: David Daney Acked-by: Florian Fainelli > --- > drivers/staging/octeon/ethernet-mdio.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c > index 63800ba..e31949c 100644 > --- a/drivers/staging/octeon/ethernet-mdio.c > +++ b/drivers/staging/octeon/ethernet-mdio.c > @@ -164,9 +164,9 @@ int cvm_oct_phy_setup_device(struct net_device *dev) > > int phy_addr = cvmx_helper_board_get_mii_address(priv->port); > if (phy_addr != -1) { > - char phy_id[20]; > + char phy_id[MII_BUS_ID_SIZE + 3]; > > - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", phy_addr); > + snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", phy_addr); > > priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0, > PHY_INTERFACE_MODE_GMII); From sshtylyov@mvista.com Fri Feb 24 11:36:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 11:36:40 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:48271 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903648Ab2BXKgd (ORCPT ); Fri, 24 Feb 2012 11:36:33 +0100 Received: by bkcjk13 with SMTP id jk13so2428781bkc.36 for ; Fri, 24 Feb 2012 02:36:27 -0800 (PST) Received-SPF: pass (google.com: domain of sshtylyov@mvista.com designates 10.204.152.208 as permitted sender) client-ip=10.204.152.208; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sshtylyov@mvista.com designates 10.204.152.208 as permitted sender) smtp.mail=sshtylyov@mvista.com Received: from mr.google.com ([10.204.152.208]) by 10.204.152.208 with SMTP id h16mr866275bkw.6.1330079787618 (num_hops = 1); Fri, 24 Feb 2012 02:36:27 -0800 (PST) Received: by 10.204.152.208 with SMTP id h16mr720808bkw.6.1330079787416; Fri, 24 Feb 2012 02:36:27 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-85-203.pppoe.mtu-net.ru. [91.79.85.203]) by mx.google.com with ESMTPS id x22sm7819507bkw.11.2012.02.24.02.36.25 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 02:36:26 -0800 (PST) Message-ID: <4F4767DF.4090102@mvista.com> Date: Fri, 24 Feb 2012 14:35:11 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH V2 1/6] MIPS: lantiq: remove redunant ltq_gpio_request() declaration and add device parameter References: <1330012913-13293-1-git-send-email-blogic@openwrt.org> In-Reply-To: <1330012913-13293-1-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQm27IjMHVkDuCRcKlwwVqqkOZTv1uNCGA2CMzJpRkvCncPpwp/6lSkH0q6EGYoo3uxHqs+/ X-archive-position: 32538 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 941 Lines: 28 Hello. On 23-02-2012 20:01, John Crispin wrote: > 3.2 introduced devm_request_gpio() to allow managed gpios. > The devres api requires a struct device pointer to work. Add a parameter to ltq_gpio_request() > so that managed gpios can work. > Signed-off-by: John Crispin [...] > diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h > index bf05854..d90eef3 100644 > --- a/arch/mips/include/asm/mach-lantiq/lantiq.h > +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h > @@ -39,6 +39,10 @@ extern unsigned int ltq_get_soc_type(void); > /* spinlock all ebu i/o */ > extern spinlock_t ebu_lock; > > +/* request a non-gpio and set the PIO config */ > +extern int ltq_gpio_request(struct device *dev, unsigned int pin, > + unsigned int mux, unsigned int dir, const char *name); > + Where are the call sites of this function? Shoudln't they be modified? WBR, Sergei From sshtylyov@mvista.com Fri Feb 24 11:38:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 11:38:14 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:42177 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903647Ab2BXKiI (ORCPT ); Fri, 24 Feb 2012 11:38:08 +0100 Received: by bkcjk13 with SMTP id jk13so2430056bkc.36 for ; Fri, 24 Feb 2012 02:38:03 -0800 (PST) Received-SPF: pass (google.com: domain of sshtylyov@mvista.com designates 10.204.130.129 as permitted sender) client-ip=10.204.130.129; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sshtylyov@mvista.com designates 10.204.130.129 as permitted sender) smtp.mail=sshtylyov@mvista.com Received: from mr.google.com ([10.204.130.129]) by 10.204.130.129 with SMTP id t1mr818573bks.42.1330079883138 (num_hops = 1); Fri, 24 Feb 2012 02:38:03 -0800 (PST) Received: by 10.204.130.129 with SMTP id t1mr679672bks.42.1330079882941; Fri, 24 Feb 2012 02:38:02 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-85-203.pppoe.mtu-net.ru. [91.79.85.203]) by mx.google.com with ESMTPS id o7sm7808015bkw.16.2012.02.24.02.38.01 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 02:38:02 -0800 (PST) Message-ID: <4F47683F.1010303@mvista.com> Date: Fri, 24 Feb 2012 14:36:47 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH V2 4/6] NET: MIPS: lantiq: convert etop to managed gpio References: <1330012913-13293-1-git-send-email-blogic@openwrt.org> <1330012913-13293-4-git-send-email-blogic@openwrt.org> In-Reply-To: <1330012913-13293-4-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQmKmSW3SrRZ2GNMV4pdVLW+H8VLu7jXzvHDlrIVJqicfIdhFGCmcOQdop76fdJUvHcrmbPo X-archive-position: 32539 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1216 Lines: 39 Hello. On 23-02-2012 20:01, John Crispin wrote: > ltq_gpio_request() now uses devres to manage the gpios. We need to pass a > struct device pointer to make it work. > Signed-off-by: John Crispin > Cc: netdev@vger.kernel.org > --- > drivers/net/ethernet/lantiq_etop.c | 9 ++++++--- > 1 files changed, 6 insertions(+), 3 deletions(-) > diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c > index 66ec54a..e5ec8b1 100644 > --- a/drivers/net/ethernet/lantiq_etop.c > +++ b/drivers/net/ethernet/lantiq_etop.c > @@ -292,9 +292,6 @@ ltq_etop_gbit_init(void) > { > ltq_pmu_enable(PMU_SWITCH); > > - ltq_gpio_request(42, 2, 1, "MDIO"); > - ltq_gpio_request(43, 2, 1, "MDC"); > - > ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); > /** Disable MDIO auto polling mode */ > ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); > @@ -873,6 +870,12 @@ ltq_etop_probe(struct platform_device *pdev) > err = -ENOMEM; > goto err_out; > } > + if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") || > + ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) { This needs to be merged with patch 1 to keep the git tree bisectable WBR, Sergei From sshtylyov@mvista.com Fri Feb 24 11:39:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 11:39:59 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:59751 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903649Ab2BXKjy (ORCPT ); Fri, 24 Feb 2012 11:39:54 +0100 Received: by bkcjk13 with SMTP id jk13so2431468bkc.36 for ; Fri, 24 Feb 2012 02:39:48 -0800 (PST) Received-SPF: pass (google.com: domain of sshtylyov@mvista.com designates 10.204.151.3 as permitted sender) client-ip=10.204.151.3; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sshtylyov@mvista.com designates 10.204.151.3 as permitted sender) smtp.mail=sshtylyov@mvista.com Received: from mr.google.com ([10.204.151.3]) by 10.204.151.3 with SMTP id a3mr842938bkw.34.1330079988792 (num_hops = 1); Fri, 24 Feb 2012 02:39:48 -0800 (PST) Received: by 10.204.151.3 with SMTP id a3mr699775bkw.34.1330079988594; Fri, 24 Feb 2012 02:39:48 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-85-203.pppoe.mtu-net.ru. [91.79.85.203]) by mx.google.com with ESMTPS id d5sm7874037bkb.3.2012.02.24.02.39.47 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 02:39:47 -0800 (PST) Message-ID: <4F4768A9.5040502@mvista.com> Date: Fri, 24 Feb 2012 14:38:33 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH V2 5/6] MIPS: lantiq: convert pci to managed gpio References: <1330012913-13293-1-git-send-email-blogic@openwrt.org> <1330012913-13293-5-git-send-email-blogic@openwrt.org> In-Reply-To: <1330012913-13293-5-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQmW4G7VafBU4Fd71ucX6qbnmy4u+Mey4Omzn1asLpCxME9ew1uJvDo5HNLg2QaF1z3xLmtf X-archive-position: 32540 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1232 Lines: 40 Hello. On 23-02-2012 20:01, John Crispin wrote: > ltq_gpio_request() now uses devres to manage the gpios. We need to pass a > struct device pointer to make it work. > Signed-off-by: John Crispin [...] > diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c > index 3bf42c8..47b5d8e 100644 > --- a/arch/mips/pci/pci-lantiq.c > +++ b/arch/mips/pci/pci-lantiq.c > @@ -150,24 +150,26 @@ static u32 ltq_calc_bar11mask(void) > return bar11mask; > } > > -static void ltq_pci_setup_gpio(int gpio) > +static void ltq_pci_setup_gpio(struct device *dev) > { > + struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data; > int i; > for (i = 0; i< ARRAY_SIZE(ltq_pci_gpio_map); i++) { > - if (gpio & (1 << i)) { > - ltq_gpio_request(ltq_pci_gpio_map[i].pin, > + if (conf->gpio & (1 << i)) { > + ltq_gpio_request(dev, ltq_pci_gpio_map[i].pin, > ltq_pci_gpio_map[i].mux, > ltq_pci_gpio_map[i].dir, > ltq_pci_gpio_map[i].name); > } > } > - ltq_gpio_request(21, 0, 1, "pci-reset"); > - ltq_pci_req_mask = (gpio>> PCI_REQ_SHIFT)& PCI_REQ_MASK; > + ltq_gpio_request(dev, 21, 0, 1, "pci-reset"); This needs to be merged with patch 1. WBR, Sergei From sshtylyov@mvista.com Fri Feb 24 11:40:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 11:41:00 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:65118 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903647Ab2BXKkz (ORCPT ); Fri, 24 Feb 2012 11:40:55 +0100 Received: by bkcjk13 with SMTP id jk13so2432240bkc.36 for ; Fri, 24 Feb 2012 02:40:50 -0800 (PST) Received-SPF: pass (google.com: domain of sshtylyov@mvista.com designates 10.204.154.28 as permitted sender) client-ip=10.204.154.28; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sshtylyov@mvista.com designates 10.204.154.28 as permitted sender) smtp.mail=sshtylyov@mvista.com Received: from mr.google.com ([10.204.154.28]) by 10.204.154.28 with SMTP id m28mr817896bkw.54.1330080050046 (num_hops = 1); Fri, 24 Feb 2012 02:40:50 -0800 (PST) Received: by 10.204.154.28 with SMTP id m28mr674211bkw.54.1330080049866; Fri, 24 Feb 2012 02:40:49 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-85-203.pppoe.mtu-net.ru. [91.79.85.203]) by mx.google.com with ESMTPS id u8sm7833252bkg.13.2012.02.24.02.40.48 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 02:40:49 -0800 (PST) Message-ID: <4F4768E6.8080302@mvista.com> Date: Fri, 24 Feb 2012 14:39:34 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH V2 6/6] MIPS: lantiq: convert gpio_stp to managed gpio References: <1330012913-13293-1-git-send-email-blogic@openwrt.org> <1330012913-13293-6-git-send-email-blogic@openwrt.org> In-Reply-To: <1330012913-13293-6-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQn/pYXQmhxhi+cGmYlAmt7OyuS+Mbae5iwHuijWUcgR05gl44MUVnHeW6xkXJFeNk+Yk18S X-archive-position: 32541 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1375 Lines: 41 Hello. On 23-02-2012 20:01, John Crispin wrote: > ltq_gpio_request() now uses devres to manage the gpios. We need to pass a > struct device pointer to make it work. > Signed-off-by: John Crispin > --- > arch/mips/lantiq/xway/gpio_stp.c | 13 ++++++++----- > 1 files changed, 8 insertions(+), 5 deletions(-) > diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c > index cb6f170..e6b4809 100644 > --- a/arch/mips/lantiq/xway/gpio_stp.c > +++ b/arch/mips/lantiq/xway/gpio_stp.c > @@ -80,11 +80,6 @@ static struct gpio_chip ltq_stp_chip = { > > static int ltq_stp_hw_init(void) > { > - /* the 3 pins used to control the external stp */ > - ltq_gpio_request(4, 2, 1, "stp-st"); > - ltq_gpio_request(5, 2, 1, "stp-d"); > - ltq_gpio_request(6, 2, 1, "stp-sh"); > - > /* sane defaults */ > ltq_stp_w32(0, LTQ_STP_AR); > ltq_stp_w32(0, LTQ_STP_CPU0); > @@ -133,6 +128,14 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev) > dev_err(&pdev->dev, "failed to remap STP memory\n"); > return -ENOMEM; > } > + > + /* the 3 pins used to control the external stp */ > + if (ltq_gpio_request(&pdev->dev, 4, 2, 1, "stp-st") || > + ltq_gpio_request(&pdev->dev, 5, 2, 1, "stp-d") || > + ltq_gpio_request(&pdev->dev, 6, 2, 1, "stp-sh")) { This needs to be merged to patch 1... WBR, Sergei From sshtylyov@mvista.com Fri Feb 24 11:47:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 11:47:14 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:45904 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903648Ab2BXKrH (ORCPT ); Fri, 24 Feb 2012 11:47:07 +0100 Received: by bkcjk13 with SMTP id jk13so2437168bkc.36 for ; Fri, 24 Feb 2012 02:47:02 -0800 (PST) Received-SPF: pass (google.com: domain of sshtylyov@mvista.com designates 10.204.128.75 as permitted sender) client-ip=10.204.128.75; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sshtylyov@mvista.com designates 10.204.128.75 as permitted sender) smtp.mail=sshtylyov@mvista.com Received: from mr.google.com ([10.204.128.75]) by 10.204.128.75 with SMTP id j11mr640685bks.2.1330080422499 (num_hops = 1); Fri, 24 Feb 2012 02:47:02 -0800 (PST) Received: by 10.204.128.75 with SMTP id j11mr525746bks.2.1330080422307; Fri, 24 Feb 2012 02:47:02 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-85-203.pppoe.mtu-net.ru. [91.79.85.203]) by mx.google.com with ESMTPS id ey8sm7922479bkb.1.2012.02.24.02.47.00 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 02:47:01 -0800 (PST) Message-ID: <4F476A5A.1060007@mvista.com> Date: Fri, 24 Feb 2012 14:45:46 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH V2 08/14] MIPS: lantiq: convert falcon gpio to clkdev api References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> <1330012993-13510-8-git-send-email-blogic@openwrt.org> In-Reply-To: <1330012993-13510-8-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQnqSaP75/5Mk5alLzB233WC0TbQV+dgtCE87fid0/qfT/7mFkRDKB737L3fbNu/PqCkavlF X-archive-position: 32542 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 809 Lines: 30 Hello. On 23-02-2012 20:03, John Crispin wrote: > The falcon gpio clocks used to be enabled when registering the platform device. > Move this code into the driver and use clkdev api. > Signed-off-by: John Crispin [...] > diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c > index b7611d7..89c9896 100644 > --- a/arch/mips/lantiq/falcon/gpio.c > +++ b/arch/mips/lantiq/falcon/gpio.c [...] > @@ -332,6 +333,14 @@ falcon_gpio_probe(struct platform_device *pdev) > goto err; > } > > + gpio_port->clk = clk_get(&pdev->dev, NULL); > + if (!gpio_port->clk) { clk_get() returns error, not NULL. So you should use IS_ERR(gpio_port->clk). > + dev_err(&pdev->dev, "Could not get clock\n"); > + ret = -ENOENT; ret = PTR_ERR(gpio_port->clk); WBR, Sergei From sshtylyov@mvista.com Fri Feb 24 11:48:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 11:48:22 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:54524 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903648Ab2BXKsR (ORCPT ); Fri, 24 Feb 2012 11:48:17 +0100 Received: by bkcjk13 with SMTP id jk13so2437974bkc.36 for ; Fri, 24 Feb 2012 02:48:12 -0800 (PST) Received-SPF: pass (google.com: domain of sshtylyov@mvista.com designates 10.204.148.79 as permitted sender) client-ip=10.204.148.79; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sshtylyov@mvista.com designates 10.204.148.79 as permitted sender) smtp.mail=sshtylyov@mvista.com Received: from mr.google.com ([10.204.148.79]) by 10.204.148.79 with SMTP id o15mr841456bkv.33.1330080492504 (num_hops = 1); Fri, 24 Feb 2012 02:48:12 -0800 (PST) Received: by 10.204.148.79 with SMTP id o15mr701574bkv.33.1330080492299; Fri, 24 Feb 2012 02:48:12 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-85-203.pppoe.mtu-net.ru. [91.79.85.203]) by mx.google.com with ESMTPS id jc4sm7903668bkc.7.2012.02.24.02.48.10 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 02:48:11 -0800 (PST) Message-ID: <4F476AA0.7030703@mvista.com> Date: Fri, 24 Feb 2012 14:46:56 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH V2 07/14] MIPS: lantiq: convert gpio_stp driver to clkdev api References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> <1330012993-13510-7-git-send-email-blogic@openwrt.org> In-Reply-To: <1330012993-13510-7-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQmtDQzAdxi2EQCfFOnnjFlLLF0K9LZs42NkeYJRo3sQ21e05n6vIoD1iKuK0Ge6Sz2QJNGQ X-archive-position: 32543 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 618 Lines: 25 Hello. On 23-02-2012 20:03, John Crispin wrote: > Update from old pmu_{dis,en}able() to ckldev api. > Signed-off-by: John Crispin [...] > diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c > index e6b4809..8e07958 100644 > --- a/arch/mips/lantiq/xway/gpio_stp.c > +++ b/arch/mips/lantiq/xway/gpio_stp.c [...] > @@ -105,7 +108,9 @@ static int ltq_stp_hw_init(void) > */ > ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0); > > - ltq_pmu_enable(PMU_LED); > + clk = clk_get(dev, NULL); > + WARN_ON(!clk); clk_get() returns error, not NULL. WBR, Sergei From sshtylyov@mvista.com Fri Feb 24 11:54:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 11:54:45 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:37989 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903649Ab2BXKyj (ORCPT ); Fri, 24 Feb 2012 11:54:39 +0100 Received: by bkcjk13 with SMTP id jk13so2442776bkc.36 for ; Fri, 24 Feb 2012 02:54:34 -0800 (PST) Received-SPF: pass (google.com: domain of sshtylyov@mvista.com designates 10.205.134.1 as permitted sender) client-ip=10.205.134.1; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sshtylyov@mvista.com designates 10.205.134.1 as permitted sender) smtp.mail=sshtylyov@mvista.com Received: from mr.google.com ([10.205.134.1]) by 10.205.134.1 with SMTP id ia1mr847169bkc.78.1330080874368 (num_hops = 1); Fri, 24 Feb 2012 02:54:34 -0800 (PST) Received: by 10.205.134.1 with SMTP id ia1mr700426bkc.78.1330080874174; Fri, 24 Feb 2012 02:54:34 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-85-203.pppoe.mtu-net.ru. [91.79.85.203]) by mx.google.com with ESMTPS id x20sm7930231bka.9.2012.02.24.02.54.32 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 02:54:33 -0800 (PST) Message-ID: <4F476C1E.9020608@mvista.com> Date: Fri, 24 Feb 2012 14:53:18 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH V2 10/14] MIPS: lantiq: convert falcon debug uart to clkdev api References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> <1330012993-13510-10-git-send-email-blogic@openwrt.org> In-Reply-To: <1330012993-13510-10-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQm9LAdJJXYwnat1NDkUxtnzlnRzj0zwdBdbYdsIwqKxslHHA5mJTS8c9zL33G1CmYoBb7vK X-archive-position: 32544 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1189 Lines: 37 Hello. On 23-02-2012 20:03, John Crispin wrote: > On Falcon SoCs we have a secondary serial port that can be used to help > debug the voice core. For the port to work several clocking bits need to > be activated. We convert the code to clkdev api. You also convert to new ltq_gpio_request() here. I don't think you should mix these two things up in one patch. > Signed-off-by: John Crispin [...] > diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c > index 99fb70f..cf88afd 100644 > --- a/drivers/tty/serial/lantiq.c > +++ b/drivers/tty/serial/lantiq.c [...] > @@ -529,6 +533,19 @@ lqasc_request_port(struct uart_port *port) > if (port->membase == NULL) > return -ENOMEM; > } > + > + if (ltq_is_falcon()&& (port->line == 1)) { > + struct ltq_uart_port *ltq_port = lqasc_port[pdev->id]; > + if (ltq_gpio_request(&pdev->dev, MUXC_SIF_RX_PIN, > + 3, 0, "asc1-rx") || > + ltq_gpio_request(&pdev->dev, MUXC_SIF_TX_PIN, > + 3, 1, "asc1-tx")) > + return -EBUSY; > + ltq_port->clk = clk_get(&pdev->dev, NULL); > + if (!ltq_port->clk) clk_get() returns error code, not NULL. Use IS_ERR() and PTR_ERR(). WBR, Sergei From sshtylyov@mvista.com Fri Feb 24 11:56:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 11:56:43 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:42842 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903647Ab2BXK4f (ORCPT ); Fri, 24 Feb 2012 11:56:35 +0100 Received: by bkcjk13 with SMTP id jk13so2444340bkc.36 for ; Fri, 24 Feb 2012 02:56:30 -0800 (PST) Received-SPF: pass (google.com: domain of sshtylyov@mvista.com designates 10.205.129.137 as permitted sender) client-ip=10.205.129.137; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sshtylyov@mvista.com designates 10.205.129.137 as permitted sender) smtp.mail=sshtylyov@mvista.com Received: from mr.google.com ([10.205.129.137]) by 10.205.129.137 with SMTP id hi9mr803173bkc.131.1330080990753 (num_hops = 1); Fri, 24 Feb 2012 02:56:30 -0800 (PST) Received: by 10.205.129.137 with SMTP id hi9mr668368bkc.131.1330080990560; Fri, 24 Feb 2012 02:56:30 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-85-203.pppoe.mtu-net.ru. [91.79.85.203]) by mx.google.com with ESMTPS id ey8sm7975326bkb.1.2012.02.24.02.56.29 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 02:56:29 -0800 (PST) Message-ID: <4F476C93.2000304@mvista.com> Date: Fri, 24 Feb 2012 14:55:15 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api References: <1330012993-13510-1-git-send-email-blogic@openwrt.org> <1330012993-13510-11-git-send-email-blogic@openwrt.org> In-Reply-To: <1330012993-13510-11-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkGbSpcjSlVgvFfEMd5HDltmIsCIjHtPVS1IS3ygryd3Qyx1LM/hC+OPBon4GmycpqoU+69 X-archive-position: 32545 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1069 Lines: 39 Hello. On 23-02-2012 20:03, John Crispin wrote: > Update from old pmu_{dis,en}able() to ckldev api. > Signed-off-by: John Crispin > Cc: netdev@vger.kernel.org [...] > diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c > index e5ec8b1..6b2e4b4 100644 > --- a/drivers/net/ethernet/lantiq_etop.c > +++ b/drivers/net/ethernet/lantiq_etop.c [...] > @@ -886,6 +903,22 @@ ltq_etop_probe(struct platform_device *pdev) > priv->pdev = pdev; > priv->pldata = dev_get_platdata(&pdev->dev); > priv->netdev = dev; > + > + priv->clk_ppe = clk_get(&pdev->dev, NULL); > + if (!priv->clk_ppe) > + return -ENOENT; > + if (ltq_has_gbit()) { > + priv->clk_switch = clk_get(&pdev->dev, "switch"); > + if (!priv->clk_switch) clk_get() doesn't retirn NULL, it returns error code. > + return -ENOENT; > + } > + if (ltq_is_ase()) { > + priv->clk_ephy = clk_get(&pdev->dev, "ephy"); > + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); > + if (!priv->clk_ephy || !priv->clk_ephycgu) Same here. WBR, Sergei From arnd@arndb.de Fri Feb 24 16:49:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 16:49:38 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.126.186]:53695 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903652Ab2BXPte (ORCPT ); Fri, 24 Feb 2012 16:49:34 +0100 Received: from klappe2.localnet (deibp9eh1--blueice3n2.emea.ibm.com [195.212.29.180]) by mrelayeu.kundenserver.de (node=mreu4) with ESMTP (Nemesis) id 0LwBkQ-1SWCRt0XAE-017RQY; Fri, 24 Feb 2012 16:49:03 +0100 From: Arnd Bergmann To: Marek Szyprowski Subject: Re: [PATCH 00/14] DMA-mapping framework redesign preparation Date: Fri, 24 Feb 2012 15:48:59 +0000 User-Agent: KMail/1.12.2 (Linux/3.3.0-rc1; KDE/4.3.2; x86_64; ; ) Cc: linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Stephen Rothwell , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Kyungmin Park , Andrzej Pietrasiewicz References: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com> In-Reply-To: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Message-Id: <201202241548.59791.arnd@arndb.de> X-Provags-ID: V02:K0:T7az3aeAxJJ2biO5z7hE5jD6TBIYwaYasOrCkwG3CUl vTSpX2XwMIxuIVDPdgwnGbr6FRW8RxQICDQWSWXyApB3pO4U1Q QfBbxFcWfTMxLmF0cS8rtUYp8GDWUNMeNHEJFNLUA2J9ej9uns xhueLubFJiBlXL2eVEch3AkSsFkCZm2ZIbFmpjtY3ulrbChUxy F9hdbMLvUJm6Ap1t7D9RQepxYPTHA/E3xdcAp47h9BphDn/Vz/ GObA9B/ql/AkniRF9iYr6C3elm/tPlVwGfOcB6d0EmorDfrZmO DDiJBO2oGhz71dxK7ynoB/fIMas0g3e0kDxsB3jjWc1oSWtHus kqfQlD5ooX2o7Tw051bI= X-archive-position: 32546 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arnd@arndb.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 679 Lines: 14 On Friday 23 December 2011, Marek Szyprowski wrote: > The solution we found is to introduce a new public dma mapping functions > with additional attributes argument: dma_alloc_attrs and > dma_free_attrs(). This way all different kinds of architecture specific > buffer mappings can be hidden behind the attributes without the need of > creating several versions of dma_alloc_ function. Since the patches are now in linux-next, we should make sure that they can actually get merged into 3.4. I've looked at all the patches again and found them to be straightforward and helpful, I hope we can get them merged next time. Please add my Reviewed-by: Arnd Bergmann From danny.kukawka@bisect.de Fri Feb 24 17:01:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 17:01:50 +0100 (CET) Received: from wp188.webpack.hosteurope.de ([80.237.132.195]:44429 "EHLO wp188.webpack.hosteurope.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903755Ab2BXQBn (ORCPT ); Fri, 24 Feb 2012 17:01:43 +0100 Received: from charybdis-ext.suse.de ([195.135.221.2] helo=g231.suse.de); authenticated by wp188.webpack.hosteurope.de running ExIM with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) id 1S0xaO-0005hi-UO; Fri, 24 Feb 2012 17:01:32 +0100 From: Danny Kukawka To: Christian Benvenuti , Roopa Prabhu , Neel Patel , Nishank Trivedi , Guo-Fu Tseng , Ralf Baechle , Andy Gospodarek Cc: Danny Kukawka , "David S. Miller" , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: [PATCH 01/12] ethernet: .ndo_set_mac_address: check given address, if invalid return -EADDRNOTAVAIL Date: Fri, 24 Feb 2012 17:01:11 +0100 Message-Id: <1330099282-4588-2-git-send-email-danny.kukawka@bisect.de> X-Mailer: git-send-email 1.7.8.3 In-Reply-To: <1330099282-4588-1-git-send-email-danny.kukawka@bisect.de> References: <1330099282-4588-1-git-send-email-danny.kukawka@bisect.de> X-bounce-key: webpack.hosteurope.de;danny.kukawka@bisect.de;1330099303;0498b75c; X-archive-position: 32547 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: danny.kukawka@bisect.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6496 Lines: 176 Check if given address is valid in .ndo_set_mac_address, if invalid return -EADDRNOTAVAIL as eth_mac_addr() already does if is_valid_ether_addr() fails. Signed-off-by: Danny Kukawka --- drivers/net/ethernet/amd/amd8111e.c | 3 +++ drivers/net/ethernet/amd/atarilance.c | 3 +++ drivers/net/ethernet/chelsio/cxgb/cxgb2.c | 3 +++ drivers/net/ethernet/cisco/enic/enic_main.c | 3 +++ drivers/net/ethernet/freescale/fec_mpc52xx.c | 3 +++ drivers/net/ethernet/jme.c | 3 +++ drivers/net/ethernet/micrel/ks8851_mll.c | 3 +++ drivers/net/ethernet/micrel/ksz884x.c | 3 +++ drivers/net/ethernet/seeq/sgiseeq.c | 3 +++ drivers/net/ethernet/sgi/ioc3-eth.c | 3 +++ drivers/net/ethernet/tehuti/tehuti.c | 3 +++ 11 files changed, 33 insertions(+), 0 deletions(-) diff --git a/drivers/net/ethernet/amd/amd8111e.c b/drivers/net/ethernet/amd/amd8111e.c index 9f62504..b0e3603 100644 --- a/drivers/net/ethernet/amd/amd8111e.c +++ b/drivers/net/ethernet/amd/amd8111e.c @@ -1549,6 +1549,9 @@ static int amd8111e_set_mac_address(struct net_device *dev, void *p) int i; struct sockaddr *addr = p; + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); spin_lock_irq(&lp->lock); /* Setting the MAC address to the device */ diff --git a/drivers/net/ethernet/amd/atarilance.c b/drivers/net/ethernet/amd/atarilance.c index 70ed79c..a9612f7 100644 --- a/drivers/net/ethernet/amd/atarilance.c +++ b/drivers/net/ethernet/amd/atarilance.c @@ -1125,6 +1125,9 @@ static int lance_set_mac_address( struct net_device *dev, void *addr ) struct sockaddr *saddr = addr; int i; + if (!is_valid_ether_addr(saddr->sa_data)) + return -EADDRNOTAVAIL; + if (lp->cardtype != OLD_RIEBL && lp->cardtype != NEW_RIEBL) return -EOPNOTSUPP; diff --git a/drivers/net/ethernet/chelsio/cxgb/cxgb2.c b/drivers/net/ethernet/chelsio/cxgb/cxgb2.c index 1d17c92..8e363ce 100644 --- a/drivers/net/ethernet/chelsio/cxgb/cxgb2.c +++ b/drivers/net/ethernet/chelsio/cxgb/cxgb2.c @@ -841,6 +841,9 @@ static int t1_set_mac_addr(struct net_device *dev, void *p) struct cmac *mac = adapter->port[dev->if_port].mac; struct sockaddr *addr = p; + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + if (!mac->ops->macaddress_set) return -EOPNOTSUPP; diff --git a/drivers/net/ethernet/cisco/enic/enic_main.c b/drivers/net/ethernet/cisco/enic/enic_main.c index e27ec1d..67a340d 100644 --- a/drivers/net/ethernet/cisco/enic/enic_main.c +++ b/drivers/net/ethernet/cisco/enic/enic_main.c @@ -903,6 +903,9 @@ static int enic_set_mac_address(struct net_device *netdev, void *p) struct enic *enic = netdev_priv(netdev); int err; + if (!is_valid_ether_addr(saddr->sa_data)) + return -EADDRNOTAVAIL; + err = enic_dev_del_station_addr(enic); if (err) return err; diff --git a/drivers/net/ethernet/freescale/fec_mpc52xx.c b/drivers/net/ethernet/freescale/fec_mpc52xx.c index 7b34d8c..26ea3ad 100644 --- a/drivers/net/ethernet/freescale/fec_mpc52xx.c +++ b/drivers/net/ethernet/freescale/fec_mpc52xx.c @@ -123,6 +123,9 @@ static int mpc52xx_fec_set_mac_address(struct net_device *dev, void *addr) { struct sockaddr *sock = addr; + if (!is_valid_ether_addr(sock->sa_data)) + return -EADDRNOTAVAIL; + memcpy(dev->dev_addr, sock->sa_data, dev->addr_len); mpc52xx_fec_set_paddr(dev, sock->sa_data); diff --git a/drivers/net/ethernet/jme.c b/drivers/net/ethernet/jme.c index 1b86d0b..117598e 100644 --- a/drivers/net/ethernet/jme.c +++ b/drivers/net/ethernet/jme.c @@ -2271,6 +2271,9 @@ jme_set_macaddr(struct net_device *netdev, void *p) struct jme_adapter *jme = netdev_priv(netdev); struct sockaddr *addr = p; + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + if (netif_running(netdev)) return -EBUSY; diff --git a/drivers/net/ethernet/micrel/ks8851_mll.c b/drivers/net/ethernet/micrel/ks8851_mll.c index 10d5798..82430ff 100644 --- a/drivers/net/ethernet/micrel/ks8851_mll.c +++ b/drivers/net/ethernet/micrel/ks8851_mll.c @@ -1239,6 +1239,9 @@ static int ks_set_mac_address(struct net_device *netdev, void *paddr) struct sockaddr *addr = paddr; u8 *da; + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + netdev->addr_assign_type &= ~NET_ADDR_RANDOM; memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); diff --git a/drivers/net/ethernet/micrel/ksz884x.c b/drivers/net/ethernet/micrel/ksz884x.c index ef723b1..db29407 100644 --- a/drivers/net/ethernet/micrel/ksz884x.c +++ b/drivers/net/ethernet/micrel/ksz884x.c @@ -5668,6 +5668,9 @@ static int netdev_set_mac_address(struct net_device *dev, void *addr) struct sockaddr *mac = addr; uint interrupt; + if (!is_valid_ether_addr(mac->sa_data)) + return -EADDRNOTAVAIL; + if (priv->port.first_port > 0) hw_del_addr(hw, dev->dev_addr); else { diff --git a/drivers/net/ethernet/seeq/sgiseeq.c b/drivers/net/ethernet/seeq/sgiseeq.c index bb8c822..41ad6ba 100644 --- a/drivers/net/ethernet/seeq/sgiseeq.c +++ b/drivers/net/ethernet/seeq/sgiseeq.c @@ -163,6 +163,9 @@ static int sgiseeq_set_mac_address(struct net_device *dev, void *addr) struct sgiseeq_private *sp = netdev_priv(dev); struct sockaddr *sa = addr; + if (!is_valid_ether_addr(sa->sa_data)) + return -EADDRNOTAVAIL; + memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); spin_lock_irq(&sp->tx_lock); diff --git a/drivers/net/ethernet/sgi/ioc3-eth.c b/drivers/net/ethernet/sgi/ioc3-eth.c index ac149d9..a069546 100644 --- a/drivers/net/ethernet/sgi/ioc3-eth.c +++ b/drivers/net/ethernet/sgi/ioc3-eth.c @@ -458,6 +458,9 @@ static int ioc3_set_mac_address(struct net_device *dev, void *addr) struct ioc3_private *ip = netdev_priv(dev); struct sockaddr *sa = addr; + if (!is_valid_ether_addr(sa->sa_data)) + return -EADDRNOTAVAIL; + memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); spin_lock_irq(&ip->ioc3_lock); diff --git a/drivers/net/ethernet/tehuti/tehuti.c b/drivers/net/ethernet/tehuti/tehuti.c index ad973ff..30822ac 100644 --- a/drivers/net/ethernet/tehuti/tehuti.c +++ b/drivers/net/ethernet/tehuti/tehuti.c @@ -837,6 +837,9 @@ static int bdx_set_mac(struct net_device *ndev, void *p) struct sockaddr *addr = p; ENTER; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; /* if (netif_running(dev)) return -EBUSY -- 1.7.8.3 From danny.kukawka@bisect.de Fri Feb 24 17:01:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 17:02:17 +0100 (CET) Received: from wp188.webpack.hosteurope.de ([80.237.132.195]:44460 "EHLO wp188.webpack.hosteurope.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903754Ab2BXQBz (ORCPT ); Fri, 24 Feb 2012 17:01:55 +0100 Received: from charybdis-ext.suse.de ([195.135.221.2] helo=g231.suse.de); authenticated by wp188.webpack.hosteurope.de running ExIM with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) id 1S0xaO-0005hi-PU; Fri, 24 Feb 2012 17:01:32 +0100 From: Danny Kukawka To: "David S. Miller" , Andy Gospodarek , Guo-Fu Tseng , Petko Manolov , "VMware, Inc." , "John W. Linville" , linux390@de.ibm.com, Mauro Carvalho Chehab Cc: Danny Kukawka , Stephen Hemminger , Joe Perches , Jeff Kirsher , Jiri Pirko , netdev@vger.kernel.org, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, libertas-dev@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-s390@vger.kernel.org, linux-hams@vger.kernel.org, linux-mips@linux-mips.org Subject: [PATCH 00/12] Part 2: check given MAC address, if invalid return -EADDRNOTAVAIL Date: Fri, 24 Feb 2012 17:01:10 +0100 Message-Id: <1330099282-4588-1-git-send-email-danny.kukawka@bisect.de> X-Mailer: git-send-email 1.7.8.3 X-bounce-key: webpack.hosteurope.de;danny.kukawka@bisect.de;1330099315;658d9812; X-archive-position: 32548 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: danny.kukawka@bisect.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3275 Lines: 64 Second Part of series patches to unifiy the return value of .ndo_set_mac_address if the given address isn't valid. These changes check if a given (MAC) address is valid in .ndo_set_mac_address, if invalid return -EADDRNOTAVAIL as eth_mac_addr() already does if is_valid_ether_addr() fails. These patches are against net-next. Danny Kukawka (12): ethernet: .ndo_set_mac_address: check given address, if invalid return -EADDRNOTAVAIL cris/eth_v10: check given MAC address, if invalid return -EADDRNOTAVAIL dvb_net: check given MAC address, if invalid return -EADDRNOTAVAIL fddi/skfp: check given MAC address, if invalid return -EADDRNOTAVAIL team: check given MAC address, if invalid return -EADDRNOTAVAIL tokenring: check given MAC address, if invalid return -EADDRNOTAVAIL usb/rtl8150: check given MAC address, if invalid return -EADDRNOTAVAIL vmxnet3: check given MAC address, if invalid return -EADDRNOTAVAIL wan/lapbether: check given MAC address, if invalid return -EADDRNOTAVAIL wireless: check given MAC address, if invalid return -EADDRNOTAVAIL s390/net/qeth_l2_main: check given MAC address, if invalid return -EADDRNOTAVAIL rose: check given MAC address, if invalid return -EADDRNOTAVAIL drivers/media/dvb/dvb-core/dvb_net.c | 5 ++++- drivers/net/cris/eth_v10.c | 3 +++ drivers/net/ethernet/amd/amd8111e.c | 3 +++ drivers/net/ethernet/amd/atarilance.c | 3 +++ drivers/net/ethernet/chelsio/cxgb/cxgb2.c | 3 +++ drivers/net/ethernet/cisco/enic/enic_main.c | 3 +++ drivers/net/ethernet/freescale/fec_mpc52xx.c | 3 +++ drivers/net/ethernet/jme.c | 3 +++ drivers/net/ethernet/micrel/ks8851_mll.c | 3 +++ drivers/net/ethernet/micrel/ksz884x.c | 3 +++ drivers/net/ethernet/seeq/sgiseeq.c | 3 +++ drivers/net/ethernet/sgi/ioc3-eth.c | 3 +++ drivers/net/ethernet/tehuti/tehuti.c | 3 +++ drivers/net/fddi/skfp/skfddi.c | 3 +++ drivers/net/team/team.c | 3 +++ drivers/net/tokenring/3c359.c | 4 ++++ drivers/net/tokenring/lanstreamer.c | 4 ++++ drivers/net/tokenring/olympic.c | 4 ++++ drivers/net/tokenring/tms380tr.c | 3 +++ drivers/net/usb/rtl8150.c | 3 +++ drivers/net/vmxnet3/vmxnet3_drv.c | 3 +++ drivers/net/wan/lapbether.c | 5 +++++ drivers/net/wireless/airo.c | 3 +++ drivers/net/wireless/atmel.c | 3 +++ .../net/wireless/brcm80211/brcmfmac/dhd_linux.c | 5 ++++- drivers/net/wireless/hostap/hostap_main.c | 3 +++ drivers/net/wireless/libertas/main.c | 3 +++ drivers/net/wireless/mwifiex/main.c | 3 +++ drivers/net/wireless/zd1201.c | 2 ++ drivers/s390/net/qeth_l2_main.c | 3 +++ net/rose/rose_dev.c | 3 +++ 31 files changed, 99 insertions(+), 2 deletions(-) -- 1.7.8.3 From grant.likely@secretlab.ca Fri Feb 24 17:30:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 17:30:12 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:55359 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903755Ab2BXQaF (ORCPT ); Fri, 24 Feb 2012 17:30:05 +0100 Received: by pbcun1 with SMTP id un1so3260036pbc.36 for ; Fri, 24 Feb 2012 08:29:58 -0800 (PST) Received-SPF: pass (google.com: domain of glikely@secretlab.ca designates 10.68.136.100 as permitted sender) client-ip=10.68.136.100; Authentication-Results: mr.google.com; spf=pass (google.com: domain of glikely@secretlab.ca designates 10.68.136.100 as permitted sender) smtp.mail=glikely@secretlab.ca Received: from mr.google.com ([10.68.136.100]) by 10.68.136.100 with SMTP id pz4mr9725400pbb.26.1330100998617 (num_hops = 1); Fri, 24 Feb 2012 08:29:58 -0800 (PST) MIME-Version: 1.0 Received: by 10.68.136.100 with SMTP id pz4mr8036162pbb.26.1330100998472; Fri, 24 Feb 2012 08:29:58 -0800 (PST) Received: from localhost (S0106d8b37715ee14.cg.shawcable.net. [68.146.14.168]) by mx.google.com with ESMTPS id e6sm4710609pbr.74.2012.02.24.08.29.57 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 08:29:57 -0800 (PST) Received: by localhost (Postfix, from userid 1000) id 9CC5A3E0647; Fri, 24 Feb 2012 09:29:56 -0700 (MST) From: Grant Likely To: linux-kernel@vger.kernel.org Cc: Grant Likely , Ralf Baechle , Rob Herring , Thomas Gleixner , linux-mips@linux-mips.org Subject: [PATCH] irq_domain/mips: Allow irq_domain on MIPS Date: Fri, 24 Feb 2012 09:29:55 -0700 Message-Id: <1330100995-19823-1-git-send-email-grant.likely@secretlab.ca> X-Mailer: git-send-email 1.7.9 X-Gm-Message-State: ALoCoQnsGSN3cPtx7+vgIY7pbC8rZ4rx4U8EQcmTWBhe/MTuUfPheXvcbC7BFBDVS5gY5V9o0ONH X-archive-position: 32549 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3215 Lines: 107 This patch makes IRQ_DOMAIN usable on MIPS. It uses an ugly workaround to preserve current behaviour so that MIPS has time to add irq_domain registration to the irq controller drivers. The workaround will be removed in Linux v3.6 Signed-off-by: Grant Likely Cc: Ralf Baechle Cc: Rob Herring Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org --- This applies on top of linux-next or my irqdomain/next branch. Ralf, with your ack I should merge it via that tree. git://git.secretlab.ca/git/linux-2.6 irqdomain/next arch/mips/Kconfig | 1 + arch/mips/include/asm/irq.h | 5 +---- arch/mips/kernel/prom.c | 14 -------------- kernel/irq/irqdomain.c | 12 ++++++++++++ 4 files changed, 14 insertions(+), 18 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5ab6e89..edbbae1 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2327,6 +2327,7 @@ config USE_OF bool "Flattened Device Tree support" select OF select OF_EARLY_FLATTREE + select IRQ_DOMAIN help Include support for flattened device tree machine descriptions. diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index 2354c87..fb698dc 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -11,15 +11,12 @@ #include #include +#include #include #include -static inline void irq_dispose_mapping(unsigned int virq) -{ -} - #ifdef CONFIG_I8259 static inline int irq_canonicalize(int irq) { diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 6b8b420..558b539 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -60,20 +60,6 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start, } #endif -/* - * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# - * - * Currently the mapping mechanism is trivial; simple flat hwirq numbers are - * mapped 1:1 onto Linux irq numbers. Cascaded irq controllers are not - * supported. - */ -unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize) -{ - return intspec[0]; -} -EXPORT_SYMBOL_GPL(irq_create_of_mapping); - void __init early_init_devtree(void *params) { /* Setup flat device-tree pointer */ diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index 25a498e..af48e59 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -411,6 +411,18 @@ unsigned int irq_create_of_mapping(struct device_node *controller, domain = controller ? irq_find_host(controller) : irq_default_domain; if (!domain) { +#ifdef CONFIG_MIPS + /* + * Workaround to avoid breaking interrupt controller drivers + * that don't yet register an irq_domain. This is temporary + * code. ~~~gcl, Feb 24, 2012 + * + * Scheduled for removal in Linux v3.6. That should be enough + * time. + */ + if (intsize > 0) + return intspec[0]; +#endif printk(KERN_WARNING "irq: no irq domain found for %s !\n", controller->full_name); return 0; -- 1.7.9 From david.daney@cavium.com Fri Feb 24 18:21:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 18:21:46 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13803 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903760Ab2BXRVl (ORCPT ); Fri, 24 Feb 2012 18:21:41 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 24 Feb 2012 09:23:20 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 24 Feb 2012 09:21:37 -0800 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 24 Feb 2012 09:21:37 -0800 Message-ID: <4F47C720.6050503@cavium.com> Date: Fri, 24 Feb 2012 09:21:36 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Greg Kroah-Hartman CC: Florian Fainelli , David Daney , linux-mips@linux-mips.org, devel@driverdev.osuosl.org Subject: Re: [PATCH] staging/octeon: Fix PHY binding in octeon-ethernet driver. References: <1330024771-25396-1-git-send-email-ddaney.cavm@gmail.com> <4F47587D.5050303@openwrt.org> In-Reply-To: <4F47587D.5050303@openwrt.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 24 Feb 2012 17:21:37.0591 (UTC) FILETIME=[C3C19470:01CCF318] X-archive-position: 32550 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1533 Lines: 45 On 02/24/2012 01:29 AM, Florian Fainelli wrote: > Le 02/23/12 20:19, David Daney a écrit : >> From: David Daney >> >> Commit d6c25be (mdio-octeon: use an unique MDIO bus name.) changed the >> names used to refer to MDIO buses. The ethernet driver must be >> changed to match, so that the PHY drivers can be attached. >> >> Cc: Florian Fainelli >> Signed-off-by: David Daney > Acked-by: Florian Fainelli I would also add (and should have in the original post), that the commit causing the regression was merged for 3.3. So if possible, it would be nice to get this in before the final 3.3. Thanks, David Daney >> --- >> drivers/staging/octeon/ethernet-mdio.c | 4 ++-- >> 1 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/staging/octeon/ethernet-mdio.c >> b/drivers/staging/octeon/ethernet-mdio.c >> index 63800ba..e31949c 100644 >> --- a/drivers/staging/octeon/ethernet-mdio.c >> +++ b/drivers/staging/octeon/ethernet-mdio.c >> @@ -164,9 +164,9 @@ int cvm_oct_phy_setup_device(struct net_device *dev) >> >> int phy_addr = cvmx_helper_board_get_mii_address(priv->port); >> if (phy_addr != -1) { >> - char phy_id[20]; >> + char phy_id[MII_BUS_ID_SIZE + 3]; >> >> - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", phy_addr); >> + snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", >> phy_addr); >> >> priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0, >> PHY_INTERFACE_MODE_GMII); > > From mirqus@gmail.com Fri Feb 24 18:59:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Feb 2012 18:59:37 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:52406 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903759Ab2BXR7b convert rfc822-to-8bit (ORCPT ); Fri, 24 Feb 2012 18:59:31 +0100 Received: by iaky10 with SMTP id y10so1315821iak.36 for ; Fri, 24 Feb 2012 09:59:24 -0800 (PST) Received-SPF: pass (google.com: domain of mirqus@gmail.com designates 10.50.193.195 as permitted sender) client-ip=10.50.193.195; Authentication-Results: mr.google.com; spf=pass (google.com: domain of mirqus@gmail.com designates 10.50.193.195 as permitted sender) smtp.mail=mirqus@gmail.com; dkim=pass header.i=mirqus@gmail.com Received: from mr.google.com ([10.50.193.195]) by 10.50.193.195 with SMTP id hq3mr4667020igc.18.1330106364453 (num_hops = 1); Fri, 24 Feb 2012 09:59:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=HNn6H3hm4G/LuHJaxW51hiS54zqmUVFTWgoL8/Qwmp4=; b=uRweyO3pqeGxoxfdvseACLmdNBChiN19x/DDO3lfFzzkC4EHvlfgZClu3ED0MUHxSt 7crUfxu+uCPklEWZyUG9PVSYoVFz+4VfaBNEvTnjnXQgxZ7lplyVpX11gTcRpx5wNKLh TWLgXo2nKR4va2ROXG7Wd2IGRwoVUEpPi/2uc= Received: by 10.50.193.195 with SMTP id hq3mr3691367igc.18.1330106364352; Fri, 24 Feb 2012 09:59:24 -0800 (PST) MIME-Version: 1.0 Received: by 10.231.43.13 with HTTP; Fri, 24 Feb 2012 09:59:04 -0800 (PST) In-Reply-To: <1330099282-4588-1-git-send-email-danny.kukawka@bisect.de> References: <1330099282-4588-1-git-send-email-danny.kukawka@bisect.de> From: =?ISO-8859-2?Q?Micha=B3_Miros=B3aw?= Date: Fri, 24 Feb 2012 18:59:04 +0100 Message-ID: Subject: Re: [PATCH 00/12] Part 2: check given MAC address, if invalid return -EADDRNOTAVAIL To: Danny Kukawka Cc: "David S. Miller" , Andy Gospodarek , Guo-Fu Tseng , Petko Manolov , "VMware, Inc." , "John W. Linville" , linux390@de.ibm.com, Mauro Carvalho Chehab , Danny Kukawka , Stephen Hemminger , Joe Perches , Jeff Kirsher , Jiri Pirko , netdev@vger.kernel.org, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, libertas-dev@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-s390@vger.kernel.org, linux-hams@vger.kernel.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32551 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mirqus@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 524 Lines: 13 2012/2/24 Danny Kukawka : > Second Part of series patches to unifiy the return value of > .ndo_set_mac_address if the given address isn't valid. > > These changes check if a given (MAC) address is valid in > .ndo_set_mac_address, if invalid return -EADDRNOTAVAIL > as eth_mac_addr() already does if is_valid_ether_addr() fails. Why not just fix dev_set_mac_address() and make do_setlink() use that? Checks are specific to address family, not device model I assume. Best Regards, Michał Mirosław From geert@linux-m68k.org Sat Feb 25 11:13:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Feb 2012 11:13:30 +0100 (CET) Received: from mail-we0-f177.google.com ([74.125.82.177]:50779 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903679Ab2BYKN1 convert rfc822-to-8bit (ORCPT ); Sat, 25 Feb 2012 11:13:27 +0100 Received: by wera10 with SMTP id a10so2461953wer.36 for ; Sat, 25 Feb 2012 02:13:21 -0800 (PST) Received-SPF: pass (google.com: domain of geert.uytterhoeven@gmail.com designates 10.180.89.71 as permitted sender) client-ip=10.180.89.71; Authentication-Results: mr.google.com; spf=pass (google.com: domain of geert.uytterhoeven@gmail.com designates 10.180.89.71 as permitted sender) smtp.mail=geert.uytterhoeven@gmail.com; dkim=pass header.i=geert.uytterhoeven@gmail.com Received: from mr.google.com ([10.180.89.71]) by 10.180.89.71 with SMTP id bm7mr2946384wib.20.1330164801499 (num_hops = 1); Sat, 25 Feb 2012 02:13:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=FTo18kF83qd2ZDn8e2WM7/LVC5vCM7flxBkElmQKbL8=; b=Djb2cvWHDr0mB1R9I+E5VZYKvIB1jhAn+WYu1c3XJDMw1IizIe7b4ll5OhMRby8JUU RqKUYTXnDaqc6RjUbI1of85kTEaojeRmtzlASrjpv/8Oq+VEGxg20av4A+Dm+POK4yiH y/ZAd5eHhD/tB5D1BE88VS3R7aFvoe99lMeN8= MIME-Version: 1.0 Received: by 10.180.89.71 with SMTP id bm7mr2305867wib.20.1330164801383; Sat, 25 Feb 2012 02:13:21 -0800 (PST) Received: by 10.223.94.66 with HTTP; Sat, 25 Feb 2012 02:13:21 -0800 (PST) In-Reply-To: References: <1330099282-4588-1-git-send-email-danny.kukawka@bisect.de> Date: Sat, 25 Feb 2012 11:13:21 +0100 X-Google-Sender-Auth: 83VwX2zntM4V_D5Pq08rAC93pKU Message-ID: Subject: Re: [PATCH 00/12] Part 2: check given MAC address, if invalid return -EADDRNOTAVAIL From: Geert Uytterhoeven To: =?UTF-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= Cc: Danny Kukawka , "David S. Miller" , Andy Gospodarek , Guo-Fu Tseng , Petko Manolov , "VMware, Inc." , "John W. Linville" , linux390@de.ibm.com, Mauro Carvalho Chehab , Danny Kukawka , Stephen Hemminger , Joe Perches , Jeff Kirsher , Jiri Pirko , netdev@vger.kernel.org, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, libertas-dev@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-s390@vger.kernel.org, linux-hams@vger.kernel.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32552 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1165 Lines: 29 2012/2/24 Michał Mirosław : > 2012/2/24 Danny Kukawka : >> Second Part of series patches to unifiy the return value of >> .ndo_set_mac_address if the given address isn't valid. >> >> These changes check if a given (MAC) address is valid in >> .ndo_set_mac_address, if invalid return -EADDRNOTAVAIL >> as eth_mac_addr() already does if is_valid_ether_addr() fails. > > Why not just fix dev_set_mac_address() and make do_setlink() use that? BTW, it's also called from dev_set_mac_address(). > Checks are specific to address family, not device model I assume. Indeed, why can't this be done in one single place, instead of sprinkling these checks over all drivers, missing all out-of-tree (note: I don't care) and all soon-to-be-submitted drivers? Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.                                 -- Linus Torvalds From multiply@multiply.com Sun Feb 26 23:49:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 26 Feb 2012 23:49:21 +0100 (CET) Received: from px593-fe.multiply.com ([38.126.198.46]:58871 "EHLO px593-fe.Multiply.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903757Ab2BZWtR (ORCPT ); Sun, 26 Feb 2012 23:49:17 +0100 Received: from localhost.localdomain (ws503-fe.pn.pezarisdesign.com [38.126.199.153]) by px593-fe.Multiply.com (8.13.8/8.12.8) with ESMTP id q1QMn9Jq031055 for ; Sun, 26 Feb 2012 17:49:10 -0500 Message-Id: <201202262249.q1QMn9Jq031055@px593-fe.Multiply.com> Date: Sun, 26 Feb 2012 17:48:46 -0500 From: " heineken direction (via Multiply) " To: linux-mips@linux-mips.org Subject: An invitation to Multiply Reply-To: heineken direction MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 X-multiply-email-id: 1330296544##linux-mips@linux-mips.org##invitation X-Multiply-CampaignID: multiply-opa-120226 X-Multiply-Source: send-email-helper-text/plain X-archive-position: 32553 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: multiply@multiply.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1028 Lines: 36 Check out my Multiply site I set up a Multiply site with my pictures, videos and blog and I want to add you as my friend so you can see it. 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Copyright 2012 Multiply 6001 Park of Commerce Blvd, Boca Raton, FL From dennis.yxun@gmail.com Mon Feb 27 11:04:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 27 Feb 2012 11:04:39 +0100 (CET) Received: from mail-tul01m020-f177.google.com ([209.85.214.177]:33574 "EHLO mail-tul01m020-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901172Ab2B0KEf (ORCPT ); Mon, 27 Feb 2012 11:04:35 +0100 Received: by obcuz6 with SMTP id uz6so6202409obc.36 for ; Mon, 27 Feb 2012 02:04:29 -0800 (PST) Received-SPF: pass (google.com: domain of dennis.yxun@gmail.com designates 10.182.216.101 as permitted sender) client-ip=10.182.216.101; Authentication-Results: mr.google.com; spf=pass (google.com: domain of dennis.yxun@gmail.com designates 10.182.216.101 as permitted sender) smtp.mail=dennis.yxun@gmail.com; dkim=pass header.i=dennis.yxun@gmail.com Received: from mr.google.com ([10.182.216.101]) by 10.182.216.101 with SMTP id op5mr4609893obc.54.1330337069143 (num_hops = 1); Mon, 27 Feb 2012 02:04:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=mXoxL2GBjrcHD6mD5sMylTWgDDiYPkffcbLVEKgPfCE=; b=vJL2wTG7taoA+mP2RhRYkpDWe5EREAAZqCO8MIzBP2DnJI8qgcZ7UJmjb++bQRw9+D E157lYSd+BvlQcNxJ/6ES9DJ22/O2h9SXFUIsa5RWA9IrEDYNqwkGYdlnLbT1w704M4y bJbmxIE+Q56PJzD+Eb/bP2cb4FWLScNsxSD58= MIME-Version: 1.0 Received: by 10.182.216.101 with SMTP id op5mr4130930obc.54.1330337069090; Mon, 27 Feb 2012 02:04:29 -0800 (PST) Received: by 10.182.220.68 with HTTP; Mon, 27 Feb 2012 02:04:29 -0800 (PST) In-Reply-To: <4ED3483E.60204@gmail.com> References: <4ED3483E.60204@gmail.com> Date: Mon, 27 Feb 2012 18:04:29 +0800 Message-ID: Subject: Re: Using NFS with HIGHMEM support From: "Dennis.Yxun" To: Jacky Lam Cc: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=f46d0447864b6f46e604b9ef3c89 X-archive-position: 32554 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dennis.yxun@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2646 Lines: 69 --f46d0447864b6f46e604b9ef3c89 Content-Type: text/plain; charset=UTF-8 HI: I'm encountered pretty much the same problem here I'm tracing with current 3.3-rc4 branch(from ralf's tree) If I put rootfs at nand flash + highmem enabled, then execute problem may give illegal instruction error, bus error, try it again may run success. but if I don't enable highmem, then problem is gone. any hints? thanks Dennis On Mon, Nov 28, 2011 at 4:37 PM, Jacky Lam wrote: > Hi, > > I am using mips-linux-3.0.4 with HIGHMEM enabled. Everything is working > fine, but I find something strange that when I execute a statically-linked > binary through NFS mounted directory. It will gives me an illegal > instruction error or SIGSEGV. If I run it again, the binary can run > without problem. I have to reboot or drop all the vm cache in order to > reproduce the error again. > > Also, if I run the binary in harddisk or dynamically link the binary, no > problem will be found. > > Any suggestion to debug this problem? Thanks. > > Jacky > > --f46d0447864b6f46e604b9ef3c89 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable HI:
=C2=A0I'm encountered pretty much the same problem here
=C2= =A0I'm tracing with current 3.3-rc4 branch(from ralf's tree)
=C2= =A0If I put rootfs at nand flash + highmem enabled, then execute problem ma= y give
illegal instruction error, bus error, try it again may run succes= s.
=C2=A0but if I don't enable highmem, then problem is gone.
=C2=A0any= hints? thanks

Dennis

On Mon, Nov = 28, 2011 at 4:37 PM, Jacky Lam <lamshuyin@gmail.com> wrote:
Hi,

=C2=A0 =C2=A0I am using mips-linux-3.0.4 with HIGHMEM enabled. Everything = is working fine, but I find something strange that when I execute a statica= lly-linked binary through NFS mounted directory. It will gives me an illega= l instruction error or =C2=A0SIGSEGV. If I run it again, the binary can run= without problem. I have to reboot or drop all the vm cache in order to rep= roduce the error again.

=C2=A0 Also, if I run the binary in harddisk or dynamically link the binar= y, no problem will be found.

=C2=A0 =C2=A0Any suggestion to debug this problem? Thanks.

Jacky


--f46d0447864b6f46e604b9ef3c89-- From ddaney.cavm@gmail.com Mon Feb 27 23:19:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 27 Feb 2012 23:19:57 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:45944 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903775Ab2B0WTw (ORCPT ); Mon, 27 Feb 2012 23:19:52 +0100 Received: by ghbf11 with SMTP id f11so624220ghb.36 for ; Mon, 27 Feb 2012 14:19:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=v5+YM8hml6+i8Iax0JgTRrVxE1ZmxHQPlVPNMAQcZuw=; b=HnlQie5ii6rX3PKCubgaOothaW3keVKCe1XFfwsD21ECuz9QyShc2RmyGBef4mOtZI rk6s99mZlZPZsr2+Ool4RSsX8iCRc4Bvb0zg2HLXh+yG0lEvhwop+++h5XYl5WnH5Lgn CTVeQf0FwNcav25O1Bg4P9C1bB6Tt9EwI7bo0= Received: by 10.236.184.202 with SMTP id s50mr18036767yhm.86.1330381186227; Mon, 27 Feb 2012 14:19:46 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id b6sm25363579anc.3.2012.02.27.14.19.43 (version=SSLv3 cipher=OTHER); Mon, 27 Feb 2012 14:19:45 -0800 (PST) Message-ID: <4F4C017E.5040200@gmail.com> Date: Mon, 27 Feb 2012 14:19:42 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Venkatesh Pallipadi , Ralf Baechle CC: Rusty Russell , Tony Luck , "Srivatsa S. Bhat" , Andrew Morton , KOSAKI Motohiro , KOSAKI Motohiro , Mike Travis , "Paul E. McKenney" , "Rafael J. Wysocki" , Paul Gortmaker , linux-kernel@vger.kernel.org, Richard Kuo , linux-hexagon@vger.kernel.org, linux-mips@linux-mips.org, Jeff Dike , Richard Weinberger , user-mode-linux-devel@lists.sourceforge.net Subject: Re: [PATCH 2/3] mips: Avoid raw handling of cpu_possible_map/cpu_online_map References: <87wr7pbwbz.fsf@rustcorp.com.au> <1329259784-20592-1-git-send-email-venki@google.com> <1329259784-20592-3-git-send-email-venki@google.com> In-Reply-To: <1329259784-20592-3-git-send-email-venki@google.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32555 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5093 Lines: 153 On 02/14/2012 02:49 PM, Venkatesh Pallipadi wrote: > Use set_cpu_* and init_cpu_* variants instead. > > Signed-off-by: Venkatesh Pallipadi I came up with the same thing, so... Acked-by: David Daney Ralf: If you too were to Acknowledge the patch, we might get it merged. David Daney > --- > arch/mips/cavium-octeon/smp.c | 2 +- > arch/mips/kernel/smp.c | 4 ++-- > arch/mips/netlogic/xlr/smp.c | 4 ++-- > arch/mips/pmc-sierra/yosemite/smp.c | 4 ++-- > arch/mips/sgi-ip27/ip27-smp.c | 2 +- > arch/mips/sibyte/bcm1480/smp.c | 5 ++--- > arch/mips/sibyte/sb1250/smp.c | 5 ++--- > 7 files changed, 12 insertions(+), 14 deletions(-) > > diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c > index efcfff4..5cce09c 100644 > --- a/arch/mips/cavium-octeon/smp.c > +++ b/arch/mips/cavium-octeon/smp.c > @@ -268,7 +268,7 @@ static int octeon_cpu_disable(void) > > spin_lock(&smp_reserve_lock); > > - cpu_clear(cpu, cpu_online_map); > + set_cpu_online(cpu, false); > cpu_clear(cpu, cpu_callin_map); > local_irq_disable(); > fixup_irqs(); > diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c > index 32c1e95..28777ff 100644 > --- a/arch/mips/kernel/smp.c > +++ b/arch/mips/kernel/smp.c > @@ -148,7 +148,7 @@ static void stop_this_cpu(void *dummy) > /* > * Remove this CPU: > */ > - cpu_clear(smp_processor_id(), cpu_online_map); > + set_cpu_online(smp_processor_id(), false); > for (;;) { > if (cpu_wait) > (*cpu_wait)(); /* Wait if available. */ > @@ -248,7 +248,7 @@ int __cpuinit __cpu_up(unsigned int cpu) > while (!cpu_isset(cpu, cpu_callin_map)) > udelay(100); > > - cpu_set(cpu, cpu_online_map); > + set_cpu_online(cpu, true); > > return 0; > } > diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c > index 080284d..8084221 100644 > --- a/arch/mips/netlogic/xlr/smp.c > +++ b/arch/mips/netlogic/xlr/smp.c > @@ -154,7 +154,7 @@ void __init nlm_smp_setup(void) > cpu_set(boot_cpu, phys_cpu_present_map); > __cpu_number_map[boot_cpu] = 0; > __cpu_logical_map[0] = boot_cpu; > - cpu_set(0, cpu_possible_map); > + set_cpu_possible(0, true); > > num_cpus = 1; > for (i = 0; i< NR_CPUS; i++) { > @@ -166,7 +166,7 @@ void __init nlm_smp_setup(void) > cpu_set(i, phys_cpu_present_map); > __cpu_number_map[i] = num_cpus; > __cpu_logical_map[num_cpus] = i; > - cpu_set(num_cpus, cpu_possible_map); > + set_cpu_possible(num_cpus, true); > ++num_cpus; > } > } > diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c > index 2608752..b2b23eb 100644 > --- a/arch/mips/pmc-sierra/yosemite/smp.c > +++ b/arch/mips/pmc-sierra/yosemite/smp.c > @@ -155,10 +155,10 @@ static void __init yos_smp_setup(void) > { > int i; > > - cpus_clear(cpu_possible_map); > + init_cpu_possible(cpumask_of(0)); > > for (i = 0; i< 2; i++) { > - cpu_set(i, cpu_possible_map); > + set_cpu_possible(i, true); > __cpu_number_map[i] = i; > __cpu_logical_map[i] = i; > } > diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c > index c6851df..735b43b 100644 > --- a/arch/mips/sgi-ip27/ip27-smp.c > +++ b/arch/mips/sgi-ip27/ip27-smp.c > @@ -76,7 +76,7 @@ static int do_cpumask(cnodeid_t cnode, nasid_t nasid, int highest) > /* Only let it join in if it's marked enabled */ > if ((acpu->cpu_info.flags& KLINFO_ENABLE)&& > (tot_cpus_found != NR_CPUS)) { > - cpu_set(cpuid, cpu_possible_map); > + set_cpu_possible(cpuid, true); > alloc_cpupda(cpuid, tot_cpus_found); > cpus_found++; > tot_cpus_found++; > diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c > index d667875..63d2211 100644 > --- a/arch/mips/sibyte/bcm1480/smp.c > +++ b/arch/mips/sibyte/bcm1480/smp.c > @@ -147,14 +147,13 @@ static void __init bcm1480_smp_setup(void) > { > int i, num; > > - cpus_clear(cpu_possible_map); > - cpu_set(0, cpu_possible_map); > + init_cpu_possible(cpumask_of(0)); > __cpu_number_map[0] = 0; > __cpu_logical_map[0] = 0; > > for (i = 1, num = 0; i< NR_CPUS; i++) { > if (cfe_cpu_stop(i) == 0) { > - cpu_set(i, cpu_possible_map); > + set_cpu_possible(i, true); > __cpu_number_map[i] = ++num; > __cpu_logical_map[num] = i; > } > diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c > index 38e7f6b..77f0df5 100644 > --- a/arch/mips/sibyte/sb1250/smp.c > +++ b/arch/mips/sibyte/sb1250/smp.c > @@ -135,14 +135,13 @@ static void __init sb1250_smp_setup(void) > { > int i, num; > > - cpus_clear(cpu_possible_map); > - cpu_set(0, cpu_possible_map); > + init_cpu_possible(cpumask_of(0)); > __cpu_number_map[0] = 0; > __cpu_logical_map[0] = 0; > > for (i = 1, num = 0; i< NR_CPUS; i++) { > if (cfe_cpu_stop(i) == 0) { > - cpu_set(i, cpu_possible_map); > + set_cpu_possible(i, true); > __cpu_number_map[i] = ++num; > __cpu_logical_map[num] = i; > } From hauke@hauke-m.de Tue Feb 28 00:57:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 00:57:19 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58037 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903777Ab2B0X5M (ORCPT ); Tue, 28 Feb 2012 00:57:12 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 53A278F6C; Tue, 28 Feb 2012 00:57:11 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Mtvz13r4xg7J; Tue, 28 Feb 2012 00:56:57 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 752AB8F60; Tue, 28 Feb 2012 00:56:57 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 00/11] ssb/bcma/BCM47XX: sprom fixes and extensions Date: Tue, 28 Feb 2012 00:56:03 +0100 Message-Id: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32556 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2477 Lines: 57 This patch series fixes some errors in the sprom structures and extends it to contain members for all sprom values for sprom version 1 to 9. This was done by looking into the open source part of the Broadcom SDK. This also adds a fallback sprom registration method to bcma. It also contains some small fixes for the bcma47xx arch code and a rewrite of the code to provide the sprom from flash. It now also provides sprom from flash for devices using bcma to control the system bus. This patch series is based on wireles-testing. I think it is the best way to merge this through John's wireless tree as the changes in the sprom struct should be used in further patches extending the pci sprom parsing and the usage of struct sprom by the brcmsmac driver. @Ralf could you please give me your Ack on the patches touching arch/mips/ or say to me what you do not like at these patches or the others. v2: * fix drivers/ssb/pci.c:334:5: warning: unused variable 'gain' * rename ccode to alpha2 * typos * use switch in bcm47xx_get_sprom_bcma() Hauke Mehrtens (11): ssb: sprom fix some sizes / signedness ssb: remove 5GHz antenna gain from sprom ssb: fix per path sprom vars ssb: add alpha2 ssb: add some missing sprom attributes bcma: export bcma_find_core bcma: add support for sprom not found on the device MIPS: BCM47XX: return number of written bytes in nvram_getenv MIPS: BCM47XX: fix signature of nvram_parse_macaddr MIPS: BCM47XX: move and extend sprom parsing MIPS: BCM47XX: provide sprom to bcma bus arch/mips/bcm47xx/Makefile | 2 +- arch/mips/bcm47xx/nvram.c | 3 +- arch/mips/bcm47xx/setup.c | 188 ++------- arch/mips/bcm47xx/sprom.c | 620 ++++++++++++++++++++++++++ arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 3 + arch/mips/include/asm/mach-bcm47xx/nvram.h | 2 +- drivers/bcma/main.c | 3 +- drivers/bcma/sprom.c | 77 +++- drivers/net/wireless/b43legacy/phy.c | 2 +- drivers/ssb/pci.c | 41 +-- drivers/ssb/pcmcia.c | 12 +- drivers/ssb/sdio.c | 12 +- include/linux/bcma/bcma.h | 7 + include/linux/ssb/ssb.h | 102 ++++- 14 files changed, 848 insertions(+), 226 deletions(-) create mode 100644 arch/mips/bcm47xx/sprom.c -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:57:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 00:57:42 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58046 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903778Ab2B0X5N (ORCPT ); Tue, 28 Feb 2012 00:57:13 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 2272A8F60; Tue, 28 Feb 2012 00:57:13 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rG5P5LJ4Pagx; Tue, 28 Feb 2012 00:56:58 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 043008F61; Tue, 28 Feb 2012 00:56:57 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 01/11] ssb: sprom fix some sizes / signedness Date: Tue, 28 Feb 2012 00:56:04 +0100 Message-Id: <1330386974-4056-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32557 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2462 Lines: 58 Some parts of the sprom struct are bigger than needed. The leddc and maxpwr values are just 8 bit long and not 16. rxpo2g and rxpo5g are signed I got these information for the open source part of the Broadcom SDK covering sprom version 1 to 9. rxpo2g contained a negative number on my bcm5354 based device, this cased an error and Broadcom SDK says this is signed. Signed-off-by: Hauke Mehrtens --- include/linux/ssb/ssb.h | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index bbc2612..f169621 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -33,8 +33,8 @@ struct ssb_sprom { u8 et1mdcport; /* MDIO for enet1 */ u16 board_rev; /* Board revision number from SPROM. */ u8 country_code; /* Country Code */ - u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */ - u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */ u16 pa0b0; @@ -53,10 +53,10 @@ struct ssb_sprom { u8 gpio1; /* GPIO pin 1 */ u8 gpio2; /* GPIO pin 2 */ u8 gpio3; /* GPIO pin 3 */ - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ u8 itssi_a; /* Idle TSSI Target for A-PHY */ u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ u8 tri2g; /* 2.4GHz TX isolation */ @@ -67,8 +67,8 @@ struct ssb_sprom { u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ - u8 rxpo2g; /* 2GHz RX power offset */ - u8 rxpo5g; /* 5GHz RX power offset */ + s8 rxpo2g; /* 2GHz RX power offset */ + s8 rxpo5g; /* 5GHz RX power offset */ u8 rssisav2g; /* 2GHz RSSI params */ u8 rssismc2g; u8 rssismf2g; -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:57:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 00:58:09 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58065 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903780Ab2B0X50 (ORCPT ); Tue, 28 Feb 2012 00:57:26 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id DFDA68F6E; Tue, 28 Feb 2012 00:57:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VuaWbTEpDf-3; Tue, 28 Feb 2012 00:57:11 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 765D38F62; Tue, 28 Feb 2012 00:56:58 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 02/11] ssb: remove 5GHz antenna gain from sprom Date: Tue, 28 Feb 2012 00:56:05 +0100 Message-Id: <1330386974-4056-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32558 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6904 Lines: 174 There is no 2.4 GHz or 5GHz antenna gain stored in sprom. The sprom just stores the gain values for antenna 1 and 2 or 1 to 4 for more recent sprom versions. On old devices antenna 2 was used for 5 GHz wifi. Signed-off-by: Hauke Mehrtens --- drivers/net/wireless/b43legacy/phy.c | 2 +- drivers/ssb/pci.c | 41 +++++++++++---------------------- drivers/ssb/pcmcia.c | 12 +++------ drivers/ssb/sdio.c | 12 +++------ include/linux/ssb/ssb.h | 7 +----- 5 files changed, 24 insertions(+), 50 deletions(-) diff --git a/drivers/net/wireless/b43legacy/phy.c b/drivers/net/wireless/b43legacy/phy.c index 96faaef..9503341 100644 --- a/drivers/net/wireless/b43legacy/phy.c +++ b/drivers/net/wireless/b43legacy/phy.c @@ -1860,7 +1860,7 @@ void b43legacy_phy_xmitpower(struct b43legacy_wldev *dev) * which accounts for the factor of 4 */ #define REG_MAX_PWR 20 max_pwr = min(REG_MAX_PWR * 4 - - dev->dev->bus->sprom.antenna_gain.ghz24.a0 + - dev->dev->bus->sprom.antenna_gain.a0 - 0x6, max_pwr); /* find the desired power in Q5.2 - power_level is in dBm diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c index befa89e..ed41244 100644 --- a/drivers/ssb/pci.c +++ b/drivers/ssb/pci.c @@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) { int i; u16 v; - s8 gain; u16 loc[3]; if (out->revision == 3) /* rev 3 moved MAC */ @@ -390,20 +389,12 @@ static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); /* Extract the antenna gain values. */ - gain = r123_extract_antgain(out->revision, in, - SSB_SPROM1_AGAIN_BG, - SSB_SPROM1_AGAIN_BG_SHIFT); - out->antenna_gain.ghz24.a0 = gain; - out->antenna_gain.ghz24.a1 = gain; - out->antenna_gain.ghz24.a2 = gain; - out->antenna_gain.ghz24.a3 = gain; - gain = r123_extract_antgain(out->revision, in, - SSB_SPROM1_AGAIN_A, - SSB_SPROM1_AGAIN_A_SHIFT); - out->antenna_gain.ghz5.a0 = gain; - out->antenna_gain.ghz5.a1 = gain; - out->antenna_gain.ghz5.a2 = gain; - out->antenna_gain.ghz5.a3 = gain; + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_BG, + SSB_SPROM1_AGAIN_BG_SHIFT); + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_A, + SSB_SPROM1_AGAIN_A_SHIFT); } /* Revs 4 5 and 8 have partially shared layout */ @@ -504,16 +495,14 @@ static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) } /* Extract the antenna gain values. */ - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01, + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01, SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT); - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01, + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01, SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT); - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23, + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23, SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT); - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23, + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23, SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT); - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, - sizeof(out->antenna_gain.ghz5)); sprom_extract_r458(out, in); @@ -602,16 +591,14 @@ static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in) SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0); /* Extract the antenna gain values. */ - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01, + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01, SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT); - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01, + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01, SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT); - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23, + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23, SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT); - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23, + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23, SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT); - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, - sizeof(out->antenna_gain.ghz5)); /* Extract cores power info info */ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) { diff --git a/drivers/ssb/pcmcia.c b/drivers/ssb/pcmcia.c index c821c6b..fbafed5 100644 --- a/drivers/ssb/pcmcia.c +++ b/drivers/ssb/pcmcia.c @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev, case SSB_PCMCIA_CIS_ANTGAIN: GOTO_ERROR_ON(tuple->TupleDataLen != 2, "antg tpl size"); - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1]; - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1]; - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1]; - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1]; - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1]; - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1]; - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1]; - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1]; + sprom->antenna_gain.a0 = tuple->TupleData[1]; + sprom->antenna_gain.a1 = tuple->TupleData[1]; + sprom->antenna_gain.a2 = tuple->TupleData[1]; + sprom->antenna_gain.a3 = tuple->TupleData[1]; break; case SSB_PCMCIA_CIS_BFLAGS: GOTO_ERROR_ON((tuple->TupleDataLen != 3) && diff --git a/drivers/ssb/sdio.c b/drivers/ssb/sdio.c index 63fd709..b2d36f7 100644 --- a/drivers/ssb/sdio.c +++ b/drivers/ssb/sdio.c @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_bus *bus, case SSB_SDIO_CIS_ANTGAIN: GOTO_ERROR_ON(tuple->size != 2, "antg tpl size"); - sprom->antenna_gain.ghz24.a0 = tuple->data[1]; - sprom->antenna_gain.ghz24.a1 = tuple->data[1]; - sprom->antenna_gain.ghz24.a2 = tuple->data[1]; - sprom->antenna_gain.ghz24.a3 = tuple->data[1]; - sprom->antenna_gain.ghz5.a0 = tuple->data[1]; - sprom->antenna_gain.ghz5.a1 = tuple->data[1]; - sprom->antenna_gain.ghz5.a2 = tuple->data[1]; - sprom->antenna_gain.ghz5.a3 = tuple->data[1]; + sprom->antenna_gain.a0 = tuple->data[1]; + sprom->antenna_gain.a1 = tuple->data[1]; + sprom->antenna_gain.a2 = tuple->data[1]; + sprom->antenna_gain.a3 = tuple->data[1]; break; case SSB_SDIO_CIS_BFLAGS: GOTO_ERROR_ON((tuple->size != 3) && diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index f169621..1de5675 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -94,12 +94,7 @@ struct ssb_sprom { * on each band. Values in dBm/4 (Q5.2). Negative gain means the * loss in the connectors is bigger than the gain. */ struct { - struct { - s8 a0, a1, a2, a3; - } ghz24; /* 2.4GHz band */ - struct { - s8 a0, a1, a2, a3; - } ghz5; /* 5GHz band */ + s8 a0, a1, a2, a3; } antenna_gain; struct { -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:57:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 00:58:31 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58076 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903781Ab2B0X51 (ORCPT ); Tue, 28 Feb 2012 00:57:27 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id D2B828F62; Tue, 28 Feb 2012 00:57:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xxdnW+RTw3h2; Tue, 28 Feb 2012 00:57:13 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id DF6C08F63; Tue, 28 Feb 2012 00:56:58 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 03/11] ssb: fix per path sprom vars Date: Tue, 28 Feb 2012 00:56:06 +0100 Message-Id: <1330386974-4056-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32559 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 766 Lines: 25 On sprom version 4 and 5 there are 4 values for pa_2g, pa_5gl, pa_5g and pa_5gh, for sprom version 8 and 9 there are only 3. Make the per path sprom store also work for older sprom versions. Signed-off-by: Hauke Mehrtens --- include/linux/ssb/ssb.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 1de5675..4928419 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -19,7 +19,7 @@ struct ssb_driver; struct ssb_sprom_core_pwr_info { u8 itssi_2g, itssi_5g; u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh; - u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3]; + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4]; }; struct ssb_sprom { -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:57:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 00:58:55 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58088 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903777Ab2B0X5k (ORCPT ); Tue, 28 Feb 2012 00:57:40 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 4D7058F6C; Tue, 28 Feb 2012 00:57:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T2+Ne1wGt6UG; Tue, 28 Feb 2012 00:57:26 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 5BFDB8F64; Tue, 28 Feb 2012 00:56:59 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 04/11] ssb: add alpha2 Date: Tue, 28 Feb 2012 00:56:07 +0100 Message-Id: <1330386974-4056-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32560 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 791 Lines: 22 This member contains the country code encoded with two chars Signed-off-by: Hauke Mehrtens --- include/linux/ssb/ssb.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 4928419..d658de4 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -33,6 +33,7 @@ struct ssb_sprom { u8 et1mdcport; /* MDIO for enet1 */ u16 board_rev; /* Board revision number from SPROM. */ u8 country_code; /* Country Code */ + char alpha2[2]; /* Country Code as two chars like EU or US */ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:57:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 00:59:19 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58095 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903782Ab2B0X5m (ORCPT ); Tue, 28 Feb 2012 00:57:42 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 2C8408F64; Tue, 28 Feb 2012 00:57:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IEwGlarDPA67; Tue, 28 Feb 2012 00:57:27 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id D16F58F65; Tue, 28 Feb 2012 00:56:59 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 05/11] ssb: add some missing sprom attributes Date: Tue, 28 Feb 2012 00:56:08 +0100 Message-Id: <1330386974-4056-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32561 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2509 Lines: 106 This patch extends the sprom struct to contain all sprom attributes found in sprom version 1 to 9. This was done accordingly to the open source part of the Broadcom SDK. Signed-off-by: Hauke Mehrtens --- include/linux/ssb/ssb.h | 76 ++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 75 insertions(+), 1 deletions(-) diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index d658de4..d276831 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -32,6 +32,8 @@ struct ssb_sprom { u8 et0mdcport; /* MDIO for enet0 */ u8 et1mdcport; /* MDIO for enet1 */ u16 board_rev; /* Board revision number from SPROM. */ + u16 board_num; /* Board number from SPROM. */ + u16 board_type; /* Board type from SPROM. */ u8 country_code; /* Country Code */ char alpha2[2]; /* Country Code as two chars like EU or US */ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ @@ -107,7 +109,79 @@ struct ssb_sprom { } ghz5; } fem; - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */ + u16 mcs2gpo[8]; + u16 mcs5gpo[8]; + u16 mcs5glpo[8]; + u16 mcs5ghpo[8]; + u8 opo; + + u8 rxgainerr2ga[3]; + u8 rxgainerr5gla[3]; + u8 rxgainerr5gma[3]; + u8 rxgainerr5gha[3]; + u8 rxgainerr5gua[3]; + + u8 noiselvl2ga[3]; + u8 noiselvl5gla[3]; + u8 noiselvl5gma[3]; + u8 noiselvl5gha[3]; + u8 noiselvl5gua[3]; + + u8 regrev; + u8 txchain; + u8 rxchain; + u8 antswitch; + u16 cddpo; + u16 stbcpo; + u16 bw40po; + u16 bwduppo; + + u8 tempthresh; + u8 tempoffset; + u16 rawtempsense; + u8 measpower; + u8 tempsense_slope; + u8 tempcorrx; + u8 tempsense_option; + u8 freqoffset_corr; + u8 iqcal_swp_dis; + u8 hw_iqcal_en; + u8 elna2g; + u8 elna5g; + u8 phycal_tempdelta; + u8 temps_period; + u8 temps_hysteresis; + u8 measpower1; + u8 measpower2; + u8 pcieingress_war; + + /* power per rate from sromrev 9 */ + u16 cckbw202gpo; + u16 cckbw20ul2gpo; + u32 legofdmbw202gpo; + u32 legofdmbw20ul2gpo; + u32 legofdmbw205glpo; + u32 legofdmbw20ul5glpo; + u32 legofdmbw205gmpo; + u32 legofdmbw20ul5gmpo; + u32 legofdmbw205ghpo; + u32 legofdmbw20ul5ghpo; + u32 mcsbw202gpo; + u32 mcsbw20ul2gpo; + u32 mcsbw402gpo; + u32 mcsbw205glpo; + u32 mcsbw20ul5glpo; + u32 mcsbw405glpo; + u32 mcsbw205gmpo; + u32 mcsbw20ul5gmpo; + u32 mcsbw405gmpo; + u32 mcsbw205ghpo; + u32 mcsbw20ul5ghpo; + u32 mcsbw405ghpo; + u16 mcs32po; + u16 legofdm40duppo; + u8 sar2g; + u8 sar5g; }; /* Information about the PCB the circuitry is soldered on. */ -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:57:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 00:59:46 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58106 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903784Ab2B0X5x (ORCPT ); Tue, 28 Feb 2012 00:57:53 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 5E9DA8F6F; Tue, 28 Feb 2012 00:57:53 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T8SD4Ck-bKjh; Tue, 28 Feb 2012 00:57:40 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 7D23C8F66; Tue, 28 Feb 2012 00:57:00 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 06/11] bcma: export bcma_find_core Date: Tue, 28 Feb 2012 00:56:09 +0100 Message-Id: <1330386974-4056-7-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32562 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1497 Lines: 45 This function is needed by the bcm47xx arch code to get the number of the ieee80211 core. Signed-off-by: Hauke Mehrtens --- drivers/bcma/main.c | 3 ++- include/linux/bcma/bcma.h | 1 + 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c index b8379b9..7e138ec 100644 --- a/drivers/bcma/main.c +++ b/drivers/bcma/main.c @@ -61,7 +61,7 @@ static struct bus_type bcma_bus_type = { .dev_attrs = bcma_device_attrs, }; -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) { struct bcma_device *core; @@ -71,6 +71,7 @@ static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) } return NULL; } +EXPORT_SYMBOL_GPL(bcma_find_core); static void bcma_release_core_dev(struct device *dev) { diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index b9f65fb..46bbd08 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -284,6 +284,7 @@ static inline void bcma_maskset16(struct bcma_device *cc, bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set); } +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid); extern bool bcma_core_is_enabled(struct bcma_device *core); extern void bcma_core_disable(struct bcma_device *core, u32 flags); extern int bcma_core_enable(struct bcma_device *core, u32 flags); -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:57:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 01:00:11 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58115 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903785Ab2B0X5z (ORCPT ); Tue, 28 Feb 2012 00:57:55 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 930B68F66; Tue, 28 Feb 2012 00:57:55 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 19u65p44cl6t; Tue, 28 Feb 2012 00:57:42 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id E9C858F67; Tue, 28 Feb 2012 00:57:00 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 07/11] bcma: add support for sprom not found on the device Date: Tue, 28 Feb 2012 00:56:10 +0100 Message-Id: <1330386974-4056-8-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32563 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4315 Lines: 143 On SoCs the sprom is stored in the nvram in a special partition on the flash chip. The nvram contains the sprom for the main bus, but sometimes also for a pci devices using bcma. This patch makes it possible for the arch code to register a function to fetch the needed sprom from the nvram and provide it to the bcma code. Signed-off-by: Hauke Mehrtens --- drivers/bcma/sprom.c | 77 ++++++++++++++++++++++++++++++++++++++++----- include/linux/bcma/bcma.h | 6 +++ 2 files changed, 75 insertions(+), 8 deletions(-) diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c index ca77525..916ae25 100644 --- a/drivers/bcma/sprom.c +++ b/drivers/bcma/sprom.c @@ -2,6 +2,8 @@ * Broadcom specific AMBA * SPROM reading * + * Copyright 2011, 2012, Hauke Mehrtens + * * Licensed under the GNU/GPL. See COPYING for details. */ @@ -14,6 +16,45 @@ #include #include +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out); + +/** + * bcma_arch_register_fallback_sprom - Registers a method providing a + * fallback SPROM if no SPROM is found. + * + * @sprom_callback: The callback function. + * + * With this function the architecture implementation may register a + * callback handler which fills the SPROM data structure. The fallback is + * used for PCI based BCMA devices, where no valid SPROM can be found + * in the shadow registers and to provide the SPROM for SoCs where BCMA is + * to controll the system bus. + * + * This function is useful for weird architectures that have a half-assed + * BCMA device hardwired to their PCI bus. + * + * This function is available for architecture code, only. So it is not + * exported. + */ +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus, + struct ssb_sprom *out)) +{ + if (get_fallback_sprom) + return -EEXIST; + get_fallback_sprom = sprom_callback; + + return 0; +} + +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus, + struct ssb_sprom *out) +{ + if (!get_fallback_sprom) + return -ENOENT; + + return get_fallback_sprom(bus, out); +} + /************************************************** * R/W ops. **************************************************/ @@ -246,23 +287,43 @@ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom) SSB_SROM8_FEM_ANTSWLUT_SHIFT); } +static bool bcma_is_sprom_available(struct bcma_bus *bus) +{ + u32 sromctrl; + + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM)) + return false; + + if (bus->drv_cc.core->id.rev >= 32) { + sromctrl = bcma_read32(bus->drv_cc.core, BCMA_CC_SROM_CONTROL); + return sromctrl & BCMA_CC_SROM_CONTROL_PRESENT; + } + return true; +} + int bcma_sprom_get(struct bcma_bus *bus) { u16 offset; u16 *sprom; - u32 sromctrl; int err = 0; if (!bus->drv_cc.core) return -EOPNOTSUPP; - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM)) - return -ENOENT; - - if (bus->drv_cc.core->id.rev >= 32) { - sromctrl = bcma_read32(bus->drv_cc.core, BCMA_CC_SROM_CONTROL); - if (!(sromctrl & BCMA_CC_SROM_CONTROL_PRESENT)) - return -ENOENT; + if (!bcma_is_sprom_available(bus)) { + /* + * Maybe there is no SPROM on the device? + * Now we ask the arch code if there is some sprom + * available for this device in some other storage. + */ + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom); + if (err) { + pr_warn("Using fallback SPROM failed (err %d)\n", err); + } else { + pr_debug("Using SPROM revision %d provided by" + " platform.\n", bus->sprom.revision); + return 0; + } } sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 46bbd08..5af9a07 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -176,6 +176,12 @@ int __bcma_driver_register(struct bcma_driver *drv, struct module *owner); extern void bcma_driver_unregister(struct bcma_driver *drv); +/* Set a fallback SPROM. + * See kdoc at the function definition for complete documentation. */ +extern int bcma_arch_register_fallback_sprom( + int (*sprom_callback)(struct bcma_bus *bus, + struct ssb_sprom *out)); + struct bcma_bus { /* The MMIO area. */ void __iomem *mmio; -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:58:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 01:00:36 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58125 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903778Ab2B0X6G (ORCPT ); Tue, 28 Feb 2012 00:58:06 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 76D748F70; Tue, 28 Feb 2012 00:58:06 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QdaLVYy+u9QU; Tue, 28 Feb 2012 00:57:53 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 5E0B88F68; Tue, 28 Feb 2012 00:57:01 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 08/11] MIPS: BCM47XX: return number of written bytes in nvram_getenv Date: Tue, 28 Feb 2012 00:56:11 +0100 Message-Id: <1330386974-4056-9-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32564 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 636 Lines: 23 Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/nvram.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index a84e3bb..d43ceff 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -107,8 +107,7 @@ int nvram_getenv(char *name, char *val, size_t val_len) value = eq + 1; if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0) { - snprintf(val, val_len, "%s", value); - return 0; + return snprintf(val, val_len, "%s", value); } } return NVRAM_ERR_ENVNOTFOUND; -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:58:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 01:01:00 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58135 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903786Ab2B0X6J (ORCPT ); Tue, 28 Feb 2012 00:58:09 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 04DDA8F68; Tue, 28 Feb 2012 00:58:09 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ocnxs6D0-M8y; Tue, 28 Feb 2012 00:57:55 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id C87DC8F69; Tue, 28 Feb 2012 00:57:01 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 09/11] MIPS: BCM47XX: fix signature of nvram_parse_macaddr Date: Tue, 28 Feb 2012 00:56:12 +0100 Message-Id: <1330386974-4056-10-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32565 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 793 Lines: 23 Explicitly enforce an char array of 6 bytes for the mac address. Signed-off-by: Hauke Mehrtens --- arch/mips/include/asm/mach-bcm47xx/nvram.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h index 184d5ec..69ef3ef 100644 --- a/arch/mips/include/asm/mach-bcm47xx/nvram.h +++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h @@ -37,7 +37,7 @@ struct nvram_header { extern int nvram_getenv(char *name, char *val, size_t val_len); -static inline void nvram_parse_macaddr(char *buf, u8 *macaddr) +static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6]) { if (strchr(buf, ':')) sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:58:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 01:01:22 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58160 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903789Ab2B0X6X (ORCPT ); Tue, 28 Feb 2012 00:58:23 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id D6B7D8F70; Tue, 28 Feb 2012 00:58:22 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ChsnnePXQ03i; Tue, 28 Feb 2012 00:58:09 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id A78168F6B; Tue, 28 Feb 2012 00:57:02 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 11/11] MIPS: BCM47XX: provide sprom to bcma bus Date: Tue, 28 Feb 2012 00:56:14 +0100 Message-Id: <1330386974-4056-12-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32566 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3082 Lines: 94 On SoCs the sprom is often stored in nvram in the flashchip. This patch registers a sprom fallback callback handler in bcma and provides the sprom needed for this device. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/setup.c | 39 +++++++++++++++++++++++++++++++++++---- 1 files changed, 35 insertions(+), 4 deletions(-) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 6b0dacd..19780aa 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -3,7 +3,7 @@ * Copyright (C) 2006 Felix Fietkau * Copyright (C) 2006 Michael Buesch * Copyright (C) 2010 Waldemar Brodkorb - * Copyright (C) 2010-2011 Hauke Mehrtens + * Copyright (C) 2010-2012 Hauke Mehrtens * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -85,7 +85,7 @@ static void bcm47xx_machine_halt(void) } #ifdef CONFIG_BCM47XX_SSB -static int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +static int bcm47xx_get_sprom_ssb(struct ssb_bus *bus, struct ssb_sprom *out) { char prefix[10]; @@ -102,7 +102,7 @@ static int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) } static int bcm47xx_get_invariants(struct ssb_bus *bus, - struct ssb_init_invariants *iv) + struct ssb_init_invariants *iv) { char buf[20]; @@ -132,7 +132,7 @@ static void __init bcm47xx_register_ssb(void) char buf[100]; struct ssb_mipscore *mcore; - err = ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom); + err = ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom_ssb); if (err) printk(KERN_WARNING "bcm47xx: someone else already registered" " a ssb SPROM callback handler (err %d)\n", err); @@ -159,10 +159,41 @@ static void __init bcm47xx_register_ssb(void) #endif #ifdef CONFIG_BCM47XX_BCMA +static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out) +{ + char prefix[10]; + struct bcma_device *core; + + switch (bus->hosttype) { + case BCMA_HOSTTYPE_PCI: + snprintf(prefix, sizeof(prefix), "pci/%u/%u/", + bus->host_pci->bus->number + 1, + PCI_SLOT(bus->host_pci->devfn)); + bcm47xx_fill_sprom(out, prefix); + return 0; + case BCMA_HOSTTYPE_SOC: + bcm47xx_fill_sprom_ethernet(out, NULL); + core = bcma_find_core(bus, BCMA_CORE_80211); + if (core) { + snprintf(prefix, sizeof(prefix), "sb/%u/", + core->core_index); + bcm47xx_fill_sprom(out, prefix); + } + return 0; + default: + pr_warn("bcm47xx: unable to fill SPROM for given bustype.\n"); + return -EINVAL; + } +} + static void __init bcm47xx_register_bcma(void) { int err; + err = bcma_arch_register_fallback_sprom(&bcm47xx_get_sprom_bcma); + if (err) + pr_warn("bcm47xx: someone else already registered a bcma SPROM callback handler (err %d)\n", err); + err = bcma_host_soc_register(&bcm47xx_bus.bcma); if (err) panic("Failed to initialize BCMA bus (err %d)", err); -- 1.7.5.4 From hauke@hauke-m.de Tue Feb 28 00:58:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 01:01:50 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:58163 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903787Ab2B0X6Z (ORCPT ); Tue, 28 Feb 2012 00:58:25 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 6FD788F68; Tue, 28 Feb 2012 00:58:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mj-RAAS18XBn; Tue, 28 Feb 2012 00:58:06 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 407DC8F6A; Tue, 28 Feb 2012 00:57:02 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, arend@broadcom.com, m@bues.ch, ralf@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 10/11] MIPS: BCM47XX: move and extend sprom parsing Date: Tue, 28 Feb 2012 00:56:13 +0100 Message-Id: <1330386974-4056-11-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> References: <1330386974-4056-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32567 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 33691 Lines: 828 Move the sprom parsing from nvram into sprom.c. There are all values needed for sprom version 1 to 9 read from nvram and there are more sanity checks added. This is based on the sprom parsing in the open source part of the Broadcom SDK. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/Makefile | 2 +- arch/mips/bcm47xx/setup.c | 151 +------- arch/mips/bcm47xx/sprom.c | 620 ++++++++++++++++++++++++++ arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 3 + 4 files changed, 625 insertions(+), 151 deletions(-) create mode 100644 arch/mips/bcm47xx/sprom.c diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile index 4add173..4389de1 100644 --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile @@ -3,5 +3,5 @@ # under Linux. # -obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o +obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o sprom.o obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index aab6b0c..6b0dacd 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -85,156 +85,7 @@ static void bcm47xx_machine_halt(void) } #ifdef CONFIG_BCM47XX_SSB -#define READ_FROM_NVRAM(_outvar, name, buf) \ - if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\ - sprom->_outvar = simple_strtoul(buf, NULL, 0); - -#define READ_FROM_NVRAM2(_outvar, name1, name2, buf) \ - if (nvram_getprefix(prefix, name1, buf, sizeof(buf)) >= 0 || \ - nvram_getprefix(prefix, name2, buf, sizeof(buf)) >= 0)\ - sprom->_outvar = simple_strtoul(buf, NULL, 0); - -static inline int nvram_getprefix(const char *prefix, char *name, - char *buf, int len) -{ - if (prefix) { - char key[100]; - - snprintf(key, sizeof(key), "%s%s", prefix, name); - return nvram_getenv(key, buf, len); - } - - return nvram_getenv(name, buf, len); -} - -static u32 nvram_getu32(const char *name, char *buf, int len) -{ - int rv; - char key[100]; - u16 var0, var1; - - snprintf(key, sizeof(key), "%s0", name); - rv = nvram_getenv(key, buf, len); - /* return 0 here so this looks like unset */ - if (rv < 0) - return 0; - var0 = simple_strtoul(buf, NULL, 0); - - snprintf(key, sizeof(key), "%s1", name); - rv = nvram_getenv(key, buf, len); - if (rv < 0) - return 0; - var1 = simple_strtoul(buf, NULL, 0); - return var1 << 16 | var0; -} - -static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) -{ - char buf[100]; - u32 boardflags; - - memset(sprom, 0, sizeof(struct ssb_sprom)); - - sprom->revision = 1; /* Fallback: Old hardware does not define this. */ - READ_FROM_NVRAM(revision, "sromrev", buf); - if (nvram_getprefix(prefix, "il0macaddr", buf, sizeof(buf)) >= 0 || - nvram_getprefix(prefix, "macaddr", buf, sizeof(buf)) >= 0) - nvram_parse_macaddr(buf, sprom->il0mac); - if (nvram_getprefix(prefix, "et0macaddr", buf, sizeof(buf)) >= 0) - nvram_parse_macaddr(buf, sprom->et0mac); - if (nvram_getprefix(prefix, "et1macaddr", buf, sizeof(buf)) >= 0) - nvram_parse_macaddr(buf, sprom->et1mac); - READ_FROM_NVRAM(et0phyaddr, "et0phyaddr", buf); - READ_FROM_NVRAM(et1phyaddr, "et1phyaddr", buf); - READ_FROM_NVRAM(et0mdcport, "et0mdcport", buf); - READ_FROM_NVRAM(et1mdcport, "et1mdcport", buf); - READ_FROM_NVRAM(board_rev, "boardrev", buf); - READ_FROM_NVRAM(country_code, "ccode", buf); - READ_FROM_NVRAM(ant_available_a, "aa5g", buf); - READ_FROM_NVRAM(ant_available_bg, "aa2g", buf); - READ_FROM_NVRAM(pa0b0, "pa0b0", buf); - READ_FROM_NVRAM(pa0b1, "pa0b1", buf); - READ_FROM_NVRAM(pa0b2, "pa0b2", buf); - READ_FROM_NVRAM(pa1b0, "pa1b0", buf); - READ_FROM_NVRAM(pa1b1, "pa1b1", buf); - READ_FROM_NVRAM(pa1b2, "pa1b2", buf); - READ_FROM_NVRAM(pa1lob0, "pa1lob0", buf); - READ_FROM_NVRAM(pa1lob2, "pa1lob1", buf); - READ_FROM_NVRAM(pa1lob1, "pa1lob2", buf); - READ_FROM_NVRAM(pa1hib0, "pa1hib0", buf); - READ_FROM_NVRAM(pa1hib2, "pa1hib1", buf); - READ_FROM_NVRAM(pa1hib1, "pa1hib2", buf); - READ_FROM_NVRAM2(gpio0, "ledbh0", "wl0gpio0", buf); - READ_FROM_NVRAM2(gpio1, "ledbh1", "wl0gpio1", buf); - READ_FROM_NVRAM2(gpio2, "ledbh2", "wl0gpio2", buf); - READ_FROM_NVRAM2(gpio3, "ledbh3", "wl0gpio3", buf); - READ_FROM_NVRAM2(maxpwr_bg, "maxp2ga0", "pa0maxpwr", buf); - READ_FROM_NVRAM2(maxpwr_al, "maxp5gla0", "pa1lomaxpwr", buf); - READ_FROM_NVRAM2(maxpwr_a, "maxp5ga0", "pa1maxpwr", buf); - READ_FROM_NVRAM2(maxpwr_ah, "maxp5gha0", "pa1himaxpwr", buf); - READ_FROM_NVRAM2(itssi_bg, "itt5ga0", "pa0itssit", buf); - READ_FROM_NVRAM2(itssi_a, "itt2ga0", "pa1itssit", buf); - READ_FROM_NVRAM(tri2g, "tri2g", buf); - READ_FROM_NVRAM(tri5gl, "tri5gl", buf); - READ_FROM_NVRAM(tri5g, "tri5g", buf); - READ_FROM_NVRAM(tri5gh, "tri5gh", buf); - READ_FROM_NVRAM(txpid2g[0], "txpid2ga0", buf); - READ_FROM_NVRAM(txpid2g[1], "txpid2ga1", buf); - READ_FROM_NVRAM(txpid2g[2], "txpid2ga2", buf); - READ_FROM_NVRAM(txpid2g[3], "txpid2ga3", buf); - READ_FROM_NVRAM(txpid5g[0], "txpid5ga0", buf); - READ_FROM_NVRAM(txpid5g[1], "txpid5ga1", buf); - READ_FROM_NVRAM(txpid5g[2], "txpid5ga2", buf); - READ_FROM_NVRAM(txpid5g[3], "txpid5ga3", buf); - READ_FROM_NVRAM(txpid5gl[0], "txpid5gla0", buf); - READ_FROM_NVRAM(txpid5gl[1], "txpid5gla1", buf); - READ_FROM_NVRAM(txpid5gl[2], "txpid5gla2", buf); - READ_FROM_NVRAM(txpid5gl[3], "txpid5gla3", buf); - READ_FROM_NVRAM(txpid5gh[0], "txpid5gha0", buf); - READ_FROM_NVRAM(txpid5gh[1], "txpid5gha1", buf); - READ_FROM_NVRAM(txpid5gh[2], "txpid5gha2", buf); - READ_FROM_NVRAM(txpid5gh[3], "txpid5gha3", buf); - READ_FROM_NVRAM(rxpo2g, "rxpo2g", buf); - READ_FROM_NVRAM(rxpo5g, "rxpo5g", buf); - READ_FROM_NVRAM(rssisav2g, "rssisav2g", buf); - READ_FROM_NVRAM(rssismc2g, "rssismc2g", buf); - READ_FROM_NVRAM(rssismf2g, "rssismf2g", buf); - READ_FROM_NVRAM(bxa2g, "bxa2g", buf); - READ_FROM_NVRAM(rssisav5g, "rssisav5g", buf); - READ_FROM_NVRAM(rssismc5g, "rssismc5g", buf); - READ_FROM_NVRAM(rssismf5g, "rssismf5g", buf); - READ_FROM_NVRAM(bxa5g, "bxa5g", buf); - READ_FROM_NVRAM(cck2gpo, "cck2gpo", buf); - - sprom->ofdm2gpo = nvram_getu32("ofdm2gpo", buf, sizeof(buf)); - sprom->ofdm5glpo = nvram_getu32("ofdm5glpo", buf, sizeof(buf)); - sprom->ofdm5gpo = nvram_getu32("ofdm5gpo", buf, sizeof(buf)); - sprom->ofdm5ghpo = nvram_getu32("ofdm5ghpo", buf, sizeof(buf)); - - READ_FROM_NVRAM(antenna_gain.ghz24.a0, "ag0", buf); - READ_FROM_NVRAM(antenna_gain.ghz24.a1, "ag1", buf); - READ_FROM_NVRAM(antenna_gain.ghz24.a2, "ag2", buf); - READ_FROM_NVRAM(antenna_gain.ghz24.a3, "ag3", buf); - memcpy(&sprom->antenna_gain.ghz5, &sprom->antenna_gain.ghz24, - sizeof(sprom->antenna_gain.ghz5)); - - if (nvram_getprefix(prefix, "boardflags", buf, sizeof(buf)) >= 0) { - boardflags = simple_strtoul(buf, NULL, 0); - if (boardflags) { - sprom->boardflags_lo = (boardflags & 0x0000FFFFU); - sprom->boardflags_hi = (boardflags & 0xFFFF0000U) >> 16; - } - } - if (nvram_getprefix(prefix, "boardflags2", buf, sizeof(buf)) >= 0) { - boardflags = simple_strtoul(buf, NULL, 0); - if (boardflags) { - sprom->boardflags2_lo = (boardflags & 0x0000FFFFU); - sprom->boardflags2_hi = (boardflags & 0xFFFF0000U) >> 16; - } - } -} - -int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +static int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) { char prefix[10]; diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c new file mode 100644 index 0000000..5c8dcd2 --- /dev/null +++ b/arch/mips/bcm47xx/sprom.c @@ -0,0 +1,620 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2006 Michael Buesch + * Copyright (C) 2010 Waldemar Brodkorb + * Copyright (C) 2010-2012 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +static void create_key(const char *prefix, const char *postfix, + const char *name, char *buf, int len) +{ + if (prefix && postfix) + snprintf(buf, len, "%s%s%s", prefix, name, postfix); + else if (prefix) + snprintf(buf, len, "%s%s", prefix, name); + else if (postfix) + snprintf(buf, len, "%s%s", name, postfix); + else + snprintf(buf, len, "%s", name); +} + +#define NVRAM_READ_VAL(type) \ +static void nvram_read_ ## type (const char *prefix, \ + const char *postfix, const char *name, \ + type *val, type allset) \ +{ \ + char buf[100]; \ + char key[40]; \ + int err; \ + type var; \ + \ + create_key(prefix, postfix, name, key, sizeof(key)); \ + \ + err = nvram_getenv(key, buf, sizeof(buf)); \ + if (err < 0) \ + return; \ + err = kstrto ## type (buf, 0, &var); \ + if (err) { \ + pr_warn("can not parse nvram name %s with value %s" \ + " got %i", key, buf, err); \ + return; \ + } \ + if (allset && var == allset) \ + return; \ + *val = var; \ +} + +NVRAM_READ_VAL(u8) +NVRAM_READ_VAL(s8) +NVRAM_READ_VAL(u16) +NVRAM_READ_VAL(u32) + +#undef NVRAM_READ_VAL + +static void nvram_read_u32_2(const char *prefix, const char *name, + u16 *val_lo, u16 *val_hi) +{ + char buf[100]; + char key[40]; + int err; + u32 val; + + create_key(prefix, NULL, name, key, sizeof(key)); + + err = nvram_getenv(key, buf, sizeof(buf)); + if (err < 0) + return; + err = kstrtou32(buf, 0, &val); + if (err) { + pr_warn("can not parse nvram name %s with value %s got %i", + key, buf, err); + return; + } + *val_lo = (val & 0x0000FFFFU); + *val_hi = (val & 0xFFFF0000U) >> 16; +} + +static void nvram_read_leddc(const char *prefix, const char *name, + u8 *leddc_on_time, u8 *leddc_off_time) +{ + char buf[100]; + char key[40]; + int err; + u32 val; + + create_key(prefix, NULL, name, key, sizeof(key)); + + err = nvram_getenv(key, buf, sizeof(buf)); + if (err < 0) + return; + err = kstrtou32(buf, 0, &val); + if (err) { + pr_warn("can not parse nvram name %s with value %s got %i", + key, buf, err); + return; + } + + if (val == 0xffff || val == 0xffffffff) + return; + + *leddc_on_time = val & 0xff; + *leddc_off_time = (val >> 16) & 0xff; +} + +static void nvram_read_macaddr(const char *prefix, const char *name, + u8 (*val)[6]) +{ + char buf[100]; + char key[40]; + int err; + + create_key(prefix, NULL, name, key, sizeof(key)); + + err = nvram_getenv(key, buf, sizeof(buf)); + if (err < 0) + return; + nvram_parse_macaddr(buf, *val); +} + +static void nvram_read_alpha2(const char *prefix, const char *name, + char (*val)[2]) +{ + char buf[10]; + char key[40]; + int err; + + create_key(prefix, NULL, name, key, sizeof(key)); + + err = nvram_getenv(key, buf, sizeof(buf)); + if (err < 0) + return; + if (buf[0] == '0') + return; + if (strlen(buf) > 2) { + pr_warn("alpha2 is too long %s", buf); + return; + } + memcpy(val, buf, sizeof(val)); +} + +static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom, + const char *prefix) +{ + nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0); + nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0); + nvram_read_u8(prefix, NULL, "ledbh0", &sprom->gpio0, 0xff); + nvram_read_u8(prefix, NULL, "ledbh1", &sprom->gpio1, 0xff); + nvram_read_u8(prefix, NULL, "ledbh2", &sprom->gpio2, 0xff); + nvram_read_u8(prefix, NULL, "ledbh3", &sprom->gpio3, 0xff); + nvram_read_u8(prefix, NULL, "aa2g", &sprom->ant_available_bg, 0); + nvram_read_u8(prefix, NULL, "aa5g", &sprom->ant_available_a, 0); + nvram_read_s8(prefix, NULL, "ag0", &sprom->antenna_gain.a0, 0); + nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0); + nvram_read_alpha2(prefix, "ccode", &sprom->alpha2); +} + +static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom, + const char *prefix) +{ + nvram_read_u16(prefix, NULL, "pa0b0", &sprom->pa0b0, 0); + nvram_read_u16(prefix, NULL, "pa0b1", &sprom->pa0b1, 0); + nvram_read_u16(prefix, NULL, "pa0b2", &sprom->pa0b2, 0); + nvram_read_u8(prefix, NULL, "pa0itssit", &sprom->itssi_bg, 0); + nvram_read_u8(prefix, NULL, "pa0maxpwr", &sprom->maxpwr_bg, 0); + nvram_read_u16(prefix, NULL, "pa1b0", &sprom->pa1b0, 0); + nvram_read_u16(prefix, NULL, "pa1b1", &sprom->pa1b1, 0); + nvram_read_u16(prefix, NULL, "pa1b2", &sprom->pa1b2, 0); + nvram_read_u8(prefix, NULL, "pa1itssit", &sprom->itssi_a, 0); + nvram_read_u8(prefix, NULL, "pa1maxpwr", &sprom->maxpwr_a, 0); +} + +static void bcm47xx_fill_sprom_r1(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u16(prefix, NULL, "boardflags", &sprom->boardflags_lo, 0); + nvram_read_u8(prefix, NULL, "cc", &sprom->country_code, 0); +} + +static void bcm47xx_fill_sprom_r2389(struct ssb_sprom *sprom, + const char *prefix) +{ + nvram_read_u8(prefix, NULL, "opo", &sprom->opo, 0); + nvram_read_u16(prefix, NULL, "pa1lob0", &sprom->pa1lob0, 0); + nvram_read_u16(prefix, NULL, "pa1lob1", &sprom->pa1lob1, 0); + nvram_read_u16(prefix, NULL, "pa1lob2", &sprom->pa1lob2, 0); + nvram_read_u16(prefix, NULL, "pa1hib0", &sprom->pa1hib0, 0); + nvram_read_u16(prefix, NULL, "pa1hib1", &sprom->pa1hib1, 0); + nvram_read_u16(prefix, NULL, "pa1hib2", &sprom->pa1hib2, 0); + nvram_read_u8(prefix, NULL, "pa1lomaxpwr", &sprom->maxpwr_al, 0); + nvram_read_u8(prefix, NULL, "pa1himaxpwr", &sprom->maxpwr_ah, 0); +} + +static void bcm47xx_fill_sprom_r2(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, + &sprom->boardflags_hi); + nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0); +} + +static void bcm47xx_fill_sprom_r389(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u8(prefix, NULL, "bxa2g", &sprom->bxa2g, 0); + nvram_read_u8(prefix, NULL, "rssisav2g", &sprom->rssisav2g, 0); + nvram_read_u8(prefix, NULL, "rssismc2g", &sprom->rssismc2g, 0); + nvram_read_u8(prefix, NULL, "rssismf2g", &sprom->rssismf2g, 0); + nvram_read_u8(prefix, NULL, "bxa5g", &sprom->bxa5g, 0); + nvram_read_u8(prefix, NULL, "rssisav5g", &sprom->rssisav5g, 0); + nvram_read_u8(prefix, NULL, "rssismc5g", &sprom->rssismc5g, 0); + nvram_read_u8(prefix, NULL, "rssismf5g", &sprom->rssismf5g, 0); + nvram_read_u8(prefix, NULL, "tri2g", &sprom->tri2g, 0); + nvram_read_u8(prefix, NULL, "tri5g", &sprom->tri5g, 0); + nvram_read_u8(prefix, NULL, "tri5gl", &sprom->tri5gl, 0); + nvram_read_u8(prefix, NULL, "tri5gh", &sprom->tri5gh, 0); + nvram_read_s8(prefix, NULL, "rxpo2g", &sprom->rxpo2g, 0); + nvram_read_s8(prefix, NULL, "rxpo5g", &sprom->rxpo5g, 0); +} + +static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, + &sprom->boardflags_hi); + nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0); + nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0); + nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time, + &sprom->leddc_off_time); +} + +static void bcm47xx_fill_sprom_r4589(struct ssb_sprom *sprom, + const char *prefix) +{ + nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, + &sprom->boardflags_hi); + nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo, + &sprom->boardflags2_hi); + nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0); + nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0); + nvram_read_s8(prefix, NULL, "ag2", &sprom->antenna_gain.a2, 0); + nvram_read_s8(prefix, NULL, "ag3", &sprom->antenna_gain.a3, 0); + nvram_read_u8(prefix, NULL, "txchain", &sprom->txchain, 0xf); + nvram_read_u8(prefix, NULL, "rxchain", &sprom->rxchain, 0xf); + nvram_read_u8(prefix, NULL, "antswitch", &sprom->antswitch, 0xff); + nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time, + &sprom->leddc_off_time); +} + +static void bcm47xx_fill_sprom_r458(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u16(prefix, NULL, "cck2gpo", &sprom->cck2gpo, 0); + nvram_read_u32(prefix, NULL, "ofdm2gpo", &sprom->ofdm2gpo, 0); + nvram_read_u32(prefix, NULL, "ofdm5gpo", &sprom->ofdm5gpo, 0); + nvram_read_u32(prefix, NULL, "ofdm5glpo", &sprom->ofdm5glpo, 0); + nvram_read_u32(prefix, NULL, "ofdm5ghpo", &sprom->ofdm5ghpo, 0); + nvram_read_u16(prefix, NULL, "cddpo", &sprom->cddpo, 0); + nvram_read_u16(prefix, NULL, "stbcpo", &sprom->stbcpo, 0); + nvram_read_u16(prefix, NULL, "bw40po", &sprom->bw40po, 0); + nvram_read_u16(prefix, NULL, "bwduppo", &sprom->bwduppo, 0); + nvram_read_u16(prefix, NULL, "mcs2gpo0", &sprom->mcs2gpo[0], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo1", &sprom->mcs2gpo[1], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo2", &sprom->mcs2gpo[2], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo3", &sprom->mcs2gpo[3], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo4", &sprom->mcs2gpo[4], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo5", &sprom->mcs2gpo[5], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo6", &sprom->mcs2gpo[6], 0); + nvram_read_u16(prefix, NULL, "mcs2gpo7", &sprom->mcs2gpo[7], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo0", &sprom->mcs5gpo[0], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo1", &sprom->mcs5gpo[1], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo2", &sprom->mcs5gpo[2], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo3", &sprom->mcs5gpo[3], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo4", &sprom->mcs5gpo[4], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo5", &sprom->mcs5gpo[5], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo6", &sprom->mcs5gpo[6], 0); + nvram_read_u16(prefix, NULL, "mcs5gpo7", &sprom->mcs5gpo[7], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo0", &sprom->mcs5glpo[0], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo1", &sprom->mcs5glpo[1], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo2", &sprom->mcs5glpo[2], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo3", &sprom->mcs5glpo[3], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo4", &sprom->mcs5glpo[4], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo5", &sprom->mcs5glpo[5], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo6", &sprom->mcs5glpo[6], 0); + nvram_read_u16(prefix, NULL, "mcs5glpo7", &sprom->mcs5glpo[7], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo0", &sprom->mcs5ghpo[0], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo1", &sprom->mcs5ghpo[1], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo2", &sprom->mcs5ghpo[2], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo3", &sprom->mcs5ghpo[3], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo4", &sprom->mcs5ghpo[4], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo5", &sprom->mcs5ghpo[5], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo6", &sprom->mcs5ghpo[6], 0); + nvram_read_u16(prefix, NULL, "mcs5ghpo7", &sprom->mcs5ghpo[7], 0); +} + +static void bcm47xx_fill_sprom_r45(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u8(prefix, NULL, "txpid2ga0", &sprom->txpid2g[0], 0); + nvram_read_u8(prefix, NULL, "txpid2ga1", &sprom->txpid2g[1], 0); + nvram_read_u8(prefix, NULL, "txpid2ga2", &sprom->txpid2g[2], 0); + nvram_read_u8(prefix, NULL, "txpid2ga3", &sprom->txpid2g[3], 0); + nvram_read_u8(prefix, NULL, "txpid5ga0", &sprom->txpid5g[0], 0); + nvram_read_u8(prefix, NULL, "txpid5ga1", &sprom->txpid5g[1], 0); + nvram_read_u8(prefix, NULL, "txpid5ga2", &sprom->txpid5g[2], 0); + nvram_read_u8(prefix, NULL, "txpid5ga3", &sprom->txpid5g[3], 0); + nvram_read_u8(prefix, NULL, "txpid5gla0", &sprom->txpid5gl[0], 0); + nvram_read_u8(prefix, NULL, "txpid5gla1", &sprom->txpid5gl[1], 0); + nvram_read_u8(prefix, NULL, "txpid5gla2", &sprom->txpid5gl[2], 0); + nvram_read_u8(prefix, NULL, "txpid5gla3", &sprom->txpid5gl[3], 0); + nvram_read_u8(prefix, NULL, "txpid5gha0", &sprom->txpid5gh[0], 0); + nvram_read_u8(prefix, NULL, "txpid5gha1", &sprom->txpid5gh[1], 0); + nvram_read_u8(prefix, NULL, "txpid5gha2", &sprom->txpid5gh[2], 0); + nvram_read_u8(prefix, NULL, "txpid5gha3", &sprom->txpid5gh[3], 0); +} + +static void bcm47xx_fill_sprom_r89(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u8(prefix, NULL, "tssipos2g", &sprom->fem.ghz2.tssipos, 0); + nvram_read_u8(prefix, NULL, "extpagain2g", + &sprom->fem.ghz2.extpa_gain, 0); + nvram_read_u8(prefix, NULL, "pdetrange2g", + &sprom->fem.ghz2.pdet_range, 0); + nvram_read_u8(prefix, NULL, "triso2g", &sprom->fem.ghz2.tr_iso, 0); + nvram_read_u8(prefix, NULL, "antswctl2g", &sprom->fem.ghz2.antswlut, 0); + nvram_read_u8(prefix, NULL, "tssipos5g", &sprom->fem.ghz5.tssipos, 0); + nvram_read_u8(prefix, NULL, "extpagain5g", + &sprom->fem.ghz5.extpa_gain, 0); + nvram_read_u8(prefix, NULL, "pdetrange5g", + &sprom->fem.ghz5.pdet_range, 0); + nvram_read_u8(prefix, NULL, "triso5g", &sprom->fem.ghz5.tr_iso, 0); + nvram_read_u8(prefix, NULL, "antswctl5g", &sprom->fem.ghz5.antswlut, 0); + nvram_read_u8(prefix, NULL, "tempthresh", &sprom->tempthresh, 0); + nvram_read_u8(prefix, NULL, "tempoffset", &sprom->tempoffset, 0); + nvram_read_u16(prefix, NULL, "rawtempsense", &sprom->rawtempsense, 0); + nvram_read_u8(prefix, NULL, "measpower", &sprom->measpower, 0); + nvram_read_u8(prefix, NULL, "tempsense_slope", + &sprom->tempsense_slope, 0); + nvram_read_u8(prefix, NULL, "tempcorrx", &sprom->tempcorrx, 0); + nvram_read_u8(prefix, NULL, "tempsense_option", + &sprom->tempsense_option, 0); + nvram_read_u8(prefix, NULL, "freqoffset_corr", + &sprom->freqoffset_corr, 0); + nvram_read_u8(prefix, NULL, "iqcal_swp_dis", &sprom->iqcal_swp_dis, 0); + nvram_read_u8(prefix, NULL, "hw_iqcal_en", &sprom->hw_iqcal_en, 0); + nvram_read_u8(prefix, NULL, "elna2g", &sprom->elna2g, 0); + nvram_read_u8(prefix, NULL, "elna5g", &sprom->elna5g, 0); + nvram_read_u8(prefix, NULL, "phycal_tempdelta", + &sprom->phycal_tempdelta, 0); + nvram_read_u8(prefix, NULL, "temps_period", &sprom->temps_period, 0); + nvram_read_u8(prefix, NULL, "temps_hysteresis", + &sprom->temps_hysteresis, 0); + nvram_read_u8(prefix, NULL, "measpower1", &sprom->measpower1, 0); + nvram_read_u8(prefix, NULL, "measpower2", &sprom->measpower2, 0); + nvram_read_u8(prefix, NULL, "rxgainerr2ga0", + &sprom->rxgainerr2ga[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr2ga1", + &sprom->rxgainerr2ga[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr2ga2", + &sprom->rxgainerr2ga[2], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gla0", + &sprom->rxgainerr5gla[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gla1", + &sprom->rxgainerr5gla[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gla2", + &sprom->rxgainerr5gla[2], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gma0", + &sprom->rxgainerr5gma[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gma1", + &sprom->rxgainerr5gma[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gma2", + &sprom->rxgainerr5gma[2], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gha0", + &sprom->rxgainerr5gha[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gha1", + &sprom->rxgainerr5gha[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gha2", + &sprom->rxgainerr5gha[2], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gua0", + &sprom->rxgainerr5gua[0], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gua1", + &sprom->rxgainerr5gua[1], 0); + nvram_read_u8(prefix, NULL, "rxgainerr5gua2", + &sprom->rxgainerr5gua[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl2ga0", &sprom->noiselvl2ga[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl2ga1", &sprom->noiselvl2ga[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl2ga2", &sprom->noiselvl2ga[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gla0", + &sprom->noiselvl5gla[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gla1", + &sprom->noiselvl5gla[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gla2", + &sprom->noiselvl5gla[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gma0", + &sprom->noiselvl5gma[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gma1", + &sprom->noiselvl5gma[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gma2", + &sprom->noiselvl5gma[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gha0", + &sprom->noiselvl5gha[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gha1", + &sprom->noiselvl5gha[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gha2", + &sprom->noiselvl5gha[2], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gua0", + &sprom->noiselvl5gua[0], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gua1", + &sprom->noiselvl5gua[1], 0); + nvram_read_u8(prefix, NULL, "noiselvl5gua2", + &sprom->noiselvl5gua[2], 0); + nvram_read_u8(prefix, NULL, "pcieingress_war", + &sprom->pcieingress_war, 0); +} + +static void bcm47xx_fill_sprom_r9(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_u16(prefix, NULL, "cckbw202gpo", &sprom->cckbw202gpo, 0); + nvram_read_u16(prefix, NULL, "cckbw20ul2gpo", &sprom->cckbw20ul2gpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw202gpo", + &sprom->legofdmbw202gpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw20ul2gpo", + &sprom->legofdmbw20ul2gpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw205glpo", + &sprom->legofdmbw205glpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw20ul5glpo", + &sprom->legofdmbw20ul5glpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw205gmpo", + &sprom->legofdmbw205gmpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw20ul5gmpo", + &sprom->legofdmbw20ul5gmpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw205ghpo", + &sprom->legofdmbw205ghpo, 0); + nvram_read_u32(prefix, NULL, "legofdmbw20ul5ghpo", + &sprom->legofdmbw20ul5ghpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw202gpo", &sprom->mcsbw202gpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw20ul2gpo", &sprom->mcsbw20ul2gpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw402gpo", &sprom->mcsbw402gpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw205glpo", &sprom->mcsbw205glpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw20ul5glpo", + &sprom->mcsbw20ul5glpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw405glpo", &sprom->mcsbw405glpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw205gmpo", &sprom->mcsbw205gmpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw20ul5gmpo", + &sprom->mcsbw20ul5gmpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw405gmpo", &sprom->mcsbw405gmpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw205ghpo", &sprom->mcsbw205ghpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw20ul5ghpo", + &sprom->mcsbw20ul5ghpo, 0); + nvram_read_u32(prefix, NULL, "mcsbw405ghpo", &sprom->mcsbw405ghpo, 0); + nvram_read_u16(prefix, NULL, "mcs32po", &sprom->mcs32po, 0); + nvram_read_u16(prefix, NULL, "legofdm40duppo", + &sprom->legofdm40duppo, 0); + nvram_read_u8(prefix, NULL, "sar2g", &sprom->sar2g, 0); + nvram_read_u8(prefix, NULL, "sar5g", &sprom->sar5g, 0); +} + +static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom, + const char *prefix) +{ + char postfix[2]; + int i; + + for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) { + struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i]; + snprintf(postfix, sizeof(postfix), "%i", i); + nvram_read_u8(prefix, postfix, "maxp2ga", + &pwr_info->maxpwr_2g, 0); + nvram_read_u8(prefix, postfix, "itt2ga", + &pwr_info->itssi_2g, 0); + nvram_read_u8(prefix, postfix, "itt5ga", + &pwr_info->itssi_5g, 0); + nvram_read_u16(prefix, postfix, "pa2gw0a", + &pwr_info->pa_2g[0], 0); + nvram_read_u16(prefix, postfix, "pa2gw1a", + &pwr_info->pa_2g[1], 0); + nvram_read_u16(prefix, postfix, "pa2gw2a", + &pwr_info->pa_2g[2], 0); + nvram_read_u8(prefix, postfix, "maxp5ga", + &pwr_info->maxpwr_5g, 0); + nvram_read_u8(prefix, postfix, "maxp5gha", + &pwr_info->maxpwr_5gh, 0); + nvram_read_u8(prefix, postfix, "maxp5gla", + &pwr_info->maxpwr_5gl, 0); + nvram_read_u16(prefix, postfix, "pa5gw0a", + &pwr_info->pa_5g[0], 0); + nvram_read_u16(prefix, postfix, "pa5gw1a", + &pwr_info->pa_5g[1], 0); + nvram_read_u16(prefix, postfix, "pa5gw2a", + &pwr_info->pa_5g[2], 0); + nvram_read_u16(prefix, postfix, "pa5glw0a", + &pwr_info->pa_5gl[0], 0); + nvram_read_u16(prefix, postfix, "pa5glw1a", + &pwr_info->pa_5gl[1], 0); + nvram_read_u16(prefix, postfix, "pa5glw2a", + &pwr_info->pa_5gl[2], 0); + nvram_read_u16(prefix, postfix, "pa5ghw0a", + &pwr_info->pa_5gh[0], 0); + nvram_read_u16(prefix, postfix, "pa5ghw1a", + &pwr_info->pa_5gh[1], 0); + nvram_read_u16(prefix, postfix, "pa5ghw2a", + &pwr_info->pa_5gh[2], 0); + } +} + +static void bcm47xx_fill_sprom_path_r45(struct ssb_sprom *sprom, + const char *prefix) +{ + char postfix[2]; + int i; + + for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) { + struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i]; + snprintf(postfix, sizeof(postfix), "%i", i); + nvram_read_u16(prefix, postfix, "pa2gw3a", + &pwr_info->pa_2g[3], 0); + nvram_read_u16(prefix, postfix, "pa5gw3a", + &pwr_info->pa_5g[3], 0); + nvram_read_u16(prefix, postfix, "pa5glw3a", + &pwr_info->pa_5gl[3], 0); + nvram_read_u16(prefix, postfix, "pa5ghw3a", + &pwr_info->pa_5gh[3], 0); + } +} + +void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, const char *prefix) +{ + nvram_read_macaddr(prefix, "et0macaddr", &sprom->et0mac); + nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0); + nvram_read_u8(prefix, NULL, "et0phyaddr", &sprom->et0phyaddr, 0); + + nvram_read_macaddr(prefix, "et1macaddr", &sprom->et1mac); + nvram_read_u8(prefix, NULL, "et1mdcport", &sprom->et1mdcport, 0); + nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0); + + nvram_read_macaddr(prefix, "macaddr", &sprom->il0mac); + nvram_read_macaddr(prefix, "il0macaddr", &sprom->il0mac); +} + +void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) +{ + memset(sprom, 0, sizeof(struct ssb_sprom)); + + bcm47xx_fill_sprom_ethernet(sprom, prefix); + + nvram_read_u8(prefix, NULL, "sromrev", &sprom->revision, 0); + + switch (sprom->revision) { + case 1: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r1(sprom, prefix); + break; + case 2: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r2389(sprom, prefix); + bcm47xx_fill_sprom_r2(sprom, prefix); + break; + case 3: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r2389(sprom, prefix); + bcm47xx_fill_sprom_r389(sprom, prefix); + bcm47xx_fill_sprom_r3(sprom, prefix); + break; + case 4: + case 5: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r4589(sprom, prefix); + bcm47xx_fill_sprom_r458(sprom, prefix); + bcm47xx_fill_sprom_r45(sprom, prefix); + bcm47xx_fill_sprom_path_r4589(sprom, prefix); + bcm47xx_fill_sprom_path_r45(sprom, prefix); + break; + case 8: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r2389(sprom, prefix); + bcm47xx_fill_sprom_r389(sprom, prefix); + bcm47xx_fill_sprom_r4589(sprom, prefix); + bcm47xx_fill_sprom_r458(sprom, prefix); + bcm47xx_fill_sprom_r89(sprom, prefix); + bcm47xx_fill_sprom_path_r4589(sprom, prefix); + break; + case 9: + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r2389(sprom, prefix); + bcm47xx_fill_sprom_r389(sprom, prefix); + bcm47xx_fill_sprom_r4589(sprom, prefix); + bcm47xx_fill_sprom_r89(sprom, prefix); + bcm47xx_fill_sprom_r9(sprom, prefix); + bcm47xx_fill_sprom_path_r4589(sprom, prefix); + break; + default: + pr_warn("Unsupported SPROM revision %d detected. Will extract" + " v1\n", sprom->revision); + sprom->revision = 1; + bcm47xx_fill_sprom_r1234589(sprom, prefix); + bcm47xx_fill_sprom_r12389(sprom, prefix); + bcm47xx_fill_sprom_r1(sprom, prefix); + } +} diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h index de95e07..5ecaf47 100644 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h @@ -44,4 +44,7 @@ union bcm47xx_bus { extern union bcm47xx_bus bcm47xx_bus; extern enum bcm47xx_bus_type bcm47xx_bus_type; +void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix); +void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, const char *prefix); + #endif /* __ASM_BCM47XX_H */ -- 1.7.5.4 From dennis.yxun@gmail.com Tue Feb 28 04:03:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 04:03:17 +0100 (CET) Received: from mail-tul01m020-f177.google.com ([209.85.214.177]:63680 "EHLO mail-tul01m020-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903774Ab2B1DDJ (ORCPT ); Tue, 28 Feb 2012 04:03:09 +0100 Received: by obcuz6 with SMTP id uz6so7520503obc.36 for ; Mon, 27 Feb 2012 19:03:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=uRGxvOeQhK9Q9dDkJO58lrpWHx+c0JyUYLCVs6WTMvg=; b=uzuMwhIN9ogs94PD34ZtxKshm2NVksdBgW6FANbbJN6koR+jscLQx93wnRcGluya+C HEFc8A33jsdQadAZhjTxASTOgp9VYvcFZ7PacIr9RrFDMUuzpo74AhVjWbe/WmO33Gy0 a83FxNFcaq+W9kwQsbi5veniWy6lifIhIyn7A= MIME-Version: 1.0 Received: by 10.182.38.7 with SMTP id c7mr5319418obk.44.1330398182673; Mon, 27 Feb 2012 19:03:02 -0800 (PST) Received: by 10.182.220.68 with HTTP; Mon, 27 Feb 2012 19:03:02 -0800 (PST) In-Reply-To: References: <28c262361003230146o7bca61e6h3af2062b1172fdb2@mail.gmail.com> Date: Tue, 28 Feb 2012 11:03:02 +0800 Message-ID: Subject: Re: data consistency of high page From: "Dennis.Yxun" To: NamJae Jeon Cc: Minchan Kim , Ralf Baechle , lkml , linux-mips , yan@mips.com Content-Type: multipart/alternative; boundary=f46d0447f28c168b6504b9fd77d8 X-archive-position: 32568 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dennis.yxun@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 13253 Lines: 343 --f46d0447f28c168b6504b9fd77d8 Content-Type: text/plain; charset=UTF-8 Hi NamJae: We hit pretty much the same problem, highmem + cache consistence but our hardware should have cache alias problem Could you try attached following patch? dmesg: [ 0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes) [ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Primary instruction cache 16kB, VIPT, 4-way, linesize 32 bytes. [ 0.000000] Primary data cache 16kB, 4-way, VIPT, no aliases, linesize 32 byt es [ 0.000000] MIPS secondary cache 128kB, 8-way, linesize 32 bytes. [ 0.000000] Writing ErrCtl register=00000000 [ 0.000000] Readback ErrCtl register=00000000 [ 0.000000] Memory: 510548k/262144k available (2728k kernel code, 13740k rese rved, 630k data, 5784k init, 262144k highmem) diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 00d70c8..536b7f9 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -83,8 +84,13 @@ void __flush_dcache_page(struct page *page) struct address_space *mapping = page_mapping(page); unsigned long addr; - if (PageHighMem(page)) + if (PageHighMem(page) && + (addr = (unsigned long) kmap_atomic(page, KM_SYNC_DCACHE))) { + flush_data_cache_page(addr); + kunmap_atomic((void *)addr, KM_SYNC_DCACHE); return; + } On Tue, Apr 5, 2011 at 4:17 PM, NamJae Jeon wrote: > Hi. > > As you know, there is cache operation about highpage in arm arch. > > arch/arm/mm/flush.c > > ----------------------------------------------------------------------------------------------- > if (!PageHighMem(page)) { > __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); > } else { > void *addr = kmap_high_get(page); > if (addr) { > __cpuc_flush_dcache_area(addr, PAGE_SIZE); > kunmap_high(page); > } else if (cache_is_vipt()) { > /* unmapped pages might still be cached */ > addr = kmap_atomic(page); > __cpuc_flush_dcache_area(addr, PAGE_SIZE); > kunmap_atomic(addr); > } > } > > ------------------------------------------------------------------------------------------------- > > currently, mips kernel just return without cache operation. > > Would you plz tell me your opinion ? > > Thanks. > > > 2010/3/23 NamJae Jeon : > > Hi. Ralf. > > > > I'm Namjae.jeon. nice to meet you. > > > > I face cache aliasing problem on mips 34ke. > > > > Our target cache is 34kB 4way i/d-cache , 32bytes linesize. > > > > As you know, there is possibility of cache aliasing on 8kB per way. > > > > But mips arch of kernel mainline can not properly handile this case. > > > > For example, highmem handling in __fluash_dcache_page function is just > return. > > > > So, if argument page is page in highmem, it can not flush in dcache line. > > > > I want to listen your opinion. > > > > Thanks. > > > > > > 2010/3/23 Minchan Kim : > >> Hi, Ralf. > >> > >> Below is thread long time ago. > >> At that time, we can't end up the problem by some reason. > >> Sorry for that. > >> > >> The problem would occur, again. > >> > >> On Fri, Oct 16, 2009 at 6:24 PM, Ralf Baechle > wrote: > >>> On Fri, Oct 16, 2009 at 02:17:19PM +0900, Minchan Kim wrote: > >>> > >>>> Many code of kernel fs usually allocate high page and flush. > >>>> But flush_dcache_page of mips checks PageHighMem to avoid flush > >>>> so that data consistency is broken, I think. > >>> > >>> What processor and cache configuration? > >>> > >>>> I found it's by you and Atsushi-san on 585fa724. > >>>> Why do we need the check? > >>>> Could you elaborte please? > >>> > >>> The if statement exists because __flush_dcache_page would crash if a > page > >>> is not mapped. This of course isn't correct but that wasn't a problem > >>> since highmem still is only supported on machines that don't have > aliases. > >>> > >>> Ralf > >>> > >> > >> Our system is following as. > >> > >> mips 34ke > >> primary i-cache 32kB VIPT 4way 32 byte line size. > >> primary d-cache 32kB 4way 32 bytes linesize > >> > >> If you have further questions, Namjae, Could you follow question of > Ralf? > >> > >> -- > >> Kind regards, > >> Minchan Kim > >> > > > > --f46d0447f28c168b6504b9fd77d8 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Hi NamJae:
=C2=A0We hit pretty much the same problem, highmem + cache co= nsistence
but our hardware should have cache alias problem
=C2=A0Coul= d you try attached following patch?

dmesg:
[=C2=A0=C2=A0=C2=A0 0.= 000000] PID hash table entries: 1024 (order: 0, 4096 bytes)=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0
[=C2=A0=C2=A0=C2=A0 0.000000] Dentry cache hash table entries: 32768 (order= : 5, 131072 bytes)=C2=A0
[=C2=A0=C2=A0=C2=A0 0.000000] Inode-cache hash= table entries: 16384 (order: 4, 65536 bytes)=C2=A0=C2=A0=C2=A0
[=C2=A0= =C2=A0=C2=A0 0.000000] Primary instruction cache 16kB, VIPT, 4-way, linesiz= e 32 bytes.=C2=A0
[=C2=A0=C2=A0=C2=A0 0.000000] Primary data cache 16kB, 4-way, VIPT, no alia= ses, linesize 32 byt
es=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0
[=C2=A0=C2=A0=C2=A0 0.000000] M= IPS secondary cache 128kB, 8-way, linesize 32 bytes.=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0
[=C2=A0=C2=A0=C2=A0 0.000000] Writing ErrCtl register=3D00000000=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0
[=C2=A0=C2=A0=C2=A0 0.000000] Readbac= k ErrCtl register=3D00000000=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0
[=C2= =A0=C2=A0=C2=A0 0.000000] Memory: 510548k/262144k available (2728k kernel c= ode, 13740k rese
rved, 630k data, 5784k init, 262144k highmem)

diff --git a/arch/mip= s/mm/cache.c b/arch/mips/mm/cache.c
index 00d70c8..536b7f9 100644
---= a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -15,6 +15,7 @@<= br> =C2=A0#include <linux/sched.h>
=C2=A0#include <linux/syscalls.h= >
=C2=A0#include <linux/mm.h>
+#include <linux/highmem.h&= gt;
=C2=A0
=C2=A0#include <asm/cacheflush.h>
=C2=A0#include = <asm/processor.h>
@@ -83,8 +84,13 @@ void __flush_dcache_page(struct page *page)
=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct address_space *mapping =3D page_ma= pping(page);
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned long ad= dr;
=C2=A0
-=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (PageHighMem(page= ))
+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (PageHighMem(page) &&= ;
+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 (addr =3D (unsigned long) kmap_atomic(page, KM_SYNC_DCACHE))) = {
+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 flush_data_cache_page(addr);
+=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 kunmap_atomic(= (void *)addr, KM_SYNC_DCACHE);
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return;
+=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 }


On Tue, Apr 5, 2011 at 4:17 PM, NamJae J= eon <linkinjeo= n@gmail.com> wrote:
Hi.

As you know, there is cache operation about highpage in arm arch.

arch/arm/mm/flush.c
---------------------------------------------------------------------------= --------------------
if (!PageHighMem(page)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0__cpuc_flush_dcache= _area(page_address(page), PAGE_SIZE);
=C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void *addr =3D kmap= _high_get(page);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (addr) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0__cpuc_flush_dcache_area(addr, PAGE_SIZE);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0kunmap_high(page);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else if (cache_is= _vipt()) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0/* unmapped pages might still be cached */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0addr =3D kmap_atomic(page);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0__cpuc_flush_dcache_area(addr, PAGE_SIZE);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0kunmap_atomic(addr);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0 =C2=A0}
---------------------------------------------------------------------------= ----------------------

currently, mips kernel just return without cache operation.

Would you plz tell me your opinion ?

Thanks.


2010/3/23 NamJae Jeon <linkinjeo= n@gmail.com>:
> Hi. Ralf.
>
> I'm Namjae.jeon. nice to meet you.
>
> I face cache aliasing problem on mips 34ke.
>
> Our target cache is 34kB 4way i/d-cache , 32bytes linesize.
>
> As you know, there is possibility of cache aliasing on 8kB per way. >
> But mips arch of kernel mainline can not properly =C2=A0handile this c= ase.
>
> For example, highmem handling in __fluash_dcache_page function is just= return.
>
> So, if argument page is page in highmem, it can not flush in dcache li= ne.
>
> I want to listen your opinion.
>
> Thanks.
>
>
> 2010/3/23 Minchan Kim <min= chan.kim@gmail.com>:
>> Hi, Ralf.
>>
>> Below is thread long time ago.
>> At that time, we can't end up the problem by some reason.
>> Sorry for that.
>>
>> The problem would occur, again.
>>
>> On Fri, Oct 16, 2009 at 6:24 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
>>> On Fri, Oct 16, 2009 at 02:17:19PM +0900, Minchan Kim wrote: >>>
>>>> Many code of kernel fs usually allocate high page and flus= h.
>>>> But flush_dcache_page of mips checks PageHighMem to avoid = flush
>>>> so that data consistency is broken, I think.
>>>
>>> What processor and cache configuration?
>>>
>>>> I found it's by you and Atsushi-san on 585fa724.
>>>> Why do we need the check?
>>>> Could you elaborte please?
>>>
>>> The if statement exists because __flush_dcache_page would cras= h if a page
>>> is not mapped. =C2=A0This of course isn't correct but that= wasn't a problem
>>> since highmem still is only supported on machines that don'= ;t have aliases.
>>>
>>> =C2=A0Ralf
>>>
>>
>> Our system is following as.
>>
>> mips 34ke
>> primary i-cache 32kB VIPT 4way 32 byte line size.
>> primary d-cache 32kB 4way =C2=A032 bytes linesize
>>
>> If you have further questions, Namjae, Could you follow question o= f Ralf?
>>
>> --
>> Kind regards,
>> Minchan Kim
>>
>


--f46d0447f28c168b6504b9fd77d8-- From linkinjeon@gmail.com Tue Feb 28 08:09:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 08:09:53 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:33011 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903545Ab2B1HJp convert rfc822-to-8bit (ORCPT ); Tue, 28 Feb 2012 08:09:45 +0100 Received: by bkcjk13 with SMTP id jk13so1690793bkc.36 for ; Mon, 27 Feb 2012 23:09:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=zdtldnmuJY03KzZ3GZtkmuiKFwq1BMw/HNa6MProWvM=; b=LAvD2+fZ1DIMFM+yx8D5DH8ZrsgPsBd3/zvb7ITUiILZwFtCSx4vXQGYE5ecCOEOYI sR16GXiETimtmt+F8zahAluIU53i45C+IGgAKdha/03smQW192eIGx3/orXrSEw5ZMtW sRrSAw21zKZKxxMOU8rWgRPuKSkz6MaIMlnho= MIME-Version: 1.0 Received: by 10.204.128.75 with SMTP id j11mr6682625bks.2.1330412980186; Mon, 27 Feb 2012 23:09:40 -0800 (PST) Received: by 10.204.104.13 with HTTP; Mon, 27 Feb 2012 23:09:40 -0800 (PST) In-Reply-To: References: <28c262361003230146o7bca61e6h3af2062b1172fdb2@mail.gmail.com> Date: Tue, 28 Feb 2012 16:09:40 +0900 Message-ID: Subject: Re: data consistency of high page From: Namjae Jeon To: "Dennis.Yxun" Cc: Minchan Kim , Ralf Baechle , lkml , linux-mips , yan@mips.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32569 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linkinjeon@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5473 Lines: 170 2012/2/28 Dennis.Yxun : > Hi NamJae: >  We hit pretty much the same problem, highmem + cache consistence > but our hardware should have cache alias problem >  Could you try attached following patch? Hi Dennis. I already fixed it as your patch in our system before. your patch looks reasonable to me. Would you post this patch with adding the below ? Reviewed-by: Namjae Jeon Tested-by: Namjae Jeon Thanks~ > > dmesg: > [    0.000000] PID hash table entries: 1024 (order: 0, 4096 > bytes) > [    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 > bytes) > [    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 > bytes) > [    0.000000] Primary instruction cache 16kB, VIPT, 4-way, linesize 32 > bytes. > [    0.000000] Primary data cache 16kB, 4-way, VIPT, no aliases, linesize 32 > byt > es > [    0.000000] MIPS secondary cache 128kB, 8-way, linesize 32 > bytes. > [    0.000000] Writing ErrCtl > register=00000000 > [    0.000000] Readback ErrCtl > register=00000000 > [    0.000000] Memory: 510548k/262144k available (2728k kernel code, 13740k > rese > rved, 630k data, 5784k init, 262144k highmem) > > diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c > index 00d70c8..536b7f9 100644 > --- a/arch/mips/mm/cache.c > +++ b/arch/mips/mm/cache.c > @@ -15,6 +15,7 @@ >  #include >  #include >  #include > +#include > >  #include >  #include > @@ -83,8 +84,13 @@ void __flush_dcache_page(struct page *page) >         struct address_space *mapping = page_mapping(page); >         unsigned long addr; > > -       if (PageHighMem(page)) > +       if (PageHighMem(page) && > +               (addr = (unsigned long) kmap_atomic(page, KM_SYNC_DCACHE))) > { > +               flush_data_cache_page(addr); > +               kunmap_atomic((void *)addr, KM_SYNC_DCACHE); >                 return; > +       } > > > > On Tue, Apr 5, 2011 at 4:17 PM, NamJae Jeon wrote: >> >> Hi. >> >> As you know, there is cache operation about highpage in arm arch. >> >> arch/arm/mm/flush.c >> >> ----------------------------------------------------------------------------------------------- >> if (!PageHighMem(page)) { >>                __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); >>        } else { >>                void *addr = kmap_high_get(page); >>                if (addr) { >>                        __cpuc_flush_dcache_area(addr, PAGE_SIZE); >>                        kunmap_high(page); >>                } else if (cache_is_vipt()) { >>                        /* unmapped pages might still be cached */ >>                        addr = kmap_atomic(page); >>                        __cpuc_flush_dcache_area(addr, PAGE_SIZE); >>                        kunmap_atomic(addr); >>                } >>        } >> >> ------------------------------------------------------------------------------------------------- >> >> currently, mips kernel just return without cache operation. >> >> Would you plz tell me your opinion ? >> >> Thanks. >> >> >> 2010/3/23 NamJae Jeon : >> > Hi. Ralf. >> > >> > I'm Namjae.jeon. nice to meet you. >> > >> > I face cache aliasing problem on mips 34ke. >> > >> > Our target cache is 34kB 4way i/d-cache , 32bytes linesize. >> > >> > As you know, there is possibility of cache aliasing on 8kB per way. >> > >> > But mips arch of kernel mainline can not properly  handile this case. >> > >> > For example, highmem handling in __fluash_dcache_page function is just >> > return. >> > >> > So, if argument page is page in highmem, it can not flush in dcache >> > line. >> > >> > I want to listen your opinion. >> > >> > Thanks. >> > >> > >> > 2010/3/23 Minchan Kim : >> >> Hi, Ralf. >> >> >> >> Below is thread long time ago. >> >> At that time, we can't end up the problem by some reason. >> >> Sorry for that. >> >> >> >> The problem would occur, again. >> >> >> >> On Fri, Oct 16, 2009 at 6:24 PM, Ralf Baechle >> >> wrote: >> >>> On Fri, Oct 16, 2009 at 02:17:19PM +0900, Minchan Kim wrote: >> >>> >> >>>> Many code of kernel fs usually allocate high page and flush. >> >>>> But flush_dcache_page of mips checks PageHighMem to avoid flush >> >>>> so that data consistency is broken, I think. >> >>> >> >>> What processor and cache configuration? >> >>> >> >>>> I found it's by you and Atsushi-san on 585fa724. >> >>>> Why do we need the check? >> >>>> Could you elaborte please? >> >>> >> >>> The if statement exists because __flush_dcache_page would crash if a >> >>> page >> >>> is not mapped.  This of course isn't correct but that wasn't a problem >> >>> since highmem still is only supported on machines that don't have >> >>> aliases. >> >>> >> >>>  Ralf >> >>> >> >> >> >> Our system is following as. >> >> >> >> mips 34ke >> >> primary i-cache 32kB VIPT 4way 32 byte line size. >> >> primary d-cache 32kB 4way  32 bytes linesize >> >> >> >> If you have further questions, Namjae, Could you follow question of >> >> Ralf? >> >> >> >> -- >> >> Kind regards, >> >> Minchan Kim >> >> >> > >> > From dennis.yxun@gmail.com Tue Feb 28 09:48:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 09:48:27 +0100 (CET) Received: from mail-tul01m020-f177.google.com ([209.85.214.177]:54619 "EHLO mail-tul01m020-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903549Ab2B1IsU (ORCPT ); Tue, 28 Feb 2012 09:48:20 +0100 Received: by obcuz6 with SMTP id uz6so7812924obc.36 for ; Tue, 28 Feb 2012 00:48:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=FH+LlM1iw5/DupuEMYIDzlsf4bNC8TAJ9hCoht/g+24=; b=OYwHxf6CLg4nvqKK+jqJrHvQHPtjOL514cEuJwhHNg5Njtsl49YSZhX/Z+O84qkqsJ CO9k5m0vNx9sifJsbD05vKNUPaMu3oBcowkPfHMG9xbiL5kAZV+L02albMygCiq5JQO2 5YHu9tdnm6MnMutg4zsRsr923nYDplE2xzCOU= MIME-Version: 1.0 Received: by 10.182.216.101 with SMTP id op5mr5627900obc.54.1330418894112; Tue, 28 Feb 2012 00:48:14 -0800 (PST) Received: by 10.182.220.68 with HTTP; Tue, 28 Feb 2012 00:48:13 -0800 (PST) In-Reply-To: References: <28c262361003230146o7bca61e6h3af2062b1172fdb2@mail.gmail.com> Date: Tue, 28 Feb 2012 16:48:13 +0800 Message-ID: Subject: Re: data consistency of high page From: "Dennis.Yxun" To: Namjae Jeon Cc: Minchan Kim , Ralf Baechle , lkml , linux-mips , yan@mips.com Content-Type: multipart/alternative; boundary=f46d0447864b96084704ba0249cb X-archive-position: 32570 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dennis.yxun@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 15754 Lines: 430 --f46d0447864b96084704ba0249cb Content-Type: text/plain; charset=UTF-8 HI NamJae: I think someone already published this patch, just can't remember when exactly~ Also, before we push this patch into repository, should we have more reviews? Is there any better solution? Should we always flush cache when it is highmem? thanks Dennis On Tue, Feb 28, 2012 at 3:09 PM, Namjae Jeon wrote: > 2012/2/28 Dennis.Yxun : > > Hi NamJae: > > We hit pretty much the same problem, highmem + cache consistence > > but our hardware should have cache alias problem > > Could you try attached following patch? > Hi Dennis. > I already fixed it as your patch in our system before. > your patch looks reasonable to me. > Would you post this patch with adding the below ? > > Reviewed-by: Namjae Jeon > Tested-by: Namjae Jeon > > Thanks~ > > > > > dmesg: > > [ 0.000000] PID hash table entries: 1024 (order: 0, 4096 > > bytes) > > [ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 > > bytes) > > [ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 > > bytes) > > [ 0.000000] Primary instruction cache 16kB, VIPT, 4-way, linesize 32 > > bytes. > > [ 0.000000] Primary data cache 16kB, 4-way, VIPT, no aliases, > linesize 32 > > byt > > es > > [ 0.000000] MIPS secondary cache 128kB, 8-way, linesize 32 > > bytes. > > [ 0.000000] Writing ErrCtl > > register=00000000 > > [ 0.000000] Readback ErrCtl > > register=00000000 > > [ 0.000000] Memory: 510548k/262144k available (2728k kernel code, > 13740k > > rese > > rved, 630k data, 5784k init, 262144k highmem) > > > > diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c > > index 00d70c8..536b7f9 100644 > > --- a/arch/mips/mm/cache.c > > +++ b/arch/mips/mm/cache.c > > @@ -15,6 +15,7 @@ > > #include > > #include > > #include > > +#include > > > > #include > > #include > > @@ -83,8 +84,13 @@ void __flush_dcache_page(struct page *page) > > struct address_space *mapping = page_mapping(page); > > unsigned long addr; > > > > - if (PageHighMem(page)) > > + if (PageHighMem(page) && > > + (addr = (unsigned long) kmap_atomic(page, > KM_SYNC_DCACHE))) > > { > > + flush_data_cache_page(addr); > > + kunmap_atomic((void *)addr, KM_SYNC_DCACHE); > > return; > > + } > > > > > > > > On Tue, Apr 5, 2011 at 4:17 PM, NamJae Jeon > wrote: > >> > >> Hi. > >> > >> As you know, there is cache operation about highpage in arm arch. > >> > >> arch/arm/mm/flush.c > >> > >> > ----------------------------------------------------------------------------------------------- > >> if (!PageHighMem(page)) { > >> __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); > >> } else { > >> void *addr = kmap_high_get(page); > >> if (addr) { > >> __cpuc_flush_dcache_area(addr, PAGE_SIZE); > >> kunmap_high(page); > >> } else if (cache_is_vipt()) { > >> /* unmapped pages might still be cached */ > >> addr = kmap_atomic(page); > >> __cpuc_flush_dcache_area(addr, PAGE_SIZE); > >> kunmap_atomic(addr); > >> } > >> } > >> > >> > ------------------------------------------------------------------------------------------------- > >> > >> currently, mips kernel just return without cache operation. > >> > >> Would you plz tell me your opinion ? > >> > >> Thanks. > >> > >> > >> 2010/3/23 NamJae Jeon : > >> > Hi. Ralf. > >> > > >> > I'm Namjae.jeon. nice to meet you. > >> > > >> > I face cache aliasing problem on mips 34ke. > >> > > >> > Our target cache is 34kB 4way i/d-cache , 32bytes linesize. > >> > > >> > As you know, there is possibility of cache aliasing on 8kB per way. > >> > > >> > But mips arch of kernel mainline can not properly handile this case. > >> > > >> > For example, highmem handling in __fluash_dcache_page function is just > >> > return. > >> > > >> > So, if argument page is page in highmem, it can not flush in dcache > >> > line. > >> > > >> > I want to listen your opinion. > >> > > >> > Thanks. > >> > > >> > > >> > 2010/3/23 Minchan Kim : > >> >> Hi, Ralf. > >> >> > >> >> Below is thread long time ago. > >> >> At that time, we can't end up the problem by some reason. > >> >> Sorry for that. > >> >> > >> >> The problem would occur, again. > >> >> > >> >> On Fri, Oct 16, 2009 at 6:24 PM, Ralf Baechle > >> >> wrote: > >> >>> On Fri, Oct 16, 2009 at 02:17:19PM +0900, Minchan Kim wrote: > >> >>> > >> >>>> Many code of kernel fs usually allocate high page and flush. > >> >>>> But flush_dcache_page of mips checks PageHighMem to avoid flush > >> >>>> so that data consistency is broken, I think. > >> >>> > >> >>> What processor and cache configuration? > >> >>> > >> >>>> I found it's by you and Atsushi-san on 585fa724. > >> >>>> Why do we need the check? > >> >>>> Could you elaborte please? > >> >>> > >> >>> The if statement exists because __flush_dcache_page would crash if a > >> >>> page > >> >>> is not mapped. This of course isn't correct but that wasn't a > problem > >> >>> since highmem still is only supported on machines that don't have > >> >>> aliases. > >> >>> > >> >>> Ralf > >> >>> > >> >> > >> >> Our system is following as. > >> >> > >> >> mips 34ke > >> >> primary i-cache 32kB VIPT 4way 32 byte line size. > >> >> primary d-cache 32kB 4way 32 bytes linesize > >> >> > >> >> If you have further questions, Namjae, Could you follow question of > >> >> Ralf? > >> >> > >> >> -- > >> >> Kind regards, > >> >> Minchan Kim > >> >> > >> > > >> > > > --f46d0447864b96084704ba0249cb Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable HI NamJae:
=C2=A0=C2=A0=C2=A0 I think someone already published this pat= ch, just can't remember when exactly~
Also, before we push this patc= h into repository, should we have more reviews?
Is there any better solu= tion? Should we always flush cache when it is highmem?
=C2=A0=C2=A0=C2=A0 thanks

Dennis

O= n Tue, Feb 28, 2012 at 3:09 PM, Namjae Jeon <linkinjeon@gmail.com> wrote:=
2012/2/28 Dennis.Yxun <dennis.y= xun@gmail.com>:
> Hi NamJae:
> =C2=A0We hit pretty much the same problem, highmem + cache consistence=
> but our hardware should have cache alias problem
> =C2=A0Could you try attached following patch?
Hi Dennis.
I already fixed it as your patch in our system before.
your patch looks reasonable to me.
Would you post this patch with adding the below ?

Reviewed-by: Namjae Jeon <linkin= jeon@gmail.com>
Tested-by: Namjae Jeon <linkinje= on@gmail.com>

Thanks~

>
> dmesg:
> [=C2=A0=C2=A0=C2=A0 0.000000] PID hash table entries: 1024 (order: 0, = 4096
> bytes)
> [=C2=A0=C2=A0=C2=A0 0.000000] Dentry cache hash table entries: 32768 (= order: 5, 131072
> bytes)
> [=C2=A0=C2=A0=C2=A0 0.000000] Inode-cache hash table entries: 16384 (o= rder: 4, 65536
> bytes)
> [=C2=A0=C2=A0=C2=A0 0.000000] Primary instruction cache 16kB, VIPT, 4-= way, linesize 32
> bytes.
> [=C2=A0=C2=A0=C2=A0 0.000000] Primary data cache 16kB, 4-way, VIPT, no= aliases, linesize 32
> byt
> es
> [=C2=A0=C2=A0=C2=A0 0.000000] MIPS secondary cache 128kB, 8-way, lines= ize 32
> bytes.
> [=C2=A0=C2=A0=C2=A0 0.000000] Writing ErrCtl
> register=3D00000000
> [=C2=A0=C2=A0=C2=A0 0.000000] Readback ErrCtl
> register=3D00000000
> [=C2=A0=C2=A0=C2=A0 0.000000] Memory: 510548k/262144k available (2728k= kernel code, 13740k
> rese
> rved, 630k data, 5784k init, 262144k highmem)
>
> diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
> index 00d70c8..536b7f9 100644
> --- a/arch/mips/mm/cache.c
> +++ b/arch/mips/mm/cache.c
> @@ -15,6 +15,7 @@
> =C2=A0#include <linux/sched.h>
> =C2=A0#include <linux/syscalls.h>
> =C2=A0#include <linux/mm.h>
> +#include <linux/highmem.h>
>
> =C2=A0#include <asm/cacheflush.h>
> =C2=A0#include <asm/processor.h>
> @@ -83,8 +84,13 @@ void __flush_dcache_page(struct page *page)
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct address_space *mappi= ng =3D page_mapping(page);
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned long addr;
>
> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (PageHighMem(page))
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (PageHighMem(page) &&=
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 (addr =3D (unsigned long) kmap_atomic(page, KM_SYNC_DCACHE)= ))
> {
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 flush_data_cache_page(addr);
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 kunmap_atomic((void *)addr, KM_SYNC_DCACHE);
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 return;
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }
>
>
>
> On Tue, Apr 5, 2011 at 4:17 PM, NamJae Jeon <linkinjeon@gmail.com> wrote:
>>
>> Hi.
>>
>> As you know, there is cache operation about highpage in arm arch.<= br> >>
>> arch/arm/mm/flush.c
>>
>> ------------------------------------------------------------------= -----------------------------
>> if (!PageHighMem(page)) {
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0__cpuc_flus= h_dcache_area(page_address(page), PAGE_SIZE);
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void *addr = =3D kmap_high_get(page);
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (addr) {=
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0__cpuc_flush_dcache_area(addr, PAGE_SIZE);
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0kunmap_high(page);
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else if (= cache_is_vipt()) {
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0/* unmapped pages might still be cached */
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0addr =3D kmap_atomic(page);
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0__cpuc_flush_dcache_area(addr, PAGE_SIZE);
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0kunmap_atomic(addr);
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>>
>> ------------------------------------------------------------------= -------------------------------
>>
>> currently, mips kernel just return without cache operation.
>>
>> Would you plz tell me your opinion ?
>>
>> Thanks.
>>
>>
>> 2010/3/23 NamJae Jeon <= linkinjeon@gmail.com>:
>> > Hi. Ralf.
>> >
>> > I'm Namjae.jeon. nice to meet you.
>> >
>> > I face cache aliasing problem on mips 34ke.
>> >
>> > Our target cache is 34kB 4way i/d-cache , 32bytes linesize. >> >
>> > As you know, there is possibility of cache aliasing on 8kB pe= r way.
>> >
>> > But mips arch of kernel mainline can not properly =C2=A0handi= le this case.
>> >
>> > For example, highmem handling in __fluash_dcache_page functio= n is just
>> > return.
>> >
>> > So, if argument page is page in highmem, it can not flush in = dcache
>> > line.
>> >
>> > I want to listen your opinion.
>> >
>> > Thanks.
>> >
>> >
>> > 2010/3/23 Minchan Kim <minchan.kim@gmail.com>:
>> >> Hi, Ralf.
>> >>
>> >> Below is thread long time ago.
>> >> At that time, we can't end up the problem by some rea= son.
>> >> Sorry for that.
>> >>
>> >> The problem would occur, again.
>> >>
>> >> On Fri, Oct 16, 2009 at 6:24 PM, Ralf Baechle <ralf@linux-mips.org>
>> >> wrote:
>> >>> On Fri, Oct 16, 2009 at 02:17:19PM +0900, Minchan Kim= wrote:
>> >>>
>> >>>> Many code of kernel fs usually allocate high page= and flush.
>> >>>> But flush_dcache_page of mips checks PageHighMem = to avoid flush
>> >>>> so that data consistency is broken, I think.
>> >>>
>> >>> What processor and cache configuration?
>> >>>
>> >>>> I found it's by you and Atsushi-san on 585fa7= 24.
>> >>>> Why do we need the check?
>> >>>> Could you elaborte please?
>> >>>
>> >>> The if statement exists because __flush_dcache_page w= ould crash if a
>> >>> page
>> >>> is not mapped. =C2=A0This of course isn't correct= but that wasn't a problem
>> >>> since highmem still is only supported on machines tha= t don't have
>> >>> aliases.
>> >>>
>> >>> =C2=A0Ralf
>> >>>
>> >>
>> >> Our system is following as.
>> >>
>> >> mips 34ke
>> >> primary i-cache 32kB VIPT 4way 32 byte line size.
>> >> primary d-cache 32kB 4way =C2=A032 bytes linesize
>> >>
>> >> If you have further questions, Namjae, Could you follow q= uestion of
>> >> Ralf?
>> >>
>> >> --
>> >> Kind regards,
>> >> Minchan Kim
>> >>
>> >
>>
>

--f46d0447864b96084704ba0249cb-- From paul.gortmaker@windriver.com Tue Feb 28 20:25:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 20:25:13 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:64675 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903594Ab2B1TZG (ORCPT ); Tue, 28 Feb 2012 20:25:06 +0100 Received: from yow-lpgnfs-02.corp.ad.wrs.com (yow-lpgnfs-02.ottawa.windriver.com [128.224.149.8]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q1SJOuvS014095; Tue, 28 Feb 2012 11:24:58 -0800 (PST) From: Paul Gortmaker To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: [PATCH 1/5] serial: MIPS DECstation zs.c driver needs module.h Date: Tue, 28 Feb 2012 14:24:44 -0500 Message-Id: <1330457088-14587-2-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> References: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> X-archive-position: 32571 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 675 Lines: 24 This driver is a module and needs module.h, otherwise it will break when we remove a bogus usage of module.h from one of the other MIPS headers. Signed-off-by: Paul Gortmaker --- drivers/tty/serial/zs.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/tty/serial/zs.c b/drivers/tty/serial/zs.c index b7455b5..73315e3 100644 --- a/drivers/tty/serial/zs.c +++ b/drivers/tty/serial/zs.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include -- 1.7.9.1 From paul.gortmaker@windriver.com Tue Feb 28 20:25:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 20:25:40 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:64672 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903774Ab2B1TZG (ORCPT ); Tue, 28 Feb 2012 20:25:06 +0100 Received: from yow-lpgnfs-02.corp.ad.wrs.com (yow-lpgnfs-02.ottawa.windriver.com [128.224.149.8]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q1SJOuvR014095; Tue, 28 Feb 2012 11:24:57 -0800 (PST) From: Paul Gortmaker To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: [PATCH 0/5] MIPS: module.h usage cleanup. Date: Tue, 28 Feb 2012 14:24:43 -0500 Message-Id: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 32572 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1763 Lines: 45 Hi Ralf, Not a lot to see here, really. MIPS had usages of module.h tucked away in a couple asm files, and that was masking some of the other implicit users, plus preventing MIPS from getting the full benefit of not having to feed module.h to cpp 35,000 times. I've left the two drivers/serial commits separate, in case there is a desire to have them go in via Greg's trees, but they are a required dependency for the arch/mips fixes, so I think it makes sense they stay together with the other changes here. I will have some arch independent module.h cleanups (in fs and lib) that will require me to create a module.h tree for 3.4, so I can carry this there if required. But this lot is all self-contained to MIPS and so I'd be fine with (and actually prefer) this going in via the MIPS tree. No strong preference - either way, let me know. Thanks, Paul. --- Paul Gortmaker (5): serial: MIPS DECstation zs.c driver needs module.h serial: MIPS swarm sb1250-duart.c driver needs module.h MIPS: fix several implicit uses of export.h/module.h MIPS: delete bogus module.h usage in termios.h MIPS: dont use module.h just to export symbols in asm/uasm.h arch/mips/alchemy/devboards/db1200.c | 1 + arch/mips/cavium-octeon/setup.c | 1 + arch/mips/include/asm/module.h | 1 + arch/mips/include/asm/termios.h | 2 +- arch/mips/include/asm/uasm.h | 2 +- arch/mips/kernel/traps.c | 1 + arch/mips/pmc-sierra/yosemite/setup.c | 1 + arch/mips/rb532/devices.c | 1 + arch/mips/sni/setup.c | 1 + drivers/tty/serial/sb1250-duart.c | 1 + drivers/tty/serial/zs.c | 1 + 11 files changed, 11 insertions(+), 2 deletions(-) -- 1.7.9.1 From paul.gortmaker@windriver.com Tue Feb 28 20:25:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 20:26:03 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:64678 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903777Ab2B1TZG (ORCPT ); Tue, 28 Feb 2012 20:25:06 +0100 Received: from yow-lpgnfs-02.corp.ad.wrs.com (yow-lpgnfs-02.ottawa.windriver.com [128.224.149.8]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q1SJOuvT014095; Tue, 28 Feb 2012 11:24:59 -0800 (PST) From: Paul Gortmaker To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: [PATCH 2/5] serial: MIPS swarm sb1250-duart.c driver needs module.h Date: Tue, 28 Feb 2012 14:24:45 -0500 Message-Id: <1330457088-14587-3-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> References: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> X-archive-position: 32573 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 727 Lines: 24 This driver is a module and needs module.h, otherwise it will break when we remove a bogus usage of module.h from one of the other MIPS headers. Signed-off-by: Paul Gortmaker --- drivers/tty/serial/sb1250-duart.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/tty/serial/sb1250-duart.c b/drivers/tty/serial/sb1250-duart.c index 0be8a2f..f76b1688 100644 --- a/drivers/tty/serial/sb1250-duart.c +++ b/drivers/tty/serial/sb1250-duart.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include -- 1.7.9.1 From paul.gortmaker@windriver.com Tue Feb 28 20:25:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 20:26:24 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:64684 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903778Ab2B1TZH (ORCPT ); Tue, 28 Feb 2012 20:25:07 +0100 Received: from yow-lpgnfs-02.corp.ad.wrs.com (yow-lpgnfs-02.ottawa.windriver.com [128.224.149.8]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q1SJOuvU014095; Tue, 28 Feb 2012 11:24:59 -0800 (PST) From: Paul Gortmaker To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: [PATCH 3/5] MIPS: fix several implicit uses of export.h/module.h Date: Tue, 28 Feb 2012 14:24:46 -0500 Message-Id: <1330457088-14587-4-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> References: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> X-archive-position: 32574 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3063 Lines: 100 These will show up as a build failure once we clean up a misuse of module.h in the mips termios header. Uses export.h: (EXPORT_SYMBOL) arch/mips/cavium-octeon/setup.c arch/mips/pmc-sierra/yosemite/setup.c arch/mips/rb532/devices.c arch/mips/sni/setup.c Uses module.h: (symbol_get/put) arch/mips/alchemy/devboards/db1200.c Uses module.h: (print_modules) arch/mips/kernel/traps.c Signed-off-by: Paul Gortmaker --- arch/mips/alchemy/devboards/db1200.c | 1 + arch/mips/cavium-octeon/setup.c | 1 + arch/mips/kernel/traps.c | 1 + arch/mips/pmc-sierra/yosemite/setup.c | 1 + arch/mips/rb532/devices.c | 1 + arch/mips/sni/setup.c | 1 + 6 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c index a83302b..7dde016 100644 --- a/arch/mips/alchemy/devboards/db1200.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 260b273..3a01231 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index cc4a3f1..62cbffd 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index 3498ac9..b6472fc 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index a969eb8..ea77428 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ #include +#include #include #include #include diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index d16b462..413f17f 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -10,6 +10,7 @@ */ #include #include +#include #include #include #include -- 1.7.9.1 From paul.gortmaker@windriver.com Tue Feb 28 20:25:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 20:26:46 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:64695 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903779Ab2B1TZH (ORCPT ); Tue, 28 Feb 2012 20:25:07 +0100 Received: from yow-lpgnfs-02.corp.ad.wrs.com (yow-lpgnfs-02.ottawa.windriver.com [128.224.149.8]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q1SJOuvV014095; Tue, 28 Feb 2012 11:25:00 -0800 (PST) From: Paul Gortmaker To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: [PATCH 4/5] MIPS: delete bogus module.h usage in termios.h Date: Tue, 28 Feb 2012 14:24:47 -0500 Message-Id: <1330457088-14587-5-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> References: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> X-archive-position: 32575 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1231 Lines: 41 There is no need for this. Removing it causes a small amount of fallout (shown below) due to a few implicit header presence assumptions that are easily fixed. arch/mips/include/asm/termios.h:103: error: implicit declaration of function 'access_ok' arch/mips/include/asm/module.h:17: error: expected specifier-qualifier-list before 'Elf64_Addr' Signed-off-by: Paul Gortmaker --- arch/mips/include/asm/module.h | 1 + arch/mips/include/asm/termios.h | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index 7467d1d..5300080 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -2,6 +2,7 @@ #define _ASM_MODULE_H #include +#include #include struct mod_arch_specific { diff --git a/arch/mips/include/asm/termios.h b/arch/mips/include/asm/termios.h index 8f77f77..abdd87a 100644 --- a/arch/mips/include/asm/termios.h +++ b/arch/mips/include/asm/termios.h @@ -60,7 +60,7 @@ struct termio { }; #ifdef __KERNEL__ -#include +#include /* * intr=^C quit=^\ erase=del kill=^U -- 1.7.9.1 From paul.gortmaker@windriver.com Tue Feb 28 20:25:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Feb 2012 20:27:08 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:64699 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903780Ab2B1TZI (ORCPT ); Tue, 28 Feb 2012 20:25:08 +0100 Received: from yow-lpgnfs-02.corp.ad.wrs.com (yow-lpgnfs-02.ottawa.windriver.com [128.224.149.8]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q1SJOuvW014095; Tue, 28 Feb 2012 11:25:01 -0800 (PST) From: Paul Gortmaker To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: [PATCH 5/5] MIPS: dont use module.h just to export symbols in asm/uasm.h Date: Tue, 28 Feb 2012 14:24:48 -0500 Message-Id: <1330457088-14587-6-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> References: <1330457088-14587-1-git-send-email-paul.gortmaker@windriver.com> X-archive-position: 32576 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 715 Lines: 25 Putting module.h into widely used headers just bogs cpp down with reams of stuff that isn't needed. Here, we only need visibility to EXPORT_SYMBOL. Signed-off-by: Paul Gortmaker --- arch/mips/include/asm/uasm.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 504d40a..440a21d 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -11,7 +11,7 @@ #include #ifdef CONFIG_EXPORT_UASM -#include +#include #define __uasminit #define __uasminitdata #define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym) -- 1.7.9.1 From danny.kukawka@bisect.de Wed Feb 29 08:04:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 29 Feb 2012 08:04:32 +0100 (CET) Received: from wp188.webpack.hosteurope.de ([80.237.132.195]:53567 "EHLO wp188.webpack.hosteurope.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903555Ab2B2HEZ convert rfc822-to-8bit (ORCPT ); Wed, 29 Feb 2012 08:04:25 +0100 Received: from nrbg-4d077c62.pool.mediaways.net ([77.7.124.98] helo=hp-compaq-2710p-wlan.fritz.box); authenticated by wp188.webpack.hosteurope.de running ExIM with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) id 1S2dZn-0003ie-JD; Wed, 29 Feb 2012 08:03:51 +0100 From: Danny Kukawka To: Geert Uytterhoeven Subject: Re: [PATCH 00/12] Part 2: check given MAC address, if invalid return -EADDRNOTAVAIL Date: Wed, 29 Feb 2012 08:02:49 +0100 User-Agent: KMail/1.9.10 Cc: =?utf-8?q?Micha=C5=82_Miros=C5=82aw?= , "David S. Miller" , Andy Gospodarek , "Guo-Fu Tseng" , Petko Manolov , "VMware, Inc." , "John W. Linville" , linux390@de.ibm.com, Mauro Carvalho Chehab , Stephen Hemminger , Joe Perches , Jeff Kirsher , Jiri Pirko , netdev@vger.kernel.org, linux-usb@vger.kernel.org, linux-wireless@vger.kernel.org, libertas-dev@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-s390@vger.kernel.org, linux-hams@vger.kernel.org, linux-mips@linux-mips.org References: <1330099282-4588-1-git-send-email-danny.kukawka@bisect.de> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <201202290802.52234.danny.kukawka@bisect.de> X-bounce-key: webpack.hosteurope.de;danny.kukawka@bisect.de;1330499065;d1620e5d; X-archive-position: 32577 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: danny.kukawka@bisect.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1047 Lines: 25 On Samstag, 25. Februar 2012, Geert Uytterhoeven wrote: > 2012/2/24 Michał Mirosław : > > 2012/2/24 Danny Kukawka : > >> Second Part of series patches to unifiy the return value of > >> .ndo_set_mac_address if the given address isn't valid. > >> > >> These changes check if a given (MAC) address is valid in > >> .ndo_set_mac_address, if invalid return -EADDRNOTAVAIL > >> as eth_mac_addr() already does if is_valid_ether_addr() fails. > > > > Why not just fix dev_set_mac_address() and make do_setlink() use that? > > BTW, it's also called from dev_set_mac_address(). > > > Checks are specific to address family, not device model I assume. > > Indeed, why can't this be done in one single place, instead of sprinkling > these checks over all drivers, missing all out-of-tree (note: I don't care) > and all soon-to-be-submitted drivers? Since the .ndo_set_mac_address functions are used by some drivers internally too, you may get some new checks on other places. But I'll take a look at it. Danny From an4linu@gmail.com Wed Feb 29 10:43:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 29 Feb 2012 10:43:34 +0100 (CET) Received: from mail-we0-f177.google.com ([74.125.82.177]:35849 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903554Ab2B2Jna (ORCPT ); Wed, 29 Feb 2012 10:43:30 +0100 Received: by werp11 with SMTP id p11so2341338wer.36 for ; Wed, 29 Feb 2012 01:43:25 -0800 (PST) Received-SPF: pass (google.com: domain of anoop.pa@gmail.com designates 10.180.101.37 as permitted sender) client-ip=10.180.101.37; Authentication-Results: mr.google.com; spf=pass (google.com: domain of anoop.pa@gmail.com designates 10.180.101.37 as permitted sender) smtp.mail=anoop.pa@gmail.com; dkim=pass header.i=anoop.pa@gmail.com Received: from mr.google.com ([10.180.101.37]) by 10.180.101.37 with SMTP id fd5mr18077181wib.1.1330508605492 (num_hops = 1); Wed, 29 Feb 2012 01:43:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=b7Av3XqmpTnXBW0jNo+I1tZU8Ydc0DFx3gidTW1RhTc=; b=dSm3X5P2U+jy01hfAHeOpfw1RFWM65tOpV18YoTioZJvhdH58seMmb5trk0UVwFJca i62szniLmlnauFUOKo78nR56HmZwdF8fl11+5BG+q+K14EuXa/uxoTqMf8PzhTGwHSGg NHkN54OJr1575JPRwuC9+/N81yhxtB0CuzMRo= MIME-Version: 1.0 Received: by 10.180.101.37 with SMTP id fd5mr14388531wib.1.1330508605364; Wed, 29 Feb 2012 01:43:25 -0800 (PST) Received: by 10.223.151.14 with HTTP; Wed, 29 Feb 2012 01:43:25 -0800 (PST) In-Reply-To: References: <4ED3483E.60204@gmail.com> Date: Wed, 29 Feb 2012 15:13:25 +0530 X-Google-Sender-Auth: gNzfP43NGwnstNRC3Dc0zg0Zzxw Message-ID: Subject: Re: Using NFS with HIGHMEM support From: Ans_linu To: "Dennis.Yxun" Cc: Jacky Lam , linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=f46d04428158cb182c04ba172cd4 X-archive-position: 32578 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: an4linu@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3759 Lines: 96 --f46d04428158cb182c04ba172cd4 Content-Type: text/plain; charset=ISO-8859-1 Hi , I have faced similar issues before. Not sure this will help. But please take a look at. http://www.linux-mips.org/archives/linux-mips/2010-08/msg00075.html Thanks Ans On Mon, Feb 27, 2012 at 3:34 PM, Dennis.Yxun wrote: > HI: > I'm encountered pretty much the same problem here > I'm tracing with current 3.3-rc4 branch(from ralf's tree) > If I put rootfs at nand flash + highmem enabled, then execute problem may > give > illegal instruction error, bus error, try it again may run success. > but if I don't enable highmem, then problem is gone. > any hints? thanks > > Dennis > > > On Mon, Nov 28, 2011 at 4:37 PM, Jacky Lam wrote: > >> Hi, >> >> I am using mips-linux-3.0.4 with HIGHMEM enabled. Everything is >> working fine, but I find something strange that when I execute a >> statically-linked binary through NFS mounted directory. It will gives me an >> illegal instruction error or SIGSEGV. If I run it again, the binary can >> run without problem. I have to reboot or drop all the vm cache in order to >> reproduce the error again. >> >> Also, if I run the binary in harddisk or dynamically link the binary, >> no problem will be found. >> >> Any suggestion to debug this problem? Thanks. >> >> Jacky >> >> > --f46d04428158cb182c04ba172cd4 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Hi ,
=A0
I have faced similar issues before.
=A0
Not sure this will help. But please take a look at.
=A0
=A0
Thanks
Ans

On Mon, Feb 27, 2012 at 3:34 PM, Dennis.Yxun <dennis.yxun@gma= il.com> wrote:
HI:
=A0I'm encountered pretty = much the same problem here
=A0I'm tracing with current 3.3-rc4 branc= h(from ralf's tree)
=A0If I put rootfs at nand flash + highmem enabled, then execute problem ma= y give
illegal instruction error, bus error, try it again may run succes= s.
=A0but if I don't enable highmem, then problem is gone.
=A0any= hints? thanks

Dennis=20


On Mon, Nov 28, 2011 at 4:37 PM, Jacky Lam <l= amshuyin@gmail.com> wrote:
Hi,

=A0 =A0I am using mips-lin= ux-3.0.4 with HIGHMEM enabled. Everything is working fine, but I find somet= hing strange that when I execute a statically-linked binary through NFS mou= nted directory. It will gives me an illegal instruction error or =A0SIGSEGV= . If I run it again, the binary can run without problem. I have to reboot o= r drop all the vm cache in order to reproduce the error again.

=A0 Also, if I run the binary in harddisk or dynamically link the binar= y, no problem will be found.

=A0 =A0Any suggestion to debug this pro= blem? Tha