From david.daney@cavium.com Sat Oct 1 00:18:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Oct 2011 00:18:40 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19150 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491078Ab1I3WSg (ORCPT ); Sat, 1 Oct 2011 00:18:36 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 30 Sep 2011 15:19:15 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 30 Sep 2011 15:17:55 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 30 Sep 2011 15:17:54 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id p8UMHom9027319; Fri, 30 Sep 2011 15:17:50 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p8UMHnsU027318; Fri, 30 Sep 2011 15:17:49 -0700 From: David Daney To: netdev@vger.kernel.org, davem@davemloft.net Cc: linux-mips@linux-mips.org, David Daney , Greg Dietsche , "Uwe Kleine-Konig" , Giuseppe Cavallaro Subject: [PATCH] netdev/phy/icplus: Use mdiobus_write() and mdiobus_read() for proper locking. Date: Fri, 30 Sep 2011 15:17:48 -0700 Message-Id: <1317421068-27278-1-git-send-email-david.daney@cavium.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 30 Sep 2011 22:17:55.0306 (UTC) FILETIME=[CD605CA0:01CC7FBE] X-archive-position: 31189 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10 Status: RO Content-Length: 1857 Lines: 63 Usually you have to take the bus lock. Why not here too? I saw this when working on something else. Not even compile tested. Signed-off-by: David Daney Cc: Greg Dietsche Cc: "Uwe Kleine-Konig" Cc: Giuseppe Cavallaro --- drivers/net/phy/icplus.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index d4cbc29..bd4c740 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -42,36 +42,36 @@ static int ip175c_config_init(struct phy_device *phydev) if (full_reset_performed == 0) { /* master reset */ - err = phydev->bus->write(phydev->bus, 30, 0, 0x175c); + err = mdiobus_write(phydev->bus, 30, 0, 0x175c); if (err < 0) return err; /* ensure no bus delays overlap reset period */ - err = phydev->bus->read(phydev->bus, 30, 0); + err = mdiobus_read(phydev->bus, 30, 0); /* data sheet specifies reset period is 2 msec */ mdelay(2); /* enable IP175C mode */ - err = phydev->bus->write(phydev->bus, 29, 31, 0x175c); + err = mdiobus_write(phydev->bus, 29, 31, 0x175c); if (err < 0) return err; /* Set MII0 speed and duplex (in PHY mode) */ - err = phydev->bus->write(phydev->bus, 29, 22, 0x420); + err = mdiobus_write(phydev->bus, 29, 22, 0x420); if (err < 0) return err; /* reset switch ports */ for (i = 0; i < 5; i++) { - err = phydev->bus->write(phydev->bus, i, - MII_BMCR, BMCR_RESET); + err = mdiobus_write(phydev->bus, i, + MII_BMCR, BMCR_RESET); if (err < 0) return err; } for (i = 0; i < 5; i++) - err = phydev->bus->read(phydev->bus, i, MII_BMCR); + err = mdiobus_read(phydev->bus, i, MII_BMCR); mdelay(2); -- 1.7.2.3 From davem@davemloft.net Sat Oct 1 00:54:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Oct 2011 00:54:36 +0200 (CEST) Received: from shards.monkeyblade.net ([198.137.202.13]:57585 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491078Ab1I3Wyc (ORCPT ); Sat, 1 Oct 2011 00:54:32 +0200 Received: from localhost (cpe-66-65-62-183.nyc.res.rr.com [66.65.62.183]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id p8UMsLQQ028035 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 30 Sep 2011 15:54:26 -0700 Date: Fri, 30 Sep 2011 18:54:21 -0400 (EDT) Message-Id: <20110930.185421.252729993071152404.davem@davemloft.net> To: david.daney@cavium.com Cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] netdev/phy: Use mdiobus_read() so that proper locks are taken. From: David Miller In-Reply-To: <1317419482-25655-1-git-send-email-david.daney@cavium.com> References: <1317419482-25655-1-git-send-email-david.daney@cavium.com> X-Mailer: Mew version 6.3 on Emacs 23.2 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (shards.monkeyblade.net [198.137.202.13]); Fri, 30 Sep 2011 15:54:28 -0700 (PDT) X-archive-position: 31190 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 24 Content-Length: 414 Lines: 11 From: David Daney Date: Fri, 30 Sep 2011 14:51:22 -0700 > Accesses to the mdio busses must be done with the mdio_lock to ensure > proper operation. Conveniently we have the helper function > mdiobus_read() to do that for us. Lets use it in get_phy_id() instead > of accessing the bus without the lock held. > > Signed-off-by: David Daney Applied to net-next. From davem@davemloft.net Sat Oct 1 00:54:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Oct 2011 00:55:02 +0200 (CEST) Received: from shards.monkeyblade.net ([198.137.202.13]:57594 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491082Ab1I3Wyk (ORCPT ); Sat, 1 Oct 2011 00:54:40 +0200 Received: from localhost (cpe-66-65-62-183.nyc.res.rr.com [66.65.62.183]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id p8UMsYWU028048 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 30 Sep 2011 15:54:34 -0700 Date: Fri, 30 Sep 2011 18:54:33 -0400 (EDT) Message-Id: <20110930.185433.371029849281805679.davem@davemloft.net> To: david.daney@cavium.com Cc: netdev@vger.kernel.org, linux-mips@linux-mips.org, Gregory.Dietsche@cuw.edu, u.kleine-koenig@pengutronix.de, peppe.cavallaro@st.com Subject: Re: [PATCH] netdev/phy/icplus: Use mdiobus_write() and mdiobus_read() for proper locking. From: David Miller In-Reply-To: <1317421068-27278-1-git-send-email-david.daney@cavium.com> References: <1317421068-27278-1-git-send-email-david.daney@cavium.com> X-Mailer: Mew version 6.3 on Emacs 23.2 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (shards.monkeyblade.net [198.137.202.13]); Fri, 30 Sep 2011 15:54:36 -0700 (PDT) X-archive-position: 31191 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 25 Content-Length: 450 Lines: 13 From: David Daney Date: Fri, 30 Sep 2011 15:17:48 -0700 > Usually you have to take the bus lock. Why not here too? > > I saw this when working on something else. Not even compile tested. > > Signed-off-by: David Daney > Cc: Greg Dietsche > Cc: "Uwe Kleine-Konig" > Cc: Giuseppe Cavallaro Applied to net-next. From dhillf@gmail.com Sat Oct 1 07:19:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Oct 2011 07:20:07 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:62884 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491092Ab1JAFT7 (ORCPT ); Sat, 1 Oct 2011 07:19:59 +0200 Received: by wyi11 with SMTP id 11so2218072wyi.36 for ; Fri, 30 Sep 2011 22:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; bh=AmsZ2EystNIMyZwzo+LyfxyMI267J/UFIUOO7vctxNc=; b=TMlhiSJR2e2+F1ypyBthUqPgtX/ari1Md17DFO99I2oI8Hw3NAlj7Nv7jtMsxXu3kD EiaWeQIqodFD2u/oudufsoF6WGEj7mBu/Ux8Mk+wkCMDPZ7ZRlDpxrEuwazl/c2nO0GO MlptfS+TNs9rYWOZ+ouHpoChUPQ2jwB3oRNkI= MIME-Version: 1.0 Received: by 10.216.138.138 with SMTP id a10mr14962418wej.58.1317446393853; Fri, 30 Sep 2011 22:19:53 -0700 (PDT) Received: by 10.216.73.193 with HTTP; Fri, 30 Sep 2011 22:19:53 -0700 (PDT) Date: Sat, 1 Oct 2011 13:19:53 +0800 Message-ID: Subject: [RFC] count TLB refill for Netlogic XLR chip From: Hillf Danton To: linux-mips@linux-mips.org Cc: "Jayachandran C." , Ralf Baechle Content-Type: text/plain; charset=UTF-8 X-archive-position: 31192 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 111 Content-Length: 1315 Lines: 38 TLB miss is one of the concerned factors when tuning the performance of user applications, and there are on netlogic XLR chip eight 64-bit registers, c0 register 22 select 0-7, which could be used as temporary storage. One of them is used for counting TLB refill, and any comment is appreciated. Thanks Signed-off-by: Hillf Danton --- --- a/arch/mips/mm/tlbex.c Sat Aug 13 11:44:39 2011 +++ b/arch/mips/mm/tlbex.c Sat Oct 1 12:41:07 2011 @@ -1239,6 +1239,11 @@ static void __cpuinit build_r4000_tlb_re memset(relocs, 0, sizeof(relocs)); memset(final_handler, 0, sizeof(final_handler)); + if (current_cpu_type() == CPU_XLR) { + UASM_i_MFC0(p, K0, 22, 0); + UASM_i_ADDIU(p, K0, K0, 1); + UASM_i_MTC0(p, K0, 22, 0); + } if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) { htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, scratch_reg); --- a/arch/mips/lib/dump_tlb.c Sat May 14 15:21:02 2011 +++ b/arch/mips/lib/dump_tlb.c Sat Oct 1 12:46:19 2011 @@ -99,6 +99,10 @@ static void dump_tlb(int first, int last (entrylo1 & 1) ? 1 : 0); } } + if (current_cpu_type() == CPU_XLR) { + entrylo0 = __read_64bit_c0_register($22, 0); + printk("TLB refill count %llu\n", entrylo0); + } printk("\n"); write_c0_entryhi(s_entryhi); From dhillf@gmail.com Sat Oct 1 08:18:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Oct 2011 08:19:07 +0200 (CEST) Received: from mail-gy0-f177.google.com ([209.85.160.177]:46094 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491105Ab1JAGS4 (ORCPT ); Sat, 1 Oct 2011 08:18:56 +0200 Received: by gyg13 with SMTP id 13so2546058gyg.36 for ; Fri, 30 Sep 2011 23:18:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; bh=klyWNYQfqadrFJIISmSM/yAJlwgQy/oJz70EOEwGPjo=; b=aUAWCGs4hwYTs0E98FClDAbz3h+RBQvwnyNPzK3qIWdvi6+kB2ZWpMjiw2r/yDMWEa Tr3tRV95uWeVp8uxNzhyj6J2u36oVor52iu/0iCXLcAqNNi/2E0VrcpcZBPwdyI00/kH vVuTtDBhG6AvY7tQVyS/c8MS1ETk/GQXSDK9c= MIME-Version: 1.0 Received: by 10.236.175.98 with SMTP id y62mr40047732yhl.78.1317449929361; Fri, 30 Sep 2011 23:18:49 -0700 (PDT) Received: by 10.236.109.38 with HTTP; Fri, 30 Sep 2011 23:18:49 -0700 (PDT) Date: Sat, 1 Oct 2011 14:18:49 +0800 Message-ID: Subject: [RFC] activate performance counter registers on Netlogic XLR chip From: Hillf Danton To: linux-mips@linux-mips.org Cc: "Jayachandran C." , Ralf Baechle Content-Type: text/plain; charset=UTF-8 X-archive-position: 31193 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 119 Content-Length: 2395 Lines: 72 On Netlogic XLR chip two pairs of performance counter registers, perf_ctrl0: c0 reg 25 sel 0, perf_cntr0: c0 reg 25 sel 1 perf_ctrl1: c0 reg 25 sel 2, perf_cntr0: c0 reg 25 sel 3 provide a means for software to count processor events. At most 64 events can be counted, such as, Instruction fetched and retired, branch instructions Instruction and Data Cache Unit statistics Instruction and Data TLB statistics Instruction Fetch Unit statistics Instruction Execution Unit statistics Load/store Unit statistics Cycle Count They are activated based on the model of mips/74k, and any comment is appreciated. Thanks Signed-off-by: Hillf Danton --- --- a/arch/mips/oprofile/Makefile Tue Jul 12 21:50:26 2011 +++ b/arch/mips/oprofile/Makefile Sat Oct 1 13:44:28 2011 @@ -16,3 +16,4 @@ oprofile-$(CONFIG_CPU_R10000) += op_mod oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o +oprofile-$(CONFIG_CPU_XLR) += op_model_mipsxx.o --- a/arch/mips/oprofile/common.c Tue Jul 12 21:50:26 2011 +++ b/arch/mips/oprofile/common.c Sat Oct 1 13:45:23 2011 @@ -89,6 +89,7 @@ int __init oprofile_arch_init(struct opr case CPU_R10000: case CPU_R12000: case CPU_R14000: + case CPU_XLR: lmodel = &op_model_mipsxx_ops; break; --- a/arch/mips/oprofile/op_model_mipsxx.c Sat May 14 15:21:02 2011 +++ b/arch/mips/oprofile/op_model_mipsxx.c Sat Oct 1 13:50:26 2011 @@ -19,7 +19,11 @@ #define M_PERFCTL_SUPERVISOR (1UL << 2) #define M_PERFCTL_USER (1UL << 3) #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) +#ifdef CONFIG_CPU_XLR +#define M_PERFCTL_EVENT(event) ((((event) & 0x3f) << 5) | 0x2001) +#else #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) +#endif #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) #define M_PERFCTL_MT_EN(filter) ((filter) << 20) #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) @@ -264,6 +268,7 @@ static inline int n_counters(void) switch (current_cpu_type()) { case CPU_R10000: + case CPU_XLR: counters = 2; break; @@ -365,6 +370,9 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/sb1"; break; + case CPU_XLR: + op_model_mipsxx_ops.cpu_type = "mips/xlr"; + break; default: printk(KERN_ERR "Profiling unsupported for this CPU\n"); From jayachandranc@netlogicmicro.com Sat Oct 1 09:43:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Oct 2011 09:43:15 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:4198 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491130Ab1JAHnH (ORCPT ); Sat, 1 Oct 2011 09:43:07 +0200 X-TM-IMSS-Message-ID: <46d24d3d00010283@netlogicmicro.com> Received: from hqcas01.netlogicmicro.com ([10.10.50.14]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0; TLS: TLSv1/SSLv3,128bits,AES128-SHA) id 46d24d3d00010283 ; Sat, 1 Oct 2011 00:42:59 -0700 Date: Sat, 1 Oct 2011 13:09:36 +0530 From: Jayachandran C. To: Hillf Danton CC: , Ralf Baechle Subject: Re: [RFC] count TLB refill for Netlogic XLR chip Message-ID: <20111001073936.GA15674@jayachandranc.netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 01 Oct 2011 07:39:36.0568 (UTC) FILETIME=[44E4D780:01CC800D] X-archive-position: 31194 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 129 Content-Length: 1980 Lines: 54 On Sat, Oct 01, 2011 at 01:19:53PM +0800, Hillf Danton wrote: > TLB miss is one of the concerned factors when tuning the performance of user > applications, and there are on netlogic XLR chip eight 64-bit registers, > c0 register 22 select 0-7, which could be used as temporary storage. > > One of them is used for counting TLB refill, and any comment is appreciated. > Few comments: Adding this unconditionally will add overhead to the TLB refill handler, this should be probably controlled by a boot-time variable, or with some perf/profile framework. If you have access to our SDK, it uses register 22,2 for counting TLB misses it would be good to retain that compability, otherwise it will mess up when we merge this back to our internal code. The reporting part currently will only print the misses on a crash (if I am not mistaken), again this has to be tied in with some standard framework. > Signed-off-by: Hillf Danton > --- > > --- a/arch/mips/mm/tlbex.c Sat Aug 13 11:44:39 2011 > +++ b/arch/mips/mm/tlbex.c Sat Oct 1 12:41:07 2011 > @@ -1239,6 +1239,11 @@ static void __cpuinit build_r4000_tlb_re > memset(relocs, 0, sizeof(relocs)); > memset(final_handler, 0, sizeof(final_handler)); > > + if (current_cpu_type() == CPU_XLR) { > + UASM_i_MFC0(p, K0, 22, 0); > + UASM_i_ADDIU(p, K0, K0, 1); > + UASM_i_MTC0(p, K0, 22, 0); > + } > if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) { > htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, > scratch_reg); > --- a/arch/mips/lib/dump_tlb.c Sat May 14 15:21:02 2011 > +++ b/arch/mips/lib/dump_tlb.c Sat Oct 1 12:46:19 2011 > @@ -99,6 +99,10 @@ static void dump_tlb(int first, int last > (entrylo1 & 1) ? 1 : 0); > } > } > + if (current_cpu_type() == CPU_XLR) { > + entrylo0 = __read_64bit_c0_register($22, 0); > + printk("TLB refill count %llu\n", entrylo0); > + } > printk("\n"); > > write_c0_entryhi(s_entryhi); JC. From jayachandranc@netlogicmicro.com Sat Oct 1 10:18:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Oct 2011 10:18:25 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:3169 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491157Ab1JAISS (ORCPT ); Sat, 1 Oct 2011 10:18:18 +0200 X-TM-IMSS-Message-ID: <46f28190000102de@netlogicmicro.com> Received: from hqcas01.netlogicmicro.com ([10.10.50.14]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0; TLS: TLSv1/SSLv3,128bits,AES128-SHA) id 46f28190000102de ; Sat, 1 Oct 2011 01:18:09 -0700 Date: Sat, 1 Oct 2011 13:48:02 +0530 From: Jayachandran C. To: Hillf Danton CC: , Ralf Baechle Subject: Re: [RFC] activate performance counter registers on Netlogic XLR chip Message-ID: <20111001081801.GB15674@jayachandranc.netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 01 Oct 2011 08:17:58.0397 (UTC) FILETIME=[A0E412D0:01CC8012] X-archive-position: 31195 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 134 Content-Length: 958 Lines: 25 On Sat, Oct 01, 2011 at 02:18:49PM +0800, Hillf Danton wrote: > On Netlogic XLR chip two pairs of performance counter registers, > > perf_ctrl0: c0 reg 25 sel 0, perf_cntr0: c0 reg 25 sel 1 > perf_ctrl1: c0 reg 25 sel 2, perf_cntr0: c0 reg 25 sel 3 > > provide a means for software to count processor events. > > At most 64 events can be counted, such as, > Instruction fetched and retired, branch instructions > Instruction and Data Cache Unit statistics > Instruction and Data TLB statistics > Instruction Fetch Unit statistics > Instruction Execution Unit statistics > Load/store Unit statistics > Cycle Count > > They are activated based on the model of mips/74k, and > any comment is appreciated. I have not looked at 74k, but on XLR there is only one set of perf counter registers in a core (or 4 hardware threads). These perf counters can count either the events on one thread or all of the threads put together. JC. From dhillf@gmail.com Sun Oct 2 09:13:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Oct 2011 09:13:42 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:42020 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490993Ab1JBHNf (ORCPT ); Sun, 2 Oct 2011 09:13:35 +0200 Received: by wyi11 with SMTP id 11so2921582wyi.36 for ; Sun, 02 Oct 2011 00:13:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=InfL9PfFLh7NXF75ElkvYYLBfxg1FvvPycS5vaOkt8M=; b=pAwkfxtruTkfyXVdiDIEHCnsRmzaFUU9VsydV/wH2yfn547+DnLgTEU92R/XiqEZWO HZEjjmQgIteW41NeTplA+oG/wiszcgF0N0G4n9cr1t+YzNVQZhCBr4ndZSceyDH3EzXB ArPZX8vMLo1CGViLHEotOkQQFL3JmPzNjCx98= MIME-Version: 1.0 Received: by 10.216.230.2 with SMTP id i2mr1869147weq.28.1317539609717; Sun, 02 Oct 2011 00:13:29 -0700 (PDT) Received: by 10.216.73.193 with HTTP; Sun, 2 Oct 2011 00:13:29 -0700 (PDT) In-Reply-To: <20111001073936.GA15674@jayachandranc.netlogicmicro.com> References: <20111001073936.GA15674@jayachandranc.netlogicmicro.com> Date: Sun, 2 Oct 2011 15:13:29 +0800 Message-ID: Subject: Re: [RFC] count TLB refill for Netlogic XLR chip From: Hillf Danton To: "Jayachandran C." Cc: linux-mips@linux-mips.org, Ralf Baechle Content-Type: text/plain; charset=UTF-8 X-archive-position: 31196 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 428 Content-Length: 1206 Lines: 35 On Sat, Oct 1, 2011 at 3:39 PM, Jayachandran C. wrote: > On Sat, Oct 01, 2011 at 01:19:53PM +0800, Hillf Danton wrote: >> TLB miss is one of the concerned factors when tuning the performance of user >> applications, and there are on netlogic XLR chip eight 64-bit registers, >> c0 register 22 select 0-7, which could be used as temporary storage. >> >> One of them is used for counting TLB refill, and any comment is appreciated. >> > > Few comments: > > Adding this unconditionally will add overhead to the TLB refill handler, this > should be probably controlled by a boot-time variable, or with some > perf/profile framework. > Boot-time variable will be added. > If you have access to our SDK, it uses register 22,2 for counting TLB misses > it would be good to retain that compability, otherwise it will mess up when > we merge this back to our internal code. > It is clear for all users if the usage of reg 22 is defined in , say, mips-extns.h? > The reporting part currently will only print the misses on a crash (if I am > not mistaken), again this has to be tied in with some standard framework. > How about one line added in /proc/interrupts? Thanks Hillf From dhillf@gmail.com Sun Oct 2 09:21:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Oct 2011 09:22:04 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:43352 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490993Ab1JBHV7 convert rfc822-to-8bit (ORCPT ); Sun, 2 Oct 2011 09:21:59 +0200 Received: by wwf27 with SMTP id 27so3529300wwf.24 for ; Sun, 02 Oct 2011 00:21:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=euy7Hl4NzFcXDUOHfEVex9cOLdl6lYeJ0kj/bD0cG1U=; b=OPycXfhDCN4bBLefH9LuptFq2MmFMy9BSGv/g0tVIZEAn4xebnn6RYnYp8oLMCZJk4 d3KpfdjNuQ2L/GzZhCDpdoCokdpCQdvrErntjvO4sazw3njkfHgZOTCIneqcqWfjKcui 976vpt2cpJxEgmP1OE4tlA04E0zzUuppWiqpQ= MIME-Version: 1.0 Received: by 10.216.80.90 with SMTP id j68mr15681062wee.28.1317540113558; Sun, 02 Oct 2011 00:21:53 -0700 (PDT) Received: by 10.216.73.193 with HTTP; Sun, 2 Oct 2011 00:21:53 -0700 (PDT) In-Reply-To: <20111001081801.GB15674@jayachandranc.netlogicmicro.com> References: <20111001081801.GB15674@jayachandranc.netlogicmicro.com> Date: Sun, 2 Oct 2011 15:21:53 +0800 Message-ID: Subject: Re: [RFC] activate performance counter registers on Netlogic XLR chip From: Hillf Danton To: "Jayachandran C." Cc: linux-mips@linux-mips.org, Ralf Baechle Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 31197 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 432 Content-Length: 1219 Lines: 32 On Sat, Oct 1, 2011 at 4:18 PM, Jayachandran C. wrote: > On Sat, Oct 01, 2011 at 02:18:49PM +0800, Hillf Danton wrote: >> On Netlogic XLR chip two pairs of performance counter registers, >> >>    perf_ctrl0: c0 reg 25 sel 0, perf_cntr0: c0 reg 25 sel 1 >>    perf_ctrl1: c0 reg 25 sel 2, perf_cntr0: c0 reg 25 sel 3 >> >> provide a means for software to count processor events. >> >> At most 64 events can be counted, such as, >>    Instruction fetched and retired, branch instructions >>    Instruction and Data Cache Unit statistics >>    Instruction and Data TLB statistics >>    Instruction Fetch Unit statistics >>    Instruction Execution Unit statistics >>    Load/store Unit statistics >>    Cycle Count >> >> They are activated based on the model of mips/74k, and >> any comment is appreciated. > > I have not looked at 74k, but on XLR there is only one set of perf counter > registers in a core (or 4 hardware threads). These perf counters can count > either the events on one thread or all of the threads put together. > It is encoded in the patch to count events on all threads. Yeah it is better to count events according to user's favor. Thanks Hillf From dhillf@gmail.com Sun Oct 2 09:26:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Oct 2011 09:26:25 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:43918 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491090Ab1JBH0T (ORCPT ); Sun, 2 Oct 2011 09:26:19 +0200 Received: by wyi11 with SMTP id 11so2926509wyi.36 for ; Sun, 02 Oct 2011 00:26:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; bh=RnzzuiM1xlTgkKgoGcttznR78IK9iRhzSWhPQX/QtcA=; b=woP3lIZ2cNdBnHFVlhAGJz/H+ww1JCbE1IzVqKl/Tu+Ai0x1lU1XBai0KgMgwag61f q1WvKhrmUUXApybqZP/LRzDC0Bp7v91JtgMruIpTdQ4Y92UorPPVAXvnY7EzhZW1dteh 2HslDxrj+3Cw+bl1XphX46OdLUhoLWI01QGPg= MIME-Version: 1.0 Received: by 10.216.198.84 with SMTP id u62mr11990528wen.13.1317540374092; Sun, 02 Oct 2011 00:26:14 -0700 (PDT) Received: by 10.216.73.193 with HTTP; Sun, 2 Oct 2011 00:26:14 -0700 (PDT) Date: Sun, 2 Oct 2011 15:26:14 +0800 Message-ID: Subject: [RFC] mark Netlogic XLR chip as SMT capable From: Hillf Danton To: linux-mips@linux-mips.org Cc: "Jayachandran C." , Ralf Baechle Content-Type: text/plain; charset=UTF-8 X-archive-position: 31198 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 433 Content-Length: 1164 Lines: 37 Netlogic XLR chip has multiple cores. Each core includes four integrated hardware threads, and they share L1 data and instruction caches. If XLR chip is marked to be SMT capable, linux scheduler then could do more, say idle load balancing. Any comment is welcom, thanks. Signed-off-by: Hillf Danton --- --- a/arch/mips/netlogic/xlr/smp.c Sun Oct 2 14:15:28 2011 +++ b/arch/mips/netlogic/xlr/smp.c Sun Oct 2 14:15:58 2011 @@ -176,6 +176,7 @@ void __init nlm_smp_setup(void) void nlm_prepare_cpus(unsigned int max_cpus) { + smp_num_siblings = 4; } struct plat_smp_ops nlm_smp_ops = { --- a/arch/mips/kernel/smp.c Sun Oct 2 14:12:09 2011 +++ b/arch/mips/kernel/smp.c Sun Oct 2 14:14:58 2011 @@ -73,7 +73,12 @@ static inline void set_cpu_sibling_map(i if (smp_num_siblings > 1) { for_each_cpu_mask(i, cpu_sibling_setup_map) { - if (cpu_data[cpu].core == cpu_data[i].core) { + if (current_cpu_type() == CPU_XLR) { + if (((i>>2) & 0x7) == ((cpu>>2) & 0x7)) + goto set; + } + else if (cpu_data[cpu].core == cpu_data[i].core) { +set: cpu_set(i, cpu_sibling_map[cpu]); cpu_set(cpu, cpu_sibling_map[i]); } From jayachandranc@netlogicmicro.com Sun Oct 2 10:30:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Oct 2011 10:31:03 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:1529 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491124Ab1JBIa4 (ORCPT ); Sun, 2 Oct 2011 10:30:56 +0200 X-TM-IMSS-Message-ID: <4c2468c30001169f@netlogicmicro.com> Received: from hqcas01.netlogicmicro.com ([10.10.50.14]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0; TLS: TLSv1/SSLv3,128bits,AES128-SHA) id 4c2468c30001169f ; Sun, 2 Oct 2011 01:30:47 -0700 Date: Sun, 2 Oct 2011 14:00:45 +0530 From: Jayachandran C. To: Hillf Danton CC: , Ralf Baechle Subject: Re: [RFC] mark Netlogic XLR chip as SMT capable Message-ID: <20111002083044.GA23668@jayachandranc.netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 02 Oct 2011 08:30:46.0629 (UTC) FILETIME=[9534B950:01CC80DD] X-archive-position: 31199 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 441 Content-Length: 1460 Lines: 44 On Sun, Oct 02, 2011 at 03:26:14PM +0800, Hillf Danton wrote: > Netlogic XLR chip has multiple cores. Each core includes four integrated > hardware threads, and they share L1 data and instruction caches. > > If XLR chip is marked to be SMT capable, linux scheduler then could do more, > say idle load balancing. > > Any comment is welcom, thanks. I may be missing something here, but how about just setting cpu_data[].core in the init_secondary method? That would avoid the change to kernel/smp.c. > > Signed-off-by: Hillf Danton > --- > > --- a/arch/mips/netlogic/xlr/smp.c Sun Oct 2 14:15:28 2011 > +++ b/arch/mips/netlogic/xlr/smp.c Sun Oct 2 14:15:58 2011 > @@ -176,6 +176,7 @@ void __init nlm_smp_setup(void) > > void nlm_prepare_cpus(unsigned int max_cpus) > { > + smp_num_siblings = 4; > } > > struct plat_smp_ops nlm_smp_ops = { > --- a/arch/mips/kernel/smp.c Sun Oct 2 14:12:09 2011 > +++ b/arch/mips/kernel/smp.c Sun Oct 2 14:14:58 2011 > @@ -73,7 +73,12 @@ static inline void set_cpu_sibling_map(i > > if (smp_num_siblings > 1) { > for_each_cpu_mask(i, cpu_sibling_setup_map) { > - if (cpu_data[cpu].core == cpu_data[i].core) { > + if (current_cpu_type() == CPU_XLR) { > + if (((i>>2) & 0x7) == ((cpu>>2) & 0x7)) > + goto set; > + } > + else if (cpu_data[cpu].core == cpu_data[i].core) { > +set: > cpu_set(i, cpu_sibling_map[cpu]); > cpu_set(cpu, cpu_sibling_map[i]); > } JC. From dhillf@gmail.com Mon Oct 3 07:46:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Oct 2011 07:46:59 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:57089 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491142Ab1JCFqv convert rfc822-to-8bit (ORCPT ); Mon, 3 Oct 2011 07:46:51 +0200 Received: by wyi11 with SMTP id 11so3579596wyi.36 for ; Sun, 02 Oct 2011 22:46:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=B3kH5w8m1x19xBpyvNUdel9KeWwwoPxxWU1meVHo8mU=; b=YvC8Qxh90tybaVZPz1WNq/OajpzewZyi0xZSzPFgl4lXvuhW5WZMMVvOtV8Iz848PP 1vmX5YOIWxV+5FaAgQVEi2VqCQXGBpWLEbwtXTd2nGq0uCDXO1oHGoOCy31pOo3KpwZ1 egoPRAZM1Q3Jg2OUAW158wd9mLIdpwvSFAPyw= MIME-Version: 1.0 Received: by 10.216.230.2 with SMTP id i2mr2891191weq.28.1317620806260; Sun, 02 Oct 2011 22:46:46 -0700 (PDT) Received: by 10.216.73.193 with HTTP; Sun, 2 Oct 2011 22:46:46 -0700 (PDT) In-Reply-To: <20111002083044.GA23668@jayachandranc.netlogicmicro.com> References: <20111002083044.GA23668@jayachandranc.netlogicmicro.com> Date: Mon, 3 Oct 2011 13:46:46 +0800 Message-ID: Subject: Re: [RFC] mark Netlogic XLR chip as SMT capable From: Hillf Danton To: "Jayachandran C." Cc: linux-mips@linux-mips.org, Ralf Baechle Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 31200 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 798 Content-Length: 1751 Lines: 56 On Sun, Oct 2, 2011 at 4:30 PM, Jayachandran C. wrote: > On Sun, Oct 02, 2011 at 03:26:14PM +0800, Hillf Danton wrote: >> Netlogic XLR chip has multiple cores. Each core includes four integrated >> hardware threads, and they share L1 data and instruction caches. >> >> If XLR chip is marked to be SMT capable, linux scheduler then could do more, >> say idle load balancing. >> >> Any comment is welcom, thanks. > > I may be missing something here, but how about just setting cpu_data[].core in > the init_secondary method?  That would avoid the change to kernel/smp.c. > Got and thanks. It is re-prepared as the following:) Hillf ---------------------------------------------------------------------------- Subject: [RFC] Mark Netlogic XLR chip to be SMT capable Netlogic XLR chip has multiple cores. Each core includes four integrated hardware threads, and they share L1 data and instruction caches. If XLR chip is marked to be SMT capable, scheduler then could do more, say, idle load balancing. According to JC's comment changes are now confined only to the code of XLR. Signed-off-by: Hillf Danton --- --- a/arch/mips/netlogic/xlr/smp.c Sun Oct 2 14:15:28 2011 +++ b/arch/mips/netlogic/xlr/smp.c Mon Oct 3 13:33:02 2011 @@ -104,6 +104,12 @@ void nlm_early_init_secondary(void) */ static void __cpuinit nlm_init_secondary(void) { + unsigned int cpu, core_id; + + cpu = smp_processor_id(); + core_id = (cpu >> 2) & 0x7; + cpu_data[cpu].core = core_id; + nlm_smp_irq_init(); } @@ -176,6 +182,8 @@ void __init nlm_smp_setup(void) void nlm_prepare_cpus(unsigned int max_cpus) { + /* declare we are SMT capable */ + smp_num_siblings = 4; } struct plat_smp_ops nlm_smp_ops = { From ralf@linux-mips.org Mon Oct 3 12:32:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Oct 2011 12:32:10 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52337 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491871Ab1JCKcG (ORCPT ); Mon, 3 Oct 2011 12:32:06 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p93AW47W012644; Mon, 3 Oct 2011 11:32:04 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p93AW4cX012642; Mon, 3 Oct 2011 11:32:04 +0100 Date: Mon, 3 Oct 2011 11:32:04 +0100 From: Ralf Baechle To: Hillf Danton Cc: "Jayachandran C." , linux-mips@linux-mips.org Subject: Re: [RFC] mark Netlogic XLR chip as SMT capable Message-ID: <20111003103204.GC6038@linux-mips.org> References: <20111002083044.GA23668@jayachandranc.netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31201 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 952 Content-Length: 454 Lines: 14 On Mon, Oct 03, 2011 at 01:46:46PM +0800, Hillf Danton wrote: > + unsigned int cpu, core_id; > + > + cpu = smp_processor_id(); > + core_id = (cpu >> 2) & 0x7; > + cpu_data[cpu].core = core_id; This is going to break in setups where Linux is not being booted on what the hardware considers CPU core 0. Which is not uncommon in embedded setups. You may want to probe the hardware for the core ID rather than relying on smp_processor_id() here. Ralf From jayachandranc@netlogicmicro.com Mon Oct 3 12:39:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Oct 2011 12:39:56 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:1362 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491881Ab1JCKjj (ORCPT ); Mon, 3 Oct 2011 12:39:39 +0200 X-TM-IMSS-Message-ID: <51c099400001312a@netlogicmicro.com> Received: from hqcas01.netlogicmicro.com ([10.10.50.14]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0; TLS: TLSv1/SSLv3,128bits,AES128-SHA) id 51c099400001312a ; Mon, 3 Oct 2011 03:39:29 -0700 Date: Mon, 3 Oct 2011 16:09:36 +0530 From: Jayachandran C. To: Ralf Baechle CC: Hillf Danton , Subject: Re: [RFC] mark Netlogic XLR chip as SMT capable Message-ID: <20111003103935.GA6016@jayachandranc.netlogicmicro.com> References: <20111002083044.GA23668@jayachandranc.netlogicmicro.com> <20111003103204.GC6038@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20111003103204.GC6038@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 03 Oct 2011 10:39:29.0363 (UTC) FILETIME=[BABA2A30:01CC81B8] X-archive-position: 31202 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 955 Content-Length: 733 Lines: 21 On Mon, Oct 03, 2011 at 11:32:04AM +0100, Ralf Baechle wrote: > On Mon, Oct 03, 2011 at 01:46:46PM +0800, Hillf Danton wrote: > > > + unsigned int cpu, core_id; > > + > > + cpu = smp_processor_id(); > > + core_id = (cpu >> 2) & 0x7; > > + cpu_data[cpu].core = core_id; > > This is going to break in setups where Linux is not being booted on > what the hardware considers CPU core 0. Which is not uncommon in embedded > setups. You may want to probe the hardware for the core ID rather than > relying on smp_processor_id() here. Yes, the function hard_smp_processor_id() from netlogic/mips-extns.h has to be used here. This also conflicts with the recent patch-set for XLP support, but I don't know the status of that yet. JC. From venkat.subbiah@caviumnetworks.com Mon Oct 3 22:27:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Oct 2011 22:27:55 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:7697 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491905Ab1JCU1s (ORCPT ); Mon, 3 Oct 2011 22:27:48 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 03 Oct 2011 13:28:56 -0700 Received: from casmarthost.caveonetworks.com ([192.168.16.225]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 3 Oct 2011 13:27:39 -0700 Received: from localhost (webpowersw-sdk106.caveonetworks.com [10.18.162.106]) by casmarthost.caveonetworks.com (8.13.8/8.13.8) with ESMTP id p93KRbQm016177; Mon, 3 Oct 2011 13:27:39 -0700 From: Venkat Subbiah To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: linux-rt-users@vger.kernel.org, david.daney@cavium.com Subject: 0001-MIPS-Octeon-Mark-SMP-IPI-interrupt-as-IRQF_NO_THREAD.patch Date: Mon, 3 Oct 2011 13:26:44 -0700 Message-Id: <1317673604-10554-1-git-send-email-venkat.subbiah@caviumnetworks.com> X-Mailer: git-send-email 1.7.0.4 X-OriginalArrivalTime: 03 Oct 2011 20:27:40.0095 (UTC) FILETIME=[E5A484F0:01CC820A] X-archive-position: 31203 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: venkat.subbiah@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1513 Content-Length: 0 Lines: 0 From venkat.subbiah@caviumnetworks.com Mon Oct 3 22:32:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Oct 2011 22:32:18 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:7805 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491905Ab1JCUcJ (ORCPT ); Mon, 3 Oct 2011 22:32:09 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 03 Oct 2011 13:33:22 -0700 Received: from casmarthost.caveonetworks.com ([192.168.16.225]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 3 Oct 2011 13:32:05 -0700 Received: from localhost (webpowersw-sdk106.caveonetworks.com [10.18.162.106]) by casmarthost.caveonetworks.com (8.13.8/8.13.8) with ESMTP id p93KW3GB016316; Mon, 3 Oct 2011 13:32:05 -0700 From: Venkat Subbiah To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: linux-rt-users@vger.kernel.org, david.daney@cavium.com Subject: [PATCH] MIPS: Octeon: Mark SMP-IPI interrupt as IRQF_NO_THREAD Date: Mon, 3 Oct 2011 13:31:10 -0700 Message-Id: <1317673870-10671-1-git-send-email-venkat.subbiah@caviumnetworks.com> X-Mailer: git-send-email 1.7.0.4 X-OriginalArrivalTime: 03 Oct 2011 20:32:05.0819 (UTC) FILETIME=[8406C8B0:01CC820B] X-archive-position: 31204 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: venkat.subbiah@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1519 Content-Length: 1100 Lines: 33 From: Venkat Subbiah This is to exclude it from force threading to allow RT patch set to work. And while on this line * Remove IRQF_DISABLED as as this flag is NOOP * Add IRQF_PERCPU as this is a per cpu interrupt. Signed-off-by: Venkat Subbiah Acked-by: David Daney --- arch/mips/cavium-octeon/smp.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 8b60642..efcfff4 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -207,8 +207,9 @@ void octeon_prepare_cpus(unsigned int max_cpus) * the other bits alone. */ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); - if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, - "SMP-IPI", mailbox_interrupt)) { + if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, + IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", + mailbox_interrupt)) { panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); } } -- 1.7.0.4 From tglx@linutronix.de Mon Oct 3 23:45:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Oct 2011 23:45:08 +0200 (CEST) Received: from www.linutronix.de ([62.245.132.108]:48848 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491907Ab1JCVpC (ORCPT ); Mon, 3 Oct 2011 23:45:02 +0200 Received: from localhost ([127.0.0.1]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1RAqJY-0007rh-K9; Mon, 03 Oct 2011 23:44:44 +0200 Date: Mon, 3 Oct 2011 23:44:43 +0200 (CEST) From: Thomas Gleixner To: Venkat Subbiah cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-rt-users@vger.kernel.org, david.daney@cavium.com Subject: Re: [PATCH] MIPS: Octeon: Mark SMP-IPI interrupt as IRQF_NO_THREAD In-Reply-To: <1317673870-10671-1-git-send-email-venkat.subbiah@caviumnetworks.com> Message-ID: References: <1317673870-10671-1-git-send-email-venkat.subbiah@caviumnetworks.com> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 X-archive-position: 31205 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tglx@linutronix.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1586 Content-Length: 465 Lines: 17 On Mon, 3 Oct 2011, Venkat Subbiah wrote: > From: Venkat Subbiah > > This is to exclude it from force threading to allow RT patch set to work. > And while on this line > * Remove IRQF_DISABLED as as this flag is NOOP > * Add IRQF_PERCPU as this is a per cpu interrupt. > > > Signed-off-by: Venkat Subbiah > Acked-by: David Daney Acked-by: Thomas Gleixner From venkat.subbiah@cavium.com Tue Oct 4 01:31:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Oct 2011 01:31:43 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13332 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491909Ab1JCXbg (ORCPT ); Tue, 4 Oct 2011 01:31:36 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 03 Oct 2011 16:32:45 -0700 Received: from casmarthost.caveonetworks.com ([192.168.16.225]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 3 Oct 2011 16:31:25 -0700 Received: from localhost (webpowersw-sdk106.caveonetworks.com [10.18.162.106]) by casmarthost.caveonetworks.com (8.13.8/8.13.8) with ESMTP id p93NVLTW022242; Mon, 3 Oct 2011 16:31:23 -0700 From: Venkat Subbiah To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: linux-rt-users@vger.kernel.org, david.daney@cavium.com Subject: [PATCH] MIPS: Octeon: Mark octeon_wdt interrupt as IRQF_NO_THREAD Date: Mon, 3 Oct 2011 16:30:28 -0700 Message-Id: <1317684628-17488-1-git-send-email-venkat.subbiah@cavium.com> X-Mailer: git-send-email 1.7.0.4 X-OriginalArrivalTime: 03 Oct 2011 23:31:25.0100 (UTC) FILETIME=[910EC6C0:01CC8224] X-archive-position: 31206 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: venkat.subbiah@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1636 Content-Length: 1207 Lines: 33 This is to exclude it from force threading to allow RT patch set to work. The watchdog timers are per-CPU and the addresses of register that reset the timer are calculated based on the current CPU. Therefore we cannot allow it to run on a thread on a different CPU. Also we only do a single register write, which is much faster than scheduling a handler thread. And while on this line remove IRQF_DISABLED as this flag is a NOP. Signed-off-by: Venkat Subbiah Acked-by: David Daney --- drivers/watchdog/octeon-wdt-main.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/watchdog/octeon-wdt-main.c b/drivers/watchdog/octeon-wdt-main.c index 945ee83..7c0d863 100644 --- a/drivers/watchdog/octeon-wdt-main.c +++ b/drivers/watchdog/octeon-wdt-main.c @@ -402,7 +402,7 @@ static void octeon_wdt_setup_interrupt(int cpu) irq = OCTEON_IRQ_WDOG0 + core; if (request_irq(irq, octeon_wdt_poke_irq, - IRQF_DISABLED, "octeon_wdt", octeon_wdt_poke_irq)) + IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) panic("octeon_wdt: Couldn't obtain irq %d", irq); cpumask_set_cpu(cpu, &irq_enabled_cpus); -- 1.7.0.4 From venkat.subbiah@cavium.com Tue Oct 4 02:23:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Oct 2011 02:23:13 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14435 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490951Ab1JDAXE (ORCPT ); Tue, 4 Oct 2011 02:23:04 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 03 Oct 2011 17:24:16 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 3 Oct 2011 17:22:59 -0700 Received: from [10.18.162.106] ([64.2.3.195]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 3 Oct 2011 17:22:59 -0700 Message-ID: <4E8A51AC.8060905@cavium.com> Date: Mon, 03 Oct 2011 17:22:04 -0700 From: Venkat Subbiah User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Wim Van Sebroeck CC: linux-rt-users@vger.kernel.org, david.daney@cavium.com Subject: Re: [PATCH] MIPS: Octeon: Mark octeon_wdt interrupt as IRQF_NO_THREAD References: <1317684628-17488-1-git-send-email-venkat.subbiah@cavium.com> In-Reply-To: <1317684628-17488-1-git-send-email-venkat.subbiah@cavium.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 04 Oct 2011 00:22:59.0284 (UTC) FILETIME=[C555C940:01CC822B] X-archive-position: 31207 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: venkat.subbiah@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1663 Content-Length: 1397 Lines: 36 On 10/03/2011 04:30 PM, Venkat Subbiah wrote: > This is to exclude it from force threading to allow RT patch set to work. > > The watchdog timers are per-CPU and the addresses of register that reset > the timer are calculated based on the current CPU. Therefore we cannot > allow it to run on a thread on a different CPU. Also we only do a > single register write, which is much faster than scheduling a handler > thread. > > And while on this line remove IRQF_DISABLED as this flag is a NOP. > > > Signed-off-by: Venkat Subbiah > Acked-by: David Daney > --- > drivers/watchdog/octeon-wdt-main.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/watchdog/octeon-wdt-main.c b/drivers/watchdog/octeon-wdt-main.c > index 945ee83..7c0d863 100644 > --- a/drivers/watchdog/octeon-wdt-main.c > +++ b/drivers/watchdog/octeon-wdt-main.c > @@ -402,7 +402,7 @@ static void octeon_wdt_setup_interrupt(int cpu) > irq = OCTEON_IRQ_WDOG0 + core; > > if (request_irq(irq, octeon_wdt_poke_irq, > - IRQF_DISABLED, "octeon_wdt", octeon_wdt_poke_irq)) > + IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) > panic("octeon_wdt: Couldn't obtain irq %d", irq); > > cpumask_set_cpu(cpu,&irq_enabled_cpus); Sending it to kernel watchdog maintainers. Forgot to include them in the prior email. Thanks, Venkat From dhillf@gmail.com Tue Oct 4 12:48:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Oct 2011 12:48:40 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:39172 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491023Ab1JDKsb convert rfc822-to-8bit (ORCPT ); Tue, 4 Oct 2011 12:48:31 +0200 Received: by wyi11 with SMTP id 11so421709wyi.36 for ; Tue, 04 Oct 2011 03:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=mxfpB5gv2gHxW7ila+ZnxFT+ITcEz/4F7/5YrbfXoPc=; b=X6T5LePl551KrqKQa/Z8KgbaSEg70y9QQifk7Aor0tzeyP/3bbwYX2zloVbuqiswIP crbDKWUq3W1pJvf990qNXydsBRQqknnZqcHM5stp/O5RBfJQukjrJ6Pk3WHqLvFLnapi ZLClaqf5+ksi3G+BPed3tBHbNRbYQfZmyvT7Q= MIME-Version: 1.0 Received: by 10.216.229.91 with SMTP id g69mr1312606weq.13.1317725305866; Tue, 04 Oct 2011 03:48:25 -0700 (PDT) Received: by 10.216.73.193 with HTTP; Tue, 4 Oct 2011 03:48:25 -0700 (PDT) In-Reply-To: <20111003103935.GA6016@jayachandranc.netlogicmicro.com> References: <20111002083044.GA23668@jayachandranc.netlogicmicro.com> <20111003103204.GC6038@linux-mips.org> <20111003103935.GA6016@jayachandranc.netlogicmicro.com> Date: Tue, 4 Oct 2011 18:48:25 +0800 Message-ID: Subject: Re: [RFC] mark Netlogic XLR chip as SMT capable From: Hillf Danton To: "Jayachandran C." Cc: Ralf Baechle , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 31208 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1901 Content-Length: 2054 Lines: 65 On Mon, Oct 3, 2011 at 6:39 PM, Jayachandran C. wrote: > On Mon, Oct 03, 2011 at 11:32:04AM +0100, Ralf Baechle wrote: >> On Mon, Oct 03, 2011 at 01:46:46PM +0800, Hillf Danton wrote: >> >> > +   unsigned int cpu, core_id; >> > + >> > +   cpu = smp_processor_id(); >> > +   core_id = (cpu >> 2) & 0x7; >> > +   cpu_data[cpu].core = core_id; >> >> This is going to break in setups where Linux is not being booted on >> what the hardware considers CPU core 0.  Which is not uncommon in embedded >> setups.  You may want to probe the hardware for the core ID rather than >> relying on smp_processor_id() here. > > Yes, the function hard_smp_processor_id() from netlogic/mips-extns.h has to > be used here. > > This also conflicts with the recent patch-set for XLP support, but I don't > know the status of that yet. > Thanks JC and Ralf. Your comments are included in the following version. Hillf ---------------------------------------------------------------------------- Subject: [RFC] Mark Netlogic XLR chip to be SMT capable Netlogic XLR chip has multiple cores. Each core includes four integrated hardware threads, and they share L1 data and instruction caches. If the chip is marked to be SMT capable, scheduler then could do more, say, idle load balancing. Changes are now confined only to the code of XLR, and hardware is probed to get core ID for correct setup. Signed-off-by: Hillf Danton --- --- a/arch/mips/netlogic/xlr/smp.c Sun Oct 2 14:15:28 2011 +++ b/arch/mips/netlogic/xlr/smp.c Mon Oct 3 13:33:02 2011 @@ -104,6 +104,12 @@ void nlm_early_init_secondary(void) */ static void __cpuinit nlm_init_secondary(void) { + unsigned int cpu, core_id; + + cpu = hard_smp_processor_id(); + core_id = (cpu >> 2) & 7; + cpu_data[cpu].core = core_id; + nlm_smp_irq_init(); } @@ -176,6 +182,8 @@ void __init nlm_smp_setup(void) void nlm_prepare_cpus(unsigned int max_cpus) { + /* declare we are SMT capable */ + smp_num_siblings = 4; } struct plat_smp_ops nlm_smp_ops = { From aba@not.so.argh.org Thu Oct 6 09:55:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Oct 2011 09:55:12 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:37467 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491136Ab1JFHzI (ORCPT ); Thu, 6 Oct 2011 09:55:08 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1RBinK-0003hS-Sx; Thu, 06 Oct 2011 07:55:07 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1RBinE-0005d6-RT; Thu, 06 Oct 2011 09:55:00 +0200 Date: Thu, 6 Oct 2011 09:55:00 +0200 From: Andreas Barth To: linux-mips@linux-mips.org, debian-mips@lists.debian.org Cc: sebastian@breakpoint.cc Subject: [PATCH] mips/ide: flush dcache also if icache does not snoop dcache Message-ID: <20111006075500.GE4110@mails.so.argh.org> Mail-Followup-To: Andreas Barth , linux-mips@linux-mips.org, debian-mips@lists.debian.org, sebastian@breakpoint.cc MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) X-archive-position: 31209 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3593 Content-Length: 2189 Lines: 66 Hi, we apply this patch in Debian for quite some time (the linked bug report is available on http://bugs.debian.org/404951 ). There was some discussion about it in http://comments.gmane.org/gmane.linux.ide/45092 but not concluded (or at least: the patch is not merged). In case it's useful it should IMHO go upstream. In case anything should be fixed we should fix whatever is necessary. (I don't have any own opinion with the patch, except that I want to get patches merged as far as useful.) So, my question is: Anything that needs to be changed? Or should we just continue the situation as is? Regards, Andi From: Sebastian Andrzej Siewior Subject: mips/ide: flush dcache also if icache does not snoop dcache If this is not done then the new just read data which remains in dcache will not make it into icache on time. Thus the CPU loads invalid data and executes crap. The result is that the user is not able to execute anything from its IDE based media while reading plain data is still working well. This problem has been reported as Debian #404951. Cc: stable@kernel.org Signed-off-by: Sebastian Andrzej Siewior --- arch/mips/include/asm/mach-generic/ide.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h index 9c93a5b..e80e47f 100644 --- a/arch/mips/include/asm/mach-generic/ide.h +++ b/arch/mips/include/asm/mach-generic/ide.h @@ -23,7 +23,7 @@ static inline void __ide_flush_prologue(void) { #ifdef CONFIG_SMP - if (cpu_has_dc_aliases) + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) preempt_disable(); #endif } @@ -31,14 +31,14 @@ static inline void __ide_flush_prologue(void) static inline void __ide_flush_epilogue(void) { #ifdef CONFIG_SMP - if (cpu_has_dc_aliases) + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) preempt_enable(); #endif } static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) { - if (cpu_has_dc_aliases) { + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) { unsigned long end = addr + size; while (addr < end) { From manuel.lauss@googlemail.com Thu Oct 6 15:37:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Oct 2011 15:38:06 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:40999 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491170Ab1JFNhy (ORCPT ); Thu, 6 Oct 2011 15:37:54 +0200 Received: by yxi11 with SMTP id 11so3170132yxi.36 for ; Thu, 06 Oct 2011 06:37:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=Ko4bcxq2OSPmRE09BqUnSS+cRtv6bRf5XUgh6/GjxQA=; b=cHa4LpT2W0POBuSknp7RylapdxXH8tqkAWxtm0SaMo+hNDkPhEADCtmHXUcxr2QkX0 pbX4URGFVkf9lhqRAY8vRv13CB8N8UZ1AULXBPpPZm3y9YgwTorQOMl48wMfaeswH53S ejAgBPtpkUQbMBb3lrxrqGMtRBv+n5c7myPUs= Received: by 10.223.5.3 with SMTP id 3mr3652289fat.4.1317908267033; Thu, 06 Oct 2011 06:37:47 -0700 (PDT) Received: from localhost.localdomain (188-22-157-177.adsl.highway.telekom.at. [188.22.157.177]) by mx.google.com with ESMTPS id y8sm7183015faj.10.2011.10.06.06.37.41 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Oct 2011 06:37:43 -0700 (PDT) From: Manuel Lauss To: Ralf Baechle , Linux-MIPS Cc: Manuel Lauss Subject: [PATCH V2] MIPS: Alchemy: redo PCI as platform driver Date: Thu, 6 Oct 2011 15:37:41 +0200 Message-Id: <1317908261-25608-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.7 X-archive-position: 31210 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3798 Content-Length: 59995 Lines: 1909 - Rewrite Alchemy PCI support as a platform driver. - Fixup boards which have PCI. Run-tested on DB1500 and DB1550. Signed-off-by: Manuel Lauss --- V2: changed PM to use syscore_ops instead of the platform_driver PM callbacks. syscore_ops are called much earlier during the resume process which makes restoring the wired entry much more straightforward. This is a replacement patch for the one already in mips-queue and mips-next. arch/mips/alchemy/common/Makefile | 2 - arch/mips/alchemy/common/pci.c | 104 ----- arch/mips/alchemy/common/setup.c | 6 +- arch/mips/alchemy/devboards/db1x00/board_setup.c | 24 - arch/mips/alchemy/devboards/db1x00/platform.c | 123 ++++++ arch/mips/alchemy/devboards/pb1500/board_setup.c | 33 +- arch/mips/alchemy/devboards/pb1500/platform.c | 48 ++- arch/mips/alchemy/devboards/pb1550/board_setup.c | 6 - arch/mips/alchemy/devboards/pb1550/platform.c | 48 ++- arch/mips/alchemy/gpr/board_setup.c | 12 - arch/mips/alchemy/gpr/platform.c | 47 ++ arch/mips/alchemy/mtx-1/board_setup.c | 40 -- arch/mips/alchemy/mtx-1/platform.c | 62 +++ arch/mips/alchemy/xxs1500/board_setup.c | 8 - arch/mips/include/asm/mach-au1x00/au1000.h | 142 ++++-- arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-au1000.c | 43 -- arch/mips/pci/ops-au1000.c | 308 ------------- arch/mips/pci/pci-alchemy.c | 513 ++++++++++++++++++++++ 19 files changed, 947 insertions(+), 625 deletions(-) delete mode 100644 arch/mips/alchemy/common/pci.c delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.c diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 62f0d39..811ece7 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -14,5 +14,3 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) obj-$(CONFIG_GPIOLIB) += gpiolib.o endif - -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c deleted file mode 100644 index 7866cf5..0000000 --- a/arch/mips/alchemy/common/pci.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1x00 PCI support. - * - * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * Support for all devices (greater than 16) added by David Gathright. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include - -#include - -/* TBD */ -static struct resource pci_io_resource = { - .start = PCI_IO_START, - .end = PCI_IO_END, - .name = "PCI IO space", - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = { - .start = PCI_MEM_START, - .end = PCI_MEM_END, - .name = "PCI memory space", - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops au1x_pci_ops; - -static struct pci_controller au1x_controller = { - .pci_ops = &au1x_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, -}; - -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) -static unsigned long virt_io_addr; -#endif - -static int __init au1x_pci_setup(void) -{ - extern void au1x_pci_cfg_init(void); - -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) - virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, - Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); - - if (!virt_io_addr) { - printk(KERN_ERR "Unable to ioremap pci space\n"); - return 1; - } - au1x_controller.io_map_base = virt_io_addr; - -#ifdef CONFIG_DMA_NONCOHERENT - { - /* - * Set the NC bit in controller for Au1500 pre-AC silicon - */ - u32 prid = read_c0_prid(); - - if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) { - au_writel((1 << 16) | au_readl(Au1500_PCI_CFG), - Au1500_PCI_CFG); - printk(KERN_INFO "Non-coherent PCI accesses enabled\n"); - } - } -#endif - - set_io_port_base(virt_io_addr); -#endif - - au1x_pci_cfg_init(); - - register_pci_controller(&au1x_controller); - return 0; -} - -arch_initcall(au1x_pci_setup); diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 1b887c8..37ffd99 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -73,8 +73,8 @@ void __init plat_mem_setup(void) /* This routine should be valid for all Au1x based boards */ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) { - u32 start = (u32)Au1500_PCI_MEM_START; - u32 end = (u32)Au1500_PCI_MEM_END; + unsigned long start = ALCHEMY_PCI_MEMWIN_START; + unsigned long end = ALCHEMY_PCI_MEMWIN_END; /* Don't fixup 36-bit addresses */ if ((phys_addr >> 32) != 0) @@ -82,7 +82,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) /* Check for PCI memory window */ if (phys_addr >= start && (phys_addr + size - 1) <= end) - return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START); + return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr); /* default nop */ return phys_addr; diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 5c956fe..2b2178f 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -40,24 +40,6 @@ #include -#ifdef CONFIG_MIPS_DB1500 -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ -}; - -#endif - - -#ifdef CONFIG_MIPS_DB1550 -char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */ - [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */ -}; -#endif - - #ifdef CONFIG_MIPS_BOSPORUS char irq_tab_alchemy[][5] __initdata = { [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */ @@ -91,12 +73,6 @@ const char *get_system_type(void) #ifdef CONFIG_MIPS_MIRAGE -char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */ - [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */ -}; - static void mirage_power_off(void) { alchemy_gpio_direction_output(210, 1); diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 70bcfb5..990367f 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -25,6 +25,8 @@ #include #include "../platform.h" +struct pci_dev; + /* DB1xxx PCMCIA interrupt sources: * CD0/1 GPIO0/3 * STSCHG0/1 GPIO1/4 @@ -85,6 +87,127 @@ #endif #endif +#ifdef CONFIG_PCI +#ifdef CONFIG_MIPS_DB1500 +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} +#endif + +#ifdef CONFIG_MIPS_DB1550 +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 11) + return (pin == 1) ? AU1550_PCI_INTC : 0xff; + if (slot == 12) { + switch (pin) { + case 1: return AU1550_PCI_INTB; + case 2: return AU1550_PCI_INTC; + case 3: return AU1550_PCI_INTD; + case 4: return AU1550_PCI_INTA; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1550_PCI_INTA; + case 2: return AU1550_PCI_INTB; + case 3: return AU1550_PCI_INTC; + case 4: return AU1550_PCI_INTD; + } + } + return -1; +} +#endif + +#ifdef CONFIG_MIPS_BOSPORUS +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 11) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + default: return 0xff; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} +#endif + +#ifdef CONFIG_MIPS_MIRAGE +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 11) + return (pin == 1) ? AU1500_PCI_INTD : 0xff; + if (slot == 12) + return (pin == 3) ? AU1500_PCI_INTC : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + default: return 0xff; + } + } + return -1; +} +#endif + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata db1xxx_pci_pd = { + .board_map_irq = db1xxx_map_pci_irq, +}; + +static struct platform_device db1xxx_pci_host_dev = { + .dev.platform_data = &db1xxx_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + +static int __init db15x0_pci_init(void) +{ + return platform_device_register(&db1xxx_pci_host_dev); +} +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +arch_initcall(db15x0_pci_init); +#endif + static int __init db1xxx_dev_init(void) { #ifdef DB1XXX_HAS_PCMCIA diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index 3b4fa32..37c1883 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c @@ -33,13 +33,6 @@ #include - -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ -}; - - const char *get_system_type(void) { return "Alchemy Pb1500"; @@ -101,20 +94,18 @@ void __init board_setup(void) #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ #ifdef CONFIG_PCI - /* Setup PCI bus controller */ - au_writel(0, Au1500_PCI_CMEM); - au_writel(0x00003fff, Au1500_CFG_BASE); -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif - au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); - au_writel(0, Au1500_PCI_MWBASE_REV_CCL); - au_writel(0x02a00356, Au1500_PCI_STATCMD); - au_writel(0x00003c04, Au1500_PCI_HDRTYPE); - au_writel(0x00000008, Au1500_PCI_MBAR); - au_sync(); + { + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR); + /* Setup PCI bus controller */ + __raw_writel(0x00003fff, base + PCI_REG_CMEM); + __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV); + __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL); + __raw_writel(0x02a00356, base + PCI_REG_STATCMD); + __raw_writel(0x00003c04, base + PCI_REG_PARAM); + __raw_writel(0x00000008, base + PCI_REG_MBAR); + wmb(); + } #endif /* Enable sys bus clock divider when IDLE state or no bus activity. */ diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c index 42b0e6b..9f0b5a0 100644 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -19,11 +19,56 @@ */ #include +#include #include #include #include "../platform.h" +static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata pb1500_pci_pd = { + .board_map_irq = pb1500_map_pci_irq, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device pb1500_pci_host = { + .dev.platform_data = &pb1500_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + static int __init pb1500_dev_init(void) { int swapped; @@ -41,7 +86,8 @@ static int __init pb1500_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + platform_device_register(&pb1500_pci_host); return 0; } -device_initcall(pb1500_dev_init); +arch_initcall(pb1500_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c index b790213..0f62d1e 100644 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c @@ -37,12 +37,6 @@ #include - -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */ -}; - const char *get_system_type(void) { return "Alchemy Pb1550"; diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c index 87c79b7..0c5711f 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -19,13 +19,56 @@ */ #include - +#include #include #include #include #include "../platform.h" +static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) { + switch (pin) { + case 1: return AU1500_PCI_INTB; + case 2: return AU1500_PCI_INTC; + case 3: return AU1500_PCI_INTD; + case 4: return AU1500_PCI_INTA; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata pb1550_pci_pd = { + .board_map_irq = pb1550_map_pci_irq, +}; + +static struct platform_device pb1550_pci_host = { + .dev.platform_data = &pb1550_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + static int __init pb1550_dev_init(void) { int swapped; @@ -57,7 +100,8 @@ static int __init pb1550_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 4, swapped); + platform_device_register(&pb1550_pci_host); return 0; } -device_initcall(pb1550_dev_init); +arch_initcall(pb1550_dev_init); diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c index 5f8f069..dea45c7 100644 --- a/arch/mips/alchemy/gpr/board_setup.c +++ b/arch/mips/alchemy/gpr/board_setup.c @@ -36,10 +36,6 @@ #include -char irq_tab_alchemy[][5] __initdata = { - [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, -}; - static void gpr_reset(char *c) { /* switch System-LED to orange (red# and green# on) */ @@ -76,12 +72,4 @@ void __init board_setup(void) /* Take away Reset of UMTS-card */ alchemy_gpio_direction_output(215, 1); - -#ifdef CONFIG_PCI -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif -#endif } diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c index 14b4662..982ce85 100644 --- a/arch/mips/alchemy/gpr/platform.c +++ b/arch/mips/alchemy/gpr/platform.c @@ -167,6 +167,45 @@ static struct i2c_board_info gpr_i2c_info[] __initdata = { } }; + + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot == 0) && (pin == 1)) + return AU1550_PCI_INTA; + else if ((slot == 0) && (pin == 2)) + return AU1550_PCI_INTB; + + return -1; +} + +static struct alchemy_pci_platdata gpr_pci_pd = { + .board_map_irq = gpr_map_pci_irq, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device gpr_pci_host_dev = { + .dev.platform_data = &gpr_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + static struct platform_device *gpr_devices[] __initdata = { &gpr_wdt_device, &gpr_mtd_device, @@ -174,6 +213,14 @@ static struct platform_device *gpr_devices[] __initdata = { &gpr_led_devices, }; +static int __init gpr_pci_init(void) +{ + return platform_device_register(&gpr_pci_host_dev); +} +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +arch_initcall(gpr_pci_init); + + static int __init gpr_dev_init(void) { i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info)); diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index 3ae984c..851a5ab 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -38,20 +38,6 @@ #include -char irq_tab_alchemy[][5] __initdata = { - [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */ - [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ - [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */ - [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ - [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */ - [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ - [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */ - [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ -}; - -extern int (*board_pci_idsel)(unsigned int devsel, int assert); -int mtx1_pci_idsel(unsigned int devsel, int assert); - static void mtx1_reset(char *c) { /* Jump to the reset vector */ @@ -74,15 +60,6 @@ void __init board_setup(void) alchemy_gpio_direction_output(204, 0); #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ -#ifdef CONFIG_PCI -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif - board_pci_idsel = mtx1_pci_idsel; -#endif - /* Initialize sys_pinfunc */ au_writel(SYS_PF_NI2, SYS_PINFUNC); @@ -104,23 +81,6 @@ void __init board_setup(void) printk(KERN_INFO "4G Systems MTX-1 Board\n"); } -int -mtx1_pci_idsel(unsigned int devsel, int assert) -{ - /* This function is only necessary to support a proprietary Cardbus - * adapter on the mtx-1 "singleboard" variant. It triggers a custom - * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. - */ - if (assert && devsel != 0) - /* Suppress signal to Cardbus */ - alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ - else - alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */ - - udelay(1); - return 1; -} - static int __init mtx1_init_irq(void) { irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c index 55628e3..cc47b68 100644 --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/mtx-1/platform.c @@ -135,7 +135,69 @@ static struct platform_device mtx1_mtd = { .resource = &mtx1_mtd_resource, }; +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static int mtx1_pci_idsel(unsigned int devsel, int assert) +{ + /* This function is only necessary to support a proprietary Cardbus + * adapter on the mtx-1 "singleboard" variant. It triggers a custom + * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. + */ + if (assert && devsel != 0) + /* Suppress signal to Cardbus */ + alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ + else + alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */ + + udelay(1); + return 1; +} + +static const char mtx1_irqtab[][5] = { + [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */ + [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ + [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */ + [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ + [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */ + [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ + [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */ + [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ +}; + +static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + return mtx1_irqtab[slot][pin]; +} + +static struct alchemy_pci_platdata mtx1_pci_pd = { + .board_map_irq = mtx1_map_pci_irq, + .board_pci_idsel = mtx1_pci_idsel, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device mtx1_pci_host = { + .dev.platform_data = &mtx1_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + + static struct __initdata platform_device * mtx1_devs[] = { + &mtx1_pci_host, &mtx1_gpio_leds, &mtx1_wdt, &mtx1_button, diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c index 81e57fa..3fa83f7 100644 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ b/arch/mips/alchemy/xxs1500/board_setup.c @@ -70,14 +70,6 @@ void __init board_setup(void) /* Enable DTR (MCR bit 0) = USB power up */ __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); wmb(); - -#ifdef CONFIG_PCI -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif -#endif } static int __init xxs1500_init_irq(void) diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 1bbcb30..49a227d 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -254,6 +254,14 @@ enum alchemy_usb_block { }; int alchemy_usb_control(int block, int enable); +/* PCI controller platform data */ +struct alchemy_pci_platdata { + int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); + int (*board_pci_idsel)(unsigned int devsel, int assert); + /* bits to set/clear in PCI_CONFIG register */ + unsigned long pci_cfg_set; + unsigned long pci_cfg_clr; +}; /* SOC Interrupt numbers */ @@ -1309,58 +1317,30 @@ enum soc_au1200_ints { # define AC97C_RS (1 << 1) # define AC97C_CE (1 << 0) -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) -/* Au1500 PCI Controller */ -#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ -#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) -#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) -# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \ - (1 << 25) | (1 << 26) | (1 << 27)) -#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) -#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) -#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) -#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) -#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) -#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) -#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) -#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) -#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) -#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) -#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) -#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) - -#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */ -/* - * All of our structures, like PCI resource, have 32-bit members. - * Drivers are expected to do an ioremap on the PCI MEM resource, but it's - * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch - * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and - * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM - * addresses. For PCI I/O, it's simpler because we get to do the ioremap - * ourselves and then adjust the device's resources. +/* The PCI chip selects are outside the 32bit space, and since we can't + * just program the 36bit addresses into BARs, we have to take a chunk + * out of the 32bit space and reserve it for PCI. When these addresses + * are ioremap()ed, they'll be fixed up to the real 36bit address before + * being passed to the real ioremap function. */ -#define Au1500_EXT_CFG 0x600000000ULL -#define Au1500_EXT_CFG_TYPE1 0x680000000ULL -#define Au1500_PCI_IO_START 0x500000000ULL -#define Au1500_PCI_IO_END 0x5000FFFFFULL -#define Au1500_PCI_MEM_START 0x440000000ULL -#define Au1500_PCI_MEM_END 0x44FFFFFFFULL +#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) +#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) -#define PCI_IO_START 0x00001000 -#define PCI_IO_END 0x000FFFFF -#define PCI_MEM_START 0x40000000 -#define PCI_MEM_END 0x4FFFFFFF +/* for PCI IO it's simpler because we get to do the ioremap ourselves and then + * adjust the device's resources. + */ +#define ALCHEMY_PCI_IOWIN_START 0x00001000 +#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF -#define PCI_FIRST_DEVFN (0 << 3) -#define PCI_LAST_DEVFN (19 << 3) +#ifdef CONFIG_PCI #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xfffffffffULL -#else /* Au1000 and Au1100 and Au1200 */ +#else /* Don't allow any legacy ports probing */ #define IOPORT_RESOURCE_START 0x10000000 @@ -1368,13 +1348,77 @@ enum soc_au1200_ints { #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xfffffffffULL -#define PCI_IO_START 0 -#define PCI_IO_END 0 -#define PCI_MEM_START 0 -#define PCI_MEM_END 0 -#define PCI_FIRST_DEVFN 0 -#define PCI_LAST_DEVFN 0 - #endif +/* PCI controller block register offsets */ +#define PCI_REG_CMEM 0x0000 +#define PCI_REG_CONFIG 0x0004 +#define PCI_REG_B2BMASK_CCH 0x0008 +#define PCI_REG_B2BBASE0_VID 0x000C +#define PCI_REG_B2BBASE1_SID 0x0010 +#define PCI_REG_MWMASK_DEV 0x0014 +#define PCI_REG_MWBASE_REV_CCL 0x0018 +#define PCI_REG_ERR_ADDR 0x001C +#define PCI_REG_SPEC_INTACK 0x0020 +#define PCI_REG_ID 0x0100 +#define PCI_REG_STATCMD 0x0104 +#define PCI_REG_CLASSREV 0x0108 +#define PCI_REG_PARAM 0x010C +#define PCI_REG_MBAR 0x0110 +#define PCI_REG_TIMEOUT 0x0140 + +/* PCI controller block register bits */ +#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */ +#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) +#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) +#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */ +#define PCI_CONFIG_ET (1 << 26) /* error in target mode */ +#define PCI_CONFIG_EF (1 << 25) /* fatal error */ +#define PCI_CONFIG_EP (1 << 24) /* parity error */ +#define PCI_CONFIG_EM (1 << 23) /* multiple errors */ +#define PCI_CONFIG_BM (1 << 22) /* bad master error */ +#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */ +#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */ +#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */ +#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */ +#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */ +#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */ +#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */ +#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */ +#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */ +#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */ +#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */ +#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */ +#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */ +#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */ +#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */ +#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */ +#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */ +#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */ +#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */ +#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */ +#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) +#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */ +#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) +#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) +#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) +#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) +#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) +#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) +#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) +#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) +#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) +#define PCI_ID_DID(x) (((x) & 0xffff) << 16) +#define PCI_ID_VID(x) ((x) & 0xffff) +#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) +#define PCI_STATCMD_CMD(x) ((x) & 0xffff) +#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) +#define PCI_CLASSREV_REV(x) ((x) & 0xff) +#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) +#define PCI_PARAM_HT(x) (((x) & 0xff) << 16) +#define PCI_PARAM_LT(x) (((x) & 0xff) << 8) +#define PCI_PARAM_CLS(x) ((x) & 0xff) +#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */ +#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */ + #endif diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 4df8799..bb82cbd 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -18,14 +18,13 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ ops-bcm63xx.o +obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o # # These are still pretty much in the old state, watch, go blind. # obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o -obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o -obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c deleted file mode 100644 index e2ddfc4..0000000 --- a/arch/mips/pci/fixup-au1000.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Board specific PCI fixups. - * - * Copyright 2001-2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include - -extern char irq_tab_alchemy[][5]; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_tab_alchemy[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c deleted file mode 100644 index 9a57c5a..0000000 --- a/arch/mips/pci/ops-au1000.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1xx0 PCI support. - * - * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * Support for all devices (greater than 16) added by David Gathright. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#include - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(KERN_DEBUG x) -#else -#define DBG(x...) -#endif - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -int (*board_pci_idsel)(unsigned int devsel, int assert); - -void mod_wired_entry(int entry, unsigned long entrylo0, - unsigned long entrylo1, unsigned long entryhi, - unsigned long pagemask) -{ - unsigned long old_pagemask; - unsigned long old_ctx; - - /* Save old context and create impossible VPN2 value */ - old_ctx = read_c0_entryhi() & 0xff; - old_pagemask = read_c0_pagemask(); - write_c0_index(entry); - write_c0_pagemask(pagemask); - write_c0_entryhi(entryhi); - write_c0_entrylo0(entrylo0); - write_c0_entrylo1(entrylo1); - tlb_write_indexed(); - write_c0_entryhi(old_ctx); - write_c0_pagemask(old_pagemask); -} - -static struct vm_struct *pci_cfg_vm; -static int pci_cfg_wired_entry; -static unsigned long last_entryLo0, last_entryLo1; - -/* - * We can't ioremap the entire pci config space because it's too large. - * Nor can we call ioremap dynamically because some device drivers use - * the PCI config routines from within interrupt handlers and that - * becomes a problem in get_vm_area(). We use one wired TLB to handle - * all config accesses for all busses. - */ -void __init au1x_pci_cfg_init(void) -{ - /* Reserve a wired entry for PCI config accesses */ - pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); - if (!pci_cfg_vm) - panic(KERN_ERR "PCI unable to get vm area\n"); - pci_cfg_wired_entry = read_c0_wired(); - add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); - last_entryLo0 = last_entryLo1 = 0xffffffff; -} - -static int config_access(unsigned char access_type, struct pci_bus *bus, - unsigned int dev_fn, unsigned char where, u32 *data) -{ -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) - unsigned int device = PCI_SLOT(dev_fn); - unsigned int function = PCI_FUNC(dev_fn); - unsigned long offset, status; - unsigned long cfg_base; - unsigned long flags; - int error = PCIBIOS_SUCCESSFUL; - unsigned long entryLo0, entryLo1; - - if (device > 19) { - *data = 0xffffffff; - return -1; - } - - local_irq_save(flags); - au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)), - Au1500_PCI_STATCMD); - au_sync_udelay(1); - - /* - * Allow board vendors to implement their own off-chip IDSEL. - * If it doesn't succeed, may as well bail out at this point. - */ - if (board_pci_idsel && board_pci_idsel(device, 1) == 0) { - *data = 0xffffffff; - local_irq_restore(flags); - return -1; - } - - /* Setup the config window */ - if (bus->number == 0) - cfg_base = (1 << device) << 11; - else - cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); - - /* Setup the lower bits of the 36-bit address */ - offset = (function << 8) | (where & ~0x3); - /* Pick up any address that falls below the page mask */ - offset |= cfg_base & ~PAGE_MASK; - - /* Page boundary */ - cfg_base = cfg_base & PAGE_MASK; - - /* - * To improve performance, if the current device is the same as - * the last device accessed, we don't touch the TLB. - */ - entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; - entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; - if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) { - mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, - (unsigned long)pci_cfg_vm->addr, PM_4K); - last_entryLo0 = entryLo0; - last_entryLo1 = entryLo1; - } - - if (access_type == PCI_ACCESS_WRITE) - au_writel(*data, (int)(pci_cfg_vm->addr + offset)); - else - *data = au_readl((int)(pci_cfg_vm->addr + offset)); - - au_sync_udelay(2); - - DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n", - access_type, bus->number, device, where, *data, offset); - - /* Check master abort */ - status = au_readl(Au1500_PCI_STATCMD); - - if (status & (1 << 29)) { - *data = 0xffffffff; - error = -1; - DBG("Au1x Master Abort\n"); - } else if ((status >> 28) & 0xf) { - DBG("PCI ERR detected: device %u, status %lx\n", - device, (status >> 28) & 0xf); - - /* Clear errors */ - au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD); - - *data = 0xffffffff; - error = -1; - } - - /* Take away the IDSEL. */ - if (board_pci_idsel) - (void)board_pci_idsel(device, 0); - - local_irq_restore(flags); - return error; -#endif -} - -static int read_config_byte(struct pci_bus *bus, unsigned int devfn, - int where, u8 *val) -{ - u32 data; - int ret; - - ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (where & 1) - data >>= 8; - if (where & 2) - data >>= 16; - *val = data & 0xff; - return ret; -} - -static int read_config_word(struct pci_bus *bus, unsigned int devfn, - int where, u16 *val) -{ - u32 data; - int ret; - - ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (where & 2) - data >>= 16; - *val = data & 0xffff; - return ret; -} - -static int read_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, u32 *val) -{ - int ret; - - ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); - return ret; -} - -static int write_config_byte(struct pci_bus *bus, unsigned int devfn, - int where, u8 val) -{ - u32 data = 0; - - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_word(struct pci_bus *bus, unsigned int devfn, - int where, u16 val) -{ - u32 data = 0; - - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, u32 val) -{ - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int config_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - switch (size) { - case 1: { - u8 _val; - int rc = read_config_byte(bus, devfn, where, &_val); - - *val = _val; - return rc; - } - case 2: { - u16 _val; - int rc = read_config_word(bus, devfn, where, &_val); - - *val = _val; - return rc; - } - default: - return read_config_dword(bus, devfn, where, val); - } -} - -static int config_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - switch (size) { - case 1: - return write_config_byte(bus, devfn, where, (u8) val); - case 2: - return write_config_word(bus, devfn, where, (u16) val); - default: - return write_config_dword(bus, devfn, where, val); - } -} - -struct pci_ops au1x_pci_ops = { - config_read, - config_write -}; diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c new file mode 100644 index 0000000..ac34f47 --- /dev/null +++ b/arch/mips/pci/pci-alchemy.c @@ -0,0 +1,513 @@ +/* + * Alchemy PCI host mode support. + * + * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * Support for all devices (greater than 16) added by David Gathright. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_DEBUG_PCI +#define DBG(x...) printk(KERN_DEBUG x) +#else +#define DBG(x...) do {} while (0) +#endif + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +struct alchemy_pci_context { + struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ + void __iomem *regs; /* ctrl base */ + /* tools for wired entry for config space access */ + unsigned long last_elo0; + unsigned long last_elo1; + int wired_entry; + struct vm_struct *pci_cfg_vm; + + unsigned long pm[12]; + + int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); + int (*board_pci_idsel)(unsigned int devsel, int assert); +}; + +/* for syscore_ops. There's only one PCI controller on Alchemy chips, so this + * should suffice for now. + */ +static struct alchemy_pci_context *__alchemy_pci_ctx = NULL; + + +/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr + * in arch/mips/alchemy/common/setup.c + */ +static struct resource alchemy_pci_def_memres = { + .start = ALCHEMY_PCI_MEMWIN_START, + .end = ALCHEMY_PCI_MEMWIN_END, + .name = "PCI memory space", + .flags = IORESOURCE_MEM +}; + +static struct resource alchemy_pci_def_iores = { + .start = ALCHEMY_PCI_IOWIN_START, + .end = ALCHEMY_PCI_IOWIN_END, + .name = "PCI IO space", + .flags = IORESOURCE_IO +}; + +static void mod_wired_entry(int entry, unsigned long entrylo0, + unsigned long entrylo1, unsigned long entryhi, + unsigned long pagemask) +{ + unsigned long old_pagemask; + unsigned long old_ctx; + + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & 0xff; + old_pagemask = read_c0_pagemask(); + write_c0_index(entry); + write_c0_pagemask(pagemask); + write_c0_entryhi(entryhi); + write_c0_entrylo0(entrylo0); + write_c0_entrylo1(entrylo1); + tlb_write_indexed(); + write_c0_entryhi(old_ctx); + write_c0_pagemask(old_pagemask); +} + +static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx) +{ + ctx->wired_entry = read_c0_wired(); + add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); + ctx->last_elo0 = ctx->last_elo1 = ~0; +} + +static int config_access(unsigned char access_type, struct pci_bus *bus, + unsigned int dev_fn, unsigned char where, u32 *data) +{ + struct alchemy_pci_context *ctx = bus->sysdata; + unsigned int device = PCI_SLOT(dev_fn); + unsigned int function = PCI_FUNC(dev_fn); + unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r; + int error = PCIBIOS_SUCCESSFUL; + + if (device > 19) { + *data = 0xffffffff; + return -1; + } + + local_irq_save(flags); + r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; + r |= PCI_STATCMD_STATUS(0x2000); + __raw_writel(r, ctx->regs + PCI_REG_STATCMD); + wmb(); + + /* Allow board vendors to implement their own off-chip IDSEL. + * If it doesn't succeed, may as well bail out at this point. + */ + if (ctx->board_pci_idsel(device, 1) == 0) { + *data = 0xffffffff; + local_irq_restore(flags); + return -1; + } + + /* Setup the config window */ + if (bus->number == 0) + cfg_base = (1 << device) << 11; + else + cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); + + /* Setup the lower bits of the 36-bit address */ + offset = (function << 8) | (where & ~0x3); + /* Pick up any address that falls below the page mask */ + offset |= cfg_base & ~PAGE_MASK; + + /* Page boundary */ + cfg_base = cfg_base & PAGE_MASK; + + /* To improve performance, if the current device is the same as + * the last device accessed, we don't touch the TLB. + */ + entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; + entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; + if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) { + mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1, + (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); + ctx->last_elo0 = entryLo0; + ctx->last_elo1 = entryLo1; + } + + if (access_type == PCI_ACCESS_WRITE) + __raw_writel(*data, ctx->pci_cfg_vm->addr + offset); + else + *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); + wmb(); + + DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n", + access_type, bus->number, device, where, *data, offset); + + /* check for errors, master abort */ + status = __raw_readl(ctx->regs + PCI_REG_STATCMD); + if (status & (1 << 29)) { + *data = 0xffffffff; + error = -1; + DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d", + access_type, bus->number, device); + } else if ((status >> 28) & 0xf) { + DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", + device, (status >> 28) & 0xf); + + /* clear errors */ + __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); + + *data = 0xffffffff; + error = -1; + } + + /* Take away the IDSEL. */ + (void)ctx->board_pci_idsel(device, 0); + + local_irq_restore(flags); + return error; +} + +static int read_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 *val) +{ + u32 data; + int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + + if (where & 1) + data >>= 8; + if (where & 2) + data >>= 16; + *val = data & 0xff; + return ret; +} + +static int read_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 *val) +{ + u32 data; + int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + + if (where & 2) + data >>= 16; + *val = data & 0xffff; + return ret; +} + +static int read_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 *val) +{ + return config_access(PCI_ACCESS_READ, bus, devfn, where, val); +} + +static int write_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 val) +{ + u32 data = 0; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 val) +{ + u32 data = 0; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 val) +{ + return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val); +} + +static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + switch (size) { + case 1: { + u8 _val; + int rc = read_config_byte(bus, devfn, where, &_val); + + *val = _val; + return rc; + } + case 2: { + u16 _val; + int rc = read_config_word(bus, devfn, where, &_val); + + *val = _val; + return rc; + } + default: + return read_config_dword(bus, devfn, where, val); + } +} + +static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + switch (size) { + case 1: + return write_config_byte(bus, devfn, where, (u8) val); + case 2: + return write_config_word(bus, devfn, where, (u16) val); + default: + return write_config_dword(bus, devfn, where, val); + } +} + +static struct pci_ops alchemy_pci_ops = { + .read = alchemy_pci_read, + .write = alchemy_pci_write, +}; + +static int alchemy_pci_def_idsel(unsigned int devsel, int assert) +{ + return 1; /* success */ +} + +static int __devinit alchemy_pci_probe(struct platform_device *pdev) +{ + struct alchemy_pci_platdata *pd = pdev->dev.platform_data; + struct alchemy_pci_context *ctx; + void __iomem *virt_io; + unsigned long val; + struct resource *r; + int ret; + + /* need at least PCI IRQ mapping table */ + if (!pd) { + dev_err(&pdev->dev, "need platform data for PCI setup\n"); + ret = -ENODEV; + goto out; + } + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + dev_err(&pdev->dev, "no memory for pcictl context\n"); + ret = -ENOMEM; + goto out; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no pcictl ctrl regs resource\n"); + ret = -ENODEV; + goto out1; + } + + if (!request_mem_region(r->start, resource_size(r), pdev->name)) { + dev_err(&pdev->dev, "cannot claim pci regs\n"); + ret = -ENODEV; + goto out1; + } + + ctx->regs = ioremap_nocache(r->start, resource_size(r)); + if (!ctx->regs) { + dev_err(&pdev->dev, "cannot map pci regs\n"); + ret = -ENODEV; + goto out2; + } + + /* map parts of the PCI IO area */ + /* REVISIT: if this changes with a newer variant (doubt it) make this + * a platform resource. + */ + virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000); + if (!virt_io) { + dev_err(&pdev->dev, "cannot remap pci io space\n"); + ret = -ENODEV; + goto out3; + } + ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; + +#ifdef CONFIG_DMA_NONCOHERENT + /* Au1500 revisions older than AD have borked coherent PCI */ + if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && + (read_c0_prid() < 0x01030202)) { + val = __raw_readl(ctx->regs + PCI_REG_CONFIG); + val |= PCI_CONFIG_NC; + __raw_writel(val, ctx->regs + PCI_REG_CONFIG); + wmb(); + dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n"); + } +#endif + + if (pd->board_map_irq) + ctx->board_map_irq = pd->board_map_irq; + + if (pd->board_pci_idsel) + ctx->board_pci_idsel = pd->board_pci_idsel; + else + ctx->board_pci_idsel = alchemy_pci_def_idsel; + + /* fill in relevant pci_controller members */ + ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops; + ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres; + ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores; + + /* we can't ioremap the entire pci config space because it's too large, + * nor can we dynamically ioremap it because some drivers use the + * PCI config routines from within atomic contex and that becomes a + * problem in get_vm_area(). Instead we use one wired TLB entry to + * handle all config accesses for all busses. + */ + ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); + if (!ctx->pci_cfg_vm) { + dev_err(&pdev->dev, "unable to get vm area\n"); + ret = -ENOMEM; + goto out4; + } + ctx->wired_entry = 8191; /* impossibly high value */ + alchemy_pci_wired_entry(ctx); /* install it */ + + set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); + + /* board may want to modify bits in the config register, do it now */ + val = __raw_readl(ctx->regs + PCI_REG_CONFIG); + val &= ~pd->pci_cfg_clr; + val |= pd->pci_cfg_set; + val &= ~PCI_CONFIG_PD; /* clear disable bit */ + __raw_writel(val, ctx->regs + PCI_REG_CONFIG); + wmb(); + + __alchemy_pci_ctx = ctx; + platform_set_drvdata(pdev, ctx); + register_pci_controller(&ctx->alchemy_pci_ctrl); + + return 0; + +out4: + iounmap(virt_io); +out3: + iounmap(ctx->regs); +out2: + release_mem_region(r->start, resource_size(r)); +out1: + kfree(ctx); +out: + return ret; +} + +/* save PCI controller register contents. */ +static int alchemy_pci_suspend(void) +{ + struct alchemy_pci_context *ctx = __alchemy_pci_ctx; + if (!ctx) + return 0; + + ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); + ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; + ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); + ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); + ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); + ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); + ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); + ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); + ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); + ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); + ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); + ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); + + return 0; +} + +static void alchemy_pci_resume(void) +{ + struct alchemy_pci_context *ctx = __alchemy_pci_ctx; + if (!ctx) + return; + + __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); + __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); + __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); + __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); + __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); + __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); + __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); + __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); + __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); + __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); + __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); + wmb(); + __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); + wmb(); + + /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired + * on resume, making it necessary to recreate it as soon as possible. + */ + ctx->wired_entry = 8191; /* impossibly high value */ + alchemy_pci_wired_entry(ctx); /* install it */ +} + +static struct syscore_ops alchemy_pci_pmops = { + .suspend = alchemy_pci_suspend, + .resume = alchemy_pci_resume, +}; + +static struct platform_driver alchemy_pcictl_driver = { + .probe = alchemy_pci_probe, + .driver = { + .name = "alchemy-pci", + .owner = THIS_MODULE, + }, +}; + +static int __init alchemy_pci_init(void) +{ + /* Au1500/Au1550 have PCI */ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1550: + register_syscore_ops(&alchemy_pci_pmops); + return platform_driver_register(&alchemy_pcictl_driver); + } + return 0; +} +arch_initcall(alchemy_pci_init); + + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct alchemy_pci_context *ctx = dev->sysdata; + if (ctx && ctx->board_map_irq) + return ctx->board_map_irq(dev, slot, pin); + return -1; +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} -- 1.7.7 From ralf@linux-mips.org Fri Oct 7 18:33:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Oct 2011 18:33:36 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:53101 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491194Ab1JGQdc (ORCPT ); Fri, 7 Oct 2011 18:33:32 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p97GXVkA027763; Fri, 7 Oct 2011 17:33:31 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p97GXUa6027761; Fri, 7 Oct 2011 17:33:30 +0100 Date: Fri, 7 Oct 2011 17:33:30 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH V2] MIPS: Alchemy: redo PCI as platform driver Message-ID: <20111007163330.GA26918@linux-mips.org> References: <1317908261-25608-1-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1317908261-25608-1-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31211 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4833 Content-Length: 373 Lines: 10 On Thu, Oct 06, 2011 at 03:37:41PM +0200, Manuel Lauss wrote: > V2: changed PM to use syscore_ops instead of the platform_driver PM callbacks. > syscore_ops are called much earlier during the resume process which > makes restoring the wired entry much more straightforward. Shouldn't the handling of wired entries rather be done in arch/mips/power/cpu.c? Ralf From manuel.lauss@googlemail.com Fri Oct 7 19:33:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Oct 2011 19:33:45 +0200 (CEST) Received: from mail-gx0-f177.google.com ([209.85.161.177]:49364 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491196Ab1JGRdl convert rfc822-to-8bit (ORCPT ); Fri, 7 Oct 2011 19:33:41 +0200 Received: by ggnm2 with SMTP id m2so3668305ggn.36 for ; Fri, 07 Oct 2011 10:33:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=3B8gzzWBzAn9Y8casjElE9Yi6hjuEPdN16InymItd6Q=; b=Gfyink+bvuBl2vVlr0XZ4gK+OkeZHnZaJnbnFKx7B8kGXWgvyKFg4xR3Z6zKZeFx4y DzUsoH/9POxWMjWJZkDIg7uQVPsYJZsIdojWJhAu7a1itAd8ZlEe0x6CJKw38B8Cr7zH URrXTmSw3MxfwCttfxAb4zwzw9wzUFyFhwgCM= Received: by 10.236.131.82 with SMTP id l58mr11811310yhi.90.1318008815745; Fri, 07 Oct 2011 10:33:35 -0700 (PDT) MIME-Version: 1.0 Received: by 10.236.105.169 with HTTP; Fri, 7 Oct 2011 10:33:15 -0700 (PDT) In-Reply-To: <20111007163330.GA26918@linux-mips.org> References: <1317908261-25608-1-git-send-email-manuel.lauss@googlemail.com> <20111007163330.GA26918@linux-mips.org> From: Manuel Lauss Date: Fri, 7 Oct 2011 19:33:15 +0200 Message-ID: Subject: Re: [PATCH V2] MIPS: Alchemy: redo PCI as platform driver To: Ralf Baechle Cc: Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 31212 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4889 Content-Length: 585 Lines: 14 On Fri, Oct 7, 2011 at 6:33 PM, Ralf Baechle wrote: > On Thu, Oct 06, 2011 at 03:37:41PM +0200, Manuel Lauss wrote: > >> V2: changed PM to use syscore_ops instead of the platform_driver PM callbacks. >>     syscore_ops are called much earlier during the resume process which >>     makes restoring the wired entry much more straightforward. > > Shouldn't the handling of wired entries rather be done in > arch/mips/power/cpu.c? It should, but save_processor_state() is only called during hibernation, and I am not qualified enough (yet) to implement it. Manuel From bhelgaas@google.com Fri Oct 7 23:51:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Oct 2011 23:51:24 +0200 (CEST) Received: from smtp-out.google.com ([216.239.44.51]:56948 "EHLO smtp-out.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491196Ab1JGVvP convert rfc822-to-8bit (ORCPT ); Fri, 7 Oct 2011 23:51:15 +0200 Received: from wpaz1.hot.corp.google.com (wpaz1.hot.corp.google.com [172.24.198.65]) by smtp-out.google.com with ESMTP id p97LpBxX001360 for ; Fri, 7 Oct 2011 14:51:11 -0700 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=google.com; s=beta; t=1318024273; bh=vu9HG0r02pKb8vJyBzdPooTpl68=; h=MIME-Version:In-Reply-To:References:From:Date:Message-ID:Subject: To:Cc:Content-Type:Content-Transfer-Encoding; b=K1wRG5gJ+6Vc5OD5m9DmInv1dPsxkdwVpgwD7MNzEPGJUjX669IGdkCb0z7YdYVeL bciBoXhIiO3PTS8j3jZ7Q== DomainKey-Signature: a=rsa-sha1; s=beta; d=google.com; c=nofws; q=dns; h=dkim-signature:mime-version:in-reply-to:references:from:date: message-id:subject:to:cc:content-type: content-transfer-encoding:x-system-of-record; b=cswvRyEOvXoIo94yjTvhJ8IoA+2f1F70CDZVdialb+/iklPlzi3pkMlG0KR4YvdWf ue6Eevz6NtcYSliFTaeHA== Received: from yxk36 (yxk36.prod.google.com [10.190.3.164]) by wpaz1.hot.corp.google.com with ESMTP id p97Lp9bM013587 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NOT) for ; Fri, 7 Oct 2011 14:51:10 -0700 Received: by yxk36 with SMTP id 36so5622736yxk.2 for ; Fri, 07 Oct 2011 14:51:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=beta; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=wdheew5yIpxf//CcHXFdHacKe3CbzL0OhLJQAozjEr8=; b=poFWkvtEAYT67mvqQUizIlGo9tKlrLvBUn43AxHdlQj8lAOqWnsoH9sm9y6inTSMhH ZjGYF/14ywWPJCW4f0lA== Received: by 10.150.239.8 with SMTP id m8mr2040208ybh.327.1318024269469; Fri, 07 Oct 2011 14:51:09 -0700 (PDT) Received: by 10.150.239.8 with SMTP id m8mr2040178ybh.327.1318024269235; Fri, 07 Oct 2011 14:51:09 -0700 (PDT) MIME-Version: 1.0 Received: by 10.150.198.8 with HTTP; Fri, 7 Oct 2011 14:50:49 -0700 (PDT) In-Reply-To: <1314845309-3277-1-git-send-email-dczhu@mips.com> References: <1314845309-3277-1-git-send-email-dczhu@mips.com> From: Bjorn Helgaas Date: Fri, 7 Oct 2011 15:50:49 -0600 Message-ID: Subject: Re: [RESEND PATCH v3 0/2] Pass resources to pci_create_bus() and fix MIPS PCI resources To: Deng-Cheng Zhu Cc: jbarnes@virtuousgeek.org, ralf@linux-mips.org, monstr@monstr.eu, benh@kernel.crashing.org, paulus@samba.org, davem@davemloft.net, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, eyal@mips.com, zenon@mips.com, dengcheng.zhu@gmail.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-System-Of-Record: true X-archive-position: 31213 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5078 Content-Length: 1687 Lines: 43 On Wed, Aug 31, 2011 at 8:48 PM, Deng-Cheng Zhu wrote: > (Resending the patch set to include more arch maintainers.) > > Change the pci_create_bus() interface to pass in available resources to get them > settled down early. This is to avoid possible resource conflicts while doing > pci_scan_slot() in pci_scan_child_bus(). Note that pcibios_fixup_bus() can get > rid of such conflicts, but it's done AFTER scanning slots. > > In addition, MIPS PCI resources are now fixed using this new interface. Jesse, I assume these are headed for the 3.2 merge window, right? Do you have a git tree anywhere where we could check without having to bother you? Bjorn > -- Changes -- > v3 - v2: > o Do not do fixups for root buses in pcibios_fixup_bus(). > o Skip bus creation when bus resources cannot be allocated. > o PCI domain/bus numbers added to the error info in controller_resources(). > > v2 - v1: > o Merge [PATCH 1/3] to [PATCH 3/3], so now 2 patches in total. > o Add more info to patch description. > o Fix arch breaks in default resource setup discovered by Bjorn Helgaas. > > Deng-Cheng Zhu (2): >  PCI: Pass available resources into pci_create_bus() >  MIPS: PCI: Pass controller's resources to pci_create_bus() in >    pcibios_scanbus() > >  arch/microblaze/pci/pci-common.c |    3 +- >  arch/mips/pci/pci.c              |   61 +++++++++++++++++++++++++++++++++----- >  arch/powerpc/kernel/pci-common.c |    3 +- >  arch/sparc/kernel/pci.c          |    3 +- >  arch/x86/pci/acpi.c              |    2 +- >  drivers/pci/probe.c              |   15 +++++++-- >  include/linux/pci.h              |    3 +- >  7 files changed, 73 insertions(+), 17 deletions(-) > > From dhillf@gmail.com Sun Oct 9 14:54:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 09 Oct 2011 14:54:09 +0200 (CEST) Received: from mail-ww0-f41.google.com ([74.125.82.41]:38957 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491014Ab1JIMyC (ORCPT ); Sun, 9 Oct 2011 14:54:02 +0200 Received: by wwf10 with SMTP id 10so2676922wwf.0 for ; Sun, 09 Oct 2011 05:53:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; bh=GmbfinFG3O5ZGHcYzjyE1iEYGbOVdh2Vrs5sqV/KF6k=; b=DcLnqZ2iuypdhaMVhMsX93cjeXBTI+rNT9Rkb0/RioT0cDFXrednbGP9mpn1Z/YfJ+ r6U+wO4w7QAMNy9e1EUM/PSPrZTLLAUdiYiJtRGyvn+knmjhnouH9k3i5pu/wEPcVBLK lZbgTvO8uqbOFRn88JoKNh2BCrAin9RT+JrLU= MIME-Version: 1.0 Received: by 10.216.185.5 with SMTP id t5mr3189629wem.28.1318164837197; Sun, 09 Oct 2011 05:53:57 -0700 (PDT) Received: by 10.216.73.193 with HTTP; Sun, 9 Oct 2011 05:53:57 -0700 (PDT) Date: Sun, 9 Oct 2011 20:53:57 +0800 Message-ID: Subject: [RFC] Flush huge TLB From: Hillf Danton To: linux-mips@linux-mips.org Cc: Ralf Baechle , "Jayachandran C." Content-Type: text/plain; charset=UTF-8 X-archive-position: 31214 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5645 Content-Length: 1475 Lines: 55 When flushing TLB, if @vma is backed by huge page, huge TLB should be flushed, due to the fact that huge page is defined to be far from normal page, and the flushing is shorten a bit. Any comment is welcome. Thanks Signed-off-by: Hillf Danton --- --- a/arch/mips/mm/tlb-r4k.c Mon May 30 21:17:04 2011 +++ b/arch/mips/mm/tlb-r4k.c Sun Oct 9 20:50:06 2011 @@ -120,22 +120,35 @@ void local_flush_tlb_range(struct vm_are if (cpu_context(cpu, mm) != 0) { unsigned long size, flags; + int huge = is_vm_hugetlb_page(vma); ENTER_CRITICAL(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; + if (huge) { + size = (end - start) / HPAGE_SIZE; + } else { + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + } if (size <= current_cpu_data.tlbsize/2) { int oldpid = read_c0_entryhi(); int newpid = cpu_asid(cpu, mm); - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); + if (huge) { + start &= HPAGE_MASK; + end &= HPAGE_MASK; + } else { + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + } while (start < end) { int idx; write_c0_entryhi(start | newpid); - start += (PAGE_SIZE << 1); + if (huge) + start += HPAGE_SIZE; + else + start += (PAGE_SIZE << 1); mtc0_tlbw_hazard(); tlb_probe(); tlb_probe_hazard(); From david.daney@cavium.com Mon Oct 10 19:17:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Oct 2011 19:17:37 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:1094 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491179Ab1JJRRU (ORCPT ); Mon, 10 Oct 2011 19:17:20 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 10 Oct 2011 10:18:35 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 10 Oct 2011 10:17:17 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 10 Oct 2011 10:17:17 -0700 Message-ID: <4E932897.9050301@cavium.com> Date: Mon, 10 Oct 2011 10:17:11 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Hillf Danton , Ralf Baechle CC: linux-mips@linux-mips.org, "Jayachandran C." Subject: Re: [RFC] Flush huge TLB References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 10 Oct 2011 17:17:17.0108 (UTC) FILETIME=[75E74740:01CC8770] X-archive-position: 31215 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6475 Content-Length: 2191 Lines: 87 On 10/09/2011 05:53 AM, Hillf Danton wrote: > When flushing TLB, if @vma is backed by huge page, huge TLB should be flushed, > due to the fact that huge page is defined to be far from normal page, and the > flushing is shorten a bit. > > Any comment is welcome. > Note that the current implementation works, but is not optimal. > Thanks > > Signed-off-by: Hillf Danton > --- > > --- a/arch/mips/mm/tlb-r4k.c Mon May 30 21:17:04 2011 > +++ b/arch/mips/mm/tlb-r4k.c Sun Oct 9 20:50:06 2011 > @@ -120,22 +120,35 @@ void local_flush_tlb_range(struct vm_are > > if (cpu_context(cpu, mm) != 0) { > unsigned long size, flags; > + int huge = is_vm_hugetlb_page(vma); > > ENTER_CRITICAL(flags); > - size = (end - start + (PAGE_SIZE - 1))>> PAGE_SHIFT; > - size = (size + 1)>> 1; > + if (huge) { > + size = (end - start) / HPAGE_SIZE; > + } else { > + size = (end - start + (PAGE_SIZE - 1))>> PAGE_SHIFT; > + size = (size + 1)>> 1; > + } Perhaps: if (huge) { start = round_down(start, HPAGE_SIZE); end = round_up(start, HPAGE_SIZE); size = (end - start) >> HPAGE_SHIFT; } else { start = round_down(start, PAGE_SIZE << 1); end = round_up(start, PAGE_SIZE << 1); size = (end - start) >> (PAGE_SHIFT + 1); } . . . > if (size<= current_cpu_data.tlbsize/2) { Has anybody benchmarked this heuristic? I guess it seems reasonable. > int oldpid = read_c0_entryhi(); > int newpid = cpu_asid(cpu, mm); > > - start&= (PAGE_MASK<< 1); > - end += ((PAGE_SIZE<< 1) - 1); > - end&= (PAGE_MASK<< 1); > + if (huge) { > + start&= HPAGE_MASK; > + end&= HPAGE_MASK; > + } else { > + start&= (PAGE_MASK<< 1); > + end += ((PAGE_SIZE<< 1) - 1); > + end&= (PAGE_MASK<< 1); > + } This stuff is done above so is removed. > while (start< end) { > int idx; > > write_c0_entryhi(start | newpid); > - start += (PAGE_SIZE<< 1); > + if (huge) > + start += HPAGE_SIZE; > + else > + start += (PAGE_SIZE<< 1); > mtc0_tlbw_hazard(); > tlb_probe(); > tlb_probe_hazard(); > > If we do something like that, then... Acked-by: David Daney From bhelgaas@google.com Mon Oct 10 23:04:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Oct 2011 23:04:57 +0200 (CEST) Received: from smtp-out.google.com ([74.125.121.67]:29799 "EHLO smtp-out.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491753Ab1JJVEt (ORCPT ); Mon, 10 Oct 2011 23:04:49 +0200 Received: from wpaz21.hot.corp.google.com (wpaz21.hot.corp.google.com [172.24.198.85]) by smtp-out.google.com with ESMTP id p9AL4h1w009239 for ; Mon, 10 Oct 2011 14:04:43 -0700 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=google.com; s=beta; t=1318280689; bh=Dwn+kl1Tk6Bf88ymwpRNAT6hxmw=; h=MIME-Version:In-Reply-To:References:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=LSoh9nbvTCl59gYlRyrIg6kZHrf+LNU5VvAxt1rEdo7VCMuMF3Q9vCrqIm4igE6sM baUAzNhZ89D2/6PnSC2Ig== DomainKey-Signature: a=rsa-sha1; s=beta; d=google.com; c=nofws; q=dns; h=dkim-signature:mime-version:in-reply-to:references:from:date: message-id:subject:to:cc:content-type:x-system-of-record; b=uLZtfZzHecsL4YNJSFoWi65OSfxRKSbFAJBhJeD/1uSJ/XNegnAAEF2+sYQcmWH+h FrrEq48bZy099FXyg9K5g== Received: from gyd8 (gyd8.prod.google.com [10.243.49.200]) by wpaz21.hot.corp.google.com with ESMTP id p9AL1ILm025305 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NOT) for ; Mon, 10 Oct 2011 14:04:42 -0700 Received: by gyd8 with SMTP id 8so9848386gyd.11 for ; Mon, 10 Oct 2011 14:04:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=beta; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=IpgDZtq0dWRgFvKP1adf+T78a5+sXS5C1Q3chCXse8U=; b=sQN4sv3WuabhbKVuirZgGh+l8vxHqDMgyYPEoM3ASRw38jvo0hCb6gKXXAtC15hPL9 R+bjQDhkhBGMECFK6B6w== Received: by 10.150.244.20 with SMTP id r20mr7874847ybh.50.1318280681335; Mon, 10 Oct 2011 14:04:41 -0700 (PDT) Received: by 10.150.244.20 with SMTP id r20mr7874813ybh.50.1318280681112; Mon, 10 Oct 2011 14:04:41 -0700 (PDT) MIME-Version: 1.0 Received: by 10.150.198.8 with HTTP; Mon, 10 Oct 2011 14:04:21 -0700 (PDT) In-Reply-To: References: <1314845309-3277-1-git-send-email-dczhu@mips.com> From: Bjorn Helgaas Date: Mon, 10 Oct 2011 15:04:21 -0600 Message-ID: Subject: Re: [RESEND PATCH v3 0/2] Pass resources to pci_create_bus() and fix MIPS PCI resources To: Deng-Cheng Zhu Cc: jbarnes@virtuousgeek.org, ralf@linux-mips.org, monstr@monstr.eu, benh@kernel.crashing.org, paulus@samba.org, davem@davemloft.net, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, eyal@mips.com, zenon@mips.com, dengcheng.zhu@gmail.com Content-Type: text/plain; charset=ISO-8859-1 X-System-Of-Record: true X-archive-position: 31216 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6640 Content-Length: 2247 Lines: 53 On Fri, Oct 7, 2011 at 3:50 PM, Bjorn Helgaas wrote: > On Wed, Aug 31, 2011 at 8:48 PM, Deng-Cheng Zhu wrote: >> (Resending the patch set to include more arch maintainers.) >> >> Change the pci_create_bus() interface to pass in available resources to get them >> settled down early. This is to avoid possible resource conflicts while doing >> pci_scan_slot() in pci_scan_child_bus(). Note that pcibios_fixup_bus() can get >> rid of such conflicts, but it's done AFTER scanning slots. >> >> In addition, MIPS PCI resources are now fixed using this new interface. > > Jesse, I assume these are headed for the 3.2 merge window, right? I tried to build on these patches to convert x86 to using the new pci_create_bus() interface, but I couldn't figure out a nice way to handle an arbitrary number of resources. We made pci_create_bus() take a "struct pci_bus_resource *" (https://lkml.org/lkml/2011/8/26/88): struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata, struct pci_bus_resource *bus_res); Where pci_bus_resource looks like this: struct pci_bus_resource { struct list_head list; struct resource *res; unsigned int flags; }; Conceptually, we're passing a list of resources to pci_create_bus(), which I think is the right thing. But I think the best way to do that is by passing a pointer to a struct list_head, not a pointer to a pci_bus_resource. If we pass a pci_bus_resource, we're basically using that as a container for a list (as per include/linux/list.h), but it's not a well-formed list. Normally a list contains one list_head per element, plus an extra list_head for the head of the list. There's a nice drawing on page 296 of http://lwn.net/images/pdf/LDD3/ch11.pdf. The list built in your MIPS patch (https://lkml.org/lkml/2011/8/26/89) consists of two pci_bus_resource structs (each with a list_head), but there's no third list_head for the head of the list. I think if you tried to use list_for_each_entry() to iterate through the list, it would not work correctly. I'll post a slightly modified series to show what I mean. Take a look and see if it makes sense to you. Bjorn From dczhu@mips.com Tue Oct 11 01:52:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Oct 2011 01:52:22 +0200 (CEST) Received: from dns1.mips.com ([12.201.5.69]:49162 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491758Ab1JJXwO convert rfc822-to-8bit (ORCPT ); Tue, 11 Oct 2011 01:52:14 +0200 Received: from exchdb01.mips.com (exchdb01.mips.com [192.168.36.67]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id p9ANn7br011082; Mon, 10 Oct 2011 16:49:07 -0700 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([fe80::2897:a30d:a923:303%16]) with mapi id 14.01.0270.001; Mon, 10 Oct 2011 16:49:07 -0700 From: "Zhu, DengCheng" To: Bjorn Helgaas CC: "jbarnes@virtuousgeek.org" , "ralf@linux-mips.org" , "monstr@monstr.eu" , "benh@kernel.crashing.org" , "paulus@samba.org" , "davem@davemloft.net" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , "Barzilay, Eyal" , "Fortuna, Zenon" , "dengcheng.zhu@gmail.com" Subject: RE: [RESEND PATCH v3 0/2] Pass resources to pci_create_bus() and fix MIPS PCI resources Thread-Topic: [RESEND PATCH v3 0/2] Pass resources to pci_create_bus() and fix MIPS PCI resources Thread-Index: AQHMaFGlI7Hp27+M00OrntK+WpTVnJVyGw+AgASqA4D//68aHQ== Date: Mon, 10 Oct 2011 23:49:06 +0000 Message-ID: References: <1314845309-3277-1-git-send-email-dczhu@mips.com> , In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: iiay/VHfaASoyHWbbhfuEw== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 31217 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6717 Content-Length: 3042 Lines: 72 2011/10/11 Bjorn Helgaas > > On Fri, Oct 7, 2011 at 3:50 PM, Bjorn Helgaas wrote: > > On Wed, Aug 31, 2011 at 8:48 PM, Deng-Cheng Zhu wrote: > >> (Resending the patch set to include more arch maintainers.) > >> > >> Change the pci_create_bus() interface to pass in available resources to get them > >> settled down early. This is to avoid possible resource conflicts while doing > >> pci_scan_slot() in pci_scan_child_bus(). Note that pcibios_fixup_bus() can get > >> rid of such conflicts, but it's done AFTER scanning slots. > >> > >> In addition, MIPS PCI resources are now fixed using this new interface. > > > > Jesse, I assume these are headed for the 3.2 merge window, right? > > I tried to build on these patches to convert x86 to using the new > pci_create_bus() interface, but I couldn't figure out a nice way to > handle an arbitrary number of resources. > > We made pci_create_bus() take a "struct pci_bus_resource *" > (https://lkml.org/lkml/2011/8/26/88): > > struct pci_bus *pci_create_bus(struct device *parent, int bus, > struct pci_ops *ops, void *sysdata, > struct pci_bus_resource *bus_res); > > Where pci_bus_resource looks like this: > > struct pci_bus_resource { > struct list_head list; > struct resource *res; > unsigned int flags; > }; > > Conceptually, we're passing a list of resources to pci_create_bus(), > which I think is the right thing. But I think the best way to do that > is by passing a pointer to a struct list_head, not a pointer to a > pci_bus_resource. > > If we pass a pci_bus_resource, we're basically using that as a > container for a list (as per include/linux/list.h), but it's not a > well-formed list. Normally a list contains one list_head per element, > plus an extra list_head for the head of the list. There's a nice > drawing on page 296 of http://lwn.net/images/pdf/LDD3/ch11.pdf. > > The list built in your MIPS patch (https://lkml.org/lkml/2011/8/26/89) > consists of two pci_bus_resource structs (each with a list_head), but > there's no third list_head for the head of the list. I think if you > tried to use list_for_each_entry() to iterate through the list, it > would not work correctly. > > I'll post a slightly modified series to show what I mean. Take a look > and see if it makes sense to you. Yes, I can easily understand what you mean, because this point was ever considered while writing this patch series. We pass the element list as opposed to a list_head for the head of the element list because we simply want to link the elements into pci_bus->resources in pci_create_bus(). This can be done by a single line: list_add_tail(&b->resources, &bus_res->list); In addition, if we need to do list_for_each_entry() on the list, our target should always be pci_bus->resources rather than the pci_bus_resource list which is passed into pci_create_bus() to be part (the meat) of pci_bus->resources. Deng-Cheng From benh@kernel.crashing.org Tue Oct 11 09:53:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Oct 2011 09:53:10 +0200 (CEST) Received: from gate.crashing.org ([63.228.1.57]:33286 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491160Ab1JKHxC (ORCPT ); Tue, 11 Oct 2011 09:53:02 +0200 Received: from [IPv6:::1] (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p9B7mFI1031341; Tue, 11 Oct 2011 02:48:16 -0500 Subject: RE: [RESEND PATCH v3 0/2] Pass resources to pci_create_bus() and fix MIPS PCI resources From: Benjamin Herrenschmidt To: "Zhu, DengCheng" Cc: Bjorn Helgaas , "jbarnes@virtuousgeek.org" , "ralf@linux-mips.org" , "monstr@monstr.eu" , "paulus@samba.org" , "davem@davemloft.net" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , "Barzilay, Eyal" , "Fortuna, Zenon" , "dengcheng.zhu@gmail.com" In-Reply-To: References: <1314845309-3277-1-git-send-email-dczhu@mips.com> , Content-Type: text/plain; charset="UTF-8" Date: Tue, 11 Oct 2011 09:48:15 +0200 Message-ID: <1318319295.29415.452.camel@pasglop> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 Content-Transfer-Encoding: 7bit X-archive-position: 31218 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: benh@kernel.crashing.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6929 Content-Length: 1809 Lines: 39 On Mon, 2011-10-10 at 23:49 +0000, Zhu, DengCheng wrote: > Yes, I can easily understand what you mean, because this point was ever > considered while writing this patch series. We pass the element list as > opposed to a list_head for the head of the element list because we simply > want to link the elements into pci_bus->resources in pci_create_bus(). This > can be done by a single line: > list_add_tail(&b->resources, &bus_res->list); > > In addition, if we need to do list_for_each_entry() on the list, our target > should always be pci_bus->resources rather than the pci_bus_resource list > which is passed into pci_create_bus() to be part (the meat) of > pci_bus->resources. I must admit I don't completely understand what this patch is about, other than it will most probably break the way we do resource management on powerpc :-) I don't understand the point about conflicts in scan_slot and I don't see what you win by "settling down early". Also keep in mind that the resources read from the device need to be remapped on some archs like powerpc which we do from a header quirk at the moment. We also have very different behaviour depending on the platform that we can trigger ranging from ignoring all resources read from the devices because we want the kernel to fully re-assign everything, to on the contrary only every using what the firmware set (no re-assigning possible), with variants such as re-assigning everything using a custom algorithm etc.... We do rely in various places on the concept of scan first, alloc/fixup next, then use. Merging scan & alloc/fixup of resources in one pass is a major conceptual change. It might be ok but I need to convince myself it is by understanding better what's going on and what problem you are really trying to solve here. Cheers, Ben. From aspam@cox.net Tue Oct 11 12:00:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Oct 2011 12:00:12 +0200 (CEST) Received: from lo.gmane.org ([80.91.229.12]:50606 "EHLO lo.gmane.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491167Ab1JKKAH (ORCPT ); Tue, 11 Oct 2011 12:00:07 +0200 Received: from list by lo.gmane.org with local (Exim 4.69) (envelope-from ) id 1RDZ82-0000CN-HK for linux-mips@linux-mips.org; Tue, 11 Oct 2011 12:00:06 +0200 Received: from ip68-100-141-95.dc.dc.cox.net ([68.100.141.95]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Tue, 11 Oct 2011 12:00:06 +0200 Received: from aspam by ip68-100-141-95.dc.dc.cox.net with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Tue, 11 Oct 2011 12:00:06 +0200 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Joe Buehler Subject: using mprotect to write to .text Date: Mon, 10 Oct 2011 20:02:39 +0000 (UTC) Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: usenet@dough.gmane.org X-Gmane-NNTP-Posting-Host: sea.gmane.org User-Agent: Loom/3.14 (http://gmane.org/) X-Loom-IP: 68.100.141.95 (Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.7; en-US; rv:1.9.2.23) Gecko/20110920 Firefox/3.6.23) X-archive-position: 31219 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aspam@cox.net Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7014 Content-Length: 387 Lines: 10 I intend to use mprotect in a running binary to allow it to modify its .text section. The detailed behavior of mprotect for a multithreaded program on SMP hardware is not documented as far as I can tell. Can I depend on the LINUX mprotect call to take care of icache flushing, handling of hazards, etc.? I am using Octeon CN5650 on 2.6.21.7 and 2.6.27.7 if it matters. Joe Buehler From bhelgaas@google.com Tue Oct 11 18:15:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Oct 2011 18:16:06 +0200 (CEST) Received: from smtp-out.google.com ([74.125.121.67]:5758 "EHLO smtp-out.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491178Ab1JKQP7 (ORCPT ); Tue, 11 Oct 2011 18:15:59 +0200 Received: from hpaq5.eem.corp.google.com (hpaq5.eem.corp.google.com [172.25.149.5]) by smtp-out.google.com with ESMTP id p9BGFuXG010927 for ; Tue, 11 Oct 2011 09:15:56 -0700 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=google.com; s=beta; t=1318349759; bh=i6bVgBGliiteWxs1f8CotbXdZYQ=; h=MIME-Version:In-Reply-To:References:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=TxeEKiPVIQFOCNPlx3PDdqpgS42VpO2E4drPIj0TGbP+cipM97EvtJjYGn+ILepuF syl7onoGD5gR4zkfrp8mw== DomainKey-Signature: a=rsa-sha1; s=beta; d=google.com; c=nofws; q=dns; h=dkim-signature:mime-version:in-reply-to:references:from:date: message-id:subject:to:cc:content-type; b=HupOsJWMAs0WaWV3GY40Qw3t3te1RJVPR4BItRwoZpg4FeXqS8QP9oSO1guQ/RQkx Fs/Nd8D1STzfxrYvzxACg== Received: from vws14 (vws14.prod.google.com [10.241.21.142]) by hpaq5.eem.corp.google.com with ESMTP id p9BGFOpa026621 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NOT) for ; Tue, 11 Oct 2011 09:15:55 -0700 Received: by vws14 with SMTP id 14so10837916vws.7 for ; Tue, 11 Oct 2011 09:15:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=beta; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=42EKK+bugRDdUFpQ1nnd8ipW/Eicjf4X8J0IChj8xj4=; b=ZZA+3QDpN3G5kEshjnvbsmX0L4LhZjyljGCQZyf2HgAdKEI/3lSoslanObR6Kfq1nW ePENsPwdfiy/z5Pv6WnQ== Received: by 10.150.244.20 with SMTP id r20mr10776274ybh.50.1318349755412; Tue, 11 Oct 2011 09:15:55 -0700 (PDT) Received: by 10.150.244.20 with SMTP id r20mr10776241ybh.50.1318349755238; Tue, 11 Oct 2011 09:15:55 -0700 (PDT) MIME-Version: 1.0 Received: by 10.150.198.8 with HTTP; Tue, 11 Oct 2011 09:15:34 -0700 (PDT) In-Reply-To: <1318319295.29415.452.camel@pasglop> References: <1314845309-3277-1-git-send-email-dczhu@mips.com> <1318319295.29415.452.camel@pasglop> From: Bjorn Helgaas Date: Tue, 11 Oct 2011 10:15:34 -0600 Message-ID: Subject: Re: [RESEND PATCH v3 0/2] Pass resources to pci_create_bus() and fix MIPS PCI resources To: Benjamin Herrenschmidt Cc: "Zhu, DengCheng" , "jbarnes@virtuousgeek.org" , "ralf@linux-mips.org" , "monstr@monstr.eu" , "paulus@samba.org" , "davem@davemloft.net" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , "Barzilay, Eyal" , "Fortuna, Zenon" , "dengcheng.zhu@gmail.com" Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 31220 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7303 Content-Length: 2790 Lines: 62 On Tue, Oct 11, 2011 at 1:48 AM, Benjamin Herrenschmidt wrote: > I must admit I don't completely understand what this patch is about, > other than it will most probably break the way we do resource management > on powerpc :-) > > I don't understand the point about conflicts in scan_slot and I don't > see what you win by "settling down early". Also keep in mind that the > resources read from the device need to be remapped on some archs like > powerpc which we do from a header quirk at the moment. These patches only deal with root bus resources, i.e., the non-architected PCI host bridge windows. They don't have anything to do with normal PCI BARs. MIPS sets up root buses differently than powerpc, so it has a problem that powerpc doesn't have. Here's the original MIPS flow (before this series): pci_scan_bus pci_scan_bus_parented pci_create_bus <-- A create root bus pci_scan_child_bus pci_scan_slot pci_scan_single_device pci_scan_device pci_setup_device pci_fixup_device (pci_fixup_early) <-- B pci_device_add pci_fixup_device (pci_fixup_header) <-- C pcibios_fixup_bus <-- D fill in root bus resources At point A, we allocate a struct pci_bus for the root bus. pci_create_bus() fills in defaults for the resources available on that bus: ioport_resource and iomem_resource, which cover all possible address space. Later at point D, we replace those defaults with the correct resources (hose->io_resource and hose->mem_resource in this MIPS case). The problem is that the root bus resources are wrong during the interval between A and D. Anything that looks at them may break. In the case Deng-Cheng found, the quirk_piix4_acpi() fixup at point C claimed a region, which incorrectly became the child of ioport_resource instead of host->io_resource. Deng-Cheng's patches close this window by basically combining the fixup at D with the root bus creation at A. Powerpc doesn't have the same problem because it calls pci_create_bus() directly so it can fix the root bus resources with pcibios_setup_phb_resources() *before* it scans the bus. Even though powerpc and many other architectures don't have the MIPS problem, I think it's worth changing the code because the existing pattern is poor. In almost all cases, we know what the host bridge apertures are before we create the root bus. It's error-prone to have pci_create_bus() fill in default resources, then rely on the architecture to fix that up later. I think it's better to supply the resources up front. Bjorn From david.daney@cavium.com Tue Oct 11 18:36:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Oct 2011 18:36:59 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5801 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491773Ab1JKQgy (ORCPT ); Tue, 11 Oct 2011 18:36:54 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 11 Oct 2011 09:38:10 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 11 Oct 2011 09:36:51 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 11 Oct 2011 09:36:51 -0700 Message-ID: <4E9470A1.8020309@cavium.com> Date: Tue, 11 Oct 2011 09:36:49 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Joe Buehler CC: linux-mips@linux-mips.org Subject: Re: using mprotect to write to .text References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 11 Oct 2011 16:36:51.0911 (UTC) FILETIME=[FAC95570:01CC8833] X-archive-position: 31221 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7319 Content-Length: 768 Lines: 33 On 10/10/2011 01:02 PM, Joe Buehler wrote: > I intend to use mprotect in a running binary to allow it to modify its .text > section. The detailed behavior of mprotect for a multithreaded program on SMP > hardware is not documented as far as I can tell. It is well documented. What is not well defined is what happens if you modify the code and then try to execute it. > > Can I depend on the LINUX mprotect call to take care of icache flushing, > handling of hazards, etc.? No, it does nothing of the sort. You need cacheflush() for that. > I am using Octeon CN5650 on 2.6.21.7 and 2.6.27.7 if > it matters. It doesn't really matter. What you need is something like: #include . . . cacheflush(location, size, ICACHE); . . . David Daney From aspam@cox.net Tue Oct 11 19:32:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Oct 2011 19:32:10 +0200 (CEST) Received: from eastrmfepo102.cox.net ([68.230.241.214]:44763 "EHLO eastrmfepo102.cox.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1JKRcH (ORCPT ); Tue, 11 Oct 2011 19:32:07 +0200 Received: from eastrmimpo03.cox.net ([68.1.16.126]) by eastrmfepo102.cox.net (InterMail vM.8.01.04.00 201-2260-137-20101110) with ESMTP id <20111011173156.BCLP12239.eastrmfepo102.cox.net@eastrmimpo03.cox.net>; Tue, 11 Oct 2011 13:31:56 -0400 Received: from thunder.sweets ([68.100.141.95]) by eastrmimpo03.cox.net with bizsmtp id jVXw1h00523hm2k02VXwhk; Tue, 11 Oct 2011 13:31:56 -0400 X-CT-Class: Clean X-CT-Score: 0.00 X-CT-RefID: str=0001.0A020208.4E947D8C.00B6,ss=1,re=0.000,fgs=0 X-CT-Spam: 0 X-Authority-Analysis: v=1.1 cv=ASjpOCvEPoSfhuYnpalwTqAN2s78hBywh12H8bbbxwo= c=1 sm=1 a=sqqFQ7cWU8cA:10 a=PLag0n9VLbMA:10 a=G8Uczd0VNMoA:10 a=8nJEP1OIZ-IA:10 a=NpDSbZnL7oWxO3tJXEQWVQ==:17 a=e22fObK1KDoUUrQu0gcA:9 a=wPNLvfGTeEIA:10 a=NpDSbZnL7oWxO3tJXEQWVQ==:117 X-CM-Score: 0.00 Authentication-Results: cox.net; none Received: from [10.10.10.15] (thunder.sweets [10.10.10.15]) by thunder.sweets (Postfix) with ESMTP id AA4E4FD78; Tue, 11 Oct 2011 13:31:55 -0400 (EDT) Message-ID: <4E947D8A.9090409@cox.net> Date: Tue, 11 Oct 2011 13:31:54 -0400 From: Joe Buehler User-Agent: Thunderbird 1.5.0.12 (X11/20090114) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org Subject: Re: using mprotect to write to .text References: <4E9470A1.8020309@cavium.com> In-Reply-To: <4E9470A1.8020309@cavium.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 31222 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aspam@cox.net Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7401 Content-Length: 631 Lines: 21 David Daney wrote: > No, it does nothing of the sort. You need cacheflush() for that. OK, I looked at cacheflush and it can be used to flush the icache on all CPUs, which is what I want. My current code sequence is more than that however. Something like this: CVMX_ICACHE_INVALIDATE; CVMX_SYNC; uint64_t tmp; asm volatile (" la %0,10f\n" " jr.hb %0\n" " nop\n" " 10:\n" : "=r" (tmp) : : "memory"); I can certainly modify cacheflush for my application so the extra hazard clearing is done when icache is flushed. Is there any way to avoid that and use existing kernel functionality? Joe Buehler From david.daney@cavium.com Tue Oct 11 20:06:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Oct 2011 20:06:19 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10835 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1JKSGO (ORCPT ); Tue, 11 Oct 2011 20:06:14 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 11 Oct 2011 11:07:30 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 11 Oct 2011 11:06:12 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 11 Oct 2011 11:06:12 -0700 Message-ID: <4E948593.6030604@cavium.com> Date: Tue, 11 Oct 2011 11:06:11 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Joe Buehler CC: linux-mips@linux-mips.org Subject: Re: using mprotect to write to .text References: <4E9470A1.8020309@cavium.com> <4E947D8A.9090409@cox.net> In-Reply-To: <4E947D8A.9090409@cox.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 11 Oct 2011 18:06:12.0232 (UTC) FILETIME=[75C96880:01CC8840] X-archive-position: 31223 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7420 Content-Length: 1069 Lines: 37 On 10/11/2011 10:31 AM, Joe Buehler wrote: > David Daney wrote: > >> No, it does nothing of the sort. You need cacheflush() for that. > > OK, I looked at cacheflush and it can be used to flush the icache on all > CPUs, which is what I want. My current code sequence is more than that > however. Something like this: > > CVMX_ICACHE_INVALIDATE; This only works if you can guarantee that the code will never be run on a different CPU than the current one. For most Linux code you cannot make such an assertion. > CVMX_SYNC; Unneeded. > uint64_t tmp; > asm volatile (" la %0,10f\n" > " jr.hb %0\n" > " nop\n" > " 10:\n" : "=r" (tmp) : : "memory"); jr.hb is equivalent to jr on Octeon. > > I can certainly modify cacheflush for my application so the extra hazard > clearing is done when icache is flushed. Is there any way to avoid that > and use existing kernel functionality? > I cannot parse the meaning out of these last two sentences. The cacheflush() system call both exists and works. You want to change it? David Daney From aspam@cox.net Tue Oct 11 20:35:26 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Oct 2011 20:35:30 +0200 (CEST) Received: from eastrmfepo203.cox.net ([68.230.241.218]:38395 "EHLO eastrmfepo203.cox.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1JKSf0 (ORCPT ); Tue, 11 Oct 2011 20:35:26 +0200 Received: from eastrmimpo02.cox.net ([68.1.16.120]) by eastrmfepo203.cox.net (InterMail vM.8.01.04.00 201-2260-137-20101110) with ESMTP id <20111011183516.ZGZQ3766.eastrmfepo203.cox.net@eastrmimpo02.cox.net>; Tue, 11 Oct 2011 14:35:16 -0400 Received: from thunder.sweets ([68.100.141.95]) by eastrmimpo02.cox.net with bizsmtp id jWbG1h00723hm2k02WbGnP; Tue, 11 Oct 2011 14:35:16 -0400 X-CT-Class: Clean X-CT-Score: 0.00 X-CT-RefID: str=0001.0A020207.4E948C64.0072,ss=1,re=0.000,fgs=0 X-CT-Spam: 0 X-Authority-Analysis: v=1.1 cv=oaIW6hvuqrvZuBstGxzMQDCn9/QU+BfQ2mb81G/9NAc= c=1 sm=1 a=sqqFQ7cWU8cA:10 a=PLag0n9VLbMA:10 a=G8Uczd0VNMoA:10 a=8nJEP1OIZ-IA:10 a=NpDSbZnL7oWxO3tJXEQWVQ==:17 a=UdjR6XGtzev_aqXJbLwA:9 a=wPNLvfGTeEIA:10 a=NpDSbZnL7oWxO3tJXEQWVQ==:117 X-CM-Score: 0.00 Authentication-Results: cox.net; none Received: from [10.10.10.15] (thunder.sweets [10.10.10.15]) by thunder.sweets (Postfix) with ESMTP id 980BCFD78; Tue, 11 Oct 2011 14:35:15 -0400 (EDT) Message-ID: <4E948C62.3000802@cox.net> Date: Tue, 11 Oct 2011 14:35:14 -0400 From: Joe Buehler User-Agent: Thunderbird 1.5.0.12 (X11/20090114) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org Subject: Re: using mprotect to write to .text References: <4E9470A1.8020309@cavium.com> <4E947D8A.9090409@cox.net> <4E948593.6030604@cavium.com> In-Reply-To: <4E948593.6030604@cavium.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 31224 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aspam@cox.net Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7463 Content-Length: 1070 Lines: 23 David Daney wrote: > I cannot parse the meaning out of these last two sentences. The > cacheflush() system call both exists and works. You want to change it? Let me rewind a bit. I have a multithreaded binary running on multiple physical CPUs. As part of a debugging mechanism, I want to make changes to .text from a thread dedicated to the purpose. This requires at the least icache flushes on all CPUs but also hazard avoidance measures on all CPUs. So I understand anyway. The cacheflush call will do the flush but not the hazard avoidance. In order to solve my particular issue I am thinking about adding the hazard avoidance into cacheflush for my particular application. It is not a question of cacheflush being wrong, but of extending it to meet my needs. In fact, it seems like a useful change -- it will allow an application to do exactly what I want to do, and easily so, and would seem a logical place for the functionality to reside. Sorry if I seem a bit muddled -- this is extremely low level and not what I deal with day to day. Joe Buehler From david.daney@cavium.com Tue Oct 11 20:43:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Oct 2011 20:43:29 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12859 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1JKSnY (ORCPT ); Tue, 11 Oct 2011 20:43:24 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 11 Oct 2011 11:44:40 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 11 Oct 2011 11:43:22 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 11 Oct 2011 11:43:22 -0700 Message-ID: <4E948E48.60205@cavium.com> Date: Tue, 11 Oct 2011 11:43:20 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Joe Buehler CC: linux-mips@linux-mips.org Subject: Re: using mprotect to write to .text References: <4E9470A1.8020309@cavium.com> <4E947D8A.9090409@cox.net> <4E948593.6030604@cavium.com> <4E948C62.3000802@cox.net> In-Reply-To: <4E948C62.3000802@cox.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 11 Oct 2011 18:43:22.0166 (UTC) FILETIME=[A6EE5560:01CC8845] X-archive-position: 31225 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7473 Content-Length: 1266 Lines: 33 Two points you may not be aware of: 1) cacheflush() clears all hazards. 2) There are no hazards on Octeon. On 10/11/2011 11:35 AM, Joe Buehler wrote: > David Daney wrote: > >> I cannot parse the meaning out of these last two sentences. The >> cacheflush() system call both exists and works. You want to change it? > > Let me rewind a bit. I have a multithreaded binary running on multiple > physical CPUs. As part of a debugging mechanism, I want to make changes > to .text from a thread dedicated to the purpose. This requires at the > least icache flushes on all CPUs but also hazard avoidance measures on > all CPUs. So I understand anyway. > > The cacheflush call will do the flush but not the hazard avoidance. In > order to solve my particular issue I am thinking about adding the hazard > avoidance into cacheflush for my particular application. It is not a > question of cacheflush being wrong, but of extending it to meet my > needs. In fact, it seems like a useful change -- it will allow an > application to do exactly what I want to do, and easily so, and would > seem a logical place for the functionality to reside. > > Sorry if I seem a bit muddled -- this is extremely low level and not > what I deal with day to day. > > Joe Buehler > From ralf@linux-mips.org Wed Oct 12 01:17:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Oct 2011 01:17:52 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56612 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491178Ab1JKXRt (ORCPT ); Wed, 12 Oct 2011 01:17:49 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p9BNHaNs031856; Wed, 12 Oct 2011 00:17:36 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p9BNHZnH031853; Wed, 12 Oct 2011 00:17:35 +0100 Date: Wed, 12 Oct 2011 00:17:35 +0100 From: Ralf Baechle To: David Daney Cc: Joe Buehler , linux-mips@linux-mips.org Subject: Re: using mprotect to write to .text Message-ID: <20111011231735.GA19175@linux-mips.org> References: <4E9470A1.8020309@cavium.com> <4E947D8A.9090409@cox.net> <4E948593.6030604@cavium.com> <4E948C62.3000802@cox.net> <4E948E48.60205@cavium.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4E948E48.60205@cavium.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31226 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7656 Content-Length: 681 Lines: 16 On Tue, Oct 11, 2011 at 11:43:20AM -0700, David Daney wrote: > 1) cacheflush() clears all hazards. More by accident than design - when I wrote the cacheflush syscall and manpage in 1995 the term execution hazard barrier didn't yet exist in manuals though the CPU behaviour was documented in the R4000 / R4600 manual of those days as a small number of pipeline cycles required to handle. The return patch of the syscall was taking care of this implicitly. And today the required R2 hazard barrier is provided by the ERET instruction of the return path, so everything is fine. But it may be worth updating the man page. A change every 15 years or so isn't that bad ;-) Ralf From aba@not.so.argh.org Wed Oct 12 21:07:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Oct 2011 21:07:10 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:53511 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491837Ab1JLTHH (ORCPT ); Wed, 12 Oct 2011 21:07:07 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1RE48v-0001e8-5C; Wed, 12 Oct 2011 19:07:05 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1RE48p-00069v-G5; Wed, 12 Oct 2011 21:06:59 +0200 Date: Wed, 12 Oct 2011 21:06:59 +0200 From: Andreas Barth To: Wu Zhangjin Cc: linux-mips@linux-mips.org, debian-mips@lists.debian.org Subject: YeeLoong / hotkey driver Message-ID: <20111012190659.GC15003@mails.so.argh.org> Mail-Followup-To: Andreas Barth , Wu Zhangjin , linux-mips@linux-mips.org, debian-mips@lists.debian.org MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) X-archive-position: 31227 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8405 Content-Length: 401 Lines: 14 Hi, there is currently a mail thread about the hotkeys not working with the default debian kernel. After a bit of search, I noticed the patches within http://www.linux-mips.org/archives/linux-mips/2009-11/msg00598.html however I didn't find a conclusion. Do you remember (or does anyone else) what happened to the patches or how we could get hotkey support into the default kernels? Thanks! Andi From ralf@linux-mips.org Thu Oct 13 10:04:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Oct 2011 10:04:19 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60139 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490965Ab1JMIEP (ORCPT ); Thu, 13 Oct 2011 10:04:15 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p9D84D3e017383; Thu, 13 Oct 2011 09:04:13 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p9D84CG7017372; Thu, 13 Oct 2011 09:04:12 +0100 Date: Thu, 13 Oct 2011 09:04:12 +0100 From: Ralf Baechle To: Andreas Barth , Wu Zhangjin , linux-mips@linux-mips.org, debian-mips@lists.debian.org Subject: Re: YeeLoong / hotkey driver Message-ID: <20111013080412.GA17240@linux-mips.org> References: <20111012190659.GC15003@mails.so.argh.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20111012190659.GC15003@mails.so.argh.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31228 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8854 Content-Length: 606 Lines: 15 On Wed, Oct 12, 2011 at 09:06:59PM +0200, Andreas Barth wrote: > there is currently a mail thread about the hotkeys not working with > the default debian kernel. After a bit of search, I noticed the > patches within > http://www.linux-mips.org/archives/linux-mips/2009-11/msg00598.html > however I didn't find a conclusion. > > Do you remember (or does anyone else) what happened to the patches or > how we could get hotkey support into the default kernels? Thanks! Back then a debate started and no updated version of the patch was ever posted. But nothing fundamentally wrong with the patch. Ralf From manesoni@cisco.com Thu Oct 13 11:08:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Oct 2011 11:08:11 +0200 (CEST) Received: from ams-iport-4.cisco.com ([144.254.224.147]:51584 "EHLO ams-iport-4.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490967Ab1JMJIA (ORCPT ); Thu, 13 Oct 2011 11:08:00 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=manesoni@cisco.com; l=13306; q=dns/txt; s=iport; t=1318496880; x=1319706480; h=date:from:to:cc:subject:message-id:reply-to:mime-version; bh=xsQfrO4hGVA9U0oKvysvyso8gxAe8bcO5sORXbnh7tk=; b=SfXFZpg4yyR2DW19GTUq5bPXnaGQyZx473AyC33h344Db9aNBbYdBz8N FK0JsM4zqNLoBKT233Q9vgF+3+vOEKoPXNsrdU0Lx18gz+3vISbQlLyc3 pS9jhwSw+5mvp0RTBhGUwZMx3tqoDOBP+qaSSdg1IyZEXq93azOWpP0nN A=; X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: Av0EAA6qlk6Q/khR/2dsb2JhbABDqFCBBYFTAQIWAQIBERM/MB8mGDwIIqEsAYMpDwGacIcMYQSHf4t5kV0 X-IronPort-AV: E=Sophos;i="4.69,339,1315180800"; d="scan'208";a="931013" Received: from ams-core-1.cisco.com ([144.254.72.81]) by ams-iport-4.cisco.com with ESMTP; 13 Oct 2011 09:07:54 +0000 Received: from cisco.com (dhcp-72-163-207-192.cisco.com [72.163.207.192]) by ams-core-1.cisco.com (8.14.3/8.14.3) with ESMTP id p9D97r9M025692; Thu, 13 Oct 2011 09:07:53 GMT Received: by cisco.com (Postfix, from userid 1001) id EC6FB81CA3; Thu, 13 Oct 2011 14:37:49 +0530 (IST) Date: Thu, 13 Oct 2011 14:37:49 +0530 From: Maneesh Soni To: ralf@linux-mips.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ananth@in.ibm.com, david.daney@cavium.com, kamensky@cisco.com Subject: [PATCH] MIPS Kprobes: Support branch instructions probing Message-ID: <20111013090749.GB16761@cisco.com> Reply-To: manesoni@cisco.com MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 31229 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manesoni@cisco.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8896 Content-Length: 12860 Lines: 446 From: Maneesh Soni This patch provides support for kprobes on branch instructions. The branch instruction at the probed address is actually emulated and not executed out-of-line like other normal instructions. Instead the delay-slot instruction is copied and single stepped out of line. At the time of probe hit, the original branch instruction is evaluated and the target cp0_epc is computed similar to compute_retrun_epc(). It is also checked if the delay slot instruction can be skipped, which is true if there is a NOP in delay slot or branch is taken in case of branch likely instructions. Once the delay slot instruction is single stepped the normal execution resume with the cp0_epc updated the earlier computed cp0_epc as per the branch instructions. Signed-off-by: Maneesh Soni --- arch/mips/include/asm/kprobes.h | 7 + arch/mips/kernel/kprobes.c | 341 +++++++++++++++++++++++++++++++++++---- 2 files changed, 320 insertions(+), 28 deletions(-) diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h index e6ea4d4..c0a3e6f 100644 --- a/arch/mips/include/asm/kprobes.h +++ b/arch/mips/include/asm/kprobes.h @@ -74,6 +74,8 @@ struct prev_kprobe { : MAX_JPROBES_STACK_SIZE) +#define SKIP_DELAYSLOT 1 + /* per-cpu kprobe control block */ struct kprobe_ctlblk { unsigned long kprobe_status; @@ -81,6 +83,11 @@ struct kprobe_ctlblk { unsigned long kprobe_saved_SR; unsigned long kprobe_saved_epc; unsigned long jprobe_saved_sp; + + /* Per-thread fields, used while emulating branches */ + unsigned long flags; + unsigned long target_epc; + struct pt_regs jprobe_saved_regs; u8 jprobes_stack[MAX_JPROBES_STACK_SIZE]; struct prev_kprobe prev_kprobe; diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c index ee28683..0a4a61c 100644 --- a/arch/mips/kernel/kprobes.c +++ b/arch/mips/kernel/kprobes.c @@ -121,8 +121,8 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) prev_insn = p->addr[-1]; insn = p->addr[0]; - if (insn_has_delayslot(insn) || insn_has_delayslot(prev_insn)) { - pr_notice("Kprobes for branch and jump instructions are not supported\n"); + if (insn_has_delayslot(prev_insn)) { + pr_notice("Kprobes for branch delayslot are not supported\n"); ret = -EINVAL; goto out; } @@ -138,9 +138,20 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) * In the kprobe->ainsn.insn[] array we store the original * instruction at index zero and a break trap instruction at * index one. + * + * On MIPS arch if the instruction at probed address is a + * branch instruction, we need to execute the instruction at + * Branch Delayslot (BD) at the time of probe hit. As MIPS also + * doesn't have single stepping support, the BD instruction can + * not be executed in-line and it would be executed on SSOL slot + * using a normal breakpoint instruction in the next slot. + * So, read the instruction and save it for later execution. */ + if (insn_has_delayslot(insn)) + memcpy(&p->ainsn.insn[0], p->addr + 1, sizeof(kprobe_opcode_t)); + else + memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t)); - memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t)); p->ainsn.insn[1] = breakpoint2_insn; p->opcode = *p->addr; @@ -191,16 +202,297 @@ static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs, kcb->kprobe_saved_epc = regs->cp0_epc; } -static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs) +/* + * Borrowed heavily from arch/mips/kernel/branch.c:__compute_return_epc() + * + * Evaluate the branch instruction at probed address during probe hit. The + * result of evaluation would be the updated epc. The insturction in delayslot + * would actually be single stepped using a normal breakpoint) on SSOL slot. + * + * The result is also saved in the kprobe control block for later use, + * in case we need to execute the delayslot instruction. The latter will be + * false for NOP instruction in dealyslot and the branch-likely instructions + * when the branch is taken. And for those cases we set a flag as + * SKIP_DELAYSLOT in the kprobe control block + */ +static int evaluate_branch_instruction(struct kprobe *p, struct pt_regs *regs, + struct kprobe_ctlblk *kcb) { + union mips_instruction insn = p->opcode; + unsigned int dspcontrol; + long epc; + + epc = regs->cp0_epc; + if (epc & 3) + goto unaligned; + + if (p->ainsn.insn->word == 0) + kcb->flags |= SKIP_DELAYSLOT; + else + kcb->flags &= ~SKIP_DELAYSLOT; + + switch (insn.i_format.opcode) { + /* + * jr and jalr are in r_format format. + */ + case spec_op: + switch (insn.r_format.func) { + case jalr_op: + regs->regs[insn.r_format.rd] = epc + 8; + + /* Fall through */ + case jr_op: + regs->cp0_epc = regs->regs[insn.r_format.rs]; + break; + } + break; + + /* + * This group contains: + * bltz_op, bgez_op, bltzl_op, bgezl_op, + * bltzal_op, bgezal_op, bltzall_op, bgezall_op. + */ + case bcond_op: + switch (insn.i_format.rt) { + case bltz_op: + if ((long)regs->regs[insn.i_format.rs] < 0) + epc = epc + 4 + (insn.i_format.simmediate << 2); + else + epc += 8; + regs->cp0_epc = epc; + break; + + case bltzl_op: + if ((long)regs->regs[insn.i_format.rs] < 0) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + kcb->flags |= SKIP_DELAYSLOT; + } else + epc += 8; + regs->cp0_epc = epc; + break; + + case bgez_op: + if ((long)regs->regs[insn.i_format.rs] >= 0) + epc = epc + 4 + (insn.i_format.simmediate << 2); + else + epc += 8; + regs->cp0_epc = epc; + break; + case bgezl_op: + if ((long)regs->regs[insn.i_format.rs] >= 0) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + kcb->flags |= SKIP_DELAYSLOT; + } else + epc += 8; + regs->cp0_epc = epc; + break; + + case bltzal_op: + regs->regs[31] = epc + 8; + if ((long)regs->regs[insn.i_format.rs] < 0) + epc = epc + 4 + (insn.i_format.simmediate << 2); + else + epc += 8; + regs->cp0_epc = epc; + break; + + case bltzall_op: + regs->regs[31] = epc + 8; + if ((long)regs->regs[insn.i_format.rs] < 0) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + kcb->flags |= SKIP_DELAYSLOT; + } else + epc += 8; + regs->cp0_epc = epc; + break; + + case bgezal_op: + regs->regs[31] = epc + 8; + if ((long)regs->regs[insn.i_format.rs] >= 0) + epc = epc + 4 + (insn.i_format.simmediate << 2); + else + epc += 8; + regs->cp0_epc = epc; + break; + + case bgezall_op: + regs->regs[31] = epc + 8; + if ((long)regs->regs[insn.i_format.rs] >= 0) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + kcb->flags |= SKIP_DELAYSLOT; + } else + epc += 8; + regs->cp0_epc = epc; + break; + + case bposge32_op: + if (!cpu_has_dsp) + goto sigill; + + dspcontrol = rddsp(0x01); + + if (dspcontrol >= 32) + epc = epc + 4 + (insn.i_format.simmediate << 2); + else + epc += 8; + regs->cp0_epc = epc; + break; + } + break; + + /* + * These are unconditional and in j_format. + */ + case jal_op: + regs->regs[31] = regs->cp0_epc + 8; + case j_op: + epc += 4; + epc >>= 28; + epc <<= 28; + epc |= (insn.j_format.target << 2); + regs->cp0_epc = epc; + break; + + /* + * These are conditional and in i_format. + */ + case beq_op: + if (regs->regs[insn.i_format.rs] == + regs->regs[insn.i_format.rt]) + epc = epc + 4 + (insn.i_format.simmediate << 2); + else + epc += 8; + regs->cp0_epc = epc; + break; + + case beql_op: + if (regs->regs[insn.i_format.rs] == + regs->regs[insn.i_format.rt]) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + kcb->flags |= SKIP_DELAYSLOT; + } else + epc += 8; + regs->cp0_epc = epc; + break; + + case bne_op: + if (regs->regs[insn.i_format.rs] != + regs->regs[insn.i_format.rt]) + epc = epc + 4 + (insn.i_format.simmediate << 2); + else + epc += 8; + regs->cp0_epc = epc; + break; + + case bnel_op: + if (regs->regs[insn.i_format.rs] != + regs->regs[insn.i_format.rt]) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + kcb->flags |= SKIP_DELAYSLOT; + } else + epc += 8; + regs->cp0_epc = epc; + break; + + case blez_op: /* not really i_format */ + /* rt field assumed to be zero */ + if ((long)regs->regs[insn.i_format.rs] <= 0) + epc = epc + 4 + (insn.i_format.simmediate << 2); + else + epc += 8; + regs->cp0_epc = epc; + break; + + case blezl_op: + /* rt field assumed to be zero */ + if ((long)regs->regs[insn.i_format.rs] <= 0) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + kcb->flags |= SKIP_DELAYSLOT; + } else + epc += 8; + regs->cp0_epc = epc; + break; + + case bgtz_op: + /* rt field assumed to be zero */ + if ((long)regs->regs[insn.i_format.rs] > 0) + epc = epc + 4 + (insn.i_format.simmediate << 2); + else + epc += 8; + regs->cp0_epc = epc; + break; + + case bgtzl_op: + /* rt field assumed to be zero */ + if ((long)regs->regs[insn.i_format.rs] > 0) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + kcb->flags |= SKIP_DELAYSLOT; + } else + epc += 8; + regs->cp0_epc = epc; + break; + } + + kcb->target_epc = regs->cp0_epc; + + return 1; + +unaligned: + printk(KERN_ERR "%s: unaligned epc - sending SIGBUS.\n", current->comm); + force_sig(SIGBUS, current); + return -EFAULT; + +sigill: + printk(KERN_ERR "%s: DSP branch but not DSP ASE - sending SIGBUS.\n", + current->comm); + force_sig(SIGBUS, current); + return -EFAULT; + +} + +static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs, + struct kprobe_ctlblk *kcb) +{ + int ret = 0; + regs->cp0_status &= ~ST0_IE; /* single step inline if the instruction is a break */ if (p->opcode.word == breakpoint_insn.word || p->opcode.word == breakpoint2_insn.word) regs->cp0_epc = (unsigned long)p->addr; - else - regs->cp0_epc = (unsigned long)&p->ainsn.insn[0]; + else if (insn_has_delayslot(p->opcode)) { + ret = evaluate_branch_instruction(p, regs, kcb); + if (ret < 0) { + printk(KERN_ERR "Kprobes: Error evaluating branch\n"); + return; + } + } + regs->cp0_epc = (unsigned long)&p->ainsn.insn[0]; +} + +/* + * Called after single-stepping. p->addr is the address of the + * instruction whose first byte has been replaced by the "break 0" + * instruction. To avoid the SMP problems that can occur when we + * temporarily put back the original opcode to single-step, we + * single-stepped a copy of the instruction. The address of this + * copy is p->ainsn.insn. + * + * This function prepares to return from the post-single-step + * breakpoint trap. In case of branch instructions, the target + * epc to be restored. + */ +static void __kprobes resume_execution(struct kprobe *p, + struct pt_regs *regs, + struct kprobe_ctlblk *kcb) +{ + if (insn_has_delayslot(p->opcode)) + regs->cp0_epc = kcb->target_epc; + else { + unsigned long orig_epc = kcb->kprobe_saved_epc; + regs->cp0_epc = orig_epc + 4; + } } static int __kprobes kprobe_handler(struct pt_regs *regs) @@ -239,8 +531,13 @@ static int __kprobes kprobe_handler(struct pt_regs *regs) save_previous_kprobe(kcb); set_current_kprobe(p, regs, kcb); kprobes_inc_nmissed_count(p); - prepare_singlestep(p, regs); + prepare_singlestep(p, regs, kcb); kcb->kprobe_status = KPROBE_REENTER; + if (kcb->flags & SKIP_DELAYSLOT) { + resume_execution(p, regs, kcb); + restore_previous_kprobe(kcb); + preempt_enable_no_resched(); + } return 1; } else { if (addr->word != breakpoint_insn.word) { @@ -284,8 +581,15 @@ static int __kprobes kprobe_handler(struct pt_regs *regs) } ss_probe: - prepare_singlestep(p, regs); - kcb->kprobe_status = KPROBE_HIT_SS; + prepare_singlestep(p, regs, kcb); + if (kcb->flags & SKIP_DELAYSLOT) { + kcb->kprobe_status = KPROBE_HIT_SSDONE; + if (p->post_handler) + p->post_handler(p, regs, 0); + resume_execution(p, regs, kcb); + } else + kcb->kprobe_status = KPROBE_HIT_SS; + return 1; no_kprobe: @@ -294,25 +598,6 @@ no_kprobe: } -/* - * Called after single-stepping. p->addr is the address of the - * instruction whose first byte has been replaced by the "break 0" - * instruction. To avoid the SMP problems that can occur when we - * temporarily put back the original opcode to single-step, we - * single-stepped a copy of the instruction. The address of this - * copy is p->ainsn.insn. - * - * This function prepares to return from the post-single-step - * breakpoint trap. - */ -static void __kprobes resume_execution(struct kprobe *p, - struct pt_regs *regs, - struct kprobe_ctlblk *kcb) -{ - unsigned long orig_epc = kcb->kprobe_saved_epc; - regs->cp0_epc = orig_epc + 4; -} - static inline int post_kprobe_handler(struct pt_regs *regs) { struct kprobe *cur = kprobe_running(); -- 1.7.1 From ananth@in.ibm.com Thu Oct 13 11:41:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Oct 2011 11:41:53 +0200 (CEST) Received: from e9.ny.us.ibm.com ([32.97.182.139]:37522 "EHLO e9.ny.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491001Ab1JMJlq (ORCPT ); Thu, 13 Oct 2011 11:41:46 +0200 Received: from d01relay07.pok.ibm.com (d01relay07.pok.ibm.com [9.56.227.147]) by e9.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id p9D95VCc015628; Thu, 13 Oct 2011 05:05:31 -0400 Received: from d01av03.pok.ibm.com (d01av03.pok.ibm.com [9.56.224.217]) by d01relay07.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p9D9fcgE2355264; Thu, 13 Oct 2011 05:41:38 -0400 Received: from d01av03.pok.ibm.com (loopback [127.0.0.1]) by d01av03.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p9D9fXdd031323; Thu, 13 Oct 2011 06:41:35 -0300 Received: from thinktux.localdomain (thinktux.in.ibm.com [9.124.35.31]) by d01av03.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p9D9fVde030793; Thu, 13 Oct 2011 06:41:32 -0300 Received: by thinktux.localdomain (Postfix, from userid 500) id 31F22220595; Thu, 13 Oct 2011 15:11:38 +0530 (IST) Date: Thu, 13 Oct 2011 15:11:38 +0530 From: Ananth N Mavinakayanahalli To: Maneesh Soni Cc: ralf@linux-mips.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, david.daney@cavium.com, kamensky@cisco.com Subject: Re: [PATCH] MIPS Kprobes: Support branch instructions probing Message-ID: <20111013094137.GA19054@in.ibm.com> Reply-To: ananth@in.ibm.com References: <20111013090749.GB16761@cisco.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20111013090749.GB16761@cisco.com> User-Agent: Mutt/1.5.17 (2007-11-01) X-archive-position: 31230 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ananth@in.ibm.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8918 Content-Length: 1177 Lines: 38 On Thu, Oct 13, 2011 at 02:37:49PM +0530, Maneesh Soni wrote: ... I know nothing of MIPS internals, but... > static int __kprobes kprobe_handler(struct pt_regs *regs) > @@ -239,8 +531,13 @@ static int __kprobes kprobe_handler(struct pt_regs *regs) > save_previous_kprobe(kcb); > set_current_kprobe(p, regs, kcb); > kprobes_inc_nmissed_count(p); > - prepare_singlestep(p, regs); > + prepare_singlestep(p, regs, kcb); > kcb->kprobe_status = KPROBE_REENTER; > + if (kcb->flags & SKIP_DELAYSLOT) { > + resume_execution(p, regs, kcb); > + restore_previous_kprobe(kcb); > + preempt_enable_no_resched(); > + } > return 1; > } else { > if (addr->word != breakpoint_insn.word) { > @@ -284,8 +581,15 @@ static int __kprobes kprobe_handler(struct pt_regs *regs) > } > > ss_probe: > - prepare_singlestep(p, regs); > - kcb->kprobe_status = KPROBE_HIT_SS; > + prepare_singlestep(p, regs, kcb); > + if (kcb->flags & SKIP_DELAYSLOT) { > + kcb->kprobe_status = KPROBE_HIT_SSDONE; > + if (p->post_handler) > + p->post_handler(p, regs, 0); > + resume_execution(p, regs, kcb); You are missing a preempt_disable_no_resched() here. Ananth From ananth@in.ibm.com Thu Oct 13 12:12:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Oct 2011 12:12:13 +0200 (CEST) Received: from e9.ny.us.ibm.com ([32.97.182.139]:41452 "EHLO e9.ny.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491002Ab1JMKMG (ORCPT ); Thu, 13 Oct 2011 12:12:06 +0200 Received: from d01relay06.pok.ibm.com (d01relay06.pok.ibm.com [9.56.227.116]) by e9.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id p9D9Zqtc028321; Thu, 13 Oct 2011 05:35:52 -0400 Received: from d01av01.pok.ibm.com (d01av01.pok.ibm.com [9.56.224.215]) by d01relay06.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p9DABxPn2466026; Thu, 13 Oct 2011 06:11:59 -0400 Received: from d01av01.pok.ibm.com (loopback [127.0.0.1]) by d01av01.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p9DABxnO011547; Thu, 13 Oct 2011 06:11:59 -0400 Received: from thinktux.localdomain (thinktux.in.ibm.com [9.124.35.31]) by d01av01.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p9DABvov011472; Thu, 13 Oct 2011 06:11:58 -0400 Received: by thinktux.localdomain (Postfix, from userid 500) id 7DA95220595; Thu, 13 Oct 2011 15:42:04 +0530 (IST) Date: Thu, 13 Oct 2011 15:42:04 +0530 From: Ananth N Mavinakayanahalli To: Maneesh Soni Cc: ralf@linux-mips.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, david.daney@cavium.com, kamensky@cisco.com Subject: Re: [PATCH] MIPS Kprobes: Support branch instructions probing Message-ID: <20111013101204.GB19054@in.ibm.com> Reply-To: ananth@in.ibm.com References: <20111013090749.GB16761@cisco.com> <20111013094137.GA19054@in.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20111013094137.GA19054@in.ibm.com> User-Agent: Mutt/1.5.17 (2007-11-01) X-archive-position: 31231 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ananth@in.ibm.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8949 Content-Length: 1369 Lines: 41 On Thu, Oct 13, 2011 at 03:11:37PM +0530, Ananth N Mavinakayanahalli wrote: > On Thu, Oct 13, 2011 at 02:37:49PM +0530, Maneesh Soni wrote: > > ... > > I know nothing of MIPS internals, but... > > > static int __kprobes kprobe_handler(struct pt_regs *regs) > > @@ -239,8 +531,13 @@ static int __kprobes kprobe_handler(struct pt_regs *regs) > > save_previous_kprobe(kcb); > > set_current_kprobe(p, regs, kcb); > > kprobes_inc_nmissed_count(p); > > - prepare_singlestep(p, regs); > > + prepare_singlestep(p, regs, kcb); > > kcb->kprobe_status = KPROBE_REENTER; > > + if (kcb->flags & SKIP_DELAYSLOT) { > > + resume_execution(p, regs, kcb); > > + restore_previous_kprobe(kcb); > > + preempt_enable_no_resched(); > > + } > > return 1; > > } else { > > if (addr->word != breakpoint_insn.word) { > > @@ -284,8 +581,15 @@ static int __kprobes kprobe_handler(struct pt_regs *regs) > > } > > > > ss_probe: > > - prepare_singlestep(p, regs); > > - kcb->kprobe_status = KPROBE_HIT_SS; > > + prepare_singlestep(p, regs, kcb); > > + if (kcb->flags & SKIP_DELAYSLOT) { > > + kcb->kprobe_status = KPROBE_HIT_SSDONE; > > + if (p->post_handler) > > + p->post_handler(p, regs, 0); > > + resume_execution(p, regs, kcb); > > You are missing a preempt_disable_no_resched() here. Oops! I meant preempt_enable_no_resched(). Ananth From manesoni@cisco.com Thu Oct 13 12:12:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Oct 2011 12:12:41 +0200 (CEST) Received: from ams-iport-1.cisco.com ([144.254.224.140]:65451 "EHLO ams-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491005Ab1JMKM2 (ORCPT ); Thu, 13 Oct 2011 12:12:28 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=manesoni@cisco.com; l=1484; q=dns/txt; s=iport; t=1318500748; x=1319710348; h=date:from:to:cc:subject:message-id:reply-to:references: mime-version:in-reply-to; bh=I/P10tROSvc4qVtiIw5YlPNk5SCeWfBBDnB7FvyV1cI=; b=PUvrHb3q9ERZqs2XF6inMqjP6ilMMNDn5fsbFC9PvC2QHsHV2Rd51vWF AGfWZEi6ec/uFR/6MCKmdlxyhFruCtNXUlnz8UuZRqcBrdQqFtiFOQCjg 1ElbJOUmjouba3KuFw8m3xK3d6+mYk8JY2UllQPmMgpavOrFp6tVa59FW 8=; X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: Av4EABe5lk6Q/khM/2dsb2JhbABDqFGBBYFTAQEBBBIBAgEREz8QCxgcEhQYMQsqoS8BgykPAZpwhwxhBId/i3mRXQ X-IronPort-AV: E=Sophos;i="4.69,339,1315180800"; d="scan'208";a="119017620" Received: from ams-core-3.cisco.com ([144.254.72.76]) by ams-iport-1.cisco.com with ESMTP; 13 Oct 2011 10:12:21 +0000 Received: from cisco.com (dhcp-72-163-207-192.cisco.com [72.163.207.192]) by ams-core-3.cisco.com (8.14.3/8.14.3) with ESMTP id p9DACLpQ002738; Thu, 13 Oct 2011 10:12:21 GMT Received: by cisco.com (Postfix, from userid 1001) id 16EDD81C9F; Thu, 13 Oct 2011 15:42:18 +0530 (IST) Date: Thu, 13 Oct 2011 15:42:18 +0530 From: Maneesh Soni To: Ananth N Mavinakayanahalli Cc: ralf@linux-mips.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, david.daney@cavium.com, kamensky@cisco.com Subject: Re: [PATCH] MIPS Kprobes: Support branch instructions probing Message-ID: <20111013101217.GD16761@cisco.com> Reply-To: manesoni@cisco.com References: <20111013090749.GB16761@cisco.com> <20111013094137.GA19054@in.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20111013094137.GA19054@in.ibm.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 31232 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manesoni@cisco.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8950 Content-Length: 1441 Lines: 43 On Thu, Oct 13, 2011 at 03:11:38PM +0530, Ananth N Mavinakayanahalli wrote: > On Thu, Oct 13, 2011 at 02:37:49PM +0530, Maneesh Soni wrote: > > ... > > I know nothing of MIPS internals, but... > > > static int __kprobes kprobe_handler(struct pt_regs *regs) > > @@ -239,8 +531,13 @@ static int __kprobes kprobe_handler(struct pt_regs *regs) > > save_previous_kprobe(kcb); > > set_current_kprobe(p, regs, kcb); > > kprobes_inc_nmissed_count(p); > > - prepare_singlestep(p, regs); > > + prepare_singlestep(p, regs, kcb); > > kcb->kprobe_status = KPROBE_REENTER; > > + if (kcb->flags & SKIP_DELAYSLOT) { > > + resume_execution(p, regs, kcb); > > + restore_previous_kprobe(kcb); > > + preempt_enable_no_resched(); > > + } > > return 1; > > } else { > > if (addr->word != breakpoint_insn.word) { > > @@ -284,8 +581,15 @@ static int __kprobes kprobe_handler(struct pt_regs *regs) > > } > > > > ss_probe: > > - prepare_singlestep(p, regs); > > - kcb->kprobe_status = KPROBE_HIT_SS; > > + prepare_singlestep(p, regs, kcb); > > + if (kcb->flags & SKIP_DELAYSLOT) { > > + kcb->kprobe_status = KPROBE_HIT_SSDONE; > > + if (p->post_handler) > > + p->post_handler(p, regs, 0); > > + resume_execution(p, regs, kcb); > > You are missing a preempt_disable_no_resched() here. > ok.. you meant preempt_enable_no_resched(). Will add it in the next version. Thanks for pointing it out. Thanks Maneesh From david.daney@cavium.com Thu Oct 13 19:29:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Oct 2011 19:29:07 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13849 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491072Ab1JMR3A (ORCPT ); Thu, 13 Oct 2011 19:29:00 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 13 Oct 2011 10:30:14 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 13 Oct 2011 10:28:55 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 13 Oct 2011 10:28:55 -0700 Message-ID: <4E971FD3.2020308@cavium.com> Date: Thu, 13 Oct 2011 10:28:51 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: manesoni@cisco.com CC: ralf@linux-mips.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ananth@in.ibm.com, kamensky@cisco.com Subject: Re: [PATCH] MIPS Kprobes: Support branch instructions probing References: <20111013090749.GB16761@cisco.com> In-Reply-To: <20111013090749.GB16761@cisco.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 13 Oct 2011 17:28:55.0701 (UTC) FILETIME=[95895C50:01CC89CD] X-archive-position: 31233 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9411 Content-Length: 2248 Lines: 75 On 10/13/2011 02:07 AM, Maneesh Soni wrote: > > From: Maneesh Soni > > This patch provides support for kprobes on branch instructions. The branch > instruction at the probed address is actually emulated and not executed > out-of-line like other normal instructions. Instead the delay-slot instruction > is copied and single stepped out of line. > > At the time of probe hit, the original branch instruction is evaluated > and the target cp0_epc is computed similar to compute_retrun_epc(). It > is also checked if the delay slot instruction can be skipped, which is > true if there is a NOP in delay slot or branch is taken in case of > branch likely instructions. Once the delay slot instruction is single > stepped the normal execution resume with the cp0_epc updated the earlier > computed cp0_epc as per the branch instructions. > I haven't tested it but... > Signed-off-by: Maneesh Soni > --- > arch/mips/include/asm/kprobes.h | 7 + > arch/mips/kernel/kprobes.c | 341 +++++++++++++++++++++++++++++++++++---- > 2 files changed, 320 insertions(+), 28 deletions(-) > [...] > +static int evaluate_branch_instruction(struct kprobe *p, struct pt_regs *regs, > + struct kprobe_ctlblk *kcb) > { > + union mips_instruction insn = p->opcode; > + unsigned int dspcontrol; > + long epc; > + > + epc = regs->cp0_epc; > + if (epc& 3) > + goto unaligned; > + > + if (p->ainsn.insn->word == 0) > + kcb->flags |= SKIP_DELAYSLOT; > + else > + kcb->flags&= ~SKIP_DELAYSLOT; > + > + switch (insn.i_format.opcode) { > + /* > + * jr and jalr are in r_format format. > + */ > + case spec_op: [...] > + case bgtzl_op: > + /* rt field assumed to be zero */ > + if ((long)regs->regs[insn.i_format.rs]> 0) { > + epc = epc + 4 + (insn.i_format.simmediate<< 2); > + kcb->flags |= SKIP_DELAYSLOT; > + } else > + epc += 8; > + regs->cp0_epc = epc; > + break; Where is the handling for: case cop1_op: #ifdef CONFIG_CPU_CAVIUM_OCTEON case lwc2_op: /* This is bbit0 on Octeon */ case ldc2_op: /* This is bbit032 on Octeon */ case swc2_op: /* This is bbit1 on Octeon */ case sdc2_op: /* This is bbit132 on Octeon */ #endif These are all defined in insn_has_delayslot() but not here. From ralf@linux-mips.org Thu Oct 13 20:07:26 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Oct 2011 20:07:30 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52799 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491072Ab1JMSH0 (ORCPT ); Thu, 13 Oct 2011 20:07:26 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p9DI7H39008742; Thu, 13 Oct 2011 19:07:17 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p9DI7EtP008733; Thu, 13 Oct 2011 19:07:14 +0100 Date: Thu, 13 Oct 2011 19:07:14 +0100 From: Ralf Baechle To: David Daney Cc: manesoni@cisco.com, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ananth@in.ibm.com, kamensky@cisco.com Subject: Re: [PATCH] MIPS Kprobes: Support branch instructions probing Message-ID: <20111013180714.GA7422@linux-mips.org> References: <20111013090749.GB16761@cisco.com> <4E971FD3.2020308@cavium.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4E971FD3.2020308@cavium.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31234 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9454 Content-Length: 796 Lines: 26 On Thu, Oct 13, 2011 at 10:28:51AM -0700, David Daney wrote: > Where is the handling for: > > case cop1_op: > > #ifdef CONFIG_CPU_CAVIUM_OCTEON > case lwc2_op: /* This is bbit0 on Octeon */ > case ldc2_op: /* This is bbit032 on Octeon */ > case swc2_op: /* This is bbit1 on Octeon */ > case sdc2_op: /* This is bbit132 on Octeon */ > #endif > > These are all defined in insn_has_delayslot() but not here. Which is a wonderful demonstration for why duplicating such a large function from branch.c was a baaad thing to do. Maneesh, can you refactor the code to share everything that was copied from __compute_return_epc() can be shared with kprobes? Idealy make everything a two part series, first one patch to refactor branch.c and the 2nd patch to deal with kprobes. Thanks, Ralf From kamensky@cisco.com Thu Oct 13 21:16:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 13 Oct 2011 21:16:42 +0200 (CEST) Received: from mtv-iport-3.cisco.com ([173.36.130.14]:28120 "EHLO mtv-iport-3.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491073Ab1JMTQf (ORCPT ); Thu, 13 Oct 2011 21:16:35 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=kamensky@cisco.com; l=1300; q=dns/txt; s=iport; t=1318533395; x=1319742995; h=date:from:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=kCOm0p0jHIuwKTTRh9wRM7Z9XdZNQGDZhM07BaFeitU=; b=SyWH2BkMfgquu7qOsvBqHOjr3y69BqFyLG9pVg6UU+Tu8vwuD8phbGoO TVH8wyYsf1WIxk6JEe1mdogbFN5Ed370K5vSSl4pX/CSpf8yI7Rl37ho7 MSLtnv/4mxZpSyEa80gT8eZAwr2pa5BAgx/MpbCdWcVTb46jZzVrOe57l 4=; X-IronPort-AV: E=Sophos;i="4.69,342,1315180800"; d="scan'208";a="7734723" Received: from mtv-core-3.cisco.com ([171.68.58.8]) by mtv-iport-3.cisco.com with ESMTP; 13 Oct 2011 19:16:28 +0000 Received: from infra-view9 (infra-view9.cisco.com [171.70.70.104]) by mtv-core-3.cisco.com (8.14.3/8.14.3) with ESMTP id p9DJGRFZ023626; Thu, 13 Oct 2011 19:16:27 GMT Date: Thu, 13 Oct 2011 12:16:27 -0700 (PDT) From: Victor Kamensky To: Ralf Baechle cc: David Daney , manesoni@cisco.com, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ananth@in.ibm.com Subject: Re: [PATCH] MIPS Kprobes: Support branch instructions probing In-Reply-To: <20111013180714.GA7422@linux-mips.org> Message-ID: References: <20111013090749.GB16761@cisco.com> <4E971FD3.2020308@cavium.com> <20111013180714.GA7422@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 31235 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kamensky@cisco.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9512 Content-Length: 1254 Lines: 46 On Thu, 13 Oct 2011, Ralf Baechle wrote: > On Thu, Oct 13, 2011 at 10:28:51AM -0700, David Daney wrote: > > > Where is the handling for: > > > > case cop1_op: > > > > #ifdef CONFIG_CPU_CAVIUM_OCTEON > > case lwc2_op: /* This is bbit0 on Octeon */ > > case ldc2_op: /* This is bbit032 on Octeon */ > > case swc2_op: /* This is bbit1 on Octeon */ > > case sdc2_op: /* This is bbit132 on Octeon */ > > #endif > > > > These are all defined in insn_has_delayslot() but not here. David, nice catch! > Which is a wonderful demonstration for why duplicating such a large > function from branch.c was a baaad thing to do. > > Maneesh, can you refactor the code to share everything that was copied > from __compute_return_epc() can be shared with kprobes? Idealy make > everything a two part series, first one patch to refactor branch.c Yes, it does make a lot of sense. Don't you think we need to do EXPORT_SYMBOL for __compute_return_epc as well? So it could be used by klms. Actually we have yet another copy of it in mips uprobes code, which normally is built as klm, if we refactor and export __compute_return_epc all three places could use the same function. Thanks, Victor > and > the 2nd patch to deal with kprobes. > > Thanks, > > Ralf > From ralf@linux-mips.org Fri Oct 14 00:59:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Oct 2011 00:59:35 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52280 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491849Ab1JMW7b (ORCPT ); Fri, 14 Oct 2011 00:59:31 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p9DMxKqd002403; Thu, 13 Oct 2011 23:59:20 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p9DMxI4v002394; Thu, 13 Oct 2011 23:59:18 +0100 Date: Thu, 13 Oct 2011 23:59:18 +0100 From: Ralf Baechle To: Victor Kamensky Cc: David Daney , manesoni@cisco.com, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ananth@in.ibm.com Subject: Re: [PATCH] MIPS Kprobes: Support branch instructions probing Message-ID: <20111013225918.GA12513@linux-mips.org> References: <20111013090749.GB16761@cisco.com> <4E971FD3.2020308@cavium.com> <20111013180714.GA7422@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31236 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9676 Content-Length: 675 Lines: 16 On Thu, Oct 13, 2011 at 12:16:27PM -0700, Victor Kamensky wrote: > Yes, it does make a lot of sense. Don't you think we need to do > EXPORT_SYMBOL for __compute_return_epc as well? So it could be used by > klms. > > Actually we have yet another copy of it in mips uprobes code, which > normally is built as klm, if we refactor and export __compute_return_epc > all three places could use the same function. Nothing wrong with exporting __compute_return_epc() as long as there are actually users of the exported symbol. So far it's only used from the kernel proper which is why it's not been exported. However I'd prefer it to be exported as EXPORT_SYMBOL_GPL(). Ralf From pebolle@tiscali.nl Fri Oct 14 14:30:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Oct 2011 14:30:29 +0200 (CEST) Received: from smtp-out2.tiscali.nl ([195.241.79.177]:33521 "EHLO smtp-out2.tiscali.nl" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491106Ab1JNMaU (ORCPT ); Fri, 14 Oct 2011 14:30:20 +0200 Received: from [212.123.169.34] (helo=[192.168.1.101]) by smtp-out2.tiscali.nl with esmtp (Exim) (envelope-from ) id 1REgu3-0007Ez-60; Fri, 14 Oct 2011 14:30:19 +0200 Subject: [PATCH 14/21] mips: drop unused Kconfig symbols From: Paul Bolle To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Date: Fri, 14 Oct 2011 14:29:51 +0200 Message-ID: <1318595391.6132.72.camel@x61.thuisdomein> Mime-Version: 1.0 X-Mailer: Evolution 2.32.3 (2.32.3-1.fc14) Content-Transfer-Encoding: 7bit X-archive-position: 31237 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pebolle@tiscali.nl Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10217 Content-Length: 2502 Lines: 90 Signed-off-by: Paul Bolle --- arch/mips/Kconfig | 14 -------------- arch/mips/powertv/Kconfig | 2 -- arch/mips/powertv/asic/Kconfig | 28 ---------------------------- 3 files changed, 0 insertions(+), 44 deletions(-) delete mode 100644 arch/mips/powertv/asic/Kconfig diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b122adc..6b1e0dd 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -823,10 +823,6 @@ config ARCH_HAS_ILOG2_U64 bool default n -config ARCH_SUPPORTS_OPROFILE - bool - default y if !MIPS_MT_SMTC - config GENERIC_HWEIGHT bool default y @@ -2258,16 +2254,6 @@ config HZ source "kernel/Kconfig.preempt" -config MIPS_INSANE_LARGE - bool "Support for large 64-bit configurations" - depends on CPU_R10000 && 64BIT - help - MIPS R10000 does support a 44 bit / 16TB address space as opposed to - previous 64-bit processors which only supported 40 bit / 1TB. If you - need processes of more than 1TB virtual address space, say Y here. - This will result in additional memory usage, so it is not - recommended for normal users. - config KEXEC bool "Kexec system call (EXPERIMENTAL)" depends on EXPERIMENTAL diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig index ff0e7e3..1a1b03e 100644 --- a/arch/mips/powertv/Kconfig +++ b/arch/mips/powertv/Kconfig @@ -1,5 +1,3 @@ -source "arch/mips/powertv/asic/Kconfig" - config BOOTLOADER_DRIVER bool "PowerTV Bootloader Driver Support" default n diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig deleted file mode 100644 index 2016bfe..0000000 --- a/arch/mips/powertv/asic/Kconfig +++ /dev/null @@ -1,28 +0,0 @@ -config MIN_RUNTIME_RESOURCES - bool "Support for minimum runtime resources" - default n - depends on POWERTV - help - Enables support for minimizing the number of (SA asic) runtime - resources that are preallocated by the kernel. - -config MIN_RUNTIME_DOCSIS - bool "Support for minimum DOCSIS resource" - default y - depends on MIN_RUNTIME_RESOURCES - help - Enables support for the preallocated DOCSIS resource. - -config MIN_RUNTIME_PMEM - bool "Support for minimum PMEM resource" - default y - depends on MIN_RUNTIME_RESOURCES - help - Enables support for the preallocated Memory resource. - -config MIN_RUNTIME_TFTP - bool "Support for minimum TFTP resource" - default y - depends on MIN_RUNTIME_RESOURCES - help - Enables support for the preallocated TFTP resource. -- 1.7.4.4 From dhillf@gmail.com Fri Oct 14 15:09:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Oct 2011 15:09:49 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:52886 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491023Ab1JNNJn (ORCPT ); Fri, 14 Oct 2011 15:09:43 +0200 Received: by wyi11 with SMTP id 11so3682456wyi.36 for ; Fri, 14 Oct 2011 06:09:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=wT6pf7V5Z7C+x+EMT2UVHGikKdnfQBqGA1EWx9u4LGU=; b=FiDCEsnCIzhhHeOLsXqMJljwdF7uA5ePJ5atsCZZAP8GwHLYh2k32FkfA4xZkQIY49 ZwhYQ0WFqDWs7DTYq/UBcSFNEB8RTL2+qp87Rt5ckxCuU1YdWO7tJ5mD/0t1M6NDdAuc +M5CrOhSB1DbubQbdEcQiI3LWYS4I94vYh9TA= MIME-Version: 1.0 Received: by 10.216.220.158 with SMTP id o30mr2947555wep.58.1318597777726; Fri, 14 Oct 2011 06:09:37 -0700 (PDT) Received: by 10.216.73.193 with HTTP; Fri, 14 Oct 2011 06:09:37 -0700 (PDT) In-Reply-To: <4E932897.9050301@cavium.com> References: <4E932897.9050301@cavium.com> Date: Fri, 14 Oct 2011 21:09:37 +0800 Message-ID: Subject: Re: [RFC] Flush huge TLB From: Hillf Danton To: David Daney Cc: Ralf Baechle , linux-mips@linux-mips.org, "Jayachandran C." Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: base64 X-archive-position: 31238 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10262 Content-Length: 7210 Lines: 94 T24gVHVlLCBPY3QgMTEsIDIwMTEgYXQgMToxNyBBTSwgRGF2aWQgRGFuZXkgPGRhdmlkLmRhbmV5 QGNhdml1bS5jb20+IHdyb3RlOgo+IE9uIDEwLzA5LzIwMTEgMDU6NTMgQU0sIEhpbGxmIERhbnRv biB3cm90ZToKPj4KPj4gV2hlbiBmbHVzaGluZyBUTEIsIGlmIEB2bWEgaXMgYmFja2VkIGJ5IGh1 Z2UgcGFnZSwgaHVnZSBUTEIgc2hvdWxkIGJlCj4+IGZsdXNoZWQsCj4+IGR1ZSB0byB0aGUgZmFj dCB0aGF0IGh1Z2UgcGFnZSBpcyBkZWZpbmVkIHRvIGJlIGZhciBmcm9tIG5vcm1hbCBwYWdlLCBh bmQKPj4gdGhlCj4+IGZsdXNoaW5nIGlzIHNob3J0ZW4gYSBiaXQuCj4+Cj4+IEFueSBjb21tZW50 IGlzIHdlbGNvbWUuCj4+Cj4KPiBOb3RlIHRoYXQgdGhlIGN1cnJlbnQgaW1wbGVtZW50YXRpb24g d29ya3MsIGJ1dCBpcyBub3Qgb3B0aW1hbC4KPgo+PiBUaGFua3MKPj4KPj4gU2lnbmVkLW9mZi1i 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d=cisco.com; i=manesoni@cisco.com; l=2602; q=dns/txt; s=iport; t=1318613318; x=1319822918; h=date:from:to:cc:subject:message-id:reply-to:references: mime-version:in-reply-to; bh=SsVo/wNCYiiAEZNZ+I+6NS7fn1aLzYkcNgQqQsnAMTU=; b=ATCxbf3PpFeldhQd/8D9FCCxJ/lYQjqNx+sh1xQOypvi+sq9QDrHXW+K cOWDl/sXKTyfqb0AuNcOELU2N6USqhqdLrWLgyoAvtr8n1VKJX7YSQdhS FUOG5YvcY/dyQ4d55nmKEZi8r+A/CzuK8UlLFmt+wNoaWOBkcIjrgeW3v U=; X-IronPort-AV: E=Sophos;i="4.69,347,1315180800"; d="scan'208";a="1047933" Received: from ams-core-4.cisco.com ([144.254.72.77]) by ams-iport-3.cisco.com with ESMTP; 14 Oct 2011 17:28:32 +0000 Received: from manesoni-ws.cisco.com ([10.65.83.37]) by ams-core-4.cisco.com (8.14.3/8.14.3) with ESMTP id p9EHSVTs002371; Fri, 14 Oct 2011 17:28:32 GMT Received: by manesoni-ws.cisco.com (Postfix, from userid 1001) id 780AD81CA3; Fri, 14 Oct 2011 22:58:31 +0530 (IST) Date: Fri, 14 Oct 2011 22:58:31 +0530 From: Maneesh Soni To: David Daney Cc: ralf@linux-mips.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ananth@in.ibm.com, kamensky@cisco.com Subject: Re: [PATCH] MIPS Kprobes: Support branch instructions probing Message-ID: <20111014172831.GA8521@cisco.com> Reply-To: manesoni@cisco.com References: <20111013090749.GB16761@cisco.com> <4E971FD3.2020308@cavium.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4E971FD3.2020308@cavium.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 31239 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manesoni@cisco.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10582 Content-Length: 2521 Lines: 81 On Thu, Oct 13, 2011 at 10:28:51AM -0700, David Daney wrote: > On 10/13/2011 02:07 AM, Maneesh Soni wrote: > > > >From: Maneesh Soni > > > >This patch provides support for kprobes on branch instructions. The branch > >instruction at the probed address is actually emulated and not executed > >out-of-line like other normal instructions. Instead the delay-slot instruction > >is copied and single stepped out of line. > > > >At the time of probe hit, the original branch instruction is evaluated > >and the target cp0_epc is computed similar to compute_retrun_epc(). It > >is also checked if the delay slot instruction can be skipped, which is > >true if there is a NOP in delay slot or branch is taken in case of > >branch likely instructions. Once the delay slot instruction is single > >stepped the normal execution resume with the cp0_epc updated the earlier > >computed cp0_epc as per the branch instructions. > > > > I haven't tested it but... > > > >Signed-off-by: Maneesh Soni > >--- > > arch/mips/include/asm/kprobes.h | 7 + > > arch/mips/kernel/kprobes.c | 341 +++++++++++++++++++++++++++++++++++---- > > 2 files changed, 320 insertions(+), 28 deletions(-) > > > [...] > >+static int evaluate_branch_instruction(struct kprobe *p, struct pt_regs *regs, > >+ struct kprobe_ctlblk *kcb) > > { > >+ union mips_instruction insn = p->opcode; > >+ unsigned int dspcontrol; > >+ long epc; > >+ > >+ epc = regs->cp0_epc; > >+ if (epc& 3) > >+ goto unaligned; > >+ > >+ if (p->ainsn.insn->word == 0) > >+ kcb->flags |= SKIP_DELAYSLOT; > >+ else > >+ kcb->flags&= ~SKIP_DELAYSLOT; > >+ > >+ switch (insn.i_format.opcode) { > >+ /* > >+ * jr and jalr are in r_format format. > >+ */ > >+ case spec_op: > [...] > >+ case bgtzl_op: > >+ /* rt field assumed to be zero */ > >+ if ((long)regs->regs[insn.i_format.rs]> 0) { > >+ epc = epc + 4 + (insn.i_format.simmediate<< 2); > >+ kcb->flags |= SKIP_DELAYSLOT; > >+ } else > >+ epc += 8; > >+ regs->cp0_epc = epc; > >+ break; > > > > Where is the handling for: > > case cop1_op: > > #ifdef CONFIG_CPU_CAVIUM_OCTEON > case lwc2_op: /* This is bbit0 on Octeon */ > case ldc2_op: /* This is bbit032 on Octeon */ > case swc2_op: /* This is bbit1 on Octeon */ > case sdc2_op: /* This is bbit132 on Octeon */ > #endif > > These are all defined in insn_has_delayslot() but not here. My bad.. will include them as well. Actually as Ralf suggested, will keep this as common code. Thanks Maneesh From manesoni@cisco.com Fri Oct 14 19:31:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Oct 2011 19:31:26 +0200 (CEST) Received: from ams-iport-2.cisco.com ([144.254.224.141]:32937 "EHLO ams-iport-2.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491102Ab1JNRbS (ORCPT ); Fri, 14 Oct 2011 19:31:18 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=manesoni@cisco.com; l=1066; q=dns/txt; s=iport; t=1318613478; x=1319823078; h=date:from:to:cc:subject:message-id:reply-to:references: mime-version:in-reply-to; bh=sgyZMNQx0Srr5JqvCixPcO9cNQZYQaevx2IfCu0J5wU=; b=J2B9M7Hca+3vX2ADUEQljjwGgEg4p143ZPkKhup37ROUWnzy9FWSVGnt fijuVm8kqlPi8Q4bRQkwbUH62KvrauoNig9U37lbtyGkcIcaTfBrD/uWE I96+nWMWDI0UTJAM6YQQ30Zol3i1Kz3s1PjPHF4rolFOhtNcM+F4tkvSu 4=; X-IronPort-AV: E=Sophos;i="4.69,347,1315180800"; d="scan'208";a="57827076" Received: from ams-core-4.cisco.com ([144.254.72.77]) by ams-iport-2.cisco.com with ESMTP; 14 Oct 2011 17:31:12 +0000 Received: from manesoni-ws.cisco.com ([10.65.83.37]) by ams-core-4.cisco.com (8.14.3/8.14.3) with ESMTP id p9EHVBK7002818; Fri, 14 Oct 2011 17:31:12 GMT Received: by manesoni-ws.cisco.com (Postfix, from userid 1001) id 76F8581CA3; Fri, 14 Oct 2011 23:01:11 +0530 (IST) Date: Fri, 14 Oct 2011 23:01:11 +0530 From: Maneesh Soni To: Ralf Baechle Cc: David Daney , linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ananth@in.ibm.com, kamensky@cisco.com Subject: Re: [PATCH] MIPS Kprobes: Support branch instructions probing Message-ID: <20111014173111.GB8521@cisco.com> Reply-To: manesoni@cisco.com References: <20111013090749.GB16761@cisco.com> <4E971FD3.2020308@cavium.com> <20111013180714.GA7422@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20111013180714.GA7422@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 31240 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manesoni@cisco.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10585 Content-Length: 1034 Lines: 32 On Thu, Oct 13, 2011 at 07:07:14PM +0100, Ralf Baechle wrote: > On Thu, Oct 13, 2011 at 10:28:51AM -0700, David Daney wrote: > > > Where is the handling for: > > > > case cop1_op: > > > > #ifdef CONFIG_CPU_CAVIUM_OCTEON > > case lwc2_op: /* This is bbit0 on Octeon */ > > case ldc2_op: /* This is bbit032 on Octeon */ > > case swc2_op: /* This is bbit1 on Octeon */ > > case sdc2_op: /* This is bbit132 on Octeon */ > > #endif > > > > These are all defined in insn_has_delayslot() but not here. > > Which is a wonderful demonstration for why duplicating such a large > function from branch.c was a baaad thing to do. > > Maneesh, can you refactor the code to share everything that was copied > from __compute_return_epc() can be shared with kprobes? Idealy make > everything a two part series, first one patch to refactor branch.c and > the 2nd patch to deal with kprobes. > Sure.. the branch likely instructions are not make it look good but still do it in the next version. Thanks for the comments. Regards, Maneesh From wuzhangjin@gmail.com Sat Oct 15 04:37:12 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 15 Oct 2011 04:37:17 +0200 (CEST) Received: from mail-iy0-f177.google.com ([209.85.210.177]:52922 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490964Ab1JOChM (ORCPT ); Sat, 15 Oct 2011 04:37:12 +0200 Received: by iarr31 with SMTP id r31so3933182iar.36 for ; Fri, 14 Oct 2011 19:37:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type; bh=71IBgndisftPrNZ4bVQ02Qs1zKqsdl4OayAJZ4/BkQI=; b=nQn4a8sW4NlWTot1K5YHLGMWJqhMAcKXRlMlYYbhJhK19oGEbZnJ28miRPW0TXBmyd BFc2eNcaYZWVI/vx5IHfCOfcPbxJSEt3EIosVlE85vgfMbV+8G0tlAuIVmemKpbBxzVy TcqG8vgoE2mFH+rk2nREGld/GgZf3D+L309dE= MIME-Version: 1.0 Received: by 10.231.68.136 with SMTP id v8mr3609625ibi.51.1318646226145; Fri, 14 Oct 2011 19:37:06 -0700 (PDT) Received: by 10.231.59.135 with HTTP; Fri, 14 Oct 2011 19:37:06 -0700 (PDT) In-Reply-To: <20111012190659.GC15003@mails.so.argh.org> References: <20111012190659.GC15003@mails.so.argh.org> Date: Sat, 15 Oct 2011 10:37:06 +0800 Message-ID: Subject: Re: YeeLoong / hotkey driver From: wu zhangjin To: Andreas Barth , Wu Zhangjin , linux-mips@linux-mips.org, debian-mips@lists.debian.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 31241 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10929 Content-Length: 859 Lines: 32 On Thu, Oct 13, 2011 at 3:06 AM, Andreas Barth wrote: > Hi, > > there is currently a mail thread about the hotkeys not working with > the default debian kernel. After a bit of search, I noticed the > patches within > http://www.linux-mips.org/archives/linux-mips/2009-11/msg00598.html > however I didn't find a conclusion. > > Do you remember (or does anyone else) what happened to the patches or > how we could get hotkey support into the default kernels? Thanks! The latest version is here: http://dev.lemote.com/cgit/linux-loongson-community.git/tree/drivers/platform/mips/yeeloong_laptop.c?h=linux-3.0-stable It may be related to some other changes, please get more info from: http://dev.lemote.com/cgit/linux-loongson-community.git/ or http://dev.lemote.com/code/linux-loongson-community Regards, Wu Zhangjin > > > > Andi > From wuzhangjin@gmail.com Sat Oct 15 04:50:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 15 Oct 2011 04:51:03 +0200 (CEST) Received: from mail-iy0-f177.google.com ([209.85.210.177]:59243 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490964Ab1JOCuz convert rfc822-to-8bit (ORCPT ); Sat, 15 Oct 2011 04:50:55 +0200 Received: by iarr31 with SMTP id r31so3944350iar.36 for ; Fri, 14 Oct 2011 19:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=Kr7t6/fQTcPDLei54ZEWdQ+XtPdEk5iRkOMHYc2r8bc=; b=nUYq7hzuVQj/xagCNXaxWWBgQOyCo/6xZohUTbjg2jg+RDoieMXsAJVJl3jrityn/W Ce+SSzfMEdEtWA57fFKRl51eS3seCwvMXFrUNJoB6MRTDoomCglppdqhN2jF+ougLmAM 7LkF0fGpLJJrZMdgvgH3gyueHRihPZnlM0RZw= MIME-Version: 1.0 Received: by 10.231.45.135 with SMTP id e7mr377109ibf.12.1318647049062; Fri, 14 Oct 2011 19:50:49 -0700 (PDT) Received: by 10.231.59.135 with HTTP; Fri, 14 Oct 2011 19:50:49 -0700 (PDT) In-Reply-To: <20111013080412.GA17240@linux-mips.org> References: <20111012190659.GC15003@mails.so.argh.org> <20111013080412.GA17240@linux-mips.org> Date: Sat, 15 Oct 2011 10:50:49 +0800 Message-ID: Subject: Re: YeeLoong / hotkey driver From: wu zhangjin To: Ralf Baechle Cc: Andreas Barth , linux-mips@linux-mips.org, debian-mips@lists.debian.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 31242 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10930 Content-Length: 1041 Lines: 31 On Thu, Oct 13, 2011 at 4:04 PM, Ralf Baechle wrote: > On Wed, Oct 12, 2011 at 09:06:59PM +0200, Andreas Barth wrote: > >> there is currently a mail thread about the hotkeys not working with >> the default debian kernel. After a bit of search, I noticed the >> patches within >> http://www.linux-mips.org/archives/linux-mips/2009-11/msg00598.html >> however I didn't find a conclusion. >> >> Do you remember (or does anyone else) what happened to the patches or >> how we could get hotkey support into the default kernels? Thanks! > > Back then a debate started and no updated version of the patch was ever > posted.  But nothing fundamentally wrong with the patch. The old patch is out-of-date, perhaps we can start a new trip to upstream the latest version maintained at http://dev.lemote.com/code/linux-loongson-community. The latest one threaded the irq interrupt handler and fixed some bugs. Hope somebody else can work on it for I'm a little busy currently ;-) Thanks Ralf, Regards, Wu Zhangjin > >  Ralf > From miloody@gmail.com Mon Oct 17 13:36:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Oct 2011 13:36:22 +0200 (CEST) Received: from mail-yw0-f49.google.com ([209.85.213.49]:45877 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491026Ab1JQLgS (ORCPT ); Mon, 17 Oct 2011 13:36:18 +0200 Received: by ywe9 with SMTP id 9so715862ywe.36 for ; Mon, 17 Oct 2011 04:36:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; bh=8EllmUJZFEhOAi8ogaDX0Glc68u8lyvhglXzNYaR8CQ=; b=xvKb0x/aBHXFvFcDgRzTDMMNLlVQlWBQSTqldgq3JvBIKIOi+pN1tEZ+EFbwimriYw t5FVK6f4hZ+o3/8adCra7SBroK2yihU3j8o6y9j3W075lUmjI9f8eDIXKv933f2P4YvM eVQ8883XEezmGucHByGxMB0T/aVeFXsdhfdXA= MIME-Version: 1.0 Received: by 10.42.154.7 with SMTP id o7mr37821821icw.48.1318851371675; Mon, 17 Oct 2011 04:36:11 -0700 (PDT) Received: by 10.42.170.1 with HTTP; Mon, 17 Oct 2011 04:36:11 -0700 (PDT) Date: Mon, 17 Oct 2011 19:36:11 +0800 Message-ID: Subject: some questions about translation lookaside buffer From: loody To: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 31244 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 11767 Content-Length: 675 Lines: 19 Dear all: I have some questions about local_flush_tlb_one. 1. what will happen if I use local_flush_tlb_one to flush a page that doesn't exist in translation lookaside buffer entries. The index return by read_c0_index(), should be negative. but this function seems not handle the case that idx < 0. 2. as I know, translation lookaside buffer is a place to keep record the memory mapping, it doesn't like cache have place to store the data. a. If the entry is cacheable, what we only to do is flush the cache? b. if the entry is uncached, there is nothing to do? if above b is correct, what will happen if we have an entry that is uncached and dirty? -- Regards, From ralf@linux-mips.org Mon Oct 17 16:57:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Oct 2011 16:57:10 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35738 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491031Ab1JQO5F (ORCPT ); Mon, 17 Oct 2011 16:57:05 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p9HEv3G9026072; Mon, 17 Oct 2011 15:57:03 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p9HEv3uu026071; Mon, 17 Oct 2011 15:57:03 +0100 Date: Mon, 17 Oct 2011 15:57:03 +0100 From: Ralf Baechle To: loody Cc: Linux MIPS Mailing List Subject: Re: some questions about translation lookaside buffer Message-ID: <20111017145702.GC10290@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31245 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 11977 Content-Length: 1086 Lines: 27 On Mon, Oct 17, 2011 at 07:36:11PM +0800, loody wrote: > Dear all: > I have some questions about local_flush_tlb_one. > 1. what will happen if I use local_flush_tlb_one to flush a page that > doesn't exist in translation lookaside buffer entries. > > The index return by read_c0_index(), should be negative. > but this function seems not handle the case that idx < 0. > > 2. as I know, translation lookaside buffer is a place to keep record > the memory mapping, it doesn't like cache have place to store the > data. > a. If the entry is cacheable, what we only to do is flush the cache? > b. if the entry is uncached, there is nothing to do? > if above b is correct, what will happen if we have an entry that is > uncached and dirty? If c0_index contains a value < 0 (or rather one with bit 31 set) then there is nothing that needs to be flushed. Note that MIPS D-cache (I-caches don't get written back so are not of concern) are tagged with a physical address so cache handling is no consideration for local_flush_tlb_one or any of the other TLB flush functions. Ralf From miloody@gmail.com Mon Oct 17 18:17:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Oct 2011 18:17:33 +0200 (CEST) Received: from mail-gy0-f177.google.com ([209.85.160.177]:59553 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491177Ab1JQQR2 convert rfc822-to-8bit (ORCPT ); Mon, 17 Oct 2011 18:17:28 +0200 Received: by gyd10 with SMTP id 10so3622163gyd.36 for ; Mon, 17 Oct 2011 09:17:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=ARUvrYy8mqH88BXTyHdjc57zKx2D6716ZbxyKEUk8S4=; b=Pd71hz5g9Iu02CcT0pchFmMyQVVgMDxaMxgbfLhE61SxxqyvC6rQEHgJpqZHnRF4x3 A0xImZb5pFt+BC0D4HPMgDOg6b8tI4BZVQPusmTWCLpsmIrcau6XpWfnbMUgbaQakvV1 R/CQdqpm/c9rTWJ5504qkX8gggD40FxXzDKSA= MIME-Version: 1.0 Received: by 10.42.161.70 with SMTP id s6mr39669956icx.40.1318868241792; Mon, 17 Oct 2011 09:17:21 -0700 (PDT) Received: by 10.42.170.1 with HTTP; Mon, 17 Oct 2011 09:17:21 -0700 (PDT) In-Reply-To: <20111017145702.GC10290@linux-mips.org> References: <20111017145702.GC10290@linux-mips.org> Date: Tue, 18 Oct 2011 00:17:21 +0800 Message-ID: Subject: Re: some questions about translation lookaside buffer From: loody To: Ralf Baechle Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 31246 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12058 Content-Length: 1606 Lines: 38 hi ralf: Thanks for your reply :) 2011/10/17 Ralf Baechle : > On Mon, Oct 17, 2011 at 07:36:11PM +0800, loody wrote: > >> Dear all: >> I have some questions about local_flush_tlb_one. >> 1. what will happen if I use local_flush_tlb_one to flush a page that >> doesn't exist in translation lookaside buffer entries. >> >> The index return by read_c0_index(), should be negative. >> but this function seems not handle the case that idx < 0. >> >> 2. as I know, translation lookaside buffer is a place to keep record >> the memory mapping, it doesn't like cache have place to store the >> data. >>     a. If the entry is cacheable, what we only to do is flush the cache? >>     b. if the entry is uncached, there is nothing to do? >> if above b is correct, what will happen if we have an entry that is >> uncached and dirty? > > If c0_index contains a value < 0 (or rather one with bit 31 set) then > there is nothing that needs to be flushed. but how about the case of c0_index >= 0, I found the code tried to write the index with entry_lo0 and entry_lo1 as 0. it seems clear the PFN part of the index. So it is the flush action? > > Note that MIPS D-cache (I-caches don't get written back so are not of > concern) are tagged with a physical address so cache handling is no > consideration for local_flush_tlb_one or any of the other TLB flush > functions. why tlb flush functions don't need to take care cache handling? if tlb flush don't need to care cache, what is tlb flush used for, since tlb is nothing but a place to do the address translation, right? -- Appreciate your help, From florian@openwrt.org Mon Oct 17 19:43:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Oct 2011 19:43:12 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:53694 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491177Ab1JQRnG (ORCPT ); Mon, 17 Oct 2011 19:43:06 +0200 Received: by wyg8 with SMTP id 8so1968623wyg.36 for ; Mon, 17 Oct 2011 10:43:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:mime-version:content-type :content-transfer-encoding:message-id; bh=QEI7NqYxWsPFonW3RDDusrVTC8XzBo5Yh4vrhZ97MyA=; b=mQytI7Iv/IwJYXv0+zLVqMS558Q7urikQGpPzyqpXITdby0Yq/7EPg2Zou2uIyxwWr mRp+iXlNPJSm7TJHXhEXTCoNLgQo8uYAdslV6ED7Lc3Ub8EcN8fXuMiVSKGvuAc4uYdV ui4/kDkn21XAQg1jc07BrJzPH2V42C2BTMhAY= Received: by 10.227.199.18 with SMTP id eq18mr6650360wbb.61.1318873380195; Mon, 17 Oct 2011 10:43:00 -0700 (PDT) Received: from lenovo.localnet (fbx.mimichou.net. [82.247.4.1]) by mx.google.com with ESMTPS id z9sm32337453wbn.19.2011.10.17.10.42.58 (version=SSLv3 cipher=OTHER); Mon, 17 Oct 2011 10:42:59 -0700 (PDT) From: Florian Fainelli To: ralf@linux-mips.org, linux-mips@linux-mips.org, Greg KH Subject: [PATCH] Revert "MIPS: MTX-1: Make au1000_eth probe all PHY Date: Mon, 17 Oct 2011 19:43:06 +0200 User-Agent: KMail/1.13.7 (Linux/3.1.0-rc7-amd64; KDE/4.6.5; x86_64; ; ) MIME-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-Id: <201110171943.06143.florian@openwrt.org> X-archive-position: 31247 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12148 Content-Length: 1137 Lines: 41 Commit ec3eb823 was not applicable in 2.6.32 and introduces a build breakage. Revert that commit since it is irrelevant for this kernel version. CC: stable@kernel.org Signed-off-by: Florian Fainelli --- Greg, this is applicable from 2.6.32+ to 2.6.33+ included. diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c index 956f946..e30e42a 100644 --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/mtx-1/platform.c @@ -28,8 +28,6 @@ #include #include -#include - static struct gpio_keys_button mtx1_gpio_button[] = { { .gpio = 207, @@ -142,17 +140,10 @@ static struct __initdata platform_device * mtx1_devs[] = { &mtx1_mtd, }; -static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = { - .phy_search_highest_addr = 1, - .phy1_search_mac0 = 1, -}; - static int __init mtx1_register_devices(void) { int rc; - au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata); - rc = gpio_request(mtx1_gpio_button[0].gpio, mtx1_gpio_button[0].desc); if (rc < 0) { -- 1.7.5.4 From proge@riseup.net Tue Oct 18 02:34:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Oct 2011 02:34:51 +0200 (CEST) Received: from mx1.riseup.net ([204.13.164.18]:39531 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491184Ab1JRAen (ORCPT ); Tue, 18 Oct 2011 02:34:43 +0200 Received: from fruiteater.riseup.net (fruiteater-pn.riseup.net [10.0.1.74]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "*.riseup.net", Issuer "Gandi Standard SSL CA" (verified OK)) by mx1.riseup.net (Postfix) with ESMTPS id 14B10596C7; Mon, 17 Oct 2011 17:34:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: proge@fruiteater.riseup.net) with ESMTPSA id BA8A05B7 Date: Mon, 17 Oct 2011 18:00:15 -0500 From: Paul Roge To: wu zhangjin Cc: Ralf Baechle , Andreas Barth , linux-mips@linux-mips.org, debian-mips@lists.debian.org Subject: Re: YeeLoong / hotkey driver Message-ID: <20111017180015.1e5fc4fe@dragon.agroecology> In-Reply-To: References: <20111012190659.GC15003@mails.so.argh.org> <20111013080412.GA17240@linux-mips.org> X-Mailer: Claws Mail 3.7.6 (GTK+ 2.20.1; mipsel-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/cGZhmzMQE5qKtYo/1vqe0Yq"; protocol="application/pgp-signature" X-Virus-Scanned: clamav-milter 0.97 at mx1 X-Virus-Status: Clean X-archive-position: 31248 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: proge@riseup.net Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12492 Content-Length: 1814 Lines: 47 --Sig_/cGZhmzMQE5qKtYo/1vqe0Yq Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable > The old patch is out-of-date, perhaps we can start a new trip to > upstream the latest version maintained at > http://dev.lemote.com/code/linux-loongson-community. >=20 > The latest one threaded the irq interrupt handler and fixed some bugs. >=20 > Hope somebody else can work on it for I'm a little busy currently ;-) Since I am new to configuring kernels, I doubt that I can help very much on= this.=20 The 3.0.4-libre-lemote kernel from http://linux-libre.fsfla.org/pub/linux-l= ibre/lemote/gnewsense has everything except hotkey support for wireless. Th= e CONFIG_RTL8187 and CONFIG_RTL8187B options are disabled in the config fil= e. Typing "echo 1 > /sys/class/rfkill/rfkill0/state" does nothing, even whe= n the kernel is reconfigured with those drivers enabled. The 2.36.8-loongson-2f kernel from http://bjlx.org.cn/loongson2f/squeeze ha= s functional hotkey and wireless networking capability. However, the date r= esets to 1968 when restarted, thus messing up certificates, and scrolling w= ith the keybad is disabled.=20 I would really appreciate suggestions for adding wireless/hotkey capability= to the 3.0.4-libre-lemote kernel, or fixing the date problem and adding th= e keybad scrolling capability on 2.36.8-loongson-2f! Should I add the patch= , modify options, or both?=20 Thanks! Paul --Sig_/cGZhmzMQE5qKtYo/1vqe0Yq Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEARECAAYFAk6cs38ACgkQuBW/tw9lDuQWVgCguqMlpZWNuQkr9kBaUf4TBT4X CNAAoLyH/Tf1pu5zES1Mt0sR/pWTPi60 =ZGWQ -----END PGP SIGNATURE----- --Sig_/cGZhmzMQE5qKtYo/1vqe0Yq-- From aaro.koskinen@iki.fi Thu Oct 20 00:33:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 20 Oct 2011 00:33:33 +0200 (CEST) Received: from filtteri1.pp.htv.fi ([213.243.153.184]:56588 "EHLO filtteri1.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491105Ab1JSWd3 (ORCPT ); Thu, 20 Oct 2011 00:33:29 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri1.pp.htv.fi (Postfix) with ESMTP id 358928BBAC; Thu, 20 Oct 2011 01:33:28 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp6.welho.com ([213.243.153.40]) by localhost (filtteri1.pp.htv.fi [213.243.153.184]) (amavisd-new, port 10024) with ESMTP id 3EWl2D2TFavC; Thu, 20 Oct 2011 01:33:27 +0300 (EEST) Received: from dell.pp.htv.fi (cs178075134192.pp.htv.fi [178.75.134.192]) by smtp6.welho.com (Postfix) with ESMTP id A9E435BC005; Thu, 20 Oct 2011 01:33:27 +0300 (EEST) From: Aaro Koskinen To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH] mips: fix the build with C=1 Date: Thu, 20 Oct 2011 01:33:27 +0300 Message-Id: <1319063607-11316-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 31249 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14485 Content-Length: 1895 Lines: 61 When trying to compile the 3.1-rc10 kernel for my MIPS board with C=1 (sparse checking), the build fails early with the error: CHK include/linux/version.h UPD include/linux/version.h CHK include/generated/utsrelease.h UPD include/generated/utsrelease.h Checking missing-syscalls for N32 CALL scripts/checksyscalls.sh Checking missing-syscalls for O32 CALL scripts/checksyscalls.sh CC kernel/bounds.s GEN include/generated/bounds.h CC arch/mips/kernel/asm-offsets.s GEN include/generated/asm-offsets.h CALL scripts/checksyscalls.sh HOSTCC scripts/genksyms/genksyms.o SHIPPED scripts/genksyms/lex.lex.c SHIPPED scripts/genksyms/keywords.hash.c SHIPPED scripts/genksyms/parse.tab.h HOSTCC scripts/genksyms/lex.lex.o SHIPPED scripts/genksyms/parse.tab.c HOSTCC scripts/genksyms/parse.tab.o HOSTLD scripts/genksyms/genksyms /bin/sh: Syntax error: "(" unexpected make[3]: *** [scripts/mod/empty.o] Error 2 make[2]: *** [scripts/mod] Error 2 make[1]: *** [scripts] Error 2 It seems the shell chokes because sparse is called with command line arguments such as: -D__INT8_C(c)='c' Converting these to form: -D'__INT8_C(c)'='c' seems to fix the problem. Signed-off-by: Aaro Koskinen --- arch/mips/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 53e3514..30346b0 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -226,7 +226,7 @@ LDFLAGS += -m $(ld-emul) ifdef CONFIG_MIPS CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -xc /dev/null | \ egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \ - sed -e 's/^\#define /-D/' -e "s/ /='/" -e "s/$$/'/") + sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e "s/$$/'/") ifdef CONFIG_64BIT CHECKFLAGS += -m64 endif -- 1.7.2.5 From ralf@linux-mips.org Thu Oct 20 15:32:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 20 Oct 2011 15:33:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41844 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491152Ab1JTNcy (ORCPT ); Thu, 20 Oct 2011 15:32:54 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p9KDWoFC007427; Thu, 20 Oct 2011 14:32:50 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p9KDWmRK007408; Thu, 20 Oct 2011 14:32:48 +0100 Date: Thu, 20 Oct 2011 14:32:48 +0100 From: Ralf Baechle To: Aaro Koskinen Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: fix the build with C=1 Message-ID: <20111020133248.GA20032@linux-mips.org> References: <1319063607-11316-1-git-send-email-aaro.koskinen@iki.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1319063607-11316-1-git-send-email-aaro.koskinen@iki.fi> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31250 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14974 Content-Length: 275 Lines: 10 On Thu, Oct 20, 2011 at 01:33:27AM +0300, Aaro Koskinen wrote: > When trying to compile the 3.1-rc10 kernel for my MIPS board with C=1 > (sparse checking), the build fails early with the error: This is triggered by builds with GCC 4.5 and newer. Applied. Thanks! Ralf From tsbogend@alpha.franken.de Thu Oct 20 17:09:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 20 Oct 2011 17:09:37 +0200 (CEST) Received: from elvis.franken.de ([193.175.24.41]:33513 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491152Ab1JTPJ2 (ORCPT ); Thu, 20 Oct 2011 17:09:28 +0200 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1RGuFL-0008H4-00; Thu, 20 Oct 2011 17:09:27 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 6072A1DA26; Thu, 20 Oct 2011 17:08:59 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] GIO bus support for SGI IP22/28 To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20111020150859.6072A1DA26@solo.franken.de> Date: Thu, 20 Oct 2011 17:08:59 +0200 (CEST) X-archive-position: 31251 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 15075 Content-Length: 17406 Lines: 679 SGI IP22/IP28 machines have GIO busses for adding graphics and other extension cards. This patch adds support for GIO driver/device handling and converts the newport console driver to a GIO driver. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/gio_device.h | 56 +++++ arch/mips/sgi-ip22/Makefile | 2 +- arch/mips/sgi-ip22/ip22-gio.c | 408 +++++++++++++++++++++++++++++++++++ arch/mips/sgi-ip22/ip22-mc.c | 10 +- arch/mips/sgi-ip22/ip22-setup.c | 21 -- drivers/video/console/newport_con.c | 61 ++++-- 6 files changed, 512 insertions(+), 46 deletions(-) diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h new file mode 100644 index 0000000..5437c84 --- /dev/null +++ b/arch/mips/include/asm/gio_device.h @@ -0,0 +1,56 @@ +#include +#include + +struct gio_device_id { + __u8 id; +}; + +struct gio_device { + struct device dev; + struct resource resource; + unsigned int irq; + unsigned int slotno; + + const char *name; + struct gio_device_id id; + unsigned id32:1; + unsigned gio64:1; +}; +#define to_gio_device(d) container_of(d, struct gio_device, dev) + +struct gio_driver { + const char *name; + struct module *owner; + const struct gio_device_id *id_table; + + int (*probe)(struct gio_device *, const struct gio_device_id *); + void (*remove)(struct gio_device *); + int (*suspend)(struct gio_device *, pm_message_t); + int (*resume)(struct gio_device *); + void (*shutdown)(struct gio_device *); + + struct device_driver driver; +}; +#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver) + +extern const struct gio_device_id *gio_match_device(const struct gio_device_id *, + const struct gio_device *); +extern struct gio_device *gio_dev_get(struct gio_device *); +extern void gio_dev_put(struct gio_device *); + +extern int gio_device_register(struct gio_device *); +extern void gio_device_unregister(struct gio_device *); +extern void gio_release_dev(struct device *); + +static inline void gio_device_free(struct gio_device *dev) +{ + gio_release_dev(&dev->dev); +} + +extern int gio_register_driver(struct gio_driver *); +extern void gio_unregister_driver(struct gio_driver *); + +#define gio_get_drvdata(_dev) drv_get_drvdata(&(_dev)->dev) +#define gio_set_drvdata(_dev, data) drv_set_drvdata(&(_dev)->dev, (data)) + +extern void gio_set_master(struct gio_device *); diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile index cc53849..411cda9 100644 --- a/arch/mips/sgi-ip22/Makefile +++ b/arch/mips/sgi-ip22/Makefile @@ -4,7 +4,7 @@ # obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \ - ip22-platform.o ip22-reset.o ip22-setup.o + ip22-platform.o ip22-reset.o ip22-setup.o ip22-gio.o obj-$(CONFIG_SGI_IP22) += ip22-berr.o obj-$(CONFIG_SGI_IP28) += ip28-berr.o diff --git a/arch/mips/sgi-ip22/ip22-gio.c b/arch/mips/sgi-ip22/ip22-gio.c new file mode 100644 index 0000000..64fcabc --- /dev/null +++ b/arch/mips/sgi-ip22/ip22-gio.c @@ -0,0 +1,408 @@ +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +static struct bus_type gio_bus; + +static struct { + const char *name; + __u8 id; +} gio_name_table[] = { + { .name = "SGI Impact", .id = 0x10 }, + { .name = "Phobos G160", .id = 0x35 }, + /* fake IDs */ + { .name = "SGI Newport", .id = 0x7e }, + { .name = "SGI GR2/GR3", .id = 0x7f }, +}; + +/** + * gio_match_device - Tell if an of_device structure has a matching + * gio_match structure + * @ids: array of of device match structures to search in + * @dev: the of device structure to match against + * + * Used by a driver to check whether an of_device present in the + * system is in its list of supported devices. + */ +const struct gio_device_id *gio_match_device(const struct gio_device_id *match, + const struct gio_device *dev) +{ + const struct gio_device_id *ids; + + for (ids = match; ids->id != 0xff; ids++) + if (ids->id == dev->id.id) + return ids; + + return NULL; +} +EXPORT_SYMBOL(gio_match_device); + +struct gio_device *gio_dev_get(struct gio_device *dev) +{ + struct device *tmp; + + if (!dev) + return NULL; + tmp = get_device(&dev->dev); + if (tmp) + return to_gio_device(tmp); + else + return NULL; +} +EXPORT_SYMBOL(gio_dev_get); + +void gio_dev_put(struct gio_device *dev) +{ + if (dev) + put_device(&dev->dev); +} +EXPORT_SYMBOL(gio_dev_put); + +static ssize_t dev_show_name(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gio_device *giodev; + + giodev = to_gio_device(dev); + return sprintf(buf, "%s", giodev->name); +} + +static DEVICE_ATTR(name, S_IRUGO, dev_show_name, NULL); + +static ssize_t dev_show_id(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gio_device *giodev; + + giodev = to_gio_device(dev); + return sprintf(buf, "%x", giodev->id.id); +} + +static DEVICE_ATTR(id, S_IRUGO, dev_show_id, NULL); + +/** + * gio_release_dev - free an gio device structure when all users of it are finished. + * @dev: device that's been disconnected + * + * Will be called only by the device core when all users of this gio device are + * done. + */ +void gio_release_dev(struct device *dev) +{ + struct gio_device *giodev; + + giodev = to_gio_device(dev); + kfree(giodev); +} +EXPORT_SYMBOL(gio_release_dev); + +int gio_device_register(struct gio_device *giodev) +{ + int rc; + + giodev->dev.bus = &gio_bus; + rc = device_register(&giodev->dev); + if (rc) + return rc; + + rc = device_create_file(&giodev->dev, &dev_attr_name); + if (rc) + goto err; + rc = device_create_file(&giodev->dev, &dev_attr_id); + if (rc) + goto err; + + return 0; + +err: + device_unregister(&giodev->dev); + return rc; +} +EXPORT_SYMBOL(gio_device_register); + +void gio_device_unregister(struct gio_device *giodev) +{ + device_remove_file(&giodev->dev, &dev_attr_id); + device_remove_file(&giodev->dev, &dev_attr_name); + device_unregister(&giodev->dev); +} +EXPORT_SYMBOL(gio_device_unregister); + +static int gio_bus_match(struct device *dev, struct device_driver *drv) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *gio_drv = to_gio_driver(drv); + + return gio_match_device(gio_drv->id_table, gio_dev) != NULL; +} + +static int gio_device_probe(struct device *dev) +{ + int error = -ENODEV; + struct gio_driver *drv; + struct gio_device *gio_dev; + const struct gio_device_id *match; + + drv = to_gio_driver(dev->driver); + gio_dev = to_gio_device(dev); + + if (!drv->probe) + return error; + + gio_dev_get(gio_dev); + + match = gio_match_device(drv->id_table, gio_dev); + if (match) + error = drv->probe(gio_dev, match); + if (error) + gio_dev_put(gio_dev); + + return error; +} + +static int gio_device_remove(struct device *dev) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + + if (dev->driver && drv->remove) + drv->remove(gio_dev); + return 0; +} + +static int gio_device_suspend(struct device *dev, pm_message_t state) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + int error = 0; + + if (dev->driver && drv->suspend) + error = drv->suspend(gio_dev, state); + return error; +} + +static int gio_device_resume(struct device *dev) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + int error = 0; + + if (dev->driver && drv->resume) + error = drv->resume(gio_dev); + return error; +} + +static void gio_device_shutdown(struct device *dev) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + + if (dev->driver && drv->shutdown) + drv->shutdown(gio_dev); +} + +int gio_register_driver(struct gio_driver *drv) +{ + /* initialize common driver fields */ + if (!drv->driver.name) + drv->driver.name = drv->name; + if (!drv->driver.owner) + drv->driver.owner = drv->owner; + drv->driver.bus = &gio_bus; + + /* register with core */ + return driver_register(&drv->driver); +} +EXPORT_SYMBOL(gio_register_driver); + +void gio_unregister_driver(struct gio_driver *drv) +{ + driver_unregister(&drv->driver); +} +EXPORT_SYMBOL(gio_unregister_driver); + +void gio_set_master(struct gio_device *dev) +{ + u32 tmp = sgimc->giopar; + + switch (dev->slotno) { + case 0: + tmp |= SGIMC_GIOPAR_MASTERGFX; + break; + case 1: + tmp |= SGIMC_GIOPAR_MASTEREXP0; + break; + case 2: + tmp |= SGIMC_GIOPAR_MASTEREXP1; + break; + } + sgimc->giopar = tmp; +} +EXPORT_SYMBOL(gio_set_master); + +void ip22_gio_set_64bit(int slotno) +{ + u32 tmp = sgimc->giopar; + + switch (slotno) { + case 0: + tmp |= SGIMC_GIOPAR_GFX64; + break; + case 1: + tmp |= SGIMC_GIOPAR_EXP064; + break; + case 2: + tmp |= SGIMC_GIOPAR_EXP164; + break; + } + sgimc->giopar = tmp; +} + +static int ip22_gio_id(unsigned long addr, u32 *res) +{ + u8 tmp8; + u8 tmp16; + u32 tmp32; + u8 *ptr8; + u16 *ptr16; + u32 *ptr32; + + ptr32 = (void *)CKSEG1ADDR(addr); + if (!get_dbe(tmp32, ptr32)) { + /* + * We got no DBE, but this doesn't mean anything. + * If GIO is pipelined (which can't be disabled + * for GFX slot) we don't get a DBE, but we see + * the transfer size as data. So we do an 8bit + * and a 16bit access and check whether the common + * data matches + */ + ptr8 = (void *)CKSEG1ADDR(addr + 3); + get_dbe(tmp8, ptr8); + ptr16 = (void *)CKSEG1ADDR(addr + 2); + get_dbe(tmp16, ptr16); + if (tmp8 == (tmp16 & 0xff) && + tmp8 == (tmp32 & 0xff) && + tmp16 == (tmp32 & 0xffff)) { + *res = tmp32; + return 1; + } + } + return 0; /* nothing here */ +} + +#define HQ2_MYSTERY_OFFS 0x6A07C +#define NEWPORT_USTATUS_OFFS 0xF133C + +static int ip22_is_gr2(unsigned long addr) +{ + u32 tmp; + u32 *ptr; + + /* HQ2 only allows 32bit accesses */ + ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS); + if (!get_dbe(tmp, ptr)) { + if (tmp == 0xdeadbeef) + return 1; + } + return 0; +} + + +static void ip22_check_gio(int slotno, unsigned long addr) +{ + const char *name = "Unknown"; + struct gio_device *gio_dev; + u32 tmp; + __u8 id; + int i; + + /* first look for GR2/GR3 by checking mystery register */ + if (ip22_is_gr2(addr)) + tmp = 0x7f; + else { + if (!ip22_gio_id(addr, &tmp)) { + /* + * no GIO signature at start address of slot, but + * Newport doesn't have one, so let's check usea + * status register + */ + if (ip22_gio_id(addr + NEWPORT_USTATUS_OFFS, &tmp)) + tmp = 0x7e; + else + tmp = 0; + } + } + if (tmp) { + id = GIO_ID(tmp); + if (tmp & GIO_32BIT_ID) { + if (tmp & GIO_64BIT_IFACE) + ip22_gio_set_64bit(slotno); + } + for (i = 0; i < ARRAY_SIZE(gio_name_table); i++) { + if (id == gio_name_table[i].id) { + name = gio_name_table[i].name; + break; + } + } + printk(KERN_INFO "GIO: slot %d : %s (id %x)\n", + slotno, name, id); + gio_dev = kzalloc(sizeof *gio_dev, GFP_KERNEL); + gio_dev->name = name; + gio_dev->slotno = slotno; + gio_dev->id.id = id; + gio_dev->resource.start = addr; + gio_dev->resource.end = addr + 0x3fffff; + gio_dev->resource.flags = IORESOURCE_MEM; + dev_set_name(&gio_dev->dev, "gio%d", slotno); + gio_device_register(gio_dev); + } else + printk(KERN_INFO "GIO: slot %d : Empty\n", slotno); +} + +static struct bus_type gio_bus = { + .name = "gio", + .match = gio_bus_match, + .probe = gio_device_probe, + .remove = gio_device_remove, + .suspend = gio_device_suspend, + .resume = gio_device_resume, + .shutdown = gio_device_shutdown, +}; + +static struct resource gio_bus_resource = { + .start = GIO_SLOT_GFX_BASE, + .end = GIO_SLOT_GFX_BASE + 0x9fffff, + .name = "GIO Bus", + .flags = IORESOURCE_MEM, +}; + +int __init ip22_gio_init(void) +{ + int ret; + + ret = bus_register(&gio_bus); + if (!ret) { + request_resource(&iomem_resource, &gio_bus_resource); + printk(KERN_INFO "GIO: Probing bus...\n"); + if (ip22_is_fullhouse()) { + ip22_check_gio(0, GIO_SLOT_GFX_BASE); + ip22_check_gio(1, GIO_SLOT_EXP0_BASE); + } else { + ip22_check_gio(0, GIO_SLOT_GFX_BASE); + ip22_check_gio(1, GIO_SLOT_EXP0_BASE); + ip22_check_gio(2, GIO_SLOT_EXP1_BASE); + } + } + return ret; +} + +fs_initcall(ip22_gio_init); + diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c index d22262e..75ada8a 100644 --- a/arch/mips/sgi-ip22/ip22-mc.c +++ b/arch/mips/sgi-ip22/ip22-mc.c @@ -139,11 +139,11 @@ void __init sgimc_init(void) * zero. */ /* don't touch parity settings for IP28 */ -#ifndef CONFIG_SGI_IP28 tmp = sgimc->cpuctrl0; - tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | - SGIMC_CCTRL0_R4KNOCHKPARR); +#ifndef CONFIG_SGI_IP28 + tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM; #endif + tmp |= SGIMC_CCTRL0_R4KNOCHKPARR; sgimc->cpuctrl0 = tmp; /* Step 3: Setup the MC write buffer depth, this is controlled @@ -178,7 +178,8 @@ void __init sgimc_init(void) */ /* First the basic invariants across all GIO64 implementations. */ - tmp = SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ + tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */ + tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */ if (ip22_is_fullhouse()) { @@ -193,7 +194,6 @@ void __init sgimc_init(void) tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */ tmp |= SGIMC_GIOPAR_PLINEEXP1; tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */ - tmp |= SGIMC_GIOPAR_GFX64; /* GFX at 64 bits */ } } else { /* Guiness specific settings. */ diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 5e66213..c7bdfe4 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -26,9 +26,6 @@ #include #include -unsigned long sgi_gfxaddr; -EXPORT_SYMBOL_GPL(sgi_gfxaddr); - extern void ip22_be_init(void) __init; void __init plat_mem_setup(void) @@ -78,22 +75,4 @@ void __init plat_mem_setup(void) prom_flags |= PROM_FLAG_USE_AS_CONSOLE; add_preferred_console("arc", 0, NULL); } - -#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE) - { - ULONG *gfxinfo; - ULONG * (*__vec)(void) = (void *) (long) - *((_PULONG *)(long)((PROMBLOCK)->pvector + 0x20)); - - gfxinfo = __vec(); - sgi_gfxaddr = ((gfxinfo[1] >= 0xa0000000 - && gfxinfo[1] <= 0xc0000000) - ? gfxinfo[1] - 0xa0000000 : 0); - - /* newport addresses? */ - if (sgi_gfxaddr == 0x1f0f0000 || sgi_gfxaddr == 0x1f4f0000) { - conswitchp = &newport_con; - } - } -#endif } diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c index 93317b5..628b7ec 100644 --- a/drivers/video/console/newport_con.c +++ b/drivers/video/console/newport_con.c @@ -25,14 +25,13 @@ #include #include #include +#include + #include