From dczhu@mips.com Thu Sep 1 04:57:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Sep 2011 04:57:37 +0200 (CEST) Received: from dns1.mips.com ([12.201.5.69]:49984 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491197Ab1IAC53 (ORCPT ); Thu, 1 Sep 2011 04:57:29 +0200 Received: from exchdb01.mips.com (exchhub01.mips.com [192.168.36.84]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id p812mblQ000533; Wed, 31 Aug 2011 19:48:37 -0700 Received: from fun-lab.MIPSCN.CEC (192.168.225.107) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Wed, 31 Aug 2011 19:48:35 -0700 From: Deng-Cheng Zhu To: , , , , , , , , , , CC: , , , , , , Subject: [RESEND PATCH v3 0/2] Pass resources to pci_create_bus() and fix MIPS PCI resources Date: Thu, 1 Sep 2011 10:48:27 +0800 Message-ID: <1314845309-3277-1-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: eJnRtwcEeRdoqM5qEDla1Q== X-archive-position: 31025 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 133 Content-Length: 1398 Lines: 34 (Resending the patch set to include more arch maintainers.) Change the pci_create_bus() interface to pass in available resources to get them settled down early. This is to avoid possible resource conflicts while doing pci_scan_slot() in pci_scan_child_bus(). Note that pcibios_fixup_bus() can get rid of such conflicts, but it's done AFTER scanning slots. In addition, MIPS PCI resources are now fixed using this new interface. -- Changes -- v3 - v2: o Do not do fixups for root buses in pcibios_fixup_bus(). o Skip bus creation when bus resources cannot be allocated. o PCI domain/bus numbers added to the error info in controller_resources(). v2 - v1: o Merge [PATCH 1/3] to [PATCH 3/3], so now 2 patches in total. o Add more info to patch description. o Fix arch breaks in default resource setup discovered by Bjorn Helgaas. Deng-Cheng Zhu (2): PCI: Pass available resources into pci_create_bus() MIPS: PCI: Pass controller's resources to pci_create_bus() in pcibios_scanbus() arch/microblaze/pci/pci-common.c | 3 +- arch/mips/pci/pci.c | 61 +++++++++++++++++++++++++++++++++----- arch/powerpc/kernel/pci-common.c | 3 +- arch/sparc/kernel/pci.c | 3 +- arch/x86/pci/acpi.c | 2 +- drivers/pci/probe.c | 15 +++++++-- include/linux/pci.h | 3 +- 7 files changed, 73 insertions(+), 17 deletions(-) From dczhu@mips.com Thu Sep 1 04:57:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Sep 2011 04:58:00 +0200 (CEST) Received: from dns1.mips.com ([12.201.5.69]:49985 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491201Ab1IAC5c (ORCPT ); Thu, 1 Sep 2011 04:57:32 +0200 Received: from exchdb01.mips.com (exchhub01.mips.com [192.168.36.84]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id p812mqFv000538; Wed, 31 Aug 2011 19:48:53 -0700 Received: from fun-lab.MIPSCN.CEC (192.168.225.107) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Wed, 31 Aug 2011 19:48:47 -0700 From: Deng-Cheng Zhu To: , , , , , , , , , , CC: , , , , , , Subject: [RESEND PATCH v3 1/2] PCI: Pass available resources into pci_create_bus() Date: Thu, 1 Sep 2011 10:48:28 +0800 Message-ID: <1314845309-3277-2-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1314845309-3277-1-git-send-email-dczhu@mips.com> References: <1314845309-3277-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: 2gIJ6+cDy8UI0H/cL/LiXg== X-archive-position: 31026 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 138 Content-Length: 5591 Lines: 144 Currently, after pci_create_bus(), resources available on the bus could be handled by pci_scan_child_bus(). The problem is that, in pci_scan_child_bus(), before calling arch-dependent pcibios_fixup_bus(), PCI quirks will probably conflict (while doing pci_claim_resource()) with resources like system controller's I/O resource that have not yet been added to the bus. One can see that, by default, ioport_resource and iomem_resource are filled into the bus->resource[] array as the initial resources in pci_create_bus(). So, to avoid such conflicts, add those really available resources right before returning the newly created bus in pci_create_bus() whose interface should then be extended to receive them. A related discussion thread can be found here: http://www.spinics.net/lists/mips/msg41654.html Reviewed-by: Bjorn Helgaas Signed-off-by: Deng-Cheng Zhu --- Changes (v3 - v2): None Changes (v2 - v1): o Add more info to the patch description. o Fix arch breaks in default resource setup discovered by Bjorn Helgaas. arch/microblaze/pci/pci-common.c | 3 ++- arch/powerpc/kernel/pci-common.c | 3 ++- arch/sparc/kernel/pci.c | 3 ++- arch/x86/pci/acpi.c | 2 +- drivers/pci/probe.c | 15 +++++++++++---- include/linux/pci.h | 3 ++- 6 files changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index 4cfae20..9c35aa6 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -1581,7 +1581,8 @@ static void __devinit pcibios_scan_phb(struct pci_controller *hose) node ? node->full_name : ""); /* Create an empty bus for the toplevel */ - bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose); + bus = pci_create_bus(hose->parent, hose->first_busno, + hose->ops, hose, NULL); if (bus == NULL) { printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", hose->global_number); diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 32656f1..2ede26a 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -1703,7 +1703,8 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose) node ? node->full_name : ""); /* Create an empty bus for the toplevel */ - bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose); + bus = pci_create_bus(hose->parent, hose->first_busno, + hose->ops, hose, NULL); if (bus == NULL) { pr_err("Failed to create bus for PCI domain %04x\n", hose->global_number); diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index 1e94f94..77c38bb 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c @@ -689,7 +689,8 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, printk("PCI: Scanning PBM %s\n", node->full_name); - bus = pci_create_bus(parent, pbm->pci_first_busno, pbm->pci_ops, pbm); + bus = pci_create_bus(parent, pbm->pci_first_busno, + pbm->pci_ops, pbm, NULL); if (!bus) { printk(KERN_ERR "Failed to create bus for %s\n", node->full_name); diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index c953302..bab2113 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -353,7 +353,7 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) memcpy(bus->sysdata, sd, sizeof(*sd)); kfree(sd); } else { - bus = pci_create_bus(NULL, busnum, &pci_root_ops, sd); + bus = pci_create_bus(NULL, busnum, &pci_root_ops, sd, NULL); if (bus) { get_current_resources(device, busnum, domain, bus); bus->subordinate = pci_scan_child_bus(bus); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 8473727..47a364c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1516,7 +1516,8 @@ unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) } struct pci_bus * pci_create_bus(struct device *parent, - int bus, struct pci_ops *ops, void *sysdata) + int bus, struct pci_ops *ops, void *sysdata, + struct pci_bus_resource *bus_res) { int error; struct pci_bus *b, *b2; @@ -1570,8 +1571,14 @@ struct pci_bus * pci_create_bus(struct device *parent, pci_create_legacy_files(b); b->number = b->secondary = bus; - b->resource[0] = &ioport_resource; - b->resource[1] = &iomem_resource; + + /* Add initial resources to the bus */ + if (bus_res != NULL) + list_add_tail(&b->resources, &bus_res->list); + else { + b->resource[0] = &ioport_resource; + b->resource[1] = &iomem_resource; + } return b; @@ -1592,7 +1599,7 @@ struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, { struct pci_bus *b; - b = pci_create_bus(parent, bus, ops, sysdata); + b = pci_create_bus(parent, bus, ops, sysdata, NULL); if (b) b->subordinate = pci_scan_child_bus(b); return b; diff --git a/include/linux/pci.h b/include/linux/pci.h index 8c230cb..5e1bacd 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -666,7 +666,8 @@ static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *o return root_bus; } struct pci_bus *pci_create_bus(struct device *parent, int bus, - struct pci_ops *ops, void *sysdata); + struct pci_ops *ops, void *sysdata, + struct pci_bus_resource *bus_res); struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr); void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); -- 1.7.1 From dczhu@mips.com Thu Sep 1 04:58:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Sep 2011 04:58:23 +0200 (CEST) Received: from dns1.mips.com ([12.201.5.69]:48744 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491890Ab1IAC6D (ORCPT ); Thu, 1 Sep 2011 04:58:03 +0200 Received: from exchdb01.mips.com (exchhub01.mips.com [192.168.36.84]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id p812n24m000541; Wed, 31 Aug 2011 19:49:03 -0700 Received: from fun-lab.MIPSCN.CEC (192.168.225.107) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Wed, 31 Aug 2011 19:48:56 -0700 From: Deng-Cheng Zhu To: , , , , , , , , , , CC: , , , , , , Subject: [RESEND PATCH v3 2/2] MIPS: PCI: Pass controller's resources to pci_create_bus() in pcibios_scanbus() Date: Thu, 1 Sep 2011 10:48:29 +0800 Message-ID: <1314845309-3277-3-git-send-email-dczhu@mips.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1314845309-3277-1-git-send-email-dczhu@mips.com> References: <1314845309-3277-1-git-send-email-dczhu@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: 5zCUfjbrjzhoRWDYSfwuqQ== X-archive-position: 31027 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dczhu@mips.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 141 Content-Length: 3525 Lines: 117 Use the new interface of pci_create_bus() so that system controller's resources are added to the root bus upon bus creation, thereby avoiding conflicts with PCI quirks before pcibios_fixup_bus() gets the chance to do right things in pci_scan_child_bus(). Reviewed-by: Bjorn Helgaas Signed-off-by: Deng-Cheng Zhu --- Changes (v3 - v2): o Do not do fixups for root buses in pcibios_fixup_bus(). o Skip bus creation when bus resources cannot be allocated. o PCI domain/bus numbers added to the error info in controller_resources(). o Patch description modified according to the changes above. Changes (v2 - v1): o Merge [PATCH 1/3] to [PATCH 3/3] of v1. o Add more info to patch description. arch/mips/pci/pci.c | 61 ++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 53 insertions(+), 8 deletions(-) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 33bba7b..c76fb30 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -76,11 +76,42 @@ pcibios_align_resource(void *data, const struct resource *res, return start; } +static struct pci_bus_resource * +controller_resources(const struct pci_controller *ctrl, int domain, int busno) +{ + struct pci_bus_resource *mem_res, *io_res; + + mem_res = kzalloc(sizeof(struct pci_bus_resource), GFP_KERNEL); + if (!mem_res) + goto err_out; + + mem_res->res = ctrl->mem_resource; + mem_res->flags = 0; + INIT_LIST_HEAD(&mem_res->list); + + io_res = kzalloc(sizeof(struct pci_bus_resource), GFP_KERNEL); + if (!io_res) { + kfree(mem_res); + goto err_out; + } + + io_res->res = ctrl->io_resource; + io_res->flags = 0; + list_add(&io_res->list, &mem_res->list); + + return mem_res; +err_out: + printk(KERN_ERR "PCI bus %04x:%02x: Can't allocate bus resource.\n", + domain, busno); + return NULL; +} + static void __devinit pcibios_scanbus(struct pci_controller *hose) { static int next_busno; static int need_domain_info; - struct pci_bus *bus; + struct pci_bus *bus = NULL; + struct pci_bus_resource *bus_res; if (!hose->iommu) PCI_DMA_BUS_IS_PHYS = 1; @@ -88,7 +119,22 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) if (hose->get_busno && pci_probe_only) next_busno = (*hose->get_busno)(); - bus = pci_scan_bus(next_busno, hose->pci_ops, hose); + bus_res = controller_resources(hose, hose->index, next_busno); + if (bus_res) { + bus = pci_create_bus(NULL, next_busno, hose->pci_ops, + hose, bus_res); + if (bus) { + bus->subordinate = pci_scan_child_bus(bus); + pci_bus_add_devices(bus); + } else { + /* io_resource */ + kfree(list_first_entry(&bus_res->list, + struct pci_bus_resource, list)); + /* mem_resource */ + kfree(bus_res); + } + } + hose->bus = bus; need_domain_info = need_domain_info || hose->index; @@ -265,15 +311,14 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) { /* Propagate hose info into the subordinate devices. */ - struct pci_controller *hose = bus->sysdata; struct list_head *ln; struct pci_dev *dev = bus->self; - if (!dev) { - bus->resource[0] = hose->io_resource; - bus->resource[1] = hose->mem_resource; - } else if (pci_probe_only && - (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { + /* + * Root bus resources should already be set up correctly in + * pci_create_bus(), so don't do fixups for it. + */ + if (pci_probe_only && (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { pci_read_bridge_bases(bus); pcibios_fixup_device_resources(dev, bus); } -- 1.7.1 From saurabh140585@gmail.com Fri Sep 2 09:59:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Sep 2011 09:59:24 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:58683 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490992Ab1IBH7U (ORCPT ); Fri, 2 Sep 2011 09:59:20 +0200 Received: by fxd20 with SMTP id 20so1798038fxd.36 for ; Fri, 02 Sep 2011 00:59:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; bh=mHqstqRTAWTzu2fjAbDGWwiw6Sw8P1gx3cnBNZF0tbg=; b=Q12WRuL1ohCS/mK+ejUIJphhZab4e/gdJx219eAcW4ZzXGsEa/gCqHksZUwSXMEKDC rV0GkfuMfY8/P9j1sYQ/oCSxg7XKXISB6l43hpwl4c7D6/GA4XWGxY5C+ktzYAhygJd5 qIMX46CokCWT/xsWpABA6B2rfZNLHo5hxCwg0= MIME-Version: 1.0 Received: by 10.223.87.204 with SMTP id x12mr1303121fal.27.1314950354931; Fri, 02 Sep 2011 00:59:14 -0700 (PDT) Received: by 10.223.83.203 with HTTP; Fri, 2 Sep 2011 00:59:14 -0700 (PDT) Date: Fri, 2 Sep 2011 13:29:14 +0530 Message-ID: Subject: MIPS:Octeon: mailbox_interrupt is not registered as per cpu From: SAURABH MALPANI To: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=001517447e8ecd907804abf0bc78 X-archive-position: 31028 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: saurabh140585@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1103 Content-Length: 2355 Lines: 51 --001517447e8ecd907804abf0bc78 Content-Type: text/plain; charset=UTF-8 mailbox_interrupt is not registered with IRQF_PERCPU but it is supposed to be percpu interrupt. Is that on purpose or a miss? I am porting some code from x86 to octeon which requires special handling for per cpu interrupts. void octeon_prepare_cpus(unsigned int max_cpus) { cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, "mailbox0", mailbox_interrupt)) { panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); } if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED, "mailbox1", mailbox_interrupt)) { panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); } } -- Saurabh --001517447e8ecd907804abf0bc78 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable mailbox_interrupt is not registered with IRQF_PERCPU but it is supposed to = be percpu interrupt. Is that on purpose or a miss? I am porting some code f= rom x86 to octeon which requires special handling for per cpu interrupts.= =C2=A0

void octeon_prepare_cpus(unsigned int max_cpus)
{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 cvmx_write_csr(CVMX_CIU_MBOX_CLR= X(cvmx_get_core_num()), 0xffffffff);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 = if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 "mailbox0", mailbox_interrupt)) {
=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 panic("Cannot request= _irq(OCTEON_IRQ_MBOX0)\n");
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (request_irq(OCTEON_IRQ_MBOX1, mailb= ox_interrupt, IRQF_DISABLED,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 "mailbox1", mailbox_interrupt)) {
=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 panic("Cannot request= _irq(OCTEON_IRQ_MBOX1)\n");
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
}


--
Saurabh
--001517447e8ecd907804abf0bc78-- From jpirko@redhat.com Fri Sep 2 12:31:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Sep 2011 12:31:35 +0200 (CEST) Received: from mx1.redhat.com ([209.132.183.28]:53894 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491019Ab1IBKbZ (ORCPT ); Fri, 2 Sep 2011 12:31:25 +0200 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p82AUdaT018239 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 2 Sep 2011 06:30:40 -0400 Received: from localhost ([10.3.113.8]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p82AUYqL006208; Fri, 2 Sep 2011 06:30:35 -0400 From: Jiri Pirko To: netdev@vger.kernel.org Cc: ralf@linux-mips.org, fubar@us.ibm.com, andy@greyhouse.net, kaber@trash.net, bprakash@broadcom.com, JBottomley@parallels.com, robert.w.love@intel.com, davem@davemloft.net, shemminger@linux-foundation.org, decot@google.com, bhutchings@solarflare.com, mirq-linux@rere.qmqm.pl, alexander.h.duyck@intel.com, amit.salecha@qlogic.com, eric.dumazet@gmail.com, therbert@google.com, paulmck@linux.vnet.ibm.com, laijs@cn.fujitsu.com, xiaosuo@gmail.com, greearb@candelatech.com, loke.chetan@gmail.com, linux-mips@linux-mips.org, linux-scsi@vger.kernel.org, devel@open-fcoe.org, bridge@lists.linux-foundation.org Subject: [patch net-next-2.6] net: consolidate and fix ethtool_ops->get_settings calling Date: Thu, 1 Sep 2011 21:28:24 +0200 Message-Id: <1314905304-16485-1-git-send-email-jpirko@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-archive-position: 31029 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jpirko@redhat.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 742 Content-Length: 11093 Lines: 338 This patch does several things: - introduces __ethtool_get_settings which is called from ethtool code and from dev_ethtool_get_settings() as well. - dev_ethtool_get_settings() becomes rtnl wrapper for __ethtool_get_settings() - changes calling in drivers so rtnl locking is respected. In iboe_get_rate was previously ->get_settings() called unlocked. This fixes it - introduces rtnl_lock in bnx2fc_vport_create() and fcoe_vport_create() so bnx2fc_if_create() and fcoe_if_create() are called locked as they are from other places. - prb_calc_retire_blk_tmo() in af_packet.c was not calling get_settings with rtnl_lock. So use dev_ethtool_get_settings here. - use __ethtool_get_settings() in bonding code Signed-off-by: Jiri Pirko --- arch/mips/txx9/generic/setup_tx4939.c | 2 +- drivers/net/bonding/bond_main.c | 13 ++++------ drivers/net/macvlan.c | 3 +- drivers/scsi/bnx2fc/bnx2fc_fcoe.c | 4 ++- drivers/scsi/fcoe/fcoe.c | 4 ++- include/linux/ethtool.h | 3 ++ net/8021q/vlan_dev.c | 3 +- net/bridge/br_if.c | 2 +- net/core/dev.c | 17 +++++--------- net/core/ethtool.c | 17 +++++++++---- net/core/net-sysfs.c | 4 +- net/packet/af_packet.c | 41 +++++++++++++++----------------- 12 files changed, 59 insertions(+), 54 deletions(-) diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c index e9f95dc..ba3cec3 100644 --- a/arch/mips/txx9/generic/setup_tx4939.c +++ b/arch/mips/txx9/generic/setup_tx4939.c @@ -321,7 +321,7 @@ void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask) static u32 tx4939_get_eth_speed(struct net_device *dev) { struct ethtool_cmd cmd; - if (dev_ethtool_get_settings(dev, &cmd)) + if (__ethtool_get_settings(dev, &cmd)) return 100; /* default 100Mbps */ return ethtool_cmd_speed(&cmd); diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 8cb75a6..1dcb07c 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -557,7 +557,7 @@ down: static int bond_update_speed_duplex(struct slave *slave) { struct net_device *slave_dev = slave->dev; - struct ethtool_cmd etool = { .cmd = ETHTOOL_GSET }; + struct ethtool_cmd ecmd; u32 slave_speed; int res; @@ -565,18 +565,15 @@ static int bond_update_speed_duplex(struct slave *slave) slave->speed = SPEED_100; slave->duplex = DUPLEX_FULL; - if (!slave_dev->ethtool_ops || !slave_dev->ethtool_ops->get_settings) - return -1; - - res = slave_dev->ethtool_ops->get_settings(slave_dev, &etool); + res = __ethtool_get_settings(slave_dev, &ecmd); if (res < 0) return -1; - slave_speed = ethtool_cmd_speed(&etool); + slave_speed = ethtool_cmd_speed(&ecmd); if (slave_speed == 0 || slave_speed == ((__u32) -1)) return -1; - switch (etool.duplex) { + switch (ecmd.duplex) { case DUPLEX_FULL: case DUPLEX_HALF: break; @@ -585,7 +582,7 @@ static int bond_update_speed_duplex(struct slave *slave) } slave->speed = slave_speed; - slave->duplex = etool.duplex; + slave->duplex = ecmd.duplex; return 0; } diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c index 836e13f..b100c90 100644 --- a/drivers/net/macvlan.c +++ b/drivers/net/macvlan.c @@ -543,7 +543,8 @@ static int macvlan_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { const struct macvlan_dev *vlan = netdev_priv(dev); - return dev_ethtool_get_settings(vlan->lowerdev, cmd); + + return __ethtool_get_settings(vlan->lowerdev, cmd); } static const struct ethtool_ops macvlan_ethtool_ops = { diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c index 2c780a7..820a184 100644 --- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c +++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c @@ -673,7 +673,7 @@ static void bnx2fc_link_speed_update(struct fc_lport *lport) struct net_device *netdev = interface->netdev; struct ethtool_cmd ecmd; - if (!dev_ethtool_get_settings(netdev, &ecmd)) { + if (!__ethtool_get_settings(netdev, &ecmd)) { lport->link_supported_speeds &= ~(FC_PORTSPEED_1GBIT | FC_PORTSPEED_10GBIT); if (ecmd.supported & (SUPPORTED_1000baseT_Half | @@ -1001,9 +1001,11 @@ static int bnx2fc_vport_create(struct fc_vport *vport, bool disabled) "this interface\n"); return -EIO; } + rtnl_lock(); mutex_lock(&bnx2fc_dev_lock); vn_port = bnx2fc_if_create(interface, &vport->dev, 1); mutex_unlock(&bnx2fc_dev_lock); + rtnl_unlock(); if (IS_ERR(vn_port)) { printk(KERN_ERR PFX "bnx2fc_vport_create (%s) failed\n", diff --git a/drivers/scsi/fcoe/fcoe.c b/drivers/scsi/fcoe/fcoe.c index 3416ab6..83aa3ac 100644 --- a/drivers/scsi/fcoe/fcoe.c +++ b/drivers/scsi/fcoe/fcoe.c @@ -2043,7 +2043,7 @@ int fcoe_link_speed_update(struct fc_lport *lport) struct net_device *netdev = fcoe_netdev(lport); struct ethtool_cmd ecmd; - if (!dev_ethtool_get_settings(netdev, &ecmd)) { + if (!__ethtool_get_settings(netdev, &ecmd)) { lport->link_supported_speeds &= ~(FC_PORTSPEED_1GBIT | FC_PORTSPEED_10GBIT); if (ecmd.supported & (SUPPORTED_1000baseT_Half | @@ -2452,7 +2452,9 @@ static int fcoe_vport_create(struct fc_vport *vport, bool disabled) } mutex_lock(&fcoe_config_mutex); + rtnl_lock(); vn_port = fcoe_if_create(fcoe, &vport->dev, 1); + rtnl_unlock(); mutex_unlock(&fcoe_config_mutex); if (IS_ERR(vn_port)) { diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index 3829712..8571f18 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -728,6 +728,9 @@ enum ethtool_sfeatures_retval_bits { /* needed by dev_disable_lro() */ extern int __ethtool_set_flags(struct net_device *dev, u32 flags); +extern int __ethtool_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd); + /** * enum ethtool_phys_id_state - indicator state for physical identification * @ETHTOOL_ID_INACTIVE: Physical ID indicator should be deactivated diff --git a/net/8021q/vlan_dev.c b/net/8021q/vlan_dev.c index eba705b..c8cf939 100644 --- a/net/8021q/vlan_dev.c +++ b/net/8021q/vlan_dev.c @@ -610,7 +610,8 @@ static int vlan_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { const struct vlan_dev_info *vlan = vlan_dev_info(dev); - return dev_ethtool_get_settings(vlan->real_dev, cmd); + + return __ethtool_get_settings(vlan->real_dev, cmd); } static void vlan_ethtool_get_drvinfo(struct net_device *dev, diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c index b365bba..043a5eb 100644 --- a/net/bridge/br_if.c +++ b/net/bridge/br_if.c @@ -35,7 +35,7 @@ static int port_cost(struct net_device *dev) { struct ethtool_cmd ecmd; - if (!dev_ethtool_get_settings(dev, &ecmd)) { + if (!__ethtool_get_settings(dev, &ecmd)) { switch (ethtool_cmd_speed(&ecmd)) { case SPEED_10000: return 2; diff --git a/net/core/dev.c b/net/core/dev.c index 11b0fc7..abdc0e3 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -4570,22 +4570,17 @@ void dev_set_rx_mode(struct net_device *dev) * @dev: device * @cmd: memory area for ethtool_ops::get_settings() result * - * The cmd arg is initialized properly (cleared and - * ethtool_cmd::cmd field set to ETHTOOL_GSET). - * - * Return device's ethtool_ops::get_settings() result value or - * -EOPNOTSUPP when device doesn't expose - * ethtool_ops::get_settings() operation. + * This is wrapper taking rtnl lock for __ethtool_get_settings() */ int dev_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { - if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings) - return -EOPNOTSUPP; + int ret; - memset(cmd, 0, sizeof(struct ethtool_cmd)); - cmd->cmd = ETHTOOL_GSET; - return dev->ethtool_ops->get_settings(dev, cmd); + rtnl_lock(); + ret = __ethtool_get_settings(dev, cmd); + rtnl_unlock(); + return ret; } EXPORT_SYMBOL(dev_ethtool_get_settings); diff --git a/net/core/ethtool.c b/net/core/ethtool.c index 6cdba5f..94326d4 100644 --- a/net/core/ethtool.c +++ b/net/core/ethtool.c @@ -569,15 +569,22 @@ int __ethtool_set_flags(struct net_device *dev, u32 data) return 0; } +int __ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings) + return -EOPNOTSUPP; + + memset(cmd, 0, sizeof(struct ethtool_cmd)); + cmd->cmd = ETHTOOL_GSET; + return dev->ethtool_ops->get_settings(dev, cmd); +} + static int ethtool_get_settings(struct net_device *dev, void __user *useraddr) { - struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; int err; + struct ethtool_cmd cmd; - if (!dev->ethtool_ops->get_settings) - return -EOPNOTSUPP; - - err = dev->ethtool_ops->get_settings(dev, &cmd); + err = __ethtool_get_settings(dev, &cmd); if (err < 0) return err; diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c index 90fdb46..48e6279 100644 --- a/net/core/net-sysfs.c +++ b/net/core/net-sysfs.c @@ -172,7 +172,7 @@ static ssize_t show_speed(struct device *dev, if (netif_running(netdev)) { struct ethtool_cmd cmd; - if (!dev_ethtool_get_settings(netdev, &cmd)) + if (!__ethtool_get_settings(netdev, &cmd)) ret = sprintf(buf, fmt_udec, ethtool_cmd_speed(&cmd)); } rtnl_unlock(); @@ -190,7 +190,7 @@ static ssize_t show_duplex(struct device *dev, if (netif_running(netdev)) { struct ethtool_cmd cmd; - if (!dev_ethtool_get_settings(netdev, &cmd)) + if (!__ethtool_get_settings(netdev, &cmd)) ret = sprintf(buf, "%s\n", cmd.duplex ? "full" : "half"); } diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 2ea3d63..1bcc794 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -530,33 +530,30 @@ static int prb_calc_retire_blk_tmo(struct packet_sock *po, { struct net_device *dev; unsigned int mbits = 0, msec = 0, div = 0, tmo = 0; + struct ethtool_cmd ecmd; dev = dev_get_by_index(sock_net(&po->sk), po->ifindex); if (unlikely(dev == NULL)) return DEFAULT_PRB_RETIRE_TOV; - if (dev->ethtool_ops && dev->ethtool_ops->get_settings) { - struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET, }; - - if (!dev->ethtool_ops->get_settings(dev, &ecmd)) { - switch (ecmd.speed) { - case SPEED_10000: - msec = 1; - div = 10000/1000; - break; - case SPEED_1000: - msec = 1; - div = 1000/1000; - break; - /* - * If the link speed is so slow you don't really - * need to worry about perf anyways - */ - case SPEED_100: - case SPEED_10: - default: - return DEFAULT_PRB_RETIRE_TOV; - } + if (!dev_ethtool_get_settings(dev, &ecmd)) { + switch (ecmd.speed) { + case SPEED_10000: + msec = 1; + div = 10000/1000; + break; + case SPEED_1000: + msec = 1; + div = 1000/1000; + break; + /* + * If the link speed is so slow you don't really + * need to worry about perf anyways + */ + case SPEED_100: + case SPEED_10: + default: + return DEFAULT_PRB_RETIRE_TOV; } } -- 1.7.6 From jpirko@redhat.com Fri Sep 2 14:26:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Sep 2011 14:26:56 +0200 (CEST) Received: from mx1.redhat.com ([209.132.183.28]:49892 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491024Ab1IBM0r (ORCPT ); Fri, 2 Sep 2011 14:26:47 +0200 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p82CQY22022028 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 2 Sep 2011 08:26:34 -0400 Received: from localhost ([10.3.113.8]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p82CQVtf029152; Fri, 2 Sep 2011 08:26:32 -0400 Date: Fri, 2 Sep 2011 14:26:30 +0200 From: Jiri Pirko To: netdev@vger.kernel.org Cc: ralf@linux-mips.org, fubar@us.ibm.com, andy@greyhouse.net, kaber@trash.net, bprakash@broadcom.com, JBottomley@parallels.com, robert.w.love@intel.com, davem@davemloft.net, shemminger@linux-foundation.org, decot@google.com, bhutchings@solarflare.com, mirq-linux@rere.qmqm.pl, alexander.h.duyck@intel.com, amit.salecha@qlogic.com, eric.dumazet@gmail.com, therbert@google.com, paulmck@linux.vnet.ibm.com, laijs@cn.fujitsu.com, xiaosuo@gmail.com, greearb@candelatech.com, loke.chetan@gmail.com, linux-mips@linux-mips.org, linux-scsi@vger.kernel.org, devel@open-fcoe.org, bridge@lists.linux-foundation.org Subject: [patch net-next-2.6 v2] net: consolidate and fix ethtool_ops->get_settings calling Message-ID: <20110902122630.GC1991@minipsycho> References: <1314905304-16485-1-git-send-email-jpirko@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1314905304-16485-1-git-send-email-jpirko@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-archive-position: 31030 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jpirko@redhat.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1282 Content-Length: 11171 Lines: 342 This patch does several things: - introduces __ethtool_get_settings which is called from ethtool code and from dev_ethtool_get_settings() as well. - dev_ethtool_get_settings() becomes rtnl wrapper for __ethtool_get_settings() - changes calling in drivers so rtnl locking is respected. In iboe_get_rate was previously ->get_settings() called unlocked. This fixes it - introduces rtnl_lock in bnx2fc_vport_create() and fcoe_vport_create() so bnx2fc_if_create() and fcoe_if_create() are called locked as they are from other places. - prb_calc_retire_blk_tmo() in af_packet.c was not calling get_settings with rntl_lock. So use dev_ethtool_get_settings here. - use __ethtool_get_settings() in bonding code Signed-off-by: Jiri Pirko v1->v2: add missing export_symbol --- arch/mips/txx9/generic/setup_tx4939.c | 2 +- drivers/net/bonding/bond_main.c | 13 ++++------ drivers/net/macvlan.c | 3 +- drivers/scsi/bnx2fc/bnx2fc_fcoe.c | 4 ++- drivers/scsi/fcoe/fcoe.c | 4 ++- include/linux/ethtool.h | 3 ++ net/8021q/vlan_dev.c | 3 +- net/bridge/br_if.c | 2 +- net/core/dev.c | 17 +++++--------- net/core/ethtool.c | 18 ++++++++++---- net/core/net-sysfs.c | 4 +- net/packet/af_packet.c | 41 +++++++++++++++----------------- 12 files changed, 60 insertions(+), 54 deletions(-) diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c index e9f95dc..ba3cec3 100644 --- a/arch/mips/txx9/generic/setup_tx4939.c +++ b/arch/mips/txx9/generic/setup_tx4939.c @@ -321,7 +321,7 @@ void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask) static u32 tx4939_get_eth_speed(struct net_device *dev) { struct ethtool_cmd cmd; - if (dev_ethtool_get_settings(dev, &cmd)) + if (__ethtool_get_settings(dev, &cmd)) return 100; /* default 100Mbps */ return ethtool_cmd_speed(&cmd); diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 8cb75a6..1dcb07c 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -557,7 +557,7 @@ down: static int bond_update_speed_duplex(struct slave *slave) { struct net_device *slave_dev = slave->dev; - struct ethtool_cmd etool = { .cmd = ETHTOOL_GSET }; + struct ethtool_cmd ecmd; u32 slave_speed; int res; @@ -565,18 +565,15 @@ static int bond_update_speed_duplex(struct slave *slave) slave->speed = SPEED_100; slave->duplex = DUPLEX_FULL; - if (!slave_dev->ethtool_ops || !slave_dev->ethtool_ops->get_settings) - return -1; - - res = slave_dev->ethtool_ops->get_settings(slave_dev, &etool); + res = __ethtool_get_settings(slave_dev, &ecmd); if (res < 0) return -1; - slave_speed = ethtool_cmd_speed(&etool); + slave_speed = ethtool_cmd_speed(&ecmd); if (slave_speed == 0 || slave_speed == ((__u32) -1)) return -1; - switch (etool.duplex) { + switch (ecmd.duplex) { case DUPLEX_FULL: case DUPLEX_HALF: break; @@ -585,7 +582,7 @@ static int bond_update_speed_duplex(struct slave *slave) } slave->speed = slave_speed; - slave->duplex = etool.duplex; + slave->duplex = ecmd.duplex; return 0; } diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c index 836e13f..b100c90 100644 --- a/drivers/net/macvlan.c +++ b/drivers/net/macvlan.c @@ -543,7 +543,8 @@ static int macvlan_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { const struct macvlan_dev *vlan = netdev_priv(dev); - return dev_ethtool_get_settings(vlan->lowerdev, cmd); + + return __ethtool_get_settings(vlan->lowerdev, cmd); } static const struct ethtool_ops macvlan_ethtool_ops = { diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c index 2c780a7..820a184 100644 --- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c +++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c @@ -673,7 +673,7 @@ static void bnx2fc_link_speed_update(struct fc_lport *lport) struct net_device *netdev = interface->netdev; struct ethtool_cmd ecmd; - if (!dev_ethtool_get_settings(netdev, &ecmd)) { + if (!__ethtool_get_settings(netdev, &ecmd)) { lport->link_supported_speeds &= ~(FC_PORTSPEED_1GBIT | FC_PORTSPEED_10GBIT); if (ecmd.supported & (SUPPORTED_1000baseT_Half | @@ -1001,9 +1001,11 @@ static int bnx2fc_vport_create(struct fc_vport *vport, bool disabled) "this interface\n"); return -EIO; } + rtnl_lock(); mutex_lock(&bnx2fc_dev_lock); vn_port = bnx2fc_if_create(interface, &vport->dev, 1); mutex_unlock(&bnx2fc_dev_lock); + rtnl_unlock(); if (IS_ERR(vn_port)) { printk(KERN_ERR PFX "bnx2fc_vport_create (%s) failed\n", diff --git a/drivers/scsi/fcoe/fcoe.c b/drivers/scsi/fcoe/fcoe.c index 3416ab6..83aa3ac 100644 --- a/drivers/scsi/fcoe/fcoe.c +++ b/drivers/scsi/fcoe/fcoe.c @@ -2043,7 +2043,7 @@ int fcoe_link_speed_update(struct fc_lport *lport) struct net_device *netdev = fcoe_netdev(lport); struct ethtool_cmd ecmd; - if (!dev_ethtool_get_settings(netdev, &ecmd)) { + if (!__ethtool_get_settings(netdev, &ecmd)) { lport->link_supported_speeds &= ~(FC_PORTSPEED_1GBIT | FC_PORTSPEED_10GBIT); if (ecmd.supported & (SUPPORTED_1000baseT_Half | @@ -2452,7 +2452,9 @@ static int fcoe_vport_create(struct fc_vport *vport, bool disabled) } mutex_lock(&fcoe_config_mutex); + rtnl_lock(); vn_port = fcoe_if_create(fcoe, &vport->dev, 1); + rtnl_unlock(); mutex_unlock(&fcoe_config_mutex); if (IS_ERR(vn_port)) { diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index 3829712..8571f18 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -728,6 +728,9 @@ enum ethtool_sfeatures_retval_bits { /* needed by dev_disable_lro() */ extern int __ethtool_set_flags(struct net_device *dev, u32 flags); +extern int __ethtool_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd); + /** * enum ethtool_phys_id_state - indicator state for physical identification * @ETHTOOL_ID_INACTIVE: Physical ID indicator should be deactivated diff --git a/net/8021q/vlan_dev.c b/net/8021q/vlan_dev.c index eba705b..c8cf939 100644 --- a/net/8021q/vlan_dev.c +++ b/net/8021q/vlan_dev.c @@ -610,7 +610,8 @@ static int vlan_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { const struct vlan_dev_info *vlan = vlan_dev_info(dev); - return dev_ethtool_get_settings(vlan->real_dev, cmd); + + return __ethtool_get_settings(vlan->real_dev, cmd); } static void vlan_ethtool_get_drvinfo(struct net_device *dev, diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c index b365bba..043a5eb 100644 --- a/net/bridge/br_if.c +++ b/net/bridge/br_if.c @@ -35,7 +35,7 @@ static int port_cost(struct net_device *dev) { struct ethtool_cmd ecmd; - if (!dev_ethtool_get_settings(dev, &ecmd)) { + if (!__ethtool_get_settings(dev, &ecmd)) { switch (ethtool_cmd_speed(&ecmd)) { case SPEED_10000: return 2; diff --git a/net/core/dev.c b/net/core/dev.c index 11b0fc7..abdc0e3 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -4570,22 +4570,17 @@ void dev_set_rx_mode(struct net_device *dev) * @dev: device * @cmd: memory area for ethtool_ops::get_settings() result * - * The cmd arg is initialized properly (cleared and - * ethtool_cmd::cmd field set to ETHTOOL_GSET). - * - * Return device's ethtool_ops::get_settings() result value or - * -EOPNOTSUPP when device doesn't expose - * ethtool_ops::get_settings() operation. + * This is wrapper taking rtnl lock for __ethtool_get_settings() */ int dev_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { - if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings) - return -EOPNOTSUPP; + int ret; - memset(cmd, 0, sizeof(struct ethtool_cmd)); - cmd->cmd = ETHTOOL_GSET; - return dev->ethtool_ops->get_settings(dev, cmd); + rtnl_lock(); + ret = __ethtool_get_settings(dev, cmd); + rtnl_unlock(); + return ret; } EXPORT_SYMBOL(dev_ethtool_get_settings); diff --git a/net/core/ethtool.c b/net/core/ethtool.c index 6cdba5f..307297c 100644 --- a/net/core/ethtool.c +++ b/net/core/ethtool.c @@ -569,15 +569,23 @@ int __ethtool_set_flags(struct net_device *dev, u32 data) return 0; } +int __ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings) + return -EOPNOTSUPP; + + memset(cmd, 0, sizeof(struct ethtool_cmd)); + cmd->cmd = ETHTOOL_GSET; + return dev->ethtool_ops->get_settings(dev, cmd); +} +EXPORT_SYMBOL(__ethtool_get_settings); + static int ethtool_get_settings(struct net_device *dev, void __user *useraddr) { - struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; int err; + struct ethtool_cmd cmd; - if (!dev->ethtool_ops->get_settings) - return -EOPNOTSUPP; - - err = dev->ethtool_ops->get_settings(dev, &cmd); + err = __ethtool_get_settings(dev, &cmd); if (err < 0) return err; diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c index 90fdb46..48e6279 100644 --- a/net/core/net-sysfs.c +++ b/net/core/net-sysfs.c @@ -172,7 +172,7 @@ static ssize_t show_speed(struct device *dev, if (netif_running(netdev)) { struct ethtool_cmd cmd; - if (!dev_ethtool_get_settings(netdev, &cmd)) + if (!__ethtool_get_settings(netdev, &cmd)) ret = sprintf(buf, fmt_udec, ethtool_cmd_speed(&cmd)); } rtnl_unlock(); @@ -190,7 +190,7 @@ static ssize_t show_duplex(struct device *dev, if (netif_running(netdev)) { struct ethtool_cmd cmd; - if (!dev_ethtool_get_settings(netdev, &cmd)) + if (!__ethtool_get_settings(netdev, &cmd)) ret = sprintf(buf, "%s\n", cmd.duplex ? "full" : "half"); } diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 2ea3d63..1bcc794 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -530,33 +530,30 @@ static int prb_calc_retire_blk_tmo(struct packet_sock *po, { struct net_device *dev; unsigned int mbits = 0, msec = 0, div = 0, tmo = 0; + struct ethtool_cmd ecmd; dev = dev_get_by_index(sock_net(&po->sk), po->ifindex); if (unlikely(dev == NULL)) return DEFAULT_PRB_RETIRE_TOV; - if (dev->ethtool_ops && dev->ethtool_ops->get_settings) { - struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET, }; - - if (!dev->ethtool_ops->get_settings(dev, &ecmd)) { - switch (ecmd.speed) { - case SPEED_10000: - msec = 1; - div = 10000/1000; - break; - case SPEED_1000: - msec = 1; - div = 1000/1000; - break; - /* - * If the link speed is so slow you don't really - * need to worry about perf anyways - */ - case SPEED_100: - case SPEED_10: - default: - return DEFAULT_PRB_RETIRE_TOV; - } + if (!dev_ethtool_get_settings(dev, &ecmd)) { + switch (ecmd.speed) { + case SPEED_10000: + msec = 1; + div = 10000/1000; + break; + case SPEED_1000: + msec = 1; + div = 1000/1000; + break; + /* + * If the link speed is so slow you don't really + * need to worry about perf anyways + */ + case SPEED_100: + case SPEED_10: + default: + return DEFAULT_PRB_RETIRE_TOV; } } -- 1.7.6 From khali@linux-fr.org Fri Sep 2 15:21:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Sep 2011 15:21:30 +0200 (CEST) Received: from zone0.gcu-squad.org ([212.85.147.21]:28324 "EHLO services.gcu-squad.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491047Ab1IBNVX (ORCPT ); Fri, 2 Sep 2011 15:21:23 +0200 Received: from jdelvare.pck.nerim.net ([62.212.121.182] helo=endymion.delvare) by services.gcu-squad.org (GCU Mailer Daemon) with esmtpsa id 1QzUqu-0002cd-8l (TLSv1:AES128-SHA:128) (envelope-from ) ; Fri, 02 Sep 2011 16:36:16 +0200 Date: Fri, 2 Sep 2011 15:21:04 +0200 From: Jean Delvare To: Matt Turner Cc: linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck , "Maciej W. Rozycki" Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20110902152104.1cc3e2c6@endymion.delvare> In-Reply-To: References: <1313710991-3596-1-git-send-email-mattst88@gmail.com> X-Mailer: Claws Mail 3.7.5 (GTK+ 2.20.1; x86_64-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 31031 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khali@linux-fr.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 443 Lines: 12 On Wed, 24 Aug 2011 11:36:48 -0400, Matt Turner wrote: > On Thu, Aug 18, 2011 at 7:43 PM, Matt Turner wrote: > > Signed-off-by: Matt Turner > > Signed-off-by: Maciej W. Rozycki > > Do you want to take this patch, or should Ralf through his tree? My tree is fine, unless Ralf has a specific reason to pick it. Just give me a couple hours to review the patch. -- Jean Delvare From macro@linux-mips.org Fri Sep 2 15:35:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Sep 2011 15:35:51 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:50424 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491053Ab1IBNfo (ORCPT ); Fri, 2 Sep 2011 15:35:44 +0200 Date: Fri, 2 Sep 2011 14:35:44 +0100 (BST) From: "Maciej W. Rozycki" To: Jean Delvare cc: Matt Turner , linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts In-Reply-To: <20110902152104.1cc3e2c6@endymion.delvare> Message-ID: References: <1313710991-3596-1-git-send-email-mattst88@gmail.com> <20110902152104.1cc3e2c6@endymion.delvare> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 31032 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 642 Lines: 18 On Fri, 2 Sep 2011, Jean Delvare wrote: > > > Signed-off-by: Matt Turner > > > Signed-off-by: Maciej W. Rozycki > > > > Do you want to take this patch, or should Ralf through his tree? > > My tree is fine, unless Ralf has a specific reason to pick it. Just > give me a couple hours to review the patch. As a side note I do really need to get back to this series and see if there's anything else that needs reviving. Hopefully within the next couple of weeks. Thanks, Matt, for taking care of this patch. I reckon I've got some other old SWARM stuff that needs digging up too. Maciej From bhutchings@solarflare.com Fri Sep 2 20:46:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Sep 2011 20:46:20 +0200 (CEST) Received: from exchange.solarflare.com ([216.237.3.220]:16994 "EHLO exchange.solarflare.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491088Ab1IBSqP (ORCPT ); Fri, 2 Sep 2011 20:46:15 +0200 Received: from [10.17.20.137] ([10.17.20.137]) by exchange.solarflare.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 2 Sep 2011 11:46:07 -0700 Subject: Re: [patch net-next-2.6 v2] net: consolidate and fix ethtool_ops->get_settings calling From: Ben Hutchings To: Jiri Pirko Cc: netdev@vger.kernel.org, ralf@linux-mips.org, fubar@us.ibm.com, andy@greyhouse.net, kaber@trash.net, bprakash@broadcom.com, JBottomley@parallels.com, robert.w.love@intel.com, davem@davemloft.net, shemminger@linux-foundation.org, decot@google.com, mirq-linux@rere.qmqm.pl, alexander.h.duyck@intel.com, amit.salecha@qlogic.com, eric.dumazet@gmail.com, therbert@google.com, paulmck@linux.vnet.ibm.com, laijs@cn.fujitsu.com, xiaosuo@gmail.com, greearb@candelatech.com, loke.chetan@gmail.com, linux-mips@linux-mips.org, linux-scsi@vger.kernel.org, devel@open-fcoe.org, bridge@lists.linux-foundation.org In-Reply-To: <20110902122630.GC1991@minipsycho> References: <1314905304-16485-1-git-send-email-jpirko@redhat.com> <20110902122630.GC1991@minipsycho> Content-Type: text/plain; charset="UTF-8" Organization: Solarflare Communications Date: Fri, 02 Sep 2011 19:46:01 +0100 Message-ID: <1314989161.3419.5.camel@bwh-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Sep 2011 18:46:07.0494 (UTC) FILETIME=[935D2260:01CC69A0] X-TM-AS-Product-Ver: SMEX-8.0.0.1181-6.500.1024-18360.005 X-TM-AS-Result: No--7.381000-0.000000-31 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-archive-position: 31033 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhutchings@solarflare.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1592 Content-Length: 780 Lines: 22 On Fri, 2011-09-02 at 14:26 +0200, Jiri Pirko wrote: > This patch does several things: > - introduces __ethtool_get_settings which is called from ethtool code and > from dev_ethtool_get_settings() as well. > - dev_ethtool_get_settings() becomes rtnl wrapper for > __ethtool_get_settings() [...] I don't like this locking change. Most other dev_*() functions require the caller to hold RTNL, and it will break any OOT module calling dev_ethtool_get_settings() without producing any warning at compile time. Why not put an ASSERT_RTNL() in it instead? The rest of this looks fine. Ben. -- Ben Hutchings, Staff Engineer, Solarflare Not speaking for my employer; that's the marketing department's job. They asked us to note that Solarflare product names are trademarked. From jpirko@redhat.com Fri Sep 2 22:43:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Sep 2011 22:43:34 +0200 (CEST) Received: from mx1.redhat.com ([209.132.183.28]:18215 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491090Ab1IBUn1 (ORCPT ); Fri, 2 Sep 2011 22:43:27 +0200 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p82Kgi9i026887 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 2 Sep 2011 16:42:45 -0400 Received: from localhost ([10.3.113.8]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p82KgfVd021649; Fri, 2 Sep 2011 16:42:42 -0400 Date: Fri, 2 Sep 2011 22:42:41 +0200 From: Jiri Pirko To: Ben Hutchings Cc: netdev@vger.kernel.org, ralf@linux-mips.org, fubar@us.ibm.com, andy@greyhouse.net, kaber@trash.net, bprakash@broadcom.com, JBottomley@parallels.com, robert.w.love@intel.com, davem@davemloft.net, shemminger@linux-foundation.org, decot@google.com, mirq-linux@rere.qmqm.pl, alexander.h.duyck@intel.com, amit.salecha@qlogic.com, eric.dumazet@gmail.com, therbert@google.com, paulmck@linux.vnet.ibm.com, laijs@cn.fujitsu.com, xiaosuo@gmail.com, greearb@candelatech.com, loke.chetan@gmail.com, linux-mips@linux-mips.org, linux-scsi@vger.kernel.org, devel@open-fcoe.org, bridge@lists.linux-foundation.org Subject: Re: [patch net-next-2.6 v2] net: consolidate and fix ethtool_ops->get_settings calling Message-ID: <20110902204239.GA14802@minipsycho> References: <1314905304-16485-1-git-send-email-jpirko@redhat.com> <20110902122630.GC1991@minipsycho> <1314989161.3419.5.camel@bwh-desktop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1314989161.3419.5.camel@bwh-desktop> User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-archive-position: 31034 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jpirko@redhat.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1678 Content-Length: 1098 Lines: 29 Fri, Sep 02, 2011 at 08:46:01PM CEST, bhutchings@solarflare.com wrote: >On Fri, 2011-09-02 at 14:26 +0200, Jiri Pirko wrote: >> This patch does several things: >> - introduces __ethtool_get_settings which is called from ethtool code and >> from dev_ethtool_get_settings() as well. >> - dev_ethtool_get_settings() becomes rtnl wrapper for >> __ethtool_get_settings() >[...] > >I don't like this locking change. Most other dev_*() functions require >the caller to hold RTNL, and it will break any OOT module calling >dev_ethtool_get_settings() without producing any warning at compile >time. Why not put an ASSERT_RTNL() in it instead? Hmm. Okay, then I would remove dev_ethtool_get_settings() from net/core/dev.c and only put __ethtool_get_settings() to net/core/ethtool.c. Makes more sense to me to have it there... ASSERT_RTNL woudl be good there as well. > >The rest of this looks fine. > >Ben. > >-- >Ben Hutchings, Staff Engineer, Solarflare >Not speaking for my employer; that's the marketing department's job. >They asked us to note that Solarflare product names are trademarked. > From khali@linux-fr.org Sat Sep 3 10:30:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Sep 2011 10:31:01 +0200 (CEST) Received: from zone0.gcu-squad.org ([212.85.147.21]:10951 "EHLO services.gcu-squad.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491103Ab1ICIa4 (ORCPT ); Sat, 3 Sep 2011 10:30:56 +0200 Received: from jdelvare.pck.nerim.net ([62.212.121.182] helo=endymion.delvare) by services.gcu-squad.org (GCU Mailer Daemon) with esmtpsa id 1QzmnN-0004T2-Rb (TLSv1:AES128-SHA:128) (envelope-from ) ; Sat, 03 Sep 2011 11:45:50 +0200 Date: Sat, 3 Sep 2011 10:30:36 +0200 From: Jean Delvare To: Matt Turner Cc: linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck , "Maciej W. Rozycki" Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20110903103036.161616a5@endymion.delvare> In-Reply-To: <1313710991-3596-1-git-send-email-mattst88@gmail.com> References: <1313710991-3596-1-git-send-email-mattst88@gmail.com> X-Mailer: Claws Mail 3.7.5 (GTK+ 2.20.1; x86_64-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 31035 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khali@linux-fr.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 15557 Lines: 496 Hi Matt, On Thu, 18 Aug 2011 19:43:11 -0400, Matt Turner wrote: > From: Maciej W. Rozycki > > This is a rewrite of large parts of the driver mainly so that it uses > SMBus interrupts to offload the CPU from busy-waiting on status inputs. > As a part of the overhaul of the init and exit calls, all accesses to the > hardware got converted to use accessory functions via an ioremap() cookie. This could have been split into incremental patches, to make review easier. > [mattst88] Added BCM1480 interrupts and rebased minimally. Ditto. checkpatch complains about this, please fix: WARNING: line over 80 characters #257: FILE: drivers/i2c/busses/i2c-sibyte.c:157: + if (adap->status > 0 && ((adap->status & (M_SMB_ERROR | M_SMB_ERROR_TYPE)) == M_SMB_ERROR)) { Very nice patch overall, I only have minor comments, see below inline. > > Signed-off-by: Matt Turner > Signed-off-by: Maciej W. Rozycki > --- > This is the second version of this patch that I've sent. This version > fixes the problem with the ENXIO return. > > drivers/i2c/busses/i2c-sibyte.c | 296 +++++++++++++++++++++++++++++--------- > 1 files changed, 226 insertions(+), 70 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-sibyte.c b/drivers/i2c/busses/i2c-sibyte.c > index 0fe505d..d2f1cf1 100644 > --- a/drivers/i2c/busses/i2c-sibyte.c > +++ b/drivers/i2c/busses/i2c-sibyte.c > @@ -2,6 +2,7 @@ > * Copyright (C) 2004 Steven J. Hill > * Copyright (C) 2001,2002,2003 Broadcom Corporation > * Copyright (C) 1995-2000 Simon G. Vogl > + * Copyright (C) 2008 Maciej W. Rozycki Wow, looks like this patch has been sleeping for quite some time... > * > * This program is free software; you can redistribute it and/or > * modify it under the terms of the GNU General Public License > @@ -18,104 +19,164 @@ > * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. > */ > > +#include > +#include > #include > #include > #include > #include > +#include > +#include > +#include > +#include > #include > +#include > #include > #include > +#include > > > struct i2c_algo_sibyte_data { > - void *data; /* private data */ > - int bus; /* which bus */ > - void *reg_base; /* CSR base */ > + wait_queue_head_t wait; /* IRQ queue */ > + void __iomem *csr; /* mapped CSR handle */ > + phys_t base; /* physical CSR base */ > + char *name; /* IRQ handler name */ Should be a const pointer. Also, if the name is only for the IRQ, then irq_name would be a better name. > + spinlock_t lock; /* atomiser */ A more useful comment would explain what exactly is being protected by the lock. > + int irq; /* IRQ line */ > + int status; /* IRQ status */ You could document than -1 means error. > }; > > -/* ----- global defines ----------------------------------------------- */ > -#define SMB_CSR(a,r) ((long)(a->reg_base + r)) > > +static irqreturn_t i2c_sibyte_interrupt(int irq, void *dev_id) > +{ > + struct i2c_adapter *i2c_adap = dev_id; > + struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; > + void __iomem *csr = adap->csr; > + u8 status; > + > + /* > + * Ugh, no way to detect the finish interrupt, > + * but if busy it is obviously not one. > + */ > + status = __raw_readq(csr + R_SMB_STATUS); > + if ((status & (M_SMB_ERROR | M_SMB_BUSY)) == M_SMB_BUSY) > + return IRQ_NONE; > + > + /* > + * Clear the error interrupt (write 1 to clear); > + * the finish interrupt was cleared by the read above. > + */ > + __raw_writeq(status, csr + R_SMB_STATUS); > + > + /* Post the status. */ > + spin_lock(&adap->lock); > + adap->status = status & (M_SMB_ERROR_TYPE | M_SMB_ERROR | M_SMB_BUSY); > + wake_up(&adap->wait); > + spin_unlock(&adap->lock); > + > + return IRQ_HANDLED; > +} > > -static int smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr, > - unsigned short flags, char read_write, > - u8 command, int size, union i2c_smbus_data * data) > +static s32 i2c_sibyte_smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr, > + unsigned short cflags, > + char read_write, u8 command, int size, > + union i2c_smbus_data *data) > { > struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; > + void __iomem *csr = adap->csr; > + unsigned long flags; > int data_bytes = 0; > int error; > > - while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) > - ; > + spin_lock_irqsave(&adap->lock, flags); > + > + if (adap->status < 0) { > + error = -EIO; > + goto out_unlock; > + } Well, this can only happen if the previous transaction ended up with a failure, right? This means that a single error will break the SMBus forever. Is there no way to reset the controller to a sane state if this happens? > > switch (size) { > case I2C_SMBUS_QUICK: > - csr_out32((V_SMB_ADDR(addr) | > - (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) | > - V_SMB_TT_QUICKCMD), SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_ADDR(addr) | > + (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) | > + V_SMB_TT_QUICKCMD, > + csr + R_SMB_START); > break; > case I2C_SMBUS_BYTE: > if (read_write == I2C_SMBUS_READ) { > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE, > + csr + R_SMB_START); > data_bytes = 1; > } else { > - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE, > + csr + R_SMB_START); > } > break; > case I2C_SMBUS_BYTE_DATA: > - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); > + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); > if (read_write == I2C_SMBUS_READ) { > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE, > + csr + R_SMB_START); > data_bytes = 1; > } else { > - csr_out32(V_SMB_LB(data->byte), > - SMB_CSR(adap, R_SMB_DATA)); > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_LB(data->byte), csr + R_SMB_DATA); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE, > + csr + R_SMB_START); > } > break; > case I2C_SMBUS_WORD_DATA: > - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); > + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); > if (read_write == I2C_SMBUS_READ) { > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE, > + csr + R_SMB_START); > data_bytes = 2; > } else { > - csr_out32(V_SMB_LB(data->word & 0xff), > - SMB_CSR(adap, R_SMB_DATA)); > - csr_out32(V_SMB_MB(data->word >> 8), > - SMB_CSR(adap, R_SMB_DATA)); > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_LB(data->word & 0xff), > + csr + R_SMB_DATA); > + __raw_writeq(V_SMB_MB(data->word >> 8), > + csr + R_SMB_DATA); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE, > + csr + R_SMB_START); > } > break; > default: > - return -EOPNOTSUPP; > + error = -EOPNOTSUPP; > + goto out_unlock; > } > + mmiowb(); > + __raw_readq(csr + R_SMB_START); > + adap->status = -1; > + > + spin_unlock_irqrestore(&adap->lock, flags); > > - while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) > - ; > + wait_event_timeout(adap->wait, (adap->status >= 0), HZ); 1 second is a rather long timeout. The driver only supports small transactions, so even if a slave slows down the clock, I can hardly imagine a transaction lasting more that, say, 10 ms. So I think you can safely lower the timeout to HZ / 5 or even HZ / 10. Also, shouldn't you check the return value? This would let you return the right error code (-ETIMEDOUT according to Documentation/i2c/fault-codes) and you would no longer have to check for adap->status sign in the rest of the function. > > - error = csr_in32(SMB_CSR(adap, R_SMB_STATUS)); > - if (error & M_SMB_ERROR) { > - /* Clear error bit by writing a 1 */ > - csr_out32(M_SMB_ERROR, SMB_CSR(adap, R_SMB_STATUS)); > - return (error & M_SMB_ERROR_TYPE) ? -EIO : -ENXIO; > + spin_lock_irqsave(&adap->lock, flags); > + > + if (adap->status > 0 && ((adap->status & (M_SMB_ERROR | M_SMB_ERROR_TYPE)) == M_SMB_ERROR)) { > + error = -ENXIO; > + goto out_unlock; > + } > + if (adap->status < 0 || (adap->status & (M_SMB_ERROR | M_SMB_BUSY))) { > + error = -EIO; > + goto out_unlock; > } > > if (data_bytes == 1) > - data->byte = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xff; > + data->byte = __raw_readq(csr + R_SMB_DATA) & 0xff; > if (data_bytes == 2) > - data->word = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xffff; > + data->word = __raw_readq(csr + R_SMB_DATA) & 0xffff; > > - return 0; > + error = 0; > + > +out_unlock: > + spin_unlock_irqrestore(&adap->lock, flags); > + > + return error; > } > > -static u32 bit_func(struct i2c_adapter *adap) > +static u32 i2c_sibyte_bit_func(struct i2c_adapter *adap) If you're renaming this then please drop the "bit" part in it, it's most likely coming from a copy-and-paste from i2c-algo-bit and has no meaning in the sibyte driver. > { > return (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | > I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA); > @@ -125,8 +186,8 @@ static u32 bit_func(struct i2c_adapter *adap) > /* -----exported algorithm data: ------------------------------------- */ > > static const struct i2c_algorithm i2c_sibyte_algo = { > - .smbus_xfer = smbus_xfer, > - .functionality = bit_func, > + .smbus_xfer = i2c_sibyte_smbus_xfer, > + .functionality = i2c_sibyte_bit_func, > }; > > /* > @@ -135,37 +196,121 @@ static const struct i2c_algorithm i2c_sibyte_algo = { > static int __init i2c_sibyte_add_bus(struct i2c_adapter *i2c_adap, int speed) > { > struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; > + void __iomem *csr; > + int err; > > - /* Register new adapter to i2c module... */ > - i2c_adap->algo = &i2c_sibyte_algo; > + adap->status = 0; > + init_waitqueue_head(&adap->wait); > + spin_lock_init(&adap->lock); > + > + csr = ioremap(adap->base, R_SMB_PEC + SMB_REGISTER_SPACING); > + if (!csr) { > + err = -ENOMEM; > + goto out; > + } > + adap->csr = csr; > > /* Set the requested frequency. */ > - csr_out32(speed, SMB_CSR(adap,R_SMB_FREQ)); > - csr_out32(0, SMB_CSR(adap,R_SMB_CONTROL)); > + __raw_writeq(speed, csr + R_SMB_FREQ); > + > + /* Clear any pending error interrupt. */ > + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); > + /* Disable interrupts. */ > + __raw_writeq(0, csr + R_SMB_CONTROL); > + mmiowb(); > + __raw_readq(csr + R_SMB_CONTROL); Shouldn't it be the other way around, disable interrupts first and then clear any pending one? Looks racy otherwise, but maybe it makes no difference in practice. > + > + err = request_irq(adap->irq, i2c_sibyte_interrupt, IRQF_SHARED, > + adap->name, i2c_adap); > + if (err < 0) > + goto out_unmap; > + > + /* Enable finish and error interrupts. */ > + __raw_writeq(M_SMB_FINISH_INTR | M_SMB_ERR_INTR, csr + R_SMB_CONTROL); > + > + /* Register new adapter to i2c module... */ > + err = i2c_add_numbered_adapter(i2c_adap); > + if (err < 0) > + goto out_unirq; > + > + return 0; > > - return i2c_add_numbered_adapter(i2c_adap); > +out_unirq: > + /* Disable interrupts. */ > + __raw_writeq(0, csr + R_SMB_CONTROL); > + mmiowb(); > + __raw_readq(csr + R_SMB_CONTROL); > + > + free_irq(adap->irq, i2c_adap); > + > + /* Clear any pending error interrupt. */ > + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); You may consider moving this block to a separate function, as it is duplicated in the i2c_sibyte_remove_bus() function below. > +out_unmap: > + iounmap(csr); > +out: > + return err; > } > > +static void i2c_sibyte_remove_bus(struct i2c_adapter *i2c_adap) > +{ > + struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; > + void __iomem *csr = adap->csr; > + > + i2c_del_adapter(i2c_adap); > + > + /* Disable interrupts. */ > + __raw_writeq(0, csr + R_SMB_CONTROL); > + mmiowb(); > + __raw_readq(csr + R_SMB_CONTROL); > > -static struct i2c_algo_sibyte_data sibyte_board_data[2] = { > - { NULL, 0, (void *) (CKSEG1+A_SMB_BASE(0)) }, > - { NULL, 1, (void *) (CKSEG1+A_SMB_BASE(1)) } > + free_irq(adap->irq, i2c_adap); > + > + /* Clear any pending error interrupt. */ > + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); > + > + iounmap(csr); > +} > + > +static struct i2c_algo_sibyte_data i2c_sibyte_board_data[2] = { > +#ifdef CONFIG_SIBYTE_SB1250 > + { > + .name = "sb1250-smbus-0", > + .base = A_SMB_0, > + .irq = K_INT_SMB_0, > + }, > + { > + .name = "sb1250-smbus-1", > + .base = A_SMB_1, > + .irq = K_INT_SMB_1, > + } > +#else > + { > + .name = "bcm1480-smbus-0", > + .base = A_SMB_0, > + .irq = K_BCM1480_INT_SMB_0, > + }, > + { > + .name = "bcm1480-smbus-1", > + .base = A_SMB_1, > + .irq = K_BCM1480_INT_SMB_1, > + } > +#endif > }; > > -static struct i2c_adapter sibyte_board_adapter[2] = { > +static struct i2c_adapter i2c_sibyte_board_adapter[2] = { > { > .owner = THIS_MODULE, > .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, > - .algo = NULL, > - .algo_data = &sibyte_board_data[0], > + .algo = &i2c_sibyte_algo, > + .algo_data = &i2c_sibyte_board_data[0], > .nr = 0, > .name = "SiByte SMBus 0", > }, > { > .owner = THIS_MODULE, > .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, > - .algo = NULL, > - .algo_data = &sibyte_board_data[1], > + .algo = &i2c_sibyte_algo, > + .algo_data = &i2c_sibyte_board_data[1], > .nr = 1, > .name = "SiByte SMBus 1", > }, > @@ -173,21 +318,32 @@ static struct i2c_adapter sibyte_board_adapter[2] = { > > static int __init i2c_sibyte_init(void) > { > + int err; > + > pr_info("i2c-sibyte: i2c SMBus adapter module for SiByte board\n"); > - if (i2c_sibyte_add_bus(&sibyte_board_adapter[0], K_SMB_FREQ_100KHZ) < 0) > - return -ENODEV; > - if (i2c_sibyte_add_bus(&sibyte_board_adapter[1], > - K_SMB_FREQ_400KHZ) < 0) { > - i2c_del_adapter(&sibyte_board_adapter[0]); > - return -ENODEV; > - } > + > + err = i2c_sibyte_add_bus(&i2c_sibyte_board_adapter[0], > + K_SMB_FREQ_100KHZ); > + if (err < 0) > + goto out; > + > + err = i2c_sibyte_add_bus(&i2c_sibyte_board_adapter[1], > + K_SMB_FREQ_400KHZ); > + if (err < 0) > + goto out_remove; > + > return 0; > + > +out_remove: > + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[0]); > +out: > + return err; > } > > static void __exit i2c_sibyte_exit(void) > { > - i2c_del_adapter(&sibyte_board_adapter[0]); > - i2c_del_adapter(&sibyte_board_adapter[1]); > + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[1]); > + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[0]); > } > > module_init(i2c_sibyte_init); Please address my concerns where you agree and send an updated patch. -- Jean Delvare From jpirko@redhat.com Sat Sep 3 15:34:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Sep 2011 15:35:00 +0200 (CEST) Received: from mx1.redhat.com ([209.132.183.28]:2963 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491002Ab1ICNeu (ORCPT ); Sat, 3 Sep 2011 15:34:50 +0200 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p83DYZCD019866 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Sat, 3 Sep 2011 09:34:36 -0400 Received: from localhost ([10.3.113.8]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p83DYVmK000464; Sat, 3 Sep 2011 09:34:32 -0400 Date: Sat, 3 Sep 2011 15:34:30 +0200 From: Jiri Pirko To: Ben Hutchings Cc: netdev@vger.kernel.org, ralf@linux-mips.org, fubar@us.ibm.com, andy@greyhouse.net, kaber@trash.net, bprakash@broadcom.com, JBottomley@parallels.com, robert.w.love@intel.com, davem@davemloft.net, shemminger@linux-foundation.org, decot@google.com, mirq-linux@rere.qmqm.pl, alexander.h.duyck@intel.com, amit.salecha@qlogic.com, eric.dumazet@gmail.com, therbert@google.com, paulmck@linux.vnet.ibm.com, laijs@cn.fujitsu.com, xiaosuo@gmail.com, greearb@candelatech.com, loke.chetan@gmail.com, linux-mips@linux-mips.org, linux-scsi@vger.kernel.org, devel@open-fcoe.org, bridge@lists.linux-foundation.org Subject: [patch net-next-2.6 v3] net: consolidate and fix ethtool_ops->get_settings calling Message-ID: <20110903133428.GA2821@minipsycho> References: <1314905304-16485-1-git-send-email-jpirko@redhat.com> <20110902122630.GC1991@minipsycho> <1314989161.3419.5.camel@bwh-desktop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1314989161.3419.5.camel@bwh-desktop> User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-archive-position: 31036 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jpirko@redhat.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1886 Content-Length: 12762 Lines: 393 This patch does several things: - introduces __ethtool_get_settings which is called from ethtool code and from drivers as well. Put ASSERT_RTNL there. - dev_ethtool_get_settings() is replaced by __ethtool_get_settings() - changes calling in drivers so rtnl locking is respected. In iboe_get_rate was previously ->get_settings() called unlocked. This fixes it. Also prb_calc_retire_blk_tmo() in af_packet.c had the same problem. Also fixed by calling __dev_get_by_index() instead of dev_get_by_index() and holding rtnl_lock for both calls. - introduces rtnl_lock in bnx2fc_vport_create() and fcoe_vport_create() so bnx2fc_if_create() and fcoe_if_create() are called locked as they are from other places. - use __ethtool_get_settings() in bonding code Signed-off-by: Jiri Pirko v2->v3: -removed dev_ethtool_get_settings() -added ASSERT_RTNL into __ethtool_get_settings() -prb_calc_retire_blk_tmo - use __dev_get_by_index() and lock around it and __ethtool_get_settings() call v1->v2: add missing export_symbol --- arch/mips/txx9/generic/setup_tx4939.c | 2 +- drivers/net/bonding/bond_main.c | 13 +++----- drivers/net/macvlan.c | 3 +- drivers/scsi/bnx2fc/bnx2fc_fcoe.c | 4 ++- drivers/scsi/fcoe/fcoe.c | 4 ++- include/linux/ethtool.h | 3 ++ include/linux/netdevice.h | 3 -- include/rdma/ib_addr.h | 6 +++- net/8021q/vlan_dev.c | 3 +- net/bridge/br_if.c | 2 +- net/core/dev.c | 24 --------------- net/core/ethtool.c | 20 +++++++++--- net/core/net-sysfs.c | 4 +- net/packet/af_packet.c | 52 +++++++++++++++++---------------- 14 files changed, 69 insertions(+), 74 deletions(-) diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c index e9f95dc..ba3cec3 100644 --- a/arch/mips/txx9/generic/setup_tx4939.c +++ b/arch/mips/txx9/generic/setup_tx4939.c @@ -321,7 +321,7 @@ void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask) static u32 tx4939_get_eth_speed(struct net_device *dev) { struct ethtool_cmd cmd; - if (dev_ethtool_get_settings(dev, &cmd)) + if (__ethtool_get_settings(dev, &cmd)) return 100; /* default 100Mbps */ return ethtool_cmd_speed(&cmd); diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 8cb75a6..1dcb07c 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -557,7 +557,7 @@ down: static int bond_update_speed_duplex(struct slave *slave) { struct net_device *slave_dev = slave->dev; - struct ethtool_cmd etool = { .cmd = ETHTOOL_GSET }; + struct ethtool_cmd ecmd; u32 slave_speed; int res; @@ -565,18 +565,15 @@ static int bond_update_speed_duplex(struct slave *slave) slave->speed = SPEED_100; slave->duplex = DUPLEX_FULL; - if (!slave_dev->ethtool_ops || !slave_dev->ethtool_ops->get_settings) - return -1; - - res = slave_dev->ethtool_ops->get_settings(slave_dev, &etool); + res = __ethtool_get_settings(slave_dev, &ecmd); if (res < 0) return -1; - slave_speed = ethtool_cmd_speed(&etool); + slave_speed = ethtool_cmd_speed(&ecmd); if (slave_speed == 0 || slave_speed == ((__u32) -1)) return -1; - switch (etool.duplex) { + switch (ecmd.duplex) { case DUPLEX_FULL: case DUPLEX_HALF: break; @@ -585,7 +582,7 @@ static int bond_update_speed_duplex(struct slave *slave) } slave->speed = slave_speed; - slave->duplex = etool.duplex; + slave->duplex = ecmd.duplex; return 0; } diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c index 836e13f..b100c90 100644 --- a/drivers/net/macvlan.c +++ b/drivers/net/macvlan.c @@ -543,7 +543,8 @@ static int macvlan_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { const struct macvlan_dev *vlan = netdev_priv(dev); - return dev_ethtool_get_settings(vlan->lowerdev, cmd); + + return __ethtool_get_settings(vlan->lowerdev, cmd); } static const struct ethtool_ops macvlan_ethtool_ops = { diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c index 2c780a7..820a184 100644 --- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c +++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c @@ -673,7 +673,7 @@ static void bnx2fc_link_speed_update(struct fc_lport *lport) struct net_device *netdev = interface->netdev; struct ethtool_cmd ecmd; - if (!dev_ethtool_get_settings(netdev, &ecmd)) { + if (!__ethtool_get_settings(netdev, &ecmd)) { lport->link_supported_speeds &= ~(FC_PORTSPEED_1GBIT | FC_PORTSPEED_10GBIT); if (ecmd.supported & (SUPPORTED_1000baseT_Half | @@ -1001,9 +1001,11 @@ static int bnx2fc_vport_create(struct fc_vport *vport, bool disabled) "this interface\n"); return -EIO; } + rtnl_lock(); mutex_lock(&bnx2fc_dev_lock); vn_port = bnx2fc_if_create(interface, &vport->dev, 1); mutex_unlock(&bnx2fc_dev_lock); + rtnl_unlock(); if (IS_ERR(vn_port)) { printk(KERN_ERR PFX "bnx2fc_vport_create (%s) failed\n", diff --git a/drivers/scsi/fcoe/fcoe.c b/drivers/scsi/fcoe/fcoe.c index 3416ab6..83aa3ac 100644 --- a/drivers/scsi/fcoe/fcoe.c +++ b/drivers/scsi/fcoe/fcoe.c @@ -2043,7 +2043,7 @@ int fcoe_link_speed_update(struct fc_lport *lport) struct net_device *netdev = fcoe_netdev(lport); struct ethtool_cmd ecmd; - if (!dev_ethtool_get_settings(netdev, &ecmd)) { + if (!__ethtool_get_settings(netdev, &ecmd)) { lport->link_supported_speeds &= ~(FC_PORTSPEED_1GBIT | FC_PORTSPEED_10GBIT); if (ecmd.supported & (SUPPORTED_1000baseT_Half | @@ -2452,7 +2452,9 @@ static int fcoe_vport_create(struct fc_vport *vport, bool disabled) } mutex_lock(&fcoe_config_mutex); + rtnl_lock(); vn_port = fcoe_if_create(fcoe, &vport->dev, 1); + rtnl_unlock(); mutex_unlock(&fcoe_config_mutex); if (IS_ERR(vn_port)) { diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index 3829712..8571f18 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -728,6 +728,9 @@ enum ethtool_sfeatures_retval_bits { /* needed by dev_disable_lro() */ extern int __ethtool_set_flags(struct net_device *dev, u32 flags); +extern int __ethtool_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd); + /** * enum ethtool_phys_id_state - indicator state for physical identification * @ETHTOOL_ID_INACTIVE: Physical ID indicator should be deactivated diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index dad7e4d..8b1080b 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -2600,9 +2600,6 @@ static inline int netif_is_bond_slave(struct net_device *dev) extern struct pernet_operations __net_initdata loopback_net_ops; -int dev_ethtool_get_settings(struct net_device *dev, - struct ethtool_cmd *cmd); - static inline u32 dev_ethtool_get_rx_csum(struct net_device *dev) { if (dev->features & NETIF_F_RXCSUM) diff --git a/include/rdma/ib_addr.h b/include/rdma/ib_addr.h index ae8c68f..639a449 100644 --- a/include/rdma/ib_addr.h +++ b/include/rdma/ib_addr.h @@ -218,8 +218,12 @@ static inline int iboe_get_rate(struct net_device *dev) { struct ethtool_cmd cmd; u32 speed; + int err; - if (dev_ethtool_get_settings(dev, &cmd)) + rtnl_lock(); + err = __ethtool_get_settings(dev, &cmd); + rtnl_unlock(); + if (err) return IB_RATE_PORT_CURRENT; speed = ethtool_cmd_speed(&cmd); diff --git a/net/8021q/vlan_dev.c b/net/8021q/vlan_dev.c index eba705b..c8cf939 100644 --- a/net/8021q/vlan_dev.c +++ b/net/8021q/vlan_dev.c @@ -610,7 +610,8 @@ static int vlan_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { const struct vlan_dev_info *vlan = vlan_dev_info(dev); - return dev_ethtool_get_settings(vlan->real_dev, cmd); + + return __ethtool_get_settings(vlan->real_dev, cmd); } static void vlan_ethtool_get_drvinfo(struct net_device *dev, diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c index b365bba..043a5eb 100644 --- a/net/bridge/br_if.c +++ b/net/bridge/br_if.c @@ -35,7 +35,7 @@ static int port_cost(struct net_device *dev) { struct ethtool_cmd ecmd; - if (!dev_ethtool_get_settings(dev, &ecmd)) { + if (!__ethtool_get_settings(dev, &ecmd)) { switch (ethtool_cmd_speed(&ecmd)) { case SPEED_10000: return 2; diff --git a/net/core/dev.c b/net/core/dev.c index 11b0fc7..94f3254 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -4566,30 +4566,6 @@ void dev_set_rx_mode(struct net_device *dev) } /** - * dev_ethtool_get_settings - call device's ethtool_ops::get_settings() - * @dev: device - * @cmd: memory area for ethtool_ops::get_settings() result - * - * The cmd arg is initialized properly (cleared and - * ethtool_cmd::cmd field set to ETHTOOL_GSET). - * - * Return device's ethtool_ops::get_settings() result value or - * -EOPNOTSUPP when device doesn't expose - * ethtool_ops::get_settings() operation. - */ -int dev_ethtool_get_settings(struct net_device *dev, - struct ethtool_cmd *cmd) -{ - if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings) - return -EOPNOTSUPP; - - memset(cmd, 0, sizeof(struct ethtool_cmd)); - cmd->cmd = ETHTOOL_GSET; - return dev->ethtool_ops->get_settings(dev, cmd); -} -EXPORT_SYMBOL(dev_ethtool_get_settings); - -/** * dev_get_flags - get flags reported to userspace * @dev: device * diff --git a/net/core/ethtool.c b/net/core/ethtool.c index 6cdba5f..f444817 100644 --- a/net/core/ethtool.c +++ b/net/core/ethtool.c @@ -569,15 +569,25 @@ int __ethtool_set_flags(struct net_device *dev, u32 data) return 0; } -static int ethtool_get_settings(struct net_device *dev, void __user *useraddr) +int __ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { - struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; - int err; + ASSERT_RTNL(); - if (!dev->ethtool_ops->get_settings) + if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings) return -EOPNOTSUPP; - err = dev->ethtool_ops->get_settings(dev, &cmd); + memset(cmd, 0, sizeof(struct ethtool_cmd)); + cmd->cmd = ETHTOOL_GSET; + return dev->ethtool_ops->get_settings(dev, cmd); +} +EXPORT_SYMBOL(__ethtool_get_settings); + +static int ethtool_get_settings(struct net_device *dev, void __user *useraddr) +{ + int err; + struct ethtool_cmd cmd; + + err = __ethtool_get_settings(dev, &cmd); if (err < 0) return err; diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c index 90fdb46..48e6279 100644 --- a/net/core/net-sysfs.c +++ b/net/core/net-sysfs.c @@ -172,7 +172,7 @@ static ssize_t show_speed(struct device *dev, if (netif_running(netdev)) { struct ethtool_cmd cmd; - if (!dev_ethtool_get_settings(netdev, &cmd)) + if (!__ethtool_get_settings(netdev, &cmd)) ret = sprintf(buf, fmt_udec, ethtool_cmd_speed(&cmd)); } rtnl_unlock(); @@ -190,7 +190,7 @@ static ssize_t show_duplex(struct device *dev, if (netif_running(netdev)) { struct ethtool_cmd cmd; - if (!dev_ethtool_get_settings(netdev, &cmd)) + if (!__ethtool_get_settings(netdev, &cmd)) ret = sprintf(buf, "%s\n", cmd.duplex ? "full" : "half"); } diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 2ea3d63..25e68f5 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -530,33 +530,35 @@ static int prb_calc_retire_blk_tmo(struct packet_sock *po, { struct net_device *dev; unsigned int mbits = 0, msec = 0, div = 0, tmo = 0; + struct ethtool_cmd ecmd; + int err; - dev = dev_get_by_index(sock_net(&po->sk), po->ifindex); - if (unlikely(dev == NULL)) + rtnl_lock(); + dev = __dev_get_by_index(sock_net(&po->sk), po->ifindex); + if (unlikely(!dev)) { + rtnl_unlock(); return DEFAULT_PRB_RETIRE_TOV; - - if (dev->ethtool_ops && dev->ethtool_ops->get_settings) { - struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET, }; - - if (!dev->ethtool_ops->get_settings(dev, &ecmd)) { - switch (ecmd.speed) { - case SPEED_10000: - msec = 1; - div = 10000/1000; - break; - case SPEED_1000: - msec = 1; - div = 1000/1000; - break; - /* - * If the link speed is so slow you don't really - * need to worry about perf anyways - */ - case SPEED_100: - case SPEED_10: - default: - return DEFAULT_PRB_RETIRE_TOV; - } + } + err = __ethtool_get_settings(dev, &ecmd); + rtnl_unlock(); + if (!err) { + switch (ecmd.speed) { + case SPEED_10000: + msec = 1; + div = 10000/1000; + break; + case SPEED_1000: + msec = 1; + div = 1000/1000; + break; + /* + * If the link speed is so slow you don't really + * need to worry about perf anyways + */ + case SPEED_100: + case SPEED_10: + default: + return DEFAULT_PRB_RETIRE_TOV; } } -- 1.7.6 From bhutchings@solarflare.com Sat Sep 3 15:47:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Sep 2011 15:47:14 +0200 (CEST) Received: from exchange.solarflare.com ([216.237.3.220]:15333 "EHLO exchange.solarflare.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491123Ab1ICNrH (ORCPT ); Sat, 3 Sep 2011 15:47:07 +0200 Received: from [192.168.4.185] ([88.96.1.126]) by exchange.solarflare.com with Microsoft SMTPSVC(6.0.3790.4675); Sat, 3 Sep 2011 06:46:55 -0700 Subject: Re: [patch net-next-2.6 v3] net: consolidate and fix ethtool_ops->get_settings calling From: Ben Hutchings To: Jiri Pirko Cc: netdev@vger.kernel.org, ralf@linux-mips.org, fubar@us.ibm.com, andy@greyhouse.net, kaber@trash.net, bprakash@broadcom.com, JBottomley@parallels.com, robert.w.love@intel.com, davem@davemloft.net, shemminger@linux-foundation.org, decot@google.com, mirq-linux@rere.qmqm.pl, alexander.h.duyck@intel.com, amit.salecha@qlogic.com, eric.dumazet@gmail.com, therbert@google.com, paulmck@linux.vnet.ibm.com, laijs@cn.fujitsu.com, xiaosuo@gmail.com, greearb@candelatech.com, loke.chetan@gmail.com, linux-mips@linux-mips.org, linux-scsi@vger.kernel.org, devel@open-fcoe.org, bridge@lists.linux-foundation.org Date: Sat, 03 Sep 2011 14:46:47 +0100 In-Reply-To: <20110903133428.GA2821@minipsycho> References: <1314905304-16485-1-git-send-email-jpirko@redhat.com> <20110902122630.GC1991@minipsycho> <1314989161.3419.5.camel@bwh-desktop> <20110903133428.GA2821@minipsycho> Organization: Solarflare Communications Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.0.2- Content-Transfer-Encoding: 7bit Message-ID: <1315057614.3092.160.camel@deadeye> Mime-Version: 1.0 X-OriginalArrivalTime: 03 Sep 2011 13:46:55.0806 (UTC) FILETIME=[F1BCADE0:01CC6A3F] X-TM-AS-Product-Ver: SMEX-8.0.0.1181-6.500.1024-18362.005 X-TM-AS-Result: No--5.126500-0.000000-31 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-archive-position: 31037 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhutchings@solarflare.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1891 Content-Length: 1160 Lines: 25 On Sat, 2011-09-03 at 15:34 +0200, Jiri Pirko wrote: > This patch does several things: > - introduces __ethtool_get_settings which is called from ethtool code and > from drivers as well. Put ASSERT_RTNL there. > - dev_ethtool_get_settings() is replaced by __ethtool_get_settings() > - changes calling in drivers so rtnl locking is respected. In > iboe_get_rate was previously ->get_settings() called unlocked. This > fixes it. Also prb_calc_retire_blk_tmo() in af_packet.c had the same > problem. Also fixed by calling __dev_get_by_index() instead of > dev_get_by_index() and holding rtnl_lock for both calls. > - introduces rtnl_lock in bnx2fc_vport_create() and fcoe_vport_create() > so bnx2fc_if_create() and fcoe_if_create() are called locked as they > are from other places. > - use __ethtool_get_settings() in bonding code > > Signed-off-by: Jiri Pirko Reviewed-by: Ben Hutchings [except FCoE bits] Ben. -- Ben Hutchings, Staff Engineer, Solarflare Not speaking for my employer; that's the marketing department's job. They asked us to note that Solarflare product names are trademarked. From jayachandranc@netlogicmicro.com Sun Sep 4 20:04:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 04 Sep 2011 20:04:39 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:4984 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491066Ab1IDSEc (ORCPT ); Sun, 4 Sep 2011 20:04:32 +0200 X-TM-IMSS-Message-ID: <9ba5cbc30002db9d@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 9ba5cbc30002db9d ; Sun, 4 Sep 2011 11:02:23 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 4 Sep 2011 11:05:36 -0700 Date: Sun, 4 Sep 2011 23:40:21 +0530 From: Jayachandran C To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 0/4] MIPS: Support for Netlogic XLP processors Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 04 Sep 2011 18:05:36.0842 (UTC) FILETIME=[3F6892A0:01CC6B2D] X-archive-position: 31038 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2158 Content-Length: 3756 Lines: 72 This patchset adds support for Netlogic's new XLP processor series. Please see http://netlogicmicro.com/Products/ProductBriefs/MultiCore/XLP832.htm for more details on this processor, The changes here has the platform support with UART, PIC and 32-way SMP. Comments on the code and suggestions are very welcome. Changes from the previous patchset: - Fixes for review comments for the first patchset - Remove 32-bit support code for now, this will be added when 32-bit support works. - Removed unused assembly macros and BSD code from include/netlogic Jayachandran C (4): MIPS: Netlogic: XLP CPU support. MIPS: Netlogic: Platform files for XLP processors. MIPS: Netlogic: Build support for netlogic XLP MIPS: Netlogic: Add default XLP config. arch/mips/Kconfig | 44 ++ arch/mips/configs/nlm_xlp_defconfig | 590 ++++++++++++++++++++ arch/mips/include/asm/cpu.h | 3 +- .../asm/mach-netlogic/cpu-feature-overrides.h | 18 +- arch/mips/include/asm/module.h | 2 + arch/mips/include/asm/netlogic/xlp-hal/bridge.h | 187 +++++++ .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 83 +++ arch/mips/include/asm/netlogic/xlp-hal/haldefs.h | 154 +++++ arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 155 +++++ arch/mips/include/asm/netlogic/xlp-hal/pic.h | 383 +++++++++++++ arch/mips/include/asm/netlogic/xlp-hal/sys.h | 128 +++++ arch/mips/include/asm/netlogic/xlp-hal/uart.h | 191 +++++++ arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 71 +++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/cpu-probe.c | 19 +- arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/mm/c-r4k.c | 3 + arch/mips/netlogic/Kconfig | 3 + arch/mips/netlogic/Platform | 7 + arch/mips/netlogic/xlp/Makefile | 5 + arch/mips/netlogic/xlp/irq.c | 240 ++++++++ arch/mips/netlogic/xlp/nlm_hal.c | 85 +++ arch/mips/netlogic/xlp/platform.c | 108 ++++ arch/mips/netlogic/xlp/setup.c | 98 ++++ arch/mips/netlogic/xlp/smp.c | 285 ++++++++++ arch/mips/netlogic/xlp/smpboot.S | 217 +++++++ arch/mips/netlogic/xlp/time.c | 74 +++ arch/mips/netlogic/xlp/xlp_console.c | 50 ++ 29 files changed, 3198 insertions(+), 8 deletions(-) create mode 100644 arch/mips/configs/nlm_xlp_defconfig create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/bridge.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/haldefs.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/sys.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/uart.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/xlp.h create mode 100644 arch/mips/netlogic/xlp/Makefile create mode 100644 arch/mips/netlogic/xlp/irq.c create mode 100644 arch/mips/netlogic/xlp/nlm_hal.c create mode 100644 arch/mips/netlogic/xlp/platform.c create mode 100644 arch/mips/netlogic/xlp/setup.c create mode 100644 arch/mips/netlogic/xlp/smp.c create mode 100644 arch/mips/netlogic/xlp/smpboot.S create mode 100644 arch/mips/netlogic/xlp/time.c create mode 100644 arch/mips/netlogic/xlp/xlp_console.c -- 1.7.4.1 From jayachandranc@netlogicmicro.com Sun Sep 4 20:05:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 04 Sep 2011 20:05:38 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:1117 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491066Ab1IDSFb (ORCPT ); Sun, 4 Sep 2011 20:05:31 +0200 X-TM-IMSS-Message-ID: <9ba6b78a0002dba1@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 9ba6b78a0002dba1 ; Sun, 4 Sep 2011 11:03:23 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 4 Sep 2011 11:05:56 -0700 Date: Sun, 4 Sep 2011 23:40:41 +0530 From: Jayachandran C To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 1/4] MIPS: Netlogic: XLP CPU support. Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 04 Sep 2011 18:05:56.0513 (UTC) FILETIME=[4B222110:01CC6B2D] X-archive-position: 31039 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2159 Content-Length: 4939 Lines: 158 Add support for Netlogic's XLP MIPS SoC. This patch adds: * XLP processor ID in cpu_probe.c and asm/cpu.h * XLP case to asm/module.h * CPU_XLP case to mm/tlbex.c * minor change to r4k cache handling to ignore XLP secondary cache * XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h Signed-off-by: Jayachandran C --- arch/mips/include/asm/cpu.h | 3 ++- .../asm/mach-netlogic/cpu-feature-overrides.h | 18 ++++++++++++++---- arch/mips/include/asm/module.h | 2 ++ arch/mips/kernel/cpu-probe.c | 19 ++++++++++++++++--- arch/mips/mm/c-r4k.c | 3 +++ 5 files changed, 37 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 5f95a4b..4bcb668b 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -167,6 +167,7 @@ #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 +#define PRID_IMP_NETLOGIC_XLP832 0x1000 /* * Definitions for 7:0 on legacy processors */ @@ -260,7 +261,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, - CPU_XLR, + CPU_XLR, CPU_XLP, CPU_LAST }; diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h index 3780743..d193fb6 100644 --- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h @@ -24,23 +24,33 @@ #define cpu_has_llsc 1 #define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 1 #define cpu_has_dsp 0 #define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 #define cpu_icache_snoops_remote_store 1 #define cpu_has_64bits 1 #define cpu_has_mips32r1 1 -#define cpu_has_mips32r2 0 #define cpu_has_mips64r1 1 -#define cpu_has_mips64r2 0 #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 +#if defined(CONFIG_CPU_XLR) +#define cpu_has_userlocal 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r2 0 +#elif defined(CONFIG_CPU_XLP) +#define cpu_has_userlocal 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r2 1 +#define cpu_has_dc_aliases 1 +#else +#error "Unknown Netlogic CPU" +#endif + #endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index bc01a02..2278e34 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -120,6 +120,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "OCTEON " #elif defined CONFIG_CPU_XLR #define MODULE_PROC_FAMILY "XLR " +#elif defined CONFIG_CPU_XLP +#define MODULE_PROC_FAMILY "XLP " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 664bc13..501d302 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -191,6 +191,7 @@ void __init check_wait(void) case CPU_CAVIUM_OCTEON2: case CPU_JZRISC: case CPU_XLR: + case CPU_XLP: cpu_wait = r4k_wait; break; @@ -1020,6 +1021,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) MIPS_CPU_LLSC); switch (c->processor_id & 0xff00) { + case PRID_IMP_NETLOGIC_XLP832: + c->cputype = CPU_XLP; + __cpu_name[cpu] = "Netlogic XLP"; + break; + case PRID_IMP_NETLOGIC_XLR732: case PRID_IMP_NETLOGIC_XLR716: case PRID_IMP_NETLOGIC_XLR532: @@ -1050,14 +1056,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) break; default: - printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", + pr_info("Unknown Netlogic chip id [%02x]!\n", c->processor_id); c->cputype = CPU_XLR; break; } - c->isa_level = MIPS_CPU_ISA_M64R1; - c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; + if (c->cputype == CPU_XLP) { + c->isa_level = MIPS_CPU_ISA_M64R2; + c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); + /* This will be updated again after all threads are woken up */ + c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; + } else { + c->isa_level = MIPS_CPU_ISA_M64R1; + c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; + } } #ifdef CONFIG_64BIT diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a79fe9a..4f9eb0b 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void) loongson2_sc_init(); return; #endif + case CPU_XLP: + /* don't need to worry about L2, fully coherent */ + return; default: if (c->isa_level == MIPS_CPU_ISA_M32R1 || -- 1.7.4.1 From jayachandranc@netlogicmicro.com Sun Sep 4 20:06:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 04 Sep 2011 20:07:08 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:1607 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491066Ab1IDSGd (ORCPT ); Sun, 4 Sep 2011 20:06:33 +0200 X-TM-IMSS-Message-ID: <9ba7a2d50002dba9@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 9ba7a2d50002dba9 ; Sun, 4 Sep 2011 11:04:23 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 4 Sep 2011 11:07:23 -0700 Date: Sun, 4 Sep 2011 23:42:08 +0530 From: Jayachandran C To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 2/4] MIPS: Netlogic: Platform files for XLP processors. Message-ID: <7aed2c03c63291c90b7fadd3f768899159f1657e.1315075195.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 04 Sep 2011 18:07:23.0467 (UTC) FILETIME=[7EF641B0:01CC6B2D] X-archive-position: 31041 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2161 Content-Length: 87198 Lines: 2660 * Add include/asm/netlogic/xlp-hal/ - hardware access library for XLP * Add netlogic/xlp - platform files including PIC support, early console and FDT based startup Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlp-hal/bridge.h | 187 ++++++++++ .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 83 +++++ arch/mips/include/asm/netlogic/xlp-hal/haldefs.h | 154 ++++++++ arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 155 ++++++++ arch/mips/include/asm/netlogic/xlp-hal/pic.h | 383 ++++++++++++++++++++ arch/mips/include/asm/netlogic/xlp-hal/sys.h | 128 +++++++ arch/mips/include/asm/netlogic/xlp-hal/uart.h | 191 ++++++++++ arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 71 ++++ arch/mips/netlogic/xlp/Makefile | 4 + arch/mips/netlogic/xlp/irq.c | 240 ++++++++++++ arch/mips/netlogic/xlp/nlm_hal.c | 85 +++++ arch/mips/netlogic/xlp/platform.c | 108 ++++++ arch/mips/netlogic/xlp/setup.c | 98 +++++ arch/mips/netlogic/xlp/smp.c | 285 +++++++++++++++ arch/mips/netlogic/xlp/smpboot.S | 217 +++++++++++ arch/mips/netlogic/xlp/time.c | 74 ++++ arch/mips/netlogic/xlp/xlp_console.c | 50 +++ 17 files changed, 2513 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/bridge.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/haldefs.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/sys.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/uart.h create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/xlp.h create mode 100644 arch/mips/netlogic/xlp/Makefile create mode 100644 arch/mips/netlogic/xlp/irq.c create mode 100644 arch/mips/netlogic/xlp/nlm_hal.c create mode 100644 arch/mips/netlogic/xlp/platform.c create mode 100644 arch/mips/netlogic/xlp/setup.c create mode 100644 arch/mips/netlogic/xlp/smp.c create mode 100644 arch/mips/netlogic/xlp/smpboot.S create mode 100644 arch/mips/netlogic/xlp/time.c create mode 100644 arch/mips/netlogic/xlp/xlp_console.c diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h new file mode 100644 index 0000000..ca95133 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h @@ -0,0 +1,187 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NLM_HAL_BRIDGE_H__ +#define __NLM_HAL_BRIDGE_H__ + +/** +* @file_name mio.h +* @author Netlogic Microsystems +* @brief Basic definitions of XLP memory and io subsystem +*/ + +/* + * BRIDGE specific registers + * + * These registers start after the PCIe header, which has 0x40 + * standard entries + */ +#define BRIDGE_MODE 0x00 +#define BRIDGE_PCI_CFG_BASE 0x01 +#define BRIDGE_PCI_CFG_LIMIT 0x02 +#define BRIDGE_PCIE_CFG_BASE 0x03 +#define BRIDGE_PCIE_CFG_LIMIT 0x04 +#define BRIDGE_BUSNUM_BAR0 0x05 +#define BRIDGE_BUSNUM_BAR1 0x06 +#define BRIDGE_BUSNUM_BAR2 0x07 +#define BRIDGE_BUSNUM_BAR3 0x08 +#define BRIDGE_BUSNUM_BAR4 0x09 +#define BRIDGE_BUSNUM_BAR5 0x0a +#define BRIDGE_BUSNUM_BAR6 0x0b +#define BRIDGE_FLASH_BAR0 0x0c +#define BRIDGE_FLASH_BAR1 0x0d +#define BRIDGE_FLASH_BAR2 0x0e +#define BRIDGE_FLASH_BAR3 0x0f +#define BRIDGE_FLASH_LIMIT0 0x10 +#define BRIDGE_FLASH_LIMIT1 0x11 +#define BRIDGE_FLASH_LIMIT2 0x12 +#define BRIDGE_FLASH_LIMIT3 0x13 + +#define BRIDGE_DRAM_BAR(i) (0x14 + (i)) +#define BRIDGE_DRAM_BAR0 0x14 +#define BRIDGE_DRAM_BAR1 0x15 +#define BRIDGE_DRAM_BAR2 0x16 +#define BRIDGE_DRAM_BAR3 0x17 +#define BRIDGE_DRAM_BAR4 0x18 +#define BRIDGE_DRAM_BAR5 0x19 +#define BRIDGE_DRAM_BAR6 0x1a +#define BRIDGE_DRAM_BAR7 0x1b + +#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) +#define BRIDGE_DRAM_LIMIT0 0x1c +#define BRIDGE_DRAM_LIMIT1 0x1d +#define BRIDGE_DRAM_LIMIT2 0x1e +#define BRIDGE_DRAM_LIMIT3 0x1f +#define BRIDGE_DRAM_LIMIT4 0x20 +#define BRIDGE_DRAM_LIMIT5 0x21 +#define BRIDGE_DRAM_LIMIT6 0x22 +#define BRIDGE_DRAM_LIMIT7 0x23 + +#define BRIDGE_DRAM_NODE_TRANSLN0 0x24 +#define BRIDGE_DRAM_NODE_TRANSLN1 0x25 +#define BRIDGE_DRAM_NODE_TRANSLN2 0x26 +#define BRIDGE_DRAM_NODE_TRANSLN3 0x27 +#define BRIDGE_DRAM_NODE_TRANSLN4 0x28 +#define BRIDGE_DRAM_NODE_TRANSLN5 0x29 +#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a +#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b +#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c +#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d +#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e +#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f +#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30 +#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 +#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 +#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 +#define BRIDGE_PCIEMEM_BASE0 0x34 +#define BRIDGE_PCIEMEM_BASE1 0x35 +#define BRIDGE_PCIEMEM_BASE2 0x36 +#define BRIDGE_PCIEMEM_BASE3 0x37 +#define BRIDGE_PCIEMEM_LIMIT0 0x38 +#define BRIDGE_PCIEMEM_LIMIT1 0x39 +#define BRIDGE_PCIEMEM_LIMIT2 0x3a +#define BRIDGE_PCIEMEM_LIMIT3 0x3b +#define BRIDGE_PCIEIO_BASE0 0x3c +#define BRIDGE_PCIEIO_BASE1 0x3d +#define BRIDGE_PCIEIO_BASE2 0x3e +#define BRIDGE_PCIEIO_BASE3 0x3f +#define BRIDGE_PCIEIO_LIMIT0 0x40 +#define BRIDGE_PCIEIO_LIMIT1 0x41 +#define BRIDGE_PCIEIO_LIMIT2 0x42 +#define BRIDGE_PCIEIO_LIMIT3 0x43 +#define BRIDGE_PCIEMEM_BASE4 0x44 +#define BRIDGE_PCIEMEM_BASE5 0x45 +#define BRIDGE_PCIEMEM_BASE6 0x46 +#define BRIDGE_PCIEMEM_LIMIT4 0x47 +#define BRIDGE_PCIEMEM_LIMIT5 0x48 +#define BRIDGE_PCIEMEM_LIMIT6 0x49 +#define BRIDGE_PCIEIO_BASE4 0x4a +#define BRIDGE_PCIEIO_BASE5 0x4b +#define BRIDGE_PCIEIO_BASE6 0x4c +#define BRIDGE_PCIEIO_LIMIT4 0x4d +#define BRIDGE_PCIEIO_LIMIT5 0x4e +#define BRIDGE_PCIEIO_LIMIT6 0x4f +#define BRIDGE_NBU_EVENT_CNT_CTL 0x50 +#define BRIDGE_EVNTCTR1_LOW 0x51 +#define BRIDGE_EVNTCTR1_HI 0x52 +#define BRIDGE_EVNT_CNT_CTL2 0x53 +#define BRIDGE_EVNTCTR2_LOW 0x54 +#define BRIDGE_EVNTCTR2_HI 0x55 +#define BRIDGE_TRACEBUF_MATCH0 0x56 +#define BRIDGE_TRACEBUF_MATCH1 0x57 +#define BRIDGE_TRACEBUF_MATCH_LOW 0x58 +#define BRIDGE_TRACEBUF_MATCH_HI 0x59 +#define BRIDGE_TRACEBUF_CTRL 0x5a +#define BRIDGE_TRACEBUF_INIT 0x5b +#define BRIDGE_TRACEBUF_ACCESS 0x5c +#define BRIDGE_TRACEBUF_READ_DATA0 0x5d +#define BRIDGE_TRACEBUF_READ_DATA1 0x5d +#define BRIDGE_TRACEBUF_READ_DATA2 0x5f +#define BRIDGE_TRACEBUF_READ_DATA3 0x60 +#define BRIDGE_TRACEBUF_STATUS 0x61 +#define BRIDGE_ADDRESS_ERROR0 0x62 +#define BRIDGE_ADDRESS_ERROR1 0x63 +#define BRIDGE_ADDRESS_ERROR2 0x64 +#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65 +#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66 +#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67 +#define BRIDGE_LINE_FLUSH0 0x68 +#define BRIDGE_LINE_FLUSH1 0x69 +#define BRIDGE_NODE_ID 0x6a +#define BRIDGE_ERROR_INTERRUPT_EN 0x6b +#define BRIDGE_PCIE0_WEIGHT 0x2c0 +#define BRIDGE_PCIE1_WEIGHT 0x2c1 +#define BRIDGE_PCIE2_WEIGHT 0x2c2 +#define BRIDGE_PCIE3_WEIGHT 0x2c3 +#define BRIDGE_USB_WEIGHT 0x2c4 +#define BRIDGE_NET_WEIGHT 0x2c5 +#define BRIDGE_POE_WEIGHT 0x2c6 +#define BRIDGE_CMS_WEIGHT 0x2c7 +#define BRIDGE_DMAENG_WEIGHT 0x2c8 +#define BRIDGE_SEC_WEIGHT 0x2c9 +#define BRIDGE_COMP_WEIGHT 0x2ca +#define BRIDGE_GIO_WEIGHT 0x2cb +#define BRIDGE_FLASH_WEIGHT 0x2cc + +#ifndef __ASSEMBLY__ + +#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_get_bridge_pcibase(node) \ + nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) +#define nlm_get_bridge_regbase(node) \ + (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) + +#endif /* __ASSEMBLY__ */ +#endif /* __NLM_HAL_BRIDGE_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h new file mode 100644 index 0000000..bf7d41d --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h @@ -0,0 +1,83 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NLM_HAL_CPUCONTROL_H__ +#define __NLM_HAL_CPUCONTROL_H__ + +#define CPU_BLOCKID_IFU 0 +#define CPU_BLOCKID_ICU 1 +#define CPU_BLOCKID_IEU 2 +#define CPU_BLOCKID_LSU 3 +#define CPU_BLOCKID_MMU 4 +#define CPU_BLOCKID_PRF 5 +#define CPU_BLOCKID_SCH 7 +#define CPU_BLOCKID_SCU 8 +#define CPU_BLOCKID_FPU 9 +#define CPU_BLOCKID_MAP 10 + +#define LSU_DEFEATURE 0x304 +#define LSU_CERRLOG_REGID 0x09 +#define SCHED_DEFEATURE 0x700 + +/* Offsets of interest from the 'MAP' Block */ +#define MAP_THREADMODE 0x00 +#define MAP_EXT_EBASE_ENABLE 0x04 +#define MAP_CCDI_CONFIG 0x08 +#define MAP_THRD0_CCDI_STATUS 0x0c +#define MAP_THRD1_CCDI_STATUS 0x10 +#define MAP_THRD2_CCDI_STATUS 0x14 +#define MAP_THRD3_CCDI_STATUS 0x18 +#define MAP_THRD0_DEBUG_MODE 0x1c +#define MAP_THRD1_DEBUG_MODE 0x20 +#define MAP_THRD2_DEBUG_MODE 0x24 +#define MAP_THRD3_DEBUG_MODE 0x28 +#define MAP_MISC_STATE 0x60 +#define MAP_DEBUG_READ_CTL 0x64 +#define MAP_DEBUG_READ_REG0 0x68 +#define MAP_DEBUG_READ_REG1 0x6c + +#define MMU_SETUP 0x400 +#define MMU_LFSRSEED 0x401 +#define MMU_HPW_NUM_PAGE_LVL 0x410 +#define MMU_PGWKR_PGDBASE 0x411 +#define MMU_PGWKR_PGDSHFT 0x412 +#define MMU_PGWKR_PGDMASK 0x413 +#define MMU_PGWKR_PUDSHFT 0x414 +#define MMU_PGWKR_PUDMASK 0x415 +#define MMU_PGWKR_PMDSHFT 0x416 +#define MMU_PGWKR_PMDMASK 0x417 +#define MMU_PGWKR_PTESHFT 0x418 +#define MMU_PGWKR_PTEMASK 0x419 + +#endif /* __NLM_CPUCONTROL_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/haldefs.h b/arch/mips/include/asm/netlogic/xlp-hal/haldefs.h new file mode 100644 index 0000000..642f411 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/haldefs.h @@ -0,0 +1,154 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NLM_HAL_HALDEFS_H__ +#define __NLM_HAL_HALDEFS_H__ + +/* + * This file contains platform specific memory mapped IO implementation + * and will provide a way to read 32/64 bit memory mapped registers in + * all ABIs + */ +#ifndef CONFIG_64BIT +#error "o32 compile not supported yet" +#endif +/* + * For o32 compilation, we have to disable interrupts and enable KX bit to + * access 64 bit addresses or data. + * + * We need to disable interrupts because we save just the lower 32 bits of + * registers in interrupt handling. So if we get hit by an interrupt while + * using the upper 32 bits of a register, we lose. + */ +static inline uint32_t nlm_save_flags_kx(void) +{ + return change_c0_status(ST0_KX | ST0_IE, ST0_KX); +} + +static inline uint32_t nlm_save_flags_cop2(void) +{ + return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2); +} + +static inline void nlm_restore_flags(uint32_t sr) +{ + write_c0_status(sr); +} + +/* + * The n64 implementations are simple, the o32 implementations when they + * are added, will have to disable interrupts and enable KX before doing + * 64 bit ops. + */ +static inline uint32_t +nlm_read_reg(uint64_t base, uint32_t reg) +{ + volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; + + return *addr; +} + +static inline void +nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) +{ + volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; + + *addr = val; +} + +static inline uint64_t +nlm_read_reg64(uint64_t base, uint32_t reg) +{ + uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); + volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; + + return *ptr; +} + +static inline void +nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) +{ + uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); + volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; + + *ptr = val; +} + +/* + * Routines to store 32/64 bit values to 64 bit addresses, + * used when going thru XKPHYS to access registers + */ +static inline uint32_t +nlm_read_reg_xkphys(uint64_t base, uint32_t reg) +{ + return nlm_read_reg(base, reg); +} + +static inline void +nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) +{ + nlm_write_reg(base, reg, val); +} + +static inline uint64_t +nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) +{ + return nlm_read_reg64(base, reg); +} + +static inline void +nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) +{ + nlm_write_reg64(base, reg, val); +} + +/* Location where IO base is mapped */ +extern uint64_t xlp_io_base; + +static inline uint64_t +nlm_pcicfg_base(uint32_t devoffset) +{ + return xlp_io_base + devoffset; +} + +static inline uint64_t +nlm_xkphys_map_pcibar0(uint64_t pcibase) +{ + uint64_t paddr; + + paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu; + return (uint64_t)0x9000000000000000 | paddr; +} + +#endif diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h new file mode 100644 index 0000000..d239f8d --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h @@ -0,0 +1,155 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NLM_HAL_IOMAP_H__ +#define __NLM_HAL_IOMAP_H__ + +#define XLP_DEFAULT_IO_BASE 0x18000000 +#define NMI_BASE 0xbfc00000 +#define XLP_IO_CLK 133333333 + +#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */ +#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE) +#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE) +#define XLP_IO_SIZE (64 << 20) /* ECFG space size */ +#define XLP_IO_PCI_HDRSZ 0x100 +#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) +#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ + ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) + +#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) +/* coherent inter chip */ +#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1) +#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2) +#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3) +#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4) + +#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i) +#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0) +#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1) +#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2) +#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3) + +#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i) +#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0) +#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1) +#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2) +#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3) +#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) +#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) + +#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) +#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) + +#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0) + +#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1) +#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2) +#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3) + +#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i) +#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0) +#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1) +#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i) +#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) +#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) +#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) +/* system management */ +#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) +#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) + +#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0) +#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) +#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) +/* SD flash */ +#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) +#define XLP_IO_MMC_OFFSET(node, slot) \ + ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) + +/* PCI config header register id's */ +#define XLP_PCI_CFGREG0 0x00 +#define XLP_PCI_CFGREG1 0x01 +#define XLP_PCI_CFGREG2 0x02 +#define XLP_PCI_CFGREG3 0x03 +#define XLP_PCI_CFGREG4 0x04 +#define XLP_PCI_CFGREG5 0x05 +#define XLP_PCI_DEVINFO_REG0 0x30 +#define XLP_PCI_DEVINFO_REG1 0x31 +#define XLP_PCI_DEVINFO_REG2 0x32 +#define XLP_PCI_DEVINFO_REG3 0x33 +#define XLP_PCI_DEVINFO_REG4 0x34 +#define XLP_PCI_DEVINFO_REG5 0x35 +#define XLP_PCI_DEVINFO_REG6 0x36 +#define XLP_PCI_DEVINFO_REG7 0x37 +#define XLP_PCI_DEVSCRATCH_REG0 0x38 +#define XLP_PCI_DEVSCRATCH_REG1 0x39 +#define XLP_PCI_DEVSCRATCH_REG2 0x3a +#define XLP_PCI_DEVSCRATCH_REG3 0x3b +#define XLP_PCI_MSGSTN_REG 0x3c +#define XLP_PCI_IRTINFO_REG 0x3d +#define XLP_PCI_UCODEINFO_REG 0x3e +#define XLP_PCI_SBB_WT_REG 0x3f + +/* PCI IDs for SoC device */ +#define PCI_VENDOR_NETLOGIC 0x184e + +#define PCI_DEVICE_ID_NLM_ROOT 0x1001 +#define PCI_DEVICE_ID_NLM_ICI 0x1002 +#define PCI_DEVICE_ID_NLM_PIC 0x1003 +#define PCI_DEVICE_ID_NLM_PCIE 0x1004 +#define PCI_DEVICE_ID_NLM_EHCI 0x1007 +#define PCI_DEVICE_ID_NLM_ILK 0x1008 +#define PCI_DEVICE_ID_NLM_NAE 0x1009 +#define PCI_DEVICE_ID_NLM_POE 0x100A +#define PCI_DEVICE_ID_NLM_FMN 0x100B +#define PCI_DEVICE_ID_NLM_RAID 0x100D +#define PCI_DEVICE_ID_NLM_SAE 0x100D +#define PCI_DEVICE_ID_NLM_RSA 0x100E +#define PCI_DEVICE_ID_NLM_CMP 0x100F +#define PCI_DEVICE_ID_NLM_UART 0x1010 +#define PCI_DEVICE_ID_NLM_I2C 0x1011 +#define PCI_DEVICE_ID_NLM_NOR 0x1015 +#define PCI_DEVICE_ID_NLM_NAND 0x1016 +#define PCI_DEVICE_ID_NLM_MMC 0x1018 + +#ifndef __ASSEMBLY__ + +#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) + +extern uint64_t xlp_sys_base; +extern uint64_t xlp_pic_base; +#endif /* !__ASSEMBLY */ + +#endif /* __NLM_HAL_IOMAP_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h new file mode 100644 index 0000000..ff3f1c7 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h @@ -0,0 +1,383 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NLM_HAL_PIC_H +#define _NLM_HAL_PIC_H + +/* PIC Specific registers */ +#define PIC_CTRL 0x00 + +/* PIC control register defines */ +#define PIC_CTRL_ITV 32 /* interrupt timeout value */ +#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */ +#define PIC_CTRL_ITE 18 /* interrupt timeout enable */ +#define PIC_CTRL_STE 10 /* system timer interrupt enable */ +#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */ +#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */ +#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */ +#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */ +#define PIC_CTRL_WTE 0 /* watchdog timer enable */ + +/* PIC Status register defines */ +#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */ +#define PIC_ITE_STATUS 32 /* interrupt timeout status */ +#define PIC_STS_STATUS 4 /* System timer interrupt status */ +#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */ +#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */ + +/* PIC IPI control register offsets */ +#define PIC_IPICTRL_NMI 32 +#define PIC_IPICTRL_RIV 20 /* received interrupt vector */ +#define PIC_IPICTRL_IDB 16 /* interrupt destination base */ +#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */ + +/* PIC IRT register offsets */ +#define PIC_IRT_ENABLE 31 +#define PIC_IRT_NMI 29 +#define PIC_IRT_SCH 28 /* Scheduling scheme */ +#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */ +#define PIC_IRT_DT 19 /* Destination type */ +#define PIC_IRT_DB 16 /* Destination base */ +#define PIC_IRT_DTE 0 /* Destination thread enables */ + +#define PIC_BYTESWAP 0x02 +#define PIC_STATUS 0x04 +#define PIC_INTR_TIMEOUT 0x06 +#define PIC_ICI0_INTR_TIMEOUT 0x08 +#define PIC_ICI1_INTR_TIMEOUT 0x0a +#define PIC_ICI2_INTR_TIMEOUT 0x0c +#define PIC_IPI_CTL 0x0e +#define PIC_INT_ACK 0x10 +#define PIC_INT_PENDING0 0x12 +#define PIC_INT_PENDING1 0x14 +#define PIC_INT_PENDING2 0x16 + +#define PIC_WDOG0_MAXVAL 0x18 +#define PIC_WDOG0_COUNT 0x1a +#define PIC_WDOG0_ENABLE0 0x1c +#define PIC_WDOG0_ENABLE1 0x1e +#define PIC_WDOG0_BEATCMD 0x20 +#define PIC_WDOG0_BEAT0 0x22 +#define PIC_WDOG0_BEAT1 0x24 + +#define PIC_WDOG1_MAXVAL 0x26 +#define PIC_WDOG1_COUNT 0x28 +#define PIC_WDOG1_ENABLE0 0x2a +#define PIC_WDOG1_ENABLE1 0x2c +#define PIC_WDOG1_BEATCMD 0x2e +#define PIC_WDOG1_BEAT0 0x30 +#define PIC_WDOG1_BEAT1 0x32 + +#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) +#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) +#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0)) +#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0)) +#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) +#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0)) +#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0)) + +#define PIC_TIMER0_MAXVAL 0x34 +#define PIC_TIMER1_MAXVAL 0x36 +#define PIC_TIMER2_MAXVAL 0x38 +#define PIC_TIMER3_MAXVAL 0x3a +#define PIC_TIMER4_MAXVAL 0x3c +#define PIC_TIMER5_MAXVAL 0x3e +#define PIC_TIMER6_MAXVAL 0x40 +#define PIC_TIMER7_MAXVAL 0x42 +#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2)) + +#define PIC_TIMER0_COUNT 0x44 +#define PIC_TIMER1_COUNT 0x46 +#define PIC_TIMER2_COUNT 0x48 +#define PIC_TIMER3_COUNT 0x4a +#define PIC_TIMER4_COUNT 0x4c +#define PIC_TIMER5_COUNT 0x4e +#define PIC_TIMER6_COUNT 0x50 +#define PIC_TIMER7_COUNT 0x52 +#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2)) + +#define PIC_ITE0_N0_N1 0x54 +#define PIC_ITE1_N0_N1 0x58 +#define PIC_ITE2_N0_N1 0x5c +#define PIC_ITE3_N0_N1 0x60 +#define PIC_ITE4_N0_N1 0x64 +#define PIC_ITE5_N0_N1 0x68 +#define PIC_ITE6_N0_N1 0x6c +#define PIC_ITE7_N0_N1 0x70 +#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4)) + +#define PIC_ITE0_N2_N3 0x56 +#define PIC_ITE1_N2_N3 0x5a +#define PIC_ITE2_N2_N3 0x5e +#define PIC_ITE3_N2_N3 0x62 +#define PIC_ITE4_N2_N3 0x66 +#define PIC_ITE5_N2_N3 0x6a +#define PIC_ITE6_N2_N3 0x6e +#define PIC_ITE7_N2_N3 0x72 +#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4)) + +#define PIC_IRT0 0x74 +#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) + +#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL + +/* + * IRT Map + */ +#define PIC_NUM_IRTS 160 + +#define PIC_IRT_WD_0_INDEX 0 +#define PIC_IRT_WD_1_INDEX 1 +#define PIC_IRT_WD_NMI_0_INDEX 2 +#define PIC_IRT_WD_NMI_1_INDEX 3 +#define PIC_IRT_TIMER_0_INDEX 4 +#define PIC_IRT_TIMER_1_INDEX 5 +#define PIC_IRT_TIMER_2_INDEX 6 +#define PIC_IRT_TIMER_3_INDEX 7 +#define PIC_IRT_TIMER_4_INDEX 8 +#define PIC_IRT_TIMER_5_INDEX 9 +#define PIC_IRT_TIMER_6_INDEX 10 +#define PIC_IRT_TIMER_7_INDEX 11 +#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX +#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX) + + +/* 11 and 12 */ +#define PIC_NUM_MSG_Q_IRTS 32 +#define PIC_IRT_MSG_Q0_INDEX 12 +#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX) +/* 12 to 43 */ +#define PIC_IRT_MSG_0_INDEX 44 +#define PIC_IRT_MSG_1_INDEX 45 +/* 44 and 45 */ +#define PIC_NUM_PCIE_MSIX_IRTS 32 +#define PIC_IRT_PCIE_MSIX_0_INDEX 46 +#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX) +/* 46 to 77 */ +#define PIC_NUM_PCIE_LINK_IRTS 4 +#define PIC_IRT_PCIE_LINK_0_INDEX 78 +#define PIC_IRT_PCIE_LINK_1_INDEX 79 +#define PIC_IRT_PCIE_LINK_2_INDEX 80 +#define PIC_IRT_PCIE_LINK_3_INDEX 81 +#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) +/* 78 to 81 */ +#define PIC_NUM_NA_IRTS 32 +/* 82 to 113 */ +#define PIC_IRT_NA_0_INDEX 82 +#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX) +#define PIC_IRT_POE_INDEX 114 + +#define PIC_NUM_USB_IRTS 6 +#define PIC_IRT_USB_0_INDEX 115 +#define PIC_IRT_EHCI_0_INDEX 115 +#define PIC_IRT_EHCI_1_INDEX 118 +#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX) +/* 115 to 120 */ +#define PIC_IRT_GDX_INDEX 121 +#define PIC_IRT_SEC_INDEX 122 +#define PIC_IRT_RSA_INDEX 123 + +#define PIC_NUM_COMP_IRTS 4 +#define PIC_IRT_COMP_0_INDEX 124 +#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX) +/* 124 to 127 */ +#define PIC_IRT_GBU_INDEX 128 +#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */ +#define PIC_IRT_ICC_1_INDEX 130 +#define PIC_IRT_ICC_2_INDEX 131 +#define PIC_IRT_CAM_INDEX 132 +#define PIC_IRT_UART_0_INDEX 133 +#define PIC_IRT_UART_1_INDEX 134 +#define PIC_IRT_I2C_0_INDEX 135 +#define PIC_IRT_I2C_1_INDEX 136 +#define PIC_IRT_SYS_0_INDEX 137 +#define PIC_IRT_SYS_1_INDEX 138 +#define PIC_IRT_JTAG_INDEX 139 +#define PIC_IRT_PIC_INDEX 140 +#define PIC_IRT_NBU_INDEX 141 +#define PIC_IRT_TCU_INDEX 142 +#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */ +#define PIC_IRT_DMC_0_INDEX 144 +#define PIC_IRT_DMC_1_INDEX 145 + +#define PIC_NUM_GPIO_IRTS 4 +#define PIC_IRT_GPIO_0_INDEX 146 +#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX) + +/* 146 to 149 */ +#define PIC_IRT_NOR_INDEX 150 +#define PIC_IRT_NAND_INDEX 151 +#define PIC_IRT_SPI_INDEX 152 +#define PIC_IRT_MMC_INDEX 153 + +#define PIC_CLOCK_TIMER 7 +#define PIC_IRQ_BASE 8 + +#if !defined(LOCORE) && !defined(__ASSEMBLY__) + +#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE) +#define PIC_IRT_LAST_IRQ 63 +#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ) + +/* + * Misc + */ +#define PIC_IRT_VALID 1 +#define PIC_LOCAL_SCHEDULING 1 +#define PIC_GLOBAL_SCHEDULING 0 + +#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) +#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) +#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) +#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) + +/* IRT and h/w interrupt routines */ +static inline int +nlm_pic_read_irt(uint64_t base, int irt_index) +{ + return nlm_read_pic_reg(base, PIC_IRT(irt_index)); +} + +static inline void +nlm_pic_send_ipi(uint64_t base, int cpu, int vec, int nmi) +{ + uint64_t ipi; + int node, ncpu; + + node = cpu / 32; + ncpu = cpu & 0x1f; + ipi = ((uint64_t)nmi << 31) | (vec << 20) | (node << 17) | + (1 << (cpu & 0xf)); + if (ncpu > 15) + ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */ + + nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); +} + +static inline uint64_t +nlm_pic_read_control(uint64_t base) +{ + return nlm_read_pic_reg(base, PIC_CTRL); +} + +static inline void +nlm_pic_write_control(uint64_t base, uint64_t control) +{ + nlm_write_pic_reg(base, PIC_CTRL, control); +} + +static inline void +nlm_pic_update_control(uint64_t base, uint64_t control) +{ + uint64_t val; + + val = nlm_read_pic_reg(base, PIC_CTRL); + nlm_write_pic_reg(base, PIC_CTRL, control | val); +} + +static inline void +nlm_pic_ack(uint64_t base, int irt_num) +{ + nlm_write_pic_reg(base, PIC_INT_ACK, irt_num); + + /* Ack the Status register for Watchdog & System timers */ + if (irt_num < 12) + nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num)); +} + +static inline void +nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) +{ + uint64_t val; + + val = nlm_read_pic_reg(base, PIC_IRT(irt)); + val |= cpu & 0xf; + if (cpu > 15) + val |= 1 << 16; + nlm_write_pic_reg(base, PIC_IRT(irt), val); +} + +static inline void +nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, + int sch, int vec, int dt, int db, int dte) +{ + uint64_t val; + + val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) | + ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) | + ((dt & 0x1) << 19) | ((db & 0x7) << 16) | + (dte & 0xffff); + + nlm_write_pic_reg(base, PIC_IRT(irt_num), val); +} + +static inline void +nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, + int sch, int vec, int cpu) +{ + nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, + (cpu >> 4), /* thread group */ + 1 << (cpu & 0xf)); /* thread mask */ +} + +static inline uint64_t +nlm_pic_read_timer(uint64_t base, int timer) +{ + return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); +} + +static inline void +nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) +{ + nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value); +} + +static inline void +nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) +{ + uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL); + int en; + + en = (irq > 0); + nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value); + nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer), + en, 0, 0, irq, cpu); + + /* enable the timer */ + pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); + nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl); +} + +#endif /* __ASSEMBLY__ */ +#endif /* _NLM_HAL_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h new file mode 100644 index 0000000..258e8cc --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h @@ -0,0 +1,128 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NLM_HAL_SYS_H__ +#define __NLM_HAL_SYS_H__ + +/** +* @file_name sys.h +* @author Netlogic Microsystems +* @brief HAL for System configuration registers +*/ +#define SYS_CHIP_RESET 0x00 +#define SYS_POWER_ON_RESET_CFG 0x01 +#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02 +#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03 +#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04 +#define SYS_EFUSE_DEVICE_CFG3 0x05 +#define SYS_EFUSE_DEVICE_CFG4 0x06 +#define SYS_EFUSE_DEVICE_CFG5 0x07 +#define SYS_EFUSE_DEVICE_CFG6 0x08 +#define SYS_EFUSE_DEVICE_CFG7 0x09 +#define SYS_PLL_CTRL 0x0a +#define SYS_CPU_RESET 0x0b +#define SYS_CPU_NONCOHERENT_MODE 0x0d +#define SYS_CORE_DFS_DIS_CTRL 0x0e +#define SYS_CORE_DFS_RST_CTRL 0x0f +#define SYS_CORE_DFS_BYP_CTRL 0x10 +#define SYS_CORE_DFS_PHA_CTRL 0x11 +#define SYS_CORE_DFS_DIV_INC_CTRL 0x12 +#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13 +#define SYS_CORE_DFS_DIV_VALUE 0x14 +#define SYS_RESET 0x15 +#define SYS_DFS_DIS_CTRL 0x16 +#define SYS_DFS_RST_CTRL 0x17 +#define SYS_DFS_BYP_CTRL 0x18 +#define SYS_DFS_DIV_INC_CTRL 0x19 +#define SYS_DFS_DIV_DEC_CTRL 0x1a +#define SYS_DFS_DIV_VALUE0 0x1b +#define SYS_DFS_DIV_VALUE1 0x1c +#define SYS_SENSE_AMP_DLY 0x1d +#define SYS_SOC_SENSE_AMP_DLY 0x1e +#define SYS_CTRL0 0x1f +#define SYS_CTRL1 0x20 +#define SYS_TIMEOUT_BS1 0x21 +#define SYS_BYTE_SWAP 0x22 +#define SYS_VRM_VID 0x23 +#define SYS_PWR_RAM_CMD 0x24 +#define SYS_PWR_RAM_ADDR 0x25 +#define SYS_PWR_RAM_DATA0 0x26 +#define SYS_PWR_RAM_DATA1 0x27 +#define SYS_PWR_RAM_DATA2 0x28 +#define SYS_PWR_UCODE 0x29 +#define SYS_CPU0_PWR_STATUS 0x2a +#define SYS_CPU1_PWR_STATUS 0x2b +#define SYS_CPU2_PWR_STATUS 0x2c +#define SYS_CPU3_PWR_STATUS 0x2d +#define SYS_CPU4_PWR_STATUS 0x2e +#define SYS_CPU5_PWR_STATUS 0x2f +#define SYS_CPU6_PWR_STATUS 0x30 +#define SYS_CPU7_PWR_STATUS 0x31 +#define SYS_STATUS 0x32 +#define SYS_INT_POL 0x33 +#define SYS_INT_TYPE 0x34 +#define SYS_INT_STATUS 0x35 +#define SYS_INT_MASK0 0x36 +#define SYS_INT_MASK1 0x37 +#define SYS_UCO_S_ECC 0x38 +#define SYS_UCO_M_ECC 0x39 +#define SYS_UCO_ADDR 0x3a +#define SYS_UCO_INSTR 0x3b +#define SYS_MEM_BIST0 0x3c +#define SYS_MEM_BIST1 0x3d +#define SYS_MEM_BIST2 0x3e +#define SYS_MEM_BIST3 0x3f +#define SYS_MEM_BIST4 0x40 +#define SYS_MEM_BIST5 0x41 +#define SYS_MEM_BIST6 0x42 +#define SYS_MEM_BIST7 0x43 +#define SYS_MEM_BIST8 0x44 +#define SYS_MEM_BIST9 0x45 +#define SYS_MEM_BIST10 0x46 +#define SYS_MEM_BIST11 0x47 +#define SYS_MEM_BIST12 0x48 +#define SYS_SCRTCH0 0x49 +#define SYS_SCRTCH1 0x4a +#define SYS_SCRTCH2 0x4b +#define SYS_SCRTCH3 0x4c + +#ifndef __ASSEMBLY__ + +#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) +#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) + +#endif +#endif diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h new file mode 100644 index 0000000..6a7046c --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h @@ -0,0 +1,191 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __XLP_HAL_UART_H__ +#define __XLP_HAL_UART_H__ + +/* UART Specific registers */ +#define UART_RX_DATA 0x00 +#define UART_TX_DATA 0x00 + +#define UART_INT_EN 0x01 +#define UART_INT_ID 0x02 +#define UART_FIFO_CTL 0x02 +#define UART_LINE_CTL 0x03 +#define UART_MODEM_CTL 0x04 +#define UART_LINE_STS 0x05 +#define UART_MODEM_STS 0x06 + +#define UART_DIVISOR0 0x00 +#define UART_DIVISOR1 0x01 + +#define BASE_BAUD (XLP_IO_CLK/16) +#define BAUD_DIVISOR(baud) (BASE_BAUD / baud) + +/* LCR mask values */ +#define LCR_5BITS 0x00 +#define LCR_6BITS 0x01 +#define LCR_7BITS 0x02 +#define LCR_8BITS 0x03 +#define LCR_STOPB 0x04 +#define LCR_PENAB 0x08 +#define LCR_PODD 0x00 +#define LCR_PEVEN 0x10 +#define LCR_PONE 0x20 +#define LCR_PZERO 0x30 +#define LCR_SBREAK 0x40 +#define LCR_EFR_ENABLE 0xbf +#define LCR_DLAB 0x80 + +/* MCR mask values */ +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_DRS 0x04 +#define MCR_IE 0x08 +#define MCR_LOOPBACK 0x10 + +/* FCR mask values */ +#define FCR_RCV_RST 0x02 +#define FCR_XMT_RST 0x04 +#define FCR_RX_LOW 0x00 +#define FCR_RX_MEDL 0x40 +#define FCR_RX_MEDH 0x80 +#define FCR_RX_HIGH 0xc0 + +/* IER mask values */ +#define IER_ERXRDY 0x1 +#define IER_ETXRDY 0x2 +#define IER_ERLS 0x4 +#define IER_EMSC 0x8 + +#if !defined(LOCORE) && !defined(__ASSEMBLY__) + +#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_get_uart_pcibase(node, inst) \ + nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst)) +#define nlm_get_uart_regbase(node, inst) \ + (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) + +static inline void +nlm_uart_set_baudrate(uint64_t base, int baud) +{ + uint32_t lcr; + + lcr = nlm_read_uart_reg(base, UART_LINE_CTL); + + /* enable divisor register, and write baud values */ + nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7)); + nlm_write_uart_reg(base, UART_DIVISOR0, + (BAUD_DIVISOR(baud) & 0xff)); + nlm_write_uart_reg(base, UART_DIVISOR1, + ((BAUD_DIVISOR(baud) >> 8) & 0xff)); + + /* restore default lcr */ + nlm_write_uart_reg(base, UART_LINE_CTL, lcr); +} + +static inline void +nlm_uart_outbyte(uint64_t base, char c) +{ + uint32_t lsr; + + for (;;) { + lsr = nlm_read_uart_reg(base, UART_LINE_STS); + if (lsr & 0x20) + break; + } + + nlm_write_uart_reg(base, UART_TX_DATA, (int)c); +} + +static inline char +nlm_uart_inbyte(uint64_t base) +{ + int data, lsr; + + for (;;) { + lsr = nlm_read_uart_reg(base, UART_LINE_STS); + if (lsr & 0x80) { /* parity/frame/break-error - push a zero */ + data = 0; + break; + } + if (lsr & 0x01) { /* Rx data */ + data = nlm_read_uart_reg(base, UART_RX_DATA); + break; + } + } + + return (char)data; +} + +static inline int +nlm_uart_init(uint64_t base, int baud, int databits, int stopbits, + int parity, int int_en, int loopback) +{ + uint32_t lcr; + + lcr = 0; + if (databits >= 8) + lcr |= LCR_8BITS; + else if (databits == 7) + lcr |= LCR_7BITS; + else if (databits == 6) + lcr |= LCR_6BITS; + else + lcr |= LCR_5BITS; + + if (stopbits > 1) + lcr |= LCR_STOPB; + + lcr |= parity << 3; + + /* setup default lcr */ + nlm_write_uart_reg(base, UART_LINE_CTL, lcr); + + /* Reset the FIFOs */ + nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST); + + nlm_uart_set_baudrate(base, baud); + + if (loopback) + nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f); + + if (int_en) + nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY); + + return 0; +} +#endif /* !LOCORE && !__ASSEMBLY__ */ +#endif /* __XLP_HAL_UART_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h new file mode 100644 index 0000000..5e44a0e --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -0,0 +1,71 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NLM_HAL_XLP_H +#define _NLM_HAL_XLP_H + +#define RESET_VEC_PHYS 0x1fc00000 +#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) +#define BOOT_THREAD_MODE 0 + +#define PIC_UART_0_IRQ 17 +#define PIC_UART_1_IRQ 18 + +#ifndef __ASSEMBLY__ +/* Platform UART functions */ +struct uart_port; +unsigned int nlm_xlr_uart_in(struct uart_port *, int); +void nlm_xlr_uart_out(struct uart_port *, int, int); + +/* SMP support functions */ +struct irq_desc; +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); +int nlm_wakeup_secondary_cpus(u32 wakeup_mask); +void nlm_smp_irq_init(void); +void nlm_boot_smp_nmi(void); +void prom_pre_boot_secondary_cpus(void); +void nlm_boot_core0_siblings(void); + +extern struct plat_smp_ops nlm_smp_ops; +extern unsigned long nlm_common_ebase; +extern char nlm_reset_entry[], nlm_reset_entry_end[]; + +void xlp_mmu_init(void); +void nlm_hal_init(void); +int nlm_irq_to_irt(int irq); +int nlm_irt_to_irq(int irt); + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASM_NLM_XLP_H */ diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile new file mode 100644 index 0000000..d1023e0 --- /dev/null +++ b/arch/mips/netlogic/xlp/Makefile @@ -0,0 +1,4 @@ +obj-y = setup.o platform.o irq.o setup.o time.o nlm_hal.o +obj-$(CONFIG_EARLY_PRINTK) += xlp_console.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/netlogic/xlp/irq.c b/arch/mips/netlogic/xlp/irq.c new file mode 100644 index 0000000..60096d5 --- /dev/null +++ b/arch/mips/netlogic/xlp/irq.c @@ -0,0 +1,240 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +/* + * These are the routines that handle all the low level interrupt stuff. + * Actions handled here are: initialization of the interrupt map, requesting of + * interrupt lines by handlers, dispatching if interrupts to handlers, probing + * for interrupt lines + */ + +/* Globals */ +static uint64_t nlm_xlp_irq_mask; +static DEFINE_SPINLOCK(nlm_common_pic_lock); + +static void xlp_pic_enable(struct irq_data *d) +{ + unsigned long flags; + uint64_t reg; + int irt, irq; + + irq = d->irq; + irt = nlm_irq_to_irt(irq); + if (irt == -1) + return; + + spin_lock_irqsave(&nlm_common_pic_lock, flags); + + reg = nlm_read_pic_reg(xlp_pic_base, PIC_IRT(irt)); + nlm_write_pic_reg(xlp_pic_base, PIC_IRT(irt), + reg | (1 << 28) | (1 << 31)); + + spin_unlock_irqrestore(&nlm_common_pic_lock, flags); +} + +static void xlp_pic_disable(struct irq_data *d) +{ + uint64_t reg; + unsigned long flags; + int irt, irq; + + irq = d->irq; + irt = nlm_irq_to_irt(irq); + if (irt == -1) + return; + + spin_lock_irqsave(&nlm_common_pic_lock, flags); + reg = nlm_read_pic_reg(xlp_pic_base, PIC_IRT(irt)); + nlm_write_pic_reg(xlp_pic_base, PIC_IRT(irt), (reg & ~(1 << 31))); + spin_unlock_irqrestore(&nlm_common_pic_lock, flags); +} + +static void xlp_pic_mask_ack(struct irq_data *d) +{ + uint64_t mask = 1ull << d->irq; + + write_c0_eirr(mask); /* ack by writing EIRR */ +} + +static void xlp_pic_unmask(struct irq_data *d) +{ + unsigned long flags; + int irt, irq; + + irq = d->irq; + irt = nlm_irq_to_irt(irq); + if (irt == -1) + return; + + /* If level triggered, ack it after the device condition is cleared */ + spin_lock_irqsave(&nlm_common_pic_lock, flags); + nlm_pic_ack(xlp_pic_base, irt); + spin_unlock_irqrestore(&nlm_common_pic_lock, flags); +} + +static struct irq_chip xlp_pic = { + .name = "XLP-PIC", + .irq_enable = xlp_pic_enable, + .irq_disable = xlp_pic_disable, + .irq_mask_ack = xlp_pic_mask_ack, + .irq_unmask = xlp_pic_unmask, +}; + +static void cpuintr_disable(struct irq_data *d) +{ + uint64_t eimr; + uint64_t mask = 1ull << d->irq; + + eimr = read_c0_eimr(); + write_c0_eimr(eimr & ~mask); +} + +static void cpuintr_enable(struct irq_data *d) +{ + uint64_t eimr; + uint64_t mask = 1ull << d->irq; + + eimr = read_c0_eimr(); + write_c0_eimr(eimr | mask); +} + +static void cpuintr_ack(struct irq_data *d) +{ + uint64_t mask = 1ull << d->irq; + + write_c0_eirr(mask); +} + +static void cpuintr_nop(struct irq_data *d) +{ + WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq); +} + +/* + * Chip definition for CPU originated interrupts(timer, msg) and + * IPIs + */ +struct irq_chip nlm_cpu_intr = { + .name = "XLP-CPU-INTR", + .irq_enable = cpuintr_enable, + .irq_disable = cpuintr_disable, + .irq_mask = cpuintr_nop, + .irq_ack = cpuintr_nop, + .irq_eoi = cpuintr_ack, +}; + +void __init init_nlm_common_irqs(void) +{ + int i, irq, irt; + + for (i = 0; i < PIC_IRT_FIRST_IRQ; i++) + irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq); + + for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++) + irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq); + +#ifdef CONFIG_SMP + irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr, + nlm_smp_function_ipi_handler); + irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr, + nlm_smp_resched_ipi_handler); + nlm_xlp_irq_mask |= + ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE)); +#endif + + for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) { + nlm_xlp_irq_mask |= (1ULL << irq); + irt = nlm_irq_to_irt(irq); + if (irt == -1) + continue; + nlm_pic_write_irt_direct(xlp_pic_base, irt, 1, 0, 0, irq, 1); + } + + nlm_xlp_irq_mask |= (1ULL << IRQ_TIMER); +} + +void __init arch_init_irq(void) +{ + /* Initialize the irq descriptors */ + init_nlm_common_irqs(); + + write_c0_eimr(nlm_xlp_irq_mask); +} + +void __cpuinit nlm_smp_irq_init(void) +{ + /* set interrupt mask for non-zero cpus */ + write_c0_eimr(nlm_xlp_irq_mask); +} + +asmlinkage void plat_irq_dispatch(void) +{ + uint64_t eirr; + int i; + + eirr = read_c0_eirr() & read_c0_eimr(); + if (eirr & (1 << IRQ_TIMER)) { + do_IRQ(IRQ_TIMER); + return; + } + + i = __ilog2_u64(eirr); + if (i == -1) + return; + + do_IRQ(i); +} diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c new file mode 100644 index 0000000..8130b60 --- /dev/null +++ b/arch/mips/netlogic/xlp/nlm_hal.c @@ -0,0 +1,85 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* These addresses are computed by the nlm_hal_init() */ +uint64_t xlp_io_base; +uint64_t xlp_sys_base; +uint64_t xlp_pic_base; + +/* Main initialization */ +void nlm_hal_init(void) +{ + xlp_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); + xlp_sys_base = nlm_get_sys_regbase(0); /* node 0 */ + xlp_pic_base = nlm_get_pic_regbase(0); /* node 0 */ +} + +int nlm_irq_to_irt(int irq) +{ + if (!PIC_IRQ_IS_IRT(irq)) + return -1; + + switch (irq) { + case PIC_UART_0_IRQ: + return PIC_IRT_UART_0_INDEX; + case PIC_UART_1_IRQ: + return PIC_IRT_UART_1_INDEX; + default: + return -1; + } +} + +int nlm_irt_to_irq(int irt) +{ + switch (irt) { + case PIC_IRT_UART_0_INDEX: + return PIC_UART_0_IRQ; + case PIC_IRT_UART_1_INDEX: + return PIC_UART_1_IRQ; + default: + return -1; + } +} diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c new file mode 100644 index 0000000..e2e90f6 --- /dev/null +++ b/arch/mips/netlogic/xlp/platform.c @@ -0,0 +1,108 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset) +{ + return nlm_read_reg(p->iobase, offset); +} + +void nlm_xlp_uart_out(struct uart_port *p, int offset, int value) +{ + nlm_write_reg(p->iobase, offset, value); +} + +#define PORT(_irq) \ + { \ + .irq = _irq, \ + .regshift = 2, \ + .iotype = UPIO_MEM32, \ + .flags = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\ + UPF_BOOT_AUTOCONF), \ + .uartclk = XLP_IO_CLK, \ + .type = PORT_16550A, \ + .serial_in = nlm_xlp_uart_in, \ + .serial_out = nlm_xlp_uart_out, \ + } + +static struct plat_serial8250_port xlp_uart_data[] = { + PORT(PIC_UART_0_IRQ), + PORT(PIC_UART_1_IRQ), + {}, +}; + +static struct platform_device uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = xlp_uart_data, + }, +}; + +static int __init nlm_platform_uart_init(void) +{ + unsigned long mmio; + + mmio = (unsigned long)nlm_get_uart_regbase(0, 0); + xlp_uart_data[0].iobase = mmio; + xlp_uart_data[0].membase = (void __iomem *)mmio; + xlp_uart_data[0].mapbase = mmio; + + mmio = (unsigned long)nlm_get_uart_regbase(0, 1); + xlp_uart_data[1].iobase = mmio; + xlp_uart_data[1].membase = (void __iomem *)mmio; + xlp_uart_data[1].mapbase = mmio; + + return platform_device_register(&uart_device); +} + +arch_initcall(nlm_platform_uart_init); diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c new file mode 100644 index 0000000..ecaced7 --- /dev/null +++ b/arch/mips/netlogic/xlp/setup.c @@ -0,0 +1,98 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +unsigned long nlm_common_ebase = 0x0; + +static void nlm_linux_exit(void) +{ + nlm_write_sys_reg(xlp_sys_base, SYS_CHIP_RESET, 1); + for ( ; ; ) + cpu_wait(); +} + +void __init plat_mem_setup(void) +{ + panic_timeout = 5; + _machine_restart = (void (*)(char *))nlm_linux_exit; + _machine_halt = nlm_linux_exit; + pm_power_off = nlm_linux_exit; +} + +const char *get_system_type(void) +{ + return "Netlogic XLP Series"; +} + +void __init prom_free_prom_memory(void) +{ + /* Nothing yet */ +} + +void xlp_mmu_init(void) +{ + write_c0_config6(read_c0_config6() | 0x24); + current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; + write_c0_config7(PM_DEFAULT_MASK >> + (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); +} + +void __init prom_init(void) +{ + void *fdtp; + + fdtp = (void *)(long)fw_arg0; + xlp_mmu_init(); + nlm_hal_init(); + early_init_devtree(fdtp); + + nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); +#ifdef CONFIG_SMP + nlm_wakeup_secondary_cpus(0xffffffff); + register_smp_ops(&nlm_smp_ops); +#endif +} diff --git a/arch/mips/netlogic/xlp/smp.c b/arch/mips/netlogic/xlp/smp.c new file mode 100644 index 0000000..5fe02c5 --- /dev/null +++ b/arch/mips/netlogic/xlp/smp.c @@ -0,0 +1,285 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include + +void nlm_send_ipi_single(int logical_cpu, unsigned int action) +{ + int cpu = cpu_logical_map(logical_cpu); + int ipi; + + if (action & SMP_CALL_FUNCTION) + ipi = IRQ_IPI_SMP_FUNCTION; + else if (action & SMP_RESCHEDULE_YOURSELF) + ipi = IRQ_IPI_SMP_RESCHEDULE; + else + return; + + nlm_pic_send_ipi(xlp_pic_base, cpu, ipi, 0); +} + +void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + int cpu; + + for_each_cpu(cpu, mask) { + nlm_send_ipi_single(cpu, action); + } +} + +/* IRQ_IPI_SMP_FUNCTION Handler */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + smp_call_function_interrupt(); + write_c0_eirr(1ull << irq); +} + +/* IRQ_IPI_SMP_RESCHEDULE handler */ +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + scheduler_ipi(); + write_c0_eirr(1ull << irq); +} + +/* + * Called before going into mips code, early cpu init + */ +void nlm_early_init_secondary(int cpu) +{ + write_c0_ebase((uint32_t)nlm_common_ebase); + if (cpu % 4 == 0) + xlp_mmu_init(); +} + +/* + * Code to run on secondary just after probing the CPU + */ +static void __cpuinit nlm_init_secondary(void) +{ + nlm_smp_irq_init(); +} + +void nlm_smp_finish(void) +{ +#ifdef notyet + nlm_common_msgring_cpu_init(); +#endif + local_irq_enable(); +} + +void nlm_cpus_done(void) +{ +} + +/* + * Boot all other cpus in the system, initialize them, and bring them into + * the boot function + */ +int nlm_cpu_unblock[NR_CPUS]; +int nlm_cpu_ready[NR_CPUS]; +unsigned long nlm_next_gp; +unsigned long nlm_next_sp; +cpumask_t phys_cpu_present_map; + +void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) +{ + unsigned long gp = (unsigned long)task_thread_info(idle); + unsigned long sp = (unsigned long)__KSTK_TOS(idle); + int cpu = cpu_logical_map(logical_cpu); + + nlm_next_sp = sp; + nlm_next_gp = gp; + + /* barrier */ + __sync(); + nlm_cpu_unblock[cpu] = 1; +} + +void __init nlm_smp_setup(void) +{ + unsigned int boot_cpu; + int num_cpus, i; + + boot_cpu = hard_smp_processor_id(); + cpus_clear(phys_cpu_present_map); + + cpu_set(boot_cpu, phys_cpu_present_map); + __cpu_number_map[boot_cpu] = 0; + __cpu_logical_map[0] = boot_cpu; + cpu_set(0, cpu_possible_map); + + num_cpus = 1; + for (i = 0; i < NR_CPUS; i++) { + if (nlm_cpu_ready[i]) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = num_cpus; + __cpu_logical_map[num_cpus] = i; + cpu_set(num_cpus, cpu_possible_map); + ++num_cpus; + } + } + + pr_info("Phys CPU present map: %lx, possible map %lx\n", + (unsigned long)phys_cpu_present_map.bits[0], + (unsigned long)cpu_possible_map.bits[0]); + + pr_info("Detected %i Slave CPU(s)\n", num_cpus); +} + +void nlm_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops nlm_smp_ops = { + .send_ipi_single = nlm_send_ipi_single, + .send_ipi_mask = nlm_send_ipi_mask, + .init_secondary = nlm_init_secondary, + .smp_finish = nlm_smp_finish, + .cpus_done = nlm_cpus_done, + .boot_secondary = nlm_boot_secondary, + .smp_setup = nlm_smp_setup, + .prepare_cpus = nlm_prepare_cpus, +}; + +unsigned long secondary_entry; +uint32_t nlm_coremask; +unsigned int nlm_threads_per_core; +unsigned int nlm_threadmode; + +static void nlm_enable_secondary_cores(unsigned int cores_bitmap) +{ + uint32_t core, value, coremask; + + for (core = 1; core < 8; core++) { + coremask = 1 << core; + if ((cores_bitmap & coremask) == 0) + continue; + + /* Enable CPU clock */ + value = nlm_read_sys_reg(xlp_sys_base, SYS_CORE_DFS_DIS_CTRL); + value &= ~coremask; + nlm_write_sys_reg(xlp_sys_base, SYS_CORE_DFS_DIS_CTRL, value); + + /* Remove CPU Reset */ + value = nlm_read_sys_reg(xlp_sys_base, SYS_CPU_RESET); + value &= ~coremask; + nlm_write_sys_reg(xlp_sys_base, SYS_CPU_RESET, value); + + /* Poll for CPU to mark itself coherent */ + do { + value = nlm_read_sys_reg(xlp_sys_base, + SYS_CPU_NONCOHERENT_MODE); + } while ((value & coremask) != 0); + } +} + + +static void nlm_parse_cpumask(u32 cpu_mask) +{ + uint32_t core0_thr_mask, core_thr_mask; + int i; + + core0_thr_mask = cpu_mask & 0xf; + switch (core0_thr_mask) { + case 1: + nlm_threads_per_core = 1; + nlm_threadmode = 0; + break; + case 3: + nlm_threads_per_core = 2; + nlm_threadmode = 2; + break; + case 0xf: + nlm_threads_per_core = 4; + nlm_threadmode = 3; + break; + default: + goto unsupp; + } + + /* Verify other cores CPU masks */ + nlm_coremask = 1; + for (i = 1; i < 8; i++) { + core_thr_mask = (cpu_mask >> (i * 4)) & 0xf; + if (core_thr_mask) { + if (core_thr_mask != core0_thr_mask) + goto unsupp; + nlm_coremask |= 1 << i; + } + } + return; + +unsupp: + panic("Unsupported CPU mask %x\n", cpu_mask); +} + +int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask) +{ + unsigned long reset_vec; + unsigned int *reset_data; + + /* Update reset entry point with CPU init code */ + reset_vec = CKSEG1ADDR(RESET_VEC_PHYS); + memcpy((void *)reset_vec, (void *)nlm_reset_entry, + (nlm_reset_entry_end - nlm_reset_entry)); + + /* verify the mask and setup core config variables */ + nlm_parse_cpumask(wakeup_mask); + + /* Setup CPU init parameters */ + reset_data = (unsigned int *)CKSEG1ADDR(RESET_DATA_PHYS); + reset_data[BOOT_THREAD_MODE] = nlm_threadmode; + + /* first wakeup core 0 siblings */ + nlm_boot_core0_siblings(); + + /* enable the reset of the cores */ + nlm_enable_secondary_cores(nlm_coremask); + return 0; +} diff --git a/arch/mips/netlogic/xlp/smpboot.S b/arch/mips/netlogic/xlp/smpboot.S new file mode 100644 index 0000000..7dd3232 --- /dev/null +++ b/arch/mips/netlogic/xlp/smpboot.S @@ -0,0 +1,217 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define CP0_EBASE $15 +#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ + XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ + SYS_CPU_NONCOHERENT_MODE * 4 + +.macro __config_lsu + li t0, LSU_DEFEATURE + mfcr t1, t0 + + lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */ + or t1, t1, t2 + li t2, ~0xe /* S1RCM */ + and t1, t1, t2 + mtcr t1, t0 + + li t0, SCHED_DEFEATURE + lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */ + mtcr t1, t0 +.endm + + .set noreorder + .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ + + __CPUINIT +EXPORT(nlm_reset_entry) + mfc0 t0, CP0_EBASE, 1 + mfc0 t1, CP0_EBASE, 1 + srl t1, 5 + andi t1, 0x3 /* t1 <- node */ + li t2, 0x40000 + mul t3, t2, t1 /* t3 = node * 0x40000 */ + srl t0, t0, 2 + and t0, t0, 0x7 /* t0 <- core */ + li t1, 0x1 + sll t0, t1, t0 + nor t0, t0, zero /* t0 <- ~(1 << core) */ + li t2, SYS_CPU_COHERENT_BASE(0) + add t2, t2, t3 /* t2 <- SYS offset for node */ + lw t1, 0(t2) + and t1, t1, t0 + sw t1, 0(t2) + + /* read back to ensure complete */ + lw t1, 0(t2) + sync + + /* Configure LSU on Non-0 Cores. */ + __config_lsu + +/* + * Wake up sibling threads from the initial thread in + * a core. + */ +EXPORT(nlm_boot_siblings) + li t0, CKSEG1ADDR(RESET_DATA_PHYS) + lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ + li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) + mfcr t2, t0 + or t2, t2, t1 + mtcr t2, t0 + + /* + * The new hardware thread starts at the next instruction + * For all the cases other than core 0 thread 0, we will + * jump to the secondary wait function. + */ + mfc0 v0, CP0_EBASE, 1 + andi v0, 0x7f /* v0 <- node/core */ + +#if 1 + /* A0 errata - Write MMU_SETUP after changing thread mode register. */ + andi v1, v0, 0x3 /* v1 <- thread id */ + bnez v1, 2f + nop + + li t0, MMU_SETUP + li t1, 0 + mtcr t1, t0 + ehb +#endif + +2: beqz v0, 3f + nop + + /* setup status reg */ + mfc0 t1, CP0_STATUS + li t0, ST0_BEV + or t1, t0 + xor t1, t0 +#ifdef CONFIG_64BIT + ori t1, ST0_KX +#endif + mtc0 t1, CP0_STATUS + + /* SETUP TLBs for a mapped kernel here */ + PTR_LA t0, prom_pre_boot_secondary_cpus + jalr t0 + nop + + /* + * For the boot CPU, we have to restore registers and + * return + */ +3: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ + li t1, 0xfadebeef + dmtc0 t1, $4, 2 /* restore SP from UserLocal */ + PTR_SUBU sp, t0, PT_SIZE + RESTORE_ALL + jr ra + nop +EXPORT(nlm_reset_entry_end) + +EXPORT(nlm_boot_core0_siblings) /* "Master" (n0c0t0) cpu starts from here */ + __config_lsu + dmtc0 sp, $4, 2 /* SP saved in UserLocal */ + SAVE_ALL + sync + /* find the location to which nlm_boot_siblings was relocated */ + li t0, CKSEG1ADDR(RESET_VEC_PHYS) + dla t1, nlm_reset_entry + dla t2, nlm_boot_siblings + dsubu t2, t1 + daddu t2, t0 + /* call it */ + jr t2 + nop + __FINIT + + __CPUINIT +NESTED(prom_pre_boot_secondary_cpus, 16, sp) + .set mips64 + mfc0 a0, CP0_EBASE, 1 /* read ebase */ + andi a0, 0x3ff /* a0 has the processor_id() */ + sll t0, a0, 2 /* offset in cpu array */ + + PTR_LA t1, nlm_cpu_ready /* mark CPU ready */ + PTR_ADDU t1, t0 + li t2, 1 + sw t2, 0(t1) + + PTR_LA t1, nlm_cpu_unblock + PTR_ADDU t1, t0 +1: lw t2, 0(t1) /* wait till unblocked */ + bnez t2, 2f + nop + nop + nop + nop + nop + nop + j 1b + nop + +2: PTR_LA t1, nlm_next_sp + PTR_L sp, 0(t1) + PTR_LA t1, nlm_next_gp + PTR_L gp, 0(t1) + + /* a0 has the processor id */ + PTR_LA t0, nlm_early_init_secondary + jalr t0 + nop + + PTR_LA t0, smp_bootstrap + jr t0 + nop +END(prom_pre_boot_secondary_cpus) + __FINIT diff --git a/arch/mips/netlogic/xlp/time.c b/arch/mips/netlogic/xlp/time.c new file mode 100644 index 0000000..1ccae37 --- /dev/null +++ b/arch/mips/netlogic/xlp/time.c @@ -0,0 +1,74 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return IRQ_TIMER; +} + +static unsigned int xlp_get_cpu_frequency(void) +{ + unsigned int pll_divf, pll_divr, dfs_div, denom; + unsigned int val; + uint64_t num; + + val = nlm_read_sys_reg(xlp_sys_base, SYS_POWER_ON_RESET_CFG); + pll_divf = (val >> 10) & 0x7f; + pll_divr = (val >> 8) & 0x3; + dfs_div = (val >> 17) & 0x3; + + num = pll_divf + 1; + denom = 3 * (pll_divr + 1) * (1 << (dfs_div + 1)); + num = num * 800000000ULL; + do_div(num, denom); + return (unsigned int)num; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = xlp_get_cpu_frequency(); + pr_info("MIPS counter frequency [%ld]\n", + (unsigned long)mips_hpt_frequency); +} diff --git a/arch/mips/netlogic/xlp/xlp_console.c b/arch/mips/netlogic/xlp/xlp_console.c new file mode 100644 index 0000000..cff97f1 --- /dev/null +++ b/arch/mips/netlogic/xlp/xlp_console.c @@ -0,0 +1,50 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +void prom_putchar(char c) +{ + uint64_t mmio; + + mmio = nlm_get_uart_regbase(0, 0); + while (nlm_read_uart_reg(mmio, UART_LINE_STS) == 0) + ; + nlm_write_reg(mmio, UART_TX_DATA, c); +} -- 1.7.4.1 From jayachandranc@netlogicmicro.com Sun Sep 4 20:06:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 04 Sep 2011 20:06:39 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:1606 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491179Ab1IDSGb (ORCPT ); Sun, 4 Sep 2011 20:06:31 +0200 X-TM-IMSS-Message-ID: <9ba7a3cf0002dbaa@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 9ba7a3cf0002dbaa ; Sun, 4 Sep 2011 11:04:24 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 4 Sep 2011 11:07:45 -0700 Date: Sun, 4 Sep 2011 23:42:30 +0530 From: Jayachandran C To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 3/4] MIPS: Netlogic: Build support for netlogic XLP Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 04 Sep 2011 18:07:45.0513 (UTC) FILETIME=[8C1A3590:01CC6B2D] X-archive-position: 31040 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2162 Content-Length: 5294 Lines: 165 Kconfig and makefile updates Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 44 +++++++++++++++++++++++++++++++++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/netlogic/Kconfig | 3 ++ arch/mips/netlogic/Platform | 7 ++++++ arch/mips/netlogic/xlp/Makefile | 5 ++- 7 files changed, 60 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2bb1c85..c8a89bf 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -788,6 +788,34 @@ config NLM_XLR_BOARD Support for systems based on Netlogic XLR and XLS processors. Say Y here if you have a XLR or XLS based board. +config NLM_XLP_BOARD + bool "Netlogic XLP based systems" + depends on EXPERIMENTAL + select BOOT_ELF32 + select NLM_COMMON + select NLM_XLP + select SYS_HAS_CPU_XLP + select SYS_SUPPORTS_SMP + select HW_HAS_PCI + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select 64BIT_PHYS_ADDR + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select DMA_COHERENT + select NR_CPUS_DEFAULT_32 + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select ZONE_DMA if 64BIT + select SYNC_R4K + select SYS_HAS_EARLY_PRINTK + help + This board is based on Netlogic XLP Processor. + Say Y here if you have a XLP based board. + endchoice source "arch/mips/alchemy/Kconfig" @@ -1480,6 +1508,19 @@ config CPU_XLR select CPU_SUPPORTS_HUGEPAGES help Netlogic Microsystems XLR/XLS processors. + +config CPU_XLP + bool "Netlogic XLP SoC" + depends on SYS_HAS_CPU_XLP + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select CPU_HAS_LLSC + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select CPU_HAS_PREFETCH + help + Netlogic Microsystems XLP processors. endchoice if CPU_LOONGSON2F @@ -1613,6 +1654,9 @@ config SYS_HAS_CPU_BMIPS5000 config SYS_HAS_CPU_XLR bool +config SYS_HAS_CPU_XLP + bool + # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 83bba33..ab31b00 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_XLP) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index b2cad4f..2a7c74f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o obj-$(CONFIG_CPU_XLR) += dump_tlb.o +obj-$(CONFIG_CPU_XLP) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 4d8c162..59b0905 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o +obj-$(CONFIG_CPU_XLP) += c-r4k.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig index a5ca743..464d4b2 100644 --- a/arch/mips/netlogic/Kconfig +++ b/arch/mips/netlogic/Kconfig @@ -3,3 +3,6 @@ config NLM_COMMON config NLM_XLR bool + +config NLM_XLP + bool diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform index 502d912..9853153 100644 --- a/arch/mips/netlogic/Platform +++ b/arch/mips/netlogic/Platform @@ -8,9 +8,16 @@ cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic # use mips64 if xlr is not available # cflags-$(CONFIG_NLM_XLR) += $(call cc-option,-march=xlr,-march=mips64) +cflags-$(CONFIG_NLM_XLP) += $(call cc-option,-march=xlp,-march=mips64r2) # # NETLOGIC XLR/XLS SoC, Simulator and boards # core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff80100000 + +# +# NETLOGIC XLP SoC, Simulator and boards +# +core-$(CONFIG_NLM_XLP) += arch/mips/netlogic/xlp/ +load-$(CONFIG_NLM_XLP_BOARD) += 0xffffffff80100000 diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile index d1023e0..aea1918 100644 --- a/arch/mips/netlogic/xlp/Makefile +++ b/arch/mips/netlogic/xlp/Makefile @@ -1,4 +1,5 @@ -obj-y = setup.o platform.o irq.o setup.o time.o nlm_hal.o -obj-$(CONFIG_EARLY_PRINTK) += xlp_console.o +obj-y += setup.o platform.o irq.o setup.o time.o nlm_hal.o +obj-$(CONFIG_SMP) += smp.o smpboot.o +obj-$(CONFIG_EARLY_PRINTK) += xlp_console.o EXTRA_CFLAGS += -Werror -- 1.7.4.1 From jayachandranc@netlogicmicro.com Sun Sep 4 20:07:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 04 Sep 2011 20:07:42 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:1846 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491066Ab1IDSHd (ORCPT ); Sun, 4 Sep 2011 20:07:33 +0200 X-TM-IMSS-Message-ID: <9ba88f090002dbab@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 9ba88f090002dbab ; Sun, 4 Sep 2011 11:05:24 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 4 Sep 2011 11:08:18 -0700 Date: Sun, 4 Sep 2011 23:43:03 +0530 From: Jayachandran C To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 4/4] MIPS: Netlogic: Add default XLP config. Message-ID: <47b2b2b08d10adea0e8b780d4b2653162cf141ef.1315075195.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 04 Sep 2011 18:08:18.0685 (UTC) FILETIME=[9FDFDAD0:01CC6B2D] X-archive-position: 31042 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2163 Content-Length: 15220 Lines: 605 Signed-off-by: Jayachandran C --- arch/mips/configs/nlm_xlp_defconfig | 590 +++++++++++++++++++++++++++++++++++ 1 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlp_defconfig diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig new file mode 100644 index 0000000..35fd371 --- /dev/null +++ b/arch/mips/configs/nlm_xlp_defconfig @@ -0,0 +1,590 @@ +CONFIG_NLM_XLP_BOARD=y +CONFIG_64BIT=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_SMP=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_SECCOMP is not set +CONFIG_USE_OF=y +CONFIG_EXPERIMENTAL=y +CONFIG_CROSS_COMPILE="mips-linux-gnu-" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_CGROUPS=y +CONFIG_NAMESPACES=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlp" +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_INITRAMFS_COMPRESSION_LZMA=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_MISC=y +CONFIG_MIPS32_COMPAT=y +CONFIG_MIPS32_O32=y +CONFIG_MIPS32_N32=y +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_NET_IPIP=m +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETLABEL=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_TIPC=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_DECNET=m +CONFIG_LLC2=m +CONFIG_IPX=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +CONFIG_PHONET=m +CONFIG_IEEE802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_DCB=y +CONFIG_NET_PKTGEN=m +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_CONNECTOR=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_OSD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_CDROM_PKTCDVD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_TGT=m +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_TGT_ATTRS=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_LIBFCOE=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_N_HDLC=m +# CONFIG_DEVKMEM is not set +CONFIG_STALDRV=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_RAW_DRIVER=m +CONFIG_W1=y +# CONFIG_W1_CON is not set +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2760=m +CONFIG_W1_SLAVE_BQ27000=m +# CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_CACHEFILES=m +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ADFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EXOFS_FS=m +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +CONFIG_ACORN_PARTITION_ICS=y +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_PRINTK_TIME=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KGDB=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_TOMOYO=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRC_CCITT=m +CONFIG_CRC7=m -- 1.7.4.1 From saurabh140585@gmail.com Mon Sep 5 12:23:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Sep 2011 12:24:00 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:47425 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491784Ab1IEKXy convert rfc822-to-8bit (ORCPT ); Mon, 5 Sep 2011 12:23:54 +0200 Received: by fxd20 with SMTP id 20so4218300fxd.36 for ; Mon, 05 Sep 2011 03:23:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type :content-transfer-encoding; bh=lTrtfBuVIBz7ZqZdU+z2gRggaaXca1k4sC9927p/Hac=; b=C0p/a6MycIok5dMXSU3ddpJTtHN86j4++uT/cT3ZVY/CCG1N5atZyLZHZblW4Bl/0z 685yiubF+Xu9xp7DPHOSjJndLeWQ3ZL1fnm10g/c7YylUClR30bOmBBaA3bHneeMD8Ql oMCABK4onO2fRbqP6zzJoIYgv1kZe4/DfJ6Bg= MIME-Version: 1.0 Received: by 10.223.33.19 with SMTP id f19mr4453334fad.122.1315218228797; Mon, 05 Sep 2011 03:23:48 -0700 (PDT) Received: by 10.223.83.203 with HTTP; Mon, 5 Sep 2011 03:23:48 -0700 (PDT) Date: Mon, 5 Sep 2011 15:53:48 +0530 Message-ID: Subject: MIPS: Octeon: mailbox_interrupt is not registered as per cpu From: SAURABH MALPANI To: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 31043 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: saurabh140585@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2369 Content-Length: 955 Lines: 27 Hi, Query: mailbox_interrupt is not registered with IRQF_PERCPU but it is supposed to be percpu interrupt. Is that on purpose or a miss? I am porting some code from x86 to octeon which requires special handling for per cpu interrupts. void octeon_prepare_cpus(unsigned int max_cpus) {         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);         if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,                         "mailbox0", mailbox_interrupt)) {                 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");         }         if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,                         "mailbox1", mailbox_interrupt)) {                 panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");         } } -- Saurabh From yi.zou@intel.com Tue Sep 6 05:26:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Sep 2011 05:26:09 +0200 (CEST) Received: from mga09.intel.com ([134.134.136.24]:11191 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491067Ab1IFD0A (ORCPT ); Tue, 6 Sep 2011 05:26:00 +0200 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 05 Sep 2011 20:25:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.67,352,1309762800"; d="scan'208";a="45518266" Received: from orsmsx602.amr.corp.intel.com ([10.22.226.211]) by orsmga001.jf.intel.com with ESMTP; 05 Sep 2011 20:25:51 -0700 Received: from orsmsx601.amr.corp.intel.com (10.22.226.213) by orsmsx602.amr.corp.intel.com (10.22.226.211) with Microsoft SMTP Server (TLS) id 8.2.255.0; Mon, 5 Sep 2011 20:25:51 -0700 Received: from orsmsx509.amr.corp.intel.com ([10.22.226.43]) by orsmsx601.amr.corp.intel.com ([10.22.226.213]) with mapi; Mon, 5 Sep 2011 20:25:51 -0700 From: "Zou, Yi" To: Ben Hutchings , Jiri Pirko CC: "netdev@vger.kernel.org" , "ralf@linux-mips.org" , "fubar@us.ibm.com" , "andy@greyhouse.net" , "kaber@trash.net" , "bprakash@broadcom.com" , "JBottomley@parallels.com" , "Love, Robert W" , "davem@davemloft.net" , "shemminger@linux-foundation.org" , "decot@google.com" , "mirq-linux@rere.qmqm.pl" , "Duyck, Alexander H" , "amit.salecha@qlogic.com" , "eric.dumazet@gmail.com" , "therbert@google.com" , "paulmck@linux.vnet.ibm.com" , "laijs@cn.fujitsu.com" , "xiaosuo@gmail.com" , "greearb@candelatech.com" , "loke.chetan@gmail.com" , "linux-mips@linux-mips.org" , "linux-scsi@vger.kernel.org" , "devel@open-fcoe.org" , "bridge@lists.linux-foundation.org" Date: Mon, 5 Sep 2011 20:25:39 -0700 Subject: RE: [patch net-next-2.6 v3] net: consolidate and fix ethtool_ops->get_settings calling Thread-Topic: [patch net-next-2.6 v3] net: consolidate and fix ethtool_ops->get_settings calling Thread-Index: AcxqP/jbBlcrHR8fSM6B1+PO8DGrZQB31Uyw Message-ID: <5A9BD224CEA58D4CB62235967D650C160A1B7D1C@orsmsx509.amr.corp.intel.com> References: <1314905304-16485-1-git-send-email-jpirko@redhat.com> <20110902122630.GC1991@minipsycho> <1314989161.3419.5.camel@bwh-desktop> <20110903133428.GA2821@minipsycho> <1315057614.3092.160.camel@deadeye> In-Reply-To: <1315057614.3092.160.camel@deadeye> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 X-archive-position: 31044 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yi.zou@intel.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2834 Content-Length: 2059 Lines: 27 PiANCj4gT24gU2F0LCAyMDExLTA5LTAzIGF0IDE1OjM0ICswMjAwLCBKaXJpIFBpcmtvIHdyb3Rl Og0KPiA+IFRoaXMgcGF0Y2ggZG9lcyBzZXZlcmFsIHRoaW5nczoNCj4gPiAtIGludHJvZHVjZXMg X19ldGh0b29sX2dldF9zZXR0aW5ncyB3aGljaCBpcyBjYWxsZWQgZnJvbSBldGh0b29sIGNvZGUN Cj4gYW5kDQo+ID4gICBmcm9tIGRyaXZlcnMgYXMgd2VsbC4gUHV0IEFTU0VSVF9SVE5MIHRoZXJl Lg0KPiA+IC0gZGV2X2V0aHRvb2xfZ2V0X3NldHRpbmdzKCkgaXMgcmVwbGFjZWQgYnkgX19ldGh0 b29sX2dldF9zZXR0aW5ncygpDQo+ID4gLSBjaGFuZ2VzIGNhbGxpbmcgaW4gZHJpdmVycyBzbyBy dG5sIGxvY2tpbmcgaXMgcmVzcGVjdGVkLiBJbg0KPiA+ICAgaWJvZV9nZXRfcmF0ZSB3YXMgcHJl dmlvdXNseSAtPmdldF9zZXR0aW5ncygpIGNhbGxlZCB1bmxvY2tlZC4gVGhpcw0KPiA+ICAgZml4 ZXMgaXQuIEFsc28gcHJiX2NhbGNfcmV0aXJlX2Jsa190bW8oKSBpbiBhZl9wYWNrZXQuYyBoYWQg dGhlIHNhbWUNCj4gPiAgIHByb2JsZW0uIEFsc28gZml4ZWQgYnkgY2FsbGluZyBfX2Rldl9nZXRf YnlfaW5kZXgoKSBpbnN0ZWFkIG9mDQo+ID4gICBkZXZfZ2V0X2J5X2luZGV4KCkgYW5kIGhvbGRp bmcgcnRubF9sb2NrIGZvciBib3RoIGNhbGxzLg0KPiA+IC0gaW50cm9kdWNlcyBydG5sX2xvY2sg aW4gYm54MmZjX3Zwb3J0X2NyZWF0ZSgpIGFuZCBmY29lX3Zwb3J0X2NyZWF0ZSgpDQo+ID4gICBz byBibngyZmNfaWZfY3JlYXRlKCkgYW5kIGZjb2VfaWZfY3JlYXRlKCkgYXJlIGNhbGxlZCBsb2Nr ZWQgYXMgdGhleQ0KPiA+ICAgYXJlIGZyb20gb3RoZXIgcGxhY2VzLg0KPiA+IC0gdXNlIF9fZXRo dG9vbF9nZXRfc2V0dGluZ3MoKSBpbiBib25kaW5nIGNvZGUNCj4gPg0KPiA+IFNpZ25lZC1vZmYt Ynk6IEppcmkgUGlya28gPGpwaXJrb0ByZWRoYXQuY29tPg0KPiBSZXZpZXdlZC1ieTogQmVuIEh1 dGNoaW5ncyA8Ymh1dGNoaW5nc0Bzb2xhcmZsYXJlLmNvbT4gW2V4Y2VwdCBGQ29FIGJpdHNdDQo+ IA0KPiBCZW4uDQpGQ29FIGJpdHMgbG9vayBvayB0byBtZS4gVGhhbmtzLA0KDQpSZXZpZXdlZC1i eTogWWkgWm91IDx5aS56b3VAaW50ZWwuY29tPg0KDQo+IA0KPiAtLQ0KPiBCZW4gSHV0Y2hpbmdz LCBTdGFmZiBFbmdpbmVlciwgU29sYXJmbGFyZQ0KPiBOb3Qgc3BlYWtpbmcgZm9yIG15IGVtcGxv eWVyOyB0aGF0J3MgdGhlIG1hcmtldGluZyBkZXBhcnRtZW50J3Mgam9iLg0KPiBUaGV5IGFza2Vk IHVzIHRvIG5vdGUgdGhhdCBTb2xhcmZsYXJlIHByb2R1Y3QgbmFtZXMgYXJlIHRyYWRlbWFya2Vk Lg0KPiANCj4gLS0NCj4gVG8gdW5zdWJzY3JpYmUgZnJvbSB0aGlzIGxpc3Q6IHNlbmQgdGhlIGxp bmUgInVuc3Vic2NyaWJlIGxpbnV4LXNjc2kiIGluDQo+IHRoZSBib2R5IG9mIGEgbWVzc2FnZSB0 byBtYWpvcmRvbW9Admdlci5rZXJuZWwub3JnDQo+IE1vcmUgbWFqb3Jkb21vIGluZm8gYXQgIGh0 dHA6Ly92Z2VyLmtlcm5lbC5vcmcvbWFqb3Jkb21vLWluZm8uaHRtbA0K From bprakash@broadcom.com Tue Sep 6 08:52:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Sep 2011 08:52:49 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:1450 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491067Ab1IFGwl (ORCPT ); Tue, 6 Sep 2011 08:52:41 +0200 Received: from [10.9.200.131] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Mon, 05 Sep 2011 23:58:00 -0700 X-Server-Uuid: B55A25B1-5D7D-41F8-BC53-C57E7AD3C201 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Mon, 5 Sep 2011 23:52:22 -0700 Received: from [10.240.250.183] (unknown [10.240.250.183]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 4904874D03; Mon, 5 Sep 2011 23:52:21 -0700 (PDT) Message-ID: <4E65C326.3010506@broadcom.com> Date: Mon, 5 Sep 2011 23:52:22 -0700 From: "Bhanu Prakash Gollapudi" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.20) Gecko/20110804 Thunderbird/3.1.12 MIME-Version: 1.0 To: "Zou, Yi" cc: "Ben Hutchings" , "Jiri Pirko" , "netdev@vger.kernel.org" , "ralf@linux-mips.org" , "fubar@us.ibm.com" , "andy@greyhouse.net" , "kaber@trash.net" , "JBottomley@parallels.com" , "Love, Robert W" , "davem@davemloft.net" , "shemminger@linux-foundation.org" , "decot@google.com" , "mirq-linux@rere.qmqm.pl" , "Duyck, Alexander H" , "amit.salecha@qlogic.com" , "eric.dumazet@gmail.com" , "therbert@google.com" , "paulmck@linux.vnet.ibm.com" , "laijs@cn.fujitsu.com" , "xiaosuo@gmail.com" , "greearb@candelatech.com" , "loke.chetan@gmail.com" , "linux-mips@linux-mips.org" , "linux-scsi@vger.kernel.org" , "devel@open-fcoe.org" , "bridge@lists.linux-foundation.org" Subject: Re: [patch net-next-2.6 v3] net: consolidate and fix ethtool_ops->get_settings calling References: <1314905304-16485-1-git-send-email-jpirko@redhat.com> <20110902122630.GC1991@minipsycho> <1314989161.3419.5.camel@bwh-desktop> <20110903133428.GA2821@minipsycho> <1315057614.3092.160.camel@deadeye> <5A9BD224CEA58D4CB62235967D650C160A1B7D1C@orsmsx509.amr.corp.intel.com> In-Reply-To: <5A9BD224CEA58D4CB62235967D650C160A1B7D1C@orsmsx509.amr.corp.intel.com> X-WSS-ID: 627B1BF23KO14224740-01-01 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 31045 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bprakash@broadcom.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2898 Content-Length: 1643 Lines: 41 On 9/5/2011 8:25 PM, Zou, Yi wrote: >> >> On Sat, 2011-09-03 at 15:34 +0200, Jiri Pirko wrote: >>> This patch does several things: >>> - introduces __ethtool_get_settings which is called from ethtool code >> and >>> from drivers as well. Put ASSERT_RTNL there. >>> - dev_ethtool_get_settings() is replaced by __ethtool_get_settings() >>> - changes calling in drivers so rtnl locking is respected. In >>> iboe_get_rate was previously ->get_settings() called unlocked. This >>> fixes it. Also prb_calc_retire_blk_tmo() in af_packet.c had the same >>> problem. Also fixed by calling __dev_get_by_index() instead of >>> dev_get_by_index() and holding rtnl_lock for both calls. >>> - introduces rtnl_lock in bnx2fc_vport_create() and fcoe_vport_create() >>> so bnx2fc_if_create() and fcoe_if_create() are called locked as they >>> are from other places. >>> - use __ethtool_get_settings() in bonding code >>> >>> Signed-off-by: Jiri Pirko >> Reviewed-by: Ben Hutchings [except FCoE bits] >> >> Ben. > FCoE bits look ok to me. Thanks, > > Reviewed-by: Yi Zou bnx2fc changes looks OK to me. Reviewed-by: Bhanu Prakash Gollapudi > >> >> -- >> Ben Hutchings, Staff Engineer, Solarflare >> Not speaking for my employer; that's the marketing department's job. >> They asked us to note that Solarflare product names are trademarked. >> >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-scsi" in >> the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html From ralf@linux-mips.org Tue Sep 6 14:21:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Sep 2011 14:22:04 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:43290 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491143Ab1IFMV7 (ORCPT ); Tue, 6 Sep 2011 14:21:59 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p86CLKCA027435; Tue, 6 Sep 2011 14:21:20 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p86CKea8027414; Tue, 6 Sep 2011 14:20:40 +0200 Date: Tue, 6 Sep 2011 14:20:40 +0200 From: Ralf Baechle To: Jiri Pirko , tg@linux-mips.org Cc: Ben Hutchings , netdev@vger.kernel.org, fubar@us.ibm.com, andy@greyhouse.net, kaber@trash.net, bprakash@broadcom.com, JBottomley@parallels.com, robert.w.love@intel.com, davem@davemloft.net, shemminger@linux-foundation.org, decot@google.com, mirq-linux@rere.qmqm.pl, alexander.h.duyck@intel.com, amit.salecha@qlogic.com, eric.dumazet@gmail.com, therbert@google.com, paulmck@linux.vnet.ibm.com, laijs@cn.fujitsu.com, xiaosuo@gmail.com, greearb@candelatech.com, loke.chetan@gmail.com, linux-mips@linux-mips.org, linux-scsi@vger.kernel.org, devel@open-fcoe.org, bridge@lists.linux-foundation.org Subject: Re: [patch net-next-2.6 v3] net: consolidate and fix ethtool_ops->get_settings calling Message-ID: <20110906122040.GA25774@linux-mips.org> References: <1314905304-16485-1-git-send-email-jpirko@redhat.com> <20110902122630.GC1991@minipsycho> <1314989161.3419.5.camel@bwh-desktop> <20110903133428.GA2821@minipsycho> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110903133428.GA2821@minipsycho> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31046 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3086 Content-Length: 213 Lines: 9 On Sat, Sep 03, 2011 at 03:34:30PM +0200, Jiri Pirko wrote: > arch/mips/txx9/generic/setup_tx4939.c | 2 +- Acked-by: Ralf Baechle Feel free to merge this through the net tree. Ralf From david.daney@cavium.com Tue Sep 6 20:38:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Sep 2011 20:38:53 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10577 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491846Ab1IFSio (ORCPT ); Tue, 6 Sep 2011 20:38:44 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 06 Sep 2011 11:39:47 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 6 Sep 2011 11:38:35 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 6 Sep 2011 11:38:34 -0700 Message-ID: <4E6668A4.8010300@cavium.com> Date: Tue, 06 Sep 2011 11:38:28 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: SAURABH MALPANI CC: linux-mips@linux-mips.org Subject: Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 06 Sep 2011 18:38:34.0976 (UTC) FILETIME=[2F4B5E00:01CC6CC4] X-archive-position: 31047 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3389 Content-Length: 1240 Lines: 38 On 09/05/2011 03:23 AM, SAURABH MALPANI wrote: > Hi, > > correct mail filters.> > > Query: > > mailbox_interrupt is not registered with IRQF_PERCPU but it is > supposed to be percpu interrupt. Is that on purpose or a miss? On Octeon the per-cpuness of a particular irq is a property of the irq itself rather than being controlled by IRQF_PERCPU. So other than being perhaps stylistically in poor taste, no harm is done by omitting IRQF_PERCPU here. > I am > porting some code from x86 to octeon which requires special handling > for per cpu interrupts. > > void octeon_prepare_cpus(unsigned int max_cpus) > { > cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); > if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, > "mailbox0", mailbox_interrupt)) { > panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); > } > if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED, > "mailbox1", mailbox_interrupt)) { > panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); > } > } > > -- > Saurabh > > From saurabh140585@gmail.com Tue Sep 6 21:02:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Sep 2011 21:02:46 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:64283 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491846Ab1IFTCk convert rfc822-to-8bit (ORCPT ); Tue, 6 Sep 2011 21:02:40 +0200 Received: by fxd20 with SMTP id 20so86236fxd.36 for ; Tue, 06 Sep 2011 12:02:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=vYlgo6q3QCm1VtQZFfatT3+O2qszT0XoYx4Kwuv1JJo=; b=j/J+i5ABAvX9Fb3TMkxGCIYxFzeIyhQdb/E+ep89oUcrQHMeO4BTLbNBpQ46i3GQgn Je+VsRD/1/3eoDFajKHzGZY4SB8WO/0n8tN0IPMpnq8n0oEIruqAIn3ZveVxLf3OywYO 4F8H5h5x21hwzsKxUdP4xQ/TUNnG3MPd1wWN0= MIME-Version: 1.0 Received: by 10.223.63.8 with SMTP id z8mr346285fah.84.1315335755219; Tue, 06 Sep 2011 12:02:35 -0700 (PDT) Received: by 10.223.83.203 with HTTP; Tue, 6 Sep 2011 12:02:35 -0700 (PDT) In-Reply-To: <4E6668A4.8010300@cavium.com> References: <4E6668A4.8010300@cavium.com> Date: Wed, 7 Sep 2011 00:32:35 +0530 Message-ID: Subject: Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu From: SAURABH MALPANI To: David Daney Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 31048 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: saurabh140585@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3411 Content-Length: 1911 Lines: 64 Hi David, Thanks a bunch for clarifying this. Just to complete, I have some code which calls CHECK_IRQ_PER_CPU(desc->status) after every time a descriptor is created for an irq. And based on it we create either per cpu data structures or single data structure for that particular irq. After your clarification, I can safely create exception for OCTEON_IRQ_MBOX0 and OCTEON_IRQ_MBOX1 as you mention that missing the flag is just cosmetic. Thanks again Saurabh On Wed, Sep 7, 2011 at 12:08 AM, David Daney wrote: > On 09/05/2011 03:23 AM, SAURABH MALPANI wrote: >> >> Hi, >> >> > correct mail filters.> >> >> Query: >> >> mailbox_interrupt is not registered with IRQF_PERCPU but it is >> supposed to be percpu interrupt. Is that on purpose or a miss? > > On Octeon the per-cpuness of a particular irq is a property of the irq > itself rather than being controlled by IRQF_PERCPU.  So other than being > perhaps stylistically in poor taste, no harm is done by omitting IRQF_PERCPU > here. > >> I am >> porting some code from x86 to octeon which requires special handling >> for per cpu interrupts. >> >>  void octeon_prepare_cpus(unsigned int max_cpus) >> { >>          cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), >> 0xffffffff); >>          if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, >> IRQF_DISABLED, >>                          "mailbox0", mailbox_interrupt)) { >>                  panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); >>          } >>          if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, >> IRQF_DISABLED, >>                          "mailbox1", mailbox_interrupt)) { >>                  panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); >>          } >> } >> >> -- >> Saurabh >> >> > > -- Saurabh From david.daney@cavium.com Tue Sep 6 21:17:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Sep 2011 21:17:14 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12114 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491846Ab1IFTRJ (ORCPT ); Tue, 6 Sep 2011 21:17:09 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 06 Sep 2011 12:18:20 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 6 Sep 2011 12:17:08 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 6 Sep 2011 12:17:08 -0700 Message-ID: <4E6671B0.4040603@cavium.com> Date: Tue, 06 Sep 2011 12:17:04 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: SAURABH MALPANI CC: linux-mips@linux-mips.org Subject: Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu References: <4E6668A4.8010300@cavium.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 06 Sep 2011 19:17:08.0099 (UTC) FILETIME=[9205ED30:01CC6CC9] X-archive-position: 31049 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3419 Content-Length: 2058 Lines: 71 On 09/06/2011 12:02 PM, SAURABH MALPANI wrote: > Hi David, > > Thanks a bunch for clarifying this. Just to complete, I have some code > which calls CHECK_IRQ_PER_CPU(desc->status) after every time a > descriptor is created for an irq. And based on it we create either per > cpu data structures or single data structure for that particular irq. > > After your clarification, I can safely create exception for > OCTEON_IRQ_MBOX0 and OCTEON_IRQ_MBOX1 as you mention that missing the > flag is just cosmetic. > Well the performance counter and timer interrupts may suffer in a similar manner. David Daney > Thanks again > Saurabh > > > On Wed, Sep 7, 2011 at 12:08 AM, David Daney wrote: >> On 09/05/2011 03:23 AM, SAURABH MALPANI wrote: >>> >>> Hi, >>> >>> >> correct mail filters.> >>> >>> Query: >>> >>> mailbox_interrupt is not registered with IRQF_PERCPU but it is >>> supposed to be percpu interrupt. Is that on purpose or a miss? >> >> On Octeon the per-cpuness of a particular irq is a property of the irq >> itself rather than being controlled by IRQF_PERCPU. So other than being >> perhaps stylistically in poor taste, no harm is done by omitting IRQF_PERCPU >> here. >> >>> I am >>> porting some code from x86 to octeon which requires special handling >>> for per cpu interrupts. >>> >>> void octeon_prepare_cpus(unsigned int max_cpus) >>> { >>> cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), >>> 0xffffffff); >>> if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, >>> IRQF_DISABLED, >>> "mailbox0", mailbox_interrupt)) { >>> panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); >>> } >>> if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, >>> IRQF_DISABLED, >>> "mailbox1", mailbox_interrupt)) { >>> panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); >>> } >>> } >>> >>> -- >>> Saurabh >>> >>> >> >> > > > From saurabh140585@gmail.com Tue Sep 6 21:22:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Sep 2011 21:22:09 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:39476 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491846Ab1IFTWE (ORCPT ); Tue, 6 Sep 2011 21:22:04 +0200 Received: by fxd20 with SMTP id 20so105701fxd.36 for ; Tue, 06 Sep 2011 12:21:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=aHESF7+hJosJoOMjGzH7rlLoe94+rBb/mSvjwexmE+4=; b=aJbUX+GaP/dKZO/J1bNDtzWgXfz48GaYPr19hvLn9wAVc+jAS4a5sLMPSamY71+GR/ 2HKEXU/aqOwyOZX5LCAUB7RVODpC7hmLAzMFihHBmUstL54aBYYbxBzyh/dSs2Q4T5yT +5W+lbT376Jfz2rOqhvAzW+mQlpslpEc26r1I= MIME-Version: 1.0 Received: by 10.223.47.67 with SMTP id m3mr393345faf.27.1315336919574; Tue, 06 Sep 2011 12:21:59 -0700 (PDT) Received: by 10.223.83.203 with HTTP; Tue, 6 Sep 2011 12:21:59 -0700 (PDT) In-Reply-To: <4E6671B0.4040603@cavium.com> References: <4E6668A4.8010300@cavium.com> <4E6671B0.4040603@cavium.com> Date: Wed, 7 Sep 2011 00:51:59 +0530 Message-ID: Subject: Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu From: SAURABH MALPANI To: David Daney Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 31050 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: saurabh140585@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3422 Content-Length: 951 Lines: 26 On Wed, Sep 7, 2011 at 12:47 AM, David Daney wrote: > On 09/06/2011 12:02 PM, SAURABH MALPANI wrote: >> >> Hi David, >> >> Thanks a bunch for clarifying this. Just to complete, I have some code >> which calls CHECK_IRQ_PER_CPU(desc->status) after every time a >> descriptor is created for an irq. And based on it we create either per >> cpu data structures or single data structure for that particular irq. >> >> After your clarification, I can safely create exception for >> OCTEON_IRQ_MBOX0 and OCTEON_IRQ_MBOX1 as you mention that missing the >> flag is just cosmetic. >> > > Well the performance counter and timer interrupts may suffer in a similar > manner. > > David Daney > Since the timer interrupt is registered via the clock device infrastructure, I found that hrtimer_interrupt irq descriptor was indeed succeeding the CHECK_IRQ_PER_CPU test. So far in our testing we only hit an exception for mailbox interrupt. From yong.zhang0@gmail.com Wed Sep 7 10:14:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Sep 2011 10:14:56 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:52700 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491003Ab1IGIOo (ORCPT ); Wed, 7 Sep 2011 10:14:44 +0200 Received: by wyh11 with SMTP id 11so6215183wyh.36 for ; Wed, 07 Sep 2011 01:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=v9ZjpXS1iPvP0cXbhjXODmdgbg0oEMRTjHej6LH/gQc=; b=TtJascjXCDQLPGzUJB8qeGRLOvGEt1xA4Q/paI+Cb30jGVpUjh5shWWflaK0dFZ28r z2//kfHqDEgGNa1YsIHuaY6oeup9rKWsMGRhanHcesQYEnL6f696ONmkV/Mr9yK2JzXT McIwsS1LfOFgqhC2FtabZJECmaZjQs6f1M5hw= Received: by 10.227.37.17 with SMTP id v17mr6218674wbd.2.1315383278236; Wed, 07 Sep 2011 01:14:38 -0700 (PDT) Received: from localhost ([61.148.56.138]) by mx.google.com with ESMTPS id l13sm2798880wbp.20.2011.09.07.01.14.36 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Sep 2011 01:14:37 -0700 (PDT) From: Yong Zhang To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de, mingo@elte.hu, Ralf Baechle , Peter Zijlstra , Paul Mackerras , Arnaldo Carvalho de Melo , Manuel Lauss , Yong Zhang , John Stultz , David Daney , Benjamin Herrenschmidt , Jesper Nilsson , Chris Metcalf , David Howells , Kevin Cernekee , Russell King , Andrew Morton , Mike Frysinger , Eric Dumazet , Arun Sharma , Martin Schwidefsky , John Crispin , Ralph Hempel , Lucas De Marchi , Anoop P A , "David S. Miller" , Jiri Kosina , "Justin P. Mattock" , Joe Perches , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-mips@linux-mips.org Subject: [PATCH 14/62] MIPS: irq: Remove IRQF_DISABLED Date: Wed, 7 Sep 2011 16:10:11 +0800 Message-Id: <1315383059-3673-15-git-send-email-yong.zhang0@gmail.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1315383059-3673-1-git-send-email-yong.zhang0@gmail.com> References: <1315383059-3673-1-git-send-email-yong.zhang0@gmail.com> X-archive-position: 31051 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang0@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3711 Content-Length: 20721 Lines: 588 This flag is a NOOP and can be removed now. Signed-off-by: Yong Zhang --- arch/mips/alchemy/common/dbdma.c | 2 +- arch/mips/alchemy/common/time.c | 2 +- arch/mips/alchemy/devboards/db1200/platform.c | 4 ++-- arch/mips/cavium-octeon/smp.c | 2 +- arch/mips/dec/setup.c | 1 - arch/mips/include/asm/mach-generic/floppy.h | 2 +- arch/mips/include/asm/mach-jazz/floppy.h | 2 +- arch/mips/jazz/irq.c | 2 +- arch/mips/kernel/cevt-bcm1480.c | 2 +- arch/mips/kernel/cevt-ds1287.c | 2 +- arch/mips/kernel/cevt-gt641xx.c | 2 +- arch/mips/kernel/cevt-r4k.c | 2 +- arch/mips/kernel/cevt-sb1250.c | 2 +- arch/mips/kernel/cevt-txx9.c | 2 +- arch/mips/kernel/i8253.c | 2 +- arch/mips/kernel/perf_event.c | 2 +- arch/mips/kernel/rtlx.c | 1 - arch/mips/kernel/smtc.c | 2 +- arch/mips/lantiq/irq.c | 1 - arch/mips/loongson/common/cs5536/cs5536_mfgpt.c | 2 +- arch/mips/mti-malta/malta-int.c | 4 ++-- arch/mips/pci/ops-pmcmsp.c | 2 +- arch/mips/pci/ops-tx3927.c | 2 +- arch/mips/pci/pci-tx4927.c | 2 +- arch/mips/pci/pci-tx4938.c | 2 +- arch/mips/pci/pci-tx4939.c | 2 +- arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c | 2 +- arch/mips/pmc-sierra/msp71xx/msp_smp.c | 4 ++-- arch/mips/pnx8550/common/int.c | 3 +-- arch/mips/pnx8550/common/time.c | 4 ++-- arch/mips/sgi-ip22/ip22-int.c | 5 ----- arch/mips/sgi-ip27/ip27-irq.c | 2 +- arch/mips/sgi-ip27/ip27-timer.c | 2 +- arch/mips/sgi-ip32/ip32-irq.c | 2 -- arch/mips/sni/irq.c | 2 +- arch/mips/sni/time.c | 2 +- arch/mips/txx9/generic/pci.c | 2 +- 37 files changed, 36 insertions(+), 47 deletions(-) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 3a5abb5..4025d77 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -1048,7 +1048,7 @@ static int __init au1xxx_dbdma_init(void) return -ENODEV; } - ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, + ret = request_irq(irq_nr, dbdma_interrupt, 0, "Au1xxx dbdma", (void *)dbdma_gptr); if (ret) printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index d5da6ad..146a5fa 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -92,7 +92,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { static struct irqaction au1x_rtcmatch2_irqaction = { .handler = au1x_rtcmatch2_irq, - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .name = "timer", .dev_id = &au1x_rtcmatch2_clockdev, }; diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index fbb5593..252f54c 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -271,12 +271,12 @@ static int db1200_mmc_cd_setup(void *mmc_host, int en) if (en) { ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, - IRQF_DISABLED, "sd_insert", mmc_host); + 0, "sd_insert", mmc_host); if (ret) goto out; ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, - IRQF_DISABLED, "sd_eject", mmc_host); + 0, "sd_eject", mmc_host); if (ret) { free_irq(DB1200_SD0_INSERT_INT, mmc_host); goto out; diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 8b60642..b6a0807 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -207,7 +207,7 @@ void octeon_prepare_cpus(unsigned int max_cpus) * the other bits alone. */ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); - if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, + if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, 0, "SMP-IPI", mailbox_interrupt)) { panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); } diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index fa45e92..f47152a 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -108,7 +108,6 @@ static struct irqaction fpuirq = { }; static struct irqaction busirq = { - .flags = IRQF_DISABLED, .name = "bus error", }; diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h index 001a8ce..a38f4d4 100644 --- a/arch/mips/include/asm/mach-generic/floppy.h +++ b/arch/mips/include/asm/mach-generic/floppy.h @@ -98,7 +98,7 @@ static inline void fd_disable_irq(void) static inline int fd_request_irq(void) { return request_irq(FLOPPY_IRQ, floppy_interrupt, - IRQF_DISABLED, "floppy", NULL); + 0, "floppy", NULL); } static inline void fd_free_irq(void) diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h index 56e9ca6..88b5acb 100644 --- a/arch/mips/include/asm/mach-jazz/floppy.h +++ b/arch/mips/include/asm/mach-jazz/floppy.h @@ -90,7 +90,7 @@ static inline void fd_disable_irq(void) static inline int fd_request_irq(void) { return request_irq(FLOPPY_IRQ, floppy_interrupt, - IRQF_DISABLED, "floppy", NULL); + 0, "floppy", NULL); } static inline void fd_free_irq(void) diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index ca9bd20..0f4a147 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -133,7 +133,7 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id) static struct irqaction r4030_timer_irqaction = { .handler = r4030_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .name = "R4030 timer", }; diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c index 36c3898..69bbfae 100644 --- a/arch/mips/kernel/cevt-bcm1480.c +++ b/arch/mips/kernel/cevt-bcm1480.c @@ -145,7 +145,7 @@ void __cpuinit sb1480_clockevent_init(void) bcm1480_unmask_irq(cpu, irq); action->handler = sibyte_counter_handler; - action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; + action->flags = IRQF_PERCPU | IRQF_TIMER; action->name = name; action->dev_id = cd; diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c index 939157e..ed648cb 100644 --- a/arch/mips/kernel/cevt-ds1287.c +++ b/arch/mips/kernel/cevt-ds1287.c @@ -108,7 +108,7 @@ static irqreturn_t ds1287_interrupt(int irq, void *dev_id) static struct irqaction ds1287_irqaction = { .handler = ds1287_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, + .flags = IRQF_PERCPU | IRQF_TIMER, .name = "ds1287", }; diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c index 339f363..831b475 100644 --- a/arch/mips/kernel/cevt-gt641xx.c +++ b/arch/mips/kernel/cevt-gt641xx.c @@ -114,7 +114,7 @@ static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id) static struct irqaction gt641xx_timer0_irqaction = { .handler = gt641xx_timer0_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, + .flags = IRQF_PERCPU | IRQF_TIMER, .name = "gt641xx_timer0", }; diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 98c5a97..4a3a1af 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -84,7 +84,7 @@ out: struct irqaction c0_compare_irqaction = { .handler = c0_compare_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, + .flags = IRQF_PERCPU | IRQF_TIMER, .name = "timer", }; diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c index 590c54f..e73439f 100644 --- a/arch/mips/kernel/cevt-sb1250.c +++ b/arch/mips/kernel/cevt-sb1250.c @@ -144,7 +144,7 @@ void __cpuinit sb1250_clockevent_init(void) sb1250_unmask_irq(cpu, irq); action->handler = sibyte_counter_handler; - action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; + action->flags = IRQF_PERCPU | IRQF_TIMER; action->name = name; action->dev_id = cd; diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c index f0ab92a..e5c30b1 100644 --- a/arch/mips/kernel/cevt-txx9.c +++ b/arch/mips/kernel/cevt-txx9.c @@ -146,7 +146,7 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id) static struct irqaction txx9tmr_irq = { .handler = txx9tmr_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, + .flags = IRQF_PERCPU | IRQF_TIMER, .name = "txx9tmr", .dev_id = &txx9_clock_event_device, }; diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c index be4ee7d..a9e3794 100644 --- a/arch/mips/kernel/i8253.c +++ b/arch/mips/kernel/i8253.c @@ -19,7 +19,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) static struct irqaction irq0 = { .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER, + .flags = IRQF_NOBALANCING | IRQF_TIMER, .name = "timer" }; diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index 0aee944..025324e 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -314,7 +314,7 @@ static int mipspmu_get_irq(void) if (mipspmu->irq >= 0) { /* Request my own irq handler. */ err = request_irq(mipspmu->irq, mipspmu->handle_irq, - IRQF_DISABLED | IRQF_NOBALANCING, + IRQF_NOBALANCING, "mips_perf_pmu", NULL); if (err) { pr_warning("Unable to request IRQ%d for MIPS " diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 7a80b7c..6988543 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -474,7 +474,6 @@ static const struct file_operations rtlx_fops = { static struct irqaction rtlx_irq = { .handler = rtlx_interrupt, - .flags = IRQF_DISABLED, .name = "RTLX", }; diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index f0895e7..17c9412 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -1130,7 +1130,7 @@ static void ipi_irq_dispatch(void) static struct irqaction irq_ipi = { .handler = ipi_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_PERCPU, .name = "SMTC_IPI" }; diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index fc89795..9d072c4 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -242,7 +242,6 @@ out: static struct irqaction cascade = { .handler = no_action, - .flags = IRQF_DISABLED, .name = "cascade", }; diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c index 0cb1b97..5d1f48f 100644 --- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c +++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c @@ -111,7 +111,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) static struct irqaction irq5 = { .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER, + .flags = IRQF_NOBALANCING | IRQF_TIMER, .name = "timer" }; diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 1d36c511..dc01414 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -322,13 +322,13 @@ static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) static struct irqaction irq_resched = { .handler = ipi_resched_interrupt, - .flags = IRQF_DISABLED|IRQF_PERCPU, + .flags = IRQF_PERCPU, .name = "IPI_resched" }; static struct irqaction irq_call = { .handler = ipi_call_interrupt, - .flags = IRQF_DISABLED|IRQF_PERCPU, + .flags = IRQF_PERCPU, .name = "IPI_call" }; #endif /* CONFIG_MIPS_MT_SMP */ diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c index 8fbfbf2..389bf66 100644 --- a/arch/mips/pci/ops-pmcmsp.c +++ b/arch/mips/pci/ops-pmcmsp.c @@ -405,7 +405,7 @@ int msp_pcibios_config_access(unsigned char access_type, if (pciirqflag == 0) { ret = request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */ bpci_interrupt, - IRQF_SHARED | IRQF_DISABLED, + IRQF_SHARED, "PMC MSP PCI Host", preg); if (ret != 0) diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c index 6a3bdb5..02d64f77 100644 --- a/arch/mips/pci/ops-tx3927.c +++ b/arch/mips/pci/ops-tx3927.c @@ -225,7 +225,7 @@ void __init tx3927_setup_pcierr_irq(void) { if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI, tx3927_pcierr_interrupt, - IRQF_DISABLED, "PCI error", + 0, "PCI error", (void *)TX3927_PCIC_REG)) printk(KERN_WARNING "Failed to request irq for PCIERR\n"); } diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c index a580740..a032ae0 100644 --- a/arch/mips/pci/pci-tx4927.c +++ b/arch/mips/pci/pci-tx4927.c @@ -85,7 +85,7 @@ void __init tx4927_setup_pcierr_irq(void) { if (request_irq(TXX9_IRQ_BASE + TX4927_IR_PCIERR, tx4927_pcierr_interrupt, - IRQF_DISABLED, "PCI error", + 0, "PCI error", (void *)TX4927_PCIC_REG)) printk(KERN_WARNING "Failed to request irq for PCIERR\n"); } diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c index 20e45f3..141bba5 100644 --- a/arch/mips/pci/pci-tx4938.c +++ b/arch/mips/pci/pci-tx4938.c @@ -136,7 +136,7 @@ void __init tx4938_setup_pcierr_irq(void) { if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR, tx4927_pcierr_interrupt, - IRQF_DISABLED, "PCI error", + 0, "PCI error", (void *)TX4927_PCIC_REG)) printk(KERN_WARNING "Failed to request irq for PCIERR\n"); } diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c index 9ef8406..c10fbf2 100644 --- a/arch/mips/pci/pci-tx4939.c +++ b/arch/mips/pci/pci-tx4939.c @@ -101,7 +101,7 @@ void __init tx4939_setup_pcierr_irq(void) { if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR, tx4927_pcierr_interrupt, - IRQF_DISABLED, "PCI error", + 0, "PCI error", (void *)TX4939_PCIC_REG)) pr_warning("Failed to request irq for PCIERR\n"); } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c index c841f08..bb57ed9 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c @@ -149,7 +149,7 @@ static int msp_hwbutton_register(struct hwbutton_interrupt *hirq) CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq); *CIC_EXT_CFG_REG = cic_ext; - return request_irq(hirq->irq, hwbutton_handler, IRQF_DISABLED, + return request_irq(hirq->irq, hwbutton_handler, 0, hirq->name, hirq); } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c index bec1790..1017058 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_smp.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c @@ -51,13 +51,13 @@ static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) static struct irqaction irq_resched = { .handler = ipi_resched_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_PERCPU, .name = "IPI_resched" }; static struct irqaction irq_call = { .handler = ipi_call_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_PERCPU, .name = "IPI_call" }; diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c index 6b93c81..90feb18 100644 --- a/arch/mips/pnx8550/common/int.c +++ b/arch/mips/pnx8550/common/int.c @@ -167,13 +167,12 @@ static struct irq_chip level_irq_type = { static struct irqaction gic_action = { .handler = no_action, - .flags = IRQF_DISABLED, .name = "GIC", }; static struct irqaction timer_action = { .handler = no_action, - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .name = "Timer", }; diff --git a/arch/mips/pnx8550/common/time.c b/arch/mips/pnx8550/common/time.c index 8836c62..831d6b3 100644 --- a/arch/mips/pnx8550/common/time.c +++ b/arch/mips/pnx8550/common/time.c @@ -59,7 +59,7 @@ static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) static struct irqaction pnx8xxx_timer_irq = { .handler = pnx8xxx_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, + .flags = IRQF_PERCPU | IRQF_TIMER, .name = "pnx8xxx_timer", }; @@ -72,7 +72,7 @@ static irqreturn_t monotonic_interrupt(int irq, void *dev_id) static struct irqaction monotonic_irqaction = { .handler = monotonic_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .name = "Monotonic timer", }; diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index b4d08e4..c27ad89 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -155,32 +155,27 @@ static void __irq_entry indy_buserror_irq(void) static struct irqaction local0_cascade = { .handler = no_action, - .flags = IRQF_DISABLED, .name = "local0 cascade", }; static struct irqaction local1_cascade = { .handler = no_action, - .flags = IRQF_DISABLED, .name = "local1 cascade", }; static struct irqaction buserr = { .handler = no_action, - .flags = IRQF_DISABLED, .name = "Bus Error", }; static struct irqaction map0_cascade = { .handler = no_action, - .flags = IRQF_DISABLED, .name = "mapable0 cascade", }; #ifdef USE_LIO3_IRQ static struct irqaction map1_cascade = { .handler = no_action, - .flags = IRQF_DISABLED, .name = "mapable1 cascade", }; #define SGI_INTERRUPTS SGINT_END diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index b18b04e..649b6e1 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -116,7 +116,7 @@ static int ms1bit(unsigned long x) } /* - * This code is unnecessarily complex, because we do IRQF_DISABLED + * This code is unnecessarily complex, because we do * intr enabling. Basically, once we grab the set of intrs we need * to service, we must mask _all_ these interrupts; firstly, to make * sure the same intr does not intr again, causing recursion that diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index ef74f32..13cfeab 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -91,7 +91,7 @@ static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id) struct irqaction hub_rt_irqaction = { .handler = hub_rt_counter_handler, - .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, + .flags = IRQF_PERCPU | IRQF_TIMER, .name = "hub-rt", }; diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index c65ea76..a092860 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -113,13 +113,11 @@ extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); static struct irqaction memerr_irq = { .handler = crime_memerr_intr, - .flags = IRQF_DISABLED, .name = "CRIME memory error", }; static struct irqaction cpuerr_irq = { .handler = crime_cpuerr_intr, - .flags = IRQF_DISABLED, .name = "CRIME CPU error", }; diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c index e8e72bb..5a4ec75 100644 --- a/arch/mips/sni/irq.c +++ b/arch/mips/sni/irq.c @@ -42,7 +42,7 @@ static irqreturn_t sni_isa_irq_handler(int dummy, void *p) struct irqaction sni_isa_irq = { .handler = sni_isa_irq_handler, .name = "ISA", - .flags = IRQF_SHARED | IRQF_DISABLED + .flags = IRQF_SHARED }; /* diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index ec0be14..494c9e7 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -68,7 +68,7 @@ static irqreturn_t a20r_interrupt(int irq, void *dev_id) static struct irqaction a20r_irqaction = { .handler = a20r_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, + .flags = IRQF_PERCPU | IRQF_TIMER, .name = "a20r-timer", }; diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c index 85a87de..682efb0 100644 --- a/arch/mips/txx9/generic/pci.c +++ b/arch/mips/txx9/generic/pci.c @@ -262,7 +262,7 @@ txx9_i8259_irq_setup(int irq) int err; init_i8259_irqs(); - err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED, + err = request_irq(irq, &i8259_interrupt, IRQF_SHARED, "cascade(i8259)", (void *)(long)irq); if (!err) printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq); -- 1.7.4.1 From ralf@linux-mips.org Wed Sep 7 11:26:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Sep 2011 11:26:23 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:37912 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491189Ab1IGJ0Q (ORCPT ); Wed, 7 Sep 2011 11:26:16 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p879O1lJ027420; Wed, 7 Sep 2011 11:24:01 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p879M7WE027357; Wed, 7 Sep 2011 11:22:07 +0200 Date: Wed, 7 Sep 2011 11:22:07 +0200 From: Ralf Baechle To: Yong Zhang Cc: linux-kernel@vger.kernel.org, tglx@linutronix.de, mingo@elte.hu, Peter Zijlstra , Paul Mackerras , Arnaldo Carvalho de Melo , Manuel Lauss , John Stultz , David Daney , Benjamin Herrenschmidt , Jesper Nilsson , Chris Metcalf , David Howells , Kevin Cernekee , Russell King , Andrew Morton , Mike Frysinger , Eric Dumazet , Arun Sharma , Martin Schwidefsky , John Crispin , Ralph Hempel , Lucas De Marchi , Anoop P A , "David S. Miller" , Jiri Kosina , "Justin P. Mattock" , Joe Perches , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , linux-mips@linux-mips.org Subject: Re: [PATCH 14/62] MIPS: irq: Remove IRQF_DISABLED Message-ID: <20110907092207.GA25833@linux-mips.org> References: <1315383059-3673-1-git-send-email-yong.zhang0@gmail.com> <1315383059-3673-15-git-send-email-yong.zhang0@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1315383059-3673-15-git-send-email-yong.zhang0@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 31052 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3721 Content-Length: 161 Lines: 7 On Wed, Sep 07, 2011 at 04:10:11PM +0800, Yong Zhang wrote: > This flag is a NOOP and can be removed now. Acked-by: Ralf Baechle Ralf From maxin.john@gmail.com Fri Sep 9 00:06:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Sep 2011 00:06:16 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:41130 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491041Ab1IHWGK (ORCPT ); Fri, 9 Sep 2011 00:06:10 +0200 Received: by bkat2 with SMTP id t2so293363bka.36 for ; Thu, 08 Sep 2011 15:06:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:mime-version:content-type :content-disposition:user-agent; bh=0QL0/FnMtUiP/KIYyDDz4eZI3sxW0zd4hj32cWZugqs=; b=oceT+Z7JMHfbJSj6E1YNmzSlx4mOcaxRxrJZHLenVuT4N9au73NzbTCbMFIzs9wL42 TQ4OQLi/1NswedLYHdCqZAUc73XZrZGP0adOrD13gOe4ApdnFEmiNHJ2hiGmBeHlzC7e KnoBhP/J2N9mC2JgwiPwet/8QW+iEkIstFE4M= Received: by 10.204.151.85 with SMTP id b21mr882166bkw.8.1315519564875; Thu, 08 Sep 2011 15:06:04 -0700 (PDT) Received: from localhost (84-231-27-196.elisa-mobile.fi [84.231.27.196]) by mx.google.com with ESMTPS id t18sm1318919bkb.9.2011.09.08.15.06.01 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 08 Sep 2011 15:06:03 -0700 (PDT) Date: Fri, 9 Sep 2011 01:06:00 +0300 From: "Maxin B. John" To: Ralf Baechle Cc: David Daney , Lucas De Marchi , Kevin Cernekee , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH] mips: mm: tlbex.c: Fix compiler warnings Message-ID: <20110908220559.GA3040@maxin> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 31053 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maxin.john@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4263 Content-Length: 1044 Lines: 24 CC arch/mips/mm/tlbex.o cc1: warnings being treated as errors arch/mips/mm/tlbex.c: In function 'build_r3000_tlb_modify_handler': arch/mips/mm/tlbex.c:1769: error: 'wr.r1' is used uninitialized in this function arch/mips/mm/tlbex.c:1769: error: 'wr.r2' is used uninitialized in this function arch/mips/mm/tlbex.c:1769: error: 'wr.r3' is used uninitialized in this function make[2]: *** [arch/mips/mm/tlbex.o] Error 1 make[1]: *** [arch/mips/mm] Error 2 make: *** [arch/mips] Error 2 Signed-off-by: Maxin B. John --- diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index b6e1cff..ab51b83 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1764,6 +1764,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void) memset(handle_tlbm, 0, sizeof(handle_tlbm)); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); + memset(&wr, 0, sizeof(wr)); build_r3000_tlbchange_handler_head(&p, K0, K1); build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); From cratiu@ixiacom.com Fri Sep 9 15:23:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Sep 2011 15:23:45 +0200 (CEST) Received: from ixia-3.edge2.lax012.pnap.net ([74.217.148.5]:17584 "EHLO ixqw-mail-out.ixiacom.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491119Ab1IINXj (ORCPT ); Fri, 9 Sep 2011 15:23:39 +0200 Received: from ixro-ex1.ixiacom.com (10.205.8.10) by IXCA-HC2.ixiacom.com (10.200.2.51) with Microsoft SMTP Server id 8.2.255.0; Fri, 9 Sep 2011 06:23:32 -0700 Received: from ixro-cratiu.localnet ([10.205.20.206]) by ixro-ex1.ixiacom.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 9 Sep 2011 16:23:29 +0300 From: Cosmin Ratiu Organization: IXIA To: Subject: Octeon crash in virt_to_page(&core0_stack_variable) Date: Fri, 9 Sep 2011 16:23:28 +0300 User-Agent: KMail/1.13.7 (Linux/2.6.32-5-686; KDE/4.6.5; i686; ; ) CC: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="Boundary-00=_QNhaO/I996LuNwl" Message-ID: <201109091623.29000.cratiu@ixiacom.com> X-OriginalArrivalTime: 09 Sep 2011 13:23:29.0450 (UTC) FILETIME=[A9F648A0:01CC6EF3] X-archive-position: 31054 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cratiu@ixiacom.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4799 Content-Length: 28143 Lines: 626 --Boundary-00=_QNhaO/I996LuNwl Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Hello, I've been investigating a strange crash and I wanted to ask for your help. The crash happens when virt_to_page is called with an address from the soft= irq=20 stack of core 0 on Cavium Octeon. It may happen on other MIPS processors as= =20 well, but I'm not sure. I've attached a simple kernel module to demonstrate the problem and the out= put=20 of dmesg + the crash. Two seconds after inserting the module, the kernel=20 should crash. =46rom what I've dug up in the kernel sources, it seems the stack for the f= irst=20 idle task resides in the data segment (mapped in kseg2) while the rest are= =20 allocated with kmalloc in __cpu_up() and reside in a different area (CAC_BA= SE=20 upwards). It seems virt_to_phys produces bogus results for kseg2 and after that,=20 virt_to_page crashes trying to access invalid memory. This problem was discovered when doing BGP traffic with the TCP MD5 option= =20 activated, where the following call chain caused a crash: * tcp_v4_rcv * tcp_v4_timewait_ack * tcp_v4_send_ack -> follow stack variable rep.th * tcp_v4_md5_hash_hdr * tcp_md5_hash_header * sg_init_one * sg_set_buf * virt_to_page I noticed that tcp_v4_send_reset uses a similar stack variable and also cal= ls=20 tcp_v4_md5_hash_hdr, so it has the same problem. I don't fully understand octeon mm details, so I wanted to bring up this is= sue=20 in order to find a proper fix. To avoid the problem, I've implemented a quick hack to declare those variab= les=20 percpu instead of on the stack, so they would also reside in CAC_BASE upwar= ds.=20 I've attached a patch against 2.6.32 for reference. Cosmin. --Boundary-00=_QNhaO/I996LuNwl Content-Type: text/x-log; charset="UTF-8"; name="dmesg.log" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="dmesg.log" [ 0.000/0] Linux version 2.6.32 (IxOS linux_2.6.32/main/6.20.0.298) (ixsdk@ixca-cm-vmbld72) (gcc version 4.3.3 (Cavium Networks Version: 2_0_0 build 95) ) #1 SMP Wed Aug 24 09:26:59 PDT 2011 [ 0.000/0] boot_desc_ptr 800000000fde4300 bootinfo 800000000fde5c00 phy_mem_desc_addr 24108 [ 0.000/0] Ixia kernel instance 0, cores_per_instance 12, port_type 161 [ 0.000/0] CVMSEG size: 2 cache lines (256 bytes) [ 0.000/0] ixia_uart: configured at 800000000ffa9000 [ 0.000/0] bootconsole [early0] enabled [ 0.000/0] CPU revision is: 000d0409 (Cavium Octeon+) [ 0.000/0] Checking for the multiply/shift bug... no. [ 0.000/0] Checking for the daddiu bug... no. [ 0.000/0] Found named block linmem0.0 @ 0x3000000, size= 0xb000000 [ 0.000/0] Found named block linmem0.1 @ 0x410000000, size= 0x10000000 [ 0.000/0] Found named block linmem0.2 @ 0x20000000, size= 0x20000000 [ 0.000/0] Found named block linmem0.3 @ 0x40000000, size= 0xc0000000 [ 0.000/0] Scan_named_regions complete [ 0.000/0] Determined physical RAM map: [ 0.000/0] memory: 00000000008dd000 @ 00000000013f3000 (usable after init) [ 0.000/0] memory: 000000000b000000 @ 0000000003000000 (usable) [ 0.000/0] memory: 0000000010000000 @ 0000000410000000 (usable) [ 0.000/0] memory: 00000000e0000000 @ 0000000020000000 (usable) [ 0.000/0] Wasting 285992 bytes for tracking 5107 unused pages [ 0.000/0] Initrd not found or empty - disabling initrd [ 0.000/0] Zone PFN ranges: [ 0.000/0] Normal 0x000013f3 -> 0x00420000 [ 0.000/0] Movable zone start PFN for each node [ 0.000/0] early_node_map[4] active PFN ranges [ 0.000/0] 0: 0x000013f3 -> 0x00001cd0 [ 0.000/0] 0: 0x00003000 -> 0x0000e000 [ 0.000/0] 0: 0x00020000 -> 0x00100000 [ 0.000/0] 0: 0x00410000 -> 0x00420000 [ 0.000/0] On node 0 totalpages: 1030365 [ 0.000/0] Normal zone: 59067 pages used for memmap [ 0.000/0] Normal zone: 0 pages reserved [ 0.000/0] Normal zone: 971298 pages, LIFO batch:31 [ 0.000/0] Failed to allocate memory for Hotplug memory block [ 0.000/0] PERCPU: Embedded 10 pages/cpu @a8000000068a0000 s10624 r8192 d22144 u65536 [ 0.000/0] pcpu-alloc: s10624 r8192 d22144 u65536 alloc=16*4096 [ 0.000/0] pcpu-alloc: [0] 00 [0] 01 [0] 02 [0] 03 [0] 04 [0] 05 [0] 06 [0] 07 [ 0.000/0] pcpu-alloc: [0] 08 [0] 09 [0] 10 [0] 11 [ 0.000/0] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 971298 [ 0.000/0] Kernel command line: console=ttyS0,115200 [ 0.000/0] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000/0] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) [ 0.000/0] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) [ 0.000/0] Primary instruction cache 32kB, virtually tagged, 4 way, 64 sets, linesize 128 bytes. [ 0.000/0] Primary data cache 16kB, 64-way, 2 sets, linesize 128 bytes. [ 0.000/0] Memory: 4047476k/4121460k available (2975k kernel code, 73196k reserved, 1067k data, 9076k init, 0k highmem) [ 0.000/0] Hierarchical RCU implementation. [ 0.000/0] NR_IRQS:408 [ 0.000/0] console [ttyS0] enabled, bootconsole disabled [ 1951.025/0] Calibrating delay loop (skipped) preset value.. 1200.00 BogoMIPS (lpj=600000) [ 1951.026/0] Mount-cache hash table entries: 256 [ 1951.026/0] Checking for the daddi bug... no. [ 1951.027/0] SMP: Booting CPU01 (CoreId 1)... [ 1951.027/1] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.027/0] SMP: Booting CPU02 (CoreId 2)... [ 1951.027/2] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.028/0] SMP: Booting CPU03 (CoreId 3)... [ 1951.028/3] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.028/0] SMP: Booting CPU04 (CoreId 4)... [ 1951.028/4] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.029/0] SMP: Booting CPU05 (CoreId 5)... [ 1951.029/5] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.030/0] SMP: Booting CPU06 (CoreId 6)... [ 1951.030/6] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.030/0] SMP: Booting CPU07 (CoreId 7)... [ 1951.030/7] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.031/0] SMP: Booting CPU08 (CoreId 8)... [ 1951.031/8] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.031/0] SMP: Booting CPU09 (CoreId 9)... [ 1951.031/9] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.032/0] SMP: Booting CPU10 (CoreId 10)... [ 1951.032/a] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.033/0] SMP: Booting CPU11 (CoreId 11)... [ 1951.033/b] CPU revision is: 000d0409 (Cavium Octeon+) [ 1951.033/0] Brought up 12 CPUs [ 1951.033/0] CPU0 attaching sched-domain: [ 1951.033/0] domain 0: span 0-11 level CPU [ 1951.033/0] groups: 0 1 2 3 4 5 6 7 8 9 10 11 [ 1951.033/0] CPU1 attaching sched-domain: [ 1951.033/0] domain 0: span 0-11 level CPU [ 1951.033/0] groups: 1 2 3 4 5 6 7 8 9 10 11 0 [ 1951.033/0] CPU2 attaching sched-domain: [ 1951.033/0] domain 0: span 0-11 level CPU [ 1951.033/0] groups: 2 3 4 5 6 7 8 9 10 11 0 1 [ 1951.033/0] CPU3 attaching sched-domain: [ 1951.033/0] domain 0: span 0-11 level CPU [ 1951.033/0] groups: 3 4 5 6 7 8 9 10 11 0 1 2 [ 1951.033/0] CPU4 attaching sched-domain: [ 1951.033/0] domain 0: span 0-11 level CPU [ 1951.033/0] groups: 4 5 6 7 8 9 10 11 0 1 2 3 [ 1951.033/0] CPU5 attaching sched-domain: [ 1951.033/0] domain 0: span 0-11 level CPU [ 1951.033/0] groups: 5 6 7 8 9 10 11 0 1 2 3 4 [ 1951.033/0] CPU6 attaching sched-domain: [ 1951.033/0] domain 0: span 0-11 level CPU [ 1951.033/0] groups: 6 7 8 9 10 11 0 1 2 3 4 5 [ 1951.033/0] CPU7 attaching sched-domain: [ 1951.033/0] domain 0: span 0-11 level CPU [ 1951.033/0] groups: 7 8 9 10 11 0 1 2 3 4 5 6 [ 1951.034/0] CPU8 attaching sched-domain: [ 1951.034/0] domain 0: span 0-11 level CPU [ 1951.034/0] groups: 8 9 10 11 0 1 2 3 4 5 6 7 [ 1951.034/0] CPU9 attaching sched-domain: [ 1951.034/0] domain 0: span 0-11 level CPU [ 1951.034/0] groups: 9 10 11 0 1 2 3 4 5 6 7 8 [ 1951.034/0] CPU10 attaching sched-domain: [ 1951.034/0] domain 0: span 0-11 level CPU [ 1951.034/0] groups: 10 11 0 1 2 3 4 5 6 7 8 9 [ 1951.034/0] CPU11 attaching sched-domain: [ 1951.034/0] domain 0: span 0-11 level CPU [ 1951.034/0] groups: 11 0 1 2 3 4 5 6 7 8 9 10 [ 1951.039/0] NET: Registered protocol family 16 [ 1951.039/0] bio: create slab at 0 [ 1951.041/0] SCSI subsystem initialized [ 1951.041/0] Switching to clocksource OCTEON_CVMCOUNT [ 1951.043/8] [multinic] Initializing ... [ 1951.043/8] NET: Registered protocol family 2 [ 1951.044/8] IP route cache hash table entries: 131072 (order: 8, 1048576 bytes) [ 1951.045/8] TCP established hash table entries: 262144 (order: 10, 4194304 bytes) [ 1951.051/8] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes) [ 1951.052/8] TCP portaddr_bind hash table entries: 65536 (order: 8, 1048576 bytes) [ 1951.053/8] TCP listening hash table entries: 65536 (order: 8, 1048576 bytes) [ 1951.055/8] TCP: Hash tables configured (established 262144 bind 65536 listening 65536) [ 1951.055/8] TCP reno registered [ 1951.056/8] NET: Registered protocol family 1 [ 1951.057/8] RPC: Registered udp transport module. [ 1951.057/8] RPC: Registered tcp transport module. [ 1951.058/8] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 1952.710/8] /proc/octeon_perf: Octeon performace counter interface loaded [ 1952.713/8] msgmni has been set to 7906 [ 1952.715/1] alg: No test for stdrng (krng) [ 1952.715/8] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254) [ 1952.715/8] io scheduler noop registered [ 1952.715/8] io scheduler anticipatory registered [ 1952.715/8] io scheduler deadline registered [ 1952.716/8] io scheduler cfq registered (default) [ 1952.720/8] Ixia Backplane UART version 0.01 [ 1952.720/8] Fixed MDIO Bus: probed [ 1952.720/8] oprofile: using mips/octeon performance monitoring. [ 1952.720/8] NET: Registered protocol family 26 [ 1952.722/8] [ixroute] Initialized. [ 1952.722/8] TCP cubic registered [ 1952.723/8] NET: Registered protocol family 10 [ 1952.742/8] [ixroute6] Initialized. [ 1952.742/8] IPv6 over IPv4 tunneling driver [ 1952.742/8] NET: Registered protocol family 17 [ 1952.743/8] L2 lock: TLB refill 256 bytes [ 1952.743/8] L2 lock: General exception 128 bytes [ 1952.743/8] L2 lock: low-level interrupt 128 bytes [ 1952.743/8] L2 lock: interrupt 640 bytes [ 1952.743/8] L2 lock: memcpy 1152 bytes [ 1952.749/8] Freeing unused kernel memory: 9076k freed [ 1953.050/8] ixsysctl: module license 'Copyright 2002, Ixia Communications; all rights reserved' taints kernel. [ 1953.050/8] Disabling lock debugging due to kernel taint [ 1953.051/8] ixsysctl: ixsysctl_init: Ixia System Control Utility Module Aug 25 2011 19:38:20 [ 1953.090/a] ixllm: init_module: Ixia Link Layer Manager Aug 25 2011 19:37:57 [ 1953.126/7] pcie: TX FPGA Version 0x1107 [ 1953.126/7] pcie: RX FPGA Version 0x10e5 [ 1953.132/8] octeon_msi_irq_dispatcher_init, kernel instance 0 [ 1953.132/8] ixia_irq_msi_dispatcher_init [ 1953.195/2] cavium-ethernet: Cavium Networks Octeon SDK version 2.0.0-p4, build 373 [ 1953.195/2] Driver compiled with: USE_NAMEDBLOCK_FOR_FPA [ 1953.195/2] cavium-ethernet: Using dev: ixint0 as Ixia root dev [ 1953.195/2] everest_hw_init: kernel instance 0, cores_per_os: 12 [ 1953.195/2] octeon_ethernet.ko: Enable TX 1588 [ 1953.195/2] octeon_ethernet.ko: Enable RX 1588 [ 1953.196/2] nb name: ixia-platform-control-block size: 0x10000 addr: 0xfe15000 [ 1953.196/2] >> Core 2 coremask: fff [ 1953.196/2] cvm_eth_instance_count_add Instance count: 1 [ 1953.196/2] >> Instance 0 mac_offset: 1 fau_offset: 2044 group: 0 [ 1953.196/2] Reclaimed 0 WQE and 0 FPA entries from POW [ 1953.196/2] fpa 0: que-available: 1fb0 [ 1953.196/2] fpa 1: que-available: 1fc0 [ 1953.196/2] fpa 2: que-available: 53 [ 1953.196/2] cvm_oct_configure_common_hw: group 0 [ 1953.196/2] cvm_eth_get_interfaces_of_interest Adding interface 0 of type 5 [ 1953.196/2] Interface 0 has 1 ports (XAUI) [ 1953.196/2] Interface 1 has 1 ports (XAUI) [ 1953.196/2] cvmx_helper_interface_probe_mi: Not probing Interface type 8 [ 1953.196/2] cvmx_helper_interface_probe_mi: Not probing Interface type 9 [ 1953.196/2] Checking port 0, max_port: 0 num_ports: 1 [ 1953.196/2] ixia_probe_hw [ 1953.196/2] Bringing up device ixint0 (i/f: 0 port: 0) [ 1953.196/2] priv->tx_port 0 priv->tx_queue 0 [ 1953.196/2] cvm_oct_init_module dev->mtu: 14000 [ 1953.196/2] cvm_oct_rx_initialize: max_rx_cpus=12 [ 1953.196/2] IRQ request for 24 succeeded [ 1953.196/2] MSI Enable for msi_num 4 is location 0x80011f000000bc50 value 0x10 [ 1953.282/3] Basic DMA tests passed [ 1953.301/4] IXHOST mcb->dwBootRamBase = 0x800000000ffe9000 [ 1953.301/4] CPU Frequency: 600 MHz [ 1953.302/4] ADVERTISED FLAG = 0x0000000000008f8f [ 1953.302/4] dma_xmit_open: dma_idx: 0, tx_fifo_base: 0x8000c00000000000 [ 1953.302/4] MSI Enable for msi_num 0 is location 0x80011f000000bc50 value 0x11 [ 1953.302/4] CIU_INT0_EN0 = 0x10300000001 [ 1953.302/4] ixhostm: MessageQueueInit success [ 1953.302/4] Virtual queue base = 0x800000000fb20000 [ 1953.302/4] Base physical = 0xfb20000 [ 1953.302/4] OS instance = 0 [ 1953.302/4] Virtual chassis card map base = 0x800000000fbb0000 [ 1953.302/4] Virtual P2P rx_que_base = 0x800000000fb20000 [ 1953.302/4] [2 s. 276082 us] p2p_message_queue_init success [ 1953.302/4] IXHOST ver 3.0.0 [ 1953.322/7] hwstate: timestamp test passed [ 1953.617/2] [multinic] operation: + [ 1953.617/2] [multinic] device: ixint0 [ 1953.617/2] [multinic] id: 0 [ 1996.813/0] [1315571465 s. 798972 us] Refreshing topology Chassis X2 ... [ 1996.813/0] ---- Slot= 1 PortType=161 PortMap=0x0000ffff [ 1996.814/0] ---- Slot= 2 PortType= 83 PortMap=0x000000ff [ 2038.300/0] vcrash initializing [ 2040.299/8] core 8: &x a80000041f98fbd0 virt_to_phys(&x) 41f98fbd0 [ 2040.299/b] core 11: &x a80000041fa0bbd0 virt_to_phys(&x) 41fa0bbd0 [ 2040.299/a] core 10: &x a80000041f9cbbd0 virt_to_phys(&x) 41f9cbbd0 [ 2040.299/1] core 1: &x a80000041f87bbd0 virt_to_phys(&x) 41f87bbd0 [ 2040.299/2] core 2: &x a80000041f8bbbd0 virt_to_phys(&x) 41f8bbbd0 [ 2040.299/3] core 3: &x a80000041f8d7bd0 virt_to_phys(&x) 41f8d7bd0 [ 2040.299/5] core 5: &x a80000041f917bd0 virt_to_phys(&x) 41f917bd0 [ 2040.299/4] core 4: &x a80000041f8f7bd0 virt_to_phys(&x) 41f8f7bd0 [ 2040.299/0] core 0: &x ffffffffc03a3b70 virt_to_phys(&x) 57ffffffc03a3b70 [ 2040.299/b] core 11: virt_to_page(&x) a800000006870268 [ 2040.299/6] core 6: &x a80000041f953bd0 virt_to_phys(&x) 41f953bd0 [ 2040.299/9] core 9: &x a80000041f9afbd0 virt_to_phys(&x) 41f9afbd0 [ 2040.299/7] core 7: &x a80000041f96fbd0 virt_to_phys(&x) 41f96fbd0 [ 2040.299/a] core 10: virt_to_page(&x) a80000000686f468 [ 2040.299/1] core 1: virt_to_page(&x) a80000000686aae8 [ 2040.299/2] core 2: virt_to_page(&x) a80000000686b8e8 [ 2040.299/3] core 3: virt_to_page(&x) a80000000686bf08 [ 2040.299/5] core 5: virt_to_page(&x) a80000000686cd08 [ 2040.299/4] core 4: virt_to_page(&x) a80000000686c608 [ 2040.299/0] CPU 0 Unable to handle kernel paging request at virtual address 00000057c0d14640, epc == ffffffffc123a054, ra == ffffffffc123a030 [ 2040.299/6] core 6: virt_to_page(&x) a80000000686da28 [ 2040.299/9] core 9: virt_to_page(&x) a80000000686ee48 [ 2040.299/7] core 7: virt_to_page(&x) a80000000686e048 [ 2040.299/0] die: oom_log() temporarily disabled on this architecture [ 2040.299/0] Oops[#1]: [ 2040.299/0] Cpu 0 [ 2040.299/0] $ 0 : 0000000000000000 0000000000000000 00000057c0d14640 00000057ffffffc0 [ 2040.299/0] $ 4 : ffffffffc1240000 ffffffffc0ce0000 0000000000000000 0000000000020000 [ 2040.299/0] $ 8 : ffffffffc0ce0000 ffffffffffffffff fffffffffffffffb 0000000000000010 [ 2040.299/0] $12 : 0000000000000020 00000000000186a0 0000000000000009 0000000000000000 [ 2040.300/0] $16 : 0133ffffff20cba8 0000000000000100 ffffffffc123a000 ffffffffc0d0a220 [ 2040.300/0] $20 : ffffffffc0d09e20 ffffffffc0d09a20 ffffffffc0d09620 0000000000200200 [ 2040.300/0] $24 : 0000000000000002 ffffffffc000baa4 [ 2040.300/0] $28 : ffffffffc03a0000 ffffffffc03a3b70 ffffffffc03a0000 ffffffffc123a030 [ 2040.300/0] Hi : 00000000000b6854 [ 2040.300/0] Lo : 000000000000012b [ 2040.300/0] epc : ffffffffc123a054 vcrash+0x54/0x80 [vcrash] [ 2040.300/0] Tainted: P [ 2040.300/0] ra : ffffffffc123a030 vcrash+0x30/0x80 [vcrash] [ 2040.300/0] Status: 1000cce3 KX SX UX KERNEL EXL IE [ 2040.300/0] Cause : 00800008 [ 2040.300/0] BadVA : 00000057c0d14640 [ 2040.300/0] PrId : 000d0409 (Cavium Octeon+) [ 2040.300/0] Modules linked in: vcrash ixvaluelist(P) ixgremod(P) ixunc(P) kseusrmgr(P) evfmanager(P) filtermanager hwstate ixhostm octeon_dma octeon_ethernet octeon_mdiobus ixnam_binstats(P) octeon_msi pcie ixllm ixsysctl(P) nlproc_driver [ 2040.300/0] Process swapper (pid: 0, threadinfo=ffffffffc03a0000, task=ffffffffc03be580, tls=0000000000000000) [ 2040.300/0] Stack : ffffffffc03a0000 ffffffffc03a4788 ffffffffc0d08600 ffffffffc0065f28 [ 2040.300/0] ffffffffc03a3b90 ffffffffc03a3b90 0000000000000100 0000000000000001 [ 2040.300/0] ffffffffc03a4788 0000000000000101 0000000000000008 ffffffffc0cc31b0 [ 2040.300/0] 000000000000000a 0000000000000000 ffffffffc0d07b80 ffffffffc00609e0 [ 2040.300/0] 0000000000000000 8001070000000000 8001070000000218 8001070000000200 [ 2040.300/0] 8001070000000108 ffffffffc0ce0000 0000000000010000 000000000fde4300 [ 2040.300/0] ffffffffc03a0000 ffffffffc0060adc 0000000000000000 ffffffffc0060cb0 [ 2040.300/0] 0000000000000000 ffffffffc000ba7c a8000000068a0058 0000000000000000 [ 2040.300/0] 0000000000000001 ffffffffc0ce0000 ffffffffc0ce0000 000000000fdd0000 [ 2040.300/0] 0000000000000000 ffffffffc0000888 0000000000000000 0000000000000000 [ 2040.300/0] ... [ 2040.300/0] Call Trace: [ 2040.300/0] [] vcrash+0x54/0x80 [vcrash] [ 2040.300/0] [] run_timer_softirq+0x198/0x23c [ 2040.300/0] [] __do_softirq+0xd8/0x188 [ 2040.300/0] [] do_softirq+0x4c/0x6c [ 2040.300/0] [] irq_exit+0x48/0x8c [ 2040.300/0] [] plat_irq_dispatch+0x128/0x150 [ 2040.300/0] [] ret_from_irq+0x0/0x4 [ 2040.300/0] [] r4k_wait+0x20/0x40 [ 2040.300/0] [] cpu_idle+0x60/0x9c [ 2040.300/0] [] start_kernel+0x3e8/0x404 [ 2040.300/0] [ 2040.300/0] [ 2040.300/0] Code: 64424680 0043102d 3c04c124 2402fffc 8f850020 6484a2d8 00c23024 0c001c23 [ 2040.300/0] Kernel panic - not syncing: Fatal exception in interrupt [ 2040.300/0] Call Trace: [ 2040.300/0] [] dump_stack+0x8/0x34 [ 2040.300/0] [] panic+0x7c/0x168 [ 2040.300/0] [] die+0x114/0x11c [ 2040.300/0] [] do_page_fault+0x314/0x39c [ 2040.300/0] [] ret_from_exception+0x0/0x8 [ 2040.300/0] [] vcrash+0x54/0x80 [vcrash] [ 2040.300/0] [] run_timer_softirq+0x198/0x23c [ 2040.300/0] [] __do_softirq+0xd8/0x188 [ 2040.300/0] [] do_softirq+0x4c/0x6c [ 2040.300/0] [] irq_exit+0x48/0x8c [ 2040.300/0] [] plat_irq_dispatch+0x128/0x150 [ 2040.300/0] [] ret_from_irq+0x0/0x4 [ 2040.300/0] [] r4k_wait+0x20/0x40 [ 2040.300/0] [] cpu_idle+0x60/0x9c [ 2040.300/0] [] start_kernel+0x3e8/0x404 [ 2040.300/0] [ 2040.300/0] ixhost: ENABLE Tx message checksum [ 2040.300/0] ixhost: DISABLE Rx message checksum [ 2040.300/0] ixhost: ENABLE SGC Communication mode [ 2040.300/0] ixhost: ENABLE Lcpu Interrupt Host [ 2040.300/0] ixhost: ENABLE Host Interrupt Lcpu [ 2040.300/0] ixhost: ENABLE 32-bit Pointer mode [ 2040.300/0] ixhost: Advertised BCAST=0x0000 [ 2040.300/0] TxFrameCount= 1097 TxByteCount= 129484 [ 2040.300/0] H/W TxFifoBase=0xa80000041e4dc000 TxFifoEnd=0xa80000041e4dfff0 TxFifoSize=0x3ff0 [ 2040.300/0] RRN=0xa80000041e4dfff0 RRB=0xa80000041e4dfff8 TW=0xa80000041e4dfff4 [ 2040.301/0] [ 2040.301/0] H/W RxFifoBase=0x800000000ff29000 RxFifoEnd=0x800000000ff38ff8 RxFifoSize=0xfff8 [ 2040.301/0] RW=0x800000000ff38ff8 TR=0x800000000ff38ffc [ 2040.301/0] RxWrite=0x800000000ff38ff8 RxRead=0xa80000041e4dfff0 TxWrite=0xa80000041e4dfff4 TxRead=0x800000000ff38ffc [ 2040.301/0] ImagTransmitBase=0xa80000041e4dc000 WritePos=0x3a3c ReadPos=0x3a3c00000000 PrevWrite=0xa80000041e4dfa00 [ 2040.301/0] Receive[normal] [ 2040.301/0] WritePtr : 0x800096ac0ff2ca3c [ 2040.301/0] ReadPtr : 0x800000000ff326ac [ 2040.301/0] Advertised Read Ptr : 0x000096ac [ 2040.301/0] PrevRead : 0x800000000ff32674 [ 2040.301/0] Receive[broadcast] [ 2040.301/0] WritePtr : 0x800000000ff39000 [ 2040.301/0] ReadPtr : 0x800000000ff39000 [ 2040.301/0] Advertised Read Ptr : 0x00000000 [ 2040.301/0] PrevRead : 0x800000000ff39000 [ 2040.301/0] Octeon board_info [ 2040.301/0] ----- head=19 tail=16 buffer: [ 2040.301/0] pData = 0xa8000000018ca800 len = 64 [ 2040.301/0] (0xa8000000018ca800) 0x0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 2040.301/0] (0xa8000000018ca810) 0x0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 2040.301/0] (0xa8000000018ca820) 0x0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 2040.301/0] (0xa8000000018ca830) 0x0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 2040.301/0] [ 2040.301/0] p2h_fifo_len: 0000 p2p_fifo_len: 0000 [ 2040.301/0] p2h_count: 25524, p2p_count: 0 [ 2040.301/0] fpa 0: que-available: 1fb0 [ 2040.301/0] fpa 1: que-available: 1fc0 [ 2040.301/0] fpa 2: que-available: 53 [ 2040.301/0] ixhost::panic_handler: setting kProcessorHalted bit [ 2040.301/0] ixhost::panic_handler: done [ 2041.634/0] Reclaimed 0 WQE and 0 FPA entries from POW --Boundary-00=_QNhaO/I996LuNwl Content-Type: text/x-csrc; charset="UTF-8"; name="vcrash.c" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="vcrash.c" /* * A module that should crash the kernel on mips master core by using virt_to_page on a * softirq stack address. * * Cosmin Ratiu */ #include #include #include #include #include struct timer_list t[NR_CPUS]; void vcrash(unsigned long data) { int x; printk("core %i: &x %p virt_to_phys(&x) %lx\n", smp_processor_id(), &x, virt_to_phys(&x)); printk("core %i: virt_to_page(&x) %p\n", smp_processor_id(), virt_to_page(&x)); } int vcrash_init(void) { int cpu; printk("vcrash initializing\n"); for_each_online_cpu(cpu) { init_timer(t + cpu); t[cpu].expires = jiffies + 2 * HZ; t[cpu].function = vcrash; add_timer_on(t + cpu, cpu); } return 0; } void vcrash_exit(void) { int cpu; for_each_online_cpu(cpu) { del_timer_sync(t + cpu); } printk("vcrash exiting\n"); } module_init(vcrash_init); module_exit(vcrash_exit); MODULE_AUTHOR("Cosmin Ratiu"); MODULE_LICENSE("GPL"); --Boundary-00=_QNhaO/I996LuNwl Content-Type: text/x-patch; charset="UTF-8"; name="tcp-md5-crash.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="tcp-md5-crash.diff" Change 3360379 by cratiu@cratiu on 2011/09/02 09:44:48 *pending* TCP/md5: Switch from a stack var to a percpu var to avoid a crash. tcp_v4_send_ack uses a stack variable to construct the TCP header for the response packet. When using TCP MD5 signatures on mips architecture a crash happens sometimes when the current core is the master core using the initial stack allocated in vmlinux. The reason for this is that the initial stack is mapped in kseg2 so it can't be directly translated to a physical address by virt_to_phys as expected by sg_set_buf from the following call chain: > (optimized: sg_set_buf) > sg_init_one+0x58/0xa4 > tcp_md5_hash_header+0x30/0x64 > tcp_v4_md5_hash_hdr+0xb4/0x134 > tcp_v4_send_ack+0x16c/0x25c > (optimized: tcp_v4_timewait_ack) > tcp_v4_rcv+0x1b3c/0x1e58 As a temporary fix that should not affect performance, the stack variable is converted in a percpu variable allocated at boot time. Affected files ... ... //packages/linux_2.6.32/main/src/include/net/tcp.h#6 edit ... //packages/linux_2.6.32/main/src/net/ipv4/tcp.c#11 edit ... //packages/linux_2.6.32/main/src/net/ipv4/tcp_ipv4.c#15 edit include/net/tcp.h | 10 +++++++++ net/ipv4/tcp.c | 5 ++++ net/ipv4/tcp_ipv4.c | 53 ++++++++++++++++++++++++---------------------------- 3 files changed, 40 insertions(+), 28 deletions(-) Signed-off-by: Cosmin Ratiu --- src/include/net/tcp.h~ +++ src/include/net/tcp.h @@ -1570,5 +1570,15 @@ return skc->skc_net_params->tcp.rmem; } +struct tcp_reply_hdr { + struct tcphdr th; + __be32 opt[(TCPOLEN_TSTAMP_ALIGNED >> 2) +#ifdef CONFIG_TCP_MD5SIG + + (TCPOLEN_MD5SIG_ALIGNED >> 2) +#endif + ]; +}; + +extern struct tcp_reply_hdr *tcp_rep_percpu; #endif /* _TCP_H */ --- src/net/ipv4/tcp.c~ +++ src/net/ipv4/tcp.c @@ -3150,6 +3150,11 @@ tcp_hashinfo.lhash_size); tcp_register_congestion_control(&tcp_reno); + + /* Hack alert: a proper fix should be implemented for the md5 crash */ + tcp_rep_percpu = alloc_percpu(struct tcp_reply_hdr); + if (!tcp_rep_percpu) + panic("Cannot allocate per cpu tcp reply hdr\n"); } EXPORT_SYMBOL(tcp_close); --- src/net/ipv4/tcp_ipv4.c~ +++ src/net/ipv4/tcp_ipv4.c @@ -680,6 +680,8 @@ SOCK_STAT_INC(groupptr, TcpRstSent, skb_get_portid(skb)); } +struct tcp_reply_hdr *tcp_rep_percpu; + /* The code following below sending ACKs in SYN-RECV and TIME-WAIT states outside socket context is ugly, certainly. What can I do? */ @@ -691,53 +693,48 @@ int reply_flags, u32 vlanprio) { struct tcphdr *th = tcp_hdr(skb); - struct { - struct tcphdr th; - __be32 opt[(TCPOLEN_TSTAMP_ALIGNED >> 2) -#ifdef CONFIG_TCP_MD5SIG - + (TCPOLEN_MD5SIG_ALIGNED >> 2) -#endif - ]; - } rep; + struct tcp_reply_hdr *rep; struct ip_reply_arg arg; - memset(&rep.th, 0, sizeof(struct tcphdr)); + rep = per_cpu_ptr(tcp_rep_percpu, get_cpu()); + + memset(&rep->th, 0, sizeof(struct tcphdr)); memset(&arg, 0, sizeof(arg)); - arg.iov[0].iov_base = (unsigned char *)&rep; - arg.iov[0].iov_len = sizeof(rep.th); + arg.iov[0].iov_base = (unsigned char *)rep; + arg.iov[0].iov_len = sizeof(rep->th); if (ts) { - rep.opt[0] = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | + rep->opt[0] = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP); - rep.opt[1] = htonl(tcp_time_stamp); - rep.opt[2] = htonl(ts); + rep->opt[1] = htonl(tcp_time_stamp); + rep->opt[2] = htonl(ts); arg.iov[0].iov_len += TCPOLEN_TSTAMP_ALIGNED; } /* Swap the send and the receive. */ - rep.th.dest = th->source; - rep.th.source = th->dest; - rep.th.doff = arg.iov[0].iov_len / 4; - rep.th.seq = htonl(seq); - rep.th.ack_seq = htonl(ack); - rep.th.ack = 1; - rep.th.window = htons(win); + rep->th.dest = th->source; + rep->th.source = th->dest; + rep->th.doff = arg.iov[0].iov_len / 4; + rep->th.seq = htonl(seq); + rep->th.ack_seq = htonl(ack); + rep->th.ack = 1; + rep->th.window = htons(win); #ifdef CONFIG_TCP_MD5SIG if (key) { int offset = (ts) ? 3 : 0; - rep.opt[offset++] = htonl((TCPOPT_NOP << 24) | - (TCPOPT_NOP << 16) | - (TCPOPT_MD5SIG << 8) | - TCPOLEN_MD5SIG); + rep->opt[offset++] = htonl((TCPOPT_NOP << 24) | + (TCPOPT_NOP << 16) | + (TCPOPT_MD5SIG << 8) | + TCPOLEN_MD5SIG); arg.iov[0].iov_len += TCPOLEN_MD5SIG_ALIGNED; - rep.th.doff = arg.iov[0].iov_len/4; + rep->th.doff = arg.iov[0].iov_len/4; - tcp_v4_md5_hash_hdr((__u8 *) &rep.opt[offset], + tcp_v4_md5_hash_hdr((__u8 *) &rep->opt[offset], key, ip_hdr(skb)->saddr, - ip_hdr(skb)->daddr, &rep.th); + ip_hdr(skb)->daddr, &rep->th); } #endif arg.flags = reply_flags; --Boundary-00=_QNhaO/I996LuNwl-- From david.daney@cavium.com Fri Sep 9 18:59:12 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Sep 2011 18:59:17 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9569 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491050Ab1IIQ7M (ORCPT ); Fri, 9 Sep 2011 18:59:12 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 09 Sep 2011 10:00:22 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 9 Sep 2011 09:59:09 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 9 Sep 2011 09:59:09 -0700 Message-ID: <4E6A45D9.6090706@cavium.com> Date: Fri, 09 Sep 2011 09:59:05 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Cosmin Ratiu CC: linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: Octeon crash in virt_to_page(&core0_stack_variable) References: <201109091623.29000.cratiu@ixiacom.com> In-Reply-To: <201109091623.29000.cratiu@ixiacom.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 09 Sep 2011 16:59:09.0459 (UTC) FILETIME=[CACEF630:01CC6F11] X-archive-position: 31055 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4945 Content-Length: 2286 Lines: 60 On 09/09/2011 06:23 AM, Cosmin Ratiu wrote: > Hello, > > I've been investigating a strange crash and I wanted to ask for your help. > The crash happens when virt_to_page is called with an address from the softirq > stack of core 0 on Cavium Octeon. It may happen on other MIPS processors as > well, but I'm not sure. > > I've attached a simple kernel module to demonstrate the problem and the output > of dmesg + the crash. Two seconds after inserting the module, the kernel > should crash. > > From what I've dug up in the kernel sources, it seems the stack for the first > idle task resides in the data segment (mapped in kseg2) while the rest are > allocated with kmalloc in __cpu_up() and reside in a different area (CAC_BASE > upwards). > It seems virt_to_phys produces bogus results for kseg2 and after that, > virt_to_page crashes trying to access invalid memory. > > This problem was discovered when doing BGP traffic with the TCP MD5 option > activated, where the following call chain caused a crash: > > * tcp_v4_rcv > * tcp_v4_timewait_ack > * tcp_v4_send_ack -> follow stack variable rep.th > * tcp_v4_md5_hash_hdr > * tcp_md5_hash_header > * sg_init_one > * sg_set_buf > * virt_to_page > > I noticed that tcp_v4_send_reset uses a similar stack variable and also calls > tcp_v4_md5_hash_hdr, so it has the same problem. > > I don't fully understand octeon mm details, so I wanted to bring up this issue > in order to find a proper fix. > To avoid the problem, I've implemented a quick hack to declare those variables > percpu instead of on the stack, so they would also reside in CAC_BASE upwards. > I've attached a patch against 2.6.32 for reference. > > Cosmin. > > [...] > [ 2040.300/0] Call Trace: > [ 2040.300/0] [] vcrash+0x54/0x80 [vcrash] > [ 2040.300/0] [] run_timer_softirq+0x198/0x23c > [ 2040.300/0] [] __do_softirq+0xd8/0x188 ^^^^^^^^^ CKSEG2 addresses detected! You are using the out-of-tree mapped kernel patch which mucks about with the implementation of virt_to_phys(). Can you reproduce the TCP related crash in an unpatched kernel? If not, then it would point to problems in the out-of-tree patches you have applied. David Daney From afleming@gmail.com Sat Sep 10 01:22:38 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Sep 2011 01:22:44 +0200 (CEST) Received: from mail-gy0-f177.google.com ([209.85.160.177]:33453 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491753Ab1IIXWi convert rfc822-to-8bit (ORCPT ); Sat, 10 Sep 2011 01:22:38 +0200 Received: by gyg13 with SMTP id 13so2218704gyg.36 for ; Fri, 09 Sep 2011 16:22:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=T58vLqBLP+43952JX17AHvMgSHgz2DsSIzSOncjS32o=; b=WX9KduO75zSoh65tqEPo6sympRkd+is3AbrORupL5+5KX7c3BbvWTRvz4G3F7tnsCA ru5HwyKEC15v81sc9pr7ykTn+EfUSeg4CR2rhPMdmdGK3hbKV/AHuuZnrCPVCtA46FPq Sf/0nJwxcjyyShfD4EQtVayvIhD2XsVo1WZxg= MIME-Version: 1.0 Received: by 10.236.173.129 with SMTP id v1mr296416yhl.25.1315610552404; Fri, 09 Sep 2011 16:22:32 -0700 (PDT) Received: by 10.236.69.169 with HTTP; Fri, 9 Sep 2011 16:22:32 -0700 (PDT) In-Reply-To: <1314820906-14004-3-git-send-email-david.daney@cavium.com> References: <1314820906-14004-1-git-send-email-david.daney@cavium.com> <1314820906-14004-3-git-send-email-david.daney@cavium.com> Date: Fri, 9 Sep 2011 18:22:32 -0500 Message-ID: Subject: Re: [PATCH 2/3] netdev/of/phy: Add MDIO bus multiplexer support. From: Andy Fleming To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, "David S. Miller" Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 31056 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: afleming@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5124 Content-Length: 2026 Lines: 55 On Wed, Aug 31, 2011 at 3:01 PM, David Daney wrote: > This patch adds a somewhat generic framework for MDIO bus > multiplexers.  It is modeled on the I2C multiplexer. > > The multiplexer is needed if there are multiple PHYs with the same > address connected to the same MDIO bus adepter, or if there is > insufficient electrical drive capability for all the connected PHY > devices. > > Conceptually it could look something like this: > >                   ------------------ >                   | Control Signal | >                   --------+--------- >                           | >  ---------------   --------+------ >  | MDIO MASTER |---| Multiplexer | >  ---------------   --+-------+---- >                     |       | >                     C       C >                     h       h >                     i       i >                     l       l >                     d       d >                     |       | >     ---------       A       B   --------- >     |       |       |       |   |       | >     | PHY@1 +-------+       +---+ PHY@1 | >     |       |       |       |   |       | >     ---------       |       |   --------- >     ---------       |       |   --------- >     |       |       |       |   |       | >     | PHY@2 +-------+       +---+ PHY@2 | >     |       |                   |       | >     ---------                   --------- > > This framework configures the bus topology from device tree data.  The > mechanics of switching the multiplexer is left to device specific > drivers. > > The follow-on patch contains a multiplexer driven by GPIO lines. It's amazing how various companies' board designers have come up with the same brain-dead PHY topologies. We (Freescale) have some similar code in our tree, but it's not this generically applicable. > > Signed-off-by: David Daney > Cc: Grant Likely > Cc: "David S. Miller" Looks good to me. Acked-by: Andy Fleming From post@pfrst.de Sun Sep 11 13:15:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Sep 2011 13:15:55 +0200 (CEST) Received: from mail1.pearl-online.net ([62.159.194.147]:58444 "EHLO mail1.pearl-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491009Ab1IKLPl (ORCPT ); Sun, 11 Sep 2011 13:15:41 +0200 Received: from Mobile0.Peter (109.125.101.165.dynamic.cablesurf.de [109.125.101.165]) by mail1.pearl-online.net (Postfix) with ESMTPA id 92CEC2D505; Sun, 11 Sep 2011 13:15:27 +0200 (CEST) Received: from Indigo2.Peter (Indigo2.Peter [192.168.1.28]) by Mobile0.Peter (8.12.6/8.12.6/Sendmail/Linux 2.2.13) with ESMTP id p8BCrTAq001120; Sun, 11 Sep 2011 12:53:29 GMT Received: from Indigo2.Peter (localhost [127.0.0.1]) by Indigo2.Peter (8.12.6/8.12.6/Sendmail/Linux 2.6.14-rc2-ip28) with ESMTP id p8BBEVL5004163; Sun, 11 Sep 2011 13:14:31 +0200 Received: from localhost (pf@localhost) by Indigo2.Peter (8.12.6/8.12.6/Submit) with ESMTP id p8BBEVxP004160; Sun, 11 Sep 2011 13:14:31 +0200 X-Authentication-Warning: Indigo2.Peter: pf owned process doing -bs Date: Sun, 11 Sep 2011 13:14:31 +0200 (CEST) From: peter fuerst X-X-Sender: pf@Indigo2.Peter Reply-To: post@pfrst.de To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: attilio.fiandrotti@gmail.com Subject: [PATCH] Impact video driver for SGI Indigo2 Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed X-archive-position: 31057 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: post@pfrst.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5434 Content-Length: 49495 Lines: 1523 Here's an attempt to bloat the linux source a bit more ;-) This patch brings, yet missing, parts that make a Linux-driven Indigo2 Impact (IP28 and most probably IP22-Impact) an usable desktop-machine "out of the box". The driver provides the framebuffer console and an interface for the Xserver (mmap'ing a DMA-pool to the shadow framebuffer and doing the necessary cacheflush). Meanwhile only a few files are affected and obviously no side-effects to other parts of the kernel are to be expected. BTW: it would be appreciated, if someone could verify, that this driver also works for IP22 Impact. Signed-off-by: peter fuerst --- 1) Preparation drivers/video/Kconfig | 6 ++++++ drivers/video/Makefile | 1 + drivers/video/logo/Kconfig | 2 +- arch/mips/sgi-ip22/ip22-setup.c | 37 +++++++++++++++++++++++++++++++++++++ arch/mips/configs/ip28_defconfig | 1 + 5 files changed, 46 insertions(+), 1 deletions(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 549b960..43dbc9f 100644 --- a/drivers/video/Kconfig Thu Jan 1 00:00:00 1970 +++ b/drivers/video/Kconfig Thu Mar 10 23:37:58 2011 @@ -2383,6 +2383,12 @@ config FB_PUV3_UNIGFX Choose this option if you want to use the Unigfx device as a framebuffer device. Without the support of PCI & AGP. +config FB_IMPACT + tristate "SGI Indigo2 Impact graphics support" + depends on FB && (SGI_IP22 || SGI_IP28 || SGI_IP30) + help + SGI Indigo2 Impact (SI/HI/MI) graphics card support. + source "drivers/video/omap/Kconfig" source "drivers/video/omap2/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 8b83129..278c8fa 100644 --- a/drivers/video/Makefile Thu Jan 1 00:00:00 1970 +++ b/drivers/video/Makefile Thu Mar 10 23:44:40 2011 @@ -141,6 +141,7 @@ obj-$(CONFIG_FB_MSM) += msm/ obj-$(CONFIG_FB_NUC900) += nuc900fb.o obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o obj-$(CONFIG_FB_PUV3_UNIGFX) += fb-puv3.o +obj-$(CONFIG_FB_IMPACT) += impact.o # Platform or fallback drivers go here obj-$(CONFIG_FB_UVESA) += uvesafb.o diff --git a/drivers/video/logo/Kconfig b/drivers/video/logo/Kconfig index 39ac49e..3ac6da4 100644 --- a/drivers/video/logo/Kconfig Thu Jan 1 00:00:00 1970 +++ b/drivers/video/logo/Kconfig Fri May 8 00:51:01 2009 @@ -54,7 +54,7 @@ config LOGO_PARISC_CLUT224 config LOGO_SGI_CLUT224 bool "224-color SGI Linux logo" - depends on SGI_IP22 || SGI_IP27 || SGI_IP32 || X86_VISWS + depends on SGI_IP22 || SGI_IP27 || SGI_IP28 || SGI_IP30 || SGI_IP32 || X86_VISWS default y config LOGO_SUN_CLUT224 diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 5e66213..085b612 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c Thu Jan 1 00:00:00 1970 +++ b/arch/mips/sgi-ip22/ip22-setup.c Fri May 8 01:05:13 2009 @@ -96,4 +96,41 @@ void __init plat_mem_setup(void) } } #endif +#if defined(CONFIG_FB_IMPACT) + { + extern void setup_impact_earlycons(void); + /* + * Get graphics info before it is overwritten... + * E.g. @ 9000000020f02f78: ffffffff9fc6d770,900000001f000000 + */ +#ifdef CONFIG_ARC64 + ULONG * (*__vec)(void) = (typeof(__vec)) + ((ULONG*)PROMBLOCK->pvector)[8]; + ULONG *gfxinfo = (*__vec)(); +#else + /* supposed to work on both 32/64-bit kernels. */ + int (*__vec)(void) = (typeof(__vec)) + (long) ((int*)PROMBLOCK->pvector)[8]; + int *gfxinfo = (typeof(gfxinfo)) (*__vec)(); +#endif + /* See note on __pa() in impact.c */ + sgi_gfxaddr = __pa((void*)gfxinfo[1]); + if (sgi_gfxaddr < 0x1f000000 || 0x1fa00000 <= sgi_gfxaddr) + sgi_gfxaddr = 0; + /* + * Early params are not yet avaialble, so this setting + * must be done in the ARCS environment. + */ + ctype = ArcGetEnvironmentVariable("OSLoadOptions"); + if (!ctype || !strstr(ctype, "impact=noearly")) +#ifndef CONFIG_EARLY_PRINTK + if (ctype && strstr(ctype, "impact=early")) +#endif + setup_impact_earlycons(); + + printk(KERN_DEBUG "ARCS gfx info @ %p: %p,%p\n", + gfxinfo, (void*)gfxinfo[0], (void*)gfxinfo[1]); + printk(KERN_INFO "SGI graphics system @ 0x%08lx\n", sgi_gfxaddr); + } +#endif } diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 4dbf626..b316c86 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -78,3 +78,4 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_HW is not set # CONFIG_CRC32 is not set +CONFIG_FB_IMPACT=y 2) The driver drivers/video/impact.c | 1154 ++++++++++++++++++++++++++++++++++++++++++++++++ include/video/impact.h | 210 +++++++++ 2 files changed, 1364 insertions(+), 0 deletions(-) diff --git a/drivers/video/impact.c b/drivers/video/impact.c new file mode 100644 index 0000000..5ffc948 --- /dev/null Wed Dec 8 00:46:04 2004 +++ b/drivers/video/impact.c Mon Jul 25 00:06:58 2011 @@ -0,0 +1,1154 @@ +/* + * linux/drivers/video/impactsr.c -- SGI Octane MardiGras (IMPACTSR) graphics + * linux/drivers/video/impact.c -- SGI Indigo2 MardiGras (IMPACT) graphics + * + * Copyright (c) 2004-2006 by Stanislaw Skowronek (skylark@linux-mips.org) + * Adapted to Indigo2 by pf, 2005,2006,2009,2011 (post@pfrst.de) + * + * Based on linux/drivers/video/skeletonfb.c + * + * This driver, as most of the IP30 (SGI Octane) port, is a result of massive + * amounts of reverse engineering and trial-and-error. If anyone is interested + * in helping with it, please contact me: . + * + * The basic functions of this driver are filling and blitting rectangles. + * To achieve the latter, two DMA operations are used on Impact. It is unclear + * to me, why is it so, but even Xsgi (the IRIX X11 server) does it this way. + * It seems that fb->fb operations are not operational on these cards. + * + * For this purpose, a kernel DMA pool is allocated (pool number 0). This pool + * is (by default) 64kB in size. An ioctl could be used to set the value at + * run-time. Applications can use this pool, however proper locking has to be + * guaranteed. Kernel should be locked out from this pool by an ioctl. + * + * The IMPACTSR is quite well worked-out currently, except for the Geometry + * Engines (GE11). Any information about use of those devices would be very + * useful. It would enable a Linux OpenGL driver, as most of OpenGL calls are + * supported directly by the hardware. So far, I can't initialize the GE11. + * Verification of microcode crashes the graphics. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_64BIT +#error (S)he, who can afford Impact-graphics, shall afford a 64bit-kernel also! +#endif +#ifdef CONFIG_SGI_IP30 +# include +# define IPNR 30 +#else +# if defined(CONFIG_SGI_IP22) +# define IPNR 22 +# elif defined(CONFIG_SGI_IP26) +# define IPNR 26 +# else +# define IPNR 28 +# endif +#endif +#define isSR (IPNR > 28) /* avoid nasty #if... where possible. */ +#include