From dengcheng.zhu@gmail.com Mon Aug 1 12:13:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 12:14:01 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:62714 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491137Ab1HAKN4 convert rfc822-to-8bit (ORCPT ); Mon, 1 Aug 2011 12:13:56 +0200 Received: by yxj20 with SMTP id 20so3501949yxj.36 for ; Mon, 01 Aug 2011 03:13:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=5rfmg5VHVCeYO3pSpVmJpCyiIlomfIme0OILFD5KBBM=; b=MEwwKfBUd3NZDl2xUrTCjzEL4s+o2pNryeoaag1M7TD9yXwIXDpfiFUbw+hlrPhg01 GDumaBz4z6pjxdBqL92s0hoEB7dbU356OeeaXT6xJm/RlueW2DXqv+bJdOG9fv8fLBLI 0vcQEty0NR2GOFKxp14UB+//HUlCI7wIlj6Yk= MIME-Version: 1.0 Received: by 10.236.77.227 with SMTP id d63mr3143628yhe.299.1312193630174; Mon, 01 Aug 2011 03:13:50 -0700 (PDT) Received: by 10.236.105.130 with HTTP; Mon, 1 Aug 2011 03:13:49 -0700 (PDT) In-Reply-To: References: <1311852512-7340-1-git-send-email-dengcheng.zhu@gmail.com> <1311852512-7340-2-git-send-email-dengcheng.zhu@gmail.com> <20110728115330.GA29899@linux-mips.org> Date: Mon, 1 Aug 2011 18:13:49 +0800 Message-ID: Subject: Re: [PATCH 1/2] PCI: make pci_claim_resource() work with conflict resources as appropriate From: Deng-Cheng Zhu To: Bjorn Helgaas , Ralf Baechle Cc: jbarnes@virtuousgeek.org, torvalds@linux-foundation.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, eyal@mips.com, zenon@mips.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 30776 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 274 Content-Length: 2118 Lines: 48 It was found that PCI quirks claim resources (by calling pci_claim_resource()) *BEFORE* pcibios_fixup_bus() is called. In pcibios_fixup_bus(), pci_bus->resource[0] for the root bus DOES point to msc_io_resource. If PCI quirks do the resource claim after the arch-defined pcibios_fixup_bus() being called, then the problem with Malta goes away. So, it looks like 2 solutions out there: 1) To manage the call sequence. This seems not a desired one as it affects other arches. 2) To raise the start point of the system controller's io_resource in mips_pcibios_init() in arch/mips/mti-malta/malta-pci.c. This will place PCI quirks' resources at the same level of the system controller's resources. Ralf and Bjorn, which one sounds good to you? Deng-Cheng 2011/7/30 Bjorn Helgaas : > On Fri, Jul 29, 2011 at 12:32 AM, Deng-Cheng Zhu > wrote: >> I noticed that at 79896cf42f Linus changed the function from insert_resource() >> to request_resource() (and later evolved into request_resource_conflict()) and >> he explained the reason. So, in the NIC's case, the problem is that in >> pci_claim_resource() the function pci_find_parent_resource() returns the root >> (0x0-0xffffff) rather than the MSC PCI I/O (0x1000-0xffffff). > > This seems like the real problem: PCI has the wrong idea of the > resources available on bus 00.  The pci_bus->resource[0] for bus 00 > points to ioport_resource (the default put there by pci_create_bus()), > when it should point to to msc_io_resource instead. > > Some architectures fill in the pci_bus->resource[] array directly for > host bridges (for examples, try 'grep -r "resource\[0\] = " arch/'). > On x86 and ia64, we use pci_bus_remove_resources() and > pci_bus_add_resource(), and I'd prefer that style for new code because > it hides some ugly implementation details. > > I'm a little puzzled that we don't see this problem on more > architectures.  The grep above only found a few arches that update the > root bus resources.  I would expect most of the ones it didn't find to > be broken the same way Malta is. > > Bjorn > From florian@openwrt.org Mon Aug 1 12:22:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 12:22:52 +0200 (CEST) Received: from zmc.proxad.net ([212.27.53.206]:52677 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491141Ab1HAKWp (ORCPT ); Mon, 1 Aug 2011 12:22:45 +0200 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 13DC12F1DE3; Mon, 1 Aug 2011 12:22:45 +0200 (CEST) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id h2ROvLs41vQi; Mon, 1 Aug 2011 12:22:44 +0200 (CEST) Received: from flexo.priv.staff.proxad.net (bobafett.staff.proxad.net [213.228.1.121]) by zmc.proxad.net (Postfix) with ESMTPSA id C54C32F1E84; Mon, 1 Aug 2011 12:22:44 +0200 (CEST) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 3/3] MIPS: introduce CPU_R4K_CACHE_TLB Date: Mon, 1 Aug 2011 12:26:22 +0200 Message-Id: <1312194382-3706-3-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1312194382-3706-1-git-send-email-florian@openwrt.org> References: <1312194382-3706-1-git-send-email-florian@openwrt.org> X-archive-position: 30777 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 281 Content-Length: 2260 Lines: 58 R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to save some lines in arch/mips/mm/Makefile Signed-off-by: Florian Fainelli --- arch/mips/Kconfig | 4 ++++ arch/mips/mm/Makefile | 16 +--------------- 2 files changed, 5 insertions(+), 15 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 44eebc7..0150745 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1811,6 +1811,10 @@ config CPU_R4K_FPU bool default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) +config CPU_R4K_CACHE_TLB + bool + default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + choice prompt "MIPS MT options" diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 4d8c162..04ece1b5 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -11,24 +11,10 @@ obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o -obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o -obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5500) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o -obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o -obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o -- 1.7.4.1 From florian@openwrt.org Mon Aug 1 12:22:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 12:23:18 +0200 (CEST) Received: from zmc.proxad.net ([212.27.53.206]:52675 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491134Ab1HAKWp (ORCPT ); Mon, 1 Aug 2011 12:22:45 +0200 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id F265C2F1E8A; Mon, 1 Aug 2011 12:22:44 +0200 (CEST) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aaWBMDIpTRxb; Mon, 1 Aug 2011 12:22:44 +0200 (CEST) Received: from flexo.priv.staff.proxad.net (bobafett.staff.proxad.net [213.228.1.121]) by zmc.proxad.net (Postfix) with ESMTPSA id BFE252F1E55; Mon, 1 Aug 2011 12:22:44 +0200 (CEST) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 2/3] MIPS: introduce CPU_R4K_FPU Date: Mon, 1 Aug 2011 12:26:21 +0200 Message-Id: <1312194382-3706-2-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1312194382-3706-1-git-send-email-florian@openwrt.org> References: <1312194382-3706-1-git-send-email-florian@openwrt.org> X-archive-position: 30778 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 282 Content-Length: 2168 Lines: 58 R4K-style CPUs have this boolean defined by default. Allows us to remove some lines in arch/mips/kernel/Makefile Signed-off-by: Florian Fainelli --- arch/mips/Kconfig | 4 ++++ arch/mips/kernel/Makefile | 17 +---------------- 2 files changed, 5 insertions(+), 16 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9f4ade4..44eebc7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1807,6 +1807,10 @@ config CPU_GENERIC_DUMP_TLB bool default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX) +config CPU_R4K_FPU + bool + default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + choice prompt "MIPS MT options" diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 83bba33..eeb942d 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -32,25 +32,10 @@ obj-$(CONFIG_MODULES) += mips_ksyms.o module.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o -obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5500) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o -- 1.7.4.1 From florian@openwrt.org Mon Aug 1 12:22:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 12:23:44 +0200 (CEST) Received: from zmc.proxad.net ([212.27.53.206]:52678 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491143Ab1HAKWp (ORCPT ); Mon, 1 Aug 2011 12:22:45 +0200 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id F2FB32F1EA2; Mon, 1 Aug 2011 12:22:44 +0200 (CEST) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uJW8N5egrf-y; Mon, 1 Aug 2011 12:22:44 +0200 (CEST) Received: from flexo.priv.staff.proxad.net (bobafett.staff.proxad.net [213.228.1.121]) by zmc.proxad.net (Postfix) with ESMTPSA id BB1312F1DE3; Mon, 1 Aug 2011 12:22:44 +0200 (CEST) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 1/3] MIPS: introduce GENERIC_DUMP_TLB Date: Mon, 1 Aug 2011 12:26:20 +0200 Message-Id: <1312194382-3706-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.4.1 X-archive-position: 30779 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 283 Content-Length: 1910 Lines: 59 Allows us not to duplicate more lines in arch/mips/lib/Makefile. Signed-off-by: Florian Fainelli --- arch/mips/Kconfig | 4 ++++ arch/mips/lib/Makefile | 20 +------------------- 2 files changed, 5 insertions(+), 19 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d300c2b..9f4ade4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1803,6 +1803,10 @@ config SIBYTE_DMA_PAGEOPS config CPU_HAS_PREFETCH bool +config CPU_GENERIC_DUMP_TLB + bool + default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX) + choice prompt "MIPS MT options" diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index b2cad4f..d8c290c 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -8,27 +8,9 @@ lib-y += csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \ obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o -obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o -obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o -obj-$(CONFIG_CPU_R10000) += dump_tlb.o +obj-$(CONFIG_CPU_GENERIC_DUMP_TLB) += dump_tlb.o obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o -obj-$(CONFIG_CPU_R4300) += dump_tlb.o -obj-$(CONFIG_CPU_R4X00) += dump_tlb.o -obj-$(CONFIG_CPU_R5000) += dump_tlb.o -obj-$(CONFIG_CPU_R5432) += dump_tlb.o -obj-$(CONFIG_CPU_R5500) += dump_tlb.o -obj-$(CONFIG_CPU_R6000) += -obj-$(CONFIG_CPU_R8000) += -obj-$(CONFIG_CPU_RM7000) += dump_tlb.o -obj-$(CONFIG_CPU_RM9000) += dump_tlb.o -obj-$(CONFIG_CPU_SB1) += dump_tlb.o obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o -obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o -obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o -obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o -obj-$(CONFIG_CPU_XLR) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o -- 1.7.4.1 From jonas.gorski@gmail.com Mon Aug 1 12:31:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 12:31:51 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:52844 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491134Ab1HAKbp convert rfc822-to-8bit (ORCPT ); Mon, 1 Aug 2011 12:31:45 +0200 Received: by yxj20 with SMTP id 20so3508347yxj.36 for ; Mon, 01 Aug 2011 03:31:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=8wmF7iBnBR18vFFMDmytP8r+rJ6eh9Mk1qKkkT96p80=; b=FHT3qdmmxM9Uq68Jq+bvdYHKPbu0ox+Djno0NrAcwvbV05at2siYUEciEJoAuDd0c9 VnE5QztOEy0TF+zl/2VSWh5H763pZxTErXLm4gmx07saIr4fbrZxqbC80OV0N6FkoGOU R4/TnQypY4HJ65ClcsVe/N1Fl0NnCq07WMtPo= Received: by 10.150.51.12 with SMTP id y12mr691591yby.33.1312194699174; Mon, 01 Aug 2011 03:31:39 -0700 (PDT) MIME-Version: 1.0 Received: by 10.151.11.10 with HTTP; Mon, 1 Aug 2011 03:31:19 -0700 (PDT) In-Reply-To: <1312194382-3706-3-git-send-email-florian@openwrt.org> References: <1312194382-3706-1-git-send-email-florian@openwrt.org> <1312194382-3706-3-git-send-email-florian@openwrt.org> From: Jonas Gorski Date: Mon, 1 Aug 2011 12:31:19 +0200 Message-ID: Subject: Re: [PATCH 3/3] MIPS: introduce CPU_R4K_CACHE_TLB To: Florian Fainelli Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 30780 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 299 Content-Length: 3033 Lines: 67 Hi, On 1 August 2011 12:26, Florian Fainelli wrote: > R4K-style CPUs having common code to support their caches and tlb have this > boolean defined by default. Allows us to save some lines in > arch/mips/mm/Makefile > > Signed-off-by: Florian Fainelli > --- >  arch/mips/Kconfig     |    4 ++++ >  arch/mips/mm/Makefile |   16 +--------------- >  2 files changed, 5 insertions(+), 15 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 44eebc7..0150745 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1811,6 +1811,10 @@ config CPU_R4K_FPU >        bool >        default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) > > +config CPU_R4K_CACHE_TLB > +       bool > +       default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) > + >  choice >        prompt "MIPS MT options" > > diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile > index 4d8c162..04ece1b5 100644 > --- a/arch/mips/mm/Makefile > +++ b/arch/mips/mm/Makefile > @@ -11,24 +11,10 @@ obj-$(CONFIG_64BIT)         += pgtable-64.o >  obj-$(CONFIG_HIGHMEM)          += highmem.o >  obj-$(CONFIG_HUGETLB_PAGE)     += hugetlbpage.o > > -obj-$(CONFIG_CPU_LOONGSON2)    += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_MIPS32)       += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_MIPS64)       += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_NEVADA)       += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_R10000)       += c-r4k.o cex-gen.o tlb-r4k.o > +obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o >  obj-$(CONFIG_CPU_R3000)                += c-r3k.o tlb-r3k.o > -obj-$(CONFIG_CPU_R4300)                += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_R4X00)                += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_R5000)                += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_R5432)                += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_R5500)                += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_R8000)                += c-r4k.o cex-gen.o tlb-r8k.o This one should stay (and be added to the exceptions): tlb-r*8*k. ;-) > -obj-$(CONFIG_CPU_RM7000)       += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_RM9000)       += c-r4k.o cex-gen.o tlb-r4k.o >  obj-$(CONFIG_CPU_SB1)          += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o >  obj-$(CONFIG_CPU_TX39XX)       += c-tx39.o tlb-r3k.o > -obj-$(CONFIG_CPU_TX49XX)       += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_VR41XX)       += c-r4k.o cex-gen.o tlb-r4k.o >  obj-$(CONFIG_CPU_CAVIUM_OCTEON)        += c-octeon.o cex-oct.o tlb-r4k.o >  obj-$(CONFIG_CPU_XLR)          += c-r4k.o tlb-r4k.o cex-gen.o This one should go, too. You probably missed it because it used a different file name order ;-). I haven't checked if they are others outside of the context lines. Jonas From manuel.lauss@googlemail.com Mon Aug 1 14:52:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 14:52:06 +0200 (CEST) Received: from mail-yw0-f49.google.com ([209.85.213.49]:54917 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491134Ab1HAMwC (ORCPT ); Mon, 1 Aug 2011 14:52:02 +0200 Received: by ywm13 with SMTP id 13so761620ywm.36 for ; Mon, 01 Aug 2011 05:51:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; bh=2e8y+a5ne8lj5zdbjAtol0NyxWoQVvX/lePInybYsK0=; b=kmCI8IcFqhymxqSihlQXH9Rp6RUOnfL5iNQEt/1QeaYCyxezDIt04FRB9KZ47TdL9Q +2gLKnuIFQTEZDjhu21DEDUOYLg9pIz5C+QgXdNq0OFNQjX1af65s+8yRshJS6rtUs58 T5PSLYWyKHcPPeduNjFPKE8HqUgH2wxKKeqE4= MIME-Version: 1.0 Received: by 10.236.108.198 with SMTP id q46mr2121879yhg.291.1312203116722; Mon, 01 Aug 2011 05:51:56 -0700 (PDT) Received: by 10.236.103.172 with HTTP; Mon, 1 Aug 2011 05:51:56 -0700 (PDT) Date: Mon, 1 Aug 2011 14:51:56 +0200 Message-ID: Subject: shm broken on MIPS in current -git From: Manuel Lauss To: Vasiliy Kulikov , linux-kernel@vger.kernel.org Cc: Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 30781 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 399 Content-Length: 2042 Lines: 56 Hello Vasiliy, Commits 5774ed014f02120db9a6945a1ecebeb97c2acccb (shm: handle separate PID namespaces case) and 4c677e2eefdba9c5bfc4474e2e91b26ae8458a1d (shm: optimize locking and ipc_namespace getting) break on my MIPS systems. The following oops is printed on boot, and as a result, more than 300 zombie kworker kernel processes are resident. I don't see this oops on x86 or x64. ra points to the down_write() in ipc/shm.c::exit_shm() CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 80527c64, ra == 8024afb8 Oops[#1]: Cpu 0 $ 0 : 00000000 10003c00 00000000 10003c01 $ 4 : 8060d114 8fc45e60 8060d118 8fc3f520 $ 8 : 00000000 01312d00 0016e35f 00020000 $12 : 00000080 00000010 00000010 8fc3001c $16 : 8fc3f520 00000000 00000000 00000000 $20 : 00000000 00000000 8fc45eb4 00000000 $24 : 00000000 8011f9b0 $28 : 8fc44000 8fc45e50 00000001 8024afb8 Hi : 00000000 Lo : 01312d00 epc : 80527c64 __down_write_nested+0x68/0xf0 Not tainted ra : 8024afb8 exit_shm+0x30/0x64 Status: 10003c02 KERNEL EXL Cause : 0080800c BadVA : 00000000 PrId : 800c8000 (Au1300) Process kworker/u:0 (pid: 9, threadinfo=8fc44000, task=8fc3f520, tls=00000000) Stack : 14200972 d3054429 00000000 56b8e493 8060d118 00000000 8fc3f520 00000002 8fc2c000 8060d114 00000000 8024afb8 00000000 00000000 00000000 00000000 8060d0c0 00000000 8fc3f520 80128ae8 30480023 0b309f84 34ffeedb ef9e65d6 38019941 af430015 f6d9ebeb 00000000 00000000 00000000 8fc29ce0 8fc15300 00000000 00000000 00000000 00000000 00000000 00000000 00000000 80139578 ... Call Trace: [<80527c64>] __down_write_nested+0x68/0xf0 [<8024afb8>] exit_shm+0x30/0x64 [<80128ae8>] do_exit+0x50c/0x664 [<80139578>] ____call_usermodehelper+0xfc/0x118 [<801061bc>] kernel_thread_helper+0x10/0x18 Code: ac850008 afa60010 afa20014 40016000 30630001 3421001f 3821001f 00611825 Disabling lock debugging due to kernel taint Fixing recursive fault but reboot is needed! Thanks, Manuel Lauss From segoon@openwall.com Mon Aug 1 15:11:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 15:11:52 +0200 (CEST) Received: from mail-ey0-f178.google.com ([209.85.215.178]:56082 "EHLO mail-ey0-f178.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491134Ab1HANLs (ORCPT ); Mon, 1 Aug 2011 15:11:48 +0200 Received: by eye4 with SMTP id 4so6138430eye.9 for ; Mon, 01 Aug 2011 06:11:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=yoMvcJ4jeenBKzBULY8u5277dOmMgfeEHfzIYrK8xFU=; b=RoVpsucXfX3OIEOC8Oh8BQZaYpJW5Z/eAhdbOexjK+rCTrh6udyf+GZ1ghWLUdcIj3 mfgmudgH7RoSCEquWTM/oJuORQN8NZgFupG9E33KHPsqNIZmOPPfOegGBvdoWwzqZ4lb f6EylM9bLSx7kJVPH9Xr3VfPl0geUMxjDPnoo= Received: by 10.204.57.82 with SMTP id b18mr1212658bkh.95.1312204302852; Mon, 01 Aug 2011 06:11:42 -0700 (PDT) Received: from localhost (ppp85-140-16-100.pppoe.mtu-net.ru [85.140.16.100]) by mx.google.com with ESMTPS id p24sm1320068bkw.8.2011.08.01.06.11.39 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 01 Aug 2011 06:11:41 -0700 (PDT) Date: Mon, 1 Aug 2011 17:11:37 +0400 From: Vasiliy Kulikov To: Manuel Lauss Cc: linux-kernel@vger.kernel.org, Linux-MIPS Subject: Re: shm broken on MIPS in current -git Message-ID: <20110801131137.GA10508@albatros> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 30782 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: segoon@openwall.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 406 Content-Length: 2406 Lines: 67 Hi Manuel, On Mon, Aug 01, 2011 at 14:51 +0200, Manuel Lauss wrote: > Commits 5774ed014f02120db9a6945a1ecebeb97c2acccb > (shm: handle separate PID namespaces case) > and 4c677e2eefdba9c5bfc4474e2e91b26ae8458a1d > (shm: optimize locking and ipc_namespace getting) > break on my MIPS systems. Can you please identify what commit breaks the system? > The following oops is > printed on boot, and as a result, more than 300 zombie kworker > kernel processes are resident. I don't see this oops on x86 or x64. Do you have the same configs for x86 and mips? > ra points to the down_write() in ipc/shm.c::exit_shm() > > CPU 0 Unable to handle kernel paging request at virtual address > 00000000, epc == 80527c64, ra == 8024afb8 > Oops[#1]: > Cpu 0 > $ 0 : 00000000 10003c00 00000000 10003c01 > $ 4 : 8060d114 8fc45e60 8060d118 8fc3f520 > $ 8 : 00000000 01312d00 0016e35f 00020000 > $12 : 00000080 00000010 00000010 8fc3001c > $16 : 8fc3f520 00000000 00000000 00000000 > $20 : 00000000 00000000 8fc45eb4 00000000 > $24 : 00000000 8011f9b0 > $28 : 8fc44000 8fc45e50 00000001 8024afb8 > Hi : 00000000 > Lo : 01312d00 > epc : 80527c64 __down_write_nested+0x68/0xf0 > Not tainted > ra : 8024afb8 exit_shm+0x30/0x64 > Status: 10003c02 KERNEL EXL > Cause : 0080800c > BadVA : 00000000 > PrId : 800c8000 (Au1300) > Process kworker/u:0 (pid: 9, threadinfo=8fc44000, task=8fc3f520, tls=00000000) > Stack : 14200972 d3054429 00000000 56b8e493 8060d118 00000000 8fc3f520 00000002 > 8fc2c000 8060d114 00000000 8024afb8 00000000 00000000 00000000 00000000 > 8060d0c0 00000000 8fc3f520 80128ae8 30480023 0b309f84 34ffeedb ef9e65d6 > 38019941 af430015 f6d9ebeb 00000000 00000000 00000000 8fc29ce0 8fc15300 > 00000000 00000000 00000000 00000000 00000000 00000000 00000000 80139578 > ... > Call Trace: > [<80527c64>] __down_write_nested+0x68/0xf0 > [<8024afb8>] exit_shm+0x30/0x64 > [<80128ae8>] do_exit+0x50c/0x664 > [<80139578>] ____call_usermodehelper+0xfc/0x118 > [<801061bc>] kernel_thread_helper+0x10/0x18 > > > Code: ac850008 afa60010 afa20014 40016000 30630001 > 3421001f 3821001f 00611825 > Disabling lock debugging due to kernel taint > Fixing recursive fault but reboot is needed! > > > Thanks, > Manuel Lauss -- Vasiliy Kulikov http://www.openwall.com - bringing security into open computing environments From manuel.lauss@googlemail.com Mon Aug 1 15:22:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 15:22:58 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:38997 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491134Ab1HANWy convert rfc822-to-8bit (ORCPT ); Mon, 1 Aug 2011 15:22:54 +0200 Received: by gwb1 with SMTP id 1so4061945gwb.36 for ; Mon, 01 Aug 2011 06:22:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=bVWPyWDEQc0+YXs3W2kQC1ZDQ7KXRt86TaRkxirgMQ0=; b=A7Py5PWwP0ClOeHrO94GxZvcHsiTGbhRMwOdcfZEwMc+ds0ZN9ufDXX01Ne7lkIJXY Y2pbFIVUR5OB5pIhOOHJ4dBgNUBUxySgoaitsEtMcnEE4B4nfc32L3lYKu/XW4vvm2Wz /9qnEcJMaadeMVutfR1P12G+BkLybevyStMd0= MIME-Version: 1.0 Received: by 10.236.184.197 with SMTP id s45mr3242852yhm.157.1312204968535; Mon, 01 Aug 2011 06:22:48 -0700 (PDT) Received: by 10.236.103.172 with HTTP; Mon, 1 Aug 2011 06:22:48 -0700 (PDT) In-Reply-To: <20110801131137.GA10508@albatros> References: <20110801131137.GA10508@albatros> Date: Mon, 1 Aug 2011 15:22:48 +0200 Message-ID: Subject: Re: shm broken on MIPS in current -git From: Manuel Lauss To: Vasiliy Kulikov Cc: linux-kernel@vger.kernel.org, Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 30783 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 414 Content-Length: 1057 Lines: 32 On Mon, Aug 1, 2011 at 3:11 PM, Vasiliy Kulikov wrote: > On Mon, Aug 01, 2011 at 14:51 +0200, Manuel Lauss wrote: >> Commits 5774ed014f02120db9a6945a1ecebeb97c2acccb >> (shm: handle separate PID namespaces case) >> and 4c677e2eefdba9c5bfc4474e2e91b26ae8458a1d >> (shm: optimize locking and ipc_namespace getting) >> break on my MIPS systems. > > Can you please identify what commit breaks the system? Reverting this one fixes the oops for good: 5774ed014f02120db9a6945a1ecebeb97c2acccb (shm: handle separate PID namespaces case) >>  The following oops is >> printed on boot, and as a result, more than  300 zombie kworker >> kernel processes are resident.  I don't see this oops on x86 or x64. > > Do you have the same configs for x86 and mips? MIPS is UP, SLAB without preempt, x86 is UP/SMP, SLUB with preempt. It's not SLAB/SLUB and not preempt, and both MIPS+x86 have all namespace options enabled. both configs are temporarily available here: http://mlau.at/config-mips http://mlau.at/config-x64 Thanks! Manuel Lauss From segoon@openwall.com Mon Aug 1 15:24:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 15:24:15 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:61297 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491148Ab1HANYJ (ORCPT ); Mon, 1 Aug 2011 15:24:09 +0200 Received: by ewy3 with SMTP id 3so3550088ewy.36 for ; Mon, 01 Aug 2011 06:24:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=OF1toX79+5Yjs6+sF1pxb7kib5GuschUHxRXskQ6csk=; b=we7tJcClulT7aCK6s4MH+EyQuNOSQdPaVhmeQ4gCpUhXSr+YMHDy2sXmWS108gDqty RggdEwokHOVqZOQD3qqVQMwiMQgMUUkNgOLyFZ+5SkvJwTsuRvfiVTQQD6oTW3X93uO5 dbpQuGxja8NH9uO4LSiEy1pR1o1ggrPqVuBC8= Received: by 10.204.134.210 with SMTP id k18mr1114437bkt.17.1312205043958; Mon, 01 Aug 2011 06:24:03 -0700 (PDT) Received: from localhost (ppp85-140-16-100.pppoe.mtu-net.ru [85.140.16.100]) by mx.google.com with ESMTPS id p12sm922735bkp.1.2011.08.01.06.24.01 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 01 Aug 2011 06:24:02 -0700 (PDT) Date: Mon, 1 Aug 2011 17:23:59 +0400 From: Vasiliy Kulikov To: Manuel Lauss Cc: linux-kernel@vger.kernel.org, Linux-MIPS Subject: Re: shm broken on MIPS in current -git Message-ID: <20110801132359.GA11158@albatros> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 30784 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: segoon@openwall.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 419 Content-Length: 645 Lines: 17 On Mon, Aug 01, 2011 at 14:51 +0200, Manuel Lauss wrote: > Commits 5774ed014f02120db9a6945a1ecebeb97c2acccb > (shm: handle separate PID namespaces case) > and 4c677e2eefdba9c5bfc4474e2e91b26ae8458a1d > (shm: optimize locking and ipc_namespace getting) > break on my MIPS systems. The following oops is > printed on boot, and as a result, more than 300 zombie kworker > kernel processes are resident. I don't see this oops on x86 or x64. Also it might help if you send the whole config file to me (privately, as it is too big for ML). Thanks, -- Vasiliy Kulikov http://www.openwall.com - bringing security into open computing environments From segoon@openwall.com Mon Aug 1 15:40:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 15:40:07 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:58321 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491134Ab1HANkD (ORCPT ); Mon, 1 Aug 2011 15:40:03 +0200 Received: by ewy3 with SMTP id 3so3559645ewy.36 for ; Mon, 01 Aug 2011 06:39:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=6+2G++kYev0YJbutP+XLI2yVH+tF4ObL6XIyg/wBlSg=; b=AkzvwkzU55RNkSHw04Sr3/bcLHJBUQVURNN5F0uaeuUY6Z+BiJoY2/avOP/0Vy+oZs dRzzIgDdG/Zcm80Hwi99gb9qrdh+NM4XFJSf+sAQ1AAA4DHyxmTFtDl8XBGISfNVpuK0 sty2Oy0rFc7BcJ5P/K+Fg/SadvyTFqOe3vmeU= Received: by 10.204.134.205 with SMTP id k13mr1354608bkt.252.1312205998207; Mon, 01 Aug 2011 06:39:58 -0700 (PDT) Received: from localhost (ppp85-140-16-100.pppoe.mtu-net.ru [85.140.16.100]) by mx.google.com with ESMTPS id l1sm1150693bks.61.2011.08.01.06.39.56 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 01 Aug 2011 06:39:57 -0700 (PDT) Date: Mon, 1 Aug 2011 17:39:54 +0400 From: Vasiliy Kulikov To: Manuel Lauss Cc: linux-kernel@vger.kernel.org, Linux-MIPS Subject: Re: shm broken on MIPS in current -git Message-ID: <20110801133954.GA11452@albatros> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 30785 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: segoon@openwall.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 433 Content-Length: 1375 Lines: 37 Manuel, On Mon, Aug 01, 2011 at 14:51 +0200, Manuel Lauss wrote: > CPU 0 Unable to handle kernel paging request at virtual address > 00000000, epc == 80527c64, ra == 8024afb8 > Oops[#1]: [...] > epc : 80527c64 __down_write_nested+0x68/0xf0 Could you post the asm code of __down_write_nested() of your image? What pointer is NULL? Looks like MIPS handles namespaces in usermode helpers other way. > ra : 8024afb8 exit_shm+0x30/0x64 > Status: 10003c02 KERNEL EXL > Cause : 0080800c > BadVA : 00000000 > PrId : 800c8000 (Au1300) > Process kworker/u:0 (pid: 9, threadinfo=8fc44000, task=8fc3f520, tls=00000000) > Stack : 14200972 d3054429 00000000 56b8e493 8060d118 00000000 8fc3f520 00000002 > 8fc2c000 8060d114 00000000 8024afb8 00000000 00000000 00000000 00000000 > 8060d0c0 00000000 8fc3f520 80128ae8 30480023 0b309f84 34ffeedb ef9e65d6 > 38019941 af430015 f6d9ebeb 00000000 00000000 00000000 8fc29ce0 8fc15300 > 00000000 00000000 00000000 00000000 00000000 00000000 00000000 80139578 > ... > Call Trace: > [<80527c64>] __down_write_nested+0x68/0xf0 > [<8024afb8>] exit_shm+0x30/0x64 > [<80128ae8>] do_exit+0x50c/0x664 > [<80139578>] ____call_usermodehelper+0xfc/0x118 > [<801061bc>] kernel_thread_helper+0x10/0x18 Thanks, -- Vasiliy Kulikov http://www.openwall.com - bringing security into open computing environments From manuel.lauss@googlemail.com Mon Aug 1 16:58:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 16:58:04 +0200 (CEST) Received: from mail-gy0-f177.google.com ([209.85.160.177]:46338 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491143Ab1HAO6A convert rfc822-to-8bit (ORCPT ); Mon, 1 Aug 2011 16:58:00 +0200 Received: by gya1 with SMTP id 1so4034125gya.36 for ; Mon, 01 Aug 2011 07:57:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=6ruwyzRjr1M1Y62PU1noS9m2nhEOjmp2D/V7MYedtGI=; b=Ii93Db3hQatuNH6cQcIDrmvodVxod6tl2ts5jcDcthjdogkdJqZglntmF/bB7OTjez 6elZAOeeV4HrZ2KIKV8yN7rdAK1kC0+brZcNyYsl3Ou28atADlYNr+i3mEy70QVcIM/S faz8uCdSB7aIMcyZLkZqCYwCuUF2xi8ICCndE= MIME-Version: 1.0 Received: by 10.236.185.42 with SMTP id t30mr3365497yhm.492.1312210674675; Mon, 01 Aug 2011 07:57:54 -0700 (PDT) Received: by 10.236.103.172 with HTTP; Mon, 1 Aug 2011 07:57:54 -0700 (PDT) In-Reply-To: <20110801133954.GA11452@albatros> References: <20110801133954.GA11452@albatros> Date: Mon, 1 Aug 2011 16:57:54 +0200 Message-ID: Subject: Re: shm broken on MIPS in current -git From: Manuel Lauss To: Vasiliy Kulikov Cc: linux-kernel@vger.kernel.org, Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 30786 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 497 Content-Length: 3555 Lines: 88 On Mon, Aug 1, 2011 at 3:39 PM, Vasiliy Kulikov wrote: > Manuel, > > On Mon, Aug 01, 2011 at 14:51 +0200, Manuel Lauss wrote: >> CPU 0 Unable to handle kernel paging request at virtual address >> 00000000, epc == 80527c64, ra == 8024afb8 >> Oops[#1]: > [...] >> epc   : 80527c64 __down_write_nested+0x68/0xf0 > > Could you post the asm code of __down_write_nested() of your image? > What pointer is NULL?  Looks like MIPS handles namespaces in usermode > helpers other way. I'm no MIPS expert, but this looks like a problem with the waiter_list in struct rw_semaphore: Dump of assembler code for function __down_write_nested: 0x80530ee4 <+0>: addiu sp,sp,-48 0x80530ee8 <+4>: sw ra,44(sp) 0x80530eec <+8>: sw s1,40(sp) 0x80530ef0 <+12>: sw s0,36(sp) 0x80530ef4 <+16>: mfc0 v1,c0_status 0x80530ef8 <+20>: ori at,v1,0x1f 0x80530efc <+24>: xori at,at,0x1f 0x80530f00 <+28>: mtc0 at,c0_status 0x80530f04 <+32>: lw v0,0(a0) 0x80530f08 <+36>: beqz v0,0x80530fa4 <__down_write_nested+192> 0x80530f0c <+40>: addiu a2,a0,4 tsk = current: 0x80530f10 <+44>: lw s0,0(gp) set_task_state(tsk, UNINTERRUPTIBLE): 0x80530f14 <+48>: li v0,2 0x80530f18 <+52>: sw v0,0(s0) waiter.tsk = tsk, ... 0x80530f1c <+56>: sw v0,28(sp) 0x80530f20 <+60>: sw s0,24(sp) get_task_struct(): 0x80530f24 <+64>: addiu v0,s0,8 0x80530f28 <+68>: ll a1,0(v0) 0x80530f2c <+72>: addiu a1,a1,1 0x80530f30 <+76>: sc a1,0(v0) 0x80530f34 <+80>: beqz a1,0x80530f28 <__down_write_nested+68> list_add_tail: 0x80530f38 <+84>: addiu a1,sp,16 ; a1 = &waiter.list 0x80530f3c <+88>: lw v0,8(a0) ; v0 = &sem->wait_list 0x80530f40 <+92>: sw a1,8(a0) 0x80530f44 <+96>: sw a2,16(sp) 0x80530f48 <+100>: sw v0,20(sp) 0x80530f4c <+104>: sw a1,0(v0) <===== oops here, because v0 = 0 spin_unlock_irqrestore: 0x80530f50 <+108>: mfc0 at,c0_status 0x80530f54 <+112>: andi v1,v1,0x1 0x80530f58 <+116>: ori at,at,0x1f 0x80530f5c <+120>: xori at,at,0x1f 0x80530f60 <+124>: or v1,v1,at 0x80530f64 <+128>: mtc0 v1,c0_status [...] 0x80530f68 <+132>: lw v0,24(sp) 0x80530f6c <+136>: beqz v0,0x80530f8c <__down_write_nested+168> 0x80530f70 <+140>: li s1,2 0x80530f74 <+144>: jal 0x8052ef94 0x80530f78 <+148>: nop 0x80530f7c <+152>: sw s1,0(s0) 0x80530f80 <+156>: lw v0,24(sp) 0x80530f84 <+160>: bnez v0,0x80530f74 <__down_write_nested+144> 0x80530f88 <+164>: nop 0x80530f8c <+168>: sw zero,0(s0) 0x80530f90 <+172>: lw ra,44(sp) 0x80530f94 <+176>: lw s1,40(sp) 0x80530f98 <+180>: lw s0,36(sp) 0x80530f9c <+184>: jr ra 0x80530fa0 <+188>: addiu sp,sp,48 0x80530fa4 <+192>: lw v0,4(a0) 0x80530fa8 <+196>: bne v0,a2,0x80530f10 <__down_write_nested+44> 0x80530fac <+200>: li a1,-1 0x80530fb0 <+204>: sw a1,0(a0) 0x80530fb4 <+208>: mfc0 at,c0_status 0x80530fb8 <+212>: andi v1,v1,0x1 0x80530fbc <+216>: ori at,at,0x1f 0x80530fc0 <+220>: xori at,at,0x1f 0x80530fc4 <+224>: or v1,v1,at 0x80530fc8 <+228>: mtc0 v1,c0_status 0x80530fcc <+232>: j 0x80530f94 <__down_write_nested+176> 0x80530fd0 <+236>: lw ra,44(sp) Manuel Lauss From bhelgaas@google.com Mon Aug 1 17:21:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 17:21:41 +0200 (CEST) Received: from smtp-out.google.com ([74.125.121.67]:19625 "EHLO smtp-out.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491146Ab1HAPVe (ORCPT ); Mon, 1 Aug 2011 17:21:34 +0200 Received: from kpbe19.cbf.corp.google.com (kpbe19.cbf.corp.google.com [172.25.105.83]) by smtp-out.google.com with ESMTP id p71FLW18009257 for ; Mon, 1 Aug 2011 08:21:33 -0700 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=google.com; s=beta; t=1312212093; bh=AKiBxZMGLYI5I574yKyO9UnB5h4=; h=MIME-Version:In-Reply-To:References:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=XhSbU6tfHHHJpx8m2hygsCV/POtn0a4biE11W4vS4FbtGgaME2wBLaWhxVNLYCs68 dbgm6+LsfNfwzyQ04n+uQ== DomainKey-Signature: a=rsa-sha1; s=beta; d=google.com; c=nofws; q=dns; h=dkim-signature:mime-version:in-reply-to:references:from:date: message-id:subject:to:cc:content-type:x-system-of-record; b=YDqegdRi81+tDsX0IKb11Kj/YDCxZIZy0+MtrJ9oZsiHN8vJ+U1/+ME9WVaYFc5XS 5a+ZgfhqINlk6MaeQQh7A== Received: from ywa12 (ywa12.prod.google.com [10.192.1.12]) by kpbe19.cbf.corp.google.com with ESMTP id p71FLVut016011 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NOT) for ; Mon, 1 Aug 2011 08:21:31 -0700 Received: by ywa12 with SMTP id 12so1013557ywa.23 for ; Mon, 01 Aug 2011 08:21:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=beta; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=NchbzGmEuo1h8EIACrlAGfIRcUwrshqZqlsQN5HQQuA=; b=IqA2AV4gSXVCGBEOlTEjoJbAHlE/1+AVDKLc19NX0S9I3V6dr96/wIECKAcba/K19P sqUY8Ko/+o293msrhQ8g== Received: by 10.150.60.19 with SMTP id i19mr871206yba.270.1312212091106; Mon, 01 Aug 2011 08:21:31 -0700 (PDT) MIME-Version: 1.0 Received: by 10.150.58.10 with HTTP; Mon, 1 Aug 2011 08:21:11 -0700 (PDT) In-Reply-To: References: <1311852512-7340-1-git-send-email-dengcheng.zhu@gmail.com> <1311852512-7340-2-git-send-email-dengcheng.zhu@gmail.com> <20110728115330.GA29899@linux-mips.org> From: Bjorn Helgaas Date: Mon, 1 Aug 2011 09:21:11 -0600 Message-ID: Subject: Re: [PATCH 1/2] PCI: make pci_claim_resource() work with conflict resources as appropriate To: Deng-Cheng Zhu Cc: Ralf Baechle , jbarnes@virtuousgeek.org, torvalds@linux-foundation.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, eyal@mips.com, zenon@mips.com Content-Type: text/plain; charset=ISO-8859-1 X-System-Of-Record: true X-archive-position: 30787 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 529 Content-Length: 1104 Lines: 22 On Mon, Aug 1, 2011 at 4:13 AM, Deng-Cheng Zhu wrote: > It was found that PCI quirks claim resources (by calling pci_claim_resource()) > *BEFORE* pcibios_fixup_bus() is called. In pcibios_fixup_bus(), > pci_bus->resource[0] for the root bus DOES point to msc_io_resource. If PCI > quirks do the resource claim after the arch-defined pcibios_fixup_bus() being > called, then the problem with Malta goes away. Oh, I see. pcibios_fixup_bus() copies the hose resources to the root bus pci_bus structure. I think that's bogus because we have the interval between mips_pcibios_init() and pcibios_fixup_bus() where the root bus resources are incorrect. I think it would be better to set up the resources correctly right away, as we do on x86. In fact, I'm dubious about pci_create_bus() filling in ioport_resource and iomem_resource as defaults -- that's never what we really want there, and we have to rely on the arch coming back later to fix it up. I'd like to see some sort of restructuring there so we could pass in a list of resources at the time we create the bus. Bjorn From jj@chaosbits.net Mon Aug 1 23:09:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Aug 2011 23:09:38 +0200 (CEST) Received: from swampdragon.chaosbits.net ([90.184.90.115]:14427 "EHLO swampdragon.chaosbits.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491159Ab1HAVJe (ORCPT ); Mon, 1 Aug 2011 23:09:34 +0200 Received: by swampdragon.chaosbits.net (Postfix, from userid 1000) id E98D49405D; Mon, 1 Aug 2011 23:09:33 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by swampdragon.chaosbits.net (Postfix) with ESMTP id E7B2E9405C; Mon, 1 Aug 2011 23:09:33 +0200 (CEST) Date: Mon, 1 Aug 2011 23:09:33 +0200 (CEST) From: Jesper Juhl To: LKML cc: trivial@kernel.org, linux-mips@linux-mips.org, Ralf Baechle Subject: [PATCH][Resend] Remove unneeded version.h includes from arch/mips/ Message-ID: User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 30788 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jj@chaosbits.net Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 761 Content-Length: 1687 Lines: 56 It was pointed out by 'make versioncheck' that some includes of linux/version.h are not needed in arch/mips/. This patch removes them. Signed-off-by: Jesper Juhl --- arch/mips/include/asm/mach-powertv/dma-coherence.h | 1 - arch/mips/lantiq/xway/ebu.c | 1 - arch/mips/lantiq/xway/pmu.c | 1 - 3 files changed, 0 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h index 62c0940..3537164 100644 --- a/arch/mips/include/asm/mach-powertv/dma-coherence.h +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h @@ -13,7 +13,6 @@ #define __ASM_MACH_POWERTV_DMA_COHERENCE_H #include -#include #include #include diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c index 66eb52f..033b318 100644 --- a/arch/mips/lantiq/xway/ebu.c +++ b/arch/mips/lantiq/xway/ebu.c @@ -10,7 +10,6 @@ #include #include -#include #include #include diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c index 9d69f01e..39f0d26 100644 --- a/arch/mips/lantiq/xway/pmu.c +++ b/arch/mips/lantiq/xway/pmu.c @@ -8,7 +8,6 @@ #include #include -#include #include #include -- 1.7.6 -- Jesper Juhl http://www.chaosbits.net/ Don't top-post http://www.catb.org/jargon/html/T/top-post.html Plain text mails only, please. From ralf@linux-mips.org Tue Aug 2 11:21:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 11:21:49 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42473 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491192Ab1HBJVp (ORCPT ); Tue, 2 Aug 2011 11:21:45 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p729Lbqi018132; Tue, 2 Aug 2011 10:21:38 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p729Lapn018129; Tue, 2 Aug 2011 10:21:36 +0100 Date: Tue, 2 Aug 2011 10:21:36 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: Enable C0_UserLocal probing. Message-ID: <20110802092136.GA12709@linux-mips.org> References: <1309908953-1726-1-git-send-email-david.daney@cavium.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1309908953-1726-1-git-send-email-david.daney@cavium.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30789 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1160 Content-Length: 238 Lines: 9 On Tue, Jul 05, 2011 at 04:35:53PM -0700, David Daney wrote: > Octeon2 processor cores have a UserLocal register. Remove the hard > coded negative probe and allow the standard probing to detect this > feature. Applied, thanks! Ralf From ralf@linux-mips.org Tue Aug 2 11:32:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 11:32:34 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:43003 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491196Ab1HBJcb (ORCPT ); Tue, 2 Aug 2011 11:32:31 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p729Od5m018421; Tue, 2 Aug 2011 10:24:39 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p729OcD6018417; Tue, 2 Aug 2011 10:24:38 +0100 Date: Tue, 2 Aug 2011 10:24:38 +0100 From: Ralf Baechle To: Jesper Juhl Cc: linux-kernel@vger.kernel.org, trivial@kernel.org, Lars-Peter Clausen , linux-mips@linux-mips.org Subject: Re: [PATCH 2/7] MIPS: static should be at beginning of declaration Message-ID: <20110802092438.GA18229@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30790 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1172 Content-Length: 676 Lines: 19 On Sat, Jul 09, 2011 at 11:12:35PM +0200, Jesper Juhl wrote: > Make sure that the 'static' keywork is at the beginning of declaration > for arch/mips/include/asm/mach-jz4740/gpio.h > > This gets rid of warnings like > warning: ‘static’ is not at beginning of declaration > when building with -Wold-style-declaration (and/or -Wextra which also > enables it). > Also a few tiny whitespace changes. > - const static struct jz_gpio_bulk_request i2c_pins[] = { > + static const struct jz_gpio_bulk_request i2c_pins[] = { Quite surprising - but that still was valid C - just type for example: int typedef (*func(const char op))(int a, int b[static const a = 3]); Ralf From ralf@linux-mips.org Tue Aug 2 11:59:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 11:59:53 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59144 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491196Ab1HBJ7u (ORCPT ); Tue, 2 Aug 2011 11:59:50 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p729wNce023040; Tue, 2 Aug 2011 10:58:23 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p729wEun023012; Tue, 2 Aug 2011 10:58:14 +0100 Date: Tue, 2 Aug 2011 10:58:14 +0100 From: Ralf Baechle To: Sven Eckelmann Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Randy Dunlap , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Tony Luck , Fenghua Yu , Hirokazu Takata , Kyle McMartin , Helge Deller , "James E.J. Bottomley" , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, "David S. Miller" , Chris Metcalf , Jeff Dike , Richard Weinberger , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Arnd Bergmann , linux-doc@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, user-mode-linux-devel@lists.sourceforge.net Subject: Re: [PATCHv4 01/11] atomic: add *_dec_not_zero Message-ID: <20110802095814.GA22947@linux-mips.org> References: <1311760070-21532-1-git-send-email-sven@narfation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1311760070-21532-1-git-send-email-sven@narfation.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30791 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1204 Content-Length: 129 Lines: 7 On Wed, Jul 27, 2011 at 11:47:40AM +0200, Sven Eckelmann wrote: For MIPS: Acked-by: Ralf Baechle Ralf From ralf@linux-mips.org Tue Aug 2 12:17:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 12:17:08 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:43197 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491192Ab1HBKRE (ORCPT ); Tue, 2 Aug 2011 12:17:04 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p72AGw7h024828; Tue, 2 Aug 2011 11:16:58 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p72AGwbB024825; Tue, 2 Aug 2011 11:16:58 +0100 Date: Tue, 2 Aug 2011 11:16:58 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: Jian Peng , David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH -queue] MIPS: Trivial style cleanups in mmap.c Message-ID: <20110802101658.GC32216@linux-mips.org> References: <50c16d4ef04b5213459ba15d14e30459@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50c16d4ef04b5213459ba15d14e30459@localhost> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30792 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1224 Content-Length: 39 Lines: 5 Queued for 3.2. Thanks Kevin! Ralf From ralf@linux-mips.org Tue Aug 2 12:22:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 12:22:36 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54966 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491192Ab1HBKWd (ORCPT ); Tue, 2 Aug 2011 12:22:33 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p72AMPAG025426; Tue, 2 Aug 2011 11:22:25 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p72AMP5p025425; Tue, 2 Aug 2011 11:22:25 +0100 Date: Tue, 2 Aug 2011 11:22:25 +0100 From: Ralf Baechle To: Jesper Juhl Cc: LKML , trivial@kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH 06/37] Remove unneeded version.h includes from arch/mips/ Message-ID: <20110802102225.GD32216@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30793 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1227 Content-Length: 32 Lines: 3 Thanks, queued for 3.2. Ralf From ralf@linux-mips.org Tue Aug 2 17:58:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 17:58:09 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42777 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491177Ab1HBP6E (ORCPT ); Tue, 2 Aug 2011 17:58:04 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p72Fw0Jv023525; Tue, 2 Aug 2011 16:58:00 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p72FvxMB023522; Tue, 2 Aug 2011 16:57:59 +0100 Date: Tue, 2 Aug 2011 16:57:59 +0100 From: Ralf Baechle To: David VomLehn Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/1] Pendantic stack backtrace code Message-ID: <20110802155759.GA891@linux-mips.org> References: <20110706233614.GA19332@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110706233614.GA19332@dvomlehn-lnx2.corp.sa.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30794 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1531 Content-Length: 16569 Lines: 477 On Wed, Jul 06, 2011 at 04:36:15PM -0700, David VomLehn wrote: > This is the much updated version of the MIPS stack backtrace code submitted > a few years ago. It has a few bugs fixed and should be easier to understand > as a result of a signficant rewrite. There are some references to 64-bit > support, but support is not complete. As a result, this is only enabled > for 32-bit systems. > > The code does code analysis according to the o32 backtracing rules, plus > using information the kernel knows and a few simple heuristics. There are > a few things no such backtracer can do, but it handles quite a large > number of cases. > > In addition to simple backtracing, the code also traces over exception > frames. So, if you have an exception handler that panics, you will be able > to see how the code got to where the exception occurred. > > This file contains one cleanpatch.pl false positive: > arch/mips/kernel/backtrace/kernel-backtrace-symbols.c: A preprocessor macro > used to create declarations has "extern" in the macro body. > > Signed-off-by: David VomLehn > --- > arch/mips/Kconfig.debug | 11 + > arch/mips/include/asm/base-backtrace.h | 440 ++++++ > arch/mips/include/asm/kernel-backtrace-symbols.h | 151 ++ > arch/mips/include/asm/kernel-backtrace.h | 101 ++ > arch/mips/include/asm/sigframe.h | 39 + > arch/mips/include/asm/thread-backtrace.h | 87 ++ > arch/mips/kernel/entry.S | 17 +- > arch/mips/kernel/scall32-o32.S | 10 +- > arch/mips/kernel/signal.c | 15 +- > arch/mips/kernel/traps.c | 78 +- > arch/mips/kernel/vdso.c | 8 +- > arch/mips/lib/Makefile | 3 + > arch/mips/lib/base-backtrace.c | 1679 ++++++++++++++++++++++ > arch/mips/lib/kernel-backtrace-symbols.c | 41 + > arch/mips/lib/kernel-backtrace.c | 1080 ++++++++++++++ > arch/mips/lib/thread-backtrace.c | 289 ++++ > scripts/module-common.lds | 19 - > 17 files changed, 4020 insertions(+), 48 deletions(-) > > diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug > index 83ed00a..af3582c 100644 > --- a/arch/mips/Kconfig.debug > +++ b/arch/mips/Kconfig.debug > @@ -121,6 +121,17 @@ config DEBUG_ZBOOT > to reduce the kernel image size and speed up the booting procedure a > little. > > +config MIPS_PEDANTIC_BACKTRACE > + bool "More comprehensive backtrace code" > + default n > + depends on KALLSYMS && 32BIT > + help > + Use backtrace code that more completely handles the various > + complexities of the MIPS processors, including branch delay > + slots. This is substantially larger than the standard backtrace > + code. It also allows tracing over exception frames, which is > + occasionally very useful. > + > config SPINLOCK_TEST > bool "Enable spinlock timing tests in debugfs" > depends on DEBUG_FS > diff --git a/arch/mips/include/asm/base-backtrace.h b/arch/mips/include/asm/base-backtrace.h > new file mode 100644 > index 0000000..ddc61d1 > --- /dev/null > +++ b/arch/mips/include/asm/base-backtrace.h > @@ -0,0 +1,440 @@ > +/* > + * Definitions handling one stack frame's worth of stack backtrace. > + * > + * Copyright(C) 2007 Scientific-Atlanta, Inc. Shouldn't this now be changed to Cisco? > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#ifndef _BASE_BACKTRACE_H_ > +#define _BASE_BACKTRACE_H_ > + > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#define dbg_print printk > + > +#define PRIORITY KERN_CRIT Unused define. > + > +#undef DEBUG > + > +#ifdef DEBUG > +#define bt_dbg(fmt, ...) do { \ > + dbg_print("%s: " fmt, __func__, ##__VA_ARGS__); \ > + } while (0) printk invocations should use a loglevel. If you want output to depend on DEBUG use pr_debug(). > + > +static const char *const backtrace_rule[] = { > + "o32 ABI", "bounded" > +}; > +#else > +#define bt_dbg(fmt, ...) do { } while (0) > +#endif > + > +/* > + * Value to be returned by functions that processes each frame to indicate > + * a non-error termination of the backtrace. Errors cause a negative errno > + * to be returned and a frame that does not terminate the back trace cause > + * a zero to be returned. > + */ > +define BASE_BT_END_NULL_PC 1 ^^^^^^^^^ Indent only by one space here. > +#define BASE_BT_N_END 1 > + > +/* > + * Macros for loading addresses and storing registers: > + * LOAD_ADDR Load the address of the given object into the $at register > + * STORE_REG Store the given register. Assumes that $at points to the > + * location for the store. > + */ > +#ifdef CONFIG_64BIT > +#warning TODO: 64-bit code needs to be verified > +#define LOAD_ADDR(obj) "dla $at," #obj "\n" > +#define STORE_REG(reg) "sd " #reg ",0($at)\n" > +#endif > + > +#ifdef CONFIG_32BIT > +#define LOAD_ADDR(obj) "la $at," #obj "\n" > +#define STORE_REG(reg) "sw " #reg ",0($at)\n" > +#endif LOAD_ADDR and STORE_REG appear to be unused. > + > +/* > + * __base_backtrace_here - set the PC, SP, and return address for current func > + * @bbt: Pointer to the &struct base_bt to set > + */ > +#define __base_backtrace_here(bbt) do { \ > + register unsigned long s0 asm("s0"); \ > + register unsigned long s1 asm("s1"); \ > + register unsigned long s2 asm("s2"); \ > + register unsigned long s3 asm("s3"); \ > + register unsigned long s4 asm("s4"); \ > + register unsigned long s5 asm("s5"); \ > + register unsigned long s6 asm("s6"); \ > + register unsigned long s7 asm("s7"); \ > + register unsigned long fp asm("fp"); \ > + register unsigned long gp asm("gp"); \ > + (bbt)->pc = __base_backtrace_here_pc(); \ > + (bbt)->sp = __builtin_frame_address(0); \ > + (bbt)->ra = __builtin_return_address(0); \ > + (bbt)->gprs[SREG_S0].value = s0; \ > + (bbt)->gprs[SREG_S1].value = s1; \ > + (bbt)->gprs[SREG_S2].value = s2; \ > + (bbt)->gprs[SREG_S3].value = s3; \ > + (bbt)->gprs[SREG_S4].value = s4; \ > + (bbt)->gprs[SREG_S5].value = s5; \ > + (bbt)->gprs[SREG_S6].value = s6; \ > + (bbt)->gprs[SREG_S7].value = s7; \ > + (bbt)->gprs[SREG_S8].value = fp; \ > + (bbt)->gprs[SREG_GP].value = gp; \ > + (bbt)->gprs[SREG_RA].value = (unsigned long)(bbt)->ra;\ > + (bbt)->gprs[SREG_S0].read = true; \ > + (bbt)->gprs[SREG_S1].read = true; \ > + (bbt)->gprs[SREG_S2].read = true; \ > + (bbt)->gprs[SREG_S3].read = true; \ > + (bbt)->gprs[SREG_S4].read = true; \ > + (bbt)->gprs[SREG_S5].read = true; \ > + (bbt)->gprs[SREG_S6].read = true; \ > + (bbt)->gprs[SREG_S7].read = true; \ > + (bbt)->gprs[SREG_S8].read = true; \ > + (bbt)->gprs[SREG_GP].read = true; \ > + (bbt)->gprs[SREG_RA].read = true; \ > + (bbt)->next_pc = NULL; \ > + } while (0) > + > +/* > + * base_backtrace_first - process the first stack frame. > + * @bt: Pointer to struct base_bt object. > + * Returns: Zero on success, otherwise a negative errno value. > + * A value of -ENOSYS indicates that the $pc and $sp are valid > + * but we can't continue the backtrace. > + */ > +#define base_backtrace_first(bbt, rule) ({ \ > + memset(bbt, 0, sizeof(*(bbt))); \ > + __base_backtrace_here(bbt); \ > + __base_backtrace_analyze_frame(bbt, rule); \ > + }) > + > +/* General purpose register (GPR) numbers */ > +enum mips_reg_num { > + MREG_ZERO, MREG_AT, MREG_V0, MREG_V1, > + MREG_A0, MREG_A1, MREG_A2, MREG_A3, > + MREG_T0, MREG_T1, MREG_T2, MREG_T3, > + MREG_T4, MREG_T5, MREG_T6, MREG_T7, > + MREG_S0, MREG_S1, MREG_S2, MREG_S3, > + MREG_S4, MREG_S5, MREG_S6, MREG_S7, > + MREG_T8, MREG_T9, MREG_K0, MREG_K1, > + MREG_GP, MREG_SP, MREG_S8, MREG_RA, > + N_MREGS /* This last one is the number of GPRs */ > +}; > + > +/* Indices into list of GPRs that must be saved before use */ > +enum saved_gpr_num { > + SREG_S0, SREG_S1, SREG_S2, SREG_S3, > + SREG_S4, SREG_S5, SREG_S6, SREG_S7, > + SREG_GP, SREG_S8, SREG_RA, > + N_SREGS /* Number of saved gprs */ > +}; > + > +/* True if the corresponding MIPS register must be saved before use */ You mean a callee-saved register? > +extern const bool save_before_use[N_MREGS]; > + > +/* Convert saved_gpr_num to mips_reg_num */ > +extern const enum mips_reg_num sreg_to_mreg[N_SREGS]; > + > +/* Convert mips_reg_num to saved_gpr_num */ > +extern const enum saved_gpr_num mreg_to_sreg[N_MREGS]; > + > +/* > + * Additional instruction formats that might be nice to define in > + * asm/inst.h > + * */ > +#ifdef __MIPSEB__ > + struct any_format { /* Generic format */ > + unsigned int opcode:6; > + unsigned int remainder:26; > + }; This is the same as struct j_format but I don't mind if you want to call it a 2nd time to inst.h. with a different name. > + struct syscall_format { > + unsigned int opcode:6; > + unsigned int code:20; > + unsigned int func:6; > + }; This format is called b_format in > + struct eret_format { > + unsigned int opcode:6; > + unsigned int co:1; > + unsigned int zero:19; > + unsigned int func:6; > + }; > +#else > + struct any_format { /* Generic format */ > + unsigned int remainder:26; > + unsigned int opcode:6; > + }; > + > + struct syscall_format { > + unsigned int func:6; > + unsigned int code:20; > + unsigned int opcode:6; > + }; > + > + struct eret_format { > + unsigned int func:6; > + unsigned int zero:19; > + unsigned int co:1; > + unsigned int opcode:6; > + }; Same comments as for he structs above apply here, too. > +#endif I think this may need a few additions to handle some processor specific enhancements such as Cavium's BBIT0 etc. family of branches. > +#ifdef SPECIAL_SYMBOL > +/* arch/mips/kernel/entry.S */ > +SPECIAL_SYMBOL(ret_from_exception, KERNEL_FRAME_GLUE) > +SPECIAL_SYMBOL(ret_from_irq, KERNEL_FRAME_GLUE) [...] We could modify RESTORE_SOME etc. to automatically generate a table of these SPECIAL_SYMBOLs instead of manually maintaining this table? > +/* > + * __thread_backtrace_here - gets the PC and SP register values for the invoker > + * @tbt: Pointer to the struct thread_bt structure to set > + */ > +#define __thread_backtrace_here(tbt) do { \ > + __base_backtrace_here(&(tbt)->bbt); \ > + } while (0) Only used by thread_backtrace_first which itself is unused. > +/* > + * thread_backtrace_first - Get information for the first stack frame > + * @tbt: Pointer to trace_backtrace_t object initialized with > + * thread_backtrace_init. > + * @rule: Rules to use for analyzing the function > + * Returns: Zero on success, a negative errno otherwise. > + */ > +#define thread_backtrace_first(tbt, rule) ({ \ > + memset(tbt, 0, sizeof(*(tbt))); \ > + __thread_backtrace_here(tbt); \ > + __thread_backtrace_analyze_frame(tbt, rule); \ > + }) This macro is unused. > diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S > index 37acfa0..6548ae3 100644 > --- a/arch/mips/kernel/entry.S > +++ b/arch/mips/kernel/entry.S > @@ -40,9 +40,10 @@ FEXPORT(__ret_from_irq) > andi t0, t0, KU_USER > beqz t0, resume_kernel > > + .globl resume_userspace > resume_userspace: > local_irq_disable # make sure we dont miss an > - # interrupt setting need_resched > + # interrupt setting _need_resched Huh? The comment should say _TIF_NEED_RESCHED - but that's to long for the 80 colums. > index e9b3af2..dbf53b5 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -53,6 +53,7 @@ > #include > #include > #include > +#include > #include > > extern void check_wait(void); > @@ -86,6 +87,8 @@ extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, > struct mips_fpu_struct *ctx, int has_fpu, > void *__user *fault_addr); > > +#define MAX_STACK_FRAMES_PRINTED 100 Is this needed? The size of the stack should limit the dump naturally and the code need some sort of safeguard to protect against running beyond the end of the stack anyway. > + * If we do not have a branch delay slot, we also know that the > + * following instruction is not in a branch delay slot. If we are > + * not at the branch delay slot, we also know that the next instruction > + * can't be in a branch delay slot since that would have meant that > + * the instruction in our branch delay slot had a branch delay slot. > + * That's a no-no, so we don't worry about it. > + */ > +#if 1 Ehhh what? > + if (!vpc->have_bds) > + rc = __vpc_might_have_bds(vpc, vpc->pc + 1); > + else if (!vpc->in_bds) > + rc = __vpc_might_have_bds(vpc, vpc->pc + 2); > + else > + vpc->in_bds = false; > +#else > + if (!vpc->have_bds) > + rc = __vpc_might_have_bds(vpc, vpc->pc + 1); > + else if (!vpc->in_bds) > + rc = __vpc_might_have_bds(vpc, vpc->pc + 2); > + else > + vpc->in_bds = false; > +#endif I may be blind but the #if and the #else branch look identical. > + * match_short_get_got - checks for a match for short GOT recovery code > + * @in_vpc: Pointer to the &struct vpc for the instruction at which > + * the GOT recovery code may start. > + * > + * Returns: true if it matches, zero if it does not. > + * > + * Matches the code fragment: > + * li gp, > + * addu gp, gp, t9 > + * which is a short version of the code used to recover the GOT (global offset > + * table) pointer from the address of the current function. But there is no GOT in the kernel?? > +/* > + * find_return_abi - Find the end of the function by o32 ABI rules. > + * @bt: Pointer to struct base_bt object. > + * Returns: Zero if we found the end of the function, a negative errno value > + * if we could not. > + * > + * If the function was found, ctx->fn_return will point to the "jr ra" > + * instruction, otherwise it will be set to NULL. > + * If the function was not found, ctx->fn_return will be set to NULL_REG. > + */ > +static int find_return_abi(struct base_bt_ctx *ctx) > +{ > + int rc; > + struct vpc vpc; > + mips_instruction op; > + > + ctx->fn_return = NULL; > + > + /* Scan forward to find the "jr ra" that marks the end > + * of the current function */ Not really; gcc may place move part of the code path behind the jr $ra even though that violates the O32 ABI spec. In the kernel this happens for do_one_initcall(), mips_display_message() and more. And that's generally my concern with this approach - GCC's optimizer is becoming very good in the most recent versions. In in the long run I see us forced to go down the DWARF alley but of course the 10, 20% bloat won't be popular. But if users tell me they like this apprach and in practice it works well enough then I'm all for it. > +/* > + * This handles getting the next kernel stackframe. It checks to see if we are > + * in an exception or interrupt frame. If not, we just pass it along to the > + * process backtracing. > + * @kbt: Pointer to the struct kernel_bt object > + * > + * Returns: KERNEL_BT_END_IN_START_KERNEL The backtrace should stop > + * because the next frame is for > + * start_kernel(), whose memory has > + * probably been freed and overwritten. Not sure if it's worth the pain but we could set a flag in free_init_mem so kernel_backtrace_next would know if start_kernel is stil available. > diff --git a/scripts/module-common.lds b/scripts/module-common.lds > deleted file mode 100644 > index 0865b3e..0000000 > --- a/scripts/module-common.lds > +++ /dev/null > @@ -1,19 +0,0 @@ > -/* Looks like an accidental deletion? Ralf From wuzhangjin@gmail.com Tue Aug 2 18:07:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 18:07:58 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:47874 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491177Ab1HBQHv convert rfc822-to-8bit (ORCPT ); Tue, 2 Aug 2011 18:07:51 +0200 Received: by wwi18 with SMTP id 18so5816574wwi.24 for ; Tue, 02 Aug 2011 09:07:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=LOUNS+qtfOaNJvLn65M19TCzLhF5cHLuIKY6uRF4ego=; b=xtzqoO/uK6iVz1LImduXoUtRdhsEaNm6rDmAmaDkZK9YwTJNDN7kd8I6WIvdYNMTV+ 9wGuQI6VE7neSrjHFKD51mnlI+6IY0F13pvOW+DUV/nuUpoqsHe7oZPwa6imSAozPS1M hEr0KHShgDGZZ9RCzxMz5ecq5In6NVPKEHUH4= MIME-Version: 1.0 Received: by 10.216.90.19 with SMTP id d19mr777981wef.35.1312301257532; Tue, 02 Aug 2011 09:07:37 -0700 (PDT) Received: by 10.216.16.149 with HTTP; Tue, 2 Aug 2011 09:07:37 -0700 (PDT) In-Reply-To: <1312194382-3706-2-git-send-email-florian@openwrt.org> References: <1312194382-3706-1-git-send-email-florian@openwrt.org> <1312194382-3706-2-git-send-email-florian@openwrt.org> Date: Wed, 3 Aug 2011 00:07:37 +0800 Message-ID: Subject: Re: [PATCH 2/3] MIPS: introduce CPU_R4K_FPU From: wu zhangjin To: Florian Fainelli Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 30795 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1540 Content-Length: 2795 Lines: 70 On Mon, Aug 1, 2011 at 6:26 PM, Florian Fainelli wrote: > R4K-style CPUs have this boolean defined by default. Allows us > to remove some lines in arch/mips/kernel/Makefile > > Signed-off-by: Florian Fainelli > --- >  arch/mips/Kconfig         |    4 ++++ >  arch/mips/kernel/Makefile |   17 +---------------- >  2 files changed, 5 insertions(+), 16 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 9f4ade4..44eebc7 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1807,6 +1807,10 @@ config CPU_GENERIC_DUMP_TLB >        bool >        default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX) > > +config CPU_R4K_FPU > +       bool > +       default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) > + >  choice >        prompt "MIPS MT options" > > diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile > index 83bba33..eeb942d 100644 > --- a/arch/mips/kernel/Makefile > +++ b/arch/mips/kernel/Makefile > @@ -32,25 +32,10 @@ obj-$(CONFIG_MODULES)               += mips_ksyms.o module.o > >  obj-$(CONFIG_FUNCTION_TRACER)  += mcount.o ftrace.o > > -obj-$(CONFIG_CPU_LOONGSON2)    += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_MIPS32)       += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_MIPS64)       += r4k_fpu.o r4k_switch.o > +obj-$(CONFIG_CPU_R4K_FPU)      += r4k_fpu.o r4k_switch.o >  obj-$(CONFIG_CPU_R3000)                += r2300_fpu.o r2300_switch.o > -obj-$(CONFIG_CPU_R4300)                += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_R4X00)                += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_R5000)                += r4k_fpu.o r4k_switch.o >  obj-$(CONFIG_CPU_R6000)                += r6000_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_R5432)                += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_R5500)                += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_R8000)                += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_RM7000)       += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_RM9000)       += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_NEVADA)       += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_R10000)       += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_SB1)          += r4k_fpu.o r4k_switch.o >  obj-$(CONFIG_CPU_TX39XX)       += r2300_fpu.o r2300_switch.o > -obj-$(CONFIG_CPU_TX49XX)       += r4k_fpu.o r4k_switch.o > -obj-$(CONFIG_CPU_VR41XX)       += r4k_fpu.o r4k_switch.o >  obj-$(CONFIG_CPU_CAVIUM_OCTEON)        += octeon_switch.o >  obj-$(CONFIG_CPU_XLR)          += r4k_fpu.o r4k_switch.o Seems the above line can be removed too, this may remove them automatically: $ sed -i -e '/r4k_fpu.o\s*r4k_switch/d' -e '/r4k_switch.o\s*r4k_fpu/d' arch/mips/kernel/Makefile Best Regards, Wu Zhangjin > > -- > 1.7.4.1 > > > From manuel.lauss@googlemail.com Tue Aug 2 19:51:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:51:25 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:36145 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491200Ab1HBRvU (ORCPT ); Tue, 2 Aug 2011 19:51:20 +0200 Received: by fxd20 with SMTP id 20so73158fxd.36 for ; Tue, 02 Aug 2011 10:51:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=PX1elwv7/P436uVn2ExCvFKvnYqbVFOZ2JIacdIYxXQ=; b=vEXXR7bzgI/EPaJQwCFBKKIqsfDUVM0Y4ZQ68FHXloLqbVJB9vK+3kHZ9cMSizQkf6 MnDcECiB8g61scUT7m0ARYbWzYdDN4bmevrrCS3o0Hp4NBqQitGyaQV1IT9mfY3lZ3Uh KgRnzZjGnwL60YObArPaOEGHPdZOr+vfRyF68= Received: by 10.223.10.143 with SMTP id p15mr8431884fap.12.1312307475453; Tue, 02 Aug 2011 10:51:15 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.13 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:14 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 00/15] MIPS: Alchemy updates Date: Tue, 2 Aug 2011 19:50:55 +0200 Message-Id: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 X-archive-position: 30796 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1611 Content-Length: 6572 Lines: 123 Here's another round of Alchemy updates. It contains stuff I posted previously plus some additional patches which accumulated in the meantime. Patch 1 fixes a typo, Patch 2 removes the last hardcoded base address from Alchemy ethernet driver, Patch 3 fixes suspend to ram on au1100 (it didn't enter it), Patches 4-6 move knowledge of per-chip USB setup out of the glues into a common file, clean up USB setup and header information. Patch 8 refactors GPIO a bit so that Au1000 and Au1300 GPIO headers can be included at the same time, and in case of GPIOLIB=y, the correct gpiochip is registered at runtime. Patches 9-15 prepare for and remove all of the CONFIG_SOC_AU1??? symbols and the "au1xxx.h" header. Patch 9 removes au1xxx.h dependency from the old au1200 ide driver. Patch 11 kills it, Patch 10 removes CONFIG_SOC_AU1??? from DMA/DBDMA code Patch 12 does the same for au1xmmc.c Patches 13-14 rewrite Alchemy PCI support as a platform driver. Patch 15 finally does away with CONFIG_SOC_AU1???. Some of the devices registered in platform.c have to be moved to the boards actually using them. I haven't yet tried it, but it should now theoretically be possible to build one kernel which runs on all of the evaluation boards. The whole pile has been compile tested with all alchemy defconfigs and run-tested on Db1100,Db1200,Db1500,Db1550 and Db1300. Manuel Lauss (15): MIPS: Alchemy: fix typo in MAC0 registration net: au1000_eth: pass MACDMA address through platform resource info. MIPS: Alchemy: include Au1100 in PM code. MIPS: Alchemy: abstract USB block control register access MIPS: Alchemy: rewrite USB platform setup. MIPS: Alchemy: more base address cleanup MIPS: Alchemy: always build power code MIPS: Alchemy: support multiple GPIO styles in one kernel MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dependencies MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines MIPS: Alchemy: kill au1xxx.h header MMC: au1xmmc: remove Alchemy CPU subtype dependencies MIPS: remove __init from add_wired_entry() MIPS: Alchemy: redo PCI as platform driver MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines arch/mips/Kconfig | 2 + arch/mips/alchemy/Kconfig | 50 +-- arch/mips/alchemy/common/Makefile | 8 +- arch/mips/alchemy/common/dbdma.c | 203 ++++----- arch/mips/alchemy/common/dma.c | 72 ++-- arch/mips/alchemy/common/gpiolib-au1000.c | 126 ----- arch/mips/alchemy/common/gpiolib.c | 133 +++++ arch/mips/alchemy/common/pci.c | 104 ---- arch/mips/alchemy/common/platform.c | 372 ++++----------- arch/mips/alchemy/common/power.c | 68 +-- arch/mips/alchemy/common/setup.c | 6 +- arch/mips/alchemy/common/usb.c | 337 +++++++++++++ arch/mips/alchemy/devboards/db1200/platform.c | 153 +++++-- arch/mips/alchemy/devboards/db1x00/board_setup.c | 28 +- arch/mips/alchemy/devboards/db1x00/platform.c | 199 +++++++- arch/mips/alchemy/devboards/pb1100/platform.c | 49 ++- arch/mips/alchemy/devboards/pb1200/platform.c | 190 +++++++- arch/mips/alchemy/devboards/pb1500/board_setup.c | 33 +- arch/mips/alchemy/devboards/pb1500/platform.c | 71 +++- arch/mips/alchemy/devboards/pb1550/board_setup.c | 6 - arch/mips/alchemy/devboards/pb1550/platform.c | 119 ++++- arch/mips/alchemy/gpr/board_setup.c | 12 - arch/mips/alchemy/gpr/platform.c | 47 ++ arch/mips/alchemy/mtx-1/board_setup.c | 40 -- arch/mips/alchemy/mtx-1/platform.c | 62 +++ arch/mips/alchemy/xxs1500/board_setup.c | 8 - arch/mips/alchemy/xxs1500/platform.c | 12 +- arch/mips/include/asm/mach-au1x00/au1000.h | 559 ++++++++-------------- arch/mips/include/asm/mach-au1x00/au1xxx.h | 43 -- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 114 +++--- arch/mips/include/asm/mach-au1x00/au1xxx_ide.h | 1 + arch/mips/include/asm/mach-au1x00/au1xxx_psc.h | 26 - arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 31 +-- arch/mips/include/asm/mach-au1x00/gpio.h | 79 +++- arch/mips/include/asm/mach-db1x00/db1200.h | 2 - arch/mips/include/asm/mach-db1x00/db1x00.h | 16 +- arch/mips/include/asm/mach-pb1x00/pb1200.h | 18 +- arch/mips/include/asm/mach-pb1x00/pb1550.h | 16 +- arch/mips/mm/tlb-r3k.c | 4 +- arch/mips/mm/tlb-r4k.c | 4 +- arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-au1000.c | 43 -- arch/mips/pci/ops-au1000.c | 308 ------------ arch/mips/pci/pci-alchemy.c | 500 +++++++++++++++++++ drivers/i2c/busses/Kconfig | 2 +- drivers/i2c/busses/i2c-au1550.c | 2 +- drivers/ide/Kconfig | 6 +- drivers/ide/au1xxx-ide.c | 46 +- drivers/mmc/host/Kconfig | 2 +- drivers/mmc/host/au1xmmc.c | 93 ++-- drivers/mtd/nand/Kconfig | 2 +- drivers/mtd/nand/au1550nd.c | 6 +- drivers/net/au1000_eth.c | 48 ++- drivers/net/au1000_eth.h | 2 +- drivers/net/irda/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/usb/Kconfig | 1 - drivers/usb/host/ehci-au1xxx.c | 77 +--- drivers/usb/host/ehci-hcd.c | 2 +- drivers/usb/host/ohci-au1xxx.c | 110 +---- drivers/video/Kconfig | 4 +- sound/mips/Kconfig | 2 +- sound/soc/au1x/Kconfig | 2 +- 63 files changed, 2514 insertions(+), 2174 deletions(-) delete mode 100644 arch/mips/alchemy/common/gpiolib-au1000.c create mode 100644 arch/mips/alchemy/common/gpiolib.c delete mode 100644 arch/mips/alchemy/common/pci.c create mode 100644 arch/mips/alchemy/common/usb.c delete mode 100644 arch/mips/include/asm/mach-au1x00/au1xxx.h delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.c -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:51:53 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:33355 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491202Ab1HBRvW (ORCPT ); Tue, 2 Aug 2011 19:51:22 +0200 Received: by fxd20 with SMTP id 20so73189fxd.36 for ; Tue, 02 Aug 2011 10:51:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=E5TMJ74bk9AKptiOrFpoqm36gTnDcR1m3PV44DG4kdw=; b=SukXTT0JXE4yFa4qOyRMS9MPd61aGXrQaXxvI2xGpXt3qMMNTkY9q8DLVyheVosKF+ ShUfImexHs/jRS9aacc4UFVYvFv/0J0cd7aklEnKhWbSfwfvW+fP8ELqVBhUu+igQKrZ 6KtphkzBTOy1gDNA/wcZ/ROfKdChoNWLDREl0= Received: by 10.223.18.25 with SMTP id u25mr8394492faa.69.1312307476915; Tue, 02 Aug 2011 10:51:16 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.15 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:16 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 01/15] MIPS: Alchemy: fix typo in MAC0 registration Date: Tue, 2 Aug 2011 19:50:56 +0200 Message-Id: <1312307470-6841-2-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30797 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1612 Content-Length: 726 Lines: 24 Harmless typo which prints an error message although MAC0 was registered successfully. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 3b2c18b..f72c48d 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -492,7 +492,7 @@ static void __init alchemy_setup_macs(int ctype) memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6); ret = platform_device_register(&au1xxx_eth0_device); - if (!ret) + if (ret) printk(KERN_INFO "Alchemy: failed to register MAC0\n"); -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:52:21 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:36145 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491204Ab1HBRvX (ORCPT ); Tue, 2 Aug 2011 19:51:23 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73158fxd.36 for ; Tue, 02 Aug 2011 10:51:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Ipe+aVzkdBsUfk3u/EfXH+/WizORcOlSLcmeO0sCoVQ=; b=FM4CwHeswV2XrPbLxJMZmljP6gz4/dNOdwKg6RsyBElpaSj4x3k6ot5QtwIrO9LUHy Ox/jBjczQ2zkmvEnuZ5pWxpjag0CzFQkKbasBZMhfxj0d9AEGLr9FIftLKM7jgbmP/qF MKMXc1vXz4UMQaxP9OvUiqZxKtUOLLooP0OLI= Received: by 10.223.97.134 with SMTP id l6mr853184fan.10.1312307483048; Tue, 02 Aug 2011 10:51:23 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.20 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:21 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss , Subject: [PATCH 04/15] MIPS: Alchemy: abstract USB block control register access Date: Tue, 2 Aug 2011 19:50:59 +0200 Message-Id: <1312307470-6841-5-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30798 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1613 Content-Length: 28200 Lines: 925 Au1200 and Au1300 have one or more registers which control access to the usb blocks as well as PHY configuration. I don't want the OHCI/EHCI glues to know about the different registers and bits, a new file hides the gory details of USB configuration from them. Cc: Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/Makefile | 2 +- arch/mips/alchemy/common/dma.c | 12 +- arch/mips/alchemy/common/power.c | 42 ---- arch/mips/alchemy/common/usb.c | 337 ++++++++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/au1000.h | 84 ++------ drivers/usb/host/ehci-au1xxx.c | 77 +------ drivers/usb/host/ohci-au1xxx.c | 110 +-------- 7 files changed, 382 insertions(+), 282 deletions(-) create mode 100644 arch/mips/alchemy/common/usb.c diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 27811fe..575db47 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -6,7 +6,7 @@ # obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ - sleeper.o dma.o dbdma.o + sleeper.o dma.o dbdma.o usb.o obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c index 347980e..6652a23 100644 --- a/arch/mips/alchemy/common/dma.c +++ b/arch/mips/alchemy/common/dma.c @@ -88,12 +88,12 @@ static const struct dma_dev { { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */ { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */ { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */ - { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ - { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ - { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ - { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ - { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ - { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ + { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ + { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ + { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ + { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ + { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ + { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */ { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */ { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */ diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index b86324a..e53b4ce 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -49,7 +49,6 @@ * We only have to save/restore registers that aren't otherwise * done as part of a driver pm_* function. */ -static unsigned int sleep_usb[2]; static unsigned int sleep_sys_clocks[5]; static unsigned int sleep_sys_pinfunc; static unsigned int sleep_static_memctlr[4][3]; @@ -57,31 +56,6 @@ static unsigned int sleep_static_memctlr[4][3]; static void save_core_regs(void) { -#ifndef CONFIG_SOC_AU1200 - /* Shutdown USB host/device. */ - sleep_usb[0] = au_readl(USB_HOST_CONFIG); - - /* There appears to be some undocumented reset register.... */ - au_writel(0, 0xb0100004); - au_sync(); - au_writel(0, USB_HOST_CONFIG); - au_sync(); - - sleep_usb[1] = au_readl(USBD_ENABLE); - au_writel(0, USBD_ENABLE); - au_sync(); - -#else /* AU1200 */ - - /* enable access to OTG mmio so we can save OTG CAP/MUX. - * FIXME: write an OTG driver and move this stuff there! - */ - au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); - au_sync(); - sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ - sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ -#endif - /* Clocks and PLLs. */ sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); @@ -125,22 +99,6 @@ static void restore_core_regs(void) au_writel(sleep_sys_pinfunc, SYS_PINFUNC); au_sync(); -#ifndef CONFIG_SOC_AU1200 - au_writel(sleep_usb[0], USB_HOST_CONFIG); - au_writel(sleep_usb[1], USBD_ENABLE); - au_sync(); -#else - /* enable access to OTG memory */ - au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); - au_sync(); - - /* restore OTG caps and port mux. */ - au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ - au_sync(); - au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ - au_sync(); -#endif - /* Restore the static memory controller configuration. */ au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c new file mode 100644 index 0000000..b4192c9 --- /dev/null +++ b/arch/mips/alchemy/common/usb.c @@ -0,0 +1,337 @@ +/* + * USB block power/access management abstraction. + * + * Au1000+: The OHCI block control register is at the far end of the OHCI memory + * area. Au1550 has OHCI on different base address. No need to handle + * UDC here. + * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG + * as well as the PHY for EHCI and UDC. + * + */ + +#include +#include +#include +#include +#include +#include + +/* control register offsets */ +#define AU1000_OHCICFG 0x7fffc +#define AU1550_OHCICFG 0x07ffc +#define AU1200_USBCFG 0x04 + +/* Au1000 USB block config bits */ +#define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */ +#define USBHEN_CE (1 << 3) /* OHCI block clock enable */ +#define USBHEN_E (1 << 2) /* OHCI block enable */ +#define USBHEN_C (1 << 1) /* OHCI block coherency bit */ +#define USBHEN_BE (1 << 0) /* OHCI Big-Endian */ + +/* Au1200 USB config bits */ +#define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */ +#define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */ +#define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */ +#define USBCFG_SSD (1 << 23) /* serial short detect en */ +#define USBCFG_PPE (1 << 19) /* HS PHY PLL */ +#define USBCFG_UCE (1 << 18) /* UDC clock enable */ +#define USBCFG_ECE (1 << 17) /* EHCI clock enable */ +#define USBCFG_OCE (1 << 16) /* OHCI clock enable */ +#define USBCFG_FLA(x) (((x) & 0x3f) << 8) +#define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */ +#define USBCFG_GME (1 << 6) /* OTG mem access */ +#define USBCFG_DBE (1 << 5) /* UDC busmaster enable */ +#define USBCFG_DME (1 << 4) /* UDC mem enable */ +#define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */ +#define USBCFG_EME (1 << 2) /* EHCI mem enable */ +#define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */ +#define USBCFG_OME (1 << 0) /* OHCI mem enable */ +#define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\ + USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \ + USBCFG_GME | USBCFG_DBE | USBCFG_DME | \ + USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \ + USBCFG_OME) + + +static DEFINE_SPINLOCK(alchemy_usb_lock); + + +static inline void __au1200_ohci_control(void __iomem *base, int enable) +{ + unsigned long r = __raw_readl(base + AU1200_USBCFG); + if (enable) { + __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG); + wmb(); + udelay(2000); + } else { + __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG); + wmb(); + udelay(1000); + } +} + +static inline void __au1200_ehci_control(void __iomem *base, int enable) +{ + unsigned long r = __raw_readl(base + AU1200_USBCFG); + if (enable) { + __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG); + wmb(); + udelay(1000); + } else { + if (!(r & USBCFG_UCE)) /* UDC also off? */ + r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */ + __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG); + wmb(); + udelay(1000); + } +} + +static inline void __au1200_udc_control(void __iomem *base, int enable) +{ + unsigned long r = __raw_readl(base + AU1200_USBCFG); + if (enable) { + __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG); + wmb(); + } else { + if (!(r & USBCFG_ECE)) /* EHCI also off? */ + r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */ + __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG); + wmb(); + } +} + +static inline int au1200_coherency_bug(void) +{ +#if defined(CONFIG_DMA_COHERENT) + /* Au1200 AB USB does not support coherent memory */ + if (!(read_c0_prid() & 0xff)) { + printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n"); + printk(KERN_INFO "Au1200 USB: update your board or re-configure" + " the kernel\n"); + return -ENODEV; + } +#endif + return 0; +} + +static inline int au1200_usb_control(int block, int enable) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR); + int ret = 0; + + switch (block) { + case ALCHEMY_USB_OHCI0: + ret = au1200_coherency_bug(); + if (ret && enable) + goto out; + __au1200_ohci_control(base, enable); + break; + case ALCHEMY_USB_UDC0: + __au1200_udc_control(base, enable); + break; + case ALCHEMY_USB_EHCI0: + ret = au1200_coherency_bug(); + if (ret && enable) + goto out; + __au1200_ehci_control(base, enable); + break; + default: + ret = -ENODEV; + } +out: + return ret; +} + + +/* initialize USB block(s) to a known working state */ +static inline void au1200_usb_init(void) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR); + __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG); + wmb(); + udelay(1000); +} + +static inline void au1000_usb_init(unsigned long rb, int reg) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); + unsigned long r = __raw_readl(base); + +#if defined(__BIG_ENDIAN) + r |= USBHEN_BE; +#endif + r |= USBHEN_C; + + __raw_writel(r, base); + wmb(); + udelay(1000); +} + + +static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(rb); + unsigned long r = __raw_readl(base + creg); + + if (enable) { + __raw_writel(r | USBHEN_CE, base + creg); + wmb(); + udelay(1000); + __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg); + wmb(); + udelay(1000); + + /* wait for reset complete (read reg twice: au1500 erratum) */ + while (__raw_readl(base + creg), + !(__raw_readl(base + creg) & USBHEN_RD)) + udelay(1000); + } else { + __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg); + wmb(); + } +} + +static inline int au1000_usb_control(int block, int enable, unsigned long rb, + int creg) +{ + int ret = 0; + + switch (block) { + case ALCHEMY_USB_OHCI0: + __au1xx0_ohci_control(enable, rb, creg); + break; + default: + ret = -ENODEV; + } + return ret; +} + +/* + * alchemy_usb_control - control Alchemy on-chip USB blocks + * @block: USB block to target + * @enable: set 1 to enable a block, 0 to disable + */ +int alchemy_usb_control(int block, int enable) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&alchemy_usb_lock, flags); + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + ret = au1000_usb_control(block, enable, + AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); + break; + case ALCHEMY_CPU_AU1550: + ret = au1000_usb_control(block, enable, + AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); + break; + case ALCHEMY_CPU_AU1200: + ret = au1200_usb_control(block, enable); + break; + default: + ret = -ENODEV; + } + spin_unlock_irqrestore(&alchemy_usb_lock, flags); + return ret; +} +EXPORT_SYMBOL_GPL(alchemy_usb_control); + + +static unsigned long alchemy_usb_pmdata[2]; + +static void au1000_usb_pm(unsigned long br, int creg, int susp) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(br); + + if (susp) { + alchemy_usb_pmdata[0] = __raw_readl(base + creg); + /* There appears to be some undocumented reset register.... */ + __raw_writel(0, base + 0x04); + wmb(); + __raw_writel(0, base + creg); + wmb(); + } else { + __raw_writel(alchemy_usb_pmdata[0], base + creg); + wmb(); + } +} + +static void au1200_usb_pm(int susp) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR); + if (susp) { + /* save OTG_CAP/MUX registers which indicate port routing */ + /* FIXME: write an OTG driver to do that */ + alchemy_usb_pmdata[0] = __raw_readl(base + 0x00); + alchemy_usb_pmdata[1] = __raw_readl(base + 0x04); + } else { + /* restore access to all MMIO areas */ + au1200_usb_init(); + + /* restore OTG_CAP/MUX registers */ + __raw_writel(alchemy_usb_pmdata[0], base + 0x00); + __raw_writel(alchemy_usb_pmdata[1], base + 0x04); + wmb(); + } +} + +static void alchemy_usb_pm(int susp) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp); + break; + case ALCHEMY_CPU_AU1550: + au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp); + break; + case ALCHEMY_CPU_AU1200: + au1200_usb_pm(susp); + break; + } +} + +static int alchemy_usb_suspend(void) +{ + alchemy_usb_pm(1); + return 0; +} + +static void alchemy_usb_resume(void) +{ + alchemy_usb_pm(0); +} + +static struct syscore_ops alchemy_usb_pm_ops = { + .suspend = alchemy_usb_suspend, + .resume = alchemy_usb_resume, +}; + +static int __init alchemy_usb_init(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); + break; + case ALCHEMY_CPU_AU1550: + au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); + break; + case ALCHEMY_CPU_AU1200: + au1200_usb_init(); + break; + } + + register_syscore_ops(&alchemy_usb_pm_ops); + + return 0; +} +arch_initcall(alchemy_usb_init); diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index f260ebe..73e0d79 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -245,6 +245,15 @@ void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); void au_sleep(void); +/* USB: arch/mips/alchemy/common/usb.c */ +enum alchemy_usb_block { + ALCHEMY_USB_OHCI0, + ALCHEMY_USB_UDC0, + ALCHEMY_USB_EHCI0, + ALCHEMY_USB_OTG0, +}; +int alchemy_usb_control(int block, int enable); + /* SOC Interrupt numbers */ @@ -687,7 +696,8 @@ enum soc_au1200_ints { */ #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ -#define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */ +#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ +#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ @@ -710,12 +720,17 @@ enum soc_au1200_ints { #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ +#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ +#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ +#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ +#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ +#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ +#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ #ifdef CONFIG_SOC_AU1000 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x10100000 #define IRDA_PHYS_ADDR 0x10300000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 @@ -729,7 +744,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1500 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x10100000 #define PCI_PHYS_ADDR 0x14005000 #define PCI_MEM_PHYS_ADDR 0x400000000ULL #define PCI_IO_PHYS_ADDR 0x500000000ULL @@ -745,7 +759,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1100 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x10100000 #define IRDA_PHYS_ADDR 0x10300000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 @@ -760,7 +773,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1550 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x14020000 #define PCI_PHYS_ADDR 0x14005000 #define PE_PHYS_ADDR 0x14008000 #define PSC0_PHYS_ADDR 0x11A00000 @@ -783,8 +795,6 @@ enum soc_au1200_ints { #define STATIC_MEM_PHYS_ADDR 0x14001000 #define AES_PHYS_ADDR 0x10300000 #define CIM_PHYS_ADDR 0x14004000 -#define USBM_PHYS_ADDR 0x14020000 -#define USBH_PHYS_ADDR 0x14020100 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 #define LCD_PHYS_ADDR 0x15000000 @@ -868,21 +878,6 @@ enum soc_au1200_ints { #define USB_EHCI_LEN 0x100 #define USB_UDC_BASE 0x14022000 #define USB_UDC_LEN 0x2000 -#define USB_MSR_BASE 0xB4020000 -#define USB_MSR_MCFG 4 -#define USBMSRMCFG_OMEMEN 0 -#define USBMSRMCFG_OBMEN 1 -#define USBMSRMCFG_EMEMEN 2 -#define USBMSRMCFG_EBMEN 3 -#define USBMSRMCFG_DMEMEN 4 -#define USBMSRMCFG_DBMEN 5 -#define USBMSRMCFG_GMEMEN 6 -#define USBMSRMCFG_OHCCLKEN 16 -#define USBMSRMCFG_EHCCLKEN 17 -#define USBMSRMCFG_UDCCLKEN 18 -#define USBMSRMCFG_PHYPLLEN 19 -#define USBMSRMCFG_RDCOMB 30 -#define USBMSRMCFG_PFEN 31 #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT @@ -963,51 +958,6 @@ enum soc_au1200_ints { #define USB_OHCI_LEN 0x00100000 #endif -#ifndef CONFIG_SOC_AU1200 - -/* USB Device Controller */ -#define USBD_EP0RD 0xB0200000 -#define USBD_EP0WR 0xB0200004 -#define USBD_EP2WR 0xB0200008 -#define USBD_EP3WR 0xB020000C -#define USBD_EP4RD 0xB0200010 -#define USBD_EP5RD 0xB0200014 -#define USBD_INTEN 0xB0200018 -#define USBD_INTSTAT 0xB020001C -# define USBDEV_INT_SOF (1 << 12) -# define USBDEV_INT_HF_BIT 6 -# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) -# define USBDEV_INT_CMPLT_BIT 0 -# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) -#define USBD_CONFIG 0xB0200020 -#define USBD_EP0CS 0xB0200024 -#define USBD_EP2CS 0xB0200028 -#define USBD_EP3CS 0xB020002C -#define USBD_EP4CS 0xB0200030 -#define USBD_EP5CS 0xB0200034 -# define USBDEV_CS_SU (1 << 14) -# define USBDEV_CS_NAK (1 << 13) -# define USBDEV_CS_ACK (1 << 12) -# define USBDEV_CS_BUSY (1 << 11) -# define USBDEV_CS_TSIZE_BIT 1 -# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) -# define USBDEV_CS_STALL (1 << 0) -#define USBD_EP0RDSTAT 0xB0200040 -#define USBD_EP0WRSTAT 0xB0200044 -#define USBD_EP2WRSTAT 0xB0200048 -#define USBD_EP3WRSTAT 0xB020004C -#define USBD_EP4RDSTAT 0xB0200050 -#define USBD_EP5RDSTAT 0xB0200054 -# define USBDEV_FSTAT_FLUSH (1 << 6) -# define USBDEV_FSTAT_UF (1 << 5) -# define USBDEV_FSTAT_OF (1 << 4) -# define USBDEV_FSTAT_FCNT_BIT 0 -# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) -#define USBD_ENABLE 0xB0200058 -# define USBDEV_ENABLE (1 << 1) -# define USBDEV_CE (1 << 0) - -#endif /* !CONFIG_SOC_AU1200 */ /* Ethernet Controllers */ diff --git a/drivers/usb/host/ehci-au1xxx.c b/drivers/usb/host/ehci-au1xxx.c index 42ae574..e480dc1 100644 --- a/drivers/usb/host/ehci-au1xxx.c +++ b/drivers/usb/host/ehci-au1xxx.c @@ -14,61 +14,9 @@ #include #include -#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG) -#define USB_MCFG_PFEN (1<<31) -#define USB_MCFG_RDCOMB (1<<30) -#define USB_MCFG_SSDEN (1<<23) -#define USB_MCFG_PHYPLLEN (1<<19) -#define USB_MCFG_UCECLKEN (1<<18) -#define USB_MCFG_EHCCLKEN (1<<17) -#ifdef CONFIG_DMA_COHERENT -#define USB_MCFG_UCAM (1<<7) -#else -#define USB_MCFG_UCAM (0) -#endif -#define USB_MCFG_EBMEN (1<<3) -#define USB_MCFG_EMEMEN (1<<2) - -#define USBH_ENABLE_CE (USB_MCFG_PHYPLLEN | USB_MCFG_EHCCLKEN) -#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \ - USBH_ENABLE_CE | USB_MCFG_SSDEN | \ - USB_MCFG_UCAM | USB_MCFG_EBMEN | \ - USB_MCFG_EMEMEN) - -#define USBH_DISABLE (USB_MCFG_EBMEN | USB_MCFG_EMEMEN) extern int usb_disabled(void); -static void au1xxx_start_ehc(void) -{ - /* enable clock to EHCI block and HS PHY PLL*/ - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - /* enable EHCI mmio */ - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG); - au_sync(); - udelay(1000); -} - -static void au1xxx_stop_ehc(void) -{ - unsigned long c; - - /* Disable mem */ - au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - /* Disable EHC clock. If the HS PHY is unused disable it too. */ - c = au_readl(USB_HOST_CONFIG) & ~USB_MCFG_EHCCLKEN; - if (!(c & USB_MCFG_UCECLKEN)) /* UDC disabled? */ - c &= ~USB_MCFG_PHYPLLEN; /* yes: disable HS PHY PLL */ - au_writel(c, USB_HOST_CONFIG); - au_sync(); -} - static int au1xxx_ehci_setup(struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); @@ -136,16 +84,6 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) if (usb_disabled()) return -ENODEV; -#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT) - /* Au1200 AB USB does not support coherent memory */ - if (!(read_c0_prid() & 0xff)) { - printk(KERN_INFO "%s: this is chip revision AB!\n", pdev->name); - printk(KERN_INFO "%s: update your board or re-configure" - " the kernel\n", pdev->name); - return -ENODEV; - } -#endif - if (pdev->resource[1].flags != IORESOURCE_IRQ) { pr_debug("resource[1] is not IORESOURCE_IRQ"); return -ENOMEM; @@ -171,7 +109,11 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) goto err2; } - au1xxx_start_ehc(); + if (alchemy_usb_control(ALCHEMY_USB_EHCI0, 1)) { + printk(KERN_INFO "%s: controller init failed!\n", pdev->name); + ret = -ENODEV; + goto err3; + } ehci = hcd_to_ehci(hcd); ehci->caps = hcd->regs; @@ -187,7 +129,8 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) return ret; } - au1xxx_stop_ehc(); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); +err3: iounmap(hcd->regs); err2: release_mem_region(hcd->rsrc_start, hcd->rsrc_len); @@ -201,10 +144,10 @@ static int ehci_hcd_au1xxx_drv_remove(struct platform_device *pdev) struct usb_hcd *hcd = platform_get_drvdata(pdev); usb_remove_hcd(hcd); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); - au1xxx_stop_ehc(); platform_set_drvdata(pdev, NULL); return 0; @@ -236,7 +179,7 @@ static int ehci_hcd_au1xxx_drv_suspend(struct device *dev) // could save FLADJ in case of Vaux power loss // ... we'd only use it to handle clock skew - au1xxx_stop_ehc(); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); return rc; } @@ -246,7 +189,7 @@ static int ehci_hcd_au1xxx_drv_resume(struct device *dev) struct usb_hcd *hcd = dev_get_drvdata(dev); struct ehci_hcd *ehci = hcd_to_ehci(hcd); - au1xxx_start_ehc(); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 1); // maybe restore FLADJ diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index 958d985..299d719 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -23,92 +23,9 @@ #include -#ifndef CONFIG_SOC_AU1200 - -#define USBH_ENABLE_BE (1<<0) -#define USBH_ENABLE_C (1<<1) -#define USBH_ENABLE_E (1<<2) -#define USBH_ENABLE_CE (1<<3) -#define USBH_ENABLE_RD (1<<4) - -#ifdef __LITTLE_ENDIAN -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) -#elif defined(__BIG_ENDIAN) -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | \ - USBH_ENABLE_BE) -#else -#error not byte order defined -#endif - -#else /* Au1200 */ - -#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG) -#define USB_MCFG_PFEN (1<<31) -#define USB_MCFG_RDCOMB (1<<30) -#define USB_MCFG_SSDEN (1<<23) -#define USB_MCFG_OHCCLKEN (1<<16) -#ifdef CONFIG_DMA_COHERENT -#define USB_MCFG_UCAM (1<<7) -#else -#define USB_MCFG_UCAM (0) -#endif -#define USB_MCFG_OBMEN (1<<1) -#define USB_MCFG_OMEMEN (1<<0) - -#define USBH_ENABLE_CE USB_MCFG_OHCCLKEN - -#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \ - USBH_ENABLE_CE | USB_MCFG_SSDEN | \ - USB_MCFG_UCAM | \ - USB_MCFG_OBMEN | USB_MCFG_OMEMEN) - -#define USBH_DISABLE (USB_MCFG_OBMEN | USB_MCFG_OMEMEN) - -#endif /* Au1200 */ extern int usb_disabled(void); -static void au1xxx_start_ohc(void) -{ - /* enable host controller */ -#ifndef CONFIG_SOC_AU1200 - au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - /* wait for reset complete (read register twice; see au1500 errata) */ - while (au_readl(USB_HOST_CONFIG), - !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) - udelay(1000); - -#else /* Au1200 */ - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG); - au_sync(); - udelay(2000); -#endif /* Au1200 */ -} - -static void au1xxx_stop_ohc(void) -{ -#ifdef CONFIG_SOC_AU1200 - /* Disable mem */ - au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); -#endif - /* Disable clock */ - au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); -} - static int __devinit ohci_au1xxx_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); @@ -178,17 +95,6 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) if (usb_disabled()) return -ENODEV; -#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT) - /* Au1200 AB USB does not support coherent memory */ - if (!(read_c0_prid() & 0xff)) { - printk(KERN_INFO "%s: this is chip revision AB !!\n", - pdev->name); - printk(KERN_INFO "%s: update your board or re-configure " - "the kernel\n", pdev->name); - return -ENODEV; - } -#endif - if (pdev->resource[1].flags != IORESOURCE_IRQ) { pr_debug("resource[1] is not IORESOURCE_IRQ\n"); return -ENOMEM; @@ -214,7 +120,12 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) goto err2; } - au1xxx_start_ohc(); + if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) { + printk(KERN_INFO "%s: controller init failed!\n", pdev->name); + ret = -ENODEV; + goto err3; + } + ohci_hcd_init(hcd_to_ohci(hcd)); ret = usb_add_hcd(hcd, pdev->resource[1].start, @@ -224,7 +135,8 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) return ret; } - au1xxx_stop_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); +err3: iounmap(hcd->regs); err2: release_mem_region(hcd->rsrc_start, hcd->rsrc_len); @@ -238,7 +150,7 @@ static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev) struct usb_hcd *hcd = platform_get_drvdata(pdev); usb_remove_hcd(hcd); - au1xxx_stop_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); @@ -275,7 +187,7 @@ static int ohci_hcd_au1xxx_drv_suspend(struct device *dev) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); - au1xxx_stop_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); bail: spin_unlock_irqrestore(&ohci->lock, flags); @@ -286,7 +198,7 @@ static int ohci_hcd_au1xxx_drv_resume(struct device *dev) { struct usb_hcd *hcd = dev_get_drvdata(dev); - au1xxx_start_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 1); set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); ohci_finish_controller_resume(hcd); -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:52:49 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:34084 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491206Ab1HBRvX (ORCPT ); Tue, 2 Aug 2011 19:51:23 +0200 Received: by fxd20 with SMTP id 20so73231fxd.36 for ; Tue, 02 Aug 2011 10:51:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=8fO+0nJDWbnZw+0mBYM5SXl7kN7UyO7cNpQcq3E8qkQ=; b=s1kfpQLmnqeLKs3W7ZwPCUMa2Hi1CbIgORLunQa3zbZjPTM93n/SE7+mlgeTSkWoqW 3dodNRNLdt5TnP+L/1sKfa+6yuTLpHmerrLfatkmZ0yX+AnoOBeAUWy7SvcqJNr0cdDx 4zEix7rdRIZgE31KRxw9fNitnTEnvVGfsnykI= Received: by 10.223.20.143 with SMTP id f15mr8610244fab.49.1312307478627; Tue, 02 Aug 2011 10:51:18 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.16 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:17 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 02/15] net: au1000_eth: pass MACDMA address through platform resource info. Date: Tue, 2 Aug 2011 19:50:57 +0200 Message-Id: <1312307470-6841-3-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30799 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1614 Content-Length: 7252 Lines: 229 This patch removes the last hardcoded base address from the au1000_eth driver. The base address of the MACDMA unit was derived from the platform device id; if someone registered the MACs in inverse order both would not work. So instead pass the base address of the DMA unit to the driver with the other platform resource information. Signed-off-by: Manuel Lauss Acked-by: David S. Miller --- arch/mips/alchemy/common/platform.c | 30 +++++++++++++++------ drivers/net/au1000_eth.c | 48 ++++++++++++++++++++++++++-------- drivers/net/au1000_eth.h | 2 +- 3 files changed, 58 insertions(+), 22 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index f72c48d..15d9b2f 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -373,8 +373,8 @@ static struct platform_device pbdb_smbus_device = { #endif /* Macro to help defining the Ethernet MAC resources */ -#define MAC_RES_COUNT 3 /* MAC regs base, MAC enable reg, MAC INT */ -#define MAC_RES(_base, _enable, _irq) \ +#define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */ +#define MAC_RES(_base, _enable, _irq, _macdma) \ { \ .start = _base, \ .end = _base + 0xffff, \ @@ -389,28 +389,37 @@ static struct platform_device pbdb_smbus_device = { .start = _irq, \ .end = _irq, \ .flags = IORESOURCE_IRQ \ + }, \ + { \ + .start = _macdma, \ + .end = _macdma + 0x1ff, \ + .flags = IORESOURCE_MEM, \ } static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = { [ALCHEMY_CPU_AU1000] = { MAC_RES(AU1000_MAC0_PHYS_ADDR, AU1000_MACEN_PHYS_ADDR, - AU1000_MAC0_DMA_INT) + AU1000_MAC0_DMA_INT, + AU1000_MACDMA0_PHYS_ADDR) }, [ALCHEMY_CPU_AU1500] = { MAC_RES(AU1500_MAC0_PHYS_ADDR, AU1500_MACEN_PHYS_ADDR, - AU1500_MAC0_DMA_INT) + AU1500_MAC0_DMA_INT, + AU1000_MACDMA0_PHYS_ADDR) }, [ALCHEMY_CPU_AU1100] = { MAC_RES(AU1000_MAC0_PHYS_ADDR, AU1000_MACEN_PHYS_ADDR, - AU1100_MAC0_DMA_INT) + AU1100_MAC0_DMA_INT, + AU1000_MACDMA0_PHYS_ADDR) }, [ALCHEMY_CPU_AU1550] = { MAC_RES(AU1000_MAC0_PHYS_ADDR, AU1000_MACEN_PHYS_ADDR, - AU1550_MAC0_DMA_INT) + AU1550_MAC0_DMA_INT, + AU1000_MACDMA0_PHYS_ADDR) }, }; @@ -429,17 +438,20 @@ static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = { [ALCHEMY_CPU_AU1000] = { MAC_RES(AU1000_MAC1_PHYS_ADDR, AU1000_MACEN_PHYS_ADDR + 4, - AU1000_MAC1_DMA_INT) + AU1000_MAC1_DMA_INT, + AU1000_MACDMA1_PHYS_ADDR) }, [ALCHEMY_CPU_AU1500] = { MAC_RES(AU1500_MAC1_PHYS_ADDR, AU1500_MACEN_PHYS_ADDR + 4, - AU1500_MAC1_DMA_INT) + AU1500_MAC1_DMA_INT, + AU1000_MACDMA1_PHYS_ADDR) }, [ALCHEMY_CPU_AU1550] = { MAC_RES(AU1000_MAC1_PHYS_ADDR, AU1000_MACEN_PHYS_ADDR + 4, - AU1550_MAC1_DMA_INT) + AU1550_MAC1_DMA_INT, + AU1000_MACDMA1_PHYS_ADDR) }, }; diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c index b9debcf..7013afc 100644 --- a/drivers/net/au1000_eth.c +++ b/drivers/net/au1000_eth.c @@ -541,19 +541,17 @@ static void au1000_reset_mac(struct net_device *dev) * these are not descriptors sitting in memory. */ static void -au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base) +au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base) { int i; for (i = 0; i < NUM_RX_DMA; i++) { - aup->rx_dma_ring[i] = - (struct rx_dma *) - (rx_base + sizeof(struct rx_dma)*i); + aup->rx_dma_ring[i] = (struct rx_dma *) + (tx_base + 0x100 + sizeof(struct rx_dma) * i); } for (i = 0; i < NUM_TX_DMA; i++) { - aup->tx_dma_ring[i] = - (struct tx_dma *) - (tx_base + sizeof(struct tx_dma)*i); + aup->tx_dma_ring[i] = (struct tx_dma *) + (tx_base + sizeof(struct tx_dma) * i); } } @@ -1026,7 +1024,7 @@ static int __devinit au1000_probe(struct platform_device *pdev) struct net_device *dev = NULL; struct db_dest *pDB, *pDBfree; int irq, i, err = 0; - struct resource *base, *macen; + struct resource *base, *macen, *macdma; base = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!base) { @@ -1049,6 +1047,13 @@ static int __devinit au1000_probe(struct platform_device *pdev) goto out; } + macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!macdma) { + dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n"); + err = -ENODEV; + goto out; + } + if (!request_mem_region(base->start, resource_size(base), pdev->name)) { dev_err(&pdev->dev, "failed to request memory region for base registers\n"); @@ -1063,6 +1068,13 @@ static int __devinit au1000_probe(struct platform_device *pdev) goto err_request; } + if (!request_mem_region(macdma->start, resource_size(macdma), + pdev->name)) { + dev_err(&pdev->dev, "failed to request MACDMA memory region\n"); + err = -ENXIO; + goto err_macdma; + } + dev = alloc_etherdev(sizeof(struct au1000_private)); if (!dev) { dev_err(&pdev->dev, "alloc_etherdev failed\n"); @@ -1109,10 +1121,14 @@ static int __devinit au1000_probe(struct platform_device *pdev) } aup->mac_id = pdev->id; - if (pdev->id == 0) - au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR); - else if (pdev->id == 1) - au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR); + aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma)); + if (!aup->macdma) { + dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n"); + err = -ENXIO; + goto err_remap3; + } + + au1000_setup_hw_rings(aup, aup->macdma); /* set a random MAC now in case platform_data doesn't provide one */ random_ether_addr(dev->dev_addr); @@ -1252,6 +1268,8 @@ err_out: err_mdiobus_reg: mdiobus_free(aup->mii_bus); err_mdiobus_alloc: + iounmap(aup->macdma); +err_remap3: iounmap(aup->enable); err_remap2: iounmap(aup->mac); @@ -1261,6 +1279,8 @@ err_remap1: err_vaddr: free_netdev(dev); err_alloc: + release_mem_region(macdma->start, resource_size(macdma)); +err_macdma: release_mem_region(macen->start, resource_size(macen)); err_request: release_mem_region(base->start, resource_size(base)); @@ -1293,9 +1313,13 @@ static int __devexit au1000_remove(struct platform_device *pdev) (NUM_TX_BUFFS + NUM_RX_BUFFS), (void *)aup->vaddr, aup->dma_addr); + iounmap(aup->macdma); iounmap(aup->mac); iounmap(aup->enable); + base = platform_get_resource(pdev, IORESOURCE_MEM, 2); + release_mem_region(base->start, resource_size(base)); + base = platform_get_resource(pdev, IORESOURCE_MEM, 0); release_mem_region(base->start, resource_size(base)); diff --git a/drivers/net/au1000_eth.h b/drivers/net/au1000_eth.h index 6229c77..4b7f7ad 100644 --- a/drivers/net/au1000_eth.h +++ b/drivers/net/au1000_eth.h @@ -124,7 +124,7 @@ struct au1000_private { */ struct mac_reg *mac; /* mac registers */ u32 *enable; /* address of MAC Enable Register */ - + void __iomem *macdma; /* base of MAC DMA port */ u32 vaddr; /* virtual address of rx/tx buffers */ dma_addr_t dma_addr; /* dma address of rx/tx buffers */ -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:53:13 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:45013 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491192Ab1HBRvZ (ORCPT ); Tue, 2 Aug 2011 19:51:25 +0200 Received: by fxd20 with SMTP id 20so73262fxd.36 for ; Tue, 02 Aug 2011 10:51:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=3efbWbcTLeLW9rfV0SCWe038k+uCJfOGEYTyw/HDp/Q=; b=frRbHVGTNOfGrRmTmg66o0Na+vouZPHkI7EGpZx5Yn4JqOv3ButoXWCs3XmncGG+oY sTEcvFvG67JY+YS/2f2yxLGkl8nq+8jn78uKytbLeHWPG0bGDbvSu9br8HY4esWk/gpi 2O+sBRD1HBfqxThnmtpZ6wIFjBk03kKglYYfM= Received: by 10.223.24.92 with SMTP id u28mr8457996fab.148.1312307480167; Tue, 02 Aug 2011 10:51:20 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.18 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:19 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 03/15] MIPS: Alchemy: include Au1100 in PM code. Date: Tue, 2 Aug 2011 19:50:58 +0200 Message-Id: <1312307470-6841-4-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30800 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1615 Content-Length: 1133 Lines: 45 The current code forgets the Au1100 when looking for the correct method to suspend the chip. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/power.c | 22 ++++++++++++++-------- 1 files changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index 647e518..b86324a 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -158,15 +158,21 @@ static void restore_core_regs(void) void au_sleep(void) { - int cpuid = alchemy_get_cputype(); - if (cpuid != ALCHEMY_CPU_UNKNOWN) { - save_core_regs(); - if (cpuid <= ALCHEMY_CPU_AU1500) - alchemy_sleep_au1000(); - else if (cpuid <= ALCHEMY_CPU_AU1200) - alchemy_sleep_au1550(); - restore_core_regs(); + save_core_regs(); + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + alchemy_sleep_au1000(); + break; + case ALCHEMY_CPU_AU1550: + case ALCHEMY_CPU_AU1200: + alchemy_sleep_au1550(); + break; } + + restore_core_regs(); } #endif /* CONFIG_PM */ -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:53:41 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:33355 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491753Ab1HBRvZ (ORCPT ); Tue, 2 Aug 2011 19:51:25 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73189fxd.36 for ; Tue, 02 Aug 2011 10:51:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=sQ2pP51/Enm7D3QUbn7lUslTBKKUSRzZ5ST+0872jNg=; b=vPXgoDG7Xa2AFY8g2MUj3ICny+fCPn3/gD+vTw0tqcJytfm1mFIkWaGqE37pCqPsSs 5yGsbuAg2gx1Pgtlu33nzd5TYTyUrcw+JmaN7filWRwZ224jUC0QbS22gTMWRrQA499j bKUHQWXGLSslFGnASAMqI3tM8V5CIGr1fvYBU= Received: by 10.223.160.65 with SMTP id m1mr8572191fax.28.1312307485565; Tue, 02 Aug 2011 10:51:25 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.23 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:24 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 05/15] MIPS: Alchemy: rewrite USB platform setup. Date: Tue, 2 Aug 2011 19:51:00 +0200 Message-Id: <1312307470-6841-6-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30801 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1616 Content-Length: 8670 Lines: 310 Use runtime CPU detection to setup all USB parts. Remove the Au1200 OTG and UDC platform devices since there are no drivers for them anyway. Clean up the USB address mess in the au1000 header. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 183 +++++++++++---------------- arch/mips/include/asm/mach-au1x00/au1000.h | 55 --------- 2 files changed, 75 insertions(+), 163 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 15d9b2f..910a3bd 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -111,34 +111,84 @@ static void __init alchemy_setup_uarts(int ctype) printk(KERN_INFO "Alchemy: failed to register UARTs\n"); } -/* OHCI (USB full speed host controller) */ -static struct resource au1xxx_usb_ohci_resources[] = { - [0] = { - .start = USB_OHCI_BASE, - .end = USB_OHCI_BASE + USB_OHCI_LEN - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = FOR_PLATFORM_C_USB_HOST_INT, - .end = FOR_PLATFORM_C_USB_HOST_INT, - .flags = IORESOURCE_IRQ, - }, -}; -/* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = DMA_BIT_MASK(32); +/* The dmamask must be set for OHCI/EHCI to work */ +static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32); +static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32); -static struct platform_device au1xxx_usb_ohci_device = { - .name = "au1xxx-ohci", - .id = 0, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), - .resource = au1xxx_usb_ohci_resources, +static unsigned long alchemy_ohci_data[][2] __initdata = { + [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT }, + [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT }, + [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT }, + [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT }, + [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT }, +}; + +static unsigned long alchemy_ehci_data[][2] __initdata = { + [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT }, }; +static int __init _new_usbres(struct resource **r, struct platform_device **d) +{ + *r = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!*r) + return -ENOMEM; + *d = kzalloc(sizeof(struct platform_device), GFP_KERNEL); + if (!*d) { + kfree(*r); + return -ENOMEM; + } + + (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32); + (*d)->num_resources = 2; + (*d)->resource = *r; + + return 0; +} + +static void __init alchemy_setup_usb(int ctype) +{ + struct resource *res; + struct platform_device *pdev; + + /* setup OHCI0. Every variant has one */ + if (_new_usbres(&res, &pdev)) + return; + + res[0].start = alchemy_ohci_data[ctype][0]; + res[0].end = res[0].start + 0x100 - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = alchemy_ohci_data[ctype][1]; + res[1].end = res[1].start; + res[1].flags = IORESOURCE_IRQ; + pdev->name = "au1xxx-ohci"; + pdev->id = 0; + pdev->dev.dma_mask = &alchemy_ohci_dmamask; + + if (platform_device_register(pdev)) + printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); + + + /* setup EHCI0: Au1200 */ + if (ctype == ALCHEMY_CPU_AU1200) { + if (_new_usbres(&res, &pdev)) + return; + + res[0].start = alchemy_ehci_data[ctype][0]; + res[0].end = res[0].start + 0x100 - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = alchemy_ehci_data[ctype][1]; + res[1].end = res[1].start; + res[1].flags = IORESOURCE_IRQ; + pdev->name = "au1xxx-ehci"; + pdev->id = 0; + pdev->dev.dma_mask = &alchemy_ehci_dmamask; + + if (platform_device_register(pdev)) + printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); + } +} + /*** AU1100 LCD controller ***/ #ifdef CONFIG_FB_AU1100 @@ -170,86 +220,6 @@ static struct platform_device au1100_lcd_device = { #endif #ifdef CONFIG_SOC_AU1200 -/* EHCI (USB high speed host controller) */ -static struct resource au1xxx_usb_ehci_resources[] = { - [0] = { - .start = USB_EHCI_BASE, - .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_USB_INT, - .end = AU1200_USB_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ehci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1xxx_usb_ehci_device = { - .name = "au1xxx-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources), - .resource = au1xxx_usb_ehci_resources, -}; - -/* Au1200 UDC (USB gadget controller) */ -static struct resource au1xxx_usb_gdt_resources[] = { - [0] = { - .start = USB_UDC_BASE, - .end = USB_UDC_BASE + USB_UDC_LEN - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_USB_INT, - .end = AU1200_USB_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 udc_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1xxx_usb_gdt_device = { - .name = "au1xxx-udc", - .id = 0, - .dev = { - .dma_mask = &udc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources), - .resource = au1xxx_usb_gdt_resources, -}; - -/* Au1200 UOC (USB OTG controller) */ -static struct resource au1xxx_usb_otg_resources[] = { - [0] = { - .start = USB_UOC_BASE, - .end = USB_UOC_BASE + USB_UOC_LEN - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_USB_INT, - .end = AU1200_USB_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 uoc_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1xxx_usb_otg_device = { - .name = "au1xxx-uoc", - .id = 0, - .dev = { - .dma_mask = &uoc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources), - .resource = au1xxx_usb_otg_resources, -}; static struct resource au1200_lcd_resources[] = { [0] = { @@ -534,14 +504,10 @@ static void __init alchemy_setup_macs(int ctype) } static struct platform_device *au1xxx_platform_devices[] __initdata = { - &au1xxx_usb_ohci_device, #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, #endif #ifdef CONFIG_SOC_AU1200 - &au1xxx_usb_ehci_device, - &au1xxx_usb_gdt_device, - &au1xxx_usb_otg_device, &au1200_lcd_device, &au1200_mmc0_device, #ifndef CONFIG_MIPS_DB1200 @@ -559,6 +525,7 @@ static int __init au1xxx_platform_init(void) alchemy_setup_uarts(ctype); alchemy_setup_macs(ctype); + alchemy_setup_usb(ctype); err = platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices)); diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 73e0d79..86d39c3 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -833,56 +833,6 @@ enum soc_au1200_ints { #endif - - -/* Au1000 */ -#ifdef CONFIG_SOC_AU1000 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017FFFC -#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT -#endif /* CONFIG_SOC_AU1000 */ - -/* Au1500 */ -#ifdef CONFIG_SOC_AU1500 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017fffc -#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT -#endif /* CONFIG_SOC_AU1500 */ - -/* Au1100 */ -#ifdef CONFIG_SOC_AU1100 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017FFFC -#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT -#endif /* CONFIG_SOC_AU1100 */ - -#ifdef CONFIG_SOC_AU1550 - -#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ -#define USB_OHCI_LEN 0x00060000 -#define USB_HOST_CONFIG 0xB4027ffc -#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT -#endif /* CONFIG_SOC_AU1550 */ - - -#ifdef CONFIG_SOC_AU1200 - -#define USB_UOC_BASE 0x14020020 -#define USB_UOC_LEN 0x20 -#define USB_OHCI_BASE 0x14020100 -#define USB_OHCI_LEN 0x100 -#define USB_EHCI_BASE 0x14020200 -#define USB_EHCI_LEN 0x100 -#define USB_UDC_BASE 0x14022000 -#define USB_UDC_LEN 0x2000 - -#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT - -#endif /* CONFIG_SOC_AU1200 */ - /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) @@ -953,11 +903,6 @@ enum soc_au1200_ints { # define I2S_CONTROL_D (1 << 1) # define I2S_CONTROL_CE (1 << 0) -/* USB Host Controller */ -#ifndef USB_OHCI_LEN -#define USB_OHCI_LEN 0x00100000 -#endif - /* Ethernet Controllers */ -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:54:13 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:36145 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491754Ab1HBRv2 (ORCPT ); Tue, 2 Aug 2011 19:51:28 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73158fxd.36 for ; Tue, 02 Aug 2011 10:51:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=+JFJw4zya601KYmdMeN8rAlOr4ia6iPHviaT90n6UFs=; b=ggyvqbzwl7FWbWGLyVHNJAX6G9b4h2urIAUeYMwoTJOBypCa4iIfa0czqQ3odD0H76 wP21tcdN8cN8T2pznoU/+iyLWFZ0/sUhQupfqjwg0ECRZZMbmp2v82+VLgoOu3S2KJVJ NAvf9aTvnSz2Nap+mtV9/upCVOLcEWIxebzGA= Received: by 10.223.17.151 with SMTP id s23mr8611782faa.13.1312307487816; Tue, 02 Aug 2011 10:51:27 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.25 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:26 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 06/15] MIPS: Alchemy: more base address cleanup Date: Tue, 2 Aug 2011 19:51:01 +0200 Message-Id: <1312307470-6841-7-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30802 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1617 Content-Length: 25148 Lines: 639 remove all redundant peripheral base address defines, fix all affected boards and drivers. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 12 ++-- arch/mips/alchemy/devboards/db1200/platform.c | 52 ++++++------- arch/mips/alchemy/devboards/db1x00/platform.c | 40 ++++----- arch/mips/alchemy/devboards/pb1100/platform.c | 20 ++--- arch/mips/alchemy/devboards/pb1200/platform.c | 42 +++++----- arch/mips/alchemy/devboards/pb1500/platform.c | 22 +++--- arch/mips/alchemy/devboards/pb1550/platform.c | 40 ++++----- arch/mips/alchemy/xxs1500/platform.c | 12 ++-- arch/mips/include/asm/mach-au1x00/au1000.h | 103 ++++++------------------ arch/mips/include/asm/mach-au1x00/au1xxx_psc.h | 26 ------ arch/mips/include/asm/mach-db1x00/db1x00.h | 8 +- arch/mips/include/asm/mach-pb1x00/pb1200.h | 8 +- arch/mips/include/asm/mach-pb1x00/pb1550.h | 8 +- 13 files changed, 146 insertions(+), 247 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 910a3bd..bf1ac41 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -194,8 +194,8 @@ static void __init alchemy_setup_usb(int ctype) #ifdef CONFIG_FB_AU1100 static struct resource au1100_lcd_resources[] = { [0] = { - .start = LCD_PHYS_ADDR, - .end = LCD_PHYS_ADDR + 0x800 - 1, + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -223,8 +223,8 @@ static struct platform_device au1100_lcd_device = { static struct resource au1200_lcd_resources[] = { [0] = { - .start = LCD_PHYS_ADDR, - .end = LCD_PHYS_ADDR + 0x800 - 1, + .start = AU1200_LCD_PHYS_ADDR, + .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -328,8 +328,8 @@ static struct platform_device au1200_mmc1_device = { #ifdef SMBUS_PSC_BASE static struct resource pbdb_smbus_resources[] = { { - .start = CPHYSADDR(SMBUS_PSC_BASE), - .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff), + .start = SMBUS_PSC_BASE, + .end = SMBUS_PSC_BASE + 0xfff, .flags = IORESOURCE_MEM, }, }; diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index fbb5593..95c7327 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -343,8 +343,8 @@ struct au1xmmc_platform_data au1xmmc_platdata[] = { static struct resource au1200_psc0_res[] = { [0] = { - .start = PSC0_PHYS_ADDR, - .end = PSC0_PHYS_ADDR + 0x000fffff, + .start = AU1550_PSC0_PHYS_ADDR, + .end = AU1550_PSC0_PHYS_ADDR + 0xfff, .flags = IORESOURCE_MEM, }, [1] = { @@ -401,8 +401,8 @@ static struct platform_device db1200_spi_dev = { static struct resource au1200_psc1_res[] = { [0] = { - .start = PSC1_PHYS_ADDR, - .end = PSC1_PHYS_ADDR + 0x000fffff, + .start = AU1550_PSC1_PHYS_ADDR, + .end = AU1550_PSC1_PHYS_ADDR + 0xfff, .flags = IORESOURCE_MEM, }, [1] = { @@ -510,32 +510,28 @@ static int __init db1200_dev_init(void) /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ __raw_writel(PSC_SEL_CLK_SERCLK, - (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - DB1200_PC0_INT, - DB1200_PC0_INSERT_INT, - /*DB1200_PC0_STSCHG_INT*/0, - DB1200_PC0_EJECT_INT, - 0); - - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000, - PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, - PCMCIA_MEM_PHYS_ADDR + 0x004000000, - PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, - PCMCIA_IO_PHYS_ADDR + 0x004000000, - PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, - DB1200_PC1_INT, - DB1200_PC1_INSERT_INT, - /*DB1200_PC1_STSCHG_INT*/0, - DB1200_PC1_EJECT_INT, - 1); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + DB1200_PC0_INT, DB1200_PC0_INSERT_INT, + /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + DB1200_PC1_INT, DB1200_PC1_INSERT_INT, + /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(64 << 20, 2, swapped); diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 978d5ab..ef8017f 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -88,29 +88,25 @@ static int __init db1xxx_dev_init(void) { #ifdef DB1XXX_HAS_PCMCIA - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - DB1XXX_PCMCIA_CARD0, - DB1XXX_PCMCIA_CD0, - /*DB1XXX_PCMCIA_STSCHG0*/0, - 0, - 0); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0, + /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0); - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000, - PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, - PCMCIA_MEM_PHYS_ADDR + 0x004000000, - PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, - PCMCIA_IO_PHYS_ADDR + 0x004000000, - PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, - DB1XXX_PCMCIA_CARD1, - DB1XXX_PCMCIA_CD1, - /*DB1XXX_PCMCIA_STSCHG1*/0, - 0, - 1); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, + /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); #endif db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); return 0; diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c index 2c8dc29..8a4e733 100644 --- a/arch/mips/alchemy/devboards/pb1100/platform.c +++ b/arch/mips/alchemy/devboards/pb1100/platform.c @@ -30,17 +30,15 @@ static int __init pb1100_dev_init(void) int swapped; /* PCMCIA. single socket, identical to Pb1500 */ - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1100_GPIO11_INT, /* card */ - AU1100_GPIO9_INT, /* insert */ - /*AU1100_GPIO10_INT*/0, /* stschg */ - 0, /* eject */ - 0); /* id */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */ + /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; db1x_register_norflash(64 * 1024 * 1024, 4, swapped); diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 3ef2dce..c52809d 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -170,29 +170,25 @@ static int __init board_register_devices(void) { int swapped; - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - PB1200_PC0_INT, - PB1200_PC0_INSERT_INT, - /*PB1200_PC0_STSCHG_INT*/0, - PB1200_PC0_EJECT_INT, - 0); - - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000, - PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, - PCMCIA_MEM_PHYS_ADDR + 0x008000000, - PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, - PCMCIA_IO_PHYS_ADDR + 0x008000000, - PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, - PB1200_PC1_INT, - PB1200_PC1_INSERT_INT, - /*PB1200_PC1_STSCHG_INT*/0, - PB1200_PC1_EJECT_INT, - 1); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + PB1200_PC0_INT, PB1200_PC0_INSERT_INT, + /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, + PB1200_PC1_INT, PB1200_PC1_INSERT_INT, + /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 2, swapped); diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c index d443bc7..42b0e6b 100644 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -28,18 +28,16 @@ static int __init pb1500_dev_init(void) { int swapped; - /* PCMCIA. single socket, identical to Pb1500 */ - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1500_GPIO11_INT, /* card */ - AU1500_GPIO9_INT, /* insert */ - /*AU1500_GPIO10_INT*/0, /* stschg */ - 0, /* eject */ - 0); /* id */ + /* PCMCIA. single socket, identical to Pb1100 */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */ + /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; db1x_register_norflash(64 * 1024 * 1024, 4, swapped); diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c index d7150d0..87c79b7 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -37,29 +37,23 @@ static int __init pb1550_dev_init(void) * drivers are used to shared irqs and b) statuschange isn't really use- * ful anyway. */ - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1550_GPIO201_205_INT, - AU1550_GPIO0_INT, - 0, - 0, - 0); - - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000, - PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, - PCMCIA_MEM_PHYS_ADDR + 0x008000000, - PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, - PCMCIA_IO_PHYS_ADDR + 0x008000000, - PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, - AU1550_GPIO201_205_INT, - AU1550_GPIO1_INT, - 0, - 0, - 1); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, + AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 4, swapped); diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c index e87c45c..06a3a45 100644 --- a/arch/mips/alchemy/xxs1500/platform.c +++ b/arch/mips/alchemy/xxs1500/platform.c @@ -27,20 +27,20 @@ static struct resource xxs1500_pcmcia_res[] = { { .name = "pcmcia-io", .flags = IORESOURCE_MEM, - .start = PCMCIA_IO_PHYS_ADDR, - .end = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, + .start = AU1000_PCMCIA_IO_PHYS_ADDR, + .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, }, { .name = "pcmcia-attr", .flags = IORESOURCE_MEM, - .start = PCMCIA_ATTR_PHYS_ADDR, - .end = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + .start = AU1000_PCMCIA_ATTR_PHYS_ADDR, + .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, }, { .name = "pcmcia-mem", .flags = IORESOURCE_MEM, - .start = PCMCIA_MEM_PHYS_ADDR, - .end = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + .start = AU1000_PCMCIA_MEM_PHYS_ADDR, + .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, }, }; diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 86d39c3..bcf3d1e 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -698,114 +698,61 @@ enum soc_au1200_ints { #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ +#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ +#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ +#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ +#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ +#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */ #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ +#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */ +#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ +#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ +#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ +#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ +#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ +#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ +#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ +#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ +#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ +#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ +#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ +#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ +#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ +#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ +#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ +#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ +#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ +#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ +#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ -#ifdef CONFIG_SOC_AU1000 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define IRDA_PHYS_ADDR 0x10300000 -#define SSI0_PHYS_ADDR 0x11600000 -#define SSI1_PHYS_ADDR 0x11680000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/********************************************************************/ - -#ifdef CONFIG_SOC_AU1500 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define PCI_PHYS_ADDR 0x14005000 -#define PCI_MEM_PHYS_ADDR 0x400000000ULL -#define PCI_IO_PHYS_ADDR 0x500000000ULL -#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL -#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/********************************************************************/ - -#ifdef CONFIG_SOC_AU1100 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define IRDA_PHYS_ADDR 0x10300000 -#define SSI0_PHYS_ADDR 0x11600000 -#define SSI1_PHYS_ADDR 0x11680000 -#define LCD_PHYS_ADDR 0x15000000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/***********************************************************************/ - -#ifdef CONFIG_SOC_AU1550 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define PCI_PHYS_ADDR 0x14005000 -#define PE_PHYS_ADDR 0x14008000 -#define PSC0_PHYS_ADDR 0x11A00000 -#define PSC1_PHYS_ADDR 0x11B00000 -#define PSC2_PHYS_ADDR 0x10A00000 -#define PSC3_PHYS_ADDR 0x10B00000 -#define PCI_MEM_PHYS_ADDR 0x400000000ULL -#define PCI_IO_PHYS_ADDR 0x500000000ULL -#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL -#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/***********************************************************************/ - -#ifdef CONFIG_SOC_AU1200 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define AES_PHYS_ADDR 0x10300000 -#define CIM_PHYS_ADDR 0x14004000 -#define PSC0_PHYS_ADDR 0x11A00000 -#define PSC1_PHYS_ADDR 0x11B00000 -#define LCD_PHYS_ADDR 0x15000000 -#define SWCNT_PHYS_ADDR 0x1110010C -#define MAEFE_PHYS_ADDR 0x14012000 -#define MAEBE_PHYS_ADDR 0x14010000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - /* Static Bus Controller */ #define MEM_STCFG0 0xB4001000 #define MEM_STTIME0 0xB4001004 diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h index 892b7f1..8e2fa67 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h @@ -33,19 +33,6 @@ #ifndef _AU1000_PSC_H_ #define _AU1000_PSC_H_ -/* The PSC base addresses. */ -#ifdef CONFIG_SOC_AU1550 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#define PSC2_BASE_ADDR 0xb0a00000 -#define PSC3_BASE_ADDR 0xb0b00000 -#endif - -#ifdef CONFIG_SOC_AU1200 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#endif - /* * The PSC select and control registers are common to all protocols. */ @@ -80,19 +67,6 @@ #define PSC_AC97GPO_OFFSET 0x00000028 #define PSC_AC97GPI_OFFSET 0x0000002c -#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) -#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) -#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) -#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) -#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) -#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) -#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) -#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) -#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) -#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) -#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) -#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) - /* AC97 Config Register. */ #define PSC_AC97CFG_RT_MASK (3 << 30) #define PSC_AC97CFG_RT_FIFO1 (0 << 30) diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index a919dac..115cc7c 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -36,10 +36,10 @@ #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define SMBUS_PSC_BASE PSC2_BASE_ADDR -#define I2S_PSC_BASE PSC3_BASE_ADDR +#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR +#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR +#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR +#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR #define NAND_PHYS_ADDR 0x20000000 diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index fce4332..0ecff1c 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -37,14 +37,14 @@ * SPI and SMB are muxed on the Pb1200 board. * Refer to board documentation. */ -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define SMBUS_PSC_BASE PSC0_BASE_ADDR +#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR +#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR /* * AC97 and I2S are muxed on the Pb1200 board. * Refer to board documentation. */ -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define I2S_PSC_BASE PSC1_BASE_ADDR +#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR +#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR #define BCSR_SYSTEM_VDDI 0x001F diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h index f835c88..0b0f462 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h @@ -35,10 +35,10 @@ #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define SMBUS_PSC_BASE PSC2_BASE_ADDR -#define I2S_PSC_BASE PSC3_BASE_ADDR +#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR +#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR +#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR +#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR /* * Timing values as described in databook, * ns value stripped of -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:54:37 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:34084 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491756Ab1HBRv3 (ORCPT ); Tue, 2 Aug 2011 19:51:29 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73231fxd.36 for ; Tue, 02 Aug 2011 10:51:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=c4E/eW55d0u1Jjyr6jTuGw4wIQJM+hgJ7pWlIhCxmUE=; b=BbkwSjB/2PcZxlbnpy8/7BsMjs9YeqMsuLrCpWXkdd9i4dSMvUZJpfyoSdV7ge1QoX h5lbg+hKQZ5BEmLXLwliQ/WoOKe4fd7r93XHHTe8QfAisgedhWLqMNiSg8rGa9tUQqqO wctk822cud7KdCixWyDKL1rmhCiALBHqNxQ2E= Received: by 10.223.159.202 with SMTP id k10mr6609995fax.6.1312307489147; Tue, 02 Aug 2011 10:51:29 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.27 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:28 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 07/15] MIPS: Alchemy: always build power code Date: Tue, 2 Aug 2011 19:51:02 +0200 Message-Id: <1312307470-6841-8-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30803 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1618 Content-Length: 719 Lines: 29 No reason NOT to build it Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/power.c | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index e53b4ce..bdd6651 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -37,8 +37,6 @@ #include #include -#ifdef CONFIG_PM - /* * We need to save/restore a bunch of core registers that are * either volatile or reset to some state across a processor sleep. @@ -132,5 +130,3 @@ void au_sleep(void) restore_core_regs(); } - -#endif /* CONFIG_PM */ -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:55:05 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:45013 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491757Ab1HBRvb (ORCPT ); Tue, 2 Aug 2011 19:51:31 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73262fxd.36 for ; Tue, 02 Aug 2011 10:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=4rlGmGcooaIVihjRsHy7wzWQJtNXsZSKdQA4ogEbyjQ=; b=c+7JCFwnLsR2Wfzz5FVkzwmzCwIQkbgjCF4KmoIE8tngasK01UbE1p/XZFlZuBgJ0v /LaS3GDXwzs016DkkewR562qUl/yeOBeoH8AzO3GVs04luwmJm++1GRPObGGP6reo2ct 6iuFg+fP62kT2VD8nm3MsD/eMj5c90+mAdt04= Received: by 10.223.9.217 with SMTP id m25mr826525fam.122.1312307490892; Tue, 02 Aug 2011 10:51:30 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.29 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:30 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 08/15] MIPS: Alchemy: support multiple GPIO styles in one kernel Date: Tue, 2 Aug 2011 19:51:03 +0200 Message-Id: <1312307470-6841-9-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30804 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1619 Content-Length: 14930 Lines: 451 For GPIOLIB=y decide at runtime which gpiochips to register; in the GPIOLIB=n case, the gpio headers need to be reshuffled a bit to make multiple implementations coexist peacefully. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/Makefile | 4 +- arch/mips/alchemy/common/gpiolib-au1000.c | 126 --------------------- arch/mips/alchemy/common/gpiolib.c | 133 +++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 31 +----- arch/mips/include/asm/mach-au1x00/gpio.h | 79 +++++++++++++- 5 files changed, 212 insertions(+), 161 deletions(-) delete mode 100644 arch/mips/alchemy/common/gpiolib-au1000.c create mode 100644 arch/mips/alchemy/common/gpiolib.c diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 575db47..31728e0 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -12,9 +12,7 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o # optional gpiolib support ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) - ifeq ($(CONFIG_GPIOLIB),y) - obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o - endif + obj-$(CONFIG_GPIOLIB) += gpiolib.o endif obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c deleted file mode 100644 index c8e1a94..0000000 --- a/arch/mips/alchemy/common/gpiolib-au1000.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli - * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Notes : - * au1000 SoC have only one GPIO block : GPIO1 - * Au1100, Au15x0, Au12x0 have a second one : GPIO2 - */ - -#include -#include -#include -#include -#include - -#include -#include - -static int gpio2_get(struct gpio_chip *chip, unsigned offset) -{ - return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); -} - -static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value) -{ - alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); -} - -static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset) -{ - return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE); -} - -static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE, - value); -} - -static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset) -{ - return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); -} - - -static int gpio1_get(struct gpio_chip *chip, unsigned offset) -{ - return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE); -} - -static void gpio1_set(struct gpio_chip *chip, - unsigned offset, int value) -{ - alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value); -} - -static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset) -{ - return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE); -} - -static int gpio1_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE, - value); -} - -static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset) -{ - return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE); -} - -struct gpio_chip alchemy_gpio_chip[] = { - [0] = { - .label = "alchemy-gpio1", - .direction_input = gpio1_direction_input, - .direction_output = gpio1_direction_output, - .get = gpio1_get, - .set = gpio1_set, - .to_irq = gpio1_to_irq, - .base = ALCHEMY_GPIO1_BASE, - .ngpio = ALCHEMY_GPIO1_NUM, - }, - [1] = { - .label = "alchemy-gpio2", - .direction_input = gpio2_direction_input, - .direction_output = gpio2_direction_output, - .get = gpio2_get, - .set = gpio2_set, - .to_irq = gpio2_to_irq, - .base = ALCHEMY_GPIO2_BASE, - .ngpio = ALCHEMY_GPIO2_NUM, - }, -}; - -static int __init alchemy_gpiolib_init(void) -{ - gpiochip_add(&alchemy_gpio_chip[0]); - if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000) - gpiochip_add(&alchemy_gpio_chip[1]); - - return 0; -} -arch_initcall(alchemy_gpiolib_init); diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c new file mode 100644 index 0000000..91fb4d9 --- /dev/null +++ b/arch/mips/alchemy/common/gpiolib.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli + * GPIOLIB support for Alchemy chips. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Notes : + * This file must ONLY be built when CONFIG_GPIOLIB=y and + * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail! + * au1000 SoC have only one GPIO block : GPIO1 + * Au1100, Au15x0, Au12x0 have a second one : GPIO2 + */ + +#include +#include +#include +#include +#include +#include + +static int gpio2_get(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); +} + +static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value) +{ + alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); +} + +static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE); +} + +static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE, + value); +} + +static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); +} + + +static int gpio1_get(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE); +} + +static void gpio1_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value); +} + +static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE); +} + +static int gpio1_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE, + value); +} + +static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE); +} + +struct gpio_chip alchemy_gpio_chip[] = { + [0] = { + .label = "alchemy-gpio1", + .direction_input = gpio1_direction_input, + .direction_output = gpio1_direction_output, + .get = gpio1_get, + .set = gpio1_set, + .to_irq = gpio1_to_irq, + .base = ALCHEMY_GPIO1_BASE, + .ngpio = ALCHEMY_GPIO1_NUM, + }, + [1] = { + .label = "alchemy-gpio2", + .direction_input = gpio2_direction_input, + .direction_output = gpio2_direction_output, + .get = gpio2_get, + .set = gpio2_set, + .to_irq = gpio2_to_irq, + .base = ALCHEMY_GPIO2_BASE, + .ngpio = ALCHEMY_GPIO2_NUM, + }, +}; + +static int __init alchemy_gpiochip_init(void) +{ + int ret = 0; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + ret = gpiochip_add(&alchemy_gpio_chip[0]); + break; + case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200: + ret = gpiochip_add(&alchemy_gpio_chip[0]); + ret |= gpiochip_add(&alchemy_gpio_chip[1]); + break; + } + return ret; +} +arch_initcall(alchemy_gpiochip_init); diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 1f41a52..73853b5 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -347,17 +347,6 @@ static inline int alchemy_gpio2_to_irq(int gpio) /**********************************************************************/ -/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before - * SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this - * register enables use of GPIOs as wake source. - */ -static inline void alchemy_gpio1_input_enable(void) -{ - void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); - __raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */ - wmb(); -} - /* GPIO2 shared interrupts and control */ static inline void __alchemy_gpio2_mod_int(int gpio2, int en) @@ -561,6 +550,7 @@ static inline int alchemy_irq_to_gpio(int irq) #ifndef CONFIG_GPIOLIB +#ifdef CONFIG_ALCHEMY_GPIOINT_AU1000 #ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ @@ -665,24 +655,7 @@ static inline void gpio_unexport(unsigned gpio) #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ - -#else /* CONFIG GPIOLIB */ - - - /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */ -#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */ - -/* get everything through gpiolib */ -#define gpio_to_irq __gpio_to_irq -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep -#define irq_to_gpio alchemy_irq_to_gpio - -#include - -#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ - +#endif /* CONFIG_ALCHEMY_GPIOINT_AU1000 */ #endif /* !CONFIG_GPIOLIB */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index c3f60cd..fcdc8c4 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -1,10 +1,83 @@ +/* + * Alchemy GPIO support. + * + * With CONFIG_GPIOLIB=y different types of on-chip GPIO can be supported within + * the same kernel image. + * With CONFIG_GPIOLIB=n, your board must select ALCHEMY_GPIOINT_AU1XXX for the + * appropriate CPU type (AU1000 currently). + */ + #ifndef _ALCHEMY_GPIO_H_ #define _ALCHEMY_GPIO_H_ -#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000) - +#include #include -#endif +/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before + * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this + * register enables use of GPIOs as wake source. + */ +static inline void alchemy_gpio1_input_enable(void) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); + __raw_writel(0, base + 0x110); /* the write op is key */ + wmb(); +} + + +/* Linux gpio framework integration. +* +* 4 use cases of Alchemy GPIOS: +*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: +* Board must register gpiochips. +*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: +* A gpiochip for the 75 GPIOs is registered. +* +*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: +* the boards' gpio.h must provide the linux gpio wrapper functions, +* +*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: +* inlinable gpio functions are provided which enable access to the +* Au1300 gpios only by using the numbers straight out of the data- +* sheets. + +* Cases 1 and 3 are intended for boards which want to provide their own +* GPIO namespace and -operations (i.e. for example you have 8 GPIOs +* which are in part provided by spare Au1300 GPIO pins and in part by +* an external FPGA but you still want them to be accssible in linux +* as gpio0-7. The board can of course use the alchemy_gpioX_* functions +* as required). +*/ + +#ifdef CONFIG_GPIOLIB + +/* wraps the cpu-dependent irq_to_gpio functions */ +/* FIXME: gpiolib needs an irq_to_gpio hook */ +static inline int __au_irq_to_gpio(unsigned int irq) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: + return alchemy_irq_to_gpio(irq); + } + return -EINVAL; +} + + +/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */ +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */ + +/* get everything through gpiolib */ +#define gpio_to_irq __gpio_to_irq +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define irq_to_gpio __au_irq_to_gpio + +#include + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + + +#endif /* CONFIG_GPIOLIB */ #endif /* _ALCHEMY_GPIO_H_ */ -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:55:33 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:33355 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491759Ab1HBRvc (ORCPT ); Tue, 2 Aug 2011 19:51:32 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73189fxd.36 for ; Tue, 02 Aug 2011 10:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=r/zhnjcxNAs6+KgLiCh/bmJg1wce0bcXo1pjky76rOw=; b=F4cnLhVvNke4SlWmwwFtRgSIBscUPLTAeznY9TdkpmoJhPoPi7NBJkle3zQBsuoqUb gPjpQEC4sIS7KBcGD9ROtHa/OsGufj8cOPRKyufDTIiMkpA9w18sRRBWJMtHe0a4fFEa HTSymlhxCu6DGYIm3WNjT1zSO4Sl/26tIqNog= Received: by 10.223.68.22 with SMTP id t22mr803313fai.145.1312307492585; Tue, 02 Aug 2011 10:51:32 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.30 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:31 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 09/15] MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dependencies Date: Tue, 2 Aug 2011 19:51:04 +0200 Message-Id: <1312307470-6841-10-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30805 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1620 Content-Length: 6799 Lines: 196 au1xxx-ide uses defines from the pb1200/db1200 headers, fix this. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/devboards/db1200/platform.c | 7 +++- arch/mips/alchemy/devboards/pb1200/platform.c | 8 ++++- arch/mips/include/asm/mach-au1x00/au1xxx_ide.h | 1 + arch/mips/include/asm/mach-db1x00/db1200.h | 2 - arch/mips/include/asm/mach-pb1x00/pb1200.h | 2 - drivers/ide/au1xxx-ide.c | 44 ++++++++++++++---------- 6 files changed, 40 insertions(+), 24 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index 95c7327..6fd070d 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -213,7 +213,12 @@ static struct resource db1200_ide_res[] = { .start = DB1200_IDE_INT, .end = DB1200_IDE_INT, .flags = IORESOURCE_IRQ, - } + }, + [2] = { + .start = DSCR_CMD0_DMA_REQ1, + .end = DSCR_CMD0_DMA_REQ1, + .flags = IORESOURCE_DMA, + }, }; static u64 ide_dmamask = DMA_BIT_MASK(32); diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index c52809d..6ac0494 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -26,6 +26,7 @@ #include #include +#include #include #include "../platform.h" @@ -115,7 +116,12 @@ static struct resource ide_resources[] = { .start = IDE_INT, .end = IDE_INT, .flags = IORESOURCE_IRQ - } + }, + [2] = { + .start = DSCR_CMD0_DMA_REQ1, + .end = DSCR_CMD0_DMA_REQ1, + .flags = IORESOURCE_DMA, + }, }; static u64 ide_dmamask = DMA_BIT_MASK(32); diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h index 5656c72..e306384 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h @@ -58,6 +58,7 @@ typedef struct { #endif int irq; u32 regbase; + int ddma_id; } _auide_hwif; /******************************************************************************/ diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 3404248..7a39657 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -46,8 +46,6 @@ #define IDE_PHYS_ADDR 0x18800000 #define IDE_REG_SHIFT 5 -#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 -#define IDE_RQSIZE 128 #define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR #define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index 0ecff1c..56865e9 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -76,8 +76,6 @@ #define IDE_REG_SHIFT 5 #define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) #define IDE_INT PB1200_IDE_INT -#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 -#define IDE_RQSIZE 128 #define NAND_PHYS_ADDR 0x1C000000 diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c index b26c234..c778373 100644 --- a/drivers/ide/au1xxx-ide.c +++ b/drivers/ide/au1xxx-ide.c @@ -43,6 +43,10 @@ #define DRV_NAME "au1200-ide" #define DRV_AUTHOR "Enrico Walther / Pete Popov " +#ifndef IDE_REG_SHIFT +#define IDE_REG_SHIFT 5 +#endif + /* enable the burstmode in the dbdma */ #define IDE_AU1XXX_BURSTMODE 1 @@ -317,10 +321,11 @@ static void auide_ddma_rx_callback(int irq, void *param) } #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ -static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) +static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, + u32 devwidth, u32 flags, u32 regbase) { dev->dev_id = dev_id; - dev->dev_physaddr = (u32)IDE_PHYS_ADDR; + dev->dev_physaddr = CPHYSADDR(regbase); dev->dev_intlevel = 0; dev->dev_intpolarity = 0; dev->dev_tsize = tsize; @@ -344,7 +349,7 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) dbdev_tab_t source_dev_tab, target_dev_tab; u32 dev_id, tsize, devwidth, flags; - dev_id = IDE_DDMA_REQ; + dev_id = hwif->ddma_id; tsize = 8; /* 1 */ devwidth = 32; /* 16 */ @@ -356,20 +361,17 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) #endif /* setup dev_tab for tx channel */ - auide_init_dbdma_dev( &source_dev_tab, - dev_id, - tsize, devwidth, DEV_FLAGS_OUT | flags); + auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, + DEV_FLAGS_OUT | flags, auide->regbase); auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - auide_init_dbdma_dev( &source_dev_tab, - dev_id, - tsize, devwidth, DEV_FLAGS_IN | flags); + auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, + DEV_FLAGS_IN | flags, auide->regbase); auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); /* We also need to add a target device for the DMA */ - auide_init_dbdma_dev( &target_dev_tab, - (u32)DSCR_CMD0_ALWAYS, - tsize, devwidth, DEV_FLAGS_ANYUSE); + auide_init_dbdma_dev(&target_dev_tab, (u32)DSCR_CMD0_ALWAYS, tsize, + devwidth, DEV_FLAGS_ANYUSE, auide->regbase); auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); /* Get a channel for TX */ @@ -411,14 +413,12 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) #endif /* setup dev_tab for tx channel */ - auide_init_dbdma_dev( &source_dev_tab, - (u32)DSCR_CMD0_ALWAYS, - 8, 32, DEV_FLAGS_OUT | flags); + auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, + DEV_FLAGS_OUT | flags, auide->regbase); auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - auide_init_dbdma_dev( &source_dev_tab, - (u32)DSCR_CMD0_ALWAYS, - 8, 32, DEV_FLAGS_IN | flags); + auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, + DEV_FLAGS_IN | flags, auide->regbase); auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); /* Get a channel for TX */ @@ -540,6 +540,14 @@ static int au_ide_probe(struct platform_device *dev) goto out; } + res = platform_get_resource(dev, IORESOURCE_DMA, 0); + if (!res) { + pr_debug("%s: no DDMA ID resource\n", DRV_NAME); + ret = -ENODEV; + goto out; + } + ahwif->ddma_id = res->start; + memset(&hw, 0, sizeof(hw)); auide_setup_ports(&hw, ahwif); hw.irq = ahwif->irq; -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:55:57 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:36145 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491760Ab1HBRve (ORCPT ); Tue, 2 Aug 2011 19:51:34 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73158fxd.36 for ; Tue, 02 Aug 2011 10:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=BgjjEeBh1hreeskY1bvN/qwJ5hEbmhSPUaPab0ds6Yw=; b=ebC+CoEf0GtMSi2I+wX75aAq6m/hW0Lpe8AzExLgQ7sYZFXHm8DDlAM6clUnrb0dPR XN6fojjSHRWup+LeVRJUyG9WauG9qf+MM9CFtfKl6I5DI2VWmF9ozKc+HR8n9NlMtmXm 3wlo+Sf39AQEAtiv3xx1biEwx8hZR8e+XGOqs= Received: by 10.223.120.134 with SMTP id d6mr8405658far.112.1312307494722; Tue, 02 Aug 2011 10:51:34 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.32 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:33 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 10/15] MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines Date: Tue, 2 Aug 2011 19:51:05 +0200 Message-Id: <1312307470-6841-11-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30806 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1621 Content-Length: 24027 Lines: 659 This patch gets rid of all CONFIG_SOC_AU1XXX defines in DMA/DBDMA-related code. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/dbdma.c | 203 ++++++++++------------ arch/mips/alchemy/common/dma.c | 60 +++---- arch/mips/alchemy/common/platform.c | 16 +- arch/mips/alchemy/devboards/db1200/platform.c | 20 +- arch/mips/alchemy/devboards/pb1200/platform.c | 4 +- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 114 ++++++------- arch/mips/include/asm/mach-db1x00/db1x00.h | 8 +- arch/mips/include/asm/mach-pb1x00/pb1200.h | 8 +- arch/mips/include/asm/mach-pb1x00/pb1550.h | 8 +- 9 files changed, 206 insertions(+), 235 deletions(-) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 3a5abb5..0e63ee4 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -40,8 +40,6 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - /* * The Descriptor Based DMA supports up to 16 channels. * @@ -62,120 +60,96 @@ static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR); static int dbdma_initialized; -static dbdev_tab_t dbdev_tab[] = { -#ifdef CONFIG_SOC_AU1550 +static dbdev_tab_t *dbdev_tab; + +static dbdev_tab_t au1550_dbdev_tab[] __initdata = { /* UARTS */ - { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, - { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, - { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, - { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, + { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, + { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, + { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, + { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, /* EXT DMA */ - { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, /* USB DEV */ - { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, - { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, - { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, - { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, - { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, - { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, - - /* PSC 0 */ - { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, - { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, - - /* PSC 1 */ - { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, - { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, - - /* PSC 2 */ - { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, - { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, - - /* PSC 3 */ - { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 }, - { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 }, - - { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */ - { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */ + { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, + + /* PSCs */ + { AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 }, + + { AU1550_DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */ + { AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */ /* MAC 0 */ - { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, /* MAC 1 */ - { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, - -#endif /* CONFIG_SOC_AU1550 */ + { AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, -#ifdef CONFIG_SOC_AU1200 - { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, - { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, - { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 }, - { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 }, - - { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, +}; - { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, +static dbdev_tab_t au1200_dbdev_tab[] __initdata = { + { AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, + { AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, + { AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 }, + { AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 }, - { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, - { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, - { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, - { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, + { AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, - { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + { AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, - { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, - { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, + { AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, - { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, - { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, - { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, - { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, - { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, - { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, - { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, + { AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, + { AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, + { AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, + { AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, + { AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, + { AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, + { AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, -#endif /* CONFIG_SOC_AU1200 */ + { AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - - /* Provide 16 user definable device types */ - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, + { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, }; -#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) - +/* 32 predefined plus 32 custom */ +#define DBDEV_TAB_SIZE 64 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; @@ -1028,38 +1002,43 @@ static struct syscore_ops alchemy_dbdma_syscore_ops = { .resume = alchemy_dbdma_resume, }; -static int __init au1xxx_dbdma_init(void) +static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) { - int irq_nr, ret; + int ret; + + dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL); + if (!dbdev_tab) + return -ENOMEM; + + memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t)); + for (ret = 32; ret < DBDEV_TAB_SIZE; ret++) + dbdev_tab[ret].dev_id = ~0; dbdma_gptr->ddma_config = 0; dbdma_gptr->ddma_throttle = 0; dbdma_gptr->ddma_inten = 0xffff; au_sync(); - switch (alchemy_get_cputype()) { - case ALCHEMY_CPU_AU1550: - irq_nr = AU1550_DDMA_INT; - break; - case ALCHEMY_CPU_AU1200: - irq_nr = AU1200_DDMA_INT; - break; - default: - return -ENODEV; - } - - ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, - "Au1xxx dbdma", (void *)dbdma_gptr); + ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma", + (void *)dbdma_gptr); if (ret) printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); else { dbdma_initialized = 1; - printk(KERN_INFO "Alchemy DBDMA initialized\n"); register_syscore_ops(&alchemy_dbdma_syscore_ops); } return ret; } -subsys_initcall(au1xxx_dbdma_init); -#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ +static int __init alchemy_dbdma_init(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1550: + return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab); + case ALCHEMY_CPU_AU1200: + return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab); + } + return 0; +} +subsys_initcall(alchemy_dbdma_init); diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c index 6652a23..9b624e2 100644 --- a/arch/mips/alchemy/common/dma.c +++ b/arch/mips/alchemy/common/dma.c @@ -40,8 +40,6 @@ #include #include -#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ - defined(CONFIG_SOC_AU1100) /* * A note on resource allocation: * @@ -170,13 +168,13 @@ int request_au1000_dma(int dev_id, const char *dev_str, const struct dma_dev *dev; int i, ret; -#if defined(CONFIG_SOC_AU1100) - if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2)) - return -EINVAL; -#else - if (dev_id < 0 || dev_id >= DMA_NUM_DEV) - return -EINVAL; -#endif + if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) { + if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2)) + return -EINVAL; + } else { + if (dev_id < 0 || dev_id >= DMA_NUM_DEV) + return -EINVAL; + } for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) if (au1000_dma_table[i].dev_id < 0) @@ -239,30 +237,28 @@ EXPORT_SYMBOL(free_au1000_dma); static int __init au1000_dma_init(void) { - int base, i; - - switch (alchemy_get_cputype()) { - case ALCHEMY_CPU_AU1000: - base = AU1000_DMA_INT_BASE; - break; - case ALCHEMY_CPU_AU1500: - base = AU1500_DMA_INT_BASE; - break; - case ALCHEMY_CPU_AU1100: - base = AU1100_DMA_INT_BASE; - break; - default: - goto out; - } - - for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) - au1000_dma_table[i].irq = base + i; - - printk(KERN_INFO "Alchemy DMA initialized\n"); + int base, i; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + base = AU1000_DMA_INT_BASE; + break; + case ALCHEMY_CPU_AU1500: + base = AU1500_DMA_INT_BASE; + break; + case ALCHEMY_CPU_AU1100: + base = AU1100_DMA_INT_BASE; + break; + default: + goto out; + } + + for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) + au1000_dma_table[i].irq = base + i; + + printk(KERN_INFO "Alchemy DMA initialized\n"); out: - return 0; + return 0; } arch_initcall(au1000_dma_init); - -#endif /* AU1000 AU1500 AU1100 */ diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index bf1ac41..7eca306 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -263,13 +263,13 @@ static struct resource au1200_mmc0_resources[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_SDMS_TX0, - .end = DSCR_CMD0_SDMS_TX0, + .start = AU1200_DSCR_CMD0_SDMS_TX0, + .end = AU1200_DSCR_CMD0_SDMS_TX0, .flags = IORESOURCE_DMA, }, [3] = { - .start = DSCR_CMD0_SDMS_RX0, - .end = DSCR_CMD0_SDMS_RX0, + .start = AU1200_DSCR_CMD0_SDMS_RX0, + .end = AU1200_DSCR_CMD0_SDMS_RX0, .flags = IORESOURCE_DMA, } }; @@ -299,13 +299,13 @@ static struct resource au1200_mmc1_resources[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_SDMS_TX1, - .end = DSCR_CMD0_SDMS_TX1, + .start = AU1200_DSCR_CMD0_SDMS_TX1, + .end = AU1200_DSCR_CMD0_SDMS_TX1, .flags = IORESOURCE_DMA, }, [3] = { - .start = DSCR_CMD0_SDMS_RX1, - .end = DSCR_CMD0_SDMS_RX1, + .start = AU1200_DSCR_CMD0_SDMS_RX1, + .end = AU1200_DSCR_CMD0_SDMS_RX1, .flags = IORESOURCE_DMA, } }; diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index 6fd070d..1bc16f0 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -215,8 +215,8 @@ static struct resource db1200_ide_res[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_DMA_REQ1, - .end = DSCR_CMD0_DMA_REQ1, + .start = AU1200_DSCR_CMD0_DMA_REQ1, + .end = AU1200_DSCR_CMD0_DMA_REQ1, .flags = IORESOURCE_DMA, }, }; @@ -358,13 +358,13 @@ static struct resource au1200_psc0_res[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_PSC0_TX, - .end = DSCR_CMD0_PSC0_TX, + .start = AU1200_DSCR_CMD0_PSC0_TX, + .end = AU1200_DSCR_CMD0_PSC0_TX, .flags = IORESOURCE_DMA, }, [3] = { - .start = DSCR_CMD0_PSC0_RX, - .end = DSCR_CMD0_PSC0_RX, + .start = AU1200_DSCR_CMD0_PSC0_RX, + .end = AU1200_DSCR_CMD0_PSC0_RX, .flags = IORESOURCE_DMA, }, }; @@ -416,13 +416,13 @@ static struct resource au1200_psc1_res[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_PSC1_TX, - .end = DSCR_CMD0_PSC1_TX, + .start = AU1200_DSCR_CMD0_PSC1_TX, + .end = AU1200_DSCR_CMD0_PSC1_TX, .flags = IORESOURCE_DMA, }, [3] = { - .start = DSCR_CMD0_PSC1_RX, - .end = DSCR_CMD0_PSC1_RX, + .start = AU1200_DSCR_CMD0_PSC1_RX, + .end = AU1200_DSCR_CMD0_PSC1_RX, .flags = IORESOURCE_DMA, }, }; diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 6ac0494..7de4f88 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -118,8 +118,8 @@ static struct resource ide_resources[] = { .flags = IORESOURCE_IRQ }, [2] = { - .start = DSCR_CMD0_DMA_REQ1, - .end = DSCR_CMD0_DMA_REQ1, + .start = AU1200_DSCR_CMD0_DMA_REQ1, + .end = AU1200_DSCR_CMD0_DMA_REQ1, .flags = IORESOURCE_DMA, }, }; diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 2fdacfe..323ce2d 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -126,66 +126,62 @@ typedef volatile struct au1xxx_ddma_desc { #define SW_STATUS_INUSE (1 << 0) /* Command 0 device IDs. */ -#ifdef CONFIG_SOC_AU1550 -#define DSCR_CMD0_UART0_TX 0 -#define DSCR_CMD0_UART0_RX 1 -#define DSCR_CMD0_UART3_TX 2 -#define DSCR_CMD0_UART3_RX 3 -#define DSCR_CMD0_DMA_REQ0 4 -#define DSCR_CMD0_DMA_REQ1 5 -#define DSCR_CMD0_DMA_REQ2 6 -#define DSCR_CMD0_DMA_REQ3 7 -#define DSCR_CMD0_USBDEV_RX0 8 -#define DSCR_CMD0_USBDEV_TX0 9 -#define DSCR_CMD0_USBDEV_TX1 10 -#define DSCR_CMD0_USBDEV_TX2 11 -#define DSCR_CMD0_USBDEV_RX3 12 -#define DSCR_CMD0_USBDEV_RX4 13 -#define DSCR_CMD0_PSC0_TX 14 -#define DSCR_CMD0_PSC0_RX 15 -#define DSCR_CMD0_PSC1_TX 16 -#define DSCR_CMD0_PSC1_RX 17 -#define DSCR_CMD0_PSC2_TX 18 -#define DSCR_CMD0_PSC2_RX 19 -#define DSCR_CMD0_PSC3_TX 20 -#define DSCR_CMD0_PSC3_RX 21 -#define DSCR_CMD0_PCI_WRITE 22 -#define DSCR_CMD0_NAND_FLASH 23 -#define DSCR_CMD0_MAC0_RX 24 -#define DSCR_CMD0_MAC0_TX 25 -#define DSCR_CMD0_MAC1_RX 26 -#define DSCR_CMD0_MAC1_TX 27 -#endif /* CONFIG_SOC_AU1550 */ - -#ifdef CONFIG_SOC_AU1200 -#define DSCR_CMD0_UART0_TX 0 -#define DSCR_CMD0_UART0_RX 1 -#define DSCR_CMD0_UART1_TX 2 -#define DSCR_CMD0_UART1_RX 3 -#define DSCR_CMD0_DMA_REQ0 4 -#define DSCR_CMD0_DMA_REQ1 5 -#define DSCR_CMD0_MAE_BE 6 -#define DSCR_CMD0_MAE_FE 7 -#define DSCR_CMD0_SDMS_TX0 8 -#define DSCR_CMD0_SDMS_RX0 9 -#define DSCR_CMD0_SDMS_TX1 10 -#define DSCR_CMD0_SDMS_RX1 11 -#define DSCR_CMD0_AES_TX 13 -#define DSCR_CMD0_AES_RX 12 -#define DSCR_CMD0_PSC0_TX 14 -#define DSCR_CMD0_PSC0_RX 15 -#define DSCR_CMD0_PSC1_TX 16 -#define DSCR_CMD0_PSC1_RX 17 -#define DSCR_CMD0_CIM_RXA 18 -#define DSCR_CMD0_CIM_RXB 19 -#define DSCR_CMD0_CIM_RXC 20 -#define DSCR_CMD0_MAE_BOTH 21 -#define DSCR_CMD0_LCD 22 -#define DSCR_CMD0_NAND_FLASH 23 -#define DSCR_CMD0_PSC0_SYNC 24 -#define DSCR_CMD0_PSC1_SYNC 25 -#define DSCR_CMD0_CIM_SYNC 26 -#endif /* CONFIG_SOC_AU1200 */ +#define AU1550_DSCR_CMD0_UART0_TX 0 +#define AU1550_DSCR_CMD0_UART0_RX 1 +#define AU1550_DSCR_CMD0_UART3_TX 2 +#define AU1550_DSCR_CMD0_UART3_RX 3 +#define AU1550_DSCR_CMD0_DMA_REQ0 4 +#define AU1550_DSCR_CMD0_DMA_REQ1 5 +#define AU1550_DSCR_CMD0_DMA_REQ2 6 +#define AU1550_DSCR_CMD0_DMA_REQ3 7 +#define AU1550_DSCR_CMD0_USBDEV_RX0 8 +#define AU1550_DSCR_CMD0_USBDEV_TX0 9 +#define AU1550_DSCR_CMD0_USBDEV_TX1 10 +#define AU1550_DSCR_CMD0_USBDEV_TX2 11 +#define AU1550_DSCR_CMD0_USBDEV_RX3 12 +#define AU1550_DSCR_CMD0_USBDEV_RX4 13 +#define AU1550_DSCR_CMD0_PSC0_TX 14 +#define AU1550_DSCR_CMD0_PSC0_RX 15 +#define AU1550_DSCR_CMD0_PSC1_TX 16 +#define AU1550_DSCR_CMD0_PSC1_RX 17 +#define AU1550_DSCR_CMD0_PSC2_TX 18 +#define AU1550_DSCR_CMD0_PSC2_RX 19 +#define AU1550_DSCR_CMD0_PSC3_TX 20 +#define AU1550_DSCR_CMD0_PSC3_RX 21 +#define AU1550_DSCR_CMD0_PCI_WRITE 22 +#define AU1550_DSCR_CMD0_NAND_FLASH 23 +#define AU1550_DSCR_CMD0_MAC0_RX 24 +#define AU1550_DSCR_CMD0_MAC0_TX 25 +#define AU1550_DSCR_CMD0_MAC1_RX 26 +#define AU1550_DSCR_CMD0_MAC1_TX 27 + +#define AU1200_DSCR_CMD0_UART0_TX 0 +#define AU1200_DSCR_CMD0_UART0_RX 1 +#define AU1200_DSCR_CMD0_UART1_TX 2 +#define AU1200_DSCR_CMD0_UART1_RX 3 +#define AU1200_DSCR_CMD0_DMA_REQ0 4 +#define AU1200_DSCR_CMD0_DMA_REQ1 5 +#define AU1200_DSCR_CMD0_MAE_BE 6 +#define AU1200_DSCR_CMD0_MAE_FE 7 +#define AU1200_DSCR_CMD0_SDMS_TX0 8 +#define AU1200_DSCR_CMD0_SDMS_RX0 9 +#define AU1200_DSCR_CMD0_SDMS_TX1 10 +#define AU1200_DSCR_CMD0_SDMS_RX1 11 +#define AU1200_DSCR_CMD0_AES_TX 13 +#define AU1200_DSCR_CMD0_AES_RX 12 +#define AU1200_DSCR_CMD0_PSC0_TX 14 +#define AU1200_DSCR_CMD0_PSC0_RX 15 +#define AU1200_DSCR_CMD0_PSC1_TX 16 +#define AU1200_DSCR_CMD0_PSC1_RX 17 +#define AU1200_DSCR_CMD0_CIM_RXA 18 +#define AU1200_DSCR_CMD0_CIM_RXB 19 +#define AU1200_DSCR_CMD0_CIM_RXC 20 +#define AU1200_DSCR_CMD0_MAE_BOTH 21 +#define AU1200_DSCR_CMD0_LCD 22 +#define AU1200_DSCR_CMD0_NAND_FLASH 23 +#define AU1200_DSCR_CMD0_PSC0_SYNC 24 +#define AU1200_DSCR_CMD0_PSC1_SYNC 25 +#define AU1200_DSCR_CMD0_CIM_SYNC 26 #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index 115cc7c..a5affb0 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -31,10 +31,10 @@ #ifdef CONFIG_MIPS_DB1550 -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX +#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX +#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX #define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR #define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index 56865e9..374416a 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -28,10 +28,10 @@ #include #include -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX +#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX +#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX /* * SPI and SMB are muxed on the Pb1200 board. diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h index 0b0f462..443b88a 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h @@ -30,10 +30,10 @@ #include #include -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX +#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX +#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX #define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR #define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:56:24 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:34084 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491761Ab1HBRvh (ORCPT ); Tue, 2 Aug 2011 19:51:37 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73231fxd.36 for ; Tue, 02 Aug 2011 10:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=5XE/NAwdDYXkOjrK+WNDCDO3QaZBvIBZ/QkOt9GE110=; b=CAwiEwZ5SxQMw6YoLCvtc5aXTjQ96cwmbLw3rjAtAvdnKP/yYHmkCvLZBPoTtLjYfE y+LOBEZVKZ2W27hqvD7gJ4gymixOoiW4NVTBz6o7FNir6HccLRirXFM0pmFKdY1oTQLY Lqm1mO63RmT+FfdtV3mEWBxjzb+l0vo/NUMPA= Received: by 10.223.10.143 with SMTP id p15mr8432318fap.12.1312307497156; Tue, 02 Aug 2011 10:51:37 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.34 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:35 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 11/15] MIPS: Alchemy: kill au1xxx.h header Date: Tue, 2 Aug 2011 19:51:06 +0200 Message-Id: <1312307470-6841-12-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30807 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1622 Content-Length: 5408 Lines: 152 No longer required Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 2 +- arch/mips/alchemy/devboards/db1x00/platform.c | 2 +- arch/mips/alchemy/devboards/pb1200/platform.c | 3 +- arch/mips/include/asm/mach-au1x00/au1xxx.h | 43 ------------------------- drivers/i2c/busses/i2c-au1550.c | 2 +- drivers/ide/au1xxx-ide.c | 2 +- drivers/mtd/nand/au1550nd.c | 6 +++- 7 files changed, 11 insertions(+), 49 deletions(-) delete mode 100644 arch/mips/include/asm/mach-au1x00/au1xxx.h diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 7eca306..657ae27 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index ef8017f..70bcfb5 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #include "../platform.h" diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 7de4f88..d7915b0 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -24,10 +24,11 @@ #include #include -#include +#include #include #include #include +#include #include "../platform.h" diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h deleted file mode 100644 index 1b36550..0000000 --- a/arch/mips/include/asm/mach-au1x00/au1xxx.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _AU1XXX_H_ -#define _AU1XXX_H_ - -#include - -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) -#include - -#elif defined(CONFIG_MIPS_PB1550) -#include - -#elif defined(CONFIG_MIPS_PB1200) -#include - -#elif defined(CONFIG_MIPS_DB1200) -#include - -#endif - -#endif /* _AU1XXX_H_ */ diff --git a/drivers/i2c/busses/i2c-au1550.c b/drivers/i2c/busses/i2c-au1550.c index 532828b..a714534 100644 --- a/drivers/i2c/busses/i2c-au1550.c +++ b/drivers/i2c/busses/i2c-au1550.c @@ -36,7 +36,7 @@ #include #include -#include +#include #include struct i2c_au1550_data { diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c index c778373..259786c 100644 --- a/drivers/ide/au1xxx-ide.c +++ b/drivers/ide/au1xxx-ide.c @@ -36,7 +36,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index e7767ee..fa5736b 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -19,7 +19,11 @@ #include #include -#include +#ifdef CONFIG_MIPS_PB1550 +#include +#elif defined(CONFIG_MIPS_DB1550) +#include +#endif #include /* -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:38 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:56:51 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:45013 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491762Ab1HBRvi (ORCPT ); Tue, 2 Aug 2011 19:51:38 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73262fxd.36 for ; Tue, 02 Aug 2011 10:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=BRBoguuj1NzWic7wAt7q9OawblX8Iki5DXG2gDaNnVs=; b=EqlmtYBzLB7lKA0AaZ5nuvnvWtwSb1a5Ls1UW8X4YPtHfUIczKwqf+eHBY/pRy8/oA RLwshX+Bf1e2zOA/XvLys1WSi2HDnYFnAeq5dJ1wLdtJ5Gyn7OYP6pFKEfGCOVR37bt9 xFK2EEhhzr0wri7lbEEnWDKEUOhIQaEYg3cG8= Received: by 10.223.13.69 with SMTP id b5mr8531940faa.1.1312307498686; Tue, 02 Aug 2011 10:51:38 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.37 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:37 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss , Subject: [PATCH 12/15] MMC: au1xmmc: remove Alchemy CPU subtype dependencies Date: Tue, 2 Aug 2011 19:51:07 +0200 Message-Id: <1312307470-6841-13-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30808 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1623 Content-Length: 6870 Lines: 237 Replace all occurrences of CONFIG_SOC_AU1??? with runtime feature detection. Cc: Signed-off-by: Manuel Lauss --- I'd like for this patch to go in via the mips tree since a few more depend on it. drivers/mmc/host/au1xmmc.c | 93 +++++++++++++++++++++++-------------------- 1 files changed, 50 insertions(+), 43 deletions(-) diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index ef72e87..56e7834 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -64,11 +64,8 @@ #define AU1XMMC_DESCRIPTOR_COUNT 1 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */ -#ifdef CONFIG_SOC_AU1100 -#define AU1XMMC_DESCRIPTOR_SIZE 0x0000ffff -#else /* Au1200 */ -#define AU1XMMC_DESCRIPTOR_SIZE 0x003fffff -#endif +#define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff +#define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ @@ -127,6 +124,7 @@ struct au1xmmc_host { #define HOST_F_XMIT 0x0001 #define HOST_F_RECV 0x0002 #define HOST_F_DMA 0x0010 +#define HOST_F_DBDMA 0x0020 #define HOST_F_ACTIVE 0x0100 #define HOST_F_STOP 0x1000 @@ -151,6 +149,16 @@ struct au1xmmc_host { #define DMA_CHANNEL(h) \ (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) +static inline int has_dbdma(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1200: + return 1; + default: + return 0; + } +} + static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) { u32 val = au_readl(HOST_CONFIG(host)); @@ -353,14 +361,12 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) data->bytes_xfered = 0; if (!data->error) { - if (host->flags & HOST_F_DMA) { -#ifdef CONFIG_SOC_AU1200 /* DBDMA */ + if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { u32 chan = DMA_CHANNEL(host); chan_tab_t *c = *((chan_tab_t **)chan); au1x_dma_chan_t *cp = c->chan_ptr; data->bytes_xfered = cp->ddma_bytecnt; -#endif } else data->bytes_xfered = (data->blocks * data->blksz) - host->pio.len; @@ -570,11 +576,10 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) host->status = HOST_S_DATA; - if (host->flags & HOST_F_DMA) { -#ifdef CONFIG_SOC_AU1200 /* DBDMA */ + if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) { u32 channel = DMA_CHANNEL(host); - /* Start the DMA as soon as the buffer gets something in it */ + /* Start the DBDMA as soon as the buffer gets something in it */ if (host->flags & HOST_F_RECV) { u32 mask = SD_STATUS_DB | SD_STATUS_NE; @@ -584,7 +589,6 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) } au1xxx_dbdma_start(channel); -#endif } } @@ -633,8 +637,7 @@ static int au1xmmc_prepare_data(struct au1xmmc_host *host, au_writel(data->blksz - 1, HOST_BLKSIZE(host)); - if (host->flags & HOST_F_DMA) { -#ifdef CONFIG_SOC_AU1200 /* DBDMA */ + if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { int i; u32 channel = DMA_CHANNEL(host); @@ -663,7 +666,6 @@ static int au1xmmc_prepare_data(struct au1xmmc_host *host, datalen -= len; } -#endif } else { host->pio.index = 0; host->pio.offset = 0; @@ -838,7 +840,6 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id) return IRQ_HANDLED; } -#ifdef CONFIG_SOC_AU1200 /* 8bit memory DMA device */ static dbdev_tab_t au1xmmc_mem_dbdev = { .dev_id = DSCR_CMD0_ALWAYS, @@ -905,7 +906,7 @@ static int au1xmmc_dbdma_init(struct au1xmmc_host *host) au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); /* DBDMA is good to go */ - host->flags |= HOST_F_DMA; + host->flags |= HOST_F_DMA | HOST_F_DBDMA; return 0; } @@ -918,7 +919,6 @@ static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) au1xxx_dbdma_chan_free(host->rx_chan); } } -#endif static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en) { @@ -997,8 +997,16 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev) mmc->f_min = 450000; mmc->f_max = 24000000; - mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; - mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1100: + mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; + mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; + break; + case ALCHEMY_CPU_AU1200: + mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; + mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; + break; + } mmc->max_blk_size = 2048; mmc->max_blk_count = 512; @@ -1028,11 +1036,12 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev) tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, (unsigned long)host); -#ifdef CONFIG_SOC_AU1200 - ret = au1xmmc_dbdma_init(host); - if (ret) - printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n"); -#endif + if (has_dbdma()) { + ret = au1xmmc_dbdma_init(host); + if (ret) + printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; " + "using PIO\n"); + } #ifdef CONFIG_LEDS_CLASS if (host->platdata && host->platdata->led) { @@ -1073,9 +1082,8 @@ out5: au_writel(0, HOST_CONFIG2(host)); au_sync(); -#ifdef CONFIG_SOC_AU1200 - au1xmmc_dbdma_shutdown(host); -#endif + if (host->flags & HOST_F_DBDMA) + au1xmmc_dbdma_shutdown(host); tasklet_kill(&host->data_task); tasklet_kill(&host->finish_task); @@ -1120,9 +1128,9 @@ static int __devexit au1xmmc_remove(struct platform_device *pdev) tasklet_kill(&host->data_task); tasklet_kill(&host->finish_task); -#ifdef CONFIG_SOC_AU1200 - au1xmmc_dbdma_shutdown(host); -#endif + if (host->flags & HOST_F_DBDMA) + au1xmmc_dbdma_shutdown(host); + au1xmmc_set_power(host, 0); free_irq(host->irq, host); @@ -1181,24 +1189,23 @@ static struct platform_driver au1xmmc_driver = { static int __init au1xmmc_init(void) { -#ifdef CONFIG_SOC_AU1200 - /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride - * of 8 bits. And since devices are shared, we need to create - * our own to avoid freaking out other devices. - */ - memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); - if (!memid) - printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n"); -#endif + if (has_dbdma()) { + /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride + * of 8 bits. And since devices are shared, we need to create + * our own to avoid freaking out other devices. + */ + memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); + if (!memid) + printk(KERN_ERR "au1xmmc: cannot add memory dbdma\n"); + } return platform_driver_register(&au1xmmc_driver); } static void __exit au1xmmc_exit(void) { -#ifdef CONFIG_SOC_AU1200 - if (memid) + if (has_dbdma() && memid) au1xxx_ddma_del_device(memid); -#endif + platform_driver_unregister(&au1xmmc_driver); } -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:57:16 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:33355 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491763Ab1HBRvk (ORCPT ); Tue, 2 Aug 2011 19:51:40 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73189fxd.36 for ; Tue, 02 Aug 2011 10:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=DWKOjKoXcf9KMJQZKrK3XLoUrhELA0ijU6/uzQk01zo=; b=TeriulgoFq4wHmp0tzqDbjYES4y0PZURGmVLen7eYtKBCCrQuNZCheWMC1wx6sZNBy ZPeBWMFzNIy5CxlDrySXkbIESAOwnTBlPNVY2+I8i3EL8XSjeRujwfW5np7FOWsRvZQm 5LlLy+WiL5Z6at88rm+7AqqiIdi3deGc2AVpM= Received: by 10.223.20.143 with SMTP id f15mr8610697fab.49.1312307500282; Tue, 02 Aug 2011 10:51:40 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.38 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:39 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 13/15] MIPS: remove __init from add_wired_entry() Date: Tue, 2 Aug 2011 19:51:08 +0200 Message-Id: <1312307470-6841-14-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30809 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1624 Content-Length: 1505 Lines: 42 For Alchemy-PCI I need to add a wired entry after resuming from RAM; remove the __init from add_wired_entry() so that this actually works. Signed-off-by: Manuel Lauss --- arch/mips/mm/tlb-r3k.c | 4 ++-- arch/mips/mm/tlb-r4k.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index 40424af..87bb85d 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -223,8 +223,8 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) local_irq_restore(flags); } -void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) +void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) { unsigned long flags; unsigned long old_ctx; diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index ba40325..0d394e0 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -337,8 +337,8 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) EXIT_CRITICAL(flags); } -void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) +void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) { unsigned long flags; unsigned long wired; -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:57:46 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:36145 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491200Ab1HBRvo (ORCPT ); Tue, 2 Aug 2011 19:51:44 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73158fxd.36 for ; Tue, 02 Aug 2011 10:51:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Hy7UGh7lq5Tzf8klYMI3GZKQI3S+gXA0t3MpBeEm1oU=; b=old9N0+QwXXIZW1RC3vIotvpg2LS7w+2dLcZgKFmcglWXTLxg7e5P0zjeS3i6wFdWh aN8TWqDlm30z0B7HPRMape5y5QtDJ4M/7oFLiuKCFNCPVXGSGwiByU98n9Je+LSSdAdK lJk32JX6pPJm0KjmSXihuy9yccjLcDWDuCn2I= Received: by 10.223.151.6 with SMTP id a6mr1403406faw.120.1312307504010; Tue, 02 Aug 2011 10:51:44 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.40 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:42 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 14/15] MIPS: Alchemy: redo PCI as platform driver Date: Tue, 2 Aug 2011 19:51:09 +0200 Message-Id: <1312307470-6841-15-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30810 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1625 Content-Length: 58828 Lines: 1890 - Rewrite Alchemy PCI support as a platform driver. - Fixup boards which have PCI. Run-tested on DB1500 and DB1550. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/Makefile | 2 - arch/mips/alchemy/common/pci.c | 104 ----- arch/mips/alchemy/common/setup.c | 6 +- arch/mips/alchemy/devboards/db1x00/board_setup.c | 24 - arch/mips/alchemy/devboards/db1x00/platform.c | 123 ++++++ arch/mips/alchemy/devboards/pb1500/board_setup.c | 33 +- arch/mips/alchemy/devboards/pb1500/platform.c | 48 ++- arch/mips/alchemy/devboards/pb1550/board_setup.c | 6 - arch/mips/alchemy/devboards/pb1550/platform.c | 48 ++- arch/mips/alchemy/gpr/board_setup.c | 12 - arch/mips/alchemy/gpr/platform.c | 47 ++ arch/mips/alchemy/mtx-1/board_setup.c | 40 -- arch/mips/alchemy/mtx-1/platform.c | 62 +++ arch/mips/alchemy/xxs1500/board_setup.c | 8 - arch/mips/include/asm/mach-au1x00/au1000.h | 142 ++++--- arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-au1000.c | 43 -- arch/mips/pci/ops-au1000.c | 308 ------------- arch/mips/pci/pci-alchemy.c | 500 ++++++++++++++++++++++ 19 files changed, 934 insertions(+), 625 deletions(-) delete mode 100644 arch/mips/alchemy/common/pci.c delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.c diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 31728e0..3792739 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -14,5 +14,3 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) obj-$(CONFIG_GPIOLIB) += gpiolib.o endif - -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c deleted file mode 100644 index 7866cf5..0000000 --- a/arch/mips/alchemy/common/pci.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1x00 PCI support. - * - * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * Support for all devices (greater than 16) added by David Gathright. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include - -#include - -/* TBD */ -static struct resource pci_io_resource = { - .start = PCI_IO_START, - .end = PCI_IO_END, - .name = "PCI IO space", - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = { - .start = PCI_MEM_START, - .end = PCI_MEM_END, - .name = "PCI memory space", - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops au1x_pci_ops; - -static struct pci_controller au1x_controller = { - .pci_ops = &au1x_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, -}; - -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) -static unsigned long virt_io_addr; -#endif - -static int __init au1x_pci_setup(void) -{ - extern void au1x_pci_cfg_init(void); - -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) - virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, - Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); - - if (!virt_io_addr) { - printk(KERN_ERR "Unable to ioremap pci space\n"); - return 1; - } - au1x_controller.io_map_base = virt_io_addr; - -#ifdef CONFIG_DMA_NONCOHERENT - { - /* - * Set the NC bit in controller for Au1500 pre-AC silicon - */ - u32 prid = read_c0_prid(); - - if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) { - au_writel((1 << 16) | au_readl(Au1500_PCI_CFG), - Au1500_PCI_CFG); - printk(KERN_INFO "Non-coherent PCI accesses enabled\n"); - } - } -#endif - - set_io_port_base(virt_io_addr); -#endif - - au1x_pci_cfg_init(); - - register_pci_controller(&au1x_controller); - return 0; -} - -arch_initcall(au1x_pci_setup); diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 1b887c8..37ffd99 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -73,8 +73,8 @@ void __init plat_mem_setup(void) /* This routine should be valid for all Au1x based boards */ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) { - u32 start = (u32)Au1500_PCI_MEM_START; - u32 end = (u32)Au1500_PCI_MEM_END; + unsigned long start = ALCHEMY_PCI_MEMWIN_START; + unsigned long end = ALCHEMY_PCI_MEMWIN_END; /* Don't fixup 36-bit addresses */ if ((phys_addr >> 32) != 0) @@ -82,7 +82,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) /* Check for PCI memory window */ if (phys_addr >= start && (phys_addr + size - 1) <= end) - return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START); + return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr); /* default nop */ return phys_addr; diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 5c956fe..2b2178f 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -40,24 +40,6 @@ #include -#ifdef CONFIG_MIPS_DB1500 -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ -}; - -#endif - - -#ifdef CONFIG_MIPS_DB1550 -char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */ - [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */ -}; -#endif - - #ifdef CONFIG_MIPS_BOSPORUS char irq_tab_alchemy[][5] __initdata = { [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */ @@ -91,12 +73,6 @@ const char *get_system_type(void) #ifdef CONFIG_MIPS_MIRAGE -char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */ - [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */ -}; - static void mirage_power_off(void) { alchemy_gpio_direction_output(210, 1); diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 70bcfb5..990367f 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -25,6 +25,8 @@ #include #include "../platform.h" +struct pci_dev; + /* DB1xxx PCMCIA interrupt sources: * CD0/1 GPIO0/3 * STSCHG0/1 GPIO1/4 @@ -85,6 +87,127 @@ #endif #endif +#ifdef CONFIG_PCI +#ifdef CONFIG_MIPS_DB1500 +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} +#endif + +#ifdef CONFIG_MIPS_DB1550 +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 11) + return (pin == 1) ? AU1550_PCI_INTC : 0xff; + if (slot == 12) { + switch (pin) { + case 1: return AU1550_PCI_INTB; + case 2: return AU1550_PCI_INTC; + case 3: return AU1550_PCI_INTD; + case 4: return AU1550_PCI_INTA; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1550_PCI_INTA; + case 2: return AU1550_PCI_INTB; + case 3: return AU1550_PCI_INTC; + case 4: return AU1550_PCI_INTD; + } + } + return -1; +} +#endif + +#ifdef CONFIG_MIPS_BOSPORUS +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 11) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + default: return 0xff; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} +#endif + +#ifdef CONFIG_MIPS_MIRAGE +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 11) + return (pin == 1) ? AU1500_PCI_INTD : 0xff; + if (slot == 12) + return (pin == 3) ? AU1500_PCI_INTC : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + default: return 0xff; + } + } + return -1; +} +#endif + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata db1xxx_pci_pd = { + .board_map_irq = db1xxx_map_pci_irq, +}; + +static struct platform_device db1xxx_pci_host_dev = { + .dev.platform_data = &db1xxx_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + +static int __init db15x0_pci_init(void) +{ + return platform_device_register(&db1xxx_pci_host_dev); +} +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +arch_initcall(db15x0_pci_init); +#endif + static int __init db1xxx_dev_init(void) { #ifdef DB1XXX_HAS_PCMCIA diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index 3b4fa32..37c1883 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c @@ -33,13 +33,6 @@ #include - -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ -}; - - const char *get_system_type(void) { return "Alchemy Pb1500"; @@ -101,20 +94,18 @@ void __init board_setup(void) #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ #ifdef CONFIG_PCI - /* Setup PCI bus controller */ - au_writel(0, Au1500_PCI_CMEM); - au_writel(0x00003fff, Au1500_CFG_BASE); -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif - au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); - au_writel(0, Au1500_PCI_MWBASE_REV_CCL); - au_writel(0x02a00356, Au1500_PCI_STATCMD); - au_writel(0x00003c04, Au1500_PCI_HDRTYPE); - au_writel(0x00000008, Au1500_PCI_MBAR); - au_sync(); + { + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR); + /* Setup PCI bus controller */ + __raw_writel(0x00003fff, base + PCI_REG_CMEM); + __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV); + __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL); + __raw_writel(0x02a00356, base + PCI_REG_STATCMD); + __raw_writel(0x00003c04, base + PCI_REG_PARAM); + __raw_writel(0x00000008, base + PCI_REG_MBAR); + wmb(); + } #endif /* Enable sys bus clock divider when IDLE state or no bus activity. */ diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c index 42b0e6b..9f0b5a0 100644 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -19,11 +19,56 @@ */ #include +#include #include #include #include "../platform.h" +static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata pb1500_pci_pd = { + .board_map_irq = pb1500_map_pci_irq, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device pb1500_pci_host = { + .dev.platform_data = &pb1500_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + static int __init pb1500_dev_init(void) { int swapped; @@ -41,7 +86,8 @@ static int __init pb1500_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + platform_device_register(&pb1500_pci_host); return 0; } -device_initcall(pb1500_dev_init); +arch_initcall(pb1500_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c index b790213..0f62d1e 100644 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c @@ -37,12 +37,6 @@ #include - -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */ -}; - const char *get_system_type(void) { return "Alchemy Pb1550"; diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c index 87c79b7..0c5711f 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -19,13 +19,56 @@ */ #include - +#include #include #include #include #include "../platform.h" +static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) { + switch (pin) { + case 1: return AU1500_PCI_INTB; + case 2: return AU1500_PCI_INTC; + case 3: return AU1500_PCI_INTD; + case 4: return AU1500_PCI_INTA; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata pb1550_pci_pd = { + .board_map_irq = pb1550_map_pci_irq, +}; + +static struct platform_device pb1550_pci_host = { + .dev.platform_data = &pb1550_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + static int __init pb1550_dev_init(void) { int swapped; @@ -57,7 +100,8 @@ static int __init pb1550_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 4, swapped); + platform_device_register(&pb1550_pci_host); return 0; } -device_initcall(pb1550_dev_init); +arch_initcall(pb1550_dev_init); diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c index 5f8f069..dea45c7 100644 --- a/arch/mips/alchemy/gpr/board_setup.c +++ b/arch/mips/alchemy/gpr/board_setup.c @@ -36,10 +36,6 @@ #include -char irq_tab_alchemy[][5] __initdata = { - [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, -}; - static void gpr_reset(char *c) { /* switch System-LED to orange (red# and green# on) */ @@ -76,12 +72,4 @@ void __init board_setup(void) /* Take away Reset of UMTS-card */ alchemy_gpio_direction_output(215, 1); - -#ifdef CONFIG_PCI -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif -#endif } diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c index 14b4662..f22103a 100644 --- a/arch/mips/alchemy/gpr/platform.c +++ b/arch/mips/alchemy/gpr/platform.c @@ -167,6 +167,45 @@ static struct i2c_board_info gpr_i2c_info[] __initdata = { } }; + + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot == 0) && (pin == 1)) + return AU1500_PCI_INTA; + else if ((slot == 0) && (pin == 2)) + return AU1500_PCI_INTB; + + return 0xff; +} + +static struct alchemy_pci_platdata gpr_pci_pd = { + .board_map_irq = gpr_map_pci_irq, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device gpr_pci_host_dev = { + .dev.platform_data = &gpr_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + static struct platform_device *gpr_devices[] __initdata = { &gpr_wdt_device, &gpr_mtd_device, @@ -174,6 +213,14 @@ static struct platform_device *gpr_devices[] __initdata = { &gpr_led_devices, }; +static int __init gpr_pci_init(void) +{ + return platform_device_register(&gpr_pci_host_dev); +} +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +arch_initcall(gpr_pci_init); + + static int __init gpr_dev_init(void) { i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info)); diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index 3ae984c..851a5ab 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -38,20 +38,6 @@ #include -char irq_tab_alchemy[][5] __initdata = { - [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */ - [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ - [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */ - [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ - [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */ - [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ - [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */ - [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ -}; - -extern int (*board_pci_idsel)(unsigned int devsel, int assert); -int mtx1_pci_idsel(unsigned int devsel, int assert); - static void mtx1_reset(char *c) { /* Jump to the reset vector */ @@ -74,15 +60,6 @@ void __init board_setup(void) alchemy_gpio_direction_output(204, 0); #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ -#ifdef CONFIG_PCI -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif - board_pci_idsel = mtx1_pci_idsel; -#endif - /* Initialize sys_pinfunc */ au_writel(SYS_PF_NI2, SYS_PINFUNC); @@ -104,23 +81,6 @@ void __init board_setup(void) printk(KERN_INFO "4G Systems MTX-1 Board\n"); } -int -mtx1_pci_idsel(unsigned int devsel, int assert) -{ - /* This function is only necessary to support a proprietary Cardbus - * adapter on the mtx-1 "singleboard" variant. It triggers a custom - * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. - */ - if (assert && devsel != 0) - /* Suppress signal to Cardbus */ - alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ - else - alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */ - - udelay(1); - return 1; -} - static int __init mtx1_init_irq(void) { irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c index 55628e3..cc47b68 100644 --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/mtx-1/platform.c @@ -135,7 +135,69 @@ static struct platform_device mtx1_mtd = { .resource = &mtx1_mtd_resource, }; +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static int mtx1_pci_idsel(unsigned int devsel, int assert) +{ + /* This function is only necessary to support a proprietary Cardbus + * adapter on the mtx-1 "singleboard" variant. It triggers a custom + * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. + */ + if (assert && devsel != 0) + /* Suppress signal to Cardbus */ + alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ + else + alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */ + + udelay(1); + return 1; +} + +static const char mtx1_irqtab[][5] = { + [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */ + [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ + [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */ + [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ + [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */ + [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ + [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */ + [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ +}; + +static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + return mtx1_irqtab[slot][pin]; +} + +static struct alchemy_pci_platdata mtx1_pci_pd = { + .board_map_irq = mtx1_map_pci_irq, + .board_pci_idsel = mtx1_pci_idsel, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device mtx1_pci_host = { + .dev.platform_data = &mtx1_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + + static struct __initdata platform_device * mtx1_devs[] = { + &mtx1_pci_host, &mtx1_gpio_leds, &mtx1_wdt, &mtx1_button, diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c index 81e57fa..3fa83f7 100644 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ b/arch/mips/alchemy/xxs1500/board_setup.c @@ -70,14 +70,6 @@ void __init board_setup(void) /* Enable DTR (MCR bit 0) = USB power up */ __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); wmb(); - -#ifdef CONFIG_PCI -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif -#endif } static int __init xxs1500_init_irq(void) diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index bcf3d1e..5da2fd7 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -254,6 +254,14 @@ enum alchemy_usb_block { }; int alchemy_usb_control(int block, int enable); +/* PCI controller platform data */ +struct alchemy_pci_platdata { + int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); + int (*board_pci_idsel)(unsigned int devsel, int assert); + /* bits to set/clear in PCI_CONFIG register */ + unsigned long pci_cfg_set; + unsigned long pci_cfg_clr; +}; /* SOC Interrupt numbers */ @@ -1309,58 +1317,30 @@ enum soc_au1200_ints { # define AC97C_RS (1 << 1) # define AC97C_CE (1 << 0) -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) -/* Au1500 PCI Controller */ -#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ -#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) -#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) -# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \ - (1 << 25) | (1 << 26) | (1 << 27)) -#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) -#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) -#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) -#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) -#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) -#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) -#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) -#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) -#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) -#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) -#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) -#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) - -#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */ -/* - * All of our structures, like PCI resource, have 32-bit members. - * Drivers are expected to do an ioremap on the PCI MEM resource, but it's - * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch - * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and - * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM - * addresses. For PCI I/O, it's simpler because we get to do the ioremap - * ourselves and then adjust the device's resources. +/* The PCI chip selects are outside the 32bit space, and since we can't + * just program the 36bit addresses into BARs, we have to take a chunk + * out of the 32bit space and reserve it for PCI. When these addresses + * are ioremap()ed, they'll be fixed up to the real 36bit address before + * being passed to the real ioremap function. */ -#define Au1500_EXT_CFG 0x600000000ULL -#define Au1500_EXT_CFG_TYPE1 0x680000000ULL -#define Au1500_PCI_IO_START 0x500000000ULL -#define Au1500_PCI_IO_END 0x5000FFFFFULL -#define Au1500_PCI_MEM_START 0x440000000ULL -#define Au1500_PCI_MEM_END 0x44FFFFFFFULL +#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) +#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) -#define PCI_IO_START 0x00001000 -#define PCI_IO_END 0x000FFFFF -#define PCI_MEM_START 0x40000000 -#define PCI_MEM_END 0x4FFFFFFF +/* for PCI IO it's simpler because we get to do the ioremap ourselves and then + * adjust the device's resources. + */ +#define ALCHEMY_PCI_IOWIN_START 0x00001000 +#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF -#define PCI_FIRST_DEVFN (0 << 3) -#define PCI_LAST_DEVFN (19 << 3) +#ifdef CONFIG_PCI #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xfffffffffULL -#else /* Au1000 and Au1100 and Au1200 */ +#else /* Don't allow any legacy ports probing */ #define IOPORT_RESOURCE_START 0x10000000 @@ -1368,13 +1348,77 @@ enum soc_au1200_ints { #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xfffffffffULL -#define PCI_IO_START 0 -#define PCI_IO_END 0 -#define PCI_MEM_START 0 -#define PCI_MEM_END 0 -#define PCI_FIRST_DEVFN 0 -#define PCI_LAST_DEVFN 0 - #endif +/* PCI controller block register offsets */ +#define PCI_REG_CMEM 0x0000 +#define PCI_REG_CONFIG 0x0004 +#define PCI_REG_B2BMASK_CCH 0x0008 +#define PCI_REG_B2BBASE0_VID 0x000C +#define PCI_REG_B2BBASE1_SID 0x0010 +#define PCI_REG_MWMASK_DEV 0x0014 +#define PCI_REG_MWBASE_REV_CCL 0x0018 +#define PCI_REG_ERR_ADDR 0x001C +#define PCI_REG_SPEC_INTACK 0x0020 +#define PCI_REG_ID 0x0100 +#define PCI_REG_STATCMD 0x0104 +#define PCI_REG_CLASSREV 0x0108 +#define PCI_REG_PARAM 0x010C +#define PCI_REG_MBAR 0x0110 +#define PCI_REG_TIMEOUT 0x0140 + +/* PCI controller block register bits */ +#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */ +#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) +#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) +#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */ +#define PCI_CONFIG_ET (1 << 26) /* error in target mode */ +#define PCI_CONFIG_EF (1 << 25) /* fatal error */ +#define PCI_CONFIG_EP (1 << 24) /* parity error */ +#define PCI_CONFIG_EM (1 << 23) /* multiple errors */ +#define PCI_CONFIG_BM (1 << 22) /* bad master error */ +#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */ +#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */ +#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */ +#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */ +#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */ +#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */ +#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */ +#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */ +#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */ +#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */ +#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */ +#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */ +#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */ +#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */ +#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */ +#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */ +#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */ +#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */ +#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */ +#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */ +#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) +#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */ +#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) +#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) +#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) +#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) +#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) +#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) +#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) +#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) +#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) +#define PCI_ID_DID(x) (((x) & 0xffff) << 16) +#define PCI_ID_VID(x) ((x) & 0xffff) +#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) +#define PCI_STATCMD_CMD(x) ((x) & 0xffff) +#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) +#define PCI_CLASSREV_REV(x) ((x) & 0xff) +#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) +#define PCI_PARAM_HT(x) (((x) & 0xff) << 16) +#define PCI_PARAM_LT(x) (((x) & 0xff) << 8) +#define PCI_PARAM_CLS(x) ((x) & 0xff) +#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */ +#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */ + #endif diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 4df8799..bb82cbd 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -18,14 +18,13 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ ops-bcm63xx.o +obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o # # These are still pretty much in the old state, watch, go blind. # obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o -obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o -obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c deleted file mode 100644 index e2ddfc4..0000000 --- a/arch/mips/pci/fixup-au1000.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Board specific PCI fixups. - * - * Copyright 2001-2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include - -extern char irq_tab_alchemy[][5]; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_tab_alchemy[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c deleted file mode 100644 index 9a57c5a..0000000 --- a/arch/mips/pci/ops-au1000.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1xx0 PCI support. - * - * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * Support for all devices (greater than 16) added by David Gathright. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#include - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(KERN_DEBUG x) -#else -#define DBG(x...) -#endif - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -int (*board_pci_idsel)(unsigned int devsel, int assert); - -void mod_wired_entry(int entry, unsigned long entrylo0, - unsigned long entrylo1, unsigned long entryhi, - unsigned long pagemask) -{ - unsigned long old_pagemask; - unsigned long old_ctx; - - /* Save old context and create impossible VPN2 value */ - old_ctx = read_c0_entryhi() & 0xff; - old_pagemask = read_c0_pagemask(); - write_c0_index(entry); - write_c0_pagemask(pagemask); - write_c0_entryhi(entryhi); - write_c0_entrylo0(entrylo0); - write_c0_entrylo1(entrylo1); - tlb_write_indexed(); - write_c0_entryhi(old_ctx); - write_c0_pagemask(old_pagemask); -} - -static struct vm_struct *pci_cfg_vm; -static int pci_cfg_wired_entry; -static unsigned long last_entryLo0, last_entryLo1; - -/* - * We can't ioremap the entire pci config space because it's too large. - * Nor can we call ioremap dynamically because some device drivers use - * the PCI config routines from within interrupt handlers and that - * becomes a problem in get_vm_area(). We use one wired TLB to handle - * all config accesses for all busses. - */ -void __init au1x_pci_cfg_init(void) -{ - /* Reserve a wired entry for PCI config accesses */ - pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); - if (!pci_cfg_vm) - panic(KERN_ERR "PCI unable to get vm area\n"); - pci_cfg_wired_entry = read_c0_wired(); - add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); - last_entryLo0 = last_entryLo1 = 0xffffffff; -} - -static int config_access(unsigned char access_type, struct pci_bus *bus, - unsigned int dev_fn, unsigned char where, u32 *data) -{ -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) - unsigned int device = PCI_SLOT(dev_fn); - unsigned int function = PCI_FUNC(dev_fn); - unsigned long offset, status; - unsigned long cfg_base; - unsigned long flags; - int error = PCIBIOS_SUCCESSFUL; - unsigned long entryLo0, entryLo1; - - if (device > 19) { - *data = 0xffffffff; - return -1; - } - - local_irq_save(flags); - au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)), - Au1500_PCI_STATCMD); - au_sync_udelay(1); - - /* - * Allow board vendors to implement their own off-chip IDSEL. - * If it doesn't succeed, may as well bail out at this point. - */ - if (board_pci_idsel && board_pci_idsel(device, 1) == 0) { - *data = 0xffffffff; - local_irq_restore(flags); - return -1; - } - - /* Setup the config window */ - if (bus->number == 0) - cfg_base = (1 << device) << 11; - else - cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); - - /* Setup the lower bits of the 36-bit address */ - offset = (function << 8) | (where & ~0x3); - /* Pick up any address that falls below the page mask */ - offset |= cfg_base & ~PAGE_MASK; - - /* Page boundary */ - cfg_base = cfg_base & PAGE_MASK; - - /* - * To improve performance, if the current device is the same as - * the last device accessed, we don't touch the TLB. - */ - entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; - entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; - if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) { - mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, - (unsigned long)pci_cfg_vm->addr, PM_4K); - last_entryLo0 = entryLo0; - last_entryLo1 = entryLo1; - } - - if (access_type == PCI_ACCESS_WRITE) - au_writel(*data, (int)(pci_cfg_vm->addr + offset)); - else - *data = au_readl((int)(pci_cfg_vm->addr + offset)); - - au_sync_udelay(2); - - DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n", - access_type, bus->number, device, where, *data, offset); - - /* Check master abort */ - status = au_readl(Au1500_PCI_STATCMD); - - if (status & (1 << 29)) { - *data = 0xffffffff; - error = -1; - DBG("Au1x Master Abort\n"); - } else if ((status >> 28) & 0xf) { - DBG("PCI ERR detected: device %u, status %lx\n", - device, (status >> 28) & 0xf); - - /* Clear errors */ - au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD); - - *data = 0xffffffff; - error = -1; - } - - /* Take away the IDSEL. */ - if (board_pci_idsel) - (void)board_pci_idsel(device, 0); - - local_irq_restore(flags); - return error; -#endif -} - -static int read_config_byte(struct pci_bus *bus, unsigned int devfn, - int where, u8 *val) -{ - u32 data; - int ret; - - ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (where & 1) - data >>= 8; - if (where & 2) - data >>= 16; - *val = data & 0xff; - return ret; -} - -static int read_config_word(struct pci_bus *bus, unsigned int devfn, - int where, u16 *val) -{ - u32 data; - int ret; - - ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (where & 2) - data >>= 16; - *val = data & 0xffff; - return ret; -} - -static int read_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, u32 *val) -{ - int ret; - - ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); - return ret; -} - -static int write_config_byte(struct pci_bus *bus, unsigned int devfn, - int where, u8 val) -{ - u32 data = 0; - - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_word(struct pci_bus *bus, unsigned int devfn, - int where, u16 val) -{ - u32 data = 0; - - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, u32 val) -{ - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int config_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - switch (size) { - case 1: { - u8 _val; - int rc = read_config_byte(bus, devfn, where, &_val); - - *val = _val; - return rc; - } - case 2: { - u16 _val; - int rc = read_config_word(bus, devfn, where, &_val); - - *val = _val; - return rc; - } - default: - return read_config_dword(bus, devfn, where, val); - } -} - -static int config_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - switch (size) { - case 1: - return write_config_byte(bus, devfn, where, (u8) val); - case 2: - return write_config_word(bus, devfn, where, (u16) val); - default: - return write_config_dword(bus, devfn, where, val); - } -} - -struct pci_ops au1x_pci_ops = { - config_read, - config_write -}; diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c new file mode 100644 index 0000000..f6b599f --- /dev/null +++ b/arch/mips/pci/pci-alchemy.c @@ -0,0 +1,500 @@ +/* + * Alchemy PCI host mode support. + * + * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * Support for all devices (greater than 16) added by David Gathright. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_DEBUG_PCI +#define DBG(x...) printk(KERN_DEBUG x) +#else +#define DBG(x...) do {} while (0) +#endif + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +struct alchemy_pci_context { + struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ + void __iomem *regs; /* ctrl base */ + unsigned long last_elo0; + unsigned long last_elo1; + int wired_entry; + struct vm_struct *pci_cfg_vm; + + int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); + int (*board_pci_idsel)(unsigned int devsel, int assert); +}; + +/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr + * in arch/mips/alchemy/common/setup.c + */ +static struct resource alchemy_pci_def_memres = { + .start = ALCHEMY_PCI_MEMWIN_START, + .end = ALCHEMY_PCI_MEMWIN_END, + .name = "PCI memory space", + .flags = IORESOURCE_MEM +}; + +static struct resource alchemy_pci_def_iores = { + .start = ALCHEMY_PCI_IOWIN_START, + .end = ALCHEMY_PCI_IOWIN_END, + .name = "PCI IO space", + .flags = IORESOURCE_IO +}; + +static void mod_wired_entry(int entry, unsigned long entrylo0, + unsigned long entrylo1, unsigned long entryhi, + unsigned long pagemask) +{ + unsigned long old_pagemask; + unsigned long old_ctx; + + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & 0xff; + old_pagemask = read_c0_pagemask(); + write_c0_index(entry); + write_c0_pagemask(pagemask); + write_c0_entryhi(entryhi); + write_c0_entrylo0(entrylo0); + write_c0_entrylo1(entrylo1); + tlb_write_indexed(); + write_c0_entryhi(old_ctx); + write_c0_pagemask(old_pagemask); +} + +static int config_access(unsigned char access_type, struct pci_bus *bus, + unsigned int dev_fn, unsigned char where, u32 *data) +{ + struct alchemy_pci_context *ctx = bus->sysdata; + unsigned int device = PCI_SLOT(dev_fn); + unsigned int function = PCI_FUNC(dev_fn); + unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r; + int error = PCIBIOS_SUCCESSFUL; + + if (device > 19) { + *data = 0xffffffff; + return -1; + } + + local_irq_save(flags); + r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; + r |= PCI_STATCMD_STATUS(0x2000); + __raw_writel(r, ctx->regs + PCI_REG_STATCMD); + wmb(); + + /* + * Allow board vendors to implement their own off-chip IDSEL. + * If it doesn't succeed, may as well bail out at this point. + */ + if (ctx->board_pci_idsel(device, 1) == 0) { + *data = 0xffffffff; + local_irq_restore(flags); + return -1; + } + + /* Setup the config window */ + if (bus->number == 0) + cfg_base = (1 << device) << 11; + else + cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); + + /* Setup the lower bits of the 36-bit address */ + offset = (function << 8) | (where & ~0x3); + /* Pick up any address that falls below the page mask */ + offset |= cfg_base & ~PAGE_MASK; + + /* Page boundary */ + cfg_base = cfg_base & PAGE_MASK; + + /* + * To improve performance, if the current device is the same as + * the last device accessed, we don't touch the TLB. + */ + entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; + entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; + if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) { + mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1, + (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); + ctx->last_elo0 = entryLo0; + ctx->last_elo1 = entryLo1; + } + + if (access_type == PCI_ACCESS_WRITE) + __raw_writel(*data, ctx->pci_cfg_vm->addr + offset); + else + *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); + wmb(); + + DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n", + access_type, bus->number, device, where, *data, offset); + + /* check for errors, master abort */ + status = __raw_readl(ctx->regs + PCI_REG_STATCMD); + if (status & (1 << 29)) { + *data = 0xffffffff; + error = -1; + DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d", + access_type, bus->number, device); + } else if ((status >> 28) & 0xf) { + DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", + device, (status >> 28) & 0xf); + + /* clear errors */ + __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); + + *data = 0xffffffff; + error = -1; + } + + /* Take away the IDSEL. */ + (void)ctx->board_pci_idsel(device, 0); + + local_irq_restore(flags); + return error; +} + +static int read_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 *val) +{ + u32 data; + int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + + if (where & 1) + data >>= 8; + if (where & 2) + data >>= 16; + *val = data & 0xff; + return ret; +} + +static int read_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 *val) +{ + u32 data; + int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + + if (where & 2) + data >>= 16; + *val = data & 0xffff; + return ret; +} + +static int read_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 *val) +{ + return config_access(PCI_ACCESS_READ, bus, devfn, where, val); +} + +static int write_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 val) +{ + u32 data = 0; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 val) +{ + u32 data = 0; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 val) +{ + return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val); +} + +static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + switch (size) { + case 1: { + u8 _val; + int rc = read_config_byte(bus, devfn, where, &_val); + + *val = _val; + return rc; + } + case 2: { + u16 _val; + int rc = read_config_word(bus, devfn, where, &_val); + + *val = _val; + return rc; + } + default: + return read_config_dword(bus, devfn, where, val); + } +} + +static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + switch (size) { + case 1: + return write_config_byte(bus, devfn, where, (u8) val); + case 2: + return write_config_word(bus, devfn, where, (u16) val); + default: + return write_config_dword(bus, devfn, where, val); + } +} + +static struct pci_ops alchemy_pci_ops = { + .read = alchemy_pci_read, + .write = alchemy_pci_write, +}; + +static int alchemy_pci_def_idsel(unsigned int devsel, int assert) +{ + return 1; /* success */ +} + +static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx) +{ + ctx->wired_entry = read_c0_wired(); + add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); + ctx->last_elo0 = ctx->last_elo1 = ~0; +} + +static int __devinit alchemy_pci_probe(struct platform_device *pdev) +{ + struct alchemy_pci_platdata *pd = pdev->dev.platform_data; + struct alchemy_pci_context *ctx; + void __iomem *virt_io; + unsigned long val; + struct resource *r; + int ret; + + /* need at least PCI IRQ mapping table */ + if (!pd) { + dev_err(&pdev->dev, "need platform data for PCI setup\n"); + ret = -ENODEV; + goto out; + } + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + dev_err(&pdev->dev, "no memory for pcictl context\n"); + ret = -ENOMEM; + goto out; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no pcictl ctrl regs resource\n"); + ret = -ENODEV; + goto out1; + } + + if (!request_mem_region(r->start, resource_size(r), pdev->name)) { + dev_err(&pdev->dev, "cannot claim pci regs\n"); + ret = -ENODEV; + goto out1; + } + + ctx->regs = ioremap_nocache(r->start, resource_size(r)); + if (!ctx->regs) { + dev_err(&pdev->dev, "cannot map pci regs\n"); + ret = -ENODEV; + goto out2; + } + + /* map parts of the PCI IO area */ + /* REVISIT: if this changes with a newer variant (doubt it) make this + * a platform resource. + */ + virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000); + if (!virt_io) { + dev_err(&pdev->dev, "cannot remap pci io space\n"); + ret = -ENODEV; + goto out3; + } + ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; + +#ifdef CONFIG_DMA_NONCOHERENT + /* Au1500 revisions older than AD have borked coherent PCI */ + if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && + (read_c0_prid() < 0x01030202)) { + val = __raw_readl(ctx->regs + PCI_REG_CONFIG); + val |= PCI_CONFIG_NC; + __raw_writel(val, ctx->regs + PCI_REG_CONFIG); + wmb(); + dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n"); + } +#endif + + if (pd->board_map_irq) + ctx->board_map_irq = pd->board_map_irq; + + if (pd->board_pci_idsel) + ctx->board_pci_idsel = pd->board_pci_idsel; + else + ctx->board_pci_idsel = alchemy_pci_def_idsel; + + /* fill in relevant pci_controller members */ + ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops; + ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres; + ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores; + + /* we can't ioremap the entire pci config space because it's too large, + * nor can we dynamically ioremap it because some drivers use the + * PCI config routines from within atomic contex and that becomes a + * problem in get_vm_area(). Instead we use one wired TLB entry to + * handle all config accesses for all busses. + */ + ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); + if (!ctx->pci_cfg_vm) { + dev_err(&pdev->dev, "unable to get vm area\n"); + ret = -ENOMEM; + goto out4; + } + alchemy_pci_wired_entry(ctx); + + /* the whole mips_io_port_base thing (x86-io on MIPS) really sucks + * golf balls through a garden hose. and doesn't even have the g-d + * common courtesy to give a reach-around. Gunnery Sgt. Hartman is + * not amused. The drivers which use IO ports without mapping them + * first suck even more. But I'd rather fix them than use this work- + * around. + */ + set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); + + /* board may want to modify bits in the config register, do it now */ + val = __raw_readl(ctx->regs + PCI_REG_CONFIG); + val &= ~pd->pci_cfg_clr; + val |= pd->pci_cfg_set; + __raw_writel(val, ctx->regs + PCI_REG_CONFIG); + wmb(); + + platform_set_drvdata(pdev, ctx); + register_pci_controller(&ctx->alchemy_pci_ctrl); + +#if 0 + /* the following must be uncommented if you DO NOT register the + * PCI controller in an arch_initcall()! Another thing that + * sucks. What if some lunatic develops an I2C-attached + * PCI controller that is connected to an I2C controller on + * a PCI device? We're screwed then! + */ + pcibios_scanbus(&ctx->alchemy_pci_ctrl); + pci_fixup_irqs(pci_common_swizzle, ctx->board_map_irq); +#endif + + return 0; + +out4: + iounmap(virt_io); +out3: + iounmap(ctx->regs); +out2: + release_mem_region(r->start, resource_size(r)); +out1: + kfree(ctx); +out: + return ret; +} + + +#ifdef CONFIG_PM +static int alchemy_pci_suspend(struct device *dev) +{ + /* hm, maybe delete the wired entry, but how? */ + return 0; +} + +/* the db1xxx reset code in YAMON writes zero to C0_wired, so we have to + * recreate our wired entry on resume. If your board code isn't based on YAMON: + * tough noogies!! + */ +static int alchemy_pci_resume(struct device *dev) +{ + struct alchemy_pci_context *ctx = dev_get_drvdata(dev); + alchemy_pci_wired_entry(ctx); + return 0; +} + +static const struct dev_pm_ops alchemy_pci_pmops = { + .suspend = alchemy_pci_suspend, + .resume = alchemy_pci_resume, +}; + +#define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops) + +#else +#define ALCHEMY_PCICTL_PM NULL +#endif + +static struct platform_driver alchemy_pcictl_driver = { + .probe = alchemy_pci_probe, + .driver = { + .name = "alchemy-pci", + .owner = THIS_MODULE, + .pm = ALCHEMY_PCICTL_PM, + }, +}; + +static int __init alchemy_pci_init(void) +{ + /* Au1500/Au1550 have PCI */ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1550: + return platform_driver_register(&alchemy_pcictl_driver); + } + return 0; +} +arch_initcall(alchemy_pci_init); + + +/* globals: die die die my darling, don't say a single word.. */ +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct alchemy_pci_context *ctx = dev->sysdata; + if (ctx && ctx->board_map_irq) + return ctx->board_map_irq(dev, slot, pin); + return -1; +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + /* + struct alchemy_pci_context *ctx = dev->sysdata; + if (ctx && ctx->board_pci_plat_dev_init) + return ctx->board_pci_plat_dev_init(dev); + */ + return 0; +} -- 1.7.6 From manuel.lauss@googlemail.com Tue Aug 2 19:51:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 19:58:18 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:34084 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491765Ab1HBRvq (ORCPT ); Tue, 2 Aug 2011 19:51:46 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so73231fxd.36 for ; Tue, 02 Aug 2011 10:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=bfS0p59ClCRzDeZg6BYo1dirdboGic4U+1DXV0QlAek=; b=PwrEAkS8wsxUSPaD7DZ1SrhIJwy9HvHAU8oI6h4RnJpu6/P993qEqqXqW3uFZM8E90 TJd6+b7qvI52t9U7b414Jv2+896WbA+weAo1aw2KAomORlRkQb6F18vgVs3VI4b0xLgQ r/RWdFuks5iZ6k5Rq7PyVSy8E7CTQEWxMsElY= Received: by 10.223.68.194 with SMTP id w2mr2898434fai.139.1312307506211; Tue, 02 Aug 2011 10:51:46 -0700 (PDT) Received: from localhost.localdomain (188-22-5-211.adsl.highway.telekom.at [188.22.5.211]) by mx.google.com with ESMTPS id r12sm3608450fam.24.2011.08.02.10.51.44 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Aug 2011 10:51:45 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 15/15] MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines Date: Tue, 2 Aug 2011 19:51:10 +0200 Message-Id: <1312307470-6841-16-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30811 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1628 Content-Length: 37567 Lines: 1295 Now that no driver any longer depends on the CONFIG_SOC_AU1??? symbols, it's time to get rid of them: Move some of the platform devices to the boards which can use them, Rename a few (unused) constants in the header, Replace them with MIPS_ALCHEMY in the various Kconfig files. Finally delete them altogether from the Alchemy Kconfig file. Signed-off-by: Manuel Lauss --- arch/mips/Kconfig | 2 + arch/mips/alchemy/Kconfig | 50 ++---- arch/mips/alchemy/common/platform.c | 175 +------------------ arch/mips/alchemy/devboards/db1200/platform.c | 78 ++++++++- arch/mips/alchemy/devboards/db1x00/board_setup.c | 4 +- arch/mips/alchemy/devboards/db1x00/platform.c | 32 ++++ arch/mips/alchemy/devboards/pb1100/platform.c | 29 +++ arch/mips/alchemy/devboards/pb1200/platform.c | 137 ++++++++++++++- arch/mips/alchemy/devboards/pb1500/platform.c | 1 + arch/mips/alchemy/devboards/pb1550/platform.c | 33 ++++ arch/mips/include/asm/mach-au1x00/au1000.h | 203 ++++++++++------------ drivers/i2c/busses/Kconfig | 2 +- drivers/ide/Kconfig | 6 +- drivers/mmc/host/Kconfig | 2 +- drivers/mtd/nand/Kconfig | 2 +- drivers/net/irda/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/usb/Kconfig | 1 - drivers/usb/host/ehci-hcd.c | 2 +- drivers/video/Kconfig | 4 +- sound/mips/Kconfig | 2 +- sound/soc/au1x/Kconfig | 2 +- 22 files changed, 423 insertions(+), 348 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 177cdaf..32e7e3c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -46,6 +46,8 @@ config MIPS_ALCHEMY select GENERIC_GPIO select ARCH_WANT_OPTIONAL_GPIOLIB select SYS_SUPPORTS_ZBOOT + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI config AR7 bool "Texas Instruments AR7" diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 2ccfd4a..2a68be6 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -18,20 +18,20 @@ config MIPS_MTX1 bool "4G Systems MTX-1 board" select DMA_NONCOHERENT select HW_HAS_PCI - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_BOSPORUS bool "Alchemy Bosporus board" - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_DB1000 bool "Alchemy DB1000 board" - select SOC_AU1000 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select SYS_SUPPORTS_LITTLE_ENDIAN @@ -39,14 +39,14 @@ config MIPS_DB1000 config MIPS_DB1100 bool "Alchemy DB1100 board" - select SOC_AU1100 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_DB1200 bool "Alchemy DB1200 board" - select SOC_AU1200 + select ALCHEMY_GPIOINT_AU1000 select DMA_COHERENT select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN @@ -54,7 +54,7 @@ config MIPS_DB1200 config MIPS_DB1500 bool "Alchemy DB1500 board" - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_DISABLE_OBSOLETE_IDE @@ -64,7 +64,7 @@ config MIPS_DB1500 config MIPS_DB1550 bool "Alchemy DB1550 board" - select SOC_AU1550 + select ALCHEMY_GPIOINT_AU1000 select HW_HAS_PCI select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE @@ -74,13 +74,13 @@ config MIPS_DB1550 config MIPS_MIRAGE bool "Alchemy Mirage board" select DMA_NONCOHERENT - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_PB1000 bool "Alchemy PB1000 board" - select SOC_AU1000 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select SWAP_IO_SPACE @@ -89,7 +89,7 @@ config MIPS_PB1000 config MIPS_PB1100 bool "Alchemy PB1100 board" - select SOC_AU1100 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select SWAP_IO_SPACE @@ -98,7 +98,7 @@ config MIPS_PB1100 config MIPS_PB1200 bool "Alchemy PB1200 board" - select SOC_AU1200 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN @@ -106,7 +106,7 @@ config MIPS_PB1200 config MIPS_PB1500 bool "Alchemy PB1500 board" - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select SYS_SUPPORTS_LITTLE_ENDIAN @@ -114,7 +114,7 @@ config MIPS_PB1500 config MIPS_PB1550 bool "Alchemy PB1550 board" - select SOC_AU1550 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_DISABLE_OBSOLETE_IDE @@ -124,13 +124,13 @@ config MIPS_PB1550 config MIPS_XXS1500 bool "MyCable XXS1500 board" select DMA_NONCOHERENT - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_GPR bool "Trapeze ITS GPR board" - select SOC_AU1550 + select ALCHEMY_GPIOINT_AU1000 select HW_HAS_PCI select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE @@ -138,23 +138,3 @@ config MIPS_GPR select SYS_HAS_EARLY_PRINTK endchoice - -config SOC_AU1000 - bool - select ALCHEMY_GPIOINT_AU1000 - -config SOC_AU1100 - bool - select ALCHEMY_GPIOINT_AU1000 - -config SOC_AU1500 - bool - select ALCHEMY_GPIOINT_AU1000 - -config SOC_AU1550 - bool - select ALCHEMY_GPIOINT_AU1000 - -config SOC_AU1200 - bool - select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 657ae27..c8e5d72 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -189,159 +189,6 @@ static void __init alchemy_setup_usb(int ctype) } } -/*** AU1100 LCD controller ***/ - -#ifdef CONFIG_FB_AU1100 -static struct resource au1100_lcd_resources[] = { - [0] = { - .start = AU1100_LCD_PHYS_ADDR, - .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1100_LCD_INT, - .end = AU1100_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1100_lcd_device = { - .name = "au1100-lcd", - .id = 0, - .dev = { - .dma_mask = &au1100_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1100_lcd_resources), - .resource = au1100_lcd_resources, -}; -#endif - -#ifdef CONFIG_SOC_AU1200 - -static struct resource au1200_lcd_resources[] = { - [0] = { - .start = AU1200_LCD_PHYS_ADDR, - .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_LCD_INT, - .end = AU1200_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1200_lcd_device = { - .name = "au1200-lcd", - .id = 0, - .dev = { - .dma_mask = &au1200_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1200_lcd_resources), - .resource = au1200_lcd_resources, -}; - -static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); - -extern struct au1xmmc_platform_data au1xmmc_platdata[2]; - -static struct resource au1200_mmc0_resources[] = { - [0] = { - .start = AU1100_SD0_PHYS_ADDR, - .end = AU1100_SD0_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_SDMS_TX0, - .end = AU1200_DSCR_CMD0_SDMS_TX0, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_SDMS_RX0, - .end = AU1200_DSCR_CMD0_SDMS_RX0, - .flags = IORESOURCE_DMA, - } -}; - -static struct platform_device au1200_mmc0_device = { - .name = "au1xxx-mmc", - .id = 0, - .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &au1xmmc_platdata[0], - }, - .num_resources = ARRAY_SIZE(au1200_mmc0_resources), - .resource = au1200_mmc0_resources, -}; - -#ifndef CONFIG_MIPS_DB1200 -static struct resource au1200_mmc1_resources[] = { - [0] = { - .start = AU1100_SD1_PHYS_ADDR, - .end = AU1100_SD1_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_SDMS_TX1, - .end = AU1200_DSCR_CMD0_SDMS_TX1, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_SDMS_RX1, - .end = AU1200_DSCR_CMD0_SDMS_RX1, - .flags = IORESOURCE_DMA, - } -}; - -static struct platform_device au1200_mmc1_device = { - .name = "au1xxx-mmc", - .id = 1, - .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &au1xmmc_platdata[1], - }, - .num_resources = ARRAY_SIZE(au1200_mmc1_resources), - .resource = au1200_mmc1_resources, -}; -#endif /* #ifndef CONFIG_MIPS_DB1200 */ -#endif /* #ifdef CONFIG_SOC_AU1200 */ - -/* All Alchemy demoboards with I2C have this #define in their headers */ -#ifdef SMBUS_PSC_BASE -static struct resource pbdb_smbus_resources[] = { - { - .start = SMBUS_PSC_BASE, - .end = SMBUS_PSC_BASE + 0xfff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device pbdb_smbus_device = { - .name = "au1xpsc_smbus", - .id = 0, /* bus number */ - .num_resources = ARRAY_SIZE(pbdb_smbus_resources), - .resource = pbdb_smbus_resources, -}; -#endif - /* Macro to help defining the Ethernet MAC resources */ #define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */ #define MAC_RES(_base, _enable, _irq, _macdma) \ @@ -503,33 +350,15 @@ static void __init alchemy_setup_macs(int ctype) } } -static struct platform_device *au1xxx_platform_devices[] __initdata = { -#ifdef CONFIG_FB_AU1100 - &au1100_lcd_device, -#endif -#ifdef CONFIG_SOC_AU1200 - &au1200_lcd_device, - &au1200_mmc0_device, -#ifndef CONFIG_MIPS_DB1200 - &au1200_mmc1_device, -#endif -#endif -#ifdef SMBUS_PSC_BASE - &pbdb_smbus_device, -#endif -}; - static int __init au1xxx_platform_init(void) { - int err, ctype = alchemy_get_cputype(); + int ctype = alchemy_get_cputype(); alchemy_setup_uarts(ctype); alchemy_setup_macs(ctype); alchemy_setup_usb(ctype); - err = platform_add_devices(au1xxx_platform_devices, - ARRAY_SIZE(au1xxx_platform_devices)); - return err; + return 0; } arch_initcall(au1xxx_platform_init); diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index 1bc16f0..aae08c1 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -333,15 +333,77 @@ static struct led_classdev db1200_mmc_led = { .brightness_set = db1200_mmcled_set, }; -/* needed by arch/mips/alchemy/common/platform.c */ -struct au1xmmc_platform_data au1xmmc_platdata[] = { +static struct au1xmmc_platform_data db1200mmc_platdata = { + .cd_setup = db1200_mmc_cd_setup, + .set_power = db1200_mmc_set_power, + .card_inserted = db1200_mmc_card_inserted, + .card_readonly = db1200_mmc_card_readonly, + .led = &db1200_mmc_led, +}; + +static struct resource au1200_mmc0_resources[] = { + [0] = { + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_SDMS_TX0, + .end = AU1200_DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_SDMS_RX0, + .end = AU1200_DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); + +static struct platform_device db1200_mmc0_dev = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1200mmc_platdata, + }, + .num_resources = ARRAY_SIZE(au1200_mmc0_resources), + .resource = au1200_mmc0_resources, +}; + +/**********************************************************************/ + +static struct resource au1200_lcd_res[] = { [0] = { - .cd_setup = db1200_mmc_cd_setup, - .set_power = db1200_mmc_set_power, - .card_inserted = db1200_mmc_card_inserted, - .card_readonly = db1200_mmc_card_readonly, - .led = &db1200_mmc_led, + .start = AU1200_LCD_PHYS_ADDR, + .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_LCD_INT, + .end = AU1200_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1200_lcd_dev = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1200_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), }, + .num_resources = ARRAY_SIZE(au1200_lcd_res), + .resource = au1200_lcd_res, }; /**********************************************************************/ @@ -442,6 +504,8 @@ static struct platform_device db1200_stac_dev = { static struct platform_device *db1200_devs[] __initdata = { NULL, /* PSC0, selected by S6.8 */ &db1200_ide_dev, + &db1200_mmc0_dev, + &au1200_lcd_dev, &db1200_eth_dev, &db1200_rtc_dev, &db1200_nand_dev, diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 2b2178f..7cd36e6 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -134,9 +134,7 @@ void __init board_setup(void) /* initialize board register space */ bcsr_init(bcsr1, bcsr2); - /* Not valid for Au1550 */ -#if defined(CONFIG_IRDA) && \ - (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100)) +#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) { u32 pin_func; diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 990367f..8704865 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -19,6 +19,7 @@ */ #include +#include #include #include @@ -208,6 +209,34 @@ static int __init db15x0_pci_init(void) arch_initcall(db15x0_pci_init); #endif +#ifdef CONFIG_MIPS_DB1100 +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; +#endif + static int __init db1xxx_dev_init(void) { #ifdef DB1XXX_HAS_PCMCIA @@ -231,6 +260,9 @@ static int __init db1xxx_dev_init(void) DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); #endif +#ifdef CONFIG_MIPS_DB1100 + platform_device_register(&au1100_lcd_device); +#endif db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); return 0; } diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c index 8a4e733..9c57c01 100644 --- a/arch/mips/alchemy/devboards/pb1100/platform.c +++ b/arch/mips/alchemy/devboards/pb1100/platform.c @@ -19,12 +19,40 @@ */ #include +#include +#include #include #include #include "../platform.h" +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; + static int __init pb1100_dev_init(void) { int swapped; @@ -42,6 +70,7 @@ static int __init pb1100_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + platform_device_register(&au1100_lcd_device); return 0; } diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index d7915b0..54f7f7b 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -90,7 +90,7 @@ static int pb1200mmc1_card_inserted(void *mmc_host) return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; } -const struct au1xmmc_platform_data au1xmmc_platdata[2] = { +static struct au1xmmc_platform_data pb1200mmc_platdata[2] = { [0] = { .set_power = pb1200mmc0_set_power, .card_inserted = pb1200mmc0_card_inserted, @@ -107,6 +107,79 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = { }, }; +static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); + +static struct resource au1200_mmc0_res[] = { + [0] = { + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_SDMS_TX0, + .end = AU1200_DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_SDMS_RX0, + .end = AU1200_DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device pb1200_mmc0_dev = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &pb1200mmc_platdata[0], + }, + .num_resources = ARRAY_SIZE(au1200_mmc0_res), + .resource = au1200_mmc0_res, +}; + +static struct resource au1200_mmc1_res[] = { + [0] = { + .start = AU1100_SD1_PHYS_ADDR, + .end = AU1100_SD1_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_SDMS_TX1, + .end = AU1200_DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_SDMS_RX1, + .end = AU1200_DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device pb1200_mmc1_dev = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &pb1200mmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1200_mmc1_res), + .resource = au1200_mmc1_res, +}; + + static struct resource ide_resources[] = { [0] = { .start = IDE_PHYS_ADDR, @@ -168,9 +241,69 @@ static struct platform_device smc91c111_device = { .resource = smc91c111_resources }; +static struct resource au1200_psc0_res[] = { + [0] = { + .start = AU1550_PSC0_PHYS_ADDR, + .end = AU1550_PSC0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_PSC0_INT, + .end = AU1200_PSC0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_PSC0_TX, + .end = AU1200_DSCR_CMD0_PSC0_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_PSC0_RX, + .end = AU1200_DSCR_CMD0_PSC0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device pb1200_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1200_psc0_res), + .resource = au1200_psc0_res, +}; + +static struct resource au1200_lcd_res[] = { + [0] = { + .start = AU1200_LCD_PHYS_ADDR, + .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_LCD_INT, + .end = AU1200_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1200_lcd_dev = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1200_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1200_lcd_res), + .resource = au1200_lcd_res, +}; + static struct platform_device *board_platform_devices[] __initdata = { &ide_device, - &smc91c111_device + &smc91c111_device, + &pb1200_i2c_dev, + &pb1200_mmc0_dev, + &pb1200_mmc1_dev, + &au1200_lcd_dev, }; static int __init board_register_devices(void) diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c index 9f0b5a0..1e52a01 100644 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c index 0c5711f..a4604b8 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -18,9 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include +#include #include #include @@ -69,6 +71,36 @@ static struct platform_device pb1550_pci_host = { .resource = alchemy_pci_host_res, }; +static struct resource au1550_psc2_res[] = { + [0] = { + .start = AU1550_PSC2_PHYS_ADDR, + .end = AU1550_PSC2_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC2_INT, + .end = AU1550_PSC2_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC2_TX, + .end = AU1550_DSCR_CMD0_PSC2_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC2_RX, + .end = AU1550_DSCR_CMD0_PSC2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device pb1550_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1550_psc2_res), + .resource = au1550_psc2_res, +}; + static int __init pb1550_dev_init(void) { int swapped; @@ -101,6 +133,7 @@ static int __init pb1550_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 4, swapped); platform_device_register(&pb1550_pci_host); + platform_device_register(&pb1550_i2c_dev); return 0; } diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 5da2fd7..4afc3a9 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -592,113 +592,6 @@ enum soc_au1200_ints { #endif /* !defined (_LANGUAGE_ASSEMBLY) */ /* - * SDRAM register offsets - */ -#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ - defined(CONFIG_SOC_AU1100) -#define MEM_SDMODE0 0x0000 -#define MEM_SDMODE1 0x0004 -#define MEM_SDMODE2 0x0008 -#define MEM_SDADDR0 0x000C -#define MEM_SDADDR1 0x0010 -#define MEM_SDADDR2 0x0014 -#define MEM_SDREFCFG 0x0018 -#define MEM_SDPRECMD 0x001C -#define MEM_SDAUTOREF 0x0020 -#define MEM_SDWRMD0 0x0024 -#define MEM_SDWRMD1 0x0028 -#define MEM_SDWRMD2 0x002C -#define MEM_SDSLEEP 0x0030 -#define MEM_SDSMCKE 0x0034 - -/* - * MEM_SDMODE register content definitions - */ -#define MEM_SDMODE_F (1 << 22) -#define MEM_SDMODE_SR (1 << 21) -#define MEM_SDMODE_BS (1 << 20) -#define MEM_SDMODE_RS (3 << 18) -#define MEM_SDMODE_CS (7 << 15) -#define MEM_SDMODE_TRAS (15 << 11) -#define MEM_SDMODE_TMRD (3 << 9) -#define MEM_SDMODE_TWR (3 << 7) -#define MEM_SDMODE_TRP (3 << 5) -#define MEM_SDMODE_TRCD (3 << 3) -#define MEM_SDMODE_TCL (7 << 0) - -#define MEM_SDMODE_BS_2Bank (0 << 20) -#define MEM_SDMODE_BS_4Bank (1 << 20) -#define MEM_SDMODE_RS_11Row (0 << 18) -#define MEM_SDMODE_RS_12Row (1 << 18) -#define MEM_SDMODE_RS_13Row (2 << 18) -#define MEM_SDMODE_RS_N(N) ((N) << 18) -#define MEM_SDMODE_CS_7Col (0 << 15) -#define MEM_SDMODE_CS_8Col (1 << 15) -#define MEM_SDMODE_CS_9Col (2 << 15) -#define MEM_SDMODE_CS_10Col (3 << 15) -#define MEM_SDMODE_CS_11Col (4 << 15) -#define MEM_SDMODE_CS_N(N) ((N) << 15) -#define MEM_SDMODE_TRAS_N(N) ((N) << 11) -#define MEM_SDMODE_TMRD_N(N) ((N) << 9) -#define MEM_SDMODE_TWR_N(N) ((N) << 7) -#define MEM_SDMODE_TRP_N(N) ((N) << 5) -#define MEM_SDMODE_TRCD_N(N) ((N) << 3) -#define MEM_SDMODE_TCL_N(N) ((N) << 0) - -/* - * MEM_SDADDR register contents definitions - */ -#define MEM_SDADDR_E (1 << 20) -#define MEM_SDADDR_CSBA (0x03FF << 10) -#define MEM_SDADDR_CSMASK (0x03FF << 0) -#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) -#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) - -/* - * MEM_SDREFCFG register content definitions - */ -#define MEM_SDREFCFG_TRC (15 << 28) -#define MEM_SDREFCFG_TRPM (3 << 26) -#define MEM_SDREFCFG_E (1 << 25) -#define MEM_SDREFCFG_RE (0x1ffffff << 0) -#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) -#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) -#define MEM_SDREFCFG_REF_N(N) (N) -#endif - -/***********************************************************************/ - -/* - * Au1550 SDRAM Register Offsets - */ - -/***********************************************************************/ - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#define MEM_SDMODE0 0x0800 -#define MEM_SDMODE1 0x0808 -#define MEM_SDMODE2 0x0810 -#define MEM_SDADDR0 0x0820 -#define MEM_SDADDR1 0x0828 -#define MEM_SDADDR2 0x0830 -#define MEM_SDCONFIGA 0x0840 -#define MEM_SDCONFIGB 0x0848 -#define MEM_SDSTAT 0x0850 -#define MEM_SDERRADDR 0x0858 -#define MEM_SDSTRIDE0 0x0860 -#define MEM_SDSTRIDE1 0x0868 -#define MEM_SDSTRIDE2 0x0870 -#define MEM_SDWRMD0 0x0880 -#define MEM_SDWRMD1 0x0888 -#define MEM_SDWRMD2 0x0890 -#define MEM_SDPRECMD 0x08C0 -#define MEM_SDAUTOREF 0x08C8 -#define MEM_SDSREF 0x08D0 -#define MEM_SDSLEEP MEM_SDSREF - -#endif - -/* * Physical base addresses for integrated peripherals * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 */ @@ -761,6 +654,92 @@ enum soc_au1200_ints { #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ +/* Au1000 SDRAM memory controller register offsets */ +#define AU1000_MEM_SDMODE0 0x0000 +#define AU1000_MEM_SDMODE1 0x0004 +#define AU1000_MEM_SDMODE2 0x0008 +#define AU1000_MEM_SDADDR0 0x000C +#define AU1000_MEM_SDADDR1 0x0010 +#define AU1000_MEM_SDADDR2 0x0014 +#define AU1000_MEM_SDREFCFG 0x0018 +#define AU1000_MEM_SDPRECMD 0x001C +#define AU1000_MEM_SDAUTOREF 0x0020 +#define AU1000_MEM_SDWRMD0 0x0024 +#define AU1000_MEM_SDWRMD1 0x0028 +#define AU1000_MEM_SDWRMD2 0x002C +#define AU1000_MEM_SDSLEEP 0x0030 +#define AU1000_MEM_SDSMCKE 0x0034 + +/* MEM_SDMODE register content definitions */ +#define MEM_SDMODE_F (1 << 22) +#define MEM_SDMODE_SR (1 << 21) +#define MEM_SDMODE_BS (1 << 20) +#define MEM_SDMODE_RS (3 << 18) +#define MEM_SDMODE_CS (7 << 15) +#define MEM_SDMODE_TRAS (15 << 11) +#define MEM_SDMODE_TMRD (3 << 9) +#define MEM_SDMODE_TWR (3 << 7) +#define MEM_SDMODE_TRP (3 << 5) +#define MEM_SDMODE_TRCD (3 << 3) +#define MEM_SDMODE_TCL (7 << 0) + +#define MEM_SDMODE_BS_2Bank (0 << 20) +#define MEM_SDMODE_BS_4Bank (1 << 20) +#define MEM_SDMODE_RS_11Row (0 << 18) +#define MEM_SDMODE_RS_12Row (1 << 18) +#define MEM_SDMODE_RS_13Row (2 << 18) +#define MEM_SDMODE_RS_N(N) ((N) << 18) +#define MEM_SDMODE_CS_7Col (0 << 15) +#define MEM_SDMODE_CS_8Col (1 << 15) +#define MEM_SDMODE_CS_9Col (2 << 15) +#define MEM_SDMODE_CS_10Col (3 << 15) +#define MEM_SDMODE_CS_11Col (4 << 15) +#define MEM_SDMODE_CS_N(N) ((N) << 15) +#define MEM_SDMODE_TRAS_N(N) ((N) << 11) +#define MEM_SDMODE_TMRD_N(N) ((N) << 9) +#define MEM_SDMODE_TWR_N(N) ((N) << 7) +#define MEM_SDMODE_TRP_N(N) ((N) << 5) +#define MEM_SDMODE_TRCD_N(N) ((N) << 3) +#define MEM_SDMODE_TCL_N(N) ((N) << 0) + +/* MEM_SDADDR register contents definitions */ +#define MEM_SDADDR_E (1 << 20) +#define MEM_SDADDR_CSBA (0x03FF << 10) +#define MEM_SDADDR_CSMASK (0x03FF << 0) +#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) +#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) + +/* MEM_SDREFCFG register content definitions */ +#define MEM_SDREFCFG_TRC (15 << 28) +#define MEM_SDREFCFG_TRPM (3 << 26) +#define MEM_SDREFCFG_E (1 << 25) +#define MEM_SDREFCFG_RE (0x1ffffff << 0) +#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) +#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) +#define MEM_SDREFCFG_REF_N(N) (N) + +/* Au1550 SDRAM Register Offsets */ +#define AU1550_MEM_SDMODE0 0x0800 +#define AU1550_MEM_SDMODE1 0x0808 +#define AU1550_MEM_SDMODE2 0x0810 +#define AU1550_MEM_SDADDR0 0x0820 +#define AU1550_MEM_SDADDR1 0x0828 +#define AU1550_MEM_SDADDR2 0x0830 +#define AU1550_MEM_SDCONFIGA 0x0840 +#define AU1550_MEM_SDCONFIGB 0x0848 +#define AU1550_MEM_SDSTAT 0x0850 +#define AU1550_MEM_SDERRADDR 0x0858 +#define AU1550_MEM_SDSTRIDE0 0x0860 +#define AU1550_MEM_SDSTRIDE1 0x0868 +#define AU1550_MEM_SDSTRIDE2 0x0870 +#define AU1550_MEM_SDWRMD0 0x0880 +#define AU1550_MEM_SDWRMD1 0x0888 +#define AU1550_MEM_SDWRMD2 0x0890 +#define AU1550_MEM_SDPRECMD 0x08C0 +#define AU1550_MEM_SDAUTOREF 0x08C8 +#define AU1550_MEM_SDSREF 0x08D0 +#define AU1550_MEM_SDSLEEP MEM_SDSREF + /* Static Bus Controller */ #define MEM_STCFG0 0xB4001000 #define MEM_STTIME0 0xB4001004 @@ -778,14 +757,12 @@ enum soc_au1200_ints { #define MEM_STTIME3 0xB4001034 #define MEM_STADDR3 0xB4001038 -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) #define MEM_STNDCTL 0xB4001100 #define MEM_STSTAT 0xB4001104 #define MEM_STNAND_CMD 0x0 #define MEM_STNAND_ADDR 0x4 #define MEM_STNAND_DATA 0x20 -#endif /* Programmable Counters 0 and 1 */ @@ -1172,7 +1149,6 @@ enum soc_au1200_ints { # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) /* Au1200 only */ -#ifdef CONFIG_SOC_AU1200 #define SYS_PINFUNC_DMA (1 << 31) #define SYS_PINFUNC_S0A (1 << 30) #define SYS_PINFUNC_S1A (1 << 29) @@ -1200,7 +1176,6 @@ enum soc_au1200_ints { #define SYS_PINFUNC_P0B (1 << 4) #define SYS_PINFUNC_U0T (1 << 3) #define SYS_PINFUNC_S1B (1 << 2) -#endif /* Power Management */ #define SYS_SCRATCH0 0xB1900018 @@ -1256,12 +1231,12 @@ enum soc_au1200_ints { # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) # define SYS_CS_DI2 (1 << 16) # define SYS_CS_CI2 (1 << 15) -#ifdef CONFIG_SOC_AU1100 + # define SYS_CS_ML_BIT 7 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) # define SYS_CS_DL (1 << 6) # define SYS_CS_CL (1 << 5) -#else + # define SYS_CS_MUH_BIT 12 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) # define SYS_CS_DUH (1 << 11) @@ -1270,7 +1245,7 @@ enum soc_au1200_ints { # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) # define SYS_CS_DUD (1 << 6) # define SYS_CS_CUD (1 << 5) -#endif + # define SYS_CS_MIR_BIT 2 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) # define SYS_CS_DIR (1 << 1) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 646068e..1908195 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -301,7 +301,7 @@ config I2C_AT91 config I2C_AU1550 tristate "Au1550/Au1200 SMBus interface" - depends on SOC_AU1550 || SOC_AU1200 + depends on MIPS_ALCHEMY help If you say yes to this option, support will be included for the Au1550 and Au1200 SMBus interface. diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index 9827c5e..ec42e6c 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig @@ -677,19 +677,19 @@ config BLK_DEV_IDE_PMAC_ATA100FIRST config BLK_DEV_IDE_AU1XXX bool "IDE for AMD Alchemy Au1200" - depends on SOC_AU1200 + depends on MIPS_ALCHEMY select IDE_XFER_MODE choice prompt "IDE Mode for AMD Alchemy Au1200" default CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA - depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX + depends on BLK_DEV_IDE_AU1XXX config BLK_DEV_IDE_AU1XXX_PIO_DBDMA bool "PIO+DbDMA IDE for AMD Alchemy Au1200" config BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA bool "MDMA2+DbDMA IDE for AMD Alchemy Au1200" - depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX + depends on BLK_DEV_IDE_AU1XXX endchoice config BLK_DEV_IDE_TX4938 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 8c87096..6d74f49 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -263,7 +263,7 @@ config MMC_WBSD config MMC_AU1X tristate "Alchemy AU1XX0 MMC Card Interface support" - depends on SOC_AU1200 + depends on MIPS_ALCHEMY help This selects the AMD Alchemy(R) Multimedia card interface. If you have a Alchemy platform with a MMC slot, say Y or M here. diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 4c34252..dbfa0f7 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -138,7 +138,7 @@ config MTD_NAND_RICOH config MTD_NAND_AU1550 tristate "Au1550/1200 NAND support" - depends on SOC_AU1200 || SOC_AU1550 + depends on MIPS_ALCHEMY help This enables the driver for the NAND flash controller on the AMD/Alchemy 1550 SOC. diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig index 25bb2a0..0cda6c4 100644 --- a/drivers/net/irda/Kconfig +++ b/drivers/net/irda/Kconfig @@ -314,7 +314,7 @@ config TOSHIBA_FIR config AU1000_FIR tristate "Alchemy Au1000 SIR/FIR" - depends on SOC_AU1000 && IRDA + depends on IRDA && MIPS_ALCHEMY config SMC_IRCC_FIR tristate "SMSC IrCC (EXPERIMENTAL)" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 52e2900..a1fd73d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -88,7 +88,7 @@ config SPI_BFIN_SPORT config SPI_AU1550 tristate "Au1550/Au12x0 SPI Controller" - depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL + depends on MIPS_ALCHEMY && EXPERIMENTAL select SPI_BITBANG help If you say yes to this option, support will be included for the diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 48f1781..85d5a01 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -56,7 +56,6 @@ config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx default y if PPC_MPC512x - default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 default y if ARCH_AT91SAM9G45 diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index f72ae0b..47aa22d 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1196,7 +1196,7 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_hcd_sh_driver #endif -#ifdef CONFIG_SOC_AU1200 +#ifdef CONFIG_MIPS_ALCHEMY #include "ehci-au1xxx.c" #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver #endif diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 549b960..55a7df4 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1744,7 +1744,7 @@ endchoice config FB_AU1100 bool "Au1100 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1100 + depends on (FB = y) && MIPS_ALCHEMY select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -1755,7 +1755,7 @@ config FB_AU1100 config FB_AU1200 bool "Au1200 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1200 + depends on (FB = y) && MIPS_ALCHEMY select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT diff --git a/sound/mips/Kconfig b/sound/mips/Kconfig index a9823fa..0a0d501 100644 --- a/sound/mips/Kconfig +++ b/sound/mips/Kconfig @@ -24,7 +24,7 @@ config SND_SGI_HAL2 config SND_AU1X00 tristate "Au1x00 AC97 Port Driver" - depends on SOC_AU1000 || SOC_AU1100 || SOC_AU1500 + depends on MIPS_ALCHEMY select SND_PCM select SND_AC97_CODEC help diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index 4b67140..606039f 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -3,7 +3,7 @@ ## config SND_SOC_AU1XPSC tristate "SoC Audio for Au1200/Au1250/Au1550" - depends on SOC_AU1200 || SOC_AU1550 + depends on MIPS_ALCHEMY help This option enables support for the Programmable Serial Controllers in AC97 and I2S mode, and the Descriptor-Based DMA -- 1.7.6 From ralf@linux-mips.org Tue Aug 2 20:02:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 20:02:04 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:50531 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491200Ab1HBSCA (ORCPT ); Tue, 2 Aug 2011 20:02:00 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p72I1uLN002661; Tue, 2 Aug 2011 19:01:56 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p72I1uXx002659; Tue, 2 Aug 2011 19:01:56 +0100 Date: Tue, 2 Aug 2011 19:01:56 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 01/15] MIPS: Alchemy: fix typo in MAC0 registration Message-ID: <20110802180156.GA1718@linux-mips.org> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> <1312307470-6841-2-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1312307470-6841-2-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30812 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1632 Content-Length: 180 Lines: 8 On Tue, Aug 02, 2011 at 07:50:56PM +0200, Manuel Lauss wrote: > Harmless typo which prints an error message although MAC0 was > registered successfully. Thanks, applied. Ralf From ralf@linux-mips.org Tue Aug 2 20:11:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 20:11:10 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58612 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491200Ab1HBSLH (ORCPT ); Tue, 2 Aug 2011 20:11:07 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p72IB4DJ003598; Tue, 2 Aug 2011 19:11:04 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p72IB4tL003597; Tue, 2 Aug 2011 19:11:04 +0100 Date: Tue, 2 Aug 2011 19:11:04 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 03/15] MIPS: Alchemy: include Au1100 in PM code. Message-ID: <20110802181104.GA2842@linux-mips.org> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> <1312307470-6841-4-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1312307470-6841-4-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30813 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1642 Content-Length: 250 Lines: 10 On Tue, Aug 02, 2011 at 07:50:58PM +0200, Manuel Lauss wrote: > The current code forgets the Au1100 when looking for the > correct method to suspend the chip. > > Signed-off-by: Manuel Lauss Applied. Thanks! Ralf From ralf@linux-mips.org Tue Aug 2 21:23:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 21:23:10 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42520 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491192Ab1HBTXH (ORCPT ); Tue, 2 Aug 2011 21:23:07 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p72JN44s016030; Tue, 2 Aug 2011 20:23:04 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p72JN3QI016029; Tue, 2 Aug 2011 20:23:03 +0100 Date: Tue, 2 Aug 2011 20:23:03 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 02/15] net: au1000_eth: pass MACDMA address through platform resource info. Message-ID: <20110802192303.GA15961@linux-mips.org> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> <1312307470-6841-3-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1312307470-6841-3-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30814 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1685 Content-Length: 556 Lines: 15 On Tue, Aug 02, 2011 at 07:50:57PM +0200, Manuel Lauss wrote: > This patch removes the last hardcoded base address from the au1000_eth > driver. The base address of the MACDMA unit was derived from the > platform device id; if someone registered the MACs in inverse order > both would not work. > So instead pass the base address of the DMA unit to the driver with > the other platform resource information. > > Signed-off-by: Manuel Lauss > Acked-by: David S. Miller Thanks, queued for 3.2. Ralf From ralf@linux-mips.org Tue Aug 2 21:32:01 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 21:32:05 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40107 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491192Ab1HBTcB (ORCPT ); Tue, 2 Aug 2011 21:32:01 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p72JVxLj017058; Tue, 2 Aug 2011 20:31:59 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p72JVxtJ017050; Tue, 2 Aug 2011 20:31:59 +0100 Date: Tue, 2 Aug 2011 20:31:59 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 13/15] MIPS: remove __init from add_wired_entry() Message-ID: <20110802193159.GB15961@linux-mips.org> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> <1312307470-6841-14-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1312307470-6841-14-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30815 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1690 Content-Length: 269 Lines: 8 On Tue, Aug 02, 2011 at 07:51:08PM +0200, Manuel Lauss wrote: > For Alchemy-PCI I need to add a wired entry after resuming from RAM; > remove the __init from add_wired_entry() so that this actually works. This is needed for -stable and 3.1 as well, I assume? Ralf From manuel.lauss@googlemail.com Tue Aug 2 21:35:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Aug 2011 21:35:57 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:43830 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491192Ab1HBTfv (ORCPT ); Tue, 2 Aug 2011 21:35:51 +0200 Received: by yxj20 with SMTP id 20so73713yxj.36 for ; Tue, 02 Aug 2011 12:35:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=MAaxV2IZ2j3KN7XOF/1Z9z+QFSFyLEHl/A6ymZn30TY=; b=wvAVRHBJYLIqMkHr8aUpeC8VGsVAwVJ3fss+jiRQB12UNf24ngaQF4LLeKU6cqnJdy Sm5YUlvEf4wrYui5A8s3WT+vM77AOhun7ZLmsAWSNoGfYC9/T/IxrzQuiy+2kj/Rnnpp Qo3i7LDfjd6TeMw+/8ID4vPunM7licm+FxF2Q= MIME-Version: 1.0 Received: by 10.236.187.1 with SMTP id x1mr4608560yhm.358.1312313744774; Tue, 02 Aug 2011 12:35:44 -0700 (PDT) Received: by 10.236.103.172 with HTTP; Tue, 2 Aug 2011 12:35:44 -0700 (PDT) In-Reply-To: <20110802193159.GB15961@linux-mips.org> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> <1312307470-6841-14-git-send-email-manuel.lauss@googlemail.com> <20110802193159.GB15961@linux-mips.org> Date: Tue, 2 Aug 2011 21:35:44 +0200 Message-ID: Subject: Re: [PATCH 13/15] MIPS: remove __init from add_wired_entry() From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS Content-Type: multipart/alternative; boundary=20cf305e255197573c04a98ada3a X-archive-position: 30816 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1694 Content-Length: 1353 Lines: 32 --20cf305e255197573c04a98ada3a Content-Type: text/plain; charset=ISO-8859-1 On Tuesday, August 2, 2011, Ralf Baechle wrote: > On Tue, Aug 02, 2011 at 07:51:08PM +0200, Manuel Lauss wrote: > >> For Alchemy-PCI I need to add a wired entry after resuming from RAM; >> remove the __init from add_wired_entry() so that this actually works. > > This is needed for -stable and 3.1 as well, I assume? no, no. The patch following this one needs it, although the problem itself (missing wired entry after resume) has been here since the beginning. Manuel --20cf305e255197573c04a98ada3a Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable

On Tuesday, August 2, 2011, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Tue, Aug 02,= 2011 at 07:51:08PM +0200, Manuel Lauss wrote:
>
>> For Alch= emy-PCI I need to add a wired entry after resuming from RAM;
>> remove the __init from add_wired_entry() so that this actually wor= ks.
>
> This is needed for -stable and 3.1 as well, I assume?
no, no. =A0The patch following this one needs it,
although the pro= blem itself (missing wired entry
after resume) has been here since the beginning.

Manuel --20cf305e255197573c04a98ada3a-- From ralf@linux-mips.org Wed Aug 3 02:17:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 02:17:30 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51737 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491753Ab1HCAR1 (ORCPT ); Wed, 3 Aug 2011 02:17:27 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p730HHP7002444; Wed, 3 Aug 2011 01:17:18 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p730HGWI002441; Wed, 3 Aug 2011 01:17:16 +0100 Date: Wed, 3 Aug 2011 01:17:16 +0100 From: Ralf Baechle To: Ganesan Ramalingam Cc: linux-kernel@vger.kernel.org, David Daney , linux-mips@linux-mips.org Subject: Re: Compilation error on linux-mips git Message-ID: <20110803001716.GA2369@linux-mips.org> References: <20110727134737.GA8930@linux-mips.org> <20110727202733.GA10842@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110727202733.GA10842@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30817 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1873 Content-Length: 160 Lines: 6 On Wed, Jul 27, 2011 at 09:27:33PM +0100, Ralf Baechle wrote: I've just pushed a fix into the linux-mips git repo. Could you give it a spin? Thanks, Ralf From ganesan18@gmail.com Wed Aug 3 13:27:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 13:27:51 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:51210 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491059Ab1HCL1p (ORCPT ); Wed, 3 Aug 2011 13:27:45 +0200 Received: by fxd20 with SMTP id 20so1063627fxd.36 for ; Wed, 03 Aug 2011 04:27:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=P21RSN9bEtpcWa/JlfRwqmdTaCSHEtKieYc7B4wAyX8=; b=LusbM007HCQlzu6fYP+HSP1NHBlqeURDBP9kXO4aCN3eF/4ujsKPfSLIhFuV9LJgjt VilfjYz9zfYXWXWkQ0gpjKwaeBV0Z2T6foeT9qqhcpyMgTIj7rMO/7hRkq3yzwQm8HDU CtFIUfpCmMoMOriFN0dmlJrI9rI/JK9lacErM= Received: by 10.223.160.75 with SMTP id m11mr1041805fax.42.1312370860094; Wed, 03 Aug 2011 04:27:40 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.93.141 with HTTP; Wed, 3 Aug 2011 04:27:20 -0700 (PDT) In-Reply-To: <20110803001716.GA2369@linux-mips.org> References: <20110727134737.GA8930@linux-mips.org> <20110727202733.GA10842@linux-mips.org> <20110803001716.GA2369@linux-mips.org> From: Ganesan Ramalingam Date: Wed, 3 Aug 2011 16:57:20 +0530 Message-ID: Subject: Re: Compilation error on linux-mips git To: Ralf Baechle Cc: linux-kernel@vger.kernel.org, David Daney , linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=002354186d88edf4a404a99826c5 X-archive-position: 30818 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ganesan18@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2257 Content-Length: 1182 Lines: 38 --002354186d88edf4a404a99826c5 Content-Type: text/plain; charset=ISO-8859-1 Thanks, Compilation went through. Ganesan Ramalingam On Wed, Aug 3, 2011 at 5:47 AM, Ralf Baechle wrote: > On Wed, Jul 27, 2011 at 09:27:33PM +0100, Ralf Baechle wrote: > > I've just pushed a fix into the linux-mips git repo. Could you give it > a spin? Thanks, > > Ralf > --002354186d88edf4a404a99826c5 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Thanks,=A0Compilation went through.=A0

Ganesa= n Ramalingam

On Wed, Aug 3, 2011 at 5:47 = AM, Ralf Baechle <ralf@linux-mips.org> wrote:
On Wed, Jul 27, 2011 at 09:27:33PM +0100, R= alf Baechle wrote:

I've just pushed a fix into the linux-mips git repo. =A0Could you give = it
a spin? =A0Thanks,

=A0Ralf

--002354186d88edf4a404a99826c5-- From ralf@linux-mips.org Wed Aug 3 14:06:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 14:06:33 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46797 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491046Ab1HCMG3 (ORCPT ); Wed, 3 Aug 2011 14:06:29 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p73C6R18003223; Wed, 3 Aug 2011 13:06:28 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p73C6RhS003222; Wed, 3 Aug 2011 13:06:27 +0100 Date: Wed, 3 Aug 2011 13:06:27 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , linux-mmc@vger.kernel.org Subject: Re: [PATCH 12/15] MMC: au1xmmc: remove Alchemy CPU subtype dependencies Message-ID: <20110803120627.GA856@linux-mips.org> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> <1312307470-6841-13-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1312307470-6841-13-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30819 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2278 Content-Length: 447 Lines: 15 On Tue, Aug 02, 2011 at 07:51:07PM +0200, Manuel Lauss wrote: > Replace all occurrences of CONFIG_SOC_AU1??? with runtime feature > detection. > > Cc: > Signed-off-by: Manuel Lauss > --- > I'd like for this patch to go in via the mips tree since a few more depend > on it. Patch is looking ok. Since MMC is orphaned I've just queued it and it will go to linux-next after -rc1. Ralf From ralf@linux-mips.org Wed Aug 3 14:44:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 14:44:43 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56680 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491079Ab1HCMoj (ORCPT ); Wed, 3 Aug 2011 14:44:39 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p73CiafA004650; Wed, 3 Aug 2011 13:44:36 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p73CiaJS004648; Wed, 3 Aug 2011 13:44:36 +0100 Date: Wed, 3 Aug 2011 13:44:36 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 07/15] MIPS: Alchemy: always build power code Message-ID: <20110803124436.GA3978@linux-mips.org> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> <1312307470-6841-8-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1312307470-6841-8-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30820 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2293 Content-Length: 651 Lines: 25 On Tue, Aug 02, 2011 at 07:51:02PM +0200, Manuel Lauss wrote: > Date: Tue, 2 Aug 2011 19:51:02 +0200 > From: Manuel Lauss > To: Linux-MIPS , Ralf Baechle > > Cc: Manuel Lauss > Subject: [PATCH 07/15] MIPS: Alchemy: always build power code > > No reason NOT to build it Freely after Monthy Python ... Every byte is sacred. Every byte is great. If a byte is wasted, God gets quite irate. But I really wonder why compilation of this file wasn't controlled by something like obj-$(CONFIG_PM) += power.o Anyway, applied. Ralf From ralf@linux-mips.org Wed Aug 3 14:45:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 14:45:51 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51362 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491079Ab1HCMps (ORCPT ); Wed, 3 Aug 2011 14:45:48 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p73CjkuV004992; Wed, 3 Aug 2011 13:45:46 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p73Cjkom004990; Wed, 3 Aug 2011 13:45:46 +0100 Date: Wed, 3 Aug 2011 13:45:46 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 08/15] MIPS: Alchemy: support multiple GPIO styles in one kernel Message-ID: <20110803124546.GB3978@linux-mips.org> References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> <1312307470-6841-9-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1312307470-6841-9-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30821 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2295 Content-Length: 95 Lines: 5 On Tue, Aug 02, 2011 at 07:51:03PM +0200, Manuel Lauss wrote: Queue for 3.2. Thanks, Ralf From ralf@linux-mips.org Wed Aug 3 16:37:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 16:37:37 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33190 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491162Ab1HCOhe (ORCPT ); Wed, 3 Aug 2011 16:37:34 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p73EbQbk010460; Wed, 3 Aug 2011 15:37:26 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p73EbODL010459; Wed, 3 Aug 2011 15:37:24 +0100 Date: Wed, 3 Aug 2011 15:37:24 +0100 From: Ralf Baechle To: Alan Cox , linux-serial@vger.kernel.org Cc: John Crispin , Thomas Langer , linux-mips@linux-mips.org Subject: [PATCH] SERIAL: Lantiq: Set timeout in uart_port Message-ID: <20110803143724.GB8673@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30822 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2400 Content-Length: 1063 Lines: 35 From: John Crispin Without this patch apps using readline hang. Signed-off-by: Thomas Langer Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Cc: linux-serial@vger.kernel.org --- No replies when John Crispin first posted this patch. He's on vacation so I'm reposting hoping for an ack. I'd prefer to merge this through the MIPS tree along with other lantiq fixes -- thanks. drivers/tty/serial/lantiq.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index 58cf279..bc95f52 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -478,8 +478,10 @@ lqasc_set_termios(struct uart_port *port, spin_unlock_irqrestore(<q_asc_lock, flags); /* Don't rewrite B0 */ - if (tty_termios_baud_rate(new)) + if (tty_termios_baud_rate(new)) tty_termios_encode_baud_rate(new, baud, baud); + + uart_update_timeout(port, cflag, baud); } static const char* -- 1.7.2.3 From ralf@linux-mips.org Wed Aug 3 16:38:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 16:38:08 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33199 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491162Ab1HCOiE (ORCPT ); Wed, 3 Aug 2011 16:38:04 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p73Ec3Dl010504; Wed, 3 Aug 2011 15:38:03 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p73Ec3kF010503; Wed, 3 Aug 2011 15:38:03 +0100 Date: Wed, 3 Aug 2011 15:38:03 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH V2 1/3] MIPS: lantiq: fixes external interrupt sources Message-ID: <20110803143803.GC8673@linux-mips.org> References: <1311019720-22234-1-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1311019720-22234-1-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30823 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2402 Content-Length: 26 Lines: 3 Applied. Thanks, Ralf From ralf@linux-mips.org Wed Aug 3 16:38:52 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 16:38:55 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33202 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491188Ab1HCOiw (ORCPT ); Wed, 3 Aug 2011 16:38:52 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p73Ecpuk010516; Wed, 3 Aug 2011 15:38:51 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p73EcpqE010515; Wed, 3 Aug 2011 15:38:51 +0100 Date: Wed, 3 Aug 2011 15:38:51 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/3] MIPS: lantiq: fix setting the PCI bus speed on AR9 Message-ID: <20110803143851.GD8673@linux-mips.org> References: <1311019453-21277-1-git-send-email-blogic@openwrt.org> <1311019453-21277-2-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1311019453-21277-2-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30824 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2403 Content-Length: 26 Lines: 3 Applied. Thanks, Ralf From alan@lxorguk.ukuu.org.uk Wed Aug 3 17:07:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 17:07:22 +0200 (CEST) Received: from earthlight.etchedpixels.co.uk ([81.2.110.250]:54315 "EHLO www.etchedpixels.co.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S2100411Ab1HCPHQ (ORCPT ); Wed, 3 Aug 2011 17:07:16 +0200 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by www.etchedpixels.co.uk (8.14.4/8.14.4) with ESMTP id p73FAT04026568; Wed, 3 Aug 2011 16:10:30 +0100 Date: Wed, 3 Aug 2011 16:10:29 +0100 From: Alan Cox To: Ralf Baechle Cc: linux-serial@vger.kernel.org, linux-mips@linux-mips.org, greg@kroah.com Subject: Re: [PATCH] SERIAL: Lantiq: Set timeout in uart_port Message-ID: <20110803161029.1d46865f@lxorguk.ukuu.org.uk> In-Reply-To: <20110803143724.GB8673@linux-mips.org> References: <20110803143724.GB8673@linux-mips.org> X-Mailer: Claws Mail 3.7.9 (GTK+ 2.22.0; x86_64-redhat-linux-gnu) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAFVBMVEWysKsSBQMIAwIZCwj///8wIhxoRDXH9QHCAAABeUlEQVQ4jaXTvW7DIBAAYCQTzz2hdq+rdg494ZmBeE5KYHZjm/d/hJ6NfzBJpp5kRb5PHJwvMPMk2L9As5Y9AmYRBL+HAyJKeOU5aHRhsAAvORQ+UEgAvgddj/lwAXndw2laEDqA4x6KEBhjYRCg9tBFCOuJFxg2OKegbWjbsRTk8PPhKPD7HcRxB7cqhgBRp9Dcqs+B8v4CQvFdqeot3Kov6hBUn0AJitrzY+sgUuiA8i0r7+B3AfqKcN6t8M6HtqQ+AOoELCikgQSbgabKaJW3kn5lBs47JSGDhhLKDUh1UMipwwinMYPTBuIBjEclSaGZUk9hDlTb5sUTYN2SFFQuPe4Gox1X0FZOufjgBiV1Vls7b+GvK3SU4wfmcGo9rPPQzgIabfj4TYQo15k3bTHX9RIw/kniir5YbtJF4jkFG+dsDK1IgE413zAthU/vR2HVMmFUPIHTvF6jWCpFaGw/A3qWgnbxpSm9MSmY5b3pM1gvNc/gQfwBsGwF0VCtxZgAAAAASUVORK5CYII= Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 30825 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alan@lxorguk.ukuu.org.uk Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2427 Content-Length: 329 Lines: 11 On Wed, 3 Aug 2011 15:37:24 +0100 Ralf Baechle wrote: > From: John Crispin > > Without this patch apps using readline hang. > > Signed-off-by: Thomas Langer > Signed-off-by: John Crispin Signed-off-by: Alan Cox From ralf@linux-mips.org Wed Aug 3 18:25:42 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 18:25:46 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33521 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S2100412Ab1HCQZm (ORCPT ); Wed, 3 Aug 2011 18:25:42 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p73GHm9u017140; Wed, 3 Aug 2011 17:17:48 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p73GHjV5017133; Wed, 3 Aug 2011 17:17:45 +0100 Date: Wed, 3 Aug 2011 17:17:45 +0100 From: Ralf Baechle To: Tejun Heo Cc: benh@kernel.crashing.org, yinghai@kernel.org, hpa@zytor.com, tony.luck@intel.com, schwidefsky@de.ibm.com, liqin.chen@sunplusct.com, lethal@linux-sh.org, davem@davemloft.net, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, mingo@redhat.com, linux-mips@linux-mips.org Subject: Re: [PATCH 19/23] mips: Use HAVE_MEMBLOCK_NODE_MAP Message-ID: <20110803161745.GA13266@linux-mips.org> References: <1311694534-5161-1-git-send-email-tj@kernel.org> <1311694534-5161-20-git-send-email-tj@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1311694534-5161-20-git-send-email-tj@kernel.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30826 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2487 Content-Length: 1131 Lines: 33 On Tue, Jul 26, 2011 at 05:35:30PM +0200, Tejun Heo wrote: > mips used early_node_map[] just to prime free_area_init_nodes(). Now > memblock can be used for the same purpose and early_node_map[] is > scheduled to be dropped. Use memblock instead. > > Signed-off-by: Tejun Heo > Cc: Benjamin Herrenschmidt > Cc: Yinghai Lu > Cc: Ralf Baechle > Cc: linux-mips@linux-mips.org > --- > Only compile tested. Thanks. > > arch/mips/Kconfig | 3 +++ > arch/mips/kernel/setup.c | 3 ++- > arch/mips/sgi-ip27/ip27-memory.c | 5 +++-- > 3 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 653da62..368b2ec 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -24,6 +24,9 @@ config MIPS > select GENERIC_IRQ_PROBE > select GENERIC_IRQ_SHOW > select HAVE_ARCH_JUMP_LABEL > + select HAVE_MEMBLOCK This means will include which does not exist for MIPS. Did you accidentally not post this new file? Ralf From tj@kernel.org Wed Aug 3 18:26:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 18:26:31 +0200 (CEST) Received: from mail-ey0-f170.google.com ([209.85.215.170]:36693 "EHLO mail-ey0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S2100414Ab1HCQ01 (ORCPT ); Wed, 3 Aug 2011 18:26:27 +0200 Received: by eyd10 with SMTP id 10so944784eyd.29 for ; Wed, 03 Aug 2011 09:26:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=fsoA+NQzTZZAtORdLxO279vF5SsEUQHpaeUBumdPqo0=; b=tTtZ5ha+ojSEJpTDqj9sXm9vsU+te2/zf+Z7jNmhtn6g+6nOPYcDvI+QLrugIyGDaC 7O19d0iXe4i5+AweJ3DBYlY5PNGJR7PYym9rVZjUJrQNrD0TYbvL2c2H9QXHNkHF6CGp 5s6C+wA8iMHG42kmpNxTpZIN2U26fz4P7GqFI= Received: by 10.204.134.205 with SMTP id k13mr2279321bkt.252.1312388782297; Wed, 03 Aug 2011 09:26:22 -0700 (PDT) Received: from htj.dyndns.org ([130.75.117.88]) by mx.google.com with ESMTPS id f13sm290980bku.18.2011.08.03.09.26.20 (version=SSLv3 cipher=OTHER); Wed, 03 Aug 2011 09:26:20 -0700 (PDT) Date: Wed, 3 Aug 2011 18:26:18 +0200 From: Tejun Heo To: Ralf Baechle Cc: benh@kernel.crashing.org, yinghai@kernel.org, hpa@zytor.com, tony.luck@intel.com, schwidefsky@de.ibm.com, liqin.chen@sunplusct.com, lethal@linux-sh.org, davem@davemloft.net, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, mingo@redhat.com, linux-mips@linux-mips.org Subject: Re: [PATCH 19/23] mips: Use HAVE_MEMBLOCK_NODE_MAP Message-ID: <20110803162618.GB17477@htj.dyndns.org> References: <1311694534-5161-1-git-send-email-tj@kernel.org> <1311694534-5161-20-git-send-email-tj@kernel.org> <20110803161745.GA13266@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110803161745.GA13266@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30827 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tj@kernel.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2492 Content-Length: 1419 Lines: 41 On Wed, Aug 03, 2011 at 05:17:45PM +0100, Ralf Baechle wrote: > On Tue, Jul 26, 2011 at 05:35:30PM +0200, Tejun Heo wrote: > > > mips used early_node_map[] just to prime free_area_init_nodes(). Now > > memblock can be used for the same purpose and early_node_map[] is > > scheduled to be dropped. Use memblock instead. > > > > Signed-off-by: Tejun Heo > > Cc: Benjamin Herrenschmidt > > Cc: Yinghai Lu > > Cc: Ralf Baechle > > Cc: linux-mips@linux-mips.org > > --- > > Only compile tested. Thanks. > > > > arch/mips/Kconfig | 3 +++ > > arch/mips/kernel/setup.c | 3 ++- > > arch/mips/sgi-ip27/ip27-memory.c | 5 +++-- > > 3 files changed, 8 insertions(+), 3 deletions(-) > > > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > > index 653da62..368b2ec 100644 > > --- a/arch/mips/Kconfig > > +++ b/arch/mips/Kconfig > > @@ -24,6 +24,9 @@ config MIPS > > select GENERIC_IRQ_PROBE > > select GENERIC_IRQ_SHOW > > select HAVE_ARCH_JUMP_LABEL > > + select HAVE_MEMBLOCK > > This means will include which does > not exist for MIPS. Did you accidentally not post this new file? Nope, earlier commit 24aa07882b and its fix patch (patch 0.5 in this series) removes asm/memblock.h from all archs and drops it from linux/memblock.h. Thanks. -- tejun From cjb@laptop.org Wed Aug 3 20:40:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Aug 2011 20:40:42 +0200 (CEST) Received: from void.printf.net ([89.145.121.20]:38955 "EHLO void.printf.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S2100417Ab1HCSke (ORCPT ); Wed, 3 Aug 2011 20:40:34 +0200 Received: from 173-166-109-241-newengland.hfc.comcastbusiness.net ([173.166.109.241] helo=bob.laptop.org) by void.printf.net with esmtp (Exim 4.69) (envelope-from ) id 1QogMr-0006ve-CV; Wed, 03 Aug 2011 19:40:33 +0100 From: Chris Ball To: Ralf Baechle Cc: Manuel Lauss , Linux-MIPS , linux-mmc@vger.kernel.org Subject: Re: [PATCH 12/15] MMC: au1xmmc: remove Alchemy CPU subtype dependencies References: <1312307470-6841-1-git-send-email-manuel.lauss@googlemail.com> <1312307470-6841-13-git-send-email-manuel.lauss@googlemail.com> <20110803120627.GA856@linux-mips.org> Date: Wed, 03 Aug 2011 14:40:26 -0400 In-Reply-To: <20110803120627.GA856@linux-mips.org> (Ralf Baechle's message of "Wed, 3 Aug 2011 13:06:27 +0100") Message-ID: User-Agent: Gnus/5.110018 (No Gnus v0.18) Emacs/23.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 30828 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cjb@laptop.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2557 Content-Length: 769 Lines: 25 Hi Ralf, On Wed, Aug 03 2011, Ralf Baechle wrote: > On Tue, Aug 02, 2011 at 07:51:07PM +0200, Manuel Lauss wrote: > >> Replace all occurrences of CONFIG_SOC_AU1??? with runtime feature >> detection. >> >> Cc: >> Signed-off-by: Manuel Lauss >> --- >> I'd like for this patch to go in via the mips tree since a few more depend >> on it. > > Patch is looking ok. Since MMC is orphaned I've just queued it and it > will go to linux-next after -rc1. MMC isn't orphaned anymore -- I've been maintaining it for a year. Feel free to merge this yourself since there are dependency issues, though: Acked-by: Chris Ball -- Chris Ball One Laptop Per Child From david.daney@cavium.com Thu Aug 4 00:04:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 00:04:35 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14850 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490996Ab1HCWEb (ORCPT ); Thu, 4 Aug 2011 00:04:31 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 03 Aug 2011 15:05:38 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 3 Aug 2011 15:04:28 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 3 Aug 2011 15:04:28 -0700 Message-ID: <4E39C5EB.8070701@cavium.com> Date: Wed, 03 Aug 2011 15:04:27 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: devicetree-discuss@lists.ozlabs.org, Grant Likely CC: Linux Kernel Mailing List , linux-mips Subject: How to describe I2C and MDIO bus multiplexers with the device tree? Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 03 Aug 2011 22:04:28.0557 (UTC) FILETIME=[508EBBD0:01CC5229] X-archive-position: 30829 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2691 Content-Length: 9263 Lines: 342 I have a board (ASCII art representation below) that has a bunch of PHY devices that are connected behind a MDIO bus switch/multiplexer. This multiplexer is in turn controlled by GPIO pins on a I2C GPIO port expander. which is in turn on a I2C bus switch/multiplexer. There is another switch/multiplexer that is controlled directly via I2C. Q: How can this be represented? My attempt is below... I2C-0 MDIO-1 MDIO-0 | | | | |--------------| | | | | +---- I2C-A ----- | | +---------+ multiplexor | | | | | +---- I2C-B ----- | | | | I2C-0x70 | | | | | +---- I2C-C ----- | | | | | | | | | +---- I2C-D ----- | | | | | | | | | +---- I2C-E ----- | | | | | | | | | +---- I2C-F --------+ | | | | | | | | | | +---- I2C-G --+ | | | | |--------------| | | | | | | | | | | |------------| +-----+ | | | | | | | | | | +--------+ ds1337 RTC| | | | | | | I2C-0x68 | | |-----+-----| |--------+---------| | | |------------| | | GPIO | | | | | | | Port +--Pin 3---+ multiplexor | | | | | Expander +--Pin 4---+ | | | | | | | 74CBTLV3253 | | | | |I2C-0x38 | | | | | | | | | | | | | |-----------| |-+--------------+-| | | | | | | | | | | | | |----+-----| M M | | | GPIO | D D | | | Port | I I | | | Expander | O O | | | | | | | | |I2C-0x38 | W X | | |----------| | | | | | | | | | | | | |----+---| |----+---| | | | | | | | | | PHY-11 | | PHY-21 | | | | PHY-12 | | PHY-22 | | | | PHY-13 | | PHY-23 | | | | PHY-14 | | PHY-24 | | | |--------| |--------| | | | | |-------------| | | | multiplexor | | | | I2C-0x77 +----------------------------------------------------------------+ +---------+ foo | | | | | |-+--------+--| | | | | | M M D D I I O O | | Y Z | | |-----+--| |--+----| | PHY-3 | | PHY-4 | |--------| |-------| /dts-v1/; / { model = "cavium,brfl"; compatible = "cavium,brfl"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&ciu>; soc@0 { . . . smi0: mdio@1180000001800 { compatible = "cavium,octeon-3860-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x11800 0x00001800 0x0 0x40>; }; smi1: mdio@1180000001900 { compatible = "cavium,octeon-3860-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x11800 0x00001900 0x0 0x40>; }; . . . twsi0: i2c@1180000001000 { #address-cells = <1>; #size-cells = <0>; compatible = "cavium,octeon-3860-twsi"; reg = <0x11800 0x00001000 0x0 0x200>; interrupts = <0 45>; clock-rate = <100000>; . . . i2c-mux@70 { compatible = "nxp,pca9548"; reg = <0x38>; i2c@6 { #address-cells = <1>; #size-cells = <0>; cell-index = <6>; gpio66: gpio@38 { compatible = "nxp,pca8574"; reg = <0x38>; #gpio-cells = <2>; gpio-controller; }; } }; . . . mdio-mux@77 { compatible = "bar,foo"; reg = <0x77>; parent-bus = <&smi0> #address-cells = <1>; #size-cells = <0>; mdio@0 { #address-cells = <1>; #size-cells = <0>; cell-index = <0>; phy3: ethernet-phy@1 { reg = <1>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; mdio@1 { #address-cells = <1>; #size-cells = <0>; cell-index = <1>; phy4: ethernet-phy@1 { reg = <1>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; }; . . . }; mdio-mux@0 { compatible = "ti,sn74cbtlv3253" gpios = <&gpio66 3 1 &gpio66 4 1> parent-bus = <&smi1> #address-cells = <1>; #size-cells = <0>; mdio@2 { #address-cells = <1>; #size-cells = <0>; cell-index = <2>; phy11: ethernet-phy@1 { reg = <1>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy12: ethernet-phy@1 { reg = <2>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy13: ethernet-phy@1 { reg = <3>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy14: ethernet-phy@1 { reg = <4>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; }; mdio@3 { #address-cells = <1>; #size-cells = <0>; cell-index = <3>; phy21: ethernet-phy@1 { reg = <1>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy22: ethernet-phy@1 { reg = <2>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy23: ethernet-phy@1 { reg = <3>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy24: ethernet-phy@1 { reg = <4>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; }; }; . . . }; }; Some notes/questions: o mdio-mux@0 is a child of soc@0, but conceptually it might just as well be floating in space. o The parent-bus property of both mdio-mux@0 and mdio-mux@77 denotes the connection of the multiplexer to its 'parent' bus. o The cell-index property of the multiplexed bus instances denotes the sub-bus of the switch/multiplexer the children are connected to. Would a different property name be better here? o For mdio-mux@0 the driver will use the cell-index to determine how to program the gpios that control the switch/multiplexer. Am I totally insane? David Daney From david.daney@cavium.com Thu Aug 4 00:11:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 00:12:02 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15032 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490996Ab1HCWL6 (ORCPT ); Thu, 4 Aug 2011 00:11:58 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 03 Aug 2011 15:13:06 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 3 Aug 2011 15:11:56 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 3 Aug 2011 15:11:56 -0700 Message-ID: <4E39C7A7.3000302@cavium.com> Date: Wed, 03 Aug 2011 15:11:51 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: devicetree-discuss@lists.ozlabs.org, Grant Likely CC: Linux Kernel Mailing List , linux-mips Subject: Re: How to describe I2C and MDIO bus multiplexers with the device tree? References: <4E39C5EB.8070701@cavium.com> In-Reply-To: <4E39C5EB.8070701@cavium.com> Content-Type: multipart/mixed; boundary="------------060008040202090804020408" X-OriginalArrivalTime: 03 Aug 2011 22:11:56.0419 (UTC) FILETIME=[5B810D30:01CC522A] X-archive-position: 30830 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2695 Content-Length: 10738 Lines: 316 This is a multi-part message in MIME format. --------------060008040202090804020408 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit On 08/03/2011 03:04 PM, David Daney wrote: > > I have a board (ASCII art representation below) that has a bunch of > PHY devices that are connected behind a MDIO bus switch/multiplexer. > This multiplexer is in turn controlled by GPIO pins on a I2C GPIO port > expander. which is in turn on a I2C bus switch/multiplexer. > > There is another switch/multiplexer that is controlled directly via I2C. > > Q: How can this be represented? > > My attempt is below... > > I2C-0 MDIO-1 MDIO-0 > | | | > | |--------------| | | Crap, my mailer ate the ASCII art. Attached is the text file that should make it through. > > Some notes/questions: > > o mdio-mux@0 is a child of soc@0, but conceptually it might just as > well be floating in space. > > o The parent-bus property of both mdio-mux@0 and mdio-mux@77 denotes > the connection of the multiplexer to its 'parent' bus. > > o The cell-index property of the multiplexed bus instances denotes the > sub-bus of the switch/multiplexer the children are connected to. > Would a different property name be better here? > > o For mdio-mux@0 the driver will use the cell-index to determine how > to program the gpios that control the switch/multiplexer. > > Am I totally insane? > David Daney --------------060008040202090804020408 Content-Type: text/plain; name="multiplexer-1.txt" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="multiplexer-1.txt" I2C-0 MDIO-1 MDIO-0 | | | | |--------------| | | | | +---- I2C-A ----- | | +---------+ multiplexor | | | | | +---- I2C-B ----- | | | | I2C-0x70 | | | | | +---- I2C-C ----- | | | | | | | | | +---- I2C-D ----- | | | | | | | | | +---- I2C-E ----- | | | | | | | | | +---- I2C-F --------+ | | | | | | | | | | +---- I2C-G --+ | | | | |--------------| | | | | | | | | | | |------------| +-----+ | | | | | | | | | | +--------+ ds1337 RTC| | | | | | | I2C-0x68 | | |-----+-----| |--------+---------| | | |------------| | | GPIO | | | | | | | Port +--Pin 3---+ multiplexor | | | | | Expander +--Pin 4---+ | | | | | | | 74CBTLV3253 | | | | |I2C-0x38 | | | | | | | | | | | | | |-----------| |-+--------------+-| | | | | | | | | | | | | |----+-----| M M | | | GPIO | D D | | | Port | I I | | | Expander | O O | | | | | | | | |I2C-0x38 | W X | | |----------| | | | | | | | | | | | | |----+---| |----+---| | | | | | | | | | PHY-11 | | PHY-21 | | | | PHY-12 | | PHY-22 | | | | PHY-13 | | PHY-23 | | | | PHY-14 | | PHY-24 | | | |--------| |--------| | | | | |-------------| | | | multiplexor | | | | I2C-0x77 +----------------------------------------------------------------+ +---------+ foo | | | | | |-+--------+--| | | | | | M M D D I I O O | | Y Z | | |-----+--| |--+----| | PHY-3 | | PHY-4 | |--------| |-------| /dts-v1/; / { model = "cavium,brfl"; compatible = "cavium,brfl"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&ciu>; soc@0 { . . . smi0: mdio@1180000001800 { compatible = "cavium,octeon-3860-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x11800 0x00001800 0x0 0x40>; }; smi1: mdio@1180000001900 { compatible = "cavium,octeon-3860-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x11800 0x00001900 0x0 0x40>; }; . . . twsi0: i2c@1180000001000 { #address-cells = <1>; #size-cells = <0>; compatible = "cavium,octeon-3860-twsi"; reg = <0x11800 0x00001000 0x0 0x200>; interrupts = <0 45>; clock-rate = <100000>; . . . i2c-mux@70 { compatible = "nxp,pca9548"; reg = <0x38>; i2c@6 { #address-cells = <1>; #size-cells = <0>; cell-index = <6>; gpio66: gpio@38 { compatible = "nxp,pca8574"; reg = <0x38>; #gpio-cells = <2>; gpio-controller; }; } }; . . . mdio-mux@77 { compatible = "bar,foo"; reg = <0x77>; parent-bus = <&smi0> #address-cells = <1>; #size-cells = <0>; mdio@0 { #address-cells = <1>; #size-cells = <0>; cell-index = <0>; phy3: ethernet-phy@1 { reg = <1>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; mdio@1 { #address-cells = <1>; #size-cells = <0>; cell-index = <1>; phy4: ethernet-phy@1 { reg = <1>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; }; . . . }; mdio-mux@0 { compatible = "ti,sn74cbtlv3253" gpios = <&gpio66 3 1 &gpio66 4 1> parent-bus = <&smi1> #address-cells = <1>; #size-cells = <0>; mdio@2 { #address-cells = <1>; #size-cells = <0>; cell-index = <2>; phy11: ethernet-phy@1 { reg = <1>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy12: ethernet-phy@1 { reg = <2>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy13: ethernet-phy@1 { reg = <3>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy14: ethernet-phy@1 { reg = <4>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; }; mdio@3 { #address-cells = <1>; #size-cells = <0>; cell-index = <3>; phy21: ethernet-phy@1 { reg = <1>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy22: ethernet-phy@1 { reg = <2>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy23: ethernet-phy@1 { reg = <3>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; phy24: ethernet-phy@1 { reg = <4>; compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, <3 0x13 0 0x0a60>; }; }; }; . . . }; }; --------------060008040202090804020408-- From gregkh@suse.de Thu Aug 4 01:30:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 01:30:54 +0200 (CEST) Received: from cantor2.suse.de ([195.135.220.15]:34172 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491162Ab1HCXas (ORCPT ); Thu, 4 Aug 2011 01:30:48 +0200 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id D7451970AD; Thu, 4 Aug 2011 01:30:47 +0200 (CEST) X-Mailbox-Line: From gregkh@clark.kroah.org Wed Aug 3 15:12:53 2011 Message-Id: <20110803221252.928206230@clark.kroah.org> User-Agent: quilt/0.48-16.4 Date: Wed, 03 Aug 2011 15:01:48 -0700 From: Greg KH To: linux-kernel@vger.kernel.org, stable@kernel.org Cc: stable-review@kernel.org, torvalds@linux-foundation.org, akpm@linux-foundation.org, alan@lxorguk.ukuu.org.uk, Ralf Baechle , linux-serial@vger.kernel.org, linux-mips@linux-mips.org, Alan Cox Subject: [088/102] SERIAL: SC26xx: Fix link error. In-Reply-To: <20110803221345.GA10346@kroah.com> X-archive-position: 30831 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2760 Content-Length: 1276 Lines: 42 3.0-stable review patch. If anyone has any objections, please let us know. ------------------ From: Ralf Baechle commit f2eb3cdf14457fccb14ae8c4d7d7cee088cd3957 upstream. Kconfig allows enabling console support for the SC26xx driver even when it's configured as a module resulting in a: ERROR: "uart_console_device" [drivers/tty/serial/sc26xx.ko] undefined! modpost error since the driver was merged in eea63e0e8a60d00485b47fb6e75d9aa2566b989b [SC26XX: New serial driver for SC2681 uarts] in 2.6.25. Fixed by only allowing console support to be enabled if the driver is builtin. Signed-off-by: Ralf Baechle Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Acked-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1419,7 +1419,7 @@ config SERIAL_SC26XX config SERIAL_SC26XX_CONSOLE bool "Console on SC2681/SC2692 serial port" - depends on SERIAL_SC26XX + depends on SERIAL_SC26XX=y select SERIAL_CORE_CONSOLE help Support for Console on SC2681/SC2692 serial ports. From florian@openwrt.org Thu Aug 4 13:24:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 13:24:48 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:40407 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491076Ab1HDLYl (ORCPT ); Thu, 4 Aug 2011 13:24:41 +0200 Received: by wyg19 with SMTP id 19so1049152wyg.36 for ; Thu, 04 Aug 2011 04:24:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:mime-version :content-type:content-transfer-encoding:message-id; bh=Esga93hUS6iDiuPiUM6dHE0LqlOuavqjcCkML2ZqbWM=; b=SnN/Xegg9MGaFhEqniWnaswAjsW1xN6McTmF+oq0PvJ0syCSYxoDm1Ni72+pEP1ujg 3y9uk9+QL0XNM6ZxXgA8Fz6F61GvxFN70nGdREKxntIH8lHLmn6F+ayeQ4j2+Oo6eF8y B438Hu0yCvvxJRXT3tRMbKJitOjSPNCHah7+g= Received: by 10.227.38.13 with SMTP id z13mr604758wbd.61.1312457075634; Thu, 04 Aug 2011 04:24:35 -0700 (PDT) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id ff6sm1410041wbb.49.2011.08.04.04.24.33 (version=SSLv3 cipher=OTHER); Thu, 04 Aug 2011 04:24:34 -0700 (PDT) From: Florian Fainelli Organization: OpenWrt To: ralf@linux-mips.org Subject: [PATCH 1/3 v2] MIPS: introduce GENERIC_DUMP_TLB Date: Thu, 4 Aug 2011 13:28:25 +0200 User-Agent: KMail/1.13.6 (Linux/2.6.38-8-server; KDE/4.6.2; x86_64; ; ) Cc: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-Id: <201108041328.25230.florian@openwrt.org> X-archive-position: 30832 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3191 Content-Length: 1791 Lines: 57 Allows us not to duplicate more lines in arch/mips/lib/Makefile. Signed-off-by: Florian Fainelli --- No changes since v2 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d300c2b..9f4ade4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1803,6 +1803,10 @@ config SIBYTE_DMA_PAGEOPS config CPU_HAS_PREFETCH bool +config CPU_GENERIC_DUMP_TLB + bool + default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX) + choice prompt "MIPS MT options" diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index b2cad4f..d8c290c 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -8,27 +8,9 @@ lib-y += csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \ obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o -obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o -obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o -obj-$(CONFIG_CPU_R10000) += dump_tlb.o +obj-$(CONFIG_CPU_GENERIC_DUMP_TLB) += dump_tlb.o obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o -obj-$(CONFIG_CPU_R4300) += dump_tlb.o -obj-$(CONFIG_CPU_R4X00) += dump_tlb.o -obj-$(CONFIG_CPU_R5000) += dump_tlb.o -obj-$(CONFIG_CPU_R5432) += dump_tlb.o -obj-$(CONFIG_CPU_R5500) += dump_tlb.o -obj-$(CONFIG_CPU_R6000) += -obj-$(CONFIG_CPU_R8000) += -obj-$(CONFIG_CPU_RM7000) += dump_tlb.o -obj-$(CONFIG_CPU_RM9000) += dump_tlb.o -obj-$(CONFIG_CPU_SB1) += dump_tlb.o obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o -obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o -obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o -obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o -obj-$(CONFIG_CPU_XLR) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o -- 1.7.4.1 From florian@openwrt.org Thu Aug 4 13:24:42 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 13:25:14 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:40407 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491182Ab1HDLYm (ORCPT ); Thu, 4 Aug 2011 13:24:42 +0200 Received: by mail-wy0-f177.google.com with SMTP id 19so1049152wyg.36 for ; Thu, 04 Aug 2011 04:24:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:mime-version :content-type:content-transfer-encoding:message-id; bh=eSJR1IHSm5zwpdhu+dGEmTXTmgZY15sBFBCExYa8/3Y=; b=P8kufbH1VFKcPT8qKeBYJyw9X2qv1hSzVSHJE/vdZ95GQLBxrNrT8vQgLgqWcM7Toc Oxep3zPDmmZr8//uI9ntUZ0t8TQ5bM6WL4FbEAQKpIy5N5WsIqB9dLzs7a1WsmD/eDt5 pbw1t0Wk6AID0nfxRn0IHcBY6Hs5tCN2Jij+A= Received: by 10.217.2.202 with SMTP id p52mr637803wes.28.1312457081883; Thu, 04 Aug 2011 04:24:41 -0700 (PDT) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id k9sm1130532weq.3.2011.08.04.04.24.40 (version=SSLv3 cipher=OTHER); Thu, 04 Aug 2011 04:24:40 -0700 (PDT) From: Florian Fainelli Organization: OpenWrt To: ralf@linux-mips.org Subject: [PATCH 2/3 v2] MIPS: introduce CPU_R4K_FPU Date: Thu, 4 Aug 2011 13:28:31 +0200 User-Agent: KMail/1.13.6 (Linux/2.6.38-8-server; KDE/4.6.2; x86_64; ; ) Cc: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-Id: <201108041328.31484.florian@openwrt.org> X-archive-position: 30833 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3192 Content-Length: 2158 Lines: 59 R4K-style CPUs have this boolean defined by default. Allows us to remove some lines in arch/mips/kernel/Makefile. Signed-off-by: Florian Fainelli --- Changes since v1: - removed CPU_XLR already covered by CPU_R4K_FPU diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9f4ade4..44eebc7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1807,6 +1807,10 @@ config CPU_GENERIC_DUMP_TLB bool default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX) +config CPU_R4K_FPU + bool + default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + choice prompt "MIPS MT options" diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 83bba33..d07c112 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -32,27 +32,11 @@ obj-$(CONFIG_MODULES) += mips_ksyms.o module.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o -obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5500) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o -obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o -- 1.7.4.1 From florian@openwrt.org Thu Aug 4 13:24:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 13:25:40 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:40407 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491188Ab1HDLYr (ORCPT ); Thu, 4 Aug 2011 13:24:47 +0200 Received: by mail-wy0-f177.google.com with SMTP id 19so1049152wyg.36 for ; Thu, 04 Aug 2011 04:24:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:mime-version :content-type:content-transfer-encoding:message-id; bh=P2IaI8EoyPhPoXNorCNoyWQyV/zqAPR4WymYgpFjxQg=; b=Mm52lFcKD1wxdfos3MM2ZpiwHaiZCHoPaBgtkGV7yAoNBX8vA3IEe3QWCDNw5YbWXX RNZ0OsckxCYWUa7GxIrcEDAwWoXABxk7wGqt1zIUMNzFM63n/1+XZaOXL6L06GBUdaAY Duo0ItbKIRbrIxM/BvRSN7Aucwtlvcms3kwJE= Received: by 10.216.229.1 with SMTP id g1mr630859weq.51.1312457087441; Thu, 04 Aug 2011 04:24:47 -0700 (PDT) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id n33sm1123258weq.36.2011.08.04.04.24.45 (version=SSLv3 cipher=OTHER); Thu, 04 Aug 2011 04:24:46 -0700 (PDT) From: Florian Fainelli Organization: OpenWrt To: ralf@linux-mips.org Subject: [PATCH 3/3 v2] MIPS: introduce CPU_R4K_CACHE_TLB Date: Thu, 4 Aug 2011 13:28:37 +0200 User-Agent: KMail/1.13.6 (Linux/2.6.38-8-server; KDE/4.6.2; x86_64; ; ) Cc: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-Id: <201108041328.37455.florian@openwrt.org> X-archive-position: 30834 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3193 Content-Length: 2364 Lines: 60 R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to remove some lines in arch/mips/mm/Makefile. Signed-off-by: Florian Fainelli --- Changes since v1: - removed CPU_XLR already covered by CPU_R4K_CACHE_TLB - add back CPU_R8000 to Kconfig exception list and Makefile diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 44eebc7..a250607 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1811,6 +1811,10 @@ config CPU_R4K_FPU bool default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) +config CPU_R4K_CACHE_TLB + bool + default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + choice prompt "MIPS MT options" diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 4d8c162..8e880da 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -11,26 +11,12 @@ obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o -obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o -obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5500) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o -obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o -obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o -obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o -- 1.7.4.1 From ralf@linux-mips.org Thu Aug 4 17:07:13 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 17:07:17 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56199 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491188Ab1HDPHN (ORCPT ); Thu, 4 Aug 2011 17:07:13 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p74F7AXX005091; Thu, 4 Aug 2011 16:07:10 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p74F79Sq005089; Thu, 4 Aug 2011 16:07:09 +0100 Date: Thu, 4 Aug 2011 16:07:09 +0100 From: Ralf Baechle To: Hillf Danton Cc: LKML , linux-mips@linux-mips.org Subject: Re: [RFC patch] MIPS: select correct tc Message-ID: <20110804150709.GD3149@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30835 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3390 Content-Length: 207 Lines: 7 Please, when posting MIPS patches ALWAYS include linux-mips@linux-mips.org so patchwork can snarf up the patches. Without that there is a significant chance that I'm going to miss patches. Thanks! Ralf From ralf@linux-mips.org Thu Aug 4 17:54:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 17:55:04 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47702 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491755Ab1HDPy6 (ORCPT ); Thu, 4 Aug 2011 17:54:58 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p74Fsv0S006536 for ; Thu, 4 Aug 2011 16:54:57 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p74FsvU7006534 for linux-mips@linux-mips.org; Thu, 4 Aug 2011 16:54:57 +0100 Resent-From: Ralf Baechle Resent-Date: Thu, 4 Aug 2011 16:54:57 +0100 Resent-Message-ID: <20110804155457.GB5297@linux-mips.org> Resent-To: linux-mips@linux-mips.org Received: from mail-ww0-f43.google.com ([74.125.82.43]:49194 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491188Ab1HDOih (ORCPT ); Thu, 4 Aug 2011 16:38:37 +0200 Received: by wwe32 with SMTP id 32so1349764wwe.24 for ; Thu, 04 Aug 2011 07:38:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; bh=JpmtN0F+lYQC2pnx0bv+kLkCPfJOh15xhq1vXR2W3Sw=; b=DWS9QrSlv+PPkL2gPZbXGDE+hISbXXh8nIeYrHz3n6iVKlw1KJKMbrW+6AGWdZtjwQ mWuUgJgxx2A7fAlGGrKEsE1szL3B/KOaycbd7vBjTy7f5IwA8Oyzc+oOs28Sh4klGD8o aoiUgE5MRZ9uIF44BTI02JqrOVXms0B2ISSnw= MIME-Version: 1.0 Received: by 10.216.237.233 with SMTP id y83mr1432975weq.9.1312468711520; Thu, 04 Aug 2011 07:38:31 -0700 (PDT) Received: by 10.216.46.136 with HTTP; Thu, 4 Aug 2011 07:38:31 -0700 (PDT) Date: Thu, 4 Aug 2011 22:38:31 +0800 Message-ID: Subject: [RFC patch] MIPS: select correct tc From: Hillf Danton To: Ralf Baechle , LKML Content-Type: text/plain; charset=UTF-8 X-archive-position: 30836 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3440 Content-Length: 567 Lines: 20 If we could find tc on the tc list for @index, the found tc should be returned. Signed-off-by: Hillf Danton --- arch/mips/kernel/vpe.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index dbb6b40..044b700 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -192,7 +192,7 @@ static struct tc *get_tc(int index) } spin_unlock(&vpecontrol.tc_list_lock); - return NULL; + return res; } /* allocate a vpe and associate it with this minor (or index) */ From ralf@linux-mips.org Thu Aug 4 17:55:01 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 17:55:29 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47704 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491763Ab1HDPzB (ORCPT ); Thu, 4 Aug 2011 17:55:01 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p74Ft0p4006541 for ; Thu, 4 Aug 2011 16:55:00 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p74Ft0qQ006540 for linux-mips@linux-mips.org; Thu, 4 Aug 2011 16:55:00 +0100 Resent-From: Ralf Baechle Resent-Date: Thu, 4 Aug 2011 16:55:00 +0100 Resent-Message-ID: <20110804155500.GC5297@linux-mips.org> Resent-To: linux-mips@linux-mips.org Received: from mail-wy0-f177.google.com ([74.125.82.177]:45689 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491084Ab1HDOqs (ORCPT ); Thu, 4 Aug 2011 16:46:48 +0200 Received: by wyg19 with SMTP id 19so1219172wyg.36 for ; Thu, 04 Aug 2011 07:46:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; bh=cVkOH5iK21GrhOuDdUqnQScOdiALSR5pI8C1RLl0DB0=; b=nFVUNL5OvSfHI7CgBggStjl/gvqDVfvoh/90nLUy4awBeDV7DzlzNfo71ILIfTaODM ZKmLDwtrnzTSRjMATNRUDJIgBFbArqzU/Y9xEN0oGQubXp58kTodkWw2d2su/SrY6Xsr 2bfQ+kM9A6EivWEcu7BIVcckgPk4xxzVY1amY= MIME-Version: 1.0 Received: by 10.216.237.233 with SMTP id y83mr1443780weq.9.1312469201952; Thu, 04 Aug 2011 07:46:41 -0700 (PDT) Received: by 10.216.46.136 with HTTP; Thu, 4 Aug 2011 07:46:41 -0700 (PDT) Date: Thu, 4 Aug 2011 22:46:41 +0800 Message-ID: Subject: [RFC patch] MIPS: deduplicate comment for i8259 From: Hillf Danton To: Ralf Baechle , LKML Content-Type: text/plain; charset=UTF-8 X-archive-position: 30837 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3441 Content-Length: 657 Lines: 20 The comment for the slave PIC is changed from 8259A-1 to 8259A-2. Signed-off-by: Hillf Danton --- arch/mips/kernel/i8259.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index c018696..55d2624 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -230,7 +230,7 @@ static int i8259A_shutdown(struct sys_device *dev) */ if (i8259A_auto_eoi >= 0) { outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ - outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */ + outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ } return 0; } From ralf@linux-mips.org Thu Aug 4 17:55:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 17:55:51 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47706 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491765Ab1HDPzG (ORCPT ); Thu, 4 Aug 2011 17:55:06 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p74Ft5uE006546 for ; Thu, 4 Aug 2011 16:55:05 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p74Ft5Ix006545 for linux-mips@linux-mips.org; Thu, 4 Aug 2011 16:55:05 +0100 Resent-From: Ralf Baechle Resent-Date: Thu, 4 Aug 2011 16:55:05 +0100 Resent-Message-ID: <20110804155505.GD5297@linux-mips.org> Resent-To: linux-mips@linux-mips.org Received: from mail-wy0-f177.google.com ([74.125.82.177]:57964 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491189Ab1HDOzz (ORCPT ); Thu, 4 Aug 2011 16:55:55 +0200 Received: by wyg19 with SMTP id 19so1227597wyg.36 for ; Thu, 04 Aug 2011 07:55:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; bh=DRZP8Y5NpM6BfMJC3QwvTNV5SuEcFV8pw4Icf2XUt9M=; b=p8xmCMG/9Bk8i7cfYbzY2IUuepk3xIPZhbqZ2T1+IOA9GLZBRxcXK9vj1z+lpG0905 qCr+VqlP3ystsobe2hY21FN+Wwli/7si/G1ivgiA56/JjTCnBYQrHsMiXELD4AoWzogO xFWr6BBCMnkJVRJmsPQk9iKu17DcIQBlLApQc= MIME-Version: 1.0 Received: by 10.216.80.14 with SMTP id j14mr966826wee.9.1312469749772; Thu, 04 Aug 2011 07:55:49 -0700 (PDT) Received: by 10.216.46.136 with HTTP; Thu, 4 Aug 2011 07:55:49 -0700 (PDT) Date: Thu, 4 Aug 2011 22:55:49 +0800 Message-ID: Subject: [RFC patch] MIPS/netlogic: dont setup boot CPU twice From: Hillf Danton To: Ralf Baechle , LKML Content-Type: text/plain; charset=UTF-8 X-archive-position: 30838 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3442 Content-Length: 651 Lines: 21 When do smp setup, check for boot CPU is added, then it is impossible to be initialized twice. Signed-off-by: Hillf Danton --- arch/mips/netlogic/xlr/smp.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c index b495a7f..e6f8c62 100644 --- a/arch/mips/netlogic/xlr/smp.c +++ b/arch/mips/netlogic/xlr/smp.c @@ -167,6 +167,8 @@ void __init nlm_smp_setup(void) num_cpus = 1; for (i = 0; i < NR_CPUS; i++) { + if (i == boot_cpu) + continue; if (nlm_cpu_ready[i]) { cpu_set(i, phys_cpu_present_map); __cpu_number_map[i] = num_cpus; From jayachandranc@netlogicmicro.com Thu Aug 4 20:49:26 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Aug 2011 20:49:33 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:2282 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491755Ab1HDSt0 (ORCPT ); Thu, 4 Aug 2011 20:49:26 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id fc2a2e9f0003646f ; Thu, 4 Aug 2011 11:47:44 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 4 Aug 2011 11:50:35 -0700 Date: Fri, 5 Aug 2011 00:21:41 +0530 From: "Jayachandran C." To: Hillf Danton Cc: Ralf Baechle , LKML , linux-mips@linux-mips.org Subject: Re: [RFC patch] MIPS/netlogic: dont setup boot CPU twice Message-ID: <20110804185139.GA11724@jayachandranc.netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 04 Aug 2011 18:50:35.0451 (UTC) FILETIME=[651960B0:01CC52D7] X-archive-position: 30839 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3553 Content-Length: 1049 Lines: 30 > > When do smp setup, check for boot CPU is added, then it is impossible to be > initialized twice. > > Signed-off-by: Hillf Danton > --- >  arch/mips/netlogic/xlr/smp.c |    2 ++ >  1 files changed, 2 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c > index b495a7f..e6f8c62 100644 > --- a/arch/mips/netlogic/xlr/smp.c > +++ b/arch/mips/netlogic/xlr/smp.c > @@ -167,6 +167,8 @@ void __init nlm_smp_setup(void) > >        num_cpus = 1; >        for (i = 0; i < NR_CPUS; i++) { > +               if (i == boot_cpu) > +                       continue; >                if (nlm_cpu_ready[i]) { >                        cpu_set(i, phys_cpu_present_map); >                        __cpu_number_map[i] = num_cpus; The nlm_cpu_ready[] entry is not set for the boot_cpu, it is set for only the secondary cpus in smpboot.S. The code works as it is, but your patch makes it more explicit. My only commnet is that it might look better if you combine both the if checks. JC. From dvomlehn@cisco.com Fri Aug 5 04:02:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Aug 2011 04:03:03 +0200 (CEST) Received: from rcdn-iport-8.cisco.com ([173.37.86.79]:42919 "EHLO rcdn-iport-8.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491784Ab1HECCv (ORCPT ); Fri, 5 Aug 2011 04:02:51 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=dvomlehn@cisco.com; l=6766; q=dns/txt; s=iport; t=1312509770; x=1313719370; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=oWQ3IGsTxXll6EdoMu3w9TQ9f0WUpLwujYeJ6WhoINM=; b=YQNlyJZM5C1EiesQRncutHRFiCyx1Do4p0bcat+fLIVVS/9vhi+uhN1y JVrtnxmtiUKuny4QLbBgRMaiqxmNuL25SEzsg0cLmLesAKsxB1pWLhzcW fpCYnWymMWEOvuXpYRDlwUyzco23jQiZMNMlzf3BwOlmZE3KLxSVXfUjT o=; X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: Av0EAFBOO06rRDoI/2dsb2JhbABDp253gUABAQEBAgESARQTPwULCxguFEk1h0qiIwGeYIVjXwSjew X-IronPort-AV: E=Sophos;i="4.67,320,1309737600"; d="scan'208";a="9870324" Received: from mtv-core-3.cisco.com ([171.68.58.8]) by rcdn-iport-8.cisco.com with ESMTP; 05 Aug 2011 02:02:42 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by mtv-core-3.cisco.com (8.14.3/8.14.3) with ESMTP id p7522g53022474; Fri, 5 Aug 2011 02:02:42 GMT Date: Thu, 4 Aug 2011 22:02:42 -0400 From: David VomLehn To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/1] Pendantic stack backtrace code Message-ID: <20110805020242.GA23916@dvomlehn-lnx2.corp.sa.net> References: <20110706233614.GA19332@dvomlehn-lnx2.corp.sa.net> <20110802155759.GA891@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110802155759.GA891@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) X-archive-position: 30840 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 3771 Content-Length: 6598 Lines: 168 On Tue, Aug 02, 2011 at 10:57:59AM -0500, Ralf Baechle wrote: > On Wed, Jul 06, 2011 at 04:36:15PM -0700, David VomLehn wrote: > > > This is the much updated version of the MIPS stack backtrace code submitted > > a few years ago. ... > > + * Copyright(C) 2007 Scientific-Atlanta, Inc. > > Shouldn't this now be changed to Cisco? I don't know whether you can retractively change it, but it should certainly be Cisco from 2010 on. > > +/* True if the corresponding MIPS register must be saved before use */ > > You mean a callee-saved register? I do! > I think this may need a few additions to handle some processor specific > enhancements such as Cavium's BBIT0 etc. family of branches. Sounds like a good idea. I think it should be pretty straightforward. Has anyone besides Cavium added branches? > > +#ifdef SPECIAL_SYMBOL > > +/* arch/mips/kernel/entry.S */ > > +SPECIAL_SYMBOL(ret_from_exception, KERNEL_FRAME_GLUE) > > +SPECIAL_SYMBOL(ret_from_irq, KERNEL_FRAME_GLUE) > [...] > > We could modify RESTORE_SOME etc. to automatically generate a table of > these SPECIAL_SYMBOLs instead of manually maintaining this table? I'm not sure how to do this with RESTORE_SOME and friends, but using a macro to build the symbol table by putting it in a special section might be good. It would also help people who want to modify the code to remember that the code marking needs to be maintained. > > diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S > > index 37acfa0..6548ae3 100644 > > --- a/arch/mips/kernel/entry.S > > +++ b/arch/mips/kernel/entry.S > > @@ -40,9 +40,10 @@ FEXPORT(__ret_from_irq) > > andi t0, t0, KU_USER > > beqz t0, resume_kernel > > > > + .globl resume_userspace > > resume_userspace: > > local_irq_disable # make sure we dont miss an > > - # interrupt setting need_resched > > + # interrupt setting _need_resched > > Huh? The comment should say _TIF_NEED_RESCHED - but that's to long for > the 80 colums. Looks like I got a little incautious with vi. > > index e9b3af2..dbf53b5 100644 > > --- a/arch/mips/kernel/traps.c > > +++ b/arch/mips/kernel/traps.c > > @@ -53,6 +53,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > extern void check_wait(void); > > @@ -86,6 +87,8 @@ extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, > > struct mips_fpu_struct *ctx, int has_fpu, > > void *__user *fault_addr); > > > > +#define MAX_STACK_FRAMES_PRINTED 100 > > Is this needed? The size of the stack should limit the dump naturally and > the code need some sort of safeguard to protect against running beyond the > end of the stack anyway. Good question. There is a case I've seen with from time to time in which memory corruption causes the stack frame size to be detected to be zero. So, the frame after the current frame starts where the current frame starts and the return address is at the same location, and you just loop forever in your backtrace. Bumping this number to 1000 is fine, just so long as we are assured of termination in some reasonable timeframe. > > + * match_short_get_got - checks for a match for short GOT recovery code > > + * @in_vpc: Pointer to the &struct vpc for the instruction at which > > + * the GOT recovery code may start. > > + * > > + * Returns: true if it matches, zero if it does not. > > + * > > + * Matches the code fragment: > > + * li gp, > > + * addu gp, gp, t9 > > + * which is a short version of the code used to recover the GOT (global offset > > + * table) pointer from the address of the current function. > > But there is no GOT in the kernel?? That's true. We not only use this code for doing kernel backtraces, but we also backtrace the current task, which will normally be in user space and have a GOT. (We write out other info that allows us to post-process it and annotate the stack trace with the corresponding symbols) Doing the user space backtrace is the primary motivation this code supports ABI analysis. I'm happy to take this out for general consumption; what are your thoughts? > > +/* > > + * find_return_abi - Find the end of the function by o32 ABI rules. > > + * @bt: Pointer to struct base_bt object. > > + * Returns: Zero if we found the end of the function, a negative errno value > > + * if we could not. > > + * > > + * If the function was found, ctx->fn_return will point to the "jr ra" > > + * instruction, otherwise it will be set to NULL. > > + * If the function was not found, ctx->fn_return will be set to NULL_REG. > > + */ > > +static int find_return_abi(struct base_bt_ctx *ctx) > > +{ > > + int rc; > > + struct vpc vpc; > > + mips_instruction op; > > + > > + ctx->fn_return = NULL; > > + > > + /* Scan forward to find the "jr ra" that marks the end > > + * of the current function */ > > Not really; gcc may place move part of the code path behind the jr $ra > even though that violates the O32 ABI spec. In the kernel this happens > for do_one_initcall(), mips_display_message() and more. > > And that's generally my concern with this approach - GCC's optimizer is > becoming very good in the most recent versions. In in the long run I see > us forced to go down the DWARF alley but of course the 10, 20% bloat won't > be popular. The non-ABI tracing code already handles cases where the return code is located in the middle of the function. I'll see if I can cover this in the ABI code, too. > But if users tell me they like this apprach and in practice it works well > enough then I'm all for it. > > +/* > > + * This handles getting the next kernel stackframe. It checks to see if we are > > + * in an exception or interrupt frame. If not, we just pass it along to the > > + * process backtracing. > > + * @kbt: Pointer to the struct kernel_bt object > > + * > > + * Returns: KERNEL_BT_END_IN_START_KERNEL The backtrace should stop > > + * because the next frame is for > > + * start_kernel(), whose memory has > > + * probably been freed and overwritten. > > Not sure if it's worth the pain but we could set a flag in free_init_mem so > kernel_backtrace_next would know if start_kernel is stil available. If you had a flag, all that means is that you could backtrace to start_kernel()'s caller, which you already know is kernel_entry. For the time after free_init_mem, which is much longer than the time from boot to free_init_mem, you wouldn't be able to do the backtrace. So, I don't think it's worth it. > Ralf -- David VL From dhillf@gmail.com Fri Aug 5 15:17:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Aug 2011 15:17:55 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:58285 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491140Ab1HENRr convert rfc822-to-8bit (ORCPT ); Fri, 5 Aug 2011 15:17:47 +0200 Received: by wwe32 with SMTP id 32so2119170wwe.24 for ; Fri, 05 Aug 2011 06:17:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=maB2xdZBd8HLG8DlGZOBpHBQ25FHuJLNmwsPzGDJ4Jo=; b=tukkESIN/5umPu6yevVbIj9XcccAerxdaeCZyLxvpXvQugUCD8fjUEZrRNNB0QXEip EqteYZYEmDy8RjmTO7RigwsX7kSxEbAgfVtw/2f5XWjfbaaBC2uTpJNJZQU82yoaMxaZ vJQUvYWAPYCc3FjT2VjitulVzPs/GBPKrTwYM= MIME-Version: 1.0 Received: by 10.216.80.14 with SMTP id j14mr2161876wee.9.1312550249415; Fri, 05 Aug 2011 06:17:29 -0700 (PDT) Received: by 10.216.46.136 with HTTP; Fri, 5 Aug 2011 06:17:28 -0700 (PDT) In-Reply-To: <20110804150709.GD3149@linux-mips.org> References: <20110804150709.GD3149@linux-mips.org> Date: Fri, 5 Aug 2011 21:17:28 +0800 Message-ID: Subject: Re: [RFC patch] MIPS: select correct tc From: Hillf Danton To: Ralf Baechle Cc: LKML , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 30841 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4138 Content-Length: 297 Lines: 8 On Thu, Aug 4, 2011 at 11:07 PM, Ralf Baechle wrote: > Please, when posting MIPS patches ALWAYS include linux-mips@linux-mips.org > so patchwork can snarf up the patches.  Without that there is a significant > chance that I'm going to miss patches. > Got and thanks. Hillf From dhillf@gmail.com Fri Aug 5 15:44:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Aug 2011 15:44:10 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:57183 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491183Ab1HENoD convert rfc822-to-8bit (ORCPT ); Fri, 5 Aug 2011 15:44:03 +0200 Received: by wyh11 with SMTP id 11so515613wyh.36 for ; Fri, 05 Aug 2011 06:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=Gb0XDF/XT5kIHaXXGqcg89pop/MQJJLW4EA2DBLFA74=; b=nHOxuKSVoadNPjeLU8UyXb3iA0XelgnJA2TmrmVO0/b9FMRrGP7wtIO3fgsQr0Ht63 NpZd/VCZUeHLHbJwp9bbSBIGhkJ8PPLv8q1h9IguZqmeQyi5hFvvOfxAYsBq689n9qsG 7D8L4VaFhn/n90YfQAK3w9tyzeaOFlc4XivCg= MIME-Version: 1.0 Received: by 10.216.80.14 with SMTP id j14mr2194232wee.9.1312551837449; Fri, 05 Aug 2011 06:43:57 -0700 (PDT) Received: by 10.216.46.136 with HTTP; Fri, 5 Aug 2011 06:43:57 -0700 (PDT) In-Reply-To: <20110804185139.GA11724@jayachandranc.netlogicmicro.com> References: <20110804185139.GA11724@jayachandranc.netlogicmicro.com> Date: Fri, 5 Aug 2011 21:43:57 +0800 Message-ID: Subject: Re: [RFC patch] MIPS/netlogic: dont setup boot CPU twice From: Hillf Danton To: "Jayachandran C." Cc: Ralf Baechle , LKML , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 30842 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4155 Content-Length: 1302 Lines: 37 On Fri, Aug 5, 2011 at 2:51 AM, Jayachandran C. wrote: > The nlm_cpu_ready[] entry is not set for the boot_cpu, it is set for only > the secondary cpus in smpboot.S.  The code works as it is, but your patch > makes it more explicit. > > My only commnet is that it might look better if you combine both the if checks. > Got and thanks. It is recooked as the following. Hillf ------------------------------------------------------------------------------ Subject: [RFC patch] MIPS/netlogic: add comment for smp setup It seems that BSP could be setup twice, but the nlm_cpu_ready array is only set for ASPs in smpboot.S, not including BSP. Signed-off-by: Hillf Danton --- arch/mips/netlogic/xlr/smp.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c index b495a7f..b82667c 100644 --- a/arch/mips/netlogic/xlr/smp.c +++ b/arch/mips/netlogic/xlr/smp.c @@ -167,6 +167,10 @@ void __init nlm_smp_setup(void) num_cpus = 1; for (i = 0; i < NR_CPUS; i++) { + /* + * BSP is not set in nlm_cpu_ready array, it is only for + * ASPs (goto see smpboot.S) + */ if (nlm_cpu_ready[i]) { cpu_set(i, phys_cpu_present_map); __cpu_number_map[i] = num_cpus; From hauke@hauke-m.de Wed Aug 10 09:14:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Aug 2011 09:14:45 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:51154 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491108Ab1HJHOk (ORCPT ); Wed, 10 Aug 2011 09:14:40 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 2E3D58C90; Wed, 10 Aug 2011 09:14:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WLNTirg7OZZa; Wed, 10 Aug 2011 09:14:35 +0200 (CEST) Received: from [10.59.128.41] (unknown [82.113.99.169]) by hauke-m.de (Postfix) with ESMTPSA id 769868C88; Wed, 10 Aug 2011 09:14:30 +0200 (CEST) Message-ID: <4E422FD0.5050600@hauke-m.de> Date: Wed, 10 Aug 2011 09:14:24 +0200 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.18) Gecko/20110617 Lightning/1.0b2 Thunderbird/3.1.11 MIME-Version: 1.0 To: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= CC: linville@tuxdriver.com, linux-wireless@vger.kernel.org, linux-mips@linux-mips.org, jonas.gorski@gmail.com, ralf@linux-mips.org, mb@bu3sch.de, george@znau.edu.ua, arend@broadcom.com, b43-dev@lists.infradead.org, bernhardloos@googlemail.com, arnd@arndb.de, julian.calaby@gmail.com, sshtylyov@mvista.com Subject: Re: [PATCH 06/11] bcma: add serial console support References: <1311376815-15755-1-git-send-email-hauke@hauke-m.de> <1311376815-15755-7-git-send-email-hauke@hauke-m.de> In-Reply-To: X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 30843 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7224 Content-Length: 2226 Lines: 59 On 07/29/2011 11:06 PM, RafaÅ‚ MiÅ‚ecki wrote: > W dniu 29 lipca 2011 23:04 użytkownik RafaÅ‚ MiÅ‚ecki napisaÅ‚: >> 2011/7/23 Hauke Mehrtens : >>> This adds support for serial console to bcma, when operating on an SoC. >>> >>> Signed-off-by: Hauke Mehrtens >>> --- >>> drivers/bcma/bcma_private.h | 8 ++++ >>> drivers/bcma/driver_chipcommon.c | 48 +++++++++++++++++++++++++++ >>> drivers/bcma/driver_chipcommon_pmu.c | 26 ++++++++++++++ >>> drivers/bcma/driver_mips.c | 1 + >>> include/linux/bcma/bcma_driver_chipcommon.h | 14 ++++++++ >>> 5 files changed, 97 insertions(+), 0 deletions(-) >>> >>> diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h >>> index b97633d..22d3052 100644 >>> --- a/drivers/bcma/bcma_private.h >>> +++ b/drivers/bcma/bcma_private.h >>> @@ -29,6 +29,14 @@ void bcma_init_bus(struct bcma_bus *bus); >>> /* sprom.c */ >>> int bcma_sprom_get(struct bcma_bus *bus); >>> >>> +/* driver_chipcommon.c */ >>> +#ifdef CONFIG_BCMA_DRIVER_MIPS >>> +void bcma_chipco_serial_init(struct bcma_drv_cc *cc); >>> +#endif /* CONFIG_BCMA_DRIVER_MIPS */ >>> + >>> +/* driver_chipcommon_pmu.c */ >>> +u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc); >>> + >>> #ifdef CONFIG_BCMA_HOST_PCI >>> /* host_pci.c */ >>> extern int __init bcma_host_pci_init(void); >> >> Not sure, what do you think about this, feel free to comment. >> >> My idea was to use bcma_private.h for bcma-internal functions. For >> example, support for PCI host or SoC host, is something "internal" (as >> I call it) for bcma. Drivers in theory could be separated modules and >> I use include/linux/bcma/driver_*.h for them. >> >> If following this schema, declarations of >> bcma_pmu_alp_clock >> bcma_host_pci_init >> should be in include/linux/bcma/bcma_driver_chipcommon.h > > Same goes to the > bcma_pmu_get_clockcpu > from patch 07/11. > > Sorry for late-noticing this. > > I don't have more comments against your patch set :) Hope John will > take it soon :) > This sounds good. I will send a new patch moving the method declaration to bcma_driver_chipcommon.h for these 3 functions. Hauke From holger@freyther.de Wed Aug 10 09:24:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Aug 2011 09:24:38 +0200 (CEST) Received: from gandharva.secretlabs.de ([78.46.147.237]:26895 "EHLO gandharva.secretlabs.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491116Ab1HJHYe (ORCPT ); Wed, 10 Aug 2011 09:24:34 +0200 Received: from [172.31.14.96] (unknown [222.128.194.2]) by gandharva.secretlabs.de (Postfix) with ESMTPSA id A7C9C1B10C0F for ; Wed, 10 Aug 2011 07:35:29 +0000 (UTC) Message-ID: <4E423228.2080309@freyther.de> Date: Wed, 10 Aug 2011 09:24:24 +0200 From: Holger Hans Peter Freyther User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.18) Gecko/20110617 Lightning/1.0b2 Thunderbird/3.1.11 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [RFC][PATCH] Implement perf_callchain_user for o32 ABI (on mipsel) X-Enigmail-Version: 1.1.1 Content-Type: multipart/mixed; boundary="------------060009060802060709030201" X-archive-position: 30844 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: holger@freyther.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7227 Content-Length: 5376 Lines: 175 This is a multi-part message in MIME format. --------------060009060802060709030201 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Hi all, I wanted to use perf to profile my userspace application on MIPS but I saw that there is no solution for that. I have written some code to scan the prologue of the function to identify the stack size and where in the stack the return address is stored. 0: 27bdffd8 addiu sp,sp,-40 <-- used to find prev. stack 4: afbf0024 sw ra,36(sp) <-- stored return addr. 8: afbe0020 sw s8,32(sp) c: 03a0f021 move s8,sp 10: 3c1c0000 lui gp,0x0 14: 279c0000 addiu gp,gp,0 The code appears to work in qemu-system-mipsel (not where I am going to do my profiling) with my simple test application. The code is missing a S-o-b because I would like to get feedback if something like this would ever be accepted upstream. The other question is also about security, other ABIs, 32/64 bit... comments more than welcome holger --------------060009060802060709030201 Content-Type: text/x-patch; name="0001-mips-Implement-perf_callchain_user-by-scanning-the-p.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0001-mips-Implement-perf_callchain_user-by-scanning-the-p.pa"; filename*1="tch" >From 7a8b1fcf942dbbd1bebbf41facdc77c0d9552811 Mon Sep 17 00:00:00 2001 From: Holger Hans Peter Freyther Date: Wed, 10 Aug 2011 08:56:59 +0200 Subject: [PATCH] mips: Implement perf_callchain_user by scanning the prologue Scan the prologue for two instructions. The first one is adjusting the stack pointer for the current frame, the next one is storing the return address to the stack. Try to find both of these instructions to identify the caller of this function. It might be that the RA has not been written yet, in that case we will use the address from pt_regs. For all other frames try to find the two instructions again, exit when accessing the text or stack is failing, or too many instructions have been searched. http://elinux.org/images/6/68/ELC2008_-_Back-tracing_in_MIPS-based_Linux_Systems.pdf has helped to understand the prologue and was used in userspace for the first attempts. --- arch/mips/kernel/perf_event.c | 93 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 93 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index a824485..623d63a 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -536,12 +536,105 @@ handle_associated_event(struct cpu_hw_events *cpuc, /* Callchain handling code. */ /* + * Userspace code + */ + +/* * Leave userspace callchain empty for now. When we find a way to trace * the user stack callchains, we add here. */ void perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) { +#define ADDIU_SP_INSTR 0x27bd0000 +#define SW_RA_INSTR 0xafbf0000 + /* + * Find the first RA and FrameSize. + */ + unsigned long ra_addr = regs->regs[31]; + unsigned long sp_addr = regs->regs[29]; + unsigned long pc_addr = regs->cp0_epc; + unsigned long ra = 0; + unsigned int limit; + size_t stack_size = 0; + size_t ra_offset = 0; + + /* + * Try to find the initial stack size and the return address. It + * is possible that the code is still in the prologue and the + * return address might not have been stored to the stack yet + */ + for (limit = 0, pc_addr = regs->cp0_epc; + limit < (PAGE_SIZE / 4) && (!ra_offset || !stack_size); + --pc_addr, ++limit) { + int instr; + if (!access_ok(VERIFY_READ, pc_addr, sizeof(instr))) + return; + if (__copy_from_user_inatomic(&instr, (void *) pc_addr, sizeof(instr))) + return; + switch (instr & 0xffff0000) { + case ADDIU_SP_INSTR: + stack_size = abs((short)(instr & 0xffff)); + goto __out_of_loop; + break; + case SW_RA_INSTR: + ra_offset = instr & 0xffff; + break; + } + } + +__out_of_loop: + if (stack_size == 0) + return; + + if (ra_offset) { + ra_addr = sp_addr + ra_offset; + if (!access_ok(VERIFY_READ, ra_addr, sizeof(ra))) + return; + if (__copy_from_user_inatomic(&ra, (void *) ra_addr, sizeof(ra))) + return; + } + + sp_addr = sp_addr + stack_size; + + + /* now try to walk from the return address we found */ + limit = 0; + while (entry->nr < PERF_MAX_STACK_DEPTH && ra != 0) { + perf_callchain_store(entry, ra); + ra_offset = stack_size = 0; + + for (pc_addr = ra; + (!ra_offset || !stack_size) && limit < PAGE_SIZE/4/2; + --pc_addr, ++limit) { + int instr; + if (!access_ok(VERIFY_READ, pc_addr, sizeof(instr))) + return; + if (__copy_from_user_inatomic(&instr, (void *) pc_addr, sizeof(instr))) + return; + switch (instr & 0xffff0000) { + case ADDIU_SP_INSTR: + stack_size = abs((short)(instr & 0xffff)); + break; + case SW_RA_INSTR: + ra_offset = instr & 0xffff; + break; + } + } + + /* must have hit a limit */ + if (!ra_offset || !stack_size) + return; + + ra_addr = sp_addr + ra_offset; + if (!access_ok(VERIFY_READ, ra_addr, sizeof(ra))) + return; + if (__copy_from_user_inatomic(&ra, (void *) ra_addr, sizeof(ra))) + return; + sp_addr = sp_addr + stack_size; + } + + return; } static void save_raw_perf_callchain(struct perf_callchain_entry *entry, -- 1.7.4.1 --------------060009060802060709030201-- From ralf@linux-mips.org Wed Aug 10 17:24:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Aug 2011 17:24:05 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47525 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491156Ab1HJPYA (ORCPT ); Wed, 10 Aug 2011 17:24:00 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7AFNlxq008208; Wed, 10 Aug 2011 16:23:47 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7AFNkbD008205; Wed, 10 Aug 2011 16:23:46 +0100 Date: Wed, 10 Aug 2011 16:23:46 +0100 From: Ralf Baechle To: "David S. Miller" , Don Fry , netdev@vger.kernel.org Cc: Thomas Bogendoerfer , linux-mips@linux-mips.org Subject: [PATCH] PCnet: Fix section mismatch Message-ID: <20110810152346.GA6092@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30845 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7663 Content-Length: 1165 Lines: 32 Building MIPS mtx1_defconfig results in: MODPOST 735 modules WARNING: drivers/net/pcnet32.o(.devinit.text+0x11ec): Section mismatch in reference from the function pcnet32_probe_vlbus.constprop.22() to the variable .init.data:pcnet32_portlist The function __devinit pcnet32_probe_vlbus.constprop.22() references a variable __initdata pcnet32_portlist. If pcnet32_portlist is only used by pcnet32_probe_vlbus.constprop.22 then annotate pcnet32_portlist with a matching annotation. Signed-off-by: Ralf Baechle --- As recently discussed in the discussion of submission of a fix for a similar bug in another driver remove __initdata rather than replace it with __devinitdata. drivers/net/pcnet32.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c index 8b3090d..80b6f36 100644 --- a/drivers/net/pcnet32.c +++ b/drivers/net/pcnet32.c @@ -82,7 +82,7 @@ static int cards_found; /* * VLB I/O addresses */ -static unsigned int pcnet32_portlist[] __initdata = +static unsigned int pcnet32_portlist[] = { 0x300, 0x320, 0x340, 0x360, 0 }; static int pcnet32_debug; From david.daney@cavium.com Wed Aug 10 19:25:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Aug 2011 19:25:34 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5572 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491161Ab1HJRZ1 (ORCPT ); Wed, 10 Aug 2011 19:25:27 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 10 Aug 2011 10:26:31 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 10 Aug 2011 10:25:10 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 10 Aug 2011 10:25:10 -0700 Message-ID: <4E42BEF0.1040502@cavium.com> Date: Wed, 10 Aug 2011 10:25:04 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Holger Hans Peter Freyther , Ralf Baechle CC: linux-mips@linux-mips.org, "VomLehn, David" , gergely@homejinni.com Subject: Re: [RFC][PATCH] Implement perf_callchain_user for o32 ABI (on mipsel) References: <4E423228.2080309@freyther.de> In-Reply-To: <4E423228.2080309@freyther.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 10 Aug 2011 17:25:10.0177 (UTC) FILETIME=[74AD2110:01CC5782] X-archive-position: 30846 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7762 Content-Length: 1375 Lines: 38 On 08/10/2011 12:24 AM, Holger Hans Peter Freyther wrote: > Hi all, > > I wanted to use perf to profile my userspace application on MIPS but I saw > that there is no solution for that. I have written some code to scan the > prologue of the function to identify the stack size and where in the stack the > return address is stored. > > 0: 27bdffd8 addiu sp,sp,-40<-- used to find prev. stack > 4: afbf0024 sw ra,36(sp)<-- stored return addr. > 8: afbe0020 sw s8,32(sp) > c: 03a0f021 move s8,sp > 10: 3c1c0000 lui gp,0x0 > 14: 279c0000 addiu gp,gp,0 > > The code appears to work in qemu-system-mipsel (not where I am going to do my > profiling) with my simple test application. > > The code is missing a S-o-b because I would like to get feedback if something > like this would ever be accepted upstream. The other question is also about > security, other ABIs, 32/64 bit... > > comments more than welcome > holger You need to reconcile your patches with these: http://patchwork.linux-mips.org/patch/2579/ http://patchwork.linux-mips.org/patch/2376/ http://patchwork.linux-mips.org/patch/2375/ We probably could use some sort of backtrace code in the kernel, but three seperate implementations are too many. Also separating most of the unwinder into a separate file would be preferable to mixing it into the perf counter driver. David Daney From zecke@selfish.org Wed Aug 10 23:25:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Aug 2011 23:25:11 +0200 (CEST) Received: from lo.gmane.org ([80.91.229.12]:35276 "EHLO lo.gmane.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491864Ab1HJVZH (ORCPT ); Wed, 10 Aug 2011 23:25:07 +0200 Received: from list by lo.gmane.org with local (Exim 4.69) (envelope-from ) id 1QrGGw-00008F-12 for linux-mips@linux-mips.org; Wed, 10 Aug 2011 23:25:06 +0200 Received: from indra.secretlabs.de ([78.46.94.148]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 10 Aug 2011 23:25:06 +0200 Received: from zecke by indra.secretlabs.de with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 10 Aug 2011 23:25:06 +0200 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Holger Freyther Subject: Re: [RFC][PATCH] Implement =?utf-8?b?cGVyZl9jYWxsY2hhaW5fdXNlcg==?= for o32 ABI (on mipsel) Date: Wed, 10 Aug 2011 21:19:49 +0000 (UTC) Message-ID: References: <4E423228.2080309@freyther.de> <4E42BEF0.1040502@cavium.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: usenet@dough.gmane.org X-Gmane-NNTP-Posting-Host: sea.gmane.org User-Agent: Loom/3.14 (http://gmane.org/) X-Loom-IP: 78.46.94.148 (Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Ubuntu/11.04 Chromium/12.0.742.112 Chrome/12.0.742.112 Safari/534.30) X-archive-position: 30847 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zecke@selfish.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7920 Content-Length: 483 Lines: 16 David Daney cavium.com> writes: > We probably could use some sort of backtrace code in the kernel, but > three seperate implementations are too many. > > Also separating most of the unwinder into a separate file would be > preferable to mixing it into the perf counter driver. Ah great, the oprofile support didn't exist when I was starting. Yes, I will move the userspace unwinding into a common file and then build the perf support on top of it. holger From zecke@selfish.org Thu Aug 11 02:36:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Aug 2011 02:36:32 +0200 (CEST) Received: from gandharva.secretlabs.de ([78.46.147.237]:14569 "EHLO gandharva.secretlabs.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491867Ab1HKAg3 (ORCPT ); Thu, 11 Aug 2011 02:36:29 +0200 Received: from localhost.localdomain (unknown [1.202.86.226]) by gandharva.secretlabs.de (Postfix) with ESMTPSA id 17E5A1B10C11; Thu, 11 Aug 2011 00:47:26 +0000 (UTC) From: Holger Hans Peter Freyther To: linux-mips@linux-mips.org Cc: Holger Hans Peter Freyther Subject: [PATCH 0/2] Implement perf_callchain_user Date: Thu, 11 Aug 2011 02:36:04 +0200 Message-Id: <1313022966-28152-1-git-send-email-zecke@selfish.org> X-Mailer: git-send-email 1.7.4.1 X-archive-position: 30848 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zecke@selfish.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8019 Content-Length: 790 Lines: 22 Hi, this is moving code from oprofile/backtrace.c to a commom place and then implements perf_callchain_user using the common code. Right now the unwind_user_frame will always be compiled into the kernel. Holger Hans Peter Freyther (2): MIPS: Move userspace stack unwinding into kernel/user_backtrace.c MIPS: Implement perf_callchain_user using unwind_user_frame arch/mips/include/asm/stacktrace.h | 10 +++ arch/mips/kernel/Makefile | 3 +- arch/mips/kernel/perf_event.c | 14 ++++ arch/mips/kernel/user_backtrace.c | 129 ++++++++++++++++++++++++++++++++++ arch/mips/oprofile/backtrace.c | 133 ++---------------------------------- 5 files changed, 160 insertions(+), 129 deletions(-) create mode 100644 arch/mips/kernel/user_backtrace.c -- 1.7.4.1 From zecke@selfish.org Thu Aug 11 02:36:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Aug 2011 02:36:58 +0200 (CEST) Received: from gandharva.secretlabs.de ([78.46.147.237]:10068 "EHLO gandharva.secretlabs.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491870Ab1HKAgd (ORCPT ); Thu, 11 Aug 2011 02:36:33 +0200 Received: from localhost.localdomain (unknown [1.202.86.226]) by gandharva.secretlabs.de (Postfix) with ESMTPSA id 191871B10C16; Thu, 11 Aug 2011 00:47:30 +0000 (UTC) From: Holger Hans Peter Freyther To: linux-mips@linux-mips.org Cc: Holger Hans Peter Freyther , Holger Freyther Subject: [PATCH 1/2] MIPS: Move userspace stack unwinding into kernel/user_backtrace.c Date: Thu, 11 Aug 2011 02:36:05 +0200 Message-Id: <1313022966-28152-2-git-send-email-zecke@selfish.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1313022966-28152-1-git-send-email-zecke@selfish.org> References: <1313022966-28152-1-git-send-email-zecke@selfish.org> X-archive-position: 30849 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zecke@selfish.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8020 Content-Length: 10185 Lines: 354 Move the OProfile userspace stack unwinding into arch/mips/kernel/user_backtrace.c to be shared with the perf callchain implementation. Rename struct stackframe to user_stackframe, add a GPLv2 header to the source with the original author of the code. Always export the unwind_user_frame symbol to make it easy to use the OProfile module on an already built kernel. Signed-off-by: Holger Freyther --- arch/mips/include/asm/stacktrace.h | 10 +++ arch/mips/kernel/Makefile | 3 +- arch/mips/kernel/user_backtrace.c | 129 ++++++++++++++++++++++++++++++++++ arch/mips/oprofile/backtrace.c | 133 ++---------------------------------- 4 files changed, 146 insertions(+), 129 deletions(-) create mode 100644 arch/mips/kernel/user_backtrace.c diff --git a/arch/mips/include/asm/stacktrace.h b/arch/mips/include/asm/stacktrace.h index 780ee2c..f713da1 100644 --- a/arch/mips/include/asm/stacktrace.h +++ b/arch/mips/include/asm/stacktrace.h @@ -49,4 +49,14 @@ static __always_inline void prepare_frametrace(struct pt_regs *regs) : : "memory"); } +struct user_stackframe { + unsigned long sp; + unsigned long pc; + unsigned long ra; +}; + +int unwind_user_frame(struct user_stackframe *old_frame, + const unsigned int max_instr_check); + + #endif /* _ASM_STACKTRACE_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 83bba33..ce82fbf 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -6,7 +6,8 @@ extra-y := head.o init_task.o vmlinux.lds obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ ptrace.o reset.o setup.o signal.o syscall.o \ - time.o topology.o traps.o unaligned.o watch.o vdso.o + time.o topology.o traps.o unaligned.o watch.o vdso.o \ + user_backtrace.o ifdef CONFIG_FUNCTION_TRACER CFLAGS_REMOVE_ftrace.o = -pg diff --git a/arch/mips/kernel/user_backtrace.c b/arch/mips/kernel/user_backtrace.c new file mode 100644 index 0000000..cc1a8be --- /dev/null +++ b/arch/mips/kernel/user_backtrace.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2011 Daniel Kalmar + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License.. + */ + +#include +#include + +#include +#include +#include + +static inline int get_mem(unsigned long addr, unsigned long *result) +{ + unsigned long *address = (unsigned long *) addr; + if (!access_ok(VERIFY_READ, addr, sizeof(unsigned long))) + return -1; + if (__copy_from_user_inatomic(result, address, sizeof(unsigned long))) + return -3; + return 0; +} + +/* + * These two instruction helpers were taken from process.c + */ +static inline int is_ra_save_ins(union mips_instruction *ip) +{ + /* sw / sd $ra, offset($sp) */ + return (ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) + && ip->i_format.rs == 29 && ip->i_format.rt == 31; +} + +static inline int is_sp_move_ins(union mips_instruction *ip) +{ + /* addiu/daddiu sp,sp,-imm */ + if (ip->i_format.rs != 29 || ip->i_format.rt != 29) + return 0; + if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) + return 1; + return 0; +} + +/* + * Looks for specific instructions that mark the end of a function. + * This usually means we ran into the code area of the previous function. + */ +static inline int is_end_of_function_marker(union mips_instruction *ip) +{ + /* jr ra */ + if (ip->r_format.func == jr_op && ip->r_format.rs == 31) + return 1; + /* lui gp */ + if (ip->i_format.opcode == lui_op && ip->i_format.rt == 28) + return 1; + return 0; +} + +/* + * TODO for userspace stack unwinding: + * - handle cases where the stack is adjusted inside a function + * (generally doesn't happen) + * - find optimal value for max_instr_check + * - try to find a way to handle leaf functions + */ + +int unwind_user_frame(struct user_stackframe *old_frame, + const unsigned int max_instr_check) +{ + struct user_stackframe new_frame = *old_frame; + off_t ra_offset = 0; + size_t stack_size = 0; + unsigned long addr; + + if (old_frame->pc == 0 || old_frame->sp == 0 || old_frame->ra == 0) + return -9; + + for (addr = new_frame.pc; (addr + max_instr_check > new_frame.pc) + && (!ra_offset || !stack_size); --addr) { + union mips_instruction ip; + + if (get_mem(addr, (unsigned long *) &ip)) + return -11; + + if (is_sp_move_ins(&ip)) { + int stack_adjustment = ip.i_format.simmediate; + if (stack_adjustment > 0) + /* This marks the end of the previous function, + which means we overran. */ + break; + stack_size = (unsigned) stack_adjustment; + } else if (is_ra_save_ins(&ip)) { + int ra_slot = ip.i_format.simmediate; + if (ra_slot < 0) + /* This shouldn't happen. */ + break; + ra_offset = ra_slot; + } else if (is_end_of_function_marker(&ip)) + break; + } + + if (!ra_offset || !stack_size) + return -1; + + if (ra_offset) { + new_frame.ra = old_frame->sp + ra_offset; + if (get_mem(new_frame.ra, &(new_frame.ra))) + return -13; + } + + if (stack_size) { + new_frame.sp = old_frame->sp + stack_size; + if (get_mem(new_frame.sp, &(new_frame.sp))) + return -14; + } + + if (new_frame.sp > old_frame->sp) + return -2; + + new_frame.pc = old_frame->ra; + *old_frame = new_frame; + + return 0; +} +EXPORT_SYMBOL_GPL(unwind_user_frame); + diff --git a/arch/mips/oprofile/backtrace.c b/arch/mips/oprofile/backtrace.c index 6854ed5..265d26c 100644 --- a/arch/mips/oprofile/backtrace.c +++ b/arch/mips/oprofile/backtrace.c @@ -1,134 +1,11 @@ #include #include -#include -#include + #include #include -#include -#include -#include -#include - -struct stackframe { - unsigned long sp; - unsigned long pc; - unsigned long ra; -}; - -static inline int get_mem(unsigned long addr, unsigned long *result) -{ - unsigned long *address = (unsigned long *) addr; - if (!access_ok(VERIFY_READ, addr, sizeof(unsigned long))) - return -1; - if (__copy_from_user_inatomic(result, address, sizeof(unsigned long))) - return -3; - return 0; -} - -/* - * These two instruction helpers were taken from process.c - */ -static inline int is_ra_save_ins(union mips_instruction *ip) -{ - /* sw / sd $ra, offset($sp) */ - return (ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) - && ip->i_format.rs == 29 && ip->i_format.rt == 31; -} - -static inline int is_sp_move_ins(union mips_instruction *ip) -{ - /* addiu/daddiu sp,sp,-imm */ - if (ip->i_format.rs != 29 || ip->i_format.rt != 29) - return 0; - if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) - return 1; - return 0; -} - -/* - * Looks for specific instructions that mark the end of a function. - * This usually means we ran into the code area of the previous function. - */ -static inline int is_end_of_function_marker(union mips_instruction *ip) -{ - /* jr ra */ - if (ip->r_format.func == jr_op && ip->r_format.rs == 31) - return 1; - /* lui gp */ - if (ip->i_format.opcode == lui_op && ip->i_format.rt == 28) - return 1; - return 0; -} - -/* - * TODO for userspace stack unwinding: - * - handle cases where the stack is adjusted inside a function - * (generally doesn't happen) - * - find optimal value for max_instr_check - * - try to find a way to handle leaf functions - */ - -static inline int unwind_user_frame(struct stackframe *old_frame, - const unsigned int max_instr_check) -{ - struct stackframe new_frame = *old_frame; - off_t ra_offset = 0; - size_t stack_size = 0; - unsigned long addr; - - if (old_frame->pc == 0 || old_frame->sp == 0 || old_frame->ra == 0) - return -9; - - for (addr = new_frame.pc; (addr + max_instr_check > new_frame.pc) - && (!ra_offset || !stack_size); --addr) { - union mips_instruction ip; - - if (get_mem(addr, (unsigned long *) &ip)) - return -11; - - if (is_sp_move_ins(&ip)) { - int stack_adjustment = ip.i_format.simmediate; - if (stack_adjustment > 0) - /* This marks the end of the previous function, - which means we overran. */ - break; - stack_size = (unsigned) stack_adjustment; - } else if (is_ra_save_ins(&ip)) { - int ra_slot = ip.i_format.simmediate; - if (ra_slot < 0) - /* This shouldn't happen. */ - break; - ra_offset = ra_slot; - } else if (is_end_of_function_marker(&ip)) - break; - } - - if (!ra_offset || !stack_size) - return -1; - - if (ra_offset) { - new_frame.ra = old_frame->sp + ra_offset; - if (get_mem(new_frame.ra, &(new_frame.ra))) - return -13; - } - - if (stack_size) { - new_frame.sp = old_frame->sp + stack_size; - if (get_mem(new_frame.sp, &(new_frame.sp))) - return -14; - } - - if (new_frame.sp > old_frame->sp) - return -2; - - new_frame.pc = old_frame->ra; - *old_frame = new_frame; - - return 0; -} static inline void do_user_backtrace(unsigned long low_addr, - struct stackframe *frame, + struct user_stackframe *frame, unsigned int depth) { const unsigned int max_instr_check = 512; @@ -143,11 +20,11 @@ static inline void do_user_backtrace(unsigned long low_addr, #ifndef CONFIG_KALLSYMS static inline void do_kernel_backtrace(unsigned long low_addr, - struct stackframe *frame, + struct user_stackframe *frame, unsigned int depth) { } #else static inline void do_kernel_backtrace(unsigned long low_addr, - struct stackframe *frame, + struct user_stackframe *frame, unsigned int depth) { while (depth-- && frame->pc) { @@ -162,7 +39,7 @@ static inline void do_kernel_backtrace(unsigned long low_addr, void notrace op_mips_backtrace(struct pt_regs *const regs, unsigned int depth) { - struct stackframe frame = { .sp = regs->regs[29], + struct user_stackframe frame = { .sp = regs->regs[29], .pc = regs->cp0_epc, .ra = regs->regs[31] }; const int userspace = user_mode(regs); -- 1.7.4.1 From zecke@selfish.org Thu Aug 11 02:36:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Aug 2011 02:37:20 +0200 (CEST) Received: from gandharva.secretlabs.de ([78.46.147.237]:14397 "EHLO gandharva.secretlabs.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491864Ab1HKAgl (ORCPT ); Thu, 11 Aug 2011 02:36:41 +0200 Received: from localhost.localdomain (unknown [1.202.86.226]) by gandharva.secretlabs.de (Postfix) with ESMTPSA id CA8B91B10C17; Thu, 11 Aug 2011 00:47:38 +0000 (UTC) From: Holger Hans Peter Freyther To: linux-mips@linux-mips.org Cc: Holger Hans Peter Freyther , Holger Freyther Subject: [PATCH 2/2] MIPS: Implement perf_callchain_user using unwind_user_frame Date: Thu, 11 Aug 2011 02:36:06 +0200 Message-Id: <1313022966-28152-3-git-send-email-zecke@selfish.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1313022966-28152-1-git-send-email-zecke@selfish.org> References: <1313022966-28152-1-git-send-email-zecke@selfish.org> X-archive-position: 30850 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zecke@selfish.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8021 Content-Length: 1226 Lines: 36 Implement perf_callchain_user using the unwind_user_frame method, allow up to PAGE_SIZE / 4 instructions to be checked. Signed-off-by: Holger Freyther --- arch/mips/kernel/perf_event.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index 0aee944..7ea4d3c 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -540,6 +540,20 @@ handle_associated_event(struct cpu_hw_events *cpuc, void perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) { + struct user_stackframe frame = { .sp = regs->regs[29], + .pc = regs->cp0_epc, + .ra = regs->regs[31] }; + const unsigned long low_addr = ALIGN(frame.sp, THREAD_SIZE); + const unsigned int max_instr_check = PAGE_SIZE / 4; + const unsigned long high_addr = low_addr + THREAD_SIZE; + + + while (entry->nr < PERF_MAX_STACK_DEPTH && + !unwind_user_frame(&frame, max_instr_check)) { + perf_callchain_store(entry, frame.ra); + if (frame.sp < low_addr || frame.sp > high_addr) + break; + } } static void save_raw_perf_callchain(struct perf_callchain_entry *entry, -- 1.7.4.1 From ralf@linux-mips.org Thu Aug 11 09:35:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Aug 2011 09:35:37 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:53665 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491047Ab1HKHfa (ORCPT ); Thu, 11 Aug 2011 09:35:30 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7B7ZUp4030391 for ; Thu, 11 Aug 2011 08:35:30 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7B7ZTn0030389 for linux-mips@linux-mips.org; Thu, 11 Aug 2011 08:35:29 +0100 Date: Thu, 11 Aug 2011 08:35:29 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Kernel tarballs Message-ID: <20110811073529.GA29032@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8160 Content-Length: 357 Lines: 9 the change to the new version 3.x versioning scheme made the script that generates the kernel tarballs for linux-3.1-rc1 and later. I just fixed that and linux-3.1-rc1.tar.gz is now online. Not sure who is still downloading kernel tarballs these days but anyway, what are thoughts about moving from gzip to xz for compression and skip over bzip2? Ralf From ralf@linux-mips.org Thu Aug 11 09:52:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Aug 2011 09:52:56 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58667 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491047Ab1HKHwx (ORCPT ); Thu, 11 Aug 2011 09:52:53 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7B7qqti032558 for ; Thu, 11 Aug 2011 08:52:52 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7B7qqBE032555 for linux-mips@linux-mips.org; Thu, 11 Aug 2011 08:52:52 +0100 Date: Thu, 11 Aug 2011 08:52:52 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Re: Kernel tarballs Message-ID: <20110811075252.GA31552@linux-mips.org> References: <20110811073529.GA29032@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110811073529.GA29032@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30852 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8166 Content-Length: 372 Lines: 11 On Thu, Aug 11, 2011 at 08:35:29AM +0100, Ralf Baechle wrote: > the change to the new version 3.x versioning scheme made the script that > generates the kernel tarballs for linux-3.1-rc1 and later. I just fixed ^^^ fail Apparently the script not the only thing that failed this morning. ENEEDCOFFEE :-) Ralf From davem@davemloft.net Thu Aug 11 16:43:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Aug 2011 16:43:25 +0200 (CEST) Received: from shards.monkeyblade.net ([198.137.202.13]:57738 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491170Ab1HKOnS (ORCPT ); Thu, 11 Aug 2011 16:43:18 +0200 Received: from localhost (74-93-104-98-Washington.hfc.comcastbusiness.net [74.93.104.98]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id p7BEgtaP006759 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 11 Aug 2011 07:42:56 -0700 Date: Thu, 11 Aug 2011 07:42:55 -0700 (PDT) Message-Id: <20110811.074255.1123597785105932021.davem@davemloft.net> To: ralf@linux-mips.org Cc: pcnet32@frontier.com, netdev@vger.kernel.org, tsbogend@alpha.franken.de, linux-mips@linux-mips.org Subject: Re: [PATCH] PCnet: Fix section mismatch From: David Miller In-Reply-To: <20110810152346.GA6092@linux-mips.org> References: <20110810152346.GA6092@linux-mips.org> X-Mailer: Mew version 6.3 on Emacs 23.2 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (shards.monkeyblade.net [198.137.202.13]); Thu, 11 Aug 2011 07:42:56 -0700 (PDT) X-archive-position: 30853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8519 Content-Length: 656 Lines: 15 From: Ralf Baechle Date: Wed, 10 Aug 2011 16:23:46 +0100 > Building MIPS mtx1_defconfig results in: > > MODPOST 735 modules > WARNING: drivers/net/pcnet32.o(.devinit.text+0x11ec): Section mismatch in reference from the function pcnet32_probe_vlbus.constprop.22() to the variable .init.data:pcnet32_portlist > The function __devinit pcnet32_probe_vlbus.constprop.22() references > a variable __initdata pcnet32_portlist. > If pcnet32_portlist is only used by pcnet32_probe_vlbus.constprop.22 then > annotate pcnet32_portlist with a matching annotation. > > Signed-off-by: Ralf Baechle Applied, thanks Ralf. From mikeci@acm.org Fri Aug 12 01:23:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 01:23:35 +0200 (CEST) Received: from a.mail.sonic.net ([64.142.16.245]:39195 "EHLO a.mail.sonic.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491191Ab1HKXXb convert rfc822-to-8bit (ORCPT ); Fri, 12 Aug 2011 01:23:31 +0200 Received: from webmail.sonic.net (c.webmail.sonic.net [69.12.221.241]) by a.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p7BNNRRS002586 for ; Thu, 11 Aug 2011 16:23:29 -0700 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT X-Priority: Normal X-Mailer: AtMail PHP 5.62 Message-ID: <59027.1313105007@sonic.net> To: Reply-To: mikeci@acm.org X-Origin: 207.114.132.30 X-Atmail-Account: mikeci@sonic.net Date: Thu, 11 Aug 2011 16:23:27 -0700 Subject: Possible bug in 8250.c From: Ivica Mikec X-archive-position: 30854 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mikeci@acm.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8917 Content-Length: 408 Lines: 14 Hi! I noticed a problem in 8250.c. My board has only one UART port, and is 16550 compatible, so in function serial8250_interrupt I see that serial_in function is called twice. Second time, code "else if (end == NULL)" is executed and function return IRQ_NONE. This causes an entry in /proc/irq/spurious: count 239 unhandled 1 last_unhandled 4294700846 ms But this is not a spurious interrupt. Regards. From manuel.lauss@googlemail.com Fri Aug 12 11:39:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 11:40:04 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:50901 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491153Ab1HLJjz (ORCPT ); Fri, 12 Aug 2011 11:39:55 +0200 Received: by fxd20 with SMTP id 20so2860465fxd.36 for ; Fri, 12 Aug 2011 02:39:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=nbpP1uGZewVw8PuUcSIXMe2MG9kopu6lKGmIEIKGPKU=; b=PHBT063+YFp9avZeHxhyNl6NpmYrnXPZ8A4UwE082u50rkMjdzoecp6DFsM/6pPAsx DJgxFCVWbAMbrwpfomXi5Gy2GgTGna9eLejFAoSL0Md6EQp9Yfrje7QrgunPp0GezqGv mrdYITkzPgdGLdGoegyqGOM5hpRTwftYl2Xx4= Received: by 10.223.161.214 with SMTP id s22mr989576fax.59.1313141990608; Fri, 12 Aug 2011 02:39:50 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id s14sm467338fah.29.2011.08.12.02.39.48 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 02:39:49 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH RESEND 0/8] MIPS: Alchemy updates Date: Fri, 12 Aug 2011 11:39:37 +0200 Message-Id: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 X-archive-position: 30855 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9259 Content-Length: 4989 Lines: 94 This is a resend of the Alchemy updates without the patches Ralf already accepted and with Cc's added to others. Patches 1-3 move knowledge of per-chip USB setup out of the glues into a common file, clean up USB setup and header information. Patches 4-8 prepare for and remove all of the CONFIG_SOC_AU1??? symbols and the "au1xxx.h" header. Patch 4 removes au1xxx.h dependency from the old au1200 ide driver. Patch 6 kills it, Patch 5 removes CONFIG_SOC_AU1??? from DMA/DBDMA code Patch 7 rewrites Alchemy PCI support as a platform driver. Patch 8 finally does away with CONFIG_SOC_AU1???. Some of the devices registered in platform.c have to be moved to the boards actually using them. Manuel Lauss (8): MIPS: Alchemy: abstract USB block control register access MIPS: Alchemy: rewrite USB platform setup. MIPS: Alchemy: more base address cleanup MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dependencies MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines MIPS: Alchemy: kill au1xxx.h header MIPS: Alchemy: redo PCI as platform driver MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines The whole pile has been compile tested with all alchemy defconfigs and run-tested on Db1100,Db1200,Db1500,Db1550 and Db1300. arch/mips/Kconfig | 2 + arch/mips/alchemy/Kconfig | 50 +-- arch/mips/alchemy/common/Makefile | 4 +- arch/mips/alchemy/common/dbdma.c | 203 ++++----- arch/mips/alchemy/common/dma.c | 72 ++-- arch/mips/alchemy/common/pci.c | 104 ---- arch/mips/alchemy/common/platform.c | 340 +++----------- arch/mips/alchemy/common/power.c | 42 -- arch/mips/alchemy/common/setup.c | 6 +- arch/mips/alchemy/common/usb.c | 337 +++++++++++++ arch/mips/alchemy/devboards/db1200/platform.c | 153 +++++-- arch/mips/alchemy/devboards/db1x00/board_setup.c | 28 +- arch/mips/alchemy/devboards/db1x00/platform.c | 199 +++++++- arch/mips/alchemy/devboards/pb1100/platform.c | 49 ++- arch/mips/alchemy/devboards/pb1200/platform.c | 190 +++++++- arch/mips/alchemy/devboards/pb1500/board_setup.c | 33 +- arch/mips/alchemy/devboards/pb1500/platform.c | 71 +++- arch/mips/alchemy/devboards/pb1550/board_setup.c | 6 - arch/mips/alchemy/devboards/pb1550/platform.c | 119 ++++- arch/mips/alchemy/gpr/board_setup.c | 12 - arch/mips/alchemy/gpr/platform.c | 47 ++ arch/mips/alchemy/mtx-1/board_setup.c | 40 -- arch/mips/alchemy/mtx-1/platform.c | 62 +++ arch/mips/alchemy/xxs1500/board_setup.c | 8 - arch/mips/alchemy/xxs1500/platform.c | 12 +- arch/mips/include/asm/mach-au1x00/au1000.h | 559 ++++++++-------------- arch/mips/include/asm/mach-au1x00/au1xxx.h | 43 -- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 114 +++--- arch/mips/include/asm/mach-au1x00/au1xxx_ide.h | 1 + arch/mips/include/asm/mach-au1x00/au1xxx_psc.h | 26 - arch/mips/include/asm/mach-db1x00/db1200.h | 2 - arch/mips/include/asm/mach-db1x00/db1x00.h | 16 +- arch/mips/include/asm/mach-pb1x00/pb1200.h | 18 +- arch/mips/include/asm/mach-pb1x00/pb1550.h | 16 +- arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-au1000.c | 43 -- arch/mips/pci/ops-au1000.c | 308 ------------ arch/mips/pci/pci-alchemy.c | 516 ++++++++++++++++++++ drivers/i2c/busses/Kconfig | 2 +- drivers/i2c/busses/i2c-au1550.c | 2 +- drivers/ide/Kconfig | 6 +- drivers/ide/au1xxx-ide.c | 46 +- drivers/mmc/host/Kconfig | 2 +- drivers/mtd/nand/Kconfig | 2 +- drivers/mtd/nand/au1550nd.c | 6 +- drivers/net/irda/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/usb/Kconfig | 1 - drivers/usb/host/ehci-au1xxx.c | 77 +--- drivers/usb/host/ehci-hcd.c | 2 +- drivers/usb/host/ohci-au1xxx.c | 110 +---- drivers/video/Kconfig | 4 +- sound/mips/Kconfig | 2 +- sound/soc/au1x/Kconfig | 2 +- 54 files changed, 2191 insertions(+), 1931 deletions(-) delete mode 100644 arch/mips/alchemy/common/pci.c create mode 100644 arch/mips/alchemy/common/usb.c delete mode 100644 arch/mips/include/asm/mach-au1x00/au1xxx.h delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.c -- 1.7.6 From manuel.lauss@googlemail.com Fri Aug 12 11:39:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 11:40:32 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:50901 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491155Ab1HLJj4 (ORCPT ); Fri, 12 Aug 2011 11:39:56 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so2860465fxd.36 for ; Fri, 12 Aug 2011 02:39:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=+JFJw4zya601KYmdMeN8rAlOr4ia6iPHviaT90n6UFs=; b=kmT7zCamjUGTFcytPompZYc46LcZDTb0GT35ULw2U52X1r7SC+VSdoVuL76ryBSONK pbZ0TWtKy7bkuGXrcNnuWwxlO/DD6YlVN8V7J17fBatyr6VrFKymB0UY8yMD7wCI/1D3 z6cpMA8vxMGKY10Xf6rWj9v+FmHYR7F+m7j+g= Received: by 10.223.22.8 with SMTP id l8mr978227fab.105.1313141996398; Fri, 12 Aug 2011 02:39:56 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id s14sm467338fah.29.2011.08.12.02.39.54 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 02:39:55 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 3/8] MIPS: Alchemy: more base address cleanup Date: Fri, 12 Aug 2011 11:39:40 +0200 Message-Id: <1313141985-5830-4-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30856 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9261 Content-Length: 25148 Lines: 639 remove all redundant peripheral base address defines, fix all affected boards and drivers. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 12 ++-- arch/mips/alchemy/devboards/db1200/platform.c | 52 ++++++------- arch/mips/alchemy/devboards/db1x00/platform.c | 40 ++++----- arch/mips/alchemy/devboards/pb1100/platform.c | 20 ++--- arch/mips/alchemy/devboards/pb1200/platform.c | 42 +++++----- arch/mips/alchemy/devboards/pb1500/platform.c | 22 +++--- arch/mips/alchemy/devboards/pb1550/platform.c | 40 ++++----- arch/mips/alchemy/xxs1500/platform.c | 12 ++-- arch/mips/include/asm/mach-au1x00/au1000.h | 103 ++++++------------------ arch/mips/include/asm/mach-au1x00/au1xxx_psc.h | 26 ------ arch/mips/include/asm/mach-db1x00/db1x00.h | 8 +- arch/mips/include/asm/mach-pb1x00/pb1200.h | 8 +- arch/mips/include/asm/mach-pb1x00/pb1550.h | 8 +- 13 files changed, 146 insertions(+), 247 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 910a3bd..bf1ac41 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -194,8 +194,8 @@ static void __init alchemy_setup_usb(int ctype) #ifdef CONFIG_FB_AU1100 static struct resource au1100_lcd_resources[] = { [0] = { - .start = LCD_PHYS_ADDR, - .end = LCD_PHYS_ADDR + 0x800 - 1, + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -223,8 +223,8 @@ static struct platform_device au1100_lcd_device = { static struct resource au1200_lcd_resources[] = { [0] = { - .start = LCD_PHYS_ADDR, - .end = LCD_PHYS_ADDR + 0x800 - 1, + .start = AU1200_LCD_PHYS_ADDR, + .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -328,8 +328,8 @@ static struct platform_device au1200_mmc1_device = { #ifdef SMBUS_PSC_BASE static struct resource pbdb_smbus_resources[] = { { - .start = CPHYSADDR(SMBUS_PSC_BASE), - .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff), + .start = SMBUS_PSC_BASE, + .end = SMBUS_PSC_BASE + 0xfff, .flags = IORESOURCE_MEM, }, }; diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index fbb5593..95c7327 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -343,8 +343,8 @@ struct au1xmmc_platform_data au1xmmc_platdata[] = { static struct resource au1200_psc0_res[] = { [0] = { - .start = PSC0_PHYS_ADDR, - .end = PSC0_PHYS_ADDR + 0x000fffff, + .start = AU1550_PSC0_PHYS_ADDR, + .end = AU1550_PSC0_PHYS_ADDR + 0xfff, .flags = IORESOURCE_MEM, }, [1] = { @@ -401,8 +401,8 @@ static struct platform_device db1200_spi_dev = { static struct resource au1200_psc1_res[] = { [0] = { - .start = PSC1_PHYS_ADDR, - .end = PSC1_PHYS_ADDR + 0x000fffff, + .start = AU1550_PSC1_PHYS_ADDR, + .end = AU1550_PSC1_PHYS_ADDR + 0xfff, .flags = IORESOURCE_MEM, }, [1] = { @@ -510,32 +510,28 @@ static int __init db1200_dev_init(void) /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ __raw_writel(PSC_SEL_CLK_SERCLK, - (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - DB1200_PC0_INT, - DB1200_PC0_INSERT_INT, - /*DB1200_PC0_STSCHG_INT*/0, - DB1200_PC0_EJECT_INT, - 0); - - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000, - PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, - PCMCIA_MEM_PHYS_ADDR + 0x004000000, - PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, - PCMCIA_IO_PHYS_ADDR + 0x004000000, - PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, - DB1200_PC1_INT, - DB1200_PC1_INSERT_INT, - /*DB1200_PC1_STSCHG_INT*/0, - DB1200_PC1_EJECT_INT, - 1); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + DB1200_PC0_INT, DB1200_PC0_INSERT_INT, + /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + DB1200_PC1_INT, DB1200_PC1_INSERT_INT, + /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(64 << 20, 2, swapped); diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 978d5ab..ef8017f 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -88,29 +88,25 @@ static int __init db1xxx_dev_init(void) { #ifdef DB1XXX_HAS_PCMCIA - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - DB1XXX_PCMCIA_CARD0, - DB1XXX_PCMCIA_CD0, - /*DB1XXX_PCMCIA_STSCHG0*/0, - 0, - 0); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0, + /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0); - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000, - PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, - PCMCIA_MEM_PHYS_ADDR + 0x004000000, - PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, - PCMCIA_IO_PHYS_ADDR + 0x004000000, - PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, - DB1XXX_PCMCIA_CARD1, - DB1XXX_PCMCIA_CD1, - /*DB1XXX_PCMCIA_STSCHG1*/0, - 0, - 1); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, + /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); #endif db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); return 0; diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c index 2c8dc29..8a4e733 100644 --- a/arch/mips/alchemy/devboards/pb1100/platform.c +++ b/arch/mips/alchemy/devboards/pb1100/platform.c @@ -30,17 +30,15 @@ static int __init pb1100_dev_init(void) int swapped; /* PCMCIA. single socket, identical to Pb1500 */ - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1100_GPIO11_INT, /* card */ - AU1100_GPIO9_INT, /* insert */ - /*AU1100_GPIO10_INT*/0, /* stschg */ - 0, /* eject */ - 0); /* id */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */ + /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; db1x_register_norflash(64 * 1024 * 1024, 4, swapped); diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 3ef2dce..c52809d 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -170,29 +170,25 @@ static int __init board_register_devices(void) { int swapped; - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - PB1200_PC0_INT, - PB1200_PC0_INSERT_INT, - /*PB1200_PC0_STSCHG_INT*/0, - PB1200_PC0_EJECT_INT, - 0); - - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000, - PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, - PCMCIA_MEM_PHYS_ADDR + 0x008000000, - PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, - PCMCIA_IO_PHYS_ADDR + 0x008000000, - PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, - PB1200_PC1_INT, - PB1200_PC1_INSERT_INT, - /*PB1200_PC1_STSCHG_INT*/0, - PB1200_PC1_EJECT_INT, - 1); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + PB1200_PC0_INT, PB1200_PC0_INSERT_INT, + /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, + PB1200_PC1_INT, PB1200_PC1_INSERT_INT, + /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 2, swapped); diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c index d443bc7..42b0e6b 100644 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -28,18 +28,16 @@ static int __init pb1500_dev_init(void) { int swapped; - /* PCMCIA. single socket, identical to Pb1500 */ - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1500_GPIO11_INT, /* card */ - AU1500_GPIO9_INT, /* insert */ - /*AU1500_GPIO10_INT*/0, /* stschg */ - 0, /* eject */ - 0); /* id */ + /* PCMCIA. single socket, identical to Pb1100 */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */ + /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; db1x_register_norflash(64 * 1024 * 1024, 4, swapped); diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c index d7150d0..87c79b7 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -37,29 +37,23 @@ static int __init pb1550_dev_init(void) * drivers are used to shared irqs and b) statuschange isn't really use- * ful anyway. */ - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, - PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_MEM_PHYS_ADDR, - PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - PCMCIA_IO_PHYS_ADDR, - PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1550_GPIO201_205_INT, - AU1550_GPIO0_INT, - 0, - 0, - 0); - - db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000, - PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, - PCMCIA_MEM_PHYS_ADDR + 0x008000000, - PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, - PCMCIA_IO_PHYS_ADDR + 0x008000000, - PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, - AU1550_GPIO201_205_INT, - AU1550_GPIO1_INT, - 0, - 0, - 1); + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, + AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 4, swapped); diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c index e87c45c..06a3a45 100644 --- a/arch/mips/alchemy/xxs1500/platform.c +++ b/arch/mips/alchemy/xxs1500/platform.c @@ -27,20 +27,20 @@ static struct resource xxs1500_pcmcia_res[] = { { .name = "pcmcia-io", .flags = IORESOURCE_MEM, - .start = PCMCIA_IO_PHYS_ADDR, - .end = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, + .start = AU1000_PCMCIA_IO_PHYS_ADDR, + .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, }, { .name = "pcmcia-attr", .flags = IORESOURCE_MEM, - .start = PCMCIA_ATTR_PHYS_ADDR, - .end = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + .start = AU1000_PCMCIA_ATTR_PHYS_ADDR, + .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, }, { .name = "pcmcia-mem", .flags = IORESOURCE_MEM, - .start = PCMCIA_MEM_PHYS_ADDR, - .end = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + .start = AU1000_PCMCIA_MEM_PHYS_ADDR, + .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, }, }; diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 86d39c3..bcf3d1e 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -698,114 +698,61 @@ enum soc_au1200_ints { #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ +#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ +#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ +#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ +#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ +#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */ #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ +#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */ +#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ +#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ +#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ +#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ +#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ +#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ +#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ +#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ +#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ +#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ +#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ +#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ +#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ +#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ +#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ +#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ +#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ +#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ +#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ -#ifdef CONFIG_SOC_AU1000 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define IRDA_PHYS_ADDR 0x10300000 -#define SSI0_PHYS_ADDR 0x11600000 -#define SSI1_PHYS_ADDR 0x11680000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/********************************************************************/ - -#ifdef CONFIG_SOC_AU1500 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define PCI_PHYS_ADDR 0x14005000 -#define PCI_MEM_PHYS_ADDR 0x400000000ULL -#define PCI_IO_PHYS_ADDR 0x500000000ULL -#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL -#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/********************************************************************/ - -#ifdef CONFIG_SOC_AU1100 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define IRDA_PHYS_ADDR 0x10300000 -#define SSI0_PHYS_ADDR 0x11600000 -#define SSI1_PHYS_ADDR 0x11680000 -#define LCD_PHYS_ADDR 0x15000000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/***********************************************************************/ - -#ifdef CONFIG_SOC_AU1550 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define PCI_PHYS_ADDR 0x14005000 -#define PE_PHYS_ADDR 0x14008000 -#define PSC0_PHYS_ADDR 0x11A00000 -#define PSC1_PHYS_ADDR 0x11B00000 -#define PSC2_PHYS_ADDR 0x10A00000 -#define PSC3_PHYS_ADDR 0x10B00000 -#define PCI_MEM_PHYS_ADDR 0x400000000ULL -#define PCI_IO_PHYS_ADDR 0x500000000ULL -#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL -#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/***********************************************************************/ - -#ifdef CONFIG_SOC_AU1200 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define AES_PHYS_ADDR 0x10300000 -#define CIM_PHYS_ADDR 0x14004000 -#define PSC0_PHYS_ADDR 0x11A00000 -#define PSC1_PHYS_ADDR 0x11B00000 -#define LCD_PHYS_ADDR 0x15000000 -#define SWCNT_PHYS_ADDR 0x1110010C -#define MAEFE_PHYS_ADDR 0x14012000 -#define MAEBE_PHYS_ADDR 0x14010000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - /* Static Bus Controller */ #define MEM_STCFG0 0xB4001000 #define MEM_STTIME0 0xB4001004 diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h index 892b7f1..8e2fa67 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h @@ -33,19 +33,6 @@ #ifndef _AU1000_PSC_H_ #define _AU1000_PSC_H_ -/* The PSC base addresses. */ -#ifdef CONFIG_SOC_AU1550 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#define PSC2_BASE_ADDR 0xb0a00000 -#define PSC3_BASE_ADDR 0xb0b00000 -#endif - -#ifdef CONFIG_SOC_AU1200 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#endif - /* * The PSC select and control registers are common to all protocols. */ @@ -80,19 +67,6 @@ #define PSC_AC97GPO_OFFSET 0x00000028 #define PSC_AC97GPI_OFFSET 0x0000002c -#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) -#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) -#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) -#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) -#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) -#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) -#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) -#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) -#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) -#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) -#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) -#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) - /* AC97 Config Register. */ #define PSC_AC97CFG_RT_MASK (3 << 30) #define PSC_AC97CFG_RT_FIFO1 (0 << 30) diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index a919dac..115cc7c 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -36,10 +36,10 @@ #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define SMBUS_PSC_BASE PSC2_BASE_ADDR -#define I2S_PSC_BASE PSC3_BASE_ADDR +#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR +#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR +#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR +#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR #define NAND_PHYS_ADDR 0x20000000 diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index fce4332..0ecff1c 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -37,14 +37,14 @@ * SPI and SMB are muxed on the Pb1200 board. * Refer to board documentation. */ -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define SMBUS_PSC_BASE PSC0_BASE_ADDR +#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR +#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR /* * AC97 and I2S are muxed on the Pb1200 board. * Refer to board documentation. */ -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define I2S_PSC_BASE PSC1_BASE_ADDR +#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR +#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR #define BCSR_SYSTEM_VDDI 0x001F diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h index f835c88..0b0f462 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h @@ -35,10 +35,10 @@ #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define SMBUS_PSC_BASE PSC2_BASE_ADDR -#define I2S_PSC_BASE PSC3_BASE_ADDR +#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR +#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR +#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR +#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR /* * Timing values as described in databook, * ns value stripped of -- 1.7.6 From manuel.lauss@googlemail.com Fri Aug 12 11:39:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 11:41:00 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:50901 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491181Ab1HLJj5 (ORCPT ); Fri, 12 Aug 2011 11:39:57 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so2860465fxd.36 for ; Fri, 12 Aug 2011 02:39:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=oOZ0R0c5djfZhiq58I3J73yxmmzNqBL8EevLzyp6600=; b=trkBPKtPrIG+DBcUnf9XogkmQIuBuCQbsEnB7jWA8lApoRjTFLjRpYXMxFfBGbCSFj S9gLahKvbs7JMr8Ku5Mp+DmO17JsSTZehWo7MytfW+x5l1odseCsbpXzSk4olfOtCX+B RCMbfFp+maMwMaHHLRBqOHd+NOI9G+MBCB1FI= Received: by 10.223.53.77 with SMTP id l13mr966032fag.93.1313141997748; Fri, 12 Aug 2011 02:39:57 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id s14sm467338fah.29.2011.08.12.02.39.56 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 02:39:57 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss , linux-ide@vger.kernel.org Subject: [PATCH 4/8] MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dep Date: Fri, 12 Aug 2011 11:39:41 +0200 Message-Id: <1313141985-5830-5-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30857 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9262 Content-Length: 7100 Lines: 204 au1xxx-ide uses defines from the pb1200/db1200 headers: get DBDMA ID through platform resource information, hardcode register spacing. The only 2 users of this driver (and the only boards it can really work on realiably) use the same register layout. Cc: linux-ide@vger.kernel.org Signed-off-by: Manuel Lauss --- I'd like for this to go through the MIPS tree, as other changes in it depend on it. arch/mips/alchemy/devboards/db1200/platform.c | 7 +++- arch/mips/alchemy/devboards/pb1200/platform.c | 8 ++++- arch/mips/include/asm/mach-au1x00/au1xxx_ide.h | 1 + arch/mips/include/asm/mach-db1x00/db1200.h | 2 - arch/mips/include/asm/mach-pb1x00/pb1200.h | 2 - drivers/ide/au1xxx-ide.c | 44 ++++++++++++++---------- 6 files changed, 40 insertions(+), 24 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index 95c7327..6fd070d 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -213,7 +213,12 @@ static struct resource db1200_ide_res[] = { .start = DB1200_IDE_INT, .end = DB1200_IDE_INT, .flags = IORESOURCE_IRQ, - } + }, + [2] = { + .start = DSCR_CMD0_DMA_REQ1, + .end = DSCR_CMD0_DMA_REQ1, + .flags = IORESOURCE_DMA, + }, }; static u64 ide_dmamask = DMA_BIT_MASK(32); diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index c52809d..6ac0494 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -26,6 +26,7 @@ #include #include +#include #include #include "../platform.h" @@ -115,7 +116,12 @@ static struct resource ide_resources[] = { .start = IDE_INT, .end = IDE_INT, .flags = IORESOURCE_IRQ - } + }, + [2] = { + .start = DSCR_CMD0_DMA_REQ1, + .end = DSCR_CMD0_DMA_REQ1, + .flags = IORESOURCE_DMA, + }, }; static u64 ide_dmamask = DMA_BIT_MASK(32); diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h index 5656c72..e306384 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h @@ -58,6 +58,7 @@ typedef struct { #endif int irq; u32 regbase; + int ddma_id; } _auide_hwif; /******************************************************************************/ diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 3404248..7a39657 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -46,8 +46,6 @@ #define IDE_PHYS_ADDR 0x18800000 #define IDE_REG_SHIFT 5 -#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 -#define IDE_RQSIZE 128 #define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR #define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index 0ecff1c..56865e9 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -76,8 +76,6 @@ #define IDE_REG_SHIFT 5 #define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) #define IDE_INT PB1200_IDE_INT -#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 -#define IDE_RQSIZE 128 #define NAND_PHYS_ADDR 0x1C000000 diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c index b26c234..c778373 100644 --- a/drivers/ide/au1xxx-ide.c +++ b/drivers/ide/au1xxx-ide.c @@ -43,6 +43,10 @@ #define DRV_NAME "au1200-ide" #define DRV_AUTHOR "Enrico Walther / Pete Popov " +#ifndef IDE_REG_SHIFT +#define IDE_REG_SHIFT 5 +#endif + /* enable the burstmode in the dbdma */ #define IDE_AU1XXX_BURSTMODE 1 @@ -317,10 +321,11 @@ static void auide_ddma_rx_callback(int irq, void *param) } #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ -static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) +static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, + u32 devwidth, u32 flags, u32 regbase) { dev->dev_id = dev_id; - dev->dev_physaddr = (u32)IDE_PHYS_ADDR; + dev->dev_physaddr = CPHYSADDR(regbase); dev->dev_intlevel = 0; dev->dev_intpolarity = 0; dev->dev_tsize = tsize; @@ -344,7 +349,7 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) dbdev_tab_t source_dev_tab, target_dev_tab; u32 dev_id, tsize, devwidth, flags; - dev_id = IDE_DDMA_REQ; + dev_id = hwif->ddma_id; tsize = 8; /* 1 */ devwidth = 32; /* 16 */ @@ -356,20 +361,17 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) #endif /* setup dev_tab for tx channel */ - auide_init_dbdma_dev( &source_dev_tab, - dev_id, - tsize, devwidth, DEV_FLAGS_OUT | flags); + auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, + DEV_FLAGS_OUT | flags, auide->regbase); auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - auide_init_dbdma_dev( &source_dev_tab, - dev_id, - tsize, devwidth, DEV_FLAGS_IN | flags); + auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, + DEV_FLAGS_IN | flags, auide->regbase); auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); /* We also need to add a target device for the DMA */ - auide_init_dbdma_dev( &target_dev_tab, - (u32)DSCR_CMD0_ALWAYS, - tsize, devwidth, DEV_FLAGS_ANYUSE); + auide_init_dbdma_dev(&target_dev_tab, (u32)DSCR_CMD0_ALWAYS, tsize, + devwidth, DEV_FLAGS_ANYUSE, auide->regbase); auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); /* Get a channel for TX */ @@ -411,14 +413,12 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) #endif /* setup dev_tab for tx channel */ - auide_init_dbdma_dev( &source_dev_tab, - (u32)DSCR_CMD0_ALWAYS, - 8, 32, DEV_FLAGS_OUT | flags); + auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, + DEV_FLAGS_OUT | flags, auide->regbase); auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - auide_init_dbdma_dev( &source_dev_tab, - (u32)DSCR_CMD0_ALWAYS, - 8, 32, DEV_FLAGS_IN | flags); + auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, + DEV_FLAGS_IN | flags, auide->regbase); auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); /* Get a channel for TX */ @@ -540,6 +540,14 @@ static int au_ide_probe(struct platform_device *dev) goto out; } + res = platform_get_resource(dev, IORESOURCE_DMA, 0); + if (!res) { + pr_debug("%s: no DDMA ID resource\n", DRV_NAME); + ret = -ENODEV; + goto out; + } + ahwif->ddma_id = res->start; + memset(&hw, 0, sizeof(hw)); auide_setup_ports(&hw, ahwif); hw.irq = ahwif->irq; -- 1.7.6 From manuel.lauss@googlemail.com Fri Aug 12 11:39:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 11:41:30 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:33383 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491204Ab1HLJj6 (ORCPT ); Fri, 12 Aug 2011 11:39:58 +0200 Received: by fxd20 with SMTP id 20so2860485fxd.36 for ; Fri, 12 Aug 2011 02:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=h2zl1cyyi7mkIWohv6iAeKp91chPyCn3+OD8z0EMuW4=; b=g6AyXSL8B7azCeLJ/LtcOitkbr751XxASlLBUindvAZAHYH6+gufr8lgLUyXpCqKGP Wf0IJoIwdl4q/6/Zzc4e4tM7xNZ3+yZauxEprCc4IEDHnas0hlfJssG+eK9tF9lzfR8e 0njjGVSOqIIKKscIiMDMPOrqUqm+ZTzuWsBLs= Received: by 10.223.76.137 with SMTP id c9mr1007358fak.62.1313141992794; Fri, 12 Aug 2011 02:39:52 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id s14sm467338fah.29.2011.08.12.02.39.50 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 02:39:51 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss , linux-usb@vger.kernel.org, Greg Kroah-Hartman (USB glue parts) Subject: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access Date: Fri, 12 Aug 2011 11:39:38 +0200 Message-Id: <1313141985-5830-2-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30858 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9264 Content-Length: 28385 Lines: 929 Alchemy chips have one or more registers which control access to the usb blocks as well as PHY configuration. I don't want the OHCI/EHCI glues to know about the different registers and bits; new arch code hides the gory details of USB configuration from them. Cc: linux-usb@vger.kernel.org Cc: Greg Kroah-Hartman (USB glue parts) Signed-off-by: Manuel Lauss --- CC'ed Greg for an Ack on the USB glue parts. I'd like this to go through the MIPS tree since other changes in it depend on it. arch/mips/alchemy/common/Makefile | 2 +- arch/mips/alchemy/common/dma.c | 12 +- arch/mips/alchemy/common/power.c | 42 ---- arch/mips/alchemy/common/usb.c | 337 ++++++++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/au1000.h | 84 ++------ drivers/usb/host/ehci-au1xxx.c | 77 +------ drivers/usb/host/ohci-au1xxx.c | 110 +-------- 7 files changed, 382 insertions(+), 282 deletions(-) create mode 100644 arch/mips/alchemy/common/usb.c diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 62f0d39..31728e0 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -6,7 +6,7 @@ # obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ - sleeper.o dma.o dbdma.o + sleeper.o dma.o dbdma.o usb.o obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c index 347980e..6652a23 100644 --- a/arch/mips/alchemy/common/dma.c +++ b/arch/mips/alchemy/common/dma.c @@ -88,12 +88,12 @@ static const struct dma_dev { { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */ { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */ { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */ - { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ - { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ - { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ - { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ - { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ - { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ + { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ + { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ + { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ + { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ + { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ + { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */ { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */ { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */ diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index 9ec8559..bdd6651 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -47,7 +47,6 @@ * We only have to save/restore registers that aren't otherwise * done as part of a driver pm_* function. */ -static unsigned int sleep_usb[2]; static unsigned int sleep_sys_clocks[5]; static unsigned int sleep_sys_pinfunc; static unsigned int sleep_static_memctlr[4][3]; @@ -55,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3]; static void save_core_regs(void) { -#ifndef CONFIG_SOC_AU1200 - /* Shutdown USB host/device. */ - sleep_usb[0] = au_readl(USB_HOST_CONFIG); - - /* There appears to be some undocumented reset register.... */ - au_writel(0, 0xb0100004); - au_sync(); - au_writel(0, USB_HOST_CONFIG); - au_sync(); - - sleep_usb[1] = au_readl(USBD_ENABLE); - au_writel(0, USBD_ENABLE); - au_sync(); - -#else /* AU1200 */ - - /* enable access to OTG mmio so we can save OTG CAP/MUX. - * FIXME: write an OTG driver and move this stuff there! - */ - au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); - au_sync(); - sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ - sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ -#endif - /* Clocks and PLLs. */ sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); @@ -123,22 +97,6 @@ static void restore_core_regs(void) au_writel(sleep_sys_pinfunc, SYS_PINFUNC); au_sync(); -#ifndef CONFIG_SOC_AU1200 - au_writel(sleep_usb[0], USB_HOST_CONFIG); - au_writel(sleep_usb[1], USBD_ENABLE); - au_sync(); -#else - /* enable access to OTG memory */ - au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); - au_sync(); - - /* restore OTG caps and port mux. */ - au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ - au_sync(); - au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ - au_sync(); -#endif - /* Restore the static memory controller configuration. */ au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c new file mode 100644 index 0000000..b4192c9 --- /dev/null +++ b/arch/mips/alchemy/common/usb.c @@ -0,0 +1,337 @@ +/* + * USB block power/access management abstraction. + * + * Au1000+: The OHCI block control register is at the far end of the OHCI memory + * area. Au1550 has OHCI on different base address. No need to handle + * UDC here. + * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG + * as well as the PHY for EHCI and UDC. + * + */ + +#include +#include +#include +#include +#include +#include + +/* control register offsets */ +#define AU1000_OHCICFG 0x7fffc +#define AU1550_OHCICFG 0x07ffc +#define AU1200_USBCFG 0x04 + +/* Au1000 USB block config bits */ +#define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */ +#define USBHEN_CE (1 << 3) /* OHCI block clock enable */ +#define USBHEN_E (1 << 2) /* OHCI block enable */ +#define USBHEN_C (1 << 1) /* OHCI block coherency bit */ +#define USBHEN_BE (1 << 0) /* OHCI Big-Endian */ + +/* Au1200 USB config bits */ +#define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */ +#define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */ +#define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */ +#define USBCFG_SSD (1 << 23) /* serial short detect en */ +#define USBCFG_PPE (1 << 19) /* HS PHY PLL */ +#define USBCFG_UCE (1 << 18) /* UDC clock enable */ +#define USBCFG_ECE (1 << 17) /* EHCI clock enable */ +#define USBCFG_OCE (1 << 16) /* OHCI clock enable */ +#define USBCFG_FLA(x) (((x) & 0x3f) << 8) +#define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */ +#define USBCFG_GME (1 << 6) /* OTG mem access */ +#define USBCFG_DBE (1 << 5) /* UDC busmaster enable */ +#define USBCFG_DME (1 << 4) /* UDC mem enable */ +#define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */ +#define USBCFG_EME (1 << 2) /* EHCI mem enable */ +#define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */ +#define USBCFG_OME (1 << 0) /* OHCI mem enable */ +#define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\ + USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \ + USBCFG_GME | USBCFG_DBE | USBCFG_DME | \ + USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \ + USBCFG_OME) + + +static DEFINE_SPINLOCK(alchemy_usb_lock); + + +static inline void __au1200_ohci_control(void __iomem *base, int enable) +{ + unsigned long r = __raw_readl(base + AU1200_USBCFG); + if (enable) { + __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG); + wmb(); + udelay(2000); + } else { + __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG); + wmb(); + udelay(1000); + } +} + +static inline void __au1200_ehci_control(void __iomem *base, int enable) +{ + unsigned long r = __raw_readl(base + AU1200_USBCFG); + if (enable) { + __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG); + wmb(); + udelay(1000); + } else { + if (!(r & USBCFG_UCE)) /* UDC also off? */ + r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */ + __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG); + wmb(); + udelay(1000); + } +} + +static inline void __au1200_udc_control(void __iomem *base, int enable) +{ + unsigned long r = __raw_readl(base + AU1200_USBCFG); + if (enable) { + __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG); + wmb(); + } else { + if (!(r & USBCFG_ECE)) /* EHCI also off? */ + r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */ + __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG); + wmb(); + } +} + +static inline int au1200_coherency_bug(void) +{ +#if defined(CONFIG_DMA_COHERENT) + /* Au1200 AB USB does not support coherent memory */ + if (!(read_c0_prid() & 0xff)) { + printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n"); + printk(KERN_INFO "Au1200 USB: update your board or re-configure" + " the kernel\n"); + return -ENODEV; + } +#endif + return 0; +} + +static inline int au1200_usb_control(int block, int enable) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR); + int ret = 0; + + switch (block) { + case ALCHEMY_USB_OHCI0: + ret = au1200_coherency_bug(); + if (ret && enable) + goto out; + __au1200_ohci_control(base, enable); + break; + case ALCHEMY_USB_UDC0: + __au1200_udc_control(base, enable); + break; + case ALCHEMY_USB_EHCI0: + ret = au1200_coherency_bug(); + if (ret && enable) + goto out; + __au1200_ehci_control(base, enable); + break; + default: + ret = -ENODEV; + } +out: + return ret; +} + + +/* initialize USB block(s) to a known working state */ +static inline void au1200_usb_init(void) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR); + __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG); + wmb(); + udelay(1000); +} + +static inline void au1000_usb_init(unsigned long rb, int reg) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); + unsigned long r = __raw_readl(base); + +#if defined(__BIG_ENDIAN) + r |= USBHEN_BE; +#endif + r |= USBHEN_C; + + __raw_writel(r, base); + wmb(); + udelay(1000); +} + + +static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(rb); + unsigned long r = __raw_readl(base + creg); + + if (enable) { + __raw_writel(r | USBHEN_CE, base + creg); + wmb(); + udelay(1000); + __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg); + wmb(); + udelay(1000); + + /* wait for reset complete (read reg twice: au1500 erratum) */ + while (__raw_readl(base + creg), + !(__raw_readl(base + creg) & USBHEN_RD)) + udelay(1000); + } else { + __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg); + wmb(); + } +} + +static inline int au1000_usb_control(int block, int enable, unsigned long rb, + int creg) +{ + int ret = 0; + + switch (block) { + case ALCHEMY_USB_OHCI0: + __au1xx0_ohci_control(enable, rb, creg); + break; + default: + ret = -ENODEV; + } + return ret; +} + +/* + * alchemy_usb_control - control Alchemy on-chip USB blocks + * @block: USB block to target + * @enable: set 1 to enable a block, 0 to disable + */ +int alchemy_usb_control(int block, int enable) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&alchemy_usb_lock, flags); + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + ret = au1000_usb_control(block, enable, + AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); + break; + case ALCHEMY_CPU_AU1550: + ret = au1000_usb_control(block, enable, + AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); + break; + case ALCHEMY_CPU_AU1200: + ret = au1200_usb_control(block, enable); + break; + default: + ret = -ENODEV; + } + spin_unlock_irqrestore(&alchemy_usb_lock, flags); + return ret; +} +EXPORT_SYMBOL_GPL(alchemy_usb_control); + + +static unsigned long alchemy_usb_pmdata[2]; + +static void au1000_usb_pm(unsigned long br, int creg, int susp) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(br); + + if (susp) { + alchemy_usb_pmdata[0] = __raw_readl(base + creg); + /* There appears to be some undocumented reset register.... */ + __raw_writel(0, base + 0x04); + wmb(); + __raw_writel(0, base + creg); + wmb(); + } else { + __raw_writel(alchemy_usb_pmdata[0], base + creg); + wmb(); + } +} + +static void au1200_usb_pm(int susp) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR); + if (susp) { + /* save OTG_CAP/MUX registers which indicate port routing */ + /* FIXME: write an OTG driver to do that */ + alchemy_usb_pmdata[0] = __raw_readl(base + 0x00); + alchemy_usb_pmdata[1] = __raw_readl(base + 0x04); + } else { + /* restore access to all MMIO areas */ + au1200_usb_init(); + + /* restore OTG_CAP/MUX registers */ + __raw_writel(alchemy_usb_pmdata[0], base + 0x00); + __raw_writel(alchemy_usb_pmdata[1], base + 0x04); + wmb(); + } +} + +static void alchemy_usb_pm(int susp) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp); + break; + case ALCHEMY_CPU_AU1550: + au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp); + break; + case ALCHEMY_CPU_AU1200: + au1200_usb_pm(susp); + break; + } +} + +static int alchemy_usb_suspend(void) +{ + alchemy_usb_pm(1); + return 0; +} + +static void alchemy_usb_resume(void) +{ + alchemy_usb_pm(0); +} + +static struct syscore_ops alchemy_usb_pm_ops = { + .suspend = alchemy_usb_suspend, + .resume = alchemy_usb_resume, +}; + +static int __init alchemy_usb_init(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); + break; + case ALCHEMY_CPU_AU1550: + au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); + break; + case ALCHEMY_CPU_AU1200: + au1200_usb_init(); + break; + } + + register_syscore_ops(&alchemy_usb_pm_ops); + + return 0; +} +arch_initcall(alchemy_usb_init); diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index f260ebe..73e0d79 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -245,6 +245,15 @@ void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); void au_sleep(void); +/* USB: arch/mips/alchemy/common/usb.c */ +enum alchemy_usb_block { + ALCHEMY_USB_OHCI0, + ALCHEMY_USB_UDC0, + ALCHEMY_USB_EHCI0, + ALCHEMY_USB_OTG0, +}; +int alchemy_usb_control(int block, int enable); + /* SOC Interrupt numbers */ @@ -687,7 +696,8 @@ enum soc_au1200_ints { */ #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ -#define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */ +#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ +#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ @@ -710,12 +720,17 @@ enum soc_au1200_ints { #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ +#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ +#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ +#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ +#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ +#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ +#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ #ifdef CONFIG_SOC_AU1000 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x10100000 #define IRDA_PHYS_ADDR 0x10300000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 @@ -729,7 +744,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1500 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x10100000 #define PCI_PHYS_ADDR 0x14005000 #define PCI_MEM_PHYS_ADDR 0x400000000ULL #define PCI_IO_PHYS_ADDR 0x500000000ULL @@ -745,7 +759,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1100 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x10100000 #define IRDA_PHYS_ADDR 0x10300000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 @@ -760,7 +773,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1550 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x14020000 #define PCI_PHYS_ADDR 0x14005000 #define PE_PHYS_ADDR 0x14008000 #define PSC0_PHYS_ADDR 0x11A00000 @@ -783,8 +795,6 @@ enum soc_au1200_ints { #define STATIC_MEM_PHYS_ADDR 0x14001000 #define AES_PHYS_ADDR 0x10300000 #define CIM_PHYS_ADDR 0x14004000 -#define USBM_PHYS_ADDR 0x14020000 -#define USBH_PHYS_ADDR 0x14020100 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 #define LCD_PHYS_ADDR 0x15000000 @@ -868,21 +878,6 @@ enum soc_au1200_ints { #define USB_EHCI_LEN 0x100 #define USB_UDC_BASE 0x14022000 #define USB_UDC_LEN 0x2000 -#define USB_MSR_BASE 0xB4020000 -#define USB_MSR_MCFG 4 -#define USBMSRMCFG_OMEMEN 0 -#define USBMSRMCFG_OBMEN 1 -#define USBMSRMCFG_EMEMEN 2 -#define USBMSRMCFG_EBMEN 3 -#define USBMSRMCFG_DMEMEN 4 -#define USBMSRMCFG_DBMEN 5 -#define USBMSRMCFG_GMEMEN 6 -#define USBMSRMCFG_OHCCLKEN 16 -#define USBMSRMCFG_EHCCLKEN 17 -#define USBMSRMCFG_UDCCLKEN 18 -#define USBMSRMCFG_PHYPLLEN 19 -#define USBMSRMCFG_RDCOMB 30 -#define USBMSRMCFG_PFEN 31 #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT @@ -963,51 +958,6 @@ enum soc_au1200_ints { #define USB_OHCI_LEN 0x00100000 #endif -#ifndef CONFIG_SOC_AU1200 - -/* USB Device Controller */ -#define USBD_EP0RD 0xB0200000 -#define USBD_EP0WR 0xB0200004 -#define USBD_EP2WR 0xB0200008 -#define USBD_EP3WR 0xB020000C -#define USBD_EP4RD 0xB0200010 -#define USBD_EP5RD 0xB0200014 -#define USBD_INTEN 0xB0200018 -#define USBD_INTSTAT 0xB020001C -# define USBDEV_INT_SOF (1 << 12) -# define USBDEV_INT_HF_BIT 6 -# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) -# define USBDEV_INT_CMPLT_BIT 0 -# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) -#define USBD_CONFIG 0xB0200020 -#define USBD_EP0CS 0xB0200024 -#define USBD_EP2CS 0xB0200028 -#define USBD_EP3CS 0xB020002C -#define USBD_EP4CS 0xB0200030 -#define USBD_EP5CS 0xB0200034 -# define USBDEV_CS_SU (1 << 14) -# define USBDEV_CS_NAK (1 << 13) -# define USBDEV_CS_ACK (1 << 12) -# define USBDEV_CS_BUSY (1 << 11) -# define USBDEV_CS_TSIZE_BIT 1 -# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) -# define USBDEV_CS_STALL (1 << 0) -#define USBD_EP0RDSTAT 0xB0200040 -#define USBD_EP0WRSTAT 0xB0200044 -#define USBD_EP2WRSTAT 0xB0200048 -#define USBD_EP3WRSTAT 0xB020004C -#define USBD_EP4RDSTAT 0xB0200050 -#define USBD_EP5RDSTAT 0xB0200054 -# define USBDEV_FSTAT_FLUSH (1 << 6) -# define USBDEV_FSTAT_UF (1 << 5) -# define USBDEV_FSTAT_OF (1 << 4) -# define USBDEV_FSTAT_FCNT_BIT 0 -# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) -#define USBD_ENABLE 0xB0200058 -# define USBDEV_ENABLE (1 << 1) -# define USBDEV_CE (1 << 0) - -#endif /* !CONFIG_SOC_AU1200 */ /* Ethernet Controllers */ diff --git a/drivers/usb/host/ehci-au1xxx.c b/drivers/usb/host/ehci-au1xxx.c index 42ae574..e480dc1 100644 --- a/drivers/usb/host/ehci-au1xxx.c +++ b/drivers/usb/host/ehci-au1xxx.c @@ -14,61 +14,9 @@ #include #include -#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG) -#define USB_MCFG_PFEN (1<<31) -#define USB_MCFG_RDCOMB (1<<30) -#define USB_MCFG_SSDEN (1<<23) -#define USB_MCFG_PHYPLLEN (1<<19) -#define USB_MCFG_UCECLKEN (1<<18) -#define USB_MCFG_EHCCLKEN (1<<17) -#ifdef CONFIG_DMA_COHERENT -#define USB_MCFG_UCAM (1<<7) -#else -#define USB_MCFG_UCAM (0) -#endif -#define USB_MCFG_EBMEN (1<<3) -#define USB_MCFG_EMEMEN (1<<2) - -#define USBH_ENABLE_CE (USB_MCFG_PHYPLLEN | USB_MCFG_EHCCLKEN) -#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \ - USBH_ENABLE_CE | USB_MCFG_SSDEN | \ - USB_MCFG_UCAM | USB_MCFG_EBMEN | \ - USB_MCFG_EMEMEN) - -#define USBH_DISABLE (USB_MCFG_EBMEN | USB_MCFG_EMEMEN) extern int usb_disabled(void); -static void au1xxx_start_ehc(void) -{ - /* enable clock to EHCI block and HS PHY PLL*/ - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - /* enable EHCI mmio */ - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG); - au_sync(); - udelay(1000); -} - -static void au1xxx_stop_ehc(void) -{ - unsigned long c; - - /* Disable mem */ - au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - /* Disable EHC clock. If the HS PHY is unused disable it too. */ - c = au_readl(USB_HOST_CONFIG) & ~USB_MCFG_EHCCLKEN; - if (!(c & USB_MCFG_UCECLKEN)) /* UDC disabled? */ - c &= ~USB_MCFG_PHYPLLEN; /* yes: disable HS PHY PLL */ - au_writel(c, USB_HOST_CONFIG); - au_sync(); -} - static int au1xxx_ehci_setup(struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); @@ -136,16 +84,6 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) if (usb_disabled()) return -ENODEV; -#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT) - /* Au1200 AB USB does not support coherent memory */ - if (!(read_c0_prid() & 0xff)) { - printk(KERN_INFO "%s: this is chip revision AB!\n", pdev->name); - printk(KERN_INFO "%s: update your board or re-configure" - " the kernel\n", pdev->name); - return -ENODEV; - } -#endif - if (pdev->resource[1].flags != IORESOURCE_IRQ) { pr_debug("resource[1] is not IORESOURCE_IRQ"); return -ENOMEM; @@ -171,7 +109,11 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) goto err2; } - au1xxx_start_ehc(); + if (alchemy_usb_control(ALCHEMY_USB_EHCI0, 1)) { + printk(KERN_INFO "%s: controller init failed!\n", pdev->name); + ret = -ENODEV; + goto err3; + } ehci = hcd_to_ehci(hcd); ehci->caps = hcd->regs; @@ -187,7 +129,8 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) return ret; } - au1xxx_stop_ehc(); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); +err3: iounmap(hcd->regs); err2: release_mem_region(hcd->rsrc_start, hcd->rsrc_len); @@ -201,10 +144,10 @@ static int ehci_hcd_au1xxx_drv_remove(struct platform_device *pdev) struct usb_hcd *hcd = platform_get_drvdata(pdev); usb_remove_hcd(hcd); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); - au1xxx_stop_ehc(); platform_set_drvdata(pdev, NULL); return 0; @@ -236,7 +179,7 @@ static int ehci_hcd_au1xxx_drv_suspend(struct device *dev) // could save FLADJ in case of Vaux power loss // ... we'd only use it to handle clock skew - au1xxx_stop_ehc(); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); return rc; } @@ -246,7 +189,7 @@ static int ehci_hcd_au1xxx_drv_resume(struct device *dev) struct usb_hcd *hcd = dev_get_drvdata(dev); struct ehci_hcd *ehci = hcd_to_ehci(hcd); - au1xxx_start_ehc(); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 1); // maybe restore FLADJ diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index 958d985..299d719 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -23,92 +23,9 @@ #include -#ifndef CONFIG_SOC_AU1200 - -#define USBH_ENABLE_BE (1<<0) -#define USBH_ENABLE_C (1<<1) -#define USBH_ENABLE_E (1<<2) -#define USBH_ENABLE_CE (1<<3) -#define USBH_ENABLE_RD (1<<4) - -#ifdef __LITTLE_ENDIAN -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) -#elif defined(__BIG_ENDIAN) -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | \ - USBH_ENABLE_BE) -#else -#error not byte order defined -#endif - -#else /* Au1200 */ - -#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG) -#define USB_MCFG_PFEN (1<<31) -#define USB_MCFG_RDCOMB (1<<30) -#define USB_MCFG_SSDEN (1<<23) -#define USB_MCFG_OHCCLKEN (1<<16) -#ifdef CONFIG_DMA_COHERENT -#define USB_MCFG_UCAM (1<<7) -#else -#define USB_MCFG_UCAM (0) -#endif -#define USB_MCFG_OBMEN (1<<1) -#define USB_MCFG_OMEMEN (1<<0) - -#define USBH_ENABLE_CE USB_MCFG_OHCCLKEN - -#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \ - USBH_ENABLE_CE | USB_MCFG_SSDEN | \ - USB_MCFG_UCAM | \ - USB_MCFG_OBMEN | USB_MCFG_OMEMEN) - -#define USBH_DISABLE (USB_MCFG_OBMEN | USB_MCFG_OMEMEN) - -#endif /* Au1200 */ extern int usb_disabled(void); -static void au1xxx_start_ohc(void) -{ - /* enable host controller */ -#ifndef CONFIG_SOC_AU1200 - au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - /* wait for reset complete (read register twice; see au1500 errata) */ - while (au_readl(USB_HOST_CONFIG), - !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) - udelay(1000); - -#else /* Au1200 */ - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG); - au_sync(); - udelay(2000); -#endif /* Au1200 */ -} - -static void au1xxx_stop_ohc(void) -{ -#ifdef CONFIG_SOC_AU1200 - /* Disable mem */ - au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); -#endif - /* Disable clock */ - au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); -} - static int __devinit ohci_au1xxx_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); @@ -178,17 +95,6 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) if (usb_disabled()) return -ENODEV; -#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT) - /* Au1200 AB USB does not support coherent memory */ - if (!(read_c0_prid() & 0xff)) { - printk(KERN_INFO "%s: this is chip revision AB !!\n", - pdev->name); - printk(KERN_INFO "%s: update your board or re-configure " - "the kernel\n", pdev->name); - return -ENODEV; - } -#endif - if (pdev->resource[1].flags != IORESOURCE_IRQ) { pr_debug("resource[1] is not IORESOURCE_IRQ\n"); return -ENOMEM; @@ -214,7 +120,12 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) goto err2; } - au1xxx_start_ohc(); + if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) { + printk(KERN_INFO "%s: controller init failed!\n", pdev->name); + ret = -ENODEV; + goto err3; + } + ohci_hcd_init(hcd_to_ohci(hcd)); ret = usb_add_hcd(hcd, pdev->resource[1].start, @@ -224,7 +135,8 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) return ret; } - au1xxx_stop_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); +err3: iounmap(hcd->regs); err2: release_mem_region(hcd->rsrc_start, hcd->rsrc_len); @@ -238,7 +150,7 @@ static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev) struct usb_hcd *hcd = platform_get_drvdata(pdev); usb_remove_hcd(hcd); - au1xxx_stop_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); @@ -275,7 +187,7 @@ static int ohci_hcd_au1xxx_drv_suspend(struct device *dev) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); - au1xxx_stop_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); bail: spin_unlock_irqrestore(&ohci->lock, flags); @@ -286,7 +198,7 @@ static int ohci_hcd_au1xxx_drv_resume(struct device *dev) { struct usb_hcd *hcd = dev_get_drvdata(dev); - au1xxx_start_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 1); set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); ohci_finish_controller_resume(hcd); -- 1.7.6 From manuel.lauss@googlemail.com Fri Aug 12 11:39:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 11:42:01 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:44389 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491206Ab1HLJj7 (ORCPT ); Fri, 12 Aug 2011 11:39:59 +0200 Received: by fxd20 with SMTP id 20so2860493fxd.36 for ; Fri, 12 Aug 2011 02:39:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=sQ2pP51/Enm7D3QUbn7lUslTBKKUSRzZ5ST+0872jNg=; b=mLFyMEosSTYKV0EnQRUG4xg1qp5e0YXHOOYHvqrn9dmiEwoTT+Ouxzlto63n3cSl7E c7qas12tiP/oDdYGk4JzZpP53j1wEHC1zsxpz4XbQ/CXI6shvMs4h4Dvoe6N8G6AkcNC pVDSHJ5Y95bpFJFJW91IS5Hz13Ms/BdcEusb0= Received: by 10.223.161.80 with SMTP id q16mr965350fax.113.1313141994216; Fri, 12 Aug 2011 02:39:54 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id s14sm467338fah.29.2011.08.12.02.39.52 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 02:39:53 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 2/8] MIPS: Alchemy: rewrite USB platform setup. Date: Fri, 12 Aug 2011 11:39:39 +0200 Message-Id: <1313141985-5830-3-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30859 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9265 Content-Length: 8670 Lines: 310 Use runtime CPU detection to setup all USB parts. Remove the Au1200 OTG and UDC platform devices since there are no drivers for them anyway. Clean up the USB address mess in the au1000 header. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 183 +++++++++++---------------- arch/mips/include/asm/mach-au1x00/au1000.h | 55 --------- 2 files changed, 75 insertions(+), 163 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 15d9b2f..910a3bd 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -111,34 +111,84 @@ static void __init alchemy_setup_uarts(int ctype) printk(KERN_INFO "Alchemy: failed to register UARTs\n"); } -/* OHCI (USB full speed host controller) */ -static struct resource au1xxx_usb_ohci_resources[] = { - [0] = { - .start = USB_OHCI_BASE, - .end = USB_OHCI_BASE + USB_OHCI_LEN - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = FOR_PLATFORM_C_USB_HOST_INT, - .end = FOR_PLATFORM_C_USB_HOST_INT, - .flags = IORESOURCE_IRQ, - }, -}; -/* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = DMA_BIT_MASK(32); +/* The dmamask must be set for OHCI/EHCI to work */ +static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32); +static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32); -static struct platform_device au1xxx_usb_ohci_device = { - .name = "au1xxx-ohci", - .id = 0, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), - .resource = au1xxx_usb_ohci_resources, +static unsigned long alchemy_ohci_data[][2] __initdata = { + [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT }, + [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT }, + [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT }, + [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT }, + [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT }, +}; + +static unsigned long alchemy_ehci_data[][2] __initdata = { + [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT }, }; +static int __init _new_usbres(struct resource **r, struct platform_device **d) +{ + *r = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!*r) + return -ENOMEM; + *d = kzalloc(sizeof(struct platform_device), GFP_KERNEL); + if (!*d) { + kfree(*r); + return -ENOMEM; + } + + (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32); + (*d)->num_resources = 2; + (*d)->resource = *r; + + return 0; +} + +static void __init alchemy_setup_usb(int ctype) +{ + struct resource *res; + struct platform_device *pdev; + + /* setup OHCI0. Every variant has one */ + if (_new_usbres(&res, &pdev)) + return; + + res[0].start = alchemy_ohci_data[ctype][0]; + res[0].end = res[0].start + 0x100 - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = alchemy_ohci_data[ctype][1]; + res[1].end = res[1].start; + res[1].flags = IORESOURCE_IRQ; + pdev->name = "au1xxx-ohci"; + pdev->id = 0; + pdev->dev.dma_mask = &alchemy_ohci_dmamask; + + if (platform_device_register(pdev)) + printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); + + + /* setup EHCI0: Au1200 */ + if (ctype == ALCHEMY_CPU_AU1200) { + if (_new_usbres(&res, &pdev)) + return; + + res[0].start = alchemy_ehci_data[ctype][0]; + res[0].end = res[0].start + 0x100 - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = alchemy_ehci_data[ctype][1]; + res[1].end = res[1].start; + res[1].flags = IORESOURCE_IRQ; + pdev->name = "au1xxx-ehci"; + pdev->id = 0; + pdev->dev.dma_mask = &alchemy_ehci_dmamask; + + if (platform_device_register(pdev)) + printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); + } +} + /*** AU1100 LCD controller ***/ #ifdef CONFIG_FB_AU1100 @@ -170,86 +220,6 @@ static struct platform_device au1100_lcd_device = { #endif #ifdef CONFIG_SOC_AU1200 -/* EHCI (USB high speed host controller) */ -static struct resource au1xxx_usb_ehci_resources[] = { - [0] = { - .start = USB_EHCI_BASE, - .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_USB_INT, - .end = AU1200_USB_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ehci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1xxx_usb_ehci_device = { - .name = "au1xxx-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources), - .resource = au1xxx_usb_ehci_resources, -}; - -/* Au1200 UDC (USB gadget controller) */ -static struct resource au1xxx_usb_gdt_resources[] = { - [0] = { - .start = USB_UDC_BASE, - .end = USB_UDC_BASE + USB_UDC_LEN - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_USB_INT, - .end = AU1200_USB_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 udc_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1xxx_usb_gdt_device = { - .name = "au1xxx-udc", - .id = 0, - .dev = { - .dma_mask = &udc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources), - .resource = au1xxx_usb_gdt_resources, -}; - -/* Au1200 UOC (USB OTG controller) */ -static struct resource au1xxx_usb_otg_resources[] = { - [0] = { - .start = USB_UOC_BASE, - .end = USB_UOC_BASE + USB_UOC_LEN - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_USB_INT, - .end = AU1200_USB_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 uoc_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1xxx_usb_otg_device = { - .name = "au1xxx-uoc", - .id = 0, - .dev = { - .dma_mask = &uoc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources), - .resource = au1xxx_usb_otg_resources, -}; static struct resource au1200_lcd_resources[] = { [0] = { @@ -534,14 +504,10 @@ static void __init alchemy_setup_macs(int ctype) } static struct platform_device *au1xxx_platform_devices[] __initdata = { - &au1xxx_usb_ohci_device, #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, #endif #ifdef CONFIG_SOC_AU1200 - &au1xxx_usb_ehci_device, - &au1xxx_usb_gdt_device, - &au1xxx_usb_otg_device, &au1200_lcd_device, &au1200_mmc0_device, #ifndef CONFIG_MIPS_DB1200 @@ -559,6 +525,7 @@ static int __init au1xxx_platform_init(void) alchemy_setup_uarts(ctype); alchemy_setup_macs(ctype); + alchemy_setup_usb(ctype); err = platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices)); diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 73e0d79..86d39c3 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -833,56 +833,6 @@ enum soc_au1200_ints { #endif - - -/* Au1000 */ -#ifdef CONFIG_SOC_AU1000 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017FFFC -#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT -#endif /* CONFIG_SOC_AU1000 */ - -/* Au1500 */ -#ifdef CONFIG_SOC_AU1500 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017fffc -#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT -#endif /* CONFIG_SOC_AU1500 */ - -/* Au1100 */ -#ifdef CONFIG_SOC_AU1100 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017FFFC -#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT -#endif /* CONFIG_SOC_AU1100 */ - -#ifdef CONFIG_SOC_AU1550 - -#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ -#define USB_OHCI_LEN 0x00060000 -#define USB_HOST_CONFIG 0xB4027ffc -#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT -#endif /* CONFIG_SOC_AU1550 */ - - -#ifdef CONFIG_SOC_AU1200 - -#define USB_UOC_BASE 0x14020020 -#define USB_UOC_LEN 0x20 -#define USB_OHCI_BASE 0x14020100 -#define USB_OHCI_LEN 0x100 -#define USB_EHCI_BASE 0x14020200 -#define USB_EHCI_LEN 0x100 -#define USB_UDC_BASE 0x14022000 -#define USB_UDC_LEN 0x2000 - -#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT - -#endif /* CONFIG_SOC_AU1200 */ - /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) @@ -953,11 +903,6 @@ enum soc_au1200_ints { # define I2S_CONTROL_D (1 << 1) # define I2S_CONTROL_CE (1 << 0) -/* USB Host Controller */ -#ifndef USB_OHCI_LEN -#define USB_OHCI_LEN 0x00100000 -#endif - /* Ethernet Controllers */ -- 1.7.6 From manuel.lauss@googlemail.com Fri Aug 12 11:39:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 11:42:30 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:50901 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491207Ab1HLJj7 (ORCPT ); Fri, 12 Aug 2011 11:39:59 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so2860465fxd.36 for ; Fri, 12 Aug 2011 02:39:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=BgjjEeBh1hreeskY1bvN/qwJ5hEbmhSPUaPab0ds6Yw=; b=tmvIaCxKWkiRgSPleYQ7562alLk9D5VWwPdfTSkxntV24aethVbUnnCdCa3CrW3LfQ DyxWe9WlH5ZWdiYG7Rw0Sfx1iKE9aWguNqMDKfWntadjfWK4HYrpelTO1I2jgDcTuwM5 NQnjz6H1W23Da9AfD3tOu2IqfqnlnKfdPYhjA= Received: by 10.223.144.136 with SMTP id z8mr1020518fau.31.1313141999616; Fri, 12 Aug 2011 02:39:59 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id s14sm467338fah.29.2011.08.12.02.39.57 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 02:39:58 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 5/8] MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines Date: Fri, 12 Aug 2011 11:39:42 +0200 Message-Id: <1313141985-5830-6-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30860 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9266 Content-Length: 24027 Lines: 659 This patch gets rid of all CONFIG_SOC_AU1XXX defines in DMA/DBDMA-related code. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/dbdma.c | 203 ++++++++++------------ arch/mips/alchemy/common/dma.c | 60 +++---- arch/mips/alchemy/common/platform.c | 16 +- arch/mips/alchemy/devboards/db1200/platform.c | 20 +- arch/mips/alchemy/devboards/pb1200/platform.c | 4 +- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 114 ++++++------- arch/mips/include/asm/mach-db1x00/db1x00.h | 8 +- arch/mips/include/asm/mach-pb1x00/pb1200.h | 8 +- arch/mips/include/asm/mach-pb1x00/pb1550.h | 8 +- 9 files changed, 206 insertions(+), 235 deletions(-) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 3a5abb5..0e63ee4 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -40,8 +40,6 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - /* * The Descriptor Based DMA supports up to 16 channels. * @@ -62,120 +60,96 @@ static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR); static int dbdma_initialized; -static dbdev_tab_t dbdev_tab[] = { -#ifdef CONFIG_SOC_AU1550 +static dbdev_tab_t *dbdev_tab; + +static dbdev_tab_t au1550_dbdev_tab[] __initdata = { /* UARTS */ - { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, - { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, - { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, - { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, + { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, + { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, + { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, + { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, /* EXT DMA */ - { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, /* USB DEV */ - { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, - { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, - { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, - { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, - { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, - { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, - - /* PSC 0 */ - { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, - { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, - - /* PSC 1 */ - { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, - { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, - - /* PSC 2 */ - { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, - { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, - - /* PSC 3 */ - { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 }, - { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 }, - - { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */ - { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */ + { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, + { AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, + + /* PSCs */ + { AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 }, + { AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 }, + + { AU1550_DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */ + { AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */ /* MAC 0 */ - { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, /* MAC 1 */ - { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, - -#endif /* CONFIG_SOC_AU1550 */ + { AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, -#ifdef CONFIG_SOC_AU1200 - { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, - { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, - { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 }, - { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 }, - - { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, +}; - { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, +static dbdev_tab_t au1200_dbdev_tab[] __initdata = { + { AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, + { AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, + { AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 }, + { AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 }, - { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, - { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, - { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, - { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, + { AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, - { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + { AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, - { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, - { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, + { AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, - { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, - { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, - { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, - { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, - { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, - { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, - { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, + { AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, + { AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, + { AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, + { AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, + { AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, + { AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, + { AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, -#endif /* CONFIG_SOC_AU1200 */ + { AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - - /* Provide 16 user definable device types */ - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, - { ~0, 0, 0, 0, 0, 0, 0 }, + { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, }; -#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) - +/* 32 predefined plus 32 custom */ +#define DBDEV_TAB_SIZE 64 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; @@ -1028,38 +1002,43 @@ static struct syscore_ops alchemy_dbdma_syscore_ops = { .resume = alchemy_dbdma_resume, }; -static int __init au1xxx_dbdma_init(void) +static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) { - int irq_nr, ret; + int ret; + + dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL); + if (!dbdev_tab) + return -ENOMEM; + + memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t)); + for (ret = 32; ret < DBDEV_TAB_SIZE; ret++) + dbdev_tab[ret].dev_id = ~0; dbdma_gptr->ddma_config = 0; dbdma_gptr->ddma_throttle = 0; dbdma_gptr->ddma_inten = 0xffff; au_sync(); - switch (alchemy_get_cputype()) { - case ALCHEMY_CPU_AU1550: - irq_nr = AU1550_DDMA_INT; - break; - case ALCHEMY_CPU_AU1200: - irq_nr = AU1200_DDMA_INT; - break; - default: - return -ENODEV; - } - - ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, - "Au1xxx dbdma", (void *)dbdma_gptr); + ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma", + (void *)dbdma_gptr); if (ret) printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); else { dbdma_initialized = 1; - printk(KERN_INFO "Alchemy DBDMA initialized\n"); register_syscore_ops(&alchemy_dbdma_syscore_ops); } return ret; } -subsys_initcall(au1xxx_dbdma_init); -#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ +static int __init alchemy_dbdma_init(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1550: + return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab); + case ALCHEMY_CPU_AU1200: + return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab); + } + return 0; +} +subsys_initcall(alchemy_dbdma_init); diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c index 6652a23..9b624e2 100644 --- a/arch/mips/alchemy/common/dma.c +++ b/arch/mips/alchemy/common/dma.c @@ -40,8 +40,6 @@ #include #include -#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ - defined(CONFIG_SOC_AU1100) /* * A note on resource allocation: * @@ -170,13 +168,13 @@ int request_au1000_dma(int dev_id, const char *dev_str, const struct dma_dev *dev; int i, ret; -#if defined(CONFIG_SOC_AU1100) - if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2)) - return -EINVAL; -#else - if (dev_id < 0 || dev_id >= DMA_NUM_DEV) - return -EINVAL; -#endif + if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) { + if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2)) + return -EINVAL; + } else { + if (dev_id < 0 || dev_id >= DMA_NUM_DEV) + return -EINVAL; + } for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) if (au1000_dma_table[i].dev_id < 0) @@ -239,30 +237,28 @@ EXPORT_SYMBOL(free_au1000_dma); static int __init au1000_dma_init(void) { - int base, i; - - switch (alchemy_get_cputype()) { - case ALCHEMY_CPU_AU1000: - base = AU1000_DMA_INT_BASE; - break; - case ALCHEMY_CPU_AU1500: - base = AU1500_DMA_INT_BASE; - break; - case ALCHEMY_CPU_AU1100: - base = AU1100_DMA_INT_BASE; - break; - default: - goto out; - } - - for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) - au1000_dma_table[i].irq = base + i; - - printk(KERN_INFO "Alchemy DMA initialized\n"); + int base, i; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + base = AU1000_DMA_INT_BASE; + break; + case ALCHEMY_CPU_AU1500: + base = AU1500_DMA_INT_BASE; + break; + case ALCHEMY_CPU_AU1100: + base = AU1100_DMA_INT_BASE; + break; + default: + goto out; + } + + for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) + au1000_dma_table[i].irq = base + i; + + printk(KERN_INFO "Alchemy DMA initialized\n"); out: - return 0; + return 0; } arch_initcall(au1000_dma_init); - -#endif /* AU1000 AU1500 AU1100 */ diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index bf1ac41..7eca306 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -263,13 +263,13 @@ static struct resource au1200_mmc0_resources[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_SDMS_TX0, - .end = DSCR_CMD0_SDMS_TX0, + .start = AU1200_DSCR_CMD0_SDMS_TX0, + .end = AU1200_DSCR_CMD0_SDMS_TX0, .flags = IORESOURCE_DMA, }, [3] = { - .start = DSCR_CMD0_SDMS_RX0, - .end = DSCR_CMD0_SDMS_RX0, + .start = AU1200_DSCR_CMD0_SDMS_RX0, + .end = AU1200_DSCR_CMD0_SDMS_RX0, .flags = IORESOURCE_DMA, } }; @@ -299,13 +299,13 @@ static struct resource au1200_mmc1_resources[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_SDMS_TX1, - .end = DSCR_CMD0_SDMS_TX1, + .start = AU1200_DSCR_CMD0_SDMS_TX1, + .end = AU1200_DSCR_CMD0_SDMS_TX1, .flags = IORESOURCE_DMA, }, [3] = { - .start = DSCR_CMD0_SDMS_RX1, - .end = DSCR_CMD0_SDMS_RX1, + .start = AU1200_DSCR_CMD0_SDMS_RX1, + .end = AU1200_DSCR_CMD0_SDMS_RX1, .flags = IORESOURCE_DMA, } }; diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index 6fd070d..1bc16f0 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -215,8 +215,8 @@ static struct resource db1200_ide_res[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_DMA_REQ1, - .end = DSCR_CMD0_DMA_REQ1, + .start = AU1200_DSCR_CMD0_DMA_REQ1, + .end = AU1200_DSCR_CMD0_DMA_REQ1, .flags = IORESOURCE_DMA, }, }; @@ -358,13 +358,13 @@ static struct resource au1200_psc0_res[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_PSC0_TX, - .end = DSCR_CMD0_PSC0_TX, + .start = AU1200_DSCR_CMD0_PSC0_TX, + .end = AU1200_DSCR_CMD0_PSC0_TX, .flags = IORESOURCE_DMA, }, [3] = { - .start = DSCR_CMD0_PSC0_RX, - .end = DSCR_CMD0_PSC0_RX, + .start = AU1200_DSCR_CMD0_PSC0_RX, + .end = AU1200_DSCR_CMD0_PSC0_RX, .flags = IORESOURCE_DMA, }, }; @@ -416,13 +416,13 @@ static struct resource au1200_psc1_res[] = { .flags = IORESOURCE_IRQ, }, [2] = { - .start = DSCR_CMD0_PSC1_TX, - .end = DSCR_CMD0_PSC1_TX, + .start = AU1200_DSCR_CMD0_PSC1_TX, + .end = AU1200_DSCR_CMD0_PSC1_TX, .flags = IORESOURCE_DMA, }, [3] = { - .start = DSCR_CMD0_PSC1_RX, - .end = DSCR_CMD0_PSC1_RX, + .start = AU1200_DSCR_CMD0_PSC1_RX, + .end = AU1200_DSCR_CMD0_PSC1_RX, .flags = IORESOURCE_DMA, }, }; diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 6ac0494..7de4f88 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -118,8 +118,8 @@ static struct resource ide_resources[] = { .flags = IORESOURCE_IRQ }, [2] = { - .start = DSCR_CMD0_DMA_REQ1, - .end = DSCR_CMD0_DMA_REQ1, + .start = AU1200_DSCR_CMD0_DMA_REQ1, + .end = AU1200_DSCR_CMD0_DMA_REQ1, .flags = IORESOURCE_DMA, }, }; diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 2fdacfe..323ce2d 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -126,66 +126,62 @@ typedef volatile struct au1xxx_ddma_desc { #define SW_STATUS_INUSE (1 << 0) /* Command 0 device IDs. */ -#ifdef CONFIG_SOC_AU1550 -#define DSCR_CMD0_UART0_TX 0 -#define DSCR_CMD0_UART0_RX 1 -#define DSCR_CMD0_UART3_TX 2 -#define DSCR_CMD0_UART3_RX 3 -#define DSCR_CMD0_DMA_REQ0 4 -#define DSCR_CMD0_DMA_REQ1 5 -#define DSCR_CMD0_DMA_REQ2 6 -#define DSCR_CMD0_DMA_REQ3 7 -#define DSCR_CMD0_USBDEV_RX0 8 -#define DSCR_CMD0_USBDEV_TX0 9 -#define DSCR_CMD0_USBDEV_TX1 10 -#define DSCR_CMD0_USBDEV_TX2 11 -#define DSCR_CMD0_USBDEV_RX3 12 -#define DSCR_CMD0_USBDEV_RX4 13 -#define DSCR_CMD0_PSC0_TX 14 -#define DSCR_CMD0_PSC0_RX 15 -#define DSCR_CMD0_PSC1_TX 16 -#define DSCR_CMD0_PSC1_RX 17 -#define DSCR_CMD0_PSC2_TX 18 -#define DSCR_CMD0_PSC2_RX 19 -#define DSCR_CMD0_PSC3_TX 20 -#define DSCR_CMD0_PSC3_RX 21 -#define DSCR_CMD0_PCI_WRITE 22 -#define DSCR_CMD0_NAND_FLASH 23 -#define DSCR_CMD0_MAC0_RX 24 -#define DSCR_CMD0_MAC0_TX 25 -#define DSCR_CMD0_MAC1_RX 26 -#define DSCR_CMD0_MAC1_TX 27 -#endif /* CONFIG_SOC_AU1550 */ - -#ifdef CONFIG_SOC_AU1200 -#define DSCR_CMD0_UART0_TX 0 -#define DSCR_CMD0_UART0_RX 1 -#define DSCR_CMD0_UART1_TX 2 -#define DSCR_CMD0_UART1_RX 3 -#define DSCR_CMD0_DMA_REQ0 4 -#define DSCR_CMD0_DMA_REQ1 5 -#define DSCR_CMD0_MAE_BE 6 -#define DSCR_CMD0_MAE_FE 7 -#define DSCR_CMD0_SDMS_TX0 8 -#define DSCR_CMD0_SDMS_RX0 9 -#define DSCR_CMD0_SDMS_TX1 10 -#define DSCR_CMD0_SDMS_RX1 11 -#define DSCR_CMD0_AES_TX 13 -#define DSCR_CMD0_AES_RX 12 -#define DSCR_CMD0_PSC0_TX 14 -#define DSCR_CMD0_PSC0_RX 15 -#define DSCR_CMD0_PSC1_TX 16 -#define DSCR_CMD0_PSC1_RX 17 -#define DSCR_CMD0_CIM_RXA 18 -#define DSCR_CMD0_CIM_RXB 19 -#define DSCR_CMD0_CIM_RXC 20 -#define DSCR_CMD0_MAE_BOTH 21 -#define DSCR_CMD0_LCD 22 -#define DSCR_CMD0_NAND_FLASH 23 -#define DSCR_CMD0_PSC0_SYNC 24 -#define DSCR_CMD0_PSC1_SYNC 25 -#define DSCR_CMD0_CIM_SYNC 26 -#endif /* CONFIG_SOC_AU1200 */ +#define AU1550_DSCR_CMD0_UART0_TX 0 +#define AU1550_DSCR_CMD0_UART0_RX 1 +#define AU1550_DSCR_CMD0_UART3_TX 2 +#define AU1550_DSCR_CMD0_UART3_RX 3 +#define AU1550_DSCR_CMD0_DMA_REQ0 4 +#define AU1550_DSCR_CMD0_DMA_REQ1 5 +#define AU1550_DSCR_CMD0_DMA_REQ2 6 +#define AU1550_DSCR_CMD0_DMA_REQ3 7 +#define AU1550_DSCR_CMD0_USBDEV_RX0 8 +#define AU1550_DSCR_CMD0_USBDEV_TX0 9 +#define AU1550_DSCR_CMD0_USBDEV_TX1 10 +#define AU1550_DSCR_CMD0_USBDEV_TX2 11 +#define AU1550_DSCR_CMD0_USBDEV_RX3 12 +#define AU1550_DSCR_CMD0_USBDEV_RX4 13 +#define AU1550_DSCR_CMD0_PSC0_TX 14 +#define AU1550_DSCR_CMD0_PSC0_RX 15 +#define AU1550_DSCR_CMD0_PSC1_TX 16 +#define AU1550_DSCR_CMD0_PSC1_RX 17 +#define AU1550_DSCR_CMD0_PSC2_TX 18 +#define AU1550_DSCR_CMD0_PSC2_RX 19 +#define AU1550_DSCR_CMD0_PSC3_TX 20 +#define AU1550_DSCR_CMD0_PSC3_RX 21 +#define AU1550_DSCR_CMD0_PCI_WRITE 22 +#define AU1550_DSCR_CMD0_NAND_FLASH 23 +#define AU1550_DSCR_CMD0_MAC0_RX 24 +#define AU1550_DSCR_CMD0_MAC0_TX 25 +#define AU1550_DSCR_CMD0_MAC1_RX 26 +#define AU1550_DSCR_CMD0_MAC1_TX 27 + +#define AU1200_DSCR_CMD0_UART0_TX 0 +#define AU1200_DSCR_CMD0_UART0_RX 1 +#define AU1200_DSCR_CMD0_UART1_TX 2 +#define AU1200_DSCR_CMD0_UART1_RX 3 +#define AU1200_DSCR_CMD0_DMA_REQ0 4 +#define AU1200_DSCR_CMD0_DMA_REQ1 5 +#define AU1200_DSCR_CMD0_MAE_BE 6 +#define AU1200_DSCR_CMD0_MAE_FE 7 +#define AU1200_DSCR_CMD0_SDMS_TX0 8 +#define AU1200_DSCR_CMD0_SDMS_RX0 9 +#define AU1200_DSCR_CMD0_SDMS_TX1 10 +#define AU1200_DSCR_CMD0_SDMS_RX1 11 +#define AU1200_DSCR_CMD0_AES_TX 13 +#define AU1200_DSCR_CMD0_AES_RX 12 +#define AU1200_DSCR_CMD0_PSC0_TX 14 +#define AU1200_DSCR_CMD0_PSC0_RX 15 +#define AU1200_DSCR_CMD0_PSC1_TX 16 +#define AU1200_DSCR_CMD0_PSC1_RX 17 +#define AU1200_DSCR_CMD0_CIM_RXA 18 +#define AU1200_DSCR_CMD0_CIM_RXB 19 +#define AU1200_DSCR_CMD0_CIM_RXC 20 +#define AU1200_DSCR_CMD0_MAE_BOTH 21 +#define AU1200_DSCR_CMD0_LCD 22 +#define AU1200_DSCR_CMD0_NAND_FLASH 23 +#define AU1200_DSCR_CMD0_PSC0_SYNC 24 +#define AU1200_DSCR_CMD0_PSC1_SYNC 25 +#define AU1200_DSCR_CMD0_CIM_SYNC 26 #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index 115cc7c..a5affb0 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -31,10 +31,10 @@ #ifdef CONFIG_MIPS_DB1550 -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX +#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX +#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX #define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR #define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index 56865e9..374416a 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -28,10 +28,10 @@ #include #include -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX +#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX +#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX /* * SPI and SMB are muxed on the Pb1200 board. diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h index 0b0f462..443b88a 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h @@ -30,10 +30,10 @@ #include #include -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX +#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX +#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX +#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX #define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR #define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR -- 1.7.6 From manuel.lauss@googlemail.com Fri Aug 12 11:40:01 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 11:43:00 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:33383 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491757Ab1HLJkB (ORCPT ); Fri, 12 Aug 2011 11:40:01 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so2860485fxd.36 for ; Fri, 12 Aug 2011 02:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=5XE/NAwdDYXkOjrK+WNDCDO3QaZBvIBZ/QkOt9GE110=; b=MXYmite6YBU3t7ltGEl4zUBQYRcuc59S68wzwPJCavynit+dWWX9L5/Q44YPPW/vxE e6ySrOYh7rMX+KOn/SOZWZQfK/vWppqiKHFUAQP45Izg63A174AZ3ZjlDhOmLJovwMsd R3Ja9wqLvZZ1/QBLQlnKgtIcp2ZbN/kP3xW+s= Received: by 10.223.52.66 with SMTP id h2mr988208fag.92.1313142001133; Fri, 12 Aug 2011 02:40:01 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id s14sm467338fah.29.2011.08.12.02.39.59 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 02:40:00 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 6/8] MIPS: Alchemy: kill au1xxx.h header Date: Fri, 12 Aug 2011 11:39:43 +0200 Message-Id: <1313141985-5830-7-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30861 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9267 Content-Length: 5408 Lines: 152 No longer required Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 2 +- arch/mips/alchemy/devboards/db1x00/platform.c | 2 +- arch/mips/alchemy/devboards/pb1200/platform.c | 3 +- arch/mips/include/asm/mach-au1x00/au1xxx.h | 43 ------------------------- drivers/i2c/busses/i2c-au1550.c | 2 +- drivers/ide/au1xxx-ide.c | 2 +- drivers/mtd/nand/au1550nd.c | 6 +++- 7 files changed, 11 insertions(+), 49 deletions(-) delete mode 100644 arch/mips/include/asm/mach-au1x00/au1xxx.h diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 7eca306..657ae27 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index ef8017f..70bcfb5 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #include "../platform.h" diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 7de4f88..d7915b0 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -24,10 +24,11 @@ #include #include -#include +#include #include #include #include +#include #include "../platform.h" diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h deleted file mode 100644 index 1b36550..0000000 --- a/arch/mips/include/asm/mach-au1x00/au1xxx.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _AU1XXX_H_ -#define _AU1XXX_H_ - -#include - -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) -#include - -#elif defined(CONFIG_MIPS_PB1550) -#include - -#elif defined(CONFIG_MIPS_PB1200) -#include - -#elif defined(CONFIG_MIPS_DB1200) -#include - -#endif - -#endif /* _AU1XXX_H_ */ diff --git a/drivers/i2c/busses/i2c-au1550.c b/drivers/i2c/busses/i2c-au1550.c index 532828b..a714534 100644 --- a/drivers/i2c/busses/i2c-au1550.c +++ b/drivers/i2c/busses/i2c-au1550.c @@ -36,7 +36,7 @@ #include #include -#include +#include #include struct i2c_au1550_data { diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c index c778373..259786c 100644 --- a/drivers/ide/au1xxx-ide.c +++ b/drivers/ide/au1xxx-ide.c @@ -36,7 +36,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index e7767ee..fa5736b 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -19,7 +19,11 @@ #include #include -#include +#ifdef CONFIG_MIPS_PB1550 +#include +#elif defined(CONFIG_MIPS_DB1550) +#include +#endif #include /* -- 1.7.6 From manuel.lauss@googlemail.com Fri Aug 12 11:40:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 11:43:32 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:44389 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491759Ab1HLJkE (ORCPT ); Fri, 12 Aug 2011 11:40:04 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so2860493fxd.36 for ; Fri, 12 Aug 2011 02:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=wiWet6uoH10LIU9OomyUuhMkHwXGwMf0x5nZBAlb9v8=; b=xupiKNoOCdgP8UU1K1NFGpx9gOdPkj1iBfr02+lvPRmATSzU6ZBAR9FtbqbEmtfkHR w2RZ5fPR47odc2+cWfTHUFZNmSYFPwkQSi6ZZmACBYdD/ek4ZZVLeZcRKVQK4u/BQXsQ GmfEutI/mQxEN2yPuUTApRkCZgRB2/nhvbfsk= Received: by 10.223.74.12 with SMTP id s12mr979028faj.103.1313142003742; Fri, 12 Aug 2011 02:40:03 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id s14sm467338fah.29.2011.08.12.02.40.01 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 02:40:02 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 7/8] MIPS: Alchemy: redo PCI as platform driver Date: Fri, 12 Aug 2011 11:39:44 +0200 Message-Id: <1313141985-5830-8-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30862 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9268 Content-Length: 59931 Lines: 1906 - Rewrite Alchemy PCI support as a platform driver. - Fixup boards which have PCI. Run-tested on DB1500 and DB1550. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/Makefile | 2 - arch/mips/alchemy/common/pci.c | 104 ----- arch/mips/alchemy/common/setup.c | 6 +- arch/mips/alchemy/devboards/db1x00/board_setup.c | 24 - arch/mips/alchemy/devboards/db1x00/platform.c | 123 +++++ arch/mips/alchemy/devboards/pb1500/board_setup.c | 33 +- arch/mips/alchemy/devboards/pb1500/platform.c | 48 ++- arch/mips/alchemy/devboards/pb1550/board_setup.c | 6 - arch/mips/alchemy/devboards/pb1550/platform.c | 48 ++- arch/mips/alchemy/gpr/board_setup.c | 12 - arch/mips/alchemy/gpr/platform.c | 47 ++ arch/mips/alchemy/mtx-1/board_setup.c | 40 -- arch/mips/alchemy/mtx-1/platform.c | 62 +++ arch/mips/alchemy/xxs1500/board_setup.c | 8 - arch/mips/include/asm/mach-au1x00/au1000.h | 142 ++++-- arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-au1000.c | 43 -- arch/mips/pci/ops-au1000.c | 308 ------------- arch/mips/pci/pci-alchemy.c | 516 ++++++++++++++++++++++ 19 files changed, 950 insertions(+), 625 deletions(-) delete mode 100644 arch/mips/alchemy/common/pci.c delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.c diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 31728e0..3792739 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -14,5 +14,3 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) obj-$(CONFIG_GPIOLIB) += gpiolib.o endif - -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c deleted file mode 100644 index 7866cf5..0000000 --- a/arch/mips/alchemy/common/pci.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1x00 PCI support. - * - * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * Support for all devices (greater than 16) added by David Gathright. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include - -#include - -/* TBD */ -static struct resource pci_io_resource = { - .start = PCI_IO_START, - .end = PCI_IO_END, - .name = "PCI IO space", - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = { - .start = PCI_MEM_START, - .end = PCI_MEM_END, - .name = "PCI memory space", - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops au1x_pci_ops; - -static struct pci_controller au1x_controller = { - .pci_ops = &au1x_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, -}; - -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) -static unsigned long virt_io_addr; -#endif - -static int __init au1x_pci_setup(void) -{ - extern void au1x_pci_cfg_init(void); - -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) - virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, - Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); - - if (!virt_io_addr) { - printk(KERN_ERR "Unable to ioremap pci space\n"); - return 1; - } - au1x_controller.io_map_base = virt_io_addr; - -#ifdef CONFIG_DMA_NONCOHERENT - { - /* - * Set the NC bit in controller for Au1500 pre-AC silicon - */ - u32 prid = read_c0_prid(); - - if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) { - au_writel((1 << 16) | au_readl(Au1500_PCI_CFG), - Au1500_PCI_CFG); - printk(KERN_INFO "Non-coherent PCI accesses enabled\n"); - } - } -#endif - - set_io_port_base(virt_io_addr); -#endif - - au1x_pci_cfg_init(); - - register_pci_controller(&au1x_controller); - return 0; -} - -arch_initcall(au1x_pci_setup); diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 1b887c8..37ffd99 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -73,8 +73,8 @@ void __init plat_mem_setup(void) /* This routine should be valid for all Au1x based boards */ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) { - u32 start = (u32)Au1500_PCI_MEM_START; - u32 end = (u32)Au1500_PCI_MEM_END; + unsigned long start = ALCHEMY_PCI_MEMWIN_START; + unsigned long end = ALCHEMY_PCI_MEMWIN_END; /* Don't fixup 36-bit addresses */ if ((phys_addr >> 32) != 0) @@ -82,7 +82,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) /* Check for PCI memory window */ if (phys_addr >= start && (phys_addr + size - 1) <= end) - return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START); + return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr); /* default nop */ return phys_addr; diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 5c956fe..2b2178f 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -40,24 +40,6 @@ #include -#ifdef CONFIG_MIPS_DB1500 -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ -}; - -#endif - - -#ifdef CONFIG_MIPS_DB1550 -char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */ - [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */ -}; -#endif - - #ifdef CONFIG_MIPS_BOSPORUS char irq_tab_alchemy[][5] __initdata = { [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */ @@ -91,12 +73,6 @@ const char *get_system_type(void) #ifdef CONFIG_MIPS_MIRAGE -char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */ - [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */ -}; - static void mirage_power_off(void) { alchemy_gpio_direction_output(210, 1); diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 70bcfb5..990367f 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -25,6 +25,8 @@ #include #include "../platform.h" +struct pci_dev; + /* DB1xxx PCMCIA interrupt sources: * CD0/1 GPIO0/3 * STSCHG0/1 GPIO1/4 @@ -85,6 +87,127 @@ #endif #endif +#ifdef CONFIG_PCI +#ifdef CONFIG_MIPS_DB1500 +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} +#endif + +#ifdef CONFIG_MIPS_DB1550 +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 11) + return (pin == 1) ? AU1550_PCI_INTC : 0xff; + if (slot == 12) { + switch (pin) { + case 1: return AU1550_PCI_INTB; + case 2: return AU1550_PCI_INTC; + case 3: return AU1550_PCI_INTD; + case 4: return AU1550_PCI_INTA; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1550_PCI_INTA; + case 2: return AU1550_PCI_INTB; + case 3: return AU1550_PCI_INTC; + case 4: return AU1550_PCI_INTD; + } + } + return -1; +} +#endif + +#ifdef CONFIG_MIPS_BOSPORUS +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 11) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + default: return 0xff; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} +#endif + +#ifdef CONFIG_MIPS_MIRAGE +static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 11) + return (pin == 1) ? AU1500_PCI_INTD : 0xff; + if (slot == 12) + return (pin == 3) ? AU1500_PCI_INTC : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + default: return 0xff; + } + } + return -1; +} +#endif + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata db1xxx_pci_pd = { + .board_map_irq = db1xxx_map_pci_irq, +}; + +static struct platform_device db1xxx_pci_host_dev = { + .dev.platform_data = &db1xxx_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + +static int __init db15x0_pci_init(void) +{ + return platform_device_register(&db1xxx_pci_host_dev); +} +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +arch_initcall(db15x0_pci_init); +#endif + static int __init db1xxx_dev_init(void) { #ifdef DB1XXX_HAS_PCMCIA diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index 3b4fa32..37c1883 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c @@ -33,13 +33,6 @@ #include - -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ -}; - - const char *get_system_type(void) { return "Alchemy Pb1500"; @@ -101,20 +94,18 @@ void __init board_setup(void) #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ #ifdef CONFIG_PCI - /* Setup PCI bus controller */ - au_writel(0, Au1500_PCI_CMEM); - au_writel(0x00003fff, Au1500_CFG_BASE); -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif - au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); - au_writel(0, Au1500_PCI_MWBASE_REV_CCL); - au_writel(0x02a00356, Au1500_PCI_STATCMD); - au_writel(0x00003c04, Au1500_PCI_HDRTYPE); - au_writel(0x00000008, Au1500_PCI_MBAR); - au_sync(); + { + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR); + /* Setup PCI bus controller */ + __raw_writel(0x00003fff, base + PCI_REG_CMEM); + __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV); + __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL); + __raw_writel(0x02a00356, base + PCI_REG_STATCMD); + __raw_writel(0x00003c04, base + PCI_REG_PARAM); + __raw_writel(0x00000008, base + PCI_REG_MBAR); + wmb(); + } #endif /* Enable sys bus clock divider when IDLE state or no bus activity. */ diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c index 42b0e6b..9f0b5a0 100644 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -19,11 +19,56 @@ */ #include +#include #include #include #include "../platform.h" +static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata pb1500_pci_pd = { + .board_map_irq = pb1500_map_pci_irq, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device pb1500_pci_host = { + .dev.platform_data = &pb1500_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + static int __init pb1500_dev_init(void) { int swapped; @@ -41,7 +86,8 @@ static int __init pb1500_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + platform_device_register(&pb1500_pci_host); return 0; } -device_initcall(pb1500_dev_init); +arch_initcall(pb1500_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c index b790213..0f62d1e 100644 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c @@ -37,12 +37,6 @@ #include - -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */ -}; - const char *get_system_type(void) { return "Alchemy Pb1550"; diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c index 87c79b7..0c5711f 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -19,13 +19,56 @@ */ #include - +#include #include #include #include #include "../platform.h" +static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) { + switch (pin) { + case 1: return AU1500_PCI_INTB; + case 2: return AU1500_PCI_INTC; + case 3: return AU1500_PCI_INTD; + case 4: return AU1500_PCI_INTA; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata pb1550_pci_pd = { + .board_map_irq = pb1550_map_pci_irq, +}; + +static struct platform_device pb1550_pci_host = { + .dev.platform_data = &pb1550_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + static int __init pb1550_dev_init(void) { int swapped; @@ -57,7 +100,8 @@ static int __init pb1550_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 4, swapped); + platform_device_register(&pb1550_pci_host); return 0; } -device_initcall(pb1550_dev_init); +arch_initcall(pb1550_dev_init); diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c index 5f8f069..dea45c7 100644 --- a/arch/mips/alchemy/gpr/board_setup.c +++ b/arch/mips/alchemy/gpr/board_setup.c @@ -36,10 +36,6 @@ #include -char irq_tab_alchemy[][5] __initdata = { - [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, -}; - static void gpr_reset(char *c) { /* switch System-LED to orange (red# and green# on) */ @@ -76,12 +72,4 @@ void __init board_setup(void) /* Take away Reset of UMTS-card */ alchemy_gpio_direction_output(215, 1); - -#ifdef CONFIG_PCI -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif -#endif } diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c index 14b4662..982ce85 100644 --- a/arch/mips/alchemy/gpr/platform.c +++ b/arch/mips/alchemy/gpr/platform.c @@ -167,6 +167,45 @@ static struct i2c_board_info gpr_i2c_info[] __initdata = { } }; + + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot == 0) && (pin == 1)) + return AU1550_PCI_INTA; + else if ((slot == 0) && (pin == 2)) + return AU1550_PCI_INTB; + + return -1; +} + +static struct alchemy_pci_platdata gpr_pci_pd = { + .board_map_irq = gpr_map_pci_irq, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device gpr_pci_host_dev = { + .dev.platform_data = &gpr_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + static struct platform_device *gpr_devices[] __initdata = { &gpr_wdt_device, &gpr_mtd_device, @@ -174,6 +213,14 @@ static struct platform_device *gpr_devices[] __initdata = { &gpr_led_devices, }; +static int __init gpr_pci_init(void) +{ + return platform_device_register(&gpr_pci_host_dev); +} +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +arch_initcall(gpr_pci_init); + + static int __init gpr_dev_init(void) { i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info)); diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index 3ae984c..851a5ab 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -38,20 +38,6 @@ #include -char irq_tab_alchemy[][5] __initdata = { - [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */ - [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ - [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */ - [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ - [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */ - [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ - [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */ - [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ -}; - -extern int (*board_pci_idsel)(unsigned int devsel, int assert); -int mtx1_pci_idsel(unsigned int devsel, int assert); - static void mtx1_reset(char *c) { /* Jump to the reset vector */ @@ -74,15 +60,6 @@ void __init board_setup(void) alchemy_gpio_direction_output(204, 0); #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ -#ifdef CONFIG_PCI -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif - board_pci_idsel = mtx1_pci_idsel; -#endif - /* Initialize sys_pinfunc */ au_writel(SYS_PF_NI2, SYS_PINFUNC); @@ -104,23 +81,6 @@ void __init board_setup(void) printk(KERN_INFO "4G Systems MTX-1 Board\n"); } -int -mtx1_pci_idsel(unsigned int devsel, int assert) -{ - /* This function is only necessary to support a proprietary Cardbus - * adapter on the mtx-1 "singleboard" variant. It triggers a custom - * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. - */ - if (assert && devsel != 0) - /* Suppress signal to Cardbus */ - alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ - else - alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */ - - udelay(1); - return 1; -} - static int __init mtx1_init_irq(void) { irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c index 55628e3..cc47b68 100644 --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/mtx-1/platform.c @@ -135,7 +135,69 @@ static struct platform_device mtx1_mtd = { .resource = &mtx1_mtd_resource, }; +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static int mtx1_pci_idsel(unsigned int devsel, int assert) +{ + /* This function is only necessary to support a proprietary Cardbus + * adapter on the mtx-1 "singleboard" variant. It triggers a custom + * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. + */ + if (assert && devsel != 0) + /* Suppress signal to Cardbus */ + alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ + else + alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */ + + udelay(1); + return 1; +} + +static const char mtx1_irqtab[][5] = { + [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */ + [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ + [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */ + [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ + [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */ + [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ + [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */ + [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ +}; + +static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + return mtx1_irqtab[slot][pin]; +} + +static struct alchemy_pci_platdata mtx1_pci_pd = { + .board_map_irq = mtx1_map_pci_irq, + .board_pci_idsel = mtx1_pci_idsel, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device mtx1_pci_host = { + .dev.platform_data = &mtx1_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + + static struct __initdata platform_device * mtx1_devs[] = { + &mtx1_pci_host, &mtx1_gpio_leds, &mtx1_wdt, &mtx1_button, diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c index 81e57fa..3fa83f7 100644 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ b/arch/mips/alchemy/xxs1500/board_setup.c @@ -70,14 +70,6 @@ void __init board_setup(void) /* Enable DTR (MCR bit 0) = USB power up */ __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); wmb(); - -#ifdef CONFIG_PCI -#if defined(__MIPSEB__) - au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); -#else - au_writel(0xf, Au1500_PCI_CFG); -#endif -#endif } static int __init xxs1500_init_irq(void) diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index bcf3d1e..5da2fd7 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -254,6 +254,14 @@ enum alchemy_usb_block { }; int alchemy_usb_control(int block, int enable); +/* PCI controller platform data */ +struct alchemy_pci_platdata { + int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); + int (*board_pci_idsel)(unsigned int devsel, int assert); + /* bits to set/clear in PCI_CONFIG register */ + unsigned long pci_cfg_set; + unsigned long pci_cfg_clr; +}; /* SOC Interrupt numbers */ @@ -1309,58 +1317,30 @@ enum soc_au1200_ints { # define AC97C_RS (1 << 1) # define AC97C_CE (1 << 0) -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) -/* Au1500 PCI Controller */ -#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ -#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) -#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) -# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \ - (1 << 25) | (1 << 26) | (1 << 27)) -#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) -#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) -#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) -#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) -#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) -#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) -#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) -#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) -#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) -#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) -#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) -#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) - -#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */ -/* - * All of our structures, like PCI resource, have 32-bit members. - * Drivers are expected to do an ioremap on the PCI MEM resource, but it's - * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch - * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and - * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM - * addresses. For PCI I/O, it's simpler because we get to do the ioremap - * ourselves and then adjust the device's resources. +/* The PCI chip selects are outside the 32bit space, and since we can't + * just program the 36bit addresses into BARs, we have to take a chunk + * out of the 32bit space and reserve it for PCI. When these addresses + * are ioremap()ed, they'll be fixed up to the real 36bit address before + * being passed to the real ioremap function. */ -#define Au1500_EXT_CFG 0x600000000ULL -#define Au1500_EXT_CFG_TYPE1 0x680000000ULL -#define Au1500_PCI_IO_START 0x500000000ULL -#define Au1500_PCI_IO_END 0x5000FFFFFULL -#define Au1500_PCI_MEM_START 0x440000000ULL -#define Au1500_PCI_MEM_END 0x44FFFFFFFULL +#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) +#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) -#define PCI_IO_START 0x00001000 -#define PCI_IO_END 0x000FFFFF -#define PCI_MEM_START 0x40000000 -#define PCI_MEM_END 0x4FFFFFFF +/* for PCI IO it's simpler because we get to do the ioremap ourselves and then + * adjust the device's resources. + */ +#define ALCHEMY_PCI_IOWIN_START 0x00001000 +#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF -#define PCI_FIRST_DEVFN (0 << 3) -#define PCI_LAST_DEVFN (19 << 3) +#ifdef CONFIG_PCI #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xfffffffffULL -#else /* Au1000 and Au1100 and Au1200 */ +#else /* Don't allow any legacy ports probing */ #define IOPORT_RESOURCE_START 0x10000000 @@ -1368,13 +1348,77 @@ enum soc_au1200_ints { #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xfffffffffULL -#define PCI_IO_START 0 -#define PCI_IO_END 0 -#define PCI_MEM_START 0 -#define PCI_MEM_END 0 -#define PCI_FIRST_DEVFN 0 -#define PCI_LAST_DEVFN 0 - #endif +/* PCI controller block register offsets */ +#define PCI_REG_CMEM 0x0000 +#define PCI_REG_CONFIG 0x0004 +#define PCI_REG_B2BMASK_CCH 0x0008 +#define PCI_REG_B2BBASE0_VID 0x000C +#define PCI_REG_B2BBASE1_SID 0x0010 +#define PCI_REG_MWMASK_DEV 0x0014 +#define PCI_REG_MWBASE_REV_CCL 0x0018 +#define PCI_REG_ERR_ADDR 0x001C +#define PCI_REG_SPEC_INTACK 0x0020 +#define PCI_REG_ID 0x0100 +#define PCI_REG_STATCMD 0x0104 +#define PCI_REG_CLASSREV 0x0108 +#define PCI_REG_PARAM 0x010C +#define PCI_REG_MBAR 0x0110 +#define PCI_REG_TIMEOUT 0x0140 + +/* PCI controller block register bits */ +#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */ +#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) +#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) +#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */ +#define PCI_CONFIG_ET (1 << 26) /* error in target mode */ +#define PCI_CONFIG_EF (1 << 25) /* fatal error */ +#define PCI_CONFIG_EP (1 << 24) /* parity error */ +#define PCI_CONFIG_EM (1 << 23) /* multiple errors */ +#define PCI_CONFIG_BM (1 << 22) /* bad master error */ +#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */ +#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */ +#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */ +#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */ +#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */ +#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */ +#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */ +#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */ +#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */ +#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */ +#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */ +#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */ +#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */ +#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */ +#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */ +#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */ +#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */ +#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */ +#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */ +#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */ +#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) +#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */ +#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) +#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) +#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) +#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) +#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) +#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) +#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) +#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) +#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) +#define PCI_ID_DID(x) (((x) & 0xffff) << 16) +#define PCI_ID_VID(x) ((x) & 0xffff) +#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) +#define PCI_STATCMD_CMD(x) ((x) & 0xffff) +#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) +#define PCI_CLASSREV_REV(x) ((x) & 0xff) +#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) +#define PCI_PARAM_HT(x) (((x) & 0xff) << 16) +#define PCI_PARAM_LT(x) (((x) & 0xff) << 8) +#define PCI_PARAM_CLS(x) ((x) & 0xff) +#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */ +#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */ + #endif diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 4df8799..bb82cbd 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -18,14 +18,13 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ ops-bcm63xx.o +obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o # # These are still pretty much in the old state, watch, go blind. # obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o -obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o -obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c deleted file mode 100644 index e2ddfc4..0000000 --- a/arch/mips/pci/fixup-au1000.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Board specific PCI fixups. - * - * Copyright 2001-2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include - -extern char irq_tab_alchemy[][5]; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_tab_alchemy[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c deleted file mode 100644 index 9a57c5a..0000000 --- a/arch/mips/pci/ops-au1000.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1xx0 PCI support. - * - * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * Support for all devices (greater than 16) added by David Gathright. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#include - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(KERN_DEBUG x) -#else -#define DBG(x...) -#endif - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -int (*board_pci_idsel)(unsigned int devsel, int assert); - -void mod_wired_entry(int entry, unsigned long entrylo0, - unsigned long entrylo1, unsigned long entryhi, - unsigned long pagemask) -{ - unsigned long old_pagemask; - unsigned long old_ctx; - - /* Save old context and create impossible VPN2 value */ - old_ctx = read_c0_entryhi() & 0xff; - old_pagemask = read_c0_pagemask(); - write_c0_index(entry); - write_c0_pagemask(pagemask); - write_c0_entryhi(entryhi); - write_c0_entrylo0(entrylo0); - write_c0_entrylo1(entrylo1); - tlb_write_indexed(); - write_c0_entryhi(old_ctx); - write_c0_pagemask(old_pagemask); -} - -static struct vm_struct *pci_cfg_vm; -static int pci_cfg_wired_entry; -static unsigned long last_entryLo0, last_entryLo1; - -/* - * We can't ioremap the entire pci config space because it's too large. - * Nor can we call ioremap dynamically because some device drivers use - * the PCI config routines from within interrupt handlers and that - * becomes a problem in get_vm_area(). We use one wired TLB to handle - * all config accesses for all busses. - */ -void __init au1x_pci_cfg_init(void) -{ - /* Reserve a wired entry for PCI config accesses */ - pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); - if (!pci_cfg_vm) - panic(KERN_ERR "PCI unable to get vm area\n"); - pci_cfg_wired_entry = read_c0_wired(); - add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); - last_entryLo0 = last_entryLo1 = 0xffffffff; -} - -static int config_access(unsigned char access_type, struct pci_bus *bus, - unsigned int dev_fn, unsigned char where, u32 *data) -{ -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) - unsigned int device = PCI_SLOT(dev_fn); - unsigned int function = PCI_FUNC(dev_fn); - unsigned long offset, status; - unsigned long cfg_base; - unsigned long flags; - int error = PCIBIOS_SUCCESSFUL; - unsigned long entryLo0, entryLo1; - - if (device > 19) { - *data = 0xffffffff; - return -1; - } - - local_irq_save(flags); - au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)), - Au1500_PCI_STATCMD); - au_sync_udelay(1); - - /* - * Allow board vendors to implement their own off-chip IDSEL. - * If it doesn't succeed, may as well bail out at this point. - */ - if (board_pci_idsel && board_pci_idsel(device, 1) == 0) { - *data = 0xffffffff; - local_irq_restore(flags); - return -1; - } - - /* Setup the config window */ - if (bus->number == 0) - cfg_base = (1 << device) << 11; - else - cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); - - /* Setup the lower bits of the 36-bit address */ - offset = (function << 8) | (where & ~0x3); - /* Pick up any address that falls below the page mask */ - offset |= cfg_base & ~PAGE_MASK; - - /* Page boundary */ - cfg_base = cfg_base & PAGE_MASK; - - /* - * To improve performance, if the current device is the same as - * the last device accessed, we don't touch the TLB. - */ - entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; - entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; - if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) { - mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, - (unsigned long)pci_cfg_vm->addr, PM_4K); - last_entryLo0 = entryLo0; - last_entryLo1 = entryLo1; - } - - if (access_type == PCI_ACCESS_WRITE) - au_writel(*data, (int)(pci_cfg_vm->addr + offset)); - else - *data = au_readl((int)(pci_cfg_vm->addr + offset)); - - au_sync_udelay(2); - - DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n", - access_type, bus->number, device, where, *data, offset); - - /* Check master abort */ - status = au_readl(Au1500_PCI_STATCMD); - - if (status & (1 << 29)) { - *data = 0xffffffff; - error = -1; - DBG("Au1x Master Abort\n"); - } else if ((status >> 28) & 0xf) { - DBG("PCI ERR detected: device %u, status %lx\n", - device, (status >> 28) & 0xf); - - /* Clear errors */ - au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD); - - *data = 0xffffffff; - error = -1; - } - - /* Take away the IDSEL. */ - if (board_pci_idsel) - (void)board_pci_idsel(device, 0); - - local_irq_restore(flags); - return error; -#endif -} - -static int read_config_byte(struct pci_bus *bus, unsigned int devfn, - int where, u8 *val) -{ - u32 data; - int ret; - - ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (where & 1) - data >>= 8; - if (where & 2) - data >>= 16; - *val = data & 0xff; - return ret; -} - -static int read_config_word(struct pci_bus *bus, unsigned int devfn, - int where, u16 *val) -{ - u32 data; - int ret; - - ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (where & 2) - data >>= 16; - *val = data & 0xffff; - return ret; -} - -static int read_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, u32 *val) -{ - int ret; - - ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); - return ret; -} - -static int write_config_byte(struct pci_bus *bus, unsigned int devfn, - int where, u8 val) -{ - u32 data = 0; - - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_word(struct pci_bus *bus, unsigned int devfn, - int where, u16 val) -{ - u32 data = 0; - - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, u32 val) -{ - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int config_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - switch (size) { - case 1: { - u8 _val; - int rc = read_config_byte(bus, devfn, where, &_val); - - *val = _val; - return rc; - } - case 2: { - u16 _val; - int rc = read_config_word(bus, devfn, where, &_val); - - *val = _val; - return rc; - } - default: - return read_config_dword(bus, devfn, where, val); - } -} - -static int config_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - switch (size) { - case 1: - return write_config_byte(bus, devfn, where, (u8) val); - case 2: - return write_config_word(bus, devfn, where, (u16) val); - default: - return write_config_dword(bus, devfn, where, val); - } -} - -struct pci_ops au1x_pci_ops = { - config_read, - config_write -}; diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c new file mode 100644 index 0000000..4ee5710 --- /dev/null +++ b/arch/mips/pci/pci-alchemy.c @@ -0,0 +1,516 @@ +/* + * Alchemy PCI host mode support. + * + * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * Support for all devices (greater than 16) added by David Gathright. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_DEBUG_PCI +#define DBG(x...) printk(KERN_DEBUG x) +#else +#define DBG(x...) do {} while (0) +#endif + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +struct alchemy_pci_context { + struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ + void __iomem *regs; /* ctrl base */ + /* tools for wired entry for config space access */ + unsigned long last_elo0; + unsigned long last_elo1; + int wired_entry; + struct vm_struct *pci_cfg_vm; + + unsigned long pm[12]; + + int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); + int (*board_pci_idsel)(unsigned int devsel, int assert); +}; + +/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr + * in arch/mips/alchemy/common/setup.c + */ +static struct resource alchemy_pci_def_memres = { + .start = ALCHEMY_PCI_MEMWIN_START, + .end = ALCHEMY_PCI_MEMWIN_END, + .name = "PCI memory space", + .flags = IORESOURCE_MEM +}; + +static struct resource alchemy_pci_def_iores = { + .start = ALCHEMY_PCI_IOWIN_START, + .end = ALCHEMY_PCI_IOWIN_END, + .name = "PCI IO space", + .flags = IORESOURCE_IO +}; + +static void mod_wired_entry(int entry, unsigned long entrylo0, + unsigned long entrylo1, unsigned long entryhi, + unsigned long pagemask) +{ + unsigned long old_pagemask; + unsigned long old_ctx; + + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & 0xff; + old_pagemask = read_c0_pagemask(); + write_c0_index(entry); + write_c0_pagemask(pagemask); + write_c0_entryhi(entryhi); + write_c0_entrylo0(entrylo0); + write_c0_entrylo1(entrylo1); + tlb_write_indexed(); + write_c0_entryhi(old_ctx); + write_c0_pagemask(old_pagemask); +} + +static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx) +{ + ctx->wired_entry = read_c0_wired(); + add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); + ctx->last_elo0 = ctx->last_elo1 = ~0; +} + +static int config_access(unsigned char access_type, struct pci_bus *bus, + unsigned int dev_fn, unsigned char where, u32 *data) +{ + struct alchemy_pci_context *ctx = bus->sysdata; + unsigned int device = PCI_SLOT(dev_fn); + unsigned int function = PCI_FUNC(dev_fn); + unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r; + int error = PCIBIOS_SUCCESSFUL; + + if (device > 19) { + *data = 0xffffffff; + return -1; + } + + /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired + * on resume, clearing our wired entry. Unfortunately the ->resume() + * callback is called way way way too late (and ->suspend() too early) + * to have them destroy and recreate it. Instead just test if c0_wired + * is now lower than the index we retrieved before suspending and then + * recreate the entry if necessary. Of course this is totally bonkers + * and breaks as soon as someone else adds another wired entry somewhere + * else. Anyone have any ideas how to handle this better? + */ + if (unlikely(read_c0_wired() < ctx->wired_entry)) + alchemy_pci_wired_entry(ctx); + + local_irq_save(flags); + r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; + r |= PCI_STATCMD_STATUS(0x2000); + __raw_writel(r, ctx->regs + PCI_REG_STATCMD); + wmb(); + + /* Allow board vendors to implement their own off-chip IDSEL. + * If it doesn't succeed, may as well bail out at this point. + */ + if (ctx->board_pci_idsel(device, 1) == 0) { + *data = 0xffffffff; + local_irq_restore(flags); + return -1; + } + + /* Setup the config window */ + if (bus->number == 0) + cfg_base = (1 << device) << 11; + else + cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); + + /* Setup the lower bits of the 36-bit address */ + offset = (function << 8) | (where & ~0x3); + /* Pick up any address that falls below the page mask */ + offset |= cfg_base & ~PAGE_MASK; + + /* Page boundary */ + cfg_base = cfg_base & PAGE_MASK; + + /* To improve performance, if the current device is the same as + * the last device accessed, we don't touch the TLB. + */ + entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; + entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; + if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) { + mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1, + (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); + ctx->last_elo0 = entryLo0; + ctx->last_elo1 = entryLo1; + } + + if (access_type == PCI_ACCESS_WRITE) + __raw_writel(*data, ctx->pci_cfg_vm->addr + offset); + else + *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); + wmb(); + + DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n", + access_type, bus->number, device, where, *data, offset); + + /* check for errors, master abort */ + status = __raw_readl(ctx->regs + PCI_REG_STATCMD); + if (status & (1 << 29)) { + *data = 0xffffffff; + error = -1; + DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d", + access_type, bus->number, device); + } else if ((status >> 28) & 0xf) { + DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", + device, (status >> 28) & 0xf); + + /* clear errors */ + __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); + + *data = 0xffffffff; + error = -1; + } + + /* Take away the IDSEL. */ + (void)ctx->board_pci_idsel(device, 0); + + local_irq_restore(flags); + return error; +} + +static int read_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 *val) +{ + u32 data; + int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + + if (where & 1) + data >>= 8; + if (where & 2) + data >>= 16; + *val = data & 0xff; + return ret; +} + +static int read_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 *val) +{ + u32 data; + int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + + if (where & 2) + data >>= 16; + *val = data & 0xffff; + return ret; +} + +static int read_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 *val) +{ + return config_access(PCI_ACCESS_READ, bus, devfn, where, val); +} + +static int write_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 val) +{ + u32 data = 0; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 val) +{ + u32 data = 0; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 val) +{ + return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val); +} + +static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + switch (size) { + case 1: { + u8 _val; + int rc = read_config_byte(bus, devfn, where, &_val); + + *val = _val; + return rc; + } + case 2: { + u16 _val; + int rc = read_config_word(bus, devfn, where, &_val); + + *val = _val; + return rc; + } + default: + return read_config_dword(bus, devfn, where, val); + } +} + +static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + switch (size) { + case 1: + return write_config_byte(bus, devfn, where, (u8) val); + case 2: + return write_config_word(bus, devfn, where, (u16) val); + default: + return write_config_dword(bus, devfn, where, val); + } +} + +static struct pci_ops alchemy_pci_ops = { + .read = alchemy_pci_read, + .write = alchemy_pci_write, +}; + +static int alchemy_pci_def_idsel(unsigned int devsel, int assert) +{ + return 1; /* success */ +} + +static int __devinit alchemy_pci_probe(struct platform_device *pdev) +{ + struct alchemy_pci_platdata *pd = pdev->dev.platform_data; + struct alchemy_pci_context *ctx; + void __iomem *virt_io; + unsigned long val; + struct resource *r; + int ret; + + /* need at least PCI IRQ mapping table */ + if (!pd) { + dev_err(&pdev->dev, "need platform data for PCI setup\n"); + ret = -ENODEV; + goto out; + } + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + dev_err(&pdev->dev, "no memory for pcictl context\n"); + ret = -ENOMEM; + goto out; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no pcictl ctrl regs resource\n"); + ret = -ENODEV; + goto out1; + } + + if (!request_mem_region(r->start, resource_size(r), pdev->name)) { + dev_err(&pdev->dev, "cannot claim pci regs\n"); + ret = -ENODEV; + goto out1; + } + + ctx->regs = ioremap_nocache(r->start, resource_size(r)); + if (!ctx->regs) { + dev_err(&pdev->dev, "cannot map pci regs\n"); + ret = -ENODEV; + goto out2; + } + + /* map parts of the PCI IO area */ + /* REVISIT: if this changes with a newer variant (doubt it) make this + * a platform resource. + */ + virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000); + if (!virt_io) { + dev_err(&pdev->dev, "cannot remap pci io space\n"); + ret = -ENODEV; + goto out3; + } + ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; + +#ifdef CONFIG_DMA_NONCOHERENT + /* Au1500 revisions older than AD have borked coherent PCI */ + if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && + (read_c0_prid() < 0x01030202)) { + val = __raw_readl(ctx->regs + PCI_REG_CONFIG); + val |= PCI_CONFIG_NC; + __raw_writel(val, ctx->regs + PCI_REG_CONFIG); + wmb(); + dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n"); + } +#endif + + if (pd->board_map_irq) + ctx->board_map_irq = pd->board_map_irq; + + if (pd->board_pci_idsel) + ctx->board_pci_idsel = pd->board_pci_idsel; + else + ctx->board_pci_idsel = alchemy_pci_def_idsel; + + /* fill in relevant pci_controller members */ + ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops; + ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres; + ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores; + + /* we can't ioremap the entire pci config space because it's too large, + * nor can we dynamically ioremap it because some drivers use the + * PCI config routines from within atomic contex and that becomes a + * problem in get_vm_area(). Instead we use one wired TLB entry to + * handle all config accesses for all busses. + */ + ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); + if (!ctx->pci_cfg_vm) { + dev_err(&pdev->dev, "unable to get vm area\n"); + ret = -ENOMEM; + goto out4; + } + ctx->wired_entry = 8192; /* impossibly high value */ + + set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); + + /* board may want to modify bits in the config register, do it now */ + val = __raw_readl(ctx->regs + PCI_REG_CONFIG); + val &= ~pd->pci_cfg_clr; + val |= pd->pci_cfg_set; + val &= ~PCI_CONFIG_PD; /* clear disable bit */ + __raw_writel(val, ctx->regs + PCI_REG_CONFIG); + wmb(); + + platform_set_drvdata(pdev, ctx); + register_pci_controller(&ctx->alchemy_pci_ctrl); + + return 0; + +out4: + iounmap(virt_io); +out3: + iounmap(ctx->regs); +out2: + release_mem_region(r->start, resource_size(r)); +out1: + kfree(ctx); +out: + return ret; +} + + +#ifdef CONFIG_PM +/* save PCI controller register contents. */ +static int alchemy_pci_suspend(struct device *dev) +{ + struct alchemy_pci_context *ctx = dev_get_drvdata(dev); + + ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); + ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; + ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); + ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); + ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); + ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); + ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); + ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); + ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); + ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); + ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); + ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); + + return 0; +} + +static int alchemy_pci_resume(struct device *dev) +{ + struct alchemy_pci_context *ctx = dev_get_drvdata(dev); + + __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); + __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); + __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); + __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); + __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); + __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); + __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); + __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); + __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); + __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); + __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); + wmb(); + __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); + wmb(); + + return 0; +} + +static const struct dev_pm_ops alchemy_pci_pmops = { + .suspend = alchemy_pci_suspend, + .resume = alchemy_pci_resume, +}; + +#define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops) + +#else +#define ALCHEMY_PCICTL_PM NULL +#endif + +static struct platform_driver alchemy_pcictl_driver = { + .probe = alchemy_pci_probe, + .driver = { + .name = "alchemy-pci", + .owner = THIS_MODULE, + .pm = ALCHEMY_PCICTL_PM, + }, +}; + +static int __init alchemy_pci_init(void) +{ + /* Au1500/Au1550 have PCI */ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1550: + return platform_driver_register(&alchemy_pcictl_driver); + } + return 0; +} +arch_initcall(alchemy_pci_init); + + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct alchemy_pci_context *ctx = dev->sysdata; + if (ctx && ctx->board_map_irq) + return ctx->board_map_irq(dev, slot, pin); + return -1; +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} -- 1.7.6 From manuel.lauss@googlemail.com Fri Aug 12 11:40:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 11:44:03 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:50901 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491754Ab1HLJkG (ORCPT ); Fri, 12 Aug 2011 11:40:06 +0200 Received: by mail-fx0-f49.google.com with SMTP id 20so2860465fxd.36 for ; Fri, 12 Aug 2011 02:40:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=lLoYWUSQHZ7E0/vvrjadXrdXAHb3fFObz1wOBuGj0DY=; b=nJEiRzCmHE1Mmwf71GiOB7Ij28n5jh7Ys0z78FiogHOphktsk1E7vbFLG9pKkv9WfY Q058BYar0immk40kkN/H+XEXPODeBrF4xMyxEIoOH6CXXUifL4g0xaick24lJekvK4kk HOby//fLRspBmMCzl2ofXwetGBlqcWlcra8FQ= Received: by 10.223.161.214 with SMTP id s22mr989889fax.59.1313142006091; Fri, 12 Aug 2011 02:40:06 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id s14sm467338fah.29.2011.08.12.02.40.04 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 02:40:05 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 8/8] MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines Date: Fri, 12 Aug 2011 11:39:45 +0200 Message-Id: <1313141985-5830-9-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 30863 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9269 Content-Length: 37637 Lines: 1297 Now that no driver any longer depends on the CONFIG_SOC_AU1??? symbols, it's time to get rid of them: Move some of the platform devices to the boards which can use them, Rename a few (unused) constants in the header, Replace them with MIPS_ALCHEMY in the various Kconfig files. Finally delete them altogether from the Alchemy Kconfig file. Signed-off-by: Manuel Lauss --- This patch will throw merge conflicts with changes in the ASoC tree. arch/mips/Kconfig | 2 + arch/mips/alchemy/Kconfig | 50 ++---- arch/mips/alchemy/common/platform.c | 175 +------------------ arch/mips/alchemy/devboards/db1200/platform.c | 78 ++++++++- arch/mips/alchemy/devboards/db1x00/board_setup.c | 4 +- arch/mips/alchemy/devboards/db1x00/platform.c | 32 ++++ arch/mips/alchemy/devboards/pb1100/platform.c | 29 +++ arch/mips/alchemy/devboards/pb1200/platform.c | 137 ++++++++++++++- arch/mips/alchemy/devboards/pb1500/platform.c | 1 + arch/mips/alchemy/devboards/pb1550/platform.c | 33 ++++ arch/mips/include/asm/mach-au1x00/au1000.h | 203 ++++++++++------------ drivers/i2c/busses/Kconfig | 2 +- drivers/ide/Kconfig | 6 +- drivers/mmc/host/Kconfig | 2 +- drivers/mtd/nand/Kconfig | 2 +- drivers/net/irda/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/usb/Kconfig | 1 - drivers/usb/host/ehci-hcd.c | 2 +- drivers/video/Kconfig | 4 +- sound/mips/Kconfig | 2 +- sound/soc/au1x/Kconfig | 2 +- 22 files changed, 423 insertions(+), 348 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 177cdaf..32e7e3c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -46,6 +46,8 @@ config MIPS_ALCHEMY select GENERIC_GPIO select ARCH_WANT_OPTIONAL_GPIOLIB select SYS_SUPPORTS_ZBOOT + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI config AR7 bool "Texas Instruments AR7" diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 2ccfd4a..2a68be6 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -18,20 +18,20 @@ config MIPS_MTX1 bool "4G Systems MTX-1 board" select DMA_NONCOHERENT select HW_HAS_PCI - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_BOSPORUS bool "Alchemy Bosporus board" - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_DB1000 bool "Alchemy DB1000 board" - select SOC_AU1000 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select SYS_SUPPORTS_LITTLE_ENDIAN @@ -39,14 +39,14 @@ config MIPS_DB1000 config MIPS_DB1100 bool "Alchemy DB1100 board" - select SOC_AU1100 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_DB1200 bool "Alchemy DB1200 board" - select SOC_AU1200 + select ALCHEMY_GPIOINT_AU1000 select DMA_COHERENT select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN @@ -54,7 +54,7 @@ config MIPS_DB1200 config MIPS_DB1500 bool "Alchemy DB1500 board" - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_DISABLE_OBSOLETE_IDE @@ -64,7 +64,7 @@ config MIPS_DB1500 config MIPS_DB1550 bool "Alchemy DB1550 board" - select SOC_AU1550 + select ALCHEMY_GPIOINT_AU1000 select HW_HAS_PCI select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE @@ -74,13 +74,13 @@ config MIPS_DB1550 config MIPS_MIRAGE bool "Alchemy Mirage board" select DMA_NONCOHERENT - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_PB1000 bool "Alchemy PB1000 board" - select SOC_AU1000 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select SWAP_IO_SPACE @@ -89,7 +89,7 @@ config MIPS_PB1000 config MIPS_PB1100 bool "Alchemy PB1100 board" - select SOC_AU1100 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select SWAP_IO_SPACE @@ -98,7 +98,7 @@ config MIPS_PB1100 config MIPS_PB1200 bool "Alchemy PB1200 board" - select SOC_AU1200 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN @@ -106,7 +106,7 @@ config MIPS_PB1200 config MIPS_PB1500 bool "Alchemy PB1500 board" - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select SYS_SUPPORTS_LITTLE_ENDIAN @@ -114,7 +114,7 @@ config MIPS_PB1500 config MIPS_PB1550 bool "Alchemy PB1550 board" - select SOC_AU1550 + select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_DISABLE_OBSOLETE_IDE @@ -124,13 +124,13 @@ config MIPS_PB1550 config MIPS_XXS1500 bool "MyCable XXS1500 board" select DMA_NONCOHERENT - select SOC_AU1500 + select ALCHEMY_GPIOINT_AU1000 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_GPR bool "Trapeze ITS GPR board" - select SOC_AU1550 + select ALCHEMY_GPIOINT_AU1000 select HW_HAS_PCI select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE @@ -138,23 +138,3 @@ config MIPS_GPR select SYS_HAS_EARLY_PRINTK endchoice - -config SOC_AU1000 - bool - select ALCHEMY_GPIOINT_AU1000 - -config SOC_AU1100 - bool - select ALCHEMY_GPIOINT_AU1000 - -config SOC_AU1500 - bool - select ALCHEMY_GPIOINT_AU1000 - -config SOC_AU1550 - bool - select ALCHEMY_GPIOINT_AU1000 - -config SOC_AU1200 - bool - select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 657ae27..c8e5d72 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -189,159 +189,6 @@ static void __init alchemy_setup_usb(int ctype) } } -/*** AU1100 LCD controller ***/ - -#ifdef CONFIG_FB_AU1100 -static struct resource au1100_lcd_resources[] = { - [0] = { - .start = AU1100_LCD_PHYS_ADDR, - .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1100_LCD_INT, - .end = AU1100_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1100_lcd_device = { - .name = "au1100-lcd", - .id = 0, - .dev = { - .dma_mask = &au1100_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1100_lcd_resources), - .resource = au1100_lcd_resources, -}; -#endif - -#ifdef CONFIG_SOC_AU1200 - -static struct resource au1200_lcd_resources[] = { - [0] = { - .start = AU1200_LCD_PHYS_ADDR, - .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_LCD_INT, - .end = AU1200_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1200_lcd_device = { - .name = "au1200-lcd", - .id = 0, - .dev = { - .dma_mask = &au1200_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1200_lcd_resources), - .resource = au1200_lcd_resources, -}; - -static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); - -extern struct au1xmmc_platform_data au1xmmc_platdata[2]; - -static struct resource au1200_mmc0_resources[] = { - [0] = { - .start = AU1100_SD0_PHYS_ADDR, - .end = AU1100_SD0_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_SDMS_TX0, - .end = AU1200_DSCR_CMD0_SDMS_TX0, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_SDMS_RX0, - .end = AU1200_DSCR_CMD0_SDMS_RX0, - .flags = IORESOURCE_DMA, - } -}; - -static struct platform_device au1200_mmc0_device = { - .name = "au1xxx-mmc", - .id = 0, - .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &au1xmmc_platdata[0], - }, - .num_resources = ARRAY_SIZE(au1200_mmc0_resources), - .resource = au1200_mmc0_resources, -}; - -#ifndef CONFIG_MIPS_DB1200 -static struct resource au1200_mmc1_resources[] = { - [0] = { - .start = AU1100_SD1_PHYS_ADDR, - .end = AU1100_SD1_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_SDMS_TX1, - .end = AU1200_DSCR_CMD0_SDMS_TX1, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_SDMS_RX1, - .end = AU1200_DSCR_CMD0_SDMS_RX1, - .flags = IORESOURCE_DMA, - } -}; - -static struct platform_device au1200_mmc1_device = { - .name = "au1xxx-mmc", - .id = 1, - .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &au1xmmc_platdata[1], - }, - .num_resources = ARRAY_SIZE(au1200_mmc1_resources), - .resource = au1200_mmc1_resources, -}; -#endif /* #ifndef CONFIG_MIPS_DB1200 */ -#endif /* #ifdef CONFIG_SOC_AU1200 */ - -/* All Alchemy demoboards with I2C have this #define in their headers */ -#ifdef SMBUS_PSC_BASE -static struct resource pbdb_smbus_resources[] = { - { - .start = SMBUS_PSC_BASE, - .end = SMBUS_PSC_BASE + 0xfff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device pbdb_smbus_device = { - .name = "au1xpsc_smbus", - .id = 0, /* bus number */ - .num_resources = ARRAY_SIZE(pbdb_smbus_resources), - .resource = pbdb_smbus_resources, -}; -#endif - /* Macro to help defining the Ethernet MAC resources */ #define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */ #define MAC_RES(_base, _enable, _irq, _macdma) \ @@ -503,33 +350,15 @@ static void __init alchemy_setup_macs(int ctype) } } -static struct platform_device *au1xxx_platform_devices[] __initdata = { -#ifdef CONFIG_FB_AU1100 - &au1100_lcd_device, -#endif -#ifdef CONFIG_SOC_AU1200 - &au1200_lcd_device, - &au1200_mmc0_device, -#ifndef CONFIG_MIPS_DB1200 - &au1200_mmc1_device, -#endif -#endif -#ifdef SMBUS_PSC_BASE - &pbdb_smbus_device, -#endif -}; - static int __init au1xxx_platform_init(void) { - int err, ctype = alchemy_get_cputype(); + int ctype = alchemy_get_cputype(); alchemy_setup_uarts(ctype); alchemy_setup_macs(ctype); alchemy_setup_usb(ctype); - err = platform_add_devices(au1xxx_platform_devices, - ARRAY_SIZE(au1xxx_platform_devices)); - return err; + return 0; } arch_initcall(au1xxx_platform_init); diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index 1bc16f0..aae08c1 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -333,15 +333,77 @@ static struct led_classdev db1200_mmc_led = { .brightness_set = db1200_mmcled_set, }; -/* needed by arch/mips/alchemy/common/platform.c */ -struct au1xmmc_platform_data au1xmmc_platdata[] = { +static struct au1xmmc_platform_data db1200mmc_platdata = { + .cd_setup = db1200_mmc_cd_setup, + .set_power = db1200_mmc_set_power, + .card_inserted = db1200_mmc_card_inserted, + .card_readonly = db1200_mmc_card_readonly, + .led = &db1200_mmc_led, +}; + +static struct resource au1200_mmc0_resources[] = { + [0] = { + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_SDMS_TX0, + .end = AU1200_DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_SDMS_RX0, + .end = AU1200_DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); + +static struct platform_device db1200_mmc0_dev = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1200mmc_platdata, + }, + .num_resources = ARRAY_SIZE(au1200_mmc0_resources), + .resource = au1200_mmc0_resources, +}; + +/**********************************************************************/ + +static struct resource au1200_lcd_res[] = { [0] = { - .cd_setup = db1200_mmc_cd_setup, - .set_power = db1200_mmc_set_power, - .card_inserted = db1200_mmc_card_inserted, - .card_readonly = db1200_mmc_card_readonly, - .led = &db1200_mmc_led, + .start = AU1200_LCD_PHYS_ADDR, + .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_LCD_INT, + .end = AU1200_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1200_lcd_dev = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1200_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), }, + .num_resources = ARRAY_SIZE(au1200_lcd_res), + .resource = au1200_lcd_res, }; /**********************************************************************/ @@ -442,6 +504,8 @@ static struct platform_device db1200_stac_dev = { static struct platform_device *db1200_devs[] __initdata = { NULL, /* PSC0, selected by S6.8 */ &db1200_ide_dev, + &db1200_mmc0_dev, + &au1200_lcd_dev, &db1200_eth_dev, &db1200_rtc_dev, &db1200_nand_dev, diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 2b2178f..7cd36e6 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -134,9 +134,7 @@ void __init board_setup(void) /* initialize board register space */ bcsr_init(bcsr1, bcsr2); - /* Not valid for Au1550 */ -#if defined(CONFIG_IRDA) && \ - (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100)) +#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) { u32 pin_func; diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 990367f..8704865 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -19,6 +19,7 @@ */ #include +#include #include #include @@ -208,6 +209,34 @@ static int __init db15x0_pci_init(void) arch_initcall(db15x0_pci_init); #endif +#ifdef CONFIG_MIPS_DB1100 +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; +#endif + static int __init db1xxx_dev_init(void) { #ifdef DB1XXX_HAS_PCMCIA @@ -231,6 +260,9 @@ static int __init db1xxx_dev_init(void) DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); #endif +#ifdef CONFIG_MIPS_DB1100 + platform_device_register(&au1100_lcd_device); +#endif db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); return 0; } diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c index 8a4e733..9c57c01 100644 --- a/arch/mips/alchemy/devboards/pb1100/platform.c +++ b/arch/mips/alchemy/devboards/pb1100/platform.c @@ -19,12 +19,40 @@ */ #include +#include +#include #include #include #include "../platform.h" +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; + static int __init pb1100_dev_init(void) { int swapped; @@ -42,6 +70,7 @@ static int __init pb1100_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + platform_device_register(&au1100_lcd_device); return 0; } diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index d7915b0..54f7f7b 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -90,7 +90,7 @@ static int pb1200mmc1_card_inserted(void *mmc_host) return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; } -const struct au1xmmc_platform_data au1xmmc_platdata[2] = { +static struct au1xmmc_platform_data pb1200mmc_platdata[2] = { [0] = { .set_power = pb1200mmc0_set_power, .card_inserted = pb1200mmc0_card_inserted, @@ -107,6 +107,79 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = { }, }; +static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); + +static struct resource au1200_mmc0_res[] = { + [0] = { + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_SDMS_TX0, + .end = AU1200_DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_SDMS_RX0, + .end = AU1200_DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device pb1200_mmc0_dev = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &pb1200mmc_platdata[0], + }, + .num_resources = ARRAY_SIZE(au1200_mmc0_res), + .resource = au1200_mmc0_res, +}; + +static struct resource au1200_mmc1_res[] = { + [0] = { + .start = AU1100_SD1_PHYS_ADDR, + .end = AU1100_SD1_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_SDMS_TX1, + .end = AU1200_DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_SDMS_RX1, + .end = AU1200_DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device pb1200_mmc1_dev = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &pb1200mmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1200_mmc1_res), + .resource = au1200_mmc1_res, +}; + + static struct resource ide_resources[] = { [0] = { .start = IDE_PHYS_ADDR, @@ -168,9 +241,69 @@ static struct platform_device smc91c111_device = { .resource = smc91c111_resources }; +static struct resource au1200_psc0_res[] = { + [0] = { + .start = AU1550_PSC0_PHYS_ADDR, + .end = AU1550_PSC0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_PSC0_INT, + .end = AU1200_PSC0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_PSC0_TX, + .end = AU1200_DSCR_CMD0_PSC0_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_PSC0_RX, + .end = AU1200_DSCR_CMD0_PSC0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device pb1200_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1200_psc0_res), + .resource = au1200_psc0_res, +}; + +static struct resource au1200_lcd_res[] = { + [0] = { + .start = AU1200_LCD_PHYS_ADDR, + .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_LCD_INT, + .end = AU1200_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1200_lcd_dev = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1200_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1200_lcd_res), + .resource = au1200_lcd_res, +}; + static struct platform_device *board_platform_devices[] __initdata = { &ide_device, - &smc91c111_device + &smc91c111_device, + &pb1200_i2c_dev, + &pb1200_mmc0_dev, + &pb1200_mmc1_dev, + &au1200_lcd_dev, }; static int __init board_register_devices(void) diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c index 9f0b5a0..1e52a01 100644 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c index 0c5711f..a4604b8 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -18,9 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include +#include #include #include @@ -69,6 +71,36 @@ static struct platform_device pb1550_pci_host = { .resource = alchemy_pci_host_res, }; +static struct resource au1550_psc2_res[] = { + [0] = { + .start = AU1550_PSC2_PHYS_ADDR, + .end = AU1550_PSC2_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC2_INT, + .end = AU1550_PSC2_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC2_TX, + .end = AU1550_DSCR_CMD0_PSC2_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC2_RX, + .end = AU1550_DSCR_CMD0_PSC2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device pb1550_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1550_psc2_res), + .resource = au1550_psc2_res, +}; + static int __init pb1550_dev_init(void) { int swapped; @@ -101,6 +133,7 @@ static int __init pb1550_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 4, swapped); platform_device_register(&pb1550_pci_host); + platform_device_register(&pb1550_i2c_dev); return 0; } diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 5da2fd7..4afc3a9 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -592,113 +592,6 @@ enum soc_au1200_ints { #endif /* !defined (_LANGUAGE_ASSEMBLY) */ /* - * SDRAM register offsets - */ -#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ - defined(CONFIG_SOC_AU1100) -#define MEM_SDMODE0 0x0000 -#define MEM_SDMODE1 0x0004 -#define MEM_SDMODE2 0x0008 -#define MEM_SDADDR0 0x000C -#define MEM_SDADDR1 0x0010 -#define MEM_SDADDR2 0x0014 -#define MEM_SDREFCFG 0x0018 -#define MEM_SDPRECMD 0x001C -#define MEM_SDAUTOREF 0x0020 -#define MEM_SDWRMD0 0x0024 -#define MEM_SDWRMD1 0x0028 -#define MEM_SDWRMD2 0x002C -#define MEM_SDSLEEP 0x0030 -#define MEM_SDSMCKE 0x0034 - -/* - * MEM_SDMODE register content definitions - */ -#define MEM_SDMODE_F (1 << 22) -#define MEM_SDMODE_SR (1 << 21) -#define MEM_SDMODE_BS (1 << 20) -#define MEM_SDMODE_RS (3 << 18) -#define MEM_SDMODE_CS (7 << 15) -#define MEM_SDMODE_TRAS (15 << 11) -#define MEM_SDMODE_TMRD (3 << 9) -#define MEM_SDMODE_TWR (3 << 7) -#define MEM_SDMODE_TRP (3 << 5) -#define MEM_SDMODE_TRCD (3 << 3) -#define MEM_SDMODE_TCL (7 << 0) - -#define MEM_SDMODE_BS_2Bank (0 << 20) -#define MEM_SDMODE_BS_4Bank (1 << 20) -#define MEM_SDMODE_RS_11Row (0 << 18) -#define MEM_SDMODE_RS_12Row (1 << 18) -#define MEM_SDMODE_RS_13Row (2 << 18) -#define MEM_SDMODE_RS_N(N) ((N) << 18) -#define MEM_SDMODE_CS_7Col (0 << 15) -#define MEM_SDMODE_CS_8Col (1 << 15) -#define MEM_SDMODE_CS_9Col (2 << 15) -#define MEM_SDMODE_CS_10Col (3 << 15) -#define MEM_SDMODE_CS_11Col (4 << 15) -#define MEM_SDMODE_CS_N(N) ((N) << 15) -#define MEM_SDMODE_TRAS_N(N) ((N) << 11) -#define MEM_SDMODE_TMRD_N(N) ((N) << 9) -#define MEM_SDMODE_TWR_N(N) ((N) << 7) -#define MEM_SDMODE_TRP_N(N) ((N) << 5) -#define MEM_SDMODE_TRCD_N(N) ((N) << 3) -#define MEM_SDMODE_TCL_N(N) ((N) << 0) - -/* - * MEM_SDADDR register contents definitions - */ -#define MEM_SDADDR_E (1 << 20) -#define MEM_SDADDR_CSBA (0x03FF << 10) -#define MEM_SDADDR_CSMASK (0x03FF << 0) -#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) -#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) - -/* - * MEM_SDREFCFG register content definitions - */ -#define MEM_SDREFCFG_TRC (15 << 28) -#define MEM_SDREFCFG_TRPM (3 << 26) -#define MEM_SDREFCFG_E (1 << 25) -#define MEM_SDREFCFG_RE (0x1ffffff << 0) -#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) -#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) -#define MEM_SDREFCFG_REF_N(N) (N) -#endif - -/***********************************************************************/ - -/* - * Au1550 SDRAM Register Offsets - */ - -/***********************************************************************/ - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#define MEM_SDMODE0 0x0800 -#define MEM_SDMODE1 0x0808 -#define MEM_SDMODE2 0x0810 -#define MEM_SDADDR0 0x0820 -#define MEM_SDADDR1 0x0828 -#define MEM_SDADDR2 0x0830 -#define MEM_SDCONFIGA 0x0840 -#define MEM_SDCONFIGB 0x0848 -#define MEM_SDSTAT 0x0850 -#define MEM_SDERRADDR 0x0858 -#define MEM_SDSTRIDE0 0x0860 -#define MEM_SDSTRIDE1 0x0868 -#define MEM_SDSTRIDE2 0x0870 -#define MEM_SDWRMD0 0x0880 -#define MEM_SDWRMD1 0x0888 -#define MEM_SDWRMD2 0x0890 -#define MEM_SDPRECMD 0x08C0 -#define MEM_SDAUTOREF 0x08C8 -#define MEM_SDSREF 0x08D0 -#define MEM_SDSLEEP MEM_SDSREF - -#endif - -/* * Physical base addresses for integrated peripherals * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 */ @@ -761,6 +654,92 @@ enum soc_au1200_ints { #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ +/* Au1000 SDRAM memory controller register offsets */ +#define AU1000_MEM_SDMODE0 0x0000 +#define AU1000_MEM_SDMODE1 0x0004 +#define AU1000_MEM_SDMODE2 0x0008 +#define AU1000_MEM_SDADDR0 0x000C +#define AU1000_MEM_SDADDR1 0x0010 +#define AU1000_MEM_SDADDR2 0x0014 +#define AU1000_MEM_SDREFCFG 0x0018 +#define AU1000_MEM_SDPRECMD 0x001C +#define AU1000_MEM_SDAUTOREF 0x0020 +#define AU1000_MEM_SDWRMD0 0x0024 +#define AU1000_MEM_SDWRMD1 0x0028 +#define AU1000_MEM_SDWRMD2 0x002C +#define AU1000_MEM_SDSLEEP 0x0030 +#define AU1000_MEM_SDSMCKE 0x0034 + +/* MEM_SDMODE register content definitions */ +#define MEM_SDMODE_F (1 << 22) +#define MEM_SDMODE_SR (1 << 21) +#define MEM_SDMODE_BS (1 << 20) +#define MEM_SDMODE_RS (3 << 18) +#define MEM_SDMODE_CS (7 << 15) +#define MEM_SDMODE_TRAS (15 << 11) +#define MEM_SDMODE_TMRD (3 << 9) +#define MEM_SDMODE_TWR (3 << 7) +#define MEM_SDMODE_TRP (3 << 5) +#define MEM_SDMODE_TRCD (3 << 3) +#define MEM_SDMODE_TCL (7 << 0) + +#define MEM_SDMODE_BS_2Bank (0 << 20) +#define MEM_SDMODE_BS_4Bank (1 << 20) +#define MEM_SDMODE_RS_11Row (0 << 18) +#define MEM_SDMODE_RS_12Row (1 << 18) +#define MEM_SDMODE_RS_13Row (2 << 18) +#define MEM_SDMODE_RS_N(N) ((N) << 18) +#define MEM_SDMODE_CS_7Col (0 << 15) +#define MEM_SDMODE_CS_8Col (1 << 15) +#define MEM_SDMODE_CS_9Col (2 << 15) +#define MEM_SDMODE_CS_10Col (3 << 15) +#define MEM_SDMODE_CS_11Col (4 << 15) +#define MEM_SDMODE_CS_N(N) ((N) << 15) +#define MEM_SDMODE_TRAS_N(N) ((N) << 11) +#define MEM_SDMODE_TMRD_N(N) ((N) << 9) +#define MEM_SDMODE_TWR_N(N) ((N) << 7) +#define MEM_SDMODE_TRP_N(N) ((N) << 5) +#define MEM_SDMODE_TRCD_N(N) ((N) << 3) +#define MEM_SDMODE_TCL_N(N) ((N) << 0) + +/* MEM_SDADDR register contents definitions */ +#define MEM_SDADDR_E (1 << 20) +#define MEM_SDADDR_CSBA (0x03FF << 10) +#define MEM_SDADDR_CSMASK (0x03FF << 0) +#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) +#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) + +/* MEM_SDREFCFG register content definitions */ +#define MEM_SDREFCFG_TRC (15 << 28) +#define MEM_SDREFCFG_TRPM (3 << 26) +#define MEM_SDREFCFG_E (1 << 25) +#define MEM_SDREFCFG_RE (0x1ffffff << 0) +#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) +#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) +#define MEM_SDREFCFG_REF_N(N) (N) + +/* Au1550 SDRAM Register Offsets */ +#define AU1550_MEM_SDMODE0 0x0800 +#define AU1550_MEM_SDMODE1 0x0808 +#define AU1550_MEM_SDMODE2 0x0810 +#define AU1550_MEM_SDADDR0 0x0820 +#define AU1550_MEM_SDADDR1 0x0828 +#define AU1550_MEM_SDADDR2 0x0830 +#define AU1550_MEM_SDCONFIGA 0x0840 +#define AU1550_MEM_SDCONFIGB 0x0848 +#define AU1550_MEM_SDSTAT 0x0850 +#define AU1550_MEM_SDERRADDR 0x0858 +#define AU1550_MEM_SDSTRIDE0 0x0860 +#define AU1550_MEM_SDSTRIDE1 0x0868 +#define AU1550_MEM_SDSTRIDE2 0x0870 +#define AU1550_MEM_SDWRMD0 0x0880 +#define AU1550_MEM_SDWRMD1 0x0888 +#define AU1550_MEM_SDWRMD2 0x0890 +#define AU1550_MEM_SDPRECMD 0x08C0 +#define AU1550_MEM_SDAUTOREF 0x08C8 +#define AU1550_MEM_SDSREF 0x08D0 +#define AU1550_MEM_SDSLEEP MEM_SDSREF + /* Static Bus Controller */ #define MEM_STCFG0 0xB4001000 #define MEM_STTIME0 0xB4001004 @@ -778,14 +757,12 @@ enum soc_au1200_ints { #define MEM_STTIME3 0xB4001034 #define MEM_STADDR3 0xB4001038 -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) #define MEM_STNDCTL 0xB4001100 #define MEM_STSTAT 0xB4001104 #define MEM_STNAND_CMD 0x0 #define MEM_STNAND_ADDR 0x4 #define MEM_STNAND_DATA 0x20 -#endif /* Programmable Counters 0 and 1 */ @@ -1172,7 +1149,6 @@ enum soc_au1200_ints { # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) /* Au1200 only */ -#ifdef CONFIG_SOC_AU1200 #define SYS_PINFUNC_DMA (1 << 31) #define SYS_PINFUNC_S0A (1 << 30) #define SYS_PINFUNC_S1A (1 << 29) @@ -1200,7 +1176,6 @@ enum soc_au1200_ints { #define SYS_PINFUNC_P0B (1 << 4) #define SYS_PINFUNC_U0T (1 << 3) #define SYS_PINFUNC_S1B (1 << 2) -#endif /* Power Management */ #define SYS_SCRATCH0 0xB1900018 @@ -1256,12 +1231,12 @@ enum soc_au1200_ints { # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) # define SYS_CS_DI2 (1 << 16) # define SYS_CS_CI2 (1 << 15) -#ifdef CONFIG_SOC_AU1100 + # define SYS_CS_ML_BIT 7 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) # define SYS_CS_DL (1 << 6) # define SYS_CS_CL (1 << 5) -#else + # define SYS_CS_MUH_BIT 12 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) # define SYS_CS_DUH (1 << 11) @@ -1270,7 +1245,7 @@ enum soc_au1200_ints { # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) # define SYS_CS_DUD (1 << 6) # define SYS_CS_CUD (1 << 5) -#endif + # define SYS_CS_MIR_BIT 2 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) # define SYS_CS_DIR (1 << 1) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 646068e..1908195 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -301,7 +301,7 @@ config I2C_AT91 config I2C_AU1550 tristate "Au1550/Au1200 SMBus interface" - depends on SOC_AU1550 || SOC_AU1200 + depends on MIPS_ALCHEMY help If you say yes to this option, support will be included for the Au1550 and Au1200 SMBus interface. diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index 9827c5e..ec42e6c 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig @@ -677,19 +677,19 @@ config BLK_DEV_IDE_PMAC_ATA100FIRST config BLK_DEV_IDE_AU1XXX bool "IDE for AMD Alchemy Au1200" - depends on SOC_AU1200 + depends on MIPS_ALCHEMY select IDE_XFER_MODE choice prompt "IDE Mode for AMD Alchemy Au1200" default CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA - depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX + depends on BLK_DEV_IDE_AU1XXX config BLK_DEV_IDE_AU1XXX_PIO_DBDMA bool "PIO+DbDMA IDE for AMD Alchemy Au1200" config BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA bool "MDMA2+DbDMA IDE for AMD Alchemy Au1200" - depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX + depends on BLK_DEV_IDE_AU1XXX endchoice config BLK_DEV_IDE_TX4938 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 8c87096..6d74f49 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -263,7 +263,7 @@ config MMC_WBSD config MMC_AU1X tristate "Alchemy AU1XX0 MMC Card Interface support" - depends on SOC_AU1200 + depends on MIPS_ALCHEMY help This selects the AMD Alchemy(R) Multimedia card interface. If you have a Alchemy platform with a MMC slot, say Y or M here. diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 4c34252..dbfa0f7 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -138,7 +138,7 @@ config MTD_NAND_RICOH config MTD_NAND_AU1550 tristate "Au1550/1200 NAND support" - depends on SOC_AU1200 || SOC_AU1550 + depends on MIPS_ALCHEMY help This enables the driver for the NAND flash controller on the AMD/Alchemy 1550 SOC. diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig index 25bb2a0..0cda6c4 100644 --- a/drivers/net/irda/Kconfig +++ b/drivers/net/irda/Kconfig @@ -314,7 +314,7 @@ config TOSHIBA_FIR config AU1000_FIR tristate "Alchemy Au1000 SIR/FIR" - depends on SOC_AU1000 && IRDA + depends on IRDA && MIPS_ALCHEMY config SMC_IRCC_FIR tristate "SMSC IrCC (EXPERIMENTAL)" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 52e2900..a1fd73d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -88,7 +88,7 @@ config SPI_BFIN_SPORT config SPI_AU1550 tristate "Au1550/Au12x0 SPI Controller" - depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL + depends on MIPS_ALCHEMY && EXPERIMENTAL select SPI_BITBANG help If you say yes to this option, support will be included for the diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 48f1781..85d5a01 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -56,7 +56,6 @@ config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx default y if PPC_MPC512x - default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 default y if ARCH_AT91SAM9G45 diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index f72ae0b..47aa22d 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1196,7 +1196,7 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_hcd_sh_driver #endif -#ifdef CONFIG_SOC_AU1200 +#ifdef CONFIG_MIPS_ALCHEMY #include "ehci-au1xxx.c" #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver #endif diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 549b960..55a7df4 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1744,7 +1744,7 @@ endchoice config FB_AU1100 bool "Au1100 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1100 + depends on (FB = y) && MIPS_ALCHEMY select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -1755,7 +1755,7 @@ config FB_AU1100 config FB_AU1200 bool "Au1200 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1200 + depends on (FB = y) && MIPS_ALCHEMY select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT diff --git a/sound/mips/Kconfig b/sound/mips/Kconfig index a9823fa..0a0d501 100644 --- a/sound/mips/Kconfig +++ b/sound/mips/Kconfig @@ -24,7 +24,7 @@ config SND_SGI_HAL2 config SND_AU1X00 tristate "Au1x00 AC97 Port Driver" - depends on SOC_AU1000 || SOC_AU1100 || SOC_AU1500 + depends on MIPS_ALCHEMY select SND_PCM select SND_AC97_CODEC help diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index 4b67140..606039f 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -3,7 +3,7 @@ ## config SND_SOC_AU1XPSC tristate "SoC Audio for Au1200/Au1250/Au1550" - depends on SOC_AU1200 || SOC_AU1550 + depends on MIPS_ALCHEMY help This option enables support for the Programmable Serial Controllers in AC97 and I2S mode, and the Descriptor-Based DMA -- 1.7.6 From manuel.lauss@googlemail.com Fri Aug 12 12:28:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 12:28:55 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:45927 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491181Ab1HLK2v (ORCPT ); Fri, 12 Aug 2011 12:28:51 +0200 Received: by fxd20 with SMTP id 20so2884541fxd.36 for ; Fri, 12 Aug 2011 03:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=SBjWQp4jkHQZjCKVsuF8XU6Fqbjr2SUAUdTvsaZv2js=; b=Djl3ZAI5XoJTWyO1Ko+S+tAo+USsqzkM8eRsvJisxCdcrOkH6uFf1J+p84D3XiFScP PwB6y9KAwOi6hoPkrgADgeoqDxE6yneJAG3aSmahdeTCJBTKlz1osLXJoYJgCMpVMU8O ujUUi+JaMhUxIT1WxfCnGOhZsQFfUEbE32f8w= Received: by 10.223.7.65 with SMTP id c1mr1022869fac.131.1313144926441; Fri, 12 Aug 2011 03:28:46 -0700 (PDT) Received: from localhost.localdomain (178-191-11-228.adsl.highway.telekom.at [178.191.11.228]) by mx.google.com with ESMTPS id g16sm1574007faa.27.2011.08.12.03.28.44 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 03:28:45 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: db1200: disable cascade IRQ in handler Date: Fri, 12 Aug 2011 12:28:35 +0200 Message-Id: <1313144915-16321-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 X-archive-position: 30864 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9292 Content-Length: 1720 Lines: 49 Disable the cascade IRQ in the cascade handler. This is required to get the DB1300 working, and also gets rid of all spurious interrupts previously observed on the DB1200; so Config[OD] can be disabled again for better performance. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/devboards/bcsr.c | 4 ++++ arch/mips/alchemy/devboards/db1200/setup.c | 7 ------- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index 596ad00..463d2c4 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) { unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); + disable_irq_nosync(irq); + for ( ; bisr; bisr &= bisr - 1) generic_handle_irq(bcsr_csc_base + __ffs(bisr)); + + enable_irq(irq); } /* NOTE: both the enable and mask bits must be cleared, otherwise the diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index 1dac4f2..4a89800 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -23,13 +23,6 @@ void __init board_setup(void) unsigned long freq0, clksrc, div, pfc; unsigned short whoami; - /* Set Config[OD] (disable overlapping bus transaction): - * This gets rid of a _lot_ of spurious interrupts (especially - * wrt. IDE); but incurs ~10% performance hit in some - * cpu-bound applications. - */ - set_c0_config(1 << 19); - bcsr_init(DB1200_BCSR_PHYS_ADDR, DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); -- 1.7.6 From gregkh@suse.de Fri Aug 12 18:05:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 18:05:53 +0200 (CEST) Received: from cantor2.suse.de ([195.135.220.15]:36903 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491873Ab1HLQFr (ORCPT ); Fri, 12 Aug 2011 18:05:47 +0200 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id C5D398D40D; Fri, 12 Aug 2011 18:05:46 +0200 (CEST) Date: Fri, 12 Aug 2011 09:04:54 -0700 From: Greg KH To: Manuel Lauss Cc: Linux-MIPS , Ralf Baechle , linux-usb@vger.kernel.org Subject: Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access Message-ID: <20110812160454.GA11898@suse.de> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-2-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313141985-5830-2-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30865 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9498 Content-Length: 893 Lines: 21 On Fri, Aug 12, 2011 at 11:39:38AM +0200, Manuel Lauss wrote: > Alchemy chips have one or more registers which control access > to the usb blocks as well as PHY configuration. I don't want > the OHCI/EHCI glues to know about the different registers and bits; > new arch code hides the gory details of USB configuration from them. > > Cc: linux-usb@vger.kernel.org > Cc: Greg Kroah-Hartman (USB glue parts) > Signed-off-by: Manuel Lauss > --- > CC'ed Greg for an Ack on the USB glue parts. I'd like this to go through the > MIPS tree since other changes in it depend on it. Fine with me on the USB portions, you are just deleting code, which I like :) But should the "common" USB code really live under arch/mips/alchemy/ ? The goal is to move driver code out of arch/ and into drivers/. Why are you moving stuff backwards here? greg k-h From manuel.lauss@googlemail.com Fri Aug 12 18:21:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 18:21:21 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:42897 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491876Ab1HLQVO convert rfc822-to-8bit (ORCPT ); Fri, 12 Aug 2011 18:21:14 +0200 Received: by gwb1 with SMTP id 1so2231920gwb.36 for ; Fri, 12 Aug 2011 09:21:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=sM9LQNH3ENom3o/OGrsoRWzsC2yBXdzkcWyAdAB6Irw=; b=sv8oKsAzuqM/eL+IWD1K/MIPGWd3S4Cq7QKD8Pp1jZ8zOxmIOuibGe4E9ufinJxr0C kzUN6TkpD/0XOIEzTxpquvm6w3r0xgylMV9IH8Rb5Bm9/KeHWQH66irjegndEvIxC7Je mweBV8awrV6tOXTTU1Ip6UnfRd/pdKcfr0NEI= Received: by 10.236.157.40 with SMTP id n28mr3621689yhk.47.1313166068297; Fri, 12 Aug 2011 09:21:08 -0700 (PDT) MIME-Version: 1.0 Received: by 10.236.109.17 with HTTP; Fri, 12 Aug 2011 09:20:48 -0700 (PDT) In-Reply-To: <20110812160454.GA11898@suse.de> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-2-git-send-email-manuel.lauss@googlemail.com> <20110812160454.GA11898@suse.de> From: Manuel Lauss Date: Fri, 12 Aug 2011 18:20:48 +0200 Message-ID: Subject: Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access To: Greg KH Cc: Linux-MIPS , Ralf Baechle , linux-usb@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 30866 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9511 Content-Length: 1253 Lines: 31 On Fri, Aug 12, 2011 at 6:04 PM, Greg KH wrote: > On Fri, Aug 12, 2011 at 11:39:38AM +0200, Manuel Lauss wrote: >> Alchemy chips have one or more registers which control access >> to the usb blocks as well as PHY configuration.  I don't want >> the OHCI/EHCI glues to know about the different registers and bits; >> new arch code hides the gory details of USB configuration from them. >> >> Cc: linux-usb@vger.kernel.org >> Cc: Greg Kroah-Hartman  (USB glue parts) >> Signed-off-by: Manuel Lauss >> --- >> CC'ed Greg for an Ack on the USB glue parts.  I'd like this to go through the >>  MIPS tree since other changes in it depend on it. > > Fine with me on the USB portions, you are just deleting code, which I > like :) Thanks! > But should the "common" USB code really live under arch/mips/alchemy/ ? > The goal is to move driver code out of arch/ and into drivers/.  Why are > you moving stuff backwards here? This is just chip-dependent code for usb block and phy management, which varies wich chip subtype, the OHCI and EHCI controllers are identical on all of them. At the time moving the chip-depedent code to the other chip-dependent code seemed like a good idea... Manuel From gregkh@suse.de Fri Aug 12 19:18:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 19:18:11 +0200 (CEST) Received: from cantor2.suse.de ([195.135.220.15]:40448 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491882Ab1HLRSH (ORCPT ); Fri, 12 Aug 2011 19:18:07 +0200 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 410AE8C061; Fri, 12 Aug 2011 19:18:07 +0200 (CEST) Date: Fri, 12 Aug 2011 09:33:25 -0700 From: Greg KH To: Manuel Lauss Cc: Linux-MIPS , Ralf Baechle , linux-usb@vger.kernel.org Subject: Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access Message-ID: <20110812163325.GA13018@suse.de> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-2-git-send-email-manuel.lauss@googlemail.com> <20110812160454.GA11898@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30867 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9571 Content-Length: 1525 Lines: 36 On Fri, Aug 12, 2011 at 06:20:48PM +0200, Manuel Lauss wrote: > On Fri, Aug 12, 2011 at 6:04 PM, Greg KH wrote: > > On Fri, Aug 12, 2011 at 11:39:38AM +0200, Manuel Lauss wrote: > >> Alchemy chips have one or more registers which control access > >> to the usb blocks as well as PHY configuration.  I don't want > >> the OHCI/EHCI glues to know about the different registers and bits; > >> new arch code hides the gory details of USB configuration from them. > >> > >> Cc: linux-usb@vger.kernel.org > >> Cc: Greg Kroah-Hartman  (USB glue parts) > >> Signed-off-by: Manuel Lauss > >> --- > >> CC'ed Greg for an Ack on the USB glue parts.  I'd like this to go through the > >>  MIPS tree since other changes in it depend on it. > > > > Fine with me on the USB portions, you are just deleting code, which I > > like :) > > Thanks! > > > > But should the "common" USB code really live under arch/mips/alchemy/ ? > > The goal is to move driver code out of arch/ and into drivers/.  Why are > > you moving stuff backwards here? > > This is just chip-dependent code for usb block and phy management, which > varies wich chip subtype, the OHCI and EHCI controllers are identical on all > of them. At the time moving the chip-depedent code to the other chip-dependent > code seemed like a good idea... But that's what drivers/* is, chip-dependent code. Please move it there instead. Has the MIPS developers learned nothing from the recent ARM mess? :) greg k-h From manuel.lauss@googlemail.com Fri Aug 12 19:25:52 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 19:25:58 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:53001 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491876Ab1HLRZw convert rfc822-to-8bit (ORCPT ); Fri, 12 Aug 2011 19:25:52 +0200 Received: by yxk8 with SMTP id 8so2263692yxk.36 for ; Fri, 12 Aug 2011 10:25:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=sFP4HYhmz4pRBgBG/elHwGglTUm0PZvQu5/7+HiCWXo=; b=EhZ4yIhPdq4MTJHM+4Uq50MQgNGAIDxsKYlYBNfp1huEaRn9jHTLzVvI34ewzx5u4f 5VOEUgj26tYMRkVyRnBwFIFXHFrqt1Uz9RdqfEkME7Egbna2M5nc0p23XKJkgMbooIgA 2WV0AnUNro4ky7PLtmmei9U7lgtq+aZLdwbfk= Received: by 10.236.157.40 with SMTP id n28mr3865398yhk.47.1313169946115; Fri, 12 Aug 2011 10:25:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.236.109.17 with HTTP; Fri, 12 Aug 2011 10:25:26 -0700 (PDT) In-Reply-To: <20110812163325.GA13018@suse.de> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-2-git-send-email-manuel.lauss@googlemail.com> <20110812160454.GA11898@suse.de> <20110812163325.GA13018@suse.de> From: Manuel Lauss Date: Fri, 12 Aug 2011 19:25:26 +0200 Message-ID: Subject: Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access To: Greg KH Cc: Linux-MIPS , Ralf Baechle , linux-usb@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 30868 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9579 Content-Length: 1823 Lines: 42 On Fri, Aug 12, 2011 at 6:33 PM, Greg KH wrote: > On Fri, Aug 12, 2011 at 06:20:48PM +0200, Manuel Lauss wrote: >> On Fri, Aug 12, 2011 at 6:04 PM, Greg KH wrote: >> > On Fri, Aug 12, 2011 at 11:39:38AM +0200, Manuel Lauss wrote: >> >> Alchemy chips have one or more registers which control access >> >> to the usb blocks as well as PHY configuration.  I don't want >> >> the OHCI/EHCI glues to know about the different registers and bits; >> >> new arch code hides the gory details of USB configuration from them. >> >> >> >> Cc: linux-usb@vger.kernel.org >> >> Cc: Greg Kroah-Hartman  (USB glue parts) >> >> Signed-off-by: Manuel Lauss >> >> --- >> >> CC'ed Greg for an Ack on the USB glue parts.  I'd like this to go through the >> >>  MIPS tree since other changes in it depend on it. >> > >> > Fine with me on the USB portions, you are just deleting code, which I >> > like :) >> >> Thanks! >> >> >> > But should the "common" USB code really live under arch/mips/alchemy/ ? >> > The goal is to move driver code out of arch/ and into drivers/.  Why are >> > you moving stuff backwards here? >> >> This is just chip-dependent code for usb block and phy management, which >> varies wich chip subtype, the OHCI and EHCI controllers are identical on all >> of them.  At the time moving the chip-depedent code to the other chip-dependent >> code seemed like a good idea... > > But that's what drivers/* is, chip-dependent code.  Please move it there > instead. > > Has the MIPS developers learned nothing from the recent ARM mess? :) Personally I disagree with some of the results of the "ARM mess", but if that's what it takes to get things moving forware, so be it. Give me a few minutes to figure out what to do... Thanks! Manuel From ralf@linux-mips.org Fri Aug 12 19:27:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 19:27:10 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48342 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491876Ab1HLR1G (ORCPT ); Fri, 12 Aug 2011 19:27:06 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7CHR4hl022279; Fri, 12 Aug 2011 18:27:04 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7CHR3h8022276; Fri, 12 Aug 2011 18:27:03 +0100 Date: Fri, 12 Aug 2011 18:27:03 +0100 From: Ralf Baechle To: Greg KH Cc: Manuel Lauss , Linux-MIPS , linux-usb@vger.kernel.org Subject: Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access Message-ID: <20110812172703.GA22106@linux-mips.org> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-2-git-send-email-manuel.lauss@googlemail.com> <20110812160454.GA11898@suse.de> <20110812163325.GA13018@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110812163325.GA13018@suse.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30869 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9581 Content-Length: 215 Lines: 7 On Fri, Aug 12, 2011 at 09:33:25AM -0700, Greg KH wrote: > Has the MIPS developers learned nothing from the recent ARM mess? :) The MIPS maintainer was scratching his head over the point of this series :) Ralf From manuel.lauss@googlemail.com Fri Aug 12 20:12:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 20:12:56 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:58508 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491882Ab1HLSMp (ORCPT ); Fri, 12 Aug 2011 20:12:45 +0200 Received: by fxd20 with SMTP id 20so3210388fxd.36 for ; Fri, 12 Aug 2011 11:12:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=5Zp0+9gIJGrQ3nmPMq1vd/zfahHb527fi6P3znHldMM=; b=SmOnk6vnnhdMhqcUucQPZZNMGISr/+MbJn7yChRTI1WtNNO7R7aw+uNMXT2Zj4oLIV i8wqC5Zeo+3ktA7R0ouiMUmM8WjNeu7lMCsDHBkzf9fKdIwEyf8c25Wht2oLOkxZ/Do1 NMI+3g0xJR1oqEZ/Hyocoay/spXrFvvRFcSyo= Received: by 10.223.68.156 with SMTP id v28mr1586993fai.138.1313172760521; Fri, 12 Aug 2011 11:12:40 -0700 (PDT) Received: from localhost.localdomain (188-22-154-116.adsl.highway.telekom.at [188.22.154.116]) by mx.google.com with ESMTPS id i16sm2618806faa.21.2011.08.12.11.12.38 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Aug 2011 11:12:39 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss , linux-usb@vger.kernel.org, Greg Kroah-Hartman (USB glue parts) Subject: [PATCH V2 1/8] MIPS: Alchemy: abstract USB block control register access Date: Fri, 12 Aug 2011 20:12:33 +0200 Message-Id: <1313172753-31088-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 X-archive-position: 30870 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9626 Content-Length: 28373 Lines: 924 Alchemy chips have one or more registers which control access to the usb blocks as well as PHY configuration. I don't want the OHCI/EHCI glues to know about the different registers and bits; new code hides the gory details of USB configuration from them. Cc: linux-usb@vger.kernel.org Cc: Greg Kroah-Hartman (USB glue parts) Signed-off-by: Manuel Lauss --- V2: moved the chip-specific parts from arch home to usb/host/alchemy-common.c arch/mips/alchemy/common/dma.c | 12 +- arch/mips/alchemy/common/power.c | 42 ---- arch/mips/include/asm/mach-au1x00/au1000.h | 84 ++------ drivers/usb/host/Makefile | 1 + drivers/usb/host/alchemy-common.c | 337 ++++++++++++++++++++++++++++ drivers/usb/host/ehci-au1xxx.c | 77 +------ drivers/usb/host/ohci-au1xxx.c | 110 +-------- 7 files changed, 382 insertions(+), 281 deletions(-) create mode 100644 drivers/usb/host/alchemy-common.c diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c index 347980e..6652a23 100644 --- a/arch/mips/alchemy/common/dma.c +++ b/arch/mips/alchemy/common/dma.c @@ -88,12 +88,12 @@ static const struct dma_dev { { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */ { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */ { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */ - { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ - { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ - { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ - { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ - { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ - { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ + { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ + { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ + { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ + { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ + { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ + { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */ { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */ { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */ diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index 9ec8559..bdd6651 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -47,7 +47,6 @@ * We only have to save/restore registers that aren't otherwise * done as part of a driver pm_* function. */ -static unsigned int sleep_usb[2]; static unsigned int sleep_sys_clocks[5]; static unsigned int sleep_sys_pinfunc; static unsigned int sleep_static_memctlr[4][3]; @@ -55,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3]; static void save_core_regs(void) { -#ifndef CONFIG_SOC_AU1200 - /* Shutdown USB host/device. */ - sleep_usb[0] = au_readl(USB_HOST_CONFIG); - - /* There appears to be some undocumented reset register.... */ - au_writel(0, 0xb0100004); - au_sync(); - au_writel(0, USB_HOST_CONFIG); - au_sync(); - - sleep_usb[1] = au_readl(USBD_ENABLE); - au_writel(0, USBD_ENABLE); - au_sync(); - -#else /* AU1200 */ - - /* enable access to OTG mmio so we can save OTG CAP/MUX. - * FIXME: write an OTG driver and move this stuff there! - */ - au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); - au_sync(); - sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ - sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ -#endif - /* Clocks and PLLs. */ sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); @@ -123,22 +97,6 @@ static void restore_core_regs(void) au_writel(sleep_sys_pinfunc, SYS_PINFUNC); au_sync(); -#ifndef CONFIG_SOC_AU1200 - au_writel(sleep_usb[0], USB_HOST_CONFIG); - au_writel(sleep_usb[1], USBD_ENABLE); - au_sync(); -#else - /* enable access to OTG memory */ - au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); - au_sync(); - - /* restore OTG caps and port mux. */ - au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ - au_sync(); - au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ - au_sync(); -#endif - /* Restore the static memory controller configuration. */ au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index f260ebe..3b0a1e7 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -245,6 +245,15 @@ void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); void au_sleep(void); +/* USB: drivers/usb/host/alchemy-common.c */ +enum alchemy_usb_block { + ALCHEMY_USB_OHCI0, + ALCHEMY_USB_UDC0, + ALCHEMY_USB_EHCI0, + ALCHEMY_USB_OTG0, +}; +int alchemy_usb_control(int block, int enable); + /* SOC Interrupt numbers */ @@ -687,7 +696,8 @@ enum soc_au1200_ints { */ #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ -#define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */ +#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ +#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ @@ -710,12 +720,17 @@ enum soc_au1200_ints { #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ +#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ +#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ +#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ +#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ +#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ +#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ #ifdef CONFIG_SOC_AU1000 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x10100000 #define IRDA_PHYS_ADDR 0x10300000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 @@ -729,7 +744,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1500 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x10100000 #define PCI_PHYS_ADDR 0x14005000 #define PCI_MEM_PHYS_ADDR 0x400000000ULL #define PCI_IO_PHYS_ADDR 0x500000000ULL @@ -745,7 +759,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1100 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x10100000 #define IRDA_PHYS_ADDR 0x10300000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 @@ -760,7 +773,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1550 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define USBH_PHYS_ADDR 0x14020000 #define PCI_PHYS_ADDR 0x14005000 #define PE_PHYS_ADDR 0x14008000 #define PSC0_PHYS_ADDR 0x11A00000 @@ -783,8 +795,6 @@ enum soc_au1200_ints { #define STATIC_MEM_PHYS_ADDR 0x14001000 #define AES_PHYS_ADDR 0x10300000 #define CIM_PHYS_ADDR 0x14004000 -#define USBM_PHYS_ADDR 0x14020000 -#define USBH_PHYS_ADDR 0x14020100 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 #define LCD_PHYS_ADDR 0x15000000 @@ -868,21 +878,6 @@ enum soc_au1200_ints { #define USB_EHCI_LEN 0x100 #define USB_UDC_BASE 0x14022000 #define USB_UDC_LEN 0x2000 -#define USB_MSR_BASE 0xB4020000 -#define USB_MSR_MCFG 4 -#define USBMSRMCFG_OMEMEN 0 -#define USBMSRMCFG_OBMEN 1 -#define USBMSRMCFG_EMEMEN 2 -#define USBMSRMCFG_EBMEN 3 -#define USBMSRMCFG_DMEMEN 4 -#define USBMSRMCFG_DBMEN 5 -#define USBMSRMCFG_GMEMEN 6 -#define USBMSRMCFG_OHCCLKEN 16 -#define USBMSRMCFG_EHCCLKEN 17 -#define USBMSRMCFG_UDCCLKEN 18 -#define USBMSRMCFG_PHYPLLEN 19 -#define USBMSRMCFG_RDCOMB 30 -#define USBMSRMCFG_PFEN 31 #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT @@ -963,51 +958,6 @@ enum soc_au1200_ints { #define USB_OHCI_LEN 0x00100000 #endif -#ifndef CONFIG_SOC_AU1200 - -/* USB Device Controller */ -#define USBD_EP0RD 0xB0200000 -#define USBD_EP0WR 0xB0200004 -#define USBD_EP2WR 0xB0200008 -#define USBD_EP3WR 0xB020000C -#define USBD_EP4RD 0xB0200010 -#define USBD_EP5RD 0xB0200014 -#define USBD_INTEN 0xB0200018 -#define USBD_INTSTAT 0xB020001C -# define USBDEV_INT_SOF (1 << 12) -# define USBDEV_INT_HF_BIT 6 -# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) -# define USBDEV_INT_CMPLT_BIT 0 -# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) -#define USBD_CONFIG 0xB0200020 -#define USBD_EP0CS 0xB0200024 -#define USBD_EP2CS 0xB0200028 -#define USBD_EP3CS 0xB020002C -#define USBD_EP4CS 0xB0200030 -#define USBD_EP5CS 0xB0200034 -# define USBDEV_CS_SU (1 << 14) -# define USBDEV_CS_NAK (1 << 13) -# define USBDEV_CS_ACK (1 << 12) -# define USBDEV_CS_BUSY (1 << 11) -# define USBDEV_CS_TSIZE_BIT 1 -# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) -# define USBDEV_CS_STALL (1 << 0) -#define USBD_EP0RDSTAT 0xB0200040 -#define USBD_EP0WRSTAT 0xB0200044 -#define USBD_EP2WRSTAT 0xB0200048 -#define USBD_EP3WRSTAT 0xB020004C -#define USBD_EP4RDSTAT 0xB0200050 -#define USBD_EP5RDSTAT 0xB0200054 -# define USBDEV_FSTAT_FLUSH (1 << 6) -# define USBDEV_FSTAT_UF (1 << 5) -# define USBDEV_FSTAT_OF (1 << 4) -# define USBDEV_FSTAT_FCNT_BIT 0 -# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) -#define USBD_ENABLE 0xB0200058 -# define USBDEV_ENABLE (1 << 1) -# define USBDEV_CE (1 << 0) - -#endif /* !CONFIG_SOC_AU1200 */ /* Ethernet Controllers */ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 624a362..436cd71 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -35,3 +35,4 @@ obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o +obj-$(CONFIG_MIPS_ALCHEMY) += alchemy-common.o diff --git a/drivers/usb/host/alchemy-common.c b/drivers/usb/host/alchemy-common.c new file mode 100644 index 0000000..b4192c9 --- /dev/null +++ b/drivers/usb/host/alchemy-common.c @@ -0,0 +1,337 @@ +/* + * USB block power/access management abstraction. + * + * Au1000+: The OHCI block control register is at the far end of the OHCI memory + * area. Au1550 has OHCI on different base address. No need to handle + * UDC here. + * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG + * as well as the PHY for EHCI and UDC. + * + */ + +#include +#include +#include +#include +#include +#include + +/* control register offsets */ +#define AU1000_OHCICFG 0x7fffc +#define AU1550_OHCICFG 0x07ffc +#define AU1200_USBCFG 0x04 + +/* Au1000 USB block config bits */ +#define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */ +#define USBHEN_CE (1 << 3) /* OHCI block clock enable */ +#define USBHEN_E (1 << 2) /* OHCI block enable */ +#define USBHEN_C (1 << 1) /* OHCI block coherency bit */ +#define USBHEN_BE (1 << 0) /* OHCI Big-Endian */ + +/* Au1200 USB config bits */ +#define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */ +#define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */ +#define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */ +#define USBCFG_SSD (1 << 23) /* serial short detect en */ +#define USBCFG_PPE (1 << 19) /* HS PHY PLL */ +#define USBCFG_UCE (1 << 18) /* UDC clock enable */ +#define USBCFG_ECE (1 << 17) /* EHCI clock enable */ +#define USBCFG_OCE (1 << 16) /* OHCI clock enable */ +#define USBCFG_FLA(x) (((x) & 0x3f) << 8) +#define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */ +#define USBCFG_GME (1 << 6) /* OTG mem access */ +#define USBCFG_DBE (1 << 5) /* UDC busmaster enable */ +#define USBCFG_DME (1 << 4) /* UDC mem enable */ +#define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */ +#define USBCFG_EME (1 << 2) /* EHCI mem enable */ +#define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */ +#define USBCFG_OME (1 << 0) /* OHCI mem enable */ +#define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\ + USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \ + USBCFG_GME | USBCFG_DBE | USBCFG_DME | \ + USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \ + USBCFG_OME) + + +static DEFINE_SPINLOCK(alchemy_usb_lock); + + +static inline void __au1200_ohci_control(void __iomem *base, int enable) +{ + unsigned long r = __raw_readl(base + AU1200_USBCFG); + if (enable) { + __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG); + wmb(); + udelay(2000); + } else { + __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG); + wmb(); + udelay(1000); + } +} + +static inline void __au1200_ehci_control(void __iomem *base, int enable) +{ + unsigned long r = __raw_readl(base + AU1200_USBCFG); + if (enable) { + __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG); + wmb(); + udelay(1000); + } else { + if (!(r & USBCFG_UCE)) /* UDC also off? */ + r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */ + __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG); + wmb(); + udelay(1000); + } +} + +static inline void __au1200_udc_control(void __iomem *base, int enable) +{ + unsigned long r = __raw_readl(base + AU1200_USBCFG); + if (enable) { + __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG); + wmb(); + } else { + if (!(r & USBCFG_ECE)) /* EHCI also off? */ + r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */ + __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG); + wmb(); + } +} + +static inline int au1200_coherency_bug(void) +{ +#if defined(CONFIG_DMA_COHERENT) + /* Au1200 AB USB does not support coherent memory */ + if (!(read_c0_prid() & 0xff)) { + printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n"); + printk(KERN_INFO "Au1200 USB: update your board or re-configure" + " the kernel\n"); + return -ENODEV; + } +#endif + return 0; +} + +static inline int au1200_usb_control(int block, int enable) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR); + int ret = 0; + + switch (block) { + case ALCHEMY_USB_OHCI0: + ret = au1200_coherency_bug(); + if (ret && enable) + goto out; + __au1200_ohci_control(base, enable); + break; + case ALCHEMY_USB_UDC0: + __au1200_udc_control(base, enable); + break; + case ALCHEMY_USB_EHCI0: + ret = au1200_coherency_bug(); + if (ret && enable) + goto out; + __au1200_ehci_control(base, enable); + break; + default: + ret = -ENODEV; + } +out: + return ret; +} + + +/* initialize USB block(s) to a known working state */ +static inline void au1200_usb_init(void) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR); + __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG); + wmb(); + udelay(1000); +} + +static inline void au1000_usb_init(unsigned long rb, int reg) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); + unsigned long r = __raw_readl(base); + +#if defined(__BIG_ENDIAN) + r |= USBHEN_BE; +#endif + r |= USBHEN_C; + + __raw_writel(r, base); + wmb(); + udelay(1000); +} + + +static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(rb); + unsigned long r = __raw_readl(base + creg); + + if (enable) { + __raw_writel(r | USBHEN_CE, base + creg); + wmb(); + udelay(1000); + __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg); + wmb(); + udelay(1000); + + /* wait for reset complete (read reg twice: au1500 erratum) */ + while (__raw_readl(base + creg), + !(__raw_readl(base + creg) & USBHEN_RD)) + udelay(1000); + } else { + __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg); + wmb(); + } +} + +static inline int au1000_usb_control(int block, int enable, unsigned long rb, + int creg) +{ + int ret = 0; + + switch (block) { + case ALCHEMY_USB_OHCI0: + __au1xx0_ohci_control(enable, rb, creg); + break; + default: + ret = -ENODEV; + } + return ret; +} + +/* + * alchemy_usb_control - control Alchemy on-chip USB blocks + * @block: USB block to target + * @enable: set 1 to enable a block, 0 to disable + */ +int alchemy_usb_control(int block, int enable) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&alchemy_usb_lock, flags); + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + ret = au1000_usb_control(block, enable, + AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); + break; + case ALCHEMY_CPU_AU1550: + ret = au1000_usb_control(block, enable, + AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); + break; + case ALCHEMY_CPU_AU1200: + ret = au1200_usb_control(block, enable); + break; + default: + ret = -ENODEV; + } + spin_unlock_irqrestore(&alchemy_usb_lock, flags); + return ret; +} +EXPORT_SYMBOL_GPL(alchemy_usb_control); + + +static unsigned long alchemy_usb_pmdata[2]; + +static void au1000_usb_pm(unsigned long br, int creg, int susp) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(br); + + if (susp) { + alchemy_usb_pmdata[0] = __raw_readl(base + creg); + /* There appears to be some undocumented reset register.... */ + __raw_writel(0, base + 0x04); + wmb(); + __raw_writel(0, base + creg); + wmb(); + } else { + __raw_writel(alchemy_usb_pmdata[0], base + creg); + wmb(); + } +} + +static void au1200_usb_pm(int susp) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR); + if (susp) { + /* save OTG_CAP/MUX registers which indicate port routing */ + /* FIXME: write an OTG driver to do that */ + alchemy_usb_pmdata[0] = __raw_readl(base + 0x00); + alchemy_usb_pmdata[1] = __raw_readl(base + 0x04); + } else { + /* restore access to all MMIO areas */ + au1200_usb_init(); + + /* restore OTG_CAP/MUX registers */ + __raw_writel(alchemy_usb_pmdata[0], base + 0x00); + __raw_writel(alchemy_usb_pmdata[1], base + 0x04); + wmb(); + } +} + +static void alchemy_usb_pm(int susp) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp); + break; + case ALCHEMY_CPU_AU1550: + au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp); + break; + case ALCHEMY_CPU_AU1200: + au1200_usb_pm(susp); + break; + } +} + +static int alchemy_usb_suspend(void) +{ + alchemy_usb_pm(1); + return 0; +} + +static void alchemy_usb_resume(void) +{ + alchemy_usb_pm(0); +} + +static struct syscore_ops alchemy_usb_pm_ops = { + .suspend = alchemy_usb_suspend, + .resume = alchemy_usb_resume, +}; + +static int __init alchemy_usb_init(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); + break; + case ALCHEMY_CPU_AU1550: + au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); + break; + case ALCHEMY_CPU_AU1200: + au1200_usb_init(); + break; + } + + register_syscore_ops(&alchemy_usb_pm_ops); + + return 0; +} +arch_initcall(alchemy_usb_init); diff --git a/drivers/usb/host/ehci-au1xxx.c b/drivers/usb/host/ehci-au1xxx.c index 42ae574..e480dc1 100644 --- a/drivers/usb/host/ehci-au1xxx.c +++ b/drivers/usb/host/ehci-au1xxx.c @@ -14,61 +14,9 @@ #include #include -#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG) -#define USB_MCFG_PFEN (1<<31) -#define USB_MCFG_RDCOMB (1<<30) -#define USB_MCFG_SSDEN (1<<23) -#define USB_MCFG_PHYPLLEN (1<<19) -#define USB_MCFG_UCECLKEN (1<<18) -#define USB_MCFG_EHCCLKEN (1<<17) -#ifdef CONFIG_DMA_COHERENT -#define USB_MCFG_UCAM (1<<7) -#else -#define USB_MCFG_UCAM (0) -#endif -#define USB_MCFG_EBMEN (1<<3) -#define USB_MCFG_EMEMEN (1<<2) - -#define USBH_ENABLE_CE (USB_MCFG_PHYPLLEN | USB_MCFG_EHCCLKEN) -#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \ - USBH_ENABLE_CE | USB_MCFG_SSDEN | \ - USB_MCFG_UCAM | USB_MCFG_EBMEN | \ - USB_MCFG_EMEMEN) - -#define USBH_DISABLE (USB_MCFG_EBMEN | USB_MCFG_EMEMEN) extern int usb_disabled(void); -static void au1xxx_start_ehc(void) -{ - /* enable clock to EHCI block and HS PHY PLL*/ - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - /* enable EHCI mmio */ - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG); - au_sync(); - udelay(1000); -} - -static void au1xxx_stop_ehc(void) -{ - unsigned long c; - - /* Disable mem */ - au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - /* Disable EHC clock. If the HS PHY is unused disable it too. */ - c = au_readl(USB_HOST_CONFIG) & ~USB_MCFG_EHCCLKEN; - if (!(c & USB_MCFG_UCECLKEN)) /* UDC disabled? */ - c &= ~USB_MCFG_PHYPLLEN; /* yes: disable HS PHY PLL */ - au_writel(c, USB_HOST_CONFIG); - au_sync(); -} - static int au1xxx_ehci_setup(struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); @@ -136,16 +84,6 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) if (usb_disabled()) return -ENODEV; -#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT) - /* Au1200 AB USB does not support coherent memory */ - if (!(read_c0_prid() & 0xff)) { - printk(KERN_INFO "%s: this is chip revision AB!\n", pdev->name); - printk(KERN_INFO "%s: update your board or re-configure" - " the kernel\n", pdev->name); - return -ENODEV; - } -#endif - if (pdev->resource[1].flags != IORESOURCE_IRQ) { pr_debug("resource[1] is not IORESOURCE_IRQ"); return -ENOMEM; @@ -171,7 +109,11 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) goto err2; } - au1xxx_start_ehc(); + if (alchemy_usb_control(ALCHEMY_USB_EHCI0, 1)) { + printk(KERN_INFO "%s: controller init failed!\n", pdev->name); + ret = -ENODEV; + goto err3; + } ehci = hcd_to_ehci(hcd); ehci->caps = hcd->regs; @@ -187,7 +129,8 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev) return ret; } - au1xxx_stop_ehc(); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); +err3: iounmap(hcd->regs); err2: release_mem_region(hcd->rsrc_start, hcd->rsrc_len); @@ -201,10 +144,10 @@ static int ehci_hcd_au1xxx_drv_remove(struct platform_device *pdev) struct usb_hcd *hcd = platform_get_drvdata(pdev); usb_remove_hcd(hcd); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); - au1xxx_stop_ehc(); platform_set_drvdata(pdev, NULL); return 0; @@ -236,7 +179,7 @@ static int ehci_hcd_au1xxx_drv_suspend(struct device *dev) // could save FLADJ in case of Vaux power loss // ... we'd only use it to handle clock skew - au1xxx_stop_ehc(); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); return rc; } @@ -246,7 +189,7 @@ static int ehci_hcd_au1xxx_drv_resume(struct device *dev) struct usb_hcd *hcd = dev_get_drvdata(dev); struct ehci_hcd *ehci = hcd_to_ehci(hcd); - au1xxx_start_ehc(); + alchemy_usb_control(ALCHEMY_USB_EHCI0, 1); // maybe restore FLADJ diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index 958d985..299d719 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -23,92 +23,9 @@ #include -#ifndef CONFIG_SOC_AU1200 - -#define USBH_ENABLE_BE (1<<0) -#define USBH_ENABLE_C (1<<1) -#define USBH_ENABLE_E (1<<2) -#define USBH_ENABLE_CE (1<<3) -#define USBH_ENABLE_RD (1<<4) - -#ifdef __LITTLE_ENDIAN -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) -#elif defined(__BIG_ENDIAN) -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | \ - USBH_ENABLE_BE) -#else -#error not byte order defined -#endif - -#else /* Au1200 */ - -#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG) -#define USB_MCFG_PFEN (1<<31) -#define USB_MCFG_RDCOMB (1<<30) -#define USB_MCFG_SSDEN (1<<23) -#define USB_MCFG_OHCCLKEN (1<<16) -#ifdef CONFIG_DMA_COHERENT -#define USB_MCFG_UCAM (1<<7) -#else -#define USB_MCFG_UCAM (0) -#endif -#define USB_MCFG_OBMEN (1<<1) -#define USB_MCFG_OMEMEN (1<<0) - -#define USBH_ENABLE_CE USB_MCFG_OHCCLKEN - -#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \ - USBH_ENABLE_CE | USB_MCFG_SSDEN | \ - USB_MCFG_UCAM | \ - USB_MCFG_OBMEN | USB_MCFG_OMEMEN) - -#define USBH_DISABLE (USB_MCFG_OBMEN | USB_MCFG_OMEMEN) - -#endif /* Au1200 */ extern int usb_disabled(void); -static void au1xxx_start_ohc(void) -{ - /* enable host controller */ -#ifndef CONFIG_SOC_AU1200 - au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - /* wait for reset complete (read register twice; see au1500 errata) */ - while (au_readl(USB_HOST_CONFIG), - !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) - udelay(1000); - -#else /* Au1200 */ - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); - - au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG); - au_sync(); - udelay(2000); -#endif /* Au1200 */ -} - -static void au1xxx_stop_ohc(void) -{ -#ifdef CONFIG_SOC_AU1200 - /* Disable mem */ - au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG); - au_sync(); - udelay(1000); -#endif - /* Disable clock */ - au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); - au_sync(); -} - static int __devinit ohci_au1xxx_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); @@ -178,17 +95,6 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) if (usb_disabled()) return -ENODEV; -#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT) - /* Au1200 AB USB does not support coherent memory */ - if (!(read_c0_prid() & 0xff)) { - printk(KERN_INFO "%s: this is chip revision AB !!\n", - pdev->name); - printk(KERN_INFO "%s: update your board or re-configure " - "the kernel\n", pdev->name); - return -ENODEV; - } -#endif - if (pdev->resource[1].flags != IORESOURCE_IRQ) { pr_debug("resource[1] is not IORESOURCE_IRQ\n"); return -ENOMEM; @@ -214,7 +120,12 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) goto err2; } - au1xxx_start_ohc(); + if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) { + printk(KERN_INFO "%s: controller init failed!\n", pdev->name); + ret = -ENODEV; + goto err3; + } + ohci_hcd_init(hcd_to_ohci(hcd)); ret = usb_add_hcd(hcd, pdev->resource[1].start, @@ -224,7 +135,8 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) return ret; } - au1xxx_stop_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); +err3: iounmap(hcd->regs); err2: release_mem_region(hcd->rsrc_start, hcd->rsrc_len); @@ -238,7 +150,7 @@ static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev) struct usb_hcd *hcd = platform_get_drvdata(pdev); usb_remove_hcd(hcd); - au1xxx_stop_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); @@ -275,7 +187,7 @@ static int ohci_hcd_au1xxx_drv_suspend(struct device *dev) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); - au1xxx_stop_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); bail: spin_unlock_irqrestore(&ohci->lock, flags); @@ -286,7 +198,7 @@ static int ohci_hcd_au1xxx_drv_resume(struct device *dev) { struct usb_hcd *hcd = dev_get_drvdata(dev); - au1xxx_start_ohc(); + alchemy_usb_control(ALCHEMY_USB_OHCI0, 1); set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); ohci_finish_controller_resume(hcd); -- 1.7.6 From gregkh@suse.de Fri Aug 12 20:42:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 20:42:57 +0200 (CEST) Received: from cantor2.suse.de ([195.135.220.15]:44709 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491882Ab1HLSmu (ORCPT ); Fri, 12 Aug 2011 20:42:50 +0200 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 78F688D40D; Fri, 12 Aug 2011 20:42:50 +0200 (CEST) Date: Fri, 12 Aug 2011 11:42:27 -0700 From: Greg KH To: Manuel Lauss Cc: Linux-MIPS , Ralf Baechle , linux-usb@vger.kernel.org Subject: Re: [PATCH V2 1/8] MIPS: Alchemy: abstract USB block control register access Message-ID: <20110812184227.GA17057@suse.de> References: <1313172753-31088-1-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313172753-31088-1-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30871 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9632 Content-Length: 1323 Lines: 30 On Fri, Aug 12, 2011 at 08:12:33PM +0200, Manuel Lauss wrote: > Alchemy chips have one or more registers which control access > to the usb blocks as well as PHY configuration. I don't want > the OHCI/EHCI glues to know about the different registers and bits; > new code hides the gory details of USB configuration from them. > > Cc: linux-usb@vger.kernel.org > Cc: Greg Kroah-Hartman (USB glue parts) > Signed-off-by: Manuel Lauss > --- > V2: moved the chip-specific parts from arch home to usb/host/alchemy-common.c > > arch/mips/alchemy/common/dma.c | 12 +- > arch/mips/alchemy/common/power.c | 42 ---- > arch/mips/include/asm/mach-au1x00/au1000.h | 84 ++------ > drivers/usb/host/Makefile | 1 + > drivers/usb/host/alchemy-common.c | 337 ++++++++++++++++++++++++++++ > drivers/usb/host/ehci-au1xxx.c | 77 +------ > drivers/usb/host/ohci-au1xxx.c | 110 +-------- > 7 files changed, 382 insertions(+), 281 deletions(-) > create mode 100644 drivers/usb/host/alchemy-common.c Much nicer, thanks. I can take this in the USB tree if the MIPS developers want, or if not, feel free to add: Acked-by: Greg Kroah-Hartman and take it through the MIPS tree. greg k-h From manuel.lauss@googlemail.com Fri Aug 12 20:49:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Aug 2011 20:49:13 +0200 (CEST) Received: from mail-gx0-f177.google.com ([209.85.161.177]:43682 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491885Ab1HLStH convert rfc822-to-8bit (ORCPT ); Fri, 12 Aug 2011 20:49:07 +0200 Received: by gxk2 with SMTP id 2so2346793gxk.36 for ; Fri, 12 Aug 2011 11:49:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; bh=sXexBySvEG8HjNWYqYTfdndQGxQsQvOrK29dczwfXlg=; b=rRoUIQu0GaRcZki8vxJCustHLyPi4WcBnzklcJOFxRNFFT+syIi3i3aelvTG6034+1 pVu/X8QyEPtBnASYzoX6f2psENX/aaCxZo3oZjAKqfhsSdZGWi8kb4+W/crwd+oXnjfD KCgUJQf4h6TwN36cdt+gk4St9KntVaz1j1nuY= Received: by 10.236.116.66 with SMTP id f42mr4293634yhh.13.1313174941118; Fri, 12 Aug 2011 11:49:01 -0700 (PDT) MIME-Version: 1.0 Received: by 10.236.109.17 with HTTP; Fri, 12 Aug 2011 11:48:41 -0700 (PDT) In-Reply-To: <20110812184227.GA17057@suse.de> References: <1313172753-31088-1-git-send-email-manuel.lauss@googlemail.com> <20110812184227.GA17057@suse.de> From: Manuel Lauss Date: Fri, 12 Aug 2011 20:48:41 +0200 Message-ID: Subject: Re: [PATCH V2 1/8] MIPS: Alchemy: abstract USB block control register access To: Greg KH Cc: Linux-MIPS , Ralf Baechle , linux-usb@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 30872 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9633 Content-Length: 1522 Lines: 34 On Fri, Aug 12, 2011 at 8:42 PM, Greg KH wrote: > On Fri, Aug 12, 2011 at 08:12:33PM +0200, Manuel Lauss wrote: >> Alchemy chips have one or more registers which control access >> to the usb blocks as well as PHY configuration.  I don't want >> the OHCI/EHCI glues to know about the different registers and bits; >> new code hides the gory details of USB configuration from them. >> >> Cc: linux-usb@vger.kernel.org >> Cc: Greg Kroah-Hartman  (USB glue parts) >> Signed-off-by: Manuel Lauss >> --- >> V2: moved the chip-specific parts from arch home to usb/host/alchemy-common.c >> >>  arch/mips/alchemy/common/dma.c             |   12 +- >>  arch/mips/alchemy/common/power.c           |   42 ---- >>  arch/mips/include/asm/mach-au1x00/au1000.h |   84 ++------ >>  drivers/usb/host/Makefile                  |    1 + >>  drivers/usb/host/alchemy-common.c          |  337 ++++++++++++++++++++++++++++ >>  drivers/usb/host/ehci-au1xxx.c             |   77 +------ >>  drivers/usb/host/ohci-au1xxx.c             |  110 +-------- >>  7 files changed, 382 insertions(+), 281 deletions(-) >>  create mode 100644 drivers/usb/host/alchemy-common.c > > Much nicer, thanks. > > I can take this in the USB tree if the MIPS developers want, or if not, > feel free to add: >        Acked-by: Greg Kroah-Hartman > and take it through the MIPS tree. Great, thanks. Other patches to the MIPS tree depend on this one, so I hope Ralf will take it. Manuel From lacombar@gmail.com Mon Aug 15 07:07:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 07:07:47 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:42037 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490965Ab1HOFHn (ORCPT ); Mon, 15 Aug 2011 07:07:43 +0200 Received: by gwb1 with SMTP id 1so3205169gwb.36 for ; Sun, 14 Aug 2011 22:07:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=rMNGR7zFWwSv06d8H5iOyjiSaluzD9/TgFnDfxqQNBI=; b=dP5NSyK4pFp2on+9IEath3RQD+sCnykoeVlgNloazR0odR0tupCg82C9TaK7UsC/V0 CxdVauPuZXIwvigihepjuXry3TLP4o7lQCp8XifbB+AkMtqFCbtAb4tWuxvDS2JYST2E lj+S5FhU9uvefVOvKXKCf3uRR7VXg++aAb+Q8= Received: by 10.150.113.1 with SMTP id l1mr4701520ybc.49.1313384857187; Sun, 14 Aug 2011 22:07:37 -0700 (PDT) Received: from localhost.localdomain (69-165-142-232.dsl.teksavvy.com [69.165.142.232]) by mx.google.com with ESMTPS id e21sm668516yhn.21.2011.08.14.22.07.33 (version=SSLv3 cipher=OTHER); Sun, 14 Aug 2011 22:07:36 -0700 (PDT) From: Arnaud Lacombe To: linux-kernel@vger.kernel.org Cc: Arnaud Lacombe , Sam Ravnborg , linux-mips@linux-mips.org Subject: [PATCH 02/11] arch/mips: do not use EXTRA_CFLAGS Date: Mon, 15 Aug 2011 01:07:05 -0400 Message-Id: <1313384834-24433-3-git-send-email-lacombar@gmail.com> X-Mailer: git-send-email 1.7.6.153.g78432 In-Reply-To: <1313384834-24433-1-git-send-email-lacombar@gmail.com> References: <1313384834-24433-1-git-send-email-lacombar@gmail.com> X-archive-position: 30873 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lacombar@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10561 Content-Length: 1116 Lines: 33 Usage of these flags has been deprecated for nearly 4 years by: commit f77bf01425b11947eeb3b5b54685212c302741b8 Author: Sam Ravnborg Date: Mon Oct 15 22:25:06 2007 +0200 kbuild: introduce ccflags-y, asflags-y and ldflags-y Moreover, these flags (at least EXTRA_CFLAGS) have been documented for command line use. By default, gmake(1) do not override command line setting, so this is likely to result in build failure or unexpected behavior. Replace their usage by Kbuild's `{as,cc,ld}flags-y'. Cc: Sam Ravnborg Cc: linux-mips@linux-mips.org --- arch/mips/netlogic/xlr/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile index 9bd3f73..2dca585 100644 --- a/arch/mips/netlogic/xlr/Makefile +++ b/arch/mips/netlogic/xlr/Makefile @@ -2,4 +2,4 @@ obj-y += setup.o platform.o irq.o setup.o time.o obj-$(CONFIG_SMP) += smp.o smpboot.o obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o -EXTRA_CFLAGS += -Werror +ccflags-y += -Werror -- 1.7.6.153.g78432 From sshtylyov@mvista.com Mon Aug 15 11:45:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 11:45:51 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:56122 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491819Ab1HOJpq (ORCPT ); Mon, 15 Aug 2011 11:45:46 +0200 Received: by wyh11 with SMTP id 11so4063283wyh.36 for ; Mon, 15 Aug 2011 02:45:41 -0700 (PDT) Received: by 10.216.235.212 with SMTP id u62mr2308961weq.104.1313401540928; Mon, 15 Aug 2011 02:45:40 -0700 (PDT) Received: from [192.168.2.2] ([91.79.88.120]) by mx.google.com with ESMTPS id n6sm3516827wed.40.2011.08.15.02.45.38 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Aug 2011 02:45:39 -0700 (PDT) Message-ID: <4E48EAA0.5020901@mvista.com> Date: Mon, 15 Aug 2011 13:45:04 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 To: Arnaud Lacombe CC: linux-kernel@vger.kernel.org, Sam Ravnborg , linux-mips@linux-mips.org Subject: Re: [PATCH 02/11] arch/mips: do not use EXTRA_CFLAGS References: <1313384834-24433-1-git-send-email-lacombar@gmail.com> <1313384834-24433-3-git-send-email-lacombar@gmail.com> In-Reply-To: <1313384834-24433-3-git-send-email-lacombar@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 30874 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10710 Content-Length: 720 Lines: 24 Hello. On 15-08-2011 9:07, Arnaud Lacombe wrote: > Usage of these flags has been deprecated for nearly 4 years by: > commit f77bf01425b11947eeb3b5b54685212c302741b8 > Author: Sam Ravnborg > Date: Mon Oct 15 22:25:06 2007 +0200 > kbuild: introduce ccflags-y, asflags-y and ldflags-y > Moreover, these flags (at least EXTRA_CFLAGS) have been documented for command > line use. By default, gmake(1) do not override command line setting, so this is > likely to result in build failure or unexpected behavior. > Replace their usage by Kbuild's `{as,cc,ld}flags-y'. > Cc: Sam Ravnborg > Cc: linux-mips@linux-mips.org You didn't sign off. WBR, Sergei From ralf@linux-mips.org Mon Aug 15 14:43:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 14:43:07 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56102 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491819Ab1HOMnD (ORCPT ); Mon, 15 Aug 2011 14:43:03 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7FCgDKk025623 for ; Mon, 15 Aug 2011 13:42:13 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7FCgDAf025621 for linux-mips@linux-mips.org; Mon, 15 Aug 2011 13:42:13 +0100 Resent-From: Ralf Baechle Resent-Date: Mon, 15 Aug 2011 13:42:13 +0100 Resent-Message-ID: <20110815124213.GA25536@linux-mips.org> Resent-To: linux-mips@linux-mips.org Received: from vger.kernel.org ([209.132.180.67]:42299 "EHLO vger.kernel.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491931Ab1HOJSK (ORCPT ); Mon, 15 Aug 2011 11:18:10 +0200 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752726Ab1HOJSJ (ORCPT + 1 other); Mon, 15 Aug 2011 05:18:09 -0400 Received: from mail-ww0-f44.google.com ([74.125.82.44]:45800 "EHLO mail-ww0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752674Ab1HOJSI (ORCPT ); Mon, 15 Aug 2011 05:18:08 -0400 Received: by wwf5 with SMTP id 5so4661742wwf.1 for ; Mon, 15 Aug 2011 02:18:07 -0700 (PDT) Received: by 10.227.19.137 with SMTP id a9mr3210231wbb.105.1313399887364; Mon, 15 Aug 2011 02:18:07 -0700 (PDT) Received: from localhost (gw-ba1.picochip.com [94.175.234.108]) by mx.google.com with ESMTPS id em16sm4394259wbb.50.2011.08.15.02.18.05 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Aug 2011 02:18:05 -0700 (PDT) From: Jamie Iles To: linux-serial@vger.kernel.org Cc: arnd@arndb.de, Jamie Iles , Ralf Baechle Subject: [PATCH 3/5] mips: msp71xx/serial: convert to pr_foo() helpers Date: Mon, 15 Aug 2011 10:17:53 +0100 Message-Id: <1313399875-11006-4-git-send-email-jamie@jamieiles.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1313399875-11006-1-git-send-email-jamie@jamieiles.com> References: <1313399875-11006-1-git-send-email-jamie@jamieiles.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org X-archive-position: 30875 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10802 Content-Length: 1310 Lines: 35 Convert to pr_foo() helpers rather than printk(KERN_.*). Cc: Ralf Baechle Cc: Signed-off-by: Jamie Iles --- arch/mips/pmc-sierra/msp71xx/msp_serial.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c index f726162..c3247b5 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c @@ -65,7 +65,7 @@ void __init msp_serial_setup(void) up.line = 0; up.private_data = (void*)UART0_STATUS_REG; if (early_serial_setup(&up)) - printk(KERN_ERR "Early serial init of port 0 failed\n"); + pr_err("Early serial init of port 0 failed\n"); /* Initialize the second serial port, if one exists */ switch (mips_machtype) { @@ -89,5 +89,5 @@ void __init msp_serial_setup(void) up.line = 1; up.private_data = (void*)UART1_STATUS_REG; if (early_serial_setup(&up)) - printk(KERN_ERR "Early serial init of port 1 failed\n"); + pr_err("Early serial init of port 1 failed\n"); } -- 1.7.4.1 -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html From ralf@linux-mips.org Mon Aug 15 14:43:11 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 14:43:36 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56104 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491944Ab1HOMnL (ORCPT ); Mon, 15 Aug 2011 14:43:11 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7FCgRm4025628 for ; Mon, 15 Aug 2011 13:42:27 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7FCgRFH025627 for linux-mips@linux-mips.org; Mon, 15 Aug 2011 13:42:27 +0100 Resent-From: Ralf Baechle Resent-Date: Mon, 15 Aug 2011 13:42:27 +0100 Resent-Message-ID: <20110815124227.GB25536@linux-mips.org> Resent-To: linux-mips@linux-mips.org Received: from vger.kernel.org ([209.132.180.67]:42299 "EHLO vger.kernel.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491938Ab1HOJSL (ORCPT ); Mon, 15 Aug 2011 11:18:11 +0200 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752674Ab1HOJSK (ORCPT + 1 other); Mon, 15 Aug 2011 05:18:10 -0400 Received: from mail-wy0-f174.google.com ([74.125.82.174]:44113 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752672Ab1HOJSJ (ORCPT ); Mon, 15 Aug 2011 05:18:09 -0400 Received: by mail-wy0-f174.google.com with SMTP id 24so3358626wyg.19 for ; Mon, 15 Aug 2011 02:18:09 -0700 (PDT) Received: by 10.216.156.137 with SMTP id m9mr3194125wek.55.1313399889013; Mon, 15 Aug 2011 02:18:09 -0700 (PDT) Received: from localhost (gw-ba1.picochip.com [94.175.234.108]) by mx.google.com with ESMTPS id b47sm3501138wed.46.2011.08.15.02.18.08 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Aug 2011 02:18:08 -0700 (PDT) From: Jamie Iles To: linux-serial@vger.kernel.org Cc: arnd@arndb.de, Jamie Iles , Ralf Baechle , Alan Cox Subject: [PATCH 4/5] mips: msp71xx/serial: add workaround for DW UART Date: Mon, 15 Aug 2011 10:17:54 +0100 Message-Id: <1313399875-11006-5-git-send-email-jamie@jamieiles.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1313399875-11006-1-git-send-email-jamie@jamieiles.com> References: <1313399875-11006-1-git-send-email-jamie@jamieiles.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org X-archive-position: 30876 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10803 Content-Length: 3750 Lines: 123 The Synopsys DesignWare UART in pmc-sierra msp71xx has an extra feature where the UART detects a write attempt to the LCR whilst busy and raises an interrupt. The driver needs to clear the interrupt and rewrite the LCR. Move this into platform code and out of the 8250 driver. Cc: Ralf Baechle Cc: Alan Cox Signed-off-by: Jamie Iles --- arch/mips/pmc-sierra/msp71xx/msp_serial.c | 69 +++++++++++++++++++++++++++-- 1 files changed, 65 insertions(+), 4 deletions(-) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c index c3247b5..a1c7c7d 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -38,6 +39,55 @@ #include #include +struct msp_uart_data { + int last_lcr; +}; + +static void msp_serial_out(struct uart_port *p, int offset, int value) +{ + struct msp_uart_data *d = p->private_data; + + if (offset == UART_LCR) + d->last_lcr = value; + + offset <<= p->regshift; + writeb(value, p->membase + offset); +} + +static unsigned int msp_serial_in(struct uart_port *p, int offset) +{ + offset <<= p->regshift; + + return readb(p->membase + offset); +} + +static int msp_serial_handle_irq(struct uart_port *p) +{ + struct msp_uart_data *d = p->private_data; + unsigned int iir = readb(p->membase + (UART_IIR << p->regshift)); + + if (serial8250_handle_irq(p, iir)) { + return 1; + } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { + /* + * The DesignWare APB UART has an Busy Detect (0x07) interrupt + * meaning an LCR write attempt occurred while the UART was + * busy. The interrupt must be cleared by reading the UART + * status register (USR) and the LCR re-written. + * + * Note: MSP reserves 0x20 bytes of address space for the UART + * and the USR is mapped in a separate block at an offset of + * 0xc0 from the start of the UART. + */ + (void)readb(p->membase + 0xc0); + writeb(d->last_lcr, p->membase + (UART_LCR << p->regshift)); + + return 1; + } + + return 0; +} + void __init msp_serial_setup(void) { char *s; @@ -59,13 +109,22 @@ void __init msp_serial_setup(void) up.irq = MSP_INT_UART0; up.uartclk = uartclk; up.regshift = 2; - up.iotype = UPIO_DWAPB; /* UPIO_MEM like */ + up.iotype = UPIO_MEM; up.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; up.type = PORT_16550A; up.line = 0; - up.private_data = (void*)UART0_STATUS_REG; - if (early_serial_setup(&up)) + up.serial_out = msp_serial_out; + up.serial_in = msp_serial_in; + up.handle_irq = msp_serial_handle_irq; + up.private_data = kzalloc(sizeof(struct msp_uart_data), GFP_KERNEL); + if (!up.private_data) { + pr_err("failed to allocate uart private data\n"); + return; + } + if (early_serial_setup(&up)) { + kfree(up.private_data); pr_err("Early serial init of port 0 failed\n"); + } /* Initialize the second serial port, if one exists */ switch (mips_machtype) { @@ -88,6 +147,8 @@ void __init msp_serial_setup(void) up.irq = MSP_INT_UART1; up.line = 1; up.private_data = (void*)UART1_STATUS_REG; - if (early_serial_setup(&up)) + if (early_serial_setup(&up)) { + kfree(up.private_data); pr_err("Early serial init of port 1 failed\n"); + } } -- 1.7.4.1 -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html From ralf@linux-mips.org Mon Aug 15 15:13:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 15:13:22 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:36542 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491942Ab1HONNS (ORCPT ); Mon, 15 Aug 2011 15:13:18 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7FDCWCb030124; Mon, 15 Aug 2011 14:12:32 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7FDCVso030123; Mon, 15 Aug 2011 14:12:31 +0100 Date: Mon, 15 Aug 2011 14:12:31 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Greg KH , Linux-MIPS , linux-usb@vger.kernel.org Subject: Re: [PATCH V2 1/8] MIPS: Alchemy: abstract USB block control register access Message-ID: <20110815131231.GA25911@linux-mips.org> References: <1313172753-31088-1-git-send-email-manuel.lauss@googlemail.com> <20110812184227.GA17057@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30877 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10814 Content-Length: 455 Lines: 15 On Fri, Aug 12, 2011 at 08:48:41PM +0200, Manuel Lauss wrote: > > Much nicer, thanks. > > > > I can take this in the USB tree if the MIPS developers want, or if not, > > feel free to add: > >        Acked-by: Greg Kroah-Hartman > > and take it through the MIPS tree. > > Great, thanks. Other patches to the MIPS tree depend on this one, so > I hope Ralf will take it. Yes, queued for 3.2. I'm much happier with this one :-) Ralf From ralf@linux-mips.org Mon Aug 15 15:24:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 15:24:57 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51528 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491942Ab1HONYy (ORCPT ); Mon, 15 Aug 2011 15:24:54 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7FDO5dk031856; Mon, 15 Aug 2011 14:24:07 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7FDO5VV031855; Mon, 15 Aug 2011 14:24:05 +0100 Date: Mon, 15 Aug 2011 14:24:05 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 2/8] MIPS: Alchemy: rewrite USB platform setup. Message-ID: <20110815132405.GB25911@linux-mips.org> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-3-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313141985-5830-3-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30878 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10819 Content-Length: 33 Lines: 3 Queued for 3.2. Thanks, Ralf From ralf@linux-mips.org Mon Aug 15 15:25:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 15:25:22 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51532 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491942Ab1HONZR (ORCPT ); Mon, 15 Aug 2011 15:25:17 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7FDOVE2031876; Mon, 15 Aug 2011 14:24:31 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7FDOVmK031875; Mon, 15 Aug 2011 14:24:31 +0100 Date: Mon, 15 Aug 2011 14:24:31 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 3/8] MIPS: Alchemy: more base address cleanup Message-ID: <20110815132431.GC25911@linux-mips.org> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-4-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313141985-5830-4-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30879 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10820 Content-Length: 33 Lines: 3 Queued for 3.2. Thanks, Ralf From ralf@linux-mips.org Mon Aug 15 15:25:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 15:26:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51538 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491951Ab1HONZ6 (ORCPT ); Mon, 15 Aug 2011 15:25:58 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7FDPDTt031914; Mon, 15 Aug 2011 14:25:13 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7FDPD3P031913; Mon, 15 Aug 2011 14:25:13 +0100 Date: Mon, 15 Aug 2011 14:25:12 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 7/8] MIPS: Alchemy: redo PCI as platform driver Message-ID: <20110815132512.GD25911@linux-mips.org> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-8-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313141985-5830-8-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30880 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10822 Content-Length: 33 Lines: 3 Queued for 3.2. Thanks, Ralf From ralf@linux-mips.org Mon Aug 15 15:42:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 15:42:46 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57092 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491949Ab1HONmh (ORCPT ); Mon, 15 Aug 2011 15:42:37 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7FDfpqC001029; Mon, 15 Aug 2011 14:41:51 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7FDfpuv001028; Mon, 15 Aug 2011 14:41:51 +0100 Date: Mon, 15 Aug 2011 14:41:51 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH] MIPS: Alchemy: db1200: disable cascade IRQ in handler Message-ID: <20110815134151.GA792@linux-mips.org> References: <1313144915-16321-1-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313144915-16321-1-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30881 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10835 Content-Length: 25 Lines: 3 Thanks, applied. Ralf From ralf@linux-mips.org Mon Aug 15 15:56:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 15:56:07 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45627 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491951Ab1HON4D (ORCPT ); Mon, 15 Aug 2011 15:56:03 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7FDtG4K001694; Mon, 15 Aug 2011 14:55:17 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7FDtF8R001693; Mon, 15 Aug 2011 14:55:15 +0100 Date: Mon, 15 Aug 2011 14:55:15 +0100 From: Ralf Baechle To: Sergei Shtylyov Cc: Arnaud Lacombe , linux-kernel@vger.kernel.org, Sam Ravnborg , linux-mips@linux-mips.org Subject: Re: [PATCH 02/11] arch/mips: do not use EXTRA_CFLAGS Message-ID: <20110815135515.GA1441@linux-mips.org> References: <1313384834-24433-1-git-send-email-lacombar@gmail.com> <1313384834-24433-3-git-send-email-lacombar@gmail.com> <4E48EAA0.5020901@mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4E48EAA0.5020901@mvista.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30882 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10856 Content-Length: 246 Lines: 10 On Mon, Aug 15, 2011 at 01:45:04PM +0400, Sergei Shtylyov wrote: > You didn't sign off. True - but I won't make a big fuzz about that for a one-line. I'm sure Arnaud will vow to do right the next time :-) Applied. Thanks, Arnaud! Ralf From lacombar@gmail.com Mon Aug 15 18:19:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 18:19:12 +0200 (CEST) Received: from mail-ey0-f169.google.com ([209.85.215.169]:34994 "EHLO mail-ey0-f169.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491819Ab1HOQTG convert rfc822-to-8bit (ORCPT ); Mon, 15 Aug 2011 18:19:06 +0200 Received: by eye22 with SMTP id 22so3259954eye.0 for ; Mon, 15 Aug 2011 09:19:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=+3AZsa8fjMHGuziQ21Os81goQHToHvtZUYDYImHNR5o=; b=haHOmh6oMV2UddByfhd5si12wuXPQK42JXlkcTRI70iz0KvZzGOeaUN+uZJFXtR3+3 Zq7iosJTOPRMAwXtn5gkzz7a7QIwG4v4269Md8FUWUNFWDyPvTgKfceS9Q8dbi4JpXo+ M3BALEFnLMpZivzGS+tFyzRzjwboscTUXQso0= MIME-Version: 1.0 Received: by 10.14.151.14 with SMTP id a14mr618169eek.169.1313425140707; Mon, 15 Aug 2011 09:19:00 -0700 (PDT) Received: by 10.14.187.14 with HTTP; Mon, 15 Aug 2011 09:19:00 -0700 (PDT) In-Reply-To: <20110815135515.GA1441@linux-mips.org> References: <1313384834-24433-1-git-send-email-lacombar@gmail.com> <1313384834-24433-3-git-send-email-lacombar@gmail.com> <4E48EAA0.5020901@mvista.com> <20110815135515.GA1441@linux-mips.org> Date: Mon, 15 Aug 2011 12:19:00 -0400 Message-ID: Subject: Re: [PATCH 02/11] arch/mips: do not use EXTRA_CFLAGS From: Arnaud Lacombe To: Ralf Baechle Cc: Sergei Shtylyov , linux-kernel@vger.kernel.org, Sam Ravnborg , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 30883 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lacombar@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 11047 Content-Length: 457 Lines: 20 Hi, On Mon, Aug 15, 2011 at 9:55 AM, Ralf Baechle wrote: > On Mon, Aug 15, 2011 at 01:45:04PM +0400, Sergei Shtylyov wrote: > >>    You didn't sign off. > > True - but I won't make a big fuzz about that for a one-line.  I'm sure > Arnaud will vow to do right the next time :-) > You are welcome to slap me. If it's not too late: Signed-off-by: Arnaud Lacombe - Arnaud > Applied.  Thanks, Arnaud! > >  Ralf > From jayachandranc@netlogicmicro.com Mon Aug 15 19:28:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Aug 2011 19:28:39 +0200 (CEST) Received: from mail-ww0-f41.google.com ([74.125.82.41]:41566 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491948Ab1HOR2c convert rfc822-to-8bit (ORCPT ); Mon, 15 Aug 2011 19:28:32 +0200 Received: by wwj26 with SMTP id 26so1489581wwj.0 for ; Mon, 15 Aug 2011 10:28:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=pBJ2641kwexzFiBDzrQP1xLseNZhYTRIwmXm4DKvnEo=; b=h+87bbb2Oixs6/EsxKpvqYP40licDg0HdZhG29DUo6HBl+avykojq6rDELwXBFVzal 2WaOcioiN+0YyGpJ49YvAeuPSuHL5TYzZD8C4Z+FOnISTW5D2Ae6Ihr1lMluI9juVbnr 3da6DdaDh2jzeAInFFW7aFKBq+6lZsSu9Nv/A= MIME-Version: 1.0 Received: by 10.216.46.208 with SMTP id r58mr2200392web.78.1313429307154; Mon, 15 Aug 2011 10:28:27 -0700 (PDT) Received: by 10.216.48.1 with HTTP; Mon, 15 Aug 2011 10:28:27 -0700 (PDT) In-Reply-To: References: <1313384834-24433-1-git-send-email-lacombar@gmail.com> <1313384834-24433-3-git-send-email-lacombar@gmail.com> <4E48EAA0.5020901@mvista.com> <20110815135515.GA1441@linux-mips.org> Date: Mon, 15 Aug 2011 22:58:27 +0530 X-Google-Sender-Auth: fopiUJOTOh6QJn_zkNvmyvpPkYM Message-ID: Subject: Re: [PATCH 02/11] arch/mips: do not use EXTRA_CFLAGS From: "Jayachandran C." To: Arnaud Lacombe Cc: Ralf Baechle , Sergei Shtylyov , linux-kernel@vger.kernel.org, Sam Ravnborg , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 30884 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 11093 Content-Length: 603 Lines: 18 On Mon, Aug 15, 2011 at 9:49 PM, Arnaud Lacombe wrote: > Hi, > > On Mon, Aug 15, 2011 at 9:55 AM, Ralf Baechle wrote: >> On Mon, Aug 15, 2011 at 01:45:04PM +0400, Sergei Shtylyov wrote: >> >>>    You didn't sign off. >> >> True - but I won't make a big fuzz about that for a one-line.  I'm sure >> Arnaud will vow to do right the next time :-) >> > You are welcome to slap me. If it's not too late: > > Signed-off-by: Arnaud Lacombe Thanks for fixing this up. Looks like an acked-by is not needed :) JC (Netlogic XLR/XLS maintainer) From ralf@linux-mips.org Tue Aug 16 12:06:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Aug 2011 12:07:01 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54973 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491988Ab1HPKGv (ORCPT ); Tue, 16 Aug 2011 12:06:51 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7GA5lWq012726; Tue, 16 Aug 2011 11:05:48 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7GA5jcc012724; Tue, 16 Aug 2011 11:05:45 +0100 Date: Tue, 16 Aug 2011 11:05:45 +0100 From: Ralf Baechle To: "Jayachandran C." Cc: Arnaud Lacombe , Sergei Shtylyov , linux-kernel@vger.kernel.org, Sam Ravnborg , linux-mips@linux-mips.org Subject: Re: [PATCH 02/11] arch/mips: do not use EXTRA_CFLAGS Message-ID: <20110816100544.GA12658@linux-mips.org> References: <1313384834-24433-1-git-send-email-lacombar@gmail.com> <1313384834-24433-3-git-send-email-lacombar@gmail.com> <4E48EAA0.5020901@mvista.com> <20110815135515.GA1441@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30885 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 11596 Content-Length: 817 Lines: 23 On Mon, Aug 15, 2011 at 10:58:27PM +0530, Jayachandran C. wrote: > On Mon, Aug 15, 2011 at 9:49 PM, Arnaud Lacombe wrote: > > Hi, > > > > On Mon, Aug 15, 2011 at 9:55 AM, Ralf Baechle wrote: > >> On Mon, Aug 15, 2011 at 01:45:04PM +0400, Sergei Shtylyov wrote: > >> > >>>    You didn't sign off. > >> > >> True - but I won't make a big fuzz about that for a one-line.  I'm sure > >> Arnaud will vow to do right the next time :-) > >> > > You are welcome to slap me. If it's not too late: > > > > Signed-off-by: Arnaud Lacombe > > Thanks for fixing this up. Looks like an acked-by is not needed :) No - but generally an Acked-by: a maintainer or Reviewed-by: or Tested-by: somebody else is always welcome. The more eyeballs, the better :-) Ralf From david.daney@cavium.com Tue Aug 16 19:11:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Aug 2011 19:12:02 +0200 (CEST) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:9211 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492003Ab1HPRLr (ORCPT ); Tue, 16 Aug 2011 19:11:47 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by smtp2.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 16 Aug 2011 13:11:50 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 16 Aug 2011 10:11:05 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 16 Aug 2011 10:11:05 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id p7GHB1N8024516; Tue, 16 Aug 2011 10:11:02 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p7GHAwvH024515; Tue, 16 Aug 2011 10:10:58 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney , "David S. Miller" , Greg Kroah-Hartman Subject: [PATCH] staging: octeon-ethernet: Add missing #includes. Date: Tue, 16 Aug 2011 10:10:56 -0700 Message-Id: <1313514656-24482-1-git-send-email-david.daney@cavium.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 16 Aug 2011 17:11:05.0727 (UTC) FILETIME=[7BD2C8F0:01CC5C37] X-archive-position: 30886 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 11792 Content-Length: 1523 Lines: 44 I looks like something used to implicitly include linux/interrupt.h, and no longer does. Fix the resulting build error by explicitly including it. Signed-off-by: David Daney Cc: David S. Miller Cc: Greg Kroah-Hartman --- This could go via Ralf's linux-mips.org tree as Octeon is a MIPS archecture SOC. It would be nice to get in before the final 3.1 as it is a build breaker. drivers/staging/octeon/ethernet-rgmii.c | 1 + drivers/staging/octeon/ethernet-spi.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c index 9c0d293..c3d73f8 100644 --- a/drivers/staging/octeon/ethernet-rgmii.c +++ b/drivers/staging/octeon/ethernet-rgmii.c @@ -26,6 +26,7 @@ **********************************************************************/ #include #include +#include #include #include #include diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c index 9708254..d0e2d51 100644 --- a/drivers/staging/octeon/ethernet-spi.c +++ b/drivers/staging/octeon/ethernet-spi.c @@ -26,6 +26,7 @@ **********************************************************************/ #include #include +#include #include #include -- 1.7.2.3 From yong.zhang@windriver.com Wed Aug 17 03:55:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Aug 2011 03:55:13 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:39321 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492042Ab1HQBzF (ORCPT ); Wed, 17 Aug 2011 03:55:05 +0200 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id p7H1svPa001120 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Tue, 16 Aug 2011 18:54:57 -0700 (PDT) Received: from yzhang-desktop.corp.ad.wrs.com (128.224.158.133) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server id 14.1.255.0; Tue, 16 Aug 2011 18:54:56 -0700 From: Yong Zhang To: , CC: Ralf Baechle Subject: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex Date: Wed, 17 Aug 2011 09:54:54 +0800 Message-ID: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 30887 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang@windriver.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12139 Content-Length: 2372 Lines: 77 We can't trust in the caller(userspace) to give signed-extend parameter, thus futex-wait may fail in some special case. For example, if 'val' is too big and bit-31 is 1, the caller may enter endless loop at: futex_wait_setup() { ... if (uval != val) { queue_unlock(q, *hb); ret = -EWOULDBLOCK; ... } Below assembler code will make it more easy to understand how the patch take effect :) Dump of assembler code for function SyS_32_futex: 0xffffffff811b6fe8 <+0>: sll a1,a1,0x0 0xffffffff811b6fec <+4>: sll a2,a2,0x0 0xffffffff811b6ff0 <+8>: j 0xffffffff8121a240 0xffffffff811b6ff4 <+12>: sll a5,a5,0x0 Signed-off-by: Yong Zhang Cc: Ralf Baechle --- arch/mips/kernel/linux32.c | 7 +++++++ arch/mips/kernel/scall64-n32.S | 2 +- arch/mips/kernel/scall64-o32.S | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 876a75c..922a554 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -349,3 +349,10 @@ SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags, return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4), dfd, pathname); } + +SYSCALL_DEFINE6(32_futex, u32 __user *, uaddr, int, op, u32, val, + struct compat_timespec __user *, utime, u32 __user *, uaddr2, + u32, val3) +{ + return compat_sys_futex(uaddr, op, val, utime, uaddr2, val3); +} diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index b85842f..c956cc9 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -315,7 +315,7 @@ EXPORT(sysn32_call_table) PTR sys_fremovexattr PTR sys_tkill PTR sys_ni_syscall - PTR compat_sys_futex + PTR sys_32_futex PTR compat_sys_sched_setaffinity /* 6195 */ PTR compat_sys_sched_getaffinity PTR sys_cacheflush diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 46c4763..f48b18e 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -441,7 +441,7 @@ sys_call_table: PTR sys_fremovexattr /* 4235 */ PTR sys_tkill PTR sys_sendfile64 - PTR compat_sys_futex + PTR sys_32_futex PTR compat_sys_sched_setaffinity PTR compat_sys_sched_getaffinity /* 4240 */ PTR compat_sys_io_setup -- 1.7.4.1 From ralf@linux-mips.org Wed Aug 17 14:44:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Aug 2011 14:44:40 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60345 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491841Ab1HQMog (ORCPT ); Wed, 17 Aug 2011 14:44:36 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7HChDd2016490; Wed, 17 Aug 2011 13:43:13 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7HChC33016483; Wed, 17 Aug 2011 13:43:12 +0100 Date: Wed, 17 Aug 2011 13:43:12 +0100 From: Ralf Baechle To: Yong Zhang Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex Message-ID: <20110817124312.GA16422@linux-mips.org> References: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30888 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12405 Content-Length: 31 Lines: 3 Applied. Thanks Yong! Ralf From david.daney@cavium.com Wed Aug 17 19:17:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Aug 2011 19:18:03 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16880 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492055Ab1HQRR5 (ORCPT ); Wed, 17 Aug 2011 19:17:57 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 17 Aug 2011 10:19:02 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 17 Aug 2011 10:17:53 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 17 Aug 2011 10:17:53 -0700 Message-ID: <4E4BF7C0.80703@cavium.com> Date: Wed, 17 Aug 2011 10:17:52 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Yong Zhang CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: Re: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex References: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> In-Reply-To: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 17 Aug 2011 17:17:53.0680 (UTC) FILETIME=[99653900:01CC5D01] X-archive-position: 30889 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12646 Content-Length: 3594 Lines: 109 On 08/16/2011 06:54 PM, Yong Zhang wrote: > We can't trust in the caller(userspace) to give signed-extend > parameter, thus futex-wait may fail in some special case. > > For example, if 'val' is too big and bit-31 is 1, > the caller may enter endless loop at: > futex_wait_setup() > { > ... > > if (uval != val) { > queue_unlock(q, *hb); > ret = -EWOULDBLOCK; > > ... > } > > Below assembler code will make it more easy to understand how > the patch take effect :) > > Dump of assembler code for function SyS_32_futex: > 0xffffffff811b6fe8<+0>: sll a1,a1,0x0 > 0xffffffff811b6fec<+4>: sll a2,a2,0x0 > 0xffffffff811b6ff0<+8>: j 0xffffffff8121a240 > 0xffffffff811b6ff4<+12>: sll a5,a5,0x0 > > Signed-off-by: Yong Zhang > Cc: Ralf Baechle > --- > arch/mips/kernel/linux32.c | 7 +++++++ > arch/mips/kernel/scall64-n32.S | 2 +- > arch/mips/kernel/scall64-o32.S | 2 +- > 3 files changed, 9 insertions(+), 2 deletions(-) [...] > diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c > index 876a75c..922a554 100644 > --- a/arch/mips/kernel/linux32.c > +++ b/arch/mips/kernel/linux32.c > @@ -349,3 +349,10 @@ SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags, > return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4), > dfd, pathname); > } > + > +SYSCALL_DEFINE6(32_futex, u32 __user *, uaddr, int, op, u32, val, > + struct compat_timespec __user *, utime, u32 __user *, uaddr2, > + u32, val3) > +{ > + return compat_sys_futex(uaddr, op, val, utime, uaddr2, val3); > +} > diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S > index b85842f..c956cc9 100644 > --- a/arch/mips/kernel/scall64-n32.S > +++ b/arch/mips/kernel/scall64-n32.S > @@ -315,7 +315,7 @@ EXPORT(sysn32_call_table) > PTR sys_fremovexattr > PTR sys_tkill > PTR sys_ni_syscall > - PTR compat_sys_futex > + PTR sys_32_futex > PTR compat_sys_sched_setaffinity /* 6195 */ > PTR compat_sys_sched_getaffinity > PTR sys_cacheflush > diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S > index 46c4763..f48b18e 100644 > --- a/arch/mips/kernel/scall64-o32.S > +++ b/arch/mips/kernel/scall64-o32.S > @@ -441,7 +441,7 @@ sys_call_table: > PTR sys_fremovexattr /* 4235 */ > PTR sys_tkill > PTR sys_sendfile64 > - PTR compat_sys_futex > + PTR sys_32_futex This change is redundant, scall64-o32.S already does the right thing so additional zero extending is not needed and is just extra instructions to execute for no reason. > PTR compat_sys_sched_setaffinity > PTR compat_sys_sched_getaffinity /* 4240 */ > PTR compat_sys_io_setup But really I think this patch fixes things at the wrong level. Each architecture potentially needs a similar patch. What would happen if we did something like: diff --git a/kernel/futex_compat.c b/kernel/futex_compat.c index 5f9e689..74ada65 100644 --- a/kernel/futex_compat.c +++ b/kernel/futex_compat.c @@ -180,9 +180,9 @@ err_unlock: return ret; } -asmlinkage long compat_sys_futex(u32 __user *uaddr, int op, u32 val, - struct compat_timespec __user *utime, u32 __user *uaddr2, - u32 val3) +SYSCALL_DEFINE6(compat_sys_futex, u32 __user *, uaddr, int , op, u32, val, + struct compat_timespec __user *, utime, u32 __user *, uaddr2, + u32, val3) { struct timespec ts; ktime_t t, *tp = NULL; Obviously the function name is wrong, but a varient of SYSCALL_DEFINE*() could be created so the proper function names are produced. David Daney From yong.zhang@windriver.com Thu Aug 18 04:33:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 04:33:07 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:51939 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490968Ab1HRCdC (ORCPT ); Thu, 18 Aug 2011 04:33:02 +0200 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id p7I2Wp3j029483 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Wed, 17 Aug 2011 19:32:51 -0700 (PDT) Received: from localhost (128.224.158.133) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server (TLS) id 14.1.255.0; Wed, 17 Aug 2011 19:32:51 -0700 Date: Thu, 18 Aug 2011 10:32:47 +0800 From: Yong Zhang To: David Daney CC: , , Ralf Baechle Subject: Re: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex Message-ID: <20110818023247.GA3750@windriver.com> Reply-To: Yong Zhang References: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> <4E4BF7C0.80703@cavium.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <4E4BF7C0.80703@cavium.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [128.224.158.133] X-archive-position: 30890 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang@windriver.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12926 Content-Length: 994 Lines: 28 On Wed, Aug 17, 2011 at 10:17:52AM -0700, David Daney wrote: > >diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S > >index 46c4763..f48b18e 100644 > >--- a/arch/mips/kernel/scall64-o32.S > >+++ b/arch/mips/kernel/scall64-o32.S > >@@ -441,7 +441,7 @@ sys_call_table: > > PTR sys_fremovexattr /* 4235 */ > > PTR sys_tkill > > PTR sys_sendfile64 > >- PTR compat_sys_futex > >+ PTR sys_32_futex > > This change is redundant, scall64-o32.S already does the right thing My first virsion(not sent out) doesn't include scall64-o32.S either. > so additional zero extending is not needed and is just extra > instructions to execute for no reason. Why I'm adding it here is for: 1)code consistent, otherwise we must move SYSCALL_DEFINE6(32_futex,...) under CONFIG_MIPS32_N32; 2)I'm afraid there may be some other way to touch the high 32-bit of a register, so touching scall64-o32.S is also for safety(due to unknown reason, fix me if I'm wrong). Thanks, Yong From yong.zhang@windriver.com Thu Aug 18 04:44:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 04:44:40 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:53492 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490968Ab1HRCof (ORCPT ); Thu, 18 Aug 2011 04:44:35 +0200 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id p7I2iQxJ000765 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Wed, 17 Aug 2011 19:44:26 -0700 (PDT) Received: from localhost (128.224.158.133) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server (TLS) id 14.1.255.0; Wed, 17 Aug 2011 19:44:26 -0700 Date: Thu, 18 Aug 2011 10:44:22 +0800 From: Yong Zhang To: David Daney CC: , , Ralf Baechle Subject: Re: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex Message-ID: <20110818024422.GB3750@windriver.com> Reply-To: Yong Zhang References: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> <4E4BF7C0.80703@cavium.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <4E4BF7C0.80703@cavium.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [128.224.158.133] X-archive-position: 30891 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang@windriver.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12930 Content-Length: 1880 Lines: 60 On Wed, Aug 17, 2011 at 10:17:52AM -0700, David Daney wrote: > > PTR compat_sys_sched_setaffinity > > PTR compat_sys_sched_getaffinity /* 4240 */ > > PTR compat_sys_io_setup > > But really I think this patch fixes things at the wrong level. Each > architecture potentially needs a similar patch. What would happen if > we did something like: I have thought about it but finally I decide to keep it under arch code; because sparc64 and s390 have the same issue and they all smooth the concern by themselves. For sparc64: arch/sparc/kernel/sys32.S: 91: SIGN3(sys32_futex, compat_sys_futex, %o1, %o2, %o5) For s390: arch/s390/kernel/compat_wrapper.S ENTRY(compat_sys_futex_wrapper) llgtr %r2,%r2 # u32 * lgfr %r3,%r3 # int lgfr %r4,%r4 # int llgtr %r5,%r5 # struct compat_timespec * llgtr %r6,%r6 # u32 * lgf %r0,164(%r15) # int stg %r0,160(%r15) jg compat_sys_futex # branch to system call Maybe we can consolidate all of this like your patch in the future, but it's a different issue. Thanks, Yong > > > diff --git a/kernel/futex_compat.c b/kernel/futex_compat.c > index 5f9e689..74ada65 100644 > --- a/kernel/futex_compat.c > +++ b/kernel/futex_compat.c > @@ -180,9 +180,9 @@ err_unlock: > return ret; > } > > -asmlinkage long compat_sys_futex(u32 __user *uaddr, int op, u32 val, > - struct compat_timespec __user *utime, u32 __user *uaddr2, > - u32 val3) > +SYSCALL_DEFINE6(compat_sys_futex, u32 __user *, uaddr, int , op, u32, val, > + struct compat_timespec __user *, utime, u32 __user *, uaddr2, > + u32, val3) > { > struct timespec ts; > ktime_t t, *tp = NULL; > > Obviously the function name is wrong, but a varient of > SYSCALL_DEFINE*() could be created so the proper function names are > produced. > > David Daney From manuel.lauss@googlemail.com Thu Aug 18 11:12:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 11:12:30 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:34342 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492102Ab1HRJMW (ORCPT ); Thu, 18 Aug 2011 11:12:22 +0200 Received: by bke17 with SMTP id 17so1615096bke.36 for ; Thu, 18 Aug 2011 02:12:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=PGn9Zvk4TZSEoLGgyVO67dRrnVhDNN3orKDGQFyGwNo=; b=myuYVrAZMX41VcKI1cdRf6FRA/I1X4ZlCZpnTJu/ApsqVHKRToVblhjpX4eUQqvQIF WjvyT4/3ea6y9lB1MTSVMklZb5sq09LbOeu9Mv55fZ3eSxfCSHapKGP3oF7BTNSaEKwN Bl962ydNKOQkqSYfOsIrkAWn1j52biIlim4kg= Received: by 10.204.231.197 with SMTP id jr5mr237624bkb.155.1313658736450; Thu, 18 Aug 2011 02:12:16 -0700 (PDT) Received: from localhost.localdomain (188-22-156-154.adsl.highway.telekom.at [188.22.156.154]) by mx.google.com with ESMTPS id q1sm4284311faa.3.2011.08.18.02.12.13 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Aug 2011 02:12:14 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss , linux-ide@vger.kernel.org, "David S. Miller" Subject: [PATCH RESEND 4/8] MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dep Date: Thu, 18 Aug 2011 11:11:58 +0200 Message-Id: <1313658718-14144-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.6 X-archive-position: 30892 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13098 Content-Length: 7197 Lines: 206 au1xxx-ide uses defines from the pb1200/db1200 headers: get DBDMA ID through platform resource information, hardcode register spacing. The only 2 users of this driver (and the only boards it can really work on realiably) use the same register layout. Cc: linux-ide@vger.kernel.org Cc: David S. Miller Signed-off-by: Manuel Lauss --- Resend: adding old-IDE Maintainer David Miller to CC's I'd like for this to go through the MIPS tree, as other changes in it depend on it. arch/mips/alchemy/devboards/db1200/platform.c | 7 +++- arch/mips/alchemy/devboards/pb1200/platform.c | 8 ++++- arch/mips/include/asm/mach-au1x00/au1xxx_ide.h | 1 + arch/mips/include/asm/mach-db1x00/db1200.h | 2 - arch/mips/include/asm/mach-pb1x00/pb1200.h | 2 - drivers/ide/au1xxx-ide.c | 44 ++++++++++++++---------- 6 files changed, 40 insertions(+), 24 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index 95c7327..6fd070d 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -213,7 +213,12 @@ static struct resource db1200_ide_res[] = { .start = DB1200_IDE_INT, .end = DB1200_IDE_INT, .flags = IORESOURCE_IRQ, - } + }, + [2] = { + .start = DSCR_CMD0_DMA_REQ1, + .end = DSCR_CMD0_DMA_REQ1, + .flags = IORESOURCE_DMA, + }, }; static u64 ide_dmamask = DMA_BIT_MASK(32); diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index c52809d..6ac0494 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -26,6 +26,7 @@ #include #include +#include #include #include "../platform.h" @@ -115,7 +116,12 @@ static struct resource ide_resources[] = { .start = IDE_INT, .end = IDE_INT, .flags = IORESOURCE_IRQ - } + }, + [2] = { + .start = DSCR_CMD0_DMA_REQ1, + .end = DSCR_CMD0_DMA_REQ1, + .flags = IORESOURCE_DMA, + }, }; static u64 ide_dmamask = DMA_BIT_MASK(32); diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h index 5656c72..e306384 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h @@ -58,6 +58,7 @@ typedef struct { #endif int irq; u32 regbase; + int ddma_id; } _auide_hwif; /******************************************************************************/ diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 3404248..7a39657 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -46,8 +46,6 @@ #define IDE_PHYS_ADDR 0x18800000 #define IDE_REG_SHIFT 5 -#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 -#define IDE_RQSIZE 128 #define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR #define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index 0ecff1c..56865e9 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -76,8 +76,6 @@ #define IDE_REG_SHIFT 5 #define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) #define IDE_INT PB1200_IDE_INT -#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 -#define IDE_RQSIZE 128 #define NAND_PHYS_ADDR 0x1C000000 diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c index b26c234..c778373 100644 --- a/drivers/ide/au1xxx-ide.c +++ b/drivers/ide/au1xxx-ide.c @@ -43,6 +43,10 @@ #define DRV_NAME "au1200-ide" #define DRV_AUTHOR "Enrico Walther / Pete Popov " +#ifndef IDE_REG_SHIFT +#define IDE_REG_SHIFT 5 +#endif + /* enable the burstmode in the dbdma */ #define IDE_AU1XXX_BURSTMODE 1 @@ -317,10 +321,11 @@ static void auide_ddma_rx_callback(int irq, void *param) } #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ -static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) +static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, + u32 devwidth, u32 flags, u32 regbase) { dev->dev_id = dev_id; - dev->dev_physaddr = (u32)IDE_PHYS_ADDR; + dev->dev_physaddr = CPHYSADDR(regbase); dev->dev_intlevel = 0; dev->dev_intpolarity = 0; dev->dev_tsize = tsize; @@ -344,7 +349,7 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) dbdev_tab_t source_dev_tab, target_dev_tab; u32 dev_id, tsize, devwidth, flags; - dev_id = IDE_DDMA_REQ; + dev_id = hwif->ddma_id; tsize = 8; /* 1 */ devwidth = 32; /* 16 */ @@ -356,20 +361,17 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) #endif /* setup dev_tab for tx channel */ - auide_init_dbdma_dev( &source_dev_tab, - dev_id, - tsize, devwidth, DEV_FLAGS_OUT | flags); + auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, + DEV_FLAGS_OUT | flags, auide->regbase); auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - auide_init_dbdma_dev( &source_dev_tab, - dev_id, - tsize, devwidth, DEV_FLAGS_IN | flags); + auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, + DEV_FLAGS_IN | flags, auide->regbase); auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); /* We also need to add a target device for the DMA */ - auide_init_dbdma_dev( &target_dev_tab, - (u32)DSCR_CMD0_ALWAYS, - tsize, devwidth, DEV_FLAGS_ANYUSE); + auide_init_dbdma_dev(&target_dev_tab, (u32)DSCR_CMD0_ALWAYS, tsize, + devwidth, DEV_FLAGS_ANYUSE, auide->regbase); auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); /* Get a channel for TX */ @@ -411,14 +413,12 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) #endif /* setup dev_tab for tx channel */ - auide_init_dbdma_dev( &source_dev_tab, - (u32)DSCR_CMD0_ALWAYS, - 8, 32, DEV_FLAGS_OUT | flags); + auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, + DEV_FLAGS_OUT | flags, auide->regbase); auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - auide_init_dbdma_dev( &source_dev_tab, - (u32)DSCR_CMD0_ALWAYS, - 8, 32, DEV_FLAGS_IN | flags); + auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, + DEV_FLAGS_IN | flags, auide->regbase); auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); /* Get a channel for TX */ @@ -540,6 +540,14 @@ static int au_ide_probe(struct platform_device *dev) goto out; } + res = platform_get_resource(dev, IORESOURCE_DMA, 0); + if (!res) { + pr_debug("%s: no DDMA ID resource\n", DRV_NAME); + ret = -ENODEV; + goto out; + } + ahwif->ddma_id = res->start; + memset(&hw, 0, sizeof(hw)); auide_setup_ports(&hw, ahwif); hw.irq = ahwif->irq; -- 1.7.6 From davem@davemloft.net Thu Aug 18 13:03:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 13:03:58 +0200 (CEST) Received: from shards.monkeyblade.net ([198.137.202.13]:36390 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492129Ab1HRLDs (ORCPT ); Thu, 18 Aug 2011 13:03:48 +0200 Received: from localhost (74-93-104-98-Washington.hfc.comcastbusiness.net [74.93.104.98]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id p7IB3fNV019583 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 18 Aug 2011 04:03:43 -0700 Date: Thu, 18 Aug 2011 04:03:41 -0700 (PDT) Message-Id: <20110818.040341.498460978855618496.davem@davemloft.net> To: manuel.lauss@googlemail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-ide@vger.kernel.org Subject: Re: [PATCH RESEND 4/8] MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dep From: David Miller In-Reply-To: <1313658718-14144-1-git-send-email-manuel.lauss@googlemail.com> References: <1313658718-14144-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: Mew version 6.3 on Emacs 23.2 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (shards.monkeyblade.net [198.137.202.13]); Thu, 18 Aug 2011 04:03:44 -0700 (PDT) X-archive-position: 30893 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13152 Content-Length: 689 Lines: 18 From: Manuel Lauss Date: Thu, 18 Aug 2011 11:11:58 +0200 > au1xxx-ide uses defines from the pb1200/db1200 headers: > get DBDMA ID through platform resource information, > hardcode register spacing. The only 2 users of this driver (and > the only boards it can really work on realiably) use the same > register layout. > > Cc: linux-ide@vger.kernel.org > Cc: David S. Miller > Signed-off-by: Manuel Lauss > --- > Resend: adding old-IDE Maintainer David Miller to CC's > I'd like for this to go through the MIPS tree, as other changes in it > depend on it. Acked-by: David S. Miller From david.daney@cavium.com Thu Aug 18 18:23:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 18:24:06 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:2119 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492141Ab1HRQX6 (ORCPT ); Thu, 18 Aug 2011 18:23:58 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 18 Aug 2011 09:25:04 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 18 Aug 2011 09:23:55 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 18 Aug 2011 09:23:55 -0700 Message-ID: <4E4D3C8D.1040707@cavium.com> Date: Thu, 18 Aug 2011 09:23:41 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Yong Zhang CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: Re: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex References: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> <4E4BF7C0.80703@cavium.com> <20110818023247.GA3750@windriver.com> In-Reply-To: <20110818023247.GA3750@windriver.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 18 Aug 2011 16:23:55.0628 (UTC) FILETIME=[39C772C0:01CC5DC3] X-archive-position: 30894 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13377 Content-Length: 1256 Lines: 35 On 08/17/2011 07:32 PM, Yong Zhang wrote: > On Wed, Aug 17, 2011 at 10:17:52AM -0700, David Daney wrote: >>> diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S >>> index 46c4763..f48b18e 100644 >>> --- a/arch/mips/kernel/scall64-o32.S >>> +++ b/arch/mips/kernel/scall64-o32.S >>> @@ -441,7 +441,7 @@ sys_call_table: >>> PTR sys_fremovexattr /* 4235 */ >>> PTR sys_tkill >>> PTR sys_sendfile64 >>> - PTR compat_sys_futex >>> + PTR sys_32_futex >> >> This change is redundant, scall64-o32.S already does the right thing > > My first virsion(not sent out) doesn't include scall64-o32.S either. > >> so additional zero extending is not needed and is just extra >> instructions to execute for no reason. > > Why I'm adding it here is for: > 1)code consistent, otherwise we must move SYSCALL_DEFINE6(32_futex,...) > under CONFIG_MIPS32_N32; No, you don't have to move it. Just don't call it. > 2)I'm afraid there may be some other way to touch the high 32-bit of a > register, so touching scall64-o32.S is also for safety(due to unknown > reason, fix me if I'm wrong). OK: You are mistaken. You claim you don't understand what the code does. That is really a poor justification for modifying it. David Daney From ralf@linux-mips.org Thu Aug 18 20:03:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 20:03:52 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:37641 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492156Ab1HRSDs (ORCPT ); Thu, 18 Aug 2011 20:03:48 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IHufOp015796; Thu, 18 Aug 2011 18:56:42 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IHudii015789; Thu, 18 Aug 2011 18:56:39 +0100 Date: Thu, 18 Aug 2011 18:56:39 +0100 From: Ralf Baechle To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, "Rafael J. Wysocki" , stable@kernel.org Subject: Re: [PATCH 1/4] PM / MIPS: Use struct syscore_ops instead of sysdevs for PM (v2) Message-ID: <20110818175639.GA14371@linux-mips.org> References: <1307063211-10098-1-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1307063211-10098-1-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30895 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13472 Content-Length: 4244 Lines: 139 Thanks, applied. This should also got into 3.0-stable. Ralf On Fri, Jun 03, 2011 at 03:06:48AM +0200, Lars-Peter Clausen wrote: > From: Rafael J. Wysocki > > Convert some MIPS architecture's code to using struct syscore_ops > objects for power management instead of sysdev classes and sysdevs. > > This simplifies the code and reduces the kernel's memory footprint. > It also is necessary for removing sysdevs from the kernel entirely in > the future. > > Signed-off-by: Rafael J. Wysocki > Acked-by: Greg Kroah-Hartman > Acked-and-tested-by: Lars-Peter Clausen > Signed-off-by: Lars-Peter Clausen > --- > arch/mips/jz4740/gpio.c | 52 +++++++++++++++++++--------------------------- > 1 files changed, 22 insertions(+), 30 deletions(-) > > diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c > index 73031f7..4397972 100644 > --- a/arch/mips/jz4740/gpio.c > +++ b/arch/mips/jz4740/gpio.c > @@ -18,7 +18,7 @@ > #include > > #include > -#include > +#include > #include > #include > #include > @@ -86,7 +86,6 @@ struct jz_gpio_chip { > spinlock_t lock; > > struct gpio_chip gpio_chip; > - struct sys_device sysdev; > }; > > static struct jz_gpio_chip jz4740_gpio_chips[]; > @@ -459,49 +458,47 @@ static struct jz_gpio_chip jz4740_gpio_chips[] = { > JZ4740_GPIO_CHIP(D), > }; > > -static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev) > +static void jz4740_gpio_suspend_chip(struct jz_gpio_chip *chip) > { > - return container_of(dev, struct jz_gpio_chip, sysdev); > + chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK); > + writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET); > + writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR); > } > > -static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state) > +static int jz4740_gpio_suspend(void) > { > - struct jz_gpio_chip *chip = sysdev_to_chip(dev); > + int i; > > - chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK); > - writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET); > - writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR); > + for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); i++) > + jz4740_gpio_suspend_chip(&jz4740_gpio_chips[i]); > > return 0; > } > > -static int jz4740_gpio_resume(struct sys_device *dev) > +static void jz4740_gpio_resume_chip(struct jz_gpio_chip *chip) > { > - struct jz_gpio_chip *chip = sysdev_to_chip(dev); > uint32_t mask = chip->suspend_mask; > > writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR); > writel(mask, chip->base + JZ_REG_GPIO_MASK_SET); > +} > > - return 0; > +static void jz4740_gpio_resume(void) > +{ > + int i; > + > + for (i = ARRAY_SIZE(jz4740_gpio_chips) - 1; i >= 0 ; i--) > + jz4740_gpio_resume_chip(&jz4740_gpio_chips[i]); > } > > -static struct sysdev_class jz4740_gpio_sysdev_class = { > - .name = "gpio", > +static struct syscore_ops jz4740_gpio_syscore_ops = { > .suspend = jz4740_gpio_suspend, > .resume = jz4740_gpio_resume, > }; > > -static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) > +static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) > { > - int ret, irq; > - > - chip->sysdev.id = id; > - chip->sysdev.cls = &jz4740_gpio_sysdev_class; > - ret = sysdev_register(&chip->sysdev); > - > - if (ret) > - return ret; > + int irq; > > spin_lock_init(&chip->lock); > > @@ -519,22 +516,17 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) > irq_set_chip_and_handler(irq, &jz_gpio_irq_chip, > handle_level_irq); > } > - > - return 0; > } > > static int __init jz4740_gpio_init(void) > { > unsigned int i; > - int ret; > - > - ret = sysdev_class_register(&jz4740_gpio_sysdev_class); > - if (ret) > - return ret; > > for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i) > jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i); > > + register_syscore_ops(&jz4740_gpio_syscore_ops); > + > printk(KERN_INFO "JZ4740 GPIO initialized\n"); > > return 0; > -- > 1.7.2.5 From ralf@linux-mips.org Thu Aug 18 20:11:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 20:11:10 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:50674 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492160Ab1HRSLH (ORCPT ); Thu, 18 Aug 2011 20:11:07 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IIB44f018347; Thu, 18 Aug 2011 19:11:04 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IIB3CL018340; Thu, 18 Aug 2011 19:11:03 +0100 Date: Thu, 18 Aug 2011 19:11:03 +0100 From: Ralf Baechle To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Thomas Gleixner Subject: Re: [PATCH 2/4] MIPS: JZ4740: Use generic irq chip Message-ID: <20110818181103.GB14371@linux-mips.org> References: <1307063211-10098-1-git-send-email-lars@metafoo.de> <1307063211-10098-2-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1307063211-10098-2-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30896 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13474 Content-Length: 32 Lines: 3 Thanks, queued for 3.2. Ralf From ralf@linux-mips.org Thu Aug 18 20:11:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 20:11:34 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:50680 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492163Ab1HRSLP (ORCPT ); Thu, 18 Aug 2011 20:11:15 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IIBEbZ018385; Thu, 18 Aug 2011 19:11:14 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IIBEJD018384; Thu, 18 Aug 2011 19:11:14 +0100 Date: Thu, 18 Aug 2011 19:11:14 +0100 From: Ralf Baechle To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/4] MIPS: JZ4740: GPIO: Simplify IRQ demuxer Message-ID: <20110818181114.GC14371@linux-mips.org> References: <1307063211-10098-1-git-send-email-lars@metafoo.de> <1307063211-10098-3-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1307063211-10098-3-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30897 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13479 Content-Length: 32 Lines: 3 Thanks, queued for 3.2. Ralf From ralf@linux-mips.org Thu Aug 18 20:11:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 20:11:58 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:50684 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492164Ab1HRSLY (ORCPT ); Thu, 18 Aug 2011 20:11:24 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IIBNtZ018406; Thu, 18 Aug 2011 19:11:23 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IIBNUw018405; Thu, 18 Aug 2011 19:11:23 +0100 Date: Thu, 18 Aug 2011 19:11:23 +0100 From: Ralf Baechle To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/4] MIPS: JZ4740: GPIO: Check correct IRQ in demux handler Message-ID: <20110818181123.GD14371@linux-mips.org> References: <1307063211-10098-1-git-send-email-lars@metafoo.de> <1307063211-10098-4-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1307063211-10098-4-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30898 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13480 Content-Length: 32 Lines: 3 Thanks, queued for 3.2. Ralf From ralf@linux-mips.org Thu Aug 18 21:05:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 21:05:38 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:39234 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492155Ab1HRTFd (ORCPT ); Thu, 18 Aug 2011 21:05:33 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IJ5QHZ023988; Thu, 18 Aug 2011 20:05:26 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IJ5Olv023981; Thu, 18 Aug 2011 20:05:24 +0100 Date: Thu, 18 Aug 2011 20:05:24 +0100 From: Ralf Baechle To: David Miller Cc: manuel.lauss@googlemail.com, linux-mips@linux-mips.org, linux-ide@vger.kernel.org Subject: Re: [PATCH RESEND 4/8] MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dep Message-ID: <20110818190524.GA22920@linux-mips.org> References: <1313658718-14144-1-git-send-email-manuel.lauss@googlemail.com> <20110818.040341.498460978855618496.davem@davemloft.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110818.040341.498460978855618496.davem@davemloft.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30899 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13539 Content-Length: 32 Lines: 3 Thanks, queued for 3.2. Ralf From ralf@linux-mips.org Thu Aug 18 21:12:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 21:13:05 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47454 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492169Ab1HRTM7 (ORCPT ); Thu, 18 Aug 2011 21:12:59 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IJCujI026162; Thu, 18 Aug 2011 20:12:56 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IJCu5G026161; Thu, 18 Aug 2011 20:12:56 +0100 Date: Thu, 18 Aug 2011 20:12:56 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 5/8] MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines Message-ID: <20110818191256.GB22920@linux-mips.org> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-6-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313141985-5830-6-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30900 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13584 Content-Length: 33 Lines: 3 Queued for 3.2. Thanks, Ralf From ralf@linux-mips.org Thu Aug 18 21:13:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 21:13:31 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47457 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492171Ab1HRTNH (ORCPT ); Thu, 18 Aug 2011 21:13:07 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IJD5LI026183; Thu, 18 Aug 2011 20:13:05 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IJD55P026181; Thu, 18 Aug 2011 20:13:05 +0100 Date: Thu, 18 Aug 2011 20:13:05 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 6/8] MIPS: Alchemy: kill au1xxx.h header Message-ID: <20110818191304.GC22920@linux-mips.org> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-7-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313141985-5830-7-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30901 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13594 Content-Length: 33 Lines: 3 Queued for 3.2. Thanks, Ralf From ralf@linux-mips.org Thu Aug 18 21:13:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 21:13:55 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47460 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492172Ab1HRTNT (ORCPT ); Thu, 18 Aug 2011 21:13:19 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IJDGJA026204; Thu, 18 Aug 2011 20:13:16 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IJDGSO026203; Thu, 18 Aug 2011 20:13:16 +0100 Date: Thu, 18 Aug 2011 20:13:16 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH 8/8] MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines Message-ID: <20110818191316.GD22920@linux-mips.org> References: <1313141985-5830-1-git-send-email-manuel.lauss@googlemail.com> <1313141985-5830-9-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1313141985-5830-9-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30902 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13595 Content-Length: 33 Lines: 3 Queued for 3.2. Thanks, Ralf From ralf@linux-mips.org Thu Aug 18 22:19:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 22:19:25 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49649 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492153Ab1HRUTW (ORCPT ); Thu, 18 Aug 2011 22:19:22 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IKJDhe032357; Thu, 18 Aug 2011 21:19:13 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IKJBR0032349; Thu, 18 Aug 2011 21:19:11 +0100 Date: Thu, 18 Aug 2011 21:19:11 +0100 From: Ralf Baechle To: David Daney Cc: Yong Zhang , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex Message-ID: <20110818201911.GF22920@linux-mips.org> References: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> <4E4BF7C0.80703@cavium.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4E4BF7C0.80703@cavium.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30903 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13647 Content-Length: 2027 Lines: 55 On Wed, Aug 17, 2011 at 10:17:52AM -0700, David Daney wrote: > >diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S > >index 46c4763..f48b18e 100644 > >--- a/arch/mips/kernel/scall64-o32.S > >+++ b/arch/mips/kernel/scall64-o32.S > >@@ -441,7 +441,7 @@ sys_call_table: > > PTR sys_fremovexattr /* 4235 */ > > PTR sys_tkill > > PTR sys_sendfile64 > >- PTR compat_sys_futex > >+ PTR sys_32_futex > > This change is redundant, scall64-o32.S already does the right thing > so additional zero extending is not needed and is just extra > instructions to execute for no reason. Compat_sys_futex is a syscall entry point and for some configurations such as CONFIG_FTRACE_SYSCALLS SYSCALL_DEFINE*() will do additional work beyond cleaning up the arguments. The 3 unnecessary shifts are the overhead we just gotta live with. > > PTR compat_sys_sched_setaffinity > > PTR compat_sys_sched_getaffinity /* 4240 */ > > PTR compat_sys_io_setup > > But really I think this patch fixes things at the wrong level. Each > architecture potentially needs a similar patch. What would happen if > we did something like: > +++ b/kernel/futex_compat.c > @@ -180,9 +180,9 @@ err_unlock: > return ret; > } > > -asmlinkage long compat_sys_futex(u32 __user *uaddr, int op, u32 val, > - struct compat_timespec __user *utime, u32 __user *uaddr2, > - u32 val3) > +SYSCALL_DEFINE6(compat_sys_futex, u32 __user *, uaddr, int , op, u32, val, > + struct compat_timespec __user *, utime, u32 __user *, uaddr2, > + u32, val3) > { > struct timespec ts; > ktime_t t, *tp = NULL; > > Obviously the function name is wrong, but a varient of > SYSCALL_DEFINE*() could be created so the proper function names are > produced. Right now none of the the generic compat_ functions is wrapped in SYSCALL_DEFINE* because for some architectures a further wrapper function is needed. It seems some architectures call compat_ calls directly without SYSCALL_DEFINE* which with CONFIG_FTRACE_SYSCALLS is a bug ... Ralf From ralf@linux-mips.org Thu Aug 18 22:39:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Aug 2011 22:40:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45608 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492153Ab1HRUj6 (ORCPT ); Thu, 18 Aug 2011 22:39:58 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p7IKdv7q001875 for ; Thu, 18 Aug 2011 21:39:57 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p7IKdvWa001874 for linux-mips@linux-mips.org; Thu, 18 Aug 2011 21:39:57 +0100 Resent-From: Ralf Baechle Resent-Date: Thu, 18 Aug 2011 21:39:57 +0100 Resent-Message-ID: <20110818203957.GA1866@linux-mips.org> Resent-To: linux-mips@linux-mips.org Date: Thu, 18 Aug 2011 21:39:28 +0100 From: Ralf Baechle To: "David S. Miller" Cc: nbd@openwrt.org, florian@openwrt.org, Al Viro Subject: [PATCH] NET: Korina: Don't include Message-ID: <20110818203928.GA745@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 30904 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13656 Content-Length: 692 Lines: 25 Korina.c is a MIPS-specific SOC driver and is empty on MIPS since 2.1.7 ... Signed-off-by: Ralf Baechle --- I have another patch to remove the MIPS which will be unused after this patch, therefore I'd like to merge this patch through the MIPS tree. drivers/net/korina.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/net/korina.c b/drivers/net/korina.c index 763844c..2fc3d4a 100644 --- a/drivers/net/korina.c +++ b/drivers/net/korina.c @@ -58,7 +58,6 @@ #include #include #include -#include #include #include From mattst88@gmail.com Fri Aug 19 01:43:21 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 01:43:27 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:54513 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492164Ab1HRXnV (ORCPT ); Fri, 19 Aug 2011 01:43:21 +0200 Received: by vws8 with SMTP id 8so2396265vws.36 for ; Thu, 18 Aug 2011 16:43:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=Y2oAVUy0gpbWudJRL16dFvmyLA/UtHsGT2CF4dXf+D0=; b=xGATxosQsLJ8qyOus7N6Fb1KH6soqyfW+twIXSazCByfGSF7trEfFTWvyoNcM0NpV2 Lz9wiAy3ZZgkWz33txRUENQ/TH4PWmrjONuSS+JOZPbIv/XFDsrewOh1bxvrGgCVU4Nv fhpTr36+/8BuFAhf6ghaUJnOp/Ni7YXxMm4AE= Received: by 10.52.112.130 with SMTP id iq2mr1483411vdb.137.1313710995091; Thu, 18 Aug 2011 16:43:15 -0700 (PDT) Received: from localhost (cpe-174-109-057-197.nc.res.rr.com [174.109.57.197]) by mx.google.com with ESMTPS id eq10sm972944vdb.28.2011.08.18.16.43.13 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Aug 2011 16:43:14 -0700 (PDT) From: Matt Turner To: Jean Delvare Cc: linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck , "Maciej W. Rozycki" , Matt Turner Subject: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Date: Thu, 18 Aug 2011 19:43:11 -0400 Message-Id: <1313710991-3596-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.3.4 X-archive-position: 30905 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 12693 Lines: 432 From: Maciej W. Rozycki This is a rewrite of large parts of the driver mainly so that it uses SMBus interrupts to offload the CPU from busy-waiting on status inputs. As a part of the overhaul of the init and exit calls, all accesses to the hardware got converted to use accessory functions via an ioremap() cookie. [mattst88] Added BCM1480 interrupts and rebased minimally. Signed-off-by: Matt Turner Signed-off-by: Maciej W. Rozycki --- This is the second version of this patch that I've sent. This version fixes the problem with the ENXIO return. drivers/i2c/busses/i2c-sibyte.c | 296 +++++++++++++++++++++++++++++--------- 1 files changed, 226 insertions(+), 70 deletions(-) diff --git a/drivers/i2c/busses/i2c-sibyte.c b/drivers/i2c/busses/i2c-sibyte.c index 0fe505d..d2f1cf1 100644 --- a/drivers/i2c/busses/i2c-sibyte.c +++ b/drivers/i2c/busses/i2c-sibyte.c @@ -2,6 +2,7 @@ * Copyright (C) 2004 Steven J. Hill * Copyright (C) 2001,2002,2003 Broadcom Corporation * Copyright (C) 1995-2000 Simon G. Vogl + * Copyright (C) 2008 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -18,104 +19,164 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include +#include #include #include #include #include +#include +#include +#include +#include #include +#include #include #include +#include struct i2c_algo_sibyte_data { - void *data; /* private data */ - int bus; /* which bus */ - void *reg_base; /* CSR base */ + wait_queue_head_t wait; /* IRQ queue */ + void __iomem *csr; /* mapped CSR handle */ + phys_t base; /* physical CSR base */ + char *name; /* IRQ handler name */ + spinlock_t lock; /* atomiser */ + int irq; /* IRQ line */ + int status; /* IRQ status */ }; -/* ----- global defines ----------------------------------------------- */ -#define SMB_CSR(a,r) ((long)(a->reg_base + r)) +static irqreturn_t i2c_sibyte_interrupt(int irq, void *dev_id) +{ + struct i2c_adapter *i2c_adap = dev_id; + struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; + void __iomem *csr = adap->csr; + u8 status; + + /* + * Ugh, no way to detect the finish interrupt, + * but if busy it is obviously not one. + */ + status = __raw_readq(csr + R_SMB_STATUS); + if ((status & (M_SMB_ERROR | M_SMB_BUSY)) == M_SMB_BUSY) + return IRQ_NONE; + + /* + * Clear the error interrupt (write 1 to clear); + * the finish interrupt was cleared by the read above. + */ + __raw_writeq(status, csr + R_SMB_STATUS); + + /* Post the status. */ + spin_lock(&adap->lock); + adap->status = status & (M_SMB_ERROR_TYPE | M_SMB_ERROR | M_SMB_BUSY); + wake_up(&adap->wait); + spin_unlock(&adap->lock); + + return IRQ_HANDLED; +} -static int smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr, - unsigned short flags, char read_write, - u8 command, int size, union i2c_smbus_data * data) +static s32 i2c_sibyte_smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr, + unsigned short cflags, + char read_write, u8 command, int size, + union i2c_smbus_data *data) { struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; + void __iomem *csr = adap->csr; + unsigned long flags; int data_bytes = 0; int error; - while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) - ; + spin_lock_irqsave(&adap->lock, flags); + + if (adap->status < 0) { + error = -EIO; + goto out_unlock; + } switch (size) { case I2C_SMBUS_QUICK: - csr_out32((V_SMB_ADDR(addr) | - (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) | - V_SMB_TT_QUICKCMD), SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_ADDR(addr) | + (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) | + V_SMB_TT_QUICKCMD, + csr + R_SMB_START); break; case I2C_SMBUS_BYTE: if (read_write == I2C_SMBUS_READ) { - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE, + csr + R_SMB_START); data_bytes = 1; } else { - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE, + csr + R_SMB_START); } break; case I2C_SMBUS_BYTE_DATA: - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); if (read_write == I2C_SMBUS_READ) { - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE, + csr + R_SMB_START); data_bytes = 1; } else { - csr_out32(V_SMB_LB(data->byte), - SMB_CSR(adap, R_SMB_DATA)); - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_LB(data->byte), csr + R_SMB_DATA); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE, + csr + R_SMB_START); } break; case I2C_SMBUS_WORD_DATA: - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); if (read_write == I2C_SMBUS_READ) { - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE, + csr + R_SMB_START); data_bytes = 2; } else { - csr_out32(V_SMB_LB(data->word & 0xff), - SMB_CSR(adap, R_SMB_DATA)); - csr_out32(V_SMB_MB(data->word >> 8), - SMB_CSR(adap, R_SMB_DATA)); - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_LB(data->word & 0xff), + csr + R_SMB_DATA); + __raw_writeq(V_SMB_MB(data->word >> 8), + csr + R_SMB_DATA); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE, + csr + R_SMB_START); } break; default: - return -EOPNOTSUPP; + error = -EOPNOTSUPP; + goto out_unlock; } + mmiowb(); + __raw_readq(csr + R_SMB_START); + adap->status = -1; + + spin_unlock_irqrestore(&adap->lock, flags); - while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) - ; + wait_event_timeout(adap->wait, (adap->status >= 0), HZ); - error = csr_in32(SMB_CSR(adap, R_SMB_STATUS)); - if (error & M_SMB_ERROR) { - /* Clear error bit by writing a 1 */ - csr_out32(M_SMB_ERROR, SMB_CSR(adap, R_SMB_STATUS)); - return (error & M_SMB_ERROR_TYPE) ? -EIO : -ENXIO; + spin_lock_irqsave(&adap->lock, flags); + + if (adap->status > 0 && ((adap->status & (M_SMB_ERROR | M_SMB_ERROR_TYPE)) == M_SMB_ERROR)) { + error = -ENXIO; + goto out_unlock; + } + if (adap->status < 0 || (adap->status & (M_SMB_ERROR | M_SMB_BUSY))) { + error = -EIO; + goto out_unlock; } if (data_bytes == 1) - data->byte = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xff; + data->byte = __raw_readq(csr + R_SMB_DATA) & 0xff; if (data_bytes == 2) - data->word = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xffff; + data->word = __raw_readq(csr + R_SMB_DATA) & 0xffff; - return 0; + error = 0; + +out_unlock: + spin_unlock_irqrestore(&adap->lock, flags); + + return error; } -static u32 bit_func(struct i2c_adapter *adap) +static u32 i2c_sibyte_bit_func(struct i2c_adapter *adap) { return (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA); @@ -125,8 +186,8 @@ static u32 bit_func(struct i2c_adapter *adap) /* -----exported algorithm data: ------------------------------------- */ static const struct i2c_algorithm i2c_sibyte_algo = { - .smbus_xfer = smbus_xfer, - .functionality = bit_func, + .smbus_xfer = i2c_sibyte_smbus_xfer, + .functionality = i2c_sibyte_bit_func, }; /* @@ -135,37 +196,121 @@ static const struct i2c_algorithm i2c_sibyte_algo = { static int __init i2c_sibyte_add_bus(struct i2c_adapter *i2c_adap, int speed) { struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; + void __iomem *csr; + int err; - /* Register new adapter to i2c module... */ - i2c_adap->algo = &i2c_sibyte_algo; + adap->status = 0; + init_waitqueue_head(&adap->wait); + spin_lock_init(&adap->lock); + + csr = ioremap(adap->base, R_SMB_PEC + SMB_REGISTER_SPACING); + if (!csr) { + err = -ENOMEM; + goto out; + } + adap->csr = csr; /* Set the requested frequency. */ - csr_out32(speed, SMB_CSR(adap,R_SMB_FREQ)); - csr_out32(0, SMB_CSR(adap,R_SMB_CONTROL)); + __raw_writeq(speed, csr + R_SMB_FREQ); + + /* Clear any pending error interrupt. */ + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); + /* Disable interrupts. */ + __raw_writeq(0, csr + R_SMB_CONTROL); + mmiowb(); + __raw_readq(csr + R_SMB_CONTROL); + + err = request_irq(adap->irq, i2c_sibyte_interrupt, IRQF_SHARED, + adap->name, i2c_adap); + if (err < 0) + goto out_unmap; + + /* Enable finish and error interrupts. */ + __raw_writeq(M_SMB_FINISH_INTR | M_SMB_ERR_INTR, csr + R_SMB_CONTROL); + + /* Register new adapter to i2c module... */ + err = i2c_add_numbered_adapter(i2c_adap); + if (err < 0) + goto out_unirq; + + return 0; - return i2c_add_numbered_adapter(i2c_adap); +out_unirq: + /* Disable interrupts. */ + __raw_writeq(0, csr + R_SMB_CONTROL); + mmiowb(); + __raw_readq(csr + R_SMB_CONTROL); + + free_irq(adap->irq, i2c_adap); + + /* Clear any pending error interrupt. */ + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); +out_unmap: + iounmap(csr); +out: + return err; } +static void i2c_sibyte_remove_bus(struct i2c_adapter *i2c_adap) +{ + struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; + void __iomem *csr = adap->csr; + + i2c_del_adapter(i2c_adap); + + /* Disable interrupts. */ + __raw_writeq(0, csr + R_SMB_CONTROL); + mmiowb(); + __raw_readq(csr + R_SMB_CONTROL); -static struct i2c_algo_sibyte_data sibyte_board_data[2] = { - { NULL, 0, (void *) (CKSEG1+A_SMB_BASE(0)) }, - { NULL, 1, (void *) (CKSEG1+A_SMB_BASE(1)) } + free_irq(adap->irq, i2c_adap); + + /* Clear any pending error interrupt. */ + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); + + iounmap(csr); +} + +static struct i2c_algo_sibyte_data i2c_sibyte_board_data[2] = { +#ifdef CONFIG_SIBYTE_SB1250 + { + .name = "sb1250-smbus-0", + .base = A_SMB_0, + .irq = K_INT_SMB_0, + }, + { + .name = "sb1250-smbus-1", + .base = A_SMB_1, + .irq = K_INT_SMB_1, + } +#else + { + .name = "bcm1480-smbus-0", + .base = A_SMB_0, + .irq = K_BCM1480_INT_SMB_0, + }, + { + .name = "bcm1480-smbus-1", + .base = A_SMB_1, + .irq = K_BCM1480_INT_SMB_1, + } +#endif }; -static struct i2c_adapter sibyte_board_adapter[2] = { +static struct i2c_adapter i2c_sibyte_board_adapter[2] = { { .owner = THIS_MODULE, .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, - .algo = NULL, - .algo_data = &sibyte_board_data[0], + .algo = &i2c_sibyte_algo, + .algo_data = &i2c_sibyte_board_data[0], .nr = 0, .name = "SiByte SMBus 0", }, { .owner = THIS_MODULE, .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, - .algo = NULL, - .algo_data = &sibyte_board_data[1], + .algo = &i2c_sibyte_algo, + .algo_data = &i2c_sibyte_board_data[1], .nr = 1, .name = "SiByte SMBus 1", }, @@ -173,21 +318,32 @@ static struct i2c_adapter sibyte_board_adapter[2] = { static int __init i2c_sibyte_init(void) { + int err; + pr_info("i2c-sibyte: i2c SMBus adapter module for SiByte board\n"); - if (i2c_sibyte_add_bus(&sibyte_board_adapter[0], K_SMB_FREQ_100KHZ) < 0) - return -ENODEV; - if (i2c_sibyte_add_bus(&sibyte_board_adapter[1], - K_SMB_FREQ_400KHZ) < 0) { - i2c_del_adapter(&sibyte_board_adapter[0]); - return -ENODEV; - } + + err = i2c_sibyte_add_bus(&i2c_sibyte_board_adapter[0], + K_SMB_FREQ_100KHZ); + if (err < 0) + goto out; + + err = i2c_sibyte_add_bus(&i2c_sibyte_board_adapter[1], + K_SMB_FREQ_400KHZ); + if (err < 0) + goto out_remove; + return 0; + +out_remove: + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[0]); +out: + return err; } static void __exit i2c_sibyte_exit(void) { - i2c_del_adapter(&sibyte_board_adapter[0]); - i2c_del_adapter(&sibyte_board_adapter[1]); + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[1]); + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[0]); } module_init(i2c_sibyte_init); -- 1.7.3.4 From mattst88@gmail.com Fri Aug 19 01:45:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 01:46:02 +0200 (CEST) Received: from mail-vx0-f177.google.com ([209.85.220.177]:43004 "EHLO mail-vx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492164Ab1HRXp5 (ORCPT ); Fri, 19 Aug 2011 01:45:57 +0200 Received: by vxj2 with SMTP id 2so2641385vxj.36 for ; Thu, 18 Aug 2011 16:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=aZu46VvRSSEyzT29iFZWZTYexXx3uKhWPREInBqUOG8=; b=t6cm0AtsLOtL01CyOIm8OwF3yvwLm2x32k6bvfc2UXYe6rrhYKu40uUioNskKkv4E/ DpKVp+carzGUdN1/MSxvQXFyAuF3QcGsDoDl+isFriZGd8now9M6/mkQvRnOmkw/5PgO rYa8+0Nn4X3/kq6kO6DUVFNCRC5M24QxPknNw= Received: by 10.52.180.193 with SMTP id dq1mr1352612vdc.393.1313711151544; Thu, 18 Aug 2011 16:45:51 -0700 (PDT) Received: from localhost (cpe-174-109-057-197.nc.res.rr.com [174.109.57.197]) by mx.google.com with ESMTPS id dg6sm1520795vcb.41.2011.08.18.16.45.50 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Aug 2011 16:45:50 -0700 (PDT) From: mattst88@gmail.com To: Ralf Baechle Cc: Jean Delvare , linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Guenter Roeck , "Maciej W. Rozycki" , Matt Turner Subject: [PATCH 1/3] RTC: SWARM class device persistent clock support Date: Thu, 18 Aug 2011 19:45:46 -0400 Message-Id: <4e4da42e.06bedc0a.5ff5.4d10@mx.google.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: References: X-archive-position: 30906 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9740 Lines: 321 From: Maciej W. Rozycki This is a set of changes removing the SWARM platform driver for the M41T81 and "wiring" the class RTC driver. The Xicor clock is unaffected as we have no class driver for this device. Signed-off-by: Matt Turner Signed-off-by: Maciej W. Rozycki --- arch/mips/sibyte/swarm/Makefile | 3 +- arch/mips/sibyte/swarm/rtc_m41t81.c | 233 ----------------------------------- arch/mips/sibyte/swarm/setup.c | 14 -- 3 files changed, 1 insertions(+), 249 deletions(-) delete mode 100644 arch/mips/sibyte/swarm/rtc_m41t81.c diff --git a/arch/mips/sibyte/swarm/Makefile b/arch/mips/sibyte/swarm/Makefile index 7b45f19..8527db4 100644 --- a/arch/mips/sibyte/swarm/Makefile +++ b/arch/mips/sibyte/swarm/Makefile @@ -1,4 +1,3 @@ -obj-y := platform.o setup.o rtc_xicor1241.o \ - rtc_m41t81.o +obj-y := platform.o setup.o rtc_xicor1241.o obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c deleted file mode 100644 index b732600..0000000 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (C) 2000, 2001 Broadcom Corporation - * - * Copyright (C) 2002 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - - -/* M41T81 definitions */ - -/* - * Register bits - */ - -#define M41T81REG_SC_ST 0x80 /* stop bit */ -#define M41T81REG_HR_CB 0x40 /* century bit */ -#define M41T81REG_HR_CEB 0x80 /* century enable bit */ -#define M41T81REG_CTL_S 0x20 /* sign bit */ -#define M41T81REG_CTL_FT 0x40 /* frequency test bit */ -#define M41T81REG_CTL_OUT 0x80 /* output level */ -#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */ -#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */ -#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */ -#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */ -#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */ -#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */ -#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */ -#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */ -#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */ -#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */ -#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */ -#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */ -#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */ -#define M41T81REG_AHR_HT 0x40 /* halt update bit */ -#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */ -#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */ -#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */ -#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */ -#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */ -#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */ -#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */ -#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */ - - -/* - * Register numbers - */ - -#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */ -#define M41T81REG_SC 0x01 /* seconds */ -#define M41T81REG_MN 0x02 /* minute */ -#define M41T81REG_HR 0x03 /* hour/century */ -#define M41T81REG_DY 0x04 /* day of week */ -#define M41T81REG_DT 0x05 /* date of month */ -#define M41T81REG_MO 0x06 /* month */ -#define M41T81REG_YR 0x07 /* year */ -#define M41T81REG_CTL 0x08 /* control */ -#define M41T81REG_WD 0x09 /* watchdog */ -#define M41T81REG_AMO 0x0A /* alarm: month */ -#define M41T81REG_ADT 0x0B /* alarm: date */ -#define M41T81REG_AHR 0x0C /* alarm: hour */ -#define M41T81REG_AMN 0x0D /* alarm: minute */ -#define M41T81REG_ASC 0x0E /* alarm: second */ -#define M41T81REG_FLG 0x0F /* flags */ -#define M41T81REG_SQW 0x13 /* square wave register */ - -#define M41T81_CCR_ADDRESS 0x68 - -#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) - -static int m41t81_read(uint8_t addr) -{ - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { - /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); - return -1; - } - - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); -} - -static int m41t81_write(uint8_t addr, int b) -{ - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); - __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { - /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); - return -1; - } - - /* read the same byte again to make sure it is written */ - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - return 0; -} - -int m41t81_set_time(unsigned long t) -{ - struct rtc_time tm; - unsigned long flags; - - /* Note we don't care about the century */ - rtc_time_to_tm(t, &tm); - - /* - * Note the write order matters as it ensures the correctness. - * When we write sec, 10th sec is clear. It is reasonable to - * believe we should finish writing min within a second. - */ - - spin_lock_irqsave(&rtc_lock, flags); - tm.tm_sec = bin2bcd(tm.tm_sec); - m41t81_write(M41T81REG_SC, tm.tm_sec); - - tm.tm_min = bin2bcd(tm.tm_min); - m41t81_write(M41T81REG_MN, tm.tm_min); - - tm.tm_hour = bin2bcd(tm.tm_hour); - tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0); - m41t81_write(M41T81REG_HR, tm.tm_hour); - - /* tm_wday starts from 0 to 6 */ - if (tm.tm_wday == 0) tm.tm_wday = 7; - tm.tm_wday = bin2bcd(tm.tm_wday); - m41t81_write(M41T81REG_DY, tm.tm_wday); - - tm.tm_mday = bin2bcd(tm.tm_mday); - m41t81_write(M41T81REG_DT, tm.tm_mday); - - /* tm_mon starts from 0, *ick* */ - tm.tm_mon ++; - tm.tm_mon = bin2bcd(tm.tm_mon); - m41t81_write(M41T81REG_MO, tm.tm_mon); - - /* we don't do century, everything is beyond 2000 */ - tm.tm_year %= 100; - tm.tm_year = bin2bcd(tm.tm_year); - m41t81_write(M41T81REG_YR, tm.tm_year); - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -unsigned long m41t81_get_time(void) -{ - unsigned int year, mon, day, hour, min, sec; - unsigned long flags; - - /* - * min is valid if two reads of sec are the same. - */ - for (;;) { - spin_lock_irqsave(&rtc_lock, flags); - sec = m41t81_read(M41T81REG_SC); - min = m41t81_read(M41T81REG_MN); - if (sec == m41t81_read(M41T81REG_SC)) break; - spin_unlock_irqrestore(&rtc_lock, flags); - } - hour = m41t81_read(M41T81REG_HR) & 0x3f; - day = m41t81_read(M41T81REG_DT); - mon = m41t81_read(M41T81REG_MO); - year = m41t81_read(M41T81REG_YR); - spin_unlock_irqrestore(&rtc_lock, flags); - - sec = bcd2bin(sec); - min = bcd2bin(min); - hour = bcd2bin(hour); - day = bcd2bin(day); - mon = bcd2bin(mon); - year = bcd2bin(year); - - year += 2000; - - return mktime(year, mon, day, hour, min, sec); -} - -int m41t81_probe(void) -{ - unsigned int tmp; - - /* enable chip if it is not enabled yet */ - tmp = m41t81_read(M41T81REG_SC); - m41t81_write(M41T81REG_SC, tmp & 0x7f); - - return (m41t81_read(M41T81REG_SC) != -1); -} diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 41707a2..3cd0d27 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -60,10 +60,6 @@ extern int xicor_probe(void); extern int xicor_set_time(unsigned long); extern unsigned long xicor_get_time(void); -extern int m41t81_probe(void); -extern int m41t81_set_time(unsigned long); -extern unsigned long m41t81_get_time(void); - const char *get_system_type(void) { return "SiByte " SIBYTE_BOARD_NAME; @@ -82,7 +78,6 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup) enum swarm_rtc_type { RTC_NONE, RTC_XICOR, - RTC_M41T81, }; enum swarm_rtc_type swarm_rtc_type; @@ -96,10 +91,6 @@ void read_persistent_clock(struct timespec *ts) sec = xicor_get_time(); break; - case RTC_M41T81: - sec = m41t81_get_time(); - break; - case RTC_NONE: default: sec = mktime(2000, 1, 1, 0, 0, 0); @@ -115,9 +106,6 @@ int rtc_mips_set_time(unsigned long sec) case RTC_XICOR: return xicor_set_time(sec); - case RTC_M41T81: - return m41t81_set_time(sec); - case RTC_NONE: default: return -1; @@ -140,8 +128,6 @@ void __init plat_mem_setup(void) if (xicor_probe()) swarm_rtc_type = RTC_XICOR; - if (m41t81_probe()) - swarm_rtc_type = RTC_M41T81; #ifdef CONFIG_VT screen_info = (struct screen_info) { -- 1.7.3.4 From mattst88@gmail.com Fri Aug 19 01:45:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 01:46:28 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:58413 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492167Ab1HRXp7 (ORCPT ); Fri, 19 Aug 2011 01:45:59 +0200 Received: by vws8 with SMTP id 8so2397861vws.36 for ; Thu, 18 Aug 2011 16:45:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=kgEts75MMKOGBSP/apxXAoQe/2nDAxGnsNb+ZZmbKKk=; b=h0aB4Wppyjt8bohGN/SEFR0GCcUdZ5gBRcEFdT6IXQAQeduO8DwgaT7Rcjm5PKY0Fa IkwgJd3M99EMLfADw2JmTHqgzy+fQDA13oc1Jw/doepvUN6RPpQthjhSbepf28tgSgfN aaug/Wp8YfUDsakCRxd5KphCuFUxVzWt4VV2o= Received: by 10.52.69.106 with SMTP id d10mr1330049vdu.146.1313711153553; Thu, 18 Aug 2011 16:45:53 -0700 (PDT) Received: from localhost (cpe-174-109-057-197.nc.res.rr.com [174.109.57.197]) by mx.google.com with ESMTPS id es7sm2420686vdb.30.2011.08.18.16.45.52 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Aug 2011 16:45:52 -0700 (PDT) From: mattst88@gmail.com To: Ralf Baechle Cc: Jean Delvare , linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Guenter Roeck , "Maciej W. Rozycki" , Matt Turner Subject: [PATCH 2/3] RTC: SMBus support for the M41T80, etc. driver Date: Thu, 18 Aug 2011 19:45:47 -0400 Message-Id: <4e4da430.c763340a.7573.ffff9fe6@mx.google.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: References: X-archive-position: 30907 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 11707 Lines: 401 From: Maciej W. Rozycki The BCM1250A SOC which is used on the SWARM board utilising an M41T81 chip only supports pure I2C in the raw bit-banged mode. Nobody sane really wants to use it unless absolutely necessary and the M41T80, etc. chips work just fine with an SMBus adapter which is what the standard mode of operation of the BCM1250A. The only drawback of byte accesses with the M41T80 is the chip only latches clock data registers for the duration of an I2C transaction which works fine with a block transfers, but not byte-wise accesses. The driver currently requires an I2C adapter providing both SMBus and raw I2C access. This is a set of changes to make it work with any SMBus adapter providing at least read byte and write byte protocols. Additionally, if a given SMBus adapter supports I2C block read and/or write protocols (a common extension beyond the SMBus spec), they are used as well. The problem of unlatched clock data if SMBus byte transactions are used is resolved in the standard way. For raw I2C controllers this functionality is provided by the I2C core as SMBus emulation in a transparent way. Signed-off-by: Matt Turner Signed-off-by: Maciej W. Rozycki --- drivers/rtc/rtc-m41t80.c | 251 ++++++++++++++++++++-------------------------- 1 files changed, 107 insertions(+), 144 deletions(-) diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c index eda128f..004520a 100644 --- a/drivers/rtc/rtc-m41t80.c +++ b/drivers/rtc/rtc-m41t80.c @@ -6,6 +6,7 @@ * Based on m41t00.c by Mark A. Greer * * 2006 (c) mycable GmbH + * Copyright (c) 2008 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -38,6 +39,8 @@ #define M41T80_REG_DAY 5 #define M41T80_REG_MON 6 #define M41T80_REG_YEAR 7 +#define M41T80_REG_CONTROL 8 +#define M41T80_REG_WATCHDOG 9 #define M41T80_REG_ALARM_MON 0xa #define M41T80_REG_ALARM_DAY 0xb #define M41T80_REG_ALARM_HOUR 0xc @@ -66,7 +69,7 @@ #define M41T80_FEATURE_WD (1 << 3) /* Extra watchdog resolution */ #define M41T80_FEATURE_SQ_ALT (1 << 4) /* RSx bits are in reg 4 */ -#define DRV_VERSION "0.05" +#define DRV_VERSION "0.06" static DEFINE_MUTEX(m41t80_rtc_mutex); static const struct i2c_device_id m41t80_id[] = { @@ -89,31 +92,89 @@ struct m41t80_data { struct rtc_device *rtc; }; -static int m41t80_get_datetime(struct i2c_client *client, - struct rtc_time *tm) + +static int m41t80_write_block_data(struct i2c_client *client, + u8 reg, u8 num, u8 *buf) { - u8 buf[M41T80_DATETIME_REG_SIZE], dt_addr[1] = { M41T80_REG_SEC }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, - .buf = buf + M41T80_REG_SEC, - }, - }; + int i, rc; + + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) { + i = i2c_smbus_write_i2c_block_data(client, reg, num, buf); + } else { + for (i = 0; i < num; i++) { + rc = i2c_smbus_write_byte_data(client, reg + i, + buf[i]); + if (rc < 0) { + i = rc; + goto out; + } + } + } +out: + return i; +} - if (i2c_transfer(client->adapter, msgs, 2) < 0) { - dev_err(&client->dev, "read error\n"); - return -EIO; +static int m41t80_read_block_data(struct i2c_client *client, + u8 reg, u8 num, u8 *buf) +{ + int i, rc; + + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + i = i2c_smbus_read_i2c_block_data(client, reg, num, buf); + } else { + for (i = 0; i < num; i++) { + rc = i2c_smbus_read_byte_data(client, reg + i); + if (rc < 0) { + i = rc; + goto out; + } + buf[i] = rc; + } } +out: + return i; +} + +static int m41t80_get_datetime(struct i2c_client *client, struct rtc_time *tm) +{ + u8 buf[M41T80_DATETIME_REG_SIZE]; + int loops = 2; + int sec0, sec1; + + /* + * Time registers are latched by this chip if an I2C block + * transfer is used, but with SMBus-style byte accesses + * this is not the case, so check seconds for a wraparound. + */ + do { + if (m41t80_read_block_data(client, M41T80_REG_SEC, + M41T80_DATETIME_REG_SIZE - + M41T80_REG_SEC, + buf + M41T80_REG_SEC) < 0) { + dev_err(&client->dev, "read error\n"); + return -EIO; + } + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + sec1 = buf[M41T80_REG_SEC]; + break; + } + + sec0 = buf[M41T80_REG_SEC]; + sec1 = i2c_smbus_read_byte_data(client, M41T80_REG_SEC); + if (sec1 < 0) { + dev_err(&client->dev, "read error\n"); + return -EIO; + } + + sec0 = bcd2bin(sec0 & 0x7f); + sec1 = bcd2bin(sec1 & 0x7f); + } while (sec1 < sec0 && --loops); - tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f); + tm->tm_sec = sec1; + tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f); tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f); @@ -128,39 +189,16 @@ static int m41t80_get_datetime(struct i2c_client *client, /* Sets the given date and time to the real time clock. */ static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm) { - u8 wbuf[1 + M41T80_DATETIME_REG_SIZE]; - u8 *buf = &wbuf[1]; - u8 dt_addr[1] = { M41T80_REG_SEC }; - struct i2c_msg msgs_in[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, - .buf = buf + M41T80_REG_SEC, - }, - }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1 + M41T80_DATETIME_REG_SIZE, - .buf = wbuf, - }, - }; + u8 buf[M41T80_DATETIME_REG_SIZE]; /* Read current reg values into buf[1..7] */ - if (i2c_transfer(client->adapter, msgs_in, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_SEC, + M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, + buf + M41T80_REG_SEC) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } - wbuf[0] = 0; /* offset into rtc's regs */ /* Merge time-data and register flags into buf[0..7] */ buf[M41T80_REG_SSEC] = 0; buf[M41T80_REG_SEC] = @@ -177,8 +215,8 @@ static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm) bin2bcd(tm->tm_mon + 1) | (buf[M41T80_REG_MON] & ~0x1f); /* assume 20YY not 19YY */ buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year % 100); - - if (i2c_transfer(client->adapter, msgs, 1) != 1) { + if (m41t80_write_block_data(client, M41T80_REG_SSEC, + M41T80_DATETIME_REG_SIZE, buf) < 0) { dev_err(&client->dev, "write error\n"); return -EIO; } @@ -238,34 +276,11 @@ err: static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) { struct i2c_client *client = to_i2c_client(dev); - u8 wbuf[1 + M41T80_ALARM_REG_SIZE]; - u8 *buf = &wbuf[1]; + u8 buf[M41T80_ALARM_REG_SIZE]; u8 *reg = buf - M41T80_REG_ALARM_MON; - u8 dt_addr[1] = { M41T80_REG_ALARM_MON }; - struct i2c_msg msgs_in[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_ALARM_REG_SIZE, - .buf = buf, - }, - }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1 + M41T80_ALARM_REG_SIZE, - .buf = wbuf, - }, - }; - if (i2c_transfer(client->adapter, msgs_in, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE, buf) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } @@ -275,7 +290,6 @@ static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) reg[M41T80_REG_ALARM_MIN] = 0; reg[M41T80_REG_ALARM_SEC] = 0; - wbuf[0] = M41T80_REG_ALARM_MON; /* offset into rtc's regs */ reg[M41T80_REG_ALARM_SEC] |= t->time.tm_sec >= 0 ? bin2bcd(t->time.tm_sec) : 0x80; reg[M41T80_REG_ALARM_MIN] |= t->time.tm_min >= 0 ? @@ -289,7 +303,8 @@ static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) else reg[M41T80_REG_ALARM_DAY] |= 0x40; - if (i2c_transfer(client->adapter, msgs, 1) != 1) { + if (m41t80_write_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE, buf) < 0) { dev_err(&client->dev, "write error\n"); return -EIO; } @@ -309,24 +324,10 @@ static int m41t80_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *t) { struct i2c_client *client = to_i2c_client(dev); u8 buf[M41T80_ALARM_REG_SIZE + 1]; /* all alarm regs and flags */ - u8 dt_addr[1] = { M41T80_REG_ALARM_MON }; u8 *reg = buf - M41T80_REG_ALARM_MON; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_ALARM_REG_SIZE + 1, - .buf = buf, - }, - }; - if (i2c_transfer(client->adapter, msgs, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE + 1, buf) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } @@ -499,26 +500,16 @@ static int boot_flag; */ static void wdt_ping(void) { - unsigned char i2c_data[2]; - struct i2c_msg msgs1[1] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 2, - .buf = i2c_data, - }, - }; - struct m41t80_data *clientdata = i2c_get_clientdata(save_client); + u8 wdt = 0x80; /* WDS = 1 (0x80) */ - i2c_data[0] = 0x09; /* watchdog register */ + struct m41t80_data *clientdata = i2c_get_clientdata(save_client); if (wdt_margin > 31) - i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */ + /* mulitplier = WD_TIMO / 4, resolution = 4s (0x3) */ + wdt |= (wdt_margin & 0xfc) | 0x3; else - /* - * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02) - */ - i2c_data[1] = wdt_margin<<2 | 0x82; + /* mulitplier = WD_TIMO, resolution = 1s (0x2) */ + wdt |= wdt_margin << 2 | 0x2; /* * M41T65 has three bits for watchdog resolution. Don't set bit 7, as @@ -527,7 +518,7 @@ static void wdt_ping(void) if (clientdata->features & M41T80_FEATURE_WD) i2c_data[1] &= ~M41T80_WATCHDOG_RB2; - i2c_transfer(save_client->adapter, msgs1, 1); + i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, wdt); } /** @@ -537,36 +528,8 @@ static void wdt_ping(void) */ static void wdt_disable(void) { - unsigned char i2c_data[2], i2c_buf[0x10]; - struct i2c_msg msgs0[2] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 1, - .buf = i2c_data, - }, - { - .addr = save_client->addr, - .flags = I2C_M_RD, - .len = 1, - .buf = i2c_buf, - }, - }; - struct i2c_msg msgs1[1] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 2, - .buf = i2c_data, - }, - }; - - i2c_data[0] = 0x09; - i2c_transfer(save_client->adapter, msgs0, 2); - - i2c_data[0] = 0x09; - i2c_data[1] = 0x00; - i2c_transfer(save_client->adapter, msgs1, 1); + i2c_smbus_read_byte_data(save_client, M41T80_REG_WATCHDOG); + i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, 0); } /** @@ -768,8 +731,8 @@ static int m41t80_probe(struct i2c_client *client, struct rtc_time tm; struct m41t80_data *clientdata = NULL; - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C - | I2C_FUNC_SMBUS_BYTE_DATA)) { + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA)) { rc = -ENODEV; goto exit; } -- 1.7.3.4 From mattst88@gmail.com Fri Aug 19 01:46:38 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 01:46:52 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:32768 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492164Ab1HRXqi (ORCPT ); Fri, 19 Aug 2011 01:46:38 +0200 Received: by vws8 with SMTP id 8so2398190vws.36 for ; Thu, 18 Aug 2011 16:46:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=Sja2tKKPkvVZNEHIAl4jnyBxyCHzQnsrnB5lBbP7lpU=; b=GNyJAzeccgDk0rXjlgowy0LB6wVE/kUimBeD/Op59zRUTlyw2AeEfsoXi7Yew5Yy4W O9cL7oOPZCT890JMb3LE+4qmoF39/5t57oBY42vByr54U1MZiUOuxZ7ZlKcrbvTKbrD9 Sx//cXfYpN4qtNZJTdivlaVxCGInbcQIlcPak= Received: by 10.52.67.146 with SMTP id n18mr1386153vdt.464.1313711192224; Thu, 18 Aug 2011 16:46:32 -0700 (PDT) Received: from localhost (cpe-174-109-057-197.nc.res.rr.com [174.109.57.197]) by mx.google.com with ESMTPS id e1sm1523258vcz.7.2011.08.18.16.46.31 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Aug 2011 16:46:31 -0700 (PDT) From: Matt Turner To: Ralf Baechle Cc: Jean Delvare , linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, lm-sensors@lm-sensors.org, Guenter Roeck , Matt Turner Subject: [PATCH 3/3] MIPS: register hwmon on SWARM Date: Thu, 18 Aug 2011 19:46:25 -0400 Message-Id: <1313711185-3677-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.3.4 X-archive-position: 30908 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 889 Lines: 33 Signed-off-by: Matt Turner --- arch/mips/sibyte/swarm/swarm-i2c.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/mips/sibyte/swarm/swarm-i2c.c b/arch/mips/sibyte/swarm/swarm-i2c.c index 0625050..a6e417f 100644 --- a/arch/mips/sibyte/swarm/swarm-i2c.c +++ b/arch/mips/sibyte/swarm/swarm-i2c.c @@ -13,6 +13,11 @@ #include #include +static struct i2c_board_info swarm_i2c_info0[] __initdata = { + { + I2C_BOARD_INFO("lm90", 0x2a), + }, +}; static struct i2c_board_info swarm_i2c_info1[] __initdata = { { @@ -24,6 +29,8 @@ static int __init swarm_i2c_init(void) { int err; + err = i2c_register_board_info(0, swarm_i2c_info0, + ARRAY_SIZE(swarm_i2c_info0)); err = i2c_register_board_info(1, swarm_i2c_info1, ARRAY_SIZE(swarm_i2c_info1)); if (err < 0) -- 1.7.3.4 From jason.kwon@ericsson.com Fri Aug 19 02:10:11 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 02:10:15 +0200 (CEST) Received: from imr3.ericy.com ([198.24.6.13]:56892 "EHLO imr3.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492164Ab1HSAKL (ORCPT ); Fri, 19 Aug 2011 02:10:11 +0200 Received: from eusaamw0711.eamcs.ericsson.se ([147.117.20.178]) by imr3.ericy.com (8.13.8/8.13.8) with ESMTP id p7J0A4Y8011333 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL) for ; Thu, 18 Aug 2011 19:10:04 -0500 Received: from [IPv6:::1] (147.117.20.214) by smtps-am.internal.ericsson.com (147.117.20.178) with Microsoft SMTP Server (TLS) id 8.3.137.0; Thu, 18 Aug 2011 20:10:04 -0400 Message-ID: <4E4DA9DA.60305@ericsson.com> Date: Thu, 18 Aug 2011 17:10:02 -0700 From: Jason Kwon User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.18) Gecko/20110617 Thunderbird/3.1.11 MIME-Version: 1.0 To: Subject: Problems booting 3.0.3 kernel on Octeon CN58XX board Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 30909 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jason.kwon@ericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13765 Content-Length: 4342 Lines: 100 Attempting to boot a 3.0.3 kernel on a CN58XX board produced the following oops: CPU 4 Unable to handle kernel paging request at virtual address 0000000001c00000, epc == ffffffff811aa9f4, ra == ffffffff811aaa98 Oops[#1]: Cpu 4 $ 0 : 0000000000000000 0000000010008ce0 ffffffff821d2b80 0000000001c00000 $ 4 : 0000000001c00038 000000000000017c 0000000000080000 0000000000080072 $ 8 : 0000000000000008 0000000000000002 0000000000000003 a800000002284520 $12 : 0000000000000002 ffffffff8186ee80 ffffffffffffff80 0000000000000030 $16 : 0000000000080072 0000000000000001 0000000001bfa8f0 0000000001bfa928 $20 : a800000003aff8f0 00000000000f0000 ffffffff8186ee80 ffffffff821d2a80 $24 : 0000000000000001 0000000000000038 $28 : a80000041fc48000 a80000041fc4bd90 fffffffffffffffc ffffffff811aaa98 Hi : 0000000000000000 Lo : 0000000000000000 epc : ffffffff811aa9f4 setup_per_zone_wmarks+0x19c/0x2d8 Not tainted ra : ffffffff811aaa98 setup_per_zone_wmarks+0x240/0x2d8 Status: 10008ce2 KX SX UX KERNEL EXL Cause : 40808408 BadVA : 0000000001c00000 PrId : 000d0301 (Cavium Octeon+) Modules linked in: Process swapper (pid: 1, threadinfo=a80000041fc48000, task=a80000041fc44038, tls=0000000000000000) Stack : 0000000000000000 000000000006f75d ffffffff8186eec0 0000000000000001 0000000000000547 ffffffff81825598 ffffffff81a80000 ffffffff818b3e68 ffffffff818a40ac 0000000000000000 ffffffff81a80000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ffffffff818a40f0 ffffffff81a80000 ffffffff81100438 ffffffff818b4198 ffffffff818b3e68 ffffffff818b46c8 0000000000000000 0000000000000000 ffffffff818721d0 0000000000000000 0000000000000000 0000000000000000 ffffffff81109bb0 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ffffffff818720f8 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ... Call Trace: [] setup_per_zone_wmarks+0x19c/0x2d8 [] init_per_zone_wmark_min+0x44/0xe0 [] do_one_initcall+0x38/0x160 [] kernel_init+0xd8/0x178 [] kernel_thread_helper+0x10/0x18 Code: 007e1824 0064182d 64840038 c84afff5 64c60001 66020200 66737000 1220000c All code ======== 0: 24 18 and $0x18,%al 2: 7e 00 jle 0x4 4: 2d 18 64 00 38 sub $0x38006418,%eax 9: 00 84 64 00 00 62 dc add %al,-0x239e0000(%rsp,%riz,2) 10: f5 cmc 11: ff 4a c8 decl -0x38(%rdx) 14: 01 00 add %eax,(%rax) 16: c6 (bad) 17: 64 00 02 add %al,%fs:(%rdx) 1a: 02 66 00 add 0x0(%rsi),%ah 1d: 70 73 jo 0x92 1f: 66 data16 20: 0c 00 or $0x0,%al 22: 20 12 and %dl,(%rdx) Code starting with the faulting instruction =========================================== 0: 00 00 add %al,(%rax) 2: 62 (bad) 3: dc f5 fdiv %st,%st(5) 5: ff 4a c8 decl -0x38(%rdx) 8: 01 00 add %eax,(%rax) a: c6 (bad) b: 64 00 02 add %al,%fs:(%rdx) e: 02 66 00 add 0x0(%rsi),%ah 11: 70 73 jo 0x86 13: 66 data16 14: 0c 00 or $0x0,%al 16: 20 12 and %dl,(%rdx) (gdb) list *setup_per_zone_wmarks+0x19c 0x811aa9f4 is in setup_per_zone_wmarks (include/asm-generic/bitops/non-atomic.h:105). 100 * @nr: bit number to test 101 * @addr: Address to start counting from 102 */ 103 static inline int test_bit(int nr, const volatile unsigned long *addr) 104 { 105 return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); 106 } 107 108 #endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */ (gdb) I am able to boot 2.6.39.3 on this board. Is this a known issue? Thanks, Jason From mattst88@gmail.com Fri Aug 19 02:11:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 02:11:34 +0200 (CEST) Received: from mail-qy0-f177.google.com ([209.85.216.177]:65081 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492164Ab1HSALY (ORCPT ); Fri, 19 Aug 2011 02:11:24 +0200 Received: by qyk2 with SMTP id 2so841529qyk.15 for ; Thu, 18 Aug 2011 17:11:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=N181toF5lvNC0+skRYAJSlQoIkpwmAVbK136IzaVw/o=; b=ItNG4vvMCJA79kmAUQ8c8M5vmIXreYyGqMPHEvu1M1kwsH0FAcdH6taRsIhhdaOpRw W6/5A1oH2MMyhNZHiWVICem7tYQ5oLC2NZWBdjUoCZTp8ewaEi7+TboPiVsfbAiAJjRk O5ku2KNsVaG5kRs4lfutEfZFLO0OiHSdRhCGc= Received: by 10.224.181.72 with SMTP id bx8mr1187867qab.274.1313712677532; Thu, 18 Aug 2011 17:11:17 -0700 (PDT) Received: from localhost (cpe-174-109-057-197.nc.res.rr.com [174.109.57.197]) by mx.google.com with ESMTPS id fl1sm3128722qab.13.2011.08.18.17.11.16 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Aug 2011 17:11:16 -0700 (PDT) From: mattst88@gmail.com To: Alessandro Zummo Cc: rtc-linux@googlegroups.com, linux-mips@linux-mips.org, linux-i2c@vger.kernel.org, Ralf Baechle , Guenter Roeck , "Maciej W. Rozycki" , Matt Turner Subject: [PATCH 2/3] RTC: SMBus support for the M41T80, etc. driver Date: Thu, 18 Aug 2011 20:11:14 -0400 Message-Id: <4e4daa24.41cce00a.6802.5931@mx.google.com> X-Mailer: git-send-email 1.7.3.4 X-archive-position: 30910 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 11803 Lines: 404 From: Maciej W. Rozycki The BCM1250A SOC which is used on the SWARM board utilising an M41T81 chip only supports pure I2C in the raw bit-banged mode. Nobody sane really wants to use it unless absolutely necessary and the M41T80, etc. chips work just fine with an SMBus adapter which is what the standard mode of operation of the BCM1250A. The only drawback of byte accesses with the M41T80 is the chip only latches clock data registers for the duration of an I2C transaction which works fine with a block transfers, but not byte-wise accesses. The driver currently requires an I2C adapter providing both SMBus and raw I2C access. This is a set of changes to make it work with any SMBus adapter providing at least read byte and write byte protocols. Additionally, if a given SMBus adapter supports I2C block read and/or write protocols (a common extension beyond the SMBus spec), they are used as well. The problem of unlatched clock data if SMBus byte transactions are used is resolved in the standard way. For raw I2C controllers this functionality is provided by the I2C core as SMBus emulation in a transparent way. Signed-off-by: Matt Turner Signed-off-by: Maciej W. Rozycki --- Sorry for sending this twice. I realized that I didn't send it to the rtc list the first time. drivers/rtc/rtc-m41t80.c | 251 ++++++++++++++++++++-------------------------- 1 files changed, 107 insertions(+), 144 deletions(-) diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c index eda128f..004520a 100644 --- a/drivers/rtc/rtc-m41t80.c +++ b/drivers/rtc/rtc-m41t80.c @@ -6,6 +6,7 @@ * Based on m41t00.c by Mark A. Greer * * 2006 (c) mycable GmbH + * Copyright (c) 2008 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -38,6 +39,8 @@ #define M41T80_REG_DAY 5 #define M41T80_REG_MON 6 #define M41T80_REG_YEAR 7 +#define M41T80_REG_CONTROL 8 +#define M41T80_REG_WATCHDOG 9 #define M41T80_REG_ALARM_MON 0xa #define M41T80_REG_ALARM_DAY 0xb #define M41T80_REG_ALARM_HOUR 0xc @@ -66,7 +69,7 @@ #define M41T80_FEATURE_WD (1 << 3) /* Extra watchdog resolution */ #define M41T80_FEATURE_SQ_ALT (1 << 4) /* RSx bits are in reg 4 */ -#define DRV_VERSION "0.05" +#define DRV_VERSION "0.06" static DEFINE_MUTEX(m41t80_rtc_mutex); static const struct i2c_device_id m41t80_id[] = { @@ -89,31 +92,89 @@ struct m41t80_data { struct rtc_device *rtc; }; -static int m41t80_get_datetime(struct i2c_client *client, - struct rtc_time *tm) + +static int m41t80_write_block_data(struct i2c_client *client, + u8 reg, u8 num, u8 *buf) { - u8 buf[M41T80_DATETIME_REG_SIZE], dt_addr[1] = { M41T80_REG_SEC }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, - .buf = buf + M41T80_REG_SEC, - }, - }; + int i, rc; + + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) { + i = i2c_smbus_write_i2c_block_data(client, reg, num, buf); + } else { + for (i = 0; i < num; i++) { + rc = i2c_smbus_write_byte_data(client, reg + i, + buf[i]); + if (rc < 0) { + i = rc; + goto out; + } + } + } +out: + return i; +} - if (i2c_transfer(client->adapter, msgs, 2) < 0) { - dev_err(&client->dev, "read error\n"); - return -EIO; +static int m41t80_read_block_data(struct i2c_client *client, + u8 reg, u8 num, u8 *buf) +{ + int i, rc; + + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + i = i2c_smbus_read_i2c_block_data(client, reg, num, buf); + } else { + for (i = 0; i < num; i++) { + rc = i2c_smbus_read_byte_data(client, reg + i); + if (rc < 0) { + i = rc; + goto out; + } + buf[i] = rc; + } } +out: + return i; +} + +static int m41t80_get_datetime(struct i2c_client *client, struct rtc_time *tm) +{ + u8 buf[M41T80_DATETIME_REG_SIZE]; + int loops = 2; + int sec0, sec1; + + /* + * Time registers are latched by this chip if an I2C block + * transfer is used, but with SMBus-style byte accesses + * this is not the case, so check seconds for a wraparound. + */ + do { + if (m41t80_read_block_data(client, M41T80_REG_SEC, + M41T80_DATETIME_REG_SIZE - + M41T80_REG_SEC, + buf + M41T80_REG_SEC) < 0) { + dev_err(&client->dev, "read error\n"); + return -EIO; + } + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + sec1 = buf[M41T80_REG_SEC]; + break; + } + + sec0 = buf[M41T80_REG_SEC]; + sec1 = i2c_smbus_read_byte_data(client, M41T80_REG_SEC); + if (sec1 < 0) { + dev_err(&client->dev, "read error\n"); + return -EIO; + } + + sec0 = bcd2bin(sec0 & 0x7f); + sec1 = bcd2bin(sec1 & 0x7f); + } while (sec1 < sec0 && --loops); - tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f); + tm->tm_sec = sec1; + tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f); tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f); @@ -128,39 +189,16 @@ static int m41t80_get_datetime(struct i2c_client *client, /* Sets the given date and time to the real time clock. */ static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm) { - u8 wbuf[1 + M41T80_DATETIME_REG_SIZE]; - u8 *buf = &wbuf[1]; - u8 dt_addr[1] = { M41T80_REG_SEC }; - struct i2c_msg msgs_in[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, - .buf = buf + M41T80_REG_SEC, - }, - }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1 + M41T80_DATETIME_REG_SIZE, - .buf = wbuf, - }, - }; + u8 buf[M41T80_DATETIME_REG_SIZE]; /* Read current reg values into buf[1..7] */ - if (i2c_transfer(client->adapter, msgs_in, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_SEC, + M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, + buf + M41T80_REG_SEC) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } - wbuf[0] = 0; /* offset into rtc's regs */ /* Merge time-data and register flags into buf[0..7] */ buf[M41T80_REG_SSEC] = 0; buf[M41T80_REG_SEC] = @@ -177,8 +215,8 @@ static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm) bin2bcd(tm->tm_mon + 1) | (buf[M41T80_REG_MON] & ~0x1f); /* assume 20YY not 19YY */ buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year % 100); - - if (i2c_transfer(client->adapter, msgs, 1) != 1) { + if (m41t80_write_block_data(client, M41T80_REG_SSEC, + M41T80_DATETIME_REG_SIZE, buf) < 0) { dev_err(&client->dev, "write error\n"); return -EIO; } @@ -238,34 +276,11 @@ err: static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) { struct i2c_client *client = to_i2c_client(dev); - u8 wbuf[1 + M41T80_ALARM_REG_SIZE]; - u8 *buf = &wbuf[1]; + u8 buf[M41T80_ALARM_REG_SIZE]; u8 *reg = buf - M41T80_REG_ALARM_MON; - u8 dt_addr[1] = { M41T80_REG_ALARM_MON }; - struct i2c_msg msgs_in[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_ALARM_REG_SIZE, - .buf = buf, - }, - }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1 + M41T80_ALARM_REG_SIZE, - .buf = wbuf, - }, - }; - if (i2c_transfer(client->adapter, msgs_in, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE, buf) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } @@ -275,7 +290,6 @@ static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) reg[M41T80_REG_ALARM_MIN] = 0; reg[M41T80_REG_ALARM_SEC] = 0; - wbuf[0] = M41T80_REG_ALARM_MON; /* offset into rtc's regs */ reg[M41T80_REG_ALARM_SEC] |= t->time.tm_sec >= 0 ? bin2bcd(t->time.tm_sec) : 0x80; reg[M41T80_REG_ALARM_MIN] |= t->time.tm_min >= 0 ? @@ -289,7 +303,8 @@ static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) else reg[M41T80_REG_ALARM_DAY] |= 0x40; - if (i2c_transfer(client->adapter, msgs, 1) != 1) { + if (m41t80_write_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE, buf) < 0) { dev_err(&client->dev, "write error\n"); return -EIO; } @@ -309,24 +324,10 @@ static int m41t80_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *t) { struct i2c_client *client = to_i2c_client(dev); u8 buf[M41T80_ALARM_REG_SIZE + 1]; /* all alarm regs and flags */ - u8 dt_addr[1] = { M41T80_REG_ALARM_MON }; u8 *reg = buf - M41T80_REG_ALARM_MON; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_ALARM_REG_SIZE + 1, - .buf = buf, - }, - }; - if (i2c_transfer(client->adapter, msgs, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE + 1, buf) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } @@ -499,26 +500,16 @@ static int boot_flag; */ static void wdt_ping(void) { - unsigned char i2c_data[2]; - struct i2c_msg msgs1[1] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 2, - .buf = i2c_data, - }, - }; - struct m41t80_data *clientdata = i2c_get_clientdata(save_client); + u8 wdt = 0x80; /* WDS = 1 (0x80) */ - i2c_data[0] = 0x09; /* watchdog register */ + struct m41t80_data *clientdata = i2c_get_clientdata(save_client); if (wdt_margin > 31) - i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */ + /* mulitplier = WD_TIMO / 4, resolution = 4s (0x3) */ + wdt |= (wdt_margin & 0xfc) | 0x3; else - /* - * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02) - */ - i2c_data[1] = wdt_margin<<2 | 0x82; + /* mulitplier = WD_TIMO, resolution = 1s (0x2) */ + wdt |= wdt_margin << 2 | 0x2; /* * M41T65 has three bits for watchdog resolution. Don't set bit 7, as @@ -527,7 +518,7 @@ static void wdt_ping(void) if (clientdata->features & M41T80_FEATURE_WD) i2c_data[1] &= ~M41T80_WATCHDOG_RB2; - i2c_transfer(save_client->adapter, msgs1, 1); + i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, wdt); } /** @@ -537,36 +528,8 @@ static void wdt_ping(void) */ static void wdt_disable(void) { - unsigned char i2c_data[2], i2c_buf[0x10]; - struct i2c_msg msgs0[2] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 1, - .buf = i2c_data, - }, - { - .addr = save_client->addr, - .flags = I2C_M_RD, - .len = 1, - .buf = i2c_buf, - }, - }; - struct i2c_msg msgs1[1] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 2, - .buf = i2c_data, - }, - }; - - i2c_data[0] = 0x09; - i2c_transfer(save_client->adapter, msgs0, 2); - - i2c_data[0] = 0x09; - i2c_data[1] = 0x00; - i2c_transfer(save_client->adapter, msgs1, 1); + i2c_smbus_read_byte_data(save_client, M41T80_REG_WATCHDOG); + i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, 0); } /** @@ -768,8 +731,8 @@ static int m41t80_probe(struct i2c_client *client, struct rtc_time tm; struct m41t80_data *clientdata = NULL; - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C - | I2C_FUNC_SMBUS_BYTE_DATA)) { + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA)) { rc = -ENODEV; goto exit; } -- 1.7.3.4 From david.daney@cavium.com Fri Aug 19 03:05:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 03:05:51 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:1514 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492157Ab1HSBFq (ORCPT ); Fri, 19 Aug 2011 03:05:46 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 18 Aug 2011 18:06:53 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 18 Aug 2011 18:05:44 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 18 Aug 2011 18:05:44 -0700 Message-ID: <4E4DB6E2.3050207@cavium.com> Date: Thu, 18 Aug 2011 18:05:38 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Jason Kwon CC: linux-mips@linux-mips.org Subject: Re: Problems booting 3.0.3 kernel on Octeon CN58XX board References: <4E4DA9DA.60305@ericsson.com> In-Reply-To: <4E4DA9DA.60305@ericsson.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 19 Aug 2011 01:05:44.0304 (UTC) FILETIME=[1F344700:01CC5E0C] X-archive-position: 30911 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13782 Content-Length: 2784 Lines: 67 On 08/18/2011 05:10 PM, Jason Kwon wrote: > Attempting to boot a 3.0.3 kernel on a CN58XX board produced the > following oops: > > CPU 4 Unable to handle kernel paging request at virtual address > 0000000001c00000, epc == ffffffff811aa9f4, ra == ffffffff811aaa98 > Oops[#1]: > Cpu 4 > $ 0 : 0000000000000000 0000000010008ce0 ffffffff821d2b80 0000000001c00000 > $ 4 : 0000000001c00038 000000000000017c 0000000000080000 0000000000080072 > $ 8 : 0000000000000008 0000000000000002 0000000000000003 a800000002284520 > $12 : 0000000000000002 ffffffff8186ee80 ffffffffffffff80 0000000000000030 > $16 : 0000000000080072 0000000000000001 0000000001bfa8f0 0000000001bfa928 > $20 : a800000003aff8f0 00000000000f0000 ffffffff8186ee80 ffffffff821d2a80 > $24 : 0000000000000001 0000000000000038 > $28 : a80000041fc48000 a80000041fc4bd90 fffffffffffffffc ffffffff811aaa98 > Hi : 0000000000000000 > Lo : 0000000000000000 > epc : ffffffff811aa9f4 setup_per_zone_wmarks+0x19c/0x2d8 > Not tainted > ra : ffffffff811aaa98 setup_per_zone_wmarks+0x240/0x2d8 > Status: 10008ce2 KX SX UX KERNEL EXL > Cause : 40808408 > BadVA : 0000000001c00000 > PrId : 000d0301 (Cavium Octeon+) > Modules linked in: > Process swapper (pid: 1, threadinfo=a80000041fc48000, > task=a80000041fc44038, tls=0000000000000000) > Stack : 0000000000000000 000000000006f75d ffffffff8186eec0 0000000000000001 > 0000000000000547 ffffffff81825598 ffffffff81a80000 ffffffff818b3e68 > ffffffff818a40ac 0000000000000000 ffffffff81a80000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 ffffffff818a40f0 > ffffffff81a80000 ffffffff81100438 ffffffff818b4198 ffffffff818b3e68 > ffffffff818b46c8 0000000000000000 0000000000000000 ffffffff818721d0 > 0000000000000000 0000000000000000 0000000000000000 ffffffff81109bb0 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 ffffffff818720f8 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > ... > Call Trace: > [] setup_per_zone_wmarks+0x19c/0x2d8 > [] init_per_zone_wmark_min+0x44/0xe0 > [] do_one_initcall+0x38/0x160 > [] kernel_init+0xd8/0x178 > [] kernel_thread_helper+0x10/0x18 [...] Weird, I get the same thing on cn5860 and cn3860. cn5750 and cn5020 are fine. Normally I test on my ebh5610 board (cn5750) so I didn't notice this. It may be caused by holes in the memory map. Earlier I posted patches to set the memory as present: http://patchwork.linux-mips.org/patch/1988/ http://patchwork.linux-mips.org/patch/1989/ http://patchwork.linux-mips.org/patch/1990/ One or more of those might help, but it is just a guess at this point. I might take a look next week. David Daney From yong.zhang@windriver.com Fri Aug 19 03:56:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 03:56:31 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:46586 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492167Ab1HSB4W (ORCPT ); Fri, 19 Aug 2011 03:56:22 +0200 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id p7J1uBok013586 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Thu, 18 Aug 2011 18:56:11 -0700 (PDT) Received: from localhost (128.224.158.133) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server (TLS) id 14.1.255.0; Thu, 18 Aug 2011 18:56:11 -0700 Date: Fri, 19 Aug 2011 09:56:07 +0800 From: Yong Zhang To: David Daney CC: , , Ralf Baechle Subject: Re: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex Message-ID: <20110819015607.GA2798@windriver.com> Reply-To: Yong Zhang References: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> <4E4BF7C0.80703@cavium.com> <20110818023247.GA3750@windriver.com> <4E4D3C8D.1040707@cavium.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <4E4D3C8D.1040707@cavium.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [128.224.158.133] X-archive-position: 30912 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang@windriver.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13794 Content-Length: 1483 Lines: 40 On Thu, Aug 18, 2011 at 09:23:41AM -0700, David Daney wrote: > On 08/17/2011 07:32 PM, Yong Zhang wrote: > >On Wed, Aug 17, 2011 at 10:17:52AM -0700, David Daney wrote: > >>>diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S > >>>index 46c4763..f48b18e 100644 > >>>--- a/arch/mips/kernel/scall64-o32.S > >>>+++ b/arch/mips/kernel/scall64-o32.S > >>>@@ -441,7 +441,7 @@ sys_call_table: > >>> PTR sys_fremovexattr /* 4235 */ > >>> PTR sys_tkill > >>> PTR sys_sendfile64 > >>>- PTR compat_sys_futex > >>>+ PTR sys_32_futex > >> > >>This change is redundant, scall64-o32.S already does the right thing > > > >My first virsion(not sent out) doesn't include scall64-o32.S either. > > > >>so additional zero extending is not needed and is just extra > >>instructions to execute for no reason. > > > >Why I'm adding it here is for: > >1)code consistent, otherwise we must move SYSCALL_DEFINE6(32_futex,...) > > under CONFIG_MIPS32_N32; > > No, you don't have to move it. Just don't call it. > > > >2)I'm afraid there may be some other way to touch the high 32-bit of a > > register, so touching scall64-o32.S is also for safety(due to unknown > > reason, fix me if I'm wrong). > > OK: You are mistaken. You claim you don't understand what the code > does. That is really a poor justification for modifying it. If you don't like it and you are sure there is no potential security problem, just make a patch to remove it. Go ahead. Thanks, Yong From yong.zhang@windriver.com Fri Aug 19 05:50:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 05:51:03 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:60923 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491098Ab1HSDu5 (ORCPT ); Fri, 19 Aug 2011 05:50:57 +0200 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id p7J3nswE025687 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Thu, 18 Aug 2011 20:49:54 -0700 (PDT) Received: from localhost (128.224.158.133) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server (TLS) id 14.1.255.0; Thu, 18 Aug 2011 20:49:53 -0700 Date: Fri, 19 Aug 2011 11:49:50 +0800 From: Yong Zhang To: Ralf Baechle CC: David Daney , , , , Yong Zhang , Steven Rostedt , Frederic Weisbecker , Ingo Molnar , Martin Schwidefsky , "David S. Miller" , Thomas Gleixner , Andrew Morton Subject: How to trace compat syscalls? [Was Re: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex] Message-ID: <20110819034950.GA3350@windriver.com> Reply-To: Yong Zhang References: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> <4E4BF7C0.80703@cavium.com> <20110818201911.GF22920@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <20110818201911.GF22920@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [128.224.158.133] X-archive-position: 30913 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang@windriver.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13821 Content-Length: 3957 Lines: 102 Cc'ing more people. On Thu, Aug 18, 2011 at 09:19:11PM +0100, Ralf Baechle wrote: > > But really I think this patch fixes things at the wrong level. Each > > architecture potentially needs a similar patch. What would happen if > > we did something like: > > > +++ b/kernel/futex_compat.c > > @@ -180,9 +180,9 @@ err_unlock: > > return ret; > > } > > > > -asmlinkage long compat_sys_futex(u32 __user *uaddr, int op, u32 val, > > - struct compat_timespec __user *utime, u32 __user *uaddr2, > > - u32 val3) > > +SYSCALL_DEFINE6(compat_sys_futex, u32 __user *, uaddr, int , op, u32, val, > > + struct compat_timespec __user *, utime, u32 __user *, uaddr2, > > + u32, val3) > > { > > struct timespec ts; > > ktime_t t, *tp = NULL; > > > > Obviously the function name is wrong, but a varient of > > SYSCALL_DEFINE*() could be created so the proper function names are > > produced. > > Right now none of the the generic compat_ functions is wrapped in > SYSCALL_DEFINE* because for some architectures a further wrapper function > is needed. It seems some architectures call compat_ calls directly > without SYSCALL_DEFINE* which with CONFIG_FTRACE_SYSCALLS is a bug ... Just checked some archs which have HAVE_SYSCALL_TRACEPOINTS=y and could call compat_* syscalls when run 32bit process on 64bit kernel, I don't find any special code against FTRACE_SYSCALLS. So that means we could not trace compat syscalls even if we want to(Am I missing something?). So I think if we want to trace it, the easy way is just like what we have done on normal syscalls, IOW, we could SYSCALL_DEFINE all of the compat syscalls. Thought? BTW, I have make a trival patch to introduce COMPAT_SYSCALL_DEFINE, it's just for calling of inspiration(no test no build, and I leave SYSCALL_METADATA etc untouched.) Thanks, Yong --- diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 8c03b98..e79027f 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -221,26 +221,38 @@ extern struct trace_event_functions exit_syscall_print_funcs; __SC_STR_ADECL##x(__VA_ARGS__) \ }; \ SYSCALL_METADATA(sname, x); \ - __SYSCALL_DEFINEx(x, sname, __VA_ARGS__) + __SYSCALL_DEFINEx(, x, sname, __VA_ARGS__) + +#define COMPAT_SYSCALL_DEFINEx(x, sname, ...) \ + static const char *types_compat_##sname[] = { \ + __SC_STR_TDECL##x(__VA_ARGS__) \ + }; \ + static const char *args_compat_##sname[] = { \ + __SC_STR_ADECL##x(__VA_ARGS__) \ + }; \ + SYSCALL_METADATA(compat, sname, x); \ + __SYSCALL_DEFINEx(cmopat_, x, sname, __VA_ARGS__) #else #define SYSCALL_DEFINEx(x, sname, ...) \ - __SYSCALL_DEFINEx(x, sname, __VA_ARGS__) + __SYSCALL_DEFINEx(, x, sname, __VA_ARGS__) +#define COMPAT_SYSCALL_DEFINEx(x, sname, ...) \ + __SYSCALL_DEFINEx(compat_, x, sname, __VA_ARGS__) #endif #ifdef CONFIG_HAVE_SYSCALL_WRAPPERS -#define SYSCALL_DEFINE(name) static inline long SYSC_##name +#define SYSCALL_DEFINE(compat, name) static inline long compat##SYSC_##name -#define __SYSCALL_DEFINEx(x, name, ...) \ - asmlinkage long sys##name(__SC_DECL##x(__VA_ARGS__)); \ - static inline long SYSC##name(__SC_DECL##x(__VA_ARGS__)); \ - asmlinkage long SyS##name(__SC_LONG##x(__VA_ARGS__)) \ +#define __SYSCALL_DEFINEx(compat, x, name, ...) \ + asmlinkage long compat##sys##name(__SC_DECL##x(__VA_ARGS__)); \ + static inline long compat##SYSC##name(__SC_DECL##x(__VA_ARGS__));\ + asmlinkage long compat##SyS##name(__SC_LONG##x(__VA_ARGS__)) \ { \ __SC_TEST##x(__VA_ARGS__); \ - return (long) SYSC##name(__SC_CAST##x(__VA_ARGS__)); \ + return (long) compat##SYSC##name(__SC_CAST##x(__VA_ARGS__));\ } \ - SYSCALL_ALIAS(sys##name, SyS##name); \ - static inline long SYSC##name(__SC_DECL##x(__VA_ARGS__)) + SYSCALL_ALIAS(compat##sys##name, compat##SyS##name); \ + static inline long compat##SYSC##name(__SC_DECL##x(__VA_ARGS__)) #else /* CONFIG_HAVE_SYSCALL_WRAPPERS */ From yong.zhang@windriver.com Fri Aug 19 06:16:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 06:16:34 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:63523 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490967Ab1HSEQ1 (ORCPT ); Fri, 19 Aug 2011 06:16:27 +0200 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id p7J4Fcwp028542 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Thu, 18 Aug 2011 21:15:38 -0700 (PDT) Received: from localhost (128.224.158.133) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server (TLS) id 14.1.255.0; Thu, 18 Aug 2011 21:15:38 -0700 Date: Fri, 19 Aug 2011 12:15:34 +0800 From: Yong Zhang To: Ralf Baechle CC: David Daney , , , , Yong Zhang , Steven Rostedt , Frederic Weisbecker , Ingo Molnar , Martin Schwidefsky , "David S. Miller" , Thomas Gleixner , Andrew Morton Subject: Re: How to trace compat syscalls? [Was Re: [PATCH] MIPS: use 32-bit wrapper for compat_sys_futex] Message-ID: <20110819041534.GA4230@windriver.com> Reply-To: Yong Zhang References: <1313546094-11882-1-git-send-email-yong.zhang@windriver.com> <4E4BF7C0.80703@cavium.com> <20110818201911.GF22920@linux-mips.org> <20110819034950.GA3350@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <20110819034950.GA3350@windriver.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [128.224.158.133] X-archive-position: 30914 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang@windriver.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13831 Content-Length: 4268 Lines: 106 On Fri, Aug 19, 2011 at 11:49:50AM +0800, Yong Zhang wrote: > Cc'ing more people. > > On Thu, Aug 18, 2011 at 09:19:11PM +0100, Ralf Baechle wrote: > > > But really I think this patch fixes things at the wrong level. Each > > > architecture potentially needs a similar patch. What would happen if > > > we did something like: > > > > > +++ b/kernel/futex_compat.c > > > @@ -180,9 +180,9 @@ err_unlock: > > > return ret; > > > } > > > > > > -asmlinkage long compat_sys_futex(u32 __user *uaddr, int op, u32 val, > > > - struct compat_timespec __user *utime, u32 __user *uaddr2, > > > - u32 val3) > > > +SYSCALL_DEFINE6(compat_sys_futex, u32 __user *, uaddr, int , op, u32, val, > > > + struct compat_timespec __user *, utime, u32 __user *, uaddr2, > > > + u32, val3) > > > { > > > struct timespec ts; > > > ktime_t t, *tp = NULL; > > > > > > Obviously the function name is wrong, but a varient of > > > SYSCALL_DEFINE*() could be created so the proper function names are > > > produced. > > > > Right now none of the the generic compat_ functions is wrapped in > > SYSCALL_DEFINE* because for some architectures a further wrapper function > > is needed. It seems some architectures call compat_ calls directly > > without SYSCALL_DEFINE* which with CONFIG_FTRACE_SYSCALLS is a bug ... > > Just checked some archs which have HAVE_SYSCALL_TRACEPOINTS=y and could > call compat_* syscalls when run 32bit process on 64bit kernel, I don't > find any special code against FTRACE_SYSCALLS. So that means we could > not trace compat syscalls even if we want to(Am I missing something?). > So I think if we want to trace it, the easy way is just like what we have > done on normal syscalls, IOW, we could SYSCALL_DEFINE all of the compat > syscalls. Except the ones which call sys_* finally, :) > > Thought? > > BTW, I have make a trival patch to introduce COMPAT_SYSCALL_DEFINE, it's just > for calling of inspiration(no test no build, and I leave SYSCALL_METADATA > etc untouched.) > > Thanks, > Yong > > --- > diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h > index 8c03b98..e79027f 100644 > --- a/include/linux/syscalls.h > +++ b/include/linux/syscalls.h > @@ -221,26 +221,38 @@ extern struct trace_event_functions exit_syscall_print_funcs; > __SC_STR_ADECL##x(__VA_ARGS__) \ > }; \ > SYSCALL_METADATA(sname, x); \ > - __SYSCALL_DEFINEx(x, sname, __VA_ARGS__) > + __SYSCALL_DEFINEx(, x, sname, __VA_ARGS__) > + > +#define COMPAT_SYSCALL_DEFINEx(x, sname, ...) \ > + static const char *types_compat_##sname[] = { \ > + __SC_STR_TDECL##x(__VA_ARGS__) \ > + }; \ > + static const char *args_compat_##sname[] = { \ > + __SC_STR_ADECL##x(__VA_ARGS__) \ > + }; \ > + SYSCALL_METADATA(compat, sname, x); \ > + __SYSCALL_DEFINEx(cmopat_, x, sname, __VA_ARGS__) > #else > #define SYSCALL_DEFINEx(x, sname, ...) \ > - __SYSCALL_DEFINEx(x, sname, __VA_ARGS__) > + __SYSCALL_DEFINEx(, x, sname, __VA_ARGS__) > +#define COMPAT_SYSCALL_DEFINEx(x, sname, ...) \ > + __SYSCALL_DEFINEx(compat_, x, sname, __VA_ARGS__) > #endif > > #ifdef CONFIG_HAVE_SYSCALL_WRAPPERS > > -#define SYSCALL_DEFINE(name) static inline long SYSC_##name > +#define SYSCALL_DEFINE(compat, name) static inline long compat##SYSC_##name > > -#define __SYSCALL_DEFINEx(x, name, ...) \ > - asmlinkage long sys##name(__SC_DECL##x(__VA_ARGS__)); \ > - static inline long SYSC##name(__SC_DECL##x(__VA_ARGS__)); \ > - asmlinkage long SyS##name(__SC_LONG##x(__VA_ARGS__)) \ > +#define __SYSCALL_DEFINEx(compat, x, name, ...) \ > + asmlinkage long compat##sys##name(__SC_DECL##x(__VA_ARGS__)); \ > + static inline long compat##SYSC##name(__SC_DECL##x(__VA_ARGS__));\ > + asmlinkage long compat##SyS##name(__SC_LONG##x(__VA_ARGS__)) \ > { \ > __SC_TEST##x(__VA_ARGS__); \ > - return (long) SYSC##name(__SC_CAST##x(__VA_ARGS__)); \ > + return (long) compat##SYSC##name(__SC_CAST##x(__VA_ARGS__));\ > } \ > - SYSCALL_ALIAS(sys##name, SyS##name); \ > - static inline long SYSC##name(__SC_DECL##x(__VA_ARGS__)) > + SYSCALL_ALIAS(compat##sys##name, compat##SyS##name); \ > + static inline long compat##SYSC##name(__SC_DECL##x(__VA_ARGS__)) > > #else /* CONFIG_HAVE_SYSCALL_WRAPPERS */ > From mattst88@gmail.com Fri Aug 19 06:16:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 06:17:01 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:38863 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491108Ab1HSEQl (ORCPT ); Fri, 19 Aug 2011 06:16:41 +0200 Received: by vws8 with SMTP id 8so2557838vws.36 for ; Thu, 18 Aug 2011 21:16:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:cc:content-type; bh=kjKVTMNZ7lxCzamrq6wMO7f2Qx33HIRvJIk8bn+iXzE=; b=f8OEOv6PUgkUANhtuT8Ut8pmjp8iwSj1MwIgrjI8fr/jl+4gVunPXvNy10yXA9aty/ rSoRbyOXcQVnQ+A+yJYjXeqGWaWSOtItAnz6kfBQMZRlXGu7lop1uIq7Xet8aPugylHF Wxe9RYkNrU35RPghclcisH8NYUBwPnPcmyTJ0= Received: by 10.52.71.41 with SMTP id r9mr1428302vdu.289.1313727394220; Thu, 18 Aug 2011 21:16:34 -0700 (PDT) MIME-Version: 1.0 Received: by 10.52.168.133 with HTTP; Thu, 18 Aug 2011 21:16:14 -0700 (PDT) From: Matt Turner Date: Fri, 19 Aug 2011 00:16:14 -0400 Message-ID: Subject: select() to /dev/rtc0 to wait for clock tick timed out To: john stultz Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 30915 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13833 Content-Length: 1130 Lines: 35 Hi John, I just sent a patch series to linux-mips@ that enables the RTC on a particular Broadcom MIPS motherboard (BCM91250A SWARM). The RTC is an M41T80. When I first found the patchset (it was originally sent a a few years ago) and applied it to 2.6.37, it worked perfectly. Applied to 3.x (and I think even 2.6.38) I get the following when I run hwclock: # hwclock --systohc select() to /dev/rtc0 to wait for clock tick timed out dmesg shows: [ 1.068000] i2c /dev entries driver [ 1.072000] i2c-sibyte: i2c SMBus adapter module for SiByte board [ 1.080000] rtc-m41t80 1-0068: chip found, driver version 0.06 [ 1.088000] rtc-m41t80 1-0068: rtc core: registered m41t81 as rtc0 [ 1.172000] rtc-m41t80 1-0068: setting system clock to 2011-08-18 19:56:53 UTC (1313697413) I'm emailing you because I thought it might be the same problem as https://lkml.org/lkml/2011/1/20/306 Do you know what might be the problem? The patch series can be found here [1], if they did not find their way to you through another mailing list. Thanks, Matt [1] http://www.linux-mips.org/archives/linux-mips/2011-08/threads.html From sshtylyov@mvista.com Fri Aug 19 13:00:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 13:00:24 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:55416 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491148Ab1HSLAU (ORCPT ); Fri, 19 Aug 2011 13:00:20 +0200 Received: by wyh11 with SMTP id 11so2522513wyh.36 for ; Fri, 19 Aug 2011 04:00:13 -0700 (PDT) Received: by 10.216.255.18 with SMTP id i18mr1511080wes.64.1313751613688; Fri, 19 Aug 2011 04:00:13 -0700 (PDT) Received: from [192.168.2.2] ([91.79.76.218]) by mx.google.com with ESMTPS id y61sm2089215wec.30.2011.08.19.04.00.11 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 19 Aug 2011 04:00:12 -0700 (PDT) Message-ID: <4E4E4216.1050903@mvista.com> Date: Fri, 19 Aug 2011 14:59:34 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:6.0) Gecko/20110812 Thunderbird/6.0 MIME-Version: 1.0 To: Jason Kwon CC: linux-mips@linux-mips.org Subject: Re: Problems booting 3.0.3 kernel on Octeon CN58XX board References: <4E4DA9DA.60305@ericsson.com> In-Reply-To: <4E4DA9DA.60305@ericsson.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 30916 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13998 Content-Length: 1108 Lines: 46 Hello. On 19-08-2011 4:10, Jason Kwon wrote: > Attempting to boot a 3.0.3 kernel on a CN58XX board produced the following oops: [...] > Code: 007e1824 0064182d 64840038 c84afff5 64c60001 66020200 > 66737000 1220000c > All code > ======== > 0: 24 18 and $0x18,%al > 2: 7e 00 jle 0x4 > 4: 2d 18 64 00 38 sub $0x38006418,%eax > 9: 00 84 64 00 00 62 dc add %al,-0x239e0000(%rsp,%riz,2) > 10: f5 cmc > 11: ff 4a c8 decl -0x38(%rdx) > 14: 01 00 add %eax,(%rax) > 16: c6 (bad) > 17: 64 00 02 add %al,%fs:(%rdx) > 1a: 02 66 00 add 0x0(%rsi),%ah > 1d: 70 73 jo 0x92 > 1f: 66 data16 > 20: 0c 00 or $0x0,%al > 22: 20 12 and %dl,(%rdx) > Code starting with the faulting instruction > =========================================== > 0: 00 00 add %al,(%rax) > 2: 62 (bad) > 3: dc f5 fdiv %st,%st(5) > 5: ff 4a c8 decl -0x38(%rdx) > 8: 01 00 add %eax,(%rax) > a: c6 (bad) > b: 64 00 02 add %al,%fs:(%rdx) > e: 02 66 00 add 0x0(%rsi),%ah > 11: 70 73 jo 0x86 > 13: 66 data16 > 14: 0c 00 or $0x0,%al > 16: 20 12 and %dl,(%rdx) This is x86 disassembly -- you should have used MIPS cross-tools. WBR, Sergei From david.daney@cavium.com Fri Aug 19 18:33:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 18:33:09 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:6950 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491161Ab1HSQdC (ORCPT ); Fri, 19 Aug 2011 18:33:02 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 19 Aug 2011 09:34:04 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 19 Aug 2011 09:32:55 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 19 Aug 2011 09:32:55 -0700 Message-ID: <4E4E9036.9000802@cavium.com> Date: Fri, 19 Aug 2011 09:32:54 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Jason Kwon CC: linux-mips@linux-mips.org Subject: Re: Problems booting 3.0.3 kernel on Octeon CN58XX board References: <4E4DA9DA.60305@ericsson.com> In-Reply-To: <4E4DA9DA.60305@ericsson.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 19 Aug 2011 16:32:55.0750 (UTC) FILETIME=[A6214660:01CC5E8D] X-archive-position: 30917 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14491 Content-Length: 2485 Lines: 52 On 08/18/2011 05:10 PM, Jason Kwon wrote: > Attempting to boot a 3.0.3 kernel on a CN58XX board produced the > following oops: > > CPU 4 Unable to handle kernel paging request at virtual address > 0000000001c00000, epc == ffffffff811aa9f4, ra == ffffffff811aaa98 > Oops[#1]: > Cpu 4 > $ 0 : 0000000000000000 0000000010008ce0 ffffffff821d2b80 0000000001c00000 > $ 4 : 0000000001c00038 000000000000017c 0000000000080000 0000000000080072 > $ 8 : 0000000000000008 0000000000000002 0000000000000003 a800000002284520 > $12 : 0000000000000002 ffffffff8186ee80 ffffffffffffff80 0000000000000030 > $16 : 0000000000080072 0000000000000001 0000000001bfa8f0 0000000001bfa928 > $20 : a800000003aff8f0 00000000000f0000 ffffffff8186ee80 ffffffff821d2a80 > $24 : 0000000000000001 0000000000000038 > $28 : a80000041fc48000 a80000041fc4bd90 fffffffffffffffc ffffffff811aaa98 > Hi : 0000000000000000 > Lo : 0000000000000000 > epc : ffffffff811aa9f4 setup_per_zone_wmarks+0x19c/0x2d8 > Not tainted > ra : ffffffff811aaa98 setup_per_zone_wmarks+0x240/0x2d8 > Status: 10008ce2 KX SX UX KERNEL EXL > Cause : 40808408 > BadVA : 0000000001c00000 > PrId : 000d0301 (Cavium Octeon+) > Modules linked in: > Process swapper (pid: 1, threadinfo=a80000041fc48000, > task=a80000041fc44038, tls=0000000000000000) > Stack : 0000000000000000 000000000006f75d ffffffff8186eec0 0000000000000001 > 0000000000000547 ffffffff81825598 ffffffff81a80000 ffffffff818b3e68 > ffffffff818a40ac 0000000000000000 ffffffff81a80000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 ffffffff818a40f0 > ffffffff81a80000 ffffffff81100438 ffffffff818b4198 ffffffff818b3e68 > ffffffff818b46c8 0000000000000000 0000000000000000 ffffffff818721d0 > 0000000000000000 0000000000000000 0000000000000000 ffffffff81109bb0 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 ffffffff818720f8 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > ... > Call Trace: > [] setup_per_zone_wmarks+0x19c/0x2d8 > [] init_per_zone_wmark_min+0x44/0xe0 > [] do_one_initcall+0x38/0x160 > [] kernel_init+0xd8/0x178 > [] kernel_thread_helper+0x10/0x18 > It appears to be related to use of physical memory above the 16GB barrier. You could try reducing the amount of memory allocated to the kernel by passing 'mem=1700M' on the kernel command line. David Daney From guenter.roeck@ericsson.com Fri Aug 19 19:01:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 19:01:44 +0200 (CEST) Received: from imr3.ericy.com ([198.24.6.13]:41182 "EHLO imr3.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491816Ab1HSRBj (ORCPT ); Fri, 19 Aug 2011 19:01:39 +0200 Received: from eusaamw0711.eamcs.ericsson.se ([147.117.20.178]) by imr3.ericy.com (8.13.8/8.13.8) with ESMTP id p7JH0NkT018169 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Fri, 19 Aug 2011 12:01:02 -0500 Received: from [155.53.96.104] (147.117.20.214) by eusaamw0711.eamcs.ericsson.se (147.117.20.179) with Microsoft SMTP Server id 8.3.137.0; Fri, 19 Aug 2011 13:00:55 -0400 Subject: Re: Problems booting 3.0.3 kernel on Octeon CN58XX board From: Guenter Roeck Reply-To: To: David Daney CC: Jason Kwon , "linux-mips@linux-mips.org" In-Reply-To: <4E4E9036.9000802@cavium.com> References: <4E4DA9DA.60305@ericsson.com> <4E4E9036.9000802@cavium.com> Content-Type: text/plain; charset="UTF-8" Organization: Ericsson Date: Fri, 19 Aug 2011 10:00:48 -0700 Message-ID: <1313773248.3235.87.camel@groeck-laptop> MIME-Version: 1.0 X-Mailer: Evolution 2.32.2 Content-Transfer-Encoding: 7bit X-archive-position: 30918 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14561 Content-Length: 4052 Lines: 97 On Fri, 2011-08-19 at 12:32 -0400, David Daney wrote: > On 08/18/2011 05:10 PM, Jason Kwon wrote: > > Attempting to boot a 3.0.3 kernel on a CN58XX board produced the > > following oops: > > > > CPU 4 Unable to handle kernel paging request at virtual address > > 0000000001c00000, epc == ffffffff811aa9f4, ra == ffffffff811aaa98 > > Oops[#1]: > > Cpu 4 > > $ 0 : 0000000000000000 0000000010008ce0 ffffffff821d2b80 0000000001c00000 > > $ 4 : 0000000001c00038 000000000000017c 0000000000080000 0000000000080072 > > $ 8 : 0000000000000008 0000000000000002 0000000000000003 a800000002284520 > > $12 : 0000000000000002 ffffffff8186ee80 ffffffffffffff80 0000000000000030 > > $16 : 0000000000080072 0000000000000001 0000000001bfa8f0 0000000001bfa928 > > $20 : a800000003aff8f0 00000000000f0000 ffffffff8186ee80 ffffffff821d2a80 > > $24 : 0000000000000001 0000000000000038 > > $28 : a80000041fc48000 a80000041fc4bd90 fffffffffffffffc ffffffff811aaa98 > > Hi : 0000000000000000 > > Lo : 0000000000000000 > > epc : ffffffff811aa9f4 setup_per_zone_wmarks+0x19c/0x2d8 > > Not tainted > > ra : ffffffff811aaa98 setup_per_zone_wmarks+0x240/0x2d8 > > Status: 10008ce2 KX SX UX KERNEL EXL > > Cause : 40808408 > > BadVA : 0000000001c00000 > > PrId : 000d0301 (Cavium Octeon+) > > Modules linked in: > > Process swapper (pid: 1, threadinfo=a80000041fc48000, > > task=a80000041fc44038, tls=0000000000000000) > > Stack : 0000000000000000 000000000006f75d ffffffff8186eec0 0000000000000001 > > 0000000000000547 ffffffff81825598 ffffffff81a80000 ffffffff818b3e68 > > ffffffff818a40ac 0000000000000000 ffffffff81a80000 0000000000000000 > > 0000000000000000 0000000000000000 0000000000000000 ffffffff818a40f0 > > ffffffff81a80000 ffffffff81100438 ffffffff818b4198 ffffffff818b3e68 > > ffffffff818b46c8 0000000000000000 0000000000000000 ffffffff818721d0 > > 0000000000000000 0000000000000000 0000000000000000 ffffffff81109bb0 > > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > > 0000000000000000 0000000000000000 0000000000000000 ffffffff818720f8 > > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > > ... > > Call Trace: > > [] setup_per_zone_wmarks+0x19c/0x2d8 > > [] init_per_zone_wmark_min+0x44/0xe0 > > [] do_one_initcall+0x38/0x160 > > [] kernel_init+0xd8/0x178 > > [] kernel_thread_helper+0x10/0x18 > > > > It appears to be related to use of physical memory above the 16GB > barrier. You could try reducing the amount of memory allocated to the > kernel by passing 'mem=1700M' on the kernel command line. > Hi David, are you sure ? This is what I see with our own boards (not the reference design board): Works: Linux version 3.0.3-423-gfa07d39 (groeck@rbos-pc-13) (gcc version 4.4.1 (Debian 4.4.1-1) ) #2 SMP PREEMPT Thu Aug 18 14:09:53 PDT 2011 [ ... ] CPU revision is: 000d030b (Cavium Octeon+) Checking for the multiply/shift bug... no. Checking for the daddiu bug... no. Determined physical RAM map: memory: 00000000001fa000 @ 000000000160b000 (usable) memory: 000000000e400000 @ 0000000001900000 (usable) memory: 00000000d0000000 @ 0000000020000000 (usable) memory: 000000000ffff000 @ 00000000f0001000 (usable) memory: 0000000010000000 @ 0000000410000000 (usable) Crashes: Linux version 3.0.3-423-gfa07d39 (groeck@rbos-pc-13) (gcc version 4.4.1 (Debian 4.4.1-1) ) #2 SMP PREEMPT Thu Aug 18 14:09:53 PDT 2011 [ ... ] CPU revision is: 000d0003 (Cavium Octeon) Checking for the multiply/shift bug... no. Checking for the daddiu bug... no. Determined physical RAM map: memory: 00000000001fa000 @ 000000000160b000 (usable) memory: 000000000e400000 @ 0000000001900000 (usable) memory: 0000000060000000 @ 0000000020000000 (usable) memory: 0000000010000000 @ 0000000410000000 (usable) The memory at 0000000410000000 is there for both CPUs, yet the crash is only seen on the board with CN38xx. From a SW perspective, only difference besides the CPU type is that the working board has more memory. Thanks, Guenter From david.daney@cavium.com Fri Aug 19 19:10:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 19:10:42 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8239 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491816Ab1HSRKd (ORCPT ); Fri, 19 Aug 2011 19:10:33 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 19 Aug 2011 10:11:38 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 19 Aug 2011 10:10:29 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 19 Aug 2011 10:10:28 -0700 Message-ID: <4E4E9902.10304@cavium.com> Date: Fri, 19 Aug 2011 10:10:26 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: guenter.roeck@ericsson.com CC: Jason Kwon , "linux-mips@linux-mips.org" Subject: Re: Problems booting 3.0.3 kernel on Octeon CN58XX board References: <4E4DA9DA.60305@ericsson.com> <4E4E9036.9000802@cavium.com> <1313773248.3235.87.camel@groeck-laptop> In-Reply-To: <1313773248.3235.87.camel@groeck-laptop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 19 Aug 2011 17:10:28.0587 (UTC) FILETIME=[E4ECEBB0:01CC5E92] X-archive-position: 30919 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14578 Content-Length: 4885 Lines: 117 On 08/19/2011 10:00 AM, Guenter Roeck wrote: > On Fri, 2011-08-19 at 12:32 -0400, David Daney wrote: >> On 08/18/2011 05:10 PM, Jason Kwon wrote: >>> Attempting to boot a 3.0.3 kernel on a CN58XX board produced the >>> following oops: >>> >>> CPU 4 Unable to handle kernel paging request at virtual address >>> 0000000001c00000, epc == ffffffff811aa9f4, ra == ffffffff811aaa98 >>> Oops[#1]: >>> Cpu 4 >>> $ 0 : 0000000000000000 0000000010008ce0 ffffffff821d2b80 0000000001c00000 >>> $ 4 : 0000000001c00038 000000000000017c 0000000000080000 0000000000080072 >>> $ 8 : 0000000000000008 0000000000000002 0000000000000003 a800000002284520 >>> $12 : 0000000000000002 ffffffff8186ee80 ffffffffffffff80 0000000000000030 >>> $16 : 0000000000080072 0000000000000001 0000000001bfa8f0 0000000001bfa928 >>> $20 : a800000003aff8f0 00000000000f0000 ffffffff8186ee80 ffffffff821d2a80 >>> $24 : 0000000000000001 0000000000000038 >>> $28 : a80000041fc48000 a80000041fc4bd90 fffffffffffffffc ffffffff811aaa98 >>> Hi : 0000000000000000 >>> Lo : 0000000000000000 >>> epc : ffffffff811aa9f4 setup_per_zone_wmarks+0x19c/0x2d8 >>> Not tainted >>> ra : ffffffff811aaa98 setup_per_zone_wmarks+0x240/0x2d8 >>> Status: 10008ce2 KX SX UX KERNEL EXL >>> Cause : 40808408 >>> BadVA : 0000000001c00000 >>> PrId : 000d0301 (Cavium Octeon+) >>> Modules linked in: >>> Process swapper (pid: 1, threadinfo=a80000041fc48000, >>> task=a80000041fc44038, tls=0000000000000000) >>> Stack : 0000000000000000 000000000006f75d ffffffff8186eec0 0000000000000001 >>> 0000000000000547 ffffffff81825598 ffffffff81a80000 ffffffff818b3e68 >>> ffffffff818a40ac 0000000000000000 ffffffff81a80000 0000000000000000 >>> 0000000000000000 0000000000000000 0000000000000000 ffffffff818a40f0 >>> ffffffff81a80000 ffffffff81100438 ffffffff818b4198 ffffffff818b3e68 >>> ffffffff818b46c8 0000000000000000 0000000000000000 ffffffff818721d0 >>> 0000000000000000 0000000000000000 0000000000000000 ffffffff81109bb0 >>> 0000000000000000 0000000000000000 0000000000000000 0000000000000000 >>> 0000000000000000 0000000000000000 0000000000000000 ffffffff818720f8 >>> 0000000000000000 0000000000000000 0000000000000000 0000000000000000 >>> ... >>> Call Trace: >>> [] setup_per_zone_wmarks+0x19c/0x2d8 >>> [] init_per_zone_wmark_min+0x44/0xe0 >>> [] do_one_initcall+0x38/0x160 >>> [] kernel_init+0xd8/0x178 >>> [] kernel_thread_helper+0x10/0x18 >>> >> >> It appears to be related to use of physical memory above the 16GB >> barrier. You could try reducing the amount of memory allocated to the >> kernel by passing 'mem=1700M' on the kernel command line. >> > > Hi David, > > are you sure ? > > This is what I see with our own boards (not the reference design board): > > Works: > > Linux version 3.0.3-423-gfa07d39 (groeck@rbos-pc-13) (gcc version 4.4.1 > (Debian 4.4.1-1) ) #2 SMP PREEMPT Thu Aug 18 14:09:53 PDT 2011 > [ ... ] > CPU revision is: 000d030b (Cavium Octeon+) > Checking for the multiply/shift bug... no. > Checking for the daddiu bug... no. > Determined physical RAM map: > memory: 00000000001fa000 @ 000000000160b000 (usable) > memory: 000000000e400000 @ 0000000001900000 (usable) > memory: 00000000d0000000 @ 0000000020000000 (usable) > memory: 000000000ffff000 @ 00000000f0001000 (usable) > memory: 0000000010000000 @ 0000000410000000 (usable) > > Crashes: > > Linux version 3.0.3-423-gfa07d39 (groeck@rbos-pc-13) (gcc version 4.4.1 > (Debian 4.4.1-1) ) #2 SMP PREEMPT Thu Aug 18 14:09:53 PDT 2011 > [ ... ] > CPU revision is: 000d0003 (Cavium Octeon) > Checking for the multiply/shift bug... no. > Checking for the daddiu bug... no. > Determined physical RAM map: > memory: 00000000001fa000 @ 000000000160b000 (usable) > memory: 000000000e400000 @ 0000000001900000 (usable) > memory: 0000000060000000 @ 0000000020000000 (usable) > memory: 0000000010000000 @ 0000000410000000 (usable) > > The memory at 0000000410000000 is there for both CPUs, yet the crash is > only seen on the board with CN38xx. From a SW perspective, only > difference besides the CPU type is that the working board has more > memory. > That's right, I normally run on boards with 4GB of memory so I was not seeing it. When I reduce the memory to 2GB, I can see it on most boards. Sometimes (but not always) I see this: . . . Movable zone start PFN for each node early_node_map[5] active PFN ranges 0: 0x0000056a -> 0x00000578 0: 0x000005c0 -> 0x00001fc0 0: 0x00002080 -> 0x00003f80 0: 0x00008000 -> 0x00020000 0: 0x00104000 -> 0x00104900 Normal zone: 2808 pages exceeds realsize 2304 ^^^^^^^^^ Is a warning message indicating that something is not right in the memory initialization, which is exactly where things are going wrong. I am retesting on the HEAD and trying to figure out where it is going wrong. David Daney From jason.kwon@ericsson.com Fri Aug 19 19:14:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 19:15:00 +0200 (CEST) Received: from imr4.ericy.com ([198.24.6.9]:51200 "EHLO imr4.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491816Ab1HSROz (ORCPT ); Fri, 19 Aug 2011 19:14:55 +0200 Received: from eusaamw0712.eamcs.ericsson.se ([147.117.20.181]) by imr4.ericy.com (8.14.3/8.14.3/Debian-9.1ubuntu1) with ESMTP id p7JHEgAG006652; Fri, 19 Aug 2011 12:14:43 -0500 Received: from [IPv6:::1] (147.117.20.214) by smtps-am.internal.ericsson.com (147.117.20.181) with Microsoft SMTP Server (TLS) id 8.3.137.0; Fri, 19 Aug 2011 13:14:37 -0400 Message-ID: <4E4E99F8.4050704@ericsson.com> Date: Fri, 19 Aug 2011 10:14:32 -0700 From: Jason Kwon User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.18) Gecko/20110617 Thunderbird/3.1.11 MIME-Version: 1.0 To: Guenter Roeck CC: David Daney , "linux-mips@linux-mips.org" Subject: Re: Problems booting 3.0.3 kernel on Octeon CN58XX board References: <4E4DA9DA.60305@ericsson.com> <4E4E9036.9000802@cavium.com> <1313773248.3235.87.camel@groeck-laptop> In-Reply-To: <1313773248.3235.87.camel@groeck-laptop> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 30920 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jason.kwon@ericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14585 Content-Length: 4943 Lines: 116 On 08/19/2011 10:00 AM, Guenter Roeck wrote: > On Fri, 2011-08-19 at 12:32 -0400, David Daney wrote: >> On 08/18/2011 05:10 PM, Jason Kwon wrote: >>> Attempting to boot a 3.0.3 kernel on a CN58XX board produced the >>> following oops: >>> >>> CPU 4 Unable to handle kernel paging request at virtual address >>> 0000000001c00000, epc == ffffffff811aa9f4, ra == ffffffff811aaa98 >>> Oops[#1]: >>> Cpu 4 >>> $ 0 : 0000000000000000 0000000010008ce0 ffffffff821d2b80 0000000001c00000 >>> $ 4 : 0000000001c00038 000000000000017c 0000000000080000 0000000000080072 >>> $ 8 : 0000000000000008 0000000000000002 0000000000000003 a800000002284520 >>> $12 : 0000000000000002 ffffffff8186ee80 ffffffffffffff80 0000000000000030 >>> $16 : 0000000000080072 0000000000000001 0000000001bfa8f0 0000000001bfa928 >>> $20 : a800000003aff8f0 00000000000f0000 ffffffff8186ee80 ffffffff821d2a80 >>> $24 : 0000000000000001 0000000000000038 >>> $28 : a80000041fc48000 a80000041fc4bd90 fffffffffffffffc ffffffff811aaa98 >>> Hi : 0000000000000000 >>> Lo : 0000000000000000 >>> epc : ffffffff811aa9f4 setup_per_zone_wmarks+0x19c/0x2d8 >>> Not tainted >>> ra : ffffffff811aaa98 setup_per_zone_wmarks+0x240/0x2d8 >>> Status: 10008ce2 KX SX UX KERNEL EXL >>> Cause : 40808408 >>> BadVA : 0000000001c00000 >>> PrId : 000d0301 (Cavium Octeon+) >>> Modules linked in: >>> Process swapper (pid: 1, threadinfo=a80000041fc48000, >>> task=a80000041fc44038, tls=0000000000000000) >>> Stack : 0000000000000000 000000000006f75d ffffffff8186eec0 0000000000000001 >>> 0000000000000547 ffffffff81825598 ffffffff81a80000 ffffffff818b3e68 >>> ffffffff818a40ac 0000000000000000 ffffffff81a80000 0000000000000000 >>> 0000000000000000 0000000000000000 0000000000000000 ffffffff818a40f0 >>> ffffffff81a80000 ffffffff81100438 ffffffff818b4198 ffffffff818b3e68 >>> ffffffff818b46c8 0000000000000000 0000000000000000 ffffffff818721d0 >>> 0000000000000000 0000000000000000 0000000000000000 ffffffff81109bb0 >>> 0000000000000000 0000000000000000 0000000000000000 0000000000000000 >>> 0000000000000000 0000000000000000 0000000000000000 ffffffff818720f8 >>> 0000000000000000 0000000000000000 0000000000000000 0000000000000000 >>> ... >>> Call Trace: >>> [] setup_per_zone_wmarks+0x19c/0x2d8 >>> [] init_per_zone_wmark_min+0x44/0xe0 >>> [] do_one_initcall+0x38/0x160 >>> [] kernel_init+0xd8/0x178 >>> [] kernel_thread_helper+0x10/0x18 >>> >> It appears to be related to use of physical memory above the 16GB >> barrier. You could try reducing the amount of memory allocated to the >> kernel by passing 'mem=1700M' on the kernel command line. >> > Hi David, > > are you sure ? > > This is what I see with our own boards (not the reference design board): > > Works: > > Linux version 3.0.3-423-gfa07d39 (groeck@rbos-pc-13) (gcc version 4.4.1 > (Debian 4.4.1-1) ) #2 SMP PREEMPT Thu Aug 18 14:09:53 PDT 2011 > [ ... ] > CPU revision is: 000d030b (Cavium Octeon+) > Checking for the multiply/shift bug... no. > Checking for the daddiu bug... no. > Determined physical RAM map: > memory: 00000000001fa000 @ 000000000160b000 (usable) > memory: 000000000e400000 @ 0000000001900000 (usable) > memory: 00000000d0000000 @ 0000000020000000 (usable) > memory: 000000000ffff000 @ 00000000f0001000 (usable) > memory: 0000000010000000 @ 0000000410000000 (usable) > > Crashes: > > Linux version 3.0.3-423-gfa07d39 (groeck@rbos-pc-13) (gcc version 4.4.1 > (Debian 4.4.1-1) ) #2 SMP PREEMPT Thu Aug 18 14:09:53 PDT 2011 > [ ... ] > CPU revision is: 000d0003 (Cavium Octeon) > Checking for the multiply/shift bug... no. > Checking for the daddiu bug... no. > Determined physical RAM map: > memory: 00000000001fa000 @ 000000000160b000 (usable) > memory: 000000000e400000 @ 0000000001900000 (usable) > memory: 0000000060000000 @ 0000000020000000 (usable) > memory: 0000000010000000 @ 0000000410000000 (usable) > > The memory at 0000000410000000 is there for both CPUs, yet the crash is > only seen on the board with CN38xx. From a SW perspective, only > difference besides the CPU type is that the working board has more > memory. > > Thanks, > Guenter > > Well, I can confirm that setting mem=1700m on my CN5860 board allowed it to boot, at least: Linux version 3.0.3-Cavium-Octeon+ (jkwon@xc5-pc2) (gcc version 4.3.3 (Cavium Networks Version: 2_0_0 build 95) ) #2 SMP Thu Aug 18 15:16:58 PDT 2011 [ ... ] CPU revision is: 000d0301 (Cavium Octeon+) Checking for the multiply/shift bug... no. Checking for the daddiu bug... no. Determined physical RAM map: memory: 0000000000208000 @ 0000000001872000 (usable) memory: 000000000dc00000 @ 0000000002200000 (usable) memory: 000000005c800000 @ 0000000020000000 (usable) I also tried the memory restriction on a CN3860 board that was also hitting the same oops, and it then hit a different problem, so the restriction did seem to work on both boards. Jason From johnstul@us.ibm.com Fri Aug 19 19:23:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 19:23:39 +0200 (CEST) Received: from e39.co.us.ibm.com ([32.97.110.160]:33711 "EHLO e39.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491816Ab1HSRXf (ORCPT ); Fri, 19 Aug 2011 19:23:35 +0200 Received: from d03relay01.boulder.ibm.com (d03relay01.boulder.ibm.com [9.17.195.226]) by e39.co.us.ibm.com (8.14.4/8.13.1) with ESMTP id p7JH8DxW002946 for ; Fri, 19 Aug 2011 11:08:13 -0600 Received: from d03av01.boulder.ibm.com (d03av01.boulder.ibm.com [9.17.195.167]) by d03relay01.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p7JHNN1A053798 for ; Fri, 19 Aug 2011 11:23:23 -0600 Received: from d03av01.boulder.ibm.com (loopback [127.0.0.1]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p7JHNNTA031787 for ; Fri, 19 Aug 2011 11:23:23 -0600 Received: from [9.50.17.119] (dyn9050017119.mts.ibm.com [9.50.17.119] (may be forged)) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p7JHNL2W031705; Fri, 19 Aug 2011 11:23:22 -0600 Subject: Re: select() to /dev/rtc0 to wait for clock tick timed out From: john stultz To: Matt Turner Cc: linux-mips@linux-mips.org In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Date: Fri, 19 Aug 2011 10:23:19 -0700 Message-ID: <1313774600.2970.128.camel@work-vm> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 Content-Transfer-Encoding: 7bit X-archive-position: 30921 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: johnstul@us.ibm.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14593 Content-Length: 1161 Lines: 38 On Fri, 2011-08-19 at 00:16 -0400, Matt Turner wrote: > Hi John, > > I just sent a patch series to linux-mips@ that enables the RTC on a > particular Broadcom MIPS motherboard (BCM91250A SWARM). The RTC is an > M41T80. > > When I first found the patchset (it was originally sent a a few years > ago) and applied it to 2.6.37, it worked perfectly. > > Applied to 3.x (and I think even 2.6.38) I get the following when I run hwclock: > > # hwclock --systohc > select() to /dev/rtc0 to wait for clock tick timed out > > dmesg shows: > > [ 1.068000] i2c /dev entries driver > [ 1.072000] i2c-sibyte: i2c SMBus adapter module for SiByte board > [ 1.080000] rtc-m41t80 1-0068: chip found, driver version 0.06 > [ 1.088000] rtc-m41t80 1-0068: rtc core: registered m41t81 as rtc0 > [ 1.172000] rtc-m41t80 1-0068: setting system clock to 2011-08-18 > 19:56:53 UTC (1313697413) > > I'm emailing you because I thought it might be the same problem as > https://lkml.org/lkml/2011/1/20/306 Hmm. I thought we had gotten one that sorted. > Do you know what might be the problem? I'll take a look and see what I find. Thanks for the report! -john From guenter.roeck@ericsson.com Fri Aug 19 19:36:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 19:36:18 +0200 (CEST) Received: from imr4.ericy.com ([198.24.6.9]:52356 "EHLO imr4.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491169Ab1HSRgO (ORCPT ); Fri, 19 Aug 2011 19:36:14 +0200 Received: from eusaamw0706.eamcs.ericsson.se ([147.117.20.31]) by imr4.ericy.com (8.14.3/8.14.3/Debian-9.1ubuntu1) with ESMTP id p7JHa5w5010795; Fri, 19 Aug 2011 12:36:06 -0500 Received: from [155.53.96.104] (147.117.20.214) by eusaamw0706.eamcs.ericsson.se (147.117.20.91) with Microsoft SMTP Server id 8.3.137.0; Fri, 19 Aug 2011 13:36:02 -0400 Subject: Re: Problems booting 3.0.3 kernel on Octeon CN58XX board From: Guenter Roeck Reply-To: To: Jason Kwon CC: David Daney , "linux-mips@linux-mips.org" In-Reply-To: <4E4E99F8.4050704@ericsson.com> References: <4E4DA9DA.60305@ericsson.com> <4E4E9036.9000802@cavium.com> <1313773248.3235.87.camel@groeck-laptop> <4E4E99F8.4050704@ericsson.com> Content-Type: text/plain; charset="UTF-8" Organization: Ericsson Date: Fri, 19 Aug 2011 10:35:55 -0700 Message-ID: <1313775355.3235.90.camel@groeck-laptop> MIME-Version: 1.0 X-Mailer: Evolution 2.32.2 Content-Transfer-Encoding: 7bit X-archive-position: 30922 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14599 Content-Length: 5889 Lines: 135 On Fri, 2011-08-19 at 13:14 -0400, Jason Kwon wrote: > On 08/19/2011 10:00 AM, Guenter Roeck wrote: > > On Fri, 2011-08-19 at 12:32 -0400, David Daney wrote: > >> On 08/18/2011 05:10 PM, Jason Kwon wrote: > >>> Attempting to boot a 3.0.3 kernel on a CN58XX board produced the > >>> following oops: > >>> > >>> CPU 4 Unable to handle kernel paging request at virtual address > >>> 0000000001c00000, epc == ffffffff811aa9f4, ra == ffffffff811aaa98 > >>> Oops[#1]: > >>> Cpu 4 > >>> $ 0 : 0000000000000000 0000000010008ce0 ffffffff821d2b80 0000000001c00000 > >>> $ 4 : 0000000001c00038 000000000000017c 0000000000080000 0000000000080072 > >>> $ 8 : 0000000000000008 0000000000000002 0000000000000003 a800000002284520 > >>> $12 : 0000000000000002 ffffffff8186ee80 ffffffffffffff80 0000000000000030 > >>> $16 : 0000000000080072 0000000000000001 0000000001bfa8f0 0000000001bfa928 > >>> $20 : a800000003aff8f0 00000000000f0000 ffffffff8186ee80 ffffffff821d2a80 > >>> $24 : 0000000000000001 0000000000000038 > >>> $28 : a80000041fc48000 a80000041fc4bd90 fffffffffffffffc ffffffff811aaa98 > >>> Hi : 0000000000000000 > >>> Lo : 0000000000000000 > >>> epc : ffffffff811aa9f4 setup_per_zone_wmarks+0x19c/0x2d8 > >>> Not tainted > >>> ra : ffffffff811aaa98 setup_per_zone_wmarks+0x240/0x2d8 > >>> Status: 10008ce2 KX SX UX KERNEL EXL > >>> Cause : 40808408 > >>> BadVA : 0000000001c00000 > >>> PrId : 000d0301 (Cavium Octeon+) > >>> Modules linked in: > >>> Process swapper (pid: 1, threadinfo=a80000041fc48000, > >>> task=a80000041fc44038, tls=0000000000000000) > >>> Stack : 0000000000000000 000000000006f75d ffffffff8186eec0 0000000000000001 > >>> 0000000000000547 ffffffff81825598 ffffffff81a80000 ffffffff818b3e68 > >>> ffffffff818a40ac 0000000000000000 ffffffff81a80000 0000000000000000 > >>> 0000000000000000 0000000000000000 0000000000000000 ffffffff818a40f0 > >>> ffffffff81a80000 ffffffff81100438 ffffffff818b4198 ffffffff818b3e68 > >>> ffffffff818b46c8 0000000000000000 0000000000000000 ffffffff818721d0 > >>> 0000000000000000 0000000000000000 0000000000000000 ffffffff81109bb0 > >>> 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > >>> 0000000000000000 0000000000000000 0000000000000000 ffffffff818720f8 > >>> 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > >>> ... > >>> Call Trace: > >>> [] setup_per_zone_wmarks+0x19c/0x2d8 > >>> [] init_per_zone_wmark_min+0x44/0xe0 > >>> [] do_one_initcall+0x38/0x160 > >>> [] kernel_init+0xd8/0x178 > >>> [] kernel_thread_helper+0x10/0x18 > >>> > >> It appears to be related to use of physical memory above the 16GB > >> barrier. You could try reducing the amount of memory allocated to the > >> kernel by passing 'mem=1700M' on the kernel command line. > >> > > Hi David, > > > > are you sure ? > > > > This is what I see with our own boards (not the reference design board): > > > > Works: > > > > Linux version 3.0.3-423-gfa07d39 (groeck@rbos-pc-13) (gcc version 4.4.1 > > (Debian 4.4.1-1) ) #2 SMP PREEMPT Thu Aug 18 14:09:53 PDT 2011 > > [ ... ] > > CPU revision is: 000d030b (Cavium Octeon+) > > Checking for the multiply/shift bug... no. > > Checking for the daddiu bug... no. > > Determined physical RAM map: > > memory: 00000000001fa000 @ 000000000160b000 (usable) > > memory: 000000000e400000 @ 0000000001900000 (usable) > > memory: 00000000d0000000 @ 0000000020000000 (usable) > > memory: 000000000ffff000 @ 00000000f0001000 (usable) > > memory: 0000000010000000 @ 0000000410000000 (usable) > > > > Crashes: > > > > Linux version 3.0.3-423-gfa07d39 (groeck@rbos-pc-13) (gcc version 4.4.1 > > (Debian 4.4.1-1) ) #2 SMP PREEMPT Thu Aug 18 14:09:53 PDT 2011 > > [ ... ] > > CPU revision is: 000d0003 (Cavium Octeon) > > Checking for the multiply/shift bug... no. > > Checking for the daddiu bug... no. > > Determined physical RAM map: > > memory: 00000000001fa000 @ 000000000160b000 (usable) > > memory: 000000000e400000 @ 0000000001900000 (usable) > > memory: 0000000060000000 @ 0000000020000000 (usable) > > memory: 0000000010000000 @ 0000000410000000 (usable) > > > > The memory at 0000000410000000 is there for both CPUs, yet the crash is > > only seen on the board with CN38xx. From a SW perspective, only > > difference besides the CPU type is that the working board has more > > memory. > > > > Thanks, > > Guenter > > > > > Well, I can confirm that setting mem=1700m on my CN5860 board allowed it > to boot, at least: > > Linux version 3.0.3-Cavium-Octeon+ (jkwon@xc5-pc2) (gcc version 4.3.3 > (Cavium Networks Version: 2_0_0 build 95) ) #2 SMP Thu Aug 18 15:16:58 > PDT 2011 > [ ... ] > CPU revision is: 000d0301 (Cavium Octeon+) > Checking for the multiply/shift bug... no. > Checking for the daddiu bug... no. > Determined physical RAM map: > memory: 0000000000208000 @ 0000000001872000 (usable) > memory: 000000000dc00000 @ 0000000002200000 (usable) > memory: 000000005c800000 @ 0000000020000000 (usable) > > I also tried the memory restriction on a CN3860 board that was also > hitting the same oops, and it then hit a different problem, so the > restriction did seem to work on both boards. > Another data point: The board with CN38xx boots with mem=1700m: Linux version 3.0.3-422-gcdb65d6 (groeck@rbos-pc-13) (gcc version 4.4.1 (Debian 4.4.1-1) ) #2 SMP PREEMPT Fri Aug 19 10:14:27 PDT 2011 [ ... ] CPU revision is: 000d0003 (Cavium Octeon) Checking for the multiply/shift bug... no. Checking for the daddiu bug... no. Determined physical RAM map: memory: 00000000001fa000 @ 000000000160a000 (usable) memory: 000000000e400000 @ 0000000001900000 (usable) memory: 0000000060000000 @ 0000000020000000 (usable) memory: 0000000010000000 @ 0000000410000000 (usable) User-defined physical RAM map: memory: 000000006a400000 @ 0000000000000000 (usable) Guenter From johnstul@us.ibm.com Fri Aug 19 20:07:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 20:07:38 +0200 (CEST) Received: from e9.ny.us.ibm.com ([32.97.182.139]:60772 "EHLO e9.ny.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491860Ab1HSSHd (ORCPT ); Fri, 19 Aug 2011 20:07:33 +0200 Received: from d01relay05.pok.ibm.com (d01relay05.pok.ibm.com [9.56.227.237]) by e9.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id p7JHXqGS031610 for ; Fri, 19 Aug 2011 13:33:52 -0400 Received: from d01av01.pok.ibm.com (d01av01.pok.ibm.com [9.56.224.215]) by d01relay05.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p7JI7QC2182956 for ; Fri, 19 Aug 2011 14:07:26 -0400 Received: from d01av01.pok.ibm.com (loopback [127.0.0.1]) by d01av01.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p7JI7PEU005119 for ; Fri, 19 Aug 2011 14:07:25 -0400 Received: from [9.50.17.119] (dyn9050017119.mts.ibm.com [9.50.17.119] (may be forged)) by d01av01.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p7JI7O4i005105; Fri, 19 Aug 2011 14:07:25 -0400 Subject: Re: select() to /dev/rtc0 to wait for clock tick timed out From: john stultz To: Matt Turner Cc: linux-mips@linux-mips.org In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Date: Fri, 19 Aug 2011 11:07:22 -0700 Message-ID: <1313777242.2970.131.camel@work-vm> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 Content-Transfer-Encoding: 7bit X-archive-position: 30923 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: johnstul@us.ibm.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14614 Content-Length: 720 Lines: 25 On Fri, 2011-08-19 at 00:16 -0400, Matt Turner wrote: > Hi John, > > I just sent a patch series to linux-mips@ that enables the RTC on a > particular Broadcom MIPS motherboard (BCM91250A SWARM). The RTC is an > M41T80. > > When I first found the patchset (it was originally sent a a few years > ago) and applied it to 2.6.37, it worked perfectly. > > Applied to 3.x (and I think even 2.6.38) I get the following when I run hwclock: > > # hwclock --systohc > select() to /dev/rtc0 to wait for clock tick timed out So do alarm interrupts actually work on the hardware? The rtc-m41t80.c driver looks like it should support them ok. Does the test program at the end of Documentation/rtc.txt do much? thanks -john From david.daney@cavium.com Fri Aug 19 20:44:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 20:44:18 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11735 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491867Ab1HSSoK (ORCPT ); Fri, 19 Aug 2011 20:44:10 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 19 Aug 2011 11:45:16 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 19 Aug 2011 11:44:07 -0700 Received: from dd1.caveonetworks.com ([64.2.3.195]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 19 Aug 2011 11:44:07 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.4) with ESMTP id p7JIi4l1012556; Fri, 19 Aug 2011 11:44:05 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p7JIi2NH012555; Fri, 19 Aug 2011 11:44:03 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Jason Kwon Subject: [PATCH] MIPS: Octeon: Select CONFIG_HOLES_IN_ZONE Date: Fri, 19 Aug 2011 11:44:00 -0700 Message-Id: <1313779440-12522-1-git-send-email-david.daney@cavium.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 19 Aug 2011 18:44:07.0583 (UTC) FILETIME=[FA1BAAF0:01CC5E9F] X-archive-position: 30924 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.daney@cavium.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14632 Content-Length: 1915 Lines: 67 Current Octeon systems do in fact have holes in their memory zones. We need to select HOLES_IN_ZONE. If we do not, some memory configurations will result in crashes at boot time like this: . . . CPU 6 Unable to handle kernel paging request at virtual address 0000000000700000, epc == ffffffff8118fe00, ra == ffffffff8118fe9c Oops[#1]: Cpu 6 . . . ... Call Trace: [] setup_per_zone_wmarks+0x1b0/0x338 [] init_per_zone_wmark_min+0x64/0xd0 [] do_one_initcall+0x38/0x160 . . . Reported-by: Jason Kwon Signed-off-by: David Daney Cc: Jason Kwon --- Jason, can you test this patch? Ralf, if Jason reports that it fixes his problem, it probably is needed for 3.0 and 3.1. arch/mips/Kconfig | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d300c2b..b122adc 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -723,6 +723,7 @@ config CAVIUM_OCTEON_SIMULATOR select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_HOTPLUG_CPU select SYS_HAS_CPU_CAVIUM_OCTEON + select HOLES_IN_ZONE help The Octeon simulator is software performance model of the Cavium Octeon Processor. It supports simulating Octeon processors on x86 @@ -745,6 +746,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD select ZONE_DMA32 select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI + select HOLES_IN_ZONE help This option supports all of the Octeon reference boards from Cavium Networks. It builds a kernel that dynamically determines the Octeon @@ -974,6 +976,9 @@ config ISA_DMA_API config GENERIC_GPIO bool +config HOLES_IN_ZONE + bool + # # Endianess selection. Sufficiently obscure so many users don't know what to # answer,so we try hard to limit the available choices. Also the use of a -- 1.7.2.3 From guenter.roeck@ericsson.com Fri Aug 19 21:13:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 21:13:40 +0200 (CEST) Received: from imr4.ericy.com ([198.24.6.9]:51472 "EHLO imr4.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492171Ab1HSTNc (ORCPT ); Fri, 19 Aug 2011 21:13:32 +0200 Received: from eusaamw0706.eamcs.ericsson.se ([147.117.20.31]) by imr4.ericy.com (8.14.3/8.14.3/Debian-9.1ubuntu1) with ESMTP id p7JJDMYC029638; Fri, 19 Aug 2011 14:13:24 -0500 Received: from [155.53.96.104] (147.117.20.214) by eusaamw0706.eamcs.ericsson.se (147.117.20.91) with Microsoft SMTP Server id 8.3.137.0; Fri, 19 Aug 2011 15:13:18 -0400 Subject: Re: [PATCH] MIPS: Octeon: Select CONFIG_HOLES_IN_ZONE From: Guenter Roeck Reply-To: To: David Daney CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , Jason Kwon In-Reply-To: <1313779440-12522-1-git-send-email-david.daney@cavium.com> References: <1313779440-12522-1-git-send-email-david.daney@cavium.com> Content-Type: text/plain; charset="UTF-8" Organization: Ericsson Date: Fri, 19 Aug 2011 12:13:11 -0700 Message-ID: <1313781191.3235.96.camel@groeck-laptop> MIME-Version: 1.0 X-Mailer: Evolution 2.32.2 Content-Transfer-Encoding: 7bit X-archive-position: 30925 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14650 Content-Length: 1120 Lines: 43 On Fri, 2011-08-19 at 14:44 -0400, David Daney wrote: > Current Octeon systems do in fact have holes in their memory zones. > We need to select HOLES_IN_ZONE. If we do not, some memory > configurations will result in crashes at boot time like this: > > . > . > . > CPU 6 Unable to handle kernel paging request at virtual address 0000000000700000, epc == ffffffff8118fe00, ra == ffffffff8118fe9c > Oops[#1]: > Cpu 6 > . > . > . > ... > Call Trace: > [] setup_per_zone_wmarks+0x1b0/0x338 > [] init_per_zone_wmark_min+0x64/0xd0 > [] do_one_initcall+0x38/0x160 > . > . > . > > Reported-by: Jason Kwon > Signed-off-by: David Daney > Cc: Jason Kwon > --- > Jason, can you test this patch? > > Ralf, if Jason reports that it fixes his problem, it probably is > needed for 3.0 and 3.1. > Your patch fixes the problem for the board with CN38xx and 2GB RAM that crashed previously. Tested-by: Guenter Roeck Thanks a lot for looking into this. Guenter From mattst88@gmail.com Fri Aug 19 21:46:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 21:46:54 +0200 (CEST) Received: from mail-vx0-f177.google.com ([209.85.220.177]:34655 "EHLO mail-vx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492171Ab1HSTqu (ORCPT ); Fri, 19 Aug 2011 21:46:50 +0200 Received: by vxj2 with SMTP id 2so3487723vxj.36 for ; Fri, 19 Aug 2011 12:46:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=jpxH/l+NFJn4EN0Xpcja3fHyMtVWE7cr3rbhND92qAg=; b=pX3BRUYT2qV2RhCuy/NyPG6UhDKKUm+0R2CYnLulNtxb7ue9MTC3ARDjtg0OiQaSXg b6ft+k3xIFDn5v9L7cztHn2Ata4pDYSU8Y7s+KHDsel9fBHCmeTuRqk9R+XtOMRw5N5Z SgofhklyK9tQPvxjXSAQBr02oROZECbK00Zck= Received: by 10.52.71.41 with SMTP id r9mr137002vdu.289.1313783204445; Fri, 19 Aug 2011 12:46:44 -0700 (PDT) MIME-Version: 1.0 Received: by 10.52.156.131 with HTTP; Fri, 19 Aug 2011 12:41:59 -0700 (PDT) In-Reply-To: <1313777242.2970.131.camel@work-vm> References: <1313777242.2970.131.camel@work-vm> From: Matt Turner Date: Fri, 19 Aug 2011 15:41:59 -0400 Message-ID: Subject: Re: select() to /dev/rtc0 to wait for clock tick timed out To: john stultz Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 30926 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14680 Content-Length: 1057 Lines: 34 On Fri, Aug 19, 2011 at 2:07 PM, john stultz wrote: > On Fri, 2011-08-19 at 00:16 -0400, Matt Turner wrote: >> Hi John, >> >> I just sent a patch series to linux-mips@ that enables the RTC on a >> particular Broadcom MIPS motherboard (BCM91250A SWARM). The RTC is an >> M41T80. >> >> When I first found the patchset (it was originally sent a a few years >> ago) and applied it to 2.6.37, it worked perfectly. >> >> Applied to 3.x (and I think even 2.6.38) I get the following when I run hwclock: >> >> # hwclock --systohc >> select() to /dev/rtc0 to wait for clock tick timed out > > So do alarm interrupts actually work on the hardware? > > The rtc-m41t80.c driver looks like it should support them ok. > > Does the test program at the end of Documentation/rtc.txt do much? > > thanks > -john Counting 5 update (1/sec) interrupts from reading /dev/rtc0: ... and then it doesn't count. Would it help if I tried to bisect this? (Is there an easy way to bisect 2.6.37..master with my patches applied to each iteration?) Thanks, Matt From johnstul@us.ibm.com Fri Aug 19 22:00:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 22:00:08 +0200 (CEST) Received: from e6.ny.us.ibm.com ([32.97.182.146]:37334 "EHLO e6.ny.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492171Ab1HSUAD (ORCPT ); Fri, 19 Aug 2011 22:00:03 +0200 Received: from d01relay05.pok.ibm.com (d01relay05.pok.ibm.com [9.56.227.237]) by e6.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id p7JJZkdm021561 for ; Fri, 19 Aug 2011 15:35:46 -0400 Received: from d01av04.pok.ibm.com (d01av04.pok.ibm.com [9.56.224.64]) by d01relay05.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p7JJxrFF208692 for ; Fri, 19 Aug 2011 15:59:55 -0400 Received: from d01av04.pok.ibm.com (loopback [127.0.0.1]) by d01av04.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p7JJxr00032083 for ; Fri, 19 Aug 2011 15:59:53 -0400 Received: from [9.50.17.119] (dyn9050017119.mts.ibm.com [9.50.17.119] (may be forged)) by d01av04.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p7JJxqnI032065; Fri, 19 Aug 2011 15:59:52 -0400 Subject: Re: select() to /dev/rtc0 to wait for clock tick timed out From: john stultz To: Matt Turner Cc: linux-mips@linux-mips.org In-Reply-To: References: <1313777242.2970.131.camel@work-vm> Content-Type: text/plain; charset="UTF-8" Date: Fri, 19 Aug 2011 12:59:50 -0700 Message-ID: <1313783990.2970.136.camel@work-vm> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 Content-Transfer-Encoding: 7bit X-archive-position: 30927 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: johnstul@us.ibm.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14688 Content-Length: 5247 Lines: 230 On Fri, 2011-08-19 at 15:41 -0400, Matt Turner wrote: > On Fri, Aug 19, 2011 at 2:07 PM, john stultz wrote: > > On Fri, 2011-08-19 at 00:16 -0400, Matt Turner wrote: > > thanks > > -john > > Counting 5 update (1/sec) interrupts from reading /dev/rtc0: > > ... and then it doesn't count. > > Would it help if I tried to bisect this? (Is there an easy way to > bisect 2.6.37..master with my patches applied to each iteration?) I suspect bisecting won't help too much, as I've reworked a good chunk of the generic rtc code in 2.6.38, so its not likely to be one small change. How about this modified (cutting out the UIE testing) version of the Documentation/rtc.txt test below? I'm basically trying to find out if the alarm functionality is actually working or not, since with 2.6.38+ we use the one-shot style alarm mode to trigger UIE interrupts. thanks -john /* * Real Time Clock Driver Test/Example Program * * Compile with: * gcc -s -Wall -Wstrict-prototypes rtctest.c -o rtctest * * Copyright (C) 1996, Paul Gortmaker. * * Released under the GNU General Public License, version 2, * included herein by reference. * */ #include #include #include #include #include #include #include #include #include /* * This expects the new RTC class driver framework, working with * clocks that will often not be clones of what the PC-AT had. * Use the command line to specify another RTC if you need one. */ static const char default_rtc[] = "/dev/rtc0"; int main(int argc, char **argv) { int i, fd, retval, irqcount = 0; unsigned long tmp, data; struct rtc_time rtc_tm; const char *rtc = default_rtc; switch (argc) { case 2: rtc = argv[1]; /* FALLTHROUGH */ case 1: break; default: fprintf(stderr, "usage: rtctest [rtcdev]\n"); return 1; } fd = open(rtc, O_RDONLY); if (fd == -1) { perror(rtc); exit(errno); } fprintf(stderr, "\n\t\t\tRTC Driver Test Example.\n\n"); test_READ: /* Read the RTC time/date */ retval = ioctl(fd, RTC_RD_TIME, &rtc_tm); if (retval == -1) { perror("RTC_RD_TIME ioctl"); exit(errno); } fprintf(stderr, "\n\nCurrent RTC date/time is %d-%d-%d, %02d:%02d:%02d.\n", rtc_tm.tm_mday, rtc_tm.tm_mon + 1, rtc_tm.tm_year + 1900, rtc_tm.tm_hour, rtc_tm.tm_min, rtc_tm.tm_sec); /* Set the alarm to 5 sec in the future, and check for rollover */ rtc_tm.tm_sec += 5; if (rtc_tm.tm_sec >= 60) { rtc_tm.tm_sec %= 60; rtc_tm.tm_min++; } if (rtc_tm.tm_min == 60) { rtc_tm.tm_min = 0; rtc_tm.tm_hour++; } if (rtc_tm.tm_hour == 24) rtc_tm.tm_hour = 0; retval = ioctl(fd, RTC_ALM_SET, &rtc_tm); if (retval == -1) { if (errno == ENOTTY) { fprintf(stderr, "\n...Alarm IRQs not supported.\n"); goto test_PIE; } perror("RTC_ALM_SET ioctl"); exit(errno); } /* Read the current alarm settings */ retval = ioctl(fd, RTC_ALM_READ, &rtc_tm); if (retval == -1) { perror("RTC_ALM_READ ioctl"); exit(errno); } fprintf(stderr, "Alarm time now set to %02d:%02d:%02d.\n", rtc_tm.tm_hour, rtc_tm.tm_min, rtc_tm.tm_sec); /* Enable alarm interrupts */ retval = ioctl(fd, RTC_AIE_ON, 0); if (retval == -1) { perror("RTC_AIE_ON ioctl"); exit(errno); } fprintf(stderr, "Waiting 5 seconds for alarm..."); fflush(stderr); /* This blocks until the alarm ring causes an interrupt */ retval = read(fd, &data, sizeof(unsigned long)); if (retval == -1) { perror("read"); exit(errno); } irqcount++; fprintf(stderr, " okay. Alarm rang.\n"); /* Disable alarm interrupts */ retval = ioctl(fd, RTC_AIE_OFF, 0); if (retval == -1) { perror("RTC_AIE_OFF ioctl"); exit(errno); } test_PIE: /* Read periodic IRQ rate */ retval = ioctl(fd, RTC_IRQP_READ, &tmp); if (retval == -1) { /* not all RTCs support periodic IRQs */ if (errno == ENOTTY) { fprintf(stderr, "\nNo periodic IRQ support\n"); goto done; } perror("RTC_IRQP_READ ioctl"); exit(errno); } fprintf(stderr, "\nPeriodic IRQ rate is %ldHz.\n", tmp); fprintf(stderr, "Counting 20 interrupts at:"); fflush(stderr); /* The frequencies 128Hz, 256Hz, ... 8192Hz are only allowed for root. */ for (tmp=2; tmp<=64; tmp*=2) { retval = ioctl(fd, RTC_IRQP_SET, tmp); if (retval == -1) { /* not all RTCs can change their periodic IRQ rate */ if (errno == ENOTTY) { fprintf(stderr, "\n...Periodic IRQ rate is fixed\n"); goto done; } perror("RTC_IRQP_SET ioctl"); exit(errno); } fprintf(stderr, "\n%ldHz:\t", tmp); fflush(stderr); /* Enable periodic interrupts */ retval = ioctl(fd, RTC_PIE_ON, 0); if (retval == -1) { perror("RTC_PIE_ON ioctl"); exit(errno); } for (i=1; i<21; i++) { /* This blocks */ retval = read(fd, &data, sizeof(unsigned long)); if (retval == -1) { perror("read"); exit(errno); } fprintf(stderr, " %d",i); fflush(stderr); irqcount++; } /* Disable periodic interrupts */ retval = ioctl(fd, RTC_PIE_OFF, 0); if (retval == -1) { perror("RTC_PIE_OFF ioctl"); exit(errno); } } done: fprintf(stderr, "\n\n\t\t\t *** Test complete ***\n"); close(fd); return 0; } From mattst88@gmail.com Fri Aug 19 22:20:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 22:20:53 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:43121 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492179Ab1HSUUt (ORCPT ); Fri, 19 Aug 2011 22:20:49 +0200 Received: by vws8 with SMTP id 8so3268376vws.36 for ; Fri, 19 Aug 2011 13:20:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=OSn6QV41RgeYDeLg1ptEoWCrge3sU4FgbBHifHF8pN4=; b=EnfAAF/3CciDEW6QtGKU0maazzSVQ6dU+2Sqr5caLFb1MeTdWEVtLysxG5YxkAzi/j SoRB2HNw9Hn2EpBy9fumgZViaz8Oq5leePjEk+3o4mFne0olfBVSKzV2XQyHILNGDfM3 s3LrY68GDQ0WjZ87XOubPeJ8UT/QnAfhtoo0o= Received: by 10.52.88.133 with SMTP id bg5mr199390vdb.88.1313784412575; Fri, 19 Aug 2011 13:06:52 -0700 (PDT) MIME-Version: 1.0 Received: by 10.52.156.131 with HTTP; Fri, 19 Aug 2011 13:06:32 -0700 (PDT) In-Reply-To: <1313783990.2970.136.camel@work-vm> References: <1313777242.2970.131.camel@work-vm> <1313783990.2970.136.camel@work-vm> From: Matt Turner Date: Fri, 19 Aug 2011 16:06:32 -0400 Message-ID: Subject: Re: select() to /dev/rtc0 to wait for clock tick timed out To: john stultz Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 30928 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14693 Content-Length: 1323 Lines: 40 On Fri, Aug 19, 2011 at 3:59 PM, john stultz wrote: > On Fri, 2011-08-19 at 15:41 -0400, Matt Turner wrote: >> On Fri, Aug 19, 2011 at 2:07 PM, john stultz wrote: >> > On Fri, 2011-08-19 at 00:16 -0400, Matt Turner wrote: >> > thanks >> > -john >> >> Counting 5 update (1/sec) interrupts from reading /dev/rtc0: >> >> ... and then it doesn't count. >> >> Would it help if I tried to bisect this? (Is there an easy way to >> bisect 2.6.37..master with my patches applied to each iteration?) > > I suspect bisecting won't help too much, as I've reworked a good chunk > of the generic rtc code in 2.6.38, so its not likely to be one small > change. > > How about this modified (cutting out the UIE testing) version of the > Documentation/rtc.txt test below? > > I'm basically trying to find out if the alarm functionality is actually > working or not, since with 2.6.38+ we use the one-shot style alarm mode > to trigger UIE interrupts. > > thanks > -john Nope, just hangs. Current RTC date/time is 19-8-2011, 00:20:51. Alarm time now set to 00:20:56. Waiting 5 seconds for alarm... Would it at least help if I booted 2.6.37 to confirm that this test program works there? I'd hate to waste a bunch of your time only to find out that it's a problem with my patches. Thanks, MAtt From johnstul@us.ibm.com Fri Aug 19 22:34:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Aug 2011 22:34:49 +0200 (CEST) Received: from e39.co.us.ibm.com ([32.97.110.160]:40926 "EHLO e39.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492163Ab1HSUeo (ORCPT ); Fri, 19 Aug 2011 22:34:44 +0200 Received: from d03relay02.boulder.ibm.com (d03relay02.boulder.ibm.com [9.17.195.227]) by e39.co.us.ibm.com (8.14.4/8.13.1) with ESMTP id p7JKJOJq010254 for ; Fri, 19 Aug 2011 14:19:24 -0600 Received: from d03av01.boulder.ibm.com (d03av01.boulder.ibm.com [9.17.195.167]) by d03relay02.boulder.ibm.com (8.13.8/8.13.8/NCO v9.1) with ESMTP id p7JKYYoc157558 for ; Fri, 19 Aug 2011 14:34:34 -0600 Received: from d03av01.boulder.ibm.com (loopback [127.0.0.1]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p7JKYYWb020122 for ; Fri, 19 Aug 2011 14:34:34 -0600 Received: from [9.50.17.119] (dyn9050017119.mts.ibm.com [9.50.17.119] (may be forged)) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p7JKYWYW020039; Fri, 19 Aug 2011 14:34:33 -0600 Subject: Re: select() to /dev/rtc0 to wait for clock tick timed out From: john stultz To: Matt Turner Cc: linux-mips@linux-mips.org In-Reply-To: References: